if_alc.c revision 1.13
1 /* $OpenBSD: if_alc.c,v 1.1 2009/08/08 09:31:13 kevlo Exp $ */ 2 /*- 3 * Copyright (c) 2009, Pyun YongHyeon <yongari (at) FreeBSD.org> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice unmodified, this list of conditions, and the following 11 * disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 /* Driver for Atheros AR813x/AR815x PCIe Ethernet. */ 30 31 #ifdef _KERNEL_OPT 32 #include "vlan.h" 33 #endif 34 35 #include <sys/param.h> 36 #include <sys/proc.h> 37 #include <sys/endian.h> 38 #include <sys/systm.h> 39 #include <sys/types.h> 40 #include <sys/sockio.h> 41 #include <sys/mbuf.h> 42 #include <sys/queue.h> 43 #include <sys/kernel.h> 44 #include <sys/device.h> 45 #include <sys/callout.h> 46 #include <sys/socket.h> 47 #include <sys/module.h> 48 49 #include <sys/bus.h> 50 51 #include <net/if.h> 52 #include <net/if_dl.h> 53 #include <net/if_llc.h> 54 #include <net/if_media.h> 55 #include <net/if_ether.h> 56 57 #include <net/bpf.h> 58 59 #ifdef INET 60 #include <netinet/in.h> 61 #include <netinet/in_systm.h> 62 #include <netinet/in_var.h> 63 #include <netinet/ip.h> 64 #endif 65 66 #include <net/if_types.h> 67 #include <net/if_vlanvar.h> 68 69 #include <net/bpf.h> 70 71 #include <sys/rnd.h> 72 73 #include <dev/mii/mii.h> 74 #include <dev/mii/miivar.h> 75 76 #include <dev/pci/pcireg.h> 77 #include <dev/pci/pcivar.h> 78 #include <dev/pci/pcidevs.h> 79 80 #include <dev/pci/if_alcreg.h> 81 82 /* 83 * Devices supported by this driver. 84 */ 85 static struct alc_ident alc_ident_table[] = { 86 { PCI_VENDOR_ATTANSIC, PCI_PRODUCT_ATTANSIC_AR8131, 9 * 1024, 87 "Atheros AR8131 PCIe Gigabit Ethernet" }, 88 { PCI_VENDOR_ATTANSIC, PCI_PRODUCT_ATTANSIC_AR8132, 9 * 1024, 89 "Atheros AR8132 PCIe Fast Ethernet" }, 90 { PCI_VENDOR_ATTANSIC, PCI_PRODUCT_ATTANSIC_AR8151, 6 * 1024, 91 "Atheros AR8151 v1.0 PCIe Gigabit Ethernet" }, 92 { PCI_VENDOR_ATTANSIC, PCI_PRODUCT_ATTANSIC_AR8151_V2, 6 * 1024, 93 "Atheros AR8151 v2.0 PCIe Gigabit Ethernet" }, 94 { PCI_VENDOR_ATTANSIC, PCI_PRODUCT_ATTANSIC_AR8152_B, 6 * 1024, 95 "Atheros AR8152 v1.1 PCIe Fast Ethernet" }, 96 { PCI_VENDOR_ATTANSIC, PCI_PRODUCT_ATTANSIC_AR8152_B2, 6 * 1024, 97 "Atheros AR8152 v2.0 PCIe Fast Ethernet" }, 98 { PCI_VENDOR_ATTANSIC, PCI_PRODUCT_ATTANSIC_AR8161, 9 * 1024, 99 "Atheros AR8161 PCIe Gigabit Ethernet" }, 100 { PCI_VENDOR_ATTANSIC, PCI_PRODUCT_ATTANSIC_AR8162, 9 * 1024, 101 "Atheros AR8162 PCIe Fast Ethernet" }, 102 { PCI_VENDOR_ATTANSIC, PCI_PRODUCT_ATTANSIC_AR8171, 9 * 1024, 103 "Atheros AR8171 PCIe Gigabit Ethernet" }, 104 { PCI_VENDOR_ATTANSIC, PCI_PRODUCT_ATTANSIC_AR8172, 9 * 1024, 105 "Atheros AR8172 PCIe Fast Ethernet" }, 106 { PCI_VENDOR_ATTANSIC, PCI_PRODUCT_ATTANSIC_E2200, 9 * 1024, 107 "Killer E2200 Gigabit Ethernet" }, 108 { 0, 0, 0, NULL }, 109 }; 110 111 static int alc_match(device_t, cfdata_t, void *); 112 static void alc_attach(device_t, device_t, void *); 113 static int alc_detach(device_t, int); 114 115 static int alc_init(struct ifnet *); 116 static int alc_init_backend(struct ifnet *, bool); 117 static void alc_start(struct ifnet *); 118 static int alc_ioctl(struct ifnet *, u_long, void *); 119 static void alc_watchdog(struct ifnet *); 120 static int alc_mediachange(struct ifnet *); 121 static void alc_mediastatus(struct ifnet *, struct ifmediareq *); 122 123 static void alc_aspm(struct alc_softc *, int, int); 124 static void alc_aspm_813x(struct alc_softc *, int); 125 static void alc_aspm_816x(struct alc_softc *, int); 126 static void alc_disable_l0s_l1(struct alc_softc *); 127 static int alc_dma_alloc(struct alc_softc *); 128 static void alc_dma_free(struct alc_softc *); 129 static void alc_dsp_fixup(struct alc_softc *, int); 130 static int alc_encap(struct alc_softc *, struct mbuf **); 131 static struct alc_ident * 132 alc_find_ident(struct pci_attach_args *); 133 static void alc_get_macaddr(struct alc_softc *); 134 static void alc_get_macaddr_813x(struct alc_softc *); 135 static void alc_get_macaddr_816x(struct alc_softc *); 136 static void alc_get_macaddr_par(struct alc_softc *); 137 static void alc_init_cmb(struct alc_softc *); 138 static void alc_init_rr_ring(struct alc_softc *); 139 static int alc_init_rx_ring(struct alc_softc *, bool); 140 static void alc_init_smb(struct alc_softc *); 141 static void alc_init_tx_ring(struct alc_softc *); 142 static int alc_intr(void *); 143 static void alc_mac_config(struct alc_softc *); 144 static uint32_t alc_mii_readreg_813x(struct alc_softc *, int, int); 145 static uint32_t alc_mii_readreg_816x(struct alc_softc *, int, int); 146 static void alc_mii_writereg_813x(struct alc_softc *, int, int, int); 147 static void alc_mii_writereg_816x(struct alc_softc *, int, int, int); 148 static int alc_miibus_readreg(device_t, int, int); 149 static void alc_miibus_statchg(struct ifnet *); 150 static void alc_miibus_writereg(device_t, int, int, int); 151 static uint32_t alc_miidbg_readreg(struct alc_softc *, int); 152 static void alc_miidbg_writereg(struct alc_softc *, int, int); 153 static uint32_t alc_miiext_readreg(struct alc_softc *, int, int); 154 static uint32_t alc_miiext_writereg(struct alc_softc *, int, int, int); 155 static int alc_newbuf(struct alc_softc *, struct alc_rxdesc *, bool); 156 static void alc_phy_down(struct alc_softc *); 157 static void alc_phy_reset(struct alc_softc *); 158 static void alc_phy_reset_813x(struct alc_softc *); 159 static void alc_phy_reset_816x(struct alc_softc *); 160 static void alc_reset(struct alc_softc *); 161 static void alc_rxeof(struct alc_softc *, struct rx_rdesc *); 162 static int alc_rxintr(struct alc_softc *); 163 static void alc_iff(struct alc_softc *); 164 static void alc_rxvlan(struct alc_softc *); 165 static void alc_start_queue(struct alc_softc *); 166 static void alc_stats_clear(struct alc_softc *); 167 static void alc_stats_update(struct alc_softc *); 168 static void alc_stop(struct ifnet *, int); 169 static void alc_stop_mac(struct alc_softc *); 170 static void alc_stop_queue(struct alc_softc *); 171 static void alc_tick(void *); 172 static void alc_txeof(struct alc_softc *); 173 174 uint32_t alc_dma_burst[] = { 128, 256, 512, 1024, 2048, 4096, 0 }; 175 176 CFATTACH_DECL_NEW(alc, sizeof(struct alc_softc), 177 alc_match, alc_attach, alc_detach, NULL); 178 179 int alcdebug = 0; 180 #define DPRINTF(x) do { if (alcdebug) printf x; } while (0) 181 182 #define ETHER_ALIGN 2 183 #define ALC_CSUM_FEATURES (M_CSUM_TCPv4 | M_CSUM_UDPv4) 184 185 static int 186 alc_miibus_readreg(device_t dev, int phy, int reg) 187 { 188 struct alc_softc *sc = device_private(dev); 189 int v; 190 191 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 192 v = alc_mii_readreg_816x(sc, phy, reg); 193 else 194 v = alc_mii_readreg_813x(sc, phy, reg); 195 return (v); 196 } 197 198 static uint32_t 199 alc_mii_readreg_813x(struct alc_softc *sc, int phy, int reg) 200 { 201 uint32_t v; 202 int i; 203 204 if (phy != sc->alc_phyaddr) 205 return (0); 206 207 /* 208 * For AR8132 fast ethernet controller, do not report 1000baseT 209 * capability to mii(4). Even though AR8132 uses the same 210 * model/revision number of F1 gigabit PHY, the PHY has no 211 * ability to establish 1000baseT link. 212 */ 213 if ((sc->alc_flags & ALC_FLAG_FASTETHER) != 0 && 214 reg == MII_EXTSR) 215 return 0; 216 217 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ | 218 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); 219 for (i = ALC_PHY_TIMEOUT; i > 0; i--) { 220 DELAY(5); 221 v = CSR_READ_4(sc, ALC_MDIO); 222 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) 223 break; 224 } 225 226 if (i == 0) { 227 printf("%s: phy read timeout: phy %d, reg %d\n", 228 device_xname(sc->sc_dev), phy, reg); 229 return (0); 230 } 231 232 return ((v & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT); 233 } 234 235 static uint32_t 236 alc_mii_readreg_816x(struct alc_softc *sc, int phy, int reg) 237 { 238 uint32_t clk, v; 239 int i; 240 241 if (phy != sc->alc_phyaddr) 242 return (0); 243 244 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) 245 clk = MDIO_CLK_25_128; 246 else 247 clk = MDIO_CLK_25_4; 248 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ | 249 MDIO_SUP_PREAMBLE | clk | MDIO_REG_ADDR(reg)); 250 for (i = ALC_PHY_TIMEOUT; i > 0; i--) { 251 DELAY(5); 252 v = CSR_READ_4(sc, ALC_MDIO); 253 if ((v & MDIO_OP_BUSY) == 0) 254 break; 255 } 256 257 if (i == 0) { 258 printf("%s: phy read timeout: phy %d, reg %d\n", 259 device_xname(sc->sc_dev), phy, reg); 260 return (0); 261 } 262 263 return ((v & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT); 264 } 265 266 static void 267 alc_miibus_writereg(device_t dev, int phy, int reg, int val) 268 { 269 struct alc_softc *sc = device_private(dev); 270 271 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 272 alc_mii_writereg_816x(sc, phy, reg, val); 273 else 274 alc_mii_writereg_813x(sc, phy, reg, val); 275 276 return; 277 } 278 279 static void 280 alc_mii_writereg_813x(struct alc_softc *sc, int phy, int reg, int val) 281 { 282 uint32_t v; 283 int i; 284 285 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE | 286 (val & MDIO_DATA_MASK) << MDIO_DATA_SHIFT | 287 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); 288 for (i = ALC_PHY_TIMEOUT; i > 0; i--) { 289 DELAY(5); 290 v = CSR_READ_4(sc, ALC_MDIO); 291 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) 292 break; 293 } 294 295 if (i == 0) 296 printf("%s: phy write timeout: phy %d, reg %d\n", 297 device_xname(sc->sc_dev), phy, reg); 298 299 return; 300 } 301 302 static void 303 alc_mii_writereg_816x(struct alc_softc *sc, int phy, int reg, int val) 304 { 305 uint32_t clk, v; 306 int i; 307 308 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) 309 clk = MDIO_CLK_25_128; 310 else 311 clk = MDIO_CLK_25_4; 312 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE | 313 ((val & MDIO_DATA_MASK) << MDIO_DATA_SHIFT) | MDIO_REG_ADDR(reg) | 314 MDIO_SUP_PREAMBLE | clk); 315 for (i = ALC_PHY_TIMEOUT; i > 0; i--) { 316 DELAY(5); 317 v = CSR_READ_4(sc, ALC_MDIO); 318 if ((v & MDIO_OP_BUSY) == 0) 319 break; 320 } 321 322 if (i == 0) 323 printf("%s: phy write timeout: phy %d, reg %d\n", 324 device_xname(sc->sc_dev), phy, reg); 325 326 return; 327 } 328 329 static void 330 alc_miibus_statchg(struct ifnet *ifp) 331 { 332 struct alc_softc *sc = ifp->if_softc; 333 struct mii_data *mii = &sc->sc_miibus; 334 uint32_t reg; 335 336 if ((ifp->if_flags & IFF_RUNNING) == 0) 337 return; 338 339 sc->alc_flags &= ~ALC_FLAG_LINK; 340 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 341 (IFM_ACTIVE | IFM_AVALID)) { 342 switch (IFM_SUBTYPE(mii->mii_media_active)) { 343 case IFM_10_T: 344 case IFM_100_TX: 345 sc->alc_flags |= ALC_FLAG_LINK; 346 break; 347 case IFM_1000_T: 348 if ((sc->alc_flags & ALC_FLAG_FASTETHER) == 0) 349 sc->alc_flags |= ALC_FLAG_LINK; 350 break; 351 default: 352 break; 353 } 354 } 355 /* Stop Rx/Tx MACs. */ 356 alc_stop_mac(sc); 357 358 /* Program MACs with resolved speed/duplex/flow-control. */ 359 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) { 360 alc_start_queue(sc); 361 alc_mac_config(sc); 362 /* Re-enable Tx/Rx MACs. */ 363 reg = CSR_READ_4(sc, ALC_MAC_CFG); 364 reg |= MAC_CFG_TX_ENB | MAC_CFG_RX_ENB; 365 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 366 } 367 alc_aspm(sc, 0, IFM_SUBTYPE(mii->mii_media_active)); 368 alc_dsp_fixup(sc, IFM_SUBTYPE(mii->mii_media_active)); 369 } 370 371 static uint32_t 372 alc_miidbg_readreg(struct alc_softc *sc, int reg) 373 { 374 375 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, ALC_MII_DBG_ADDR, 376 reg); 377 return (alc_miibus_readreg(sc->sc_dev, sc->alc_phyaddr, 378 ALC_MII_DBG_DATA)); 379 } 380 381 static void 382 alc_miidbg_writereg(struct alc_softc *sc, int reg, int val) 383 { 384 385 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, ALC_MII_DBG_ADDR, 386 reg); 387 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, ALC_MII_DBG_DATA, val); 388 389 return; 390 } 391 392 static uint32_t 393 alc_miiext_readreg(struct alc_softc *sc, int devaddr, int reg) 394 { 395 uint32_t clk, v; 396 int i; 397 398 CSR_WRITE_4(sc, ALC_EXT_MDIO, EXT_MDIO_REG(reg) | 399 EXT_MDIO_DEVADDR(devaddr)); 400 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) 401 clk = MDIO_CLK_25_128; 402 else 403 clk = MDIO_CLK_25_4; 404 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ | 405 MDIO_SUP_PREAMBLE | clk | MDIO_MODE_EXT); 406 for (i = ALC_PHY_TIMEOUT; i > 0; i--) { 407 DELAY(5); 408 v = CSR_READ_4(sc, ALC_MDIO); 409 if ((v & MDIO_OP_BUSY) == 0) 410 break; 411 } 412 413 if (i == 0) { 414 printf("%s: phy ext read timeout: %d\n", 415 device_xname(sc->sc_dev), reg); 416 return (0); 417 } 418 419 return ((v & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT); 420 } 421 422 static uint32_t 423 alc_miiext_writereg(struct alc_softc *sc, int devaddr, int reg, int val) 424 { 425 uint32_t clk, v; 426 int i; 427 428 CSR_WRITE_4(sc, ALC_EXT_MDIO, EXT_MDIO_REG(reg) | 429 EXT_MDIO_DEVADDR(devaddr)); 430 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) 431 clk = MDIO_CLK_25_128; 432 else 433 clk = MDIO_CLK_25_4; 434 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE | 435 ((val & MDIO_DATA_MASK) << MDIO_DATA_SHIFT) | 436 MDIO_SUP_PREAMBLE | clk | MDIO_MODE_EXT); 437 for (i = ALC_PHY_TIMEOUT; i > 0; i--) { 438 DELAY(5); 439 v = CSR_READ_4(sc, ALC_MDIO); 440 if ((v & MDIO_OP_BUSY) == 0) 441 break; 442 } 443 444 if (i == 0) { 445 printf("%s: phy ext write timeout: reg %d\n", 446 device_xname(sc->sc_dev), reg); 447 return (0); 448 } 449 450 return (0); 451 } 452 453 static void 454 alc_dsp_fixup(struct alc_softc *sc, int media) 455 { 456 uint16_t agc, len, val; 457 458 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 459 return; 460 if (AR816X_REV(sc->alc_rev) >= AR816X_REV_C0) 461 return; 462 463 /* 464 * Vendor PHY magic. 465 * 1000BT/AZ, wrong cable length 466 */ 467 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) { 468 len = alc_miiext_readreg(sc, MII_EXT_PCS, MII_EXT_CLDCTL6); 469 len = (len >> EXT_CLDCTL6_CAB_LEN_SHIFT) & 470 EXT_CLDCTL6_CAB_LEN_MASK; 471 /* XXX: used to be (alc >> shift) & mask which is 0 */ 472 agc = alc_miidbg_readreg(sc, MII_DBG_AGC) & DBG_AGC_2_VGA_MASK; 473 agc >>= DBG_AGC_2_VGA_SHIFT; 474 if ((media == IFM_1000_T && len > EXT_CLDCTL6_CAB_LEN_SHORT1G && 475 agc > DBG_AGC_LONG1G_LIMT) || 476 (media == IFM_100_TX && len > DBG_AGC_LONG100M_LIMT && 477 agc > DBG_AGC_LONG1G_LIMT)) { 478 alc_miidbg_writereg(sc, MII_DBG_AZ_ANADECT, 479 DBG_AZ_ANADECT_LONG); 480 val = alc_miiext_readreg(sc, MII_EXT_ANEG, 481 MII_EXT_ANEG_AFE); 482 val |= ANEG_AFEE_10BT_100M_TH; 483 alc_miiext_writereg(sc, MII_EXT_ANEG, MII_EXT_ANEG_AFE, 484 val); 485 } else { 486 alc_miidbg_writereg(sc, MII_DBG_AZ_ANADECT, 487 DBG_AZ_ANADECT_DEFAULT); 488 val = alc_miiext_readreg(sc, MII_EXT_ANEG, 489 MII_EXT_ANEG_AFE); 490 val &= ~ANEG_AFEE_10BT_100M_TH; 491 alc_miiext_writereg(sc, MII_EXT_ANEG, MII_EXT_ANEG_AFE, 492 val); 493 } 494 if ((sc->alc_flags & ALC_FLAG_LINK_WAR) != 0 && 495 AR816X_REV(sc->alc_rev) == AR816X_REV_B0) { 496 if (media == IFM_1000_T) { 497 /* 498 * Giga link threshold, raise the tolerance of 499 * noise 50%. 500 */ 501 val = alc_miidbg_readreg(sc, MII_DBG_MSE20DB); 502 val &= ~DBG_MSE20DB_TH_MASK; 503 val |= (DBG_MSE20DB_TH_HI << 504 DBG_MSE20DB_TH_SHIFT); 505 alc_miidbg_writereg(sc, MII_DBG_MSE20DB, val); 506 } else if (media == IFM_100_TX) 507 alc_miidbg_writereg(sc, MII_DBG_MSE16DB, 508 DBG_MSE16DB_UP); 509 } 510 } else { 511 val = alc_miiext_readreg(sc, MII_EXT_ANEG, MII_EXT_ANEG_AFE); 512 val &= ~ANEG_AFEE_10BT_100M_TH; 513 alc_miiext_writereg(sc, MII_EXT_ANEG, MII_EXT_ANEG_AFE, val); 514 if ((sc->alc_flags & ALC_FLAG_LINK_WAR) != 0 && 515 AR816X_REV(sc->alc_rev) == AR816X_REV_B0) { 516 alc_miidbg_writereg(sc, MII_DBG_MSE16DB, 517 DBG_MSE16DB_DOWN); 518 val = alc_miidbg_readreg(sc, MII_DBG_MSE20DB); 519 val &= ~DBG_MSE20DB_TH_MASK; 520 val |= (DBG_MSE20DB_TH_DEFAULT << DBG_MSE20DB_TH_SHIFT); 521 alc_miidbg_writereg(sc, MII_DBG_MSE20DB, val); 522 } 523 } 524 } 525 526 static void 527 alc_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 528 { 529 struct alc_softc *sc = ifp->if_softc; 530 struct mii_data *mii = &sc->sc_miibus; 531 532 mii_pollstat(mii); 533 ifmr->ifm_status = mii->mii_media_status; 534 ifmr->ifm_active = mii->mii_media_active; 535 } 536 537 static int 538 alc_mediachange(struct ifnet *ifp) 539 { 540 struct alc_softc *sc = ifp->if_softc; 541 struct mii_data *mii = &sc->sc_miibus; 542 int error; 543 544 if (mii->mii_instance != 0) { 545 struct mii_softc *miisc; 546 547 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 548 mii_phy_reset(miisc); 549 } 550 error = mii_mediachg(mii); 551 552 return (error); 553 } 554 555 static struct alc_ident * 556 alc_find_ident(struct pci_attach_args *pa) 557 { 558 struct alc_ident *ident; 559 uint16_t vendor, devid; 560 561 vendor = PCI_VENDOR(pa->pa_id); 562 devid = PCI_PRODUCT(pa->pa_id); 563 for (ident = alc_ident_table; ident->name != NULL; ident++) { 564 if (vendor == ident->vendorid && devid == ident->deviceid) 565 return (ident); 566 } 567 568 return (NULL); 569 } 570 571 static int 572 alc_match(device_t dev, cfdata_t match, void *aux) 573 { 574 struct pci_attach_args *pa = aux; 575 576 return alc_find_ident(pa) != NULL; 577 } 578 579 static void 580 alc_get_macaddr(struct alc_softc *sc) 581 { 582 583 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 584 alc_get_macaddr_816x(sc); 585 else 586 alc_get_macaddr_813x(sc); 587 } 588 589 static void 590 alc_get_macaddr_813x(struct alc_softc *sc) 591 { 592 uint32_t opt; 593 uint16_t val; 594 int eeprom, i; 595 596 eeprom = 0; 597 opt = CSR_READ_4(sc, ALC_OPT_CFG); 598 if ((CSR_READ_4(sc, ALC_MASTER_CFG) & MASTER_OTP_SEL) != 0 && 599 (CSR_READ_4(sc, ALC_TWSI_DEBUG) & TWSI_DEBUG_DEV_EXIST) != 0) { 600 /* 601 * EEPROM found, let TWSI reload EEPROM configuration. 602 * This will set ethernet address of controller. 603 */ 604 eeprom++; 605 switch (sc->alc_ident->deviceid) { 606 case PCI_PRODUCT_ATTANSIC_AR8131: 607 case PCI_PRODUCT_ATTANSIC_AR8132: 608 if ((opt & OPT_CFG_CLK_ENB) == 0) { 609 opt |= OPT_CFG_CLK_ENB; 610 CSR_WRITE_4(sc, ALC_OPT_CFG, opt); 611 CSR_READ_4(sc, ALC_OPT_CFG); 612 DELAY(1000); 613 } 614 break; 615 case PCI_PRODUCT_ATTANSIC_AR8151: 616 case PCI_PRODUCT_ATTANSIC_AR8151_V2: 617 case PCI_PRODUCT_ATTANSIC_AR8152_B: 618 case PCI_PRODUCT_ATTANSIC_AR8152_B2: 619 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 620 ALC_MII_DBG_ADDR, 0x00); 621 val = alc_miibus_readreg(sc->sc_dev, sc->alc_phyaddr, 622 ALC_MII_DBG_DATA); 623 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 624 ALC_MII_DBG_DATA, val & 0xFF7F); 625 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 626 ALC_MII_DBG_ADDR, 0x3B); 627 val = alc_miibus_readreg(sc->sc_dev, sc->alc_phyaddr, 628 ALC_MII_DBG_DATA); 629 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 630 ALC_MII_DBG_DATA, val | 0x0008); 631 DELAY(20); 632 break; 633 } 634 635 CSR_WRITE_4(sc, ALC_LTSSM_ID_CFG, 636 CSR_READ_4(sc, ALC_LTSSM_ID_CFG) & ~LTSSM_ID_WRO_ENB); 637 CSR_WRITE_4(sc, ALC_WOL_CFG, 0); 638 CSR_READ_4(sc, ALC_WOL_CFG); 639 640 CSR_WRITE_4(sc, ALC_TWSI_CFG, CSR_READ_4(sc, ALC_TWSI_CFG) | 641 TWSI_CFG_SW_LD_START); 642 for (i = 100; i > 0; i--) { 643 DELAY(1000); 644 if ((CSR_READ_4(sc, ALC_TWSI_CFG) & 645 TWSI_CFG_SW_LD_START) == 0) 646 break; 647 } 648 if (i == 0) 649 printf("%s: reloading EEPROM timeout!\n", 650 device_xname(sc->sc_dev)); 651 } else { 652 if (alcdebug) 653 printf("%s: EEPROM not found!\n", device_xname(sc->sc_dev)); 654 } 655 if (eeprom != 0) { 656 switch (sc->alc_ident->deviceid) { 657 case PCI_PRODUCT_ATTANSIC_AR8131: 658 case PCI_PRODUCT_ATTANSIC_AR8132: 659 if ((opt & OPT_CFG_CLK_ENB) != 0) { 660 opt &= ~OPT_CFG_CLK_ENB; 661 CSR_WRITE_4(sc, ALC_OPT_CFG, opt); 662 CSR_READ_4(sc, ALC_OPT_CFG); 663 DELAY(1000); 664 } 665 break; 666 case PCI_PRODUCT_ATTANSIC_AR8151: 667 case PCI_PRODUCT_ATTANSIC_AR8151_V2: 668 case PCI_PRODUCT_ATTANSIC_AR8152_B: 669 case PCI_PRODUCT_ATTANSIC_AR8152_B2: 670 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 671 ALC_MII_DBG_ADDR, 0x00); 672 val = alc_miibus_readreg(sc->sc_dev, sc->alc_phyaddr, 673 ALC_MII_DBG_DATA); 674 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 675 ALC_MII_DBG_DATA, val | 0x0080); 676 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 677 ALC_MII_DBG_ADDR, 0x3B); 678 val = alc_miibus_readreg(sc->sc_dev, sc->alc_phyaddr, 679 ALC_MII_DBG_DATA); 680 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 681 ALC_MII_DBG_DATA, val & 0xFFF7); 682 DELAY(20); 683 break; 684 } 685 } 686 687 alc_get_macaddr_par(sc); 688 } 689 690 static void 691 alc_get_macaddr_816x(struct alc_softc *sc) 692 { 693 uint32_t reg; 694 int i, reloaded; 695 696 reloaded = 0; 697 /* Try to reload station address via TWSI. */ 698 for (i = 100; i > 0; i--) { 699 reg = CSR_READ_4(sc, ALC_SLD); 700 if ((reg & (SLD_PROGRESS | SLD_START)) == 0) 701 break; 702 DELAY(1000); 703 } 704 if (i != 0) { 705 CSR_WRITE_4(sc, ALC_SLD, reg | SLD_START); 706 for (i = 100; i > 0; i--) { 707 DELAY(1000); 708 reg = CSR_READ_4(sc, ALC_SLD); 709 if ((reg & SLD_START) == 0) 710 break; 711 } 712 if (i != 0) 713 reloaded++; 714 else if (alcdebug) 715 printf("%s: reloading station address via TWSI timed out!\n", 716 device_xname(sc->sc_dev)); 717 } 718 719 /* Try to reload station address from EEPROM or FLASH. */ 720 if (reloaded == 0) { 721 reg = CSR_READ_4(sc, ALC_EEPROM_LD); 722 if ((reg & (EEPROM_LD_EEPROM_EXIST | 723 EEPROM_LD_FLASH_EXIST)) != 0) { 724 for (i = 100; i > 0; i--) { 725 reg = CSR_READ_4(sc, ALC_EEPROM_LD); 726 if ((reg & (EEPROM_LD_PROGRESS | 727 EEPROM_LD_START)) == 0) 728 break; 729 DELAY(1000); 730 } 731 if (i != 0) { 732 CSR_WRITE_4(sc, ALC_EEPROM_LD, reg | 733 EEPROM_LD_START); 734 for (i = 100; i > 0; i--) { 735 DELAY(1000); 736 reg = CSR_READ_4(sc, ALC_EEPROM_LD); 737 if ((reg & EEPROM_LD_START) == 0) 738 break; 739 } 740 } else if (alcdebug) 741 printf("%s: reloading EEPROM/FLASH timed out!\n", 742 device_xname(sc->sc_dev)); 743 } 744 } 745 746 alc_get_macaddr_par(sc); 747 } 748 749 750 static void 751 alc_get_macaddr_par(struct alc_softc *sc) 752 { 753 uint32_t ea[2]; 754 755 ea[0] = CSR_READ_4(sc, ALC_PAR0); 756 ea[1] = CSR_READ_4(sc, ALC_PAR1); 757 sc->alc_eaddr[0] = (ea[1] >> 8) & 0xFF; 758 sc->alc_eaddr[1] = (ea[1] >> 0) & 0xFF; 759 sc->alc_eaddr[2] = (ea[0] >> 24) & 0xFF; 760 sc->alc_eaddr[3] = (ea[0] >> 16) & 0xFF; 761 sc->alc_eaddr[4] = (ea[0] >> 8) & 0xFF; 762 sc->alc_eaddr[5] = (ea[0] >> 0) & 0xFF; 763 } 764 765 static void 766 alc_disable_l0s_l1(struct alc_softc *sc) 767 { 768 uint32_t pmcfg; 769 770 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 771 /* Another magic from vendor. */ 772 pmcfg = CSR_READ_4(sc, ALC_PM_CFG); 773 pmcfg &= ~(PM_CFG_L1_ENTRY_TIMER_MASK | PM_CFG_CLK_SWH_L1 | 774 PM_CFG_ASPM_L0S_ENB | PM_CFG_ASPM_L1_ENB | 775 PM_CFG_MAC_ASPM_CHK | PM_CFG_SERDES_PD_EX_L1); 776 pmcfg |= PM_CFG_SERDES_BUDS_RX_L1_ENB | 777 PM_CFG_SERDES_PLL_L1_ENB | PM_CFG_SERDES_L1_ENB; 778 CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg); 779 } 780 } 781 782 static void 783 alc_phy_reset(struct alc_softc *sc) 784 { 785 786 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 787 alc_phy_reset_816x(sc); 788 else 789 alc_phy_reset_813x(sc); 790 } 791 792 static void 793 alc_phy_reset_813x(struct alc_softc *sc) 794 { 795 uint16_t data; 796 797 /* Reset magic from Linux. */ 798 CSR_WRITE_2(sc, ALC_GPHY_CFG, GPHY_CFG_SEL_ANA_RESET); 799 CSR_READ_2(sc, ALC_GPHY_CFG); 800 DELAY(10 * 1000); 801 802 CSR_WRITE_2(sc, ALC_GPHY_CFG, GPHY_CFG_EXT_RESET | 803 GPHY_CFG_SEL_ANA_RESET); 804 CSR_READ_2(sc, ALC_GPHY_CFG); 805 DELAY(10 * 1000); 806 807 /* DSP fixup, Vendor magic. */ 808 if (sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8152_B) { 809 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 810 ALC_MII_DBG_ADDR, 0x000A); 811 data = alc_miibus_readreg(sc->sc_dev, sc->alc_phyaddr, 812 ALC_MII_DBG_DATA); 813 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 814 ALC_MII_DBG_DATA, data & 0xDFFF); 815 } 816 if (sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8151 || 817 sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8151_V2 || 818 sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8152_B || 819 sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8152_B2) { 820 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 821 ALC_MII_DBG_ADDR, 0x003B); 822 data = alc_miibus_readreg(sc->sc_dev, sc->alc_phyaddr, 823 ALC_MII_DBG_DATA); 824 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 825 ALC_MII_DBG_DATA, data & 0xFFF7); 826 DELAY(20 * 1000); 827 } 828 if (sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8151) { 829 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 830 ALC_MII_DBG_ADDR, 0x0029); 831 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 832 ALC_MII_DBG_DATA, 0x929D); 833 } 834 if (sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8131 || 835 sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8132 || 836 sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8151_V2 || 837 sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8152_B2) { 838 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 839 ALC_MII_DBG_ADDR, 0x0029); 840 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 841 ALC_MII_DBG_DATA, 0xB6DD); 842 } 843 844 /* Load DSP codes, vendor magic. */ 845 data = ANA_LOOP_SEL_10BT | ANA_EN_MASK_TB | ANA_EN_10BT_IDLE | 846 ((1 << ANA_INTERVAL_SEL_TIMER_SHIFT) & ANA_INTERVAL_SEL_TIMER_MASK); 847 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 848 ALC_MII_DBG_ADDR, MII_ANA_CFG18); 849 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 850 ALC_MII_DBG_DATA, data); 851 852 data = ((2 << ANA_SERDES_CDR_BW_SHIFT) & ANA_SERDES_CDR_BW_MASK) | 853 ANA_SERDES_EN_DEEM | ANA_SERDES_SEL_HSP | ANA_SERDES_EN_PLL | 854 ANA_SERDES_EN_LCKDT; 855 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 856 ALC_MII_DBG_ADDR, MII_ANA_CFG5); 857 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 858 ALC_MII_DBG_DATA, data); 859 860 data = ((44 << ANA_LONG_CABLE_TH_100_SHIFT) & 861 ANA_LONG_CABLE_TH_100_MASK) | 862 ((33 << ANA_SHORT_CABLE_TH_100_SHIFT) & 863 ANA_SHORT_CABLE_TH_100_SHIFT) | 864 ANA_BP_BAD_LINK_ACCUM | ANA_BP_SMALL_BW; 865 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 866 ALC_MII_DBG_ADDR, MII_ANA_CFG54); 867 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 868 ALC_MII_DBG_DATA, data); 869 870 data = ((11 << ANA_IECHO_ADJ_3_SHIFT) & ANA_IECHO_ADJ_3_MASK) | 871 ((11 << ANA_IECHO_ADJ_2_SHIFT) & ANA_IECHO_ADJ_2_MASK) | 872 ((8 << ANA_IECHO_ADJ_1_SHIFT) & ANA_IECHO_ADJ_1_MASK) | 873 ((8 << ANA_IECHO_ADJ_0_SHIFT) & ANA_IECHO_ADJ_0_MASK); 874 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 875 ALC_MII_DBG_ADDR, MII_ANA_CFG4); 876 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 877 ALC_MII_DBG_DATA, data); 878 879 data = ((7 & ANA_MANUL_SWICH_ON_SHIFT) & ANA_MANUL_SWICH_ON_MASK) | 880 ANA_RESTART_CAL | ANA_MAN_ENABLE | ANA_SEL_HSP | ANA_EN_HB | 881 ANA_OEN_125M; 882 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 883 ALC_MII_DBG_ADDR, MII_ANA_CFG0); 884 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 885 ALC_MII_DBG_DATA, data); 886 DELAY(1000); 887 888 /* Disable hibernation. */ 889 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, ALC_MII_DBG_ADDR, 890 0x0029); 891 data = alc_miibus_readreg(sc->sc_dev, sc->alc_phyaddr, 892 ALC_MII_DBG_DATA); 893 data &= ~0x8000; 894 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, ALC_MII_DBG_DATA, 895 data); 896 897 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, ALC_MII_DBG_ADDR, 898 0x000B); 899 data = alc_miibus_readreg(sc->sc_dev, sc->alc_phyaddr, 900 ALC_MII_DBG_DATA); 901 data &= ~0x8000; 902 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, ALC_MII_DBG_DATA, 903 data); 904 } 905 906 static void 907 alc_phy_reset_816x(struct alc_softc *sc) 908 { 909 uint32_t val; 910 911 val = CSR_READ_4(sc, ALC_GPHY_CFG); 912 val &= ~(GPHY_CFG_EXT_RESET | GPHY_CFG_LED_MODE | 913 GPHY_CFG_GATE_25M_ENB | GPHY_CFG_PHY_IDDQ | GPHY_CFG_PHY_PLL_ON | 914 GPHY_CFG_PWDOWN_HW | GPHY_CFG_100AB_ENB); 915 val |= GPHY_CFG_SEL_ANA_RESET; 916 #ifdef notyet 917 val |= GPHY_CFG_HIB_PULSE | GPHY_CFG_HIB_EN | GPHY_CFG_SEL_ANA_RESET; 918 #else 919 /* Disable PHY hibernation. */ 920 val &= ~(GPHY_CFG_HIB_PULSE | GPHY_CFG_HIB_EN); 921 #endif 922 CSR_WRITE_4(sc, ALC_GPHY_CFG, val); 923 DELAY(10); 924 CSR_WRITE_4(sc, ALC_GPHY_CFG, val | GPHY_CFG_EXT_RESET); 925 DELAY(800); 926 927 /* Vendor PHY magic. */ 928 #ifdef notyet 929 alc_miidbg_writereg(sc, MII_DBG_LEGCYPS, DBG_LEGCYPS_DEFAULT); 930 alc_miidbg_writereg(sc, MII_DBG_SYSMODCTL, DBG_SYSMODCTL_DEFAULT); 931 alc_miiext_writereg(sc, MII_EXT_PCS, MII_EXT_VDRVBIAS, 932 EXT_VDRVBIAS_DEFAULT); 933 #else 934 /* Disable PHY hibernation. */ 935 alc_miidbg_writereg(sc, MII_DBG_LEGCYPS, 936 DBG_LEGCYPS_DEFAULT & ~DBG_LEGCYPS_ENB); 937 alc_miidbg_writereg(sc, MII_DBG_HIBNEG, 938 DBG_HIBNEG_DEFAULT & ~(DBG_HIBNEG_PSHIB_EN | DBG_HIBNEG_HIB_PULSE)); 939 alc_miidbg_writereg(sc, MII_DBG_GREENCFG, DBG_GREENCFG_DEFAULT); 940 #endif 941 942 /* XXX Disable EEE. */ 943 val = CSR_READ_4(sc, ALC_LPI_CTL); 944 val &= ~LPI_CTL_ENB; 945 CSR_WRITE_4(sc, ALC_LPI_CTL, val); 946 alc_miiext_writereg(sc, MII_EXT_ANEG, MII_EXT_ANEG_LOCAL_EEEADV, 0); 947 948 /* PHY power saving. */ 949 alc_miidbg_writereg(sc, MII_DBG_TST10BTCFG, DBG_TST10BTCFG_DEFAULT); 950 alc_miidbg_writereg(sc, MII_DBG_SRDSYSMOD, DBG_SRDSYSMOD_DEFAULT); 951 alc_miidbg_writereg(sc, MII_DBG_TST100BTCFG, DBG_TST100BTCFG_DEFAULT); 952 alc_miidbg_writereg(sc, MII_DBG_ANACTL, DBG_ANACTL_DEFAULT); 953 val = alc_miidbg_readreg(sc, MII_DBG_GREENCFG2); 954 val &= ~DBG_GREENCFG2_GATE_DFSE_EN; 955 alc_miidbg_writereg(sc, MII_DBG_GREENCFG2, val); 956 957 /* RTL8139C, 120m issue. */ 958 alc_miiext_writereg(sc, MII_EXT_ANEG, MII_EXT_ANEG_NLP78, 959 ANEG_NLP78_120M_DEFAULT); 960 alc_miiext_writereg(sc, MII_EXT_ANEG, MII_EXT_ANEG_S3DIG10, 961 ANEG_S3DIG10_DEFAULT); 962 963 if ((sc->alc_flags & ALC_FLAG_LINK_WAR) != 0) { 964 /* Turn off half amplitude. */ 965 val = alc_miiext_readreg(sc, MII_EXT_PCS, MII_EXT_CLDCTL3); 966 val |= EXT_CLDCTL3_BP_CABLE1TH_DET_GT; 967 alc_miiext_writereg(sc, MII_EXT_PCS, MII_EXT_CLDCTL3, val); 968 /* Turn off Green feature. */ 969 val = alc_miidbg_readreg(sc, MII_DBG_GREENCFG2); 970 val |= DBG_GREENCFG2_BP_GREEN; 971 alc_miidbg_writereg(sc, MII_DBG_GREENCFG2, val); 972 /* Turn off half bias. */ 973 val = alc_miiext_readreg(sc, MII_EXT_PCS, MII_EXT_CLDCTL5); 974 val |= EXT_CLDCTL5_BP_VD_HLFBIAS; 975 alc_miiext_writereg(sc, MII_EXT_PCS, MII_EXT_CLDCTL5, val); 976 } 977 } 978 979 static void 980 alc_phy_down(struct alc_softc *sc) 981 { 982 uint32_t gphy; 983 984 switch (sc->alc_ident->deviceid) { 985 case PCI_PRODUCT_ATTANSIC_AR8161: 986 case PCI_PRODUCT_ATTANSIC_E2200: 987 case PCI_PRODUCT_ATTANSIC_AR8162: 988 case PCI_PRODUCT_ATTANSIC_AR8171: 989 case PCI_PRODUCT_ATTANSIC_AR8172: 990 gphy = CSR_READ_4(sc, ALC_GPHY_CFG); 991 gphy &= ~(GPHY_CFG_EXT_RESET | GPHY_CFG_LED_MODE | 992 GPHY_CFG_100AB_ENB | GPHY_CFG_PHY_PLL_ON); 993 gphy |= GPHY_CFG_HIB_EN | GPHY_CFG_HIB_PULSE | 994 GPHY_CFG_SEL_ANA_RESET; 995 gphy |= GPHY_CFG_PHY_IDDQ | GPHY_CFG_PWDOWN_HW; 996 CSR_WRITE_4(sc, ALC_GPHY_CFG, gphy); 997 break; 998 case PCI_PRODUCT_ATTANSIC_AR8151: 999 case PCI_PRODUCT_ATTANSIC_AR8151_V2: 1000 case PCI_PRODUCT_ATTANSIC_AR8152_B: 1001 case PCI_PRODUCT_ATTANSIC_AR8152_B2: 1002 /* 1003 * GPHY power down caused more problems on AR8151 v2.0. 1004 * When driver is reloaded after GPHY power down, 1005 * accesses to PHY/MAC registers hung the system. Only 1006 * cold boot recovered from it. I'm not sure whether 1007 * AR8151 v1.0 also requires this one though. I don't 1008 * have AR8151 v1.0 controller in hand. 1009 * The only option left is to isolate the PHY and 1010 * initiates power down the PHY which in turn saves 1011 * more power when driver is unloaded. 1012 */ 1013 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 1014 MII_BMCR, BMCR_ISO | BMCR_PDOWN); 1015 break; 1016 default: 1017 /* Force PHY down. */ 1018 CSR_WRITE_2(sc, ALC_GPHY_CFG, GPHY_CFG_EXT_RESET | 1019 GPHY_CFG_SEL_ANA_RESET | GPHY_CFG_PHY_IDDQ | 1020 GPHY_CFG_PWDOWN_HW); 1021 DELAY(1000); 1022 break; 1023 } 1024 } 1025 1026 static void 1027 alc_aspm(struct alc_softc *sc, int init, int media) 1028 { 1029 1030 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 1031 alc_aspm_816x(sc, init); 1032 else 1033 alc_aspm_813x(sc, media); 1034 } 1035 1036 static void 1037 alc_aspm_813x(struct alc_softc *sc, int media) 1038 { 1039 uint32_t pmcfg; 1040 uint16_t linkcfg; 1041 1042 pmcfg = CSR_READ_4(sc, ALC_PM_CFG); 1043 if ((sc->alc_flags & (ALC_FLAG_APS | ALC_FLAG_PCIE)) == 1044 (ALC_FLAG_APS | ALC_FLAG_PCIE)) 1045 linkcfg = CSR_READ_2(sc, sc->alc_expcap + 1046 PCIE_LCSR); 1047 else 1048 linkcfg = 0; 1049 pmcfg &= ~PM_CFG_SERDES_PD_EX_L1; 1050 pmcfg &= ~(PM_CFG_L1_ENTRY_TIMER_MASK | PM_CFG_LCKDET_TIMER_MASK); 1051 pmcfg |= PM_CFG_MAC_ASPM_CHK; 1052 pmcfg |= (PM_CFG_LCKDET_TIMER_DEFAULT << PM_CFG_LCKDET_TIMER_SHIFT); 1053 pmcfg &= ~(PM_CFG_ASPM_L1_ENB | PM_CFG_ASPM_L0S_ENB); 1054 1055 if ((sc->alc_flags & ALC_FLAG_APS) != 0) { 1056 /* Disable extended sync except AR8152 B v1.0 */ 1057 linkcfg &= ~0x80; 1058 if (sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8152_B && 1059 sc->alc_rev == ATHEROS_AR8152_B_V10) 1060 linkcfg |= 0x80; 1061 CSR_WRITE_2(sc, sc->alc_expcap + PCIE_LCSR, 1062 linkcfg); 1063 pmcfg &= ~(PM_CFG_EN_BUFS_RX_L0S | PM_CFG_SA_DLY_ENB | 1064 PM_CFG_HOTRST); 1065 pmcfg |= (PM_CFG_L1_ENTRY_TIMER_DEFAULT << 1066 PM_CFG_L1_ENTRY_TIMER_SHIFT); 1067 pmcfg &= ~PM_CFG_PM_REQ_TIMER_MASK; 1068 pmcfg |= (PM_CFG_PM_REQ_TIMER_DEFAULT << 1069 PM_CFG_PM_REQ_TIMER_SHIFT); 1070 pmcfg |= PM_CFG_SERDES_PD_EX_L1 | PM_CFG_PCIE_RECV; 1071 } 1072 1073 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) { 1074 if ((sc->alc_flags & ALC_FLAG_L0S) != 0) 1075 pmcfg |= PM_CFG_ASPM_L0S_ENB; 1076 if ((sc->alc_flags & ALC_FLAG_L1S) != 0) 1077 pmcfg |= PM_CFG_ASPM_L1_ENB; 1078 if ((sc->alc_flags & ALC_FLAG_APS) != 0) { 1079 if (sc->alc_ident->deviceid == 1080 PCI_PRODUCT_ATTANSIC_AR8152_B) 1081 pmcfg &= ~PM_CFG_ASPM_L0S_ENB; 1082 pmcfg &= ~(PM_CFG_SERDES_L1_ENB | 1083 PM_CFG_SERDES_PLL_L1_ENB | 1084 PM_CFG_SERDES_BUDS_RX_L1_ENB); 1085 pmcfg |= PM_CFG_CLK_SWH_L1; 1086 if (media == IFM_100_TX || media == IFM_1000_T) { 1087 pmcfg &= ~PM_CFG_L1_ENTRY_TIMER_MASK; 1088 switch (sc->alc_ident->deviceid) { 1089 case PCI_PRODUCT_ATTANSIC_AR8152_B: 1090 pmcfg |= (7 << 1091 PM_CFG_L1_ENTRY_TIMER_SHIFT); 1092 break; 1093 case PCI_PRODUCT_ATTANSIC_AR8152_B2: 1094 case PCI_PRODUCT_ATTANSIC_AR8151_V2: 1095 pmcfg |= (4 << 1096 PM_CFG_L1_ENTRY_TIMER_SHIFT); 1097 break; 1098 default: 1099 pmcfg |= (15 << 1100 PM_CFG_L1_ENTRY_TIMER_SHIFT); 1101 break; 1102 } 1103 } 1104 } else { 1105 pmcfg |= PM_CFG_SERDES_L1_ENB | 1106 PM_CFG_SERDES_PLL_L1_ENB | 1107 PM_CFG_SERDES_BUDS_RX_L1_ENB; 1108 pmcfg &= ~(PM_CFG_CLK_SWH_L1 | 1109 PM_CFG_ASPM_L1_ENB | PM_CFG_ASPM_L0S_ENB); 1110 } 1111 } else { 1112 pmcfg &= ~(PM_CFG_SERDES_BUDS_RX_L1_ENB | PM_CFG_SERDES_L1_ENB | 1113 PM_CFG_SERDES_PLL_L1_ENB); 1114 pmcfg |= PM_CFG_CLK_SWH_L1; 1115 if ((sc->alc_flags & ALC_FLAG_L1S) != 0) 1116 pmcfg |= PM_CFG_ASPM_L1_ENB; 1117 } 1118 CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg); 1119 } 1120 1121 static void 1122 alc_aspm_816x(struct alc_softc *sc, int init) 1123 { 1124 uint32_t pmcfg; 1125 1126 pmcfg = CSR_READ_4(sc, ALC_PM_CFG); 1127 pmcfg &= ~PM_CFG_L1_ENTRY_TIMER_816X_MASK; 1128 pmcfg |= PM_CFG_L1_ENTRY_TIMER_816X_DEFAULT; 1129 pmcfg &= ~PM_CFG_PM_REQ_TIMER_MASK; 1130 pmcfg |= PM_CFG_PM_REQ_TIMER_816X_DEFAULT; 1131 pmcfg &= ~PM_CFG_LCKDET_TIMER_MASK; 1132 pmcfg |= PM_CFG_LCKDET_TIMER_DEFAULT; 1133 pmcfg |= PM_CFG_SERDES_PD_EX_L1 | PM_CFG_CLK_SWH_L1 | PM_CFG_PCIE_RECV; 1134 pmcfg &= ~(PM_CFG_RX_L1_AFTER_L0S | PM_CFG_TX_L1_AFTER_L0S | 1135 PM_CFG_ASPM_L1_ENB | PM_CFG_ASPM_L0S_ENB | 1136 PM_CFG_SERDES_L1_ENB | PM_CFG_SERDES_PLL_L1_ENB | 1137 PM_CFG_SERDES_BUDS_RX_L1_ENB | PM_CFG_SA_DLY_ENB | 1138 PM_CFG_MAC_ASPM_CHK | PM_CFG_HOTRST); 1139 if (AR816X_REV(sc->alc_rev) <= AR816X_REV_A1 && 1140 (sc->alc_rev & 0x01) != 0) 1141 pmcfg |= PM_CFG_SERDES_L1_ENB | PM_CFG_SERDES_PLL_L1_ENB; 1142 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) { 1143 /* Link up, enable both L0s, L1s. */ 1144 pmcfg |= PM_CFG_ASPM_L0S_ENB | PM_CFG_ASPM_L1_ENB | 1145 PM_CFG_MAC_ASPM_CHK; 1146 } else { 1147 if (init != 0) 1148 pmcfg |= PM_CFG_ASPM_L0S_ENB | PM_CFG_ASPM_L1_ENB | 1149 PM_CFG_MAC_ASPM_CHK; 1150 else if ((sc->sc_ec.ec_if.if_flags & IFF_RUNNING) != 0) 1151 pmcfg |= PM_CFG_ASPM_L1_ENB | PM_CFG_MAC_ASPM_CHK; 1152 } 1153 CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg); 1154 } 1155 1156 static void 1157 alc_attach(device_t parent, device_t self, void *aux) 1158 { 1159 1160 struct alc_softc *sc = device_private(self); 1161 struct pci_attach_args *pa = aux; 1162 pci_chipset_tag_t pc = pa->pa_pc; 1163 pci_intr_handle_t ih; 1164 const char *intrstr; 1165 struct ifnet *ifp; 1166 pcireg_t memtype; 1167 const char *aspm_state[] = { "L0s/L1", "L0s", "L1", "L0s/L1" }; 1168 uint16_t burst; 1169 int base, mii_flags, state, error = 0; 1170 uint32_t cap, ctl, val; 1171 char intrbuf[PCI_INTRSTR_LEN]; 1172 1173 sc->alc_ident = alc_find_ident(pa); 1174 1175 aprint_naive("\n"); 1176 aprint_normal(": %s\n", sc->alc_ident->name); 1177 1178 sc->sc_dev = self; 1179 sc->sc_dmat = pa->pa_dmat; 1180 sc->sc_pct = pa->pa_pc; 1181 sc->sc_pcitag = pa->pa_tag; 1182 1183 /* 1184 * Allocate IO memory 1185 */ 1186 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, ALC_PCIR_BAR); 1187 switch (memtype) { 1188 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 1189 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT_1M: 1190 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 1191 break; 1192 default: 1193 aprint_error_dev(self, "invalid base address register\n"); 1194 break; 1195 } 1196 1197 if (pci_mapreg_map(pa, ALC_PCIR_BAR, memtype, 0, &sc->sc_mem_bt, 1198 &sc->sc_mem_bh, NULL, &sc->sc_mem_size)) { 1199 aprint_error_dev(self, "could not map mem space\n"); 1200 return; 1201 } 1202 1203 if (pci_intr_map(pa, &ih) != 0) { 1204 printf(": can't map interrupt\n"); 1205 goto fail; 1206 } 1207 1208 /* 1209 * Allocate IRQ 1210 */ 1211 intrstr = pci_intr_string(sc->sc_pct, ih, intrbuf, sizeof(intrbuf)); 1212 sc->sc_irq_handle = pci_intr_establish(pc, ih, IPL_NET, alc_intr, sc); 1213 if (sc->sc_irq_handle == NULL) { 1214 printf(": could not establish interrupt"); 1215 if (intrstr != NULL) 1216 printf(" at %s", intrstr); 1217 printf("\n"); 1218 goto fail; 1219 } 1220 aprint_normal_dev(self, "interrupting at %s\n", intrstr); 1221 1222 /* Set PHY address. */ 1223 sc->alc_phyaddr = ALC_PHY_ADDR; 1224 1225 /* Initialize DMA parameters. */ 1226 sc->alc_dma_rd_burst = 0; 1227 sc->alc_dma_wr_burst = 0; 1228 sc->alc_rcb = DMA_CFG_RCB_64; 1229 if (pci_get_capability(pc, pa->pa_tag, PCI_CAP_PCIEXPRESS, 1230 &base, NULL)) { 1231 sc->alc_flags |= ALC_FLAG_PCIE; 1232 sc->alc_expcap = base; 1233 burst = pci_conf_read(sc->sc_pct, sc->sc_pcitag, 1234 base + PCIE_DCSR) >> 16; 1235 sc->alc_dma_rd_burst = (burst & 0x7000) >> 12; 1236 sc->alc_dma_wr_burst = (burst & 0x00e0) >> 5; 1237 if (alcdebug) { 1238 printf("%s: Read request size : %u bytes.\n", 1239 device_xname(sc->sc_dev), 1240 alc_dma_burst[sc->alc_dma_rd_burst]); 1241 printf("%s: TLP payload size : %u bytes.\n", 1242 device_xname(sc->sc_dev), 1243 alc_dma_burst[sc->alc_dma_wr_burst]); 1244 } 1245 if (alc_dma_burst[sc->alc_dma_rd_burst] > 1024) 1246 sc->alc_dma_rd_burst = 3; 1247 if (alc_dma_burst[sc->alc_dma_wr_burst] > 1024) 1248 sc->alc_dma_wr_burst = 3; 1249 1250 /* Clear data link and flow-control protocol error. */ 1251 val = CSR_READ_4(sc, ALC_PEX_UNC_ERR_SEV); 1252 val &= ~(PEX_UNC_ERR_SEV_DLP | PEX_UNC_ERR_SEV_FCP); 1253 CSR_WRITE_4(sc, ALC_PEX_UNC_ERR_SEV, val); 1254 1255 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 1256 CSR_WRITE_4(sc, ALC_LTSSM_ID_CFG, 1257 CSR_READ_4(sc, ALC_LTSSM_ID_CFG) & ~LTSSM_ID_WRO_ENB); 1258 CSR_WRITE_4(sc, ALC_PCIE_PHYMISC, 1259 CSR_READ_4(sc, ALC_PCIE_PHYMISC) | 1260 PCIE_PHYMISC_FORCE_RCV_DET); 1261 if (sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8152_B && 1262 sc->alc_rev == ATHEROS_AR8152_B_V10) { 1263 val = CSR_READ_4(sc, ALC_PCIE_PHYMISC2); 1264 val &= ~(PCIE_PHYMISC2_SERDES_CDR_MASK | 1265 PCIE_PHYMISC2_SERDES_TH_MASK); 1266 val |= 3 << PCIE_PHYMISC2_SERDES_CDR_SHIFT; 1267 val |= 3 << PCIE_PHYMISC2_SERDES_TH_SHIFT; 1268 CSR_WRITE_4(sc, ALC_PCIE_PHYMISC2, val); 1269 } 1270 /* Disable ASPM L0S and L1. */ 1271 cap = pci_conf_read(sc->sc_pct, sc->sc_pcitag, 1272 base + PCIE_LCAP) >> 16; 1273 if ((cap & 0x00000c00) != 0) { 1274 ctl = pci_conf_read(sc->sc_pct, sc->sc_pcitag, 1275 base + PCIE_LCSR) >> 16; 1276 if ((ctl & 0x08) != 0) 1277 sc->alc_rcb = DMA_CFG_RCB_128; 1278 if (alcdebug) 1279 printf("%s: RCB %u bytes\n", 1280 device_xname(sc->sc_dev), 1281 sc->alc_rcb == DMA_CFG_RCB_64 ? 64 : 128); 1282 state = ctl & 0x03; 1283 if (state & 0x01) 1284 sc->alc_flags |= ALC_FLAG_L0S; 1285 if (state & 0x02) 1286 sc->alc_flags |= ALC_FLAG_L1S; 1287 if (alcdebug) 1288 printf("%s: ASPM %s %s\n", 1289 device_xname(sc->sc_dev), 1290 aspm_state[state], 1291 state == 0 ? "disabled" : "enabled"); 1292 alc_disable_l0s_l1(sc); 1293 } else { 1294 aprint_debug_dev(sc->sc_dev, "no ASPM support\n"); 1295 } 1296 } else { 1297 val = CSR_READ_4(sc, ALC_PDLL_TRNS1); 1298 val &= ~PDLL_TRNS1_D3PLLOFF_ENB; 1299 CSR_WRITE_4(sc, ALC_PDLL_TRNS1, val); 1300 val = CSR_READ_4(sc, ALC_MASTER_CFG); 1301 if (AR816X_REV(sc->alc_rev) <= AR816X_REV_A1 && 1302 (sc->alc_rev & 0x01) != 0) { 1303 if ((val & MASTER_WAKEN_25M) == 0 || 1304 (val & MASTER_CLK_SEL_DIS) == 0) { 1305 val |= MASTER_WAKEN_25M | MASTER_CLK_SEL_DIS; 1306 CSR_WRITE_4(sc, ALC_MASTER_CFG, val); 1307 } 1308 } else { 1309 if ((val & MASTER_WAKEN_25M) == 0 || 1310 (val & MASTER_CLK_SEL_DIS) != 0) { 1311 val |= MASTER_WAKEN_25M; 1312 val &= ~MASTER_CLK_SEL_DIS; 1313 CSR_WRITE_4(sc, ALC_MASTER_CFG, val); 1314 } 1315 } 1316 } 1317 alc_aspm(sc, 1, IFM_UNKNOWN); 1318 } 1319 1320 /* Reset PHY. */ 1321 alc_phy_reset(sc); 1322 1323 /* Reset the ethernet controller. */ 1324 alc_stop_mac(sc); 1325 alc_reset(sc); 1326 1327 /* 1328 * One odd thing is AR8132 uses the same PHY hardware(F1 1329 * gigabit PHY) of AR8131. So atphy(4) of AR8132 reports 1330 * the PHY supports 1000Mbps but that's not true. The PHY 1331 * used in AR8132 can't establish gigabit link even if it 1332 * shows the same PHY model/revision number of AR8131. 1333 */ 1334 switch (sc->alc_ident->deviceid) { 1335 case PCI_PRODUCT_ATTANSIC_AR8161: 1336 if (PCI_SUBSYS_ID(pci_conf_read( 1337 sc->sc_pct, sc->sc_pcitag, PCI_SUBSYS_ID_REG)) == 0x0091 && 1338 sc->alc_rev == 0) 1339 sc->alc_flags |= ALC_FLAG_LINK_WAR; 1340 /* FALLTHROUGH */ 1341 case PCI_PRODUCT_ATTANSIC_E2200: 1342 case PCI_PRODUCT_ATTANSIC_AR8171: 1343 sc->alc_flags |= ALC_FLAG_AR816X_FAMILY; 1344 break; 1345 case PCI_PRODUCT_ATTANSIC_AR8162: 1346 case PCI_PRODUCT_ATTANSIC_AR8172: 1347 sc->alc_flags |= ALC_FLAG_FASTETHER | ALC_FLAG_AR816X_FAMILY; 1348 break; 1349 case PCI_PRODUCT_ATTANSIC_AR8152_B: 1350 case PCI_PRODUCT_ATTANSIC_AR8152_B2: 1351 sc->alc_flags |= ALC_FLAG_APS; 1352 /* FALLTHROUGH */ 1353 case PCI_PRODUCT_ATTANSIC_AR8132: 1354 sc->alc_flags |= ALC_FLAG_FASTETHER; 1355 break; 1356 case PCI_PRODUCT_ATTANSIC_AR8151: 1357 case PCI_PRODUCT_ATTANSIC_AR8151_V2: 1358 sc->alc_flags |= ALC_FLAG_APS; 1359 /* FALLTHROUGH */ 1360 default: 1361 break; 1362 } 1363 sc->alc_flags |= ALC_FLAG_JUMBO; 1364 1365 /* 1366 * It seems that AR813x/AR815x has silicon bug for SMB. In 1367 * addition, Atheros said that enabling SMB wouldn't improve 1368 * performance. However I think it's bad to access lots of 1369 * registers to extract MAC statistics. 1370 */ 1371 sc->alc_flags |= ALC_FLAG_SMB_BUG; 1372 /* 1373 * Don't use Tx CMB. It is known to have silicon bug. 1374 */ 1375 sc->alc_flags |= ALC_FLAG_CMB_BUG; 1376 sc->alc_rev = PCI_REVISION(pa->pa_class); 1377 sc->alc_chip_rev = CSR_READ_4(sc, ALC_MASTER_CFG) >> 1378 MASTER_CHIP_REV_SHIFT; 1379 if (alcdebug) { 1380 printf("%s: PCI device revision : 0x%04x\n", 1381 device_xname(sc->sc_dev), sc->alc_rev); 1382 printf("%s: Chip id/revision : 0x%04x\n", 1383 device_xname(sc->sc_dev), sc->alc_chip_rev); 1384 printf("%s: %u Tx FIFO, %u Rx FIFO\n", device_xname(sc->sc_dev), 1385 CSR_READ_4(sc, ALC_SRAM_TX_FIFO_LEN) * 8, 1386 CSR_READ_4(sc, ALC_SRAM_RX_FIFO_LEN) * 8); 1387 } 1388 1389 error = alc_dma_alloc(sc); 1390 if (error) 1391 goto fail; 1392 1393 callout_init(&sc->sc_tick_ch, 0); 1394 callout_setfunc(&sc->sc_tick_ch, alc_tick, sc); 1395 1396 /* Load station address. */ 1397 alc_get_macaddr(sc); 1398 1399 aprint_normal_dev(self, "Ethernet address %s\n", 1400 ether_sprintf(sc->alc_eaddr)); 1401 1402 ifp = &sc->sc_ec.ec_if; 1403 ifp->if_softc = sc; 1404 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1405 ifp->if_init = alc_init; 1406 ifp->if_ioctl = alc_ioctl; 1407 ifp->if_start = alc_start; 1408 ifp->if_stop = alc_stop; 1409 ifp->if_watchdog = alc_watchdog; 1410 ifp->if_baudrate = IF_Gbps(1); 1411 IFQ_SET_MAXLEN(&ifp->if_snd, ALC_TX_RING_CNT - 1); 1412 IFQ_SET_READY(&ifp->if_snd); 1413 strlcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 1414 1415 sc->sc_ec.ec_capabilities = ETHERCAP_VLAN_MTU; 1416 1417 #ifdef ALC_CHECKSUM 1418 ifp->if_capabilities |= IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 1419 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 1420 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_TCPv4_Rx; 1421 #endif 1422 1423 #if NVLAN > 0 1424 sc->sc_ec.ec_capabilities |= ETHERCAP_VLAN_HWTAGGING; 1425 #endif 1426 1427 /* 1428 * XXX 1429 * It seems enabling Tx checksum offloading makes more trouble. 1430 * Sometimes the controller does not receive any frames when 1431 * Tx checksum offloading is enabled. I'm not sure whether this 1432 * is a bug in Tx checksum offloading logic or I got broken 1433 * sample boards. To safety, don't enable Tx checksum offloading 1434 * by default but give chance to users to toggle it if they know 1435 * their controllers work without problems. 1436 * Fortunately, Tx checksum offloading for AR816x family 1437 * seems to work. 1438 */ 1439 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 1440 ifp->if_capenable &= ~IFCAP_CSUM_IPv4_Tx; 1441 ifp->if_capabilities &= ~ALC_CSUM_FEATURES; 1442 } 1443 1444 /* Set up MII bus. */ 1445 sc->sc_miibus.mii_ifp = ifp; 1446 sc->sc_miibus.mii_readreg = alc_miibus_readreg; 1447 sc->sc_miibus.mii_writereg = alc_miibus_writereg; 1448 sc->sc_miibus.mii_statchg = alc_miibus_statchg; 1449 1450 sc->sc_ec.ec_mii = &sc->sc_miibus; 1451 ifmedia_init(&sc->sc_miibus.mii_media, 0, alc_mediachange, 1452 alc_mediastatus); 1453 mii_flags = 0; 1454 if ((sc->alc_flags & ALC_FLAG_JUMBO) != 0) 1455 mii_flags |= MIIF_DOPAUSE; 1456 mii_attach(self, &sc->sc_miibus, 0xffffffff, MII_PHY_ANY, 1457 MII_OFFSET_ANY, mii_flags); 1458 1459 if (LIST_FIRST(&sc->sc_miibus.mii_phys) == NULL) { 1460 printf("%s: no PHY found!\n", device_xname(sc->sc_dev)); 1461 ifmedia_add(&sc->sc_miibus.mii_media, IFM_ETHER | IFM_MANUAL, 1462 0, NULL); 1463 ifmedia_set(&sc->sc_miibus.mii_media, IFM_ETHER | IFM_MANUAL); 1464 } else 1465 ifmedia_set(&sc->sc_miibus.mii_media, IFM_ETHER | IFM_AUTO); 1466 1467 if_attach(ifp); 1468 ether_ifattach(ifp, sc->alc_eaddr); 1469 1470 if (!pmf_device_register(self, NULL, NULL)) 1471 aprint_error_dev(self, "couldn't establish power handler\n"); 1472 else 1473 pmf_class_network_register(self, ifp); 1474 1475 return; 1476 fail: 1477 alc_dma_free(sc); 1478 if (sc->sc_irq_handle != NULL) { 1479 pci_intr_disestablish(sc->sc_pct, sc->sc_irq_handle); 1480 sc->sc_irq_handle = NULL; 1481 } 1482 if (sc->sc_mem_size) { 1483 bus_space_unmap(sc->sc_mem_bt, sc->sc_mem_bh, sc->sc_mem_size); 1484 sc->sc_mem_size = 0; 1485 } 1486 } 1487 1488 static int 1489 alc_detach(device_t self, int flags) 1490 { 1491 struct alc_softc *sc = device_private(self); 1492 struct ifnet *ifp = &sc->sc_ec.ec_if; 1493 int s; 1494 1495 s = splnet(); 1496 alc_stop(ifp, 0); 1497 splx(s); 1498 1499 mii_detach(&sc->sc_miibus, MII_PHY_ANY, MII_OFFSET_ANY); 1500 1501 /* Delete all remaining media. */ 1502 ifmedia_delete_instance(&sc->sc_miibus.mii_media, IFM_INST_ANY); 1503 1504 ether_ifdetach(ifp); 1505 if_detach(ifp); 1506 alc_dma_free(sc); 1507 1508 alc_phy_down(sc); 1509 if (sc->sc_irq_handle != NULL) { 1510 pci_intr_disestablish(sc->sc_pct, sc->sc_irq_handle); 1511 sc->sc_irq_handle = NULL; 1512 } 1513 if (sc->sc_mem_size) { 1514 bus_space_unmap(sc->sc_mem_bt, sc->sc_mem_bh, sc->sc_mem_size); 1515 sc->sc_mem_size = 0; 1516 } 1517 1518 return (0); 1519 } 1520 1521 static int 1522 alc_dma_alloc(struct alc_softc *sc) 1523 { 1524 struct alc_txdesc *txd; 1525 struct alc_rxdesc *rxd; 1526 int nsegs, error, i; 1527 1528 /* 1529 * Create DMA stuffs for TX ring 1530 */ 1531 error = bus_dmamap_create(sc->sc_dmat, ALC_TX_RING_SZ, 1, 1532 ALC_TX_RING_SZ, 0, BUS_DMA_NOWAIT, &sc->alc_cdata.alc_tx_ring_map); 1533 if (error) { 1534 sc->alc_cdata.alc_tx_ring_map = NULL; 1535 return (ENOBUFS); 1536 } 1537 1538 /* Allocate DMA'able memory for TX ring */ 1539 error = bus_dmamem_alloc(sc->sc_dmat, ALC_TX_RING_SZ, 1540 ETHER_ALIGN, 0, &sc->alc_rdata.alc_tx_ring_seg, 1, 1541 &nsegs, BUS_DMA_NOWAIT); 1542 if (error) { 1543 printf("%s: could not allocate DMA'able memory for Tx ring.\n", 1544 device_xname(sc->sc_dev)); 1545 return error; 1546 } 1547 1548 error = bus_dmamem_map(sc->sc_dmat, &sc->alc_rdata.alc_tx_ring_seg, 1549 nsegs, ALC_TX_RING_SZ, (void **)&sc->alc_rdata.alc_tx_ring, 1550 BUS_DMA_NOWAIT); 1551 if (error) 1552 return (ENOBUFS); 1553 1554 /* Load the DMA map for Tx ring. */ 1555 error = bus_dmamap_load(sc->sc_dmat, sc->alc_cdata.alc_tx_ring_map, 1556 sc->alc_rdata.alc_tx_ring, ALC_TX_RING_SZ, NULL, BUS_DMA_WAITOK); 1557 if (error) { 1558 printf("%s: could not load DMA'able memory for Tx ring.\n", 1559 device_xname(sc->sc_dev)); 1560 bus_dmamem_free(sc->sc_dmat, 1561 &sc->alc_rdata.alc_tx_ring_seg, 1); 1562 return error; 1563 } 1564 1565 sc->alc_rdata.alc_tx_ring_paddr = 1566 sc->alc_cdata.alc_tx_ring_map->dm_segs[0].ds_addr; 1567 1568 /* 1569 * Create DMA stuffs for RX ring 1570 */ 1571 error = bus_dmamap_create(sc->sc_dmat, ALC_RX_RING_SZ, 1, 1572 ALC_RX_RING_SZ, 0, BUS_DMA_NOWAIT, &sc->alc_cdata.alc_rx_ring_map); 1573 if (error) 1574 return (ENOBUFS); 1575 1576 /* Allocate DMA'able memory for RX ring */ 1577 error = bus_dmamem_alloc(sc->sc_dmat, ALC_RX_RING_SZ, 1578 ETHER_ALIGN, 0, &sc->alc_rdata.alc_rx_ring_seg, 1, 1579 &nsegs, BUS_DMA_NOWAIT); 1580 if (error) { 1581 printf("%s: could not allocate DMA'able memory for Rx ring.\n", 1582 device_xname(sc->sc_dev)); 1583 return error; 1584 } 1585 1586 error = bus_dmamem_map(sc->sc_dmat, &sc->alc_rdata.alc_rx_ring_seg, 1587 nsegs, ALC_RX_RING_SZ, (void **)&sc->alc_rdata.alc_rx_ring, 1588 BUS_DMA_NOWAIT); 1589 if (error) 1590 return (ENOBUFS); 1591 1592 /* Load the DMA map for Rx ring. */ 1593 error = bus_dmamap_load(sc->sc_dmat, sc->alc_cdata.alc_rx_ring_map, 1594 sc->alc_rdata.alc_rx_ring, ALC_RX_RING_SZ, NULL, BUS_DMA_WAITOK); 1595 if (error) { 1596 printf("%s: could not load DMA'able memory for Rx ring.\n", 1597 device_xname(sc->sc_dev)); 1598 bus_dmamem_free(sc->sc_dmat, 1599 &sc->alc_rdata.alc_rx_ring_seg, 1); 1600 return error; 1601 } 1602 1603 sc->alc_rdata.alc_rx_ring_paddr = 1604 sc->alc_cdata.alc_rx_ring_map->dm_segs[0].ds_addr; 1605 1606 /* 1607 * Create DMA stuffs for RX return ring 1608 */ 1609 error = bus_dmamap_create(sc->sc_dmat, ALC_RR_RING_SZ, 1, 1610 ALC_RR_RING_SZ, 0, BUS_DMA_NOWAIT, &sc->alc_cdata.alc_rr_ring_map); 1611 if (error) 1612 return (ENOBUFS); 1613 1614 /* Allocate DMA'able memory for RX return ring */ 1615 error = bus_dmamem_alloc(sc->sc_dmat, ALC_RR_RING_SZ, 1616 ETHER_ALIGN, 0, &sc->alc_rdata.alc_rr_ring_seg, 1, 1617 &nsegs, BUS_DMA_NOWAIT); 1618 if (error) { 1619 printf("%s: could not allocate DMA'able memory for Rx " 1620 "return ring.\n", device_xname(sc->sc_dev)); 1621 return error; 1622 } 1623 1624 error = bus_dmamem_map(sc->sc_dmat, &sc->alc_rdata.alc_rr_ring_seg, 1625 nsegs, ALC_RR_RING_SZ, (void **)&sc->alc_rdata.alc_rr_ring, 1626 BUS_DMA_NOWAIT); 1627 if (error) 1628 return (ENOBUFS); 1629 1630 /* Load the DMA map for Rx return ring. */ 1631 error = bus_dmamap_load(sc->sc_dmat, sc->alc_cdata.alc_rr_ring_map, 1632 sc->alc_rdata.alc_rr_ring, ALC_RR_RING_SZ, NULL, BUS_DMA_WAITOK); 1633 if (error) { 1634 printf("%s: could not load DMA'able memory for Rx return ring." 1635 "\n", device_xname(sc->sc_dev)); 1636 bus_dmamem_free(sc->sc_dmat, 1637 &sc->alc_rdata.alc_rr_ring_seg, 1); 1638 return error; 1639 } 1640 1641 sc->alc_rdata.alc_rr_ring_paddr = 1642 sc->alc_cdata.alc_rr_ring_map->dm_segs[0].ds_addr; 1643 1644 /* 1645 * Create DMA stuffs for CMB block 1646 */ 1647 error = bus_dmamap_create(sc->sc_dmat, ALC_CMB_SZ, 1, 1648 ALC_CMB_SZ, 0, BUS_DMA_NOWAIT, 1649 &sc->alc_cdata.alc_cmb_map); 1650 if (error) 1651 return (ENOBUFS); 1652 1653 /* Allocate DMA'able memory for CMB block */ 1654 error = bus_dmamem_alloc(sc->sc_dmat, ALC_CMB_SZ, 1655 ETHER_ALIGN, 0, &sc->alc_rdata.alc_cmb_seg, 1, 1656 &nsegs, BUS_DMA_NOWAIT); 1657 if (error) { 1658 printf("%s: could not allocate DMA'able memory for " 1659 "CMB block\n", device_xname(sc->sc_dev)); 1660 return error; 1661 } 1662 1663 error = bus_dmamem_map(sc->sc_dmat, &sc->alc_rdata.alc_cmb_seg, 1664 nsegs, ALC_CMB_SZ, (void **)&sc->alc_rdata.alc_cmb, 1665 BUS_DMA_NOWAIT); 1666 if (error) 1667 return (ENOBUFS); 1668 1669 /* Load the DMA map for CMB block. */ 1670 error = bus_dmamap_load(sc->sc_dmat, sc->alc_cdata.alc_cmb_map, 1671 sc->alc_rdata.alc_cmb, ALC_CMB_SZ, NULL, 1672 BUS_DMA_WAITOK); 1673 if (error) { 1674 printf("%s: could not load DMA'able memory for CMB block\n", 1675 device_xname(sc->sc_dev)); 1676 bus_dmamem_free(sc->sc_dmat, 1677 &sc->alc_rdata.alc_cmb_seg, 1); 1678 return error; 1679 } 1680 1681 sc->alc_rdata.alc_cmb_paddr = 1682 sc->alc_cdata.alc_cmb_map->dm_segs[0].ds_addr; 1683 1684 /* 1685 * Create DMA stuffs for SMB block 1686 */ 1687 error = bus_dmamap_create(sc->sc_dmat, ALC_SMB_SZ, 1, 1688 ALC_SMB_SZ, 0, BUS_DMA_NOWAIT, 1689 &sc->alc_cdata.alc_smb_map); 1690 if (error) 1691 return (ENOBUFS); 1692 1693 /* Allocate DMA'able memory for SMB block */ 1694 error = bus_dmamem_alloc(sc->sc_dmat, ALC_SMB_SZ, 1695 ETHER_ALIGN, 0, &sc->alc_rdata.alc_smb_seg, 1, 1696 &nsegs, BUS_DMA_NOWAIT); 1697 if (error) { 1698 printf("%s: could not allocate DMA'able memory for " 1699 "SMB block\n", device_xname(sc->sc_dev)); 1700 return error; 1701 } 1702 1703 error = bus_dmamem_map(sc->sc_dmat, &sc->alc_rdata.alc_smb_seg, 1704 nsegs, ALC_SMB_SZ, (void **)&sc->alc_rdata.alc_smb, 1705 BUS_DMA_NOWAIT); 1706 if (error) 1707 return (ENOBUFS); 1708 1709 /* Load the DMA map for SMB block */ 1710 error = bus_dmamap_load(sc->sc_dmat, sc->alc_cdata.alc_smb_map, 1711 sc->alc_rdata.alc_smb, ALC_SMB_SZ, NULL, 1712 BUS_DMA_WAITOK); 1713 if (error) { 1714 printf("%s: could not load DMA'able memory for SMB block\n", 1715 device_xname(sc->sc_dev)); 1716 bus_dmamem_free(sc->sc_dmat, 1717 &sc->alc_rdata.alc_smb_seg, 1); 1718 return error; 1719 } 1720 1721 sc->alc_rdata.alc_smb_paddr = 1722 sc->alc_cdata.alc_smb_map->dm_segs[0].ds_addr; 1723 1724 1725 /* Create DMA maps for Tx buffers. */ 1726 for (i = 0; i < ALC_TX_RING_CNT; i++) { 1727 txd = &sc->alc_cdata.alc_txdesc[i]; 1728 txd->tx_m = NULL; 1729 txd->tx_dmamap = NULL; 1730 error = bus_dmamap_create(sc->sc_dmat, ALC_TSO_MAXSIZE, 1731 ALC_MAXTXSEGS, ALC_TSO_MAXSEGSIZE, 0, BUS_DMA_NOWAIT, 1732 &txd->tx_dmamap); 1733 if (error) { 1734 printf("%s: could not create Tx dmamap.\n", 1735 device_xname(sc->sc_dev)); 1736 return error; 1737 } 1738 } 1739 1740 /* Create DMA maps for Rx buffers. */ 1741 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES, 0, 1742 BUS_DMA_NOWAIT, &sc->alc_cdata.alc_rx_sparemap); 1743 if (error) { 1744 printf("%s: could not create spare Rx dmamap.\n", 1745 device_xname(sc->sc_dev)); 1746 return error; 1747 } 1748 1749 for (i = 0; i < ALC_RX_RING_CNT; i++) { 1750 rxd = &sc->alc_cdata.alc_rxdesc[i]; 1751 rxd->rx_m = NULL; 1752 rxd->rx_dmamap = NULL; 1753 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 1754 MCLBYTES, 0, BUS_DMA_NOWAIT, &rxd->rx_dmamap); 1755 if (error) { 1756 printf("%s: could not create Rx dmamap.\n", 1757 device_xname(sc->sc_dev)); 1758 return error; 1759 } 1760 } 1761 1762 return (0); 1763 } 1764 1765 1766 static void 1767 alc_dma_free(struct alc_softc *sc) 1768 { 1769 struct alc_txdesc *txd; 1770 struct alc_rxdesc *rxd; 1771 int i; 1772 1773 /* Tx buffers */ 1774 for (i = 0; i < ALC_TX_RING_CNT; i++) { 1775 txd = &sc->alc_cdata.alc_txdesc[i]; 1776 if (txd->tx_dmamap != NULL) { 1777 bus_dmamap_destroy(sc->sc_dmat, txd->tx_dmamap); 1778 txd->tx_dmamap = NULL; 1779 } 1780 } 1781 /* Rx buffers */ 1782 for (i = 0; i < ALC_RX_RING_CNT; i++) { 1783 rxd = &sc->alc_cdata.alc_rxdesc[i]; 1784 if (rxd->rx_dmamap != NULL) { 1785 bus_dmamap_destroy(sc->sc_dmat, rxd->rx_dmamap); 1786 rxd->rx_dmamap = NULL; 1787 } 1788 } 1789 if (sc->alc_cdata.alc_rx_sparemap != NULL) { 1790 bus_dmamap_destroy(sc->sc_dmat, sc->alc_cdata.alc_rx_sparemap); 1791 sc->alc_cdata.alc_rx_sparemap = NULL; 1792 } 1793 1794 /* Tx ring. */ 1795 if (sc->alc_cdata.alc_tx_ring_map != NULL) 1796 bus_dmamap_unload(sc->sc_dmat, sc->alc_cdata.alc_tx_ring_map); 1797 if (sc->alc_cdata.alc_tx_ring_map != NULL && 1798 sc->alc_rdata.alc_tx_ring != NULL) 1799 bus_dmamem_free(sc->sc_dmat, 1800 &sc->alc_rdata.alc_tx_ring_seg, 1); 1801 sc->alc_rdata.alc_tx_ring = NULL; 1802 sc->alc_cdata.alc_tx_ring_map = NULL; 1803 1804 /* Rx ring. */ 1805 if (sc->alc_cdata.alc_rx_ring_map != NULL) 1806 bus_dmamap_unload(sc->sc_dmat, sc->alc_cdata.alc_rx_ring_map); 1807 if (sc->alc_cdata.alc_rx_ring_map != NULL && 1808 sc->alc_rdata.alc_rx_ring != NULL) 1809 bus_dmamem_free(sc->sc_dmat, 1810 &sc->alc_rdata.alc_rx_ring_seg, 1); 1811 sc->alc_rdata.alc_rx_ring = NULL; 1812 sc->alc_cdata.alc_rx_ring_map = NULL; 1813 1814 /* Rx return ring. */ 1815 if (sc->alc_cdata.alc_rr_ring_map != NULL) 1816 bus_dmamap_unload(sc->sc_dmat, sc->alc_cdata.alc_rr_ring_map); 1817 if (sc->alc_cdata.alc_rr_ring_map != NULL && 1818 sc->alc_rdata.alc_rr_ring != NULL) 1819 bus_dmamem_free(sc->sc_dmat, 1820 &sc->alc_rdata.alc_rr_ring_seg, 1); 1821 sc->alc_rdata.alc_rr_ring = NULL; 1822 sc->alc_cdata.alc_rr_ring_map = NULL; 1823 1824 /* CMB block */ 1825 if (sc->alc_cdata.alc_cmb_map != NULL) 1826 bus_dmamap_unload(sc->sc_dmat, sc->alc_cdata.alc_cmb_map); 1827 if (sc->alc_cdata.alc_cmb_map != NULL && 1828 sc->alc_rdata.alc_cmb != NULL) 1829 bus_dmamem_free(sc->sc_dmat, 1830 &sc->alc_rdata.alc_cmb_seg, 1); 1831 sc->alc_rdata.alc_cmb = NULL; 1832 sc->alc_cdata.alc_cmb_map = NULL; 1833 1834 /* SMB block */ 1835 if (sc->alc_cdata.alc_smb_map != NULL) 1836 bus_dmamap_unload(sc->sc_dmat, sc->alc_cdata.alc_smb_map); 1837 if (sc->alc_cdata.alc_smb_map != NULL && 1838 sc->alc_rdata.alc_smb != NULL) 1839 bus_dmamem_free(sc->sc_dmat, 1840 &sc->alc_rdata.alc_smb_seg, 1); 1841 sc->alc_rdata.alc_smb = NULL; 1842 sc->alc_cdata.alc_smb_map = NULL; 1843 } 1844 1845 static int 1846 alc_encap(struct alc_softc *sc, struct mbuf **m_head) 1847 { 1848 struct alc_txdesc *txd, *txd_last; 1849 struct tx_desc *desc; 1850 struct mbuf *m; 1851 bus_dmamap_t map; 1852 uint32_t cflags, poff, vtag; 1853 int error, idx, nsegs, prod; 1854 #if NVLAN > 0 1855 struct m_tag *mtag; 1856 #endif 1857 1858 m = *m_head; 1859 cflags = vtag = 0; 1860 poff = 0; 1861 1862 prod = sc->alc_cdata.alc_tx_prod; 1863 txd = &sc->alc_cdata.alc_txdesc[prod]; 1864 txd_last = txd; 1865 map = txd->tx_dmamap; 1866 1867 error = bus_dmamap_load_mbuf(sc->sc_dmat, map, *m_head, BUS_DMA_NOWAIT); 1868 1869 if (error == EFBIG) { 1870 error = 0; 1871 1872 *m_head = m_pullup(*m_head, MHLEN); 1873 if (*m_head == NULL) { 1874 printf("%s: can't defrag TX mbuf\n", 1875 device_xname(sc->sc_dev)); 1876 return ENOBUFS; 1877 } 1878 1879 error = bus_dmamap_load_mbuf(sc->sc_dmat, map, *m_head, 1880 BUS_DMA_NOWAIT); 1881 1882 if (error != 0) { 1883 printf("%s: could not load defragged TX mbuf\n", 1884 device_xname(sc->sc_dev)); 1885 m_freem(*m_head); 1886 *m_head = NULL; 1887 return error; 1888 } 1889 } else if (error) { 1890 printf("%s: could not load TX mbuf\n", device_xname(sc->sc_dev)); 1891 return (error); 1892 } 1893 1894 nsegs = map->dm_nsegs; 1895 1896 if (nsegs == 0) { 1897 m_freem(*m_head); 1898 *m_head = NULL; 1899 return (EIO); 1900 } 1901 1902 /* Check descriptor overrun. */ 1903 if (sc->alc_cdata.alc_tx_cnt + nsegs >= ALC_TX_RING_CNT - 3) { 1904 bus_dmamap_unload(sc->sc_dmat, map); 1905 return (ENOBUFS); 1906 } 1907 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 1908 BUS_DMASYNC_PREWRITE); 1909 1910 m = *m_head; 1911 desc = NULL; 1912 idx = 0; 1913 #if NVLAN > 0 1914 /* Configure VLAN hardware tag insertion. */ 1915 if ((mtag = VLAN_OUTPUT_TAG(&sc->sc_ec, m))) { 1916 vtag = htons(VLAN_TAG_VALUE(mtag)); 1917 vtag = (vtag << TD_VLAN_SHIFT) & TD_VLAN_MASK; 1918 cflags |= TD_INS_VLAN_TAG; 1919 } 1920 #endif 1921 /* Configure Tx checksum offload. */ 1922 if ((m->m_pkthdr.csum_flags & ALC_CSUM_FEATURES) != 0) { 1923 cflags |= TD_CUSTOM_CSUM; 1924 /* Set checksum start offset. */ 1925 cflags |= ((poff >> 1) << TD_PLOAD_OFFSET_SHIFT) & 1926 TD_PLOAD_OFFSET_MASK; 1927 } 1928 for (; idx < nsegs; idx++) { 1929 desc = &sc->alc_rdata.alc_tx_ring[prod]; 1930 desc->len = 1931 htole32(TX_BYTES(map->dm_segs[idx].ds_len) | vtag); 1932 desc->flags = htole32(cflags); 1933 desc->addr = htole64(map->dm_segs[idx].ds_addr); 1934 sc->alc_cdata.alc_tx_cnt++; 1935 ALC_DESC_INC(prod, ALC_TX_RING_CNT); 1936 } 1937 /* Update producer index. */ 1938 sc->alc_cdata.alc_tx_prod = prod; 1939 1940 /* Finally set EOP on the last descriptor. */ 1941 prod = (prod + ALC_TX_RING_CNT - 1) % ALC_TX_RING_CNT; 1942 desc = &sc->alc_rdata.alc_tx_ring[prod]; 1943 desc->flags |= htole32(TD_EOP); 1944 1945 /* Swap dmamap of the first and the last. */ 1946 txd = &sc->alc_cdata.alc_txdesc[prod]; 1947 map = txd_last->tx_dmamap; 1948 txd_last->tx_dmamap = txd->tx_dmamap; 1949 txd->tx_dmamap = map; 1950 txd->tx_m = m; 1951 1952 return (0); 1953 } 1954 1955 static void 1956 alc_start(struct ifnet *ifp) 1957 { 1958 struct alc_softc *sc = ifp->if_softc; 1959 struct mbuf *m_head; 1960 int enq; 1961 1962 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 1963 return; 1964 1965 /* Reclaim transmitted frames. */ 1966 if (sc->alc_cdata.alc_tx_cnt >= ALC_TX_DESC_HIWAT) 1967 alc_txeof(sc); 1968 1969 enq = 0; 1970 for (;;) { 1971 IFQ_DEQUEUE(&ifp->if_snd, m_head); 1972 if (m_head == NULL) 1973 break; 1974 1975 /* 1976 * Pack the data into the transmit ring. If we 1977 * don't have room, set the OACTIVE flag and wait 1978 * for the NIC to drain the ring. 1979 */ 1980 if (alc_encap(sc, &m_head)) { 1981 if (m_head == NULL) 1982 break; 1983 ifp->if_flags |= IFF_OACTIVE; 1984 break; 1985 } 1986 enq = 1; 1987 1988 /* 1989 * If there's a BPF listener, bounce a copy of this frame 1990 * to him. 1991 */ 1992 bpf_mtap(ifp, m_head); 1993 } 1994 1995 if (enq) { 1996 /* Sync descriptors. */ 1997 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_tx_ring_map, 0, 1998 sc->alc_cdata.alc_tx_ring_map->dm_mapsize, 1999 BUS_DMASYNC_PREWRITE); 2000 /* Kick. Assume we're using normal Tx priority queue. */ 2001 CSR_WRITE_4(sc, ALC_MBOX_TD_PROD_IDX, 2002 (sc->alc_cdata.alc_tx_prod << 2003 MBOX_TD_PROD_LO_IDX_SHIFT) & 2004 MBOX_TD_PROD_LO_IDX_MASK); 2005 /* Set a timeout in case the chip goes out to lunch. */ 2006 ifp->if_timer = ALC_TX_TIMEOUT; 2007 } 2008 } 2009 2010 static void 2011 alc_watchdog(struct ifnet *ifp) 2012 { 2013 struct alc_softc *sc = ifp->if_softc; 2014 2015 if ((sc->alc_flags & ALC_FLAG_LINK) == 0) { 2016 printf("%s: watchdog timeout (missed link)\n", 2017 device_xname(sc->sc_dev)); 2018 ifp->if_oerrors++; 2019 alc_init_backend(ifp, false); 2020 return; 2021 } 2022 2023 printf("%s: watchdog timeout\n", device_xname(sc->sc_dev)); 2024 ifp->if_oerrors++; 2025 alc_init_backend(ifp, false); 2026 2027 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 2028 alc_start(ifp); 2029 } 2030 2031 static int 2032 alc_ioctl(struct ifnet *ifp, u_long cmd, void *data) 2033 { 2034 struct alc_softc *sc = ifp->if_softc; 2035 int s, error = 0; 2036 2037 s = splnet(); 2038 2039 error = ether_ioctl(ifp, cmd, data); 2040 if (error == ENETRESET) { 2041 if (ifp->if_flags & IFF_RUNNING) 2042 alc_iff(sc); 2043 error = 0; 2044 } 2045 2046 splx(s); 2047 return (error); 2048 } 2049 2050 static void 2051 alc_mac_config(struct alc_softc *sc) 2052 { 2053 struct mii_data *mii; 2054 uint32_t reg; 2055 2056 mii = &sc->sc_miibus; 2057 reg = CSR_READ_4(sc, ALC_MAC_CFG); 2058 reg &= ~(MAC_CFG_FULL_DUPLEX | MAC_CFG_TX_FC | MAC_CFG_RX_FC | 2059 MAC_CFG_SPEED_MASK); 2060 if (sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8151 || 2061 sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8151_V2 || 2062 sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8152_B2) 2063 reg |= MAC_CFG_HASH_ALG_CRC32 | MAC_CFG_SPEED_MODE_SW; 2064 /* Reprogram MAC with resolved speed/duplex. */ 2065 switch (IFM_SUBTYPE(mii->mii_media_active)) { 2066 case IFM_10_T: 2067 case IFM_100_TX: 2068 reg |= MAC_CFG_SPEED_10_100; 2069 break; 2070 case IFM_1000_T: 2071 reg |= MAC_CFG_SPEED_1000; 2072 break; 2073 } 2074 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 2075 reg |= MAC_CFG_FULL_DUPLEX; 2076 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0) 2077 reg |= MAC_CFG_TX_FC; 2078 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0) 2079 reg |= MAC_CFG_RX_FC; 2080 } 2081 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 2082 } 2083 2084 static void 2085 alc_stats_clear(struct alc_softc *sc) 2086 { 2087 struct smb sb, *smb; 2088 uint32_t *reg; 2089 int i; 2090 2091 if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0) { 2092 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_smb_map, 0, 2093 sc->alc_cdata.alc_smb_map->dm_mapsize, 2094 BUS_DMASYNC_POSTREAD); 2095 smb = sc->alc_rdata.alc_smb; 2096 /* Update done, clear. */ 2097 smb->updated = 0; 2098 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_smb_map, 0, 2099 sc->alc_cdata.alc_smb_map->dm_mapsize, 2100 BUS_DMASYNC_PREWRITE); 2101 } else { 2102 for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered; 2103 reg++) { 2104 CSR_READ_4(sc, ALC_RX_MIB_BASE + i); 2105 i += sizeof(uint32_t); 2106 } 2107 /* Read Tx statistics. */ 2108 for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes; 2109 reg++) { 2110 CSR_READ_4(sc, ALC_TX_MIB_BASE + i); 2111 i += sizeof(uint32_t); 2112 } 2113 } 2114 } 2115 2116 static void 2117 alc_stats_update(struct alc_softc *sc) 2118 { 2119 struct ifnet *ifp = &sc->sc_ec.ec_if; 2120 struct alc_hw_stats *stat; 2121 struct smb sb, *smb; 2122 uint32_t *reg; 2123 int i; 2124 2125 stat = &sc->alc_stats; 2126 if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0) { 2127 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_smb_map, 0, 2128 sc->alc_cdata.alc_smb_map->dm_mapsize, 2129 BUS_DMASYNC_POSTREAD); 2130 smb = sc->alc_rdata.alc_smb; 2131 if (smb->updated == 0) 2132 return; 2133 } else { 2134 smb = &sb; 2135 /* Read Rx statistics. */ 2136 for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered; 2137 reg++) { 2138 *reg = CSR_READ_4(sc, ALC_RX_MIB_BASE + i); 2139 i += sizeof(uint32_t); 2140 } 2141 /* Read Tx statistics. */ 2142 for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes; 2143 reg++) { 2144 *reg = CSR_READ_4(sc, ALC_TX_MIB_BASE + i); 2145 i += sizeof(uint32_t); 2146 } 2147 } 2148 2149 /* Rx stats. */ 2150 stat->rx_frames += smb->rx_frames; 2151 stat->rx_bcast_frames += smb->rx_bcast_frames; 2152 stat->rx_mcast_frames += smb->rx_mcast_frames; 2153 stat->rx_pause_frames += smb->rx_pause_frames; 2154 stat->rx_control_frames += smb->rx_control_frames; 2155 stat->rx_crcerrs += smb->rx_crcerrs; 2156 stat->rx_lenerrs += smb->rx_lenerrs; 2157 stat->rx_bytes += smb->rx_bytes; 2158 stat->rx_runts += smb->rx_runts; 2159 stat->rx_fragments += smb->rx_fragments; 2160 stat->rx_pkts_64 += smb->rx_pkts_64; 2161 stat->rx_pkts_65_127 += smb->rx_pkts_65_127; 2162 stat->rx_pkts_128_255 += smb->rx_pkts_128_255; 2163 stat->rx_pkts_256_511 += smb->rx_pkts_256_511; 2164 stat->rx_pkts_512_1023 += smb->rx_pkts_512_1023; 2165 stat->rx_pkts_1024_1518 += smb->rx_pkts_1024_1518; 2166 stat->rx_pkts_1519_max += smb->rx_pkts_1519_max; 2167 stat->rx_pkts_truncated += smb->rx_pkts_truncated; 2168 stat->rx_fifo_oflows += smb->rx_fifo_oflows; 2169 stat->rx_rrs_errs += smb->rx_rrs_errs; 2170 stat->rx_alignerrs += smb->rx_alignerrs; 2171 stat->rx_bcast_bytes += smb->rx_bcast_bytes; 2172 stat->rx_mcast_bytes += smb->rx_mcast_bytes; 2173 stat->rx_pkts_filtered += smb->rx_pkts_filtered; 2174 2175 /* Tx stats. */ 2176 stat->tx_frames += smb->tx_frames; 2177 stat->tx_bcast_frames += smb->tx_bcast_frames; 2178 stat->tx_mcast_frames += smb->tx_mcast_frames; 2179 stat->tx_pause_frames += smb->tx_pause_frames; 2180 stat->tx_excess_defer += smb->tx_excess_defer; 2181 stat->tx_control_frames += smb->tx_control_frames; 2182 stat->tx_deferred += smb->tx_deferred; 2183 stat->tx_bytes += smb->tx_bytes; 2184 stat->tx_pkts_64 += smb->tx_pkts_64; 2185 stat->tx_pkts_65_127 += smb->tx_pkts_65_127; 2186 stat->tx_pkts_128_255 += smb->tx_pkts_128_255; 2187 stat->tx_pkts_256_511 += smb->tx_pkts_256_511; 2188 stat->tx_pkts_512_1023 += smb->tx_pkts_512_1023; 2189 stat->tx_pkts_1024_1518 += smb->tx_pkts_1024_1518; 2190 stat->tx_pkts_1519_max += smb->tx_pkts_1519_max; 2191 stat->tx_single_colls += smb->tx_single_colls; 2192 stat->tx_multi_colls += smb->tx_multi_colls; 2193 stat->tx_late_colls += smb->tx_late_colls; 2194 stat->tx_excess_colls += smb->tx_excess_colls; 2195 stat->tx_abort += smb->tx_abort; 2196 stat->tx_underrun += smb->tx_underrun; 2197 stat->tx_desc_underrun += smb->tx_desc_underrun; 2198 stat->tx_lenerrs += smb->tx_lenerrs; 2199 stat->tx_pkts_truncated += smb->tx_pkts_truncated; 2200 stat->tx_bcast_bytes += smb->tx_bcast_bytes; 2201 stat->tx_mcast_bytes += smb->tx_mcast_bytes; 2202 2203 /* Update counters in ifnet. */ 2204 ifp->if_opackets += smb->tx_frames; 2205 2206 ifp->if_collisions += smb->tx_single_colls + 2207 smb->tx_multi_colls * 2 + smb->tx_late_colls + 2208 smb->tx_abort * HDPX_CFG_RETRY_DEFAULT; 2209 2210 /* 2211 * XXX 2212 * tx_pkts_truncated counter looks suspicious. It constantly 2213 * increments with no sign of Tx errors. This may indicate 2214 * the counter name is not correct one so I've removed the 2215 * counter in output errors. 2216 */ 2217 ifp->if_oerrors += smb->tx_abort + smb->tx_late_colls + 2218 smb->tx_underrun; 2219 2220 ifp->if_ipackets += smb->rx_frames; 2221 2222 ifp->if_ierrors += smb->rx_crcerrs + smb->rx_lenerrs + 2223 smb->rx_runts + smb->rx_pkts_truncated + 2224 smb->rx_fifo_oflows + smb->rx_rrs_errs + 2225 smb->rx_alignerrs; 2226 2227 if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0) { 2228 /* Update done, clear. */ 2229 smb->updated = 0; 2230 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_smb_map, 0, 2231 sc->alc_cdata.alc_smb_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 2232 } 2233 } 2234 2235 static int 2236 alc_intr(void *arg) 2237 { 2238 struct alc_softc *sc = arg; 2239 struct ifnet *ifp = &sc->sc_ec.ec_if; 2240 uint32_t status; 2241 2242 status = CSR_READ_4(sc, ALC_INTR_STATUS); 2243 if ((status & ALC_INTRS) == 0) 2244 return (0); 2245 2246 /* Acknowledge and disable interrupts. */ 2247 CSR_WRITE_4(sc, ALC_INTR_STATUS, status | INTR_DIS_INT); 2248 2249 if (ifp->if_flags & IFF_RUNNING) { 2250 if (status & INTR_RX_PKT) { 2251 int error; 2252 2253 error = alc_rxintr(sc); 2254 if (error) { 2255 alc_init_backend(ifp, false); 2256 return (0); 2257 } 2258 } 2259 2260 if (status & (INTR_DMA_RD_TO_RST | INTR_DMA_WR_TO_RST | 2261 INTR_TXQ_TO_RST)) { 2262 if (status & INTR_DMA_RD_TO_RST) 2263 printf("%s: DMA read error! -- resetting\n", 2264 device_xname(sc->sc_dev)); 2265 if (status & INTR_DMA_WR_TO_RST) 2266 printf("%s: DMA write error! -- resetting\n", 2267 device_xname(sc->sc_dev)); 2268 if (status & INTR_TXQ_TO_RST) 2269 printf("%s: TxQ reset! -- resetting\n", 2270 device_xname(sc->sc_dev)); 2271 alc_init_backend(ifp, false); 2272 return (0); 2273 } 2274 2275 alc_txeof(sc); 2276 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 2277 alc_start(ifp); 2278 } 2279 2280 /* Re-enable interrupts. */ 2281 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0x7FFFFFFF); 2282 return (1); 2283 } 2284 2285 static void 2286 alc_txeof(struct alc_softc *sc) 2287 { 2288 struct ifnet *ifp = &sc->sc_ec.ec_if; 2289 struct alc_txdesc *txd; 2290 uint32_t cons, prod; 2291 int prog; 2292 2293 if (sc->alc_cdata.alc_tx_cnt == 0) 2294 return; 2295 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_tx_ring_map, 0, 2296 sc->alc_cdata.alc_tx_ring_map->dm_mapsize, 2297 BUS_DMASYNC_POSTREAD); 2298 if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0) { 2299 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_cmb_map, 0, 2300 sc->alc_cdata.alc_cmb_map->dm_mapsize, 2301 BUS_DMASYNC_POSTREAD); 2302 prod = sc->alc_rdata.alc_cmb->cons; 2303 } else 2304 prod = CSR_READ_4(sc, ALC_MBOX_TD_CONS_IDX); 2305 /* Assume we're using normal Tx priority queue. */ 2306 prod = (prod & MBOX_TD_CONS_LO_IDX_MASK) >> 2307 MBOX_TD_CONS_LO_IDX_SHIFT; 2308 cons = sc->alc_cdata.alc_tx_cons; 2309 /* 2310 * Go through our Tx list and free mbufs for those 2311 * frames which have been transmitted. 2312 */ 2313 for (prog = 0; cons != prod; prog++, 2314 ALC_DESC_INC(cons, ALC_TX_RING_CNT)) { 2315 if (sc->alc_cdata.alc_tx_cnt <= 0) 2316 break; 2317 prog++; 2318 ifp->if_flags &= ~IFF_OACTIVE; 2319 sc->alc_cdata.alc_tx_cnt--; 2320 txd = &sc->alc_cdata.alc_txdesc[cons]; 2321 if (txd->tx_m != NULL) { 2322 /* Reclaim transmitted mbufs. */ 2323 bus_dmamap_unload(sc->sc_dmat, txd->tx_dmamap); 2324 m_freem(txd->tx_m); 2325 txd->tx_m = NULL; 2326 } 2327 } 2328 2329 if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0) 2330 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_cmb_map, 0, 2331 sc->alc_cdata.alc_cmb_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 2332 sc->alc_cdata.alc_tx_cons = cons; 2333 /* 2334 * Unarm watchdog timer only when there is no pending 2335 * frames in Tx queue. 2336 */ 2337 if (sc->alc_cdata.alc_tx_cnt == 0) 2338 ifp->if_timer = 0; 2339 } 2340 2341 static int 2342 alc_newbuf(struct alc_softc *sc, struct alc_rxdesc *rxd, bool init) 2343 { 2344 struct mbuf *m; 2345 bus_dmamap_t map; 2346 int error; 2347 2348 MGETHDR(m, init ? M_WAITOK : M_DONTWAIT, MT_DATA); 2349 if (m == NULL) 2350 return (ENOBUFS); 2351 MCLGET(m, init ? M_WAITOK : M_DONTWAIT); 2352 if (!(m->m_flags & M_EXT)) { 2353 m_freem(m); 2354 return (ENOBUFS); 2355 } 2356 2357 m->m_len = m->m_pkthdr.len = RX_BUF_SIZE_MAX; 2358 2359 error = bus_dmamap_load_mbuf(sc->sc_dmat, 2360 sc->alc_cdata.alc_rx_sparemap, m, BUS_DMA_NOWAIT); 2361 2362 if (error != 0) { 2363 if (!error) { 2364 bus_dmamap_unload(sc->sc_dmat, 2365 sc->alc_cdata.alc_rx_sparemap); 2366 error = EFBIG; 2367 printf("%s: too many segments?!\n", 2368 device_xname(sc->sc_dev)); 2369 } 2370 m_freem(m); 2371 2372 if (init) 2373 printf("%s: can't load RX mbuf\n", device_xname(sc->sc_dev)); 2374 2375 return (error); 2376 } 2377 2378 if (rxd->rx_m != NULL) { 2379 bus_dmamap_sync(sc->sc_dmat, rxd->rx_dmamap, 0, 2380 rxd->rx_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 2381 bus_dmamap_unload(sc->sc_dmat, rxd->rx_dmamap); 2382 } 2383 map = rxd->rx_dmamap; 2384 rxd->rx_dmamap = sc->alc_cdata.alc_rx_sparemap; 2385 sc->alc_cdata.alc_rx_sparemap = map; 2386 rxd->rx_m = m; 2387 rxd->rx_desc->addr = htole64(rxd->rx_dmamap->dm_segs[0].ds_addr); 2388 return (0); 2389 } 2390 2391 static int 2392 alc_rxintr(struct alc_softc *sc) 2393 { 2394 struct ifnet *ifp = &sc->sc_ec.ec_if; 2395 struct rx_rdesc *rrd; 2396 uint32_t nsegs, status; 2397 int rr_cons, prog; 2398 2399 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_rr_ring_map, 0, 2400 sc->alc_cdata.alc_rr_ring_map->dm_mapsize, BUS_DMASYNC_POSTREAD); 2401 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_rx_ring_map, 0, 2402 sc->alc_cdata.alc_rx_ring_map->dm_mapsize, BUS_DMASYNC_POSTREAD); 2403 rr_cons = sc->alc_cdata.alc_rr_cons; 2404 for (prog = 0; (ifp->if_flags & IFF_RUNNING) != 0;) { 2405 rrd = &sc->alc_rdata.alc_rr_ring[rr_cons]; 2406 status = le32toh(rrd->status); 2407 if ((status & RRD_VALID) == 0) 2408 break; 2409 nsegs = RRD_RD_CNT(le32toh(rrd->rdinfo)); 2410 if (nsegs == 0) { 2411 /* This should not happen! */ 2412 if (alcdebug) 2413 printf("%s: unexpected segment count -- " 2414 "resetting\n", device_xname(sc->sc_dev)); 2415 return (EIO); 2416 } 2417 alc_rxeof(sc, rrd); 2418 /* Clear Rx return status. */ 2419 rrd->status = 0; 2420 ALC_DESC_INC(rr_cons, ALC_RR_RING_CNT); 2421 sc->alc_cdata.alc_rx_cons += nsegs; 2422 sc->alc_cdata.alc_rx_cons %= ALC_RR_RING_CNT; 2423 prog += nsegs; 2424 } 2425 2426 if (prog > 0) { 2427 /* Update the consumer index. */ 2428 sc->alc_cdata.alc_rr_cons = rr_cons; 2429 /* Sync Rx return descriptors. */ 2430 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_rr_ring_map, 0, 2431 sc->alc_cdata.alc_rr_ring_map->dm_mapsize, 2432 BUS_DMASYNC_PREWRITE); 2433 /* 2434 * Sync updated Rx descriptors such that controller see 2435 * modified buffer addresses. 2436 */ 2437 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_rx_ring_map, 0, 2438 sc->alc_cdata.alc_rx_ring_map->dm_mapsize, 2439 BUS_DMASYNC_PREWRITE); 2440 /* 2441 * Let controller know availability of new Rx buffers. 2442 * Since alc(4) use RXQ_CFG_RD_BURST_DEFAULT descriptors 2443 * it may be possible to update ALC_MBOX_RD0_PROD_IDX 2444 * only when Rx buffer pre-fetching is required. In 2445 * addition we already set ALC_RX_RD_FREE_THRESH to 2446 * RX_RD_FREE_THRESH_LO_DEFAULT descriptors. However 2447 * it still seems that pre-fetching needs more 2448 * experimentation. 2449 */ 2450 CSR_WRITE_4(sc, ALC_MBOX_RD0_PROD_IDX, 2451 sc->alc_cdata.alc_rx_cons); 2452 } 2453 2454 return (0); 2455 } 2456 2457 /* Receive a frame. */ 2458 static void 2459 alc_rxeof(struct alc_softc *sc, struct rx_rdesc *rrd) 2460 { 2461 struct ifnet *ifp = &sc->sc_ec.ec_if; 2462 struct alc_rxdesc *rxd; 2463 struct mbuf *mp, *m; 2464 uint32_t rdinfo, status; 2465 int count, nsegs, rx_cons; 2466 2467 status = le32toh(rrd->status); 2468 rdinfo = le32toh(rrd->rdinfo); 2469 rx_cons = RRD_RD_IDX(rdinfo); 2470 nsegs = RRD_RD_CNT(rdinfo); 2471 2472 sc->alc_cdata.alc_rxlen = RRD_BYTES(status); 2473 if (status & (RRD_ERR_SUM | RRD_ERR_LENGTH)) { 2474 /* 2475 * We want to pass the following frames to upper 2476 * layer regardless of error status of Rx return 2477 * ring. 2478 * 2479 * o IP/TCP/UDP checksum is bad. 2480 * o frame length and protocol specific length 2481 * does not match. 2482 * 2483 * Force network stack compute checksum for 2484 * errored frames. 2485 */ 2486 status |= RRD_TCP_UDPCSUM_NOK | RRD_IPCSUM_NOK; 2487 if ((status & (RRD_ERR_CRC | RRD_ERR_ALIGN | 2488 RRD_ERR_TRUNC | RRD_ERR_RUNT)) != 0) 2489 return; 2490 } 2491 2492 for (count = 0; count < nsegs; count++, 2493 ALC_DESC_INC(rx_cons, ALC_RX_RING_CNT)) { 2494 rxd = &sc->alc_cdata.alc_rxdesc[rx_cons]; 2495 mp = rxd->rx_m; 2496 /* Add a new receive buffer to the ring. */ 2497 if (alc_newbuf(sc, rxd, false) != 0) { 2498 ifp->if_iqdrops++; 2499 /* Reuse Rx buffers. */ 2500 if (sc->alc_cdata.alc_rxhead != NULL) 2501 m_freem(sc->alc_cdata.alc_rxhead); 2502 break; 2503 } 2504 2505 /* 2506 * Assume we've received a full sized frame. 2507 * Actual size is fixed when we encounter the end of 2508 * multi-segmented frame. 2509 */ 2510 mp->m_len = sc->alc_buf_size; 2511 2512 /* Chain received mbufs. */ 2513 if (sc->alc_cdata.alc_rxhead == NULL) { 2514 sc->alc_cdata.alc_rxhead = mp; 2515 sc->alc_cdata.alc_rxtail = mp; 2516 } else { 2517 mp->m_flags &= ~M_PKTHDR; 2518 sc->alc_cdata.alc_rxprev_tail = 2519 sc->alc_cdata.alc_rxtail; 2520 sc->alc_cdata.alc_rxtail->m_next = mp; 2521 sc->alc_cdata.alc_rxtail = mp; 2522 } 2523 2524 if (count == nsegs - 1) { 2525 /* Last desc. for this frame. */ 2526 m = sc->alc_cdata.alc_rxhead; 2527 m->m_flags |= M_PKTHDR; 2528 /* 2529 * It seems that L1C/L2C controller has no way 2530 * to tell hardware to strip CRC bytes. 2531 */ 2532 m->m_pkthdr.len = 2533 sc->alc_cdata.alc_rxlen - ETHER_CRC_LEN; 2534 if (nsegs > 1) { 2535 /* Set last mbuf size. */ 2536 mp->m_len = sc->alc_cdata.alc_rxlen - 2537 (nsegs - 1) * sc->alc_buf_size; 2538 /* Remove the CRC bytes in chained mbufs. */ 2539 if (mp->m_len <= ETHER_CRC_LEN) { 2540 sc->alc_cdata.alc_rxtail = 2541 sc->alc_cdata.alc_rxprev_tail; 2542 sc->alc_cdata.alc_rxtail->m_len -= 2543 (ETHER_CRC_LEN - mp->m_len); 2544 sc->alc_cdata.alc_rxtail->m_next = NULL; 2545 m_freem(mp); 2546 } else { 2547 mp->m_len -= ETHER_CRC_LEN; 2548 } 2549 } else 2550 m->m_len = m->m_pkthdr.len; 2551 m->m_pkthdr.rcvif = ifp; 2552 #if NVLAN > 0 2553 /* 2554 * Due to hardware bugs, Rx checksum offloading 2555 * was intentionally disabled. 2556 */ 2557 if (status & RRD_VLAN_TAG) { 2558 u_int32_t vtag = RRD_VLAN(le32toh(rrd->vtag)); 2559 VLAN_INPUT_TAG(ifp, m, ntohs(vtag), ); 2560 } 2561 #endif 2562 2563 bpf_mtap(ifp, m); 2564 2565 /* Pass it on. */ 2566 (*ifp->if_input)(ifp, m); 2567 } 2568 } 2569 /* Reset mbuf chains. */ 2570 ALC_RXCHAIN_RESET(sc); 2571 } 2572 2573 static void 2574 alc_tick(void *xsc) 2575 { 2576 struct alc_softc *sc = xsc; 2577 struct mii_data *mii = &sc->sc_miibus; 2578 int s; 2579 2580 s = splnet(); 2581 mii_tick(mii); 2582 alc_stats_update(sc); 2583 splx(s); 2584 2585 callout_schedule(&sc->sc_tick_ch, hz); 2586 } 2587 2588 static void 2589 alc_osc_reset(struct alc_softc *sc) 2590 { 2591 uint32_t reg; 2592 2593 reg = CSR_READ_4(sc, ALC_MISC3); 2594 reg &= ~MISC3_25M_BY_SW; 2595 reg |= MISC3_25M_NOTO_INTNL; 2596 CSR_WRITE_4(sc, ALC_MISC3, reg); 2597 2598 reg = CSR_READ_4(sc, ALC_MISC); 2599 if (AR816X_REV(sc->alc_rev) >= AR816X_REV_B0) { 2600 /* 2601 * Restore over-current protection default value. 2602 * This value could be reset by MAC reset. 2603 */ 2604 reg &= ~MISC_PSW_OCP_MASK; 2605 reg |= (MISC_PSW_OCP_DEFAULT << MISC_PSW_OCP_SHIFT); 2606 reg &= ~MISC_INTNLOSC_OPEN; 2607 CSR_WRITE_4(sc, ALC_MISC, reg); 2608 CSR_WRITE_4(sc, ALC_MISC, reg | MISC_INTNLOSC_OPEN); 2609 reg = CSR_READ_4(sc, ALC_MISC2); 2610 reg &= ~MISC2_CALB_START; 2611 CSR_WRITE_4(sc, ALC_MISC2, reg); 2612 CSR_WRITE_4(sc, ALC_MISC2, reg | MISC2_CALB_START); 2613 2614 } else { 2615 reg &= ~MISC_INTNLOSC_OPEN; 2616 /* Disable isolate for revision A devices. */ 2617 if (AR816X_REV(sc->alc_rev) <= AR816X_REV_A1) 2618 reg &= ~MISC_ISO_ENB; 2619 CSR_WRITE_4(sc, ALC_MISC, reg | MISC_INTNLOSC_OPEN); 2620 CSR_WRITE_4(sc, ALC_MISC, reg); 2621 } 2622 2623 DELAY(20); 2624 } 2625 2626 static void 2627 alc_reset(struct alc_softc *sc) 2628 { 2629 uint32_t pmcfg, reg; 2630 int i; 2631 2632 pmcfg = 0; 2633 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 2634 /* Reset workaround. */ 2635 CSR_WRITE_4(sc, ALC_MBOX_RD0_PROD_IDX, 1); 2636 if (AR816X_REV(sc->alc_rev) <= AR816X_REV_A1 && 2637 (sc->alc_rev & 0x01) != 0) { 2638 /* Disable L0s/L1s before reset. */ 2639 pmcfg = CSR_READ_4(sc, ALC_PM_CFG); 2640 if ((pmcfg & (PM_CFG_ASPM_L0S_ENB | PM_CFG_ASPM_L1_ENB)) 2641 != 0) { 2642 pmcfg &= ~(PM_CFG_ASPM_L0S_ENB | 2643 PM_CFG_ASPM_L1_ENB); 2644 CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg); 2645 } 2646 } 2647 } 2648 reg = CSR_READ_4(sc, ALC_MASTER_CFG); 2649 reg |= MASTER_OOB_DIS_OFF | MASTER_RESET; 2650 CSR_WRITE_4(sc, ALC_MASTER_CFG, reg); 2651 2652 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 2653 for (i = ALC_RESET_TIMEOUT; i > 0; i--) { 2654 DELAY(10); 2655 if (CSR_READ_4(sc, ALC_MBOX_RD0_PROD_IDX) == 0) 2656 break; 2657 } 2658 if (i == 0) 2659 printf("%s: MAC reset timeout!\n", device_xname(sc->sc_dev)); 2660 } 2661 for (i = ALC_RESET_TIMEOUT; i > 0; i--) { 2662 DELAY(10); 2663 if ((CSR_READ_4(sc, ALC_MASTER_CFG) & MASTER_RESET) == 0) 2664 break; 2665 } 2666 if (i == 0) 2667 printf("%s: master reset timeout!\n", device_xname(sc->sc_dev)); 2668 2669 for (i = ALC_RESET_TIMEOUT; i > 0; i--) { 2670 reg = CSR_READ_4(sc, ALC_IDLE_STATUS); 2671 if ((reg & (IDLE_STATUS_RXMAC | IDLE_STATUS_TXMAC | 2672 IDLE_STATUS_RXQ | IDLE_STATUS_TXQ)) == 0) 2673 break; 2674 DELAY(10); 2675 } 2676 if (i == 0) 2677 printf("%s: reset timeout(0x%08x)!\n", 2678 device_xname(sc->sc_dev), reg); 2679 2680 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 2681 if (AR816X_REV(sc->alc_rev) <= AR816X_REV_A1 && 2682 (sc->alc_rev & 0x01) != 0) { 2683 reg = CSR_READ_4(sc, ALC_MASTER_CFG); 2684 reg |= MASTER_CLK_SEL_DIS; 2685 CSR_WRITE_4(sc, ALC_MASTER_CFG, reg); 2686 /* Restore L0s/L1s config. */ 2687 if ((pmcfg & (PM_CFG_ASPM_L0S_ENB | PM_CFG_ASPM_L1_ENB)) 2688 != 0) 2689 CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg); 2690 } 2691 2692 alc_osc_reset(sc); 2693 reg = CSR_READ_4(sc, ALC_MISC3); 2694 reg &= ~MISC3_25M_BY_SW; 2695 reg |= MISC3_25M_NOTO_INTNL; 2696 CSR_WRITE_4(sc, ALC_MISC3, reg); 2697 reg = CSR_READ_4(sc, ALC_MISC); 2698 reg &= ~MISC_INTNLOSC_OPEN; 2699 if (AR816X_REV(sc->alc_rev) <= AR816X_REV_A1) 2700 reg &= ~MISC_ISO_ENB; 2701 CSR_WRITE_4(sc, ALC_MISC, reg); 2702 DELAY(20); 2703 } 2704 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0 || 2705 sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8152_B || 2706 sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8151_V2) 2707 CSR_WRITE_4(sc, ALC_SERDES_LOCK, 2708 CSR_READ_4(sc, ALC_SERDES_LOCK) | SERDES_MAC_CLK_SLOWDOWN | 2709 SERDES_PHY_CLK_SLOWDOWN); 2710 } 2711 2712 static int 2713 alc_init(struct ifnet *ifp) 2714 { 2715 2716 return alc_init_backend(ifp, true); 2717 } 2718 2719 static int 2720 alc_init_backend(struct ifnet *ifp, bool init) 2721 { 2722 struct alc_softc *sc = ifp->if_softc; 2723 struct mii_data *mii; 2724 uint8_t eaddr[ETHER_ADDR_LEN]; 2725 bus_addr_t paddr; 2726 uint32_t reg, rxf_hi, rxf_lo; 2727 int error; 2728 2729 /* 2730 * Cancel any pending I/O. 2731 */ 2732 alc_stop(ifp, 0); 2733 /* 2734 * Reset the chip to a known state. 2735 */ 2736 alc_reset(sc); 2737 2738 /* Initialize Rx descriptors. */ 2739 error = alc_init_rx_ring(sc, init); 2740 if (error != 0) { 2741 printf("%s: no memory for Rx buffers.\n", device_xname(sc->sc_dev)); 2742 alc_stop(ifp, 0); 2743 return (error); 2744 } 2745 alc_init_rr_ring(sc); 2746 alc_init_tx_ring(sc); 2747 alc_init_cmb(sc); 2748 alc_init_smb(sc); 2749 2750 /* Enable all clocks. */ 2751 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 2752 CSR_WRITE_4(sc, ALC_CLK_GATING_CFG, CLK_GATING_DMAW_ENB | 2753 CLK_GATING_DMAR_ENB | CLK_GATING_TXQ_ENB | 2754 CLK_GATING_RXQ_ENB | CLK_GATING_TXMAC_ENB | 2755 CLK_GATING_RXMAC_ENB); 2756 if (AR816X_REV(sc->alc_rev) >= AR816X_REV_B0) 2757 CSR_WRITE_4(sc, ALC_IDLE_DECISN_TIMER, 2758 IDLE_DECISN_TIMER_DEFAULT_1MS); 2759 } else 2760 CSR_WRITE_4(sc, ALC_CLK_GATING_CFG, 0); 2761 2762 2763 /* Reprogram the station address. */ 2764 memcpy(eaddr, CLLADDR(ifp->if_sadl), sizeof(eaddr)); 2765 CSR_WRITE_4(sc, ALC_PAR0, 2766 eaddr[2] << 24 | eaddr[3] << 16 | eaddr[4] << 8 | eaddr[5]); 2767 CSR_WRITE_4(sc, ALC_PAR1, eaddr[0] << 8 | eaddr[1]); 2768 /* 2769 * Clear WOL status and disable all WOL feature as WOL 2770 * would interfere Rx operation under normal environments. 2771 */ 2772 CSR_READ_4(sc, ALC_WOL_CFG); 2773 CSR_WRITE_4(sc, ALC_WOL_CFG, 0); 2774 /* Set Tx descriptor base addresses. */ 2775 paddr = sc->alc_rdata.alc_tx_ring_paddr; 2776 CSR_WRITE_4(sc, ALC_TX_BASE_ADDR_HI, ALC_ADDR_HI(paddr)); 2777 CSR_WRITE_4(sc, ALC_TDL_HEAD_ADDR_LO, ALC_ADDR_LO(paddr)); 2778 /* We don't use high priority ring. */ 2779 CSR_WRITE_4(sc, ALC_TDH_HEAD_ADDR_LO, 0); 2780 /* Set Tx descriptor counter. */ 2781 CSR_WRITE_4(sc, ALC_TD_RING_CNT, 2782 (ALC_TX_RING_CNT << TD_RING_CNT_SHIFT) & TD_RING_CNT_MASK); 2783 /* Set Rx descriptor base addresses. */ 2784 paddr = sc->alc_rdata.alc_rx_ring_paddr; 2785 CSR_WRITE_4(sc, ALC_RX_BASE_ADDR_HI, ALC_ADDR_HI(paddr)); 2786 CSR_WRITE_4(sc, ALC_RD0_HEAD_ADDR_LO, ALC_ADDR_LO(paddr)); 2787 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 2788 /* We use one Rx ring. */ 2789 CSR_WRITE_4(sc, ALC_RD1_HEAD_ADDR_LO, 0); 2790 CSR_WRITE_4(sc, ALC_RD2_HEAD_ADDR_LO, 0); 2791 CSR_WRITE_4(sc, ALC_RD3_HEAD_ADDR_LO, 0); 2792 } 2793 /* Set Rx descriptor counter. */ 2794 CSR_WRITE_4(sc, ALC_RD_RING_CNT, 2795 (ALC_RX_RING_CNT << RD_RING_CNT_SHIFT) & RD_RING_CNT_MASK); 2796 2797 /* 2798 * Let hardware split jumbo frames into alc_max_buf_sized chunks. 2799 * if it do not fit the buffer size. Rx return descriptor holds 2800 * a counter that indicates how many fragments were made by the 2801 * hardware. The buffer size should be multiple of 8 bytes. 2802 * Since hardware has limit on the size of buffer size, always 2803 * use the maximum value. 2804 * For strict-alignment architectures make sure to reduce buffer 2805 * size by 8 bytes to make room for alignment fixup. 2806 */ 2807 sc->alc_buf_size = RX_BUF_SIZE_MAX; 2808 CSR_WRITE_4(sc, ALC_RX_BUF_SIZE, sc->alc_buf_size); 2809 2810 paddr = sc->alc_rdata.alc_rr_ring_paddr; 2811 /* Set Rx return descriptor base addresses. */ 2812 CSR_WRITE_4(sc, ALC_RRD0_HEAD_ADDR_LO, ALC_ADDR_LO(paddr)); 2813 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 2814 /* We use one Rx return ring. */ 2815 CSR_WRITE_4(sc, ALC_RRD1_HEAD_ADDR_LO, 0); 2816 CSR_WRITE_4(sc, ALC_RRD2_HEAD_ADDR_LO, 0); 2817 CSR_WRITE_4(sc, ALC_RRD3_HEAD_ADDR_LO, 0); 2818 }\ 2819 /* Set Rx return descriptor counter. */ 2820 CSR_WRITE_4(sc, ALC_RRD_RING_CNT, 2821 (ALC_RR_RING_CNT << RRD_RING_CNT_SHIFT) & RRD_RING_CNT_MASK); 2822 paddr = sc->alc_rdata.alc_cmb_paddr; 2823 CSR_WRITE_4(sc, ALC_CMB_BASE_ADDR_LO, ALC_ADDR_LO(paddr)); 2824 paddr = sc->alc_rdata.alc_smb_paddr; 2825 CSR_WRITE_4(sc, ALC_SMB_BASE_ADDR_HI, ALC_ADDR_HI(paddr)); 2826 CSR_WRITE_4(sc, ALC_SMB_BASE_ADDR_LO, ALC_ADDR_LO(paddr)); 2827 2828 if (sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8152_B) { 2829 /* Reconfigure SRAM - Vendor magic. */ 2830 CSR_WRITE_4(sc, ALC_SRAM_RX_FIFO_LEN, 0x000002A0); 2831 CSR_WRITE_4(sc, ALC_SRAM_TX_FIFO_LEN, 0x00000100); 2832 CSR_WRITE_4(sc, ALC_SRAM_RX_FIFO_ADDR, 0x029F0000); 2833 CSR_WRITE_4(sc, ALC_SRAM_RD0_ADDR, 0x02BF02A0); 2834 CSR_WRITE_4(sc, ALC_SRAM_TX_FIFO_ADDR, 0x03BF02C0); 2835 CSR_WRITE_4(sc, ALC_SRAM_TD_ADDR, 0x03DF03C0); 2836 CSR_WRITE_4(sc, ALC_TXF_WATER_MARK, 0x00000000); 2837 CSR_WRITE_4(sc, ALC_RD_DMA_CFG, 0x00000000); 2838 } 2839 2840 /* Tell hardware that we're ready to load DMA blocks. */ 2841 CSR_WRITE_4(sc, ALC_DMA_BLOCK, DMA_BLOCK_LOAD); 2842 2843 /* Configure interrupt moderation timer. */ 2844 sc->alc_int_rx_mod = ALC_IM_RX_TIMER_DEFAULT; 2845 sc->alc_int_tx_mod = ALC_IM_TX_TIMER_DEFAULT; 2846 reg = ALC_USECS(sc->alc_int_rx_mod) << IM_TIMER_RX_SHIFT; 2847 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) 2848 reg |= ALC_USECS(sc->alc_int_tx_mod) << IM_TIMER_TX_SHIFT; 2849 CSR_WRITE_4(sc, ALC_IM_TIMER, reg); 2850 /* 2851 * We don't want to automatic interrupt clear as task queue 2852 * for the interrupt should know interrupt status. 2853 */ 2854 reg = CSR_READ_4(sc, ALC_MASTER_CFG); 2855 reg &= ~(MASTER_IM_RX_TIMER_ENB | MASTER_IM_TX_TIMER_ENB); 2856 reg |= MASTER_SA_TIMER_ENB; 2857 if (ALC_USECS(sc->alc_int_rx_mod) != 0) 2858 reg |= MASTER_IM_RX_TIMER_ENB; 2859 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0 && 2860 ALC_USECS(sc->alc_int_tx_mod) != 0) 2861 reg |= MASTER_IM_TX_TIMER_ENB; 2862 CSR_WRITE_4(sc, ALC_MASTER_CFG, reg); 2863 /* 2864 * Disable interrupt re-trigger timer. We don't want automatic 2865 * re-triggering of un-ACKed interrupts. 2866 */ 2867 CSR_WRITE_4(sc, ALC_INTR_RETRIG_TIMER, ALC_USECS(0)); 2868 /* Configure CMB. */ 2869 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 2870 CSR_WRITE_4(sc, ALC_CMB_TD_THRESH, ALC_TX_RING_CNT / 3); 2871 CSR_WRITE_4(sc, ALC_CMB_TX_TIMER, 2872 ALC_USECS(sc->alc_int_tx_mod)); 2873 } else { 2874 if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0) { 2875 CSR_WRITE_4(sc, ALC_CMB_TD_THRESH, 4); 2876 CSR_WRITE_4(sc, ALC_CMB_TX_TIMER, ALC_USECS(5000)); 2877 } else 2878 CSR_WRITE_4(sc, ALC_CMB_TX_TIMER, ALC_USECS(0)); 2879 } 2880 /* 2881 * Hardware can be configured to issue SMB interrupt based 2882 * on programmed interval. Since there is a callout that is 2883 * invoked for every hz in driver we use that instead of 2884 * relying on periodic SMB interrupt. 2885 */ 2886 CSR_WRITE_4(sc, ALC_SMB_STAT_TIMER, ALC_USECS(0)); 2887 /* Clear MAC statistics. */ 2888 alc_stats_clear(sc); 2889 2890 /* 2891 * Always use maximum frame size that controller can support. 2892 * Otherwise received frames that has larger frame length 2893 * than alc(4) MTU would be silently dropped in hardware. This 2894 * would make path-MTU discovery hard as sender wouldn't get 2895 * any responses from receiver. alc(4) supports 2896 * multi-fragmented frames on Rx path so it has no issue on 2897 * assembling fragmented frames. Using maximum frame size also 2898 * removes the need to reinitialize hardware when interface 2899 * MTU configuration was changed. 2900 * 2901 * Be conservative in what you do, be liberal in what you 2902 * accept from others - RFC 793. 2903 */ 2904 CSR_WRITE_4(sc, ALC_FRAME_SIZE, sc->alc_ident->max_framelen); 2905 2906 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 2907 /* Disable header split(?) */ 2908 CSR_WRITE_4(sc, ALC_HDS_CFG, 0); 2909 2910 /* Configure IPG/IFG parameters. */ 2911 CSR_WRITE_4(sc, ALC_IPG_IFG_CFG, 2912 ((IPG_IFG_IPGT_DEFAULT << IPG_IFG_IPGT_SHIFT) & 2913 IPG_IFG_IPGT_MASK) | 2914 ((IPG_IFG_MIFG_DEFAULT << IPG_IFG_MIFG_SHIFT) & 2915 IPG_IFG_MIFG_MASK) | 2916 ((IPG_IFG_IPG1_DEFAULT << IPG_IFG_IPG1_SHIFT) & 2917 IPG_IFG_IPG1_MASK) | 2918 ((IPG_IFG_IPG2_DEFAULT << IPG_IFG_IPG2_SHIFT) & 2919 IPG_IFG_IPG2_MASK)); 2920 /* Set parameters for half-duplex media. */ 2921 CSR_WRITE_4(sc, ALC_HDPX_CFG, 2922 ((HDPX_CFG_LCOL_DEFAULT << HDPX_CFG_LCOL_SHIFT) & 2923 HDPX_CFG_LCOL_MASK) | 2924 ((HDPX_CFG_RETRY_DEFAULT << HDPX_CFG_RETRY_SHIFT) & 2925 HDPX_CFG_RETRY_MASK) | HDPX_CFG_EXC_DEF_EN | 2926 ((HDPX_CFG_ABEBT_DEFAULT << HDPX_CFG_ABEBT_SHIFT) & 2927 HDPX_CFG_ABEBT_MASK) | 2928 ((HDPX_CFG_JAMIPG_DEFAULT << HDPX_CFG_JAMIPG_SHIFT) & 2929 HDPX_CFG_JAMIPG_MASK)); 2930 } 2931 2932 /* 2933 * Set TSO/checksum offload threshold. For frames that is 2934 * larger than this threshold, hardware wouldn't do 2935 * TSO/checksum offloading. 2936 */ 2937 reg = (sc->alc_ident->max_framelen >> TSO_OFFLOAD_THRESH_UNIT_SHIFT) & 2938 TSO_OFFLOAD_THRESH_MASK; 2939 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 2940 reg |= TSO_OFFLOAD_ERRLGPKT_DROP_ENB; 2941 CSR_WRITE_4(sc, ALC_TSO_OFFLOAD_THRESH, reg); 2942 /* Configure TxQ. */ 2943 reg = (alc_dma_burst[sc->alc_dma_rd_burst] << 2944 TXQ_CFG_TX_FIFO_BURST_SHIFT) & TXQ_CFG_TX_FIFO_BURST_MASK; 2945 if (sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8152_B || 2946 sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8152_B2) 2947 reg >>= 1; 2948 reg |= (TXQ_CFG_TD_BURST_DEFAULT << TXQ_CFG_TD_BURST_SHIFT) & 2949 TXQ_CFG_TD_BURST_MASK; 2950 reg |= TXQ_CFG_IP_OPTION_ENB | TXQ_CFG_8023_ENB; 2951 CSR_WRITE_4(sc, ALC_TXQ_CFG, reg | TXQ_CFG_ENHANCED_MODE); 2952 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 2953 reg = (TXQ_CFG_TD_BURST_DEFAULT << HQTD_CFG_Q1_BURST_SHIFT | 2954 TXQ_CFG_TD_BURST_DEFAULT << HQTD_CFG_Q2_BURST_SHIFT | 2955 TXQ_CFG_TD_BURST_DEFAULT << HQTD_CFG_Q3_BURST_SHIFT | 2956 HQTD_CFG_BURST_ENB); 2957 CSR_WRITE_4(sc, ALC_HQTD_CFG, reg); 2958 reg = WRR_PRI_RESTRICT_NONE; 2959 reg |= (WRR_PRI_DEFAULT << WRR_PRI0_SHIFT | 2960 WRR_PRI_DEFAULT << WRR_PRI1_SHIFT | 2961 WRR_PRI_DEFAULT << WRR_PRI2_SHIFT | 2962 WRR_PRI_DEFAULT << WRR_PRI3_SHIFT); 2963 CSR_WRITE_4(sc, ALC_WRR, reg); 2964 } else { 2965 /* Configure Rx free descriptor pre-fetching. */ 2966 CSR_WRITE_4(sc, ALC_RX_RD_FREE_THRESH, 2967 ((RX_RD_FREE_THRESH_HI_DEFAULT << 2968 RX_RD_FREE_THRESH_HI_SHIFT) & RX_RD_FREE_THRESH_HI_MASK) | 2969 ((RX_RD_FREE_THRESH_LO_DEFAULT << 2970 RX_RD_FREE_THRESH_LO_SHIFT) & RX_RD_FREE_THRESH_LO_MASK)); 2971 } 2972 2973 /* 2974 * Configure flow control parameters. 2975 * XON : 80% of Rx FIFO 2976 * XOFF : 30% of Rx FIFO 2977 */ 2978 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 2979 reg = CSR_READ_4(sc, ALC_SRAM_RX_FIFO_LEN); 2980 reg &= SRAM_RX_FIFO_LEN_MASK; 2981 reg *= 8; 2982 if (reg > 8 * 1024) 2983 reg -= RX_FIFO_PAUSE_816X_RSVD; 2984 else 2985 reg -= RX_BUF_SIZE_MAX; 2986 reg /= 8; 2987 CSR_WRITE_4(sc, ALC_RX_FIFO_PAUSE_THRESH, 2988 ((reg << RX_FIFO_PAUSE_THRESH_LO_SHIFT) & 2989 RX_FIFO_PAUSE_THRESH_LO_MASK) | 2990 (((RX_FIFO_PAUSE_816X_RSVD / 8) << 2991 RX_FIFO_PAUSE_THRESH_HI_SHIFT) & 2992 RX_FIFO_PAUSE_THRESH_HI_MASK)); 2993 } else if (sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8131 || 2994 sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8132) { 2995 reg = CSR_READ_4(sc, ALC_SRAM_RX_FIFO_LEN); 2996 rxf_hi = (reg * 8) / 10; 2997 rxf_lo = (reg * 3) / 10; 2998 CSR_WRITE_4(sc, ALC_RX_FIFO_PAUSE_THRESH, 2999 ((rxf_lo << RX_FIFO_PAUSE_THRESH_LO_SHIFT) & 3000 RX_FIFO_PAUSE_THRESH_LO_MASK) | 3001 ((rxf_hi << RX_FIFO_PAUSE_THRESH_HI_SHIFT) & 3002 RX_FIFO_PAUSE_THRESH_HI_MASK)); 3003 } 3004 3005 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 3006 /* Disable RSS until I understand L1C/L2C's RSS logic. */ 3007 CSR_WRITE_4(sc, ALC_RSS_IDT_TABLE0, 0); 3008 CSR_WRITE_4(sc, ALC_RSS_CPU, 0); 3009 } 3010 3011 /* Configure RxQ. */ 3012 reg = (RXQ_CFG_RD_BURST_DEFAULT << RXQ_CFG_RD_BURST_SHIFT) & 3013 RXQ_CFG_RD_BURST_MASK; 3014 reg |= RXQ_CFG_RSS_MODE_DIS; 3015 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 3016 reg |= (RXQ_CFG_816X_IDT_TBL_SIZE_DEFAULT << 3017 RXQ_CFG_816X_IDT_TBL_SIZE_SHIFT) & 3018 RXQ_CFG_816X_IDT_TBL_SIZE_MASK; 3019 if ((sc->alc_flags & ALC_FLAG_FASTETHER) == 0 && 3020 sc->alc_ident->deviceid != PCI_PRODUCT_ATTANSIC_AR8151_V2) 3021 reg |= RXQ_CFG_ASPM_THROUGHPUT_LIMIT_1M; 3022 CSR_WRITE_4(sc, ALC_RXQ_CFG, reg); 3023 3024 /* Configure DMA parameters. */ 3025 reg = DMA_CFG_OUT_ORDER | DMA_CFG_RD_REQ_PRI; 3026 reg |= sc->alc_rcb; 3027 if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0) 3028 reg |= DMA_CFG_CMB_ENB; 3029 if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0) 3030 reg |= DMA_CFG_SMB_ENB; 3031 else 3032 reg |= DMA_CFG_SMB_DIS; 3033 reg |= (sc->alc_dma_rd_burst & DMA_CFG_RD_BURST_MASK) << 3034 DMA_CFG_RD_BURST_SHIFT; 3035 reg |= (sc->alc_dma_wr_burst & DMA_CFG_WR_BURST_MASK) << 3036 DMA_CFG_WR_BURST_SHIFT; 3037 reg |= (DMA_CFG_RD_DELAY_CNT_DEFAULT << DMA_CFG_RD_DELAY_CNT_SHIFT) & 3038 DMA_CFG_RD_DELAY_CNT_MASK; 3039 reg |= (DMA_CFG_WR_DELAY_CNT_DEFAULT << DMA_CFG_WR_DELAY_CNT_SHIFT) & 3040 DMA_CFG_WR_DELAY_CNT_MASK; 3041 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 3042 switch (AR816X_REV(sc->alc_rev)) { 3043 case AR816X_REV_A0: 3044 case AR816X_REV_A1: 3045 reg |= DMA_CFG_RD_CHNL_SEL_1; 3046 break; 3047 case AR816X_REV_B0: 3048 /* FALLTHROUGH */ 3049 default: 3050 reg |= DMA_CFG_RD_CHNL_SEL_3; 3051 break; 3052 } 3053 } 3054 CSR_WRITE_4(sc, ALC_DMA_CFG, reg); 3055 3056 /* 3057 * Configure Tx/Rx MACs. 3058 * - Auto-padding for short frames. 3059 * - Enable CRC generation. 3060 * Actual reconfiguration of MAC for resolved speed/duplex 3061 * is followed after detection of link establishment. 3062 * AR813x/AR815x always does checksum computation regardless 3063 * of MAC_CFG_RXCSUM_ENB bit. Also the controller is known to 3064 * have bug in protocol field in Rx return structure so 3065 * these controllers can't handle fragmented frames. Disable 3066 * Rx checksum offloading until there is a newer controller 3067 * that has sane implementation. 3068 */ 3069 reg = MAC_CFG_TX_CRC_ENB | MAC_CFG_TX_AUTO_PAD | MAC_CFG_FULL_DUPLEX | 3070 ((MAC_CFG_PREAMBLE_DEFAULT << MAC_CFG_PREAMBLE_SHIFT) & 3071 MAC_CFG_PREAMBLE_MASK); 3072 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0 || 3073 sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8151 || 3074 sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8151_V2 || 3075 sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8152_B2) 3076 reg |= MAC_CFG_HASH_ALG_CRC32 | MAC_CFG_SPEED_MODE_SW; 3077 if ((sc->alc_flags & ALC_FLAG_FASTETHER) != 0) 3078 reg |= MAC_CFG_SPEED_10_100; 3079 else 3080 reg |= MAC_CFG_SPEED_1000; 3081 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 3082 3083 /* Set up the receive filter. */ 3084 alc_iff(sc); 3085 alc_rxvlan(sc); 3086 3087 /* Acknowledge all pending interrupts and clear it. */ 3088 CSR_WRITE_4(sc, ALC_INTR_MASK, ALC_INTRS); 3089 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0xFFFFFFFF); 3090 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0); 3091 3092 sc->alc_flags &= ~ALC_FLAG_LINK; 3093 /* Switch to the current media. */ 3094 mii = &sc->sc_miibus; 3095 mii_mediachg(mii); 3096 3097 callout_schedule(&sc->sc_tick_ch, hz); 3098 3099 ifp->if_flags |= IFF_RUNNING; 3100 ifp->if_flags &= ~IFF_OACTIVE; 3101 3102 return (0); 3103 } 3104 3105 static void 3106 alc_stop(struct ifnet *ifp, int disable) 3107 { 3108 struct alc_softc *sc = ifp->if_softc; 3109 struct alc_txdesc *txd; 3110 struct alc_rxdesc *rxd; 3111 uint32_t reg; 3112 int i; 3113 3114 callout_stop(&sc->sc_tick_ch); 3115 3116 /* 3117 * Mark the interface down and cancel the watchdog timer. 3118 */ 3119 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 3120 ifp->if_timer = 0; 3121 3122 sc->alc_flags &= ~ALC_FLAG_LINK; 3123 3124 alc_stats_update(sc); 3125 3126 mii_down(&sc->sc_miibus); 3127 3128 /* Disable interrupts. */ 3129 CSR_WRITE_4(sc, ALC_INTR_MASK, 0); 3130 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0xFFFFFFFF); 3131 3132 /* Disable DMA. */ 3133 reg = CSR_READ_4(sc, ALC_DMA_CFG); 3134 reg &= ~(DMA_CFG_CMB_ENB | DMA_CFG_SMB_ENB); 3135 reg |= DMA_CFG_SMB_DIS; 3136 CSR_WRITE_4(sc, ALC_DMA_CFG, reg); 3137 DELAY(1000); 3138 3139 /* Stop Rx/Tx MACs. */ 3140 alc_stop_mac(sc); 3141 3142 /* Disable interrupts which might be touched in taskq handler. */ 3143 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0xFFFFFFFF); 3144 3145 /* Disable L0s/L1s */ 3146 alc_aspm(sc, 0, IFM_UNKNOWN); 3147 3148 /* Reclaim Rx buffers that have been processed. */ 3149 if (sc->alc_cdata.alc_rxhead != NULL) 3150 m_freem(sc->alc_cdata.alc_rxhead); 3151 ALC_RXCHAIN_RESET(sc); 3152 /* 3153 * Free Tx/Rx mbufs still in the queues. 3154 */ 3155 for (i = 0; i < ALC_RX_RING_CNT; i++) { 3156 rxd = &sc->alc_cdata.alc_rxdesc[i]; 3157 if (rxd->rx_m != NULL) { 3158 bus_dmamap_unload(sc->sc_dmat, rxd->rx_dmamap); 3159 m_freem(rxd->rx_m); 3160 rxd->rx_m = NULL; 3161 } 3162 } 3163 for (i = 0; i < ALC_TX_RING_CNT; i++) { 3164 txd = &sc->alc_cdata.alc_txdesc[i]; 3165 if (txd->tx_m != NULL) { 3166 bus_dmamap_unload(sc->sc_dmat, txd->tx_dmamap); 3167 m_freem(txd->tx_m); 3168 txd->tx_m = NULL; 3169 } 3170 } 3171 } 3172 3173 static void 3174 alc_stop_mac(struct alc_softc *sc) 3175 { 3176 uint32_t reg; 3177 int i; 3178 3179 alc_stop_queue(sc); 3180 /* Disable Rx/Tx MAC. */ 3181 reg = CSR_READ_4(sc, ALC_MAC_CFG); 3182 if ((reg & (MAC_CFG_TX_ENB | MAC_CFG_RX_ENB)) != 0) { 3183 reg &= ~(MAC_CFG_TX_ENB | MAC_CFG_RX_ENB); 3184 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 3185 } 3186 for (i = ALC_TIMEOUT; i > 0; i--) { 3187 reg = CSR_READ_4(sc, ALC_IDLE_STATUS); 3188 if ((reg & (IDLE_STATUS_RXMAC | IDLE_STATUS_TXMAC)) == 0) 3189 break; 3190 DELAY(10); 3191 } 3192 if (i == 0) 3193 printf("%s: could not disable Rx/Tx MAC(0x%08x)!\n", 3194 device_xname(sc->sc_dev), reg); 3195 } 3196 3197 static void 3198 alc_start_queue(struct alc_softc *sc) 3199 { 3200 uint32_t qcfg[] = { 3201 0, 3202 RXQ_CFG_QUEUE0_ENB, 3203 RXQ_CFG_QUEUE0_ENB | RXQ_CFG_QUEUE1_ENB, 3204 RXQ_CFG_QUEUE0_ENB | RXQ_CFG_QUEUE1_ENB | RXQ_CFG_QUEUE2_ENB, 3205 RXQ_CFG_ENB 3206 }; 3207 uint32_t cfg; 3208 3209 /* Enable RxQ. */ 3210 cfg = CSR_READ_4(sc, ALC_RXQ_CFG); 3211 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 3212 cfg &= ~RXQ_CFG_ENB; 3213 cfg |= qcfg[1]; 3214 } else 3215 cfg |= RXQ_CFG_QUEUE0_ENB; 3216 CSR_WRITE_4(sc, ALC_RXQ_CFG, cfg); 3217 /* Enable TxQ. */ 3218 cfg = CSR_READ_4(sc, ALC_TXQ_CFG); 3219 cfg |= TXQ_CFG_ENB; 3220 CSR_WRITE_4(sc, ALC_TXQ_CFG, cfg); 3221 } 3222 3223 static void 3224 alc_stop_queue(struct alc_softc *sc) 3225 { 3226 uint32_t reg; 3227 int i; 3228 3229 /* Disable RxQ. */ 3230 reg = CSR_READ_4(sc, ALC_RXQ_CFG); 3231 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 3232 if ((reg & RXQ_CFG_ENB) != 0) { 3233 reg &= ~RXQ_CFG_ENB; 3234 CSR_WRITE_4(sc, ALC_RXQ_CFG, reg); 3235 } 3236 } else { 3237 if ((reg & RXQ_CFG_QUEUE0_ENB) != 0) { 3238 reg &= ~RXQ_CFG_QUEUE0_ENB; 3239 CSR_WRITE_4(sc, ALC_RXQ_CFG, reg); 3240 } 3241 } 3242 /* Disable TxQ. */ 3243 reg = CSR_READ_4(sc, ALC_TXQ_CFG); 3244 if ((reg & TXQ_CFG_ENB) != 0) { 3245 reg &= ~TXQ_CFG_ENB; 3246 CSR_WRITE_4(sc, ALC_TXQ_CFG, reg); 3247 } 3248 DELAY(40); 3249 for (i = ALC_TIMEOUT; i > 0; i--) { 3250 reg = CSR_READ_4(sc, ALC_IDLE_STATUS); 3251 if ((reg & (IDLE_STATUS_RXQ | IDLE_STATUS_TXQ)) == 0) 3252 break; 3253 DELAY(10); 3254 } 3255 if (i == 0) 3256 printf("%s: could not disable RxQ/TxQ (0x%08x)!\n", 3257 device_xname(sc->sc_dev), reg); 3258 } 3259 3260 static void 3261 alc_init_tx_ring(struct alc_softc *sc) 3262 { 3263 struct alc_ring_data *rd; 3264 struct alc_txdesc *txd; 3265 int i; 3266 3267 sc->alc_cdata.alc_tx_prod = 0; 3268 sc->alc_cdata.alc_tx_cons = 0; 3269 sc->alc_cdata.alc_tx_cnt = 0; 3270 3271 rd = &sc->alc_rdata; 3272 memset(rd->alc_tx_ring, 0, ALC_TX_RING_SZ); 3273 for (i = 0; i < ALC_TX_RING_CNT; i++) { 3274 txd = &sc->alc_cdata.alc_txdesc[i]; 3275 txd->tx_m = NULL; 3276 } 3277 3278 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_tx_ring_map, 0, 3279 sc->alc_cdata.alc_tx_ring_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 3280 } 3281 3282 static int 3283 alc_init_rx_ring(struct alc_softc *sc, bool init) 3284 { 3285 struct alc_ring_data *rd; 3286 struct alc_rxdesc *rxd; 3287 int i; 3288 3289 sc->alc_cdata.alc_rx_cons = ALC_RX_RING_CNT - 1; 3290 rd = &sc->alc_rdata; 3291 memset(rd->alc_rx_ring, 0, ALC_RX_RING_SZ); 3292 for (i = 0; i < ALC_RX_RING_CNT; i++) { 3293 rxd = &sc->alc_cdata.alc_rxdesc[i]; 3294 rxd->rx_m = NULL; 3295 rxd->rx_desc = &rd->alc_rx_ring[i]; 3296 if (alc_newbuf(sc, rxd, init) != 0) 3297 return (ENOBUFS); 3298 } 3299 3300 /* 3301 * Since controller does not update Rx descriptors, driver 3302 * does have to read Rx descriptors back so BUS_DMASYNC_PREWRITE 3303 * is enough to ensure coherence. 3304 */ 3305 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_rx_ring_map, 0, 3306 sc->alc_cdata.alc_rx_ring_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 3307 /* Let controller know availability of new Rx buffers. */ 3308 CSR_WRITE_4(sc, ALC_MBOX_RD0_PROD_IDX, sc->alc_cdata.alc_rx_cons); 3309 3310 return (0); 3311 } 3312 3313 static void 3314 alc_init_rr_ring(struct alc_softc *sc) 3315 { 3316 struct alc_ring_data *rd; 3317 3318 sc->alc_cdata.alc_rr_cons = 0; 3319 ALC_RXCHAIN_RESET(sc); 3320 3321 rd = &sc->alc_rdata; 3322 memset(rd->alc_rr_ring, 0, ALC_RR_RING_SZ); 3323 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_rr_ring_map, 0, 3324 sc->alc_cdata.alc_rr_ring_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 3325 } 3326 3327 static void 3328 alc_init_cmb(struct alc_softc *sc) 3329 { 3330 struct alc_ring_data *rd; 3331 3332 rd = &sc->alc_rdata; 3333 memset(rd->alc_cmb, 0, ALC_CMB_SZ); 3334 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_cmb_map, 0, 3335 sc->alc_cdata.alc_cmb_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 3336 } 3337 3338 static void 3339 alc_init_smb(struct alc_softc *sc) 3340 { 3341 struct alc_ring_data *rd; 3342 3343 rd = &sc->alc_rdata; 3344 memset(rd->alc_smb, 0, ALC_SMB_SZ); 3345 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_smb_map, 0, 3346 sc->alc_cdata.alc_smb_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 3347 } 3348 3349 static void 3350 alc_rxvlan(struct alc_softc *sc) 3351 { 3352 uint32_t reg; 3353 3354 reg = CSR_READ_4(sc, ALC_MAC_CFG); 3355 if (sc->sc_ec.ec_capenable & ETHERCAP_VLAN_HWTAGGING) 3356 reg |= MAC_CFG_VLAN_TAG_STRIP; 3357 else 3358 reg &= ~MAC_CFG_VLAN_TAG_STRIP; 3359 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 3360 } 3361 3362 static void 3363 alc_iff(struct alc_softc *sc) 3364 { 3365 struct ethercom *ec = &sc->sc_ec; 3366 struct ifnet *ifp = &ec->ec_if; 3367 struct ether_multi *enm; 3368 struct ether_multistep step; 3369 uint32_t crc; 3370 uint32_t mchash[2]; 3371 uint32_t rxcfg; 3372 3373 rxcfg = CSR_READ_4(sc, ALC_MAC_CFG); 3374 rxcfg &= ~(MAC_CFG_ALLMULTI | MAC_CFG_BCAST | MAC_CFG_PROMISC); 3375 ifp->if_flags &= ~IFF_ALLMULTI; 3376 3377 /* 3378 * Always accept broadcast frames. 3379 */ 3380 rxcfg |= MAC_CFG_BCAST; 3381 3382 if (ifp->if_flags & IFF_PROMISC || ec->ec_multicnt > 0) { 3383 ifp->if_flags |= IFF_ALLMULTI; 3384 if (ifp->if_flags & IFF_PROMISC) 3385 rxcfg |= MAC_CFG_PROMISC; 3386 else 3387 rxcfg |= MAC_CFG_ALLMULTI; 3388 mchash[0] = mchash[1] = 0xFFFFFFFF; 3389 } else { 3390 /* Program new filter. */ 3391 memset(mchash, 0, sizeof(mchash)); 3392 3393 ETHER_FIRST_MULTI(step, ec, enm); 3394 while (enm != NULL) { 3395 crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 3396 mchash[crc >> 31] |= 1 << ((crc >> 26) & 0x1f); 3397 ETHER_NEXT_MULTI(step, enm); 3398 } 3399 } 3400 3401 CSR_WRITE_4(sc, ALC_MAR0, mchash[0]); 3402 CSR_WRITE_4(sc, ALC_MAR1, mchash[1]); 3403 CSR_WRITE_4(sc, ALC_MAC_CFG, rxcfg); 3404 } 3405 3406 MODULE(MODULE_CLASS_DRIVER, if_alc, "pci"); 3407 3408 #ifdef _MODULE 3409 #include "ioconf.c" 3410 #endif 3411 3412 static int 3413 if_alc_modcmd(modcmd_t cmd, void *opaque) 3414 { 3415 int error = 0; 3416 3417 switch (cmd) { 3418 case MODULE_CMD_INIT: 3419 #ifdef _MODULE 3420 error = config_init_component(cfdriver_ioconf_if_alc, 3421 cfattach_ioconf_if_alc, cfdata_ioconf_if_alc); 3422 #endif 3423 return error; 3424 case MODULE_CMD_FINI: 3425 #ifdef _MODULE 3426 error = config_fini_component(cfdriver_ioconf_if_alc, 3427 cfattach_ioconf_if_alc, cfdata_ioconf_if_alc); 3428 #endif 3429 return error; 3430 default: 3431 return ENOTTY; 3432 } 3433 } 3434
Indexes created Fri Sep 26 08:10:20 GMT 2025