if_alc.c revision 1.15
1 /* $OpenBSD: if_alc.c,v 1.1 2009/08/08 09:31:13 kevlo Exp $ */ 2 /*- 3 * Copyright (c) 2009, Pyun YongHyeon <yongari (at) FreeBSD.org> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice unmodified, this list of conditions, and the following 11 * disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 /* Driver for Atheros AR813x/AR815x PCIe Ethernet. */ 30 31 #ifdef _KERNEL_OPT 32 #include "vlan.h" 33 #endif 34 35 #include <sys/param.h> 36 #include <sys/proc.h> 37 #include <sys/endian.h> 38 #include <sys/systm.h> 39 #include <sys/types.h> 40 #include <sys/sockio.h> 41 #include <sys/mbuf.h> 42 #include <sys/queue.h> 43 #include <sys/kernel.h> 44 #include <sys/device.h> 45 #include <sys/callout.h> 46 #include <sys/socket.h> 47 #include <sys/module.h> 48 49 #include <sys/bus.h> 50 51 #include <net/if.h> 52 #include <net/if_dl.h> 53 #include <net/if_llc.h> 54 #include <net/if_media.h> 55 #include <net/if_ether.h> 56 57 #include <net/bpf.h> 58 59 #ifdef INET 60 #include <netinet/in.h> 61 #include <netinet/in_systm.h> 62 #include <netinet/in_var.h> 63 #include <netinet/ip.h> 64 #endif 65 66 #include <net/if_types.h> 67 #include <net/if_vlanvar.h> 68 69 #include <net/bpf.h> 70 71 #include <dev/mii/mii.h> 72 #include <dev/mii/miivar.h> 73 74 #include <dev/pci/pcireg.h> 75 #include <dev/pci/pcivar.h> 76 #include <dev/pci/pcidevs.h> 77 78 #include <dev/pci/if_alcreg.h> 79 80 /* 81 * Devices supported by this driver. 82 */ 83 static struct alc_ident alc_ident_table[] = { 84 { PCI_VENDOR_ATTANSIC, PCI_PRODUCT_ATTANSIC_AR8131, 9 * 1024, 85 "Atheros AR8131 PCIe Gigabit Ethernet" }, 86 { PCI_VENDOR_ATTANSIC, PCI_PRODUCT_ATTANSIC_AR8132, 9 * 1024, 87 "Atheros AR8132 PCIe Fast Ethernet" }, 88 { PCI_VENDOR_ATTANSIC, PCI_PRODUCT_ATTANSIC_AR8151, 6 * 1024, 89 "Atheros AR8151 v1.0 PCIe Gigabit Ethernet" }, 90 { PCI_VENDOR_ATTANSIC, PCI_PRODUCT_ATTANSIC_AR8151_V2, 6 * 1024, 91 "Atheros AR8151 v2.0 PCIe Gigabit Ethernet" }, 92 { PCI_VENDOR_ATTANSIC, PCI_PRODUCT_ATTANSIC_AR8152_B, 6 * 1024, 93 "Atheros AR8152 v1.1 PCIe Fast Ethernet" }, 94 { PCI_VENDOR_ATTANSIC, PCI_PRODUCT_ATTANSIC_AR8152_B2, 6 * 1024, 95 "Atheros AR8152 v2.0 PCIe Fast Ethernet" }, 96 { PCI_VENDOR_ATTANSIC, PCI_PRODUCT_ATTANSIC_AR8161, 9 * 1024, 97 "Atheros AR8161 PCIe Gigabit Ethernet" }, 98 { PCI_VENDOR_ATTANSIC, PCI_PRODUCT_ATTANSIC_AR8162, 9 * 1024, 99 "Atheros AR8162 PCIe Fast Ethernet" }, 100 { PCI_VENDOR_ATTANSIC, PCI_PRODUCT_ATTANSIC_AR8171, 9 * 1024, 101 "Atheros AR8171 PCIe Gigabit Ethernet" }, 102 { PCI_VENDOR_ATTANSIC, PCI_PRODUCT_ATTANSIC_AR8172, 9 * 1024, 103 "Atheros AR8172 PCIe Fast Ethernet" }, 104 { PCI_VENDOR_ATTANSIC, PCI_PRODUCT_ATTANSIC_E2200, 9 * 1024, 105 "Killer E2200 Gigabit Ethernet" }, 106 { 0, 0, 0, NULL }, 107 }; 108 109 static int alc_match(device_t, cfdata_t, void *); 110 static void alc_attach(device_t, device_t, void *); 111 static int alc_detach(device_t, int); 112 113 static int alc_init(struct ifnet *); 114 static int alc_init_backend(struct ifnet *, bool); 115 static void alc_start(struct ifnet *); 116 static int alc_ioctl(struct ifnet *, u_long, void *); 117 static void alc_watchdog(struct ifnet *); 118 static int alc_mediachange(struct ifnet *); 119 static void alc_mediastatus(struct ifnet *, struct ifmediareq *); 120 121 static void alc_aspm(struct alc_softc *, int, int); 122 static void alc_aspm_813x(struct alc_softc *, int); 123 static void alc_aspm_816x(struct alc_softc *, int); 124 static void alc_disable_l0s_l1(struct alc_softc *); 125 static int alc_dma_alloc(struct alc_softc *); 126 static void alc_dma_free(struct alc_softc *); 127 static void alc_dsp_fixup(struct alc_softc *, int); 128 static int alc_encap(struct alc_softc *, struct mbuf **); 129 static struct alc_ident * 130 alc_find_ident(struct pci_attach_args *); 131 static void alc_get_macaddr(struct alc_softc *); 132 static void alc_get_macaddr_813x(struct alc_softc *); 133 static void alc_get_macaddr_816x(struct alc_softc *); 134 static void alc_get_macaddr_par(struct alc_softc *); 135 static void alc_init_cmb(struct alc_softc *); 136 static void alc_init_rr_ring(struct alc_softc *); 137 static int alc_init_rx_ring(struct alc_softc *, bool); 138 static void alc_init_smb(struct alc_softc *); 139 static void alc_init_tx_ring(struct alc_softc *); 140 static int alc_intr(void *); 141 static void alc_mac_config(struct alc_softc *); 142 static uint32_t alc_mii_readreg_813x(struct alc_softc *, int, int); 143 static uint32_t alc_mii_readreg_816x(struct alc_softc *, int, int); 144 static void alc_mii_writereg_813x(struct alc_softc *, int, int, int); 145 static void alc_mii_writereg_816x(struct alc_softc *, int, int, int); 146 static int alc_miibus_readreg(device_t, int, int); 147 static void alc_miibus_statchg(struct ifnet *); 148 static void alc_miibus_writereg(device_t, int, int, int); 149 static uint32_t alc_miidbg_readreg(struct alc_softc *, int); 150 static void alc_miidbg_writereg(struct alc_softc *, int, int); 151 static uint32_t alc_miiext_readreg(struct alc_softc *, int, int); 152 static uint32_t alc_miiext_writereg(struct alc_softc *, int, int, int); 153 static int alc_newbuf(struct alc_softc *, struct alc_rxdesc *, bool); 154 static void alc_phy_down(struct alc_softc *); 155 static void alc_phy_reset(struct alc_softc *); 156 static void alc_phy_reset_813x(struct alc_softc *); 157 static void alc_phy_reset_816x(struct alc_softc *); 158 static void alc_reset(struct alc_softc *); 159 static void alc_rxeof(struct alc_softc *, struct rx_rdesc *); 160 static int alc_rxintr(struct alc_softc *); 161 static void alc_iff(struct alc_softc *); 162 static void alc_rxvlan(struct alc_softc *); 163 static void alc_start_queue(struct alc_softc *); 164 static void alc_stats_clear(struct alc_softc *); 165 static void alc_stats_update(struct alc_softc *); 166 static void alc_stop(struct ifnet *, int); 167 static void alc_stop_mac(struct alc_softc *); 168 static void alc_stop_queue(struct alc_softc *); 169 static void alc_tick(void *); 170 static void alc_txeof(struct alc_softc *); 171 172 uint32_t alc_dma_burst[] = { 128, 256, 512, 1024, 2048, 4096, 0 }; 173 174 CFATTACH_DECL_NEW(alc, sizeof(struct alc_softc), 175 alc_match, alc_attach, alc_detach, NULL); 176 177 int alcdebug = 0; 178 #define DPRINTF(x) do { if (alcdebug) printf x; } while (0) 179 180 #define ETHER_ALIGN 2 181 #define ALC_CSUM_FEATURES (M_CSUM_TCPv4 | M_CSUM_UDPv4) 182 183 static int 184 alc_miibus_readreg(device_t dev, int phy, int reg) 185 { 186 struct alc_softc *sc = device_private(dev); 187 int v; 188 189 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 190 v = alc_mii_readreg_816x(sc, phy, reg); 191 else 192 v = alc_mii_readreg_813x(sc, phy, reg); 193 return (v); 194 } 195 196 static uint32_t 197 alc_mii_readreg_813x(struct alc_softc *sc, int phy, int reg) 198 { 199 uint32_t v; 200 int i; 201 202 if (phy != sc->alc_phyaddr) 203 return (0); 204 205 /* 206 * For AR8132 fast ethernet controller, do not report 1000baseT 207 * capability to mii(4). Even though AR8132 uses the same 208 * model/revision number of F1 gigabit PHY, the PHY has no 209 * ability to establish 1000baseT link. 210 */ 211 if ((sc->alc_flags & ALC_FLAG_FASTETHER) != 0 && 212 reg == MII_EXTSR) 213 return 0; 214 215 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ | 216 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); 217 for (i = ALC_PHY_TIMEOUT; i > 0; i--) { 218 DELAY(5); 219 v = CSR_READ_4(sc, ALC_MDIO); 220 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) 221 break; 222 } 223 224 if (i == 0) { 225 printf("%s: phy read timeout: phy %d, reg %d\n", 226 device_xname(sc->sc_dev), phy, reg); 227 return (0); 228 } 229 230 return ((v & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT); 231 } 232 233 static uint32_t 234 alc_mii_readreg_816x(struct alc_softc *sc, int phy, int reg) 235 { 236 uint32_t clk, v; 237 int i; 238 239 if (phy != sc->alc_phyaddr) 240 return (0); 241 242 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) 243 clk = MDIO_CLK_25_128; 244 else 245 clk = MDIO_CLK_25_4; 246 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ | 247 MDIO_SUP_PREAMBLE | clk | MDIO_REG_ADDR(reg)); 248 for (i = ALC_PHY_TIMEOUT; i > 0; i--) { 249 DELAY(5); 250 v = CSR_READ_4(sc, ALC_MDIO); 251 if ((v & MDIO_OP_BUSY) == 0) 252 break; 253 } 254 255 if (i == 0) { 256 printf("%s: phy read timeout: phy %d, reg %d\n", 257 device_xname(sc->sc_dev), phy, reg); 258 return (0); 259 } 260 261 return ((v & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT); 262 } 263 264 static void 265 alc_miibus_writereg(device_t dev, int phy, int reg, int val) 266 { 267 struct alc_softc *sc = device_private(dev); 268 269 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 270 alc_mii_writereg_816x(sc, phy, reg, val); 271 else 272 alc_mii_writereg_813x(sc, phy, reg, val); 273 274 return; 275 } 276 277 static void 278 alc_mii_writereg_813x(struct alc_softc *sc, int phy, int reg, int val) 279 { 280 uint32_t v; 281 int i; 282 283 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE | 284 (val & MDIO_DATA_MASK) << MDIO_DATA_SHIFT | 285 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); 286 for (i = ALC_PHY_TIMEOUT; i > 0; i--) { 287 DELAY(5); 288 v = CSR_READ_4(sc, ALC_MDIO); 289 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) 290 break; 291 } 292 293 if (i == 0) 294 printf("%s: phy write timeout: phy %d, reg %d\n", 295 device_xname(sc->sc_dev), phy, reg); 296 297 return; 298 } 299 300 static void 301 alc_mii_writereg_816x(struct alc_softc *sc, int phy, int reg, int val) 302 { 303 uint32_t clk, v; 304 int i; 305 306 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) 307 clk = MDIO_CLK_25_128; 308 else 309 clk = MDIO_CLK_25_4; 310 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE | 311 ((val & MDIO_DATA_MASK) << MDIO_DATA_SHIFT) | MDIO_REG_ADDR(reg) | 312 MDIO_SUP_PREAMBLE | clk); 313 for (i = ALC_PHY_TIMEOUT; i > 0; i--) { 314 DELAY(5); 315 v = CSR_READ_4(sc, ALC_MDIO); 316 if ((v & MDIO_OP_BUSY) == 0) 317 break; 318 } 319 320 if (i == 0) 321 printf("%s: phy write timeout: phy %d, reg %d\n", 322 device_xname(sc->sc_dev), phy, reg); 323 324 return; 325 } 326 327 static void 328 alc_miibus_statchg(struct ifnet *ifp) 329 { 330 struct alc_softc *sc = ifp->if_softc; 331 struct mii_data *mii = &sc->sc_miibus; 332 uint32_t reg; 333 334 if ((ifp->if_flags & IFF_RUNNING) == 0) 335 return; 336 337 sc->alc_flags &= ~ALC_FLAG_LINK; 338 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 339 (IFM_ACTIVE | IFM_AVALID)) { 340 switch (IFM_SUBTYPE(mii->mii_media_active)) { 341 case IFM_10_T: 342 case IFM_100_TX: 343 sc->alc_flags |= ALC_FLAG_LINK; 344 break; 345 case IFM_1000_T: 346 if ((sc->alc_flags & ALC_FLAG_FASTETHER) == 0) 347 sc->alc_flags |= ALC_FLAG_LINK; 348 break; 349 default: 350 break; 351 } 352 } 353 /* Stop Rx/Tx MACs. */ 354 alc_stop_mac(sc); 355 356 /* Program MACs with resolved speed/duplex/flow-control. */ 357 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) { 358 alc_start_queue(sc); 359 alc_mac_config(sc); 360 /* Re-enable Tx/Rx MACs. */ 361 reg = CSR_READ_4(sc, ALC_MAC_CFG); 362 reg |= MAC_CFG_TX_ENB | MAC_CFG_RX_ENB; 363 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 364 } 365 alc_aspm(sc, 0, IFM_SUBTYPE(mii->mii_media_active)); 366 alc_dsp_fixup(sc, IFM_SUBTYPE(mii->mii_media_active)); 367 } 368 369 static uint32_t 370 alc_miidbg_readreg(struct alc_softc *sc, int reg) 371 { 372 373 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, ALC_MII_DBG_ADDR, 374 reg); 375 return (alc_miibus_readreg(sc->sc_dev, sc->alc_phyaddr, 376 ALC_MII_DBG_DATA)); 377 } 378 379 static void 380 alc_miidbg_writereg(struct alc_softc *sc, int reg, int val) 381 { 382 383 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, ALC_MII_DBG_ADDR, 384 reg); 385 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, ALC_MII_DBG_DATA, val); 386 387 return; 388 } 389 390 static uint32_t 391 alc_miiext_readreg(struct alc_softc *sc, int devaddr, int reg) 392 { 393 uint32_t clk, v; 394 int i; 395 396 CSR_WRITE_4(sc, ALC_EXT_MDIO, EXT_MDIO_REG(reg) | 397 EXT_MDIO_DEVADDR(devaddr)); 398 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) 399 clk = MDIO_CLK_25_128; 400 else 401 clk = MDIO_CLK_25_4; 402 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ | 403 MDIO_SUP_PREAMBLE | clk | MDIO_MODE_EXT); 404 for (i = ALC_PHY_TIMEOUT; i > 0; i--) { 405 DELAY(5); 406 v = CSR_READ_4(sc, ALC_MDIO); 407 if ((v & MDIO_OP_BUSY) == 0) 408 break; 409 } 410 411 if (i == 0) { 412 printf("%s: phy ext read timeout: %d\n", 413 device_xname(sc->sc_dev), reg); 414 return (0); 415 } 416 417 return ((v & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT); 418 } 419 420 static uint32_t 421 alc_miiext_writereg(struct alc_softc *sc, int devaddr, int reg, int val) 422 { 423 uint32_t clk, v; 424 int i; 425 426 CSR_WRITE_4(sc, ALC_EXT_MDIO, EXT_MDIO_REG(reg) | 427 EXT_MDIO_DEVADDR(devaddr)); 428 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) 429 clk = MDIO_CLK_25_128; 430 else 431 clk = MDIO_CLK_25_4; 432 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE | 433 ((val & MDIO_DATA_MASK) << MDIO_DATA_SHIFT) | 434 MDIO_SUP_PREAMBLE | clk | MDIO_MODE_EXT); 435 for (i = ALC_PHY_TIMEOUT; i > 0; i--) { 436 DELAY(5); 437 v = CSR_READ_4(sc, ALC_MDIO); 438 if ((v & MDIO_OP_BUSY) == 0) 439 break; 440 } 441 442 if (i == 0) { 443 printf("%s: phy ext write timeout: reg %d\n", 444 device_xname(sc->sc_dev), reg); 445 return (0); 446 } 447 448 return (0); 449 } 450 451 static void 452 alc_dsp_fixup(struct alc_softc *sc, int media) 453 { 454 uint16_t agc, len, val; 455 456 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 457 return; 458 if (AR816X_REV(sc->alc_rev) >= AR816X_REV_C0) 459 return; 460 461 /* 462 * Vendor PHY magic. 463 * 1000BT/AZ, wrong cable length 464 */ 465 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) { 466 len = alc_miiext_readreg(sc, MII_EXT_PCS, MII_EXT_CLDCTL6); 467 len = (len >> EXT_CLDCTL6_CAB_LEN_SHIFT) & 468 EXT_CLDCTL6_CAB_LEN_MASK; 469 /* XXX: used to be (alc >> shift) & mask which is 0 */ 470 agc = alc_miidbg_readreg(sc, MII_DBG_AGC) & DBG_AGC_2_VGA_MASK; 471 agc >>= DBG_AGC_2_VGA_SHIFT; 472 if ((media == IFM_1000_T && len > EXT_CLDCTL6_CAB_LEN_SHORT1G && 473 agc > DBG_AGC_LONG1G_LIMT) || 474 (media == IFM_100_TX && len > DBG_AGC_LONG100M_LIMT && 475 agc > DBG_AGC_LONG1G_LIMT)) { 476 alc_miidbg_writereg(sc, MII_DBG_AZ_ANADECT, 477 DBG_AZ_ANADECT_LONG); 478 val = alc_miiext_readreg(sc, MII_EXT_ANEG, 479 MII_EXT_ANEG_AFE); 480 val |= ANEG_AFEE_10BT_100M_TH; 481 alc_miiext_writereg(sc, MII_EXT_ANEG, MII_EXT_ANEG_AFE, 482 val); 483 } else { 484 alc_miidbg_writereg(sc, MII_DBG_AZ_ANADECT, 485 DBG_AZ_ANADECT_DEFAULT); 486 val = alc_miiext_readreg(sc, MII_EXT_ANEG, 487 MII_EXT_ANEG_AFE); 488 val &= ~ANEG_AFEE_10BT_100M_TH; 489 alc_miiext_writereg(sc, MII_EXT_ANEG, MII_EXT_ANEG_AFE, 490 val); 491 } 492 if ((sc->alc_flags & ALC_FLAG_LINK_WAR) != 0 && 493 AR816X_REV(sc->alc_rev) == AR816X_REV_B0) { 494 if (media == IFM_1000_T) { 495 /* 496 * Giga link threshold, raise the tolerance of 497 * noise 50%. 498 */ 499 val = alc_miidbg_readreg(sc, MII_DBG_MSE20DB); 500 val &= ~DBG_MSE20DB_TH_MASK; 501 val |= (DBG_MSE20DB_TH_HI << 502 DBG_MSE20DB_TH_SHIFT); 503 alc_miidbg_writereg(sc, MII_DBG_MSE20DB, val); 504 } else if (media == IFM_100_TX) 505 alc_miidbg_writereg(sc, MII_DBG_MSE16DB, 506 DBG_MSE16DB_UP); 507 } 508 } else { 509 val = alc_miiext_readreg(sc, MII_EXT_ANEG, MII_EXT_ANEG_AFE); 510 val &= ~ANEG_AFEE_10BT_100M_TH; 511 alc_miiext_writereg(sc, MII_EXT_ANEG, MII_EXT_ANEG_AFE, val); 512 if ((sc->alc_flags & ALC_FLAG_LINK_WAR) != 0 && 513 AR816X_REV(sc->alc_rev) == AR816X_REV_B0) { 514 alc_miidbg_writereg(sc, MII_DBG_MSE16DB, 515 DBG_MSE16DB_DOWN); 516 val = alc_miidbg_readreg(sc, MII_DBG_MSE20DB); 517 val &= ~DBG_MSE20DB_TH_MASK; 518 val |= (DBG_MSE20DB_TH_DEFAULT << DBG_MSE20DB_TH_SHIFT); 519 alc_miidbg_writereg(sc, MII_DBG_MSE20DB, val); 520 } 521 } 522 } 523 524 static void 525 alc_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 526 { 527 struct alc_softc *sc = ifp->if_softc; 528 struct mii_data *mii = &sc->sc_miibus; 529 530 if ((ifp->if_flags & IFF_UP) == 0) 531 return; 532 533 mii_pollstat(mii); 534 ifmr->ifm_status = mii->mii_media_status; 535 ifmr->ifm_active = mii->mii_media_active; 536 } 537 538 static int 539 alc_mediachange(struct ifnet *ifp) 540 { 541 struct alc_softc *sc = ifp->if_softc; 542 struct mii_data *mii = &sc->sc_miibus; 543 int error; 544 545 if (mii->mii_instance != 0) { 546 struct mii_softc *miisc; 547 548 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 549 mii_phy_reset(miisc); 550 } 551 error = mii_mediachg(mii); 552 553 return (error); 554 } 555 556 static struct alc_ident * 557 alc_find_ident(struct pci_attach_args *pa) 558 { 559 struct alc_ident *ident; 560 uint16_t vendor, devid; 561 562 vendor = PCI_VENDOR(pa->pa_id); 563 devid = PCI_PRODUCT(pa->pa_id); 564 for (ident = alc_ident_table; ident->name != NULL; ident++) { 565 if (vendor == ident->vendorid && devid == ident->deviceid) 566 return (ident); 567 } 568 569 return (NULL); 570 } 571 572 static int 573 alc_match(device_t dev, cfdata_t match, void *aux) 574 { 575 struct pci_attach_args *pa = aux; 576 577 return alc_find_ident(pa) != NULL; 578 } 579 580 static void 581 alc_get_macaddr(struct alc_softc *sc) 582 { 583 584 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 585 alc_get_macaddr_816x(sc); 586 else 587 alc_get_macaddr_813x(sc); 588 } 589 590 static void 591 alc_get_macaddr_813x(struct alc_softc *sc) 592 { 593 uint32_t opt; 594 uint16_t val; 595 int eeprom, i; 596 597 eeprom = 0; 598 opt = CSR_READ_4(sc, ALC_OPT_CFG); 599 if ((CSR_READ_4(sc, ALC_MASTER_CFG) & MASTER_OTP_SEL) != 0 && 600 (CSR_READ_4(sc, ALC_TWSI_DEBUG) & TWSI_DEBUG_DEV_EXIST) != 0) { 601 /* 602 * EEPROM found, let TWSI reload EEPROM configuration. 603 * This will set ethernet address of controller. 604 */ 605 eeprom++; 606 switch (sc->alc_ident->deviceid) { 607 case PCI_PRODUCT_ATTANSIC_AR8131: 608 case PCI_PRODUCT_ATTANSIC_AR8132: 609 if ((opt & OPT_CFG_CLK_ENB) == 0) { 610 opt |= OPT_CFG_CLK_ENB; 611 CSR_WRITE_4(sc, ALC_OPT_CFG, opt); 612 CSR_READ_4(sc, ALC_OPT_CFG); 613 DELAY(1000); 614 } 615 break; 616 case PCI_PRODUCT_ATTANSIC_AR8151: 617 case PCI_PRODUCT_ATTANSIC_AR8151_V2: 618 case PCI_PRODUCT_ATTANSIC_AR8152_B: 619 case PCI_PRODUCT_ATTANSIC_AR8152_B2: 620 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 621 ALC_MII_DBG_ADDR, 0x00); 622 val = alc_miibus_readreg(sc->sc_dev, sc->alc_phyaddr, 623 ALC_MII_DBG_DATA); 624 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 625 ALC_MII_DBG_DATA, val & 0xFF7F); 626 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 627 ALC_MII_DBG_ADDR, 0x3B); 628 val = alc_miibus_readreg(sc->sc_dev, sc->alc_phyaddr, 629 ALC_MII_DBG_DATA); 630 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 631 ALC_MII_DBG_DATA, val | 0x0008); 632 DELAY(20); 633 break; 634 } 635 636 CSR_WRITE_4(sc, ALC_LTSSM_ID_CFG, 637 CSR_READ_4(sc, ALC_LTSSM_ID_CFG) & ~LTSSM_ID_WRO_ENB); 638 CSR_WRITE_4(sc, ALC_WOL_CFG, 0); 639 CSR_READ_4(sc, ALC_WOL_CFG); 640 641 CSR_WRITE_4(sc, ALC_TWSI_CFG, CSR_READ_4(sc, ALC_TWSI_CFG) | 642 TWSI_CFG_SW_LD_START); 643 for (i = 100; i > 0; i--) { 644 DELAY(1000); 645 if ((CSR_READ_4(sc, ALC_TWSI_CFG) & 646 TWSI_CFG_SW_LD_START) == 0) 647 break; 648 } 649 if (i == 0) 650 printf("%s: reloading EEPROM timeout!\n", 651 device_xname(sc->sc_dev)); 652 } else { 653 if (alcdebug) 654 printf("%s: EEPROM not found!\n", device_xname(sc->sc_dev)); 655 } 656 if (eeprom != 0) { 657 switch (sc->alc_ident->deviceid) { 658 case PCI_PRODUCT_ATTANSIC_AR8131: 659 case PCI_PRODUCT_ATTANSIC_AR8132: 660 if ((opt & OPT_CFG_CLK_ENB) != 0) { 661 opt &= ~OPT_CFG_CLK_ENB; 662 CSR_WRITE_4(sc, ALC_OPT_CFG, opt); 663 CSR_READ_4(sc, ALC_OPT_CFG); 664 DELAY(1000); 665 } 666 break; 667 case PCI_PRODUCT_ATTANSIC_AR8151: 668 case PCI_PRODUCT_ATTANSIC_AR8151_V2: 669 case PCI_PRODUCT_ATTANSIC_AR8152_B: 670 case PCI_PRODUCT_ATTANSIC_AR8152_B2: 671 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 672 ALC_MII_DBG_ADDR, 0x00); 673 val = alc_miibus_readreg(sc->sc_dev, sc->alc_phyaddr, 674 ALC_MII_DBG_DATA); 675 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 676 ALC_MII_DBG_DATA, val | 0x0080); 677 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 678 ALC_MII_DBG_ADDR, 0x3B); 679 val = alc_miibus_readreg(sc->sc_dev, sc->alc_phyaddr, 680 ALC_MII_DBG_DATA); 681 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 682 ALC_MII_DBG_DATA, val & 0xFFF7); 683 DELAY(20); 684 break; 685 } 686 } 687 688 alc_get_macaddr_par(sc); 689 } 690 691 static void 692 alc_get_macaddr_816x(struct alc_softc *sc) 693 { 694 uint32_t reg; 695 int i, reloaded; 696 697 reloaded = 0; 698 /* Try to reload station address via TWSI. */ 699 for (i = 100; i > 0; i--) { 700 reg = CSR_READ_4(sc, ALC_SLD); 701 if ((reg & (SLD_PROGRESS | SLD_START)) == 0) 702 break; 703 DELAY(1000); 704 } 705 if (i != 0) { 706 CSR_WRITE_4(sc, ALC_SLD, reg | SLD_START); 707 for (i = 100; i > 0; i--) { 708 DELAY(1000); 709 reg = CSR_READ_4(sc, ALC_SLD); 710 if ((reg & SLD_START) == 0) 711 break; 712 } 713 if (i != 0) 714 reloaded++; 715 else if (alcdebug) 716 printf("%s: reloading station address via TWSI timed out!\n", 717 device_xname(sc->sc_dev)); 718 } 719 720 /* Try to reload station address from EEPROM or FLASH. */ 721 if (reloaded == 0) { 722 reg = CSR_READ_4(sc, ALC_EEPROM_LD); 723 if ((reg & (EEPROM_LD_EEPROM_EXIST | 724 EEPROM_LD_FLASH_EXIST)) != 0) { 725 for (i = 100; i > 0; i--) { 726 reg = CSR_READ_4(sc, ALC_EEPROM_LD); 727 if ((reg & (EEPROM_LD_PROGRESS | 728 EEPROM_LD_START)) == 0) 729 break; 730 DELAY(1000); 731 } 732 if (i != 0) { 733 CSR_WRITE_4(sc, ALC_EEPROM_LD, reg | 734 EEPROM_LD_START); 735 for (i = 100; i > 0; i--) { 736 DELAY(1000); 737 reg = CSR_READ_4(sc, ALC_EEPROM_LD); 738 if ((reg & EEPROM_LD_START) == 0) 739 break; 740 } 741 } else if (alcdebug) 742 printf("%s: reloading EEPROM/FLASH timed out!\n", 743 device_xname(sc->sc_dev)); 744 } 745 } 746 747 alc_get_macaddr_par(sc); 748 } 749 750 751 static void 752 alc_get_macaddr_par(struct alc_softc *sc) 753 { 754 uint32_t ea[2]; 755 756 ea[0] = CSR_READ_4(sc, ALC_PAR0); 757 ea[1] = CSR_READ_4(sc, ALC_PAR1); 758 sc->alc_eaddr[0] = (ea[1] >> 8) & 0xFF; 759 sc->alc_eaddr[1] = (ea[1] >> 0) & 0xFF; 760 sc->alc_eaddr[2] = (ea[0] >> 24) & 0xFF; 761 sc->alc_eaddr[3] = (ea[0] >> 16) & 0xFF; 762 sc->alc_eaddr[4] = (ea[0] >> 8) & 0xFF; 763 sc->alc_eaddr[5] = (ea[0] >> 0) & 0xFF; 764 } 765 766 static void 767 alc_disable_l0s_l1(struct alc_softc *sc) 768 { 769 uint32_t pmcfg; 770 771 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 772 /* Another magic from vendor. */ 773 pmcfg = CSR_READ_4(sc, ALC_PM_CFG); 774 pmcfg &= ~(PM_CFG_L1_ENTRY_TIMER_MASK | PM_CFG_CLK_SWH_L1 | 775 PM_CFG_ASPM_L0S_ENB | PM_CFG_ASPM_L1_ENB | 776 PM_CFG_MAC_ASPM_CHK | PM_CFG_SERDES_PD_EX_L1); 777 pmcfg |= PM_CFG_SERDES_BUDS_RX_L1_ENB | 778 PM_CFG_SERDES_PLL_L1_ENB | PM_CFG_SERDES_L1_ENB; 779 CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg); 780 } 781 } 782 783 static void 784 alc_phy_reset(struct alc_softc *sc) 785 { 786 787 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 788 alc_phy_reset_816x(sc); 789 else 790 alc_phy_reset_813x(sc); 791 } 792 793 static void 794 alc_phy_reset_813x(struct alc_softc *sc) 795 { 796 uint16_t data; 797 798 /* Reset magic from Linux. */ 799 CSR_WRITE_2(sc, ALC_GPHY_CFG, GPHY_CFG_SEL_ANA_RESET); 800 CSR_READ_2(sc, ALC_GPHY_CFG); 801 DELAY(10 * 1000); 802 803 CSR_WRITE_2(sc, ALC_GPHY_CFG, GPHY_CFG_EXT_RESET | 804 GPHY_CFG_SEL_ANA_RESET); 805 CSR_READ_2(sc, ALC_GPHY_CFG); 806 DELAY(10 * 1000); 807 808 /* DSP fixup, Vendor magic. */ 809 if (sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8152_B) { 810 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 811 ALC_MII_DBG_ADDR, 0x000A); 812 data = alc_miibus_readreg(sc->sc_dev, sc->alc_phyaddr, 813 ALC_MII_DBG_DATA); 814 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 815 ALC_MII_DBG_DATA, data & 0xDFFF); 816 } 817 if (sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8151 || 818 sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8151_V2 || 819 sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8152_B || 820 sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8152_B2) { 821 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 822 ALC_MII_DBG_ADDR, 0x003B); 823 data = alc_miibus_readreg(sc->sc_dev, sc->alc_phyaddr, 824 ALC_MII_DBG_DATA); 825 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 826 ALC_MII_DBG_DATA, data & 0xFFF7); 827 DELAY(20 * 1000); 828 } 829 if (sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8151) { 830 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 831 ALC_MII_DBG_ADDR, 0x0029); 832 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 833 ALC_MII_DBG_DATA, 0x929D); 834 } 835 if (sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8131 || 836 sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8132 || 837 sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8151_V2 || 838 sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8152_B2) { 839 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 840 ALC_MII_DBG_ADDR, 0x0029); 841 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 842 ALC_MII_DBG_DATA, 0xB6DD); 843 } 844 845 /* Load DSP codes, vendor magic. */ 846 data = ANA_LOOP_SEL_10BT | ANA_EN_MASK_TB | ANA_EN_10BT_IDLE | 847 ((1 << ANA_INTERVAL_SEL_TIMER_SHIFT) & ANA_INTERVAL_SEL_TIMER_MASK); 848 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 849 ALC_MII_DBG_ADDR, MII_ANA_CFG18); 850 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 851 ALC_MII_DBG_DATA, data); 852 853 data = ((2 << ANA_SERDES_CDR_BW_SHIFT) & ANA_SERDES_CDR_BW_MASK) | 854 ANA_SERDES_EN_DEEM | ANA_SERDES_SEL_HSP | ANA_SERDES_EN_PLL | 855 ANA_SERDES_EN_LCKDT; 856 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 857 ALC_MII_DBG_ADDR, MII_ANA_CFG5); 858 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 859 ALC_MII_DBG_DATA, data); 860 861 data = ((44 << ANA_LONG_CABLE_TH_100_SHIFT) & 862 ANA_LONG_CABLE_TH_100_MASK) | 863 ((33 << ANA_SHORT_CABLE_TH_100_SHIFT) & 864 ANA_SHORT_CABLE_TH_100_SHIFT) | 865 ANA_BP_BAD_LINK_ACCUM | ANA_BP_SMALL_BW; 866 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 867 ALC_MII_DBG_ADDR, MII_ANA_CFG54); 868 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 869 ALC_MII_DBG_DATA, data); 870 871 data = ((11 << ANA_IECHO_ADJ_3_SHIFT) & ANA_IECHO_ADJ_3_MASK) | 872 ((11 << ANA_IECHO_ADJ_2_SHIFT) & ANA_IECHO_ADJ_2_MASK) | 873 ((8 << ANA_IECHO_ADJ_1_SHIFT) & ANA_IECHO_ADJ_1_MASK) | 874 ((8 << ANA_IECHO_ADJ_0_SHIFT) & ANA_IECHO_ADJ_0_MASK); 875 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 876 ALC_MII_DBG_ADDR, MII_ANA_CFG4); 877 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 878 ALC_MII_DBG_DATA, data); 879 880 data = ((7 & ANA_MANUL_SWICH_ON_SHIFT) & ANA_MANUL_SWICH_ON_MASK) | 881 ANA_RESTART_CAL | ANA_MAN_ENABLE | ANA_SEL_HSP | ANA_EN_HB | 882 ANA_OEN_125M; 883 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 884 ALC_MII_DBG_ADDR, MII_ANA_CFG0); 885 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 886 ALC_MII_DBG_DATA, data); 887 DELAY(1000); 888 889 /* Disable hibernation. */ 890 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, ALC_MII_DBG_ADDR, 891 0x0029); 892 data = alc_miibus_readreg(sc->sc_dev, sc->alc_phyaddr, 893 ALC_MII_DBG_DATA); 894 data &= ~0x8000; 895 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, ALC_MII_DBG_DATA, 896 data); 897 898 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, ALC_MII_DBG_ADDR, 899 0x000B); 900 data = alc_miibus_readreg(sc->sc_dev, sc->alc_phyaddr, 901 ALC_MII_DBG_DATA); 902 data &= ~0x8000; 903 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, ALC_MII_DBG_DATA, 904 data); 905 } 906 907 static void 908 alc_phy_reset_816x(struct alc_softc *sc) 909 { 910 uint32_t val; 911 912 val = CSR_READ_4(sc, ALC_GPHY_CFG); 913 val &= ~(GPHY_CFG_EXT_RESET | GPHY_CFG_LED_MODE | 914 GPHY_CFG_GATE_25M_ENB | GPHY_CFG_PHY_IDDQ | GPHY_CFG_PHY_PLL_ON | 915 GPHY_CFG_PWDOWN_HW | GPHY_CFG_100AB_ENB); 916 val |= GPHY_CFG_SEL_ANA_RESET; 917 #ifdef notyet 918 val |= GPHY_CFG_HIB_PULSE | GPHY_CFG_HIB_EN | GPHY_CFG_SEL_ANA_RESET; 919 #else 920 /* Disable PHY hibernation. */ 921 val &= ~(GPHY_CFG_HIB_PULSE | GPHY_CFG_HIB_EN); 922 #endif 923 CSR_WRITE_4(sc, ALC_GPHY_CFG, val); 924 DELAY(10); 925 CSR_WRITE_4(sc, ALC_GPHY_CFG, val | GPHY_CFG_EXT_RESET); 926 DELAY(800); 927 928 /* Vendor PHY magic. */ 929 #ifdef notyet 930 alc_miidbg_writereg(sc, MII_DBG_LEGCYPS, DBG_LEGCYPS_DEFAULT); 931 alc_miidbg_writereg(sc, MII_DBG_SYSMODCTL, DBG_SYSMODCTL_DEFAULT); 932 alc_miiext_writereg(sc, MII_EXT_PCS, MII_EXT_VDRVBIAS, 933 EXT_VDRVBIAS_DEFAULT); 934 #else 935 /* Disable PHY hibernation. */ 936 alc_miidbg_writereg(sc, MII_DBG_LEGCYPS, 937 DBG_LEGCYPS_DEFAULT & ~DBG_LEGCYPS_ENB); 938 alc_miidbg_writereg(sc, MII_DBG_HIBNEG, 939 DBG_HIBNEG_DEFAULT & ~(DBG_HIBNEG_PSHIB_EN | DBG_HIBNEG_HIB_PULSE)); 940 alc_miidbg_writereg(sc, MII_DBG_GREENCFG, DBG_GREENCFG_DEFAULT); 941 #endif 942 943 /* XXX Disable EEE. */ 944 val = CSR_READ_4(sc, ALC_LPI_CTL); 945 val &= ~LPI_CTL_ENB; 946 CSR_WRITE_4(sc, ALC_LPI_CTL, val); 947 alc_miiext_writereg(sc, MII_EXT_ANEG, MII_EXT_ANEG_LOCAL_EEEADV, 0); 948 949 /* PHY power saving. */ 950 alc_miidbg_writereg(sc, MII_DBG_TST10BTCFG, DBG_TST10BTCFG_DEFAULT); 951 alc_miidbg_writereg(sc, MII_DBG_SRDSYSMOD, DBG_SRDSYSMOD_DEFAULT); 952 alc_miidbg_writereg(sc, MII_DBG_TST100BTCFG, DBG_TST100BTCFG_DEFAULT); 953 alc_miidbg_writereg(sc, MII_DBG_ANACTL, DBG_ANACTL_DEFAULT); 954 val = alc_miidbg_readreg(sc, MII_DBG_GREENCFG2); 955 val &= ~DBG_GREENCFG2_GATE_DFSE_EN; 956 alc_miidbg_writereg(sc, MII_DBG_GREENCFG2, val); 957 958 /* RTL8139C, 120m issue. */ 959 alc_miiext_writereg(sc, MII_EXT_ANEG, MII_EXT_ANEG_NLP78, 960 ANEG_NLP78_120M_DEFAULT); 961 alc_miiext_writereg(sc, MII_EXT_ANEG, MII_EXT_ANEG_S3DIG10, 962 ANEG_S3DIG10_DEFAULT); 963 964 if ((sc->alc_flags & ALC_FLAG_LINK_WAR) != 0) { 965 /* Turn off half amplitude. */ 966 val = alc_miiext_readreg(sc, MII_EXT_PCS, MII_EXT_CLDCTL3); 967 val |= EXT_CLDCTL3_BP_CABLE1TH_DET_GT; 968 alc_miiext_writereg(sc, MII_EXT_PCS, MII_EXT_CLDCTL3, val); 969 /* Turn off Green feature. */ 970 val = alc_miidbg_readreg(sc, MII_DBG_GREENCFG2); 971 val |= DBG_GREENCFG2_BP_GREEN; 972 alc_miidbg_writereg(sc, MII_DBG_GREENCFG2, val); 973 /* Turn off half bias. */ 974 val = alc_miiext_readreg(sc, MII_EXT_PCS, MII_EXT_CLDCTL5); 975 val |= EXT_CLDCTL5_BP_VD_HLFBIAS; 976 alc_miiext_writereg(sc, MII_EXT_PCS, MII_EXT_CLDCTL5, val); 977 } 978 } 979 980 static void 981 alc_phy_down(struct alc_softc *sc) 982 { 983 uint32_t gphy; 984 985 switch (sc->alc_ident->deviceid) { 986 case PCI_PRODUCT_ATTANSIC_AR8161: 987 case PCI_PRODUCT_ATTANSIC_E2200: 988 case PCI_PRODUCT_ATTANSIC_AR8162: 989 case PCI_PRODUCT_ATTANSIC_AR8171: 990 case PCI_PRODUCT_ATTANSIC_AR8172: 991 gphy = CSR_READ_4(sc, ALC_GPHY_CFG); 992 gphy &= ~(GPHY_CFG_EXT_RESET | GPHY_CFG_LED_MODE | 993 GPHY_CFG_100AB_ENB | GPHY_CFG_PHY_PLL_ON); 994 gphy |= GPHY_CFG_HIB_EN | GPHY_CFG_HIB_PULSE | 995 GPHY_CFG_SEL_ANA_RESET; 996 gphy |= GPHY_CFG_PHY_IDDQ | GPHY_CFG_PWDOWN_HW; 997 CSR_WRITE_4(sc, ALC_GPHY_CFG, gphy); 998 break; 999 case PCI_PRODUCT_ATTANSIC_AR8151: 1000 case PCI_PRODUCT_ATTANSIC_AR8151_V2: 1001 case PCI_PRODUCT_ATTANSIC_AR8152_B: 1002 case PCI_PRODUCT_ATTANSIC_AR8152_B2: 1003 /* 1004 * GPHY power down caused more problems on AR8151 v2.0. 1005 * When driver is reloaded after GPHY power down, 1006 * accesses to PHY/MAC registers hung the system. Only 1007 * cold boot recovered from it. I'm not sure whether 1008 * AR8151 v1.0 also requires this one though. I don't 1009 * have AR8151 v1.0 controller in hand. 1010 * The only option left is to isolate the PHY and 1011 * initiates power down the PHY which in turn saves 1012 * more power when driver is unloaded. 1013 */ 1014 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 1015 MII_BMCR, BMCR_ISO | BMCR_PDOWN); 1016 break; 1017 default: 1018 /* Force PHY down. */ 1019 CSR_WRITE_2(sc, ALC_GPHY_CFG, GPHY_CFG_EXT_RESET | 1020 GPHY_CFG_SEL_ANA_RESET | GPHY_CFG_PHY_IDDQ | 1021 GPHY_CFG_PWDOWN_HW); 1022 DELAY(1000); 1023 break; 1024 } 1025 } 1026 1027 static void 1028 alc_aspm(struct alc_softc *sc, int init, int media) 1029 { 1030 1031 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 1032 alc_aspm_816x(sc, init); 1033 else 1034 alc_aspm_813x(sc, media); 1035 } 1036 1037 static void 1038 alc_aspm_813x(struct alc_softc *sc, int media) 1039 { 1040 uint32_t pmcfg; 1041 uint16_t linkcfg; 1042 1043 pmcfg = CSR_READ_4(sc, ALC_PM_CFG); 1044 if ((sc->alc_flags & (ALC_FLAG_APS | ALC_FLAG_PCIE)) == 1045 (ALC_FLAG_APS | ALC_FLAG_PCIE)) 1046 linkcfg = CSR_READ_2(sc, sc->alc_expcap + 1047 PCIE_LCSR); 1048 else 1049 linkcfg = 0; 1050 pmcfg &= ~PM_CFG_SERDES_PD_EX_L1; 1051 pmcfg &= ~(PM_CFG_L1_ENTRY_TIMER_MASK | PM_CFG_LCKDET_TIMER_MASK); 1052 pmcfg |= PM_CFG_MAC_ASPM_CHK; 1053 pmcfg |= (PM_CFG_LCKDET_TIMER_DEFAULT << PM_CFG_LCKDET_TIMER_SHIFT); 1054 pmcfg &= ~(PM_CFG_ASPM_L1_ENB | PM_CFG_ASPM_L0S_ENB); 1055 1056 if ((sc->alc_flags & ALC_FLAG_APS) != 0) { 1057 /* Disable extended sync except AR8152 B v1.0 */ 1058 linkcfg &= ~0x80; 1059 if (sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8152_B && 1060 sc->alc_rev == ATHEROS_AR8152_B_V10) 1061 linkcfg |= 0x80; 1062 CSR_WRITE_2(sc, sc->alc_expcap + PCIE_LCSR, 1063 linkcfg); 1064 pmcfg &= ~(PM_CFG_EN_BUFS_RX_L0S | PM_CFG_SA_DLY_ENB | 1065 PM_CFG_HOTRST); 1066 pmcfg |= (PM_CFG_L1_ENTRY_TIMER_DEFAULT << 1067 PM_CFG_L1_ENTRY_TIMER_SHIFT); 1068 pmcfg &= ~PM_CFG_PM_REQ_TIMER_MASK; 1069 pmcfg |= (PM_CFG_PM_REQ_TIMER_DEFAULT << 1070 PM_CFG_PM_REQ_TIMER_SHIFT); 1071 pmcfg |= PM_CFG_SERDES_PD_EX_L1 | PM_CFG_PCIE_RECV; 1072 } 1073 1074 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) { 1075 if ((sc->alc_flags & ALC_FLAG_L0S) != 0) 1076 pmcfg |= PM_CFG_ASPM_L0S_ENB; 1077 if ((sc->alc_flags & ALC_FLAG_L1S) != 0) 1078 pmcfg |= PM_CFG_ASPM_L1_ENB; 1079 if ((sc->alc_flags & ALC_FLAG_APS) != 0) { 1080 if (sc->alc_ident->deviceid == 1081 PCI_PRODUCT_ATTANSIC_AR8152_B) 1082 pmcfg &= ~PM_CFG_ASPM_L0S_ENB; 1083 pmcfg &= ~(PM_CFG_SERDES_L1_ENB | 1084 PM_CFG_SERDES_PLL_L1_ENB | 1085 PM_CFG_SERDES_BUDS_RX_L1_ENB); 1086 pmcfg |= PM_CFG_CLK_SWH_L1; 1087 if (media == IFM_100_TX || media == IFM_1000_T) { 1088 pmcfg &= ~PM_CFG_L1_ENTRY_TIMER_MASK; 1089 switch (sc->alc_ident->deviceid) { 1090 case PCI_PRODUCT_ATTANSIC_AR8152_B: 1091 pmcfg |= (7 << 1092 PM_CFG_L1_ENTRY_TIMER_SHIFT); 1093 break; 1094 case PCI_PRODUCT_ATTANSIC_AR8152_B2: 1095 case PCI_PRODUCT_ATTANSIC_AR8151_V2: 1096 pmcfg |= (4 << 1097 PM_CFG_L1_ENTRY_TIMER_SHIFT); 1098 break; 1099 default: 1100 pmcfg |= (15 << 1101 PM_CFG_L1_ENTRY_TIMER_SHIFT); 1102 break; 1103 } 1104 } 1105 } else { 1106 pmcfg |= PM_CFG_SERDES_L1_ENB | 1107 PM_CFG_SERDES_PLL_L1_ENB | 1108 PM_CFG_SERDES_BUDS_RX_L1_ENB; 1109 pmcfg &= ~(PM_CFG_CLK_SWH_L1 | 1110 PM_CFG_ASPM_L1_ENB | PM_CFG_ASPM_L0S_ENB); 1111 } 1112 } else { 1113 pmcfg &= ~(PM_CFG_SERDES_BUDS_RX_L1_ENB | PM_CFG_SERDES_L1_ENB | 1114 PM_CFG_SERDES_PLL_L1_ENB); 1115 pmcfg |= PM_CFG_CLK_SWH_L1; 1116 if ((sc->alc_flags & ALC_FLAG_L1S) != 0) 1117 pmcfg |= PM_CFG_ASPM_L1_ENB; 1118 } 1119 CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg); 1120 } 1121 1122 static void 1123 alc_aspm_816x(struct alc_softc *sc, int init) 1124 { 1125 uint32_t pmcfg; 1126 1127 pmcfg = CSR_READ_4(sc, ALC_PM_CFG); 1128 pmcfg &= ~PM_CFG_L1_ENTRY_TIMER_816X_MASK; 1129 pmcfg |= PM_CFG_L1_ENTRY_TIMER_816X_DEFAULT; 1130 pmcfg &= ~PM_CFG_PM_REQ_TIMER_MASK; 1131 pmcfg |= PM_CFG_PM_REQ_TIMER_816X_DEFAULT; 1132 pmcfg &= ~PM_CFG_LCKDET_TIMER_MASK; 1133 pmcfg |= PM_CFG_LCKDET_TIMER_DEFAULT; 1134 pmcfg |= PM_CFG_SERDES_PD_EX_L1 | PM_CFG_CLK_SWH_L1 | PM_CFG_PCIE_RECV; 1135 pmcfg &= ~(PM_CFG_RX_L1_AFTER_L0S | PM_CFG_TX_L1_AFTER_L0S | 1136 PM_CFG_ASPM_L1_ENB | PM_CFG_ASPM_L0S_ENB | 1137 PM_CFG_SERDES_L1_ENB | PM_CFG_SERDES_PLL_L1_ENB | 1138 PM_CFG_SERDES_BUDS_RX_L1_ENB | PM_CFG_SA_DLY_ENB | 1139 PM_CFG_MAC_ASPM_CHK | PM_CFG_HOTRST); 1140 if (AR816X_REV(sc->alc_rev) <= AR816X_REV_A1 && 1141 (sc->alc_rev & 0x01) != 0) 1142 pmcfg |= PM_CFG_SERDES_L1_ENB | PM_CFG_SERDES_PLL_L1_ENB; 1143 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) { 1144 /* Link up, enable both L0s, L1s. */ 1145 pmcfg |= PM_CFG_ASPM_L0S_ENB | PM_CFG_ASPM_L1_ENB | 1146 PM_CFG_MAC_ASPM_CHK; 1147 } else { 1148 if (init != 0) 1149 pmcfg |= PM_CFG_ASPM_L0S_ENB | PM_CFG_ASPM_L1_ENB | 1150 PM_CFG_MAC_ASPM_CHK; 1151 else if ((sc->sc_ec.ec_if.if_flags & IFF_RUNNING) != 0) 1152 pmcfg |= PM_CFG_ASPM_L1_ENB | PM_CFG_MAC_ASPM_CHK; 1153 } 1154 CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg); 1155 } 1156 1157 static void 1158 alc_attach(device_t parent, device_t self, void *aux) 1159 { 1160 1161 struct alc_softc *sc = device_private(self); 1162 struct pci_attach_args *pa = aux; 1163 pci_chipset_tag_t pc = pa->pa_pc; 1164 pci_intr_handle_t ih; 1165 const char *intrstr; 1166 struct ifnet *ifp; 1167 pcireg_t memtype; 1168 const char *aspm_state[] = { "L0s/L1", "L0s", "L1", "L0s/L1" }; 1169 uint16_t burst; 1170 int base, mii_flags, state, error = 0; 1171 uint32_t cap, ctl, val; 1172 char intrbuf[PCI_INTRSTR_LEN]; 1173 1174 sc->alc_ident = alc_find_ident(pa); 1175 1176 aprint_naive("\n"); 1177 aprint_normal(": %s\n", sc->alc_ident->name); 1178 1179 sc->sc_dev = self; 1180 sc->sc_dmat = pa->pa_dmat; 1181 sc->sc_pct = pa->pa_pc; 1182 sc->sc_pcitag = pa->pa_tag; 1183 1184 /* 1185 * Allocate IO memory 1186 */ 1187 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, ALC_PCIR_BAR); 1188 switch (memtype) { 1189 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 1190 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT_1M: 1191 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 1192 break; 1193 default: 1194 aprint_error_dev(self, "invalid base address register\n"); 1195 break; 1196 } 1197 1198 if (pci_mapreg_map(pa, ALC_PCIR_BAR, memtype, 0, &sc->sc_mem_bt, 1199 &sc->sc_mem_bh, NULL, &sc->sc_mem_size)) { 1200 aprint_error_dev(self, "could not map mem space\n"); 1201 return; 1202 } 1203 1204 if (pci_intr_map(pa, &ih) != 0) { 1205 printf(": can't map interrupt\n"); 1206 goto fail; 1207 } 1208 1209 /* 1210 * Allocate IRQ 1211 */ 1212 intrstr = pci_intr_string(sc->sc_pct, ih, intrbuf, sizeof(intrbuf)); 1213 sc->sc_irq_handle = pci_intr_establish(pc, ih, IPL_NET, alc_intr, sc); 1214 if (sc->sc_irq_handle == NULL) { 1215 printf(": could not establish interrupt"); 1216 if (intrstr != NULL) 1217 printf(" at %s", intrstr); 1218 printf("\n"); 1219 goto fail; 1220 } 1221 aprint_normal_dev(self, "interrupting at %s\n", intrstr); 1222 1223 /* Set PHY address. */ 1224 sc->alc_phyaddr = ALC_PHY_ADDR; 1225 1226 /* Initialize DMA parameters. */ 1227 sc->alc_dma_rd_burst = 0; 1228 sc->alc_dma_wr_burst = 0; 1229 sc->alc_rcb = DMA_CFG_RCB_64; 1230 if (pci_get_capability(pc, pa->pa_tag, PCI_CAP_PCIEXPRESS, 1231 &base, NULL)) { 1232 sc->alc_flags |= ALC_FLAG_PCIE; 1233 sc->alc_expcap = base; 1234 burst = pci_conf_read(sc->sc_pct, sc->sc_pcitag, 1235 base + PCIE_DCSR) >> 16; 1236 sc->alc_dma_rd_burst = (burst & 0x7000) >> 12; 1237 sc->alc_dma_wr_burst = (burst & 0x00e0) >> 5; 1238 if (alcdebug) { 1239 printf("%s: Read request size : %u bytes.\n", 1240 device_xname(sc->sc_dev), 1241 alc_dma_burst[sc->alc_dma_rd_burst]); 1242 printf("%s: TLP payload size : %u bytes.\n", 1243 device_xname(sc->sc_dev), 1244 alc_dma_burst[sc->alc_dma_wr_burst]); 1245 } 1246 if (alc_dma_burst[sc->alc_dma_rd_burst] > 1024) 1247 sc->alc_dma_rd_burst = 3; 1248 if (alc_dma_burst[sc->alc_dma_wr_burst] > 1024) 1249 sc->alc_dma_wr_burst = 3; 1250 1251 /* Clear data link and flow-control protocol error. */ 1252 val = CSR_READ_4(sc, ALC_PEX_UNC_ERR_SEV); 1253 val &= ~(PEX_UNC_ERR_SEV_DLP | PEX_UNC_ERR_SEV_FCP); 1254 CSR_WRITE_4(sc, ALC_PEX_UNC_ERR_SEV, val); 1255 1256 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 1257 CSR_WRITE_4(sc, ALC_LTSSM_ID_CFG, 1258 CSR_READ_4(sc, ALC_LTSSM_ID_CFG) & ~LTSSM_ID_WRO_ENB); 1259 CSR_WRITE_4(sc, ALC_PCIE_PHYMISC, 1260 CSR_READ_4(sc, ALC_PCIE_PHYMISC) | 1261 PCIE_PHYMISC_FORCE_RCV_DET); 1262 if (sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8152_B && 1263 sc->alc_rev == ATHEROS_AR8152_B_V10) { 1264 val = CSR_READ_4(sc, ALC_PCIE_PHYMISC2); 1265 val &= ~(PCIE_PHYMISC2_SERDES_CDR_MASK | 1266 PCIE_PHYMISC2_SERDES_TH_MASK); 1267 val |= 3 << PCIE_PHYMISC2_SERDES_CDR_SHIFT; 1268 val |= 3 << PCIE_PHYMISC2_SERDES_TH_SHIFT; 1269 CSR_WRITE_4(sc, ALC_PCIE_PHYMISC2, val); 1270 } 1271 /* Disable ASPM L0S and L1. */ 1272 cap = pci_conf_read(sc->sc_pct, sc->sc_pcitag, 1273 base + PCIE_LCAP) >> 16; 1274 if ((cap & 0x00000c00) != 0) { 1275 ctl = pci_conf_read(sc->sc_pct, sc->sc_pcitag, 1276 base + PCIE_LCSR) >> 16; 1277 if ((ctl & 0x08) != 0) 1278 sc->alc_rcb = DMA_CFG_RCB_128; 1279 if (alcdebug) 1280 printf("%s: RCB %u bytes\n", 1281 device_xname(sc->sc_dev), 1282 sc->alc_rcb == DMA_CFG_RCB_64 ? 64 : 128); 1283 state = ctl & 0x03; 1284 if (state & 0x01) 1285 sc->alc_flags |= ALC_FLAG_L0S; 1286 if (state & 0x02) 1287 sc->alc_flags |= ALC_FLAG_L1S; 1288 if (alcdebug) 1289 printf("%s: ASPM %s %s\n", 1290 device_xname(sc->sc_dev), 1291 aspm_state[state], 1292 state == 0 ? "disabled" : "enabled"); 1293 alc_disable_l0s_l1(sc); 1294 } else { 1295 aprint_debug_dev(sc->sc_dev, "no ASPM support\n"); 1296 } 1297 } else { 1298 val = CSR_READ_4(sc, ALC_PDLL_TRNS1); 1299 val &= ~PDLL_TRNS1_D3PLLOFF_ENB; 1300 CSR_WRITE_4(sc, ALC_PDLL_TRNS1, val); 1301 val = CSR_READ_4(sc, ALC_MASTER_CFG); 1302 if (AR816X_REV(sc->alc_rev) <= AR816X_REV_A1 && 1303 (sc->alc_rev & 0x01) != 0) { 1304 if ((val & MASTER_WAKEN_25M) == 0 || 1305 (val & MASTER_CLK_SEL_DIS) == 0) { 1306 val |= MASTER_WAKEN_25M | MASTER_CLK_SEL_DIS; 1307 CSR_WRITE_4(sc, ALC_MASTER_CFG, val); 1308 } 1309 } else { 1310 if ((val & MASTER_WAKEN_25M) == 0 || 1311 (val & MASTER_CLK_SEL_DIS) != 0) { 1312 val |= MASTER_WAKEN_25M; 1313 val &= ~MASTER_CLK_SEL_DIS; 1314 CSR_WRITE_4(sc, ALC_MASTER_CFG, val); 1315 } 1316 } 1317 } 1318 alc_aspm(sc, 1, IFM_UNKNOWN); 1319 } 1320 1321 /* Reset PHY. */ 1322 alc_phy_reset(sc); 1323 1324 /* Reset the ethernet controller. */ 1325 alc_stop_mac(sc); 1326 alc_reset(sc); 1327 1328 /* 1329 * One odd thing is AR8132 uses the same PHY hardware(F1 1330 * gigabit PHY) of AR8131. So atphy(4) of AR8132 reports 1331 * the PHY supports 1000Mbps but that's not true. The PHY 1332 * used in AR8132 can't establish gigabit link even if it 1333 * shows the same PHY model/revision number of AR8131. 1334 */ 1335 switch (sc->alc_ident->deviceid) { 1336 case PCI_PRODUCT_ATTANSIC_AR8161: 1337 if (PCI_SUBSYS_ID(pci_conf_read( 1338 sc->sc_pct, sc->sc_pcitag, PCI_SUBSYS_ID_REG)) == 0x0091 && 1339 sc->alc_rev == 0) 1340 sc->alc_flags |= ALC_FLAG_LINK_WAR; 1341 /* FALLTHROUGH */ 1342 case PCI_PRODUCT_ATTANSIC_E2200: 1343 case PCI_PRODUCT_ATTANSIC_AR8171: 1344 sc->alc_flags |= ALC_FLAG_AR816X_FAMILY; 1345 break; 1346 case PCI_PRODUCT_ATTANSIC_AR8162: 1347 case PCI_PRODUCT_ATTANSIC_AR8172: 1348 sc->alc_flags |= ALC_FLAG_FASTETHER | ALC_FLAG_AR816X_FAMILY; 1349 break; 1350 case PCI_PRODUCT_ATTANSIC_AR8152_B: 1351 case PCI_PRODUCT_ATTANSIC_AR8152_B2: 1352 sc->alc_flags |= ALC_FLAG_APS; 1353 /* FALLTHROUGH */ 1354 case PCI_PRODUCT_ATTANSIC_AR8132: 1355 sc->alc_flags |= ALC_FLAG_FASTETHER; 1356 break; 1357 case PCI_PRODUCT_ATTANSIC_AR8151: 1358 case PCI_PRODUCT_ATTANSIC_AR8151_V2: 1359 sc->alc_flags |= ALC_FLAG_APS; 1360 /* FALLTHROUGH */ 1361 default: 1362 break; 1363 } 1364 sc->alc_flags |= ALC_FLAG_JUMBO; 1365 1366 /* 1367 * It seems that AR813x/AR815x has silicon bug for SMB. In 1368 * addition, Atheros said that enabling SMB wouldn't improve 1369 * performance. However I think it's bad to access lots of 1370 * registers to extract MAC statistics. 1371 */ 1372 sc->alc_flags |= ALC_FLAG_SMB_BUG; 1373 /* 1374 * Don't use Tx CMB. It is known to have silicon bug. 1375 */ 1376 sc->alc_flags |= ALC_FLAG_CMB_BUG; 1377 sc->alc_rev = PCI_REVISION(pa->pa_class); 1378 sc->alc_chip_rev = CSR_READ_4(sc, ALC_MASTER_CFG) >> 1379 MASTER_CHIP_REV_SHIFT; 1380 if (alcdebug) { 1381 printf("%s: PCI device revision : 0x%04x\n", 1382 device_xname(sc->sc_dev), sc->alc_rev); 1383 printf("%s: Chip id/revision : 0x%04x\n", 1384 device_xname(sc->sc_dev), sc->alc_chip_rev); 1385 printf("%s: %u Tx FIFO, %u Rx FIFO\n", device_xname(sc->sc_dev), 1386 CSR_READ_4(sc, ALC_SRAM_TX_FIFO_LEN) * 8, 1387 CSR_READ_4(sc, ALC_SRAM_RX_FIFO_LEN) * 8); 1388 } 1389 1390 error = alc_dma_alloc(sc); 1391 if (error) 1392 goto fail; 1393 1394 callout_init(&sc->sc_tick_ch, 0); 1395 callout_setfunc(&sc->sc_tick_ch, alc_tick, sc); 1396 1397 /* Load station address. */ 1398 alc_get_macaddr(sc); 1399 1400 aprint_normal_dev(self, "Ethernet address %s\n", 1401 ether_sprintf(sc->alc_eaddr)); 1402 1403 ifp = &sc->sc_ec.ec_if; 1404 ifp->if_softc = sc; 1405 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1406 ifp->if_init = alc_init; 1407 ifp->if_ioctl = alc_ioctl; 1408 ifp->if_start = alc_start; 1409 ifp->if_stop = alc_stop; 1410 ifp->if_watchdog = alc_watchdog; 1411 IFQ_SET_MAXLEN(&ifp->if_snd, ALC_TX_RING_CNT - 1); 1412 IFQ_SET_READY(&ifp->if_snd); 1413 strlcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 1414 1415 sc->sc_ec.ec_capabilities = ETHERCAP_VLAN_MTU; 1416 1417 #ifdef ALC_CHECKSUM 1418 ifp->if_capabilities |= IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 1419 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 1420 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_TCPv4_Rx; 1421 #endif 1422 1423 #if NVLAN > 0 1424 sc->sc_ec.ec_capabilities |= ETHERCAP_VLAN_HWTAGGING; 1425 #endif 1426 1427 /* 1428 * XXX 1429 * It seems enabling Tx checksum offloading makes more trouble. 1430 * Sometimes the controller does not receive any frames when 1431 * Tx checksum offloading is enabled. I'm not sure whether this 1432 * is a bug in Tx checksum offloading logic or I got broken 1433 * sample boards. To safety, don't enable Tx checksum offloading 1434 * by default but give chance to users to toggle it if they know 1435 * their controllers work without problems. 1436 * Fortunately, Tx checksum offloading for AR816x family 1437 * seems to work. 1438 */ 1439 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 1440 ifp->if_capenable &= ~IFCAP_CSUM_IPv4_Tx; 1441 ifp->if_capabilities &= ~ALC_CSUM_FEATURES; 1442 } 1443 1444 /* Set up MII bus. */ 1445 sc->sc_miibus.mii_ifp = ifp; 1446 sc->sc_miibus.mii_readreg = alc_miibus_readreg; 1447 sc->sc_miibus.mii_writereg = alc_miibus_writereg; 1448 sc->sc_miibus.mii_statchg = alc_miibus_statchg; 1449 1450 sc->sc_ec.ec_mii = &sc->sc_miibus; 1451 ifmedia_init(&sc->sc_miibus.mii_media, 0, alc_mediachange, 1452 alc_mediastatus); 1453 mii_flags = 0; 1454 if ((sc->alc_flags & ALC_FLAG_JUMBO) != 0) 1455 mii_flags |= MIIF_DOPAUSE; 1456 mii_attach(self, &sc->sc_miibus, 0xffffffff, MII_PHY_ANY, 1457 MII_OFFSET_ANY, mii_flags); 1458 1459 if (LIST_FIRST(&sc->sc_miibus.mii_phys) == NULL) { 1460 printf("%s: no PHY found!\n", device_xname(sc->sc_dev)); 1461 ifmedia_add(&sc->sc_miibus.mii_media, IFM_ETHER | IFM_MANUAL, 1462 0, NULL); 1463 ifmedia_set(&sc->sc_miibus.mii_media, IFM_ETHER | IFM_MANUAL); 1464 } else 1465 ifmedia_set(&sc->sc_miibus.mii_media, IFM_ETHER | IFM_AUTO); 1466 1467 if_attach(ifp); 1468 ether_ifattach(ifp, sc->alc_eaddr); 1469 1470 if (!pmf_device_register(self, NULL, NULL)) 1471 aprint_error_dev(self, "couldn't establish power handler\n"); 1472 else 1473 pmf_class_network_register(self, ifp); 1474 1475 return; 1476 fail: 1477 alc_dma_free(sc); 1478 if (sc->sc_irq_handle != NULL) { 1479 pci_intr_disestablish(sc->sc_pct, sc->sc_irq_handle); 1480 sc->sc_irq_handle = NULL; 1481 } 1482 if (sc->sc_mem_size) { 1483 bus_space_unmap(sc->sc_mem_bt, sc->sc_mem_bh, sc->sc_mem_size); 1484 sc->sc_mem_size = 0; 1485 } 1486 } 1487 1488 static int 1489 alc_detach(device_t self, int flags) 1490 { 1491 struct alc_softc *sc = device_private(self); 1492 struct ifnet *ifp = &sc->sc_ec.ec_if; 1493 int s; 1494 1495 s = splnet(); 1496 alc_stop(ifp, 0); 1497 splx(s); 1498 1499 mii_detach(&sc->sc_miibus, MII_PHY_ANY, MII_OFFSET_ANY); 1500 1501 /* Delete all remaining media. */ 1502 ifmedia_delete_instance(&sc->sc_miibus.mii_media, IFM_INST_ANY); 1503 1504 ether_ifdetach(ifp); 1505 if_detach(ifp); 1506 alc_dma_free(sc); 1507 1508 alc_phy_down(sc); 1509 if (sc->sc_irq_handle != NULL) { 1510 pci_intr_disestablish(sc->sc_pct, sc->sc_irq_handle); 1511 sc->sc_irq_handle = NULL; 1512 } 1513 if (sc->sc_mem_size) { 1514 bus_space_unmap(sc->sc_mem_bt, sc->sc_mem_bh, sc->sc_mem_size); 1515 sc->sc_mem_size = 0; 1516 } 1517 1518 return (0); 1519 } 1520 1521 static int 1522 alc_dma_alloc(struct alc_softc *sc) 1523 { 1524 struct alc_txdesc *txd; 1525 struct alc_rxdesc *rxd; 1526 int nsegs, error, i; 1527 1528 /* 1529 * Create DMA stuffs for TX ring 1530 */ 1531 error = bus_dmamap_create(sc->sc_dmat, ALC_TX_RING_SZ, 1, 1532 ALC_TX_RING_SZ, 0, BUS_DMA_NOWAIT, &sc->alc_cdata.alc_tx_ring_map); 1533 if (error) { 1534 sc->alc_cdata.alc_tx_ring_map = NULL; 1535 return (ENOBUFS); 1536 } 1537 1538 /* Allocate DMA'able memory for TX ring */ 1539 error = bus_dmamem_alloc(sc->sc_dmat, ALC_TX_RING_SZ, 1540 ETHER_ALIGN, 0, &sc->alc_rdata.alc_tx_ring_seg, 1, 1541 &nsegs, BUS_DMA_NOWAIT); 1542 if (error) { 1543 printf("%s: could not allocate DMA'able memory for Tx ring.\n", 1544 device_xname(sc->sc_dev)); 1545 return error; 1546 } 1547 1548 error = bus_dmamem_map(sc->sc_dmat, &sc->alc_rdata.alc_tx_ring_seg, 1549 nsegs, ALC_TX_RING_SZ, (void **)&sc->alc_rdata.alc_tx_ring, 1550 BUS_DMA_NOWAIT); 1551 if (error) 1552 return (ENOBUFS); 1553 1554 /* Load the DMA map for Tx ring. */ 1555 error = bus_dmamap_load(sc->sc_dmat, sc->alc_cdata.alc_tx_ring_map, 1556 sc->alc_rdata.alc_tx_ring, ALC_TX_RING_SZ, NULL, BUS_DMA_WAITOK); 1557 if (error) { 1558 printf("%s: could not load DMA'able memory for Tx ring.\n", 1559 device_xname(sc->sc_dev)); 1560 bus_dmamem_free(sc->sc_dmat, 1561 &sc->alc_rdata.alc_tx_ring_seg, 1); 1562 return error; 1563 } 1564 1565 sc->alc_rdata.alc_tx_ring_paddr = 1566 sc->alc_cdata.alc_tx_ring_map->dm_segs[0].ds_addr; 1567 1568 /* 1569 * Create DMA stuffs for RX ring 1570 */ 1571 error = bus_dmamap_create(sc->sc_dmat, ALC_RX_RING_SZ, 1, 1572 ALC_RX_RING_SZ, 0, BUS_DMA_NOWAIT, &sc->alc_cdata.alc_rx_ring_map); 1573 if (error) 1574 return (ENOBUFS); 1575 1576 /* Allocate DMA'able memory for RX ring */ 1577 error = bus_dmamem_alloc(sc->sc_dmat, ALC_RX_RING_SZ, 1578 ETHER_ALIGN, 0, &sc->alc_rdata.alc_rx_ring_seg, 1, 1579 &nsegs, BUS_DMA_NOWAIT); 1580 if (error) { 1581 printf("%s: could not allocate DMA'able memory for Rx ring.\n", 1582 device_xname(sc->sc_dev)); 1583 return error; 1584 } 1585 1586 error = bus_dmamem_map(sc->sc_dmat, &sc->alc_rdata.alc_rx_ring_seg, 1587 nsegs, ALC_RX_RING_SZ, (void **)&sc->alc_rdata.alc_rx_ring, 1588 BUS_DMA_NOWAIT); 1589 if (error) 1590 return (ENOBUFS); 1591 1592 /* Load the DMA map for Rx ring. */ 1593 error = bus_dmamap_load(sc->sc_dmat, sc->alc_cdata.alc_rx_ring_map, 1594 sc->alc_rdata.alc_rx_ring, ALC_RX_RING_SZ, NULL, BUS_DMA_WAITOK); 1595 if (error) { 1596 printf("%s: could not load DMA'able memory for Rx ring.\n", 1597 device_xname(sc->sc_dev)); 1598 bus_dmamem_free(sc->sc_dmat, 1599 &sc->alc_rdata.alc_rx_ring_seg, 1); 1600 return error; 1601 } 1602 1603 sc->alc_rdata.alc_rx_ring_paddr = 1604 sc->alc_cdata.alc_rx_ring_map->dm_segs[0].ds_addr; 1605 1606 /* 1607 * Create DMA stuffs for RX return ring 1608 */ 1609 error = bus_dmamap_create(sc->sc_dmat, ALC_RR_RING_SZ, 1, 1610 ALC_RR_RING_SZ, 0, BUS_DMA_NOWAIT, &sc->alc_cdata.alc_rr_ring_map); 1611 if (error) 1612 return (ENOBUFS); 1613 1614 /* Allocate DMA'able memory for RX return ring */ 1615 error = bus_dmamem_alloc(sc->sc_dmat, ALC_RR_RING_SZ, 1616 ETHER_ALIGN, 0, &sc->alc_rdata.alc_rr_ring_seg, 1, 1617 &nsegs, BUS_DMA_NOWAIT); 1618 if (error) { 1619 printf("%s: could not allocate DMA'able memory for Rx " 1620 "return ring.\n", device_xname(sc->sc_dev)); 1621 return error; 1622 } 1623 1624 error = bus_dmamem_map(sc->sc_dmat, &sc->alc_rdata.alc_rr_ring_seg, 1625 nsegs, ALC_RR_RING_SZ, (void **)&sc->alc_rdata.alc_rr_ring, 1626 BUS_DMA_NOWAIT); 1627 if (error) 1628 return (ENOBUFS); 1629 1630 /* Load the DMA map for Rx return ring. */ 1631 error = bus_dmamap_load(sc->sc_dmat, sc->alc_cdata.alc_rr_ring_map, 1632 sc->alc_rdata.alc_rr_ring, ALC_RR_RING_SZ, NULL, BUS_DMA_WAITOK); 1633 if (error) { 1634 printf("%s: could not load DMA'able memory for Rx return ring." 1635 "\n", device_xname(sc->sc_dev)); 1636 bus_dmamem_free(sc->sc_dmat, 1637 &sc->alc_rdata.alc_rr_ring_seg, 1); 1638 return error; 1639 } 1640 1641 sc->alc_rdata.alc_rr_ring_paddr = 1642 sc->alc_cdata.alc_rr_ring_map->dm_segs[0].ds_addr; 1643 1644 /* 1645 * Create DMA stuffs for CMB block 1646 */ 1647 error = bus_dmamap_create(sc->sc_dmat, ALC_CMB_SZ, 1, 1648 ALC_CMB_SZ, 0, BUS_DMA_NOWAIT, 1649 &sc->alc_cdata.alc_cmb_map); 1650 if (error) 1651 return (ENOBUFS); 1652 1653 /* Allocate DMA'able memory for CMB block */ 1654 error = bus_dmamem_alloc(sc->sc_dmat, ALC_CMB_SZ, 1655 ETHER_ALIGN, 0, &sc->alc_rdata.alc_cmb_seg, 1, 1656 &nsegs, BUS_DMA_NOWAIT); 1657 if (error) { 1658 printf("%s: could not allocate DMA'able memory for " 1659 "CMB block\n", device_xname(sc->sc_dev)); 1660 return error; 1661 } 1662 1663 error = bus_dmamem_map(sc->sc_dmat, &sc->alc_rdata.alc_cmb_seg, 1664 nsegs, ALC_CMB_SZ, (void **)&sc->alc_rdata.alc_cmb, 1665 BUS_DMA_NOWAIT); 1666 if (error) 1667 return (ENOBUFS); 1668 1669 /* Load the DMA map for CMB block. */ 1670 error = bus_dmamap_load(sc->sc_dmat, sc->alc_cdata.alc_cmb_map, 1671 sc->alc_rdata.alc_cmb, ALC_CMB_SZ, NULL, 1672 BUS_DMA_WAITOK); 1673 if (error) { 1674 printf("%s: could not load DMA'able memory for CMB block\n", 1675 device_xname(sc->sc_dev)); 1676 bus_dmamem_free(sc->sc_dmat, 1677 &sc->alc_rdata.alc_cmb_seg, 1); 1678 return error; 1679 } 1680 1681 sc->alc_rdata.alc_cmb_paddr = 1682 sc->alc_cdata.alc_cmb_map->dm_segs[0].ds_addr; 1683 1684 /* 1685 * Create DMA stuffs for SMB block 1686 */ 1687 error = bus_dmamap_create(sc->sc_dmat, ALC_SMB_SZ, 1, 1688 ALC_SMB_SZ, 0, BUS_DMA_NOWAIT, 1689 &sc->alc_cdata.alc_smb_map); 1690 if (error) 1691 return (ENOBUFS); 1692 1693 /* Allocate DMA'able memory for SMB block */ 1694 error = bus_dmamem_alloc(sc->sc_dmat, ALC_SMB_SZ, 1695 ETHER_ALIGN, 0, &sc->alc_rdata.alc_smb_seg, 1, 1696 &nsegs, BUS_DMA_NOWAIT); 1697 if (error) { 1698 printf("%s: could not allocate DMA'able memory for " 1699 "SMB block\n", device_xname(sc->sc_dev)); 1700 return error; 1701 } 1702 1703 error = bus_dmamem_map(sc->sc_dmat, &sc->alc_rdata.alc_smb_seg, 1704 nsegs, ALC_SMB_SZ, (void **)&sc->alc_rdata.alc_smb, 1705 BUS_DMA_NOWAIT); 1706 if (error) 1707 return (ENOBUFS); 1708 1709 /* Load the DMA map for SMB block */ 1710 error = bus_dmamap_load(sc->sc_dmat, sc->alc_cdata.alc_smb_map, 1711 sc->alc_rdata.alc_smb, ALC_SMB_SZ, NULL, 1712 BUS_DMA_WAITOK); 1713 if (error) { 1714 printf("%s: could not load DMA'able memory for SMB block\n", 1715 device_xname(sc->sc_dev)); 1716 bus_dmamem_free(sc->sc_dmat, 1717 &sc->alc_rdata.alc_smb_seg, 1); 1718 return error; 1719 } 1720 1721 sc->alc_rdata.alc_smb_paddr = 1722 sc->alc_cdata.alc_smb_map->dm_segs[0].ds_addr; 1723 1724 1725 /* Create DMA maps for Tx buffers. */ 1726 for (i = 0; i < ALC_TX_RING_CNT; i++) { 1727 txd = &sc->alc_cdata.alc_txdesc[i]; 1728 txd->tx_m = NULL; 1729 txd->tx_dmamap = NULL; 1730 error = bus_dmamap_create(sc->sc_dmat, ALC_TSO_MAXSIZE, 1731 ALC_MAXTXSEGS, ALC_TSO_MAXSEGSIZE, 0, BUS_DMA_NOWAIT, 1732 &txd->tx_dmamap); 1733 if (error) { 1734 printf("%s: could not create Tx dmamap.\n", 1735 device_xname(sc->sc_dev)); 1736 return error; 1737 } 1738 } 1739 1740 /* Create DMA maps for Rx buffers. */ 1741 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES, 0, 1742 BUS_DMA_NOWAIT, &sc->alc_cdata.alc_rx_sparemap); 1743 if (error) { 1744 printf("%s: could not create spare Rx dmamap.\n", 1745 device_xname(sc->sc_dev)); 1746 return error; 1747 } 1748 1749 for (i = 0; i < ALC_RX_RING_CNT; i++) { 1750 rxd = &sc->alc_cdata.alc_rxdesc[i]; 1751 rxd->rx_m = NULL; 1752 rxd->rx_dmamap = NULL; 1753 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 1754 MCLBYTES, 0, BUS_DMA_NOWAIT, &rxd->rx_dmamap); 1755 if (error) { 1756 printf("%s: could not create Rx dmamap.\n", 1757 device_xname(sc->sc_dev)); 1758 return error; 1759 } 1760 } 1761 1762 return (0); 1763 } 1764 1765 1766 static void 1767 alc_dma_free(struct alc_softc *sc) 1768 { 1769 struct alc_txdesc *txd; 1770 struct alc_rxdesc *rxd; 1771 int i; 1772 1773 /* Tx buffers */ 1774 for (i = 0; i < ALC_TX_RING_CNT; i++) { 1775 txd = &sc->alc_cdata.alc_txdesc[i]; 1776 if (txd->tx_dmamap != NULL) { 1777 bus_dmamap_destroy(sc->sc_dmat, txd->tx_dmamap); 1778 txd->tx_dmamap = NULL; 1779 } 1780 } 1781 /* Rx buffers */ 1782 for (i = 0; i < ALC_RX_RING_CNT; i++) { 1783 rxd = &sc->alc_cdata.alc_rxdesc[i]; 1784 if (rxd->rx_dmamap != NULL) { 1785 bus_dmamap_destroy(sc->sc_dmat, rxd->rx_dmamap); 1786 rxd->rx_dmamap = NULL; 1787 } 1788 } 1789 if (sc->alc_cdata.alc_rx_sparemap != NULL) { 1790 bus_dmamap_destroy(sc->sc_dmat, sc->alc_cdata.alc_rx_sparemap); 1791 sc->alc_cdata.alc_rx_sparemap = NULL; 1792 } 1793 1794 /* Tx ring. */ 1795 if (sc->alc_cdata.alc_tx_ring_map != NULL) 1796 bus_dmamap_unload(sc->sc_dmat, sc->alc_cdata.alc_tx_ring_map); 1797 if (sc->alc_cdata.alc_tx_ring_map != NULL && 1798 sc->alc_rdata.alc_tx_ring != NULL) 1799 bus_dmamem_free(sc->sc_dmat, 1800 &sc->alc_rdata.alc_tx_ring_seg, 1); 1801 sc->alc_rdata.alc_tx_ring = NULL; 1802 sc->alc_cdata.alc_tx_ring_map = NULL; 1803 1804 /* Rx ring. */ 1805 if (sc->alc_cdata.alc_rx_ring_map != NULL) 1806 bus_dmamap_unload(sc->sc_dmat, sc->alc_cdata.alc_rx_ring_map); 1807 if (sc->alc_cdata.alc_rx_ring_map != NULL && 1808 sc->alc_rdata.alc_rx_ring != NULL) 1809 bus_dmamem_free(sc->sc_dmat, 1810 &sc->alc_rdata.alc_rx_ring_seg, 1); 1811 sc->alc_rdata.alc_rx_ring = NULL; 1812 sc->alc_cdata.alc_rx_ring_map = NULL; 1813 1814 /* Rx return ring. */ 1815 if (sc->alc_cdata.alc_rr_ring_map != NULL) 1816 bus_dmamap_unload(sc->sc_dmat, sc->alc_cdata.alc_rr_ring_map); 1817 if (sc->alc_cdata.alc_rr_ring_map != NULL && 1818 sc->alc_rdata.alc_rr_ring != NULL) 1819 bus_dmamem_free(sc->sc_dmat, 1820 &sc->alc_rdata.alc_rr_ring_seg, 1); 1821 sc->alc_rdata.alc_rr_ring = NULL; 1822 sc->alc_cdata.alc_rr_ring_map = NULL; 1823 1824 /* CMB block */ 1825 if (sc->alc_cdata.alc_cmb_map != NULL) 1826 bus_dmamap_unload(sc->sc_dmat, sc->alc_cdata.alc_cmb_map); 1827 if (sc->alc_cdata.alc_cmb_map != NULL && 1828 sc->alc_rdata.alc_cmb != NULL) 1829 bus_dmamem_free(sc->sc_dmat, 1830 &sc->alc_rdata.alc_cmb_seg, 1); 1831 sc->alc_rdata.alc_cmb = NULL; 1832 sc->alc_cdata.alc_cmb_map = NULL; 1833 1834 /* SMB block */ 1835 if (sc->alc_cdata.alc_smb_map != NULL) 1836 bus_dmamap_unload(sc->sc_dmat, sc->alc_cdata.alc_smb_map); 1837 if (sc->alc_cdata.alc_smb_map != NULL && 1838 sc->alc_rdata.alc_smb != NULL) 1839 bus_dmamem_free(sc->sc_dmat, 1840 &sc->alc_rdata.alc_smb_seg, 1); 1841 sc->alc_rdata.alc_smb = NULL; 1842 sc->alc_cdata.alc_smb_map = NULL; 1843 } 1844 1845 static int 1846 alc_encap(struct alc_softc *sc, struct mbuf **m_head) 1847 { 1848 struct alc_txdesc *txd, *txd_last; 1849 struct tx_desc *desc; 1850 struct mbuf *m; 1851 bus_dmamap_t map; 1852 uint32_t cflags, poff, vtag; 1853 int error, idx, nsegs, prod; 1854 #if NVLAN > 0 1855 struct m_tag *mtag; 1856 #endif 1857 1858 m = *m_head; 1859 cflags = vtag = 0; 1860 poff = 0; 1861 1862 prod = sc->alc_cdata.alc_tx_prod; 1863 txd = &sc->alc_cdata.alc_txdesc[prod]; 1864 txd_last = txd; 1865 map = txd->tx_dmamap; 1866 1867 error = bus_dmamap_load_mbuf(sc->sc_dmat, map, *m_head, BUS_DMA_NOWAIT); 1868 1869 if (error == EFBIG) { 1870 error = 0; 1871 1872 *m_head = m_pullup(*m_head, MHLEN); 1873 if (*m_head == NULL) { 1874 printf("%s: can't defrag TX mbuf\n", 1875 device_xname(sc->sc_dev)); 1876 return ENOBUFS; 1877 } 1878 1879 error = bus_dmamap_load_mbuf(sc->sc_dmat, map, *m_head, 1880 BUS_DMA_NOWAIT); 1881 1882 if (error != 0) { 1883 printf("%s: could not load defragged TX mbuf\n", 1884 device_xname(sc->sc_dev)); 1885 m_freem(*m_head); 1886 *m_head = NULL; 1887 return error; 1888 } 1889 } else if (error) { 1890 printf("%s: could not load TX mbuf\n", device_xname(sc->sc_dev)); 1891 return (error); 1892 } 1893 1894 nsegs = map->dm_nsegs; 1895 1896 if (nsegs == 0) { 1897 m_freem(*m_head); 1898 *m_head = NULL; 1899 return (EIO); 1900 } 1901 1902 /* Check descriptor overrun. */ 1903 if (sc->alc_cdata.alc_tx_cnt + nsegs >= ALC_TX_RING_CNT - 3) { 1904 bus_dmamap_unload(sc->sc_dmat, map); 1905 return (ENOBUFS); 1906 } 1907 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 1908 BUS_DMASYNC_PREWRITE); 1909 1910 m = *m_head; 1911 desc = NULL; 1912 idx = 0; 1913 #if NVLAN > 0 1914 /* Configure VLAN hardware tag insertion. */ 1915 if ((mtag = VLAN_OUTPUT_TAG(&sc->sc_ec, m))) { 1916 vtag = htons(VLAN_TAG_VALUE(mtag)); 1917 vtag = (vtag << TD_VLAN_SHIFT) & TD_VLAN_MASK; 1918 cflags |= TD_INS_VLAN_TAG; 1919 } 1920 #endif 1921 /* Configure Tx checksum offload. */ 1922 if ((m->m_pkthdr.csum_flags & ALC_CSUM_FEATURES) != 0) { 1923 cflags |= TD_CUSTOM_CSUM; 1924 /* Set checksum start offset. */ 1925 cflags |= ((poff >> 1) << TD_PLOAD_OFFSET_SHIFT) & 1926 TD_PLOAD_OFFSET_MASK; 1927 } 1928 for (; idx < nsegs; idx++) { 1929 desc = &sc->alc_rdata.alc_tx_ring[prod]; 1930 desc->len = 1931 htole32(TX_BYTES(map->dm_segs[idx].ds_len) | vtag); 1932 desc->flags = htole32(cflags); 1933 desc->addr = htole64(map->dm_segs[idx].ds_addr); 1934 sc->alc_cdata.alc_tx_cnt++; 1935 ALC_DESC_INC(prod, ALC_TX_RING_CNT); 1936 } 1937 /* Update producer index. */ 1938 sc->alc_cdata.alc_tx_prod = prod; 1939 1940 /* Finally set EOP on the last descriptor. */ 1941 prod = (prod + ALC_TX_RING_CNT - 1) % ALC_TX_RING_CNT; 1942 desc = &sc->alc_rdata.alc_tx_ring[prod]; 1943 desc->flags |= htole32(TD_EOP); 1944 1945 /* Swap dmamap of the first and the last. */ 1946 txd = &sc->alc_cdata.alc_txdesc[prod]; 1947 map = txd_last->tx_dmamap; 1948 txd_last->tx_dmamap = txd->tx_dmamap; 1949 txd->tx_dmamap = map; 1950 txd->tx_m = m; 1951 1952 return (0); 1953 } 1954 1955 static void 1956 alc_start(struct ifnet *ifp) 1957 { 1958 struct alc_softc *sc = ifp->if_softc; 1959 struct mbuf *m_head; 1960 int enq; 1961 1962 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 1963 return; 1964 if ((sc->alc_flags & ALC_FLAG_LINK) == 0) 1965 return; 1966 if (IFQ_IS_EMPTY(&ifp->if_snd)) 1967 return; 1968 1969 /* Reclaim transmitted frames. */ 1970 if (sc->alc_cdata.alc_tx_cnt >= ALC_TX_DESC_HIWAT) 1971 alc_txeof(sc); 1972 1973 enq = 0; 1974 for (;;) { 1975 IFQ_DEQUEUE(&ifp->if_snd, m_head); 1976 if (m_head == NULL) 1977 break; 1978 1979 /* 1980 * Pack the data into the transmit ring. If we 1981 * don't have room, set the OACTIVE flag and wait 1982 * for the NIC to drain the ring. 1983 */ 1984 if (alc_encap(sc, &m_head)) { 1985 if (m_head == NULL) 1986 break; 1987 ifp->if_flags |= IFF_OACTIVE; 1988 break; 1989 } 1990 enq = 1; 1991 1992 /* 1993 * If there's a BPF listener, bounce a copy of this frame 1994 * to him. 1995 */ 1996 bpf_mtap(ifp, m_head); 1997 } 1998 1999 if (enq) { 2000 /* Sync descriptors. */ 2001 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_tx_ring_map, 0, 2002 sc->alc_cdata.alc_tx_ring_map->dm_mapsize, 2003 BUS_DMASYNC_PREWRITE); 2004 /* Kick. Assume we're using normal Tx priority queue. */ 2005 CSR_WRITE_4(sc, ALC_MBOX_TD_PROD_IDX, 2006 (sc->alc_cdata.alc_tx_prod << 2007 MBOX_TD_PROD_LO_IDX_SHIFT) & 2008 MBOX_TD_PROD_LO_IDX_MASK); 2009 /* Set a timeout in case the chip goes out to lunch. */ 2010 ifp->if_timer = ALC_TX_TIMEOUT; 2011 } 2012 } 2013 2014 static void 2015 alc_watchdog(struct ifnet *ifp) 2016 { 2017 struct alc_softc *sc = ifp->if_softc; 2018 2019 if ((sc->alc_flags & ALC_FLAG_LINK) == 0) { 2020 printf("%s: watchdog timeout (missed link)\n", 2021 device_xname(sc->sc_dev)); 2022 ifp->if_oerrors++; 2023 alc_init_backend(ifp, false); 2024 return; 2025 } 2026 2027 printf("%s: watchdog timeout\n", device_xname(sc->sc_dev)); 2028 ifp->if_oerrors++; 2029 alc_init_backend(ifp, false); 2030 alc_start(ifp); 2031 } 2032 2033 static int 2034 alc_ioctl(struct ifnet *ifp, u_long cmd, void *data) 2035 { 2036 struct alc_softc *sc = ifp->if_softc; 2037 int s, error = 0; 2038 2039 s = splnet(); 2040 2041 error = ether_ioctl(ifp, cmd, data); 2042 if (error == ENETRESET) { 2043 if (ifp->if_flags & IFF_RUNNING) 2044 alc_iff(sc); 2045 error = 0; 2046 } 2047 2048 splx(s); 2049 return (error); 2050 } 2051 2052 static void 2053 alc_mac_config(struct alc_softc *sc) 2054 { 2055 struct mii_data *mii; 2056 uint32_t reg; 2057 2058 mii = &sc->sc_miibus; 2059 reg = CSR_READ_4(sc, ALC_MAC_CFG); 2060 reg &= ~(MAC_CFG_FULL_DUPLEX | MAC_CFG_TX_FC | MAC_CFG_RX_FC | 2061 MAC_CFG_SPEED_MASK); 2062 if (sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8151 || 2063 sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8151_V2 || 2064 sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8152_B2) 2065 reg |= MAC_CFG_HASH_ALG_CRC32 | MAC_CFG_SPEED_MODE_SW; 2066 /* Reprogram MAC with resolved speed/duplex. */ 2067 switch (IFM_SUBTYPE(mii->mii_media_active)) { 2068 case IFM_10_T: 2069 case IFM_100_TX: 2070 reg |= MAC_CFG_SPEED_10_100; 2071 break; 2072 case IFM_1000_T: 2073 reg |= MAC_CFG_SPEED_1000; 2074 break; 2075 } 2076 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 2077 reg |= MAC_CFG_FULL_DUPLEX; 2078 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0) 2079 reg |= MAC_CFG_TX_FC; 2080 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0) 2081 reg |= MAC_CFG_RX_FC; 2082 } 2083 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 2084 } 2085 2086 static void 2087 alc_stats_clear(struct alc_softc *sc) 2088 { 2089 struct smb sb, *smb; 2090 uint32_t *reg; 2091 int i; 2092 2093 if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0) { 2094 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_smb_map, 0, 2095 sc->alc_cdata.alc_smb_map->dm_mapsize, 2096 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2097 smb = sc->alc_rdata.alc_smb; 2098 /* Update done, clear. */ 2099 smb->updated = 0; 2100 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_smb_map, 0, 2101 sc->alc_cdata.alc_smb_map->dm_mapsize, 2102 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2103 } else { 2104 for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered; 2105 reg++) { 2106 CSR_READ_4(sc, ALC_RX_MIB_BASE + i); 2107 i += sizeof(uint32_t); 2108 } 2109 /* Read Tx statistics. */ 2110 for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes; 2111 reg++) { 2112 CSR_READ_4(sc, ALC_TX_MIB_BASE + i); 2113 i += sizeof(uint32_t); 2114 } 2115 } 2116 } 2117 2118 static void 2119 alc_stats_update(struct alc_softc *sc) 2120 { 2121 struct ifnet *ifp = &sc->sc_ec.ec_if; 2122 struct alc_hw_stats *stat; 2123 struct smb sb, *smb; 2124 uint32_t *reg; 2125 int i; 2126 2127 stat = &sc->alc_stats; 2128 if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0) { 2129 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_smb_map, 0, 2130 sc->alc_cdata.alc_smb_map->dm_mapsize, 2131 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2132 smb = sc->alc_rdata.alc_smb; 2133 if (smb->updated == 0) 2134 return; 2135 } else { 2136 smb = &sb; 2137 /* Read Rx statistics. */ 2138 for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered; 2139 reg++) { 2140 *reg = CSR_READ_4(sc, ALC_RX_MIB_BASE + i); 2141 i += sizeof(uint32_t); 2142 } 2143 /* Read Tx statistics. */ 2144 for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes; 2145 reg++) { 2146 *reg = CSR_READ_4(sc, ALC_TX_MIB_BASE + i); 2147 i += sizeof(uint32_t); 2148 } 2149 } 2150 2151 /* Rx stats. */ 2152 stat->rx_frames += smb->rx_frames; 2153 stat->rx_bcast_frames += smb->rx_bcast_frames; 2154 stat->rx_mcast_frames += smb->rx_mcast_frames; 2155 stat->rx_pause_frames += smb->rx_pause_frames; 2156 stat->rx_control_frames += smb->rx_control_frames; 2157 stat->rx_crcerrs += smb->rx_crcerrs; 2158 stat->rx_lenerrs += smb->rx_lenerrs; 2159 stat->rx_bytes += smb->rx_bytes; 2160 stat->rx_runts += smb->rx_runts; 2161 stat->rx_fragments += smb->rx_fragments; 2162 stat->rx_pkts_64 += smb->rx_pkts_64; 2163 stat->rx_pkts_65_127 += smb->rx_pkts_65_127; 2164 stat->rx_pkts_128_255 += smb->rx_pkts_128_255; 2165 stat->rx_pkts_256_511 += smb->rx_pkts_256_511; 2166 stat->rx_pkts_512_1023 += smb->rx_pkts_512_1023; 2167 stat->rx_pkts_1024_1518 += smb->rx_pkts_1024_1518; 2168 stat->rx_pkts_1519_max += smb->rx_pkts_1519_max; 2169 stat->rx_pkts_truncated += smb->rx_pkts_truncated; 2170 stat->rx_fifo_oflows += smb->rx_fifo_oflows; 2171 stat->rx_rrs_errs += smb->rx_rrs_errs; 2172 stat->rx_alignerrs += smb->rx_alignerrs; 2173 stat->rx_bcast_bytes += smb->rx_bcast_bytes; 2174 stat->rx_mcast_bytes += smb->rx_mcast_bytes; 2175 stat->rx_pkts_filtered += smb->rx_pkts_filtered; 2176 2177 /* Tx stats. */ 2178 stat->tx_frames += smb->tx_frames; 2179 stat->tx_bcast_frames += smb->tx_bcast_frames; 2180 stat->tx_mcast_frames += smb->tx_mcast_frames; 2181 stat->tx_pause_frames += smb->tx_pause_frames; 2182 stat->tx_excess_defer += smb->tx_excess_defer; 2183 stat->tx_control_frames += smb->tx_control_frames; 2184 stat->tx_deferred += smb->tx_deferred; 2185 stat->tx_bytes += smb->tx_bytes; 2186 stat->tx_pkts_64 += smb->tx_pkts_64; 2187 stat->tx_pkts_65_127 += smb->tx_pkts_65_127; 2188 stat->tx_pkts_128_255 += smb->tx_pkts_128_255; 2189 stat->tx_pkts_256_511 += smb->tx_pkts_256_511; 2190 stat->tx_pkts_512_1023 += smb->tx_pkts_512_1023; 2191 stat->tx_pkts_1024_1518 += smb->tx_pkts_1024_1518; 2192 stat->tx_pkts_1519_max += smb->tx_pkts_1519_max; 2193 stat->tx_single_colls += smb->tx_single_colls; 2194 stat->tx_multi_colls += smb->tx_multi_colls; 2195 stat->tx_late_colls += smb->tx_late_colls; 2196 stat->tx_excess_colls += smb->tx_excess_colls; 2197 stat->tx_underrun += smb->tx_underrun; 2198 stat->tx_desc_underrun += smb->tx_desc_underrun; 2199 stat->tx_lenerrs += smb->tx_lenerrs; 2200 stat->tx_pkts_truncated += smb->tx_pkts_truncated; 2201 stat->tx_bcast_bytes += smb->tx_bcast_bytes; 2202 stat->tx_mcast_bytes += smb->tx_mcast_bytes; 2203 2204 /* Update counters in ifnet. */ 2205 ifp->if_opackets += smb->tx_frames; 2206 2207 ifp->if_collisions += smb->tx_single_colls + 2208 smb->tx_multi_colls * 2 + smb->tx_late_colls + 2209 smb->tx_excess_colls * HDPX_CFG_RETRY_DEFAULT; 2210 2211 ifp->if_oerrors += smb->tx_late_colls + smb->tx_excess_colls + 2212 smb->tx_underrun + smb->tx_pkts_truncated; 2213 2214 ifp->if_ipackets += smb->rx_frames; 2215 2216 ifp->if_ierrors += smb->rx_crcerrs + smb->rx_lenerrs + 2217 smb->rx_runts + smb->rx_pkts_truncated + 2218 smb->rx_fifo_oflows + smb->rx_rrs_errs + 2219 smb->rx_alignerrs; 2220 2221 if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0) { 2222 /* Update done, clear. */ 2223 smb->updated = 0; 2224 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_smb_map, 0, 2225 sc->alc_cdata.alc_smb_map->dm_mapsize, 2226 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2227 } 2228 } 2229 2230 static int 2231 alc_intr(void *arg) 2232 { 2233 struct alc_softc *sc = arg; 2234 struct ifnet *ifp = &sc->sc_ec.ec_if; 2235 uint32_t status; 2236 2237 status = CSR_READ_4(sc, ALC_INTR_STATUS); 2238 if ((status & ALC_INTRS) == 0) 2239 return (0); 2240 2241 /* Acknowledge and disable interrupts. */ 2242 CSR_WRITE_4(sc, ALC_INTR_STATUS, status | INTR_DIS_INT); 2243 2244 if (ifp->if_flags & IFF_RUNNING) { 2245 if (status & INTR_RX_PKT) { 2246 int error; 2247 2248 error = alc_rxintr(sc); 2249 if (error) { 2250 alc_init_backend(ifp, false); 2251 return (0); 2252 } 2253 } 2254 2255 if (status & (INTR_DMA_RD_TO_RST | INTR_DMA_WR_TO_RST | 2256 INTR_TXQ_TO_RST)) { 2257 if (status & INTR_DMA_RD_TO_RST) 2258 printf("%s: DMA read error! -- resetting\n", 2259 device_xname(sc->sc_dev)); 2260 if (status & INTR_DMA_WR_TO_RST) 2261 printf("%s: DMA write error! -- resetting\n", 2262 device_xname(sc->sc_dev)); 2263 if (status & INTR_TXQ_TO_RST) 2264 printf("%s: TxQ reset! -- resetting\n", 2265 device_xname(sc->sc_dev)); 2266 alc_init_backend(ifp, false); 2267 return (0); 2268 } 2269 2270 alc_txeof(sc); 2271 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 2272 alc_start(ifp); 2273 } 2274 2275 /* Re-enable interrupts. */ 2276 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0x7FFFFFFF); 2277 return (1); 2278 } 2279 2280 static void 2281 alc_txeof(struct alc_softc *sc) 2282 { 2283 struct ifnet *ifp = &sc->sc_ec.ec_if; 2284 struct alc_txdesc *txd; 2285 uint32_t cons, prod; 2286 int prog; 2287 2288 if (sc->alc_cdata.alc_tx_cnt == 0) 2289 return; 2290 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_tx_ring_map, 0, 2291 sc->alc_cdata.alc_tx_ring_map->dm_mapsize, 2292 BUS_DMASYNC_POSTREAD); 2293 if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0) { 2294 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_cmb_map, 0, 2295 sc->alc_cdata.alc_cmb_map->dm_mapsize, 2296 BUS_DMASYNC_POSTREAD); 2297 prod = sc->alc_rdata.alc_cmb->cons; 2298 } else 2299 prod = CSR_READ_4(sc, ALC_MBOX_TD_CONS_IDX); 2300 /* Assume we're using normal Tx priority queue. */ 2301 prod = (prod & MBOX_TD_CONS_LO_IDX_MASK) >> 2302 MBOX_TD_CONS_LO_IDX_SHIFT; 2303 cons = sc->alc_cdata.alc_tx_cons; 2304 /* 2305 * Go through our Tx list and free mbufs for those 2306 * frames which have been transmitted. 2307 */ 2308 for (prog = 0; cons != prod; prog++, 2309 ALC_DESC_INC(cons, ALC_TX_RING_CNT)) { 2310 if (sc->alc_cdata.alc_tx_cnt <= 0) 2311 break; 2312 prog++; 2313 ifp->if_flags &= ~IFF_OACTIVE; 2314 sc->alc_cdata.alc_tx_cnt--; 2315 txd = &sc->alc_cdata.alc_txdesc[cons]; 2316 if (txd->tx_m != NULL) { 2317 /* Reclaim transmitted mbufs. */ 2318 bus_dmamap_sync(sc->sc_dmat, txd->tx_dmamap, 0, 2319 txd->tx_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 2320 bus_dmamap_unload(sc->sc_dmat, txd->tx_dmamap); 2321 m_freem(txd->tx_m); 2322 txd->tx_m = NULL; 2323 } 2324 } 2325 2326 if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0) 2327 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_cmb_map, 0, 2328 sc->alc_cdata.alc_cmb_map->dm_mapsize, BUS_DMASYNC_PREREAD); 2329 sc->alc_cdata.alc_tx_cons = cons; 2330 /* 2331 * Unarm watchdog timer only when there is no pending 2332 * frames in Tx queue. 2333 */ 2334 if (sc->alc_cdata.alc_tx_cnt == 0) 2335 ifp->if_timer = 0; 2336 } 2337 2338 static int 2339 alc_newbuf(struct alc_softc *sc, struct alc_rxdesc *rxd, bool init) 2340 { 2341 struct mbuf *m; 2342 bus_dmamap_t map; 2343 int error; 2344 2345 MGETHDR(m, init ? M_WAITOK : M_DONTWAIT, MT_DATA); 2346 if (m == NULL) 2347 return (ENOBUFS); 2348 MCLGET(m, init ? M_WAITOK : M_DONTWAIT); 2349 if (!(m->m_flags & M_EXT)) { 2350 m_freem(m); 2351 return (ENOBUFS); 2352 } 2353 2354 m->m_len = m->m_pkthdr.len = RX_BUF_SIZE_MAX; 2355 2356 error = bus_dmamap_load_mbuf(sc->sc_dmat, 2357 sc->alc_cdata.alc_rx_sparemap, m, BUS_DMA_NOWAIT); 2358 2359 if (error != 0) { 2360 if (!error) { 2361 bus_dmamap_unload(sc->sc_dmat, 2362 sc->alc_cdata.alc_rx_sparemap); 2363 error = EFBIG; 2364 printf("%s: too many segments?!\n", 2365 device_xname(sc->sc_dev)); 2366 } 2367 m_freem(m); 2368 2369 if (init) 2370 printf("%s: can't load RX mbuf\n", device_xname(sc->sc_dev)); 2371 2372 return (error); 2373 } 2374 2375 if (rxd->rx_m != NULL) { 2376 bus_dmamap_sync(sc->sc_dmat, rxd->rx_dmamap, 0, 2377 rxd->rx_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 2378 bus_dmamap_unload(sc->sc_dmat, rxd->rx_dmamap); 2379 } 2380 map = rxd->rx_dmamap; 2381 rxd->rx_dmamap = sc->alc_cdata.alc_rx_sparemap; 2382 sc->alc_cdata.alc_rx_sparemap = map; 2383 bus_dmamap_sync(sc->sc_dmat, rxd->rx_dmamap, 0, rxd->rx_dmamap->dm_mapsize, 2384 BUS_DMASYNC_PREREAD); 2385 rxd->rx_m = m; 2386 rxd->rx_desc->addr = htole64(rxd->rx_dmamap->dm_segs[0].ds_addr); 2387 return (0); 2388 } 2389 2390 static int 2391 alc_rxintr(struct alc_softc *sc) 2392 { 2393 struct ifnet *ifp = &sc->sc_ec.ec_if; 2394 struct rx_rdesc *rrd; 2395 uint32_t nsegs, status; 2396 int rr_cons, prog; 2397 2398 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_rr_ring_map, 0, 2399 sc->alc_cdata.alc_rr_ring_map->dm_mapsize, 2400 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2401 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_rx_ring_map, 0, 2402 sc->alc_cdata.alc_rx_ring_map->dm_mapsize, 2403 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2404 rr_cons = sc->alc_cdata.alc_rr_cons; 2405 for (prog = 0; (ifp->if_flags & IFF_RUNNING) != 0;) { 2406 rrd = &sc->alc_rdata.alc_rr_ring[rr_cons]; 2407 status = le32toh(rrd->status); 2408 if ((status & RRD_VALID) == 0) 2409 break; 2410 nsegs = RRD_RD_CNT(le32toh(rrd->rdinfo)); 2411 if (nsegs == 0) { 2412 /* This should not happen! */ 2413 if (alcdebug) 2414 printf("%s: unexpected segment count -- " 2415 "resetting\n", device_xname(sc->sc_dev)); 2416 return (EIO); 2417 } 2418 alc_rxeof(sc, rrd); 2419 /* Clear Rx return status. */ 2420 rrd->status = 0; 2421 ALC_DESC_INC(rr_cons, ALC_RR_RING_CNT); 2422 sc->alc_cdata.alc_rx_cons += nsegs; 2423 sc->alc_cdata.alc_rx_cons %= ALC_RR_RING_CNT; 2424 prog += nsegs; 2425 } 2426 2427 if (prog > 0) { 2428 /* Update the consumer index. */ 2429 sc->alc_cdata.alc_rr_cons = rr_cons; 2430 /* Sync Rx return descriptors. */ 2431 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_rr_ring_map, 0, 2432 sc->alc_cdata.alc_rr_ring_map->dm_mapsize, 2433 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2434 /* 2435 * Sync updated Rx descriptors such that controller see 2436 * modified buffer addresses. 2437 */ 2438 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_rx_ring_map, 0, 2439 sc->alc_cdata.alc_rx_ring_map->dm_mapsize, 2440 BUS_DMASYNC_PREWRITE); 2441 /* 2442 * Let controller know availability of new Rx buffers. 2443 * Since alc(4) use RXQ_CFG_RD_BURST_DEFAULT descriptors 2444 * it may be possible to update ALC_MBOX_RD0_PROD_IDX 2445 * only when Rx buffer pre-fetching is required. In 2446 * addition we already set ALC_RX_RD_FREE_THRESH to 2447 * RX_RD_FREE_THRESH_LO_DEFAULT descriptors. However 2448 * it still seems that pre-fetching needs more 2449 * experimentation. 2450 */ 2451 CSR_WRITE_4(sc, ALC_MBOX_RD0_PROD_IDX, 2452 sc->alc_cdata.alc_rx_cons); 2453 } 2454 2455 return (0); 2456 } 2457 2458 /* Receive a frame. */ 2459 static void 2460 alc_rxeof(struct alc_softc *sc, struct rx_rdesc *rrd) 2461 { 2462 struct ifnet *ifp = &sc->sc_ec.ec_if; 2463 struct alc_rxdesc *rxd; 2464 struct mbuf *mp, *m; 2465 uint32_t rdinfo, status; 2466 int count, nsegs, rx_cons; 2467 2468 status = le32toh(rrd->status); 2469 rdinfo = le32toh(rrd->rdinfo); 2470 rx_cons = RRD_RD_IDX(rdinfo); 2471 nsegs = RRD_RD_CNT(rdinfo); 2472 2473 sc->alc_cdata.alc_rxlen = RRD_BYTES(status); 2474 if (status & (RRD_ERR_SUM | RRD_ERR_LENGTH)) { 2475 /* 2476 * We want to pass the following frames to upper 2477 * layer regardless of error status of Rx return 2478 * ring. 2479 * 2480 * o IP/TCP/UDP checksum is bad. 2481 * o frame length and protocol specific length 2482 * does not match. 2483 * 2484 * Force network stack compute checksum for 2485 * errored frames. 2486 */ 2487 status |= RRD_TCP_UDPCSUM_NOK | RRD_IPCSUM_NOK; 2488 if ((status & (RRD_ERR_CRC | RRD_ERR_ALIGN | 2489 RRD_ERR_TRUNC | RRD_ERR_RUNT)) != 0) 2490 return; 2491 } 2492 2493 for (count = 0; count < nsegs; count++, 2494 ALC_DESC_INC(rx_cons, ALC_RX_RING_CNT)) { 2495 rxd = &sc->alc_cdata.alc_rxdesc[rx_cons]; 2496 mp = rxd->rx_m; 2497 /* Add a new receive buffer to the ring. */ 2498 if (alc_newbuf(sc, rxd, false) != 0) { 2499 ifp->if_iqdrops++; 2500 /* Reuse Rx buffers. */ 2501 if (sc->alc_cdata.alc_rxhead != NULL) 2502 m_freem(sc->alc_cdata.alc_rxhead); 2503 break; 2504 } 2505 2506 /* 2507 * Assume we've received a full sized frame. 2508 * Actual size is fixed when we encounter the end of 2509 * multi-segmented frame. 2510 */ 2511 mp->m_len = sc->alc_buf_size; 2512 2513 /* Chain received mbufs. */ 2514 if (sc->alc_cdata.alc_rxhead == NULL) { 2515 sc->alc_cdata.alc_rxhead = mp; 2516 sc->alc_cdata.alc_rxtail = mp; 2517 } else { 2518 mp->m_flags &= ~M_PKTHDR; 2519 sc->alc_cdata.alc_rxprev_tail = 2520 sc->alc_cdata.alc_rxtail; 2521 sc->alc_cdata.alc_rxtail->m_next = mp; 2522 sc->alc_cdata.alc_rxtail = mp; 2523 } 2524 2525 if (count == nsegs - 1) { 2526 /* Last desc. for this frame. */ 2527 m = sc->alc_cdata.alc_rxhead; 2528 m->m_flags |= M_PKTHDR; 2529 /* 2530 * It seems that L1C/L2C controller has no way 2531 * to tell hardware to strip CRC bytes. 2532 */ 2533 m->m_pkthdr.len = 2534 sc->alc_cdata.alc_rxlen - ETHER_CRC_LEN; 2535 if (nsegs > 1) { 2536 /* Set last mbuf size. */ 2537 mp->m_len = sc->alc_cdata.alc_rxlen - 2538 (nsegs - 1) * sc->alc_buf_size; 2539 /* Remove the CRC bytes in chained mbufs. */ 2540 if (mp->m_len <= ETHER_CRC_LEN) { 2541 sc->alc_cdata.alc_rxtail = 2542 sc->alc_cdata.alc_rxprev_tail; 2543 sc->alc_cdata.alc_rxtail->m_len -= 2544 (ETHER_CRC_LEN - mp->m_len); 2545 sc->alc_cdata.alc_rxtail->m_next = NULL; 2546 m_freem(mp); 2547 } else { 2548 mp->m_len -= ETHER_CRC_LEN; 2549 } 2550 } else 2551 m->m_len = m->m_pkthdr.len; 2552 m->m_pkthdr.rcvif = ifp; 2553 #if NVLAN > 0 2554 /* 2555 * Due to hardware bugs, Rx checksum offloading 2556 * was intentionally disabled. 2557 */ 2558 if (status & RRD_VLAN_TAG) { 2559 u_int32_t vtag = RRD_VLAN(le32toh(rrd->vtag)); 2560 VLAN_INPUT_TAG(ifp, m, ntohs(vtag), ); 2561 } 2562 #endif 2563 2564 bpf_mtap(ifp, m); 2565 2566 /* Pass it on. */ 2567 (*ifp->if_input)(ifp, m); 2568 } 2569 } 2570 /* Reset mbuf chains. */ 2571 ALC_RXCHAIN_RESET(sc); 2572 } 2573 2574 static void 2575 alc_tick(void *xsc) 2576 { 2577 struct alc_softc *sc = xsc; 2578 struct mii_data *mii = &sc->sc_miibus; 2579 int s; 2580 2581 s = splnet(); 2582 mii_tick(mii); 2583 alc_stats_update(sc); 2584 splx(s); 2585 2586 callout_schedule(&sc->sc_tick_ch, hz); 2587 } 2588 2589 static void 2590 alc_osc_reset(struct alc_softc *sc) 2591 { 2592 uint32_t reg; 2593 2594 reg = CSR_READ_4(sc, ALC_MISC3); 2595 reg &= ~MISC3_25M_BY_SW; 2596 reg |= MISC3_25M_NOTO_INTNL; 2597 CSR_WRITE_4(sc, ALC_MISC3, reg); 2598 2599 reg = CSR_READ_4(sc, ALC_MISC); 2600 if (AR816X_REV(sc->alc_rev) >= AR816X_REV_B0) { 2601 /* 2602 * Restore over-current protection default value. 2603 * This value could be reset by MAC reset. 2604 */ 2605 reg &= ~MISC_PSW_OCP_MASK; 2606 reg |= (MISC_PSW_OCP_DEFAULT << MISC_PSW_OCP_SHIFT); 2607 reg &= ~MISC_INTNLOSC_OPEN; 2608 CSR_WRITE_4(sc, ALC_MISC, reg); 2609 CSR_WRITE_4(sc, ALC_MISC, reg | MISC_INTNLOSC_OPEN); 2610 reg = CSR_READ_4(sc, ALC_MISC2); 2611 reg &= ~MISC2_CALB_START; 2612 CSR_WRITE_4(sc, ALC_MISC2, reg); 2613 CSR_WRITE_4(sc, ALC_MISC2, reg | MISC2_CALB_START); 2614 2615 } else { 2616 reg &= ~MISC_INTNLOSC_OPEN; 2617 /* Disable isolate for revision A devices. */ 2618 if (AR816X_REV(sc->alc_rev) <= AR816X_REV_A1) 2619 reg &= ~MISC_ISO_ENB; 2620 CSR_WRITE_4(sc, ALC_MISC, reg | MISC_INTNLOSC_OPEN); 2621 CSR_WRITE_4(sc, ALC_MISC, reg); 2622 } 2623 2624 DELAY(20); 2625 } 2626 2627 static void 2628 alc_reset(struct alc_softc *sc) 2629 { 2630 uint32_t pmcfg, reg; 2631 int i; 2632 2633 pmcfg = 0; 2634 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 2635 /* Reset workaround. */ 2636 CSR_WRITE_4(sc, ALC_MBOX_RD0_PROD_IDX, 1); 2637 if (AR816X_REV(sc->alc_rev) <= AR816X_REV_A1 && 2638 (sc->alc_rev & 0x01) != 0) { 2639 /* Disable L0s/L1s before reset. */ 2640 pmcfg = CSR_READ_4(sc, ALC_PM_CFG); 2641 if ((pmcfg & (PM_CFG_ASPM_L0S_ENB | PM_CFG_ASPM_L1_ENB)) 2642 != 0) { 2643 pmcfg &= ~(PM_CFG_ASPM_L0S_ENB | 2644 PM_CFG_ASPM_L1_ENB); 2645 CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg); 2646 } 2647 } 2648 } 2649 reg = CSR_READ_4(sc, ALC_MASTER_CFG); 2650 reg |= MASTER_OOB_DIS_OFF | MASTER_RESET; 2651 CSR_WRITE_4(sc, ALC_MASTER_CFG, reg); 2652 2653 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 2654 for (i = ALC_RESET_TIMEOUT; i > 0; i--) { 2655 DELAY(10); 2656 if (CSR_READ_4(sc, ALC_MBOX_RD0_PROD_IDX) == 0) 2657 break; 2658 } 2659 if (i == 0) 2660 printf("%s: MAC reset timeout!\n", device_xname(sc->sc_dev)); 2661 } 2662 for (i = ALC_RESET_TIMEOUT; i > 0; i--) { 2663 DELAY(10); 2664 if ((CSR_READ_4(sc, ALC_MASTER_CFG) & MASTER_RESET) == 0) 2665 break; 2666 } 2667 if (i == 0) 2668 printf("%s: master reset timeout!\n", device_xname(sc->sc_dev)); 2669 2670 for (i = ALC_RESET_TIMEOUT; i > 0; i--) { 2671 reg = CSR_READ_4(sc, ALC_IDLE_STATUS); 2672 if ((reg & (IDLE_STATUS_RXMAC | IDLE_STATUS_TXMAC | 2673 IDLE_STATUS_RXQ | IDLE_STATUS_TXQ)) == 0) 2674 break; 2675 DELAY(10); 2676 } 2677 if (i == 0) 2678 printf("%s: reset timeout(0x%08x)!\n", 2679 device_xname(sc->sc_dev), reg); 2680 2681 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 2682 if (AR816X_REV(sc->alc_rev) <= AR816X_REV_A1 && 2683 (sc->alc_rev & 0x01) != 0) { 2684 reg = CSR_READ_4(sc, ALC_MASTER_CFG); 2685 reg |= MASTER_CLK_SEL_DIS; 2686 CSR_WRITE_4(sc, ALC_MASTER_CFG, reg); 2687 /* Restore L0s/L1s config. */ 2688 if ((pmcfg & (PM_CFG_ASPM_L0S_ENB | PM_CFG_ASPM_L1_ENB)) 2689 != 0) 2690 CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg); 2691 } 2692 2693 alc_osc_reset(sc); 2694 reg = CSR_READ_4(sc, ALC_MISC3); 2695 reg &= ~MISC3_25M_BY_SW; 2696 reg |= MISC3_25M_NOTO_INTNL; 2697 CSR_WRITE_4(sc, ALC_MISC3, reg); 2698 reg = CSR_READ_4(sc, ALC_MISC); 2699 reg &= ~MISC_INTNLOSC_OPEN; 2700 if (AR816X_REV(sc->alc_rev) <= AR816X_REV_A1) 2701 reg &= ~MISC_ISO_ENB; 2702 CSR_WRITE_4(sc, ALC_MISC, reg); 2703 DELAY(20); 2704 } 2705 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0 || 2706 sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8152_B || 2707 sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8151_V2) 2708 CSR_WRITE_4(sc, ALC_SERDES_LOCK, 2709 CSR_READ_4(sc, ALC_SERDES_LOCK) | SERDES_MAC_CLK_SLOWDOWN | 2710 SERDES_PHY_CLK_SLOWDOWN); 2711 } 2712 2713 static int 2714 alc_init(struct ifnet *ifp) 2715 { 2716 2717 return alc_init_backend(ifp, true); 2718 } 2719 2720 static int 2721 alc_init_backend(struct ifnet *ifp, bool init) 2722 { 2723 struct alc_softc *sc = ifp->if_softc; 2724 struct mii_data *mii; 2725 uint8_t eaddr[ETHER_ADDR_LEN]; 2726 bus_addr_t paddr; 2727 uint32_t reg, rxf_hi, rxf_lo; 2728 int error; 2729 2730 /* 2731 * Cancel any pending I/O. 2732 */ 2733 alc_stop(ifp, 0); 2734 /* 2735 * Reset the chip to a known state. 2736 */ 2737 alc_reset(sc); 2738 2739 /* Initialize Rx descriptors. */ 2740 error = alc_init_rx_ring(sc, init); 2741 if (error != 0) { 2742 printf("%s: no memory for Rx buffers.\n", device_xname(sc->sc_dev)); 2743 alc_stop(ifp, 0); 2744 return (error); 2745 } 2746 alc_init_rr_ring(sc); 2747 alc_init_tx_ring(sc); 2748 alc_init_cmb(sc); 2749 alc_init_smb(sc); 2750 2751 /* Enable all clocks. */ 2752 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 2753 CSR_WRITE_4(sc, ALC_CLK_GATING_CFG, CLK_GATING_DMAW_ENB | 2754 CLK_GATING_DMAR_ENB | CLK_GATING_TXQ_ENB | 2755 CLK_GATING_RXQ_ENB | CLK_GATING_TXMAC_ENB | 2756 CLK_GATING_RXMAC_ENB); 2757 if (AR816X_REV(sc->alc_rev) >= AR816X_REV_B0) 2758 CSR_WRITE_4(sc, ALC_IDLE_DECISN_TIMER, 2759 IDLE_DECISN_TIMER_DEFAULT_1MS); 2760 } else 2761 CSR_WRITE_4(sc, ALC_CLK_GATING_CFG, 0); 2762 2763 2764 /* Reprogram the station address. */ 2765 memcpy(eaddr, CLLADDR(ifp->if_sadl), sizeof(eaddr)); 2766 CSR_WRITE_4(sc, ALC_PAR0, 2767 eaddr[2] << 24 | eaddr[3] << 16 | eaddr[4] << 8 | eaddr[5]); 2768 CSR_WRITE_4(sc, ALC_PAR1, eaddr[0] << 8 | eaddr[1]); 2769 /* 2770 * Clear WOL status and disable all WOL feature as WOL 2771 * would interfere Rx operation under normal environments. 2772 */ 2773 CSR_READ_4(sc, ALC_WOL_CFG); 2774 CSR_WRITE_4(sc, ALC_WOL_CFG, 0); 2775 /* Set Tx descriptor base addresses. */ 2776 paddr = sc->alc_rdata.alc_tx_ring_paddr; 2777 CSR_WRITE_4(sc, ALC_TX_BASE_ADDR_HI, ALC_ADDR_HI(paddr)); 2778 CSR_WRITE_4(sc, ALC_TDL_HEAD_ADDR_LO, ALC_ADDR_LO(paddr)); 2779 /* We don't use high priority ring. */ 2780 CSR_WRITE_4(sc, ALC_TDH_HEAD_ADDR_LO, 0); 2781 /* Set Tx descriptor counter. */ 2782 CSR_WRITE_4(sc, ALC_TD_RING_CNT, 2783 (ALC_TX_RING_CNT << TD_RING_CNT_SHIFT) & TD_RING_CNT_MASK); 2784 /* Set Rx descriptor base addresses. */ 2785 paddr = sc->alc_rdata.alc_rx_ring_paddr; 2786 CSR_WRITE_4(sc, ALC_RX_BASE_ADDR_HI, ALC_ADDR_HI(paddr)); 2787 CSR_WRITE_4(sc, ALC_RD0_HEAD_ADDR_LO, ALC_ADDR_LO(paddr)); 2788 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 2789 /* We use one Rx ring. */ 2790 CSR_WRITE_4(sc, ALC_RD1_HEAD_ADDR_LO, 0); 2791 CSR_WRITE_4(sc, ALC_RD2_HEAD_ADDR_LO, 0); 2792 CSR_WRITE_4(sc, ALC_RD3_HEAD_ADDR_LO, 0); 2793 } 2794 /* Set Rx descriptor counter. */ 2795 CSR_WRITE_4(sc, ALC_RD_RING_CNT, 2796 (ALC_RX_RING_CNT << RD_RING_CNT_SHIFT) & RD_RING_CNT_MASK); 2797 2798 /* 2799 * Let hardware split jumbo frames into alc_max_buf_sized chunks. 2800 * if it do not fit the buffer size. Rx return descriptor holds 2801 * a counter that indicates how many fragments were made by the 2802 * hardware. The buffer size should be multiple of 8 bytes. 2803 * Since hardware has limit on the size of buffer size, always 2804 * use the maximum value. 2805 * For strict-alignment architectures make sure to reduce buffer 2806 * size by 8 bytes to make room for alignment fixup. 2807 */ 2808 sc->alc_buf_size = RX_BUF_SIZE_MAX; 2809 CSR_WRITE_4(sc, ALC_RX_BUF_SIZE, sc->alc_buf_size); 2810 2811 paddr = sc->alc_rdata.alc_rr_ring_paddr; 2812 /* Set Rx return descriptor base addresses. */ 2813 CSR_WRITE_4(sc, ALC_RRD0_HEAD_ADDR_LO, ALC_ADDR_LO(paddr)); 2814 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 2815 /* We use one Rx return ring. */ 2816 CSR_WRITE_4(sc, ALC_RRD1_HEAD_ADDR_LO, 0); 2817 CSR_WRITE_4(sc, ALC_RRD2_HEAD_ADDR_LO, 0); 2818 CSR_WRITE_4(sc, ALC_RRD3_HEAD_ADDR_LO, 0); 2819 }\ 2820 /* Set Rx return descriptor counter. */ 2821 CSR_WRITE_4(sc, ALC_RRD_RING_CNT, 2822 (ALC_RR_RING_CNT << RRD_RING_CNT_SHIFT) & RRD_RING_CNT_MASK); 2823 paddr = sc->alc_rdata.alc_cmb_paddr; 2824 CSR_WRITE_4(sc, ALC_CMB_BASE_ADDR_LO, ALC_ADDR_LO(paddr)); 2825 paddr = sc->alc_rdata.alc_smb_paddr; 2826 CSR_WRITE_4(sc, ALC_SMB_BASE_ADDR_HI, ALC_ADDR_HI(paddr)); 2827 CSR_WRITE_4(sc, ALC_SMB_BASE_ADDR_LO, ALC_ADDR_LO(paddr)); 2828 2829 if (sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8152_B) { 2830 /* Reconfigure SRAM - Vendor magic. */ 2831 CSR_WRITE_4(sc, ALC_SRAM_RX_FIFO_LEN, 0x000002A0); 2832 CSR_WRITE_4(sc, ALC_SRAM_TX_FIFO_LEN, 0x00000100); 2833 CSR_WRITE_4(sc, ALC_SRAM_RX_FIFO_ADDR, 0x029F0000); 2834 CSR_WRITE_4(sc, ALC_SRAM_RD0_ADDR, 0x02BF02A0); 2835 CSR_WRITE_4(sc, ALC_SRAM_TX_FIFO_ADDR, 0x03BF02C0); 2836 CSR_WRITE_4(sc, ALC_SRAM_TD_ADDR, 0x03DF03C0); 2837 CSR_WRITE_4(sc, ALC_TXF_WATER_MARK, 0x00000000); 2838 CSR_WRITE_4(sc, ALC_RD_DMA_CFG, 0x00000000); 2839 } 2840 2841 /* Tell hardware that we're ready to load DMA blocks. */ 2842 CSR_WRITE_4(sc, ALC_DMA_BLOCK, DMA_BLOCK_LOAD); 2843 2844 /* Configure interrupt moderation timer. */ 2845 sc->alc_int_rx_mod = ALC_IM_RX_TIMER_DEFAULT; 2846 sc->alc_int_tx_mod = ALC_IM_TX_TIMER_DEFAULT; 2847 reg = ALC_USECS(sc->alc_int_rx_mod) << IM_TIMER_RX_SHIFT; 2848 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) 2849 reg |= ALC_USECS(sc->alc_int_tx_mod) << IM_TIMER_TX_SHIFT; 2850 CSR_WRITE_4(sc, ALC_IM_TIMER, reg); 2851 /* 2852 * We don't want to automatic interrupt clear as task queue 2853 * for the interrupt should know interrupt status. 2854 */ 2855 reg = CSR_READ_4(sc, ALC_MASTER_CFG); 2856 reg &= ~(MASTER_IM_RX_TIMER_ENB | MASTER_IM_TX_TIMER_ENB); 2857 reg |= MASTER_SA_TIMER_ENB; 2858 if (ALC_USECS(sc->alc_int_rx_mod) != 0) 2859 reg |= MASTER_IM_RX_TIMER_ENB; 2860 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0 && 2861 ALC_USECS(sc->alc_int_tx_mod) != 0) 2862 reg |= MASTER_IM_TX_TIMER_ENB; 2863 CSR_WRITE_4(sc, ALC_MASTER_CFG, reg); 2864 /* 2865 * Disable interrupt re-trigger timer. We don't want automatic 2866 * re-triggering of un-ACKed interrupts. 2867 */ 2868 CSR_WRITE_4(sc, ALC_INTR_RETRIG_TIMER, ALC_USECS(0)); 2869 /* Configure CMB. */ 2870 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 2871 CSR_WRITE_4(sc, ALC_CMB_TD_THRESH, ALC_TX_RING_CNT / 3); 2872 CSR_WRITE_4(sc, ALC_CMB_TX_TIMER, 2873 ALC_USECS(sc->alc_int_tx_mod)); 2874 } else { 2875 if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0) { 2876 CSR_WRITE_4(sc, ALC_CMB_TD_THRESH, 4); 2877 CSR_WRITE_4(sc, ALC_CMB_TX_TIMER, ALC_USECS(5000)); 2878 } else 2879 CSR_WRITE_4(sc, ALC_CMB_TX_TIMER, ALC_USECS(0)); 2880 } 2881 /* 2882 * Hardware can be configured to issue SMB interrupt based 2883 * on programmed interval. Since there is a callout that is 2884 * invoked for every hz in driver we use that instead of 2885 * relying on periodic SMB interrupt. 2886 */ 2887 CSR_WRITE_4(sc, ALC_SMB_STAT_TIMER, ALC_USECS(0)); 2888 /* Clear MAC statistics. */ 2889 alc_stats_clear(sc); 2890 2891 /* 2892 * Always use maximum frame size that controller can support. 2893 * Otherwise received frames that has larger frame length 2894 * than alc(4) MTU would be silently dropped in hardware. This 2895 * would make path-MTU discovery hard as sender wouldn't get 2896 * any responses from receiver. alc(4) supports 2897 * multi-fragmented frames on Rx path so it has no issue on 2898 * assembling fragmented frames. Using maximum frame size also 2899 * removes the need to reinitialize hardware when interface 2900 * MTU configuration was changed. 2901 * 2902 * Be conservative in what you do, be liberal in what you 2903 * accept from others - RFC 793. 2904 */ 2905 CSR_WRITE_4(sc, ALC_FRAME_SIZE, sc->alc_ident->max_framelen); 2906 2907 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 2908 /* Disable header split(?) */ 2909 CSR_WRITE_4(sc, ALC_HDS_CFG, 0); 2910 2911 /* Configure IPG/IFG parameters. */ 2912 CSR_WRITE_4(sc, ALC_IPG_IFG_CFG, 2913 ((IPG_IFG_IPGT_DEFAULT << IPG_IFG_IPGT_SHIFT) & 2914 IPG_IFG_IPGT_MASK) | 2915 ((IPG_IFG_MIFG_DEFAULT << IPG_IFG_MIFG_SHIFT) & 2916 IPG_IFG_MIFG_MASK) | 2917 ((IPG_IFG_IPG1_DEFAULT << IPG_IFG_IPG1_SHIFT) & 2918 IPG_IFG_IPG1_MASK) | 2919 ((IPG_IFG_IPG2_DEFAULT << IPG_IFG_IPG2_SHIFT) & 2920 IPG_IFG_IPG2_MASK)); 2921 /* Set parameters for half-duplex media. */ 2922 CSR_WRITE_4(sc, ALC_HDPX_CFG, 2923 ((HDPX_CFG_LCOL_DEFAULT << HDPX_CFG_LCOL_SHIFT) & 2924 HDPX_CFG_LCOL_MASK) | 2925 ((HDPX_CFG_RETRY_DEFAULT << HDPX_CFG_RETRY_SHIFT) & 2926 HDPX_CFG_RETRY_MASK) | HDPX_CFG_EXC_DEF_EN | 2927 ((HDPX_CFG_ABEBT_DEFAULT << HDPX_CFG_ABEBT_SHIFT) & 2928 HDPX_CFG_ABEBT_MASK) | 2929 ((HDPX_CFG_JAMIPG_DEFAULT << HDPX_CFG_JAMIPG_SHIFT) & 2930 HDPX_CFG_JAMIPG_MASK)); 2931 } 2932 2933 /* 2934 * Set TSO/checksum offload threshold. For frames that is 2935 * larger than this threshold, hardware wouldn't do 2936 * TSO/checksum offloading. 2937 */ 2938 reg = (sc->alc_ident->max_framelen >> TSO_OFFLOAD_THRESH_UNIT_SHIFT) & 2939 TSO_OFFLOAD_THRESH_MASK; 2940 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 2941 reg |= TSO_OFFLOAD_ERRLGPKT_DROP_ENB; 2942 CSR_WRITE_4(sc, ALC_TSO_OFFLOAD_THRESH, reg); 2943 /* Configure TxQ. */ 2944 reg = (alc_dma_burst[sc->alc_dma_rd_burst] << 2945 TXQ_CFG_TX_FIFO_BURST_SHIFT) & TXQ_CFG_TX_FIFO_BURST_MASK; 2946 if (sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8152_B || 2947 sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8152_B2) 2948 reg >>= 1; 2949 reg |= (TXQ_CFG_TD_BURST_DEFAULT << TXQ_CFG_TD_BURST_SHIFT) & 2950 TXQ_CFG_TD_BURST_MASK; 2951 reg |= TXQ_CFG_IP_OPTION_ENB | TXQ_CFG_8023_ENB; 2952 CSR_WRITE_4(sc, ALC_TXQ_CFG, reg | TXQ_CFG_ENHANCED_MODE); 2953 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 2954 reg = (TXQ_CFG_TD_BURST_DEFAULT << HQTD_CFG_Q1_BURST_SHIFT | 2955 TXQ_CFG_TD_BURST_DEFAULT << HQTD_CFG_Q2_BURST_SHIFT | 2956 TXQ_CFG_TD_BURST_DEFAULT << HQTD_CFG_Q3_BURST_SHIFT | 2957 HQTD_CFG_BURST_ENB); 2958 CSR_WRITE_4(sc, ALC_HQTD_CFG, reg); 2959 reg = WRR_PRI_RESTRICT_NONE; 2960 reg |= (WRR_PRI_DEFAULT << WRR_PRI0_SHIFT | 2961 WRR_PRI_DEFAULT << WRR_PRI1_SHIFT | 2962 WRR_PRI_DEFAULT << WRR_PRI2_SHIFT | 2963 WRR_PRI_DEFAULT << WRR_PRI3_SHIFT); 2964 CSR_WRITE_4(sc, ALC_WRR, reg); 2965 } else { 2966 /* Configure Rx free descriptor pre-fetching. */ 2967 CSR_WRITE_4(sc, ALC_RX_RD_FREE_THRESH, 2968 ((RX_RD_FREE_THRESH_HI_DEFAULT << 2969 RX_RD_FREE_THRESH_HI_SHIFT) & RX_RD_FREE_THRESH_HI_MASK) | 2970 ((RX_RD_FREE_THRESH_LO_DEFAULT << 2971 RX_RD_FREE_THRESH_LO_SHIFT) & RX_RD_FREE_THRESH_LO_MASK)); 2972 } 2973 2974 /* 2975 * Configure flow control parameters. 2976 * XON : 80% of Rx FIFO 2977 * XOFF : 30% of Rx FIFO 2978 */ 2979 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 2980 reg = CSR_READ_4(sc, ALC_SRAM_RX_FIFO_LEN); 2981 reg &= SRAM_RX_FIFO_LEN_MASK; 2982 reg *= 8; 2983 if (reg > 8 * 1024) 2984 reg -= RX_FIFO_PAUSE_816X_RSVD; 2985 else 2986 reg -= RX_BUF_SIZE_MAX; 2987 reg /= 8; 2988 CSR_WRITE_4(sc, ALC_RX_FIFO_PAUSE_THRESH, 2989 ((reg << RX_FIFO_PAUSE_THRESH_LO_SHIFT) & 2990 RX_FIFO_PAUSE_THRESH_LO_MASK) | 2991 (((RX_FIFO_PAUSE_816X_RSVD / 8) << 2992 RX_FIFO_PAUSE_THRESH_HI_SHIFT) & 2993 RX_FIFO_PAUSE_THRESH_HI_MASK)); 2994 } else if (sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8131 || 2995 sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8132) { 2996 reg = CSR_READ_4(sc, ALC_SRAM_RX_FIFO_LEN); 2997 rxf_hi = (reg * 8) / 10; 2998 rxf_lo = (reg * 3) / 10; 2999 CSR_WRITE_4(sc, ALC_RX_FIFO_PAUSE_THRESH, 3000 ((rxf_lo << RX_FIFO_PAUSE_THRESH_LO_SHIFT) & 3001 RX_FIFO_PAUSE_THRESH_LO_MASK) | 3002 ((rxf_hi << RX_FIFO_PAUSE_THRESH_HI_SHIFT) & 3003 RX_FIFO_PAUSE_THRESH_HI_MASK)); 3004 } 3005 3006 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 3007 /* Disable RSS until I understand L1C/L2C's RSS logic. */ 3008 CSR_WRITE_4(sc, ALC_RSS_IDT_TABLE0, 0); 3009 CSR_WRITE_4(sc, ALC_RSS_CPU, 0); 3010 } 3011 3012 /* Configure RxQ. */ 3013 reg = (RXQ_CFG_RD_BURST_DEFAULT << RXQ_CFG_RD_BURST_SHIFT) & 3014 RXQ_CFG_RD_BURST_MASK; 3015 reg |= RXQ_CFG_RSS_MODE_DIS; 3016 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 3017 reg |= (RXQ_CFG_816X_IDT_TBL_SIZE_DEFAULT << 3018 RXQ_CFG_816X_IDT_TBL_SIZE_SHIFT) & 3019 RXQ_CFG_816X_IDT_TBL_SIZE_MASK; 3020 if ((sc->alc_flags & ALC_FLAG_FASTETHER) == 0 && 3021 sc->alc_ident->deviceid != PCI_PRODUCT_ATTANSIC_AR8151_V2) 3022 reg |= RXQ_CFG_ASPM_THROUGHPUT_LIMIT_1M; 3023 CSR_WRITE_4(sc, ALC_RXQ_CFG, reg); 3024 3025 /* Configure DMA parameters. */ 3026 reg = DMA_CFG_OUT_ORDER | DMA_CFG_RD_REQ_PRI; 3027 reg |= sc->alc_rcb; 3028 if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0) 3029 reg |= DMA_CFG_CMB_ENB; 3030 if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0) 3031 reg |= DMA_CFG_SMB_ENB; 3032 else 3033 reg |= DMA_CFG_SMB_DIS; 3034 reg |= (sc->alc_dma_rd_burst & DMA_CFG_RD_BURST_MASK) << 3035 DMA_CFG_RD_BURST_SHIFT; 3036 reg |= (sc->alc_dma_wr_burst & DMA_CFG_WR_BURST_MASK) << 3037 DMA_CFG_WR_BURST_SHIFT; 3038 reg |= (DMA_CFG_RD_DELAY_CNT_DEFAULT << DMA_CFG_RD_DELAY_CNT_SHIFT) & 3039 DMA_CFG_RD_DELAY_CNT_MASK; 3040 reg |= (DMA_CFG_WR_DELAY_CNT_DEFAULT << DMA_CFG_WR_DELAY_CNT_SHIFT) & 3041 DMA_CFG_WR_DELAY_CNT_MASK; 3042 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 3043 switch (AR816X_REV(sc->alc_rev)) { 3044 case AR816X_REV_A0: 3045 case AR816X_REV_A1: 3046 reg |= DMA_CFG_RD_CHNL_SEL_1; 3047 break; 3048 case AR816X_REV_B0: 3049 /* FALLTHROUGH */ 3050 default: 3051 reg |= DMA_CFG_RD_CHNL_SEL_3; 3052 break; 3053 } 3054 } 3055 CSR_WRITE_4(sc, ALC_DMA_CFG, reg); 3056 3057 /* 3058 * Configure Tx/Rx MACs. 3059 * - Auto-padding for short frames. 3060 * - Enable CRC generation. 3061 * Actual reconfiguration of MAC for resolved speed/duplex 3062 * is followed after detection of link establishment. 3063 * AR813x/AR815x always does checksum computation regardless 3064 * of MAC_CFG_RXCSUM_ENB bit. Also the controller is known to 3065 * have bug in protocol field in Rx return structure so 3066 * these controllers can't handle fragmented frames. Disable 3067 * Rx checksum offloading until there is a newer controller 3068 * that has sane implementation. 3069 */ 3070 reg = MAC_CFG_TX_CRC_ENB | MAC_CFG_TX_AUTO_PAD | MAC_CFG_FULL_DUPLEX | 3071 ((MAC_CFG_PREAMBLE_DEFAULT << MAC_CFG_PREAMBLE_SHIFT) & 3072 MAC_CFG_PREAMBLE_MASK); 3073 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0 || 3074 sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8151 || 3075 sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8151_V2 || 3076 sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8152_B2) 3077 reg |= MAC_CFG_HASH_ALG_CRC32 | MAC_CFG_SPEED_MODE_SW; 3078 if ((sc->alc_flags & ALC_FLAG_FASTETHER) != 0) 3079 reg |= MAC_CFG_SPEED_10_100; 3080 else 3081 reg |= MAC_CFG_SPEED_1000; 3082 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 3083 3084 /* Set up the receive filter. */ 3085 alc_iff(sc); 3086 alc_rxvlan(sc); 3087 3088 /* Acknowledge all pending interrupts and clear it. */ 3089 CSR_WRITE_4(sc, ALC_INTR_MASK, ALC_INTRS); 3090 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0xFFFFFFFF); 3091 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0); 3092 3093 sc->alc_flags &= ~ALC_FLAG_LINK; 3094 /* Switch to the current media. */ 3095 mii = &sc->sc_miibus; 3096 mii_mediachg(mii); 3097 3098 callout_schedule(&sc->sc_tick_ch, hz); 3099 3100 ifp->if_flags |= IFF_RUNNING; 3101 ifp->if_flags &= ~IFF_OACTIVE; 3102 3103 return (0); 3104 } 3105 3106 static void 3107 alc_stop(struct ifnet *ifp, int disable) 3108 { 3109 struct alc_softc *sc = ifp->if_softc; 3110 struct alc_txdesc *txd; 3111 struct alc_rxdesc *rxd; 3112 uint32_t reg; 3113 int i; 3114 3115 callout_stop(&sc->sc_tick_ch); 3116 3117 /* 3118 * Mark the interface down and cancel the watchdog timer. 3119 */ 3120 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 3121 ifp->if_timer = 0; 3122 3123 sc->alc_flags &= ~ALC_FLAG_LINK; 3124 3125 alc_stats_update(sc); 3126 3127 mii_down(&sc->sc_miibus); 3128 3129 /* Disable interrupts. */ 3130 CSR_WRITE_4(sc, ALC_INTR_MASK, 0); 3131 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0xFFFFFFFF); 3132 3133 /* Disable DMA. */ 3134 reg = CSR_READ_4(sc, ALC_DMA_CFG); 3135 reg &= ~(DMA_CFG_CMB_ENB | DMA_CFG_SMB_ENB); 3136 reg |= DMA_CFG_SMB_DIS; 3137 CSR_WRITE_4(sc, ALC_DMA_CFG, reg); 3138 DELAY(1000); 3139 3140 /* Stop Rx/Tx MACs. */ 3141 alc_stop_mac(sc); 3142 3143 /* Disable interrupts which might be touched in taskq handler. */ 3144 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0xFFFFFFFF); 3145 3146 /* Disable L0s/L1s */ 3147 alc_aspm(sc, 0, IFM_UNKNOWN); 3148 3149 /* Reclaim Rx buffers that have been processed. */ 3150 if (sc->alc_cdata.alc_rxhead != NULL) 3151 m_freem(sc->alc_cdata.alc_rxhead); 3152 ALC_RXCHAIN_RESET(sc); 3153 /* 3154 * Free Tx/Rx mbufs still in the queues. 3155 */ 3156 for (i = 0; i < ALC_RX_RING_CNT; i++) { 3157 rxd = &sc->alc_cdata.alc_rxdesc[i]; 3158 if (rxd->rx_m != NULL) { 3159 bus_dmamap_sync(sc->sc_dmat, rxd->rx_dmamap, 0, 3160 rxd->rx_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 3161 bus_dmamap_unload(sc->sc_dmat, rxd->rx_dmamap); 3162 m_freem(rxd->rx_m); 3163 rxd->rx_m = NULL; 3164 } 3165 } 3166 for (i = 0; i < ALC_TX_RING_CNT; i++) { 3167 txd = &sc->alc_cdata.alc_txdesc[i]; 3168 if (txd->tx_m != NULL) { 3169 bus_dmamap_sync(sc->sc_dmat, txd->tx_dmamap, 0, 3170 txd->tx_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 3171 bus_dmamap_unload(sc->sc_dmat, txd->tx_dmamap); 3172 m_freem(txd->tx_m); 3173 txd->tx_m = NULL; 3174 } 3175 } 3176 } 3177 3178 static void 3179 alc_stop_mac(struct alc_softc *sc) 3180 { 3181 uint32_t reg; 3182 int i; 3183 3184 alc_stop_queue(sc); 3185 /* Disable Rx/Tx MAC. */ 3186 reg = CSR_READ_4(sc, ALC_MAC_CFG); 3187 if ((reg & (MAC_CFG_TX_ENB | MAC_CFG_RX_ENB)) != 0) { 3188 reg &= ~(MAC_CFG_TX_ENB | MAC_CFG_RX_ENB); 3189 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 3190 } 3191 for (i = ALC_TIMEOUT; i > 0; i--) { 3192 reg = CSR_READ_4(sc, ALC_IDLE_STATUS); 3193 if ((reg & (IDLE_STATUS_RXMAC | IDLE_STATUS_TXMAC)) == 0) 3194 break; 3195 DELAY(10); 3196 } 3197 if (i == 0) 3198 printf("%s: could not disable Rx/Tx MAC(0x%08x)!\n", 3199 device_xname(sc->sc_dev), reg); 3200 } 3201 3202 static void 3203 alc_start_queue(struct alc_softc *sc) 3204 { 3205 uint32_t qcfg[] = { 3206 0, 3207 RXQ_CFG_QUEUE0_ENB, 3208 RXQ_CFG_QUEUE0_ENB | RXQ_CFG_QUEUE1_ENB, 3209 RXQ_CFG_QUEUE0_ENB | RXQ_CFG_QUEUE1_ENB | RXQ_CFG_QUEUE2_ENB, 3210 RXQ_CFG_ENB 3211 }; 3212 uint32_t cfg; 3213 3214 /* Enable RxQ. */ 3215 cfg = CSR_READ_4(sc, ALC_RXQ_CFG); 3216 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 3217 cfg &= ~RXQ_CFG_ENB; 3218 cfg |= qcfg[1]; 3219 } else 3220 cfg |= RXQ_CFG_QUEUE0_ENB; 3221 CSR_WRITE_4(sc, ALC_RXQ_CFG, cfg); 3222 /* Enable TxQ. */ 3223 cfg = CSR_READ_4(sc, ALC_TXQ_CFG); 3224 cfg |= TXQ_CFG_ENB; 3225 CSR_WRITE_4(sc, ALC_TXQ_CFG, cfg); 3226 } 3227 3228 static void 3229 alc_stop_queue(struct alc_softc *sc) 3230 { 3231 uint32_t reg; 3232 int i; 3233 3234 /* Disable RxQ. */ 3235 reg = CSR_READ_4(sc, ALC_RXQ_CFG); 3236 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 3237 if ((reg & RXQ_CFG_ENB) != 0) { 3238 reg &= ~RXQ_CFG_ENB; 3239 CSR_WRITE_4(sc, ALC_RXQ_CFG, reg); 3240 } 3241 } else { 3242 if ((reg & RXQ_CFG_QUEUE0_ENB) != 0) { 3243 reg &= ~RXQ_CFG_QUEUE0_ENB; 3244 CSR_WRITE_4(sc, ALC_RXQ_CFG, reg); 3245 } 3246 } 3247 /* Disable TxQ. */ 3248 reg = CSR_READ_4(sc, ALC_TXQ_CFG); 3249 if ((reg & TXQ_CFG_ENB) != 0) { 3250 reg &= ~TXQ_CFG_ENB; 3251 CSR_WRITE_4(sc, ALC_TXQ_CFG, reg); 3252 } 3253 DELAY(40); 3254 for (i = ALC_TIMEOUT; i > 0; i--) { 3255 reg = CSR_READ_4(sc, ALC_IDLE_STATUS); 3256 if ((reg & (IDLE_STATUS_RXQ | IDLE_STATUS_TXQ)) == 0) 3257 break; 3258 DELAY(10); 3259 } 3260 if (i == 0) 3261 printf("%s: could not disable RxQ/TxQ (0x%08x)!\n", 3262 device_xname(sc->sc_dev), reg); 3263 } 3264 3265 static void 3266 alc_init_tx_ring(struct alc_softc *sc) 3267 { 3268 struct alc_ring_data *rd; 3269 struct alc_txdesc *txd; 3270 int i; 3271 3272 sc->alc_cdata.alc_tx_prod = 0; 3273 sc->alc_cdata.alc_tx_cons = 0; 3274 sc->alc_cdata.alc_tx_cnt = 0; 3275 3276 rd = &sc->alc_rdata; 3277 memset(rd->alc_tx_ring, 0, ALC_TX_RING_SZ); 3278 for (i = 0; i < ALC_TX_RING_CNT; i++) { 3279 txd = &sc->alc_cdata.alc_txdesc[i]; 3280 txd->tx_m = NULL; 3281 } 3282 3283 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_tx_ring_map, 0, 3284 sc->alc_cdata.alc_tx_ring_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 3285 } 3286 3287 static int 3288 alc_init_rx_ring(struct alc_softc *sc, bool init) 3289 { 3290 struct alc_ring_data *rd; 3291 struct alc_rxdesc *rxd; 3292 int i; 3293 3294 sc->alc_cdata.alc_rx_cons = ALC_RX_RING_CNT - 1; 3295 rd = &sc->alc_rdata; 3296 memset(rd->alc_rx_ring, 0, ALC_RX_RING_SZ); 3297 for (i = 0; i < ALC_RX_RING_CNT; i++) { 3298 rxd = &sc->alc_cdata.alc_rxdesc[i]; 3299 rxd->rx_m = NULL; 3300 rxd->rx_desc = &rd->alc_rx_ring[i]; 3301 if (alc_newbuf(sc, rxd, init) != 0) 3302 return (ENOBUFS); 3303 } 3304 3305 /* 3306 * Since controller does not update Rx descriptors, driver 3307 * does have to read Rx descriptors back so BUS_DMASYNC_PREWRITE 3308 * is enough to ensure coherence. 3309 */ 3310 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_rx_ring_map, 0, 3311 sc->alc_cdata.alc_rx_ring_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 3312 /* Let controller know availability of new Rx buffers. */ 3313 CSR_WRITE_4(sc, ALC_MBOX_RD0_PROD_IDX, sc->alc_cdata.alc_rx_cons); 3314 3315 return (0); 3316 } 3317 3318 static void 3319 alc_init_rr_ring(struct alc_softc *sc) 3320 { 3321 struct alc_ring_data *rd; 3322 3323 sc->alc_cdata.alc_rr_cons = 0; 3324 ALC_RXCHAIN_RESET(sc); 3325 3326 rd = &sc->alc_rdata; 3327 memset(rd->alc_rr_ring, 0, ALC_RR_RING_SZ); 3328 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_rr_ring_map, 0, 3329 sc->alc_cdata.alc_rr_ring_map->dm_mapsize, 3330 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3331 } 3332 3333 static void 3334 alc_init_cmb(struct alc_softc *sc) 3335 { 3336 struct alc_ring_data *rd; 3337 3338 rd = &sc->alc_rdata; 3339 memset(rd->alc_cmb, 0, ALC_CMB_SZ); 3340 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_cmb_map, 0, 3341 sc->alc_cdata.alc_cmb_map->dm_mapsize, 3342 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3343 } 3344 3345 static void 3346 alc_init_smb(struct alc_softc *sc) 3347 { 3348 struct alc_ring_data *rd; 3349 3350 rd = &sc->alc_rdata; 3351 memset(rd->alc_smb, 0, ALC_SMB_SZ); 3352 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_smb_map, 0, 3353 sc->alc_cdata.alc_smb_map->dm_mapsize, 3354 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3355 } 3356 3357 static void 3358 alc_rxvlan(struct alc_softc *sc) 3359 { 3360 uint32_t reg; 3361 3362 reg = CSR_READ_4(sc, ALC_MAC_CFG); 3363 if (sc->sc_ec.ec_capenable & ETHERCAP_VLAN_HWTAGGING) 3364 reg |= MAC_CFG_VLAN_TAG_STRIP; 3365 else 3366 reg &= ~MAC_CFG_VLAN_TAG_STRIP; 3367 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 3368 } 3369 3370 static void 3371 alc_iff(struct alc_softc *sc) 3372 { 3373 struct ethercom *ec = &sc->sc_ec; 3374 struct ifnet *ifp = &ec->ec_if; 3375 struct ether_multi *enm; 3376 struct ether_multistep step; 3377 uint32_t crc; 3378 uint32_t mchash[2]; 3379 uint32_t rxcfg; 3380 3381 rxcfg = CSR_READ_4(sc, ALC_MAC_CFG); 3382 rxcfg &= ~(MAC_CFG_ALLMULTI | MAC_CFG_BCAST | MAC_CFG_PROMISC); 3383 ifp->if_flags &= ~IFF_ALLMULTI; 3384 3385 /* 3386 * Always accept broadcast frames. 3387 */ 3388 rxcfg |= MAC_CFG_BCAST; 3389 3390 if (ifp->if_flags & IFF_PROMISC || ec->ec_multicnt > 0) { 3391 ifp->if_flags |= IFF_ALLMULTI; 3392 if (ifp->if_flags & IFF_PROMISC) 3393 rxcfg |= MAC_CFG_PROMISC; 3394 else 3395 rxcfg |= MAC_CFG_ALLMULTI; 3396 mchash[0] = mchash[1] = 0xFFFFFFFF; 3397 } else { 3398 /* Program new filter. */ 3399 memset(mchash, 0, sizeof(mchash)); 3400 3401 ETHER_FIRST_MULTI(step, ec, enm); 3402 while (enm != NULL) { 3403 crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 3404 mchash[crc >> 31] |= 1 << ((crc >> 26) & 0x1f); 3405 ETHER_NEXT_MULTI(step, enm); 3406 } 3407 } 3408 3409 CSR_WRITE_4(sc, ALC_MAR0, mchash[0]); 3410 CSR_WRITE_4(sc, ALC_MAR1, mchash[1]); 3411 CSR_WRITE_4(sc, ALC_MAC_CFG, rxcfg); 3412 } 3413 3414 MODULE(MODULE_CLASS_DRIVER, if_alc, "pci"); 3415 3416 #ifdef _MODULE 3417 #include "ioconf.c" 3418 #endif 3419 3420 static int 3421 if_alc_modcmd(modcmd_t cmd, void *opaque) 3422 { 3423 int error = 0; 3424 3425 switch (cmd) { 3426 case MODULE_CMD_INIT: 3427 #ifdef _MODULE 3428 error = config_init_component(cfdriver_ioconf_if_alc, 3429 cfattach_ioconf_if_alc, cfdata_ioconf_if_alc); 3430 #endif 3431 return error; 3432 case MODULE_CMD_FINI: 3433 #ifdef _MODULE 3434 error = config_fini_component(cfdriver_ioconf_if_alc, 3435 cfattach_ioconf_if_alc, cfdata_ioconf_if_alc); 3436 #endif 3437 return error; 3438 default: 3439 return ENOTTY; 3440 } 3441 } 3442
Indexes created Fri Sep 26 20:09:58 GMT 2025