if_alc.c revision 1.25
1 /* $NetBSD: if_alc.c,v 1.25 2017/09/26 07:42:06 knakahara Exp $ */ 2 /* $OpenBSD: if_alc.c,v 1.1 2009/08/08 09:31:13 kevlo Exp $ */ 3 /*- 4 * Copyright (c) 2009, Pyun YongHyeon <yongari (at) FreeBSD.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice unmodified, this list of conditions, and the following 12 * disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 /* Driver for Atheros AR813x/AR815x PCIe Ethernet. */ 31 32 #ifdef _KERNEL_OPT 33 #include "vlan.h" 34 #endif 35 36 #include <sys/param.h> 37 #include <sys/proc.h> 38 #include <sys/endian.h> 39 #include <sys/systm.h> 40 #include <sys/types.h> 41 #include <sys/sockio.h> 42 #include <sys/mbuf.h> 43 #include <sys/queue.h> 44 #include <sys/kernel.h> 45 #include <sys/device.h> 46 #include <sys/callout.h> 47 #include <sys/socket.h> 48 #include <sys/module.h> 49 50 #include <sys/bus.h> 51 52 #include <net/if.h> 53 #include <net/if_dl.h> 54 #include <net/if_llc.h> 55 #include <net/if_media.h> 56 #include <net/if_ether.h> 57 58 #include <net/bpf.h> 59 60 #ifdef INET 61 #include <netinet/in.h> 62 #include <netinet/in_systm.h> 63 #include <netinet/in_var.h> 64 #include <netinet/ip.h> 65 #endif 66 67 #include <net/if_types.h> 68 #include <net/if_vlanvar.h> 69 70 #include <net/bpf.h> 71 72 #include <dev/mii/mii.h> 73 #include <dev/mii/miivar.h> 74 75 #include <dev/pci/pcireg.h> 76 #include <dev/pci/pcivar.h> 77 #include <dev/pci/pcidevs.h> 78 79 #include <dev/pci/if_alcreg.h> 80 81 /* 82 * Devices supported by this driver. 83 */ 84 static struct alc_ident alc_ident_table[] = { 85 { PCI_VENDOR_ATTANSIC, PCI_PRODUCT_ATTANSIC_AR8131, 9 * 1024, 86 "Atheros AR8131 PCIe Gigabit Ethernet" }, 87 { PCI_VENDOR_ATTANSIC, PCI_PRODUCT_ATTANSIC_AR8132, 9 * 1024, 88 "Atheros AR8132 PCIe Fast Ethernet" }, 89 { PCI_VENDOR_ATTANSIC, PCI_PRODUCT_ATTANSIC_AR8151, 6 * 1024, 90 "Atheros AR8151 v1.0 PCIe Gigabit Ethernet" }, 91 { PCI_VENDOR_ATTANSIC, PCI_PRODUCT_ATTANSIC_AR8151_V2, 6 * 1024, 92 "Atheros AR8151 v2.0 PCIe Gigabit Ethernet" }, 93 { PCI_VENDOR_ATTANSIC, PCI_PRODUCT_ATTANSIC_AR8152_B, 6 * 1024, 94 "Atheros AR8152 v1.1 PCIe Fast Ethernet" }, 95 { PCI_VENDOR_ATTANSIC, PCI_PRODUCT_ATTANSIC_AR8152_B2, 6 * 1024, 96 "Atheros AR8152 v2.0 PCIe Fast Ethernet" }, 97 { PCI_VENDOR_ATTANSIC, PCI_PRODUCT_ATTANSIC_AR8161, 9 * 1024, 98 "Atheros AR8161 PCIe Gigabit Ethernet" }, 99 { PCI_VENDOR_ATTANSIC, PCI_PRODUCT_ATTANSIC_AR8162, 9 * 1024, 100 "Atheros AR8162 PCIe Fast Ethernet" }, 101 { PCI_VENDOR_ATTANSIC, PCI_PRODUCT_ATTANSIC_AR8171, 9 * 1024, 102 "Atheros AR8171 PCIe Gigabit Ethernet" }, 103 { PCI_VENDOR_ATTANSIC, PCI_PRODUCT_ATTANSIC_AR8172, 9 * 1024, 104 "Atheros AR8172 PCIe Fast Ethernet" }, 105 { PCI_VENDOR_ATTANSIC, PCI_PRODUCT_ATTANSIC_E2200, 9 * 1024, 106 "Killer E2200 Gigabit Ethernet" }, 107 { 0, 0, 0, NULL }, 108 }; 109 110 static int alc_match(device_t, cfdata_t, void *); 111 static void alc_attach(device_t, device_t, void *); 112 static int alc_detach(device_t, int); 113 114 static int alc_init(struct ifnet *); 115 static int alc_init_backend(struct ifnet *, bool); 116 static void alc_start(struct ifnet *); 117 static int alc_ioctl(struct ifnet *, u_long, void *); 118 static void alc_watchdog(struct ifnet *); 119 static int alc_mediachange(struct ifnet *); 120 static void alc_mediastatus(struct ifnet *, struct ifmediareq *); 121 122 static void alc_aspm(struct alc_softc *, int, int); 123 static void alc_aspm_813x(struct alc_softc *, int); 124 static void alc_aspm_816x(struct alc_softc *, int); 125 static void alc_disable_l0s_l1(struct alc_softc *); 126 static int alc_dma_alloc(struct alc_softc *); 127 static void alc_dma_free(struct alc_softc *); 128 static void alc_dsp_fixup(struct alc_softc *, int); 129 static int alc_encap(struct alc_softc *, struct mbuf **); 130 static struct alc_ident * 131 alc_find_ident(struct pci_attach_args *); 132 static void alc_get_macaddr(struct alc_softc *); 133 static void alc_get_macaddr_813x(struct alc_softc *); 134 static void alc_get_macaddr_816x(struct alc_softc *); 135 static void alc_get_macaddr_par(struct alc_softc *); 136 static void alc_init_cmb(struct alc_softc *); 137 static void alc_init_rr_ring(struct alc_softc *); 138 static int alc_init_rx_ring(struct alc_softc *, bool); 139 static void alc_init_smb(struct alc_softc *); 140 static void alc_init_tx_ring(struct alc_softc *); 141 static int alc_intr(void *); 142 static void alc_mac_config(struct alc_softc *); 143 static uint32_t alc_mii_readreg_813x(struct alc_softc *, int, int); 144 static uint32_t alc_mii_readreg_816x(struct alc_softc *, int, int); 145 static void alc_mii_writereg_813x(struct alc_softc *, int, int, int); 146 static void alc_mii_writereg_816x(struct alc_softc *, int, int, int); 147 static int alc_miibus_readreg(device_t, int, int); 148 static void alc_miibus_statchg(struct ifnet *); 149 static void alc_miibus_writereg(device_t, int, int, int); 150 static uint32_t alc_miidbg_readreg(struct alc_softc *, int); 151 static void alc_miidbg_writereg(struct alc_softc *, int, int); 152 static uint32_t alc_miiext_readreg(struct alc_softc *, int, int); 153 static uint32_t alc_miiext_writereg(struct alc_softc *, int, int, int); 154 static int alc_newbuf(struct alc_softc *, struct alc_rxdesc *, bool); 155 static void alc_phy_down(struct alc_softc *); 156 static void alc_phy_reset(struct alc_softc *); 157 static void alc_phy_reset_813x(struct alc_softc *); 158 static void alc_phy_reset_816x(struct alc_softc *); 159 static void alc_reset(struct alc_softc *); 160 static void alc_rxeof(struct alc_softc *, struct rx_rdesc *); 161 static int alc_rxintr(struct alc_softc *); 162 static void alc_iff(struct alc_softc *); 163 static void alc_rxvlan(struct alc_softc *); 164 static void alc_start_queue(struct alc_softc *); 165 static void alc_stats_clear(struct alc_softc *); 166 static void alc_stats_update(struct alc_softc *); 167 static void alc_stop(struct ifnet *, int); 168 static void alc_stop_mac(struct alc_softc *); 169 static void alc_stop_queue(struct alc_softc *); 170 static void alc_tick(void *); 171 static void alc_txeof(struct alc_softc *); 172 173 uint32_t alc_dma_burst[] = { 128, 256, 512, 1024, 2048, 4096, 0 }; 174 175 CFATTACH_DECL_NEW(alc, sizeof(struct alc_softc), 176 alc_match, alc_attach, alc_detach, NULL); 177 178 int alcdebug = 0; 179 #define DPRINTF(x) do { if (alcdebug) printf x; } while (0) 180 181 #define ETHER_ALIGN 2 182 #define ALC_CSUM_FEATURES (M_CSUM_TCPv4 | M_CSUM_UDPv4) 183 184 static int 185 alc_miibus_readreg(device_t dev, int phy, int reg) 186 { 187 struct alc_softc *sc = device_private(dev); 188 int v; 189 190 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 191 v = alc_mii_readreg_816x(sc, phy, reg); 192 else 193 v = alc_mii_readreg_813x(sc, phy, reg); 194 return (v); 195 } 196 197 static uint32_t 198 alc_mii_readreg_813x(struct alc_softc *sc, int phy, int reg) 199 { 200 uint32_t v; 201 int i; 202 203 if (phy != sc->alc_phyaddr) 204 return (0); 205 206 /* 207 * For AR8132 fast ethernet controller, do not report 1000baseT 208 * capability to mii(4). Even though AR8132 uses the same 209 * model/revision number of F1 gigabit PHY, the PHY has no 210 * ability to establish 1000baseT link. 211 */ 212 if ((sc->alc_flags & ALC_FLAG_FASTETHER) != 0 && 213 reg == MII_EXTSR) 214 return 0; 215 216 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ | 217 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); 218 for (i = ALC_PHY_TIMEOUT; i > 0; i--) { 219 DELAY(5); 220 v = CSR_READ_4(sc, ALC_MDIO); 221 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) 222 break; 223 } 224 225 if (i == 0) { 226 printf("%s: phy read timeout: phy %d, reg %d\n", 227 device_xname(sc->sc_dev), phy, reg); 228 return (0); 229 } 230 231 return ((v & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT); 232 } 233 234 static uint32_t 235 alc_mii_readreg_816x(struct alc_softc *sc, int phy, int reg) 236 { 237 uint32_t clk, v; 238 int i; 239 240 if (phy != sc->alc_phyaddr) 241 return (0); 242 243 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) 244 clk = MDIO_CLK_25_128; 245 else 246 clk = MDIO_CLK_25_4; 247 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ | 248 MDIO_SUP_PREAMBLE | clk | MDIO_REG_ADDR(reg)); 249 for (i = ALC_PHY_TIMEOUT; i > 0; i--) { 250 DELAY(5); 251 v = CSR_READ_4(sc, ALC_MDIO); 252 if ((v & MDIO_OP_BUSY) == 0) 253 break; 254 } 255 256 if (i == 0) { 257 printf("%s: phy read timeout: phy %d, reg %d\n", 258 device_xname(sc->sc_dev), phy, reg); 259 return (0); 260 } 261 262 return ((v & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT); 263 } 264 265 static void 266 alc_miibus_writereg(device_t dev, int phy, int reg, int val) 267 { 268 struct alc_softc *sc = device_private(dev); 269 270 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 271 alc_mii_writereg_816x(sc, phy, reg, val); 272 else 273 alc_mii_writereg_813x(sc, phy, reg, val); 274 275 return; 276 } 277 278 static void 279 alc_mii_writereg_813x(struct alc_softc *sc, int phy, int reg, int val) 280 { 281 uint32_t v; 282 int i; 283 284 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE | 285 (val & MDIO_DATA_MASK) << MDIO_DATA_SHIFT | 286 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); 287 for (i = ALC_PHY_TIMEOUT; i > 0; i--) { 288 DELAY(5); 289 v = CSR_READ_4(sc, ALC_MDIO); 290 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) 291 break; 292 } 293 294 if (i == 0) 295 printf("%s: phy write timeout: phy %d, reg %d\n", 296 device_xname(sc->sc_dev), phy, reg); 297 298 return; 299 } 300 301 static void 302 alc_mii_writereg_816x(struct alc_softc *sc, int phy, int reg, int val) 303 { 304 uint32_t clk, v; 305 int i; 306 307 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) 308 clk = MDIO_CLK_25_128; 309 else 310 clk = MDIO_CLK_25_4; 311 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE | 312 ((val & MDIO_DATA_MASK) << MDIO_DATA_SHIFT) | MDIO_REG_ADDR(reg) | 313 MDIO_SUP_PREAMBLE | clk); 314 for (i = ALC_PHY_TIMEOUT; i > 0; i--) { 315 DELAY(5); 316 v = CSR_READ_4(sc, ALC_MDIO); 317 if ((v & MDIO_OP_BUSY) == 0) 318 break; 319 } 320 321 if (i == 0) 322 printf("%s: phy write timeout: phy %d, reg %d\n", 323 device_xname(sc->sc_dev), phy, reg); 324 325 return; 326 } 327 328 static void 329 alc_miibus_statchg(struct ifnet *ifp) 330 { 331 struct alc_softc *sc = ifp->if_softc; 332 struct mii_data *mii = &sc->sc_miibus; 333 uint32_t reg; 334 335 if ((ifp->if_flags & IFF_RUNNING) == 0) 336 return; 337 338 sc->alc_flags &= ~ALC_FLAG_LINK; 339 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 340 (IFM_ACTIVE | IFM_AVALID)) { 341 switch (IFM_SUBTYPE(mii->mii_media_active)) { 342 case IFM_10_T: 343 case IFM_100_TX: 344 sc->alc_flags |= ALC_FLAG_LINK; 345 break; 346 case IFM_1000_T: 347 if ((sc->alc_flags & ALC_FLAG_FASTETHER) == 0) 348 sc->alc_flags |= ALC_FLAG_LINK; 349 break; 350 default: 351 break; 352 } 353 } 354 /* Stop Rx/Tx MACs. */ 355 alc_stop_mac(sc); 356 357 /* Program MACs with resolved speed/duplex/flow-control. */ 358 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) { 359 alc_start_queue(sc); 360 alc_mac_config(sc); 361 /* Re-enable Tx/Rx MACs. */ 362 reg = CSR_READ_4(sc, ALC_MAC_CFG); 363 reg |= MAC_CFG_TX_ENB | MAC_CFG_RX_ENB; 364 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 365 } 366 alc_aspm(sc, 0, IFM_SUBTYPE(mii->mii_media_active)); 367 alc_dsp_fixup(sc, IFM_SUBTYPE(mii->mii_media_active)); 368 } 369 370 static uint32_t 371 alc_miidbg_readreg(struct alc_softc *sc, int reg) 372 { 373 374 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, ALC_MII_DBG_ADDR, 375 reg); 376 return (alc_miibus_readreg(sc->sc_dev, sc->alc_phyaddr, 377 ALC_MII_DBG_DATA)); 378 } 379 380 static void 381 alc_miidbg_writereg(struct alc_softc *sc, int reg, int val) 382 { 383 384 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, ALC_MII_DBG_ADDR, 385 reg); 386 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, ALC_MII_DBG_DATA, val); 387 388 return; 389 } 390 391 static uint32_t 392 alc_miiext_readreg(struct alc_softc *sc, int devaddr, int reg) 393 { 394 uint32_t clk, v; 395 int i; 396 397 CSR_WRITE_4(sc, ALC_EXT_MDIO, EXT_MDIO_REG(reg) | 398 EXT_MDIO_DEVADDR(devaddr)); 399 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) 400 clk = MDIO_CLK_25_128; 401 else 402 clk = MDIO_CLK_25_4; 403 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ | 404 MDIO_SUP_PREAMBLE | clk | MDIO_MODE_EXT); 405 for (i = ALC_PHY_TIMEOUT; i > 0; i--) { 406 DELAY(5); 407 v = CSR_READ_4(sc, ALC_MDIO); 408 if ((v & MDIO_OP_BUSY) == 0) 409 break; 410 } 411 412 if (i == 0) { 413 printf("%s: phy ext read timeout: %d\n", 414 device_xname(sc->sc_dev), reg); 415 return (0); 416 } 417 418 return ((v & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT); 419 } 420 421 static uint32_t 422 alc_miiext_writereg(struct alc_softc *sc, int devaddr, int reg, int val) 423 { 424 uint32_t clk, v; 425 int i; 426 427 CSR_WRITE_4(sc, ALC_EXT_MDIO, EXT_MDIO_REG(reg) | 428 EXT_MDIO_DEVADDR(devaddr)); 429 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) 430 clk = MDIO_CLK_25_128; 431 else 432 clk = MDIO_CLK_25_4; 433 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE | 434 ((val & MDIO_DATA_MASK) << MDIO_DATA_SHIFT) | 435 MDIO_SUP_PREAMBLE | clk | MDIO_MODE_EXT); 436 for (i = ALC_PHY_TIMEOUT; i > 0; i--) { 437 DELAY(5); 438 v = CSR_READ_4(sc, ALC_MDIO); 439 if ((v & MDIO_OP_BUSY) == 0) 440 break; 441 } 442 443 if (i == 0) { 444 printf("%s: phy ext write timeout: reg %d\n", 445 device_xname(sc->sc_dev), reg); 446 return (0); 447 } 448 449 return (0); 450 } 451 452 static void 453 alc_dsp_fixup(struct alc_softc *sc, int media) 454 { 455 uint16_t agc, len, val; 456 457 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 458 return; 459 if (AR816X_REV(sc->alc_rev) >= AR816X_REV_C0) 460 return; 461 462 /* 463 * Vendor PHY magic. 464 * 1000BT/AZ, wrong cable length 465 */ 466 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) { 467 len = alc_miiext_readreg(sc, MII_EXT_PCS, MII_EXT_CLDCTL6); 468 len = (len >> EXT_CLDCTL6_CAB_LEN_SHIFT) & 469 EXT_CLDCTL6_CAB_LEN_MASK; 470 /* XXX: used to be (alc >> shift) & mask which is 0 */ 471 agc = alc_miidbg_readreg(sc, MII_DBG_AGC) & DBG_AGC_2_VGA_MASK; 472 agc >>= DBG_AGC_2_VGA_SHIFT; 473 if ((media == IFM_1000_T && len > EXT_CLDCTL6_CAB_LEN_SHORT1G && 474 agc > DBG_AGC_LONG1G_LIMT) || 475 (media == IFM_100_TX && len > DBG_AGC_LONG100M_LIMT && 476 agc > DBG_AGC_LONG1G_LIMT)) { 477 alc_miidbg_writereg(sc, MII_DBG_AZ_ANADECT, 478 DBG_AZ_ANADECT_LONG); 479 val = alc_miiext_readreg(sc, MII_EXT_ANEG, 480 MII_EXT_ANEG_AFE); 481 val |= ANEG_AFEE_10BT_100M_TH; 482 alc_miiext_writereg(sc, MII_EXT_ANEG, MII_EXT_ANEG_AFE, 483 val); 484 } else { 485 alc_miidbg_writereg(sc, MII_DBG_AZ_ANADECT, 486 DBG_AZ_ANADECT_DEFAULT); 487 val = alc_miiext_readreg(sc, MII_EXT_ANEG, 488 MII_EXT_ANEG_AFE); 489 val &= ~ANEG_AFEE_10BT_100M_TH; 490 alc_miiext_writereg(sc, MII_EXT_ANEG, MII_EXT_ANEG_AFE, 491 val); 492 } 493 if ((sc->alc_flags & ALC_FLAG_LINK_WAR) != 0 && 494 AR816X_REV(sc->alc_rev) == AR816X_REV_B0) { 495 if (media == IFM_1000_T) { 496 /* 497 * Giga link threshold, raise the tolerance of 498 * noise 50%. 499 */ 500 val = alc_miidbg_readreg(sc, MII_DBG_MSE20DB); 501 val &= ~DBG_MSE20DB_TH_MASK; 502 val |= (DBG_MSE20DB_TH_HI << 503 DBG_MSE20DB_TH_SHIFT); 504 alc_miidbg_writereg(sc, MII_DBG_MSE20DB, val); 505 } else if (media == IFM_100_TX) 506 alc_miidbg_writereg(sc, MII_DBG_MSE16DB, 507 DBG_MSE16DB_UP); 508 } 509 } else { 510 val = alc_miiext_readreg(sc, MII_EXT_ANEG, MII_EXT_ANEG_AFE); 511 val &= ~ANEG_AFEE_10BT_100M_TH; 512 alc_miiext_writereg(sc, MII_EXT_ANEG, MII_EXT_ANEG_AFE, val); 513 if ((sc->alc_flags & ALC_FLAG_LINK_WAR) != 0 && 514 AR816X_REV(sc->alc_rev) == AR816X_REV_B0) { 515 alc_miidbg_writereg(sc, MII_DBG_MSE16DB, 516 DBG_MSE16DB_DOWN); 517 val = alc_miidbg_readreg(sc, MII_DBG_MSE20DB); 518 val &= ~DBG_MSE20DB_TH_MASK; 519 val |= (DBG_MSE20DB_TH_DEFAULT << DBG_MSE20DB_TH_SHIFT); 520 alc_miidbg_writereg(sc, MII_DBG_MSE20DB, val); 521 } 522 } 523 } 524 525 static void 526 alc_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 527 { 528 struct alc_softc *sc = ifp->if_softc; 529 struct mii_data *mii = &sc->sc_miibus; 530 531 if ((ifp->if_flags & IFF_UP) == 0) 532 return; 533 534 mii_pollstat(mii); 535 ifmr->ifm_status = mii->mii_media_status; 536 ifmr->ifm_active = mii->mii_media_active; 537 } 538 539 static int 540 alc_mediachange(struct ifnet *ifp) 541 { 542 struct alc_softc *sc = ifp->if_softc; 543 struct mii_data *mii = &sc->sc_miibus; 544 int error; 545 546 if (mii->mii_instance != 0) { 547 struct mii_softc *miisc; 548 549 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 550 mii_phy_reset(miisc); 551 } 552 error = mii_mediachg(mii); 553 554 return (error); 555 } 556 557 static struct alc_ident * 558 alc_find_ident(struct pci_attach_args *pa) 559 { 560 struct alc_ident *ident; 561 uint16_t vendor, devid; 562 563 vendor = PCI_VENDOR(pa->pa_id); 564 devid = PCI_PRODUCT(pa->pa_id); 565 for (ident = alc_ident_table; ident->name != NULL; ident++) { 566 if (vendor == ident->vendorid && devid == ident->deviceid) 567 return (ident); 568 } 569 570 return (NULL); 571 } 572 573 static int 574 alc_match(device_t dev, cfdata_t match, void *aux) 575 { 576 struct pci_attach_args *pa = aux; 577 578 return alc_find_ident(pa) != NULL; 579 } 580 581 static void 582 alc_get_macaddr(struct alc_softc *sc) 583 { 584 585 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 586 alc_get_macaddr_816x(sc); 587 else 588 alc_get_macaddr_813x(sc); 589 } 590 591 static void 592 alc_get_macaddr_813x(struct alc_softc *sc) 593 { 594 uint32_t opt; 595 uint16_t val; 596 int eeprom, i; 597 598 eeprom = 0; 599 opt = CSR_READ_4(sc, ALC_OPT_CFG); 600 if ((CSR_READ_4(sc, ALC_MASTER_CFG) & MASTER_OTP_SEL) != 0 && 601 (CSR_READ_4(sc, ALC_TWSI_DEBUG) & TWSI_DEBUG_DEV_EXIST) != 0) { 602 /* 603 * EEPROM found, let TWSI reload EEPROM configuration. 604 * This will set ethernet address of controller. 605 */ 606 eeprom++; 607 switch (sc->alc_ident->deviceid) { 608 case PCI_PRODUCT_ATTANSIC_AR8131: 609 case PCI_PRODUCT_ATTANSIC_AR8132: 610 if ((opt & OPT_CFG_CLK_ENB) == 0) { 611 opt |= OPT_CFG_CLK_ENB; 612 CSR_WRITE_4(sc, ALC_OPT_CFG, opt); 613 CSR_READ_4(sc, ALC_OPT_CFG); 614 DELAY(1000); 615 } 616 break; 617 case PCI_PRODUCT_ATTANSIC_AR8151: 618 case PCI_PRODUCT_ATTANSIC_AR8151_V2: 619 case PCI_PRODUCT_ATTANSIC_AR8152_B: 620 case PCI_PRODUCT_ATTANSIC_AR8152_B2: 621 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 622 ALC_MII_DBG_ADDR, 0x00); 623 val = alc_miibus_readreg(sc->sc_dev, sc->alc_phyaddr, 624 ALC_MII_DBG_DATA); 625 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 626 ALC_MII_DBG_DATA, val & 0xFF7F); 627 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 628 ALC_MII_DBG_ADDR, 0x3B); 629 val = alc_miibus_readreg(sc->sc_dev, sc->alc_phyaddr, 630 ALC_MII_DBG_DATA); 631 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 632 ALC_MII_DBG_DATA, val | 0x0008); 633 DELAY(20); 634 break; 635 } 636 637 CSR_WRITE_4(sc, ALC_LTSSM_ID_CFG, 638 CSR_READ_4(sc, ALC_LTSSM_ID_CFG) & ~LTSSM_ID_WRO_ENB); 639 CSR_WRITE_4(sc, ALC_WOL_CFG, 0); 640 CSR_READ_4(sc, ALC_WOL_CFG); 641 642 CSR_WRITE_4(sc, ALC_TWSI_CFG, CSR_READ_4(sc, ALC_TWSI_CFG) | 643 TWSI_CFG_SW_LD_START); 644 for (i = 100; i > 0; i--) { 645 DELAY(1000); 646 if ((CSR_READ_4(sc, ALC_TWSI_CFG) & 647 TWSI_CFG_SW_LD_START) == 0) 648 break; 649 } 650 if (i == 0) 651 printf("%s: reloading EEPROM timeout!\n", 652 device_xname(sc->sc_dev)); 653 } else { 654 if (alcdebug) 655 printf("%s: EEPROM not found!\n", device_xname(sc->sc_dev)); 656 } 657 if (eeprom != 0) { 658 switch (sc->alc_ident->deviceid) { 659 case PCI_PRODUCT_ATTANSIC_AR8131: 660 case PCI_PRODUCT_ATTANSIC_AR8132: 661 if ((opt & OPT_CFG_CLK_ENB) != 0) { 662 opt &= ~OPT_CFG_CLK_ENB; 663 CSR_WRITE_4(sc, ALC_OPT_CFG, opt); 664 CSR_READ_4(sc, ALC_OPT_CFG); 665 DELAY(1000); 666 } 667 break; 668 case PCI_PRODUCT_ATTANSIC_AR8151: 669 case PCI_PRODUCT_ATTANSIC_AR8151_V2: 670 case PCI_PRODUCT_ATTANSIC_AR8152_B: 671 case PCI_PRODUCT_ATTANSIC_AR8152_B2: 672 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 673 ALC_MII_DBG_ADDR, 0x00); 674 val = alc_miibus_readreg(sc->sc_dev, sc->alc_phyaddr, 675 ALC_MII_DBG_DATA); 676 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 677 ALC_MII_DBG_DATA, val | 0x0080); 678 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 679 ALC_MII_DBG_ADDR, 0x3B); 680 val = alc_miibus_readreg(sc->sc_dev, sc->alc_phyaddr, 681 ALC_MII_DBG_DATA); 682 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 683 ALC_MII_DBG_DATA, val & 0xFFF7); 684 DELAY(20); 685 break; 686 } 687 } 688 689 alc_get_macaddr_par(sc); 690 } 691 692 static void 693 alc_get_macaddr_816x(struct alc_softc *sc) 694 { 695 uint32_t reg; 696 int i, reloaded; 697 698 reloaded = 0; 699 /* Try to reload station address via TWSI. */ 700 for (i = 100; i > 0; i--) { 701 reg = CSR_READ_4(sc, ALC_SLD); 702 if ((reg & (SLD_PROGRESS | SLD_START)) == 0) 703 break; 704 DELAY(1000); 705 } 706 if (i != 0) { 707 CSR_WRITE_4(sc, ALC_SLD, reg | SLD_START); 708 for (i = 100; i > 0; i--) { 709 DELAY(1000); 710 reg = CSR_READ_4(sc, ALC_SLD); 711 if ((reg & SLD_START) == 0) 712 break; 713 } 714 if (i != 0) 715 reloaded++; 716 else if (alcdebug) 717 printf("%s: reloading station address via TWSI timed out!\n", 718 device_xname(sc->sc_dev)); 719 } 720 721 /* Try to reload station address from EEPROM or FLASH. */ 722 if (reloaded == 0) { 723 reg = CSR_READ_4(sc, ALC_EEPROM_LD); 724 if ((reg & (EEPROM_LD_EEPROM_EXIST | 725 EEPROM_LD_FLASH_EXIST)) != 0) { 726 for (i = 100; i > 0; i--) { 727 reg = CSR_READ_4(sc, ALC_EEPROM_LD); 728 if ((reg & (EEPROM_LD_PROGRESS | 729 EEPROM_LD_START)) == 0) 730 break; 731 DELAY(1000); 732 } 733 if (i != 0) { 734 CSR_WRITE_4(sc, ALC_EEPROM_LD, reg | 735 EEPROM_LD_START); 736 for (i = 100; i > 0; i--) { 737 DELAY(1000); 738 reg = CSR_READ_4(sc, ALC_EEPROM_LD); 739 if ((reg & EEPROM_LD_START) == 0) 740 break; 741 } 742 } else if (alcdebug) 743 printf("%s: reloading EEPROM/FLASH timed out!\n", 744 device_xname(sc->sc_dev)); 745 } 746 } 747 748 alc_get_macaddr_par(sc); 749 } 750 751 752 static void 753 alc_get_macaddr_par(struct alc_softc *sc) 754 { 755 uint32_t ea[2]; 756 757 ea[0] = CSR_READ_4(sc, ALC_PAR0); 758 ea[1] = CSR_READ_4(sc, ALC_PAR1); 759 sc->alc_eaddr[0] = (ea[1] >> 8) & 0xFF; 760 sc->alc_eaddr[1] = (ea[1] >> 0) & 0xFF; 761 sc->alc_eaddr[2] = (ea[0] >> 24) & 0xFF; 762 sc->alc_eaddr[3] = (ea[0] >> 16) & 0xFF; 763 sc->alc_eaddr[4] = (ea[0] >> 8) & 0xFF; 764 sc->alc_eaddr[5] = (ea[0] >> 0) & 0xFF; 765 } 766 767 static void 768 alc_disable_l0s_l1(struct alc_softc *sc) 769 { 770 uint32_t pmcfg; 771 772 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 773 /* Another magic from vendor. */ 774 pmcfg = CSR_READ_4(sc, ALC_PM_CFG); 775 pmcfg &= ~(PM_CFG_L1_ENTRY_TIMER_MASK | PM_CFG_CLK_SWH_L1 | 776 PM_CFG_ASPM_L0S_ENB | PM_CFG_ASPM_L1_ENB | 777 PM_CFG_MAC_ASPM_CHK | PM_CFG_SERDES_PD_EX_L1); 778 pmcfg |= PM_CFG_SERDES_BUDS_RX_L1_ENB | 779 PM_CFG_SERDES_PLL_L1_ENB | PM_CFG_SERDES_L1_ENB; 780 CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg); 781 } 782 } 783 784 static void 785 alc_phy_reset(struct alc_softc *sc) 786 { 787 788 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 789 alc_phy_reset_816x(sc); 790 else 791 alc_phy_reset_813x(sc); 792 } 793 794 static void 795 alc_phy_reset_813x(struct alc_softc *sc) 796 { 797 uint16_t data; 798 799 /* Reset magic from Linux. */ 800 CSR_WRITE_2(sc, ALC_GPHY_CFG, GPHY_CFG_SEL_ANA_RESET); 801 CSR_READ_2(sc, ALC_GPHY_CFG); 802 DELAY(10 * 1000); 803 804 CSR_WRITE_2(sc, ALC_GPHY_CFG, GPHY_CFG_EXT_RESET | 805 GPHY_CFG_SEL_ANA_RESET); 806 CSR_READ_2(sc, ALC_GPHY_CFG); 807 DELAY(10 * 1000); 808 809 /* DSP fixup, Vendor magic. */ 810 if (sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8152_B) { 811 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 812 ALC_MII_DBG_ADDR, 0x000A); 813 data = alc_miibus_readreg(sc->sc_dev, sc->alc_phyaddr, 814 ALC_MII_DBG_DATA); 815 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 816 ALC_MII_DBG_DATA, data & 0xDFFF); 817 } 818 if (sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8151 || 819 sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8151_V2 || 820 sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8152_B || 821 sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8152_B2) { 822 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 823 ALC_MII_DBG_ADDR, 0x003B); 824 data = alc_miibus_readreg(sc->sc_dev, sc->alc_phyaddr, 825 ALC_MII_DBG_DATA); 826 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 827 ALC_MII_DBG_DATA, data & 0xFFF7); 828 DELAY(20 * 1000); 829 } 830 if (sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8151) { 831 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 832 ALC_MII_DBG_ADDR, 0x0029); 833 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 834 ALC_MII_DBG_DATA, 0x929D); 835 } 836 if (sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8131 || 837 sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8132 || 838 sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8151_V2 || 839 sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8152_B2) { 840 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 841 ALC_MII_DBG_ADDR, 0x0029); 842 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 843 ALC_MII_DBG_DATA, 0xB6DD); 844 } 845 846 /* Load DSP codes, vendor magic. */ 847 data = ANA_LOOP_SEL_10BT | ANA_EN_MASK_TB | ANA_EN_10BT_IDLE | 848 ((1 << ANA_INTERVAL_SEL_TIMER_SHIFT) & ANA_INTERVAL_SEL_TIMER_MASK); 849 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 850 ALC_MII_DBG_ADDR, MII_ANA_CFG18); 851 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 852 ALC_MII_DBG_DATA, data); 853 854 data = ((2 << ANA_SERDES_CDR_BW_SHIFT) & ANA_SERDES_CDR_BW_MASK) | 855 ANA_SERDES_EN_DEEM | ANA_SERDES_SEL_HSP | ANA_SERDES_EN_PLL | 856 ANA_SERDES_EN_LCKDT; 857 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 858 ALC_MII_DBG_ADDR, MII_ANA_CFG5); 859 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 860 ALC_MII_DBG_DATA, data); 861 862 data = ((44 << ANA_LONG_CABLE_TH_100_SHIFT) & 863 ANA_LONG_CABLE_TH_100_MASK) | 864 ((33 << ANA_SHORT_CABLE_TH_100_SHIFT) & 865 ANA_SHORT_CABLE_TH_100_SHIFT) | 866 ANA_BP_BAD_LINK_ACCUM | ANA_BP_SMALL_BW; 867 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 868 ALC_MII_DBG_ADDR, MII_ANA_CFG54); 869 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 870 ALC_MII_DBG_DATA, data); 871 872 data = ((11 << ANA_IECHO_ADJ_3_SHIFT) & ANA_IECHO_ADJ_3_MASK) | 873 ((11 << ANA_IECHO_ADJ_2_SHIFT) & ANA_IECHO_ADJ_2_MASK) | 874 ((8 << ANA_IECHO_ADJ_1_SHIFT) & ANA_IECHO_ADJ_1_MASK) | 875 ((8 << ANA_IECHO_ADJ_0_SHIFT) & ANA_IECHO_ADJ_0_MASK); 876 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 877 ALC_MII_DBG_ADDR, MII_ANA_CFG4); 878 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 879 ALC_MII_DBG_DATA, data); 880 881 data = ((7 & ANA_MANUL_SWICH_ON_SHIFT) & ANA_MANUL_SWICH_ON_MASK) | 882 ANA_RESTART_CAL | ANA_MAN_ENABLE | ANA_SEL_HSP | ANA_EN_HB | 883 ANA_OEN_125M; 884 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 885 ALC_MII_DBG_ADDR, MII_ANA_CFG0); 886 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 887 ALC_MII_DBG_DATA, data); 888 DELAY(1000); 889 890 /* Disable hibernation. */ 891 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, ALC_MII_DBG_ADDR, 892 0x0029); 893 data = alc_miibus_readreg(sc->sc_dev, sc->alc_phyaddr, 894 ALC_MII_DBG_DATA); 895 data &= ~0x8000; 896 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, ALC_MII_DBG_DATA, 897 data); 898 899 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, ALC_MII_DBG_ADDR, 900 0x000B); 901 data = alc_miibus_readreg(sc->sc_dev, sc->alc_phyaddr, 902 ALC_MII_DBG_DATA); 903 data &= ~0x8000; 904 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, ALC_MII_DBG_DATA, 905 data); 906 } 907 908 static void 909 alc_phy_reset_816x(struct alc_softc *sc) 910 { 911 uint32_t val; 912 913 val = CSR_READ_4(sc, ALC_GPHY_CFG); 914 val &= ~(GPHY_CFG_EXT_RESET | GPHY_CFG_LED_MODE | 915 GPHY_CFG_GATE_25M_ENB | GPHY_CFG_PHY_IDDQ | GPHY_CFG_PHY_PLL_ON | 916 GPHY_CFG_PWDOWN_HW | GPHY_CFG_100AB_ENB); 917 val |= GPHY_CFG_SEL_ANA_RESET; 918 #ifdef notyet 919 val |= GPHY_CFG_HIB_PULSE | GPHY_CFG_HIB_EN | GPHY_CFG_SEL_ANA_RESET; 920 #else 921 /* Disable PHY hibernation. */ 922 val &= ~(GPHY_CFG_HIB_PULSE | GPHY_CFG_HIB_EN); 923 #endif 924 CSR_WRITE_4(sc, ALC_GPHY_CFG, val); 925 DELAY(10); 926 CSR_WRITE_4(sc, ALC_GPHY_CFG, val | GPHY_CFG_EXT_RESET); 927 DELAY(800); 928 929 /* Vendor PHY magic. */ 930 #ifdef notyet 931 alc_miidbg_writereg(sc, MII_DBG_LEGCYPS, DBG_LEGCYPS_DEFAULT); 932 alc_miidbg_writereg(sc, MII_DBG_SYSMODCTL, DBG_SYSMODCTL_DEFAULT); 933 alc_miiext_writereg(sc, MII_EXT_PCS, MII_EXT_VDRVBIAS, 934 EXT_VDRVBIAS_DEFAULT); 935 #else 936 /* Disable PHY hibernation. */ 937 alc_miidbg_writereg(sc, MII_DBG_LEGCYPS, 938 DBG_LEGCYPS_DEFAULT & ~DBG_LEGCYPS_ENB); 939 alc_miidbg_writereg(sc, MII_DBG_HIBNEG, 940 DBG_HIBNEG_DEFAULT & ~(DBG_HIBNEG_PSHIB_EN | DBG_HIBNEG_HIB_PULSE)); 941 alc_miidbg_writereg(sc, MII_DBG_GREENCFG, DBG_GREENCFG_DEFAULT); 942 #endif 943 944 /* XXX Disable EEE. */ 945 val = CSR_READ_4(sc, ALC_LPI_CTL); 946 val &= ~LPI_CTL_ENB; 947 CSR_WRITE_4(sc, ALC_LPI_CTL, val); 948 alc_miiext_writereg(sc, MII_EXT_ANEG, MII_EXT_ANEG_LOCAL_EEEADV, 0); 949 950 /* PHY power saving. */ 951 alc_miidbg_writereg(sc, MII_DBG_TST10BTCFG, DBG_TST10BTCFG_DEFAULT); 952 alc_miidbg_writereg(sc, MII_DBG_SRDSYSMOD, DBG_SRDSYSMOD_DEFAULT); 953 alc_miidbg_writereg(sc, MII_DBG_TST100BTCFG, DBG_TST100BTCFG_DEFAULT); 954 alc_miidbg_writereg(sc, MII_DBG_ANACTL, DBG_ANACTL_DEFAULT); 955 val = alc_miidbg_readreg(sc, MII_DBG_GREENCFG2); 956 val &= ~DBG_GREENCFG2_GATE_DFSE_EN; 957 alc_miidbg_writereg(sc, MII_DBG_GREENCFG2, val); 958 959 /* RTL8139C, 120m issue. */ 960 alc_miiext_writereg(sc, MII_EXT_ANEG, MII_EXT_ANEG_NLP78, 961 ANEG_NLP78_120M_DEFAULT); 962 alc_miiext_writereg(sc, MII_EXT_ANEG, MII_EXT_ANEG_S3DIG10, 963 ANEG_S3DIG10_DEFAULT); 964 965 if ((sc->alc_flags & ALC_FLAG_LINK_WAR) != 0) { 966 /* Turn off half amplitude. */ 967 val = alc_miiext_readreg(sc, MII_EXT_PCS, MII_EXT_CLDCTL3); 968 val |= EXT_CLDCTL3_BP_CABLE1TH_DET_GT; 969 alc_miiext_writereg(sc, MII_EXT_PCS, MII_EXT_CLDCTL3, val); 970 /* Turn off Green feature. */ 971 val = alc_miidbg_readreg(sc, MII_DBG_GREENCFG2); 972 val |= DBG_GREENCFG2_BP_GREEN; 973 alc_miidbg_writereg(sc, MII_DBG_GREENCFG2, val); 974 /* Turn off half bias. */ 975 val = alc_miiext_readreg(sc, MII_EXT_PCS, MII_EXT_CLDCTL5); 976 val |= EXT_CLDCTL5_BP_VD_HLFBIAS; 977 alc_miiext_writereg(sc, MII_EXT_PCS, MII_EXT_CLDCTL5, val); 978 } 979 } 980 981 static void 982 alc_phy_down(struct alc_softc *sc) 983 { 984 uint32_t gphy; 985 986 switch (sc->alc_ident->deviceid) { 987 case PCI_PRODUCT_ATTANSIC_AR8161: 988 case PCI_PRODUCT_ATTANSIC_E2200: 989 case PCI_PRODUCT_ATTANSIC_AR8162: 990 case PCI_PRODUCT_ATTANSIC_AR8171: 991 case PCI_PRODUCT_ATTANSIC_AR8172: 992 gphy = CSR_READ_4(sc, ALC_GPHY_CFG); 993 gphy &= ~(GPHY_CFG_EXT_RESET | GPHY_CFG_LED_MODE | 994 GPHY_CFG_100AB_ENB | GPHY_CFG_PHY_PLL_ON); 995 gphy |= GPHY_CFG_HIB_EN | GPHY_CFG_HIB_PULSE | 996 GPHY_CFG_SEL_ANA_RESET; 997 gphy |= GPHY_CFG_PHY_IDDQ | GPHY_CFG_PWDOWN_HW; 998 CSR_WRITE_4(sc, ALC_GPHY_CFG, gphy); 999 break; 1000 case PCI_PRODUCT_ATTANSIC_AR8151: 1001 case PCI_PRODUCT_ATTANSIC_AR8151_V2: 1002 case PCI_PRODUCT_ATTANSIC_AR8152_B: 1003 case PCI_PRODUCT_ATTANSIC_AR8152_B2: 1004 /* 1005 * GPHY power down caused more problems on AR8151 v2.0. 1006 * When driver is reloaded after GPHY power down, 1007 * accesses to PHY/MAC registers hung the system. Only 1008 * cold boot recovered from it. I'm not sure whether 1009 * AR8151 v1.0 also requires this one though. I don't 1010 * have AR8151 v1.0 controller in hand. 1011 * The only option left is to isolate the PHY and 1012 * initiates power down the PHY which in turn saves 1013 * more power when driver is unloaded. 1014 */ 1015 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 1016 MII_BMCR, BMCR_ISO | BMCR_PDOWN); 1017 break; 1018 default: 1019 /* Force PHY down. */ 1020 CSR_WRITE_2(sc, ALC_GPHY_CFG, GPHY_CFG_EXT_RESET | 1021 GPHY_CFG_SEL_ANA_RESET | GPHY_CFG_PHY_IDDQ | 1022 GPHY_CFG_PWDOWN_HW); 1023 DELAY(1000); 1024 break; 1025 } 1026 } 1027 1028 static void 1029 alc_aspm(struct alc_softc *sc, int init, int media) 1030 { 1031 1032 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 1033 alc_aspm_816x(sc, init); 1034 else 1035 alc_aspm_813x(sc, media); 1036 } 1037 1038 static void 1039 alc_aspm_813x(struct alc_softc *sc, int media) 1040 { 1041 uint32_t pmcfg; 1042 uint16_t linkcfg; 1043 1044 pmcfg = CSR_READ_4(sc, ALC_PM_CFG); 1045 if ((sc->alc_flags & (ALC_FLAG_APS | ALC_FLAG_PCIE)) == 1046 (ALC_FLAG_APS | ALC_FLAG_PCIE)) 1047 linkcfg = CSR_READ_2(sc, sc->alc_expcap + 1048 PCIE_LCSR); 1049 else 1050 linkcfg = 0; 1051 pmcfg &= ~PM_CFG_SERDES_PD_EX_L1; 1052 pmcfg &= ~(PM_CFG_L1_ENTRY_TIMER_MASK | PM_CFG_LCKDET_TIMER_MASK); 1053 pmcfg |= PM_CFG_MAC_ASPM_CHK; 1054 pmcfg |= (PM_CFG_LCKDET_TIMER_DEFAULT << PM_CFG_LCKDET_TIMER_SHIFT); 1055 pmcfg &= ~(PM_CFG_ASPM_L1_ENB | PM_CFG_ASPM_L0S_ENB); 1056 1057 if ((sc->alc_flags & ALC_FLAG_APS) != 0) { 1058 /* Disable extended sync except AR8152 B v1.0 */ 1059 linkcfg &= ~0x80; 1060 if (sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8152_B && 1061 sc->alc_rev == ATHEROS_AR8152_B_V10) 1062 linkcfg |= 0x80; 1063 CSR_WRITE_2(sc, sc->alc_expcap + PCIE_LCSR, 1064 linkcfg); 1065 pmcfg &= ~(PM_CFG_EN_BUFS_RX_L0S | PM_CFG_SA_DLY_ENB | 1066 PM_CFG_HOTRST); 1067 pmcfg |= (PM_CFG_L1_ENTRY_TIMER_DEFAULT << 1068 PM_CFG_L1_ENTRY_TIMER_SHIFT); 1069 pmcfg &= ~PM_CFG_PM_REQ_TIMER_MASK; 1070 pmcfg |= (PM_CFG_PM_REQ_TIMER_DEFAULT << 1071 PM_CFG_PM_REQ_TIMER_SHIFT); 1072 pmcfg |= PM_CFG_SERDES_PD_EX_L1 | PM_CFG_PCIE_RECV; 1073 } 1074 1075 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) { 1076 if ((sc->alc_flags & ALC_FLAG_L0S) != 0) 1077 pmcfg |= PM_CFG_ASPM_L0S_ENB; 1078 if ((sc->alc_flags & ALC_FLAG_L1S) != 0) 1079 pmcfg |= PM_CFG_ASPM_L1_ENB; 1080 if ((sc->alc_flags & ALC_FLAG_APS) != 0) { 1081 if (sc->alc_ident->deviceid == 1082 PCI_PRODUCT_ATTANSIC_AR8152_B) 1083 pmcfg &= ~PM_CFG_ASPM_L0S_ENB; 1084 pmcfg &= ~(PM_CFG_SERDES_L1_ENB | 1085 PM_CFG_SERDES_PLL_L1_ENB | 1086 PM_CFG_SERDES_BUDS_RX_L1_ENB); 1087 pmcfg |= PM_CFG_CLK_SWH_L1; 1088 if (media == IFM_100_TX || media == IFM_1000_T) { 1089 pmcfg &= ~PM_CFG_L1_ENTRY_TIMER_MASK; 1090 switch (sc->alc_ident->deviceid) { 1091 case PCI_PRODUCT_ATTANSIC_AR8152_B: 1092 pmcfg |= (7 << 1093 PM_CFG_L1_ENTRY_TIMER_SHIFT); 1094 break; 1095 case PCI_PRODUCT_ATTANSIC_AR8152_B2: 1096 case PCI_PRODUCT_ATTANSIC_AR8151_V2: 1097 pmcfg |= (4 << 1098 PM_CFG_L1_ENTRY_TIMER_SHIFT); 1099 break; 1100 default: 1101 pmcfg |= (15 << 1102 PM_CFG_L1_ENTRY_TIMER_SHIFT); 1103 break; 1104 } 1105 } 1106 } else { 1107 pmcfg |= PM_CFG_SERDES_L1_ENB | 1108 PM_CFG_SERDES_PLL_L1_ENB | 1109 PM_CFG_SERDES_BUDS_RX_L1_ENB; 1110 pmcfg &= ~(PM_CFG_CLK_SWH_L1 | 1111 PM_CFG_ASPM_L1_ENB | PM_CFG_ASPM_L0S_ENB); 1112 } 1113 } else { 1114 pmcfg &= ~(PM_CFG_SERDES_BUDS_RX_L1_ENB | PM_CFG_SERDES_L1_ENB | 1115 PM_CFG_SERDES_PLL_L1_ENB); 1116 pmcfg |= PM_CFG_CLK_SWH_L1; 1117 if ((sc->alc_flags & ALC_FLAG_L1S) != 0) 1118 pmcfg |= PM_CFG_ASPM_L1_ENB; 1119 } 1120 CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg); 1121 } 1122 1123 static void 1124 alc_aspm_816x(struct alc_softc *sc, int init) 1125 { 1126 uint32_t pmcfg; 1127 1128 pmcfg = CSR_READ_4(sc, ALC_PM_CFG); 1129 pmcfg &= ~PM_CFG_L1_ENTRY_TIMER_816X_MASK; 1130 pmcfg |= PM_CFG_L1_ENTRY_TIMER_816X_DEFAULT; 1131 pmcfg &= ~PM_CFG_PM_REQ_TIMER_MASK; 1132 pmcfg |= PM_CFG_PM_REQ_TIMER_816X_DEFAULT; 1133 pmcfg &= ~PM_CFG_LCKDET_TIMER_MASK; 1134 pmcfg |= PM_CFG_LCKDET_TIMER_DEFAULT; 1135 pmcfg |= PM_CFG_SERDES_PD_EX_L1 | PM_CFG_CLK_SWH_L1 | PM_CFG_PCIE_RECV; 1136 pmcfg &= ~(PM_CFG_RX_L1_AFTER_L0S | PM_CFG_TX_L1_AFTER_L0S | 1137 PM_CFG_ASPM_L1_ENB | PM_CFG_ASPM_L0S_ENB | 1138 PM_CFG_SERDES_L1_ENB | PM_CFG_SERDES_PLL_L1_ENB | 1139 PM_CFG_SERDES_BUDS_RX_L1_ENB | PM_CFG_SA_DLY_ENB | 1140 PM_CFG_MAC_ASPM_CHK | PM_CFG_HOTRST); 1141 if (AR816X_REV(sc->alc_rev) <= AR816X_REV_A1 && 1142 (sc->alc_rev & 0x01) != 0) 1143 pmcfg |= PM_CFG_SERDES_L1_ENB | PM_CFG_SERDES_PLL_L1_ENB; 1144 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) { 1145 /* Link up, enable both L0s, L1s. */ 1146 pmcfg |= PM_CFG_ASPM_L0S_ENB | PM_CFG_ASPM_L1_ENB | 1147 PM_CFG_MAC_ASPM_CHK; 1148 } else { 1149 if (init != 0) 1150 pmcfg |= PM_CFG_ASPM_L0S_ENB | PM_CFG_ASPM_L1_ENB | 1151 PM_CFG_MAC_ASPM_CHK; 1152 else if ((sc->sc_ec.ec_if.if_flags & IFF_RUNNING) != 0) 1153 pmcfg |= PM_CFG_ASPM_L1_ENB | PM_CFG_MAC_ASPM_CHK; 1154 } 1155 CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg); 1156 } 1157 1158 static void 1159 alc_attach(device_t parent, device_t self, void *aux) 1160 { 1161 1162 struct alc_softc *sc = device_private(self); 1163 struct pci_attach_args *pa = aux; 1164 pci_chipset_tag_t pc = pa->pa_pc; 1165 pci_intr_handle_t ih; 1166 const char *intrstr; 1167 struct ifnet *ifp; 1168 pcireg_t memtype; 1169 const char *aspm_state[] = { "L0s/L1", "L0s", "L1", "L0s/L1" }; 1170 uint16_t burst; 1171 int base, mii_flags, state, error = 0; 1172 uint32_t cap, ctl, val; 1173 char intrbuf[PCI_INTRSTR_LEN]; 1174 1175 sc->alc_ident = alc_find_ident(pa); 1176 1177 aprint_naive("\n"); 1178 aprint_normal(": %s\n", sc->alc_ident->name); 1179 1180 sc->sc_dev = self; 1181 sc->sc_dmat = pa->pa_dmat; 1182 sc->sc_pct = pa->pa_pc; 1183 sc->sc_pcitag = pa->pa_tag; 1184 1185 /* 1186 * Allocate IO memory 1187 */ 1188 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, ALC_PCIR_BAR); 1189 switch (memtype) { 1190 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 1191 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT_1M: 1192 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 1193 break; 1194 default: 1195 aprint_error_dev(self, "invalid base address register\n"); 1196 break; 1197 } 1198 1199 if (pci_mapreg_map(pa, ALC_PCIR_BAR, memtype, 0, &sc->sc_mem_bt, 1200 &sc->sc_mem_bh, NULL, &sc->sc_mem_size)) { 1201 aprint_error_dev(self, "could not map mem space\n"); 1202 return; 1203 } 1204 1205 if (pci_intr_map(pa, &ih) != 0) { 1206 printf(": can't map interrupt\n"); 1207 goto fail; 1208 } 1209 1210 /* 1211 * Allocate IRQ 1212 */ 1213 intrstr = pci_intr_string(sc->sc_pct, ih, intrbuf, sizeof(intrbuf)); 1214 sc->sc_irq_handle = pci_intr_establish(pc, ih, IPL_NET, alc_intr, sc); 1215 if (sc->sc_irq_handle == NULL) { 1216 printf(": could not establish interrupt"); 1217 if (intrstr != NULL) 1218 printf(" at %s", intrstr); 1219 printf("\n"); 1220 goto fail; 1221 } 1222 aprint_normal_dev(self, "interrupting at %s\n", intrstr); 1223 1224 /* Set PHY address. */ 1225 sc->alc_phyaddr = ALC_PHY_ADDR; 1226 1227 /* Initialize DMA parameters. */ 1228 sc->alc_dma_rd_burst = 0; 1229 sc->alc_dma_wr_burst = 0; 1230 sc->alc_rcb = DMA_CFG_RCB_64; 1231 if (pci_get_capability(pc, pa->pa_tag, PCI_CAP_PCIEXPRESS, 1232 &base, NULL)) { 1233 sc->alc_flags |= ALC_FLAG_PCIE; 1234 sc->alc_expcap = base; 1235 burst = pci_conf_read(sc->sc_pct, sc->sc_pcitag, 1236 base + PCIE_DCSR) >> 16; 1237 sc->alc_dma_rd_burst = (burst & 0x7000) >> 12; 1238 sc->alc_dma_wr_burst = (burst & 0x00e0) >> 5; 1239 if (alcdebug) { 1240 printf("%s: Read request size : %u bytes.\n", 1241 device_xname(sc->sc_dev), 1242 alc_dma_burst[sc->alc_dma_rd_burst]); 1243 printf("%s: TLP payload size : %u bytes.\n", 1244 device_xname(sc->sc_dev), 1245 alc_dma_burst[sc->alc_dma_wr_burst]); 1246 } 1247 if (alc_dma_burst[sc->alc_dma_rd_burst] > 1024) 1248 sc->alc_dma_rd_burst = 3; 1249 if (alc_dma_burst[sc->alc_dma_wr_burst] > 1024) 1250 sc->alc_dma_wr_burst = 3; 1251 1252 /* Clear data link and flow-control protocol error. */ 1253 val = CSR_READ_4(sc, ALC_PEX_UNC_ERR_SEV); 1254 val &= ~(PEX_UNC_ERR_SEV_DLP | PEX_UNC_ERR_SEV_FCP); 1255 CSR_WRITE_4(sc, ALC_PEX_UNC_ERR_SEV, val); 1256 1257 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 1258 CSR_WRITE_4(sc, ALC_LTSSM_ID_CFG, 1259 CSR_READ_4(sc, ALC_LTSSM_ID_CFG) & ~LTSSM_ID_WRO_ENB); 1260 CSR_WRITE_4(sc, ALC_PCIE_PHYMISC, 1261 CSR_READ_4(sc, ALC_PCIE_PHYMISC) | 1262 PCIE_PHYMISC_FORCE_RCV_DET); 1263 if (sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8152_B && 1264 sc->alc_rev == ATHEROS_AR8152_B_V10) { 1265 val = CSR_READ_4(sc, ALC_PCIE_PHYMISC2); 1266 val &= ~(PCIE_PHYMISC2_SERDES_CDR_MASK | 1267 PCIE_PHYMISC2_SERDES_TH_MASK); 1268 val |= 3 << PCIE_PHYMISC2_SERDES_CDR_SHIFT; 1269 val |= 3 << PCIE_PHYMISC2_SERDES_TH_SHIFT; 1270 CSR_WRITE_4(sc, ALC_PCIE_PHYMISC2, val); 1271 } 1272 /* Disable ASPM L0S and L1. */ 1273 cap = pci_conf_read(sc->sc_pct, sc->sc_pcitag, 1274 base + PCIE_LCAP) >> 16; 1275 if ((cap & PCIE_LCAP_ASPM) != 0) { 1276 ctl = pci_conf_read(sc->sc_pct, sc->sc_pcitag, 1277 base + PCIE_LCSR) >> 16; 1278 if ((ctl & 0x08) != 0) 1279 sc->alc_rcb = DMA_CFG_RCB_128; 1280 if (alcdebug) 1281 printf("%s: RCB %u bytes\n", 1282 device_xname(sc->sc_dev), 1283 sc->alc_rcb == DMA_CFG_RCB_64 ? 64 : 128); 1284 state = ctl & 0x03; 1285 if (state & 0x01) 1286 sc->alc_flags |= ALC_FLAG_L0S; 1287 if (state & 0x02) 1288 sc->alc_flags |= ALC_FLAG_L1S; 1289 if (alcdebug) 1290 printf("%s: ASPM %s %s\n", 1291 device_xname(sc->sc_dev), 1292 aspm_state[state], 1293 state == 0 ? "disabled" : "enabled"); 1294 alc_disable_l0s_l1(sc); 1295 } else { 1296 aprint_debug_dev(sc->sc_dev, "no ASPM support\n"); 1297 } 1298 } else { 1299 val = CSR_READ_4(sc, ALC_PDLL_TRNS1); 1300 val &= ~PDLL_TRNS1_D3PLLOFF_ENB; 1301 CSR_WRITE_4(sc, ALC_PDLL_TRNS1, val); 1302 val = CSR_READ_4(sc, ALC_MASTER_CFG); 1303 if (AR816X_REV(sc->alc_rev) <= AR816X_REV_A1 && 1304 (sc->alc_rev & 0x01) != 0) { 1305 if ((val & MASTER_WAKEN_25M) == 0 || 1306 (val & MASTER_CLK_SEL_DIS) == 0) { 1307 val |= MASTER_WAKEN_25M | MASTER_CLK_SEL_DIS; 1308 CSR_WRITE_4(sc, ALC_MASTER_CFG, val); 1309 } 1310 } else { 1311 if ((val & MASTER_WAKEN_25M) == 0 || 1312 (val & MASTER_CLK_SEL_DIS) != 0) { 1313 val |= MASTER_WAKEN_25M; 1314 val &= ~MASTER_CLK_SEL_DIS; 1315 CSR_WRITE_4(sc, ALC_MASTER_CFG, val); 1316 } 1317 } 1318 } 1319 alc_aspm(sc, 1, IFM_UNKNOWN); 1320 } 1321 1322 /* Reset PHY. */ 1323 alc_phy_reset(sc); 1324 1325 /* Reset the ethernet controller. */ 1326 alc_stop_mac(sc); 1327 alc_reset(sc); 1328 1329 /* 1330 * One odd thing is AR8132 uses the same PHY hardware(F1 1331 * gigabit PHY) of AR8131. So atphy(4) of AR8132 reports 1332 * the PHY supports 1000Mbps but that's not true. The PHY 1333 * used in AR8132 can't establish gigabit link even if it 1334 * shows the same PHY model/revision number of AR8131. 1335 */ 1336 switch (sc->alc_ident->deviceid) { 1337 case PCI_PRODUCT_ATTANSIC_AR8161: 1338 if (PCI_SUBSYS_ID(pci_conf_read( 1339 sc->sc_pct, sc->sc_pcitag, PCI_SUBSYS_ID_REG)) == 0x0091 && 1340 sc->alc_rev == 0) 1341 sc->alc_flags |= ALC_FLAG_LINK_WAR; 1342 /* FALLTHROUGH */ 1343 case PCI_PRODUCT_ATTANSIC_E2200: 1344 case PCI_PRODUCT_ATTANSIC_AR8171: 1345 sc->alc_flags |= ALC_FLAG_AR816X_FAMILY; 1346 break; 1347 case PCI_PRODUCT_ATTANSIC_AR8162: 1348 case PCI_PRODUCT_ATTANSIC_AR8172: 1349 sc->alc_flags |= ALC_FLAG_FASTETHER | ALC_FLAG_AR816X_FAMILY; 1350 break; 1351 case PCI_PRODUCT_ATTANSIC_AR8152_B: 1352 case PCI_PRODUCT_ATTANSIC_AR8152_B2: 1353 sc->alc_flags |= ALC_FLAG_APS; 1354 /* FALLTHROUGH */ 1355 case PCI_PRODUCT_ATTANSIC_AR8132: 1356 sc->alc_flags |= ALC_FLAG_FASTETHER; 1357 break; 1358 case PCI_PRODUCT_ATTANSIC_AR8151: 1359 case PCI_PRODUCT_ATTANSIC_AR8151_V2: 1360 sc->alc_flags |= ALC_FLAG_APS; 1361 /* FALLTHROUGH */ 1362 default: 1363 break; 1364 } 1365 sc->alc_flags |= ALC_FLAG_JUMBO; 1366 1367 /* 1368 * It seems that AR813x/AR815x has silicon bug for SMB. In 1369 * addition, Atheros said that enabling SMB wouldn't improve 1370 * performance. However I think it's bad to access lots of 1371 * registers to extract MAC statistics. 1372 */ 1373 sc->alc_flags |= ALC_FLAG_SMB_BUG; 1374 /* 1375 * Don't use Tx CMB. It is known to have silicon bug. 1376 */ 1377 sc->alc_flags |= ALC_FLAG_CMB_BUG; 1378 sc->alc_rev = PCI_REVISION(pa->pa_class); 1379 sc->alc_chip_rev = CSR_READ_4(sc, ALC_MASTER_CFG) >> 1380 MASTER_CHIP_REV_SHIFT; 1381 if (alcdebug) { 1382 printf("%s: PCI device revision : 0x%04x\n", 1383 device_xname(sc->sc_dev), sc->alc_rev); 1384 printf("%s: Chip id/revision : 0x%04x\n", 1385 device_xname(sc->sc_dev), sc->alc_chip_rev); 1386 printf("%s: %u Tx FIFO, %u Rx FIFO\n", device_xname(sc->sc_dev), 1387 CSR_READ_4(sc, ALC_SRAM_TX_FIFO_LEN) * 8, 1388 CSR_READ_4(sc, ALC_SRAM_RX_FIFO_LEN) * 8); 1389 } 1390 1391 error = alc_dma_alloc(sc); 1392 if (error) 1393 goto fail; 1394 1395 callout_init(&sc->sc_tick_ch, 0); 1396 callout_setfunc(&sc->sc_tick_ch, alc_tick, sc); 1397 1398 /* Load station address. */ 1399 alc_get_macaddr(sc); 1400 1401 aprint_normal_dev(self, "Ethernet address %s\n", 1402 ether_sprintf(sc->alc_eaddr)); 1403 1404 ifp = &sc->sc_ec.ec_if; 1405 ifp->if_softc = sc; 1406 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1407 ifp->if_init = alc_init; 1408 ifp->if_ioctl = alc_ioctl; 1409 ifp->if_start = alc_start; 1410 ifp->if_stop = alc_stop; 1411 ifp->if_watchdog = alc_watchdog; 1412 IFQ_SET_MAXLEN(&ifp->if_snd, ALC_TX_RING_CNT - 1); 1413 IFQ_SET_READY(&ifp->if_snd); 1414 strlcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 1415 1416 sc->sc_ec.ec_capabilities = ETHERCAP_VLAN_MTU; 1417 1418 #ifdef ALC_CHECKSUM 1419 ifp->if_capabilities |= IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 1420 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 1421 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 1422 #endif 1423 1424 #if NVLAN > 0 1425 sc->sc_ec.ec_capabilities |= ETHERCAP_VLAN_HWTAGGING; 1426 #endif 1427 1428 /* 1429 * XXX 1430 * It seems enabling Tx checksum offloading makes more trouble. 1431 * Sometimes the controller does not receive any frames when 1432 * Tx checksum offloading is enabled. I'm not sure whether this 1433 * is a bug in Tx checksum offloading logic or I got broken 1434 * sample boards. To safety, don't enable Tx checksum offloading 1435 * by default but give chance to users to toggle it if they know 1436 * their controllers work without problems. 1437 * Fortunately, Tx checksum offloading for AR816x family 1438 * seems to work. 1439 */ 1440 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 1441 ifp->if_capenable &= ~IFCAP_CSUM_IPv4_Tx; 1442 ifp->if_capabilities &= ~ALC_CSUM_FEATURES; 1443 } 1444 1445 /* Set up MII bus. */ 1446 sc->sc_miibus.mii_ifp = ifp; 1447 sc->sc_miibus.mii_readreg = alc_miibus_readreg; 1448 sc->sc_miibus.mii_writereg = alc_miibus_writereg; 1449 sc->sc_miibus.mii_statchg = alc_miibus_statchg; 1450 1451 sc->sc_ec.ec_mii = &sc->sc_miibus; 1452 ifmedia_init(&sc->sc_miibus.mii_media, 0, alc_mediachange, 1453 alc_mediastatus); 1454 mii_flags = 0; 1455 if ((sc->alc_flags & ALC_FLAG_JUMBO) != 0) 1456 mii_flags |= MIIF_DOPAUSE; 1457 mii_attach(self, &sc->sc_miibus, 0xffffffff, MII_PHY_ANY, 1458 MII_OFFSET_ANY, mii_flags); 1459 1460 if (LIST_FIRST(&sc->sc_miibus.mii_phys) == NULL) { 1461 printf("%s: no PHY found!\n", device_xname(sc->sc_dev)); 1462 ifmedia_add(&sc->sc_miibus.mii_media, IFM_ETHER | IFM_MANUAL, 1463 0, NULL); 1464 ifmedia_set(&sc->sc_miibus.mii_media, IFM_ETHER | IFM_MANUAL); 1465 } else 1466 ifmedia_set(&sc->sc_miibus.mii_media, IFM_ETHER | IFM_AUTO); 1467 1468 if_attach(ifp); 1469 if_deferred_start_init(ifp, NULL); 1470 ether_ifattach(ifp, sc->alc_eaddr); 1471 1472 if (!pmf_device_register(self, NULL, NULL)) 1473 aprint_error_dev(self, "couldn't establish power handler\n"); 1474 else 1475 pmf_class_network_register(self, ifp); 1476 1477 return; 1478 fail: 1479 alc_dma_free(sc); 1480 if (sc->sc_irq_handle != NULL) { 1481 pci_intr_disestablish(sc->sc_pct, sc->sc_irq_handle); 1482 sc->sc_irq_handle = NULL; 1483 } 1484 if (sc->sc_mem_size) { 1485 bus_space_unmap(sc->sc_mem_bt, sc->sc_mem_bh, sc->sc_mem_size); 1486 sc->sc_mem_size = 0; 1487 } 1488 } 1489 1490 static int 1491 alc_detach(device_t self, int flags) 1492 { 1493 struct alc_softc *sc = device_private(self); 1494 struct ifnet *ifp = &sc->sc_ec.ec_if; 1495 int s; 1496 1497 s = splnet(); 1498 alc_stop(ifp, 0); 1499 splx(s); 1500 1501 mii_detach(&sc->sc_miibus, MII_PHY_ANY, MII_OFFSET_ANY); 1502 1503 /* Delete all remaining media. */ 1504 ifmedia_delete_instance(&sc->sc_miibus.mii_media, IFM_INST_ANY); 1505 1506 ether_ifdetach(ifp); 1507 if_detach(ifp); 1508 alc_dma_free(sc); 1509 1510 alc_phy_down(sc); 1511 if (sc->sc_irq_handle != NULL) { 1512 pci_intr_disestablish(sc->sc_pct, sc->sc_irq_handle); 1513 sc->sc_irq_handle = NULL; 1514 } 1515 if (sc->sc_mem_size) { 1516 bus_space_unmap(sc->sc_mem_bt, sc->sc_mem_bh, sc->sc_mem_size); 1517 sc->sc_mem_size = 0; 1518 } 1519 1520 return (0); 1521 } 1522 1523 static int 1524 alc_dma_alloc(struct alc_softc *sc) 1525 { 1526 struct alc_txdesc *txd; 1527 struct alc_rxdesc *rxd; 1528 int nsegs, error, i; 1529 1530 /* 1531 * Create DMA stuffs for TX ring 1532 */ 1533 error = bus_dmamap_create(sc->sc_dmat, ALC_TX_RING_SZ, 1, 1534 ALC_TX_RING_SZ, 0, BUS_DMA_NOWAIT, &sc->alc_cdata.alc_tx_ring_map); 1535 if (error) { 1536 sc->alc_cdata.alc_tx_ring_map = NULL; 1537 return (ENOBUFS); 1538 } 1539 1540 /* Allocate DMA'able memory for TX ring */ 1541 error = bus_dmamem_alloc(sc->sc_dmat, ALC_TX_RING_SZ, 1542 ETHER_ALIGN, 0, &sc->alc_rdata.alc_tx_ring_seg, 1, 1543 &nsegs, BUS_DMA_NOWAIT); 1544 if (error) { 1545 printf("%s: could not allocate DMA'able memory for Tx ring.\n", 1546 device_xname(sc->sc_dev)); 1547 return error; 1548 } 1549 1550 error = bus_dmamem_map(sc->sc_dmat, &sc->alc_rdata.alc_tx_ring_seg, 1551 nsegs, ALC_TX_RING_SZ, (void **)&sc->alc_rdata.alc_tx_ring, 1552 BUS_DMA_NOWAIT); 1553 if (error) 1554 return (ENOBUFS); 1555 1556 /* Load the DMA map for Tx ring. */ 1557 error = bus_dmamap_load(sc->sc_dmat, sc->alc_cdata.alc_tx_ring_map, 1558 sc->alc_rdata.alc_tx_ring, ALC_TX_RING_SZ, NULL, BUS_DMA_WAITOK); 1559 if (error) { 1560 printf("%s: could not load DMA'able memory for Tx ring.\n", 1561 device_xname(sc->sc_dev)); 1562 bus_dmamem_free(sc->sc_dmat, 1563 &sc->alc_rdata.alc_tx_ring_seg, 1); 1564 return error; 1565 } 1566 1567 sc->alc_rdata.alc_tx_ring_paddr = 1568 sc->alc_cdata.alc_tx_ring_map->dm_segs[0].ds_addr; 1569 1570 /* 1571 * Create DMA stuffs for RX ring 1572 */ 1573 error = bus_dmamap_create(sc->sc_dmat, ALC_RX_RING_SZ, 1, 1574 ALC_RX_RING_SZ, 0, BUS_DMA_NOWAIT, &sc->alc_cdata.alc_rx_ring_map); 1575 if (error) 1576 return (ENOBUFS); 1577 1578 /* Allocate DMA'able memory for RX ring */ 1579 error = bus_dmamem_alloc(sc->sc_dmat, ALC_RX_RING_SZ, 1580 ETHER_ALIGN, 0, &sc->alc_rdata.alc_rx_ring_seg, 1, 1581 &nsegs, BUS_DMA_NOWAIT); 1582 if (error) { 1583 printf("%s: could not allocate DMA'able memory for Rx ring.\n", 1584 device_xname(sc->sc_dev)); 1585 return error; 1586 } 1587 1588 error = bus_dmamem_map(sc->sc_dmat, &sc->alc_rdata.alc_rx_ring_seg, 1589 nsegs, ALC_RX_RING_SZ, (void **)&sc->alc_rdata.alc_rx_ring, 1590 BUS_DMA_NOWAIT); 1591 if (error) 1592 return (ENOBUFS); 1593 1594 /* Load the DMA map for Rx ring. */ 1595 error = bus_dmamap_load(sc->sc_dmat, sc->alc_cdata.alc_rx_ring_map, 1596 sc->alc_rdata.alc_rx_ring, ALC_RX_RING_SZ, NULL, BUS_DMA_WAITOK); 1597 if (error) { 1598 printf("%s: could not load DMA'able memory for Rx ring.\n", 1599 device_xname(sc->sc_dev)); 1600 bus_dmamem_free(sc->sc_dmat, 1601 &sc->alc_rdata.alc_rx_ring_seg, 1); 1602 return error; 1603 } 1604 1605 sc->alc_rdata.alc_rx_ring_paddr = 1606 sc->alc_cdata.alc_rx_ring_map->dm_segs[0].ds_addr; 1607 1608 /* 1609 * Create DMA stuffs for RX return ring 1610 */ 1611 error = bus_dmamap_create(sc->sc_dmat, ALC_RR_RING_SZ, 1, 1612 ALC_RR_RING_SZ, 0, BUS_DMA_NOWAIT, &sc->alc_cdata.alc_rr_ring_map); 1613 if (error) 1614 return (ENOBUFS); 1615 1616 /* Allocate DMA'able memory for RX return ring */ 1617 error = bus_dmamem_alloc(sc->sc_dmat, ALC_RR_RING_SZ, 1618 ETHER_ALIGN, 0, &sc->alc_rdata.alc_rr_ring_seg, 1, 1619 &nsegs, BUS_DMA_NOWAIT); 1620 if (error) { 1621 printf("%s: could not allocate DMA'able memory for Rx " 1622 "return ring.\n", device_xname(sc->sc_dev)); 1623 return error; 1624 } 1625 1626 error = bus_dmamem_map(sc->sc_dmat, &sc->alc_rdata.alc_rr_ring_seg, 1627 nsegs, ALC_RR_RING_SZ, (void **)&sc->alc_rdata.alc_rr_ring, 1628 BUS_DMA_NOWAIT); 1629 if (error) 1630 return (ENOBUFS); 1631 1632 /* Load the DMA map for Rx return ring. */ 1633 error = bus_dmamap_load(sc->sc_dmat, sc->alc_cdata.alc_rr_ring_map, 1634 sc->alc_rdata.alc_rr_ring, ALC_RR_RING_SZ, NULL, BUS_DMA_WAITOK); 1635 if (error) { 1636 printf("%s: could not load DMA'able memory for Rx return ring." 1637 "\n", device_xname(sc->sc_dev)); 1638 bus_dmamem_free(sc->sc_dmat, 1639 &sc->alc_rdata.alc_rr_ring_seg, 1); 1640 return error; 1641 } 1642 1643 sc->alc_rdata.alc_rr_ring_paddr = 1644 sc->alc_cdata.alc_rr_ring_map->dm_segs[0].ds_addr; 1645 1646 /* 1647 * Create DMA stuffs for CMB block 1648 */ 1649 error = bus_dmamap_create(sc->sc_dmat, ALC_CMB_SZ, 1, 1650 ALC_CMB_SZ, 0, BUS_DMA_NOWAIT, 1651 &sc->alc_cdata.alc_cmb_map); 1652 if (error) 1653 return (ENOBUFS); 1654 1655 /* Allocate DMA'able memory for CMB block */ 1656 error = bus_dmamem_alloc(sc->sc_dmat, ALC_CMB_SZ, 1657 ETHER_ALIGN, 0, &sc->alc_rdata.alc_cmb_seg, 1, 1658 &nsegs, BUS_DMA_NOWAIT); 1659 if (error) { 1660 printf("%s: could not allocate DMA'able memory for " 1661 "CMB block\n", device_xname(sc->sc_dev)); 1662 return error; 1663 } 1664 1665 error = bus_dmamem_map(sc->sc_dmat, &sc->alc_rdata.alc_cmb_seg, 1666 nsegs, ALC_CMB_SZ, (void **)&sc->alc_rdata.alc_cmb, 1667 BUS_DMA_NOWAIT); 1668 if (error) 1669 return (ENOBUFS); 1670 1671 /* Load the DMA map for CMB block. */ 1672 error = bus_dmamap_load(sc->sc_dmat, sc->alc_cdata.alc_cmb_map, 1673 sc->alc_rdata.alc_cmb, ALC_CMB_SZ, NULL, 1674 BUS_DMA_WAITOK); 1675 if (error) { 1676 printf("%s: could not load DMA'able memory for CMB block\n", 1677 device_xname(sc->sc_dev)); 1678 bus_dmamem_free(sc->sc_dmat, 1679 &sc->alc_rdata.alc_cmb_seg, 1); 1680 return error; 1681 } 1682 1683 sc->alc_rdata.alc_cmb_paddr = 1684 sc->alc_cdata.alc_cmb_map->dm_segs[0].ds_addr; 1685 1686 /* 1687 * Create DMA stuffs for SMB block 1688 */ 1689 error = bus_dmamap_create(sc->sc_dmat, ALC_SMB_SZ, 1, 1690 ALC_SMB_SZ, 0, BUS_DMA_NOWAIT, 1691 &sc->alc_cdata.alc_smb_map); 1692 if (error) 1693 return (ENOBUFS); 1694 1695 /* Allocate DMA'able memory for SMB block */ 1696 error = bus_dmamem_alloc(sc->sc_dmat, ALC_SMB_SZ, 1697 ETHER_ALIGN, 0, &sc->alc_rdata.alc_smb_seg, 1, 1698 &nsegs, BUS_DMA_NOWAIT); 1699 if (error) { 1700 printf("%s: could not allocate DMA'able memory for " 1701 "SMB block\n", device_xname(sc->sc_dev)); 1702 return error; 1703 } 1704 1705 error = bus_dmamem_map(sc->sc_dmat, &sc->alc_rdata.alc_smb_seg, 1706 nsegs, ALC_SMB_SZ, (void **)&sc->alc_rdata.alc_smb, 1707 BUS_DMA_NOWAIT); 1708 if (error) 1709 return (ENOBUFS); 1710 1711 /* Load the DMA map for SMB block */ 1712 error = bus_dmamap_load(sc->sc_dmat, sc->alc_cdata.alc_smb_map, 1713 sc->alc_rdata.alc_smb, ALC_SMB_SZ, NULL, 1714 BUS_DMA_WAITOK); 1715 if (error) { 1716 printf("%s: could not load DMA'able memory for SMB block\n", 1717 device_xname(sc->sc_dev)); 1718 bus_dmamem_free(sc->sc_dmat, 1719 &sc->alc_rdata.alc_smb_seg, 1); 1720 return error; 1721 } 1722 1723 sc->alc_rdata.alc_smb_paddr = 1724 sc->alc_cdata.alc_smb_map->dm_segs[0].ds_addr; 1725 1726 1727 /* Create DMA maps for Tx buffers. */ 1728 for (i = 0; i < ALC_TX_RING_CNT; i++) { 1729 txd = &sc->alc_cdata.alc_txdesc[i]; 1730 txd->tx_m = NULL; 1731 txd->tx_dmamap = NULL; 1732 error = bus_dmamap_create(sc->sc_dmat, ALC_TSO_MAXSIZE, 1733 ALC_MAXTXSEGS, ALC_TSO_MAXSEGSIZE, 0, BUS_DMA_NOWAIT, 1734 &txd->tx_dmamap); 1735 if (error) { 1736 printf("%s: could not create Tx dmamap.\n", 1737 device_xname(sc->sc_dev)); 1738 return error; 1739 } 1740 } 1741 1742 /* Create DMA maps for Rx buffers. */ 1743 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES, 0, 1744 BUS_DMA_NOWAIT, &sc->alc_cdata.alc_rx_sparemap); 1745 if (error) { 1746 printf("%s: could not create spare Rx dmamap.\n", 1747 device_xname(sc->sc_dev)); 1748 return error; 1749 } 1750 1751 for (i = 0; i < ALC_RX_RING_CNT; i++) { 1752 rxd = &sc->alc_cdata.alc_rxdesc[i]; 1753 rxd->rx_m = NULL; 1754 rxd->rx_dmamap = NULL; 1755 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 1756 MCLBYTES, 0, BUS_DMA_NOWAIT, &rxd->rx_dmamap); 1757 if (error) { 1758 printf("%s: could not create Rx dmamap.\n", 1759 device_xname(sc->sc_dev)); 1760 return error; 1761 } 1762 } 1763 1764 return (0); 1765 } 1766 1767 1768 static void 1769 alc_dma_free(struct alc_softc *sc) 1770 { 1771 struct alc_txdesc *txd; 1772 struct alc_rxdesc *rxd; 1773 int i; 1774 1775 /* Tx buffers */ 1776 for (i = 0; i < ALC_TX_RING_CNT; i++) { 1777 txd = &sc->alc_cdata.alc_txdesc[i]; 1778 if (txd->tx_dmamap != NULL) { 1779 bus_dmamap_destroy(sc->sc_dmat, txd->tx_dmamap); 1780 txd->tx_dmamap = NULL; 1781 } 1782 } 1783 /* Rx buffers */ 1784 for (i = 0; i < ALC_RX_RING_CNT; i++) { 1785 rxd = &sc->alc_cdata.alc_rxdesc[i]; 1786 if (rxd->rx_dmamap != NULL) { 1787 bus_dmamap_destroy(sc->sc_dmat, rxd->rx_dmamap); 1788 rxd->rx_dmamap = NULL; 1789 } 1790 } 1791 if (sc->alc_cdata.alc_rx_sparemap != NULL) { 1792 bus_dmamap_destroy(sc->sc_dmat, sc->alc_cdata.alc_rx_sparemap); 1793 sc->alc_cdata.alc_rx_sparemap = NULL; 1794 } 1795 1796 /* Tx ring. */ 1797 if (sc->alc_cdata.alc_tx_ring_map != NULL) 1798 bus_dmamap_unload(sc->sc_dmat, sc->alc_cdata.alc_tx_ring_map); 1799 if (sc->alc_cdata.alc_tx_ring_map != NULL && 1800 sc->alc_rdata.alc_tx_ring != NULL) 1801 bus_dmamem_free(sc->sc_dmat, 1802 &sc->alc_rdata.alc_tx_ring_seg, 1); 1803 sc->alc_rdata.alc_tx_ring = NULL; 1804 sc->alc_cdata.alc_tx_ring_map = NULL; 1805 1806 /* Rx ring. */ 1807 if (sc->alc_cdata.alc_rx_ring_map != NULL) 1808 bus_dmamap_unload(sc->sc_dmat, sc->alc_cdata.alc_rx_ring_map); 1809 if (sc->alc_cdata.alc_rx_ring_map != NULL && 1810 sc->alc_rdata.alc_rx_ring != NULL) 1811 bus_dmamem_free(sc->sc_dmat, 1812 &sc->alc_rdata.alc_rx_ring_seg, 1); 1813 sc->alc_rdata.alc_rx_ring = NULL; 1814 sc->alc_cdata.alc_rx_ring_map = NULL; 1815 1816 /* Rx return ring. */ 1817 if (sc->alc_cdata.alc_rr_ring_map != NULL) 1818 bus_dmamap_unload(sc->sc_dmat, sc->alc_cdata.alc_rr_ring_map); 1819 if (sc->alc_cdata.alc_rr_ring_map != NULL && 1820 sc->alc_rdata.alc_rr_ring != NULL) 1821 bus_dmamem_free(sc->sc_dmat, 1822 &sc->alc_rdata.alc_rr_ring_seg, 1); 1823 sc->alc_rdata.alc_rr_ring = NULL; 1824 sc->alc_cdata.alc_rr_ring_map = NULL; 1825 1826 /* CMB block */ 1827 if (sc->alc_cdata.alc_cmb_map != NULL) 1828 bus_dmamap_unload(sc->sc_dmat, sc->alc_cdata.alc_cmb_map); 1829 if (sc->alc_cdata.alc_cmb_map != NULL && 1830 sc->alc_rdata.alc_cmb != NULL) 1831 bus_dmamem_free(sc->sc_dmat, 1832 &sc->alc_rdata.alc_cmb_seg, 1); 1833 sc->alc_rdata.alc_cmb = NULL; 1834 sc->alc_cdata.alc_cmb_map = NULL; 1835 1836 /* SMB block */ 1837 if (sc->alc_cdata.alc_smb_map != NULL) 1838 bus_dmamap_unload(sc->sc_dmat, sc->alc_cdata.alc_smb_map); 1839 if (sc->alc_cdata.alc_smb_map != NULL && 1840 sc->alc_rdata.alc_smb != NULL) 1841 bus_dmamem_free(sc->sc_dmat, 1842 &sc->alc_rdata.alc_smb_seg, 1); 1843 sc->alc_rdata.alc_smb = NULL; 1844 sc->alc_cdata.alc_smb_map = NULL; 1845 } 1846 1847 static int 1848 alc_encap(struct alc_softc *sc, struct mbuf **m_head) 1849 { 1850 struct alc_txdesc *txd, *txd_last; 1851 struct tx_desc *desc; 1852 struct mbuf *m; 1853 bus_dmamap_t map; 1854 uint32_t cflags, poff, vtag; 1855 int error, idx, nsegs, prod; 1856 1857 m = *m_head; 1858 cflags = vtag = 0; 1859 poff = 0; 1860 1861 prod = sc->alc_cdata.alc_tx_prod; 1862 txd = &sc->alc_cdata.alc_txdesc[prod]; 1863 txd_last = txd; 1864 map = txd->tx_dmamap; 1865 1866 error = bus_dmamap_load_mbuf(sc->sc_dmat, map, *m_head, BUS_DMA_NOWAIT); 1867 1868 if (error == EFBIG) { 1869 error = 0; 1870 1871 *m_head = m_pullup(*m_head, MHLEN); 1872 if (*m_head == NULL) { 1873 printf("%s: can't defrag TX mbuf\n", 1874 device_xname(sc->sc_dev)); 1875 return ENOBUFS; 1876 } 1877 1878 error = bus_dmamap_load_mbuf(sc->sc_dmat, map, *m_head, 1879 BUS_DMA_NOWAIT); 1880 1881 if (error != 0) { 1882 printf("%s: could not load defragged TX mbuf\n", 1883 device_xname(sc->sc_dev)); 1884 m_freem(*m_head); 1885 *m_head = NULL; 1886 return error; 1887 } 1888 } else if (error) { 1889 printf("%s: could not load TX mbuf\n", device_xname(sc->sc_dev)); 1890 return (error); 1891 } 1892 1893 nsegs = map->dm_nsegs; 1894 1895 if (nsegs == 0) { 1896 m_freem(*m_head); 1897 *m_head = NULL; 1898 return (EIO); 1899 } 1900 1901 /* Check descriptor overrun. */ 1902 if (sc->alc_cdata.alc_tx_cnt + nsegs >= ALC_TX_RING_CNT - 3) { 1903 bus_dmamap_unload(sc->sc_dmat, map); 1904 return (ENOBUFS); 1905 } 1906 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 1907 BUS_DMASYNC_PREWRITE); 1908 1909 m = *m_head; 1910 desc = NULL; 1911 idx = 0; 1912 #if NVLAN > 0 1913 /* Configure VLAN hardware tag insertion. */ 1914 if (vlan_has_tag(m)) { 1915 vtag = htons(vlan_get_tag(m)); 1916 vtag = (vtag << TD_VLAN_SHIFT) & TD_VLAN_MASK; 1917 cflags |= TD_INS_VLAN_TAG; 1918 } 1919 #endif 1920 /* Configure Tx checksum offload. */ 1921 if ((m->m_pkthdr.csum_flags & ALC_CSUM_FEATURES) != 0) { 1922 cflags |= TD_CUSTOM_CSUM; 1923 /* Set checksum start offset. */ 1924 cflags |= ((poff >> 1) << TD_PLOAD_OFFSET_SHIFT) & 1925 TD_PLOAD_OFFSET_MASK; 1926 } 1927 for (; idx < nsegs; idx++) { 1928 desc = &sc->alc_rdata.alc_tx_ring[prod]; 1929 desc->len = 1930 htole32(TX_BYTES(map->dm_segs[idx].ds_len) | vtag); 1931 desc->flags = htole32(cflags); 1932 desc->addr = htole64(map->dm_segs[idx].ds_addr); 1933 sc->alc_cdata.alc_tx_cnt++; 1934 ALC_DESC_INC(prod, ALC_TX_RING_CNT); 1935 } 1936 /* Update producer index. */ 1937 sc->alc_cdata.alc_tx_prod = prod; 1938 1939 /* Finally set EOP on the last descriptor. */ 1940 prod = (prod + ALC_TX_RING_CNT - 1) % ALC_TX_RING_CNT; 1941 desc = &sc->alc_rdata.alc_tx_ring[prod]; 1942 desc->flags |= htole32(TD_EOP); 1943 1944 /* Swap dmamap of the first and the last. */ 1945 txd = &sc->alc_cdata.alc_txdesc[prod]; 1946 map = txd_last->tx_dmamap; 1947 txd_last->tx_dmamap = txd->tx_dmamap; 1948 txd->tx_dmamap = map; 1949 txd->tx_m = m; 1950 1951 return (0); 1952 } 1953 1954 static void 1955 alc_start(struct ifnet *ifp) 1956 { 1957 struct alc_softc *sc = ifp->if_softc; 1958 struct mbuf *m_head; 1959 int enq; 1960 1961 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 1962 return; 1963 if ((sc->alc_flags & ALC_FLAG_LINK) == 0) 1964 return; 1965 if (IFQ_IS_EMPTY(&ifp->if_snd)) 1966 return; 1967 1968 /* Reclaim transmitted frames. */ 1969 if (sc->alc_cdata.alc_tx_cnt >= ALC_TX_DESC_HIWAT) 1970 alc_txeof(sc); 1971 1972 enq = 0; 1973 for (;;) { 1974 IFQ_DEQUEUE(&ifp->if_snd, m_head); 1975 if (m_head == NULL) 1976 break; 1977 1978 /* 1979 * Pack the data into the transmit ring. If we 1980 * don't have room, set the OACTIVE flag and wait 1981 * for the NIC to drain the ring. 1982 */ 1983 if (alc_encap(sc, &m_head)) { 1984 if (m_head == NULL) 1985 break; 1986 ifp->if_flags |= IFF_OACTIVE; 1987 break; 1988 } 1989 enq = 1; 1990 1991 /* 1992 * If there's a BPF listener, bounce a copy of this frame 1993 * to him. 1994 */ 1995 bpf_mtap(ifp, m_head); 1996 } 1997 1998 if (enq) { 1999 /* Sync descriptors. */ 2000 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_tx_ring_map, 0, 2001 sc->alc_cdata.alc_tx_ring_map->dm_mapsize, 2002 BUS_DMASYNC_PREWRITE); 2003 /* Kick. Assume we're using normal Tx priority queue. */ 2004 CSR_WRITE_4(sc, ALC_MBOX_TD_PROD_IDX, 2005 (sc->alc_cdata.alc_tx_prod << 2006 MBOX_TD_PROD_LO_IDX_SHIFT) & 2007 MBOX_TD_PROD_LO_IDX_MASK); 2008 /* Set a timeout in case the chip goes out to lunch. */ 2009 ifp->if_timer = ALC_TX_TIMEOUT; 2010 } 2011 } 2012 2013 static void 2014 alc_watchdog(struct ifnet *ifp) 2015 { 2016 struct alc_softc *sc = ifp->if_softc; 2017 2018 if ((sc->alc_flags & ALC_FLAG_LINK) == 0) { 2019 printf("%s: watchdog timeout (missed link)\n", 2020 device_xname(sc->sc_dev)); 2021 ifp->if_oerrors++; 2022 alc_init_backend(ifp, false); 2023 return; 2024 } 2025 2026 printf("%s: watchdog timeout\n", device_xname(sc->sc_dev)); 2027 ifp->if_oerrors++; 2028 alc_init_backend(ifp, false); 2029 alc_start(ifp); 2030 } 2031 2032 static int 2033 alc_ioctl(struct ifnet *ifp, u_long cmd, void *data) 2034 { 2035 struct alc_softc *sc = ifp->if_softc; 2036 struct mii_data *mii = &sc->sc_miibus; 2037 struct ifreq *ifr = (struct ifreq *)data; 2038 int s, error = 0; 2039 2040 s = splnet(); 2041 2042 error = ether_ioctl(ifp, cmd, data); 2043 switch (cmd) { 2044 case SIOCSIFADDR: 2045 ifp->if_flags |= IFF_UP; 2046 if (!(ifp->if_flags & IFF_RUNNING)) 2047 alc_init(ifp); 2048 break; 2049 2050 case SIOCSIFFLAGS: 2051 if (ifp->if_flags & IFF_UP) { 2052 if (ifp->if_flags & IFF_RUNNING) 2053 error = ENETRESET; 2054 else 2055 alc_init(ifp); 2056 } else { 2057 if (ifp->if_flags & IFF_RUNNING) 2058 alc_stop(ifp, 0); 2059 } 2060 break; 2061 2062 case SIOCSIFMEDIA: 2063 case SIOCGIFMEDIA: 2064 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd); 2065 break; 2066 2067 default: 2068 error = ether_ioctl(ifp, cmd, data); 2069 break; 2070 } 2071 2072 if (error == ENETRESET) { 2073 if (ifp->if_flags & IFF_RUNNING) 2074 alc_iff(sc); 2075 error = 0; 2076 } 2077 2078 splx(s); 2079 return (error); 2080 } 2081 2082 static void 2083 alc_mac_config(struct alc_softc *sc) 2084 { 2085 struct mii_data *mii; 2086 uint32_t reg; 2087 2088 mii = &sc->sc_miibus; 2089 reg = CSR_READ_4(sc, ALC_MAC_CFG); 2090 reg &= ~(MAC_CFG_FULL_DUPLEX | MAC_CFG_TX_FC | MAC_CFG_RX_FC | 2091 MAC_CFG_SPEED_MASK); 2092 if (sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8151 || 2093 sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8151_V2 || 2094 sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8152_B2) 2095 reg |= MAC_CFG_HASH_ALG_CRC32 | MAC_CFG_SPEED_MODE_SW; 2096 /* Reprogram MAC with resolved speed/duplex. */ 2097 switch (IFM_SUBTYPE(mii->mii_media_active)) { 2098 case IFM_10_T: 2099 case IFM_100_TX: 2100 reg |= MAC_CFG_SPEED_10_100; 2101 break; 2102 case IFM_1000_T: 2103 reg |= MAC_CFG_SPEED_1000; 2104 break; 2105 } 2106 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 2107 reg |= MAC_CFG_FULL_DUPLEX; 2108 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0) 2109 reg |= MAC_CFG_TX_FC; 2110 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0) 2111 reg |= MAC_CFG_RX_FC; 2112 } 2113 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 2114 } 2115 2116 static void 2117 alc_stats_clear(struct alc_softc *sc) 2118 { 2119 struct smb sb, *smb; 2120 uint32_t *reg; 2121 int i; 2122 2123 if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0) { 2124 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_smb_map, 0, 2125 sc->alc_cdata.alc_smb_map->dm_mapsize, 2126 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2127 smb = sc->alc_rdata.alc_smb; 2128 /* Update done, clear. */ 2129 smb->updated = 0; 2130 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_smb_map, 0, 2131 sc->alc_cdata.alc_smb_map->dm_mapsize, 2132 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2133 } else { 2134 for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered; 2135 reg++) { 2136 CSR_READ_4(sc, ALC_RX_MIB_BASE + i); 2137 i += sizeof(uint32_t); 2138 } 2139 /* Read Tx statistics. */ 2140 for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes; 2141 reg++) { 2142 CSR_READ_4(sc, ALC_TX_MIB_BASE + i); 2143 i += sizeof(uint32_t); 2144 } 2145 } 2146 } 2147 2148 static void 2149 alc_stats_update(struct alc_softc *sc) 2150 { 2151 struct ifnet *ifp = &sc->sc_ec.ec_if; 2152 struct alc_hw_stats *stat; 2153 struct smb sb, *smb; 2154 uint32_t *reg; 2155 int i; 2156 2157 stat = &sc->alc_stats; 2158 if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0) { 2159 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_smb_map, 0, 2160 sc->alc_cdata.alc_smb_map->dm_mapsize, 2161 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2162 smb = sc->alc_rdata.alc_smb; 2163 if (smb->updated == 0) 2164 return; 2165 } else { 2166 smb = &sb; 2167 /* Read Rx statistics. */ 2168 for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered; 2169 reg++) { 2170 *reg = CSR_READ_4(sc, ALC_RX_MIB_BASE + i); 2171 i += sizeof(uint32_t); 2172 } 2173 /* Read Tx statistics. */ 2174 for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes; 2175 reg++) { 2176 *reg = CSR_READ_4(sc, ALC_TX_MIB_BASE + i); 2177 i += sizeof(uint32_t); 2178 } 2179 } 2180 2181 /* Rx stats. */ 2182 stat->rx_frames += smb->rx_frames; 2183 stat->rx_bcast_frames += smb->rx_bcast_frames; 2184 stat->rx_mcast_frames += smb->rx_mcast_frames; 2185 stat->rx_pause_frames += smb->rx_pause_frames; 2186 stat->rx_control_frames += smb->rx_control_frames; 2187 stat->rx_crcerrs += smb->rx_crcerrs; 2188 stat->rx_lenerrs += smb->rx_lenerrs; 2189 stat->rx_bytes += smb->rx_bytes; 2190 stat->rx_runts += smb->rx_runts; 2191 stat->rx_fragments += smb->rx_fragments; 2192 stat->rx_pkts_64 += smb->rx_pkts_64; 2193 stat->rx_pkts_65_127 += smb->rx_pkts_65_127; 2194 stat->rx_pkts_128_255 += smb->rx_pkts_128_255; 2195 stat->rx_pkts_256_511 += smb->rx_pkts_256_511; 2196 stat->rx_pkts_512_1023 += smb->rx_pkts_512_1023; 2197 stat->rx_pkts_1024_1518 += smb->rx_pkts_1024_1518; 2198 stat->rx_pkts_1519_max += smb->rx_pkts_1519_max; 2199 stat->rx_pkts_truncated += smb->rx_pkts_truncated; 2200 stat->rx_fifo_oflows += smb->rx_fifo_oflows; 2201 stat->rx_rrs_errs += smb->rx_rrs_errs; 2202 stat->rx_alignerrs += smb->rx_alignerrs; 2203 stat->rx_bcast_bytes += smb->rx_bcast_bytes; 2204 stat->rx_mcast_bytes += smb->rx_mcast_bytes; 2205 stat->rx_pkts_filtered += smb->rx_pkts_filtered; 2206 2207 /* Tx stats. */ 2208 stat->tx_frames += smb->tx_frames; 2209 stat->tx_bcast_frames += smb->tx_bcast_frames; 2210 stat->tx_mcast_frames += smb->tx_mcast_frames; 2211 stat->tx_pause_frames += smb->tx_pause_frames; 2212 stat->tx_excess_defer += smb->tx_excess_defer; 2213 stat->tx_control_frames += smb->tx_control_frames; 2214 stat->tx_deferred += smb->tx_deferred; 2215 stat->tx_bytes += smb->tx_bytes; 2216 stat->tx_pkts_64 += smb->tx_pkts_64; 2217 stat->tx_pkts_65_127 += smb->tx_pkts_65_127; 2218 stat->tx_pkts_128_255 += smb->tx_pkts_128_255; 2219 stat->tx_pkts_256_511 += smb->tx_pkts_256_511; 2220 stat->tx_pkts_512_1023 += smb->tx_pkts_512_1023; 2221 stat->tx_pkts_1024_1518 += smb->tx_pkts_1024_1518; 2222 stat->tx_pkts_1519_max += smb->tx_pkts_1519_max; 2223 stat->tx_single_colls += smb->tx_single_colls; 2224 stat->tx_multi_colls += smb->tx_multi_colls; 2225 stat->tx_late_colls += smb->tx_late_colls; 2226 stat->tx_excess_colls += smb->tx_excess_colls; 2227 stat->tx_underrun += smb->tx_underrun; 2228 stat->tx_desc_underrun += smb->tx_desc_underrun; 2229 stat->tx_lenerrs += smb->tx_lenerrs; 2230 stat->tx_pkts_truncated += smb->tx_pkts_truncated; 2231 stat->tx_bcast_bytes += smb->tx_bcast_bytes; 2232 stat->tx_mcast_bytes += smb->tx_mcast_bytes; 2233 2234 /* Update counters in ifnet. */ 2235 ifp->if_opackets += smb->tx_frames; 2236 2237 ifp->if_collisions += smb->tx_single_colls + 2238 smb->tx_multi_colls * 2 + smb->tx_late_colls + 2239 smb->tx_excess_colls * HDPX_CFG_RETRY_DEFAULT; 2240 2241 ifp->if_oerrors += smb->tx_late_colls + smb->tx_excess_colls + 2242 smb->tx_underrun + smb->tx_pkts_truncated; 2243 2244 ifp->if_ipackets += smb->rx_frames; 2245 2246 ifp->if_ierrors += smb->rx_crcerrs + smb->rx_lenerrs + 2247 smb->rx_runts + smb->rx_pkts_truncated + 2248 smb->rx_fifo_oflows + smb->rx_rrs_errs + 2249 smb->rx_alignerrs; 2250 2251 if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0) { 2252 /* Update done, clear. */ 2253 smb->updated = 0; 2254 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_smb_map, 0, 2255 sc->alc_cdata.alc_smb_map->dm_mapsize, 2256 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2257 } 2258 } 2259 2260 static int 2261 alc_intr(void *arg) 2262 { 2263 struct alc_softc *sc = arg; 2264 struct ifnet *ifp = &sc->sc_ec.ec_if; 2265 uint32_t status; 2266 2267 status = CSR_READ_4(sc, ALC_INTR_STATUS); 2268 if ((status & ALC_INTRS) == 0) 2269 return (0); 2270 2271 /* Acknowledge and disable interrupts. */ 2272 CSR_WRITE_4(sc, ALC_INTR_STATUS, status | INTR_DIS_INT); 2273 2274 if (ifp->if_flags & IFF_RUNNING) { 2275 if (status & INTR_RX_PKT) { 2276 int error; 2277 2278 error = alc_rxintr(sc); 2279 if (error) { 2280 alc_init_backend(ifp, false); 2281 return (0); 2282 } 2283 } 2284 2285 if (status & (INTR_DMA_RD_TO_RST | INTR_DMA_WR_TO_RST | 2286 INTR_TXQ_TO_RST)) { 2287 if (status & INTR_DMA_RD_TO_RST) 2288 printf("%s: DMA read error! -- resetting\n", 2289 device_xname(sc->sc_dev)); 2290 if (status & INTR_DMA_WR_TO_RST) 2291 printf("%s: DMA write error! -- resetting\n", 2292 device_xname(sc->sc_dev)); 2293 if (status & INTR_TXQ_TO_RST) 2294 printf("%s: TxQ reset! -- resetting\n", 2295 device_xname(sc->sc_dev)); 2296 alc_init_backend(ifp, false); 2297 return (0); 2298 } 2299 2300 alc_txeof(sc); 2301 if_schedule_deferred_start(ifp); 2302 } 2303 2304 /* Re-enable interrupts. */ 2305 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0x7FFFFFFF); 2306 return (1); 2307 } 2308 2309 static void 2310 alc_txeof(struct alc_softc *sc) 2311 { 2312 struct ifnet *ifp = &sc->sc_ec.ec_if; 2313 struct alc_txdesc *txd; 2314 uint32_t cons, prod; 2315 int prog; 2316 2317 if (sc->alc_cdata.alc_tx_cnt == 0) 2318 return; 2319 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_tx_ring_map, 0, 2320 sc->alc_cdata.alc_tx_ring_map->dm_mapsize, 2321 BUS_DMASYNC_POSTREAD); 2322 if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0) { 2323 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_cmb_map, 0, 2324 sc->alc_cdata.alc_cmb_map->dm_mapsize, 2325 BUS_DMASYNC_POSTREAD); 2326 prod = sc->alc_rdata.alc_cmb->cons; 2327 } else 2328 prod = CSR_READ_4(sc, ALC_MBOX_TD_CONS_IDX); 2329 /* Assume we're using normal Tx priority queue. */ 2330 prod = (prod & MBOX_TD_CONS_LO_IDX_MASK) >> 2331 MBOX_TD_CONS_LO_IDX_SHIFT; 2332 cons = sc->alc_cdata.alc_tx_cons; 2333 /* 2334 * Go through our Tx list and free mbufs for those 2335 * frames which have been transmitted. 2336 */ 2337 for (prog = 0; cons != prod; prog++, 2338 ALC_DESC_INC(cons, ALC_TX_RING_CNT)) { 2339 if (sc->alc_cdata.alc_tx_cnt <= 0) 2340 break; 2341 prog++; 2342 ifp->if_flags &= ~IFF_OACTIVE; 2343 sc->alc_cdata.alc_tx_cnt--; 2344 txd = &sc->alc_cdata.alc_txdesc[cons]; 2345 if (txd->tx_m != NULL) { 2346 /* Reclaim transmitted mbufs. */ 2347 bus_dmamap_sync(sc->sc_dmat, txd->tx_dmamap, 0, 2348 txd->tx_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 2349 bus_dmamap_unload(sc->sc_dmat, txd->tx_dmamap); 2350 m_freem(txd->tx_m); 2351 txd->tx_m = NULL; 2352 } 2353 } 2354 2355 if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0) 2356 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_cmb_map, 0, 2357 sc->alc_cdata.alc_cmb_map->dm_mapsize, BUS_DMASYNC_PREREAD); 2358 sc->alc_cdata.alc_tx_cons = cons; 2359 /* 2360 * Unarm watchdog timer only when there is no pending 2361 * frames in Tx queue. 2362 */ 2363 if (sc->alc_cdata.alc_tx_cnt == 0) 2364 ifp->if_timer = 0; 2365 } 2366 2367 static int 2368 alc_newbuf(struct alc_softc *sc, struct alc_rxdesc *rxd, bool init) 2369 { 2370 struct mbuf *m; 2371 bus_dmamap_t map; 2372 int error; 2373 2374 MGETHDR(m, init ? M_WAITOK : M_DONTWAIT, MT_DATA); 2375 if (m == NULL) 2376 return (ENOBUFS); 2377 MCLGET(m, init ? M_WAITOK : M_DONTWAIT); 2378 if (!(m->m_flags & M_EXT)) { 2379 m_freem(m); 2380 return (ENOBUFS); 2381 } 2382 2383 m->m_len = m->m_pkthdr.len = RX_BUF_SIZE_MAX; 2384 2385 error = bus_dmamap_load_mbuf(sc->sc_dmat, 2386 sc->alc_cdata.alc_rx_sparemap, m, BUS_DMA_NOWAIT); 2387 2388 if (error != 0) { 2389 m_freem(m); 2390 2391 if (init) 2392 printf("%s: can't load RX mbuf\n", device_xname(sc->sc_dev)); 2393 2394 return (error); 2395 } 2396 2397 if (rxd->rx_m != NULL) { 2398 bus_dmamap_sync(sc->sc_dmat, rxd->rx_dmamap, 0, 2399 rxd->rx_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 2400 bus_dmamap_unload(sc->sc_dmat, rxd->rx_dmamap); 2401 } 2402 map = rxd->rx_dmamap; 2403 rxd->rx_dmamap = sc->alc_cdata.alc_rx_sparemap; 2404 sc->alc_cdata.alc_rx_sparemap = map; 2405 bus_dmamap_sync(sc->sc_dmat, rxd->rx_dmamap, 0, rxd->rx_dmamap->dm_mapsize, 2406 BUS_DMASYNC_PREREAD); 2407 rxd->rx_m = m; 2408 rxd->rx_desc->addr = htole64(rxd->rx_dmamap->dm_segs[0].ds_addr); 2409 return (0); 2410 } 2411 2412 static int 2413 alc_rxintr(struct alc_softc *sc) 2414 { 2415 struct ifnet *ifp = &sc->sc_ec.ec_if; 2416 struct rx_rdesc *rrd; 2417 uint32_t nsegs, status; 2418 int rr_cons, prog; 2419 2420 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_rr_ring_map, 0, 2421 sc->alc_cdata.alc_rr_ring_map->dm_mapsize, 2422 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2423 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_rx_ring_map, 0, 2424 sc->alc_cdata.alc_rx_ring_map->dm_mapsize, 2425 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2426 rr_cons = sc->alc_cdata.alc_rr_cons; 2427 for (prog = 0; (ifp->if_flags & IFF_RUNNING) != 0;) { 2428 rrd = &sc->alc_rdata.alc_rr_ring[rr_cons]; 2429 status = le32toh(rrd->status); 2430 if ((status & RRD_VALID) == 0) 2431 break; 2432 nsegs = RRD_RD_CNT(le32toh(rrd->rdinfo)); 2433 if (nsegs == 0) { 2434 /* This should not happen! */ 2435 if (alcdebug) 2436 printf("%s: unexpected segment count -- " 2437 "resetting\n", device_xname(sc->sc_dev)); 2438 return (EIO); 2439 } 2440 alc_rxeof(sc, rrd); 2441 /* Clear Rx return status. */ 2442 rrd->status = 0; 2443 ALC_DESC_INC(rr_cons, ALC_RR_RING_CNT); 2444 sc->alc_cdata.alc_rx_cons += nsegs; 2445 sc->alc_cdata.alc_rx_cons %= ALC_RR_RING_CNT; 2446 prog += nsegs; 2447 } 2448 2449 if (prog > 0) { 2450 /* Update the consumer index. */ 2451 sc->alc_cdata.alc_rr_cons = rr_cons; 2452 /* Sync Rx return descriptors. */ 2453 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_rr_ring_map, 0, 2454 sc->alc_cdata.alc_rr_ring_map->dm_mapsize, 2455 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2456 /* 2457 * Sync updated Rx descriptors such that controller see 2458 * modified buffer addresses. 2459 */ 2460 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_rx_ring_map, 0, 2461 sc->alc_cdata.alc_rx_ring_map->dm_mapsize, 2462 BUS_DMASYNC_PREWRITE); 2463 /* 2464 * Let controller know availability of new Rx buffers. 2465 * Since alc(4) use RXQ_CFG_RD_BURST_DEFAULT descriptors 2466 * it may be possible to update ALC_MBOX_RD0_PROD_IDX 2467 * only when Rx buffer pre-fetching is required. In 2468 * addition we already set ALC_RX_RD_FREE_THRESH to 2469 * RX_RD_FREE_THRESH_LO_DEFAULT descriptors. However 2470 * it still seems that pre-fetching needs more 2471 * experimentation. 2472 */ 2473 CSR_WRITE_4(sc, ALC_MBOX_RD0_PROD_IDX, 2474 sc->alc_cdata.alc_rx_cons); 2475 } 2476 2477 return (0); 2478 } 2479 2480 /* Receive a frame. */ 2481 static void 2482 alc_rxeof(struct alc_softc *sc, struct rx_rdesc *rrd) 2483 { 2484 struct ifnet *ifp = &sc->sc_ec.ec_if; 2485 struct alc_rxdesc *rxd; 2486 struct mbuf *mp, *m; 2487 uint32_t rdinfo, status; 2488 int count, nsegs, rx_cons; 2489 2490 status = le32toh(rrd->status); 2491 rdinfo = le32toh(rrd->rdinfo); 2492 rx_cons = RRD_RD_IDX(rdinfo); 2493 nsegs = RRD_RD_CNT(rdinfo); 2494 2495 sc->alc_cdata.alc_rxlen = RRD_BYTES(status); 2496 if (status & (RRD_ERR_SUM | RRD_ERR_LENGTH)) { 2497 /* 2498 * We want to pass the following frames to upper 2499 * layer regardless of error status of Rx return 2500 * ring. 2501 * 2502 * o IP/TCP/UDP checksum is bad. 2503 * o frame length and protocol specific length 2504 * does not match. 2505 * 2506 * Force network stack compute checksum for 2507 * errored frames. 2508 */ 2509 status |= RRD_TCP_UDPCSUM_NOK | RRD_IPCSUM_NOK; 2510 if ((status & (RRD_ERR_CRC | RRD_ERR_ALIGN | 2511 RRD_ERR_TRUNC | RRD_ERR_RUNT)) != 0) 2512 return; 2513 } 2514 2515 for (count = 0; count < nsegs; count++, 2516 ALC_DESC_INC(rx_cons, ALC_RX_RING_CNT)) { 2517 rxd = &sc->alc_cdata.alc_rxdesc[rx_cons]; 2518 mp = rxd->rx_m; 2519 /* Add a new receive buffer to the ring. */ 2520 if (alc_newbuf(sc, rxd, false) != 0) { 2521 ifp->if_iqdrops++; 2522 /* Reuse Rx buffers. */ 2523 if (sc->alc_cdata.alc_rxhead != NULL) 2524 m_freem(sc->alc_cdata.alc_rxhead); 2525 break; 2526 } 2527 2528 /* 2529 * Assume we've received a full sized frame. 2530 * Actual size is fixed when we encounter the end of 2531 * multi-segmented frame. 2532 */ 2533 mp->m_len = sc->alc_buf_size; 2534 2535 /* Chain received mbufs. */ 2536 if (sc->alc_cdata.alc_rxhead == NULL) { 2537 sc->alc_cdata.alc_rxhead = mp; 2538 sc->alc_cdata.alc_rxtail = mp; 2539 } else { 2540 mp->m_flags &= ~M_PKTHDR; 2541 sc->alc_cdata.alc_rxprev_tail = 2542 sc->alc_cdata.alc_rxtail; 2543 sc->alc_cdata.alc_rxtail->m_next = mp; 2544 sc->alc_cdata.alc_rxtail = mp; 2545 } 2546 2547 if (count == nsegs - 1) { 2548 /* Last desc. for this frame. */ 2549 m = sc->alc_cdata.alc_rxhead; 2550 m->m_flags |= M_PKTHDR; 2551 /* 2552 * It seems that L1C/L2C controller has no way 2553 * to tell hardware to strip CRC bytes. 2554 */ 2555 m->m_pkthdr.len = 2556 sc->alc_cdata.alc_rxlen - ETHER_CRC_LEN; 2557 if (nsegs > 1) { 2558 /* Set last mbuf size. */ 2559 mp->m_len = sc->alc_cdata.alc_rxlen - 2560 (nsegs - 1) * sc->alc_buf_size; 2561 /* Remove the CRC bytes in chained mbufs. */ 2562 if (mp->m_len <= ETHER_CRC_LEN) { 2563 sc->alc_cdata.alc_rxtail = 2564 sc->alc_cdata.alc_rxprev_tail; 2565 sc->alc_cdata.alc_rxtail->m_len -= 2566 (ETHER_CRC_LEN - mp->m_len); 2567 sc->alc_cdata.alc_rxtail->m_next = NULL; 2568 m_freem(mp); 2569 } else { 2570 mp->m_len -= ETHER_CRC_LEN; 2571 } 2572 } else 2573 m->m_len = m->m_pkthdr.len; 2574 m_set_rcvif(m, ifp); 2575 #if NVLAN > 0 2576 /* 2577 * Due to hardware bugs, Rx checksum offloading 2578 * was intentionally disabled. 2579 */ 2580 if (status & RRD_VLAN_TAG) { 2581 u_int32_t vtag = RRD_VLAN(le32toh(rrd->vtag)); 2582 vlan_set_tag(m, ntohs(vtag)); 2583 } 2584 #endif 2585 2586 /* Pass it on. */ 2587 if_percpuq_enqueue(ifp->if_percpuq, m); 2588 } 2589 } 2590 /* Reset mbuf chains. */ 2591 ALC_RXCHAIN_RESET(sc); 2592 } 2593 2594 static void 2595 alc_tick(void *xsc) 2596 { 2597 struct alc_softc *sc = xsc; 2598 struct mii_data *mii = &sc->sc_miibus; 2599 int s; 2600 2601 s = splnet(); 2602 mii_tick(mii); 2603 alc_stats_update(sc); 2604 splx(s); 2605 2606 callout_schedule(&sc->sc_tick_ch, hz); 2607 } 2608 2609 static void 2610 alc_osc_reset(struct alc_softc *sc) 2611 { 2612 uint32_t reg; 2613 2614 reg = CSR_READ_4(sc, ALC_MISC3); 2615 reg &= ~MISC3_25M_BY_SW; 2616 reg |= MISC3_25M_NOTO_INTNL; 2617 CSR_WRITE_4(sc, ALC_MISC3, reg); 2618 2619 reg = CSR_READ_4(sc, ALC_MISC); 2620 if (AR816X_REV(sc->alc_rev) >= AR816X_REV_B0) { 2621 /* 2622 * Restore over-current protection default value. 2623 * This value could be reset by MAC reset. 2624 */ 2625 reg &= ~MISC_PSW_OCP_MASK; 2626 reg |= (MISC_PSW_OCP_DEFAULT << MISC_PSW_OCP_SHIFT); 2627 reg &= ~MISC_INTNLOSC_OPEN; 2628 CSR_WRITE_4(sc, ALC_MISC, reg); 2629 CSR_WRITE_4(sc, ALC_MISC, reg | MISC_INTNLOSC_OPEN); 2630 reg = CSR_READ_4(sc, ALC_MISC2); 2631 reg &= ~MISC2_CALB_START; 2632 CSR_WRITE_4(sc, ALC_MISC2, reg); 2633 CSR_WRITE_4(sc, ALC_MISC2, reg | MISC2_CALB_START); 2634 2635 } else { 2636 reg &= ~MISC_INTNLOSC_OPEN; 2637 /* Disable isolate for revision A devices. */ 2638 if (AR816X_REV(sc->alc_rev) <= AR816X_REV_A1) 2639 reg &= ~MISC_ISO_ENB; 2640 CSR_WRITE_4(sc, ALC_MISC, reg | MISC_INTNLOSC_OPEN); 2641 CSR_WRITE_4(sc, ALC_MISC, reg); 2642 } 2643 2644 DELAY(20); 2645 } 2646 2647 static void 2648 alc_reset(struct alc_softc *sc) 2649 { 2650 uint32_t pmcfg, reg; 2651 int i; 2652 2653 pmcfg = 0; 2654 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 2655 /* Reset workaround. */ 2656 CSR_WRITE_4(sc, ALC_MBOX_RD0_PROD_IDX, 1); 2657 if (AR816X_REV(sc->alc_rev) <= AR816X_REV_A1 && 2658 (sc->alc_rev & 0x01) != 0) { 2659 /* Disable L0s/L1s before reset. */ 2660 pmcfg = CSR_READ_4(sc, ALC_PM_CFG); 2661 if ((pmcfg & (PM_CFG_ASPM_L0S_ENB | PM_CFG_ASPM_L1_ENB)) 2662 != 0) { 2663 pmcfg &= ~(PM_CFG_ASPM_L0S_ENB | 2664 PM_CFG_ASPM_L1_ENB); 2665 CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg); 2666 } 2667 } 2668 } 2669 reg = CSR_READ_4(sc, ALC_MASTER_CFG); 2670 reg |= MASTER_OOB_DIS_OFF | MASTER_RESET; 2671 CSR_WRITE_4(sc, ALC_MASTER_CFG, reg); 2672 2673 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 2674 for (i = ALC_RESET_TIMEOUT; i > 0; i--) { 2675 DELAY(10); 2676 if (CSR_READ_4(sc, ALC_MBOX_RD0_PROD_IDX) == 0) 2677 break; 2678 } 2679 if (i == 0) 2680 printf("%s: MAC reset timeout!\n", device_xname(sc->sc_dev)); 2681 } 2682 for (i = ALC_RESET_TIMEOUT; i > 0; i--) { 2683 DELAY(10); 2684 if ((CSR_READ_4(sc, ALC_MASTER_CFG) & MASTER_RESET) == 0) 2685 break; 2686 } 2687 if (i == 0) 2688 printf("%s: master reset timeout!\n", device_xname(sc->sc_dev)); 2689 2690 for (i = ALC_RESET_TIMEOUT; i > 0; i--) { 2691 reg = CSR_READ_4(sc, ALC_IDLE_STATUS); 2692 if ((reg & (IDLE_STATUS_RXMAC | IDLE_STATUS_TXMAC | 2693 IDLE_STATUS_RXQ | IDLE_STATUS_TXQ)) == 0) 2694 break; 2695 DELAY(10); 2696 } 2697 if (i == 0) 2698 printf("%s: reset timeout(0x%08x)!\n", 2699 device_xname(sc->sc_dev), reg); 2700 2701 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 2702 if (AR816X_REV(sc->alc_rev) <= AR816X_REV_A1 && 2703 (sc->alc_rev & 0x01) != 0) { 2704 reg = CSR_READ_4(sc, ALC_MASTER_CFG); 2705 reg |= MASTER_CLK_SEL_DIS; 2706 CSR_WRITE_4(sc, ALC_MASTER_CFG, reg); 2707 /* Restore L0s/L1s config. */ 2708 if ((pmcfg & (PM_CFG_ASPM_L0S_ENB | PM_CFG_ASPM_L1_ENB)) 2709 != 0) 2710 CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg); 2711 } 2712 2713 alc_osc_reset(sc); 2714 reg = CSR_READ_4(sc, ALC_MISC3); 2715 reg &= ~MISC3_25M_BY_SW; 2716 reg |= MISC3_25M_NOTO_INTNL; 2717 CSR_WRITE_4(sc, ALC_MISC3, reg); 2718 reg = CSR_READ_4(sc, ALC_MISC); 2719 reg &= ~MISC_INTNLOSC_OPEN; 2720 if (AR816X_REV(sc->alc_rev) <= AR816X_REV_A1) 2721 reg &= ~MISC_ISO_ENB; 2722 CSR_WRITE_4(sc, ALC_MISC, reg); 2723 DELAY(20); 2724 } 2725 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0 || 2726 sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8152_B || 2727 sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8151_V2) 2728 CSR_WRITE_4(sc, ALC_SERDES_LOCK, 2729 CSR_READ_4(sc, ALC_SERDES_LOCK) | SERDES_MAC_CLK_SLOWDOWN | 2730 SERDES_PHY_CLK_SLOWDOWN); 2731 } 2732 2733 static int 2734 alc_init(struct ifnet *ifp) 2735 { 2736 2737 return alc_init_backend(ifp, true); 2738 } 2739 2740 static int 2741 alc_init_backend(struct ifnet *ifp, bool init) 2742 { 2743 struct alc_softc *sc = ifp->if_softc; 2744 struct mii_data *mii; 2745 uint8_t eaddr[ETHER_ADDR_LEN]; 2746 bus_addr_t paddr; 2747 uint32_t reg, rxf_hi, rxf_lo; 2748 int error; 2749 2750 /* 2751 * Cancel any pending I/O. 2752 */ 2753 alc_stop(ifp, 0); 2754 /* 2755 * Reset the chip to a known state. 2756 */ 2757 alc_reset(sc); 2758 2759 /* Initialize Rx descriptors. */ 2760 error = alc_init_rx_ring(sc, init); 2761 if (error != 0) { 2762 printf("%s: no memory for Rx buffers.\n", device_xname(sc->sc_dev)); 2763 alc_stop(ifp, 0); 2764 return (error); 2765 } 2766 alc_init_rr_ring(sc); 2767 alc_init_tx_ring(sc); 2768 alc_init_cmb(sc); 2769 alc_init_smb(sc); 2770 2771 /* Enable all clocks. */ 2772 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 2773 CSR_WRITE_4(sc, ALC_CLK_GATING_CFG, CLK_GATING_DMAW_ENB | 2774 CLK_GATING_DMAR_ENB | CLK_GATING_TXQ_ENB | 2775 CLK_GATING_RXQ_ENB | CLK_GATING_TXMAC_ENB | 2776 CLK_GATING_RXMAC_ENB); 2777 if (AR816X_REV(sc->alc_rev) >= AR816X_REV_B0) 2778 CSR_WRITE_4(sc, ALC_IDLE_DECISN_TIMER, 2779 IDLE_DECISN_TIMER_DEFAULT_1MS); 2780 } else 2781 CSR_WRITE_4(sc, ALC_CLK_GATING_CFG, 0); 2782 2783 2784 /* Reprogram the station address. */ 2785 memcpy(eaddr, CLLADDR(ifp->if_sadl), sizeof(eaddr)); 2786 CSR_WRITE_4(sc, ALC_PAR0, 2787 eaddr[2] << 24 | eaddr[3] << 16 | eaddr[4] << 8 | eaddr[5]); 2788 CSR_WRITE_4(sc, ALC_PAR1, eaddr[0] << 8 | eaddr[1]); 2789 /* 2790 * Clear WOL status and disable all WOL feature as WOL 2791 * would interfere Rx operation under normal environments. 2792 */ 2793 CSR_READ_4(sc, ALC_WOL_CFG); 2794 CSR_WRITE_4(sc, ALC_WOL_CFG, 0); 2795 /* Set Tx descriptor base addresses. */ 2796 paddr = sc->alc_rdata.alc_tx_ring_paddr; 2797 CSR_WRITE_4(sc, ALC_TX_BASE_ADDR_HI, ALC_ADDR_HI(paddr)); 2798 CSR_WRITE_4(sc, ALC_TDL_HEAD_ADDR_LO, ALC_ADDR_LO(paddr)); 2799 /* We don't use high priority ring. */ 2800 CSR_WRITE_4(sc, ALC_TDH_HEAD_ADDR_LO, 0); 2801 /* Set Tx descriptor counter. */ 2802 CSR_WRITE_4(sc, ALC_TD_RING_CNT, 2803 (ALC_TX_RING_CNT << TD_RING_CNT_SHIFT) & TD_RING_CNT_MASK); 2804 /* Set Rx descriptor base addresses. */ 2805 paddr = sc->alc_rdata.alc_rx_ring_paddr; 2806 CSR_WRITE_4(sc, ALC_RX_BASE_ADDR_HI, ALC_ADDR_HI(paddr)); 2807 CSR_WRITE_4(sc, ALC_RD0_HEAD_ADDR_LO, ALC_ADDR_LO(paddr)); 2808 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 2809 /* We use one Rx ring. */ 2810 CSR_WRITE_4(sc, ALC_RD1_HEAD_ADDR_LO, 0); 2811 CSR_WRITE_4(sc, ALC_RD2_HEAD_ADDR_LO, 0); 2812 CSR_WRITE_4(sc, ALC_RD3_HEAD_ADDR_LO, 0); 2813 } 2814 /* Set Rx descriptor counter. */ 2815 CSR_WRITE_4(sc, ALC_RD_RING_CNT, 2816 (ALC_RX_RING_CNT << RD_RING_CNT_SHIFT) & RD_RING_CNT_MASK); 2817 2818 /* 2819 * Let hardware split jumbo frames into alc_max_buf_sized chunks. 2820 * if it do not fit the buffer size. Rx return descriptor holds 2821 * a counter that indicates how many fragments were made by the 2822 * hardware. The buffer size should be multiple of 8 bytes. 2823 * Since hardware has limit on the size of buffer size, always 2824 * use the maximum value. 2825 * For strict-alignment architectures make sure to reduce buffer 2826 * size by 8 bytes to make room for alignment fixup. 2827 */ 2828 sc->alc_buf_size = RX_BUF_SIZE_MAX; 2829 CSR_WRITE_4(sc, ALC_RX_BUF_SIZE, sc->alc_buf_size); 2830 2831 paddr = sc->alc_rdata.alc_rr_ring_paddr; 2832 /* Set Rx return descriptor base addresses. */ 2833 CSR_WRITE_4(sc, ALC_RRD0_HEAD_ADDR_LO, ALC_ADDR_LO(paddr)); 2834 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 2835 /* We use one Rx return ring. */ 2836 CSR_WRITE_4(sc, ALC_RRD1_HEAD_ADDR_LO, 0); 2837 CSR_WRITE_4(sc, ALC_RRD2_HEAD_ADDR_LO, 0); 2838 CSR_WRITE_4(sc, ALC_RRD3_HEAD_ADDR_LO, 0); 2839 }\ 2840 /* Set Rx return descriptor counter. */ 2841 CSR_WRITE_4(sc, ALC_RRD_RING_CNT, 2842 (ALC_RR_RING_CNT << RRD_RING_CNT_SHIFT) & RRD_RING_CNT_MASK); 2843 paddr = sc->alc_rdata.alc_cmb_paddr; 2844 CSR_WRITE_4(sc, ALC_CMB_BASE_ADDR_LO, ALC_ADDR_LO(paddr)); 2845 paddr = sc->alc_rdata.alc_smb_paddr; 2846 CSR_WRITE_4(sc, ALC_SMB_BASE_ADDR_HI, ALC_ADDR_HI(paddr)); 2847 CSR_WRITE_4(sc, ALC_SMB_BASE_ADDR_LO, ALC_ADDR_LO(paddr)); 2848 2849 if (sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8152_B) { 2850 /* Reconfigure SRAM - Vendor magic. */ 2851 CSR_WRITE_4(sc, ALC_SRAM_RX_FIFO_LEN, 0x000002A0); 2852 CSR_WRITE_4(sc, ALC_SRAM_TX_FIFO_LEN, 0x00000100); 2853 CSR_WRITE_4(sc, ALC_SRAM_RX_FIFO_ADDR, 0x029F0000); 2854 CSR_WRITE_4(sc, ALC_SRAM_RD0_ADDR, 0x02BF02A0); 2855 CSR_WRITE_4(sc, ALC_SRAM_TX_FIFO_ADDR, 0x03BF02C0); 2856 CSR_WRITE_4(sc, ALC_SRAM_TD_ADDR, 0x03DF03C0); 2857 CSR_WRITE_4(sc, ALC_TXF_WATER_MARK, 0x00000000); 2858 CSR_WRITE_4(sc, ALC_RD_DMA_CFG, 0x00000000); 2859 } 2860 2861 /* Tell hardware that we're ready to load DMA blocks. */ 2862 CSR_WRITE_4(sc, ALC_DMA_BLOCK, DMA_BLOCK_LOAD); 2863 2864 /* Configure interrupt moderation timer. */ 2865 sc->alc_int_rx_mod = ALC_IM_RX_TIMER_DEFAULT; 2866 sc->alc_int_tx_mod = ALC_IM_TX_TIMER_DEFAULT; 2867 reg = ALC_USECS(sc->alc_int_rx_mod) << IM_TIMER_RX_SHIFT; 2868 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) 2869 reg |= ALC_USECS(sc->alc_int_tx_mod) << IM_TIMER_TX_SHIFT; 2870 CSR_WRITE_4(sc, ALC_IM_TIMER, reg); 2871 /* 2872 * We don't want to automatic interrupt clear as task queue 2873 * for the interrupt should know interrupt status. 2874 */ 2875 reg = CSR_READ_4(sc, ALC_MASTER_CFG); 2876 reg &= ~(MASTER_IM_RX_TIMER_ENB | MASTER_IM_TX_TIMER_ENB); 2877 reg |= MASTER_SA_TIMER_ENB; 2878 if (ALC_USECS(sc->alc_int_rx_mod) != 0) 2879 reg |= MASTER_IM_RX_TIMER_ENB; 2880 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0 && 2881 ALC_USECS(sc->alc_int_tx_mod) != 0) 2882 reg |= MASTER_IM_TX_TIMER_ENB; 2883 CSR_WRITE_4(sc, ALC_MASTER_CFG, reg); 2884 /* 2885 * Disable interrupt re-trigger timer. We don't want automatic 2886 * re-triggering of un-ACKed interrupts. 2887 */ 2888 CSR_WRITE_4(sc, ALC_INTR_RETRIG_TIMER, ALC_USECS(0)); 2889 /* Configure CMB. */ 2890 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 2891 CSR_WRITE_4(sc, ALC_CMB_TD_THRESH, ALC_TX_RING_CNT / 3); 2892 CSR_WRITE_4(sc, ALC_CMB_TX_TIMER, 2893 ALC_USECS(sc->alc_int_tx_mod)); 2894 } else { 2895 if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0) { 2896 CSR_WRITE_4(sc, ALC_CMB_TD_THRESH, 4); 2897 CSR_WRITE_4(sc, ALC_CMB_TX_TIMER, ALC_USECS(5000)); 2898 } else 2899 CSR_WRITE_4(sc, ALC_CMB_TX_TIMER, ALC_USECS(0)); 2900 } 2901 /* 2902 * Hardware can be configured to issue SMB interrupt based 2903 * on programmed interval. Since there is a callout that is 2904 * invoked for every hz in driver we use that instead of 2905 * relying on periodic SMB interrupt. 2906 */ 2907 CSR_WRITE_4(sc, ALC_SMB_STAT_TIMER, ALC_USECS(0)); 2908 /* Clear MAC statistics. */ 2909 alc_stats_clear(sc); 2910 2911 /* 2912 * Always use maximum frame size that controller can support. 2913 * Otherwise received frames that has larger frame length 2914 * than alc(4) MTU would be silently dropped in hardware. This 2915 * would make path-MTU discovery hard as sender wouldn't get 2916 * any responses from receiver. alc(4) supports 2917 * multi-fragmented frames on Rx path so it has no issue on 2918 * assembling fragmented frames. Using maximum frame size also 2919 * removes the need to reinitialize hardware when interface 2920 * MTU configuration was changed. 2921 * 2922 * Be conservative in what you do, be liberal in what you 2923 * accept from others - RFC 793. 2924 */ 2925 CSR_WRITE_4(sc, ALC_FRAME_SIZE, sc->alc_ident->max_framelen); 2926 2927 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 2928 /* Disable header split(?) */ 2929 CSR_WRITE_4(sc, ALC_HDS_CFG, 0); 2930 2931 /* Configure IPG/IFG parameters. */ 2932 CSR_WRITE_4(sc, ALC_IPG_IFG_CFG, 2933 ((IPG_IFG_IPGT_DEFAULT << IPG_IFG_IPGT_SHIFT) & 2934 IPG_IFG_IPGT_MASK) | 2935 ((IPG_IFG_MIFG_DEFAULT << IPG_IFG_MIFG_SHIFT) & 2936 IPG_IFG_MIFG_MASK) | 2937 ((IPG_IFG_IPG1_DEFAULT << IPG_IFG_IPG1_SHIFT) & 2938 IPG_IFG_IPG1_MASK) | 2939 ((IPG_IFG_IPG2_DEFAULT << IPG_IFG_IPG2_SHIFT) & 2940 IPG_IFG_IPG2_MASK)); 2941 /* Set parameters for half-duplex media. */ 2942 CSR_WRITE_4(sc, ALC_HDPX_CFG, 2943 ((HDPX_CFG_LCOL_DEFAULT << HDPX_CFG_LCOL_SHIFT) & 2944 HDPX_CFG_LCOL_MASK) | 2945 ((HDPX_CFG_RETRY_DEFAULT << HDPX_CFG_RETRY_SHIFT) & 2946 HDPX_CFG_RETRY_MASK) | HDPX_CFG_EXC_DEF_EN | 2947 ((HDPX_CFG_ABEBT_DEFAULT << HDPX_CFG_ABEBT_SHIFT) & 2948 HDPX_CFG_ABEBT_MASK) | 2949 ((HDPX_CFG_JAMIPG_DEFAULT << HDPX_CFG_JAMIPG_SHIFT) & 2950 HDPX_CFG_JAMIPG_MASK)); 2951 } 2952 2953 /* 2954 * Set TSO/checksum offload threshold. For frames that is 2955 * larger than this threshold, hardware wouldn't do 2956 * TSO/checksum offloading. 2957 */ 2958 reg = (sc->alc_ident->max_framelen >> TSO_OFFLOAD_THRESH_UNIT_SHIFT) & 2959 TSO_OFFLOAD_THRESH_MASK; 2960 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 2961 reg |= TSO_OFFLOAD_ERRLGPKT_DROP_ENB; 2962 CSR_WRITE_4(sc, ALC_TSO_OFFLOAD_THRESH, reg); 2963 /* Configure TxQ. */ 2964 reg = (alc_dma_burst[sc->alc_dma_rd_burst] << 2965 TXQ_CFG_TX_FIFO_BURST_SHIFT) & TXQ_CFG_TX_FIFO_BURST_MASK; 2966 if (sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8152_B || 2967 sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8152_B2) 2968 reg >>= 1; 2969 reg |= (TXQ_CFG_TD_BURST_DEFAULT << TXQ_CFG_TD_BURST_SHIFT) & 2970 TXQ_CFG_TD_BURST_MASK; 2971 reg |= TXQ_CFG_IP_OPTION_ENB | TXQ_CFG_8023_ENB; 2972 CSR_WRITE_4(sc, ALC_TXQ_CFG, reg | TXQ_CFG_ENHANCED_MODE); 2973 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 2974 reg = (TXQ_CFG_TD_BURST_DEFAULT << HQTD_CFG_Q1_BURST_SHIFT | 2975 TXQ_CFG_TD_BURST_DEFAULT << HQTD_CFG_Q2_BURST_SHIFT | 2976 TXQ_CFG_TD_BURST_DEFAULT << HQTD_CFG_Q3_BURST_SHIFT | 2977 HQTD_CFG_BURST_ENB); 2978 CSR_WRITE_4(sc, ALC_HQTD_CFG, reg); 2979 reg = WRR_PRI_RESTRICT_NONE; 2980 reg |= (WRR_PRI_DEFAULT << WRR_PRI0_SHIFT | 2981 WRR_PRI_DEFAULT << WRR_PRI1_SHIFT | 2982 WRR_PRI_DEFAULT << WRR_PRI2_SHIFT | 2983 WRR_PRI_DEFAULT << WRR_PRI3_SHIFT); 2984 CSR_WRITE_4(sc, ALC_WRR, reg); 2985 } else { 2986 /* Configure Rx free descriptor pre-fetching. */ 2987 CSR_WRITE_4(sc, ALC_RX_RD_FREE_THRESH, 2988 ((RX_RD_FREE_THRESH_HI_DEFAULT << 2989 RX_RD_FREE_THRESH_HI_SHIFT) & RX_RD_FREE_THRESH_HI_MASK) | 2990 ((RX_RD_FREE_THRESH_LO_DEFAULT << 2991 RX_RD_FREE_THRESH_LO_SHIFT) & RX_RD_FREE_THRESH_LO_MASK)); 2992 } 2993 2994 /* 2995 * Configure flow control parameters. 2996 * XON : 80% of Rx FIFO 2997 * XOFF : 30% of Rx FIFO 2998 */ 2999 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 3000 reg = CSR_READ_4(sc, ALC_SRAM_RX_FIFO_LEN); 3001 reg &= SRAM_RX_FIFO_LEN_MASK; 3002 reg *= 8; 3003 if (reg > 8 * 1024) 3004 reg -= RX_FIFO_PAUSE_816X_RSVD; 3005 else 3006 reg -= RX_BUF_SIZE_MAX; 3007 reg /= 8; 3008 CSR_WRITE_4(sc, ALC_RX_FIFO_PAUSE_THRESH, 3009 ((reg << RX_FIFO_PAUSE_THRESH_LO_SHIFT) & 3010 RX_FIFO_PAUSE_THRESH_LO_MASK) | 3011 (((RX_FIFO_PAUSE_816X_RSVD / 8) << 3012 RX_FIFO_PAUSE_THRESH_HI_SHIFT) & 3013 RX_FIFO_PAUSE_THRESH_HI_MASK)); 3014 } else if (sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8131 || 3015 sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8132) { 3016 reg = CSR_READ_4(sc, ALC_SRAM_RX_FIFO_LEN); 3017 rxf_hi = (reg * 8) / 10; 3018 rxf_lo = (reg * 3) / 10; 3019 CSR_WRITE_4(sc, ALC_RX_FIFO_PAUSE_THRESH, 3020 ((rxf_lo << RX_FIFO_PAUSE_THRESH_LO_SHIFT) & 3021 RX_FIFO_PAUSE_THRESH_LO_MASK) | 3022 ((rxf_hi << RX_FIFO_PAUSE_THRESH_HI_SHIFT) & 3023 RX_FIFO_PAUSE_THRESH_HI_MASK)); 3024 } 3025 3026 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 3027 /* Disable RSS until I understand L1C/L2C's RSS logic. */ 3028 CSR_WRITE_4(sc, ALC_RSS_IDT_TABLE0, 0); 3029 CSR_WRITE_4(sc, ALC_RSS_CPU, 0); 3030 } 3031 3032 /* Configure RxQ. */ 3033 reg = (RXQ_CFG_RD_BURST_DEFAULT << RXQ_CFG_RD_BURST_SHIFT) & 3034 RXQ_CFG_RD_BURST_MASK; 3035 reg |= RXQ_CFG_RSS_MODE_DIS; 3036 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 3037 reg |= (RXQ_CFG_816X_IDT_TBL_SIZE_DEFAULT << 3038 RXQ_CFG_816X_IDT_TBL_SIZE_SHIFT) & 3039 RXQ_CFG_816X_IDT_TBL_SIZE_MASK; 3040 if ((sc->alc_flags & ALC_FLAG_FASTETHER) == 0 && 3041 sc->alc_ident->deviceid != PCI_PRODUCT_ATTANSIC_AR8151_V2) 3042 reg |= RXQ_CFG_ASPM_THROUGHPUT_LIMIT_1M; 3043 CSR_WRITE_4(sc, ALC_RXQ_CFG, reg); 3044 3045 /* Configure DMA parameters. */ 3046 reg = DMA_CFG_OUT_ORDER | DMA_CFG_RD_REQ_PRI; 3047 reg |= sc->alc_rcb; 3048 if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0) 3049 reg |= DMA_CFG_CMB_ENB; 3050 if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0) 3051 reg |= DMA_CFG_SMB_ENB; 3052 else 3053 reg |= DMA_CFG_SMB_DIS; 3054 reg |= (sc->alc_dma_rd_burst & DMA_CFG_RD_BURST_MASK) << 3055 DMA_CFG_RD_BURST_SHIFT; 3056 reg |= (sc->alc_dma_wr_burst & DMA_CFG_WR_BURST_MASK) << 3057 DMA_CFG_WR_BURST_SHIFT; 3058 reg |= (DMA_CFG_RD_DELAY_CNT_DEFAULT << DMA_CFG_RD_DELAY_CNT_SHIFT) & 3059 DMA_CFG_RD_DELAY_CNT_MASK; 3060 reg |= (DMA_CFG_WR_DELAY_CNT_DEFAULT << DMA_CFG_WR_DELAY_CNT_SHIFT) & 3061 DMA_CFG_WR_DELAY_CNT_MASK; 3062 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 3063 switch (AR816X_REV(sc->alc_rev)) { 3064 case AR816X_REV_A0: 3065 case AR816X_REV_A1: 3066 reg |= DMA_CFG_RD_CHNL_SEL_1; 3067 break; 3068 case AR816X_REV_B0: 3069 /* FALLTHROUGH */ 3070 default: 3071 reg |= DMA_CFG_RD_CHNL_SEL_3; 3072 break; 3073 } 3074 } 3075 CSR_WRITE_4(sc, ALC_DMA_CFG, reg); 3076 3077 /* 3078 * Configure Tx/Rx MACs. 3079 * - Auto-padding for short frames. 3080 * - Enable CRC generation. 3081 * Actual reconfiguration of MAC for resolved speed/duplex 3082 * is followed after detection of link establishment. 3083 * AR813x/AR815x always does checksum computation regardless 3084 * of MAC_CFG_RXCSUM_ENB bit. Also the controller is known to 3085 * have bug in protocol field in Rx return structure so 3086 * these controllers can't handle fragmented frames. Disable 3087 * Rx checksum offloading until there is a newer controller 3088 * that has sane implementation. 3089 */ 3090 reg = MAC_CFG_TX_CRC_ENB | MAC_CFG_TX_AUTO_PAD | MAC_CFG_FULL_DUPLEX | 3091 ((MAC_CFG_PREAMBLE_DEFAULT << MAC_CFG_PREAMBLE_SHIFT) & 3092 MAC_CFG_PREAMBLE_MASK); 3093 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0 || 3094 sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8151 || 3095 sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8151_V2 || 3096 sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8152_B2) 3097 reg |= MAC_CFG_HASH_ALG_CRC32 | MAC_CFG_SPEED_MODE_SW; 3098 if ((sc->alc_flags & ALC_FLAG_FASTETHER) != 0) 3099 reg |= MAC_CFG_SPEED_10_100; 3100 else 3101 reg |= MAC_CFG_SPEED_1000; 3102 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 3103 3104 /* Set up the receive filter. */ 3105 alc_iff(sc); 3106 alc_rxvlan(sc); 3107 3108 /* Acknowledge all pending interrupts and clear it. */ 3109 CSR_WRITE_4(sc, ALC_INTR_MASK, ALC_INTRS); 3110 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0xFFFFFFFF); 3111 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0); 3112 3113 sc->alc_flags &= ~ALC_FLAG_LINK; 3114 /* Switch to the current media. */ 3115 mii = &sc->sc_miibus; 3116 mii_mediachg(mii); 3117 3118 callout_schedule(&sc->sc_tick_ch, hz); 3119 3120 ifp->if_flags |= IFF_RUNNING; 3121 ifp->if_flags &= ~IFF_OACTIVE; 3122 3123 return (0); 3124 } 3125 3126 static void 3127 alc_stop(struct ifnet *ifp, int disable) 3128 { 3129 struct alc_softc *sc = ifp->if_softc; 3130 struct alc_txdesc *txd; 3131 struct alc_rxdesc *rxd; 3132 uint32_t reg; 3133 int i; 3134 3135 callout_stop(&sc->sc_tick_ch); 3136 3137 /* 3138 * Mark the interface down and cancel the watchdog timer. 3139 */ 3140 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 3141 ifp->if_timer = 0; 3142 3143 sc->alc_flags &= ~ALC_FLAG_LINK; 3144 3145 alc_stats_update(sc); 3146 3147 mii_down(&sc->sc_miibus); 3148 3149 /* Disable interrupts. */ 3150 CSR_WRITE_4(sc, ALC_INTR_MASK, 0); 3151 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0xFFFFFFFF); 3152 3153 /* Disable DMA. */ 3154 reg = CSR_READ_4(sc, ALC_DMA_CFG); 3155 reg &= ~(DMA_CFG_CMB_ENB | DMA_CFG_SMB_ENB); 3156 reg |= DMA_CFG_SMB_DIS; 3157 CSR_WRITE_4(sc, ALC_DMA_CFG, reg); 3158 DELAY(1000); 3159 3160 /* Stop Rx/Tx MACs. */ 3161 alc_stop_mac(sc); 3162 3163 /* Disable interrupts which might be touched in taskq handler. */ 3164 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0xFFFFFFFF); 3165 3166 /* Disable L0s/L1s */ 3167 alc_aspm(sc, 0, IFM_UNKNOWN); 3168 3169 /* Reclaim Rx buffers that have been processed. */ 3170 if (sc->alc_cdata.alc_rxhead != NULL) 3171 m_freem(sc->alc_cdata.alc_rxhead); 3172 ALC_RXCHAIN_RESET(sc); 3173 /* 3174 * Free Tx/Rx mbufs still in the queues. 3175 */ 3176 for (i = 0; i < ALC_RX_RING_CNT; i++) { 3177 rxd = &sc->alc_cdata.alc_rxdesc[i]; 3178 if (rxd->rx_m != NULL) { 3179 bus_dmamap_sync(sc->sc_dmat, rxd->rx_dmamap, 0, 3180 rxd->rx_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 3181 bus_dmamap_unload(sc->sc_dmat, rxd->rx_dmamap); 3182 m_freem(rxd->rx_m); 3183 rxd->rx_m = NULL; 3184 } 3185 } 3186 for (i = 0; i < ALC_TX_RING_CNT; i++) { 3187 txd = &sc->alc_cdata.alc_txdesc[i]; 3188 if (txd->tx_m != NULL) { 3189 bus_dmamap_sync(sc->sc_dmat, txd->tx_dmamap, 0, 3190 txd->tx_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 3191 bus_dmamap_unload(sc->sc_dmat, txd->tx_dmamap); 3192 m_freem(txd->tx_m); 3193 txd->tx_m = NULL; 3194 } 3195 } 3196 } 3197 3198 static void 3199 alc_stop_mac(struct alc_softc *sc) 3200 { 3201 uint32_t reg; 3202 int i; 3203 3204 alc_stop_queue(sc); 3205 /* Disable Rx/Tx MAC. */ 3206 reg = CSR_READ_4(sc, ALC_MAC_CFG); 3207 if ((reg & (MAC_CFG_TX_ENB | MAC_CFG_RX_ENB)) != 0) { 3208 reg &= ~(MAC_CFG_TX_ENB | MAC_CFG_RX_ENB); 3209 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 3210 } 3211 for (i = ALC_TIMEOUT; i > 0; i--) { 3212 reg = CSR_READ_4(sc, ALC_IDLE_STATUS); 3213 if ((reg & (IDLE_STATUS_RXMAC | IDLE_STATUS_TXMAC)) == 0) 3214 break; 3215 DELAY(10); 3216 } 3217 if (i == 0) 3218 printf("%s: could not disable Rx/Tx MAC(0x%08x)!\n", 3219 device_xname(sc->sc_dev), reg); 3220 } 3221 3222 static void 3223 alc_start_queue(struct alc_softc *sc) 3224 { 3225 uint32_t qcfg[] = { 3226 0, 3227 RXQ_CFG_QUEUE0_ENB, 3228 RXQ_CFG_QUEUE0_ENB | RXQ_CFG_QUEUE1_ENB, 3229 RXQ_CFG_QUEUE0_ENB | RXQ_CFG_QUEUE1_ENB | RXQ_CFG_QUEUE2_ENB, 3230 RXQ_CFG_ENB 3231 }; 3232 uint32_t cfg; 3233 3234 /* Enable RxQ. */ 3235 cfg = CSR_READ_4(sc, ALC_RXQ_CFG); 3236 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 3237 cfg &= ~RXQ_CFG_ENB; 3238 cfg |= qcfg[1]; 3239 } else 3240 cfg |= RXQ_CFG_QUEUE0_ENB; 3241 CSR_WRITE_4(sc, ALC_RXQ_CFG, cfg); 3242 /* Enable TxQ. */ 3243 cfg = CSR_READ_4(sc, ALC_TXQ_CFG); 3244 cfg |= TXQ_CFG_ENB; 3245 CSR_WRITE_4(sc, ALC_TXQ_CFG, cfg); 3246 } 3247 3248 static void 3249 alc_stop_queue(struct alc_softc *sc) 3250 { 3251 uint32_t reg; 3252 int i; 3253 3254 /* Disable RxQ. */ 3255 reg = CSR_READ_4(sc, ALC_RXQ_CFG); 3256 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 3257 if ((reg & RXQ_CFG_ENB) != 0) { 3258 reg &= ~RXQ_CFG_ENB; 3259 CSR_WRITE_4(sc, ALC_RXQ_CFG, reg); 3260 } 3261 } else { 3262 if ((reg & RXQ_CFG_QUEUE0_ENB) != 0) { 3263 reg &= ~RXQ_CFG_QUEUE0_ENB; 3264 CSR_WRITE_4(sc, ALC_RXQ_CFG, reg); 3265 } 3266 } 3267 /* Disable TxQ. */ 3268 reg = CSR_READ_4(sc, ALC_TXQ_CFG); 3269 if ((reg & TXQ_CFG_ENB) != 0) { 3270 reg &= ~TXQ_CFG_ENB; 3271 CSR_WRITE_4(sc, ALC_TXQ_CFG, reg); 3272 } 3273 DELAY(40); 3274 for (i = ALC_TIMEOUT; i > 0; i--) { 3275 reg = CSR_READ_4(sc, ALC_IDLE_STATUS); 3276 if ((reg & (IDLE_STATUS_RXQ | IDLE_STATUS_TXQ)) == 0) 3277 break; 3278 DELAY(10); 3279 } 3280 if (i == 0) 3281 printf("%s: could not disable RxQ/TxQ (0x%08x)!\n", 3282 device_xname(sc->sc_dev), reg); 3283 } 3284 3285 static void 3286 alc_init_tx_ring(struct alc_softc *sc) 3287 { 3288 struct alc_ring_data *rd; 3289 struct alc_txdesc *txd; 3290 int i; 3291 3292 sc->alc_cdata.alc_tx_prod = 0; 3293 sc->alc_cdata.alc_tx_cons = 0; 3294 sc->alc_cdata.alc_tx_cnt = 0; 3295 3296 rd = &sc->alc_rdata; 3297 memset(rd->alc_tx_ring, 0, ALC_TX_RING_SZ); 3298 for (i = 0; i < ALC_TX_RING_CNT; i++) { 3299 txd = &sc->alc_cdata.alc_txdesc[i]; 3300 txd->tx_m = NULL; 3301 } 3302 3303 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_tx_ring_map, 0, 3304 sc->alc_cdata.alc_tx_ring_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 3305 } 3306 3307 static int 3308 alc_init_rx_ring(struct alc_softc *sc, bool init) 3309 { 3310 struct alc_ring_data *rd; 3311 struct alc_rxdesc *rxd; 3312 int i; 3313 3314 sc->alc_cdata.alc_rx_cons = ALC_RX_RING_CNT - 1; 3315 rd = &sc->alc_rdata; 3316 memset(rd->alc_rx_ring, 0, ALC_RX_RING_SZ); 3317 for (i = 0; i < ALC_RX_RING_CNT; i++) { 3318 rxd = &sc->alc_cdata.alc_rxdesc[i]; 3319 rxd->rx_m = NULL; 3320 rxd->rx_desc = &rd->alc_rx_ring[i]; 3321 if (alc_newbuf(sc, rxd, init) != 0) 3322 return (ENOBUFS); 3323 } 3324 3325 /* 3326 * Since controller does not update Rx descriptors, driver 3327 * does have to read Rx descriptors back so BUS_DMASYNC_PREWRITE 3328 * is enough to ensure coherence. 3329 */ 3330 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_rx_ring_map, 0, 3331 sc->alc_cdata.alc_rx_ring_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 3332 /* Let controller know availability of new Rx buffers. */ 3333 CSR_WRITE_4(sc, ALC_MBOX_RD0_PROD_IDX, sc->alc_cdata.alc_rx_cons); 3334 3335 return (0); 3336 } 3337 3338 static void 3339 alc_init_rr_ring(struct alc_softc *sc) 3340 { 3341 struct alc_ring_data *rd; 3342 3343 sc->alc_cdata.alc_rr_cons = 0; 3344 ALC_RXCHAIN_RESET(sc); 3345 3346 rd = &sc->alc_rdata; 3347 memset(rd->alc_rr_ring, 0, ALC_RR_RING_SZ); 3348 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_rr_ring_map, 0, 3349 sc->alc_cdata.alc_rr_ring_map->dm_mapsize, 3350 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3351 } 3352 3353 static void 3354 alc_init_cmb(struct alc_softc *sc) 3355 { 3356 struct alc_ring_data *rd; 3357 3358 rd = &sc->alc_rdata; 3359 memset(rd->alc_cmb, 0, ALC_CMB_SZ); 3360 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_cmb_map, 0, 3361 sc->alc_cdata.alc_cmb_map->dm_mapsize, 3362 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3363 } 3364 3365 static void 3366 alc_init_smb(struct alc_softc *sc) 3367 { 3368 struct alc_ring_data *rd; 3369 3370 rd = &sc->alc_rdata; 3371 memset(rd->alc_smb, 0, ALC_SMB_SZ); 3372 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_smb_map, 0, 3373 sc->alc_cdata.alc_smb_map->dm_mapsize, 3374 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3375 } 3376 3377 static void 3378 alc_rxvlan(struct alc_softc *sc) 3379 { 3380 uint32_t reg; 3381 3382 reg = CSR_READ_4(sc, ALC_MAC_CFG); 3383 if (sc->sc_ec.ec_capenable & ETHERCAP_VLAN_HWTAGGING) 3384 reg |= MAC_CFG_VLAN_TAG_STRIP; 3385 else 3386 reg &= ~MAC_CFG_VLAN_TAG_STRIP; 3387 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 3388 } 3389 3390 static void 3391 alc_iff(struct alc_softc *sc) 3392 { 3393 struct ethercom *ec = &sc->sc_ec; 3394 struct ifnet *ifp = &ec->ec_if; 3395 struct ether_multi *enm; 3396 struct ether_multistep step; 3397 uint32_t crc; 3398 uint32_t mchash[2]; 3399 uint32_t rxcfg; 3400 3401 rxcfg = CSR_READ_4(sc, ALC_MAC_CFG); 3402 rxcfg &= ~(MAC_CFG_ALLMULTI | MAC_CFG_BCAST | MAC_CFG_PROMISC); 3403 ifp->if_flags &= ~IFF_ALLMULTI; 3404 3405 /* 3406 * Always accept broadcast frames. 3407 */ 3408 rxcfg |= MAC_CFG_BCAST; 3409 3410 if (ifp->if_flags & IFF_PROMISC || ec->ec_multicnt > 0) { 3411 ifp->if_flags |= IFF_ALLMULTI; 3412 if (ifp->if_flags & IFF_PROMISC) 3413 rxcfg |= MAC_CFG_PROMISC; 3414 else 3415 rxcfg |= MAC_CFG_ALLMULTI; 3416 mchash[0] = mchash[1] = 0xFFFFFFFF; 3417 } else { 3418 /* Program new filter. */ 3419 memset(mchash, 0, sizeof(mchash)); 3420 3421 ETHER_FIRST_MULTI(step, ec, enm); 3422 while (enm != NULL) { 3423 crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 3424 mchash[crc >> 31] |= 1 << ((crc >> 26) & 0x1f); 3425 ETHER_NEXT_MULTI(step, enm); 3426 } 3427 } 3428 3429 CSR_WRITE_4(sc, ALC_MAR0, mchash[0]); 3430 CSR_WRITE_4(sc, ALC_MAR1, mchash[1]); 3431 CSR_WRITE_4(sc, ALC_MAC_CFG, rxcfg); 3432 } 3433 3434 MODULE(MODULE_CLASS_DRIVER, if_alc, "pci"); 3435 3436 #ifdef _MODULE 3437 #include "ioconf.c" 3438 #endif 3439 3440 static int 3441 if_alc_modcmd(modcmd_t cmd, void *opaque) 3442 { 3443 int error = 0; 3444 3445 switch (cmd) { 3446 case MODULE_CMD_INIT: 3447 #ifdef _MODULE 3448 error = config_init_component(cfdriver_ioconf_if_alc, 3449 cfattach_ioconf_if_alc, cfdata_ioconf_if_alc); 3450 #endif 3451 return error; 3452 case MODULE_CMD_FINI: 3453 #ifdef _MODULE 3454 error = config_fini_component(cfdriver_ioconf_if_alc, 3455 cfattach_ioconf_if_alc, cfdata_ioconf_if_alc); 3456 #endif 3457 return error; 3458 default: 3459 return ENOTTY; 3460 } 3461 } 3462
Indexes created Fri Sep 26 08:10:20 GMT 2025