if_alc.c revision 1.28
1 /* $NetBSD: if_alc.c,v 1.28 2018/06/26 06:48:01 msaitoh Exp $ */ 2 /* $OpenBSD: if_alc.c,v 1.1 2009/08/08 09:31:13 kevlo Exp $ */ 3 /*- 4 * Copyright (c) 2009, Pyun YongHyeon <yongari (at) FreeBSD.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice unmodified, this list of conditions, and the following 12 * disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 /* Driver for Atheros AR813x/AR815x PCIe Ethernet. */ 31 32 #ifdef _KERNEL_OPT 33 #include "vlan.h" 34 #endif 35 36 #include <sys/param.h> 37 #include <sys/proc.h> 38 #include <sys/endian.h> 39 #include <sys/systm.h> 40 #include <sys/types.h> 41 #include <sys/sockio.h> 42 #include <sys/mbuf.h> 43 #include <sys/queue.h> 44 #include <sys/kernel.h> 45 #include <sys/device.h> 46 #include <sys/callout.h> 47 #include <sys/socket.h> 48 #include <sys/module.h> 49 50 #include <sys/bus.h> 51 52 #include <net/bpf.h> 53 #include <net/if.h> 54 #include <net/if_dl.h> 55 #include <net/if_llc.h> 56 #include <net/if_media.h> 57 #include <net/if_ether.h> 58 59 #ifdef INET 60 #include <netinet/in.h> 61 #include <netinet/in_systm.h> 62 #include <netinet/in_var.h> 63 #include <netinet/ip.h> 64 #endif 65 66 #include <net/if_types.h> 67 #include <net/if_vlanvar.h> 68 69 #include <dev/mii/mii.h> 70 #include <dev/mii/miivar.h> 71 72 #include <dev/pci/pcireg.h> 73 #include <dev/pci/pcivar.h> 74 #include <dev/pci/pcidevs.h> 75 76 #include <dev/pci/if_alcreg.h> 77 78 /* 79 * Devices supported by this driver. 80 */ 81 static struct alc_ident alc_ident_table[] = { 82 { PCI_VENDOR_ATTANSIC, PCI_PRODUCT_ATTANSIC_AR8131, 9 * 1024, 83 "Atheros AR8131 PCIe Gigabit Ethernet" }, 84 { PCI_VENDOR_ATTANSIC, PCI_PRODUCT_ATTANSIC_AR8132, 9 * 1024, 85 "Atheros AR8132 PCIe Fast Ethernet" }, 86 { PCI_VENDOR_ATTANSIC, PCI_PRODUCT_ATTANSIC_AR8151, 6 * 1024, 87 "Atheros AR8151 v1.0 PCIe Gigabit Ethernet" }, 88 { PCI_VENDOR_ATTANSIC, PCI_PRODUCT_ATTANSIC_AR8151_V2, 6 * 1024, 89 "Atheros AR8151 v2.0 PCIe Gigabit Ethernet" }, 90 { PCI_VENDOR_ATTANSIC, PCI_PRODUCT_ATTANSIC_AR8152_B, 6 * 1024, 91 "Atheros AR8152 v1.1 PCIe Fast Ethernet" }, 92 { PCI_VENDOR_ATTANSIC, PCI_PRODUCT_ATTANSIC_AR8152_B2, 6 * 1024, 93 "Atheros AR8152 v2.0 PCIe Fast Ethernet" }, 94 { PCI_VENDOR_ATTANSIC, PCI_PRODUCT_ATTANSIC_AR8161, 9 * 1024, 95 "Atheros AR8161 PCIe Gigabit Ethernet" }, 96 { PCI_VENDOR_ATTANSIC, PCI_PRODUCT_ATTANSIC_AR8162, 9 * 1024, 97 "Atheros AR8162 PCIe Fast Ethernet" }, 98 { PCI_VENDOR_ATTANSIC, PCI_PRODUCT_ATTANSIC_AR8171, 9 * 1024, 99 "Atheros AR8171 PCIe Gigabit Ethernet" }, 100 { PCI_VENDOR_ATTANSIC, PCI_PRODUCT_ATTANSIC_AR8172, 9 * 1024, 101 "Atheros AR8172 PCIe Fast Ethernet" }, 102 { PCI_VENDOR_ATTANSIC, PCI_PRODUCT_ATTANSIC_E2200, 9 * 1024, 103 "Killer E2200 Gigabit Ethernet" }, 104 { 0, 0, 0, NULL }, 105 }; 106 107 static int alc_match(device_t, cfdata_t, void *); 108 static void alc_attach(device_t, device_t, void *); 109 static int alc_detach(device_t, int); 110 111 static int alc_init(struct ifnet *); 112 static int alc_init_backend(struct ifnet *, bool); 113 static void alc_start(struct ifnet *); 114 static int alc_ioctl(struct ifnet *, u_long, void *); 115 static void alc_watchdog(struct ifnet *); 116 static int alc_mediachange(struct ifnet *); 117 static void alc_mediastatus(struct ifnet *, struct ifmediareq *); 118 119 static void alc_aspm(struct alc_softc *, int, int); 120 static void alc_aspm_813x(struct alc_softc *, int); 121 static void alc_aspm_816x(struct alc_softc *, int); 122 static void alc_disable_l0s_l1(struct alc_softc *); 123 static int alc_dma_alloc(struct alc_softc *); 124 static void alc_dma_free(struct alc_softc *); 125 static void alc_dsp_fixup(struct alc_softc *, int); 126 static int alc_encap(struct alc_softc *, struct mbuf **); 127 static struct alc_ident * 128 alc_find_ident(struct pci_attach_args *); 129 static void alc_get_macaddr(struct alc_softc *); 130 static void alc_get_macaddr_813x(struct alc_softc *); 131 static void alc_get_macaddr_816x(struct alc_softc *); 132 static void alc_get_macaddr_par(struct alc_softc *); 133 static void alc_init_cmb(struct alc_softc *); 134 static void alc_init_rr_ring(struct alc_softc *); 135 static int alc_init_rx_ring(struct alc_softc *, bool); 136 static void alc_init_smb(struct alc_softc *); 137 static void alc_init_tx_ring(struct alc_softc *); 138 static int alc_intr(void *); 139 static void alc_mac_config(struct alc_softc *); 140 static uint32_t alc_mii_readreg_813x(struct alc_softc *, int, int); 141 static uint32_t alc_mii_readreg_816x(struct alc_softc *, int, int); 142 static void alc_mii_writereg_813x(struct alc_softc *, int, int, int); 143 static void alc_mii_writereg_816x(struct alc_softc *, int, int, int); 144 static int alc_miibus_readreg(device_t, int, int); 145 static void alc_miibus_statchg(struct ifnet *); 146 static void alc_miibus_writereg(device_t, int, int, int); 147 static uint32_t alc_miidbg_readreg(struct alc_softc *, int); 148 static void alc_miidbg_writereg(struct alc_softc *, int, int); 149 static uint32_t alc_miiext_readreg(struct alc_softc *, int, int); 150 static uint32_t alc_miiext_writereg(struct alc_softc *, int, int, int); 151 static int alc_newbuf(struct alc_softc *, struct alc_rxdesc *, bool); 152 static void alc_phy_down(struct alc_softc *); 153 static void alc_phy_reset(struct alc_softc *); 154 static void alc_phy_reset_813x(struct alc_softc *); 155 static void alc_phy_reset_816x(struct alc_softc *); 156 static void alc_reset(struct alc_softc *); 157 static void alc_rxeof(struct alc_softc *, struct rx_rdesc *); 158 static int alc_rxintr(struct alc_softc *); 159 static void alc_iff(struct alc_softc *); 160 static void alc_rxvlan(struct alc_softc *); 161 static void alc_start_queue(struct alc_softc *); 162 static void alc_stats_clear(struct alc_softc *); 163 static void alc_stats_update(struct alc_softc *); 164 static void alc_stop(struct ifnet *, int); 165 static void alc_stop_mac(struct alc_softc *); 166 static void alc_stop_queue(struct alc_softc *); 167 static void alc_tick(void *); 168 static void alc_txeof(struct alc_softc *); 169 170 uint32_t alc_dma_burst[] = { 128, 256, 512, 1024, 2048, 4096, 0 }; 171 172 CFATTACH_DECL_NEW(alc, sizeof(struct alc_softc), 173 alc_match, alc_attach, alc_detach, NULL); 174 175 int alcdebug = 0; 176 #define DPRINTF(x) do { if (alcdebug) printf x; } while (0) 177 178 #define ETHER_ALIGN 2 179 #define ALC_CSUM_FEATURES (M_CSUM_TCPv4 | M_CSUM_UDPv4) 180 181 static int 182 alc_miibus_readreg(device_t dev, int phy, int reg) 183 { 184 struct alc_softc *sc = device_private(dev); 185 int v; 186 187 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 188 v = alc_mii_readreg_816x(sc, phy, reg); 189 else 190 v = alc_mii_readreg_813x(sc, phy, reg); 191 return (v); 192 } 193 194 static uint32_t 195 alc_mii_readreg_813x(struct alc_softc *sc, int phy, int reg) 196 { 197 uint32_t v; 198 int i; 199 200 if (phy != sc->alc_phyaddr) 201 return (0); 202 203 /* 204 * For AR8132 fast ethernet controller, do not report 1000baseT 205 * capability to mii(4). Even though AR8132 uses the same 206 * model/revision number of F1 gigabit PHY, the PHY has no 207 * ability to establish 1000baseT link. 208 */ 209 if ((sc->alc_flags & ALC_FLAG_FASTETHER) != 0 && 210 reg == MII_EXTSR) 211 return 0; 212 213 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ | 214 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); 215 for (i = ALC_PHY_TIMEOUT; i > 0; i--) { 216 DELAY(5); 217 v = CSR_READ_4(sc, ALC_MDIO); 218 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) 219 break; 220 } 221 222 if (i == 0) { 223 printf("%s: phy read timeout: phy %d, reg %d\n", 224 device_xname(sc->sc_dev), phy, reg); 225 return (0); 226 } 227 228 return ((v & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT); 229 } 230 231 static uint32_t 232 alc_mii_readreg_816x(struct alc_softc *sc, int phy, int reg) 233 { 234 uint32_t clk, v; 235 int i; 236 237 if (phy != sc->alc_phyaddr) 238 return (0); 239 240 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) 241 clk = MDIO_CLK_25_128; 242 else 243 clk = MDIO_CLK_25_4; 244 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ | 245 MDIO_SUP_PREAMBLE | clk | MDIO_REG_ADDR(reg)); 246 for (i = ALC_PHY_TIMEOUT; i > 0; i--) { 247 DELAY(5); 248 v = CSR_READ_4(sc, ALC_MDIO); 249 if ((v & MDIO_OP_BUSY) == 0) 250 break; 251 } 252 253 if (i == 0) { 254 printf("%s: phy read timeout: phy %d, reg %d\n", 255 device_xname(sc->sc_dev), phy, reg); 256 return (0); 257 } 258 259 return ((v & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT); 260 } 261 262 static void 263 alc_miibus_writereg(device_t dev, int phy, int reg, int val) 264 { 265 struct alc_softc *sc = device_private(dev); 266 267 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 268 alc_mii_writereg_816x(sc, phy, reg, val); 269 else 270 alc_mii_writereg_813x(sc, phy, reg, val); 271 272 return; 273 } 274 275 static void 276 alc_mii_writereg_813x(struct alc_softc *sc, int phy, int reg, int val) 277 { 278 uint32_t v; 279 int i; 280 281 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE | 282 (val & MDIO_DATA_MASK) << MDIO_DATA_SHIFT | 283 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); 284 for (i = ALC_PHY_TIMEOUT; i > 0; i--) { 285 DELAY(5); 286 v = CSR_READ_4(sc, ALC_MDIO); 287 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) 288 break; 289 } 290 291 if (i == 0) 292 printf("%s: phy write timeout: phy %d, reg %d\n", 293 device_xname(sc->sc_dev), phy, reg); 294 295 return; 296 } 297 298 static void 299 alc_mii_writereg_816x(struct alc_softc *sc, int phy, int reg, int val) 300 { 301 uint32_t clk, v; 302 int i; 303 304 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) 305 clk = MDIO_CLK_25_128; 306 else 307 clk = MDIO_CLK_25_4; 308 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE | 309 ((val & MDIO_DATA_MASK) << MDIO_DATA_SHIFT) | MDIO_REG_ADDR(reg) | 310 MDIO_SUP_PREAMBLE | clk); 311 for (i = ALC_PHY_TIMEOUT; i > 0; i--) { 312 DELAY(5); 313 v = CSR_READ_4(sc, ALC_MDIO); 314 if ((v & MDIO_OP_BUSY) == 0) 315 break; 316 } 317 318 if (i == 0) 319 printf("%s: phy write timeout: phy %d, reg %d\n", 320 device_xname(sc->sc_dev), phy, reg); 321 322 return; 323 } 324 325 static void 326 alc_miibus_statchg(struct ifnet *ifp) 327 { 328 struct alc_softc *sc = ifp->if_softc; 329 struct mii_data *mii = &sc->sc_miibus; 330 uint32_t reg; 331 332 if ((ifp->if_flags & IFF_RUNNING) == 0) 333 return; 334 335 sc->alc_flags &= ~ALC_FLAG_LINK; 336 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 337 (IFM_ACTIVE | IFM_AVALID)) { 338 switch (IFM_SUBTYPE(mii->mii_media_active)) { 339 case IFM_10_T: 340 case IFM_100_TX: 341 sc->alc_flags |= ALC_FLAG_LINK; 342 break; 343 case IFM_1000_T: 344 if ((sc->alc_flags & ALC_FLAG_FASTETHER) == 0) 345 sc->alc_flags |= ALC_FLAG_LINK; 346 break; 347 default: 348 break; 349 } 350 } 351 /* Stop Rx/Tx MACs. */ 352 alc_stop_mac(sc); 353 354 /* Program MACs with resolved speed/duplex/flow-control. */ 355 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) { 356 alc_start_queue(sc); 357 alc_mac_config(sc); 358 /* Re-enable Tx/Rx MACs. */ 359 reg = CSR_READ_4(sc, ALC_MAC_CFG); 360 reg |= MAC_CFG_TX_ENB | MAC_CFG_RX_ENB; 361 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 362 } 363 alc_aspm(sc, 0, IFM_SUBTYPE(mii->mii_media_active)); 364 alc_dsp_fixup(sc, IFM_SUBTYPE(mii->mii_media_active)); 365 } 366 367 static uint32_t 368 alc_miidbg_readreg(struct alc_softc *sc, int reg) 369 { 370 371 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, ALC_MII_DBG_ADDR, 372 reg); 373 return (alc_miibus_readreg(sc->sc_dev, sc->alc_phyaddr, 374 ALC_MII_DBG_DATA)); 375 } 376 377 static void 378 alc_miidbg_writereg(struct alc_softc *sc, int reg, int val) 379 { 380 381 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, ALC_MII_DBG_ADDR, 382 reg); 383 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, ALC_MII_DBG_DATA, val); 384 385 return; 386 } 387 388 static uint32_t 389 alc_miiext_readreg(struct alc_softc *sc, int devaddr, int reg) 390 { 391 uint32_t clk, v; 392 int i; 393 394 CSR_WRITE_4(sc, ALC_EXT_MDIO, EXT_MDIO_REG(reg) | 395 EXT_MDIO_DEVADDR(devaddr)); 396 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) 397 clk = MDIO_CLK_25_128; 398 else 399 clk = MDIO_CLK_25_4; 400 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ | 401 MDIO_SUP_PREAMBLE | clk | MDIO_MODE_EXT); 402 for (i = ALC_PHY_TIMEOUT; i > 0; i--) { 403 DELAY(5); 404 v = CSR_READ_4(sc, ALC_MDIO); 405 if ((v & MDIO_OP_BUSY) == 0) 406 break; 407 } 408 409 if (i == 0) { 410 printf("%s: phy ext read timeout: %d\n", 411 device_xname(sc->sc_dev), reg); 412 return (0); 413 } 414 415 return ((v & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT); 416 } 417 418 static uint32_t 419 alc_miiext_writereg(struct alc_softc *sc, int devaddr, int reg, int val) 420 { 421 uint32_t clk, v; 422 int i; 423 424 CSR_WRITE_4(sc, ALC_EXT_MDIO, EXT_MDIO_REG(reg) | 425 EXT_MDIO_DEVADDR(devaddr)); 426 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) 427 clk = MDIO_CLK_25_128; 428 else 429 clk = MDIO_CLK_25_4; 430 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE | 431 ((val & MDIO_DATA_MASK) << MDIO_DATA_SHIFT) | 432 MDIO_SUP_PREAMBLE | clk | MDIO_MODE_EXT); 433 for (i = ALC_PHY_TIMEOUT; i > 0; i--) { 434 DELAY(5); 435 v = CSR_READ_4(sc, ALC_MDIO); 436 if ((v & MDIO_OP_BUSY) == 0) 437 break; 438 } 439 440 if (i == 0) { 441 printf("%s: phy ext write timeout: reg %d\n", 442 device_xname(sc->sc_dev), reg); 443 return (0); 444 } 445 446 return (0); 447 } 448 449 static void 450 alc_dsp_fixup(struct alc_softc *sc, int media) 451 { 452 uint16_t agc, len, val; 453 454 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 455 return; 456 if (AR816X_REV(sc->alc_rev) >= AR816X_REV_C0) 457 return; 458 459 /* 460 * Vendor PHY magic. 461 * 1000BT/AZ, wrong cable length 462 */ 463 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) { 464 len = alc_miiext_readreg(sc, MII_EXT_PCS, MII_EXT_CLDCTL6); 465 len = (len >> EXT_CLDCTL6_CAB_LEN_SHIFT) & 466 EXT_CLDCTL6_CAB_LEN_MASK; 467 /* XXX: used to be (alc >> shift) & mask which is 0 */ 468 agc = alc_miidbg_readreg(sc, MII_DBG_AGC) & DBG_AGC_2_VGA_MASK; 469 agc >>= DBG_AGC_2_VGA_SHIFT; 470 if ((media == IFM_1000_T && len > EXT_CLDCTL6_CAB_LEN_SHORT1G && 471 agc > DBG_AGC_LONG1G_LIMT) || 472 (media == IFM_100_TX && len > DBG_AGC_LONG100M_LIMT && 473 agc > DBG_AGC_LONG1G_LIMT)) { 474 alc_miidbg_writereg(sc, MII_DBG_AZ_ANADECT, 475 DBG_AZ_ANADECT_LONG); 476 val = alc_miiext_readreg(sc, MII_EXT_ANEG, 477 MII_EXT_ANEG_AFE); 478 val |= ANEG_AFEE_10BT_100M_TH; 479 alc_miiext_writereg(sc, MII_EXT_ANEG, MII_EXT_ANEG_AFE, 480 val); 481 } else { 482 alc_miidbg_writereg(sc, MII_DBG_AZ_ANADECT, 483 DBG_AZ_ANADECT_DEFAULT); 484 val = alc_miiext_readreg(sc, MII_EXT_ANEG, 485 MII_EXT_ANEG_AFE); 486 val &= ~ANEG_AFEE_10BT_100M_TH; 487 alc_miiext_writereg(sc, MII_EXT_ANEG, MII_EXT_ANEG_AFE, 488 val); 489 } 490 if ((sc->alc_flags & ALC_FLAG_LINK_WAR) != 0 && 491 AR816X_REV(sc->alc_rev) == AR816X_REV_B0) { 492 if (media == IFM_1000_T) { 493 /* 494 * Giga link threshold, raise the tolerance of 495 * noise 50%. 496 */ 497 val = alc_miidbg_readreg(sc, MII_DBG_MSE20DB); 498 val &= ~DBG_MSE20DB_TH_MASK; 499 val |= (DBG_MSE20DB_TH_HI << 500 DBG_MSE20DB_TH_SHIFT); 501 alc_miidbg_writereg(sc, MII_DBG_MSE20DB, val); 502 } else if (media == IFM_100_TX) 503 alc_miidbg_writereg(sc, MII_DBG_MSE16DB, 504 DBG_MSE16DB_UP); 505 } 506 } else { 507 val = alc_miiext_readreg(sc, MII_EXT_ANEG, MII_EXT_ANEG_AFE); 508 val &= ~ANEG_AFEE_10BT_100M_TH; 509 alc_miiext_writereg(sc, MII_EXT_ANEG, MII_EXT_ANEG_AFE, val); 510 if ((sc->alc_flags & ALC_FLAG_LINK_WAR) != 0 && 511 AR816X_REV(sc->alc_rev) == AR816X_REV_B0) { 512 alc_miidbg_writereg(sc, MII_DBG_MSE16DB, 513 DBG_MSE16DB_DOWN); 514 val = alc_miidbg_readreg(sc, MII_DBG_MSE20DB); 515 val &= ~DBG_MSE20DB_TH_MASK; 516 val |= (DBG_MSE20DB_TH_DEFAULT << DBG_MSE20DB_TH_SHIFT); 517 alc_miidbg_writereg(sc, MII_DBG_MSE20DB, val); 518 } 519 } 520 } 521 522 static void 523 alc_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 524 { 525 struct alc_softc *sc = ifp->if_softc; 526 struct mii_data *mii = &sc->sc_miibus; 527 528 if ((ifp->if_flags & IFF_UP) == 0) 529 return; 530 531 mii_pollstat(mii); 532 ifmr->ifm_status = mii->mii_media_status; 533 ifmr->ifm_active = mii->mii_media_active; 534 } 535 536 static int 537 alc_mediachange(struct ifnet *ifp) 538 { 539 struct alc_softc *sc = ifp->if_softc; 540 struct mii_data *mii = &sc->sc_miibus; 541 int error; 542 543 if (mii->mii_instance != 0) { 544 struct mii_softc *miisc; 545 546 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 547 mii_phy_reset(miisc); 548 } 549 error = mii_mediachg(mii); 550 551 return (error); 552 } 553 554 static struct alc_ident * 555 alc_find_ident(struct pci_attach_args *pa) 556 { 557 struct alc_ident *ident; 558 uint16_t vendor, devid; 559 560 vendor = PCI_VENDOR(pa->pa_id); 561 devid = PCI_PRODUCT(pa->pa_id); 562 for (ident = alc_ident_table; ident->name != NULL; ident++) { 563 if (vendor == ident->vendorid && devid == ident->deviceid) 564 return (ident); 565 } 566 567 return (NULL); 568 } 569 570 static int 571 alc_match(device_t dev, cfdata_t match, void *aux) 572 { 573 struct pci_attach_args *pa = aux; 574 575 return alc_find_ident(pa) != NULL; 576 } 577 578 static void 579 alc_get_macaddr(struct alc_softc *sc) 580 { 581 582 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 583 alc_get_macaddr_816x(sc); 584 else 585 alc_get_macaddr_813x(sc); 586 } 587 588 static void 589 alc_get_macaddr_813x(struct alc_softc *sc) 590 { 591 uint32_t opt; 592 uint16_t val; 593 int eeprom, i; 594 595 eeprom = 0; 596 opt = CSR_READ_4(sc, ALC_OPT_CFG); 597 if ((CSR_READ_4(sc, ALC_MASTER_CFG) & MASTER_OTP_SEL) != 0 && 598 (CSR_READ_4(sc, ALC_TWSI_DEBUG) & TWSI_DEBUG_DEV_EXIST) != 0) { 599 /* 600 * EEPROM found, let TWSI reload EEPROM configuration. 601 * This will set ethernet address of controller. 602 */ 603 eeprom++; 604 switch (sc->alc_ident->deviceid) { 605 case PCI_PRODUCT_ATTANSIC_AR8131: 606 case PCI_PRODUCT_ATTANSIC_AR8132: 607 if ((opt & OPT_CFG_CLK_ENB) == 0) { 608 opt |= OPT_CFG_CLK_ENB; 609 CSR_WRITE_4(sc, ALC_OPT_CFG, opt); 610 CSR_READ_4(sc, ALC_OPT_CFG); 611 DELAY(1000); 612 } 613 break; 614 case PCI_PRODUCT_ATTANSIC_AR8151: 615 case PCI_PRODUCT_ATTANSIC_AR8151_V2: 616 case PCI_PRODUCT_ATTANSIC_AR8152_B: 617 case PCI_PRODUCT_ATTANSIC_AR8152_B2: 618 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 619 ALC_MII_DBG_ADDR, 0x00); 620 val = alc_miibus_readreg(sc->sc_dev, sc->alc_phyaddr, 621 ALC_MII_DBG_DATA); 622 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 623 ALC_MII_DBG_DATA, val & 0xFF7F); 624 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 625 ALC_MII_DBG_ADDR, 0x3B); 626 val = alc_miibus_readreg(sc->sc_dev, sc->alc_phyaddr, 627 ALC_MII_DBG_DATA); 628 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 629 ALC_MII_DBG_DATA, val | 0x0008); 630 DELAY(20); 631 break; 632 } 633 634 CSR_WRITE_4(sc, ALC_LTSSM_ID_CFG, 635 CSR_READ_4(sc, ALC_LTSSM_ID_CFG) & ~LTSSM_ID_WRO_ENB); 636 CSR_WRITE_4(sc, ALC_WOL_CFG, 0); 637 CSR_READ_4(sc, ALC_WOL_CFG); 638 639 CSR_WRITE_4(sc, ALC_TWSI_CFG, CSR_READ_4(sc, ALC_TWSI_CFG) | 640 TWSI_CFG_SW_LD_START); 641 for (i = 100; i > 0; i--) { 642 DELAY(1000); 643 if ((CSR_READ_4(sc, ALC_TWSI_CFG) & 644 TWSI_CFG_SW_LD_START) == 0) 645 break; 646 } 647 if (i == 0) 648 printf("%s: reloading EEPROM timeout!\n", 649 device_xname(sc->sc_dev)); 650 } else { 651 if (alcdebug) 652 printf("%s: EEPROM not found!\n", device_xname(sc->sc_dev)); 653 } 654 if (eeprom != 0) { 655 switch (sc->alc_ident->deviceid) { 656 case PCI_PRODUCT_ATTANSIC_AR8131: 657 case PCI_PRODUCT_ATTANSIC_AR8132: 658 if ((opt & OPT_CFG_CLK_ENB) != 0) { 659 opt &= ~OPT_CFG_CLK_ENB; 660 CSR_WRITE_4(sc, ALC_OPT_CFG, opt); 661 CSR_READ_4(sc, ALC_OPT_CFG); 662 DELAY(1000); 663 } 664 break; 665 case PCI_PRODUCT_ATTANSIC_AR8151: 666 case PCI_PRODUCT_ATTANSIC_AR8151_V2: 667 case PCI_PRODUCT_ATTANSIC_AR8152_B: 668 case PCI_PRODUCT_ATTANSIC_AR8152_B2: 669 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 670 ALC_MII_DBG_ADDR, 0x00); 671 val = alc_miibus_readreg(sc->sc_dev, sc->alc_phyaddr, 672 ALC_MII_DBG_DATA); 673 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 674 ALC_MII_DBG_DATA, val | 0x0080); 675 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 676 ALC_MII_DBG_ADDR, 0x3B); 677 val = alc_miibus_readreg(sc->sc_dev, sc->alc_phyaddr, 678 ALC_MII_DBG_DATA); 679 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 680 ALC_MII_DBG_DATA, val & 0xFFF7); 681 DELAY(20); 682 break; 683 } 684 } 685 686 alc_get_macaddr_par(sc); 687 } 688 689 static void 690 alc_get_macaddr_816x(struct alc_softc *sc) 691 { 692 uint32_t reg; 693 int i, reloaded; 694 695 reloaded = 0; 696 /* Try to reload station address via TWSI. */ 697 for (i = 100; i > 0; i--) { 698 reg = CSR_READ_4(sc, ALC_SLD); 699 if ((reg & (SLD_PROGRESS | SLD_START)) == 0) 700 break; 701 DELAY(1000); 702 } 703 if (i != 0) { 704 CSR_WRITE_4(sc, ALC_SLD, reg | SLD_START); 705 for (i = 100; i > 0; i--) { 706 DELAY(1000); 707 reg = CSR_READ_4(sc, ALC_SLD); 708 if ((reg & SLD_START) == 0) 709 break; 710 } 711 if (i != 0) 712 reloaded++; 713 else if (alcdebug) 714 printf("%s: reloading station address via TWSI timed out!\n", 715 device_xname(sc->sc_dev)); 716 } 717 718 /* Try to reload station address from EEPROM or FLASH. */ 719 if (reloaded == 0) { 720 reg = CSR_READ_4(sc, ALC_EEPROM_LD); 721 if ((reg & (EEPROM_LD_EEPROM_EXIST | 722 EEPROM_LD_FLASH_EXIST)) != 0) { 723 for (i = 100; i > 0; i--) { 724 reg = CSR_READ_4(sc, ALC_EEPROM_LD); 725 if ((reg & (EEPROM_LD_PROGRESS | 726 EEPROM_LD_START)) == 0) 727 break; 728 DELAY(1000); 729 } 730 if (i != 0) { 731 CSR_WRITE_4(sc, ALC_EEPROM_LD, reg | 732 EEPROM_LD_START); 733 for (i = 100; i > 0; i--) { 734 DELAY(1000); 735 reg = CSR_READ_4(sc, ALC_EEPROM_LD); 736 if ((reg & EEPROM_LD_START) == 0) 737 break; 738 } 739 } else if (alcdebug) 740 printf("%s: reloading EEPROM/FLASH timed out!\n", 741 device_xname(sc->sc_dev)); 742 } 743 } 744 745 alc_get_macaddr_par(sc); 746 } 747 748 749 static void 750 alc_get_macaddr_par(struct alc_softc *sc) 751 { 752 uint32_t ea[2]; 753 754 ea[0] = CSR_READ_4(sc, ALC_PAR0); 755 ea[1] = CSR_READ_4(sc, ALC_PAR1); 756 sc->alc_eaddr[0] = (ea[1] >> 8) & 0xFF; 757 sc->alc_eaddr[1] = (ea[1] >> 0) & 0xFF; 758 sc->alc_eaddr[2] = (ea[0] >> 24) & 0xFF; 759 sc->alc_eaddr[3] = (ea[0] >> 16) & 0xFF; 760 sc->alc_eaddr[4] = (ea[0] >> 8) & 0xFF; 761 sc->alc_eaddr[5] = (ea[0] >> 0) & 0xFF; 762 } 763 764 static void 765 alc_disable_l0s_l1(struct alc_softc *sc) 766 { 767 uint32_t pmcfg; 768 769 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 770 /* Another magic from vendor. */ 771 pmcfg = CSR_READ_4(sc, ALC_PM_CFG); 772 pmcfg &= ~(PM_CFG_L1_ENTRY_TIMER_MASK | PM_CFG_CLK_SWH_L1 | 773 PM_CFG_ASPM_L0S_ENB | PM_CFG_ASPM_L1_ENB | 774 PM_CFG_MAC_ASPM_CHK | PM_CFG_SERDES_PD_EX_L1); 775 pmcfg |= PM_CFG_SERDES_BUDS_RX_L1_ENB | 776 PM_CFG_SERDES_PLL_L1_ENB | PM_CFG_SERDES_L1_ENB; 777 CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg); 778 } 779 } 780 781 static void 782 alc_phy_reset(struct alc_softc *sc) 783 { 784 785 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 786 alc_phy_reset_816x(sc); 787 else 788 alc_phy_reset_813x(sc); 789 } 790 791 static void 792 alc_phy_reset_813x(struct alc_softc *sc) 793 { 794 uint16_t data; 795 796 /* Reset magic from Linux. */ 797 CSR_WRITE_2(sc, ALC_GPHY_CFG, GPHY_CFG_SEL_ANA_RESET); 798 CSR_READ_2(sc, ALC_GPHY_CFG); 799 DELAY(10 * 1000); 800 801 CSR_WRITE_2(sc, ALC_GPHY_CFG, GPHY_CFG_EXT_RESET | 802 GPHY_CFG_SEL_ANA_RESET); 803 CSR_READ_2(sc, ALC_GPHY_CFG); 804 DELAY(10 * 1000); 805 806 /* DSP fixup, Vendor magic. */ 807 if (sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8152_B) { 808 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 809 ALC_MII_DBG_ADDR, 0x000A); 810 data = alc_miibus_readreg(sc->sc_dev, sc->alc_phyaddr, 811 ALC_MII_DBG_DATA); 812 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 813 ALC_MII_DBG_DATA, data & 0xDFFF); 814 } 815 if (sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8151 || 816 sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8151_V2 || 817 sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8152_B || 818 sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8152_B2) { 819 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 820 ALC_MII_DBG_ADDR, 0x003B); 821 data = alc_miibus_readreg(sc->sc_dev, sc->alc_phyaddr, 822 ALC_MII_DBG_DATA); 823 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 824 ALC_MII_DBG_DATA, data & 0xFFF7); 825 DELAY(20 * 1000); 826 } 827 if (sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8151) { 828 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 829 ALC_MII_DBG_ADDR, 0x0029); 830 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 831 ALC_MII_DBG_DATA, 0x929D); 832 } 833 if (sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8131 || 834 sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8132 || 835 sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8151_V2 || 836 sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8152_B2) { 837 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 838 ALC_MII_DBG_ADDR, 0x0029); 839 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 840 ALC_MII_DBG_DATA, 0xB6DD); 841 } 842 843 /* Load DSP codes, vendor magic. */ 844 data = ANA_LOOP_SEL_10BT | ANA_EN_MASK_TB | ANA_EN_10BT_IDLE | 845 ((1 << ANA_INTERVAL_SEL_TIMER_SHIFT) & ANA_INTERVAL_SEL_TIMER_MASK); 846 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 847 ALC_MII_DBG_ADDR, MII_ANA_CFG18); 848 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 849 ALC_MII_DBG_DATA, data); 850 851 data = ((2 << ANA_SERDES_CDR_BW_SHIFT) & ANA_SERDES_CDR_BW_MASK) | 852 ANA_SERDES_EN_DEEM | ANA_SERDES_SEL_HSP | ANA_SERDES_EN_PLL | 853 ANA_SERDES_EN_LCKDT; 854 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 855 ALC_MII_DBG_ADDR, MII_ANA_CFG5); 856 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 857 ALC_MII_DBG_DATA, data); 858 859 data = ((44 << ANA_LONG_CABLE_TH_100_SHIFT) & 860 ANA_LONG_CABLE_TH_100_MASK) | 861 ((33 << ANA_SHORT_CABLE_TH_100_SHIFT) & 862 ANA_SHORT_CABLE_TH_100_SHIFT) | 863 ANA_BP_BAD_LINK_ACCUM | ANA_BP_SMALL_BW; 864 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 865 ALC_MII_DBG_ADDR, MII_ANA_CFG54); 866 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 867 ALC_MII_DBG_DATA, data); 868 869 data = ((11 << ANA_IECHO_ADJ_3_SHIFT) & ANA_IECHO_ADJ_3_MASK) | 870 ((11 << ANA_IECHO_ADJ_2_SHIFT) & ANA_IECHO_ADJ_2_MASK) | 871 ((8 << ANA_IECHO_ADJ_1_SHIFT) & ANA_IECHO_ADJ_1_MASK) | 872 ((8 << ANA_IECHO_ADJ_0_SHIFT) & ANA_IECHO_ADJ_0_MASK); 873 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 874 ALC_MII_DBG_ADDR, MII_ANA_CFG4); 875 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 876 ALC_MII_DBG_DATA, data); 877 878 data = ((7 & ANA_MANUL_SWICH_ON_SHIFT) & ANA_MANUL_SWICH_ON_MASK) | 879 ANA_RESTART_CAL | ANA_MAN_ENABLE | ANA_SEL_HSP | ANA_EN_HB | 880 ANA_OEN_125M; 881 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 882 ALC_MII_DBG_ADDR, MII_ANA_CFG0); 883 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 884 ALC_MII_DBG_DATA, data); 885 DELAY(1000); 886 887 /* Disable hibernation. */ 888 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, ALC_MII_DBG_ADDR, 889 0x0029); 890 data = alc_miibus_readreg(sc->sc_dev, sc->alc_phyaddr, 891 ALC_MII_DBG_DATA); 892 data &= ~0x8000; 893 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, ALC_MII_DBG_DATA, 894 data); 895 896 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, ALC_MII_DBG_ADDR, 897 0x000B); 898 data = alc_miibus_readreg(sc->sc_dev, sc->alc_phyaddr, 899 ALC_MII_DBG_DATA); 900 data &= ~0x8000; 901 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, ALC_MII_DBG_DATA, 902 data); 903 } 904 905 static void 906 alc_phy_reset_816x(struct alc_softc *sc) 907 { 908 uint32_t val; 909 910 val = CSR_READ_4(sc, ALC_GPHY_CFG); 911 val &= ~(GPHY_CFG_EXT_RESET | GPHY_CFG_LED_MODE | 912 GPHY_CFG_GATE_25M_ENB | GPHY_CFG_PHY_IDDQ | GPHY_CFG_PHY_PLL_ON | 913 GPHY_CFG_PWDOWN_HW | GPHY_CFG_100AB_ENB); 914 val |= GPHY_CFG_SEL_ANA_RESET; 915 #ifdef notyet 916 val |= GPHY_CFG_HIB_PULSE | GPHY_CFG_HIB_EN | GPHY_CFG_SEL_ANA_RESET; 917 #else 918 /* Disable PHY hibernation. */ 919 val &= ~(GPHY_CFG_HIB_PULSE | GPHY_CFG_HIB_EN); 920 #endif 921 CSR_WRITE_4(sc, ALC_GPHY_CFG, val); 922 DELAY(10); 923 CSR_WRITE_4(sc, ALC_GPHY_CFG, val | GPHY_CFG_EXT_RESET); 924 DELAY(800); 925 926 /* Vendor PHY magic. */ 927 #ifdef notyet 928 alc_miidbg_writereg(sc, MII_DBG_LEGCYPS, DBG_LEGCYPS_DEFAULT); 929 alc_miidbg_writereg(sc, MII_DBG_SYSMODCTL, DBG_SYSMODCTL_DEFAULT); 930 alc_miiext_writereg(sc, MII_EXT_PCS, MII_EXT_VDRVBIAS, 931 EXT_VDRVBIAS_DEFAULT); 932 #else 933 /* Disable PHY hibernation. */ 934 alc_miidbg_writereg(sc, MII_DBG_LEGCYPS, 935 DBG_LEGCYPS_DEFAULT & ~DBG_LEGCYPS_ENB); 936 alc_miidbg_writereg(sc, MII_DBG_HIBNEG, 937 DBG_HIBNEG_DEFAULT & ~(DBG_HIBNEG_PSHIB_EN | DBG_HIBNEG_HIB_PULSE)); 938 alc_miidbg_writereg(sc, MII_DBG_GREENCFG, DBG_GREENCFG_DEFAULT); 939 #endif 940 941 /* XXX Disable EEE. */ 942 val = CSR_READ_4(sc, ALC_LPI_CTL); 943 val &= ~LPI_CTL_ENB; 944 CSR_WRITE_4(sc, ALC_LPI_CTL, val); 945 alc_miiext_writereg(sc, MII_EXT_ANEG, MII_EXT_ANEG_LOCAL_EEEADV, 0); 946 947 /* PHY power saving. */ 948 alc_miidbg_writereg(sc, MII_DBG_TST10BTCFG, DBG_TST10BTCFG_DEFAULT); 949 alc_miidbg_writereg(sc, MII_DBG_SRDSYSMOD, DBG_SRDSYSMOD_DEFAULT); 950 alc_miidbg_writereg(sc, MII_DBG_TST100BTCFG, DBG_TST100BTCFG_DEFAULT); 951 alc_miidbg_writereg(sc, MII_DBG_ANACTL, DBG_ANACTL_DEFAULT); 952 val = alc_miidbg_readreg(sc, MII_DBG_GREENCFG2); 953 val &= ~DBG_GREENCFG2_GATE_DFSE_EN; 954 alc_miidbg_writereg(sc, MII_DBG_GREENCFG2, val); 955 956 /* RTL8139C, 120m issue. */ 957 alc_miiext_writereg(sc, MII_EXT_ANEG, MII_EXT_ANEG_NLP78, 958 ANEG_NLP78_120M_DEFAULT); 959 alc_miiext_writereg(sc, MII_EXT_ANEG, MII_EXT_ANEG_S3DIG10, 960 ANEG_S3DIG10_DEFAULT); 961 962 if ((sc->alc_flags & ALC_FLAG_LINK_WAR) != 0) { 963 /* Turn off half amplitude. */ 964 val = alc_miiext_readreg(sc, MII_EXT_PCS, MII_EXT_CLDCTL3); 965 val |= EXT_CLDCTL3_BP_CABLE1TH_DET_GT; 966 alc_miiext_writereg(sc, MII_EXT_PCS, MII_EXT_CLDCTL3, val); 967 /* Turn off Green feature. */ 968 val = alc_miidbg_readreg(sc, MII_DBG_GREENCFG2); 969 val |= DBG_GREENCFG2_BP_GREEN; 970 alc_miidbg_writereg(sc, MII_DBG_GREENCFG2, val); 971 /* Turn off half bias. */ 972 val = alc_miiext_readreg(sc, MII_EXT_PCS, MII_EXT_CLDCTL5); 973 val |= EXT_CLDCTL5_BP_VD_HLFBIAS; 974 alc_miiext_writereg(sc, MII_EXT_PCS, MII_EXT_CLDCTL5, val); 975 } 976 } 977 978 static void 979 alc_phy_down(struct alc_softc *sc) 980 { 981 uint32_t gphy; 982 983 switch (sc->alc_ident->deviceid) { 984 case PCI_PRODUCT_ATTANSIC_AR8161: 985 case PCI_PRODUCT_ATTANSIC_E2200: 986 case PCI_PRODUCT_ATTANSIC_AR8162: 987 case PCI_PRODUCT_ATTANSIC_AR8171: 988 case PCI_PRODUCT_ATTANSIC_AR8172: 989 gphy = CSR_READ_4(sc, ALC_GPHY_CFG); 990 gphy &= ~(GPHY_CFG_EXT_RESET | GPHY_CFG_LED_MODE | 991 GPHY_CFG_100AB_ENB | GPHY_CFG_PHY_PLL_ON); 992 gphy |= GPHY_CFG_HIB_EN | GPHY_CFG_HIB_PULSE | 993 GPHY_CFG_SEL_ANA_RESET; 994 gphy |= GPHY_CFG_PHY_IDDQ | GPHY_CFG_PWDOWN_HW; 995 CSR_WRITE_4(sc, ALC_GPHY_CFG, gphy); 996 break; 997 case PCI_PRODUCT_ATTANSIC_AR8151: 998 case PCI_PRODUCT_ATTANSIC_AR8151_V2: 999 case PCI_PRODUCT_ATTANSIC_AR8152_B: 1000 case PCI_PRODUCT_ATTANSIC_AR8152_B2: 1001 /* 1002 * GPHY power down caused more problems on AR8151 v2.0. 1003 * When driver is reloaded after GPHY power down, 1004 * accesses to PHY/MAC registers hung the system. Only 1005 * cold boot recovered from it. I'm not sure whether 1006 * AR8151 v1.0 also requires this one though. I don't 1007 * have AR8151 v1.0 controller in hand. 1008 * The only option left is to isolate the PHY and 1009 * initiates power down the PHY which in turn saves 1010 * more power when driver is unloaded. 1011 */ 1012 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 1013 MII_BMCR, BMCR_ISO | BMCR_PDOWN); 1014 break; 1015 default: 1016 /* Force PHY down. */ 1017 CSR_WRITE_2(sc, ALC_GPHY_CFG, GPHY_CFG_EXT_RESET | 1018 GPHY_CFG_SEL_ANA_RESET | GPHY_CFG_PHY_IDDQ | 1019 GPHY_CFG_PWDOWN_HW); 1020 DELAY(1000); 1021 break; 1022 } 1023 } 1024 1025 static void 1026 alc_aspm(struct alc_softc *sc, int init, int media) 1027 { 1028 1029 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 1030 alc_aspm_816x(sc, init); 1031 else 1032 alc_aspm_813x(sc, media); 1033 } 1034 1035 static void 1036 alc_aspm_813x(struct alc_softc *sc, int media) 1037 { 1038 uint32_t pmcfg; 1039 uint16_t linkcfg; 1040 1041 pmcfg = CSR_READ_4(sc, ALC_PM_CFG); 1042 if ((sc->alc_flags & (ALC_FLAG_APS | ALC_FLAG_PCIE)) == 1043 (ALC_FLAG_APS | ALC_FLAG_PCIE)) 1044 linkcfg = CSR_READ_2(sc, sc->alc_expcap + 1045 PCIE_LCSR); 1046 else 1047 linkcfg = 0; 1048 pmcfg &= ~PM_CFG_SERDES_PD_EX_L1; 1049 pmcfg &= ~(PM_CFG_L1_ENTRY_TIMER_MASK | PM_CFG_LCKDET_TIMER_MASK); 1050 pmcfg |= PM_CFG_MAC_ASPM_CHK; 1051 pmcfg |= (PM_CFG_LCKDET_TIMER_DEFAULT << PM_CFG_LCKDET_TIMER_SHIFT); 1052 pmcfg &= ~(PM_CFG_ASPM_L1_ENB | PM_CFG_ASPM_L0S_ENB); 1053 1054 if ((sc->alc_flags & ALC_FLAG_APS) != 0) { 1055 /* Disable extended sync except AR8152 B v1.0 */ 1056 linkcfg &= ~0x80; 1057 if (sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8152_B && 1058 sc->alc_rev == ATHEROS_AR8152_B_V10) 1059 linkcfg |= 0x80; 1060 CSR_WRITE_2(sc, sc->alc_expcap + PCIE_LCSR, 1061 linkcfg); 1062 pmcfg &= ~(PM_CFG_EN_BUFS_RX_L0S | PM_CFG_SA_DLY_ENB | 1063 PM_CFG_HOTRST); 1064 pmcfg |= (PM_CFG_L1_ENTRY_TIMER_DEFAULT << 1065 PM_CFG_L1_ENTRY_TIMER_SHIFT); 1066 pmcfg &= ~PM_CFG_PM_REQ_TIMER_MASK; 1067 pmcfg |= (PM_CFG_PM_REQ_TIMER_DEFAULT << 1068 PM_CFG_PM_REQ_TIMER_SHIFT); 1069 pmcfg |= PM_CFG_SERDES_PD_EX_L1 | PM_CFG_PCIE_RECV; 1070 } 1071 1072 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) { 1073 if ((sc->alc_flags & ALC_FLAG_L0S) != 0) 1074 pmcfg |= PM_CFG_ASPM_L0S_ENB; 1075 if ((sc->alc_flags & ALC_FLAG_L1S) != 0) 1076 pmcfg |= PM_CFG_ASPM_L1_ENB; 1077 if ((sc->alc_flags & ALC_FLAG_APS) != 0) { 1078 if (sc->alc_ident->deviceid == 1079 PCI_PRODUCT_ATTANSIC_AR8152_B) 1080 pmcfg &= ~PM_CFG_ASPM_L0S_ENB; 1081 pmcfg &= ~(PM_CFG_SERDES_L1_ENB | 1082 PM_CFG_SERDES_PLL_L1_ENB | 1083 PM_CFG_SERDES_BUDS_RX_L1_ENB); 1084 pmcfg |= PM_CFG_CLK_SWH_L1; 1085 if (media == IFM_100_TX || media == IFM_1000_T) { 1086 pmcfg &= ~PM_CFG_L1_ENTRY_TIMER_MASK; 1087 switch (sc->alc_ident->deviceid) { 1088 case PCI_PRODUCT_ATTANSIC_AR8152_B: 1089 pmcfg |= (7 << 1090 PM_CFG_L1_ENTRY_TIMER_SHIFT); 1091 break; 1092 case PCI_PRODUCT_ATTANSIC_AR8152_B2: 1093 case PCI_PRODUCT_ATTANSIC_AR8151_V2: 1094 pmcfg |= (4 << 1095 PM_CFG_L1_ENTRY_TIMER_SHIFT); 1096 break; 1097 default: 1098 pmcfg |= (15 << 1099 PM_CFG_L1_ENTRY_TIMER_SHIFT); 1100 break; 1101 } 1102 } 1103 } else { 1104 pmcfg |= PM_CFG_SERDES_L1_ENB | 1105 PM_CFG_SERDES_PLL_L1_ENB | 1106 PM_CFG_SERDES_BUDS_RX_L1_ENB; 1107 pmcfg &= ~(PM_CFG_CLK_SWH_L1 | 1108 PM_CFG_ASPM_L1_ENB | PM_CFG_ASPM_L0S_ENB); 1109 } 1110 } else { 1111 pmcfg &= ~(PM_CFG_SERDES_BUDS_RX_L1_ENB | PM_CFG_SERDES_L1_ENB | 1112 PM_CFG_SERDES_PLL_L1_ENB); 1113 pmcfg |= PM_CFG_CLK_SWH_L1; 1114 if ((sc->alc_flags & ALC_FLAG_L1S) != 0) 1115 pmcfg |= PM_CFG_ASPM_L1_ENB; 1116 } 1117 CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg); 1118 } 1119 1120 static void 1121 alc_aspm_816x(struct alc_softc *sc, int init) 1122 { 1123 uint32_t pmcfg; 1124 1125 pmcfg = CSR_READ_4(sc, ALC_PM_CFG); 1126 pmcfg &= ~PM_CFG_L1_ENTRY_TIMER_816X_MASK; 1127 pmcfg |= PM_CFG_L1_ENTRY_TIMER_816X_DEFAULT; 1128 pmcfg &= ~PM_CFG_PM_REQ_TIMER_MASK; 1129 pmcfg |= PM_CFG_PM_REQ_TIMER_816X_DEFAULT; 1130 pmcfg &= ~PM_CFG_LCKDET_TIMER_MASK; 1131 pmcfg |= PM_CFG_LCKDET_TIMER_DEFAULT; 1132 pmcfg |= PM_CFG_SERDES_PD_EX_L1 | PM_CFG_CLK_SWH_L1 | PM_CFG_PCIE_RECV; 1133 pmcfg &= ~(PM_CFG_RX_L1_AFTER_L0S | PM_CFG_TX_L1_AFTER_L0S | 1134 PM_CFG_ASPM_L1_ENB | PM_CFG_ASPM_L0S_ENB | 1135 PM_CFG_SERDES_L1_ENB | PM_CFG_SERDES_PLL_L1_ENB | 1136 PM_CFG_SERDES_BUDS_RX_L1_ENB | PM_CFG_SA_DLY_ENB | 1137 PM_CFG_MAC_ASPM_CHK | PM_CFG_HOTRST); 1138 if (AR816X_REV(sc->alc_rev) <= AR816X_REV_A1 && 1139 (sc->alc_rev & 0x01) != 0) 1140 pmcfg |= PM_CFG_SERDES_L1_ENB | PM_CFG_SERDES_PLL_L1_ENB; 1141 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) { 1142 /* Link up, enable both L0s, L1s. */ 1143 pmcfg |= PM_CFG_ASPM_L0S_ENB | PM_CFG_ASPM_L1_ENB | 1144 PM_CFG_MAC_ASPM_CHK; 1145 } else { 1146 if (init != 0) 1147 pmcfg |= PM_CFG_ASPM_L0S_ENB | PM_CFG_ASPM_L1_ENB | 1148 PM_CFG_MAC_ASPM_CHK; 1149 else if ((sc->sc_ec.ec_if.if_flags & IFF_RUNNING) != 0) 1150 pmcfg |= PM_CFG_ASPM_L1_ENB | PM_CFG_MAC_ASPM_CHK; 1151 } 1152 CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg); 1153 } 1154 1155 static void 1156 alc_attach(device_t parent, device_t self, void *aux) 1157 { 1158 1159 struct alc_softc *sc = device_private(self); 1160 struct pci_attach_args *pa = aux; 1161 pci_chipset_tag_t pc = pa->pa_pc; 1162 pci_intr_handle_t ih; 1163 const char *intrstr; 1164 struct ifnet *ifp; 1165 pcireg_t memtype; 1166 const char *aspm_state[] = { "L0s/L1", "L0s", "L1", "L0s/L1" }; 1167 uint16_t burst; 1168 int base, mii_flags, state, error = 0; 1169 uint32_t cap, ctl, val; 1170 char intrbuf[PCI_INTRSTR_LEN]; 1171 1172 sc->alc_ident = alc_find_ident(pa); 1173 1174 aprint_naive("\n"); 1175 aprint_normal(": %s\n", sc->alc_ident->name); 1176 1177 sc->sc_dev = self; 1178 sc->sc_dmat = pa->pa_dmat; 1179 sc->sc_pct = pa->pa_pc; 1180 sc->sc_pcitag = pa->pa_tag; 1181 1182 /* 1183 * Allocate IO memory 1184 */ 1185 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, ALC_PCIR_BAR); 1186 switch (memtype) { 1187 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 1188 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT_1M: 1189 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 1190 break; 1191 default: 1192 aprint_error_dev(self, "invalid base address register\n"); 1193 break; 1194 } 1195 1196 if (pci_mapreg_map(pa, ALC_PCIR_BAR, memtype, 0, &sc->sc_mem_bt, 1197 &sc->sc_mem_bh, NULL, &sc->sc_mem_size)) { 1198 aprint_error_dev(self, "could not map mem space\n"); 1199 return; 1200 } 1201 1202 if (pci_intr_map(pa, &ih) != 0) { 1203 printf(": can't map interrupt\n"); 1204 goto fail; 1205 } 1206 1207 /* 1208 * Allocate IRQ 1209 */ 1210 intrstr = pci_intr_string(sc->sc_pct, ih, intrbuf, sizeof(intrbuf)); 1211 sc->sc_irq_handle = pci_intr_establish(pc, ih, IPL_NET, alc_intr, sc); 1212 if (sc->sc_irq_handle == NULL) { 1213 printf(": could not establish interrupt"); 1214 if (intrstr != NULL) 1215 printf(" at %s", intrstr); 1216 printf("\n"); 1217 goto fail; 1218 } 1219 aprint_normal_dev(self, "interrupting at %s\n", intrstr); 1220 1221 /* Set PHY address. */ 1222 sc->alc_phyaddr = ALC_PHY_ADDR; 1223 1224 /* Initialize DMA parameters. */ 1225 sc->alc_dma_rd_burst = 0; 1226 sc->alc_dma_wr_burst = 0; 1227 sc->alc_rcb = DMA_CFG_RCB_64; 1228 if (pci_get_capability(pc, pa->pa_tag, PCI_CAP_PCIEXPRESS, 1229 &base, NULL)) { 1230 sc->alc_flags |= ALC_FLAG_PCIE; 1231 sc->alc_expcap = base; 1232 burst = pci_conf_read(sc->sc_pct, sc->sc_pcitag, 1233 base + PCIE_DCSR) >> 16; 1234 sc->alc_dma_rd_burst = (burst & 0x7000) >> 12; 1235 sc->alc_dma_wr_burst = (burst & 0x00e0) >> 5; 1236 if (alcdebug) { 1237 printf("%s: Read request size : %u bytes.\n", 1238 device_xname(sc->sc_dev), 1239 alc_dma_burst[sc->alc_dma_rd_burst]); 1240 printf("%s: TLP payload size : %u bytes.\n", 1241 device_xname(sc->sc_dev), 1242 alc_dma_burst[sc->alc_dma_wr_burst]); 1243 } 1244 if (alc_dma_burst[sc->alc_dma_rd_burst] > 1024) 1245 sc->alc_dma_rd_burst = 3; 1246 if (alc_dma_burst[sc->alc_dma_wr_burst] > 1024) 1247 sc->alc_dma_wr_burst = 3; 1248 1249 /* Clear data link and flow-control protocol error. */ 1250 val = CSR_READ_4(sc, ALC_PEX_UNC_ERR_SEV); 1251 val &= ~(PEX_UNC_ERR_SEV_DLP | PEX_UNC_ERR_SEV_FCP); 1252 CSR_WRITE_4(sc, ALC_PEX_UNC_ERR_SEV, val); 1253 1254 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 1255 CSR_WRITE_4(sc, ALC_LTSSM_ID_CFG, 1256 CSR_READ_4(sc, ALC_LTSSM_ID_CFG) & ~LTSSM_ID_WRO_ENB); 1257 CSR_WRITE_4(sc, ALC_PCIE_PHYMISC, 1258 CSR_READ_4(sc, ALC_PCIE_PHYMISC) | 1259 PCIE_PHYMISC_FORCE_RCV_DET); 1260 if (sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8152_B && 1261 sc->alc_rev == ATHEROS_AR8152_B_V10) { 1262 val = CSR_READ_4(sc, ALC_PCIE_PHYMISC2); 1263 val &= ~(PCIE_PHYMISC2_SERDES_CDR_MASK | 1264 PCIE_PHYMISC2_SERDES_TH_MASK); 1265 val |= 3 << PCIE_PHYMISC2_SERDES_CDR_SHIFT; 1266 val |= 3 << PCIE_PHYMISC2_SERDES_TH_SHIFT; 1267 CSR_WRITE_4(sc, ALC_PCIE_PHYMISC2, val); 1268 } 1269 /* Disable ASPM L0S and L1. */ 1270 cap = pci_conf_read(sc->sc_pct, sc->sc_pcitag, 1271 base + PCIE_LCAP) >> 16; 1272 if ((cap & PCIE_LCAP_ASPM) != 0) { 1273 ctl = pci_conf_read(sc->sc_pct, sc->sc_pcitag, 1274 base + PCIE_LCSR) >> 16; 1275 if ((ctl & 0x08) != 0) 1276 sc->alc_rcb = DMA_CFG_RCB_128; 1277 if (alcdebug) 1278 printf("%s: RCB %u bytes\n", 1279 device_xname(sc->sc_dev), 1280 sc->alc_rcb == DMA_CFG_RCB_64 ? 64 : 128); 1281 state = ctl & 0x03; 1282 if (state & 0x01) 1283 sc->alc_flags |= ALC_FLAG_L0S; 1284 if (state & 0x02) 1285 sc->alc_flags |= ALC_FLAG_L1S; 1286 if (alcdebug) 1287 printf("%s: ASPM %s %s\n", 1288 device_xname(sc->sc_dev), 1289 aspm_state[state], 1290 state == 0 ? "disabled" : "enabled"); 1291 alc_disable_l0s_l1(sc); 1292 } else { 1293 aprint_debug_dev(sc->sc_dev, "no ASPM support\n"); 1294 } 1295 } else { 1296 val = CSR_READ_4(sc, ALC_PDLL_TRNS1); 1297 val &= ~PDLL_TRNS1_D3PLLOFF_ENB; 1298 CSR_WRITE_4(sc, ALC_PDLL_TRNS1, val); 1299 val = CSR_READ_4(sc, ALC_MASTER_CFG); 1300 if (AR816X_REV(sc->alc_rev) <= AR816X_REV_A1 && 1301 (sc->alc_rev & 0x01) != 0) { 1302 if ((val & MASTER_WAKEN_25M) == 0 || 1303 (val & MASTER_CLK_SEL_DIS) == 0) { 1304 val |= MASTER_WAKEN_25M | MASTER_CLK_SEL_DIS; 1305 CSR_WRITE_4(sc, ALC_MASTER_CFG, val); 1306 } 1307 } else { 1308 if ((val & MASTER_WAKEN_25M) == 0 || 1309 (val & MASTER_CLK_SEL_DIS) != 0) { 1310 val |= MASTER_WAKEN_25M; 1311 val &= ~MASTER_CLK_SEL_DIS; 1312 CSR_WRITE_4(sc, ALC_MASTER_CFG, val); 1313 } 1314 } 1315 } 1316 alc_aspm(sc, 1, IFM_UNKNOWN); 1317 } 1318 1319 /* Reset PHY. */ 1320 alc_phy_reset(sc); 1321 1322 /* Reset the ethernet controller. */ 1323 alc_stop_mac(sc); 1324 alc_reset(sc); 1325 1326 /* 1327 * One odd thing is AR8132 uses the same PHY hardware(F1 1328 * gigabit PHY) of AR8131. So atphy(4) of AR8132 reports 1329 * the PHY supports 1000Mbps but that's not true. The PHY 1330 * used in AR8132 can't establish gigabit link even if it 1331 * shows the same PHY model/revision number of AR8131. 1332 */ 1333 switch (sc->alc_ident->deviceid) { 1334 case PCI_PRODUCT_ATTANSIC_AR8161: 1335 if (PCI_SUBSYS_ID(pci_conf_read( 1336 sc->sc_pct, sc->sc_pcitag, PCI_SUBSYS_ID_REG)) == 0x0091 && 1337 sc->alc_rev == 0) 1338 sc->alc_flags |= ALC_FLAG_LINK_WAR; 1339 /* FALLTHROUGH */ 1340 case PCI_PRODUCT_ATTANSIC_E2200: 1341 case PCI_PRODUCT_ATTANSIC_AR8171: 1342 sc->alc_flags |= ALC_FLAG_AR816X_FAMILY; 1343 break; 1344 case PCI_PRODUCT_ATTANSIC_AR8162: 1345 case PCI_PRODUCT_ATTANSIC_AR8172: 1346 sc->alc_flags |= ALC_FLAG_FASTETHER | ALC_FLAG_AR816X_FAMILY; 1347 break; 1348 case PCI_PRODUCT_ATTANSIC_AR8152_B: 1349 case PCI_PRODUCT_ATTANSIC_AR8152_B2: 1350 sc->alc_flags |= ALC_FLAG_APS; 1351 /* FALLTHROUGH */ 1352 case PCI_PRODUCT_ATTANSIC_AR8132: 1353 sc->alc_flags |= ALC_FLAG_FASTETHER; 1354 break; 1355 case PCI_PRODUCT_ATTANSIC_AR8151: 1356 case PCI_PRODUCT_ATTANSIC_AR8151_V2: 1357 sc->alc_flags |= ALC_FLAG_APS; 1358 /* FALLTHROUGH */ 1359 default: 1360 break; 1361 } 1362 sc->alc_flags |= ALC_FLAG_JUMBO; 1363 1364 /* 1365 * It seems that AR813x/AR815x has silicon bug for SMB. In 1366 * addition, Atheros said that enabling SMB wouldn't improve 1367 * performance. However I think it's bad to access lots of 1368 * registers to extract MAC statistics. 1369 */ 1370 sc->alc_flags |= ALC_FLAG_SMB_BUG; 1371 /* 1372 * Don't use Tx CMB. It is known to have silicon bug. 1373 */ 1374 sc->alc_flags |= ALC_FLAG_CMB_BUG; 1375 sc->alc_rev = PCI_REVISION(pa->pa_class); 1376 sc->alc_chip_rev = CSR_READ_4(sc, ALC_MASTER_CFG) >> 1377 MASTER_CHIP_REV_SHIFT; 1378 if (alcdebug) { 1379 printf("%s: PCI device revision : 0x%04x\n", 1380 device_xname(sc->sc_dev), sc->alc_rev); 1381 printf("%s: Chip id/revision : 0x%04x\n", 1382 device_xname(sc->sc_dev), sc->alc_chip_rev); 1383 printf("%s: %u Tx FIFO, %u Rx FIFO\n", device_xname(sc->sc_dev), 1384 CSR_READ_4(sc, ALC_SRAM_TX_FIFO_LEN) * 8, 1385 CSR_READ_4(sc, ALC_SRAM_RX_FIFO_LEN) * 8); 1386 } 1387 1388 error = alc_dma_alloc(sc); 1389 if (error) 1390 goto fail; 1391 1392 callout_init(&sc->sc_tick_ch, 0); 1393 callout_setfunc(&sc->sc_tick_ch, alc_tick, sc); 1394 1395 /* Load station address. */ 1396 alc_get_macaddr(sc); 1397 1398 aprint_normal_dev(self, "Ethernet address %s\n", 1399 ether_sprintf(sc->alc_eaddr)); 1400 1401 ifp = &sc->sc_ec.ec_if; 1402 ifp->if_softc = sc; 1403 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1404 ifp->if_init = alc_init; 1405 ifp->if_ioctl = alc_ioctl; 1406 ifp->if_start = alc_start; 1407 ifp->if_stop = alc_stop; 1408 ifp->if_watchdog = alc_watchdog; 1409 IFQ_SET_MAXLEN(&ifp->if_snd, ALC_TX_RING_CNT - 1); 1410 IFQ_SET_READY(&ifp->if_snd); 1411 strlcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 1412 1413 sc->sc_ec.ec_capabilities = ETHERCAP_VLAN_MTU; 1414 1415 #ifdef ALC_CHECKSUM 1416 ifp->if_capabilities |= IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 1417 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 1418 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 1419 #endif 1420 1421 #if NVLAN > 0 1422 sc->sc_ec.ec_capabilities |= ETHERCAP_VLAN_HWTAGGING; 1423 #endif 1424 1425 /* 1426 * XXX 1427 * It seems enabling Tx checksum offloading makes more trouble. 1428 * Sometimes the controller does not receive any frames when 1429 * Tx checksum offloading is enabled. I'm not sure whether this 1430 * is a bug in Tx checksum offloading logic or I got broken 1431 * sample boards. To safety, don't enable Tx checksum offloading 1432 * by default but give chance to users to toggle it if they know 1433 * their controllers work without problems. 1434 * Fortunately, Tx checksum offloading for AR816x family 1435 * seems to work. 1436 */ 1437 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 1438 ifp->if_capenable &= ~IFCAP_CSUM_IPv4_Tx; 1439 ifp->if_capabilities &= ~ALC_CSUM_FEATURES; 1440 } 1441 1442 /* Set up MII bus. */ 1443 sc->sc_miibus.mii_ifp = ifp; 1444 sc->sc_miibus.mii_readreg = alc_miibus_readreg; 1445 sc->sc_miibus.mii_writereg = alc_miibus_writereg; 1446 sc->sc_miibus.mii_statchg = alc_miibus_statchg; 1447 1448 sc->sc_ec.ec_mii = &sc->sc_miibus; 1449 ifmedia_init(&sc->sc_miibus.mii_media, 0, alc_mediachange, 1450 alc_mediastatus); 1451 mii_flags = 0; 1452 if ((sc->alc_flags & ALC_FLAG_JUMBO) != 0) 1453 mii_flags |= MIIF_DOPAUSE; 1454 mii_attach(self, &sc->sc_miibus, 0xffffffff, MII_PHY_ANY, 1455 MII_OFFSET_ANY, mii_flags); 1456 1457 if (LIST_FIRST(&sc->sc_miibus.mii_phys) == NULL) { 1458 printf("%s: no PHY found!\n", device_xname(sc->sc_dev)); 1459 ifmedia_add(&sc->sc_miibus.mii_media, IFM_ETHER | IFM_MANUAL, 1460 0, NULL); 1461 ifmedia_set(&sc->sc_miibus.mii_media, IFM_ETHER | IFM_MANUAL); 1462 } else 1463 ifmedia_set(&sc->sc_miibus.mii_media, IFM_ETHER | IFM_AUTO); 1464 1465 if_attach(ifp); 1466 if_deferred_start_init(ifp, NULL); 1467 ether_ifattach(ifp, sc->alc_eaddr); 1468 1469 if (!pmf_device_register(self, NULL, NULL)) 1470 aprint_error_dev(self, "couldn't establish power handler\n"); 1471 else 1472 pmf_class_network_register(self, ifp); 1473 1474 return; 1475 fail: 1476 alc_dma_free(sc); 1477 if (sc->sc_irq_handle != NULL) { 1478 pci_intr_disestablish(sc->sc_pct, sc->sc_irq_handle); 1479 sc->sc_irq_handle = NULL; 1480 } 1481 if (sc->sc_mem_size) { 1482 bus_space_unmap(sc->sc_mem_bt, sc->sc_mem_bh, sc->sc_mem_size); 1483 sc->sc_mem_size = 0; 1484 } 1485 } 1486 1487 static int 1488 alc_detach(device_t self, int flags) 1489 { 1490 struct alc_softc *sc = device_private(self); 1491 struct ifnet *ifp = &sc->sc_ec.ec_if; 1492 int s; 1493 1494 s = splnet(); 1495 alc_stop(ifp, 0); 1496 splx(s); 1497 1498 mii_detach(&sc->sc_miibus, MII_PHY_ANY, MII_OFFSET_ANY); 1499 1500 /* Delete all remaining media. */ 1501 ifmedia_delete_instance(&sc->sc_miibus.mii_media, IFM_INST_ANY); 1502 1503 ether_ifdetach(ifp); 1504 if_detach(ifp); 1505 alc_dma_free(sc); 1506 1507 alc_phy_down(sc); 1508 if (sc->sc_irq_handle != NULL) { 1509 pci_intr_disestablish(sc->sc_pct, sc->sc_irq_handle); 1510 sc->sc_irq_handle = NULL; 1511 } 1512 if (sc->sc_mem_size) { 1513 bus_space_unmap(sc->sc_mem_bt, sc->sc_mem_bh, sc->sc_mem_size); 1514 sc->sc_mem_size = 0; 1515 } 1516 1517 return (0); 1518 } 1519 1520 static int 1521 alc_dma_alloc(struct alc_softc *sc) 1522 { 1523 struct alc_txdesc *txd; 1524 struct alc_rxdesc *rxd; 1525 int nsegs, error, i; 1526 1527 /* 1528 * Create DMA stuffs for TX ring 1529 */ 1530 error = bus_dmamap_create(sc->sc_dmat, ALC_TX_RING_SZ, 1, 1531 ALC_TX_RING_SZ, 0, BUS_DMA_NOWAIT, &sc->alc_cdata.alc_tx_ring_map); 1532 if (error) { 1533 sc->alc_cdata.alc_tx_ring_map = NULL; 1534 return (ENOBUFS); 1535 } 1536 1537 /* Allocate DMA'able memory for TX ring */ 1538 error = bus_dmamem_alloc(sc->sc_dmat, ALC_TX_RING_SZ, 1539 ETHER_ALIGN, 0, &sc->alc_rdata.alc_tx_ring_seg, 1, 1540 &nsegs, BUS_DMA_NOWAIT); 1541 if (error) { 1542 printf("%s: could not allocate DMA'able memory for Tx ring.\n", 1543 device_xname(sc->sc_dev)); 1544 return error; 1545 } 1546 1547 error = bus_dmamem_map(sc->sc_dmat, &sc->alc_rdata.alc_tx_ring_seg, 1548 nsegs, ALC_TX_RING_SZ, (void **)&sc->alc_rdata.alc_tx_ring, 1549 BUS_DMA_NOWAIT); 1550 if (error) 1551 return (ENOBUFS); 1552 1553 /* Load the DMA map for Tx ring. */ 1554 error = bus_dmamap_load(sc->sc_dmat, sc->alc_cdata.alc_tx_ring_map, 1555 sc->alc_rdata.alc_tx_ring, ALC_TX_RING_SZ, NULL, BUS_DMA_WAITOK); 1556 if (error) { 1557 printf("%s: could not load DMA'able memory for Tx ring.\n", 1558 device_xname(sc->sc_dev)); 1559 bus_dmamem_free(sc->sc_dmat, 1560 &sc->alc_rdata.alc_tx_ring_seg, 1); 1561 return error; 1562 } 1563 1564 sc->alc_rdata.alc_tx_ring_paddr = 1565 sc->alc_cdata.alc_tx_ring_map->dm_segs[0].ds_addr; 1566 1567 /* 1568 * Create DMA stuffs for RX ring 1569 */ 1570 error = bus_dmamap_create(sc->sc_dmat, ALC_RX_RING_SZ, 1, 1571 ALC_RX_RING_SZ, 0, BUS_DMA_NOWAIT, &sc->alc_cdata.alc_rx_ring_map); 1572 if (error) 1573 return (ENOBUFS); 1574 1575 /* Allocate DMA'able memory for RX ring */ 1576 error = bus_dmamem_alloc(sc->sc_dmat, ALC_RX_RING_SZ, 1577 ETHER_ALIGN, 0, &sc->alc_rdata.alc_rx_ring_seg, 1, 1578 &nsegs, BUS_DMA_NOWAIT); 1579 if (error) { 1580 printf("%s: could not allocate DMA'able memory for Rx ring.\n", 1581 device_xname(sc->sc_dev)); 1582 return error; 1583 } 1584 1585 error = bus_dmamem_map(sc->sc_dmat, &sc->alc_rdata.alc_rx_ring_seg, 1586 nsegs, ALC_RX_RING_SZ, (void **)&sc->alc_rdata.alc_rx_ring, 1587 BUS_DMA_NOWAIT); 1588 if (error) 1589 return (ENOBUFS); 1590 1591 /* Load the DMA map for Rx ring. */ 1592 error = bus_dmamap_load(sc->sc_dmat, sc->alc_cdata.alc_rx_ring_map, 1593 sc->alc_rdata.alc_rx_ring, ALC_RX_RING_SZ, NULL, BUS_DMA_WAITOK); 1594 if (error) { 1595 printf("%s: could not load DMA'able memory for Rx ring.\n", 1596 device_xname(sc->sc_dev)); 1597 bus_dmamem_free(sc->sc_dmat, 1598 &sc->alc_rdata.alc_rx_ring_seg, 1); 1599 return error; 1600 } 1601 1602 sc->alc_rdata.alc_rx_ring_paddr = 1603 sc->alc_cdata.alc_rx_ring_map->dm_segs[0].ds_addr; 1604 1605 /* 1606 * Create DMA stuffs for RX return ring 1607 */ 1608 error = bus_dmamap_create(sc->sc_dmat, ALC_RR_RING_SZ, 1, 1609 ALC_RR_RING_SZ, 0, BUS_DMA_NOWAIT, &sc->alc_cdata.alc_rr_ring_map); 1610 if (error) 1611 return (ENOBUFS); 1612 1613 /* Allocate DMA'able memory for RX return ring */ 1614 error = bus_dmamem_alloc(sc->sc_dmat, ALC_RR_RING_SZ, 1615 ETHER_ALIGN, 0, &sc->alc_rdata.alc_rr_ring_seg, 1, 1616 &nsegs, BUS_DMA_NOWAIT); 1617 if (error) { 1618 printf("%s: could not allocate DMA'able memory for Rx " 1619 "return ring.\n", device_xname(sc->sc_dev)); 1620 return error; 1621 } 1622 1623 error = bus_dmamem_map(sc->sc_dmat, &sc->alc_rdata.alc_rr_ring_seg, 1624 nsegs, ALC_RR_RING_SZ, (void **)&sc->alc_rdata.alc_rr_ring, 1625 BUS_DMA_NOWAIT); 1626 if (error) 1627 return (ENOBUFS); 1628 1629 /* Load the DMA map for Rx return ring. */ 1630 error = bus_dmamap_load(sc->sc_dmat, sc->alc_cdata.alc_rr_ring_map, 1631 sc->alc_rdata.alc_rr_ring, ALC_RR_RING_SZ, NULL, BUS_DMA_WAITOK); 1632 if (error) { 1633 printf("%s: could not load DMA'able memory for Rx return ring." 1634 "\n", device_xname(sc->sc_dev)); 1635 bus_dmamem_free(sc->sc_dmat, 1636 &sc->alc_rdata.alc_rr_ring_seg, 1); 1637 return error; 1638 } 1639 1640 sc->alc_rdata.alc_rr_ring_paddr = 1641 sc->alc_cdata.alc_rr_ring_map->dm_segs[0].ds_addr; 1642 1643 /* 1644 * Create DMA stuffs for CMB block 1645 */ 1646 error = bus_dmamap_create(sc->sc_dmat, ALC_CMB_SZ, 1, 1647 ALC_CMB_SZ, 0, BUS_DMA_NOWAIT, 1648 &sc->alc_cdata.alc_cmb_map); 1649 if (error) 1650 return (ENOBUFS); 1651 1652 /* Allocate DMA'able memory for CMB block */ 1653 error = bus_dmamem_alloc(sc->sc_dmat, ALC_CMB_SZ, 1654 ETHER_ALIGN, 0, &sc->alc_rdata.alc_cmb_seg, 1, 1655 &nsegs, BUS_DMA_NOWAIT); 1656 if (error) { 1657 printf("%s: could not allocate DMA'able memory for " 1658 "CMB block\n", device_xname(sc->sc_dev)); 1659 return error; 1660 } 1661 1662 error = bus_dmamem_map(sc->sc_dmat, &sc->alc_rdata.alc_cmb_seg, 1663 nsegs, ALC_CMB_SZ, (void **)&sc->alc_rdata.alc_cmb, 1664 BUS_DMA_NOWAIT); 1665 if (error) 1666 return (ENOBUFS); 1667 1668 /* Load the DMA map for CMB block. */ 1669 error = bus_dmamap_load(sc->sc_dmat, sc->alc_cdata.alc_cmb_map, 1670 sc->alc_rdata.alc_cmb, ALC_CMB_SZ, NULL, 1671 BUS_DMA_WAITOK); 1672 if (error) { 1673 printf("%s: could not load DMA'able memory for CMB block\n", 1674 device_xname(sc->sc_dev)); 1675 bus_dmamem_free(sc->sc_dmat, 1676 &sc->alc_rdata.alc_cmb_seg, 1); 1677 return error; 1678 } 1679 1680 sc->alc_rdata.alc_cmb_paddr = 1681 sc->alc_cdata.alc_cmb_map->dm_segs[0].ds_addr; 1682 1683 /* 1684 * Create DMA stuffs for SMB block 1685 */ 1686 error = bus_dmamap_create(sc->sc_dmat, ALC_SMB_SZ, 1, 1687 ALC_SMB_SZ, 0, BUS_DMA_NOWAIT, 1688 &sc->alc_cdata.alc_smb_map); 1689 if (error) 1690 return (ENOBUFS); 1691 1692 /* Allocate DMA'able memory for SMB block */ 1693 error = bus_dmamem_alloc(sc->sc_dmat, ALC_SMB_SZ, 1694 ETHER_ALIGN, 0, &sc->alc_rdata.alc_smb_seg, 1, 1695 &nsegs, BUS_DMA_NOWAIT); 1696 if (error) { 1697 printf("%s: could not allocate DMA'able memory for " 1698 "SMB block\n", device_xname(sc->sc_dev)); 1699 return error; 1700 } 1701 1702 error = bus_dmamem_map(sc->sc_dmat, &sc->alc_rdata.alc_smb_seg, 1703 nsegs, ALC_SMB_SZ, (void **)&sc->alc_rdata.alc_smb, 1704 BUS_DMA_NOWAIT); 1705 if (error) 1706 return (ENOBUFS); 1707 1708 /* Load the DMA map for SMB block */ 1709 error = bus_dmamap_load(sc->sc_dmat, sc->alc_cdata.alc_smb_map, 1710 sc->alc_rdata.alc_smb, ALC_SMB_SZ, NULL, 1711 BUS_DMA_WAITOK); 1712 if (error) { 1713 printf("%s: could not load DMA'able memory for SMB block\n", 1714 device_xname(sc->sc_dev)); 1715 bus_dmamem_free(sc->sc_dmat, 1716 &sc->alc_rdata.alc_smb_seg, 1); 1717 return error; 1718 } 1719 1720 sc->alc_rdata.alc_smb_paddr = 1721 sc->alc_cdata.alc_smb_map->dm_segs[0].ds_addr; 1722 1723 1724 /* Create DMA maps for Tx buffers. */ 1725 for (i = 0; i < ALC_TX_RING_CNT; i++) { 1726 txd = &sc->alc_cdata.alc_txdesc[i]; 1727 txd->tx_m = NULL; 1728 txd->tx_dmamap = NULL; 1729 error = bus_dmamap_create(sc->sc_dmat, ALC_TSO_MAXSIZE, 1730 ALC_MAXTXSEGS, ALC_TSO_MAXSEGSIZE, 0, BUS_DMA_NOWAIT, 1731 &txd->tx_dmamap); 1732 if (error) { 1733 printf("%s: could not create Tx dmamap.\n", 1734 device_xname(sc->sc_dev)); 1735 return error; 1736 } 1737 } 1738 1739 /* Create DMA maps for Rx buffers. */ 1740 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES, 0, 1741 BUS_DMA_NOWAIT, &sc->alc_cdata.alc_rx_sparemap); 1742 if (error) { 1743 printf("%s: could not create spare Rx dmamap.\n", 1744 device_xname(sc->sc_dev)); 1745 return error; 1746 } 1747 1748 for (i = 0; i < ALC_RX_RING_CNT; i++) { 1749 rxd = &sc->alc_cdata.alc_rxdesc[i]; 1750 rxd->rx_m = NULL; 1751 rxd->rx_dmamap = NULL; 1752 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 1753 MCLBYTES, 0, BUS_DMA_NOWAIT, &rxd->rx_dmamap); 1754 if (error) { 1755 printf("%s: could not create Rx dmamap.\n", 1756 device_xname(sc->sc_dev)); 1757 return error; 1758 } 1759 } 1760 1761 return (0); 1762 } 1763 1764 1765 static void 1766 alc_dma_free(struct alc_softc *sc) 1767 { 1768 struct alc_txdesc *txd; 1769 struct alc_rxdesc *rxd; 1770 int i; 1771 1772 /* Tx buffers */ 1773 for (i = 0; i < ALC_TX_RING_CNT; i++) { 1774 txd = &sc->alc_cdata.alc_txdesc[i]; 1775 if (txd->tx_dmamap != NULL) { 1776 bus_dmamap_destroy(sc->sc_dmat, txd->tx_dmamap); 1777 txd->tx_dmamap = NULL; 1778 } 1779 } 1780 /* Rx buffers */ 1781 for (i = 0; i < ALC_RX_RING_CNT; i++) { 1782 rxd = &sc->alc_cdata.alc_rxdesc[i]; 1783 if (rxd->rx_dmamap != NULL) { 1784 bus_dmamap_destroy(sc->sc_dmat, rxd->rx_dmamap); 1785 rxd->rx_dmamap = NULL; 1786 } 1787 } 1788 if (sc->alc_cdata.alc_rx_sparemap != NULL) { 1789 bus_dmamap_destroy(sc->sc_dmat, sc->alc_cdata.alc_rx_sparemap); 1790 sc->alc_cdata.alc_rx_sparemap = NULL; 1791 } 1792 1793 /* Tx ring. */ 1794 if (sc->alc_cdata.alc_tx_ring_map != NULL) 1795 bus_dmamap_unload(sc->sc_dmat, sc->alc_cdata.alc_tx_ring_map); 1796 if (sc->alc_cdata.alc_tx_ring_map != NULL && 1797 sc->alc_rdata.alc_tx_ring != NULL) 1798 bus_dmamem_free(sc->sc_dmat, 1799 &sc->alc_rdata.alc_tx_ring_seg, 1); 1800 sc->alc_rdata.alc_tx_ring = NULL; 1801 sc->alc_cdata.alc_tx_ring_map = NULL; 1802 1803 /* Rx ring. */ 1804 if (sc->alc_cdata.alc_rx_ring_map != NULL) 1805 bus_dmamap_unload(sc->sc_dmat, sc->alc_cdata.alc_rx_ring_map); 1806 if (sc->alc_cdata.alc_rx_ring_map != NULL && 1807 sc->alc_rdata.alc_rx_ring != NULL) 1808 bus_dmamem_free(sc->sc_dmat, 1809 &sc->alc_rdata.alc_rx_ring_seg, 1); 1810 sc->alc_rdata.alc_rx_ring = NULL; 1811 sc->alc_cdata.alc_rx_ring_map = NULL; 1812 1813 /* Rx return ring. */ 1814 if (sc->alc_cdata.alc_rr_ring_map != NULL) 1815 bus_dmamap_unload(sc->sc_dmat, sc->alc_cdata.alc_rr_ring_map); 1816 if (sc->alc_cdata.alc_rr_ring_map != NULL && 1817 sc->alc_rdata.alc_rr_ring != NULL) 1818 bus_dmamem_free(sc->sc_dmat, 1819 &sc->alc_rdata.alc_rr_ring_seg, 1); 1820 sc->alc_rdata.alc_rr_ring = NULL; 1821 sc->alc_cdata.alc_rr_ring_map = NULL; 1822 1823 /* CMB block */ 1824 if (sc->alc_cdata.alc_cmb_map != NULL) 1825 bus_dmamap_unload(sc->sc_dmat, sc->alc_cdata.alc_cmb_map); 1826 if (sc->alc_cdata.alc_cmb_map != NULL && 1827 sc->alc_rdata.alc_cmb != NULL) 1828 bus_dmamem_free(sc->sc_dmat, 1829 &sc->alc_rdata.alc_cmb_seg, 1); 1830 sc->alc_rdata.alc_cmb = NULL; 1831 sc->alc_cdata.alc_cmb_map = NULL; 1832 1833 /* SMB block */ 1834 if (sc->alc_cdata.alc_smb_map != NULL) 1835 bus_dmamap_unload(sc->sc_dmat, sc->alc_cdata.alc_smb_map); 1836 if (sc->alc_cdata.alc_smb_map != NULL && 1837 sc->alc_rdata.alc_smb != NULL) 1838 bus_dmamem_free(sc->sc_dmat, 1839 &sc->alc_rdata.alc_smb_seg, 1); 1840 sc->alc_rdata.alc_smb = NULL; 1841 sc->alc_cdata.alc_smb_map = NULL; 1842 } 1843 1844 static int 1845 alc_encap(struct alc_softc *sc, struct mbuf **m_head) 1846 { 1847 struct alc_txdesc *txd, *txd_last; 1848 struct tx_desc *desc; 1849 struct mbuf *m; 1850 bus_dmamap_t map; 1851 uint32_t cflags, poff, vtag; 1852 int error, idx, nsegs, prod; 1853 1854 m = *m_head; 1855 cflags = vtag = 0; 1856 poff = 0; 1857 1858 prod = sc->alc_cdata.alc_tx_prod; 1859 txd = &sc->alc_cdata.alc_txdesc[prod]; 1860 txd_last = txd; 1861 map = txd->tx_dmamap; 1862 1863 error = bus_dmamap_load_mbuf(sc->sc_dmat, map, *m_head, BUS_DMA_NOWAIT); 1864 1865 if (error == EFBIG) { 1866 error = 0; 1867 1868 *m_head = m_pullup(*m_head, MHLEN); 1869 if (*m_head == NULL) { 1870 printf("%s: can't defrag TX mbuf\n", 1871 device_xname(sc->sc_dev)); 1872 return ENOBUFS; 1873 } 1874 1875 error = bus_dmamap_load_mbuf(sc->sc_dmat, map, *m_head, 1876 BUS_DMA_NOWAIT); 1877 1878 if (error != 0) { 1879 printf("%s: could not load defragged TX mbuf\n", 1880 device_xname(sc->sc_dev)); 1881 m_freem(*m_head); 1882 *m_head = NULL; 1883 return error; 1884 } 1885 } else if (error) { 1886 printf("%s: could not load TX mbuf\n", device_xname(sc->sc_dev)); 1887 return (error); 1888 } 1889 1890 nsegs = map->dm_nsegs; 1891 1892 if (nsegs == 0) { 1893 m_freem(*m_head); 1894 *m_head = NULL; 1895 return (EIO); 1896 } 1897 1898 /* Check descriptor overrun. */ 1899 if (sc->alc_cdata.alc_tx_cnt + nsegs >= ALC_TX_RING_CNT - 3) { 1900 bus_dmamap_unload(sc->sc_dmat, map); 1901 return (ENOBUFS); 1902 } 1903 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 1904 BUS_DMASYNC_PREWRITE); 1905 1906 m = *m_head; 1907 desc = NULL; 1908 idx = 0; 1909 #if NVLAN > 0 1910 /* Configure VLAN hardware tag insertion. */ 1911 if (vlan_has_tag(m)) { 1912 vtag = htons(vlan_get_tag(m)); 1913 vtag = (vtag << TD_VLAN_SHIFT) & TD_VLAN_MASK; 1914 cflags |= TD_INS_VLAN_TAG; 1915 } 1916 #endif 1917 /* Configure Tx checksum offload. */ 1918 if ((m->m_pkthdr.csum_flags & ALC_CSUM_FEATURES) != 0) { 1919 cflags |= TD_CUSTOM_CSUM; 1920 /* Set checksum start offset. */ 1921 cflags |= ((poff >> 1) << TD_PLOAD_OFFSET_SHIFT) & 1922 TD_PLOAD_OFFSET_MASK; 1923 } 1924 for (; idx < nsegs; idx++) { 1925 desc = &sc->alc_rdata.alc_tx_ring[prod]; 1926 desc->len = 1927 htole32(TX_BYTES(map->dm_segs[idx].ds_len) | vtag); 1928 desc->flags = htole32(cflags); 1929 desc->addr = htole64(map->dm_segs[idx].ds_addr); 1930 sc->alc_cdata.alc_tx_cnt++; 1931 ALC_DESC_INC(prod, ALC_TX_RING_CNT); 1932 } 1933 /* Update producer index. */ 1934 sc->alc_cdata.alc_tx_prod = prod; 1935 1936 /* Finally set EOP on the last descriptor. */ 1937 prod = (prod + ALC_TX_RING_CNT - 1) % ALC_TX_RING_CNT; 1938 desc = &sc->alc_rdata.alc_tx_ring[prod]; 1939 desc->flags |= htole32(TD_EOP); 1940 1941 /* Swap dmamap of the first and the last. */ 1942 txd = &sc->alc_cdata.alc_txdesc[prod]; 1943 map = txd_last->tx_dmamap; 1944 txd_last->tx_dmamap = txd->tx_dmamap; 1945 txd->tx_dmamap = map; 1946 txd->tx_m = m; 1947 1948 return (0); 1949 } 1950 1951 static void 1952 alc_start(struct ifnet *ifp) 1953 { 1954 struct alc_softc *sc = ifp->if_softc; 1955 struct mbuf *m_head; 1956 int enq; 1957 1958 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 1959 return; 1960 if ((sc->alc_flags & ALC_FLAG_LINK) == 0) 1961 return; 1962 if (IFQ_IS_EMPTY(&ifp->if_snd)) 1963 return; 1964 1965 /* Reclaim transmitted frames. */ 1966 if (sc->alc_cdata.alc_tx_cnt >= ALC_TX_DESC_HIWAT) 1967 alc_txeof(sc); 1968 1969 enq = 0; 1970 for (;;) { 1971 IFQ_DEQUEUE(&ifp->if_snd, m_head); 1972 if (m_head == NULL) 1973 break; 1974 1975 /* 1976 * Pack the data into the transmit ring. If we 1977 * don't have room, set the OACTIVE flag and wait 1978 * for the NIC to drain the ring. 1979 */ 1980 if (alc_encap(sc, &m_head)) { 1981 if (m_head == NULL) 1982 break; 1983 ifp->if_flags |= IFF_OACTIVE; 1984 break; 1985 } 1986 enq = 1; 1987 1988 /* 1989 * If there's a BPF listener, bounce a copy of this frame 1990 * to him. 1991 */ 1992 bpf_mtap(ifp, m_head, BPF_D_OUT); 1993 } 1994 1995 if (enq) { 1996 /* Sync descriptors. */ 1997 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_tx_ring_map, 0, 1998 sc->alc_cdata.alc_tx_ring_map->dm_mapsize, 1999 BUS_DMASYNC_PREWRITE); 2000 /* Kick. Assume we're using normal Tx priority queue. */ 2001 CSR_WRITE_4(sc, ALC_MBOX_TD_PROD_IDX, 2002 (sc->alc_cdata.alc_tx_prod << 2003 MBOX_TD_PROD_LO_IDX_SHIFT) & 2004 MBOX_TD_PROD_LO_IDX_MASK); 2005 /* Set a timeout in case the chip goes out to lunch. */ 2006 ifp->if_timer = ALC_TX_TIMEOUT; 2007 } 2008 } 2009 2010 static void 2011 alc_watchdog(struct ifnet *ifp) 2012 { 2013 struct alc_softc *sc = ifp->if_softc; 2014 2015 if ((sc->alc_flags & ALC_FLAG_LINK) == 0) { 2016 printf("%s: watchdog timeout (missed link)\n", 2017 device_xname(sc->sc_dev)); 2018 ifp->if_oerrors++; 2019 alc_init_backend(ifp, false); 2020 return; 2021 } 2022 2023 printf("%s: watchdog timeout\n", device_xname(sc->sc_dev)); 2024 ifp->if_oerrors++; 2025 alc_init_backend(ifp, false); 2026 alc_start(ifp); 2027 } 2028 2029 static int 2030 alc_ioctl(struct ifnet *ifp, u_long cmd, void *data) 2031 { 2032 struct alc_softc *sc = ifp->if_softc; 2033 struct mii_data *mii = &sc->sc_miibus; 2034 struct ifreq *ifr = (struct ifreq *)data; 2035 int s, error = 0; 2036 2037 s = splnet(); 2038 2039 error = ether_ioctl(ifp, cmd, data); 2040 switch (cmd) { 2041 case SIOCSIFADDR: 2042 ifp->if_flags |= IFF_UP; 2043 if (!(ifp->if_flags & IFF_RUNNING)) 2044 alc_init(ifp); 2045 break; 2046 2047 case SIOCSIFFLAGS: 2048 if (ifp->if_flags & IFF_UP) { 2049 if (ifp->if_flags & IFF_RUNNING) 2050 error = ENETRESET; 2051 else 2052 alc_init(ifp); 2053 } else { 2054 if (ifp->if_flags & IFF_RUNNING) 2055 alc_stop(ifp, 0); 2056 } 2057 break; 2058 2059 case SIOCSIFMEDIA: 2060 case SIOCGIFMEDIA: 2061 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd); 2062 break; 2063 2064 default: 2065 error = ether_ioctl(ifp, cmd, data); 2066 break; 2067 } 2068 2069 if (error == ENETRESET) { 2070 if (ifp->if_flags & IFF_RUNNING) 2071 alc_iff(sc); 2072 error = 0; 2073 } 2074 2075 splx(s); 2076 return (error); 2077 } 2078 2079 static void 2080 alc_mac_config(struct alc_softc *sc) 2081 { 2082 struct mii_data *mii; 2083 uint32_t reg; 2084 2085 mii = &sc->sc_miibus; 2086 reg = CSR_READ_4(sc, ALC_MAC_CFG); 2087 reg &= ~(MAC_CFG_FULL_DUPLEX | MAC_CFG_TX_FC | MAC_CFG_RX_FC | 2088 MAC_CFG_SPEED_MASK); 2089 if (sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8151 || 2090 sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8151_V2 || 2091 sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8152_B2) 2092 reg |= MAC_CFG_HASH_ALG_CRC32 | MAC_CFG_SPEED_MODE_SW; 2093 /* Reprogram MAC with resolved speed/duplex. */ 2094 switch (IFM_SUBTYPE(mii->mii_media_active)) { 2095 case IFM_10_T: 2096 case IFM_100_TX: 2097 reg |= MAC_CFG_SPEED_10_100; 2098 break; 2099 case IFM_1000_T: 2100 reg |= MAC_CFG_SPEED_1000; 2101 break; 2102 } 2103 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 2104 reg |= MAC_CFG_FULL_DUPLEX; 2105 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0) 2106 reg |= MAC_CFG_TX_FC; 2107 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0) 2108 reg |= MAC_CFG_RX_FC; 2109 } 2110 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 2111 } 2112 2113 static void 2114 alc_stats_clear(struct alc_softc *sc) 2115 { 2116 struct smb sb, *smb; 2117 uint32_t *reg; 2118 int i; 2119 2120 if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0) { 2121 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_smb_map, 0, 2122 sc->alc_cdata.alc_smb_map->dm_mapsize, 2123 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2124 smb = sc->alc_rdata.alc_smb; 2125 /* Update done, clear. */ 2126 smb->updated = 0; 2127 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_smb_map, 0, 2128 sc->alc_cdata.alc_smb_map->dm_mapsize, 2129 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2130 } else { 2131 for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered; 2132 reg++) { 2133 CSR_READ_4(sc, ALC_RX_MIB_BASE + i); 2134 i += sizeof(uint32_t); 2135 } 2136 /* Read Tx statistics. */ 2137 for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes; 2138 reg++) { 2139 CSR_READ_4(sc, ALC_TX_MIB_BASE + i); 2140 i += sizeof(uint32_t); 2141 } 2142 } 2143 } 2144 2145 static void 2146 alc_stats_update(struct alc_softc *sc) 2147 { 2148 struct ifnet *ifp = &sc->sc_ec.ec_if; 2149 struct alc_hw_stats *stat; 2150 struct smb sb, *smb; 2151 uint32_t *reg; 2152 int i; 2153 2154 stat = &sc->alc_stats; 2155 if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0) { 2156 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_smb_map, 0, 2157 sc->alc_cdata.alc_smb_map->dm_mapsize, 2158 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2159 smb = sc->alc_rdata.alc_smb; 2160 if (smb->updated == 0) 2161 return; 2162 } else { 2163 smb = &sb; 2164 /* Read Rx statistics. */ 2165 for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered; 2166 reg++) { 2167 *reg = CSR_READ_4(sc, ALC_RX_MIB_BASE + i); 2168 i += sizeof(uint32_t); 2169 } 2170 /* Read Tx statistics. */ 2171 for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes; 2172 reg++) { 2173 *reg = CSR_READ_4(sc, ALC_TX_MIB_BASE + i); 2174 i += sizeof(uint32_t); 2175 } 2176 } 2177 2178 /* Rx stats. */ 2179 stat->rx_frames += smb->rx_frames; 2180 stat->rx_bcast_frames += smb->rx_bcast_frames; 2181 stat->rx_mcast_frames += smb->rx_mcast_frames; 2182 stat->rx_pause_frames += smb->rx_pause_frames; 2183 stat->rx_control_frames += smb->rx_control_frames; 2184 stat->rx_crcerrs += smb->rx_crcerrs; 2185 stat->rx_lenerrs += smb->rx_lenerrs; 2186 stat->rx_bytes += smb->rx_bytes; 2187 stat->rx_runts += smb->rx_runts; 2188 stat->rx_fragments += smb->rx_fragments; 2189 stat->rx_pkts_64 += smb->rx_pkts_64; 2190 stat->rx_pkts_65_127 += smb->rx_pkts_65_127; 2191 stat->rx_pkts_128_255 += smb->rx_pkts_128_255; 2192 stat->rx_pkts_256_511 += smb->rx_pkts_256_511; 2193 stat->rx_pkts_512_1023 += smb->rx_pkts_512_1023; 2194 stat->rx_pkts_1024_1518 += smb->rx_pkts_1024_1518; 2195 stat->rx_pkts_1519_max += smb->rx_pkts_1519_max; 2196 stat->rx_pkts_truncated += smb->rx_pkts_truncated; 2197 stat->rx_fifo_oflows += smb->rx_fifo_oflows; 2198 stat->rx_rrs_errs += smb->rx_rrs_errs; 2199 stat->rx_alignerrs += smb->rx_alignerrs; 2200 stat->rx_bcast_bytes += smb->rx_bcast_bytes; 2201 stat->rx_mcast_bytes += smb->rx_mcast_bytes; 2202 stat->rx_pkts_filtered += smb->rx_pkts_filtered; 2203 2204 /* Tx stats. */ 2205 stat->tx_frames += smb->tx_frames; 2206 stat->tx_bcast_frames += smb->tx_bcast_frames; 2207 stat->tx_mcast_frames += smb->tx_mcast_frames; 2208 stat->tx_pause_frames += smb->tx_pause_frames; 2209 stat->tx_excess_defer += smb->tx_excess_defer; 2210 stat->tx_control_frames += smb->tx_control_frames; 2211 stat->tx_deferred += smb->tx_deferred; 2212 stat->tx_bytes += smb->tx_bytes; 2213 stat->tx_pkts_64 += smb->tx_pkts_64; 2214 stat->tx_pkts_65_127 += smb->tx_pkts_65_127; 2215 stat->tx_pkts_128_255 += smb->tx_pkts_128_255; 2216 stat->tx_pkts_256_511 += smb->tx_pkts_256_511; 2217 stat->tx_pkts_512_1023 += smb->tx_pkts_512_1023; 2218 stat->tx_pkts_1024_1518 += smb->tx_pkts_1024_1518; 2219 stat->tx_pkts_1519_max += smb->tx_pkts_1519_max; 2220 stat->tx_single_colls += smb->tx_single_colls; 2221 stat->tx_multi_colls += smb->tx_multi_colls; 2222 stat->tx_late_colls += smb->tx_late_colls; 2223 stat->tx_excess_colls += smb->tx_excess_colls; 2224 stat->tx_underrun += smb->tx_underrun; 2225 stat->tx_desc_underrun += smb->tx_desc_underrun; 2226 stat->tx_lenerrs += smb->tx_lenerrs; 2227 stat->tx_pkts_truncated += smb->tx_pkts_truncated; 2228 stat->tx_bcast_bytes += smb->tx_bcast_bytes; 2229 stat->tx_mcast_bytes += smb->tx_mcast_bytes; 2230 2231 /* Update counters in ifnet. */ 2232 ifp->if_opackets += smb->tx_frames; 2233 2234 ifp->if_collisions += smb->tx_single_colls + 2235 smb->tx_multi_colls * 2 + smb->tx_late_colls + 2236 smb->tx_excess_colls * HDPX_CFG_RETRY_DEFAULT; 2237 2238 ifp->if_oerrors += smb->tx_late_colls + smb->tx_excess_colls + 2239 smb->tx_underrun + smb->tx_pkts_truncated; 2240 2241 ifp->if_ipackets += smb->rx_frames; 2242 2243 ifp->if_ierrors += smb->rx_crcerrs + smb->rx_lenerrs + 2244 smb->rx_runts + smb->rx_pkts_truncated + 2245 smb->rx_fifo_oflows + smb->rx_rrs_errs + 2246 smb->rx_alignerrs; 2247 2248 if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0) { 2249 /* Update done, clear. */ 2250 smb->updated = 0; 2251 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_smb_map, 0, 2252 sc->alc_cdata.alc_smb_map->dm_mapsize, 2253 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2254 } 2255 } 2256 2257 static int 2258 alc_intr(void *arg) 2259 { 2260 struct alc_softc *sc = arg; 2261 struct ifnet *ifp = &sc->sc_ec.ec_if; 2262 uint32_t status; 2263 2264 status = CSR_READ_4(sc, ALC_INTR_STATUS); 2265 if ((status & ALC_INTRS) == 0) 2266 return (0); 2267 2268 /* Acknowledge and disable interrupts. */ 2269 CSR_WRITE_4(sc, ALC_INTR_STATUS, status | INTR_DIS_INT); 2270 2271 if (ifp->if_flags & IFF_RUNNING) { 2272 if (status & INTR_RX_PKT) { 2273 int error; 2274 2275 error = alc_rxintr(sc); 2276 if (error) { 2277 alc_init_backend(ifp, false); 2278 return (0); 2279 } 2280 } 2281 2282 if (status & (INTR_DMA_RD_TO_RST | INTR_DMA_WR_TO_RST | 2283 INTR_TXQ_TO_RST)) { 2284 if (status & INTR_DMA_RD_TO_RST) 2285 printf("%s: DMA read error! -- resetting\n", 2286 device_xname(sc->sc_dev)); 2287 if (status & INTR_DMA_WR_TO_RST) 2288 printf("%s: DMA write error! -- resetting\n", 2289 device_xname(sc->sc_dev)); 2290 if (status & INTR_TXQ_TO_RST) 2291 printf("%s: TxQ reset! -- resetting\n", 2292 device_xname(sc->sc_dev)); 2293 alc_init_backend(ifp, false); 2294 return (0); 2295 } 2296 2297 alc_txeof(sc); 2298 if_schedule_deferred_start(ifp); 2299 } 2300 2301 /* Re-enable interrupts. */ 2302 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0x7FFFFFFF); 2303 return (1); 2304 } 2305 2306 static void 2307 alc_txeof(struct alc_softc *sc) 2308 { 2309 struct ifnet *ifp = &sc->sc_ec.ec_if; 2310 struct alc_txdesc *txd; 2311 uint32_t cons, prod; 2312 int prog; 2313 2314 if (sc->alc_cdata.alc_tx_cnt == 0) 2315 return; 2316 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_tx_ring_map, 0, 2317 sc->alc_cdata.alc_tx_ring_map->dm_mapsize, 2318 BUS_DMASYNC_POSTREAD); 2319 if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0) { 2320 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_cmb_map, 0, 2321 sc->alc_cdata.alc_cmb_map->dm_mapsize, 2322 BUS_DMASYNC_POSTREAD); 2323 prod = sc->alc_rdata.alc_cmb->cons; 2324 } else 2325 prod = CSR_READ_4(sc, ALC_MBOX_TD_CONS_IDX); 2326 /* Assume we're using normal Tx priority queue. */ 2327 prod = (prod & MBOX_TD_CONS_LO_IDX_MASK) >> 2328 MBOX_TD_CONS_LO_IDX_SHIFT; 2329 cons = sc->alc_cdata.alc_tx_cons; 2330 /* 2331 * Go through our Tx list and free mbufs for those 2332 * frames which have been transmitted. 2333 */ 2334 for (prog = 0; cons != prod; prog++, 2335 ALC_DESC_INC(cons, ALC_TX_RING_CNT)) { 2336 if (sc->alc_cdata.alc_tx_cnt <= 0) 2337 break; 2338 prog++; 2339 ifp->if_flags &= ~IFF_OACTIVE; 2340 sc->alc_cdata.alc_tx_cnt--; 2341 txd = &sc->alc_cdata.alc_txdesc[cons]; 2342 if (txd->tx_m != NULL) { 2343 /* Reclaim transmitted mbufs. */ 2344 bus_dmamap_sync(sc->sc_dmat, txd->tx_dmamap, 0, 2345 txd->tx_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 2346 bus_dmamap_unload(sc->sc_dmat, txd->tx_dmamap); 2347 m_freem(txd->tx_m); 2348 txd->tx_m = NULL; 2349 } 2350 } 2351 2352 if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0) 2353 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_cmb_map, 0, 2354 sc->alc_cdata.alc_cmb_map->dm_mapsize, BUS_DMASYNC_PREREAD); 2355 sc->alc_cdata.alc_tx_cons = cons; 2356 /* 2357 * Unarm watchdog timer only when there is no pending 2358 * frames in Tx queue. 2359 */ 2360 if (sc->alc_cdata.alc_tx_cnt == 0) 2361 ifp->if_timer = 0; 2362 } 2363 2364 static int 2365 alc_newbuf(struct alc_softc *sc, struct alc_rxdesc *rxd, bool init) 2366 { 2367 struct mbuf *m; 2368 bus_dmamap_t map; 2369 int error; 2370 2371 MGETHDR(m, init ? M_WAITOK : M_DONTWAIT, MT_DATA); 2372 if (m == NULL) 2373 return (ENOBUFS); 2374 MCLGET(m, init ? M_WAITOK : M_DONTWAIT); 2375 if (!(m->m_flags & M_EXT)) { 2376 m_freem(m); 2377 return (ENOBUFS); 2378 } 2379 2380 m->m_len = m->m_pkthdr.len = RX_BUF_SIZE_MAX; 2381 2382 error = bus_dmamap_load_mbuf(sc->sc_dmat, 2383 sc->alc_cdata.alc_rx_sparemap, m, BUS_DMA_NOWAIT); 2384 2385 if (error != 0) { 2386 m_freem(m); 2387 2388 if (init) 2389 printf("%s: can't load RX mbuf\n", device_xname(sc->sc_dev)); 2390 2391 return (error); 2392 } 2393 2394 if (rxd->rx_m != NULL) { 2395 bus_dmamap_sync(sc->sc_dmat, rxd->rx_dmamap, 0, 2396 rxd->rx_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 2397 bus_dmamap_unload(sc->sc_dmat, rxd->rx_dmamap); 2398 } 2399 map = rxd->rx_dmamap; 2400 rxd->rx_dmamap = sc->alc_cdata.alc_rx_sparemap; 2401 sc->alc_cdata.alc_rx_sparemap = map; 2402 bus_dmamap_sync(sc->sc_dmat, rxd->rx_dmamap, 0, rxd->rx_dmamap->dm_mapsize, 2403 BUS_DMASYNC_PREREAD); 2404 rxd->rx_m = m; 2405 rxd->rx_desc->addr = htole64(rxd->rx_dmamap->dm_segs[0].ds_addr); 2406 return (0); 2407 } 2408 2409 static int 2410 alc_rxintr(struct alc_softc *sc) 2411 { 2412 struct ifnet *ifp = &sc->sc_ec.ec_if; 2413 struct rx_rdesc *rrd; 2414 uint32_t nsegs, status; 2415 int rr_cons, prog; 2416 2417 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_rr_ring_map, 0, 2418 sc->alc_cdata.alc_rr_ring_map->dm_mapsize, 2419 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2420 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_rx_ring_map, 0, 2421 sc->alc_cdata.alc_rx_ring_map->dm_mapsize, 2422 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2423 rr_cons = sc->alc_cdata.alc_rr_cons; 2424 for (prog = 0; (ifp->if_flags & IFF_RUNNING) != 0;) { 2425 rrd = &sc->alc_rdata.alc_rr_ring[rr_cons]; 2426 status = le32toh(rrd->status); 2427 if ((status & RRD_VALID) == 0) 2428 break; 2429 nsegs = RRD_RD_CNT(le32toh(rrd->rdinfo)); 2430 if (nsegs == 0) { 2431 /* This should not happen! */ 2432 if (alcdebug) 2433 printf("%s: unexpected segment count -- " 2434 "resetting\n", device_xname(sc->sc_dev)); 2435 return (EIO); 2436 } 2437 alc_rxeof(sc, rrd); 2438 /* Clear Rx return status. */ 2439 rrd->status = 0; 2440 ALC_DESC_INC(rr_cons, ALC_RR_RING_CNT); 2441 sc->alc_cdata.alc_rx_cons += nsegs; 2442 sc->alc_cdata.alc_rx_cons %= ALC_RR_RING_CNT; 2443 prog += nsegs; 2444 } 2445 2446 if (prog > 0) { 2447 /* Update the consumer index. */ 2448 sc->alc_cdata.alc_rr_cons = rr_cons; 2449 /* Sync Rx return descriptors. */ 2450 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_rr_ring_map, 0, 2451 sc->alc_cdata.alc_rr_ring_map->dm_mapsize, 2452 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2453 /* 2454 * Sync updated Rx descriptors such that controller see 2455 * modified buffer addresses. 2456 */ 2457 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_rx_ring_map, 0, 2458 sc->alc_cdata.alc_rx_ring_map->dm_mapsize, 2459 BUS_DMASYNC_PREWRITE); 2460 /* 2461 * Let controller know availability of new Rx buffers. 2462 * Since alc(4) use RXQ_CFG_RD_BURST_DEFAULT descriptors 2463 * it may be possible to update ALC_MBOX_RD0_PROD_IDX 2464 * only when Rx buffer pre-fetching is required. In 2465 * addition we already set ALC_RX_RD_FREE_THRESH to 2466 * RX_RD_FREE_THRESH_LO_DEFAULT descriptors. However 2467 * it still seems that pre-fetching needs more 2468 * experimentation. 2469 */ 2470 CSR_WRITE_4(sc, ALC_MBOX_RD0_PROD_IDX, 2471 sc->alc_cdata.alc_rx_cons); 2472 } 2473 2474 return (0); 2475 } 2476 2477 /* Receive a frame. */ 2478 static void 2479 alc_rxeof(struct alc_softc *sc, struct rx_rdesc *rrd) 2480 { 2481 struct ifnet *ifp = &sc->sc_ec.ec_if; 2482 struct alc_rxdesc *rxd; 2483 struct mbuf *mp, *m; 2484 uint32_t rdinfo, status; 2485 int count, nsegs, rx_cons; 2486 2487 status = le32toh(rrd->status); 2488 rdinfo = le32toh(rrd->rdinfo); 2489 rx_cons = RRD_RD_IDX(rdinfo); 2490 nsegs = RRD_RD_CNT(rdinfo); 2491 2492 sc->alc_cdata.alc_rxlen = RRD_BYTES(status); 2493 if (status & (RRD_ERR_SUM | RRD_ERR_LENGTH)) { 2494 /* 2495 * We want to pass the following frames to upper 2496 * layer regardless of error status of Rx return 2497 * ring. 2498 * 2499 * o IP/TCP/UDP checksum is bad. 2500 * o frame length and protocol specific length 2501 * does not match. 2502 * 2503 * Force network stack compute checksum for 2504 * errored frames. 2505 */ 2506 status |= RRD_TCP_UDPCSUM_NOK | RRD_IPCSUM_NOK; 2507 if ((status & (RRD_ERR_CRC | RRD_ERR_ALIGN | 2508 RRD_ERR_TRUNC | RRD_ERR_RUNT)) != 0) 2509 return; 2510 } 2511 2512 for (count = 0; count < nsegs; count++, 2513 ALC_DESC_INC(rx_cons, ALC_RX_RING_CNT)) { 2514 rxd = &sc->alc_cdata.alc_rxdesc[rx_cons]; 2515 mp = rxd->rx_m; 2516 /* Add a new receive buffer to the ring. */ 2517 if (alc_newbuf(sc, rxd, false) != 0) { 2518 ifp->if_iqdrops++; 2519 /* Reuse Rx buffers. */ 2520 if (sc->alc_cdata.alc_rxhead != NULL) 2521 m_freem(sc->alc_cdata.alc_rxhead); 2522 break; 2523 } 2524 2525 /* 2526 * Assume we've received a full sized frame. 2527 * Actual size is fixed when we encounter the end of 2528 * multi-segmented frame. 2529 */ 2530 mp->m_len = sc->alc_buf_size; 2531 2532 /* Chain received mbufs. */ 2533 if (sc->alc_cdata.alc_rxhead == NULL) { 2534 sc->alc_cdata.alc_rxhead = mp; 2535 sc->alc_cdata.alc_rxtail = mp; 2536 } else { 2537 m_remove_pkthdr(mp); 2538 sc->alc_cdata.alc_rxprev_tail = 2539 sc->alc_cdata.alc_rxtail; 2540 sc->alc_cdata.alc_rxtail->m_next = mp; 2541 sc->alc_cdata.alc_rxtail = mp; 2542 } 2543 2544 if (count == nsegs - 1) { 2545 /* Last desc. for this frame. */ 2546 m = sc->alc_cdata.alc_rxhead; 2547 KASSERT(m->m_flags & M_PKTHDR); 2548 /* 2549 * It seems that L1C/L2C controller has no way 2550 * to tell hardware to strip CRC bytes. 2551 */ 2552 m->m_pkthdr.len = 2553 sc->alc_cdata.alc_rxlen - ETHER_CRC_LEN; 2554 if (nsegs > 1) { 2555 /* Set last mbuf size. */ 2556 mp->m_len = sc->alc_cdata.alc_rxlen - 2557 (nsegs - 1) * sc->alc_buf_size; 2558 /* Remove the CRC bytes in chained mbufs. */ 2559 if (mp->m_len <= ETHER_CRC_LEN) { 2560 sc->alc_cdata.alc_rxtail = 2561 sc->alc_cdata.alc_rxprev_tail; 2562 sc->alc_cdata.alc_rxtail->m_len -= 2563 (ETHER_CRC_LEN - mp->m_len); 2564 sc->alc_cdata.alc_rxtail->m_next = NULL; 2565 m_freem(mp); 2566 } else { 2567 mp->m_len -= ETHER_CRC_LEN; 2568 } 2569 } else 2570 m->m_len = m->m_pkthdr.len; 2571 m_set_rcvif(m, ifp); 2572 #if NVLAN > 0 2573 /* 2574 * Due to hardware bugs, Rx checksum offloading 2575 * was intentionally disabled. 2576 */ 2577 if (status & RRD_VLAN_TAG) { 2578 u_int32_t vtag = RRD_VLAN(le32toh(rrd->vtag)); 2579 vlan_set_tag(m, ntohs(vtag)); 2580 } 2581 #endif 2582 2583 /* Pass it on. */ 2584 if_percpuq_enqueue(ifp->if_percpuq, m); 2585 } 2586 } 2587 /* Reset mbuf chains. */ 2588 ALC_RXCHAIN_RESET(sc); 2589 } 2590 2591 static void 2592 alc_tick(void *xsc) 2593 { 2594 struct alc_softc *sc = xsc; 2595 struct mii_data *mii = &sc->sc_miibus; 2596 int s; 2597 2598 s = splnet(); 2599 mii_tick(mii); 2600 alc_stats_update(sc); 2601 splx(s); 2602 2603 callout_schedule(&sc->sc_tick_ch, hz); 2604 } 2605 2606 static void 2607 alc_osc_reset(struct alc_softc *sc) 2608 { 2609 uint32_t reg; 2610 2611 reg = CSR_READ_4(sc, ALC_MISC3); 2612 reg &= ~MISC3_25M_BY_SW; 2613 reg |= MISC3_25M_NOTO_INTNL; 2614 CSR_WRITE_4(sc, ALC_MISC3, reg); 2615 2616 reg = CSR_READ_4(sc, ALC_MISC); 2617 if (AR816X_REV(sc->alc_rev) >= AR816X_REV_B0) { 2618 /* 2619 * Restore over-current protection default value. 2620 * This value could be reset by MAC reset. 2621 */ 2622 reg &= ~MISC_PSW_OCP_MASK; 2623 reg |= (MISC_PSW_OCP_DEFAULT << MISC_PSW_OCP_SHIFT); 2624 reg &= ~MISC_INTNLOSC_OPEN; 2625 CSR_WRITE_4(sc, ALC_MISC, reg); 2626 CSR_WRITE_4(sc, ALC_MISC, reg | MISC_INTNLOSC_OPEN); 2627 reg = CSR_READ_4(sc, ALC_MISC2); 2628 reg &= ~MISC2_CALB_START; 2629 CSR_WRITE_4(sc, ALC_MISC2, reg); 2630 CSR_WRITE_4(sc, ALC_MISC2, reg | MISC2_CALB_START); 2631 2632 } else { 2633 reg &= ~MISC_INTNLOSC_OPEN; 2634 /* Disable isolate for revision A devices. */ 2635 if (AR816X_REV(sc->alc_rev) <= AR816X_REV_A1) 2636 reg &= ~MISC_ISO_ENB; 2637 CSR_WRITE_4(sc, ALC_MISC, reg | MISC_INTNLOSC_OPEN); 2638 CSR_WRITE_4(sc, ALC_MISC, reg); 2639 } 2640 2641 DELAY(20); 2642 } 2643 2644 static void 2645 alc_reset(struct alc_softc *sc) 2646 { 2647 uint32_t pmcfg, reg; 2648 int i; 2649 2650 pmcfg = 0; 2651 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 2652 /* Reset workaround. */ 2653 CSR_WRITE_4(sc, ALC_MBOX_RD0_PROD_IDX, 1); 2654 if (AR816X_REV(sc->alc_rev) <= AR816X_REV_A1 && 2655 (sc->alc_rev & 0x01) != 0) { 2656 /* Disable L0s/L1s before reset. */ 2657 pmcfg = CSR_READ_4(sc, ALC_PM_CFG); 2658 if ((pmcfg & (PM_CFG_ASPM_L0S_ENB | PM_CFG_ASPM_L1_ENB)) 2659 != 0) { 2660 pmcfg &= ~(PM_CFG_ASPM_L0S_ENB | 2661 PM_CFG_ASPM_L1_ENB); 2662 CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg); 2663 } 2664 } 2665 } 2666 reg = CSR_READ_4(sc, ALC_MASTER_CFG); 2667 reg |= MASTER_OOB_DIS_OFF | MASTER_RESET; 2668 CSR_WRITE_4(sc, ALC_MASTER_CFG, reg); 2669 2670 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 2671 for (i = ALC_RESET_TIMEOUT; i > 0; i--) { 2672 DELAY(10); 2673 if (CSR_READ_4(sc, ALC_MBOX_RD0_PROD_IDX) == 0) 2674 break; 2675 } 2676 if (i == 0) 2677 printf("%s: MAC reset timeout!\n", device_xname(sc->sc_dev)); 2678 } 2679 for (i = ALC_RESET_TIMEOUT; i > 0; i--) { 2680 DELAY(10); 2681 if ((CSR_READ_4(sc, ALC_MASTER_CFG) & MASTER_RESET) == 0) 2682 break; 2683 } 2684 if (i == 0) 2685 printf("%s: master reset timeout!\n", device_xname(sc->sc_dev)); 2686 2687 for (i = ALC_RESET_TIMEOUT; i > 0; i--) { 2688 reg = CSR_READ_4(sc, ALC_IDLE_STATUS); 2689 if ((reg & (IDLE_STATUS_RXMAC | IDLE_STATUS_TXMAC | 2690 IDLE_STATUS_RXQ | IDLE_STATUS_TXQ)) == 0) 2691 break; 2692 DELAY(10); 2693 } 2694 if (i == 0) 2695 printf("%s: reset timeout(0x%08x)!\n", 2696 device_xname(sc->sc_dev), reg); 2697 2698 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 2699 if (AR816X_REV(sc->alc_rev) <= AR816X_REV_A1 && 2700 (sc->alc_rev & 0x01) != 0) { 2701 reg = CSR_READ_4(sc, ALC_MASTER_CFG); 2702 reg |= MASTER_CLK_SEL_DIS; 2703 CSR_WRITE_4(sc, ALC_MASTER_CFG, reg); 2704 /* Restore L0s/L1s config. */ 2705 if ((pmcfg & (PM_CFG_ASPM_L0S_ENB | PM_CFG_ASPM_L1_ENB)) 2706 != 0) 2707 CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg); 2708 } 2709 2710 alc_osc_reset(sc); 2711 reg = CSR_READ_4(sc, ALC_MISC3); 2712 reg &= ~MISC3_25M_BY_SW; 2713 reg |= MISC3_25M_NOTO_INTNL; 2714 CSR_WRITE_4(sc, ALC_MISC3, reg); 2715 reg = CSR_READ_4(sc, ALC_MISC); 2716 reg &= ~MISC_INTNLOSC_OPEN; 2717 if (AR816X_REV(sc->alc_rev) <= AR816X_REV_A1) 2718 reg &= ~MISC_ISO_ENB; 2719 CSR_WRITE_4(sc, ALC_MISC, reg); 2720 DELAY(20); 2721 } 2722 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0 || 2723 sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8152_B || 2724 sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8151_V2) 2725 CSR_WRITE_4(sc, ALC_SERDES_LOCK, 2726 CSR_READ_4(sc, ALC_SERDES_LOCK) | SERDES_MAC_CLK_SLOWDOWN | 2727 SERDES_PHY_CLK_SLOWDOWN); 2728 } 2729 2730 static int 2731 alc_init(struct ifnet *ifp) 2732 { 2733 2734 return alc_init_backend(ifp, true); 2735 } 2736 2737 static int 2738 alc_init_backend(struct ifnet *ifp, bool init) 2739 { 2740 struct alc_softc *sc = ifp->if_softc; 2741 struct mii_data *mii; 2742 uint8_t eaddr[ETHER_ADDR_LEN]; 2743 bus_addr_t paddr; 2744 uint32_t reg, rxf_hi, rxf_lo; 2745 int error; 2746 2747 /* 2748 * Cancel any pending I/O. 2749 */ 2750 alc_stop(ifp, 0); 2751 /* 2752 * Reset the chip to a known state. 2753 */ 2754 alc_reset(sc); 2755 2756 /* Initialize Rx descriptors. */ 2757 error = alc_init_rx_ring(sc, init); 2758 if (error != 0) { 2759 printf("%s: no memory for Rx buffers.\n", device_xname(sc->sc_dev)); 2760 alc_stop(ifp, 0); 2761 return (error); 2762 } 2763 alc_init_rr_ring(sc); 2764 alc_init_tx_ring(sc); 2765 alc_init_cmb(sc); 2766 alc_init_smb(sc); 2767 2768 /* Enable all clocks. */ 2769 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 2770 CSR_WRITE_4(sc, ALC_CLK_GATING_CFG, CLK_GATING_DMAW_ENB | 2771 CLK_GATING_DMAR_ENB | CLK_GATING_TXQ_ENB | 2772 CLK_GATING_RXQ_ENB | CLK_GATING_TXMAC_ENB | 2773 CLK_GATING_RXMAC_ENB); 2774 if (AR816X_REV(sc->alc_rev) >= AR816X_REV_B0) 2775 CSR_WRITE_4(sc, ALC_IDLE_DECISN_TIMER, 2776 IDLE_DECISN_TIMER_DEFAULT_1MS); 2777 } else 2778 CSR_WRITE_4(sc, ALC_CLK_GATING_CFG, 0); 2779 2780 2781 /* Reprogram the station address. */ 2782 memcpy(eaddr, CLLADDR(ifp->if_sadl), sizeof(eaddr)); 2783 CSR_WRITE_4(sc, ALC_PAR0, 2784 eaddr[2] << 24 | eaddr[3] << 16 | eaddr[4] << 8 | eaddr[5]); 2785 CSR_WRITE_4(sc, ALC_PAR1, eaddr[0] << 8 | eaddr[1]); 2786 /* 2787 * Clear WOL status and disable all WOL feature as WOL 2788 * would interfere Rx operation under normal environments. 2789 */ 2790 CSR_READ_4(sc, ALC_WOL_CFG); 2791 CSR_WRITE_4(sc, ALC_WOL_CFG, 0); 2792 /* Set Tx descriptor base addresses. */ 2793 paddr = sc->alc_rdata.alc_tx_ring_paddr; 2794 CSR_WRITE_4(sc, ALC_TX_BASE_ADDR_HI, ALC_ADDR_HI(paddr)); 2795 CSR_WRITE_4(sc, ALC_TDL_HEAD_ADDR_LO, ALC_ADDR_LO(paddr)); 2796 /* We don't use high priority ring. */ 2797 CSR_WRITE_4(sc, ALC_TDH_HEAD_ADDR_LO, 0); 2798 /* Set Tx descriptor counter. */ 2799 CSR_WRITE_4(sc, ALC_TD_RING_CNT, 2800 (ALC_TX_RING_CNT << TD_RING_CNT_SHIFT) & TD_RING_CNT_MASK); 2801 /* Set Rx descriptor base addresses. */ 2802 paddr = sc->alc_rdata.alc_rx_ring_paddr; 2803 CSR_WRITE_4(sc, ALC_RX_BASE_ADDR_HI, ALC_ADDR_HI(paddr)); 2804 CSR_WRITE_4(sc, ALC_RD0_HEAD_ADDR_LO, ALC_ADDR_LO(paddr)); 2805 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 2806 /* We use one Rx ring. */ 2807 CSR_WRITE_4(sc, ALC_RD1_HEAD_ADDR_LO, 0); 2808 CSR_WRITE_4(sc, ALC_RD2_HEAD_ADDR_LO, 0); 2809 CSR_WRITE_4(sc, ALC_RD3_HEAD_ADDR_LO, 0); 2810 } 2811 /* Set Rx descriptor counter. */ 2812 CSR_WRITE_4(sc, ALC_RD_RING_CNT, 2813 (ALC_RX_RING_CNT << RD_RING_CNT_SHIFT) & RD_RING_CNT_MASK); 2814 2815 /* 2816 * Let hardware split jumbo frames into alc_max_buf_sized chunks. 2817 * if it do not fit the buffer size. Rx return descriptor holds 2818 * a counter that indicates how many fragments were made by the 2819 * hardware. The buffer size should be multiple of 8 bytes. 2820 * Since hardware has limit on the size of buffer size, always 2821 * use the maximum value. 2822 * For strict-alignment architectures make sure to reduce buffer 2823 * size by 8 bytes to make room for alignment fixup. 2824 */ 2825 sc->alc_buf_size = RX_BUF_SIZE_MAX; 2826 CSR_WRITE_4(sc, ALC_RX_BUF_SIZE, sc->alc_buf_size); 2827 2828 paddr = sc->alc_rdata.alc_rr_ring_paddr; 2829 /* Set Rx return descriptor base addresses. */ 2830 CSR_WRITE_4(sc, ALC_RRD0_HEAD_ADDR_LO, ALC_ADDR_LO(paddr)); 2831 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 2832 /* We use one Rx return ring. */ 2833 CSR_WRITE_4(sc, ALC_RRD1_HEAD_ADDR_LO, 0); 2834 CSR_WRITE_4(sc, ALC_RRD2_HEAD_ADDR_LO, 0); 2835 CSR_WRITE_4(sc, ALC_RRD3_HEAD_ADDR_LO, 0); 2836 }\ 2837 /* Set Rx return descriptor counter. */ 2838 CSR_WRITE_4(sc, ALC_RRD_RING_CNT, 2839 (ALC_RR_RING_CNT << RRD_RING_CNT_SHIFT) & RRD_RING_CNT_MASK); 2840 paddr = sc->alc_rdata.alc_cmb_paddr; 2841 CSR_WRITE_4(sc, ALC_CMB_BASE_ADDR_LO, ALC_ADDR_LO(paddr)); 2842 paddr = sc->alc_rdata.alc_smb_paddr; 2843 CSR_WRITE_4(sc, ALC_SMB_BASE_ADDR_HI, ALC_ADDR_HI(paddr)); 2844 CSR_WRITE_4(sc, ALC_SMB_BASE_ADDR_LO, ALC_ADDR_LO(paddr)); 2845 2846 if (sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8152_B) { 2847 /* Reconfigure SRAM - Vendor magic. */ 2848 CSR_WRITE_4(sc, ALC_SRAM_RX_FIFO_LEN, 0x000002A0); 2849 CSR_WRITE_4(sc, ALC_SRAM_TX_FIFO_LEN, 0x00000100); 2850 CSR_WRITE_4(sc, ALC_SRAM_RX_FIFO_ADDR, 0x029F0000); 2851 CSR_WRITE_4(sc, ALC_SRAM_RD0_ADDR, 0x02BF02A0); 2852 CSR_WRITE_4(sc, ALC_SRAM_TX_FIFO_ADDR, 0x03BF02C0); 2853 CSR_WRITE_4(sc, ALC_SRAM_TD_ADDR, 0x03DF03C0); 2854 CSR_WRITE_4(sc, ALC_TXF_WATER_MARK, 0x00000000); 2855 CSR_WRITE_4(sc, ALC_RD_DMA_CFG, 0x00000000); 2856 } 2857 2858 /* Tell hardware that we're ready to load DMA blocks. */ 2859 CSR_WRITE_4(sc, ALC_DMA_BLOCK, DMA_BLOCK_LOAD); 2860 2861 /* Configure interrupt moderation timer. */ 2862 sc->alc_int_rx_mod = ALC_IM_RX_TIMER_DEFAULT; 2863 sc->alc_int_tx_mod = ALC_IM_TX_TIMER_DEFAULT; 2864 reg = ALC_USECS(sc->alc_int_rx_mod) << IM_TIMER_RX_SHIFT; 2865 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) 2866 reg |= ALC_USECS(sc->alc_int_tx_mod) << IM_TIMER_TX_SHIFT; 2867 CSR_WRITE_4(sc, ALC_IM_TIMER, reg); 2868 /* 2869 * We don't want to automatic interrupt clear as task queue 2870 * for the interrupt should know interrupt status. 2871 */ 2872 reg = CSR_READ_4(sc, ALC_MASTER_CFG); 2873 reg &= ~(MASTER_IM_RX_TIMER_ENB | MASTER_IM_TX_TIMER_ENB); 2874 reg |= MASTER_SA_TIMER_ENB; 2875 if (ALC_USECS(sc->alc_int_rx_mod) != 0) 2876 reg |= MASTER_IM_RX_TIMER_ENB; 2877 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0 && 2878 ALC_USECS(sc->alc_int_tx_mod) != 0) 2879 reg |= MASTER_IM_TX_TIMER_ENB; 2880 CSR_WRITE_4(sc, ALC_MASTER_CFG, reg); 2881 /* 2882 * Disable interrupt re-trigger timer. We don't want automatic 2883 * re-triggering of un-ACKed interrupts. 2884 */ 2885 CSR_WRITE_4(sc, ALC_INTR_RETRIG_TIMER, ALC_USECS(0)); 2886 /* Configure CMB. */ 2887 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 2888 CSR_WRITE_4(sc, ALC_CMB_TD_THRESH, ALC_TX_RING_CNT / 3); 2889 CSR_WRITE_4(sc, ALC_CMB_TX_TIMER, 2890 ALC_USECS(sc->alc_int_tx_mod)); 2891 } else { 2892 if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0) { 2893 CSR_WRITE_4(sc, ALC_CMB_TD_THRESH, 4); 2894 CSR_WRITE_4(sc, ALC_CMB_TX_TIMER, ALC_USECS(5000)); 2895 } else 2896 CSR_WRITE_4(sc, ALC_CMB_TX_TIMER, ALC_USECS(0)); 2897 } 2898 /* 2899 * Hardware can be configured to issue SMB interrupt based 2900 * on programmed interval. Since there is a callout that is 2901 * invoked for every hz in driver we use that instead of 2902 * relying on periodic SMB interrupt. 2903 */ 2904 CSR_WRITE_4(sc, ALC_SMB_STAT_TIMER, ALC_USECS(0)); 2905 /* Clear MAC statistics. */ 2906 alc_stats_clear(sc); 2907 2908 /* 2909 * Always use maximum frame size that controller can support. 2910 * Otherwise received frames that has larger frame length 2911 * than alc(4) MTU would be silently dropped in hardware. This 2912 * would make path-MTU discovery hard as sender wouldn't get 2913 * any responses from receiver. alc(4) supports 2914 * multi-fragmented frames on Rx path so it has no issue on 2915 * assembling fragmented frames. Using maximum frame size also 2916 * removes the need to reinitialize hardware when interface 2917 * MTU configuration was changed. 2918 * 2919 * Be conservative in what you do, be liberal in what you 2920 * accept from others - RFC 793. 2921 */ 2922 CSR_WRITE_4(sc, ALC_FRAME_SIZE, sc->alc_ident->max_framelen); 2923 2924 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 2925 /* Disable header split(?) */ 2926 CSR_WRITE_4(sc, ALC_HDS_CFG, 0); 2927 2928 /* Configure IPG/IFG parameters. */ 2929 CSR_WRITE_4(sc, ALC_IPG_IFG_CFG, 2930 ((IPG_IFG_IPGT_DEFAULT << IPG_IFG_IPGT_SHIFT) & 2931 IPG_IFG_IPGT_MASK) | 2932 ((IPG_IFG_MIFG_DEFAULT << IPG_IFG_MIFG_SHIFT) & 2933 IPG_IFG_MIFG_MASK) | 2934 ((IPG_IFG_IPG1_DEFAULT << IPG_IFG_IPG1_SHIFT) & 2935 IPG_IFG_IPG1_MASK) | 2936 ((IPG_IFG_IPG2_DEFAULT << IPG_IFG_IPG2_SHIFT) & 2937 IPG_IFG_IPG2_MASK)); 2938 /* Set parameters for half-duplex media. */ 2939 CSR_WRITE_4(sc, ALC_HDPX_CFG, 2940 ((HDPX_CFG_LCOL_DEFAULT << HDPX_CFG_LCOL_SHIFT) & 2941 HDPX_CFG_LCOL_MASK) | 2942 ((HDPX_CFG_RETRY_DEFAULT << HDPX_CFG_RETRY_SHIFT) & 2943 HDPX_CFG_RETRY_MASK) | HDPX_CFG_EXC_DEF_EN | 2944 ((HDPX_CFG_ABEBT_DEFAULT << HDPX_CFG_ABEBT_SHIFT) & 2945 HDPX_CFG_ABEBT_MASK) | 2946 ((HDPX_CFG_JAMIPG_DEFAULT << HDPX_CFG_JAMIPG_SHIFT) & 2947 HDPX_CFG_JAMIPG_MASK)); 2948 } 2949 2950 /* 2951 * Set TSO/checksum offload threshold. For frames that is 2952 * larger than this threshold, hardware wouldn't do 2953 * TSO/checksum offloading. 2954 */ 2955 reg = (sc->alc_ident->max_framelen >> TSO_OFFLOAD_THRESH_UNIT_SHIFT) & 2956 TSO_OFFLOAD_THRESH_MASK; 2957 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 2958 reg |= TSO_OFFLOAD_ERRLGPKT_DROP_ENB; 2959 CSR_WRITE_4(sc, ALC_TSO_OFFLOAD_THRESH, reg); 2960 /* Configure TxQ. */ 2961 reg = (alc_dma_burst[sc->alc_dma_rd_burst] << 2962 TXQ_CFG_TX_FIFO_BURST_SHIFT) & TXQ_CFG_TX_FIFO_BURST_MASK; 2963 if (sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8152_B || 2964 sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8152_B2) 2965 reg >>= 1; 2966 reg |= (TXQ_CFG_TD_BURST_DEFAULT << TXQ_CFG_TD_BURST_SHIFT) & 2967 TXQ_CFG_TD_BURST_MASK; 2968 reg |= TXQ_CFG_IP_OPTION_ENB | TXQ_CFG_8023_ENB; 2969 CSR_WRITE_4(sc, ALC_TXQ_CFG, reg | TXQ_CFG_ENHANCED_MODE); 2970 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 2971 reg = (TXQ_CFG_TD_BURST_DEFAULT << HQTD_CFG_Q1_BURST_SHIFT | 2972 TXQ_CFG_TD_BURST_DEFAULT << HQTD_CFG_Q2_BURST_SHIFT | 2973 TXQ_CFG_TD_BURST_DEFAULT << HQTD_CFG_Q3_BURST_SHIFT | 2974 HQTD_CFG_BURST_ENB); 2975 CSR_WRITE_4(sc, ALC_HQTD_CFG, reg); 2976 reg = WRR_PRI_RESTRICT_NONE; 2977 reg |= (WRR_PRI_DEFAULT << WRR_PRI0_SHIFT | 2978 WRR_PRI_DEFAULT << WRR_PRI1_SHIFT | 2979 WRR_PRI_DEFAULT << WRR_PRI2_SHIFT | 2980 WRR_PRI_DEFAULT << WRR_PRI3_SHIFT); 2981 CSR_WRITE_4(sc, ALC_WRR, reg); 2982 } else { 2983 /* Configure Rx free descriptor pre-fetching. */ 2984 CSR_WRITE_4(sc, ALC_RX_RD_FREE_THRESH, 2985 ((RX_RD_FREE_THRESH_HI_DEFAULT << 2986 RX_RD_FREE_THRESH_HI_SHIFT) & RX_RD_FREE_THRESH_HI_MASK) | 2987 ((RX_RD_FREE_THRESH_LO_DEFAULT << 2988 RX_RD_FREE_THRESH_LO_SHIFT) & RX_RD_FREE_THRESH_LO_MASK)); 2989 } 2990 2991 /* 2992 * Configure flow control parameters. 2993 * XON : 80% of Rx FIFO 2994 * XOFF : 30% of Rx FIFO 2995 */ 2996 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 2997 reg = CSR_READ_4(sc, ALC_SRAM_RX_FIFO_LEN); 2998 reg &= SRAM_RX_FIFO_LEN_MASK; 2999 reg *= 8; 3000 if (reg > 8 * 1024) 3001 reg -= RX_FIFO_PAUSE_816X_RSVD; 3002 else 3003 reg -= RX_BUF_SIZE_MAX; 3004 reg /= 8; 3005 CSR_WRITE_4(sc, ALC_RX_FIFO_PAUSE_THRESH, 3006 ((reg << RX_FIFO_PAUSE_THRESH_LO_SHIFT) & 3007 RX_FIFO_PAUSE_THRESH_LO_MASK) | 3008 (((RX_FIFO_PAUSE_816X_RSVD / 8) << 3009 RX_FIFO_PAUSE_THRESH_HI_SHIFT) & 3010 RX_FIFO_PAUSE_THRESH_HI_MASK)); 3011 } else if (sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8131 || 3012 sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8132) { 3013 reg = CSR_READ_4(sc, ALC_SRAM_RX_FIFO_LEN); 3014 rxf_hi = (reg * 8) / 10; 3015 rxf_lo = (reg * 3) / 10; 3016 CSR_WRITE_4(sc, ALC_RX_FIFO_PAUSE_THRESH, 3017 ((rxf_lo << RX_FIFO_PAUSE_THRESH_LO_SHIFT) & 3018 RX_FIFO_PAUSE_THRESH_LO_MASK) | 3019 ((rxf_hi << RX_FIFO_PAUSE_THRESH_HI_SHIFT) & 3020 RX_FIFO_PAUSE_THRESH_HI_MASK)); 3021 } 3022 3023 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 3024 /* Disable RSS until I understand L1C/L2C's RSS logic. */ 3025 CSR_WRITE_4(sc, ALC_RSS_IDT_TABLE0, 0); 3026 CSR_WRITE_4(sc, ALC_RSS_CPU, 0); 3027 } 3028 3029 /* Configure RxQ. */ 3030 reg = (RXQ_CFG_RD_BURST_DEFAULT << RXQ_CFG_RD_BURST_SHIFT) & 3031 RXQ_CFG_RD_BURST_MASK; 3032 reg |= RXQ_CFG_RSS_MODE_DIS; 3033 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 3034 reg |= (RXQ_CFG_816X_IDT_TBL_SIZE_DEFAULT << 3035 RXQ_CFG_816X_IDT_TBL_SIZE_SHIFT) & 3036 RXQ_CFG_816X_IDT_TBL_SIZE_MASK; 3037 if ((sc->alc_flags & ALC_FLAG_FASTETHER) == 0 && 3038 sc->alc_ident->deviceid != PCI_PRODUCT_ATTANSIC_AR8151_V2) 3039 reg |= RXQ_CFG_ASPM_THROUGHPUT_LIMIT_1M; 3040 CSR_WRITE_4(sc, ALC_RXQ_CFG, reg); 3041 3042 /* Configure DMA parameters. */ 3043 reg = DMA_CFG_OUT_ORDER | DMA_CFG_RD_REQ_PRI; 3044 reg |= sc->alc_rcb; 3045 if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0) 3046 reg |= DMA_CFG_CMB_ENB; 3047 if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0) 3048 reg |= DMA_CFG_SMB_ENB; 3049 else 3050 reg |= DMA_CFG_SMB_DIS; 3051 reg |= (sc->alc_dma_rd_burst & DMA_CFG_RD_BURST_MASK) << 3052 DMA_CFG_RD_BURST_SHIFT; 3053 reg |= (sc->alc_dma_wr_burst & DMA_CFG_WR_BURST_MASK) << 3054 DMA_CFG_WR_BURST_SHIFT; 3055 reg |= (DMA_CFG_RD_DELAY_CNT_DEFAULT << DMA_CFG_RD_DELAY_CNT_SHIFT) & 3056 DMA_CFG_RD_DELAY_CNT_MASK; 3057 reg |= (DMA_CFG_WR_DELAY_CNT_DEFAULT << DMA_CFG_WR_DELAY_CNT_SHIFT) & 3058 DMA_CFG_WR_DELAY_CNT_MASK; 3059 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 3060 switch (AR816X_REV(sc->alc_rev)) { 3061 case AR816X_REV_A0: 3062 case AR816X_REV_A1: 3063 reg |= DMA_CFG_RD_CHNL_SEL_1; 3064 break; 3065 case AR816X_REV_B0: 3066 /* FALLTHROUGH */ 3067 default: 3068 reg |= DMA_CFG_RD_CHNL_SEL_3; 3069 break; 3070 } 3071 } 3072 CSR_WRITE_4(sc, ALC_DMA_CFG, reg); 3073 3074 /* 3075 * Configure Tx/Rx MACs. 3076 * - Auto-padding for short frames. 3077 * - Enable CRC generation. 3078 * Actual reconfiguration of MAC for resolved speed/duplex 3079 * is followed after detection of link establishment. 3080 * AR813x/AR815x always does checksum computation regardless 3081 * of MAC_CFG_RXCSUM_ENB bit. Also the controller is known to 3082 * have bug in protocol field in Rx return structure so 3083 * these controllers can't handle fragmented frames. Disable 3084 * Rx checksum offloading until there is a newer controller 3085 * that has sane implementation. 3086 */ 3087 reg = MAC_CFG_TX_CRC_ENB | MAC_CFG_TX_AUTO_PAD | MAC_CFG_FULL_DUPLEX | 3088 ((MAC_CFG_PREAMBLE_DEFAULT << MAC_CFG_PREAMBLE_SHIFT) & 3089 MAC_CFG_PREAMBLE_MASK); 3090 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0 || 3091 sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8151 || 3092 sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8151_V2 || 3093 sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8152_B2) 3094 reg |= MAC_CFG_HASH_ALG_CRC32 | MAC_CFG_SPEED_MODE_SW; 3095 if ((sc->alc_flags & ALC_FLAG_FASTETHER) != 0) 3096 reg |= MAC_CFG_SPEED_10_100; 3097 else 3098 reg |= MAC_CFG_SPEED_1000; 3099 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 3100 3101 /* Set up the receive filter. */ 3102 alc_iff(sc); 3103 alc_rxvlan(sc); 3104 3105 /* Acknowledge all pending interrupts and clear it. */ 3106 CSR_WRITE_4(sc, ALC_INTR_MASK, ALC_INTRS); 3107 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0xFFFFFFFF); 3108 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0); 3109 3110 sc->alc_flags &= ~ALC_FLAG_LINK; 3111 /* Switch to the current media. */ 3112 mii = &sc->sc_miibus; 3113 mii_mediachg(mii); 3114 3115 callout_schedule(&sc->sc_tick_ch, hz); 3116 3117 ifp->if_flags |= IFF_RUNNING; 3118 ifp->if_flags &= ~IFF_OACTIVE; 3119 3120 return (0); 3121 } 3122 3123 static void 3124 alc_stop(struct ifnet *ifp, int disable) 3125 { 3126 struct alc_softc *sc = ifp->if_softc; 3127 struct alc_txdesc *txd; 3128 struct alc_rxdesc *rxd; 3129 uint32_t reg; 3130 int i; 3131 3132 callout_stop(&sc->sc_tick_ch); 3133 3134 /* 3135 * Mark the interface down and cancel the watchdog timer. 3136 */ 3137 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 3138 ifp->if_timer = 0; 3139 3140 sc->alc_flags &= ~ALC_FLAG_LINK; 3141 3142 alc_stats_update(sc); 3143 3144 mii_down(&sc->sc_miibus); 3145 3146 /* Disable interrupts. */ 3147 CSR_WRITE_4(sc, ALC_INTR_MASK, 0); 3148 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0xFFFFFFFF); 3149 3150 /* Disable DMA. */ 3151 reg = CSR_READ_4(sc, ALC_DMA_CFG); 3152 reg &= ~(DMA_CFG_CMB_ENB | DMA_CFG_SMB_ENB); 3153 reg |= DMA_CFG_SMB_DIS; 3154 CSR_WRITE_4(sc, ALC_DMA_CFG, reg); 3155 DELAY(1000); 3156 3157 /* Stop Rx/Tx MACs. */ 3158 alc_stop_mac(sc); 3159 3160 /* Disable interrupts which might be touched in taskq handler. */ 3161 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0xFFFFFFFF); 3162 3163 /* Disable L0s/L1s */ 3164 alc_aspm(sc, 0, IFM_UNKNOWN); 3165 3166 /* Reclaim Rx buffers that have been processed. */ 3167 if (sc->alc_cdata.alc_rxhead != NULL) 3168 m_freem(sc->alc_cdata.alc_rxhead); 3169 ALC_RXCHAIN_RESET(sc); 3170 /* 3171 * Free Tx/Rx mbufs still in the queues. 3172 */ 3173 for (i = 0; i < ALC_RX_RING_CNT; i++) { 3174 rxd = &sc->alc_cdata.alc_rxdesc[i]; 3175 if (rxd->rx_m != NULL) { 3176 bus_dmamap_sync(sc->sc_dmat, rxd->rx_dmamap, 0, 3177 rxd->rx_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 3178 bus_dmamap_unload(sc->sc_dmat, rxd->rx_dmamap); 3179 m_freem(rxd->rx_m); 3180 rxd->rx_m = NULL; 3181 } 3182 } 3183 for (i = 0; i < ALC_TX_RING_CNT; i++) { 3184 txd = &sc->alc_cdata.alc_txdesc[i]; 3185 if (txd->tx_m != NULL) { 3186 bus_dmamap_sync(sc->sc_dmat, txd->tx_dmamap, 0, 3187 txd->tx_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 3188 bus_dmamap_unload(sc->sc_dmat, txd->tx_dmamap); 3189 m_freem(txd->tx_m); 3190 txd->tx_m = NULL; 3191 } 3192 } 3193 } 3194 3195 static void 3196 alc_stop_mac(struct alc_softc *sc) 3197 { 3198 uint32_t reg; 3199 int i; 3200 3201 alc_stop_queue(sc); 3202 /* Disable Rx/Tx MAC. */ 3203 reg = CSR_READ_4(sc, ALC_MAC_CFG); 3204 if ((reg & (MAC_CFG_TX_ENB | MAC_CFG_RX_ENB)) != 0) { 3205 reg &= ~(MAC_CFG_TX_ENB | MAC_CFG_RX_ENB); 3206 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 3207 } 3208 for (i = ALC_TIMEOUT; i > 0; i--) { 3209 reg = CSR_READ_4(sc, ALC_IDLE_STATUS); 3210 if ((reg & (IDLE_STATUS_RXMAC | IDLE_STATUS_TXMAC)) == 0) 3211 break; 3212 DELAY(10); 3213 } 3214 if (i == 0) 3215 printf("%s: could not disable Rx/Tx MAC(0x%08x)!\n", 3216 device_xname(sc->sc_dev), reg); 3217 } 3218 3219 static void 3220 alc_start_queue(struct alc_softc *sc) 3221 { 3222 uint32_t qcfg[] = { 3223 0, 3224 RXQ_CFG_QUEUE0_ENB, 3225 RXQ_CFG_QUEUE0_ENB | RXQ_CFG_QUEUE1_ENB, 3226 RXQ_CFG_QUEUE0_ENB | RXQ_CFG_QUEUE1_ENB | RXQ_CFG_QUEUE2_ENB, 3227 RXQ_CFG_ENB 3228 }; 3229 uint32_t cfg; 3230 3231 /* Enable RxQ. */ 3232 cfg = CSR_READ_4(sc, ALC_RXQ_CFG); 3233 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 3234 cfg &= ~RXQ_CFG_ENB; 3235 cfg |= qcfg[1]; 3236 } else 3237 cfg |= RXQ_CFG_QUEUE0_ENB; 3238 CSR_WRITE_4(sc, ALC_RXQ_CFG, cfg); 3239 /* Enable TxQ. */ 3240 cfg = CSR_READ_4(sc, ALC_TXQ_CFG); 3241 cfg |= TXQ_CFG_ENB; 3242 CSR_WRITE_4(sc, ALC_TXQ_CFG, cfg); 3243 } 3244 3245 static void 3246 alc_stop_queue(struct alc_softc *sc) 3247 { 3248 uint32_t reg; 3249 int i; 3250 3251 /* Disable RxQ. */ 3252 reg = CSR_READ_4(sc, ALC_RXQ_CFG); 3253 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 3254 if ((reg & RXQ_CFG_ENB) != 0) { 3255 reg &= ~RXQ_CFG_ENB; 3256 CSR_WRITE_4(sc, ALC_RXQ_CFG, reg); 3257 } 3258 } else { 3259 if ((reg & RXQ_CFG_QUEUE0_ENB) != 0) { 3260 reg &= ~RXQ_CFG_QUEUE0_ENB; 3261 CSR_WRITE_4(sc, ALC_RXQ_CFG, reg); 3262 } 3263 } 3264 /* Disable TxQ. */ 3265 reg = CSR_READ_4(sc, ALC_TXQ_CFG); 3266 if ((reg & TXQ_CFG_ENB) != 0) { 3267 reg &= ~TXQ_CFG_ENB; 3268 CSR_WRITE_4(sc, ALC_TXQ_CFG, reg); 3269 } 3270 DELAY(40); 3271 for (i = ALC_TIMEOUT; i > 0; i--) { 3272 reg = CSR_READ_4(sc, ALC_IDLE_STATUS); 3273 if ((reg & (IDLE_STATUS_RXQ | IDLE_STATUS_TXQ)) == 0) 3274 break; 3275 DELAY(10); 3276 } 3277 if (i == 0) 3278 printf("%s: could not disable RxQ/TxQ (0x%08x)!\n", 3279 device_xname(sc->sc_dev), reg); 3280 } 3281 3282 static void 3283 alc_init_tx_ring(struct alc_softc *sc) 3284 { 3285 struct alc_ring_data *rd; 3286 struct alc_txdesc *txd; 3287 int i; 3288 3289 sc->alc_cdata.alc_tx_prod = 0; 3290 sc->alc_cdata.alc_tx_cons = 0; 3291 sc->alc_cdata.alc_tx_cnt = 0; 3292 3293 rd = &sc->alc_rdata; 3294 memset(rd->alc_tx_ring, 0, ALC_TX_RING_SZ); 3295 for (i = 0; i < ALC_TX_RING_CNT; i++) { 3296 txd = &sc->alc_cdata.alc_txdesc[i]; 3297 txd->tx_m = NULL; 3298 } 3299 3300 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_tx_ring_map, 0, 3301 sc->alc_cdata.alc_tx_ring_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 3302 } 3303 3304 static int 3305 alc_init_rx_ring(struct alc_softc *sc, bool init) 3306 { 3307 struct alc_ring_data *rd; 3308 struct alc_rxdesc *rxd; 3309 int i; 3310 3311 sc->alc_cdata.alc_rx_cons = ALC_RX_RING_CNT - 1; 3312 rd = &sc->alc_rdata; 3313 memset(rd->alc_rx_ring, 0, ALC_RX_RING_SZ); 3314 for (i = 0; i < ALC_RX_RING_CNT; i++) { 3315 rxd = &sc->alc_cdata.alc_rxdesc[i]; 3316 rxd->rx_m = NULL; 3317 rxd->rx_desc = &rd->alc_rx_ring[i]; 3318 if (alc_newbuf(sc, rxd, init) != 0) 3319 return (ENOBUFS); 3320 } 3321 3322 /* 3323 * Since controller does not update Rx descriptors, driver 3324 * does have to read Rx descriptors back so BUS_DMASYNC_PREWRITE 3325 * is enough to ensure coherence. 3326 */ 3327 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_rx_ring_map, 0, 3328 sc->alc_cdata.alc_rx_ring_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 3329 /* Let controller know availability of new Rx buffers. */ 3330 CSR_WRITE_4(sc, ALC_MBOX_RD0_PROD_IDX, sc->alc_cdata.alc_rx_cons); 3331 3332 return (0); 3333 } 3334 3335 static void 3336 alc_init_rr_ring(struct alc_softc *sc) 3337 { 3338 struct alc_ring_data *rd; 3339 3340 sc->alc_cdata.alc_rr_cons = 0; 3341 ALC_RXCHAIN_RESET(sc); 3342 3343 rd = &sc->alc_rdata; 3344 memset(rd->alc_rr_ring, 0, ALC_RR_RING_SZ); 3345 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_rr_ring_map, 0, 3346 sc->alc_cdata.alc_rr_ring_map->dm_mapsize, 3347 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3348 } 3349 3350 static void 3351 alc_init_cmb(struct alc_softc *sc) 3352 { 3353 struct alc_ring_data *rd; 3354 3355 rd = &sc->alc_rdata; 3356 memset(rd->alc_cmb, 0, ALC_CMB_SZ); 3357 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_cmb_map, 0, 3358 sc->alc_cdata.alc_cmb_map->dm_mapsize, 3359 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3360 } 3361 3362 static void 3363 alc_init_smb(struct alc_softc *sc) 3364 { 3365 struct alc_ring_data *rd; 3366 3367 rd = &sc->alc_rdata; 3368 memset(rd->alc_smb, 0, ALC_SMB_SZ); 3369 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_smb_map, 0, 3370 sc->alc_cdata.alc_smb_map->dm_mapsize, 3371 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3372 } 3373 3374 static void 3375 alc_rxvlan(struct alc_softc *sc) 3376 { 3377 uint32_t reg; 3378 3379 reg = CSR_READ_4(sc, ALC_MAC_CFG); 3380 if (sc->sc_ec.ec_capenable & ETHERCAP_VLAN_HWTAGGING) 3381 reg |= MAC_CFG_VLAN_TAG_STRIP; 3382 else 3383 reg &= ~MAC_CFG_VLAN_TAG_STRIP; 3384 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 3385 } 3386 3387 static void 3388 alc_iff(struct alc_softc *sc) 3389 { 3390 struct ethercom *ec = &sc->sc_ec; 3391 struct ifnet *ifp = &ec->ec_if; 3392 struct ether_multi *enm; 3393 struct ether_multistep step; 3394 uint32_t crc; 3395 uint32_t mchash[2]; 3396 uint32_t rxcfg; 3397 3398 rxcfg = CSR_READ_4(sc, ALC_MAC_CFG); 3399 rxcfg &= ~(MAC_CFG_ALLMULTI | MAC_CFG_BCAST | MAC_CFG_PROMISC); 3400 ifp->if_flags &= ~IFF_ALLMULTI; 3401 3402 /* 3403 * Always accept broadcast frames. 3404 */ 3405 rxcfg |= MAC_CFG_BCAST; 3406 3407 if (ifp->if_flags & IFF_PROMISC || ec->ec_multicnt > 0) { 3408 ifp->if_flags |= IFF_ALLMULTI; 3409 if (ifp->if_flags & IFF_PROMISC) 3410 rxcfg |= MAC_CFG_PROMISC; 3411 else 3412 rxcfg |= MAC_CFG_ALLMULTI; 3413 mchash[0] = mchash[1] = 0xFFFFFFFF; 3414 } else { 3415 /* Program new filter. */ 3416 memset(mchash, 0, sizeof(mchash)); 3417 3418 ETHER_FIRST_MULTI(step, ec, enm); 3419 while (enm != NULL) { 3420 crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 3421 mchash[crc >> 31] |= 1 << ((crc >> 26) & 0x1f); 3422 ETHER_NEXT_MULTI(step, enm); 3423 } 3424 } 3425 3426 CSR_WRITE_4(sc, ALC_MAR0, mchash[0]); 3427 CSR_WRITE_4(sc, ALC_MAR1, mchash[1]); 3428 CSR_WRITE_4(sc, ALC_MAC_CFG, rxcfg); 3429 } 3430 3431 MODULE(MODULE_CLASS_DRIVER, if_alc, "pci"); 3432 3433 #ifdef _MODULE 3434 #include "ioconf.c" 3435 #endif 3436 3437 static int 3438 if_alc_modcmd(modcmd_t cmd, void *opaque) 3439 { 3440 int error = 0; 3441 3442 switch (cmd) { 3443 case MODULE_CMD_INIT: 3444 #ifdef _MODULE 3445 error = config_init_component(cfdriver_ioconf_if_alc, 3446 cfattach_ioconf_if_alc, cfdata_ioconf_if_alc); 3447 #endif 3448 return error; 3449 case MODULE_CMD_FINI: 3450 #ifdef _MODULE 3451 error = config_fini_component(cfdriver_ioconf_if_alc, 3452 cfattach_ioconf_if_alc, cfdata_ioconf_if_alc); 3453 #endif 3454 return error; 3455 default: 3456 return ENOTTY; 3457 } 3458 } 3459
Indexes created Thu Sep 25 08:09:54 GMT 2025