if_alc.c revision 1.29
1 /* $NetBSD: if_alc.c,v 1.29 2018/12/09 11:14:02 jdolecek Exp $ */ 2 /* $OpenBSD: if_alc.c,v 1.1 2009/08/08 09:31:13 kevlo Exp $ */ 3 /*- 4 * Copyright (c) 2009, Pyun YongHyeon <yongari (at) FreeBSD.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice unmodified, this list of conditions, and the following 12 * disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 /* Driver for Atheros AR813x/AR815x PCIe Ethernet. */ 31 32 #ifdef _KERNEL_OPT 33 #include "vlan.h" 34 #endif 35 36 #include <sys/param.h> 37 #include <sys/proc.h> 38 #include <sys/endian.h> 39 #include <sys/systm.h> 40 #include <sys/types.h> 41 #include <sys/sockio.h> 42 #include <sys/mbuf.h> 43 #include <sys/queue.h> 44 #include <sys/kernel.h> 45 #include <sys/device.h> 46 #include <sys/callout.h> 47 #include <sys/socket.h> 48 #include <sys/module.h> 49 50 #include <sys/bus.h> 51 52 #include <net/bpf.h> 53 #include <net/if.h> 54 #include <net/if_dl.h> 55 #include <net/if_llc.h> 56 #include <net/if_media.h> 57 #include <net/if_ether.h> 58 59 #ifdef INET 60 #include <netinet/in.h> 61 #include <netinet/in_systm.h> 62 #include <netinet/in_var.h> 63 #include <netinet/ip.h> 64 #endif 65 66 #include <net/if_types.h> 67 #include <net/if_vlanvar.h> 68 69 #include <dev/mii/mii.h> 70 #include <dev/mii/miivar.h> 71 72 #include <dev/pci/pcireg.h> 73 #include <dev/pci/pcivar.h> 74 #include <dev/pci/pcidevs.h> 75 76 #include <dev/pci/if_alcreg.h> 77 78 /* 79 * Devices supported by this driver. 80 */ 81 static struct alc_ident alc_ident_table[] = { 82 { PCI_VENDOR_ATTANSIC, PCI_PRODUCT_ATTANSIC_AR8131, 9 * 1024, 83 "Atheros AR8131 PCIe Gigabit Ethernet" }, 84 { PCI_VENDOR_ATTANSIC, PCI_PRODUCT_ATTANSIC_AR8132, 9 * 1024, 85 "Atheros AR8132 PCIe Fast Ethernet" }, 86 { PCI_VENDOR_ATTANSIC, PCI_PRODUCT_ATTANSIC_AR8151, 6 * 1024, 87 "Atheros AR8151 v1.0 PCIe Gigabit Ethernet" }, 88 { PCI_VENDOR_ATTANSIC, PCI_PRODUCT_ATTANSIC_AR8151_V2, 6 * 1024, 89 "Atheros AR8151 v2.0 PCIe Gigabit Ethernet" }, 90 { PCI_VENDOR_ATTANSIC, PCI_PRODUCT_ATTANSIC_AR8152_B, 6 * 1024, 91 "Atheros AR8152 v1.1 PCIe Fast Ethernet" }, 92 { PCI_VENDOR_ATTANSIC, PCI_PRODUCT_ATTANSIC_AR8152_B2, 6 * 1024, 93 "Atheros AR8152 v2.0 PCIe Fast Ethernet" }, 94 { PCI_VENDOR_ATTANSIC, PCI_PRODUCT_ATTANSIC_AR8161, 9 * 1024, 95 "Atheros AR8161 PCIe Gigabit Ethernet" }, 96 { PCI_VENDOR_ATTANSIC, PCI_PRODUCT_ATTANSIC_AR8162, 9 * 1024, 97 "Atheros AR8162 PCIe Fast Ethernet" }, 98 { PCI_VENDOR_ATTANSIC, PCI_PRODUCT_ATTANSIC_AR8171, 9 * 1024, 99 "Atheros AR8171 PCIe Gigabit Ethernet" }, 100 { PCI_VENDOR_ATTANSIC, PCI_PRODUCT_ATTANSIC_AR8172, 9 * 1024, 101 "Atheros AR8172 PCIe Fast Ethernet" }, 102 { PCI_VENDOR_ATTANSIC, PCI_PRODUCT_ATTANSIC_E2200, 9 * 1024, 103 "Killer E2200 Gigabit Ethernet" }, 104 { 0, 0, 0, NULL }, 105 }; 106 107 static int alc_match(device_t, cfdata_t, void *); 108 static void alc_attach(device_t, device_t, void *); 109 static int alc_detach(device_t, int); 110 111 static int alc_init(struct ifnet *); 112 static int alc_init_backend(struct ifnet *, bool); 113 static void alc_start(struct ifnet *); 114 static int alc_ioctl(struct ifnet *, u_long, void *); 115 static void alc_watchdog(struct ifnet *); 116 static int alc_mediachange(struct ifnet *); 117 static void alc_mediastatus(struct ifnet *, struct ifmediareq *); 118 119 static void alc_aspm(struct alc_softc *, int, int); 120 static void alc_aspm_813x(struct alc_softc *, int); 121 static void alc_aspm_816x(struct alc_softc *, int); 122 static void alc_disable_l0s_l1(struct alc_softc *); 123 static int alc_dma_alloc(struct alc_softc *); 124 static void alc_dma_free(struct alc_softc *); 125 static void alc_dsp_fixup(struct alc_softc *, int); 126 static int alc_encap(struct alc_softc *, struct mbuf **); 127 static struct alc_ident * 128 alc_find_ident(struct pci_attach_args *); 129 static void alc_get_macaddr(struct alc_softc *); 130 static void alc_get_macaddr_813x(struct alc_softc *); 131 static void alc_get_macaddr_816x(struct alc_softc *); 132 static void alc_get_macaddr_par(struct alc_softc *); 133 static void alc_init_cmb(struct alc_softc *); 134 static void alc_init_rr_ring(struct alc_softc *); 135 static int alc_init_rx_ring(struct alc_softc *, bool); 136 static void alc_init_smb(struct alc_softc *); 137 static void alc_init_tx_ring(struct alc_softc *); 138 static int alc_intr(void *); 139 static void alc_mac_config(struct alc_softc *); 140 static uint32_t alc_mii_readreg_813x(struct alc_softc *, int, int); 141 static uint32_t alc_mii_readreg_816x(struct alc_softc *, int, int); 142 static void alc_mii_writereg_813x(struct alc_softc *, int, int, int); 143 static void alc_mii_writereg_816x(struct alc_softc *, int, int, int); 144 static int alc_miibus_readreg(device_t, int, int); 145 static void alc_miibus_statchg(struct ifnet *); 146 static void alc_miibus_writereg(device_t, int, int, int); 147 static uint32_t alc_miidbg_readreg(struct alc_softc *, int); 148 static void alc_miidbg_writereg(struct alc_softc *, int, int); 149 static uint32_t alc_miiext_readreg(struct alc_softc *, int, int); 150 static uint32_t alc_miiext_writereg(struct alc_softc *, int, int, int); 151 static int alc_newbuf(struct alc_softc *, struct alc_rxdesc *, bool); 152 static void alc_phy_down(struct alc_softc *); 153 static void alc_phy_reset(struct alc_softc *); 154 static void alc_phy_reset_813x(struct alc_softc *); 155 static void alc_phy_reset_816x(struct alc_softc *); 156 static void alc_reset(struct alc_softc *); 157 static void alc_rxeof(struct alc_softc *, struct rx_rdesc *); 158 static int alc_rxintr(struct alc_softc *); 159 static void alc_iff(struct alc_softc *); 160 static void alc_rxvlan(struct alc_softc *); 161 static void alc_start_queue(struct alc_softc *); 162 static void alc_stats_clear(struct alc_softc *); 163 static void alc_stats_update(struct alc_softc *); 164 static void alc_stop(struct ifnet *, int); 165 static void alc_stop_mac(struct alc_softc *); 166 static void alc_stop_queue(struct alc_softc *); 167 static void alc_tick(void *); 168 static void alc_txeof(struct alc_softc *); 169 170 uint32_t alc_dma_burst[] = { 128, 256, 512, 1024, 2048, 4096, 0 }; 171 172 CFATTACH_DECL_NEW(alc, sizeof(struct alc_softc), 173 alc_match, alc_attach, alc_detach, NULL); 174 175 int alcdebug = 0; 176 #define DPRINTF(x) do { if (alcdebug) printf x; } while (0) 177 178 #define ETHER_ALIGN 2 179 #define ALC_CSUM_FEATURES (M_CSUM_TCPv4 | M_CSUM_UDPv4) 180 181 static int 182 alc_miibus_readreg(device_t dev, int phy, int reg) 183 { 184 struct alc_softc *sc = device_private(dev); 185 int v; 186 187 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 188 v = alc_mii_readreg_816x(sc, phy, reg); 189 else 190 v = alc_mii_readreg_813x(sc, phy, reg); 191 return (v); 192 } 193 194 static uint32_t 195 alc_mii_readreg_813x(struct alc_softc *sc, int phy, int reg) 196 { 197 uint32_t v; 198 int i; 199 200 if (phy != sc->alc_phyaddr) 201 return (0); 202 203 /* 204 * For AR8132 fast ethernet controller, do not report 1000baseT 205 * capability to mii(4). Even though AR8132 uses the same 206 * model/revision number of F1 gigabit PHY, the PHY has no 207 * ability to establish 1000baseT link. 208 */ 209 if ((sc->alc_flags & ALC_FLAG_FASTETHER) != 0 && 210 reg == MII_EXTSR) 211 return 0; 212 213 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ | 214 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); 215 for (i = ALC_PHY_TIMEOUT; i > 0; i--) { 216 DELAY(5); 217 v = CSR_READ_4(sc, ALC_MDIO); 218 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) 219 break; 220 } 221 222 if (i == 0) { 223 printf("%s: phy read timeout: phy %d, reg %d\n", 224 device_xname(sc->sc_dev), phy, reg); 225 return (0); 226 } 227 228 return ((v & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT); 229 } 230 231 static uint32_t 232 alc_mii_readreg_816x(struct alc_softc *sc, int phy, int reg) 233 { 234 uint32_t clk, v; 235 int i; 236 237 if (phy != sc->alc_phyaddr) 238 return (0); 239 240 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) 241 clk = MDIO_CLK_25_128; 242 else 243 clk = MDIO_CLK_25_4; 244 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ | 245 MDIO_SUP_PREAMBLE | clk | MDIO_REG_ADDR(reg)); 246 for (i = ALC_PHY_TIMEOUT; i > 0; i--) { 247 DELAY(5); 248 v = CSR_READ_4(sc, ALC_MDIO); 249 if ((v & MDIO_OP_BUSY) == 0) 250 break; 251 } 252 253 if (i == 0) { 254 printf("%s: phy read timeout: phy %d, reg %d\n", 255 device_xname(sc->sc_dev), phy, reg); 256 return (0); 257 } 258 259 return ((v & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT); 260 } 261 262 static void 263 alc_miibus_writereg(device_t dev, int phy, int reg, int val) 264 { 265 struct alc_softc *sc = device_private(dev); 266 267 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 268 alc_mii_writereg_816x(sc, phy, reg, val); 269 else 270 alc_mii_writereg_813x(sc, phy, reg, val); 271 272 return; 273 } 274 275 static void 276 alc_mii_writereg_813x(struct alc_softc *sc, int phy, int reg, int val) 277 { 278 uint32_t v; 279 int i; 280 281 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE | 282 (val & MDIO_DATA_MASK) << MDIO_DATA_SHIFT | 283 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); 284 for (i = ALC_PHY_TIMEOUT; i > 0; i--) { 285 DELAY(5); 286 v = CSR_READ_4(sc, ALC_MDIO); 287 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) 288 break; 289 } 290 291 if (i == 0) 292 printf("%s: phy write timeout: phy %d, reg %d\n", 293 device_xname(sc->sc_dev), phy, reg); 294 295 return; 296 } 297 298 static void 299 alc_mii_writereg_816x(struct alc_softc *sc, int phy, int reg, int val) 300 { 301 uint32_t clk, v; 302 int i; 303 304 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) 305 clk = MDIO_CLK_25_128; 306 else 307 clk = MDIO_CLK_25_4; 308 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE | 309 ((val & MDIO_DATA_MASK) << MDIO_DATA_SHIFT) | MDIO_REG_ADDR(reg) | 310 MDIO_SUP_PREAMBLE | clk); 311 for (i = ALC_PHY_TIMEOUT; i > 0; i--) { 312 DELAY(5); 313 v = CSR_READ_4(sc, ALC_MDIO); 314 if ((v & MDIO_OP_BUSY) == 0) 315 break; 316 } 317 318 if (i == 0) 319 printf("%s: phy write timeout: phy %d, reg %d\n", 320 device_xname(sc->sc_dev), phy, reg); 321 322 return; 323 } 324 325 static void 326 alc_miibus_statchg(struct ifnet *ifp) 327 { 328 struct alc_softc *sc = ifp->if_softc; 329 struct mii_data *mii = &sc->sc_miibus; 330 uint32_t reg; 331 332 if ((ifp->if_flags & IFF_RUNNING) == 0) 333 return; 334 335 sc->alc_flags &= ~ALC_FLAG_LINK; 336 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 337 (IFM_ACTIVE | IFM_AVALID)) { 338 switch (IFM_SUBTYPE(mii->mii_media_active)) { 339 case IFM_10_T: 340 case IFM_100_TX: 341 sc->alc_flags |= ALC_FLAG_LINK; 342 break; 343 case IFM_1000_T: 344 if ((sc->alc_flags & ALC_FLAG_FASTETHER) == 0) 345 sc->alc_flags |= ALC_FLAG_LINK; 346 break; 347 default: 348 break; 349 } 350 } 351 /* Stop Rx/Tx MACs. */ 352 alc_stop_mac(sc); 353 354 /* Program MACs with resolved speed/duplex/flow-control. */ 355 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) { 356 alc_start_queue(sc); 357 alc_mac_config(sc); 358 /* Re-enable Tx/Rx MACs. */ 359 reg = CSR_READ_4(sc, ALC_MAC_CFG); 360 reg |= MAC_CFG_TX_ENB | MAC_CFG_RX_ENB; 361 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 362 } 363 alc_aspm(sc, 0, IFM_SUBTYPE(mii->mii_media_active)); 364 alc_dsp_fixup(sc, IFM_SUBTYPE(mii->mii_media_active)); 365 } 366 367 static uint32_t 368 alc_miidbg_readreg(struct alc_softc *sc, int reg) 369 { 370 371 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, ALC_MII_DBG_ADDR, 372 reg); 373 return (alc_miibus_readreg(sc->sc_dev, sc->alc_phyaddr, 374 ALC_MII_DBG_DATA)); 375 } 376 377 static void 378 alc_miidbg_writereg(struct alc_softc *sc, int reg, int val) 379 { 380 381 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, ALC_MII_DBG_ADDR, 382 reg); 383 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, ALC_MII_DBG_DATA, val); 384 385 return; 386 } 387 388 static uint32_t 389 alc_miiext_readreg(struct alc_softc *sc, int devaddr, int reg) 390 { 391 uint32_t clk, v; 392 int i; 393 394 CSR_WRITE_4(sc, ALC_EXT_MDIO, EXT_MDIO_REG(reg) | 395 EXT_MDIO_DEVADDR(devaddr)); 396 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) 397 clk = MDIO_CLK_25_128; 398 else 399 clk = MDIO_CLK_25_4; 400 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ | 401 MDIO_SUP_PREAMBLE | clk | MDIO_MODE_EXT); 402 for (i = ALC_PHY_TIMEOUT; i > 0; i--) { 403 DELAY(5); 404 v = CSR_READ_4(sc, ALC_MDIO); 405 if ((v & MDIO_OP_BUSY) == 0) 406 break; 407 } 408 409 if (i == 0) { 410 printf("%s: phy ext read timeout: %d\n", 411 device_xname(sc->sc_dev), reg); 412 return (0); 413 } 414 415 return ((v & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT); 416 } 417 418 static uint32_t 419 alc_miiext_writereg(struct alc_softc *sc, int devaddr, int reg, int val) 420 { 421 uint32_t clk, v; 422 int i; 423 424 CSR_WRITE_4(sc, ALC_EXT_MDIO, EXT_MDIO_REG(reg) | 425 EXT_MDIO_DEVADDR(devaddr)); 426 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) 427 clk = MDIO_CLK_25_128; 428 else 429 clk = MDIO_CLK_25_4; 430 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE | 431 ((val & MDIO_DATA_MASK) << MDIO_DATA_SHIFT) | 432 MDIO_SUP_PREAMBLE | clk | MDIO_MODE_EXT); 433 for (i = ALC_PHY_TIMEOUT; i > 0; i--) { 434 DELAY(5); 435 v = CSR_READ_4(sc, ALC_MDIO); 436 if ((v & MDIO_OP_BUSY) == 0) 437 break; 438 } 439 440 if (i == 0) { 441 printf("%s: phy ext write timeout: reg %d\n", 442 device_xname(sc->sc_dev), reg); 443 return (0); 444 } 445 446 return (0); 447 } 448 449 static void 450 alc_dsp_fixup(struct alc_softc *sc, int media) 451 { 452 uint16_t agc, len, val; 453 454 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 455 return; 456 if (AR816X_REV(sc->alc_rev) >= AR816X_REV_C0) 457 return; 458 459 /* 460 * Vendor PHY magic. 461 * 1000BT/AZ, wrong cable length 462 */ 463 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) { 464 len = alc_miiext_readreg(sc, MII_EXT_PCS, MII_EXT_CLDCTL6); 465 len = (len >> EXT_CLDCTL6_CAB_LEN_SHIFT) & 466 EXT_CLDCTL6_CAB_LEN_MASK; 467 /* XXX: used to be (alc >> shift) & mask which is 0 */ 468 agc = alc_miidbg_readreg(sc, MII_DBG_AGC) & DBG_AGC_2_VGA_MASK; 469 agc >>= DBG_AGC_2_VGA_SHIFT; 470 if ((media == IFM_1000_T && len > EXT_CLDCTL6_CAB_LEN_SHORT1G && 471 agc > DBG_AGC_LONG1G_LIMT) || 472 (media == IFM_100_TX && len > DBG_AGC_LONG100M_LIMT && 473 agc > DBG_AGC_LONG1G_LIMT)) { 474 alc_miidbg_writereg(sc, MII_DBG_AZ_ANADECT, 475 DBG_AZ_ANADECT_LONG); 476 val = alc_miiext_readreg(sc, MII_EXT_ANEG, 477 MII_EXT_ANEG_AFE); 478 val |= ANEG_AFEE_10BT_100M_TH; 479 alc_miiext_writereg(sc, MII_EXT_ANEG, MII_EXT_ANEG_AFE, 480 val); 481 } else { 482 alc_miidbg_writereg(sc, MII_DBG_AZ_ANADECT, 483 DBG_AZ_ANADECT_DEFAULT); 484 val = alc_miiext_readreg(sc, MII_EXT_ANEG, 485 MII_EXT_ANEG_AFE); 486 val &= ~ANEG_AFEE_10BT_100M_TH; 487 alc_miiext_writereg(sc, MII_EXT_ANEG, MII_EXT_ANEG_AFE, 488 val); 489 } 490 if ((sc->alc_flags & ALC_FLAG_LINK_WAR) != 0 && 491 AR816X_REV(sc->alc_rev) == AR816X_REV_B0) { 492 if (media == IFM_1000_T) { 493 /* 494 * Giga link threshold, raise the tolerance of 495 * noise 50%. 496 */ 497 val = alc_miidbg_readreg(sc, MII_DBG_MSE20DB); 498 val &= ~DBG_MSE20DB_TH_MASK; 499 val |= (DBG_MSE20DB_TH_HI << 500 DBG_MSE20DB_TH_SHIFT); 501 alc_miidbg_writereg(sc, MII_DBG_MSE20DB, val); 502 } else if (media == IFM_100_TX) 503 alc_miidbg_writereg(sc, MII_DBG_MSE16DB, 504 DBG_MSE16DB_UP); 505 } 506 } else { 507 val = alc_miiext_readreg(sc, MII_EXT_ANEG, MII_EXT_ANEG_AFE); 508 val &= ~ANEG_AFEE_10BT_100M_TH; 509 alc_miiext_writereg(sc, MII_EXT_ANEG, MII_EXT_ANEG_AFE, val); 510 if ((sc->alc_flags & ALC_FLAG_LINK_WAR) != 0 && 511 AR816X_REV(sc->alc_rev) == AR816X_REV_B0) { 512 alc_miidbg_writereg(sc, MII_DBG_MSE16DB, 513 DBG_MSE16DB_DOWN); 514 val = alc_miidbg_readreg(sc, MII_DBG_MSE20DB); 515 val &= ~DBG_MSE20DB_TH_MASK; 516 val |= (DBG_MSE20DB_TH_DEFAULT << DBG_MSE20DB_TH_SHIFT); 517 alc_miidbg_writereg(sc, MII_DBG_MSE20DB, val); 518 } 519 } 520 } 521 522 static void 523 alc_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 524 { 525 struct alc_softc *sc = ifp->if_softc; 526 struct mii_data *mii = &sc->sc_miibus; 527 528 if ((ifp->if_flags & IFF_UP) == 0) 529 return; 530 531 mii_pollstat(mii); 532 ifmr->ifm_status = mii->mii_media_status; 533 ifmr->ifm_active = mii->mii_media_active; 534 } 535 536 static int 537 alc_mediachange(struct ifnet *ifp) 538 { 539 struct alc_softc *sc = ifp->if_softc; 540 struct mii_data *mii = &sc->sc_miibus; 541 int error; 542 543 if (mii->mii_instance != 0) { 544 struct mii_softc *miisc; 545 546 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 547 mii_phy_reset(miisc); 548 } 549 error = mii_mediachg(mii); 550 551 return (error); 552 } 553 554 static struct alc_ident * 555 alc_find_ident(struct pci_attach_args *pa) 556 { 557 struct alc_ident *ident; 558 uint16_t vendor, devid; 559 560 vendor = PCI_VENDOR(pa->pa_id); 561 devid = PCI_PRODUCT(pa->pa_id); 562 for (ident = alc_ident_table; ident->name != NULL; ident++) { 563 if (vendor == ident->vendorid && devid == ident->deviceid) 564 return (ident); 565 } 566 567 return (NULL); 568 } 569 570 static int 571 alc_match(device_t dev, cfdata_t match, void *aux) 572 { 573 struct pci_attach_args *pa = aux; 574 575 return alc_find_ident(pa) != NULL; 576 } 577 578 static void 579 alc_get_macaddr(struct alc_softc *sc) 580 { 581 582 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 583 alc_get_macaddr_816x(sc); 584 else 585 alc_get_macaddr_813x(sc); 586 } 587 588 static void 589 alc_get_macaddr_813x(struct alc_softc *sc) 590 { 591 uint32_t opt; 592 uint16_t val; 593 int eeprom, i; 594 595 eeprom = 0; 596 opt = CSR_READ_4(sc, ALC_OPT_CFG); 597 if ((CSR_READ_4(sc, ALC_MASTER_CFG) & MASTER_OTP_SEL) != 0 && 598 (CSR_READ_4(sc, ALC_TWSI_DEBUG) & TWSI_DEBUG_DEV_EXIST) != 0) { 599 /* 600 * EEPROM found, let TWSI reload EEPROM configuration. 601 * This will set ethernet address of controller. 602 */ 603 eeprom++; 604 switch (sc->alc_ident->deviceid) { 605 case PCI_PRODUCT_ATTANSIC_AR8131: 606 case PCI_PRODUCT_ATTANSIC_AR8132: 607 if ((opt & OPT_CFG_CLK_ENB) == 0) { 608 opt |= OPT_CFG_CLK_ENB; 609 CSR_WRITE_4(sc, ALC_OPT_CFG, opt); 610 CSR_READ_4(sc, ALC_OPT_CFG); 611 DELAY(1000); 612 } 613 break; 614 case PCI_PRODUCT_ATTANSIC_AR8151: 615 case PCI_PRODUCT_ATTANSIC_AR8151_V2: 616 case PCI_PRODUCT_ATTANSIC_AR8152_B: 617 case PCI_PRODUCT_ATTANSIC_AR8152_B2: 618 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 619 ALC_MII_DBG_ADDR, 0x00); 620 val = alc_miibus_readreg(sc->sc_dev, sc->alc_phyaddr, 621 ALC_MII_DBG_DATA); 622 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 623 ALC_MII_DBG_DATA, val & 0xFF7F); 624 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 625 ALC_MII_DBG_ADDR, 0x3B); 626 val = alc_miibus_readreg(sc->sc_dev, sc->alc_phyaddr, 627 ALC_MII_DBG_DATA); 628 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 629 ALC_MII_DBG_DATA, val | 0x0008); 630 DELAY(20); 631 break; 632 } 633 634 CSR_WRITE_4(sc, ALC_LTSSM_ID_CFG, 635 CSR_READ_4(sc, ALC_LTSSM_ID_CFG) & ~LTSSM_ID_WRO_ENB); 636 CSR_WRITE_4(sc, ALC_WOL_CFG, 0); 637 CSR_READ_4(sc, ALC_WOL_CFG); 638 639 CSR_WRITE_4(sc, ALC_TWSI_CFG, CSR_READ_4(sc, ALC_TWSI_CFG) | 640 TWSI_CFG_SW_LD_START); 641 for (i = 100; i > 0; i--) { 642 DELAY(1000); 643 if ((CSR_READ_4(sc, ALC_TWSI_CFG) & 644 TWSI_CFG_SW_LD_START) == 0) 645 break; 646 } 647 if (i == 0) 648 printf("%s: reloading EEPROM timeout!\n", 649 device_xname(sc->sc_dev)); 650 } else { 651 if (alcdebug) 652 printf("%s: EEPROM not found!\n", device_xname(sc->sc_dev)); 653 } 654 if (eeprom != 0) { 655 switch (sc->alc_ident->deviceid) { 656 case PCI_PRODUCT_ATTANSIC_AR8131: 657 case PCI_PRODUCT_ATTANSIC_AR8132: 658 if ((opt & OPT_CFG_CLK_ENB) != 0) { 659 opt &= ~OPT_CFG_CLK_ENB; 660 CSR_WRITE_4(sc, ALC_OPT_CFG, opt); 661 CSR_READ_4(sc, ALC_OPT_CFG); 662 DELAY(1000); 663 } 664 break; 665 case PCI_PRODUCT_ATTANSIC_AR8151: 666 case PCI_PRODUCT_ATTANSIC_AR8151_V2: 667 case PCI_PRODUCT_ATTANSIC_AR8152_B: 668 case PCI_PRODUCT_ATTANSIC_AR8152_B2: 669 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 670 ALC_MII_DBG_ADDR, 0x00); 671 val = alc_miibus_readreg(sc->sc_dev, sc->alc_phyaddr, 672 ALC_MII_DBG_DATA); 673 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 674 ALC_MII_DBG_DATA, val | 0x0080); 675 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 676 ALC_MII_DBG_ADDR, 0x3B); 677 val = alc_miibus_readreg(sc->sc_dev, sc->alc_phyaddr, 678 ALC_MII_DBG_DATA); 679 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 680 ALC_MII_DBG_DATA, val & 0xFFF7); 681 DELAY(20); 682 break; 683 } 684 } 685 686 alc_get_macaddr_par(sc); 687 } 688 689 static void 690 alc_get_macaddr_816x(struct alc_softc *sc) 691 { 692 uint32_t reg; 693 int i, reloaded; 694 695 reloaded = 0; 696 /* Try to reload station address via TWSI. */ 697 for (i = 100; i > 0; i--) { 698 reg = CSR_READ_4(sc, ALC_SLD); 699 if ((reg & (SLD_PROGRESS | SLD_START)) == 0) 700 break; 701 DELAY(1000); 702 } 703 if (i != 0) { 704 CSR_WRITE_4(sc, ALC_SLD, reg | SLD_START); 705 for (i = 100; i > 0; i--) { 706 DELAY(1000); 707 reg = CSR_READ_4(sc, ALC_SLD); 708 if ((reg & SLD_START) == 0) 709 break; 710 } 711 if (i != 0) 712 reloaded++; 713 else if (alcdebug) 714 printf("%s: reloading station address via TWSI timed out!\n", 715 device_xname(sc->sc_dev)); 716 } 717 718 /* Try to reload station address from EEPROM or FLASH. */ 719 if (reloaded == 0) { 720 reg = CSR_READ_4(sc, ALC_EEPROM_LD); 721 if ((reg & (EEPROM_LD_EEPROM_EXIST | 722 EEPROM_LD_FLASH_EXIST)) != 0) { 723 for (i = 100; i > 0; i--) { 724 reg = CSR_READ_4(sc, ALC_EEPROM_LD); 725 if ((reg & (EEPROM_LD_PROGRESS | 726 EEPROM_LD_START)) == 0) 727 break; 728 DELAY(1000); 729 } 730 if (i != 0) { 731 CSR_WRITE_4(sc, ALC_EEPROM_LD, reg | 732 EEPROM_LD_START); 733 for (i = 100; i > 0; i--) { 734 DELAY(1000); 735 reg = CSR_READ_4(sc, ALC_EEPROM_LD); 736 if ((reg & EEPROM_LD_START) == 0) 737 break; 738 } 739 } else if (alcdebug) 740 printf("%s: reloading EEPROM/FLASH timed out!\n", 741 device_xname(sc->sc_dev)); 742 } 743 } 744 745 alc_get_macaddr_par(sc); 746 } 747 748 749 static void 750 alc_get_macaddr_par(struct alc_softc *sc) 751 { 752 uint32_t ea[2]; 753 754 ea[0] = CSR_READ_4(sc, ALC_PAR0); 755 ea[1] = CSR_READ_4(sc, ALC_PAR1); 756 sc->alc_eaddr[0] = (ea[1] >> 8) & 0xFF; 757 sc->alc_eaddr[1] = (ea[1] >> 0) & 0xFF; 758 sc->alc_eaddr[2] = (ea[0] >> 24) & 0xFF; 759 sc->alc_eaddr[3] = (ea[0] >> 16) & 0xFF; 760 sc->alc_eaddr[4] = (ea[0] >> 8) & 0xFF; 761 sc->alc_eaddr[5] = (ea[0] >> 0) & 0xFF; 762 } 763 764 static void 765 alc_disable_l0s_l1(struct alc_softc *sc) 766 { 767 uint32_t pmcfg; 768 769 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 770 /* Another magic from vendor. */ 771 pmcfg = CSR_READ_4(sc, ALC_PM_CFG); 772 pmcfg &= ~(PM_CFG_L1_ENTRY_TIMER_MASK | PM_CFG_CLK_SWH_L1 | 773 PM_CFG_ASPM_L0S_ENB | PM_CFG_ASPM_L1_ENB | 774 PM_CFG_MAC_ASPM_CHK | PM_CFG_SERDES_PD_EX_L1); 775 pmcfg |= PM_CFG_SERDES_BUDS_RX_L1_ENB | 776 PM_CFG_SERDES_PLL_L1_ENB | PM_CFG_SERDES_L1_ENB; 777 CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg); 778 } 779 } 780 781 static void 782 alc_phy_reset(struct alc_softc *sc) 783 { 784 785 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 786 alc_phy_reset_816x(sc); 787 else 788 alc_phy_reset_813x(sc); 789 } 790 791 static void 792 alc_phy_reset_813x(struct alc_softc *sc) 793 { 794 uint16_t data; 795 796 /* Reset magic from Linux. */ 797 CSR_WRITE_2(sc, ALC_GPHY_CFG, GPHY_CFG_SEL_ANA_RESET); 798 CSR_READ_2(sc, ALC_GPHY_CFG); 799 DELAY(10 * 1000); 800 801 CSR_WRITE_2(sc, ALC_GPHY_CFG, GPHY_CFG_EXT_RESET | 802 GPHY_CFG_SEL_ANA_RESET); 803 CSR_READ_2(sc, ALC_GPHY_CFG); 804 DELAY(10 * 1000); 805 806 /* DSP fixup, Vendor magic. */ 807 if (sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8152_B) { 808 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 809 ALC_MII_DBG_ADDR, 0x000A); 810 data = alc_miibus_readreg(sc->sc_dev, sc->alc_phyaddr, 811 ALC_MII_DBG_DATA); 812 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 813 ALC_MII_DBG_DATA, data & 0xDFFF); 814 } 815 if (sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8151 || 816 sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8151_V2 || 817 sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8152_B || 818 sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8152_B2) { 819 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 820 ALC_MII_DBG_ADDR, 0x003B); 821 data = alc_miibus_readreg(sc->sc_dev, sc->alc_phyaddr, 822 ALC_MII_DBG_DATA); 823 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 824 ALC_MII_DBG_DATA, data & 0xFFF7); 825 DELAY(20 * 1000); 826 } 827 if (sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8151) { 828 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 829 ALC_MII_DBG_ADDR, 0x0029); 830 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 831 ALC_MII_DBG_DATA, 0x929D); 832 } 833 if (sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8131 || 834 sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8132 || 835 sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8151_V2 || 836 sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8152_B2) { 837 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 838 ALC_MII_DBG_ADDR, 0x0029); 839 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 840 ALC_MII_DBG_DATA, 0xB6DD); 841 } 842 843 /* Load DSP codes, vendor magic. */ 844 data = ANA_LOOP_SEL_10BT | ANA_EN_MASK_TB | ANA_EN_10BT_IDLE | 845 ((1 << ANA_INTERVAL_SEL_TIMER_SHIFT) & ANA_INTERVAL_SEL_TIMER_MASK); 846 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 847 ALC_MII_DBG_ADDR, MII_ANA_CFG18); 848 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 849 ALC_MII_DBG_DATA, data); 850 851 data = ((2 << ANA_SERDES_CDR_BW_SHIFT) & ANA_SERDES_CDR_BW_MASK) | 852 ANA_SERDES_EN_DEEM | ANA_SERDES_SEL_HSP | ANA_SERDES_EN_PLL | 853 ANA_SERDES_EN_LCKDT; 854 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 855 ALC_MII_DBG_ADDR, MII_ANA_CFG5); 856 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 857 ALC_MII_DBG_DATA, data); 858 859 data = ((44 << ANA_LONG_CABLE_TH_100_SHIFT) & 860 ANA_LONG_CABLE_TH_100_MASK) | 861 ((33 << ANA_SHORT_CABLE_TH_100_SHIFT) & 862 ANA_SHORT_CABLE_TH_100_SHIFT) | 863 ANA_BP_BAD_LINK_ACCUM | ANA_BP_SMALL_BW; 864 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 865 ALC_MII_DBG_ADDR, MII_ANA_CFG54); 866 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 867 ALC_MII_DBG_DATA, data); 868 869 data = ((11 << ANA_IECHO_ADJ_3_SHIFT) & ANA_IECHO_ADJ_3_MASK) | 870 ((11 << ANA_IECHO_ADJ_2_SHIFT) & ANA_IECHO_ADJ_2_MASK) | 871 ((8 << ANA_IECHO_ADJ_1_SHIFT) & ANA_IECHO_ADJ_1_MASK) | 872 ((8 << ANA_IECHO_ADJ_0_SHIFT) & ANA_IECHO_ADJ_0_MASK); 873 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 874 ALC_MII_DBG_ADDR, MII_ANA_CFG4); 875 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 876 ALC_MII_DBG_DATA, data); 877 878 data = ((7 & ANA_MANUL_SWICH_ON_SHIFT) & ANA_MANUL_SWICH_ON_MASK) | 879 ANA_RESTART_CAL | ANA_MAN_ENABLE | ANA_SEL_HSP | ANA_EN_HB | 880 ANA_OEN_125M; 881 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 882 ALC_MII_DBG_ADDR, MII_ANA_CFG0); 883 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 884 ALC_MII_DBG_DATA, data); 885 DELAY(1000); 886 887 /* Disable hibernation. */ 888 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, ALC_MII_DBG_ADDR, 889 0x0029); 890 data = alc_miibus_readreg(sc->sc_dev, sc->alc_phyaddr, 891 ALC_MII_DBG_DATA); 892 data &= ~0x8000; 893 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, ALC_MII_DBG_DATA, 894 data); 895 896 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, ALC_MII_DBG_ADDR, 897 0x000B); 898 data = alc_miibus_readreg(sc->sc_dev, sc->alc_phyaddr, 899 ALC_MII_DBG_DATA); 900 data &= ~0x8000; 901 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, ALC_MII_DBG_DATA, 902 data); 903 } 904 905 static void 906 alc_phy_reset_816x(struct alc_softc *sc) 907 { 908 uint32_t val; 909 910 val = CSR_READ_4(sc, ALC_GPHY_CFG); 911 val &= ~(GPHY_CFG_EXT_RESET | GPHY_CFG_LED_MODE | 912 GPHY_CFG_GATE_25M_ENB | GPHY_CFG_PHY_IDDQ | GPHY_CFG_PHY_PLL_ON | 913 GPHY_CFG_PWDOWN_HW | GPHY_CFG_100AB_ENB); 914 val |= GPHY_CFG_SEL_ANA_RESET; 915 #ifdef notyet 916 val |= GPHY_CFG_HIB_PULSE | GPHY_CFG_HIB_EN | GPHY_CFG_SEL_ANA_RESET; 917 #else 918 /* Disable PHY hibernation. */ 919 val &= ~(GPHY_CFG_HIB_PULSE | GPHY_CFG_HIB_EN); 920 #endif 921 CSR_WRITE_4(sc, ALC_GPHY_CFG, val); 922 DELAY(10); 923 CSR_WRITE_4(sc, ALC_GPHY_CFG, val | GPHY_CFG_EXT_RESET); 924 DELAY(800); 925 926 /* Vendor PHY magic. */ 927 #ifdef notyet 928 alc_miidbg_writereg(sc, MII_DBG_LEGCYPS, DBG_LEGCYPS_DEFAULT); 929 alc_miidbg_writereg(sc, MII_DBG_SYSMODCTL, DBG_SYSMODCTL_DEFAULT); 930 alc_miiext_writereg(sc, MII_EXT_PCS, MII_EXT_VDRVBIAS, 931 EXT_VDRVBIAS_DEFAULT); 932 #else 933 /* Disable PHY hibernation. */ 934 alc_miidbg_writereg(sc, MII_DBG_LEGCYPS, 935 DBG_LEGCYPS_DEFAULT & ~DBG_LEGCYPS_ENB); 936 alc_miidbg_writereg(sc, MII_DBG_HIBNEG, 937 DBG_HIBNEG_DEFAULT & ~(DBG_HIBNEG_PSHIB_EN | DBG_HIBNEG_HIB_PULSE)); 938 alc_miidbg_writereg(sc, MII_DBG_GREENCFG, DBG_GREENCFG_DEFAULT); 939 #endif 940 941 /* XXX Disable EEE. */ 942 val = CSR_READ_4(sc, ALC_LPI_CTL); 943 val &= ~LPI_CTL_ENB; 944 CSR_WRITE_4(sc, ALC_LPI_CTL, val); 945 alc_miiext_writereg(sc, MII_EXT_ANEG, MII_EXT_ANEG_LOCAL_EEEADV, 0); 946 947 /* PHY power saving. */ 948 alc_miidbg_writereg(sc, MII_DBG_TST10BTCFG, DBG_TST10BTCFG_DEFAULT); 949 alc_miidbg_writereg(sc, MII_DBG_SRDSYSMOD, DBG_SRDSYSMOD_DEFAULT); 950 alc_miidbg_writereg(sc, MII_DBG_TST100BTCFG, DBG_TST100BTCFG_DEFAULT); 951 alc_miidbg_writereg(sc, MII_DBG_ANACTL, DBG_ANACTL_DEFAULT); 952 val = alc_miidbg_readreg(sc, MII_DBG_GREENCFG2); 953 val &= ~DBG_GREENCFG2_GATE_DFSE_EN; 954 alc_miidbg_writereg(sc, MII_DBG_GREENCFG2, val); 955 956 /* RTL8139C, 120m issue. */ 957 alc_miiext_writereg(sc, MII_EXT_ANEG, MII_EXT_ANEG_NLP78, 958 ANEG_NLP78_120M_DEFAULT); 959 alc_miiext_writereg(sc, MII_EXT_ANEG, MII_EXT_ANEG_S3DIG10, 960 ANEG_S3DIG10_DEFAULT); 961 962 if ((sc->alc_flags & ALC_FLAG_LINK_WAR) != 0) { 963 /* Turn off half amplitude. */ 964 val = alc_miiext_readreg(sc, MII_EXT_PCS, MII_EXT_CLDCTL3); 965 val |= EXT_CLDCTL3_BP_CABLE1TH_DET_GT; 966 alc_miiext_writereg(sc, MII_EXT_PCS, MII_EXT_CLDCTL3, val); 967 /* Turn off Green feature. */ 968 val = alc_miidbg_readreg(sc, MII_DBG_GREENCFG2); 969 val |= DBG_GREENCFG2_BP_GREEN; 970 alc_miidbg_writereg(sc, MII_DBG_GREENCFG2, val); 971 /* Turn off half bias. */ 972 val = alc_miiext_readreg(sc, MII_EXT_PCS, MII_EXT_CLDCTL5); 973 val |= EXT_CLDCTL5_BP_VD_HLFBIAS; 974 alc_miiext_writereg(sc, MII_EXT_PCS, MII_EXT_CLDCTL5, val); 975 } 976 } 977 978 static void 979 alc_phy_down(struct alc_softc *sc) 980 { 981 uint32_t gphy; 982 983 switch (sc->alc_ident->deviceid) { 984 case PCI_PRODUCT_ATTANSIC_AR8161: 985 case PCI_PRODUCT_ATTANSIC_E2200: 986 case PCI_PRODUCT_ATTANSIC_AR8162: 987 case PCI_PRODUCT_ATTANSIC_AR8171: 988 case PCI_PRODUCT_ATTANSIC_AR8172: 989 gphy = CSR_READ_4(sc, ALC_GPHY_CFG); 990 gphy &= ~(GPHY_CFG_EXT_RESET | GPHY_CFG_LED_MODE | 991 GPHY_CFG_100AB_ENB | GPHY_CFG_PHY_PLL_ON); 992 gphy |= GPHY_CFG_HIB_EN | GPHY_CFG_HIB_PULSE | 993 GPHY_CFG_SEL_ANA_RESET; 994 gphy |= GPHY_CFG_PHY_IDDQ | GPHY_CFG_PWDOWN_HW; 995 CSR_WRITE_4(sc, ALC_GPHY_CFG, gphy); 996 break; 997 case PCI_PRODUCT_ATTANSIC_AR8151: 998 case PCI_PRODUCT_ATTANSIC_AR8151_V2: 999 case PCI_PRODUCT_ATTANSIC_AR8152_B: 1000 case PCI_PRODUCT_ATTANSIC_AR8152_B2: 1001 /* 1002 * GPHY power down caused more problems on AR8151 v2.0. 1003 * When driver is reloaded after GPHY power down, 1004 * accesses to PHY/MAC registers hung the system. Only 1005 * cold boot recovered from it. I'm not sure whether 1006 * AR8151 v1.0 also requires this one though. I don't 1007 * have AR8151 v1.0 controller in hand. 1008 * The only option left is to isolate the PHY and 1009 * initiates power down the PHY which in turn saves 1010 * more power when driver is unloaded. 1011 */ 1012 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 1013 MII_BMCR, BMCR_ISO | BMCR_PDOWN); 1014 break; 1015 default: 1016 /* Force PHY down. */ 1017 CSR_WRITE_2(sc, ALC_GPHY_CFG, GPHY_CFG_EXT_RESET | 1018 GPHY_CFG_SEL_ANA_RESET | GPHY_CFG_PHY_IDDQ | 1019 GPHY_CFG_PWDOWN_HW); 1020 DELAY(1000); 1021 break; 1022 } 1023 } 1024 1025 static void 1026 alc_aspm(struct alc_softc *sc, int init, int media) 1027 { 1028 1029 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 1030 alc_aspm_816x(sc, init); 1031 else 1032 alc_aspm_813x(sc, media); 1033 } 1034 1035 static void 1036 alc_aspm_813x(struct alc_softc *sc, int media) 1037 { 1038 uint32_t pmcfg; 1039 uint16_t linkcfg; 1040 1041 pmcfg = CSR_READ_4(sc, ALC_PM_CFG); 1042 if ((sc->alc_flags & (ALC_FLAG_APS | ALC_FLAG_PCIE)) == 1043 (ALC_FLAG_APS | ALC_FLAG_PCIE)) 1044 linkcfg = CSR_READ_2(sc, sc->alc_expcap + 1045 PCIE_LCSR); 1046 else 1047 linkcfg = 0; 1048 pmcfg &= ~PM_CFG_SERDES_PD_EX_L1; 1049 pmcfg &= ~(PM_CFG_L1_ENTRY_TIMER_MASK | PM_CFG_LCKDET_TIMER_MASK); 1050 pmcfg |= PM_CFG_MAC_ASPM_CHK; 1051 pmcfg |= (PM_CFG_LCKDET_TIMER_DEFAULT << PM_CFG_LCKDET_TIMER_SHIFT); 1052 pmcfg &= ~(PM_CFG_ASPM_L1_ENB | PM_CFG_ASPM_L0S_ENB); 1053 1054 if ((sc->alc_flags & ALC_FLAG_APS) != 0) { 1055 /* Disable extended sync except AR8152 B v1.0 */ 1056 linkcfg &= ~0x80; 1057 if (sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8152_B && 1058 sc->alc_rev == ATHEROS_AR8152_B_V10) 1059 linkcfg |= 0x80; 1060 CSR_WRITE_2(sc, sc->alc_expcap + PCIE_LCSR, 1061 linkcfg); 1062 pmcfg &= ~(PM_CFG_EN_BUFS_RX_L0S | PM_CFG_SA_DLY_ENB | 1063 PM_CFG_HOTRST); 1064 pmcfg |= (PM_CFG_L1_ENTRY_TIMER_DEFAULT << 1065 PM_CFG_L1_ENTRY_TIMER_SHIFT); 1066 pmcfg &= ~PM_CFG_PM_REQ_TIMER_MASK; 1067 pmcfg |= (PM_CFG_PM_REQ_TIMER_DEFAULT << 1068 PM_CFG_PM_REQ_TIMER_SHIFT); 1069 pmcfg |= PM_CFG_SERDES_PD_EX_L1 | PM_CFG_PCIE_RECV; 1070 } 1071 1072 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) { 1073 if ((sc->alc_flags & ALC_FLAG_L0S) != 0) 1074 pmcfg |= PM_CFG_ASPM_L0S_ENB; 1075 if ((sc->alc_flags & ALC_FLAG_L1S) != 0) 1076 pmcfg |= PM_CFG_ASPM_L1_ENB; 1077 if ((sc->alc_flags & ALC_FLAG_APS) != 0) { 1078 if (sc->alc_ident->deviceid == 1079 PCI_PRODUCT_ATTANSIC_AR8152_B) 1080 pmcfg &= ~PM_CFG_ASPM_L0S_ENB; 1081 pmcfg &= ~(PM_CFG_SERDES_L1_ENB | 1082 PM_CFG_SERDES_PLL_L1_ENB | 1083 PM_CFG_SERDES_BUDS_RX_L1_ENB); 1084 pmcfg |= PM_CFG_CLK_SWH_L1; 1085 if (media == IFM_100_TX || media == IFM_1000_T) { 1086 pmcfg &= ~PM_CFG_L1_ENTRY_TIMER_MASK; 1087 switch (sc->alc_ident->deviceid) { 1088 case PCI_PRODUCT_ATTANSIC_AR8152_B: 1089 pmcfg |= (7 << 1090 PM_CFG_L1_ENTRY_TIMER_SHIFT); 1091 break; 1092 case PCI_PRODUCT_ATTANSIC_AR8152_B2: 1093 case PCI_PRODUCT_ATTANSIC_AR8151_V2: 1094 pmcfg |= (4 << 1095 PM_CFG_L1_ENTRY_TIMER_SHIFT); 1096 break; 1097 default: 1098 pmcfg |= (15 << 1099 PM_CFG_L1_ENTRY_TIMER_SHIFT); 1100 break; 1101 } 1102 } 1103 } else { 1104 pmcfg |= PM_CFG_SERDES_L1_ENB | 1105 PM_CFG_SERDES_PLL_L1_ENB | 1106 PM_CFG_SERDES_BUDS_RX_L1_ENB; 1107 pmcfg &= ~(PM_CFG_CLK_SWH_L1 | 1108 PM_CFG_ASPM_L1_ENB | PM_CFG_ASPM_L0S_ENB); 1109 } 1110 } else { 1111 pmcfg &= ~(PM_CFG_SERDES_BUDS_RX_L1_ENB | PM_CFG_SERDES_L1_ENB | 1112 PM_CFG_SERDES_PLL_L1_ENB); 1113 pmcfg |= PM_CFG_CLK_SWH_L1; 1114 if ((sc->alc_flags & ALC_FLAG_L1S) != 0) 1115 pmcfg |= PM_CFG_ASPM_L1_ENB; 1116 } 1117 CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg); 1118 } 1119 1120 static void 1121 alc_aspm_816x(struct alc_softc *sc, int init) 1122 { 1123 uint32_t pmcfg; 1124 1125 pmcfg = CSR_READ_4(sc, ALC_PM_CFG); 1126 pmcfg &= ~PM_CFG_L1_ENTRY_TIMER_816X_MASK; 1127 pmcfg |= PM_CFG_L1_ENTRY_TIMER_816X_DEFAULT; 1128 pmcfg &= ~PM_CFG_PM_REQ_TIMER_MASK; 1129 pmcfg |= PM_CFG_PM_REQ_TIMER_816X_DEFAULT; 1130 pmcfg &= ~PM_CFG_LCKDET_TIMER_MASK; 1131 pmcfg |= PM_CFG_LCKDET_TIMER_DEFAULT; 1132 pmcfg |= PM_CFG_SERDES_PD_EX_L1 | PM_CFG_CLK_SWH_L1 | PM_CFG_PCIE_RECV; 1133 pmcfg &= ~(PM_CFG_RX_L1_AFTER_L0S | PM_CFG_TX_L1_AFTER_L0S | 1134 PM_CFG_ASPM_L1_ENB | PM_CFG_ASPM_L0S_ENB | 1135 PM_CFG_SERDES_L1_ENB | PM_CFG_SERDES_PLL_L1_ENB | 1136 PM_CFG_SERDES_BUDS_RX_L1_ENB | PM_CFG_SA_DLY_ENB | 1137 PM_CFG_MAC_ASPM_CHK | PM_CFG_HOTRST); 1138 if (AR816X_REV(sc->alc_rev) <= AR816X_REV_A1 && 1139 (sc->alc_rev & 0x01) != 0) 1140 pmcfg |= PM_CFG_SERDES_L1_ENB | PM_CFG_SERDES_PLL_L1_ENB; 1141 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) { 1142 /* Link up, enable both L0s, L1s. */ 1143 pmcfg |= PM_CFG_ASPM_L0S_ENB | PM_CFG_ASPM_L1_ENB | 1144 PM_CFG_MAC_ASPM_CHK; 1145 } else { 1146 if (init != 0) 1147 pmcfg |= PM_CFG_ASPM_L0S_ENB | PM_CFG_ASPM_L1_ENB | 1148 PM_CFG_MAC_ASPM_CHK; 1149 else if ((sc->sc_ec.ec_if.if_flags & IFF_RUNNING) != 0) 1150 pmcfg |= PM_CFG_ASPM_L1_ENB | PM_CFG_MAC_ASPM_CHK; 1151 } 1152 CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg); 1153 } 1154 1155 static void 1156 alc_attach(device_t parent, device_t self, void *aux) 1157 { 1158 1159 struct alc_softc *sc = device_private(self); 1160 struct pci_attach_args *pa = aux; 1161 pci_chipset_tag_t pc = pa->pa_pc; 1162 pci_intr_handle_t ih; 1163 const char *intrstr; 1164 struct ifnet *ifp; 1165 pcireg_t memtype; 1166 const char *aspm_state[] = { "L0s/L1", "L0s", "L1", "L0s/L1" }; 1167 uint16_t burst; 1168 int base, mii_flags, state, error = 0; 1169 uint32_t cap, ctl, val; 1170 char intrbuf[PCI_INTRSTR_LEN]; 1171 1172 sc->alc_ident = alc_find_ident(pa); 1173 1174 aprint_naive("\n"); 1175 aprint_normal(": %s\n", sc->alc_ident->name); 1176 1177 sc->sc_dev = self; 1178 sc->sc_dmat = pa->pa_dmat; 1179 sc->sc_pct = pa->pa_pc; 1180 sc->sc_pcitag = pa->pa_tag; 1181 1182 /* 1183 * Allocate IO memory 1184 */ 1185 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, ALC_PCIR_BAR); 1186 switch (memtype) { 1187 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 1188 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT_1M: 1189 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 1190 break; 1191 default: 1192 aprint_error_dev(self, "invalid base address register\n"); 1193 break; 1194 } 1195 1196 if (pci_mapreg_map(pa, ALC_PCIR_BAR, memtype, 0, &sc->sc_mem_bt, 1197 &sc->sc_mem_bh, NULL, &sc->sc_mem_size)) { 1198 aprint_error_dev(self, "could not map mem space\n"); 1199 return; 1200 } 1201 1202 if (pci_intr_map(pa, &ih) != 0) { 1203 printf(": can't map interrupt\n"); 1204 goto fail; 1205 } 1206 1207 /* 1208 * Allocate IRQ 1209 */ 1210 intrstr = pci_intr_string(sc->sc_pct, ih, intrbuf, sizeof(intrbuf)); 1211 sc->sc_irq_handle = pci_intr_establish_xname(pc, ih, IPL_NET, alc_intr, 1212 sc, device_xname(self)); 1213 if (sc->sc_irq_handle == NULL) { 1214 printf(": could not establish interrupt"); 1215 if (intrstr != NULL) 1216 printf(" at %s", intrstr); 1217 printf("\n"); 1218 goto fail; 1219 } 1220 aprint_normal_dev(self, "interrupting at %s\n", intrstr); 1221 1222 /* Set PHY address. */ 1223 sc->alc_phyaddr = ALC_PHY_ADDR; 1224 1225 /* Initialize DMA parameters. */ 1226 sc->alc_dma_rd_burst = 0; 1227 sc->alc_dma_wr_burst = 0; 1228 sc->alc_rcb = DMA_CFG_RCB_64; 1229 if (pci_get_capability(pc, pa->pa_tag, PCI_CAP_PCIEXPRESS, 1230 &base, NULL)) { 1231 sc->alc_flags |= ALC_FLAG_PCIE; 1232 sc->alc_expcap = base; 1233 burst = pci_conf_read(sc->sc_pct, sc->sc_pcitag, 1234 base + PCIE_DCSR) >> 16; 1235 sc->alc_dma_rd_burst = (burst & 0x7000) >> 12; 1236 sc->alc_dma_wr_burst = (burst & 0x00e0) >> 5; 1237 if (alcdebug) { 1238 printf("%s: Read request size : %u bytes.\n", 1239 device_xname(sc->sc_dev), 1240 alc_dma_burst[sc->alc_dma_rd_burst]); 1241 printf("%s: TLP payload size : %u bytes.\n", 1242 device_xname(sc->sc_dev), 1243 alc_dma_burst[sc->alc_dma_wr_burst]); 1244 } 1245 if (alc_dma_burst[sc->alc_dma_rd_burst] > 1024) 1246 sc->alc_dma_rd_burst = 3; 1247 if (alc_dma_burst[sc->alc_dma_wr_burst] > 1024) 1248 sc->alc_dma_wr_burst = 3; 1249 1250 /* Clear data link and flow-control protocol error. */ 1251 val = CSR_READ_4(sc, ALC_PEX_UNC_ERR_SEV); 1252 val &= ~(PEX_UNC_ERR_SEV_DLP | PEX_UNC_ERR_SEV_FCP); 1253 CSR_WRITE_4(sc, ALC_PEX_UNC_ERR_SEV, val); 1254 1255 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 1256 CSR_WRITE_4(sc, ALC_LTSSM_ID_CFG, 1257 CSR_READ_4(sc, ALC_LTSSM_ID_CFG) & ~LTSSM_ID_WRO_ENB); 1258 CSR_WRITE_4(sc, ALC_PCIE_PHYMISC, 1259 CSR_READ_4(sc, ALC_PCIE_PHYMISC) | 1260 PCIE_PHYMISC_FORCE_RCV_DET); 1261 if (sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8152_B && 1262 sc->alc_rev == ATHEROS_AR8152_B_V10) { 1263 val = CSR_READ_4(sc, ALC_PCIE_PHYMISC2); 1264 val &= ~(PCIE_PHYMISC2_SERDES_CDR_MASK | 1265 PCIE_PHYMISC2_SERDES_TH_MASK); 1266 val |= 3 << PCIE_PHYMISC2_SERDES_CDR_SHIFT; 1267 val |= 3 << PCIE_PHYMISC2_SERDES_TH_SHIFT; 1268 CSR_WRITE_4(sc, ALC_PCIE_PHYMISC2, val); 1269 } 1270 /* Disable ASPM L0S and L1. */ 1271 cap = pci_conf_read(sc->sc_pct, sc->sc_pcitag, 1272 base + PCIE_LCAP) >> 16; 1273 if ((cap & PCIE_LCAP_ASPM) != 0) { 1274 ctl = pci_conf_read(sc->sc_pct, sc->sc_pcitag, 1275 base + PCIE_LCSR) >> 16; 1276 if ((ctl & 0x08) != 0) 1277 sc->alc_rcb = DMA_CFG_RCB_128; 1278 if (alcdebug) 1279 printf("%s: RCB %u bytes\n", 1280 device_xname(sc->sc_dev), 1281 sc->alc_rcb == DMA_CFG_RCB_64 ? 64 : 128); 1282 state = ctl & 0x03; 1283 if (state & 0x01) 1284 sc->alc_flags |= ALC_FLAG_L0S; 1285 if (state & 0x02) 1286 sc->alc_flags |= ALC_FLAG_L1S; 1287 if (alcdebug) 1288 printf("%s: ASPM %s %s\n", 1289 device_xname(sc->sc_dev), 1290 aspm_state[state], 1291 state == 0 ? "disabled" : "enabled"); 1292 alc_disable_l0s_l1(sc); 1293 } else { 1294 aprint_debug_dev(sc->sc_dev, "no ASPM support\n"); 1295 } 1296 } else { 1297 val = CSR_READ_4(sc, ALC_PDLL_TRNS1); 1298 val &= ~PDLL_TRNS1_D3PLLOFF_ENB; 1299 CSR_WRITE_4(sc, ALC_PDLL_TRNS1, val); 1300 val = CSR_READ_4(sc, ALC_MASTER_CFG); 1301 if (AR816X_REV(sc->alc_rev) <= AR816X_REV_A1 && 1302 (sc->alc_rev & 0x01) != 0) { 1303 if ((val & MASTER_WAKEN_25M) == 0 || 1304 (val & MASTER_CLK_SEL_DIS) == 0) { 1305 val |= MASTER_WAKEN_25M | MASTER_CLK_SEL_DIS; 1306 CSR_WRITE_4(sc, ALC_MASTER_CFG, val); 1307 } 1308 } else { 1309 if ((val & MASTER_WAKEN_25M) == 0 || 1310 (val & MASTER_CLK_SEL_DIS) != 0) { 1311 val |= MASTER_WAKEN_25M; 1312 val &= ~MASTER_CLK_SEL_DIS; 1313 CSR_WRITE_4(sc, ALC_MASTER_CFG, val); 1314 } 1315 } 1316 } 1317 alc_aspm(sc, 1, IFM_UNKNOWN); 1318 } 1319 1320 /* Reset PHY. */ 1321 alc_phy_reset(sc); 1322 1323 /* Reset the ethernet controller. */ 1324 alc_stop_mac(sc); 1325 alc_reset(sc); 1326 1327 /* 1328 * One odd thing is AR8132 uses the same PHY hardware(F1 1329 * gigabit PHY) of AR8131. So atphy(4) of AR8132 reports 1330 * the PHY supports 1000Mbps but that's not true. The PHY 1331 * used in AR8132 can't establish gigabit link even if it 1332 * shows the same PHY model/revision number of AR8131. 1333 */ 1334 switch (sc->alc_ident->deviceid) { 1335 case PCI_PRODUCT_ATTANSIC_AR8161: 1336 if (PCI_SUBSYS_ID(pci_conf_read( 1337 sc->sc_pct, sc->sc_pcitag, PCI_SUBSYS_ID_REG)) == 0x0091 && 1338 sc->alc_rev == 0) 1339 sc->alc_flags |= ALC_FLAG_LINK_WAR; 1340 /* FALLTHROUGH */ 1341 case PCI_PRODUCT_ATTANSIC_E2200: 1342 case PCI_PRODUCT_ATTANSIC_AR8171: 1343 sc->alc_flags |= ALC_FLAG_AR816X_FAMILY; 1344 break; 1345 case PCI_PRODUCT_ATTANSIC_AR8162: 1346 case PCI_PRODUCT_ATTANSIC_AR8172: 1347 sc->alc_flags |= ALC_FLAG_FASTETHER | ALC_FLAG_AR816X_FAMILY; 1348 break; 1349 case PCI_PRODUCT_ATTANSIC_AR8152_B: 1350 case PCI_PRODUCT_ATTANSIC_AR8152_B2: 1351 sc->alc_flags |= ALC_FLAG_APS; 1352 /* FALLTHROUGH */ 1353 case PCI_PRODUCT_ATTANSIC_AR8132: 1354 sc->alc_flags |= ALC_FLAG_FASTETHER; 1355 break; 1356 case PCI_PRODUCT_ATTANSIC_AR8151: 1357 case PCI_PRODUCT_ATTANSIC_AR8151_V2: 1358 sc->alc_flags |= ALC_FLAG_APS; 1359 /* FALLTHROUGH */ 1360 default: 1361 break; 1362 } 1363 sc->alc_flags |= ALC_FLAG_JUMBO; 1364 1365 /* 1366 * It seems that AR813x/AR815x has silicon bug for SMB. In 1367 * addition, Atheros said that enabling SMB wouldn't improve 1368 * performance. However I think it's bad to access lots of 1369 * registers to extract MAC statistics. 1370 */ 1371 sc->alc_flags |= ALC_FLAG_SMB_BUG; 1372 /* 1373 * Don't use Tx CMB. It is known to have silicon bug. 1374 */ 1375 sc->alc_flags |= ALC_FLAG_CMB_BUG; 1376 sc->alc_rev = PCI_REVISION(pa->pa_class); 1377 sc->alc_chip_rev = CSR_READ_4(sc, ALC_MASTER_CFG) >> 1378 MASTER_CHIP_REV_SHIFT; 1379 if (alcdebug) { 1380 printf("%s: PCI device revision : 0x%04x\n", 1381 device_xname(sc->sc_dev), sc->alc_rev); 1382 printf("%s: Chip id/revision : 0x%04x\n", 1383 device_xname(sc->sc_dev), sc->alc_chip_rev); 1384 printf("%s: %u Tx FIFO, %u Rx FIFO\n", device_xname(sc->sc_dev), 1385 CSR_READ_4(sc, ALC_SRAM_TX_FIFO_LEN) * 8, 1386 CSR_READ_4(sc, ALC_SRAM_RX_FIFO_LEN) * 8); 1387 } 1388 1389 error = alc_dma_alloc(sc); 1390 if (error) 1391 goto fail; 1392 1393 callout_init(&sc->sc_tick_ch, 0); 1394 callout_setfunc(&sc->sc_tick_ch, alc_tick, sc); 1395 1396 /* Load station address. */ 1397 alc_get_macaddr(sc); 1398 1399 aprint_normal_dev(self, "Ethernet address %s\n", 1400 ether_sprintf(sc->alc_eaddr)); 1401 1402 ifp = &sc->sc_ec.ec_if; 1403 ifp->if_softc = sc; 1404 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1405 ifp->if_init = alc_init; 1406 ifp->if_ioctl = alc_ioctl; 1407 ifp->if_start = alc_start; 1408 ifp->if_stop = alc_stop; 1409 ifp->if_watchdog = alc_watchdog; 1410 IFQ_SET_MAXLEN(&ifp->if_snd, ALC_TX_RING_CNT - 1); 1411 IFQ_SET_READY(&ifp->if_snd); 1412 strlcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 1413 1414 sc->sc_ec.ec_capabilities = ETHERCAP_VLAN_MTU; 1415 1416 #ifdef ALC_CHECKSUM 1417 ifp->if_capabilities |= IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 1418 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 1419 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 1420 #endif 1421 1422 #if NVLAN > 0 1423 sc->sc_ec.ec_capabilities |= ETHERCAP_VLAN_HWTAGGING; 1424 #endif 1425 1426 /* 1427 * XXX 1428 * It seems enabling Tx checksum offloading makes more trouble. 1429 * Sometimes the controller does not receive any frames when 1430 * Tx checksum offloading is enabled. I'm not sure whether this 1431 * is a bug in Tx checksum offloading logic or I got broken 1432 * sample boards. To safety, don't enable Tx checksum offloading 1433 * by default but give chance to users to toggle it if they know 1434 * their controllers work without problems. 1435 * Fortunately, Tx checksum offloading for AR816x family 1436 * seems to work. 1437 */ 1438 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 1439 ifp->if_capenable &= ~IFCAP_CSUM_IPv4_Tx; 1440 ifp->if_capabilities &= ~ALC_CSUM_FEATURES; 1441 } 1442 1443 /* Set up MII bus. */ 1444 sc->sc_miibus.mii_ifp = ifp; 1445 sc->sc_miibus.mii_readreg = alc_miibus_readreg; 1446 sc->sc_miibus.mii_writereg = alc_miibus_writereg; 1447 sc->sc_miibus.mii_statchg = alc_miibus_statchg; 1448 1449 sc->sc_ec.ec_mii = &sc->sc_miibus; 1450 ifmedia_init(&sc->sc_miibus.mii_media, 0, alc_mediachange, 1451 alc_mediastatus); 1452 mii_flags = 0; 1453 if ((sc->alc_flags & ALC_FLAG_JUMBO) != 0) 1454 mii_flags |= MIIF_DOPAUSE; 1455 mii_attach(self, &sc->sc_miibus, 0xffffffff, MII_PHY_ANY, 1456 MII_OFFSET_ANY, mii_flags); 1457 1458 if (LIST_FIRST(&sc->sc_miibus.mii_phys) == NULL) { 1459 printf("%s: no PHY found!\n", device_xname(sc->sc_dev)); 1460 ifmedia_add(&sc->sc_miibus.mii_media, IFM_ETHER | IFM_MANUAL, 1461 0, NULL); 1462 ifmedia_set(&sc->sc_miibus.mii_media, IFM_ETHER | IFM_MANUAL); 1463 } else 1464 ifmedia_set(&sc->sc_miibus.mii_media, IFM_ETHER | IFM_AUTO); 1465 1466 if_attach(ifp); 1467 if_deferred_start_init(ifp, NULL); 1468 ether_ifattach(ifp, sc->alc_eaddr); 1469 1470 if (!pmf_device_register(self, NULL, NULL)) 1471 aprint_error_dev(self, "couldn't establish power handler\n"); 1472 else 1473 pmf_class_network_register(self, ifp); 1474 1475 return; 1476 fail: 1477 alc_dma_free(sc); 1478 if (sc->sc_irq_handle != NULL) { 1479 pci_intr_disestablish(sc->sc_pct, sc->sc_irq_handle); 1480 sc->sc_irq_handle = NULL; 1481 } 1482 if (sc->sc_mem_size) { 1483 bus_space_unmap(sc->sc_mem_bt, sc->sc_mem_bh, sc->sc_mem_size); 1484 sc->sc_mem_size = 0; 1485 } 1486 } 1487 1488 static int 1489 alc_detach(device_t self, int flags) 1490 { 1491 struct alc_softc *sc = device_private(self); 1492 struct ifnet *ifp = &sc->sc_ec.ec_if; 1493 int s; 1494 1495 s = splnet(); 1496 alc_stop(ifp, 0); 1497 splx(s); 1498 1499 mii_detach(&sc->sc_miibus, MII_PHY_ANY, MII_OFFSET_ANY); 1500 1501 /* Delete all remaining media. */ 1502 ifmedia_delete_instance(&sc->sc_miibus.mii_media, IFM_INST_ANY); 1503 1504 ether_ifdetach(ifp); 1505 if_detach(ifp); 1506 alc_dma_free(sc); 1507 1508 alc_phy_down(sc); 1509 if (sc->sc_irq_handle != NULL) { 1510 pci_intr_disestablish(sc->sc_pct, sc->sc_irq_handle); 1511 sc->sc_irq_handle = NULL; 1512 } 1513 if (sc->sc_mem_size) { 1514 bus_space_unmap(sc->sc_mem_bt, sc->sc_mem_bh, sc->sc_mem_size); 1515 sc->sc_mem_size = 0; 1516 } 1517 1518 return (0); 1519 } 1520 1521 static int 1522 alc_dma_alloc(struct alc_softc *sc) 1523 { 1524 struct alc_txdesc *txd; 1525 struct alc_rxdesc *rxd; 1526 int nsegs, error, i; 1527 1528 /* 1529 * Create DMA stuffs for TX ring 1530 */ 1531 error = bus_dmamap_create(sc->sc_dmat, ALC_TX_RING_SZ, 1, 1532 ALC_TX_RING_SZ, 0, BUS_DMA_NOWAIT, &sc->alc_cdata.alc_tx_ring_map); 1533 if (error) { 1534 sc->alc_cdata.alc_tx_ring_map = NULL; 1535 return (ENOBUFS); 1536 } 1537 1538 /* Allocate DMA'able memory for TX ring */ 1539 error = bus_dmamem_alloc(sc->sc_dmat, ALC_TX_RING_SZ, 1540 ETHER_ALIGN, 0, &sc->alc_rdata.alc_tx_ring_seg, 1, 1541 &nsegs, BUS_DMA_NOWAIT); 1542 if (error) { 1543 printf("%s: could not allocate DMA'able memory for Tx ring.\n", 1544 device_xname(sc->sc_dev)); 1545 return error; 1546 } 1547 1548 error = bus_dmamem_map(sc->sc_dmat, &sc->alc_rdata.alc_tx_ring_seg, 1549 nsegs, ALC_TX_RING_SZ, (void **)&sc->alc_rdata.alc_tx_ring, 1550 BUS_DMA_NOWAIT); 1551 if (error) 1552 return (ENOBUFS); 1553 1554 /* Load the DMA map for Tx ring. */ 1555 error = bus_dmamap_load(sc->sc_dmat, sc->alc_cdata.alc_tx_ring_map, 1556 sc->alc_rdata.alc_tx_ring, ALC_TX_RING_SZ, NULL, BUS_DMA_WAITOK); 1557 if (error) { 1558 printf("%s: could not load DMA'able memory for Tx ring.\n", 1559 device_xname(sc->sc_dev)); 1560 bus_dmamem_free(sc->sc_dmat, 1561 &sc->alc_rdata.alc_tx_ring_seg, 1); 1562 return error; 1563 } 1564 1565 sc->alc_rdata.alc_tx_ring_paddr = 1566 sc->alc_cdata.alc_tx_ring_map->dm_segs[0].ds_addr; 1567 1568 /* 1569 * Create DMA stuffs for RX ring 1570 */ 1571 error = bus_dmamap_create(sc->sc_dmat, ALC_RX_RING_SZ, 1, 1572 ALC_RX_RING_SZ, 0, BUS_DMA_NOWAIT, &sc->alc_cdata.alc_rx_ring_map); 1573 if (error) 1574 return (ENOBUFS); 1575 1576 /* Allocate DMA'able memory for RX ring */ 1577 error = bus_dmamem_alloc(sc->sc_dmat, ALC_RX_RING_SZ, 1578 ETHER_ALIGN, 0, &sc->alc_rdata.alc_rx_ring_seg, 1, 1579 &nsegs, BUS_DMA_NOWAIT); 1580 if (error) { 1581 printf("%s: could not allocate DMA'able memory for Rx ring.\n", 1582 device_xname(sc->sc_dev)); 1583 return error; 1584 } 1585 1586 error = bus_dmamem_map(sc->sc_dmat, &sc->alc_rdata.alc_rx_ring_seg, 1587 nsegs, ALC_RX_RING_SZ, (void **)&sc->alc_rdata.alc_rx_ring, 1588 BUS_DMA_NOWAIT); 1589 if (error) 1590 return (ENOBUFS); 1591 1592 /* Load the DMA map for Rx ring. */ 1593 error = bus_dmamap_load(sc->sc_dmat, sc->alc_cdata.alc_rx_ring_map, 1594 sc->alc_rdata.alc_rx_ring, ALC_RX_RING_SZ, NULL, BUS_DMA_WAITOK); 1595 if (error) { 1596 printf("%s: could not load DMA'able memory for Rx ring.\n", 1597 device_xname(sc->sc_dev)); 1598 bus_dmamem_free(sc->sc_dmat, 1599 &sc->alc_rdata.alc_rx_ring_seg, 1); 1600 return error; 1601 } 1602 1603 sc->alc_rdata.alc_rx_ring_paddr = 1604 sc->alc_cdata.alc_rx_ring_map->dm_segs[0].ds_addr; 1605 1606 /* 1607 * Create DMA stuffs for RX return ring 1608 */ 1609 error = bus_dmamap_create(sc->sc_dmat, ALC_RR_RING_SZ, 1, 1610 ALC_RR_RING_SZ, 0, BUS_DMA_NOWAIT, &sc->alc_cdata.alc_rr_ring_map); 1611 if (error) 1612 return (ENOBUFS); 1613 1614 /* Allocate DMA'able memory for RX return ring */ 1615 error = bus_dmamem_alloc(sc->sc_dmat, ALC_RR_RING_SZ, 1616 ETHER_ALIGN, 0, &sc->alc_rdata.alc_rr_ring_seg, 1, 1617 &nsegs, BUS_DMA_NOWAIT); 1618 if (error) { 1619 printf("%s: could not allocate DMA'able memory for Rx " 1620 "return ring.\n", device_xname(sc->sc_dev)); 1621 return error; 1622 } 1623 1624 error = bus_dmamem_map(sc->sc_dmat, &sc->alc_rdata.alc_rr_ring_seg, 1625 nsegs, ALC_RR_RING_SZ, (void **)&sc->alc_rdata.alc_rr_ring, 1626 BUS_DMA_NOWAIT); 1627 if (error) 1628 return (ENOBUFS); 1629 1630 /* Load the DMA map for Rx return ring. */ 1631 error = bus_dmamap_load(sc->sc_dmat, sc->alc_cdata.alc_rr_ring_map, 1632 sc->alc_rdata.alc_rr_ring, ALC_RR_RING_SZ, NULL, BUS_DMA_WAITOK); 1633 if (error) { 1634 printf("%s: could not load DMA'able memory for Rx return ring." 1635 "\n", device_xname(sc->sc_dev)); 1636 bus_dmamem_free(sc->sc_dmat, 1637 &sc->alc_rdata.alc_rr_ring_seg, 1); 1638 return error; 1639 } 1640 1641 sc->alc_rdata.alc_rr_ring_paddr = 1642 sc->alc_cdata.alc_rr_ring_map->dm_segs[0].ds_addr; 1643 1644 /* 1645 * Create DMA stuffs for CMB block 1646 */ 1647 error = bus_dmamap_create(sc->sc_dmat, ALC_CMB_SZ, 1, 1648 ALC_CMB_SZ, 0, BUS_DMA_NOWAIT, 1649 &sc->alc_cdata.alc_cmb_map); 1650 if (error) 1651 return (ENOBUFS); 1652 1653 /* Allocate DMA'able memory for CMB block */ 1654 error = bus_dmamem_alloc(sc->sc_dmat, ALC_CMB_SZ, 1655 ETHER_ALIGN, 0, &sc->alc_rdata.alc_cmb_seg, 1, 1656 &nsegs, BUS_DMA_NOWAIT); 1657 if (error) { 1658 printf("%s: could not allocate DMA'able memory for " 1659 "CMB block\n", device_xname(sc->sc_dev)); 1660 return error; 1661 } 1662 1663 error = bus_dmamem_map(sc->sc_dmat, &sc->alc_rdata.alc_cmb_seg, 1664 nsegs, ALC_CMB_SZ, (void **)&sc->alc_rdata.alc_cmb, 1665 BUS_DMA_NOWAIT); 1666 if (error) 1667 return (ENOBUFS); 1668 1669 /* Load the DMA map for CMB block. */ 1670 error = bus_dmamap_load(sc->sc_dmat, sc->alc_cdata.alc_cmb_map, 1671 sc->alc_rdata.alc_cmb, ALC_CMB_SZ, NULL, 1672 BUS_DMA_WAITOK); 1673 if (error) { 1674 printf("%s: could not load DMA'able memory for CMB block\n", 1675 device_xname(sc->sc_dev)); 1676 bus_dmamem_free(sc->sc_dmat, 1677 &sc->alc_rdata.alc_cmb_seg, 1); 1678 return error; 1679 } 1680 1681 sc->alc_rdata.alc_cmb_paddr = 1682 sc->alc_cdata.alc_cmb_map->dm_segs[0].ds_addr; 1683 1684 /* 1685 * Create DMA stuffs for SMB block 1686 */ 1687 error = bus_dmamap_create(sc->sc_dmat, ALC_SMB_SZ, 1, 1688 ALC_SMB_SZ, 0, BUS_DMA_NOWAIT, 1689 &sc->alc_cdata.alc_smb_map); 1690 if (error) 1691 return (ENOBUFS); 1692 1693 /* Allocate DMA'able memory for SMB block */ 1694 error = bus_dmamem_alloc(sc->sc_dmat, ALC_SMB_SZ, 1695 ETHER_ALIGN, 0, &sc->alc_rdata.alc_smb_seg, 1, 1696 &nsegs, BUS_DMA_NOWAIT); 1697 if (error) { 1698 printf("%s: could not allocate DMA'able memory for " 1699 "SMB block\n", device_xname(sc->sc_dev)); 1700 return error; 1701 } 1702 1703 error = bus_dmamem_map(sc->sc_dmat, &sc->alc_rdata.alc_smb_seg, 1704 nsegs, ALC_SMB_SZ, (void **)&sc->alc_rdata.alc_smb, 1705 BUS_DMA_NOWAIT); 1706 if (error) 1707 return (ENOBUFS); 1708 1709 /* Load the DMA map for SMB block */ 1710 error = bus_dmamap_load(sc->sc_dmat, sc->alc_cdata.alc_smb_map, 1711 sc->alc_rdata.alc_smb, ALC_SMB_SZ, NULL, 1712 BUS_DMA_WAITOK); 1713 if (error) { 1714 printf("%s: could not load DMA'able memory for SMB block\n", 1715 device_xname(sc->sc_dev)); 1716 bus_dmamem_free(sc->sc_dmat, 1717 &sc->alc_rdata.alc_smb_seg, 1); 1718 return error; 1719 } 1720 1721 sc->alc_rdata.alc_smb_paddr = 1722 sc->alc_cdata.alc_smb_map->dm_segs[0].ds_addr; 1723 1724 1725 /* Create DMA maps for Tx buffers. */ 1726 for (i = 0; i < ALC_TX_RING_CNT; i++) { 1727 txd = &sc->alc_cdata.alc_txdesc[i]; 1728 txd->tx_m = NULL; 1729 txd->tx_dmamap = NULL; 1730 error = bus_dmamap_create(sc->sc_dmat, ALC_TSO_MAXSIZE, 1731 ALC_MAXTXSEGS, ALC_TSO_MAXSEGSIZE, 0, BUS_DMA_NOWAIT, 1732 &txd->tx_dmamap); 1733 if (error) { 1734 printf("%s: could not create Tx dmamap.\n", 1735 device_xname(sc->sc_dev)); 1736 return error; 1737 } 1738 } 1739 1740 /* Create DMA maps for Rx buffers. */ 1741 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES, 0, 1742 BUS_DMA_NOWAIT, &sc->alc_cdata.alc_rx_sparemap); 1743 if (error) { 1744 printf("%s: could not create spare Rx dmamap.\n", 1745 device_xname(sc->sc_dev)); 1746 return error; 1747 } 1748 1749 for (i = 0; i < ALC_RX_RING_CNT; i++) { 1750 rxd = &sc->alc_cdata.alc_rxdesc[i]; 1751 rxd->rx_m = NULL; 1752 rxd->rx_dmamap = NULL; 1753 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 1754 MCLBYTES, 0, BUS_DMA_NOWAIT, &rxd->rx_dmamap); 1755 if (error) { 1756 printf("%s: could not create Rx dmamap.\n", 1757 device_xname(sc->sc_dev)); 1758 return error; 1759 } 1760 } 1761 1762 return (0); 1763 } 1764 1765 1766 static void 1767 alc_dma_free(struct alc_softc *sc) 1768 { 1769 struct alc_txdesc *txd; 1770 struct alc_rxdesc *rxd; 1771 int i; 1772 1773 /* Tx buffers */ 1774 for (i = 0; i < ALC_TX_RING_CNT; i++) { 1775 txd = &sc->alc_cdata.alc_txdesc[i]; 1776 if (txd->tx_dmamap != NULL) { 1777 bus_dmamap_destroy(sc->sc_dmat, txd->tx_dmamap); 1778 txd->tx_dmamap = NULL; 1779 } 1780 } 1781 /* Rx buffers */ 1782 for (i = 0; i < ALC_RX_RING_CNT; i++) { 1783 rxd = &sc->alc_cdata.alc_rxdesc[i]; 1784 if (rxd->rx_dmamap != NULL) { 1785 bus_dmamap_destroy(sc->sc_dmat, rxd->rx_dmamap); 1786 rxd->rx_dmamap = NULL; 1787 } 1788 } 1789 if (sc->alc_cdata.alc_rx_sparemap != NULL) { 1790 bus_dmamap_destroy(sc->sc_dmat, sc->alc_cdata.alc_rx_sparemap); 1791 sc->alc_cdata.alc_rx_sparemap = NULL; 1792 } 1793 1794 /* Tx ring. */ 1795 if (sc->alc_cdata.alc_tx_ring_map != NULL) 1796 bus_dmamap_unload(sc->sc_dmat, sc->alc_cdata.alc_tx_ring_map); 1797 if (sc->alc_cdata.alc_tx_ring_map != NULL && 1798 sc->alc_rdata.alc_tx_ring != NULL) 1799 bus_dmamem_free(sc->sc_dmat, 1800 &sc->alc_rdata.alc_tx_ring_seg, 1); 1801 sc->alc_rdata.alc_tx_ring = NULL; 1802 sc->alc_cdata.alc_tx_ring_map = NULL; 1803 1804 /* Rx ring. */ 1805 if (sc->alc_cdata.alc_rx_ring_map != NULL) 1806 bus_dmamap_unload(sc->sc_dmat, sc->alc_cdata.alc_rx_ring_map); 1807 if (sc->alc_cdata.alc_rx_ring_map != NULL && 1808 sc->alc_rdata.alc_rx_ring != NULL) 1809 bus_dmamem_free(sc->sc_dmat, 1810 &sc->alc_rdata.alc_rx_ring_seg, 1); 1811 sc->alc_rdata.alc_rx_ring = NULL; 1812 sc->alc_cdata.alc_rx_ring_map = NULL; 1813 1814 /* Rx return ring. */ 1815 if (sc->alc_cdata.alc_rr_ring_map != NULL) 1816 bus_dmamap_unload(sc->sc_dmat, sc->alc_cdata.alc_rr_ring_map); 1817 if (sc->alc_cdata.alc_rr_ring_map != NULL && 1818 sc->alc_rdata.alc_rr_ring != NULL) 1819 bus_dmamem_free(sc->sc_dmat, 1820 &sc->alc_rdata.alc_rr_ring_seg, 1); 1821 sc->alc_rdata.alc_rr_ring = NULL; 1822 sc->alc_cdata.alc_rr_ring_map = NULL; 1823 1824 /* CMB block */ 1825 if (sc->alc_cdata.alc_cmb_map != NULL) 1826 bus_dmamap_unload(sc->sc_dmat, sc->alc_cdata.alc_cmb_map); 1827 if (sc->alc_cdata.alc_cmb_map != NULL && 1828 sc->alc_rdata.alc_cmb != NULL) 1829 bus_dmamem_free(sc->sc_dmat, 1830 &sc->alc_rdata.alc_cmb_seg, 1); 1831 sc->alc_rdata.alc_cmb = NULL; 1832 sc->alc_cdata.alc_cmb_map = NULL; 1833 1834 /* SMB block */ 1835 if (sc->alc_cdata.alc_smb_map != NULL) 1836 bus_dmamap_unload(sc->sc_dmat, sc->alc_cdata.alc_smb_map); 1837 if (sc->alc_cdata.alc_smb_map != NULL && 1838 sc->alc_rdata.alc_smb != NULL) 1839 bus_dmamem_free(sc->sc_dmat, 1840 &sc->alc_rdata.alc_smb_seg, 1); 1841 sc->alc_rdata.alc_smb = NULL; 1842 sc->alc_cdata.alc_smb_map = NULL; 1843 } 1844 1845 static int 1846 alc_encap(struct alc_softc *sc, struct mbuf **m_head) 1847 { 1848 struct alc_txdesc *txd, *txd_last; 1849 struct tx_desc *desc; 1850 struct mbuf *m; 1851 bus_dmamap_t map; 1852 uint32_t cflags, poff, vtag; 1853 int error, idx, nsegs, prod; 1854 1855 m = *m_head; 1856 cflags = vtag = 0; 1857 poff = 0; 1858 1859 prod = sc->alc_cdata.alc_tx_prod; 1860 txd = &sc->alc_cdata.alc_txdesc[prod]; 1861 txd_last = txd; 1862 map = txd->tx_dmamap; 1863 1864 error = bus_dmamap_load_mbuf(sc->sc_dmat, map, *m_head, BUS_DMA_NOWAIT); 1865 1866 if (error == EFBIG) { 1867 error = 0; 1868 1869 *m_head = m_pullup(*m_head, MHLEN); 1870 if (*m_head == NULL) { 1871 printf("%s: can't defrag TX mbuf\n", 1872 device_xname(sc->sc_dev)); 1873 return ENOBUFS; 1874 } 1875 1876 error = bus_dmamap_load_mbuf(sc->sc_dmat, map, *m_head, 1877 BUS_DMA_NOWAIT); 1878 1879 if (error != 0) { 1880 printf("%s: could not load defragged TX mbuf\n", 1881 device_xname(sc->sc_dev)); 1882 m_freem(*m_head); 1883 *m_head = NULL; 1884 return error; 1885 } 1886 } else if (error) { 1887 printf("%s: could not load TX mbuf\n", device_xname(sc->sc_dev)); 1888 return (error); 1889 } 1890 1891 nsegs = map->dm_nsegs; 1892 1893 if (nsegs == 0) { 1894 m_freem(*m_head); 1895 *m_head = NULL; 1896 return (EIO); 1897 } 1898 1899 /* Check descriptor overrun. */ 1900 if (sc->alc_cdata.alc_tx_cnt + nsegs >= ALC_TX_RING_CNT - 3) { 1901 bus_dmamap_unload(sc->sc_dmat, map); 1902 return (ENOBUFS); 1903 } 1904 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 1905 BUS_DMASYNC_PREWRITE); 1906 1907 m = *m_head; 1908 desc = NULL; 1909 idx = 0; 1910 #if NVLAN > 0 1911 /* Configure VLAN hardware tag insertion. */ 1912 if (vlan_has_tag(m)) { 1913 vtag = htons(vlan_get_tag(m)); 1914 vtag = (vtag << TD_VLAN_SHIFT) & TD_VLAN_MASK; 1915 cflags |= TD_INS_VLAN_TAG; 1916 } 1917 #endif 1918 /* Configure Tx checksum offload. */ 1919 if ((m->m_pkthdr.csum_flags & ALC_CSUM_FEATURES) != 0) { 1920 cflags |= TD_CUSTOM_CSUM; 1921 /* Set checksum start offset. */ 1922 cflags |= ((poff >> 1) << TD_PLOAD_OFFSET_SHIFT) & 1923 TD_PLOAD_OFFSET_MASK; 1924 } 1925 for (; idx < nsegs; idx++) { 1926 desc = &sc->alc_rdata.alc_tx_ring[prod]; 1927 desc->len = 1928 htole32(TX_BYTES(map->dm_segs[idx].ds_len) | vtag); 1929 desc->flags = htole32(cflags); 1930 desc->addr = htole64(map->dm_segs[idx].ds_addr); 1931 sc->alc_cdata.alc_tx_cnt++; 1932 ALC_DESC_INC(prod, ALC_TX_RING_CNT); 1933 } 1934 /* Update producer index. */ 1935 sc->alc_cdata.alc_tx_prod = prod; 1936 1937 /* Finally set EOP on the last descriptor. */ 1938 prod = (prod + ALC_TX_RING_CNT - 1) % ALC_TX_RING_CNT; 1939 desc = &sc->alc_rdata.alc_tx_ring[prod]; 1940 desc->flags |= htole32(TD_EOP); 1941 1942 /* Swap dmamap of the first and the last. */ 1943 txd = &sc->alc_cdata.alc_txdesc[prod]; 1944 map = txd_last->tx_dmamap; 1945 txd_last->tx_dmamap = txd->tx_dmamap; 1946 txd->tx_dmamap = map; 1947 txd->tx_m = m; 1948 1949 return (0); 1950 } 1951 1952 static void 1953 alc_start(struct ifnet *ifp) 1954 { 1955 struct alc_softc *sc = ifp->if_softc; 1956 struct mbuf *m_head; 1957 int enq; 1958 1959 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 1960 return; 1961 if ((sc->alc_flags & ALC_FLAG_LINK) == 0) 1962 return; 1963 if (IFQ_IS_EMPTY(&ifp->if_snd)) 1964 return; 1965 1966 /* Reclaim transmitted frames. */ 1967 if (sc->alc_cdata.alc_tx_cnt >= ALC_TX_DESC_HIWAT) 1968 alc_txeof(sc); 1969 1970 enq = 0; 1971 for (;;) { 1972 IFQ_DEQUEUE(&ifp->if_snd, m_head); 1973 if (m_head == NULL) 1974 break; 1975 1976 /* 1977 * Pack the data into the transmit ring. If we 1978 * don't have room, set the OACTIVE flag and wait 1979 * for the NIC to drain the ring. 1980 */ 1981 if (alc_encap(sc, &m_head)) { 1982 if (m_head == NULL) 1983 break; 1984 ifp->if_flags |= IFF_OACTIVE; 1985 break; 1986 } 1987 enq = 1; 1988 1989 /* 1990 * If there's a BPF listener, bounce a copy of this frame 1991 * to him. 1992 */ 1993 bpf_mtap(ifp, m_head, BPF_D_OUT); 1994 } 1995 1996 if (enq) { 1997 /* Sync descriptors. */ 1998 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_tx_ring_map, 0, 1999 sc->alc_cdata.alc_tx_ring_map->dm_mapsize, 2000 BUS_DMASYNC_PREWRITE); 2001 /* Kick. Assume we're using normal Tx priority queue. */ 2002 CSR_WRITE_4(sc, ALC_MBOX_TD_PROD_IDX, 2003 (sc->alc_cdata.alc_tx_prod << 2004 MBOX_TD_PROD_LO_IDX_SHIFT) & 2005 MBOX_TD_PROD_LO_IDX_MASK); 2006 /* Set a timeout in case the chip goes out to lunch. */ 2007 ifp->if_timer = ALC_TX_TIMEOUT; 2008 } 2009 } 2010 2011 static void 2012 alc_watchdog(struct ifnet *ifp) 2013 { 2014 struct alc_softc *sc = ifp->if_softc; 2015 2016 if ((sc->alc_flags & ALC_FLAG_LINK) == 0) { 2017 printf("%s: watchdog timeout (missed link)\n", 2018 device_xname(sc->sc_dev)); 2019 ifp->if_oerrors++; 2020 alc_init_backend(ifp, false); 2021 return; 2022 } 2023 2024 printf("%s: watchdog timeout\n", device_xname(sc->sc_dev)); 2025 ifp->if_oerrors++; 2026 alc_init_backend(ifp, false); 2027 alc_start(ifp); 2028 } 2029 2030 static int 2031 alc_ioctl(struct ifnet *ifp, u_long cmd, void *data) 2032 { 2033 struct alc_softc *sc = ifp->if_softc; 2034 struct mii_data *mii = &sc->sc_miibus; 2035 struct ifreq *ifr = (struct ifreq *)data; 2036 int s, error = 0; 2037 2038 s = splnet(); 2039 2040 error = ether_ioctl(ifp, cmd, data); 2041 switch (cmd) { 2042 case SIOCSIFADDR: 2043 ifp->if_flags |= IFF_UP; 2044 if (!(ifp->if_flags & IFF_RUNNING)) 2045 alc_init(ifp); 2046 break; 2047 2048 case SIOCSIFFLAGS: 2049 if (ifp->if_flags & IFF_UP) { 2050 if (ifp->if_flags & IFF_RUNNING) 2051 error = ENETRESET; 2052 else 2053 alc_init(ifp); 2054 } else { 2055 if (ifp->if_flags & IFF_RUNNING) 2056 alc_stop(ifp, 0); 2057 } 2058 break; 2059 2060 case SIOCSIFMEDIA: 2061 case SIOCGIFMEDIA: 2062 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd); 2063 break; 2064 2065 default: 2066 error = ether_ioctl(ifp, cmd, data); 2067 break; 2068 } 2069 2070 if (error == ENETRESET) { 2071 if (ifp->if_flags & IFF_RUNNING) 2072 alc_iff(sc); 2073 error = 0; 2074 } 2075 2076 splx(s); 2077 return (error); 2078 } 2079 2080 static void 2081 alc_mac_config(struct alc_softc *sc) 2082 { 2083 struct mii_data *mii; 2084 uint32_t reg; 2085 2086 mii = &sc->sc_miibus; 2087 reg = CSR_READ_4(sc, ALC_MAC_CFG); 2088 reg &= ~(MAC_CFG_FULL_DUPLEX | MAC_CFG_TX_FC | MAC_CFG_RX_FC | 2089 MAC_CFG_SPEED_MASK); 2090 if (sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8151 || 2091 sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8151_V2 || 2092 sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8152_B2) 2093 reg |= MAC_CFG_HASH_ALG_CRC32 | MAC_CFG_SPEED_MODE_SW; 2094 /* Reprogram MAC with resolved speed/duplex. */ 2095 switch (IFM_SUBTYPE(mii->mii_media_active)) { 2096 case IFM_10_T: 2097 case IFM_100_TX: 2098 reg |= MAC_CFG_SPEED_10_100; 2099 break; 2100 case IFM_1000_T: 2101 reg |= MAC_CFG_SPEED_1000; 2102 break; 2103 } 2104 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 2105 reg |= MAC_CFG_FULL_DUPLEX; 2106 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0) 2107 reg |= MAC_CFG_TX_FC; 2108 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0) 2109 reg |= MAC_CFG_RX_FC; 2110 } 2111 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 2112 } 2113 2114 static void 2115 alc_stats_clear(struct alc_softc *sc) 2116 { 2117 struct smb sb, *smb; 2118 uint32_t *reg; 2119 int i; 2120 2121 if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0) { 2122 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_smb_map, 0, 2123 sc->alc_cdata.alc_smb_map->dm_mapsize, 2124 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2125 smb = sc->alc_rdata.alc_smb; 2126 /* Update done, clear. */ 2127 smb->updated = 0; 2128 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_smb_map, 0, 2129 sc->alc_cdata.alc_smb_map->dm_mapsize, 2130 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2131 } else { 2132 for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered; 2133 reg++) { 2134 CSR_READ_4(sc, ALC_RX_MIB_BASE + i); 2135 i += sizeof(uint32_t); 2136 } 2137 /* Read Tx statistics. */ 2138 for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes; 2139 reg++) { 2140 CSR_READ_4(sc, ALC_TX_MIB_BASE + i); 2141 i += sizeof(uint32_t); 2142 } 2143 } 2144 } 2145 2146 static void 2147 alc_stats_update(struct alc_softc *sc) 2148 { 2149 struct ifnet *ifp = &sc->sc_ec.ec_if; 2150 struct alc_hw_stats *stat; 2151 struct smb sb, *smb; 2152 uint32_t *reg; 2153 int i; 2154 2155 stat = &sc->alc_stats; 2156 if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0) { 2157 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_smb_map, 0, 2158 sc->alc_cdata.alc_smb_map->dm_mapsize, 2159 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2160 smb = sc->alc_rdata.alc_smb; 2161 if (smb->updated == 0) 2162 return; 2163 } else { 2164 smb = &sb; 2165 /* Read Rx statistics. */ 2166 for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered; 2167 reg++) { 2168 *reg = CSR_READ_4(sc, ALC_RX_MIB_BASE + i); 2169 i += sizeof(uint32_t); 2170 } 2171 /* Read Tx statistics. */ 2172 for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes; 2173 reg++) { 2174 *reg = CSR_READ_4(sc, ALC_TX_MIB_BASE + i); 2175 i += sizeof(uint32_t); 2176 } 2177 } 2178 2179 /* Rx stats. */ 2180 stat->rx_frames += smb->rx_frames; 2181 stat->rx_bcast_frames += smb->rx_bcast_frames; 2182 stat->rx_mcast_frames += smb->rx_mcast_frames; 2183 stat->rx_pause_frames += smb->rx_pause_frames; 2184 stat->rx_control_frames += smb->rx_control_frames; 2185 stat->rx_crcerrs += smb->rx_crcerrs; 2186 stat->rx_lenerrs += smb->rx_lenerrs; 2187 stat->rx_bytes += smb->rx_bytes; 2188 stat->rx_runts += smb->rx_runts; 2189 stat->rx_fragments += smb->rx_fragments; 2190 stat->rx_pkts_64 += smb->rx_pkts_64; 2191 stat->rx_pkts_65_127 += smb->rx_pkts_65_127; 2192 stat->rx_pkts_128_255 += smb->rx_pkts_128_255; 2193 stat->rx_pkts_256_511 += smb->rx_pkts_256_511; 2194 stat->rx_pkts_512_1023 += smb->rx_pkts_512_1023; 2195 stat->rx_pkts_1024_1518 += smb->rx_pkts_1024_1518; 2196 stat->rx_pkts_1519_max += smb->rx_pkts_1519_max; 2197 stat->rx_pkts_truncated += smb->rx_pkts_truncated; 2198 stat->rx_fifo_oflows += smb->rx_fifo_oflows; 2199 stat->rx_rrs_errs += smb->rx_rrs_errs; 2200 stat->rx_alignerrs += smb->rx_alignerrs; 2201 stat->rx_bcast_bytes += smb->rx_bcast_bytes; 2202 stat->rx_mcast_bytes += smb->rx_mcast_bytes; 2203 stat->rx_pkts_filtered += smb->rx_pkts_filtered; 2204 2205 /* Tx stats. */ 2206 stat->tx_frames += smb->tx_frames; 2207 stat->tx_bcast_frames += smb->tx_bcast_frames; 2208 stat->tx_mcast_frames += smb->tx_mcast_frames; 2209 stat->tx_pause_frames += smb->tx_pause_frames; 2210 stat->tx_excess_defer += smb->tx_excess_defer; 2211 stat->tx_control_frames += smb->tx_control_frames; 2212 stat->tx_deferred += smb->tx_deferred; 2213 stat->tx_bytes += smb->tx_bytes; 2214 stat->tx_pkts_64 += smb->tx_pkts_64; 2215 stat->tx_pkts_65_127 += smb->tx_pkts_65_127; 2216 stat->tx_pkts_128_255 += smb->tx_pkts_128_255; 2217 stat->tx_pkts_256_511 += smb->tx_pkts_256_511; 2218 stat->tx_pkts_512_1023 += smb->tx_pkts_512_1023; 2219 stat->tx_pkts_1024_1518 += smb->tx_pkts_1024_1518; 2220 stat->tx_pkts_1519_max += smb->tx_pkts_1519_max; 2221 stat->tx_single_colls += smb->tx_single_colls; 2222 stat->tx_multi_colls += smb->tx_multi_colls; 2223 stat->tx_late_colls += smb->tx_late_colls; 2224 stat->tx_excess_colls += smb->tx_excess_colls; 2225 stat->tx_underrun += smb->tx_underrun; 2226 stat->tx_desc_underrun += smb->tx_desc_underrun; 2227 stat->tx_lenerrs += smb->tx_lenerrs; 2228 stat->tx_pkts_truncated += smb->tx_pkts_truncated; 2229 stat->tx_bcast_bytes += smb->tx_bcast_bytes; 2230 stat->tx_mcast_bytes += smb->tx_mcast_bytes; 2231 2232 /* Update counters in ifnet. */ 2233 ifp->if_opackets += smb->tx_frames; 2234 2235 ifp->if_collisions += smb->tx_single_colls + 2236 smb->tx_multi_colls * 2 + smb->tx_late_colls + 2237 smb->tx_excess_colls * HDPX_CFG_RETRY_DEFAULT; 2238 2239 ifp->if_oerrors += smb->tx_late_colls + smb->tx_excess_colls + 2240 smb->tx_underrun + smb->tx_pkts_truncated; 2241 2242 ifp->if_ipackets += smb->rx_frames; 2243 2244 ifp->if_ierrors += smb->rx_crcerrs + smb->rx_lenerrs + 2245 smb->rx_runts + smb->rx_pkts_truncated + 2246 smb->rx_fifo_oflows + smb->rx_rrs_errs + 2247 smb->rx_alignerrs; 2248 2249 if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0) { 2250 /* Update done, clear. */ 2251 smb->updated = 0; 2252 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_smb_map, 0, 2253 sc->alc_cdata.alc_smb_map->dm_mapsize, 2254 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2255 } 2256 } 2257 2258 static int 2259 alc_intr(void *arg) 2260 { 2261 struct alc_softc *sc = arg; 2262 struct ifnet *ifp = &sc->sc_ec.ec_if; 2263 uint32_t status; 2264 2265 status = CSR_READ_4(sc, ALC_INTR_STATUS); 2266 if ((status & ALC_INTRS) == 0) 2267 return (0); 2268 2269 /* Acknowledge and disable interrupts. */ 2270 CSR_WRITE_4(sc, ALC_INTR_STATUS, status | INTR_DIS_INT); 2271 2272 if (ifp->if_flags & IFF_RUNNING) { 2273 if (status & INTR_RX_PKT) { 2274 int error; 2275 2276 error = alc_rxintr(sc); 2277 if (error) { 2278 alc_init_backend(ifp, false); 2279 return (0); 2280 } 2281 } 2282 2283 if (status & (INTR_DMA_RD_TO_RST | INTR_DMA_WR_TO_RST | 2284 INTR_TXQ_TO_RST)) { 2285 if (status & INTR_DMA_RD_TO_RST) 2286 printf("%s: DMA read error! -- resetting\n", 2287 device_xname(sc->sc_dev)); 2288 if (status & INTR_DMA_WR_TO_RST) 2289 printf("%s: DMA write error! -- resetting\n", 2290 device_xname(sc->sc_dev)); 2291 if (status & INTR_TXQ_TO_RST) 2292 printf("%s: TxQ reset! -- resetting\n", 2293 device_xname(sc->sc_dev)); 2294 alc_init_backend(ifp, false); 2295 return (0); 2296 } 2297 2298 alc_txeof(sc); 2299 if_schedule_deferred_start(ifp); 2300 } 2301 2302 /* Re-enable interrupts. */ 2303 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0x7FFFFFFF); 2304 return (1); 2305 } 2306 2307 static void 2308 alc_txeof(struct alc_softc *sc) 2309 { 2310 struct ifnet *ifp = &sc->sc_ec.ec_if; 2311 struct alc_txdesc *txd; 2312 uint32_t cons, prod; 2313 int prog; 2314 2315 if (sc->alc_cdata.alc_tx_cnt == 0) 2316 return; 2317 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_tx_ring_map, 0, 2318 sc->alc_cdata.alc_tx_ring_map->dm_mapsize, 2319 BUS_DMASYNC_POSTREAD); 2320 if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0) { 2321 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_cmb_map, 0, 2322 sc->alc_cdata.alc_cmb_map->dm_mapsize, 2323 BUS_DMASYNC_POSTREAD); 2324 prod = sc->alc_rdata.alc_cmb->cons; 2325 } else 2326 prod = CSR_READ_4(sc, ALC_MBOX_TD_CONS_IDX); 2327 /* Assume we're using normal Tx priority queue. */ 2328 prod = (prod & MBOX_TD_CONS_LO_IDX_MASK) >> 2329 MBOX_TD_CONS_LO_IDX_SHIFT; 2330 cons = sc->alc_cdata.alc_tx_cons; 2331 /* 2332 * Go through our Tx list and free mbufs for those 2333 * frames which have been transmitted. 2334 */ 2335 for (prog = 0; cons != prod; prog++, 2336 ALC_DESC_INC(cons, ALC_TX_RING_CNT)) { 2337 if (sc->alc_cdata.alc_tx_cnt <= 0) 2338 break; 2339 prog++; 2340 ifp->if_flags &= ~IFF_OACTIVE; 2341 sc->alc_cdata.alc_tx_cnt--; 2342 txd = &sc->alc_cdata.alc_txdesc[cons]; 2343 if (txd->tx_m != NULL) { 2344 /* Reclaim transmitted mbufs. */ 2345 bus_dmamap_sync(sc->sc_dmat, txd->tx_dmamap, 0, 2346 txd->tx_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 2347 bus_dmamap_unload(sc->sc_dmat, txd->tx_dmamap); 2348 m_freem(txd->tx_m); 2349 txd->tx_m = NULL; 2350 } 2351 } 2352 2353 if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0) 2354 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_cmb_map, 0, 2355 sc->alc_cdata.alc_cmb_map->dm_mapsize, BUS_DMASYNC_PREREAD); 2356 sc->alc_cdata.alc_tx_cons = cons; 2357 /* 2358 * Unarm watchdog timer only when there is no pending 2359 * frames in Tx queue. 2360 */ 2361 if (sc->alc_cdata.alc_tx_cnt == 0) 2362 ifp->if_timer = 0; 2363 } 2364 2365 static int 2366 alc_newbuf(struct alc_softc *sc, struct alc_rxdesc *rxd, bool init) 2367 { 2368 struct mbuf *m; 2369 bus_dmamap_t map; 2370 int error; 2371 2372 MGETHDR(m, init ? M_WAITOK : M_DONTWAIT, MT_DATA); 2373 if (m == NULL) 2374 return (ENOBUFS); 2375 MCLGET(m, init ? M_WAITOK : M_DONTWAIT); 2376 if (!(m->m_flags & M_EXT)) { 2377 m_freem(m); 2378 return (ENOBUFS); 2379 } 2380 2381 m->m_len = m->m_pkthdr.len = RX_BUF_SIZE_MAX; 2382 2383 error = bus_dmamap_load_mbuf(sc->sc_dmat, 2384 sc->alc_cdata.alc_rx_sparemap, m, BUS_DMA_NOWAIT); 2385 2386 if (error != 0) { 2387 m_freem(m); 2388 2389 if (init) 2390 printf("%s: can't load RX mbuf\n", device_xname(sc->sc_dev)); 2391 2392 return (error); 2393 } 2394 2395 if (rxd->rx_m != NULL) { 2396 bus_dmamap_sync(sc->sc_dmat, rxd->rx_dmamap, 0, 2397 rxd->rx_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 2398 bus_dmamap_unload(sc->sc_dmat, rxd->rx_dmamap); 2399 } 2400 map = rxd->rx_dmamap; 2401 rxd->rx_dmamap = sc->alc_cdata.alc_rx_sparemap; 2402 sc->alc_cdata.alc_rx_sparemap = map; 2403 bus_dmamap_sync(sc->sc_dmat, rxd->rx_dmamap, 0, rxd->rx_dmamap->dm_mapsize, 2404 BUS_DMASYNC_PREREAD); 2405 rxd->rx_m = m; 2406 rxd->rx_desc->addr = htole64(rxd->rx_dmamap->dm_segs[0].ds_addr); 2407 return (0); 2408 } 2409 2410 static int 2411 alc_rxintr(struct alc_softc *sc) 2412 { 2413 struct ifnet *ifp = &sc->sc_ec.ec_if; 2414 struct rx_rdesc *rrd; 2415 uint32_t nsegs, status; 2416 int rr_cons, prog; 2417 2418 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_rr_ring_map, 0, 2419 sc->alc_cdata.alc_rr_ring_map->dm_mapsize, 2420 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2421 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_rx_ring_map, 0, 2422 sc->alc_cdata.alc_rx_ring_map->dm_mapsize, 2423 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2424 rr_cons = sc->alc_cdata.alc_rr_cons; 2425 for (prog = 0; (ifp->if_flags & IFF_RUNNING) != 0;) { 2426 rrd = &sc->alc_rdata.alc_rr_ring[rr_cons]; 2427 status = le32toh(rrd->status); 2428 if ((status & RRD_VALID) == 0) 2429 break; 2430 nsegs = RRD_RD_CNT(le32toh(rrd->rdinfo)); 2431 if (nsegs == 0) { 2432 /* This should not happen! */ 2433 if (alcdebug) 2434 printf("%s: unexpected segment count -- " 2435 "resetting\n", device_xname(sc->sc_dev)); 2436 return (EIO); 2437 } 2438 alc_rxeof(sc, rrd); 2439 /* Clear Rx return status. */ 2440 rrd->status = 0; 2441 ALC_DESC_INC(rr_cons, ALC_RR_RING_CNT); 2442 sc->alc_cdata.alc_rx_cons += nsegs; 2443 sc->alc_cdata.alc_rx_cons %= ALC_RR_RING_CNT; 2444 prog += nsegs; 2445 } 2446 2447 if (prog > 0) { 2448 /* Update the consumer index. */ 2449 sc->alc_cdata.alc_rr_cons = rr_cons; 2450 /* Sync Rx return descriptors. */ 2451 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_rr_ring_map, 0, 2452 sc->alc_cdata.alc_rr_ring_map->dm_mapsize, 2453 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2454 /* 2455 * Sync updated Rx descriptors such that controller see 2456 * modified buffer addresses. 2457 */ 2458 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_rx_ring_map, 0, 2459 sc->alc_cdata.alc_rx_ring_map->dm_mapsize, 2460 BUS_DMASYNC_PREWRITE); 2461 /* 2462 * Let controller know availability of new Rx buffers. 2463 * Since alc(4) use RXQ_CFG_RD_BURST_DEFAULT descriptors 2464 * it may be possible to update ALC_MBOX_RD0_PROD_IDX 2465 * only when Rx buffer pre-fetching is required. In 2466 * addition we already set ALC_RX_RD_FREE_THRESH to 2467 * RX_RD_FREE_THRESH_LO_DEFAULT descriptors. However 2468 * it still seems that pre-fetching needs more 2469 * experimentation. 2470 */ 2471 CSR_WRITE_4(sc, ALC_MBOX_RD0_PROD_IDX, 2472 sc->alc_cdata.alc_rx_cons); 2473 } 2474 2475 return (0); 2476 } 2477 2478 /* Receive a frame. */ 2479 static void 2480 alc_rxeof(struct alc_softc *sc, struct rx_rdesc *rrd) 2481 { 2482 struct ifnet *ifp = &sc->sc_ec.ec_if; 2483 struct alc_rxdesc *rxd; 2484 struct mbuf *mp, *m; 2485 uint32_t rdinfo, status; 2486 int count, nsegs, rx_cons; 2487 2488 status = le32toh(rrd->status); 2489 rdinfo = le32toh(rrd->rdinfo); 2490 rx_cons = RRD_RD_IDX(rdinfo); 2491 nsegs = RRD_RD_CNT(rdinfo); 2492 2493 sc->alc_cdata.alc_rxlen = RRD_BYTES(status); 2494 if (status & (RRD_ERR_SUM | RRD_ERR_LENGTH)) { 2495 /* 2496 * We want to pass the following frames to upper 2497 * layer regardless of error status of Rx return 2498 * ring. 2499 * 2500 * o IP/TCP/UDP checksum is bad. 2501 * o frame length and protocol specific length 2502 * does not match. 2503 * 2504 * Force network stack compute checksum for 2505 * errored frames. 2506 */ 2507 status |= RRD_TCP_UDPCSUM_NOK | RRD_IPCSUM_NOK; 2508 if ((status & (RRD_ERR_CRC | RRD_ERR_ALIGN | 2509 RRD_ERR_TRUNC | RRD_ERR_RUNT)) != 0) 2510 return; 2511 } 2512 2513 for (count = 0; count < nsegs; count++, 2514 ALC_DESC_INC(rx_cons, ALC_RX_RING_CNT)) { 2515 rxd = &sc->alc_cdata.alc_rxdesc[rx_cons]; 2516 mp = rxd->rx_m; 2517 /* Add a new receive buffer to the ring. */ 2518 if (alc_newbuf(sc, rxd, false) != 0) { 2519 ifp->if_iqdrops++; 2520 /* Reuse Rx buffers. */ 2521 if (sc->alc_cdata.alc_rxhead != NULL) 2522 m_freem(sc->alc_cdata.alc_rxhead); 2523 break; 2524 } 2525 2526 /* 2527 * Assume we've received a full sized frame. 2528 * Actual size is fixed when we encounter the end of 2529 * multi-segmented frame. 2530 */ 2531 mp->m_len = sc->alc_buf_size; 2532 2533 /* Chain received mbufs. */ 2534 if (sc->alc_cdata.alc_rxhead == NULL) { 2535 sc->alc_cdata.alc_rxhead = mp; 2536 sc->alc_cdata.alc_rxtail = mp; 2537 } else { 2538 m_remove_pkthdr(mp); 2539 sc->alc_cdata.alc_rxprev_tail = 2540 sc->alc_cdata.alc_rxtail; 2541 sc->alc_cdata.alc_rxtail->m_next = mp; 2542 sc->alc_cdata.alc_rxtail = mp; 2543 } 2544 2545 if (count == nsegs - 1) { 2546 /* Last desc. for this frame. */ 2547 m = sc->alc_cdata.alc_rxhead; 2548 KASSERT(m->m_flags & M_PKTHDR); 2549 /* 2550 * It seems that L1C/L2C controller has no way 2551 * to tell hardware to strip CRC bytes. 2552 */ 2553 m->m_pkthdr.len = 2554 sc->alc_cdata.alc_rxlen - ETHER_CRC_LEN; 2555 if (nsegs > 1) { 2556 /* Set last mbuf size. */ 2557 mp->m_len = sc->alc_cdata.alc_rxlen - 2558 (nsegs - 1) * sc->alc_buf_size; 2559 /* Remove the CRC bytes in chained mbufs. */ 2560 if (mp->m_len <= ETHER_CRC_LEN) { 2561 sc->alc_cdata.alc_rxtail = 2562 sc->alc_cdata.alc_rxprev_tail; 2563 sc->alc_cdata.alc_rxtail->m_len -= 2564 (ETHER_CRC_LEN - mp->m_len); 2565 sc->alc_cdata.alc_rxtail->m_next = NULL; 2566 m_freem(mp); 2567 } else { 2568 mp->m_len -= ETHER_CRC_LEN; 2569 } 2570 } else 2571 m->m_len = m->m_pkthdr.len; 2572 m_set_rcvif(m, ifp); 2573 #if NVLAN > 0 2574 /* 2575 * Due to hardware bugs, Rx checksum offloading 2576 * was intentionally disabled. 2577 */ 2578 if (status & RRD_VLAN_TAG) { 2579 u_int32_t vtag = RRD_VLAN(le32toh(rrd->vtag)); 2580 vlan_set_tag(m, ntohs(vtag)); 2581 } 2582 #endif 2583 2584 /* Pass it on. */ 2585 if_percpuq_enqueue(ifp->if_percpuq, m); 2586 } 2587 } 2588 /* Reset mbuf chains. */ 2589 ALC_RXCHAIN_RESET(sc); 2590 } 2591 2592 static void 2593 alc_tick(void *xsc) 2594 { 2595 struct alc_softc *sc = xsc; 2596 struct mii_data *mii = &sc->sc_miibus; 2597 int s; 2598 2599 s = splnet(); 2600 mii_tick(mii); 2601 alc_stats_update(sc); 2602 splx(s); 2603 2604 callout_schedule(&sc->sc_tick_ch, hz); 2605 } 2606 2607 static void 2608 alc_osc_reset(struct alc_softc *sc) 2609 { 2610 uint32_t reg; 2611 2612 reg = CSR_READ_4(sc, ALC_MISC3); 2613 reg &= ~MISC3_25M_BY_SW; 2614 reg |= MISC3_25M_NOTO_INTNL; 2615 CSR_WRITE_4(sc, ALC_MISC3, reg); 2616 2617 reg = CSR_READ_4(sc, ALC_MISC); 2618 if (AR816X_REV(sc->alc_rev) >= AR816X_REV_B0) { 2619 /* 2620 * Restore over-current protection default value. 2621 * This value could be reset by MAC reset. 2622 */ 2623 reg &= ~MISC_PSW_OCP_MASK; 2624 reg |= (MISC_PSW_OCP_DEFAULT << MISC_PSW_OCP_SHIFT); 2625 reg &= ~MISC_INTNLOSC_OPEN; 2626 CSR_WRITE_4(sc, ALC_MISC, reg); 2627 CSR_WRITE_4(sc, ALC_MISC, reg | MISC_INTNLOSC_OPEN); 2628 reg = CSR_READ_4(sc, ALC_MISC2); 2629 reg &= ~MISC2_CALB_START; 2630 CSR_WRITE_4(sc, ALC_MISC2, reg); 2631 CSR_WRITE_4(sc, ALC_MISC2, reg | MISC2_CALB_START); 2632 2633 } else { 2634 reg &= ~MISC_INTNLOSC_OPEN; 2635 /* Disable isolate for revision A devices. */ 2636 if (AR816X_REV(sc->alc_rev) <= AR816X_REV_A1) 2637 reg &= ~MISC_ISO_ENB; 2638 CSR_WRITE_4(sc, ALC_MISC, reg | MISC_INTNLOSC_OPEN); 2639 CSR_WRITE_4(sc, ALC_MISC, reg); 2640 } 2641 2642 DELAY(20); 2643 } 2644 2645 static void 2646 alc_reset(struct alc_softc *sc) 2647 { 2648 uint32_t pmcfg, reg; 2649 int i; 2650 2651 pmcfg = 0; 2652 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 2653 /* Reset workaround. */ 2654 CSR_WRITE_4(sc, ALC_MBOX_RD0_PROD_IDX, 1); 2655 if (AR816X_REV(sc->alc_rev) <= AR816X_REV_A1 && 2656 (sc->alc_rev & 0x01) != 0) { 2657 /* Disable L0s/L1s before reset. */ 2658 pmcfg = CSR_READ_4(sc, ALC_PM_CFG); 2659 if ((pmcfg & (PM_CFG_ASPM_L0S_ENB | PM_CFG_ASPM_L1_ENB)) 2660 != 0) { 2661 pmcfg &= ~(PM_CFG_ASPM_L0S_ENB | 2662 PM_CFG_ASPM_L1_ENB); 2663 CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg); 2664 } 2665 } 2666 } 2667 reg = CSR_READ_4(sc, ALC_MASTER_CFG); 2668 reg |= MASTER_OOB_DIS_OFF | MASTER_RESET; 2669 CSR_WRITE_4(sc, ALC_MASTER_CFG, reg); 2670 2671 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 2672 for (i = ALC_RESET_TIMEOUT; i > 0; i--) { 2673 DELAY(10); 2674 if (CSR_READ_4(sc, ALC_MBOX_RD0_PROD_IDX) == 0) 2675 break; 2676 } 2677 if (i == 0) 2678 printf("%s: MAC reset timeout!\n", device_xname(sc->sc_dev)); 2679 } 2680 for (i = ALC_RESET_TIMEOUT; i > 0; i--) { 2681 DELAY(10); 2682 if ((CSR_READ_4(sc, ALC_MASTER_CFG) & MASTER_RESET) == 0) 2683 break; 2684 } 2685 if (i == 0) 2686 printf("%s: master reset timeout!\n", device_xname(sc->sc_dev)); 2687 2688 for (i = ALC_RESET_TIMEOUT; i > 0; i--) { 2689 reg = CSR_READ_4(sc, ALC_IDLE_STATUS); 2690 if ((reg & (IDLE_STATUS_RXMAC | IDLE_STATUS_TXMAC | 2691 IDLE_STATUS_RXQ | IDLE_STATUS_TXQ)) == 0) 2692 break; 2693 DELAY(10); 2694 } 2695 if (i == 0) 2696 printf("%s: reset timeout(0x%08x)!\n", 2697 device_xname(sc->sc_dev), reg); 2698 2699 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 2700 if (AR816X_REV(sc->alc_rev) <= AR816X_REV_A1 && 2701 (sc->alc_rev & 0x01) != 0) { 2702 reg = CSR_READ_4(sc, ALC_MASTER_CFG); 2703 reg |= MASTER_CLK_SEL_DIS; 2704 CSR_WRITE_4(sc, ALC_MASTER_CFG, reg); 2705 /* Restore L0s/L1s config. */ 2706 if ((pmcfg & (PM_CFG_ASPM_L0S_ENB | PM_CFG_ASPM_L1_ENB)) 2707 != 0) 2708 CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg); 2709 } 2710 2711 alc_osc_reset(sc); 2712 reg = CSR_READ_4(sc, ALC_MISC3); 2713 reg &= ~MISC3_25M_BY_SW; 2714 reg |= MISC3_25M_NOTO_INTNL; 2715 CSR_WRITE_4(sc, ALC_MISC3, reg); 2716 reg = CSR_READ_4(sc, ALC_MISC); 2717 reg &= ~MISC_INTNLOSC_OPEN; 2718 if (AR816X_REV(sc->alc_rev) <= AR816X_REV_A1) 2719 reg &= ~MISC_ISO_ENB; 2720 CSR_WRITE_4(sc, ALC_MISC, reg); 2721 DELAY(20); 2722 } 2723 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0 || 2724 sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8152_B || 2725 sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8151_V2) 2726 CSR_WRITE_4(sc, ALC_SERDES_LOCK, 2727 CSR_READ_4(sc, ALC_SERDES_LOCK) | SERDES_MAC_CLK_SLOWDOWN | 2728 SERDES_PHY_CLK_SLOWDOWN); 2729 } 2730 2731 static int 2732 alc_init(struct ifnet *ifp) 2733 { 2734 2735 return alc_init_backend(ifp, true); 2736 } 2737 2738 static int 2739 alc_init_backend(struct ifnet *ifp, bool init) 2740 { 2741 struct alc_softc *sc = ifp->if_softc; 2742 struct mii_data *mii; 2743 uint8_t eaddr[ETHER_ADDR_LEN]; 2744 bus_addr_t paddr; 2745 uint32_t reg, rxf_hi, rxf_lo; 2746 int error; 2747 2748 /* 2749 * Cancel any pending I/O. 2750 */ 2751 alc_stop(ifp, 0); 2752 /* 2753 * Reset the chip to a known state. 2754 */ 2755 alc_reset(sc); 2756 2757 /* Initialize Rx descriptors. */ 2758 error = alc_init_rx_ring(sc, init); 2759 if (error != 0) { 2760 printf("%s: no memory for Rx buffers.\n", device_xname(sc->sc_dev)); 2761 alc_stop(ifp, 0); 2762 return (error); 2763 } 2764 alc_init_rr_ring(sc); 2765 alc_init_tx_ring(sc); 2766 alc_init_cmb(sc); 2767 alc_init_smb(sc); 2768 2769 /* Enable all clocks. */ 2770 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 2771 CSR_WRITE_4(sc, ALC_CLK_GATING_CFG, CLK_GATING_DMAW_ENB | 2772 CLK_GATING_DMAR_ENB | CLK_GATING_TXQ_ENB | 2773 CLK_GATING_RXQ_ENB | CLK_GATING_TXMAC_ENB | 2774 CLK_GATING_RXMAC_ENB); 2775 if (AR816X_REV(sc->alc_rev) >= AR816X_REV_B0) 2776 CSR_WRITE_4(sc, ALC_IDLE_DECISN_TIMER, 2777 IDLE_DECISN_TIMER_DEFAULT_1MS); 2778 } else 2779 CSR_WRITE_4(sc, ALC_CLK_GATING_CFG, 0); 2780 2781 2782 /* Reprogram the station address. */ 2783 memcpy(eaddr, CLLADDR(ifp->if_sadl), sizeof(eaddr)); 2784 CSR_WRITE_4(sc, ALC_PAR0, 2785 eaddr[2] << 24 | eaddr[3] << 16 | eaddr[4] << 8 | eaddr[5]); 2786 CSR_WRITE_4(sc, ALC_PAR1, eaddr[0] << 8 | eaddr[1]); 2787 /* 2788 * Clear WOL status and disable all WOL feature as WOL 2789 * would interfere Rx operation under normal environments. 2790 */ 2791 CSR_READ_4(sc, ALC_WOL_CFG); 2792 CSR_WRITE_4(sc, ALC_WOL_CFG, 0); 2793 /* Set Tx descriptor base addresses. */ 2794 paddr = sc->alc_rdata.alc_tx_ring_paddr; 2795 CSR_WRITE_4(sc, ALC_TX_BASE_ADDR_HI, ALC_ADDR_HI(paddr)); 2796 CSR_WRITE_4(sc, ALC_TDL_HEAD_ADDR_LO, ALC_ADDR_LO(paddr)); 2797 /* We don't use high priority ring. */ 2798 CSR_WRITE_4(sc, ALC_TDH_HEAD_ADDR_LO, 0); 2799 /* Set Tx descriptor counter. */ 2800 CSR_WRITE_4(sc, ALC_TD_RING_CNT, 2801 (ALC_TX_RING_CNT << TD_RING_CNT_SHIFT) & TD_RING_CNT_MASK); 2802 /* Set Rx descriptor base addresses. */ 2803 paddr = sc->alc_rdata.alc_rx_ring_paddr; 2804 CSR_WRITE_4(sc, ALC_RX_BASE_ADDR_HI, ALC_ADDR_HI(paddr)); 2805 CSR_WRITE_4(sc, ALC_RD0_HEAD_ADDR_LO, ALC_ADDR_LO(paddr)); 2806 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 2807 /* We use one Rx ring. */ 2808 CSR_WRITE_4(sc, ALC_RD1_HEAD_ADDR_LO, 0); 2809 CSR_WRITE_4(sc, ALC_RD2_HEAD_ADDR_LO, 0); 2810 CSR_WRITE_4(sc, ALC_RD3_HEAD_ADDR_LO, 0); 2811 } 2812 /* Set Rx descriptor counter. */ 2813 CSR_WRITE_4(sc, ALC_RD_RING_CNT, 2814 (ALC_RX_RING_CNT << RD_RING_CNT_SHIFT) & RD_RING_CNT_MASK); 2815 2816 /* 2817 * Let hardware split jumbo frames into alc_max_buf_sized chunks. 2818 * if it do not fit the buffer size. Rx return descriptor holds 2819 * a counter that indicates how many fragments were made by the 2820 * hardware. The buffer size should be multiple of 8 bytes. 2821 * Since hardware has limit on the size of buffer size, always 2822 * use the maximum value. 2823 * For strict-alignment architectures make sure to reduce buffer 2824 * size by 8 bytes to make room for alignment fixup. 2825 */ 2826 sc->alc_buf_size = RX_BUF_SIZE_MAX; 2827 CSR_WRITE_4(sc, ALC_RX_BUF_SIZE, sc->alc_buf_size); 2828 2829 paddr = sc->alc_rdata.alc_rr_ring_paddr; 2830 /* Set Rx return descriptor base addresses. */ 2831 CSR_WRITE_4(sc, ALC_RRD0_HEAD_ADDR_LO, ALC_ADDR_LO(paddr)); 2832 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 2833 /* We use one Rx return ring. */ 2834 CSR_WRITE_4(sc, ALC_RRD1_HEAD_ADDR_LO, 0); 2835 CSR_WRITE_4(sc, ALC_RRD2_HEAD_ADDR_LO, 0); 2836 CSR_WRITE_4(sc, ALC_RRD3_HEAD_ADDR_LO, 0); 2837 }\ 2838 /* Set Rx return descriptor counter. */ 2839 CSR_WRITE_4(sc, ALC_RRD_RING_CNT, 2840 (ALC_RR_RING_CNT << RRD_RING_CNT_SHIFT) & RRD_RING_CNT_MASK); 2841 paddr = sc->alc_rdata.alc_cmb_paddr; 2842 CSR_WRITE_4(sc, ALC_CMB_BASE_ADDR_LO, ALC_ADDR_LO(paddr)); 2843 paddr = sc->alc_rdata.alc_smb_paddr; 2844 CSR_WRITE_4(sc, ALC_SMB_BASE_ADDR_HI, ALC_ADDR_HI(paddr)); 2845 CSR_WRITE_4(sc, ALC_SMB_BASE_ADDR_LO, ALC_ADDR_LO(paddr)); 2846 2847 if (sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8152_B) { 2848 /* Reconfigure SRAM - Vendor magic. */ 2849 CSR_WRITE_4(sc, ALC_SRAM_RX_FIFO_LEN, 0x000002A0); 2850 CSR_WRITE_4(sc, ALC_SRAM_TX_FIFO_LEN, 0x00000100); 2851 CSR_WRITE_4(sc, ALC_SRAM_RX_FIFO_ADDR, 0x029F0000); 2852 CSR_WRITE_4(sc, ALC_SRAM_RD0_ADDR, 0x02BF02A0); 2853 CSR_WRITE_4(sc, ALC_SRAM_TX_FIFO_ADDR, 0x03BF02C0); 2854 CSR_WRITE_4(sc, ALC_SRAM_TD_ADDR, 0x03DF03C0); 2855 CSR_WRITE_4(sc, ALC_TXF_WATER_MARK, 0x00000000); 2856 CSR_WRITE_4(sc, ALC_RD_DMA_CFG, 0x00000000); 2857 } 2858 2859 /* Tell hardware that we're ready to load DMA blocks. */ 2860 CSR_WRITE_4(sc, ALC_DMA_BLOCK, DMA_BLOCK_LOAD); 2861 2862 /* Configure interrupt moderation timer. */ 2863 sc->alc_int_rx_mod = ALC_IM_RX_TIMER_DEFAULT; 2864 sc->alc_int_tx_mod = ALC_IM_TX_TIMER_DEFAULT; 2865 reg = ALC_USECS(sc->alc_int_rx_mod) << IM_TIMER_RX_SHIFT; 2866 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) 2867 reg |= ALC_USECS(sc->alc_int_tx_mod) << IM_TIMER_TX_SHIFT; 2868 CSR_WRITE_4(sc, ALC_IM_TIMER, reg); 2869 /* 2870 * We don't want to automatic interrupt clear as task queue 2871 * for the interrupt should know interrupt status. 2872 */ 2873 reg = CSR_READ_4(sc, ALC_MASTER_CFG); 2874 reg &= ~(MASTER_IM_RX_TIMER_ENB | MASTER_IM_TX_TIMER_ENB); 2875 reg |= MASTER_SA_TIMER_ENB; 2876 if (ALC_USECS(sc->alc_int_rx_mod) != 0) 2877 reg |= MASTER_IM_RX_TIMER_ENB; 2878 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0 && 2879 ALC_USECS(sc->alc_int_tx_mod) != 0) 2880 reg |= MASTER_IM_TX_TIMER_ENB; 2881 CSR_WRITE_4(sc, ALC_MASTER_CFG, reg); 2882 /* 2883 * Disable interrupt re-trigger timer. We don't want automatic 2884 * re-triggering of un-ACKed interrupts. 2885 */ 2886 CSR_WRITE_4(sc, ALC_INTR_RETRIG_TIMER, ALC_USECS(0)); 2887 /* Configure CMB. */ 2888 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 2889 CSR_WRITE_4(sc, ALC_CMB_TD_THRESH, ALC_TX_RING_CNT / 3); 2890 CSR_WRITE_4(sc, ALC_CMB_TX_TIMER, 2891 ALC_USECS(sc->alc_int_tx_mod)); 2892 } else { 2893 if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0) { 2894 CSR_WRITE_4(sc, ALC_CMB_TD_THRESH, 4); 2895 CSR_WRITE_4(sc, ALC_CMB_TX_TIMER, ALC_USECS(5000)); 2896 } else 2897 CSR_WRITE_4(sc, ALC_CMB_TX_TIMER, ALC_USECS(0)); 2898 } 2899 /* 2900 * Hardware can be configured to issue SMB interrupt based 2901 * on programmed interval. Since there is a callout that is 2902 * invoked for every hz in driver we use that instead of 2903 * relying on periodic SMB interrupt. 2904 */ 2905 CSR_WRITE_4(sc, ALC_SMB_STAT_TIMER, ALC_USECS(0)); 2906 /* Clear MAC statistics. */ 2907 alc_stats_clear(sc); 2908 2909 /* 2910 * Always use maximum frame size that controller can support. 2911 * Otherwise received frames that has larger frame length 2912 * than alc(4) MTU would be silently dropped in hardware. This 2913 * would make path-MTU discovery hard as sender wouldn't get 2914 * any responses from receiver. alc(4) supports 2915 * multi-fragmented frames on Rx path so it has no issue on 2916 * assembling fragmented frames. Using maximum frame size also 2917 * removes the need to reinitialize hardware when interface 2918 * MTU configuration was changed. 2919 * 2920 * Be conservative in what you do, be liberal in what you 2921 * accept from others - RFC 793. 2922 */ 2923 CSR_WRITE_4(sc, ALC_FRAME_SIZE, sc->alc_ident->max_framelen); 2924 2925 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 2926 /* Disable header split(?) */ 2927 CSR_WRITE_4(sc, ALC_HDS_CFG, 0); 2928 2929 /* Configure IPG/IFG parameters. */ 2930 CSR_WRITE_4(sc, ALC_IPG_IFG_CFG, 2931 ((IPG_IFG_IPGT_DEFAULT << IPG_IFG_IPGT_SHIFT) & 2932 IPG_IFG_IPGT_MASK) | 2933 ((IPG_IFG_MIFG_DEFAULT << IPG_IFG_MIFG_SHIFT) & 2934 IPG_IFG_MIFG_MASK) | 2935 ((IPG_IFG_IPG1_DEFAULT << IPG_IFG_IPG1_SHIFT) & 2936 IPG_IFG_IPG1_MASK) | 2937 ((IPG_IFG_IPG2_DEFAULT << IPG_IFG_IPG2_SHIFT) & 2938 IPG_IFG_IPG2_MASK)); 2939 /* Set parameters for half-duplex media. */ 2940 CSR_WRITE_4(sc, ALC_HDPX_CFG, 2941 ((HDPX_CFG_LCOL_DEFAULT << HDPX_CFG_LCOL_SHIFT) & 2942 HDPX_CFG_LCOL_MASK) | 2943 ((HDPX_CFG_RETRY_DEFAULT << HDPX_CFG_RETRY_SHIFT) & 2944 HDPX_CFG_RETRY_MASK) | HDPX_CFG_EXC_DEF_EN | 2945 ((HDPX_CFG_ABEBT_DEFAULT << HDPX_CFG_ABEBT_SHIFT) & 2946 HDPX_CFG_ABEBT_MASK) | 2947 ((HDPX_CFG_JAMIPG_DEFAULT << HDPX_CFG_JAMIPG_SHIFT) & 2948 HDPX_CFG_JAMIPG_MASK)); 2949 } 2950 2951 /* 2952 * Set TSO/checksum offload threshold. For frames that is 2953 * larger than this threshold, hardware wouldn't do 2954 * TSO/checksum offloading. 2955 */ 2956 reg = (sc->alc_ident->max_framelen >> TSO_OFFLOAD_THRESH_UNIT_SHIFT) & 2957 TSO_OFFLOAD_THRESH_MASK; 2958 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 2959 reg |= TSO_OFFLOAD_ERRLGPKT_DROP_ENB; 2960 CSR_WRITE_4(sc, ALC_TSO_OFFLOAD_THRESH, reg); 2961 /* Configure TxQ. */ 2962 reg = (alc_dma_burst[sc->alc_dma_rd_burst] << 2963 TXQ_CFG_TX_FIFO_BURST_SHIFT) & TXQ_CFG_TX_FIFO_BURST_MASK; 2964 if (sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8152_B || 2965 sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8152_B2) 2966 reg >>= 1; 2967 reg |= (TXQ_CFG_TD_BURST_DEFAULT << TXQ_CFG_TD_BURST_SHIFT) & 2968 TXQ_CFG_TD_BURST_MASK; 2969 reg |= TXQ_CFG_IP_OPTION_ENB | TXQ_CFG_8023_ENB; 2970 CSR_WRITE_4(sc, ALC_TXQ_CFG, reg | TXQ_CFG_ENHANCED_MODE); 2971 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 2972 reg = (TXQ_CFG_TD_BURST_DEFAULT << HQTD_CFG_Q1_BURST_SHIFT | 2973 TXQ_CFG_TD_BURST_DEFAULT << HQTD_CFG_Q2_BURST_SHIFT | 2974 TXQ_CFG_TD_BURST_DEFAULT << HQTD_CFG_Q3_BURST_SHIFT | 2975 HQTD_CFG_BURST_ENB); 2976 CSR_WRITE_4(sc, ALC_HQTD_CFG, reg); 2977 reg = WRR_PRI_RESTRICT_NONE; 2978 reg |= (WRR_PRI_DEFAULT << WRR_PRI0_SHIFT | 2979 WRR_PRI_DEFAULT << WRR_PRI1_SHIFT | 2980 WRR_PRI_DEFAULT << WRR_PRI2_SHIFT | 2981 WRR_PRI_DEFAULT << WRR_PRI3_SHIFT); 2982 CSR_WRITE_4(sc, ALC_WRR, reg); 2983 } else { 2984 /* Configure Rx free descriptor pre-fetching. */ 2985 CSR_WRITE_4(sc, ALC_RX_RD_FREE_THRESH, 2986 ((RX_RD_FREE_THRESH_HI_DEFAULT << 2987 RX_RD_FREE_THRESH_HI_SHIFT) & RX_RD_FREE_THRESH_HI_MASK) | 2988 ((RX_RD_FREE_THRESH_LO_DEFAULT << 2989 RX_RD_FREE_THRESH_LO_SHIFT) & RX_RD_FREE_THRESH_LO_MASK)); 2990 } 2991 2992 /* 2993 * Configure flow control parameters. 2994 * XON : 80% of Rx FIFO 2995 * XOFF : 30% of Rx FIFO 2996 */ 2997 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 2998 reg = CSR_READ_4(sc, ALC_SRAM_RX_FIFO_LEN); 2999 reg &= SRAM_RX_FIFO_LEN_MASK; 3000 reg *= 8; 3001 if (reg > 8 * 1024) 3002 reg -= RX_FIFO_PAUSE_816X_RSVD; 3003 else 3004 reg -= RX_BUF_SIZE_MAX; 3005 reg /= 8; 3006 CSR_WRITE_4(sc, ALC_RX_FIFO_PAUSE_THRESH, 3007 ((reg << RX_FIFO_PAUSE_THRESH_LO_SHIFT) & 3008 RX_FIFO_PAUSE_THRESH_LO_MASK) | 3009 (((RX_FIFO_PAUSE_816X_RSVD / 8) << 3010 RX_FIFO_PAUSE_THRESH_HI_SHIFT) & 3011 RX_FIFO_PAUSE_THRESH_HI_MASK)); 3012 } else if (sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8131 || 3013 sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8132) { 3014 reg = CSR_READ_4(sc, ALC_SRAM_RX_FIFO_LEN); 3015 rxf_hi = (reg * 8) / 10; 3016 rxf_lo = (reg * 3) / 10; 3017 CSR_WRITE_4(sc, ALC_RX_FIFO_PAUSE_THRESH, 3018 ((rxf_lo << RX_FIFO_PAUSE_THRESH_LO_SHIFT) & 3019 RX_FIFO_PAUSE_THRESH_LO_MASK) | 3020 ((rxf_hi << RX_FIFO_PAUSE_THRESH_HI_SHIFT) & 3021 RX_FIFO_PAUSE_THRESH_HI_MASK)); 3022 } 3023 3024 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 3025 /* Disable RSS until I understand L1C/L2C's RSS logic. */ 3026 CSR_WRITE_4(sc, ALC_RSS_IDT_TABLE0, 0); 3027 CSR_WRITE_4(sc, ALC_RSS_CPU, 0); 3028 } 3029 3030 /* Configure RxQ. */ 3031 reg = (RXQ_CFG_RD_BURST_DEFAULT << RXQ_CFG_RD_BURST_SHIFT) & 3032 RXQ_CFG_RD_BURST_MASK; 3033 reg |= RXQ_CFG_RSS_MODE_DIS; 3034 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 3035 reg |= (RXQ_CFG_816X_IDT_TBL_SIZE_DEFAULT << 3036 RXQ_CFG_816X_IDT_TBL_SIZE_SHIFT) & 3037 RXQ_CFG_816X_IDT_TBL_SIZE_MASK; 3038 if ((sc->alc_flags & ALC_FLAG_FASTETHER) == 0 && 3039 sc->alc_ident->deviceid != PCI_PRODUCT_ATTANSIC_AR8151_V2) 3040 reg |= RXQ_CFG_ASPM_THROUGHPUT_LIMIT_1M; 3041 CSR_WRITE_4(sc, ALC_RXQ_CFG, reg); 3042 3043 /* Configure DMA parameters. */ 3044 reg = DMA_CFG_OUT_ORDER | DMA_CFG_RD_REQ_PRI; 3045 reg |= sc->alc_rcb; 3046 if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0) 3047 reg |= DMA_CFG_CMB_ENB; 3048 if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0) 3049 reg |= DMA_CFG_SMB_ENB; 3050 else 3051 reg |= DMA_CFG_SMB_DIS; 3052 reg |= (sc->alc_dma_rd_burst & DMA_CFG_RD_BURST_MASK) << 3053 DMA_CFG_RD_BURST_SHIFT; 3054 reg |= (sc->alc_dma_wr_burst & DMA_CFG_WR_BURST_MASK) << 3055 DMA_CFG_WR_BURST_SHIFT; 3056 reg |= (DMA_CFG_RD_DELAY_CNT_DEFAULT << DMA_CFG_RD_DELAY_CNT_SHIFT) & 3057 DMA_CFG_RD_DELAY_CNT_MASK; 3058 reg |= (DMA_CFG_WR_DELAY_CNT_DEFAULT << DMA_CFG_WR_DELAY_CNT_SHIFT) & 3059 DMA_CFG_WR_DELAY_CNT_MASK; 3060 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 3061 switch (AR816X_REV(sc->alc_rev)) { 3062 case AR816X_REV_A0: 3063 case AR816X_REV_A1: 3064 reg |= DMA_CFG_RD_CHNL_SEL_1; 3065 break; 3066 case AR816X_REV_B0: 3067 /* FALLTHROUGH */ 3068 default: 3069 reg |= DMA_CFG_RD_CHNL_SEL_3; 3070 break; 3071 } 3072 } 3073 CSR_WRITE_4(sc, ALC_DMA_CFG, reg); 3074 3075 /* 3076 * Configure Tx/Rx MACs. 3077 * - Auto-padding for short frames. 3078 * - Enable CRC generation. 3079 * Actual reconfiguration of MAC for resolved speed/duplex 3080 * is followed after detection of link establishment. 3081 * AR813x/AR815x always does checksum computation regardless 3082 * of MAC_CFG_RXCSUM_ENB bit. Also the controller is known to 3083 * have bug in protocol field in Rx return structure so 3084 * these controllers can't handle fragmented frames. Disable 3085 * Rx checksum offloading until there is a newer controller 3086 * that has sane implementation. 3087 */ 3088 reg = MAC_CFG_TX_CRC_ENB | MAC_CFG_TX_AUTO_PAD | MAC_CFG_FULL_DUPLEX | 3089 ((MAC_CFG_PREAMBLE_DEFAULT << MAC_CFG_PREAMBLE_SHIFT) & 3090 MAC_CFG_PREAMBLE_MASK); 3091 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0 || 3092 sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8151 || 3093 sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8151_V2 || 3094 sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8152_B2) 3095 reg |= MAC_CFG_HASH_ALG_CRC32 | MAC_CFG_SPEED_MODE_SW; 3096 if ((sc->alc_flags & ALC_FLAG_FASTETHER) != 0) 3097 reg |= MAC_CFG_SPEED_10_100; 3098 else 3099 reg |= MAC_CFG_SPEED_1000; 3100 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 3101 3102 /* Set up the receive filter. */ 3103 alc_iff(sc); 3104 alc_rxvlan(sc); 3105 3106 /* Acknowledge all pending interrupts and clear it. */ 3107 CSR_WRITE_4(sc, ALC_INTR_MASK, ALC_INTRS); 3108 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0xFFFFFFFF); 3109 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0); 3110 3111 sc->alc_flags &= ~ALC_FLAG_LINK; 3112 /* Switch to the current media. */ 3113 mii = &sc->sc_miibus; 3114 mii_mediachg(mii); 3115 3116 callout_schedule(&sc->sc_tick_ch, hz); 3117 3118 ifp->if_flags |= IFF_RUNNING; 3119 ifp->if_flags &= ~IFF_OACTIVE; 3120 3121 return (0); 3122 } 3123 3124 static void 3125 alc_stop(struct ifnet *ifp, int disable) 3126 { 3127 struct alc_softc *sc = ifp->if_softc; 3128 struct alc_txdesc *txd; 3129 struct alc_rxdesc *rxd; 3130 uint32_t reg; 3131 int i; 3132 3133 callout_stop(&sc->sc_tick_ch); 3134 3135 /* 3136 * Mark the interface down and cancel the watchdog timer. 3137 */ 3138 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 3139 ifp->if_timer = 0; 3140 3141 sc->alc_flags &= ~ALC_FLAG_LINK; 3142 3143 alc_stats_update(sc); 3144 3145 mii_down(&sc->sc_miibus); 3146 3147 /* Disable interrupts. */ 3148 CSR_WRITE_4(sc, ALC_INTR_MASK, 0); 3149 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0xFFFFFFFF); 3150 3151 /* Disable DMA. */ 3152 reg = CSR_READ_4(sc, ALC_DMA_CFG); 3153 reg &= ~(DMA_CFG_CMB_ENB | DMA_CFG_SMB_ENB); 3154 reg |= DMA_CFG_SMB_DIS; 3155 CSR_WRITE_4(sc, ALC_DMA_CFG, reg); 3156 DELAY(1000); 3157 3158 /* Stop Rx/Tx MACs. */ 3159 alc_stop_mac(sc); 3160 3161 /* Disable interrupts which might be touched in taskq handler. */ 3162 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0xFFFFFFFF); 3163 3164 /* Disable L0s/L1s */ 3165 alc_aspm(sc, 0, IFM_UNKNOWN); 3166 3167 /* Reclaim Rx buffers that have been processed. */ 3168 if (sc->alc_cdata.alc_rxhead != NULL) 3169 m_freem(sc->alc_cdata.alc_rxhead); 3170 ALC_RXCHAIN_RESET(sc); 3171 /* 3172 * Free Tx/Rx mbufs still in the queues. 3173 */ 3174 for (i = 0; i < ALC_RX_RING_CNT; i++) { 3175 rxd = &sc->alc_cdata.alc_rxdesc[i]; 3176 if (rxd->rx_m != NULL) { 3177 bus_dmamap_sync(sc->sc_dmat, rxd->rx_dmamap, 0, 3178 rxd->rx_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 3179 bus_dmamap_unload(sc->sc_dmat, rxd->rx_dmamap); 3180 m_freem(rxd->rx_m); 3181 rxd->rx_m = NULL; 3182 } 3183 } 3184 for (i = 0; i < ALC_TX_RING_CNT; i++) { 3185 txd = &sc->alc_cdata.alc_txdesc[i]; 3186 if (txd->tx_m != NULL) { 3187 bus_dmamap_sync(sc->sc_dmat, txd->tx_dmamap, 0, 3188 txd->tx_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 3189 bus_dmamap_unload(sc->sc_dmat, txd->tx_dmamap); 3190 m_freem(txd->tx_m); 3191 txd->tx_m = NULL; 3192 } 3193 } 3194 } 3195 3196 static void 3197 alc_stop_mac(struct alc_softc *sc) 3198 { 3199 uint32_t reg; 3200 int i; 3201 3202 alc_stop_queue(sc); 3203 /* Disable Rx/Tx MAC. */ 3204 reg = CSR_READ_4(sc, ALC_MAC_CFG); 3205 if ((reg & (MAC_CFG_TX_ENB | MAC_CFG_RX_ENB)) != 0) { 3206 reg &= ~(MAC_CFG_TX_ENB | MAC_CFG_RX_ENB); 3207 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 3208 } 3209 for (i = ALC_TIMEOUT; i > 0; i--) { 3210 reg = CSR_READ_4(sc, ALC_IDLE_STATUS); 3211 if ((reg & (IDLE_STATUS_RXMAC | IDLE_STATUS_TXMAC)) == 0) 3212 break; 3213 DELAY(10); 3214 } 3215 if (i == 0) 3216 printf("%s: could not disable Rx/Tx MAC(0x%08x)!\n", 3217 device_xname(sc->sc_dev), reg); 3218 } 3219 3220 static void 3221 alc_start_queue(struct alc_softc *sc) 3222 { 3223 uint32_t qcfg[] = { 3224 0, 3225 RXQ_CFG_QUEUE0_ENB, 3226 RXQ_CFG_QUEUE0_ENB | RXQ_CFG_QUEUE1_ENB, 3227 RXQ_CFG_QUEUE0_ENB | RXQ_CFG_QUEUE1_ENB | RXQ_CFG_QUEUE2_ENB, 3228 RXQ_CFG_ENB 3229 }; 3230 uint32_t cfg; 3231 3232 /* Enable RxQ. */ 3233 cfg = CSR_READ_4(sc, ALC_RXQ_CFG); 3234 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 3235 cfg &= ~RXQ_CFG_ENB; 3236 cfg |= qcfg[1]; 3237 } else 3238 cfg |= RXQ_CFG_QUEUE0_ENB; 3239 CSR_WRITE_4(sc, ALC_RXQ_CFG, cfg); 3240 /* Enable TxQ. */ 3241 cfg = CSR_READ_4(sc, ALC_TXQ_CFG); 3242 cfg |= TXQ_CFG_ENB; 3243 CSR_WRITE_4(sc, ALC_TXQ_CFG, cfg); 3244 } 3245 3246 static void 3247 alc_stop_queue(struct alc_softc *sc) 3248 { 3249 uint32_t reg; 3250 int i; 3251 3252 /* Disable RxQ. */ 3253 reg = CSR_READ_4(sc, ALC_RXQ_CFG); 3254 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 3255 if ((reg & RXQ_CFG_ENB) != 0) { 3256 reg &= ~RXQ_CFG_ENB; 3257 CSR_WRITE_4(sc, ALC_RXQ_CFG, reg); 3258 } 3259 } else { 3260 if ((reg & RXQ_CFG_QUEUE0_ENB) != 0) { 3261 reg &= ~RXQ_CFG_QUEUE0_ENB; 3262 CSR_WRITE_4(sc, ALC_RXQ_CFG, reg); 3263 } 3264 } 3265 /* Disable TxQ. */ 3266 reg = CSR_READ_4(sc, ALC_TXQ_CFG); 3267 if ((reg & TXQ_CFG_ENB) != 0) { 3268 reg &= ~TXQ_CFG_ENB; 3269 CSR_WRITE_4(sc, ALC_TXQ_CFG, reg); 3270 } 3271 DELAY(40); 3272 for (i = ALC_TIMEOUT; i > 0; i--) { 3273 reg = CSR_READ_4(sc, ALC_IDLE_STATUS); 3274 if ((reg & (IDLE_STATUS_RXQ | IDLE_STATUS_TXQ)) == 0) 3275 break; 3276 DELAY(10); 3277 } 3278 if (i == 0) 3279 printf("%s: could not disable RxQ/TxQ (0x%08x)!\n", 3280 device_xname(sc->sc_dev), reg); 3281 } 3282 3283 static void 3284 alc_init_tx_ring(struct alc_softc *sc) 3285 { 3286 struct alc_ring_data *rd; 3287 struct alc_txdesc *txd; 3288 int i; 3289 3290 sc->alc_cdata.alc_tx_prod = 0; 3291 sc->alc_cdata.alc_tx_cons = 0; 3292 sc->alc_cdata.alc_tx_cnt = 0; 3293 3294 rd = &sc->alc_rdata; 3295 memset(rd->alc_tx_ring, 0, ALC_TX_RING_SZ); 3296 for (i = 0; i < ALC_TX_RING_CNT; i++) { 3297 txd = &sc->alc_cdata.alc_txdesc[i]; 3298 txd->tx_m = NULL; 3299 } 3300 3301 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_tx_ring_map, 0, 3302 sc->alc_cdata.alc_tx_ring_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 3303 } 3304 3305 static int 3306 alc_init_rx_ring(struct alc_softc *sc, bool init) 3307 { 3308 struct alc_ring_data *rd; 3309 struct alc_rxdesc *rxd; 3310 int i; 3311 3312 sc->alc_cdata.alc_rx_cons = ALC_RX_RING_CNT - 1; 3313 rd = &sc->alc_rdata; 3314 memset(rd->alc_rx_ring, 0, ALC_RX_RING_SZ); 3315 for (i = 0; i < ALC_RX_RING_CNT; i++) { 3316 rxd = &sc->alc_cdata.alc_rxdesc[i]; 3317 rxd->rx_m = NULL; 3318 rxd->rx_desc = &rd->alc_rx_ring[i]; 3319 if (alc_newbuf(sc, rxd, init) != 0) 3320 return (ENOBUFS); 3321 } 3322 3323 /* 3324 * Since controller does not update Rx descriptors, driver 3325 * does have to read Rx descriptors back so BUS_DMASYNC_PREWRITE 3326 * is enough to ensure coherence. 3327 */ 3328 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_rx_ring_map, 0, 3329 sc->alc_cdata.alc_rx_ring_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 3330 /* Let controller know availability of new Rx buffers. */ 3331 CSR_WRITE_4(sc, ALC_MBOX_RD0_PROD_IDX, sc->alc_cdata.alc_rx_cons); 3332 3333 return (0); 3334 } 3335 3336 static void 3337 alc_init_rr_ring(struct alc_softc *sc) 3338 { 3339 struct alc_ring_data *rd; 3340 3341 sc->alc_cdata.alc_rr_cons = 0; 3342 ALC_RXCHAIN_RESET(sc); 3343 3344 rd = &sc->alc_rdata; 3345 memset(rd->alc_rr_ring, 0, ALC_RR_RING_SZ); 3346 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_rr_ring_map, 0, 3347 sc->alc_cdata.alc_rr_ring_map->dm_mapsize, 3348 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3349 } 3350 3351 static void 3352 alc_init_cmb(struct alc_softc *sc) 3353 { 3354 struct alc_ring_data *rd; 3355 3356 rd = &sc->alc_rdata; 3357 memset(rd->alc_cmb, 0, ALC_CMB_SZ); 3358 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_cmb_map, 0, 3359 sc->alc_cdata.alc_cmb_map->dm_mapsize, 3360 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3361 } 3362 3363 static void 3364 alc_init_smb(struct alc_softc *sc) 3365 { 3366 struct alc_ring_data *rd; 3367 3368 rd = &sc->alc_rdata; 3369 memset(rd->alc_smb, 0, ALC_SMB_SZ); 3370 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_smb_map, 0, 3371 sc->alc_cdata.alc_smb_map->dm_mapsize, 3372 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3373 } 3374 3375 static void 3376 alc_rxvlan(struct alc_softc *sc) 3377 { 3378 uint32_t reg; 3379 3380 reg = CSR_READ_4(sc, ALC_MAC_CFG); 3381 if (sc->sc_ec.ec_capenable & ETHERCAP_VLAN_HWTAGGING) 3382 reg |= MAC_CFG_VLAN_TAG_STRIP; 3383 else 3384 reg &= ~MAC_CFG_VLAN_TAG_STRIP; 3385 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 3386 } 3387 3388 static void 3389 alc_iff(struct alc_softc *sc) 3390 { 3391 struct ethercom *ec = &sc->sc_ec; 3392 struct ifnet *ifp = &ec->ec_if; 3393 struct ether_multi *enm; 3394 struct ether_multistep step; 3395 uint32_t crc; 3396 uint32_t mchash[2]; 3397 uint32_t rxcfg; 3398 3399 rxcfg = CSR_READ_4(sc, ALC_MAC_CFG); 3400 rxcfg &= ~(MAC_CFG_ALLMULTI | MAC_CFG_BCAST | MAC_CFG_PROMISC); 3401 ifp->if_flags &= ~IFF_ALLMULTI; 3402 3403 /* 3404 * Always accept broadcast frames. 3405 */ 3406 rxcfg |= MAC_CFG_BCAST; 3407 3408 if (ifp->if_flags & IFF_PROMISC || ec->ec_multicnt > 0) { 3409 ifp->if_flags |= IFF_ALLMULTI; 3410 if (ifp->if_flags & IFF_PROMISC) 3411 rxcfg |= MAC_CFG_PROMISC; 3412 else 3413 rxcfg |= MAC_CFG_ALLMULTI; 3414 mchash[0] = mchash[1] = 0xFFFFFFFF; 3415 } else { 3416 /* Program new filter. */ 3417 memset(mchash, 0, sizeof(mchash)); 3418 3419 ETHER_FIRST_MULTI(step, ec, enm); 3420 while (enm != NULL) { 3421 crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 3422 mchash[crc >> 31] |= 1 << ((crc >> 26) & 0x1f); 3423 ETHER_NEXT_MULTI(step, enm); 3424 } 3425 } 3426 3427 CSR_WRITE_4(sc, ALC_MAR0, mchash[0]); 3428 CSR_WRITE_4(sc, ALC_MAR1, mchash[1]); 3429 CSR_WRITE_4(sc, ALC_MAC_CFG, rxcfg); 3430 } 3431 3432 MODULE(MODULE_CLASS_DRIVER, if_alc, "pci"); 3433 3434 #ifdef _MODULE 3435 #include "ioconf.c" 3436 #endif 3437 3438 static int 3439 if_alc_modcmd(modcmd_t cmd, void *opaque) 3440 { 3441 int error = 0; 3442 3443 switch (cmd) { 3444 case MODULE_CMD_INIT: 3445 #ifdef _MODULE 3446 error = config_init_component(cfdriver_ioconf_if_alc, 3447 cfattach_ioconf_if_alc, cfdata_ioconf_if_alc); 3448 #endif 3449 return error; 3450 case MODULE_CMD_FINI: 3451 #ifdef _MODULE 3452 error = config_fini_component(cfdriver_ioconf_if_alc, 3453 cfattach_ioconf_if_alc, cfdata_ioconf_if_alc); 3454 #endif 3455 return error; 3456 default: 3457 return ENOTTY; 3458 } 3459 } 3460
Indexes created Fri Sep 26 08:10:20 GMT 2025