if_alc.c revision 1.30
1 /* $NetBSD: if_alc.c,v 1.30 2019/01/22 03:42:27 msaitoh Exp $ */ 2 /* $OpenBSD: if_alc.c,v 1.1 2009/08/08 09:31:13 kevlo Exp $ */ 3 /*- 4 * Copyright (c) 2009, Pyun YongHyeon <yongari (at) FreeBSD.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice unmodified, this list of conditions, and the following 12 * disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 /* Driver for Atheros AR813x/AR815x PCIe Ethernet. */ 31 32 #ifdef _KERNEL_OPT 33 #include "vlan.h" 34 #endif 35 36 #include <sys/param.h> 37 #include <sys/proc.h> 38 #include <sys/endian.h> 39 #include <sys/systm.h> 40 #include <sys/types.h> 41 #include <sys/sockio.h> 42 #include <sys/mbuf.h> 43 #include <sys/queue.h> 44 #include <sys/kernel.h> 45 #include <sys/device.h> 46 #include <sys/callout.h> 47 #include <sys/socket.h> 48 #include <sys/module.h> 49 50 #include <sys/bus.h> 51 52 #include <net/bpf.h> 53 #include <net/if.h> 54 #include <net/if_dl.h> 55 #include <net/if_llc.h> 56 #include <net/if_media.h> 57 #include <net/if_ether.h> 58 59 #ifdef INET 60 #include <netinet/in.h> 61 #include <netinet/in_systm.h> 62 #include <netinet/in_var.h> 63 #include <netinet/ip.h> 64 #endif 65 66 #include <net/if_types.h> 67 #include <net/if_vlanvar.h> 68 69 #include <dev/mii/mii.h> 70 #include <dev/mii/miivar.h> 71 72 #include <dev/pci/pcireg.h> 73 #include <dev/pci/pcivar.h> 74 #include <dev/pci/pcidevs.h> 75 76 #include <dev/pci/if_alcreg.h> 77 78 /* 79 * Devices supported by this driver. 80 */ 81 static struct alc_ident alc_ident_table[] = { 82 { PCI_VENDOR_ATTANSIC, PCI_PRODUCT_ATTANSIC_AR8131, 9 * 1024, 83 "Atheros AR8131 PCIe Gigabit Ethernet" }, 84 { PCI_VENDOR_ATTANSIC, PCI_PRODUCT_ATTANSIC_AR8132, 9 * 1024, 85 "Atheros AR8132 PCIe Fast Ethernet" }, 86 { PCI_VENDOR_ATTANSIC, PCI_PRODUCT_ATTANSIC_AR8151, 6 * 1024, 87 "Atheros AR8151 v1.0 PCIe Gigabit Ethernet" }, 88 { PCI_VENDOR_ATTANSIC, PCI_PRODUCT_ATTANSIC_AR8151_V2, 6 * 1024, 89 "Atheros AR8151 v2.0 PCIe Gigabit Ethernet" }, 90 { PCI_VENDOR_ATTANSIC, PCI_PRODUCT_ATTANSIC_AR8152_B, 6 * 1024, 91 "Atheros AR8152 v1.1 PCIe Fast Ethernet" }, 92 { PCI_VENDOR_ATTANSIC, PCI_PRODUCT_ATTANSIC_AR8152_B2, 6 * 1024, 93 "Atheros AR8152 v2.0 PCIe Fast Ethernet" }, 94 { PCI_VENDOR_ATTANSIC, PCI_PRODUCT_ATTANSIC_AR8161, 9 * 1024, 95 "Atheros AR8161 PCIe Gigabit Ethernet" }, 96 { PCI_VENDOR_ATTANSIC, PCI_PRODUCT_ATTANSIC_AR8162, 9 * 1024, 97 "Atheros AR8162 PCIe Fast Ethernet" }, 98 { PCI_VENDOR_ATTANSIC, PCI_PRODUCT_ATTANSIC_AR8171, 9 * 1024, 99 "Atheros AR8171 PCIe Gigabit Ethernet" }, 100 { PCI_VENDOR_ATTANSIC, PCI_PRODUCT_ATTANSIC_AR8172, 9 * 1024, 101 "Atheros AR8172 PCIe Fast Ethernet" }, 102 { PCI_VENDOR_ATTANSIC, PCI_PRODUCT_ATTANSIC_E2200, 9 * 1024, 103 "Killer E2200 Gigabit Ethernet" }, 104 { 0, 0, 0, NULL }, 105 }; 106 107 static int alc_match(device_t, cfdata_t, void *); 108 static void alc_attach(device_t, device_t, void *); 109 static int alc_detach(device_t, int); 110 111 static int alc_init(struct ifnet *); 112 static int alc_init_backend(struct ifnet *, bool); 113 static void alc_start(struct ifnet *); 114 static int alc_ioctl(struct ifnet *, u_long, void *); 115 static void alc_watchdog(struct ifnet *); 116 static int alc_mediachange(struct ifnet *); 117 static void alc_mediastatus(struct ifnet *, struct ifmediareq *); 118 119 static void alc_aspm(struct alc_softc *, int, int); 120 static void alc_aspm_813x(struct alc_softc *, int); 121 static void alc_aspm_816x(struct alc_softc *, int); 122 static void alc_disable_l0s_l1(struct alc_softc *); 123 static int alc_dma_alloc(struct alc_softc *); 124 static void alc_dma_free(struct alc_softc *); 125 static void alc_dsp_fixup(struct alc_softc *, int); 126 static int alc_encap(struct alc_softc *, struct mbuf **); 127 static struct alc_ident * 128 alc_find_ident(struct pci_attach_args *); 129 static void alc_get_macaddr(struct alc_softc *); 130 static void alc_get_macaddr_813x(struct alc_softc *); 131 static void alc_get_macaddr_816x(struct alc_softc *); 132 static void alc_get_macaddr_par(struct alc_softc *); 133 static void alc_init_cmb(struct alc_softc *); 134 static void alc_init_rr_ring(struct alc_softc *); 135 static int alc_init_rx_ring(struct alc_softc *, bool); 136 static void alc_init_smb(struct alc_softc *); 137 static void alc_init_tx_ring(struct alc_softc *); 138 static int alc_intr(void *); 139 static void alc_mac_config(struct alc_softc *); 140 static int alc_mii_readreg_813x(struct alc_softc *, int, int, uint16_t *); 141 static int alc_mii_readreg_816x(struct alc_softc *, int, int, uint16_t *); 142 static int alc_mii_writereg_813x(struct alc_softc *, int, int, uint16_t); 143 static int alc_mii_writereg_816x(struct alc_softc *, int, int, uint16_t); 144 static int alc_miibus_readreg(device_t, int, int, uint16_t *); 145 static void alc_miibus_statchg(struct ifnet *); 146 static int alc_miibus_writereg(device_t, int, int, uint16_t); 147 static int alc_miidbg_readreg(struct alc_softc *, int, uint16_t *); 148 static int alc_miidbg_writereg(struct alc_softc *, int, uint16_t); 149 static int alc_miiext_readreg(struct alc_softc *, int, int, uint16_t *); 150 static int alc_miiext_writereg(struct alc_softc *, int, int, uint16_t); 151 static int alc_newbuf(struct alc_softc *, struct alc_rxdesc *, bool); 152 static void alc_phy_down(struct alc_softc *); 153 static void alc_phy_reset(struct alc_softc *); 154 static void alc_phy_reset_813x(struct alc_softc *); 155 static void alc_phy_reset_816x(struct alc_softc *); 156 static void alc_reset(struct alc_softc *); 157 static void alc_rxeof(struct alc_softc *, struct rx_rdesc *); 158 static int alc_rxintr(struct alc_softc *); 159 static void alc_iff(struct alc_softc *); 160 static void alc_rxvlan(struct alc_softc *); 161 static void alc_start_queue(struct alc_softc *); 162 static void alc_stats_clear(struct alc_softc *); 163 static void alc_stats_update(struct alc_softc *); 164 static void alc_stop(struct ifnet *, int); 165 static void alc_stop_mac(struct alc_softc *); 166 static void alc_stop_queue(struct alc_softc *); 167 static void alc_tick(void *); 168 static void alc_txeof(struct alc_softc *); 169 170 uint32_t alc_dma_burst[] = { 128, 256, 512, 1024, 2048, 4096, 0 }; 171 172 CFATTACH_DECL_NEW(alc, sizeof(struct alc_softc), 173 alc_match, alc_attach, alc_detach, NULL); 174 175 int alcdebug = 0; 176 #define DPRINTF(x) do { if (alcdebug) printf x; } while (0) 177 178 #define ETHER_ALIGN 2 179 #define ALC_CSUM_FEATURES (M_CSUM_TCPv4 | M_CSUM_UDPv4) 180 181 static int 182 alc_miibus_readreg(device_t dev, int phy, int reg, uint16_t *val) 183 { 184 struct alc_softc *sc = device_private(dev); 185 int v; 186 187 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 188 v = alc_mii_readreg_816x(sc, phy, reg, val); 189 else 190 v = alc_mii_readreg_813x(sc, phy, reg, val); 191 return (v); 192 } 193 194 static int 195 alc_mii_readreg_813x(struct alc_softc *sc, int phy, int reg, uint16_t *val) 196 { 197 uint32_t v; 198 int i; 199 200 if (phy != sc->alc_phyaddr) 201 return -1; 202 203 /* 204 * For AR8132 fast ethernet controller, do not report 1000baseT 205 * capability to mii(4). Even though AR8132 uses the same 206 * model/revision number of F1 gigabit PHY, the PHY has no 207 * ability to establish 1000baseT link. 208 */ 209 if ((sc->alc_flags & ALC_FLAG_FASTETHER) != 0 && reg == MII_EXTSR) { 210 *val = 0; 211 return 0; 212 } 213 214 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ | 215 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); 216 for (i = ALC_PHY_TIMEOUT; i > 0; i--) { 217 DELAY(5); 218 v = CSR_READ_4(sc, ALC_MDIO); 219 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) 220 break; 221 } 222 223 if (i == 0) { 224 printf("%s: phy read timeout: phy %d, reg %d\n", 225 device_xname(sc->sc_dev), phy, reg); 226 return ETIMEDOUT; 227 } 228 229 *val = (v & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT; 230 return 0; 231 } 232 233 static int 234 alc_mii_readreg_816x(struct alc_softc *sc, int phy, int reg, uint16_t *val) 235 { 236 uint32_t clk, v; 237 int i; 238 239 if (phy != sc->alc_phyaddr) 240 return -1; 241 242 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) 243 clk = MDIO_CLK_25_128; 244 else 245 clk = MDIO_CLK_25_4; 246 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ | 247 MDIO_SUP_PREAMBLE | clk | MDIO_REG_ADDR(reg)); 248 for (i = ALC_PHY_TIMEOUT; i > 0; i--) { 249 DELAY(5); 250 v = CSR_READ_4(sc, ALC_MDIO); 251 if ((v & MDIO_OP_BUSY) == 0) 252 break; 253 } 254 255 if (i == 0) { 256 printf("%s: phy read timeout: phy %d, reg %d\n", 257 device_xname(sc->sc_dev), phy, reg); 258 return ETIMEDOUT; 259 } 260 261 *val = (v & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT; 262 return 0; 263 } 264 265 static int 266 alc_miibus_writereg(device_t dev, int phy, int reg, uint16_t val) 267 { 268 struct alc_softc *sc = device_private(dev); 269 int rv; 270 271 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 272 rv = alc_mii_writereg_816x(sc, phy, reg, val); 273 else 274 rv = alc_mii_writereg_813x(sc, phy, reg, val); 275 276 return rv; 277 } 278 279 static int 280 alc_mii_writereg_813x(struct alc_softc *sc, int phy, int reg, uint16_t val) 281 { 282 uint32_t v; 283 int i; 284 285 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE | 286 (val & MDIO_DATA_MASK) << MDIO_DATA_SHIFT | 287 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); 288 for (i = ALC_PHY_TIMEOUT; i > 0; i--) { 289 DELAY(5); 290 v = CSR_READ_4(sc, ALC_MDIO); 291 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) 292 break; 293 } 294 295 if (i == 0) { 296 printf("%s: phy write timeout: phy %d, reg %d\n", 297 device_xname(sc->sc_dev), phy, reg); 298 return ETIMEDOUT; 299 } 300 301 return 0; 302 } 303 304 static int 305 alc_mii_writereg_816x(struct alc_softc *sc, int phy, int reg, uint16_t val) 306 { 307 uint32_t clk, v; 308 int i; 309 310 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) 311 clk = MDIO_CLK_25_128; 312 else 313 clk = MDIO_CLK_25_4; 314 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE | 315 ((val & MDIO_DATA_MASK) << MDIO_DATA_SHIFT) | MDIO_REG_ADDR(reg) | 316 MDIO_SUP_PREAMBLE | clk); 317 for (i = ALC_PHY_TIMEOUT; i > 0; i--) { 318 DELAY(5); 319 v = CSR_READ_4(sc, ALC_MDIO); 320 if ((v & MDIO_OP_BUSY) == 0) 321 break; 322 } 323 324 if (i == 0) { 325 printf("%s: phy write timeout: phy %d, reg %d\n", 326 device_xname(sc->sc_dev), phy, reg); 327 return ETIMEDOUT; 328 } 329 330 return 0; 331 } 332 333 static void 334 alc_miibus_statchg(struct ifnet *ifp) 335 { 336 struct alc_softc *sc = ifp->if_softc; 337 struct mii_data *mii = &sc->sc_miibus; 338 uint32_t reg; 339 340 if ((ifp->if_flags & IFF_RUNNING) == 0) 341 return; 342 343 sc->alc_flags &= ~ALC_FLAG_LINK; 344 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 345 (IFM_ACTIVE | IFM_AVALID)) { 346 switch (IFM_SUBTYPE(mii->mii_media_active)) { 347 case IFM_10_T: 348 case IFM_100_TX: 349 sc->alc_flags |= ALC_FLAG_LINK; 350 break; 351 case IFM_1000_T: 352 if ((sc->alc_flags & ALC_FLAG_FASTETHER) == 0) 353 sc->alc_flags |= ALC_FLAG_LINK; 354 break; 355 default: 356 break; 357 } 358 } 359 /* Stop Rx/Tx MACs. */ 360 alc_stop_mac(sc); 361 362 /* Program MACs with resolved speed/duplex/flow-control. */ 363 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) { 364 alc_start_queue(sc); 365 alc_mac_config(sc); 366 /* Re-enable Tx/Rx MACs. */ 367 reg = CSR_READ_4(sc, ALC_MAC_CFG); 368 reg |= MAC_CFG_TX_ENB | MAC_CFG_RX_ENB; 369 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 370 } 371 alc_aspm(sc, 0, IFM_SUBTYPE(mii->mii_media_active)); 372 alc_dsp_fixup(sc, IFM_SUBTYPE(mii->mii_media_active)); 373 } 374 375 static int 376 alc_miidbg_readreg(struct alc_softc *sc, int reg, uint16_t *val) 377 { 378 int rv; 379 380 rv = alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, ALC_MII_DBG_ADDR, 381 reg); 382 if (rv != 0) 383 return rv; 384 385 return (alc_miibus_readreg(sc->sc_dev, sc->alc_phyaddr, 386 ALC_MII_DBG_DATA, val)); 387 } 388 389 static int 390 alc_miidbg_writereg(struct alc_softc *sc, int reg, uint16_t val) 391 { 392 int rv; 393 394 rv = alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, ALC_MII_DBG_ADDR, 395 reg); 396 if (rv != 0) 397 return rv; 398 399 rv = alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, ALC_MII_DBG_DATA, 400 val); 401 402 return rv; 403 } 404 405 static int 406 alc_miiext_readreg(struct alc_softc *sc, int devaddr, int reg, uint16_t *val) 407 { 408 uint32_t clk, v; 409 int i; 410 411 CSR_WRITE_4(sc, ALC_EXT_MDIO, EXT_MDIO_REG(reg) | 412 EXT_MDIO_DEVADDR(devaddr)); 413 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) 414 clk = MDIO_CLK_25_128; 415 else 416 clk = MDIO_CLK_25_4; 417 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ | 418 MDIO_SUP_PREAMBLE | clk | MDIO_MODE_EXT); 419 for (i = ALC_PHY_TIMEOUT; i > 0; i--) { 420 DELAY(5); 421 v = CSR_READ_4(sc, ALC_MDIO); 422 if ((v & MDIO_OP_BUSY) == 0) 423 break; 424 } 425 426 if (i == 0) { 427 printf("%s: phy ext read timeout: %d\n", 428 device_xname(sc->sc_dev), reg); 429 return ETIMEDOUT; 430 } 431 432 *val = (v & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT; 433 return 0; 434 } 435 436 static int 437 alc_miiext_writereg(struct alc_softc *sc, int devaddr, int reg, uint16_t val) 438 { 439 uint32_t clk, v; 440 int i; 441 442 CSR_WRITE_4(sc, ALC_EXT_MDIO, EXT_MDIO_REG(reg) | 443 EXT_MDIO_DEVADDR(devaddr)); 444 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) 445 clk = MDIO_CLK_25_128; 446 else 447 clk = MDIO_CLK_25_4; 448 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE | 449 ((val & MDIO_DATA_MASK) << MDIO_DATA_SHIFT) | 450 MDIO_SUP_PREAMBLE | clk | MDIO_MODE_EXT); 451 for (i = ALC_PHY_TIMEOUT; i > 0; i--) { 452 DELAY(5); 453 v = CSR_READ_4(sc, ALC_MDIO); 454 if ((v & MDIO_OP_BUSY) == 0) 455 break; 456 } 457 458 if (i == 0) { 459 printf("%s: phy ext write timeout: reg %d\n", 460 device_xname(sc->sc_dev), reg); 461 return ETIMEDOUT; 462 } 463 464 return 0; 465 } 466 467 static void 468 alc_dsp_fixup(struct alc_softc *sc, int media) 469 { 470 uint16_t agc, len, val; 471 472 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 473 return; 474 if (AR816X_REV(sc->alc_rev) >= AR816X_REV_C0) 475 return; 476 477 /* 478 * Vendor PHY magic. 479 * 1000BT/AZ, wrong cable length 480 */ 481 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) { 482 alc_miiext_readreg(sc, MII_EXT_PCS, MII_EXT_CLDCTL6, &len); 483 len = (len >> EXT_CLDCTL6_CAB_LEN_SHIFT) & 484 EXT_CLDCTL6_CAB_LEN_MASK; 485 /* XXX: used to be (alc >> shift) & mask which is 0 */ 486 alc_miidbg_readreg(sc, MII_DBG_AGC, &agc); 487 agc &= DBG_AGC_2_VGA_MASK; 488 agc >>= DBG_AGC_2_VGA_SHIFT; 489 if ((media == IFM_1000_T && len > EXT_CLDCTL6_CAB_LEN_SHORT1G && 490 agc > DBG_AGC_LONG1G_LIMT) || 491 (media == IFM_100_TX && len > DBG_AGC_LONG100M_LIMT && 492 agc > DBG_AGC_LONG1G_LIMT)) { 493 alc_miidbg_writereg(sc, MII_DBG_AZ_ANADECT, 494 DBG_AZ_ANADECT_LONG); 495 alc_miiext_readreg(sc, MII_EXT_ANEG, 496 MII_EXT_ANEG_AFE, &val); 497 val |= ANEG_AFEE_10BT_100M_TH; 498 alc_miiext_writereg(sc, MII_EXT_ANEG, MII_EXT_ANEG_AFE, 499 val); 500 } else { 501 alc_miidbg_writereg(sc, MII_DBG_AZ_ANADECT, 502 DBG_AZ_ANADECT_DEFAULT); 503 alc_miiext_readreg(sc, MII_EXT_ANEG, 504 MII_EXT_ANEG_AFE, &val); 505 val &= ~ANEG_AFEE_10BT_100M_TH; 506 alc_miiext_writereg(sc, MII_EXT_ANEG, MII_EXT_ANEG_AFE, 507 val); 508 } 509 if ((sc->alc_flags & ALC_FLAG_LINK_WAR) != 0 && 510 AR816X_REV(sc->alc_rev) == AR816X_REV_B0) { 511 if (media == IFM_1000_T) { 512 /* 513 * Giga link threshold, raise the tolerance of 514 * noise 50%. 515 */ 516 alc_miidbg_readreg(sc, MII_DBG_MSE20DB, &val); 517 val &= ~DBG_MSE20DB_TH_MASK; 518 val |= (DBG_MSE20DB_TH_HI << 519 DBG_MSE20DB_TH_SHIFT); 520 alc_miidbg_writereg(sc, MII_DBG_MSE20DB, val); 521 } else if (media == IFM_100_TX) 522 alc_miidbg_writereg(sc, MII_DBG_MSE16DB, 523 DBG_MSE16DB_UP); 524 } 525 } else { 526 alc_miiext_readreg(sc, MII_EXT_ANEG, MII_EXT_ANEG_AFE, &val); 527 val &= ~ANEG_AFEE_10BT_100M_TH; 528 alc_miiext_writereg(sc, MII_EXT_ANEG, MII_EXT_ANEG_AFE, val); 529 if ((sc->alc_flags & ALC_FLAG_LINK_WAR) != 0 && 530 AR816X_REV(sc->alc_rev) == AR816X_REV_B0) { 531 alc_miidbg_writereg(sc, MII_DBG_MSE16DB, 532 DBG_MSE16DB_DOWN); 533 alc_miidbg_readreg(sc, MII_DBG_MSE20DB, &val); 534 val &= ~DBG_MSE20DB_TH_MASK; 535 val |= (DBG_MSE20DB_TH_DEFAULT << DBG_MSE20DB_TH_SHIFT); 536 alc_miidbg_writereg(sc, MII_DBG_MSE20DB, val); 537 } 538 } 539 } 540 541 static void 542 alc_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 543 { 544 struct alc_softc *sc = ifp->if_softc; 545 struct mii_data *mii = &sc->sc_miibus; 546 547 if ((ifp->if_flags & IFF_UP) == 0) 548 return; 549 550 mii_pollstat(mii); 551 ifmr->ifm_status = mii->mii_media_status; 552 ifmr->ifm_active = mii->mii_media_active; 553 } 554 555 static int 556 alc_mediachange(struct ifnet *ifp) 557 { 558 struct alc_softc *sc = ifp->if_softc; 559 struct mii_data *mii = &sc->sc_miibus; 560 int error; 561 562 if (mii->mii_instance != 0) { 563 struct mii_softc *miisc; 564 565 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 566 mii_phy_reset(miisc); 567 } 568 error = mii_mediachg(mii); 569 570 return (error); 571 } 572 573 static struct alc_ident * 574 alc_find_ident(struct pci_attach_args *pa) 575 { 576 struct alc_ident *ident; 577 uint16_t vendor, devid; 578 579 vendor = PCI_VENDOR(pa->pa_id); 580 devid = PCI_PRODUCT(pa->pa_id); 581 for (ident = alc_ident_table; ident->name != NULL; ident++) { 582 if (vendor == ident->vendorid && devid == ident->deviceid) 583 return (ident); 584 } 585 586 return (NULL); 587 } 588 589 static int 590 alc_match(device_t dev, cfdata_t match, void *aux) 591 { 592 struct pci_attach_args *pa = aux; 593 594 return alc_find_ident(pa) != NULL; 595 } 596 597 static void 598 alc_get_macaddr(struct alc_softc *sc) 599 { 600 601 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 602 alc_get_macaddr_816x(sc); 603 else 604 alc_get_macaddr_813x(sc); 605 } 606 607 static void 608 alc_get_macaddr_813x(struct alc_softc *sc) 609 { 610 uint32_t opt; 611 uint16_t val; 612 int eeprom, i; 613 614 eeprom = 0; 615 opt = CSR_READ_4(sc, ALC_OPT_CFG); 616 if ((CSR_READ_4(sc, ALC_MASTER_CFG) & MASTER_OTP_SEL) != 0 && 617 (CSR_READ_4(sc, ALC_TWSI_DEBUG) & TWSI_DEBUG_DEV_EXIST) != 0) { 618 /* 619 * EEPROM found, let TWSI reload EEPROM configuration. 620 * This will set ethernet address of controller. 621 */ 622 eeprom++; 623 switch (sc->alc_ident->deviceid) { 624 case PCI_PRODUCT_ATTANSIC_AR8131: 625 case PCI_PRODUCT_ATTANSIC_AR8132: 626 if ((opt & OPT_CFG_CLK_ENB) == 0) { 627 opt |= OPT_CFG_CLK_ENB; 628 CSR_WRITE_4(sc, ALC_OPT_CFG, opt); 629 CSR_READ_4(sc, ALC_OPT_CFG); 630 DELAY(1000); 631 } 632 break; 633 case PCI_PRODUCT_ATTANSIC_AR8151: 634 case PCI_PRODUCT_ATTANSIC_AR8151_V2: 635 case PCI_PRODUCT_ATTANSIC_AR8152_B: 636 case PCI_PRODUCT_ATTANSIC_AR8152_B2: 637 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 638 ALC_MII_DBG_ADDR, 0x00); 639 alc_miibus_readreg(sc->sc_dev, sc->alc_phyaddr, 640 ALC_MII_DBG_DATA, &val); 641 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 642 ALC_MII_DBG_DATA, val & 0xFF7F); 643 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 644 ALC_MII_DBG_ADDR, 0x3B); 645 alc_miibus_readreg(sc->sc_dev, sc->alc_phyaddr, 646 ALC_MII_DBG_DATA, &val); 647 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 648 ALC_MII_DBG_DATA, val | 0x0008); 649 DELAY(20); 650 break; 651 } 652 653 CSR_WRITE_4(sc, ALC_LTSSM_ID_CFG, 654 CSR_READ_4(sc, ALC_LTSSM_ID_CFG) & ~LTSSM_ID_WRO_ENB); 655 CSR_WRITE_4(sc, ALC_WOL_CFG, 0); 656 CSR_READ_4(sc, ALC_WOL_CFG); 657 658 CSR_WRITE_4(sc, ALC_TWSI_CFG, CSR_READ_4(sc, ALC_TWSI_CFG) | 659 TWSI_CFG_SW_LD_START); 660 for (i = 100; i > 0; i--) { 661 DELAY(1000); 662 if ((CSR_READ_4(sc, ALC_TWSI_CFG) & 663 TWSI_CFG_SW_LD_START) == 0) 664 break; 665 } 666 if (i == 0) 667 printf("%s: reloading EEPROM timeout!\n", 668 device_xname(sc->sc_dev)); 669 } else { 670 if (alcdebug) 671 printf("%s: EEPROM not found!\n", device_xname(sc->sc_dev)); 672 } 673 if (eeprom != 0) { 674 switch (sc->alc_ident->deviceid) { 675 case PCI_PRODUCT_ATTANSIC_AR8131: 676 case PCI_PRODUCT_ATTANSIC_AR8132: 677 if ((opt & OPT_CFG_CLK_ENB) != 0) { 678 opt &= ~OPT_CFG_CLK_ENB; 679 CSR_WRITE_4(sc, ALC_OPT_CFG, opt); 680 CSR_READ_4(sc, ALC_OPT_CFG); 681 DELAY(1000); 682 } 683 break; 684 case PCI_PRODUCT_ATTANSIC_AR8151: 685 case PCI_PRODUCT_ATTANSIC_AR8151_V2: 686 case PCI_PRODUCT_ATTANSIC_AR8152_B: 687 case PCI_PRODUCT_ATTANSIC_AR8152_B2: 688 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 689 ALC_MII_DBG_ADDR, 0x00); 690 alc_miibus_readreg(sc->sc_dev, sc->alc_phyaddr, 691 ALC_MII_DBG_DATA, &val); 692 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 693 ALC_MII_DBG_DATA, val | 0x0080); 694 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 695 ALC_MII_DBG_ADDR, 0x3B); 696 alc_miibus_readreg(sc->sc_dev, sc->alc_phyaddr, 697 ALC_MII_DBG_DATA, &val); 698 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 699 ALC_MII_DBG_DATA, val & 0xFFF7); 700 DELAY(20); 701 break; 702 } 703 } 704 705 alc_get_macaddr_par(sc); 706 } 707 708 static void 709 alc_get_macaddr_816x(struct alc_softc *sc) 710 { 711 uint32_t reg; 712 int i, reloaded; 713 714 reloaded = 0; 715 /* Try to reload station address via TWSI. */ 716 for (i = 100; i > 0; i--) { 717 reg = CSR_READ_4(sc, ALC_SLD); 718 if ((reg & (SLD_PROGRESS | SLD_START)) == 0) 719 break; 720 DELAY(1000); 721 } 722 if (i != 0) { 723 CSR_WRITE_4(sc, ALC_SLD, reg | SLD_START); 724 for (i = 100; i > 0; i--) { 725 DELAY(1000); 726 reg = CSR_READ_4(sc, ALC_SLD); 727 if ((reg & SLD_START) == 0) 728 break; 729 } 730 if (i != 0) 731 reloaded++; 732 else if (alcdebug) 733 printf("%s: reloading station address via TWSI timed out!\n", 734 device_xname(sc->sc_dev)); 735 } 736 737 /* Try to reload station address from EEPROM or FLASH. */ 738 if (reloaded == 0) { 739 reg = CSR_READ_4(sc, ALC_EEPROM_LD); 740 if ((reg & (EEPROM_LD_EEPROM_EXIST | 741 EEPROM_LD_FLASH_EXIST)) != 0) { 742 for (i = 100; i > 0; i--) { 743 reg = CSR_READ_4(sc, ALC_EEPROM_LD); 744 if ((reg & (EEPROM_LD_PROGRESS | 745 EEPROM_LD_START)) == 0) 746 break; 747 DELAY(1000); 748 } 749 if (i != 0) { 750 CSR_WRITE_4(sc, ALC_EEPROM_LD, reg | 751 EEPROM_LD_START); 752 for (i = 100; i > 0; i--) { 753 DELAY(1000); 754 reg = CSR_READ_4(sc, ALC_EEPROM_LD); 755 if ((reg & EEPROM_LD_START) == 0) 756 break; 757 } 758 } else if (alcdebug) 759 printf("%s: reloading EEPROM/FLASH timed out!\n", 760 device_xname(sc->sc_dev)); 761 } 762 } 763 764 alc_get_macaddr_par(sc); 765 } 766 767 768 static void 769 alc_get_macaddr_par(struct alc_softc *sc) 770 { 771 uint32_t ea[2]; 772 773 ea[0] = CSR_READ_4(sc, ALC_PAR0); 774 ea[1] = CSR_READ_4(sc, ALC_PAR1); 775 sc->alc_eaddr[0] = (ea[1] >> 8) & 0xFF; 776 sc->alc_eaddr[1] = (ea[1] >> 0) & 0xFF; 777 sc->alc_eaddr[2] = (ea[0] >> 24) & 0xFF; 778 sc->alc_eaddr[3] = (ea[0] >> 16) & 0xFF; 779 sc->alc_eaddr[4] = (ea[0] >> 8) & 0xFF; 780 sc->alc_eaddr[5] = (ea[0] >> 0) & 0xFF; 781 } 782 783 static void 784 alc_disable_l0s_l1(struct alc_softc *sc) 785 { 786 uint32_t pmcfg; 787 788 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 789 /* Another magic from vendor. */ 790 pmcfg = CSR_READ_4(sc, ALC_PM_CFG); 791 pmcfg &= ~(PM_CFG_L1_ENTRY_TIMER_MASK | PM_CFG_CLK_SWH_L1 | 792 PM_CFG_ASPM_L0S_ENB | PM_CFG_ASPM_L1_ENB | 793 PM_CFG_MAC_ASPM_CHK | PM_CFG_SERDES_PD_EX_L1); 794 pmcfg |= PM_CFG_SERDES_BUDS_RX_L1_ENB | 795 PM_CFG_SERDES_PLL_L1_ENB | PM_CFG_SERDES_L1_ENB; 796 CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg); 797 } 798 } 799 800 static void 801 alc_phy_reset(struct alc_softc *sc) 802 { 803 804 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 805 alc_phy_reset_816x(sc); 806 else 807 alc_phy_reset_813x(sc); 808 } 809 810 static void 811 alc_phy_reset_813x(struct alc_softc *sc) 812 { 813 uint16_t data; 814 815 /* Reset magic from Linux. */ 816 CSR_WRITE_2(sc, ALC_GPHY_CFG, GPHY_CFG_SEL_ANA_RESET); 817 CSR_READ_2(sc, ALC_GPHY_CFG); 818 DELAY(10 * 1000); 819 820 CSR_WRITE_2(sc, ALC_GPHY_CFG, GPHY_CFG_EXT_RESET | 821 GPHY_CFG_SEL_ANA_RESET); 822 CSR_READ_2(sc, ALC_GPHY_CFG); 823 DELAY(10 * 1000); 824 825 /* DSP fixup, Vendor magic. */ 826 if (sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8152_B) { 827 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 828 ALC_MII_DBG_ADDR, 0x000A); 829 alc_miibus_readreg(sc->sc_dev, sc->alc_phyaddr, 830 ALC_MII_DBG_DATA, &data); 831 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 832 ALC_MII_DBG_DATA, data & 0xDFFF); 833 } 834 if (sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8151 || 835 sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8151_V2 || 836 sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8152_B || 837 sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8152_B2) { 838 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 839 ALC_MII_DBG_ADDR, 0x003B); 840 alc_miibus_readreg(sc->sc_dev, sc->alc_phyaddr, 841 ALC_MII_DBG_DATA, &data); 842 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 843 ALC_MII_DBG_DATA, data & 0xFFF7); 844 DELAY(20 * 1000); 845 } 846 if (sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8151) { 847 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 848 ALC_MII_DBG_ADDR, 0x0029); 849 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 850 ALC_MII_DBG_DATA, 0x929D); 851 } 852 if (sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8131 || 853 sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8132 || 854 sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8151_V2 || 855 sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8152_B2) { 856 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 857 ALC_MII_DBG_ADDR, 0x0029); 858 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 859 ALC_MII_DBG_DATA, 0xB6DD); 860 } 861 862 /* Load DSP codes, vendor magic. */ 863 data = ANA_LOOP_SEL_10BT | ANA_EN_MASK_TB | ANA_EN_10BT_IDLE | 864 ((1 << ANA_INTERVAL_SEL_TIMER_SHIFT) & ANA_INTERVAL_SEL_TIMER_MASK); 865 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 866 ALC_MII_DBG_ADDR, MII_ANA_CFG18); 867 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 868 ALC_MII_DBG_DATA, data); 869 870 data = ((2 << ANA_SERDES_CDR_BW_SHIFT) & ANA_SERDES_CDR_BW_MASK) | 871 ANA_SERDES_EN_DEEM | ANA_SERDES_SEL_HSP | ANA_SERDES_EN_PLL | 872 ANA_SERDES_EN_LCKDT; 873 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 874 ALC_MII_DBG_ADDR, MII_ANA_CFG5); 875 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 876 ALC_MII_DBG_DATA, data); 877 878 data = ((44 << ANA_LONG_CABLE_TH_100_SHIFT) & 879 ANA_LONG_CABLE_TH_100_MASK) | 880 ((33 << ANA_SHORT_CABLE_TH_100_SHIFT) & 881 ANA_SHORT_CABLE_TH_100_SHIFT) | 882 ANA_BP_BAD_LINK_ACCUM | ANA_BP_SMALL_BW; 883 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 884 ALC_MII_DBG_ADDR, MII_ANA_CFG54); 885 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 886 ALC_MII_DBG_DATA, data); 887 888 data = ((11 << ANA_IECHO_ADJ_3_SHIFT) & ANA_IECHO_ADJ_3_MASK) | 889 ((11 << ANA_IECHO_ADJ_2_SHIFT) & ANA_IECHO_ADJ_2_MASK) | 890 ((8 << ANA_IECHO_ADJ_1_SHIFT) & ANA_IECHO_ADJ_1_MASK) | 891 ((8 << ANA_IECHO_ADJ_0_SHIFT) & ANA_IECHO_ADJ_0_MASK); 892 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 893 ALC_MII_DBG_ADDR, MII_ANA_CFG4); 894 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 895 ALC_MII_DBG_DATA, data); 896 897 data = ((7 & ANA_MANUL_SWICH_ON_SHIFT) & ANA_MANUL_SWICH_ON_MASK) | 898 ANA_RESTART_CAL | ANA_MAN_ENABLE | ANA_SEL_HSP | ANA_EN_HB | 899 ANA_OEN_125M; 900 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 901 ALC_MII_DBG_ADDR, MII_ANA_CFG0); 902 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 903 ALC_MII_DBG_DATA, data); 904 DELAY(1000); 905 906 /* Disable hibernation. */ 907 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, ALC_MII_DBG_ADDR, 908 0x0029); 909 alc_miibus_readreg(sc->sc_dev, sc->alc_phyaddr, 910 ALC_MII_DBG_DATA, &data); 911 data &= ~0x8000; 912 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, ALC_MII_DBG_DATA, 913 data); 914 915 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, ALC_MII_DBG_ADDR, 916 0x000B); 917 alc_miibus_readreg(sc->sc_dev, sc->alc_phyaddr, 918 ALC_MII_DBG_DATA, &data); 919 data &= ~0x8000; 920 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, ALC_MII_DBG_DATA, 921 data); 922 } 923 924 static void 925 alc_phy_reset_816x(struct alc_softc *sc) 926 { 927 uint32_t val; 928 uint16_t phyval; 929 930 val = CSR_READ_4(sc, ALC_GPHY_CFG); 931 val &= ~(GPHY_CFG_EXT_RESET | GPHY_CFG_LED_MODE | 932 GPHY_CFG_GATE_25M_ENB | GPHY_CFG_PHY_IDDQ | GPHY_CFG_PHY_PLL_ON | 933 GPHY_CFG_PWDOWN_HW | GPHY_CFG_100AB_ENB); 934 val |= GPHY_CFG_SEL_ANA_RESET; 935 #ifdef notyet 936 val |= GPHY_CFG_HIB_PULSE | GPHY_CFG_HIB_EN | GPHY_CFG_SEL_ANA_RESET; 937 #else 938 /* Disable PHY hibernation. */ 939 val &= ~(GPHY_CFG_HIB_PULSE | GPHY_CFG_HIB_EN); 940 #endif 941 CSR_WRITE_4(sc, ALC_GPHY_CFG, val); 942 DELAY(10); 943 CSR_WRITE_4(sc, ALC_GPHY_CFG, val | GPHY_CFG_EXT_RESET); 944 DELAY(800); 945 946 /* Vendor PHY magic. */ 947 #ifdef notyet 948 alc_miidbg_writereg(sc, MII_DBG_LEGCYPS, DBG_LEGCYPS_DEFAULT); 949 alc_miidbg_writereg(sc, MII_DBG_SYSMODCTL, DBG_SYSMODCTL_DEFAULT); 950 alc_miiext_writereg(sc, MII_EXT_PCS, MII_EXT_VDRVBIAS, 951 EXT_VDRVBIAS_DEFAULT); 952 #else 953 /* Disable PHY hibernation. */ 954 alc_miidbg_writereg(sc, MII_DBG_LEGCYPS, 955 DBG_LEGCYPS_DEFAULT & ~DBG_LEGCYPS_ENB); 956 alc_miidbg_writereg(sc, MII_DBG_HIBNEG, 957 DBG_HIBNEG_DEFAULT & ~(DBG_HIBNEG_PSHIB_EN | DBG_HIBNEG_HIB_PULSE)); 958 alc_miidbg_writereg(sc, MII_DBG_GREENCFG, DBG_GREENCFG_DEFAULT); 959 #endif 960 961 /* XXX Disable EEE. */ 962 val = CSR_READ_4(sc, ALC_LPI_CTL); 963 val &= ~LPI_CTL_ENB; 964 CSR_WRITE_4(sc, ALC_LPI_CTL, val); 965 alc_miiext_writereg(sc, MII_EXT_ANEG, MII_EXT_ANEG_LOCAL_EEEADV, 0); 966 967 /* PHY power saving. */ 968 alc_miidbg_writereg(sc, MII_DBG_TST10BTCFG, DBG_TST10BTCFG_DEFAULT); 969 alc_miidbg_writereg(sc, MII_DBG_SRDSYSMOD, DBG_SRDSYSMOD_DEFAULT); 970 alc_miidbg_writereg(sc, MII_DBG_TST100BTCFG, DBG_TST100BTCFG_DEFAULT); 971 alc_miidbg_writereg(sc, MII_DBG_ANACTL, DBG_ANACTL_DEFAULT); 972 alc_miidbg_readreg(sc, MII_DBG_GREENCFG2, &phyval); 973 phyval &= ~DBG_GREENCFG2_GATE_DFSE_EN; 974 alc_miidbg_writereg(sc, MII_DBG_GREENCFG2, phyval); 975 976 /* RTL8139C, 120m issue. */ 977 alc_miiext_writereg(sc, MII_EXT_ANEG, MII_EXT_ANEG_NLP78, 978 ANEG_NLP78_120M_DEFAULT); 979 alc_miiext_writereg(sc, MII_EXT_ANEG, MII_EXT_ANEG_S3DIG10, 980 ANEG_S3DIG10_DEFAULT); 981 982 if ((sc->alc_flags & ALC_FLAG_LINK_WAR) != 0) { 983 /* Turn off half amplitude. */ 984 alc_miiext_readreg(sc, MII_EXT_PCS, MII_EXT_CLDCTL3, &phyval); 985 phyval |= EXT_CLDCTL3_BP_CABLE1TH_DET_GT; 986 alc_miiext_writereg(sc, MII_EXT_PCS, MII_EXT_CLDCTL3, phyval); 987 /* Turn off Green feature. */ 988 alc_miidbg_readreg(sc, MII_DBG_GREENCFG2, &phyval); 989 phyval |= DBG_GREENCFG2_BP_GREEN; 990 alc_miidbg_writereg(sc, MII_DBG_GREENCFG2, phyval); 991 /* Turn off half bias. */ 992 alc_miiext_readreg(sc, MII_EXT_PCS, MII_EXT_CLDCTL5, &phyval); 993 val |= EXT_CLDCTL5_BP_VD_HLFBIAS; 994 alc_miiext_writereg(sc, MII_EXT_PCS, MII_EXT_CLDCTL5, phyval); 995 } 996 } 997 998 static void 999 alc_phy_down(struct alc_softc *sc) 1000 { 1001 uint32_t gphy; 1002 1003 switch (sc->alc_ident->deviceid) { 1004 case PCI_PRODUCT_ATTANSIC_AR8161: 1005 case PCI_PRODUCT_ATTANSIC_E2200: 1006 case PCI_PRODUCT_ATTANSIC_AR8162: 1007 case PCI_PRODUCT_ATTANSIC_AR8171: 1008 case PCI_PRODUCT_ATTANSIC_AR8172: 1009 gphy = CSR_READ_4(sc, ALC_GPHY_CFG); 1010 gphy &= ~(GPHY_CFG_EXT_RESET | GPHY_CFG_LED_MODE | 1011 GPHY_CFG_100AB_ENB | GPHY_CFG_PHY_PLL_ON); 1012 gphy |= GPHY_CFG_HIB_EN | GPHY_CFG_HIB_PULSE | 1013 GPHY_CFG_SEL_ANA_RESET; 1014 gphy |= GPHY_CFG_PHY_IDDQ | GPHY_CFG_PWDOWN_HW; 1015 CSR_WRITE_4(sc, ALC_GPHY_CFG, gphy); 1016 break; 1017 case PCI_PRODUCT_ATTANSIC_AR8151: 1018 case PCI_PRODUCT_ATTANSIC_AR8151_V2: 1019 case PCI_PRODUCT_ATTANSIC_AR8152_B: 1020 case PCI_PRODUCT_ATTANSIC_AR8152_B2: 1021 /* 1022 * GPHY power down caused more problems on AR8151 v2.0. 1023 * When driver is reloaded after GPHY power down, 1024 * accesses to PHY/MAC registers hung the system. Only 1025 * cold boot recovered from it. I'm not sure whether 1026 * AR8151 v1.0 also requires this one though. I don't 1027 * have AR8151 v1.0 controller in hand. 1028 * The only option left is to isolate the PHY and 1029 * initiates power down the PHY which in turn saves 1030 * more power when driver is unloaded. 1031 */ 1032 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 1033 MII_BMCR, BMCR_ISO | BMCR_PDOWN); 1034 break; 1035 default: 1036 /* Force PHY down. */ 1037 CSR_WRITE_2(sc, ALC_GPHY_CFG, GPHY_CFG_EXT_RESET | 1038 GPHY_CFG_SEL_ANA_RESET | GPHY_CFG_PHY_IDDQ | 1039 GPHY_CFG_PWDOWN_HW); 1040 DELAY(1000); 1041 break; 1042 } 1043 } 1044 1045 static void 1046 alc_aspm(struct alc_softc *sc, int init, int media) 1047 { 1048 1049 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 1050 alc_aspm_816x(sc, init); 1051 else 1052 alc_aspm_813x(sc, media); 1053 } 1054 1055 static void 1056 alc_aspm_813x(struct alc_softc *sc, int media) 1057 { 1058 uint32_t pmcfg; 1059 uint16_t linkcfg; 1060 1061 pmcfg = CSR_READ_4(sc, ALC_PM_CFG); 1062 if ((sc->alc_flags & (ALC_FLAG_APS | ALC_FLAG_PCIE)) == 1063 (ALC_FLAG_APS | ALC_FLAG_PCIE)) 1064 linkcfg = CSR_READ_2(sc, sc->alc_expcap + 1065 PCIE_LCSR); 1066 else 1067 linkcfg = 0; 1068 pmcfg &= ~PM_CFG_SERDES_PD_EX_L1; 1069 pmcfg &= ~(PM_CFG_L1_ENTRY_TIMER_MASK | PM_CFG_LCKDET_TIMER_MASK); 1070 pmcfg |= PM_CFG_MAC_ASPM_CHK; 1071 pmcfg |= (PM_CFG_LCKDET_TIMER_DEFAULT << PM_CFG_LCKDET_TIMER_SHIFT); 1072 pmcfg &= ~(PM_CFG_ASPM_L1_ENB | PM_CFG_ASPM_L0S_ENB); 1073 1074 if ((sc->alc_flags & ALC_FLAG_APS) != 0) { 1075 /* Disable extended sync except AR8152 B v1.0 */ 1076 linkcfg &= ~0x80; 1077 if (sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8152_B && 1078 sc->alc_rev == ATHEROS_AR8152_B_V10) 1079 linkcfg |= 0x80; 1080 CSR_WRITE_2(sc, sc->alc_expcap + PCIE_LCSR, 1081 linkcfg); 1082 pmcfg &= ~(PM_CFG_EN_BUFS_RX_L0S | PM_CFG_SA_DLY_ENB | 1083 PM_CFG_HOTRST); 1084 pmcfg |= (PM_CFG_L1_ENTRY_TIMER_DEFAULT << 1085 PM_CFG_L1_ENTRY_TIMER_SHIFT); 1086 pmcfg &= ~PM_CFG_PM_REQ_TIMER_MASK; 1087 pmcfg |= (PM_CFG_PM_REQ_TIMER_DEFAULT << 1088 PM_CFG_PM_REQ_TIMER_SHIFT); 1089 pmcfg |= PM_CFG_SERDES_PD_EX_L1 | PM_CFG_PCIE_RECV; 1090 } 1091 1092 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) { 1093 if ((sc->alc_flags & ALC_FLAG_L0S) != 0) 1094 pmcfg |= PM_CFG_ASPM_L0S_ENB; 1095 if ((sc->alc_flags & ALC_FLAG_L1S) != 0) 1096 pmcfg |= PM_CFG_ASPM_L1_ENB; 1097 if ((sc->alc_flags & ALC_FLAG_APS) != 0) { 1098 if (sc->alc_ident->deviceid == 1099 PCI_PRODUCT_ATTANSIC_AR8152_B) 1100 pmcfg &= ~PM_CFG_ASPM_L0S_ENB; 1101 pmcfg &= ~(PM_CFG_SERDES_L1_ENB | 1102 PM_CFG_SERDES_PLL_L1_ENB | 1103 PM_CFG_SERDES_BUDS_RX_L1_ENB); 1104 pmcfg |= PM_CFG_CLK_SWH_L1; 1105 if (media == IFM_100_TX || media == IFM_1000_T) { 1106 pmcfg &= ~PM_CFG_L1_ENTRY_TIMER_MASK; 1107 switch (sc->alc_ident->deviceid) { 1108 case PCI_PRODUCT_ATTANSIC_AR8152_B: 1109 pmcfg |= (7 << 1110 PM_CFG_L1_ENTRY_TIMER_SHIFT); 1111 break; 1112 case PCI_PRODUCT_ATTANSIC_AR8152_B2: 1113 case PCI_PRODUCT_ATTANSIC_AR8151_V2: 1114 pmcfg |= (4 << 1115 PM_CFG_L1_ENTRY_TIMER_SHIFT); 1116 break; 1117 default: 1118 pmcfg |= (15 << 1119 PM_CFG_L1_ENTRY_TIMER_SHIFT); 1120 break; 1121 } 1122 } 1123 } else { 1124 pmcfg |= PM_CFG_SERDES_L1_ENB | 1125 PM_CFG_SERDES_PLL_L1_ENB | 1126 PM_CFG_SERDES_BUDS_RX_L1_ENB; 1127 pmcfg &= ~(PM_CFG_CLK_SWH_L1 | 1128 PM_CFG_ASPM_L1_ENB | PM_CFG_ASPM_L0S_ENB); 1129 } 1130 } else { 1131 pmcfg &= ~(PM_CFG_SERDES_BUDS_RX_L1_ENB | PM_CFG_SERDES_L1_ENB | 1132 PM_CFG_SERDES_PLL_L1_ENB); 1133 pmcfg |= PM_CFG_CLK_SWH_L1; 1134 if ((sc->alc_flags & ALC_FLAG_L1S) != 0) 1135 pmcfg |= PM_CFG_ASPM_L1_ENB; 1136 } 1137 CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg); 1138 } 1139 1140 static void 1141 alc_aspm_816x(struct alc_softc *sc, int init) 1142 { 1143 uint32_t pmcfg; 1144 1145 pmcfg = CSR_READ_4(sc, ALC_PM_CFG); 1146 pmcfg &= ~PM_CFG_L1_ENTRY_TIMER_816X_MASK; 1147 pmcfg |= PM_CFG_L1_ENTRY_TIMER_816X_DEFAULT; 1148 pmcfg &= ~PM_CFG_PM_REQ_TIMER_MASK; 1149 pmcfg |= PM_CFG_PM_REQ_TIMER_816X_DEFAULT; 1150 pmcfg &= ~PM_CFG_LCKDET_TIMER_MASK; 1151 pmcfg |= PM_CFG_LCKDET_TIMER_DEFAULT; 1152 pmcfg |= PM_CFG_SERDES_PD_EX_L1 | PM_CFG_CLK_SWH_L1 | PM_CFG_PCIE_RECV; 1153 pmcfg &= ~(PM_CFG_RX_L1_AFTER_L0S | PM_CFG_TX_L1_AFTER_L0S | 1154 PM_CFG_ASPM_L1_ENB | PM_CFG_ASPM_L0S_ENB | 1155 PM_CFG_SERDES_L1_ENB | PM_CFG_SERDES_PLL_L1_ENB | 1156 PM_CFG_SERDES_BUDS_RX_L1_ENB | PM_CFG_SA_DLY_ENB | 1157 PM_CFG_MAC_ASPM_CHK | PM_CFG_HOTRST); 1158 if (AR816X_REV(sc->alc_rev) <= AR816X_REV_A1 && 1159 (sc->alc_rev & 0x01) != 0) 1160 pmcfg |= PM_CFG_SERDES_L1_ENB | PM_CFG_SERDES_PLL_L1_ENB; 1161 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) { 1162 /* Link up, enable both L0s, L1s. */ 1163 pmcfg |= PM_CFG_ASPM_L0S_ENB | PM_CFG_ASPM_L1_ENB | 1164 PM_CFG_MAC_ASPM_CHK; 1165 } else { 1166 if (init != 0) 1167 pmcfg |= PM_CFG_ASPM_L0S_ENB | PM_CFG_ASPM_L1_ENB | 1168 PM_CFG_MAC_ASPM_CHK; 1169 else if ((sc->sc_ec.ec_if.if_flags & IFF_RUNNING) != 0) 1170 pmcfg |= PM_CFG_ASPM_L1_ENB | PM_CFG_MAC_ASPM_CHK; 1171 } 1172 CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg); 1173 } 1174 1175 static void 1176 alc_attach(device_t parent, device_t self, void *aux) 1177 { 1178 1179 struct alc_softc *sc = device_private(self); 1180 struct pci_attach_args *pa = aux; 1181 pci_chipset_tag_t pc = pa->pa_pc; 1182 pci_intr_handle_t ih; 1183 const char *intrstr; 1184 struct ifnet *ifp; 1185 pcireg_t memtype; 1186 const char *aspm_state[] = { "L0s/L1", "L0s", "L1", "L0s/L1" }; 1187 uint16_t burst; 1188 int base, mii_flags, state, error = 0; 1189 uint32_t cap, ctl, val; 1190 char intrbuf[PCI_INTRSTR_LEN]; 1191 1192 sc->alc_ident = alc_find_ident(pa); 1193 1194 aprint_naive("\n"); 1195 aprint_normal(": %s\n", sc->alc_ident->name); 1196 1197 sc->sc_dev = self; 1198 sc->sc_dmat = pa->pa_dmat; 1199 sc->sc_pct = pa->pa_pc; 1200 sc->sc_pcitag = pa->pa_tag; 1201 1202 /* 1203 * Allocate IO memory 1204 */ 1205 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, ALC_PCIR_BAR); 1206 switch (memtype) { 1207 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 1208 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT_1M: 1209 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 1210 break; 1211 default: 1212 aprint_error_dev(self, "invalid base address register\n"); 1213 break; 1214 } 1215 1216 if (pci_mapreg_map(pa, ALC_PCIR_BAR, memtype, 0, &sc->sc_mem_bt, 1217 &sc->sc_mem_bh, NULL, &sc->sc_mem_size)) { 1218 aprint_error_dev(self, "could not map mem space\n"); 1219 return; 1220 } 1221 1222 if (pci_intr_map(pa, &ih) != 0) { 1223 printf(": can't map interrupt\n"); 1224 goto fail; 1225 } 1226 1227 /* 1228 * Allocate IRQ 1229 */ 1230 intrstr = pci_intr_string(sc->sc_pct, ih, intrbuf, sizeof(intrbuf)); 1231 sc->sc_irq_handle = pci_intr_establish_xname(pc, ih, IPL_NET, alc_intr, 1232 sc, device_xname(self)); 1233 if (sc->sc_irq_handle == NULL) { 1234 printf(": could not establish interrupt"); 1235 if (intrstr != NULL) 1236 printf(" at %s", intrstr); 1237 printf("\n"); 1238 goto fail; 1239 } 1240 aprint_normal_dev(self, "interrupting at %s\n", intrstr); 1241 1242 /* Set PHY address. */ 1243 sc->alc_phyaddr = ALC_PHY_ADDR; 1244 1245 /* Initialize DMA parameters. */ 1246 sc->alc_dma_rd_burst = 0; 1247 sc->alc_dma_wr_burst = 0; 1248 sc->alc_rcb = DMA_CFG_RCB_64; 1249 if (pci_get_capability(pc, pa->pa_tag, PCI_CAP_PCIEXPRESS, 1250 &base, NULL)) { 1251 sc->alc_flags |= ALC_FLAG_PCIE; 1252 sc->alc_expcap = base; 1253 burst = pci_conf_read(sc->sc_pct, sc->sc_pcitag, 1254 base + PCIE_DCSR) >> 16; 1255 sc->alc_dma_rd_burst = (burst & 0x7000) >> 12; 1256 sc->alc_dma_wr_burst = (burst & 0x00e0) >> 5; 1257 if (alcdebug) { 1258 printf("%s: Read request size : %u bytes.\n", 1259 device_xname(sc->sc_dev), 1260 alc_dma_burst[sc->alc_dma_rd_burst]); 1261 printf("%s: TLP payload size : %u bytes.\n", 1262 device_xname(sc->sc_dev), 1263 alc_dma_burst[sc->alc_dma_wr_burst]); 1264 } 1265 if (alc_dma_burst[sc->alc_dma_rd_burst] > 1024) 1266 sc->alc_dma_rd_burst = 3; 1267 if (alc_dma_burst[sc->alc_dma_wr_burst] > 1024) 1268 sc->alc_dma_wr_burst = 3; 1269 1270 /* Clear data link and flow-control protocol error. */ 1271 val = CSR_READ_4(sc, ALC_PEX_UNC_ERR_SEV); 1272 val &= ~(PEX_UNC_ERR_SEV_DLP | PEX_UNC_ERR_SEV_FCP); 1273 CSR_WRITE_4(sc, ALC_PEX_UNC_ERR_SEV, val); 1274 1275 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 1276 CSR_WRITE_4(sc, ALC_LTSSM_ID_CFG, 1277 CSR_READ_4(sc, ALC_LTSSM_ID_CFG) & ~LTSSM_ID_WRO_ENB); 1278 CSR_WRITE_4(sc, ALC_PCIE_PHYMISC, 1279 CSR_READ_4(sc, ALC_PCIE_PHYMISC) | 1280 PCIE_PHYMISC_FORCE_RCV_DET); 1281 if (sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8152_B && 1282 sc->alc_rev == ATHEROS_AR8152_B_V10) { 1283 val = CSR_READ_4(sc, ALC_PCIE_PHYMISC2); 1284 val &= ~(PCIE_PHYMISC2_SERDES_CDR_MASK | 1285 PCIE_PHYMISC2_SERDES_TH_MASK); 1286 val |= 3 << PCIE_PHYMISC2_SERDES_CDR_SHIFT; 1287 val |= 3 << PCIE_PHYMISC2_SERDES_TH_SHIFT; 1288 CSR_WRITE_4(sc, ALC_PCIE_PHYMISC2, val); 1289 } 1290 /* Disable ASPM L0S and L1. */ 1291 cap = pci_conf_read(sc->sc_pct, sc->sc_pcitag, 1292 base + PCIE_LCAP) >> 16; 1293 if ((cap & PCIE_LCAP_ASPM) != 0) { 1294 ctl = pci_conf_read(sc->sc_pct, sc->sc_pcitag, 1295 base + PCIE_LCSR) >> 16; 1296 if ((ctl & 0x08) != 0) 1297 sc->alc_rcb = DMA_CFG_RCB_128; 1298 if (alcdebug) 1299 printf("%s: RCB %u bytes\n", 1300 device_xname(sc->sc_dev), 1301 sc->alc_rcb == DMA_CFG_RCB_64 ? 64 : 128); 1302 state = ctl & 0x03; 1303 if (state & 0x01) 1304 sc->alc_flags |= ALC_FLAG_L0S; 1305 if (state & 0x02) 1306 sc->alc_flags |= ALC_FLAG_L1S; 1307 if (alcdebug) 1308 printf("%s: ASPM %s %s\n", 1309 device_xname(sc->sc_dev), 1310 aspm_state[state], 1311 state == 0 ? "disabled" : "enabled"); 1312 alc_disable_l0s_l1(sc); 1313 } else { 1314 aprint_debug_dev(sc->sc_dev, "no ASPM support\n"); 1315 } 1316 } else { 1317 val = CSR_READ_4(sc, ALC_PDLL_TRNS1); 1318 val &= ~PDLL_TRNS1_D3PLLOFF_ENB; 1319 CSR_WRITE_4(sc, ALC_PDLL_TRNS1, val); 1320 val = CSR_READ_4(sc, ALC_MASTER_CFG); 1321 if (AR816X_REV(sc->alc_rev) <= AR816X_REV_A1 && 1322 (sc->alc_rev & 0x01) != 0) { 1323 if ((val & MASTER_WAKEN_25M) == 0 || 1324 (val & MASTER_CLK_SEL_DIS) == 0) { 1325 val |= MASTER_WAKEN_25M | MASTER_CLK_SEL_DIS; 1326 CSR_WRITE_4(sc, ALC_MASTER_CFG, val); 1327 } 1328 } else { 1329 if ((val & MASTER_WAKEN_25M) == 0 || 1330 (val & MASTER_CLK_SEL_DIS) != 0) { 1331 val |= MASTER_WAKEN_25M; 1332 val &= ~MASTER_CLK_SEL_DIS; 1333 CSR_WRITE_4(sc, ALC_MASTER_CFG, val); 1334 } 1335 } 1336 } 1337 alc_aspm(sc, 1, IFM_UNKNOWN); 1338 } 1339 1340 /* Reset PHY. */ 1341 alc_phy_reset(sc); 1342 1343 /* Reset the ethernet controller. */ 1344 alc_stop_mac(sc); 1345 alc_reset(sc); 1346 1347 /* 1348 * One odd thing is AR8132 uses the same PHY hardware(F1 1349 * gigabit PHY) of AR8131. So atphy(4) of AR8132 reports 1350 * the PHY supports 1000Mbps but that's not true. The PHY 1351 * used in AR8132 can't establish gigabit link even if it 1352 * shows the same PHY model/revision number of AR8131. 1353 */ 1354 switch (sc->alc_ident->deviceid) { 1355 case PCI_PRODUCT_ATTANSIC_AR8161: 1356 if (PCI_SUBSYS_ID(pci_conf_read( 1357 sc->sc_pct, sc->sc_pcitag, PCI_SUBSYS_ID_REG)) == 0x0091 && 1358 sc->alc_rev == 0) 1359 sc->alc_flags |= ALC_FLAG_LINK_WAR; 1360 /* FALLTHROUGH */ 1361 case PCI_PRODUCT_ATTANSIC_E2200: 1362 case PCI_PRODUCT_ATTANSIC_AR8171: 1363 sc->alc_flags |= ALC_FLAG_AR816X_FAMILY; 1364 break; 1365 case PCI_PRODUCT_ATTANSIC_AR8162: 1366 case PCI_PRODUCT_ATTANSIC_AR8172: 1367 sc->alc_flags |= ALC_FLAG_FASTETHER | ALC_FLAG_AR816X_FAMILY; 1368 break; 1369 case PCI_PRODUCT_ATTANSIC_AR8152_B: 1370 case PCI_PRODUCT_ATTANSIC_AR8152_B2: 1371 sc->alc_flags |= ALC_FLAG_APS; 1372 /* FALLTHROUGH */ 1373 case PCI_PRODUCT_ATTANSIC_AR8132: 1374 sc->alc_flags |= ALC_FLAG_FASTETHER; 1375 break; 1376 case PCI_PRODUCT_ATTANSIC_AR8151: 1377 case PCI_PRODUCT_ATTANSIC_AR8151_V2: 1378 sc->alc_flags |= ALC_FLAG_APS; 1379 /* FALLTHROUGH */ 1380 default: 1381 break; 1382 } 1383 sc->alc_flags |= ALC_FLAG_JUMBO; 1384 1385 /* 1386 * It seems that AR813x/AR815x has silicon bug for SMB. In 1387 * addition, Atheros said that enabling SMB wouldn't improve 1388 * performance. However I think it's bad to access lots of 1389 * registers to extract MAC statistics. 1390 */ 1391 sc->alc_flags |= ALC_FLAG_SMB_BUG; 1392 /* 1393 * Don't use Tx CMB. It is known to have silicon bug. 1394 */ 1395 sc->alc_flags |= ALC_FLAG_CMB_BUG; 1396 sc->alc_rev = PCI_REVISION(pa->pa_class); 1397 sc->alc_chip_rev = CSR_READ_4(sc, ALC_MASTER_CFG) >> 1398 MASTER_CHIP_REV_SHIFT; 1399 if (alcdebug) { 1400 printf("%s: PCI device revision : 0x%04x\n", 1401 device_xname(sc->sc_dev), sc->alc_rev); 1402 printf("%s: Chip id/revision : 0x%04x\n", 1403 device_xname(sc->sc_dev), sc->alc_chip_rev); 1404 printf("%s: %u Tx FIFO, %u Rx FIFO\n", device_xname(sc->sc_dev), 1405 CSR_READ_4(sc, ALC_SRAM_TX_FIFO_LEN) * 8, 1406 CSR_READ_4(sc, ALC_SRAM_RX_FIFO_LEN) * 8); 1407 } 1408 1409 error = alc_dma_alloc(sc); 1410 if (error) 1411 goto fail; 1412 1413 callout_init(&sc->sc_tick_ch, 0); 1414 callout_setfunc(&sc->sc_tick_ch, alc_tick, sc); 1415 1416 /* Load station address. */ 1417 alc_get_macaddr(sc); 1418 1419 aprint_normal_dev(self, "Ethernet address %s\n", 1420 ether_sprintf(sc->alc_eaddr)); 1421 1422 ifp = &sc->sc_ec.ec_if; 1423 ifp->if_softc = sc; 1424 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1425 ifp->if_init = alc_init; 1426 ifp->if_ioctl = alc_ioctl; 1427 ifp->if_start = alc_start; 1428 ifp->if_stop = alc_stop; 1429 ifp->if_watchdog = alc_watchdog; 1430 IFQ_SET_MAXLEN(&ifp->if_snd, ALC_TX_RING_CNT - 1); 1431 IFQ_SET_READY(&ifp->if_snd); 1432 strlcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 1433 1434 sc->sc_ec.ec_capabilities = ETHERCAP_VLAN_MTU; 1435 1436 #ifdef ALC_CHECKSUM 1437 ifp->if_capabilities |= IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 1438 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 1439 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 1440 #endif 1441 1442 #if NVLAN > 0 1443 sc->sc_ec.ec_capabilities |= ETHERCAP_VLAN_HWTAGGING; 1444 #endif 1445 1446 /* 1447 * XXX 1448 * It seems enabling Tx checksum offloading makes more trouble. 1449 * Sometimes the controller does not receive any frames when 1450 * Tx checksum offloading is enabled. I'm not sure whether this 1451 * is a bug in Tx checksum offloading logic or I got broken 1452 * sample boards. To safety, don't enable Tx checksum offloading 1453 * by default but give chance to users to toggle it if they know 1454 * their controllers work without problems. 1455 * Fortunately, Tx checksum offloading for AR816x family 1456 * seems to work. 1457 */ 1458 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 1459 ifp->if_capenable &= ~IFCAP_CSUM_IPv4_Tx; 1460 ifp->if_capabilities &= ~ALC_CSUM_FEATURES; 1461 } 1462 1463 /* Set up MII bus. */ 1464 sc->sc_miibus.mii_ifp = ifp; 1465 sc->sc_miibus.mii_readreg = alc_miibus_readreg; 1466 sc->sc_miibus.mii_writereg = alc_miibus_writereg; 1467 sc->sc_miibus.mii_statchg = alc_miibus_statchg; 1468 1469 sc->sc_ec.ec_mii = &sc->sc_miibus; 1470 ifmedia_init(&sc->sc_miibus.mii_media, 0, alc_mediachange, 1471 alc_mediastatus); 1472 mii_flags = 0; 1473 if ((sc->alc_flags & ALC_FLAG_JUMBO) != 0) 1474 mii_flags |= MIIF_DOPAUSE; 1475 mii_attach(self, &sc->sc_miibus, 0xffffffff, MII_PHY_ANY, 1476 MII_OFFSET_ANY, mii_flags); 1477 1478 if (LIST_FIRST(&sc->sc_miibus.mii_phys) == NULL) { 1479 printf("%s: no PHY found!\n", device_xname(sc->sc_dev)); 1480 ifmedia_add(&sc->sc_miibus.mii_media, IFM_ETHER | IFM_MANUAL, 1481 0, NULL); 1482 ifmedia_set(&sc->sc_miibus.mii_media, IFM_ETHER | IFM_MANUAL); 1483 } else 1484 ifmedia_set(&sc->sc_miibus.mii_media, IFM_ETHER | IFM_AUTO); 1485 1486 if_attach(ifp); 1487 if_deferred_start_init(ifp, NULL); 1488 ether_ifattach(ifp, sc->alc_eaddr); 1489 1490 if (!pmf_device_register(self, NULL, NULL)) 1491 aprint_error_dev(self, "couldn't establish power handler\n"); 1492 else 1493 pmf_class_network_register(self, ifp); 1494 1495 return; 1496 fail: 1497 alc_dma_free(sc); 1498 if (sc->sc_irq_handle != NULL) { 1499 pci_intr_disestablish(sc->sc_pct, sc->sc_irq_handle); 1500 sc->sc_irq_handle = NULL; 1501 } 1502 if (sc->sc_mem_size) { 1503 bus_space_unmap(sc->sc_mem_bt, sc->sc_mem_bh, sc->sc_mem_size); 1504 sc->sc_mem_size = 0; 1505 } 1506 } 1507 1508 static int 1509 alc_detach(device_t self, int flags) 1510 { 1511 struct alc_softc *sc = device_private(self); 1512 struct ifnet *ifp = &sc->sc_ec.ec_if; 1513 int s; 1514 1515 s = splnet(); 1516 alc_stop(ifp, 0); 1517 splx(s); 1518 1519 mii_detach(&sc->sc_miibus, MII_PHY_ANY, MII_OFFSET_ANY); 1520 1521 /* Delete all remaining media. */ 1522 ifmedia_delete_instance(&sc->sc_miibus.mii_media, IFM_INST_ANY); 1523 1524 ether_ifdetach(ifp); 1525 if_detach(ifp); 1526 alc_dma_free(sc); 1527 1528 alc_phy_down(sc); 1529 if (sc->sc_irq_handle != NULL) { 1530 pci_intr_disestablish(sc->sc_pct, sc->sc_irq_handle); 1531 sc->sc_irq_handle = NULL; 1532 } 1533 if (sc->sc_mem_size) { 1534 bus_space_unmap(sc->sc_mem_bt, sc->sc_mem_bh, sc->sc_mem_size); 1535 sc->sc_mem_size = 0; 1536 } 1537 1538 return (0); 1539 } 1540 1541 static int 1542 alc_dma_alloc(struct alc_softc *sc) 1543 { 1544 struct alc_txdesc *txd; 1545 struct alc_rxdesc *rxd; 1546 int nsegs, error, i; 1547 1548 /* 1549 * Create DMA stuffs for TX ring 1550 */ 1551 error = bus_dmamap_create(sc->sc_dmat, ALC_TX_RING_SZ, 1, 1552 ALC_TX_RING_SZ, 0, BUS_DMA_NOWAIT, &sc->alc_cdata.alc_tx_ring_map); 1553 if (error) { 1554 sc->alc_cdata.alc_tx_ring_map = NULL; 1555 return (ENOBUFS); 1556 } 1557 1558 /* Allocate DMA'able memory for TX ring */ 1559 error = bus_dmamem_alloc(sc->sc_dmat, ALC_TX_RING_SZ, 1560 ETHER_ALIGN, 0, &sc->alc_rdata.alc_tx_ring_seg, 1, 1561 &nsegs, BUS_DMA_NOWAIT); 1562 if (error) { 1563 printf("%s: could not allocate DMA'able memory for Tx ring.\n", 1564 device_xname(sc->sc_dev)); 1565 return error; 1566 } 1567 1568 error = bus_dmamem_map(sc->sc_dmat, &sc->alc_rdata.alc_tx_ring_seg, 1569 nsegs, ALC_TX_RING_SZ, (void **)&sc->alc_rdata.alc_tx_ring, 1570 BUS_DMA_NOWAIT); 1571 if (error) 1572 return (ENOBUFS); 1573 1574 /* Load the DMA map for Tx ring. */ 1575 error = bus_dmamap_load(sc->sc_dmat, sc->alc_cdata.alc_tx_ring_map, 1576 sc->alc_rdata.alc_tx_ring, ALC_TX_RING_SZ, NULL, BUS_DMA_WAITOK); 1577 if (error) { 1578 printf("%s: could not load DMA'able memory for Tx ring.\n", 1579 device_xname(sc->sc_dev)); 1580 bus_dmamem_free(sc->sc_dmat, 1581 &sc->alc_rdata.alc_tx_ring_seg, 1); 1582 return error; 1583 } 1584 1585 sc->alc_rdata.alc_tx_ring_paddr = 1586 sc->alc_cdata.alc_tx_ring_map->dm_segs[0].ds_addr; 1587 1588 /* 1589 * Create DMA stuffs for RX ring 1590 */ 1591 error = bus_dmamap_create(sc->sc_dmat, ALC_RX_RING_SZ, 1, 1592 ALC_RX_RING_SZ, 0, BUS_DMA_NOWAIT, &sc->alc_cdata.alc_rx_ring_map); 1593 if (error) 1594 return (ENOBUFS); 1595 1596 /* Allocate DMA'able memory for RX ring */ 1597 error = bus_dmamem_alloc(sc->sc_dmat, ALC_RX_RING_SZ, 1598 ETHER_ALIGN, 0, &sc->alc_rdata.alc_rx_ring_seg, 1, 1599 &nsegs, BUS_DMA_NOWAIT); 1600 if (error) { 1601 printf("%s: could not allocate DMA'able memory for Rx ring.\n", 1602 device_xname(sc->sc_dev)); 1603 return error; 1604 } 1605 1606 error = bus_dmamem_map(sc->sc_dmat, &sc->alc_rdata.alc_rx_ring_seg, 1607 nsegs, ALC_RX_RING_SZ, (void **)&sc->alc_rdata.alc_rx_ring, 1608 BUS_DMA_NOWAIT); 1609 if (error) 1610 return (ENOBUFS); 1611 1612 /* Load the DMA map for Rx ring. */ 1613 error = bus_dmamap_load(sc->sc_dmat, sc->alc_cdata.alc_rx_ring_map, 1614 sc->alc_rdata.alc_rx_ring, ALC_RX_RING_SZ, NULL, BUS_DMA_WAITOK); 1615 if (error) { 1616 printf("%s: could not load DMA'able memory for Rx ring.\n", 1617 device_xname(sc->sc_dev)); 1618 bus_dmamem_free(sc->sc_dmat, 1619 &sc->alc_rdata.alc_rx_ring_seg, 1); 1620 return error; 1621 } 1622 1623 sc->alc_rdata.alc_rx_ring_paddr = 1624 sc->alc_cdata.alc_rx_ring_map->dm_segs[0].ds_addr; 1625 1626 /* 1627 * Create DMA stuffs for RX return ring 1628 */ 1629 error = bus_dmamap_create(sc->sc_dmat, ALC_RR_RING_SZ, 1, 1630 ALC_RR_RING_SZ, 0, BUS_DMA_NOWAIT, &sc->alc_cdata.alc_rr_ring_map); 1631 if (error) 1632 return (ENOBUFS); 1633 1634 /* Allocate DMA'able memory for RX return ring */ 1635 error = bus_dmamem_alloc(sc->sc_dmat, ALC_RR_RING_SZ, 1636 ETHER_ALIGN, 0, &sc->alc_rdata.alc_rr_ring_seg, 1, 1637 &nsegs, BUS_DMA_NOWAIT); 1638 if (error) { 1639 printf("%s: could not allocate DMA'able memory for Rx " 1640 "return ring.\n", device_xname(sc->sc_dev)); 1641 return error; 1642 } 1643 1644 error = bus_dmamem_map(sc->sc_dmat, &sc->alc_rdata.alc_rr_ring_seg, 1645 nsegs, ALC_RR_RING_SZ, (void **)&sc->alc_rdata.alc_rr_ring, 1646 BUS_DMA_NOWAIT); 1647 if (error) 1648 return (ENOBUFS); 1649 1650 /* Load the DMA map for Rx return ring. */ 1651 error = bus_dmamap_load(sc->sc_dmat, sc->alc_cdata.alc_rr_ring_map, 1652 sc->alc_rdata.alc_rr_ring, ALC_RR_RING_SZ, NULL, BUS_DMA_WAITOK); 1653 if (error) { 1654 printf("%s: could not load DMA'able memory for Rx return ring." 1655 "\n", device_xname(sc->sc_dev)); 1656 bus_dmamem_free(sc->sc_dmat, 1657 &sc->alc_rdata.alc_rr_ring_seg, 1); 1658 return error; 1659 } 1660 1661 sc->alc_rdata.alc_rr_ring_paddr = 1662 sc->alc_cdata.alc_rr_ring_map->dm_segs[0].ds_addr; 1663 1664 /* 1665 * Create DMA stuffs for CMB block 1666 */ 1667 error = bus_dmamap_create(sc->sc_dmat, ALC_CMB_SZ, 1, 1668 ALC_CMB_SZ, 0, BUS_DMA_NOWAIT, 1669 &sc->alc_cdata.alc_cmb_map); 1670 if (error) 1671 return (ENOBUFS); 1672 1673 /* Allocate DMA'able memory for CMB block */ 1674 error = bus_dmamem_alloc(sc->sc_dmat, ALC_CMB_SZ, 1675 ETHER_ALIGN, 0, &sc->alc_rdata.alc_cmb_seg, 1, 1676 &nsegs, BUS_DMA_NOWAIT); 1677 if (error) { 1678 printf("%s: could not allocate DMA'able memory for " 1679 "CMB block\n", device_xname(sc->sc_dev)); 1680 return error; 1681 } 1682 1683 error = bus_dmamem_map(sc->sc_dmat, &sc->alc_rdata.alc_cmb_seg, 1684 nsegs, ALC_CMB_SZ, (void **)&sc->alc_rdata.alc_cmb, 1685 BUS_DMA_NOWAIT); 1686 if (error) 1687 return (ENOBUFS); 1688 1689 /* Load the DMA map for CMB block. */ 1690 error = bus_dmamap_load(sc->sc_dmat, sc->alc_cdata.alc_cmb_map, 1691 sc->alc_rdata.alc_cmb, ALC_CMB_SZ, NULL, 1692 BUS_DMA_WAITOK); 1693 if (error) { 1694 printf("%s: could not load DMA'able memory for CMB block\n", 1695 device_xname(sc->sc_dev)); 1696 bus_dmamem_free(sc->sc_dmat, 1697 &sc->alc_rdata.alc_cmb_seg, 1); 1698 return error; 1699 } 1700 1701 sc->alc_rdata.alc_cmb_paddr = 1702 sc->alc_cdata.alc_cmb_map->dm_segs[0].ds_addr; 1703 1704 /* 1705 * Create DMA stuffs for SMB block 1706 */ 1707 error = bus_dmamap_create(sc->sc_dmat, ALC_SMB_SZ, 1, 1708 ALC_SMB_SZ, 0, BUS_DMA_NOWAIT, 1709 &sc->alc_cdata.alc_smb_map); 1710 if (error) 1711 return (ENOBUFS); 1712 1713 /* Allocate DMA'able memory for SMB block */ 1714 error = bus_dmamem_alloc(sc->sc_dmat, ALC_SMB_SZ, 1715 ETHER_ALIGN, 0, &sc->alc_rdata.alc_smb_seg, 1, 1716 &nsegs, BUS_DMA_NOWAIT); 1717 if (error) { 1718 printf("%s: could not allocate DMA'able memory for " 1719 "SMB block\n", device_xname(sc->sc_dev)); 1720 return error; 1721 } 1722 1723 error = bus_dmamem_map(sc->sc_dmat, &sc->alc_rdata.alc_smb_seg, 1724 nsegs, ALC_SMB_SZ, (void **)&sc->alc_rdata.alc_smb, 1725 BUS_DMA_NOWAIT); 1726 if (error) 1727 return (ENOBUFS); 1728 1729 /* Load the DMA map for SMB block */ 1730 error = bus_dmamap_load(sc->sc_dmat, sc->alc_cdata.alc_smb_map, 1731 sc->alc_rdata.alc_smb, ALC_SMB_SZ, NULL, 1732 BUS_DMA_WAITOK); 1733 if (error) { 1734 printf("%s: could not load DMA'able memory for SMB block\n", 1735 device_xname(sc->sc_dev)); 1736 bus_dmamem_free(sc->sc_dmat, 1737 &sc->alc_rdata.alc_smb_seg, 1); 1738 return error; 1739 } 1740 1741 sc->alc_rdata.alc_smb_paddr = 1742 sc->alc_cdata.alc_smb_map->dm_segs[0].ds_addr; 1743 1744 1745 /* Create DMA maps for Tx buffers. */ 1746 for (i = 0; i < ALC_TX_RING_CNT; i++) { 1747 txd = &sc->alc_cdata.alc_txdesc[i]; 1748 txd->tx_m = NULL; 1749 txd->tx_dmamap = NULL; 1750 error = bus_dmamap_create(sc->sc_dmat, ALC_TSO_MAXSIZE, 1751 ALC_MAXTXSEGS, ALC_TSO_MAXSEGSIZE, 0, BUS_DMA_NOWAIT, 1752 &txd->tx_dmamap); 1753 if (error) { 1754 printf("%s: could not create Tx dmamap.\n", 1755 device_xname(sc->sc_dev)); 1756 return error; 1757 } 1758 } 1759 1760 /* Create DMA maps for Rx buffers. */ 1761 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES, 0, 1762 BUS_DMA_NOWAIT, &sc->alc_cdata.alc_rx_sparemap); 1763 if (error) { 1764 printf("%s: could not create spare Rx dmamap.\n", 1765 device_xname(sc->sc_dev)); 1766 return error; 1767 } 1768 1769 for (i = 0; i < ALC_RX_RING_CNT; i++) { 1770 rxd = &sc->alc_cdata.alc_rxdesc[i]; 1771 rxd->rx_m = NULL; 1772 rxd->rx_dmamap = NULL; 1773 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 1774 MCLBYTES, 0, BUS_DMA_NOWAIT, &rxd->rx_dmamap); 1775 if (error) { 1776 printf("%s: could not create Rx dmamap.\n", 1777 device_xname(sc->sc_dev)); 1778 return error; 1779 } 1780 } 1781 1782 return (0); 1783 } 1784 1785 1786 static void 1787 alc_dma_free(struct alc_softc *sc) 1788 { 1789 struct alc_txdesc *txd; 1790 struct alc_rxdesc *rxd; 1791 int i; 1792 1793 /* Tx buffers */ 1794 for (i = 0; i < ALC_TX_RING_CNT; i++) { 1795 txd = &sc->alc_cdata.alc_txdesc[i]; 1796 if (txd->tx_dmamap != NULL) { 1797 bus_dmamap_destroy(sc->sc_dmat, txd->tx_dmamap); 1798 txd->tx_dmamap = NULL; 1799 } 1800 } 1801 /* Rx buffers */ 1802 for (i = 0; i < ALC_RX_RING_CNT; i++) { 1803 rxd = &sc->alc_cdata.alc_rxdesc[i]; 1804 if (rxd->rx_dmamap != NULL) { 1805 bus_dmamap_destroy(sc->sc_dmat, rxd->rx_dmamap); 1806 rxd->rx_dmamap = NULL; 1807 } 1808 } 1809 if (sc->alc_cdata.alc_rx_sparemap != NULL) { 1810 bus_dmamap_destroy(sc->sc_dmat, sc->alc_cdata.alc_rx_sparemap); 1811 sc->alc_cdata.alc_rx_sparemap = NULL; 1812 } 1813 1814 /* Tx ring. */ 1815 if (sc->alc_cdata.alc_tx_ring_map != NULL) 1816 bus_dmamap_unload(sc->sc_dmat, sc->alc_cdata.alc_tx_ring_map); 1817 if (sc->alc_cdata.alc_tx_ring_map != NULL && 1818 sc->alc_rdata.alc_tx_ring != NULL) 1819 bus_dmamem_free(sc->sc_dmat, 1820 &sc->alc_rdata.alc_tx_ring_seg, 1); 1821 sc->alc_rdata.alc_tx_ring = NULL; 1822 sc->alc_cdata.alc_tx_ring_map = NULL; 1823 1824 /* Rx ring. */ 1825 if (sc->alc_cdata.alc_rx_ring_map != NULL) 1826 bus_dmamap_unload(sc->sc_dmat, sc->alc_cdata.alc_rx_ring_map); 1827 if (sc->alc_cdata.alc_rx_ring_map != NULL && 1828 sc->alc_rdata.alc_rx_ring != NULL) 1829 bus_dmamem_free(sc->sc_dmat, 1830 &sc->alc_rdata.alc_rx_ring_seg, 1); 1831 sc->alc_rdata.alc_rx_ring = NULL; 1832 sc->alc_cdata.alc_rx_ring_map = NULL; 1833 1834 /* Rx return ring. */ 1835 if (sc->alc_cdata.alc_rr_ring_map != NULL) 1836 bus_dmamap_unload(sc->sc_dmat, sc->alc_cdata.alc_rr_ring_map); 1837 if (sc->alc_cdata.alc_rr_ring_map != NULL && 1838 sc->alc_rdata.alc_rr_ring != NULL) 1839 bus_dmamem_free(sc->sc_dmat, 1840 &sc->alc_rdata.alc_rr_ring_seg, 1); 1841 sc->alc_rdata.alc_rr_ring = NULL; 1842 sc->alc_cdata.alc_rr_ring_map = NULL; 1843 1844 /* CMB block */ 1845 if (sc->alc_cdata.alc_cmb_map != NULL) 1846 bus_dmamap_unload(sc->sc_dmat, sc->alc_cdata.alc_cmb_map); 1847 if (sc->alc_cdata.alc_cmb_map != NULL && 1848 sc->alc_rdata.alc_cmb != NULL) 1849 bus_dmamem_free(sc->sc_dmat, 1850 &sc->alc_rdata.alc_cmb_seg, 1); 1851 sc->alc_rdata.alc_cmb = NULL; 1852 sc->alc_cdata.alc_cmb_map = NULL; 1853 1854 /* SMB block */ 1855 if (sc->alc_cdata.alc_smb_map != NULL) 1856 bus_dmamap_unload(sc->sc_dmat, sc->alc_cdata.alc_smb_map); 1857 if (sc->alc_cdata.alc_smb_map != NULL && 1858 sc->alc_rdata.alc_smb != NULL) 1859 bus_dmamem_free(sc->sc_dmat, 1860 &sc->alc_rdata.alc_smb_seg, 1); 1861 sc->alc_rdata.alc_smb = NULL; 1862 sc->alc_cdata.alc_smb_map = NULL; 1863 } 1864 1865 static int 1866 alc_encap(struct alc_softc *sc, struct mbuf **m_head) 1867 { 1868 struct alc_txdesc *txd, *txd_last; 1869 struct tx_desc *desc; 1870 struct mbuf *m; 1871 bus_dmamap_t map; 1872 uint32_t cflags, poff, vtag; 1873 int error, idx, nsegs, prod; 1874 1875 m = *m_head; 1876 cflags = vtag = 0; 1877 poff = 0; 1878 1879 prod = sc->alc_cdata.alc_tx_prod; 1880 txd = &sc->alc_cdata.alc_txdesc[prod]; 1881 txd_last = txd; 1882 map = txd->tx_dmamap; 1883 1884 error = bus_dmamap_load_mbuf(sc->sc_dmat, map, *m_head, BUS_DMA_NOWAIT); 1885 1886 if (error == EFBIG) { 1887 error = 0; 1888 1889 *m_head = m_pullup(*m_head, MHLEN); 1890 if (*m_head == NULL) { 1891 printf("%s: can't defrag TX mbuf\n", 1892 device_xname(sc->sc_dev)); 1893 return ENOBUFS; 1894 } 1895 1896 error = bus_dmamap_load_mbuf(sc->sc_dmat, map, *m_head, 1897 BUS_DMA_NOWAIT); 1898 1899 if (error != 0) { 1900 printf("%s: could not load defragged TX mbuf\n", 1901 device_xname(sc->sc_dev)); 1902 m_freem(*m_head); 1903 *m_head = NULL; 1904 return error; 1905 } 1906 } else if (error) { 1907 printf("%s: could not load TX mbuf\n", device_xname(sc->sc_dev)); 1908 return (error); 1909 } 1910 1911 nsegs = map->dm_nsegs; 1912 1913 if (nsegs == 0) { 1914 m_freem(*m_head); 1915 *m_head = NULL; 1916 return (EIO); 1917 } 1918 1919 /* Check descriptor overrun. */ 1920 if (sc->alc_cdata.alc_tx_cnt + nsegs >= ALC_TX_RING_CNT - 3) { 1921 bus_dmamap_unload(sc->sc_dmat, map); 1922 return (ENOBUFS); 1923 } 1924 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 1925 BUS_DMASYNC_PREWRITE); 1926 1927 m = *m_head; 1928 desc = NULL; 1929 idx = 0; 1930 #if NVLAN > 0 1931 /* Configure VLAN hardware tag insertion. */ 1932 if (vlan_has_tag(m)) { 1933 vtag = htons(vlan_get_tag(m)); 1934 vtag = (vtag << TD_VLAN_SHIFT) & TD_VLAN_MASK; 1935 cflags |= TD_INS_VLAN_TAG; 1936 } 1937 #endif 1938 /* Configure Tx checksum offload. */ 1939 if ((m->m_pkthdr.csum_flags & ALC_CSUM_FEATURES) != 0) { 1940 cflags |= TD_CUSTOM_CSUM; 1941 /* Set checksum start offset. */ 1942 cflags |= ((poff >> 1) << TD_PLOAD_OFFSET_SHIFT) & 1943 TD_PLOAD_OFFSET_MASK; 1944 } 1945 for (; idx < nsegs; idx++) { 1946 desc = &sc->alc_rdata.alc_tx_ring[prod]; 1947 desc->len = 1948 htole32(TX_BYTES(map->dm_segs[idx].ds_len) | vtag); 1949 desc->flags = htole32(cflags); 1950 desc->addr = htole64(map->dm_segs[idx].ds_addr); 1951 sc->alc_cdata.alc_tx_cnt++; 1952 ALC_DESC_INC(prod, ALC_TX_RING_CNT); 1953 } 1954 /* Update producer index. */ 1955 sc->alc_cdata.alc_tx_prod = prod; 1956 1957 /* Finally set EOP on the last descriptor. */ 1958 prod = (prod + ALC_TX_RING_CNT - 1) % ALC_TX_RING_CNT; 1959 desc = &sc->alc_rdata.alc_tx_ring[prod]; 1960 desc->flags |= htole32(TD_EOP); 1961 1962 /* Swap dmamap of the first and the last. */ 1963 txd = &sc->alc_cdata.alc_txdesc[prod]; 1964 map = txd_last->tx_dmamap; 1965 txd_last->tx_dmamap = txd->tx_dmamap; 1966 txd->tx_dmamap = map; 1967 txd->tx_m = m; 1968 1969 return (0); 1970 } 1971 1972 static void 1973 alc_start(struct ifnet *ifp) 1974 { 1975 struct alc_softc *sc = ifp->if_softc; 1976 struct mbuf *m_head; 1977 int enq; 1978 1979 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 1980 return; 1981 if ((sc->alc_flags & ALC_FLAG_LINK) == 0) 1982 return; 1983 if (IFQ_IS_EMPTY(&ifp->if_snd)) 1984 return; 1985 1986 /* Reclaim transmitted frames. */ 1987 if (sc->alc_cdata.alc_tx_cnt >= ALC_TX_DESC_HIWAT) 1988 alc_txeof(sc); 1989 1990 enq = 0; 1991 for (;;) { 1992 IFQ_DEQUEUE(&ifp->if_snd, m_head); 1993 if (m_head == NULL) 1994 break; 1995 1996 /* 1997 * Pack the data into the transmit ring. If we 1998 * don't have room, set the OACTIVE flag and wait 1999 * for the NIC to drain the ring. 2000 */ 2001 if (alc_encap(sc, &m_head)) { 2002 if (m_head == NULL) 2003 break; 2004 ifp->if_flags |= IFF_OACTIVE; 2005 break; 2006 } 2007 enq = 1; 2008 2009 /* 2010 * If there's a BPF listener, bounce a copy of this frame 2011 * to him. 2012 */ 2013 bpf_mtap(ifp, m_head, BPF_D_OUT); 2014 } 2015 2016 if (enq) { 2017 /* Sync descriptors. */ 2018 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_tx_ring_map, 0, 2019 sc->alc_cdata.alc_tx_ring_map->dm_mapsize, 2020 BUS_DMASYNC_PREWRITE); 2021 /* Kick. Assume we're using normal Tx priority queue. */ 2022 CSR_WRITE_4(sc, ALC_MBOX_TD_PROD_IDX, 2023 (sc->alc_cdata.alc_tx_prod << 2024 MBOX_TD_PROD_LO_IDX_SHIFT) & 2025 MBOX_TD_PROD_LO_IDX_MASK); 2026 /* Set a timeout in case the chip goes out to lunch. */ 2027 ifp->if_timer = ALC_TX_TIMEOUT; 2028 } 2029 } 2030 2031 static void 2032 alc_watchdog(struct ifnet *ifp) 2033 { 2034 struct alc_softc *sc = ifp->if_softc; 2035 2036 if ((sc->alc_flags & ALC_FLAG_LINK) == 0) { 2037 printf("%s: watchdog timeout (missed link)\n", 2038 device_xname(sc->sc_dev)); 2039 ifp->if_oerrors++; 2040 alc_init_backend(ifp, false); 2041 return; 2042 } 2043 2044 printf("%s: watchdog timeout\n", device_xname(sc->sc_dev)); 2045 ifp->if_oerrors++; 2046 alc_init_backend(ifp, false); 2047 alc_start(ifp); 2048 } 2049 2050 static int 2051 alc_ioctl(struct ifnet *ifp, u_long cmd, void *data) 2052 { 2053 struct alc_softc *sc = ifp->if_softc; 2054 struct mii_data *mii = &sc->sc_miibus; 2055 struct ifreq *ifr = (struct ifreq *)data; 2056 int s, error = 0; 2057 2058 s = splnet(); 2059 2060 error = ether_ioctl(ifp, cmd, data); 2061 switch (cmd) { 2062 case SIOCSIFADDR: 2063 ifp->if_flags |= IFF_UP; 2064 if (!(ifp->if_flags & IFF_RUNNING)) 2065 alc_init(ifp); 2066 break; 2067 2068 case SIOCSIFFLAGS: 2069 if (ifp->if_flags & IFF_UP) { 2070 if (ifp->if_flags & IFF_RUNNING) 2071 error = ENETRESET; 2072 else 2073 alc_init(ifp); 2074 } else { 2075 if (ifp->if_flags & IFF_RUNNING) 2076 alc_stop(ifp, 0); 2077 } 2078 break; 2079 2080 case SIOCSIFMEDIA: 2081 case SIOCGIFMEDIA: 2082 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd); 2083 break; 2084 2085 default: 2086 error = ether_ioctl(ifp, cmd, data); 2087 break; 2088 } 2089 2090 if (error == ENETRESET) { 2091 if (ifp->if_flags & IFF_RUNNING) 2092 alc_iff(sc); 2093 error = 0; 2094 } 2095 2096 splx(s); 2097 return (error); 2098 } 2099 2100 static void 2101 alc_mac_config(struct alc_softc *sc) 2102 { 2103 struct mii_data *mii; 2104 uint32_t reg; 2105 2106 mii = &sc->sc_miibus; 2107 reg = CSR_READ_4(sc, ALC_MAC_CFG); 2108 reg &= ~(MAC_CFG_FULL_DUPLEX | MAC_CFG_TX_FC | MAC_CFG_RX_FC | 2109 MAC_CFG_SPEED_MASK); 2110 if (sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8151 || 2111 sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8151_V2 || 2112 sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8152_B2) 2113 reg |= MAC_CFG_HASH_ALG_CRC32 | MAC_CFG_SPEED_MODE_SW; 2114 /* Reprogram MAC with resolved speed/duplex. */ 2115 switch (IFM_SUBTYPE(mii->mii_media_active)) { 2116 case IFM_10_T: 2117 case IFM_100_TX: 2118 reg |= MAC_CFG_SPEED_10_100; 2119 break; 2120 case IFM_1000_T: 2121 reg |= MAC_CFG_SPEED_1000; 2122 break; 2123 } 2124 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 2125 reg |= MAC_CFG_FULL_DUPLEX; 2126 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0) 2127 reg |= MAC_CFG_TX_FC; 2128 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0) 2129 reg |= MAC_CFG_RX_FC; 2130 } 2131 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 2132 } 2133 2134 static void 2135 alc_stats_clear(struct alc_softc *sc) 2136 { 2137 struct smb sb, *smb; 2138 uint32_t *reg; 2139 int i; 2140 2141 if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0) { 2142 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_smb_map, 0, 2143 sc->alc_cdata.alc_smb_map->dm_mapsize, 2144 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2145 smb = sc->alc_rdata.alc_smb; 2146 /* Update done, clear. */ 2147 smb->updated = 0; 2148 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_smb_map, 0, 2149 sc->alc_cdata.alc_smb_map->dm_mapsize, 2150 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2151 } else { 2152 for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered; 2153 reg++) { 2154 CSR_READ_4(sc, ALC_RX_MIB_BASE + i); 2155 i += sizeof(uint32_t); 2156 } 2157 /* Read Tx statistics. */ 2158 for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes; 2159 reg++) { 2160 CSR_READ_4(sc, ALC_TX_MIB_BASE + i); 2161 i += sizeof(uint32_t); 2162 } 2163 } 2164 } 2165 2166 static void 2167 alc_stats_update(struct alc_softc *sc) 2168 { 2169 struct ifnet *ifp = &sc->sc_ec.ec_if; 2170 struct alc_hw_stats *stat; 2171 struct smb sb, *smb; 2172 uint32_t *reg; 2173 int i; 2174 2175 stat = &sc->alc_stats; 2176 if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0) { 2177 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_smb_map, 0, 2178 sc->alc_cdata.alc_smb_map->dm_mapsize, 2179 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2180 smb = sc->alc_rdata.alc_smb; 2181 if (smb->updated == 0) 2182 return; 2183 } else { 2184 smb = &sb; 2185 /* Read Rx statistics. */ 2186 for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered; 2187 reg++) { 2188 *reg = CSR_READ_4(sc, ALC_RX_MIB_BASE + i); 2189 i += sizeof(uint32_t); 2190 } 2191 /* Read Tx statistics. */ 2192 for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes; 2193 reg++) { 2194 *reg = CSR_READ_4(sc, ALC_TX_MIB_BASE + i); 2195 i += sizeof(uint32_t); 2196 } 2197 } 2198 2199 /* Rx stats. */ 2200 stat->rx_frames += smb->rx_frames; 2201 stat->rx_bcast_frames += smb->rx_bcast_frames; 2202 stat->rx_mcast_frames += smb->rx_mcast_frames; 2203 stat->rx_pause_frames += smb->rx_pause_frames; 2204 stat->rx_control_frames += smb->rx_control_frames; 2205 stat->rx_crcerrs += smb->rx_crcerrs; 2206 stat->rx_lenerrs += smb->rx_lenerrs; 2207 stat->rx_bytes += smb->rx_bytes; 2208 stat->rx_runts += smb->rx_runts; 2209 stat->rx_fragments += smb->rx_fragments; 2210 stat->rx_pkts_64 += smb->rx_pkts_64; 2211 stat->rx_pkts_65_127 += smb->rx_pkts_65_127; 2212 stat->rx_pkts_128_255 += smb->rx_pkts_128_255; 2213 stat->rx_pkts_256_511 += smb->rx_pkts_256_511; 2214 stat->rx_pkts_512_1023 += smb->rx_pkts_512_1023; 2215 stat->rx_pkts_1024_1518 += smb->rx_pkts_1024_1518; 2216 stat->rx_pkts_1519_max += smb->rx_pkts_1519_max; 2217 stat->rx_pkts_truncated += smb->rx_pkts_truncated; 2218 stat->rx_fifo_oflows += smb->rx_fifo_oflows; 2219 stat->rx_rrs_errs += smb->rx_rrs_errs; 2220 stat->rx_alignerrs += smb->rx_alignerrs; 2221 stat->rx_bcast_bytes += smb->rx_bcast_bytes; 2222 stat->rx_mcast_bytes += smb->rx_mcast_bytes; 2223 stat->rx_pkts_filtered += smb->rx_pkts_filtered; 2224 2225 /* Tx stats. */ 2226 stat->tx_frames += smb->tx_frames; 2227 stat->tx_bcast_frames += smb->tx_bcast_frames; 2228 stat->tx_mcast_frames += smb->tx_mcast_frames; 2229 stat->tx_pause_frames += smb->tx_pause_frames; 2230 stat->tx_excess_defer += smb->tx_excess_defer; 2231 stat->tx_control_frames += smb->tx_control_frames; 2232 stat->tx_deferred += smb->tx_deferred; 2233 stat->tx_bytes += smb->tx_bytes; 2234 stat->tx_pkts_64 += smb->tx_pkts_64; 2235 stat->tx_pkts_65_127 += smb->tx_pkts_65_127; 2236 stat->tx_pkts_128_255 += smb->tx_pkts_128_255; 2237 stat->tx_pkts_256_511 += smb->tx_pkts_256_511; 2238 stat->tx_pkts_512_1023 += smb->tx_pkts_512_1023; 2239 stat->tx_pkts_1024_1518 += smb->tx_pkts_1024_1518; 2240 stat->tx_pkts_1519_max += smb->tx_pkts_1519_max; 2241 stat->tx_single_colls += smb->tx_single_colls; 2242 stat->tx_multi_colls += smb->tx_multi_colls; 2243 stat->tx_late_colls += smb->tx_late_colls; 2244 stat->tx_excess_colls += smb->tx_excess_colls; 2245 stat->tx_underrun += smb->tx_underrun; 2246 stat->tx_desc_underrun += smb->tx_desc_underrun; 2247 stat->tx_lenerrs += smb->tx_lenerrs; 2248 stat->tx_pkts_truncated += smb->tx_pkts_truncated; 2249 stat->tx_bcast_bytes += smb->tx_bcast_bytes; 2250 stat->tx_mcast_bytes += smb->tx_mcast_bytes; 2251 2252 /* Update counters in ifnet. */ 2253 ifp->if_opackets += smb->tx_frames; 2254 2255 ifp->if_collisions += smb->tx_single_colls + 2256 smb->tx_multi_colls * 2 + smb->tx_late_colls + 2257 smb->tx_excess_colls * HDPX_CFG_RETRY_DEFAULT; 2258 2259 ifp->if_oerrors += smb->tx_late_colls + smb->tx_excess_colls + 2260 smb->tx_underrun + smb->tx_pkts_truncated; 2261 2262 ifp->if_ipackets += smb->rx_frames; 2263 2264 ifp->if_ierrors += smb->rx_crcerrs + smb->rx_lenerrs + 2265 smb->rx_runts + smb->rx_pkts_truncated + 2266 smb->rx_fifo_oflows + smb->rx_rrs_errs + 2267 smb->rx_alignerrs; 2268 2269 if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0) { 2270 /* Update done, clear. */ 2271 smb->updated = 0; 2272 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_smb_map, 0, 2273 sc->alc_cdata.alc_smb_map->dm_mapsize, 2274 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2275 } 2276 } 2277 2278 static int 2279 alc_intr(void *arg) 2280 { 2281 struct alc_softc *sc = arg; 2282 struct ifnet *ifp = &sc->sc_ec.ec_if; 2283 uint32_t status; 2284 2285 status = CSR_READ_4(sc, ALC_INTR_STATUS); 2286 if ((status & ALC_INTRS) == 0) 2287 return (0); 2288 2289 /* Acknowledge and disable interrupts. */ 2290 CSR_WRITE_4(sc, ALC_INTR_STATUS, status | INTR_DIS_INT); 2291 2292 if (ifp->if_flags & IFF_RUNNING) { 2293 if (status & INTR_RX_PKT) { 2294 int error; 2295 2296 error = alc_rxintr(sc); 2297 if (error) { 2298 alc_init_backend(ifp, false); 2299 return (0); 2300 } 2301 } 2302 2303 if (status & (INTR_DMA_RD_TO_RST | INTR_DMA_WR_TO_RST | 2304 INTR_TXQ_TO_RST)) { 2305 if (status & INTR_DMA_RD_TO_RST) 2306 printf("%s: DMA read error! -- resetting\n", 2307 device_xname(sc->sc_dev)); 2308 if (status & INTR_DMA_WR_TO_RST) 2309 printf("%s: DMA write error! -- resetting\n", 2310 device_xname(sc->sc_dev)); 2311 if (status & INTR_TXQ_TO_RST) 2312 printf("%s: TxQ reset! -- resetting\n", 2313 device_xname(sc->sc_dev)); 2314 alc_init_backend(ifp, false); 2315 return (0); 2316 } 2317 2318 alc_txeof(sc); 2319 if_schedule_deferred_start(ifp); 2320 } 2321 2322 /* Re-enable interrupts. */ 2323 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0x7FFFFFFF); 2324 return (1); 2325 } 2326 2327 static void 2328 alc_txeof(struct alc_softc *sc) 2329 { 2330 struct ifnet *ifp = &sc->sc_ec.ec_if; 2331 struct alc_txdesc *txd; 2332 uint32_t cons, prod; 2333 int prog; 2334 2335 if (sc->alc_cdata.alc_tx_cnt == 0) 2336 return; 2337 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_tx_ring_map, 0, 2338 sc->alc_cdata.alc_tx_ring_map->dm_mapsize, 2339 BUS_DMASYNC_POSTREAD); 2340 if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0) { 2341 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_cmb_map, 0, 2342 sc->alc_cdata.alc_cmb_map->dm_mapsize, 2343 BUS_DMASYNC_POSTREAD); 2344 prod = sc->alc_rdata.alc_cmb->cons; 2345 } else 2346 prod = CSR_READ_4(sc, ALC_MBOX_TD_CONS_IDX); 2347 /* Assume we're using normal Tx priority queue. */ 2348 prod = (prod & MBOX_TD_CONS_LO_IDX_MASK) >> 2349 MBOX_TD_CONS_LO_IDX_SHIFT; 2350 cons = sc->alc_cdata.alc_tx_cons; 2351 /* 2352 * Go through our Tx list and free mbufs for those 2353 * frames which have been transmitted. 2354 */ 2355 for (prog = 0; cons != prod; prog++, 2356 ALC_DESC_INC(cons, ALC_TX_RING_CNT)) { 2357 if (sc->alc_cdata.alc_tx_cnt <= 0) 2358 break; 2359 prog++; 2360 ifp->if_flags &= ~IFF_OACTIVE; 2361 sc->alc_cdata.alc_tx_cnt--; 2362 txd = &sc->alc_cdata.alc_txdesc[cons]; 2363 if (txd->tx_m != NULL) { 2364 /* Reclaim transmitted mbufs. */ 2365 bus_dmamap_sync(sc->sc_dmat, txd->tx_dmamap, 0, 2366 txd->tx_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 2367 bus_dmamap_unload(sc->sc_dmat, txd->tx_dmamap); 2368 m_freem(txd->tx_m); 2369 txd->tx_m = NULL; 2370 } 2371 } 2372 2373 if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0) 2374 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_cmb_map, 0, 2375 sc->alc_cdata.alc_cmb_map->dm_mapsize, BUS_DMASYNC_PREREAD); 2376 sc->alc_cdata.alc_tx_cons = cons; 2377 /* 2378 * Unarm watchdog timer only when there is no pending 2379 * frames in Tx queue. 2380 */ 2381 if (sc->alc_cdata.alc_tx_cnt == 0) 2382 ifp->if_timer = 0; 2383 } 2384 2385 static int 2386 alc_newbuf(struct alc_softc *sc, struct alc_rxdesc *rxd, bool init) 2387 { 2388 struct mbuf *m; 2389 bus_dmamap_t map; 2390 int error; 2391 2392 MGETHDR(m, init ? M_WAITOK : M_DONTWAIT, MT_DATA); 2393 if (m == NULL) 2394 return (ENOBUFS); 2395 MCLGET(m, init ? M_WAITOK : M_DONTWAIT); 2396 if (!(m->m_flags & M_EXT)) { 2397 m_freem(m); 2398 return (ENOBUFS); 2399 } 2400 2401 m->m_len = m->m_pkthdr.len = RX_BUF_SIZE_MAX; 2402 2403 error = bus_dmamap_load_mbuf(sc->sc_dmat, 2404 sc->alc_cdata.alc_rx_sparemap, m, BUS_DMA_NOWAIT); 2405 2406 if (error != 0) { 2407 m_freem(m); 2408 2409 if (init) 2410 printf("%s: can't load RX mbuf\n", device_xname(sc->sc_dev)); 2411 2412 return (error); 2413 } 2414 2415 if (rxd->rx_m != NULL) { 2416 bus_dmamap_sync(sc->sc_dmat, rxd->rx_dmamap, 0, 2417 rxd->rx_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 2418 bus_dmamap_unload(sc->sc_dmat, rxd->rx_dmamap); 2419 } 2420 map = rxd->rx_dmamap; 2421 rxd->rx_dmamap = sc->alc_cdata.alc_rx_sparemap; 2422 sc->alc_cdata.alc_rx_sparemap = map; 2423 bus_dmamap_sync(sc->sc_dmat, rxd->rx_dmamap, 0, rxd->rx_dmamap->dm_mapsize, 2424 BUS_DMASYNC_PREREAD); 2425 rxd->rx_m = m; 2426 rxd->rx_desc->addr = htole64(rxd->rx_dmamap->dm_segs[0].ds_addr); 2427 return (0); 2428 } 2429 2430 static int 2431 alc_rxintr(struct alc_softc *sc) 2432 { 2433 struct ifnet *ifp = &sc->sc_ec.ec_if; 2434 struct rx_rdesc *rrd; 2435 uint32_t nsegs, status; 2436 int rr_cons, prog; 2437 2438 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_rr_ring_map, 0, 2439 sc->alc_cdata.alc_rr_ring_map->dm_mapsize, 2440 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2441 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_rx_ring_map, 0, 2442 sc->alc_cdata.alc_rx_ring_map->dm_mapsize, 2443 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2444 rr_cons = sc->alc_cdata.alc_rr_cons; 2445 for (prog = 0; (ifp->if_flags & IFF_RUNNING) != 0;) { 2446 rrd = &sc->alc_rdata.alc_rr_ring[rr_cons]; 2447 status = le32toh(rrd->status); 2448 if ((status & RRD_VALID) == 0) 2449 break; 2450 nsegs = RRD_RD_CNT(le32toh(rrd->rdinfo)); 2451 if (nsegs == 0) { 2452 /* This should not happen! */ 2453 if (alcdebug) 2454 printf("%s: unexpected segment count -- " 2455 "resetting\n", device_xname(sc->sc_dev)); 2456 return (EIO); 2457 } 2458 alc_rxeof(sc, rrd); 2459 /* Clear Rx return status. */ 2460 rrd->status = 0; 2461 ALC_DESC_INC(rr_cons, ALC_RR_RING_CNT); 2462 sc->alc_cdata.alc_rx_cons += nsegs; 2463 sc->alc_cdata.alc_rx_cons %= ALC_RR_RING_CNT; 2464 prog += nsegs; 2465 } 2466 2467 if (prog > 0) { 2468 /* Update the consumer index. */ 2469 sc->alc_cdata.alc_rr_cons = rr_cons; 2470 /* Sync Rx return descriptors. */ 2471 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_rr_ring_map, 0, 2472 sc->alc_cdata.alc_rr_ring_map->dm_mapsize, 2473 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2474 /* 2475 * Sync updated Rx descriptors such that controller see 2476 * modified buffer addresses. 2477 */ 2478 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_rx_ring_map, 0, 2479 sc->alc_cdata.alc_rx_ring_map->dm_mapsize, 2480 BUS_DMASYNC_PREWRITE); 2481 /* 2482 * Let controller know availability of new Rx buffers. 2483 * Since alc(4) use RXQ_CFG_RD_BURST_DEFAULT descriptors 2484 * it may be possible to update ALC_MBOX_RD0_PROD_IDX 2485 * only when Rx buffer pre-fetching is required. In 2486 * addition we already set ALC_RX_RD_FREE_THRESH to 2487 * RX_RD_FREE_THRESH_LO_DEFAULT descriptors. However 2488 * it still seems that pre-fetching needs more 2489 * experimentation. 2490 */ 2491 CSR_WRITE_4(sc, ALC_MBOX_RD0_PROD_IDX, 2492 sc->alc_cdata.alc_rx_cons); 2493 } 2494 2495 return (0); 2496 } 2497 2498 /* Receive a frame. */ 2499 static void 2500 alc_rxeof(struct alc_softc *sc, struct rx_rdesc *rrd) 2501 { 2502 struct ifnet *ifp = &sc->sc_ec.ec_if; 2503 struct alc_rxdesc *rxd; 2504 struct mbuf *mp, *m; 2505 uint32_t rdinfo, status; 2506 int count, nsegs, rx_cons; 2507 2508 status = le32toh(rrd->status); 2509 rdinfo = le32toh(rrd->rdinfo); 2510 rx_cons = RRD_RD_IDX(rdinfo); 2511 nsegs = RRD_RD_CNT(rdinfo); 2512 2513 sc->alc_cdata.alc_rxlen = RRD_BYTES(status); 2514 if (status & (RRD_ERR_SUM | RRD_ERR_LENGTH)) { 2515 /* 2516 * We want to pass the following frames to upper 2517 * layer regardless of error status of Rx return 2518 * ring. 2519 * 2520 * o IP/TCP/UDP checksum is bad. 2521 * o frame length and protocol specific length 2522 * does not match. 2523 * 2524 * Force network stack compute checksum for 2525 * errored frames. 2526 */ 2527 status |= RRD_TCP_UDPCSUM_NOK | RRD_IPCSUM_NOK; 2528 if ((status & (RRD_ERR_CRC | RRD_ERR_ALIGN | 2529 RRD_ERR_TRUNC | RRD_ERR_RUNT)) != 0) 2530 return; 2531 } 2532 2533 for (count = 0; count < nsegs; count++, 2534 ALC_DESC_INC(rx_cons, ALC_RX_RING_CNT)) { 2535 rxd = &sc->alc_cdata.alc_rxdesc[rx_cons]; 2536 mp = rxd->rx_m; 2537 /* Add a new receive buffer to the ring. */ 2538 if (alc_newbuf(sc, rxd, false) != 0) { 2539 ifp->if_iqdrops++; 2540 /* Reuse Rx buffers. */ 2541 if (sc->alc_cdata.alc_rxhead != NULL) 2542 m_freem(sc->alc_cdata.alc_rxhead); 2543 break; 2544 } 2545 2546 /* 2547 * Assume we've received a full sized frame. 2548 * Actual size is fixed when we encounter the end of 2549 * multi-segmented frame. 2550 */ 2551 mp->m_len = sc->alc_buf_size; 2552 2553 /* Chain received mbufs. */ 2554 if (sc->alc_cdata.alc_rxhead == NULL) { 2555 sc->alc_cdata.alc_rxhead = mp; 2556 sc->alc_cdata.alc_rxtail = mp; 2557 } else { 2558 m_remove_pkthdr(mp); 2559 sc->alc_cdata.alc_rxprev_tail = 2560 sc->alc_cdata.alc_rxtail; 2561 sc->alc_cdata.alc_rxtail->m_next = mp; 2562 sc->alc_cdata.alc_rxtail = mp; 2563 } 2564 2565 if (count == nsegs - 1) { 2566 /* Last desc. for this frame. */ 2567 m = sc->alc_cdata.alc_rxhead; 2568 KASSERT(m->m_flags & M_PKTHDR); 2569 /* 2570 * It seems that L1C/L2C controller has no way 2571 * to tell hardware to strip CRC bytes. 2572 */ 2573 m->m_pkthdr.len = 2574 sc->alc_cdata.alc_rxlen - ETHER_CRC_LEN; 2575 if (nsegs > 1) { 2576 /* Set last mbuf size. */ 2577 mp->m_len = sc->alc_cdata.alc_rxlen - 2578 (nsegs - 1) * sc->alc_buf_size; 2579 /* Remove the CRC bytes in chained mbufs. */ 2580 if (mp->m_len <= ETHER_CRC_LEN) { 2581 sc->alc_cdata.alc_rxtail = 2582 sc->alc_cdata.alc_rxprev_tail; 2583 sc->alc_cdata.alc_rxtail->m_len -= 2584 (ETHER_CRC_LEN - mp->m_len); 2585 sc->alc_cdata.alc_rxtail->m_next = NULL; 2586 m_freem(mp); 2587 } else { 2588 mp->m_len -= ETHER_CRC_LEN; 2589 } 2590 } else 2591 m->m_len = m->m_pkthdr.len; 2592 m_set_rcvif(m, ifp); 2593 #if NVLAN > 0 2594 /* 2595 * Due to hardware bugs, Rx checksum offloading 2596 * was intentionally disabled. 2597 */ 2598 if (status & RRD_VLAN_TAG) { 2599 u_int32_t vtag = RRD_VLAN(le32toh(rrd->vtag)); 2600 vlan_set_tag(m, ntohs(vtag)); 2601 } 2602 #endif 2603 2604 /* Pass it on. */ 2605 if_percpuq_enqueue(ifp->if_percpuq, m); 2606 } 2607 } 2608 /* Reset mbuf chains. */ 2609 ALC_RXCHAIN_RESET(sc); 2610 } 2611 2612 static void 2613 alc_tick(void *xsc) 2614 { 2615 struct alc_softc *sc = xsc; 2616 struct mii_data *mii = &sc->sc_miibus; 2617 int s; 2618 2619 s = splnet(); 2620 mii_tick(mii); 2621 alc_stats_update(sc); 2622 splx(s); 2623 2624 callout_schedule(&sc->sc_tick_ch, hz); 2625 } 2626 2627 static void 2628 alc_osc_reset(struct alc_softc *sc) 2629 { 2630 uint32_t reg; 2631 2632 reg = CSR_READ_4(sc, ALC_MISC3); 2633 reg &= ~MISC3_25M_BY_SW; 2634 reg |= MISC3_25M_NOTO_INTNL; 2635 CSR_WRITE_4(sc, ALC_MISC3, reg); 2636 2637 reg = CSR_READ_4(sc, ALC_MISC); 2638 if (AR816X_REV(sc->alc_rev) >= AR816X_REV_B0) { 2639 /* 2640 * Restore over-current protection default value. 2641 * This value could be reset by MAC reset. 2642 */ 2643 reg &= ~MISC_PSW_OCP_MASK; 2644 reg |= (MISC_PSW_OCP_DEFAULT << MISC_PSW_OCP_SHIFT); 2645 reg &= ~MISC_INTNLOSC_OPEN; 2646 CSR_WRITE_4(sc, ALC_MISC, reg); 2647 CSR_WRITE_4(sc, ALC_MISC, reg | MISC_INTNLOSC_OPEN); 2648 reg = CSR_READ_4(sc, ALC_MISC2); 2649 reg &= ~MISC2_CALB_START; 2650 CSR_WRITE_4(sc, ALC_MISC2, reg); 2651 CSR_WRITE_4(sc, ALC_MISC2, reg | MISC2_CALB_START); 2652 2653 } else { 2654 reg &= ~MISC_INTNLOSC_OPEN; 2655 /* Disable isolate for revision A devices. */ 2656 if (AR816X_REV(sc->alc_rev) <= AR816X_REV_A1) 2657 reg &= ~MISC_ISO_ENB; 2658 CSR_WRITE_4(sc, ALC_MISC, reg | MISC_INTNLOSC_OPEN); 2659 CSR_WRITE_4(sc, ALC_MISC, reg); 2660 } 2661 2662 DELAY(20); 2663 } 2664 2665 static void 2666 alc_reset(struct alc_softc *sc) 2667 { 2668 uint32_t pmcfg, reg; 2669 int i; 2670 2671 pmcfg = 0; 2672 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 2673 /* Reset workaround. */ 2674 CSR_WRITE_4(sc, ALC_MBOX_RD0_PROD_IDX, 1); 2675 if (AR816X_REV(sc->alc_rev) <= AR816X_REV_A1 && 2676 (sc->alc_rev & 0x01) != 0) { 2677 /* Disable L0s/L1s before reset. */ 2678 pmcfg = CSR_READ_4(sc, ALC_PM_CFG); 2679 if ((pmcfg & (PM_CFG_ASPM_L0S_ENB | PM_CFG_ASPM_L1_ENB)) 2680 != 0) { 2681 pmcfg &= ~(PM_CFG_ASPM_L0S_ENB | 2682 PM_CFG_ASPM_L1_ENB); 2683 CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg); 2684 } 2685 } 2686 } 2687 reg = CSR_READ_4(sc, ALC_MASTER_CFG); 2688 reg |= MASTER_OOB_DIS_OFF | MASTER_RESET; 2689 CSR_WRITE_4(sc, ALC_MASTER_CFG, reg); 2690 2691 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 2692 for (i = ALC_RESET_TIMEOUT; i > 0; i--) { 2693 DELAY(10); 2694 if (CSR_READ_4(sc, ALC_MBOX_RD0_PROD_IDX) == 0) 2695 break; 2696 } 2697 if (i == 0) 2698 printf("%s: MAC reset timeout!\n", device_xname(sc->sc_dev)); 2699 } 2700 for (i = ALC_RESET_TIMEOUT; i > 0; i--) { 2701 DELAY(10); 2702 if ((CSR_READ_4(sc, ALC_MASTER_CFG) & MASTER_RESET) == 0) 2703 break; 2704 } 2705 if (i == 0) 2706 printf("%s: master reset timeout!\n", device_xname(sc->sc_dev)); 2707 2708 for (i = ALC_RESET_TIMEOUT; i > 0; i--) { 2709 reg = CSR_READ_4(sc, ALC_IDLE_STATUS); 2710 if ((reg & (IDLE_STATUS_RXMAC | IDLE_STATUS_TXMAC | 2711 IDLE_STATUS_RXQ | IDLE_STATUS_TXQ)) == 0) 2712 break; 2713 DELAY(10); 2714 } 2715 if (i == 0) 2716 printf("%s: reset timeout(0x%08x)!\n", 2717 device_xname(sc->sc_dev), reg); 2718 2719 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 2720 if (AR816X_REV(sc->alc_rev) <= AR816X_REV_A1 && 2721 (sc->alc_rev & 0x01) != 0) { 2722 reg = CSR_READ_4(sc, ALC_MASTER_CFG); 2723 reg |= MASTER_CLK_SEL_DIS; 2724 CSR_WRITE_4(sc, ALC_MASTER_CFG, reg); 2725 /* Restore L0s/L1s config. */ 2726 if ((pmcfg & (PM_CFG_ASPM_L0S_ENB | PM_CFG_ASPM_L1_ENB)) 2727 != 0) 2728 CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg); 2729 } 2730 2731 alc_osc_reset(sc); 2732 reg = CSR_READ_4(sc, ALC_MISC3); 2733 reg &= ~MISC3_25M_BY_SW; 2734 reg |= MISC3_25M_NOTO_INTNL; 2735 CSR_WRITE_4(sc, ALC_MISC3, reg); 2736 reg = CSR_READ_4(sc, ALC_MISC); 2737 reg &= ~MISC_INTNLOSC_OPEN; 2738 if (AR816X_REV(sc->alc_rev) <= AR816X_REV_A1) 2739 reg &= ~MISC_ISO_ENB; 2740 CSR_WRITE_4(sc, ALC_MISC, reg); 2741 DELAY(20); 2742 } 2743 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0 || 2744 sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8152_B || 2745 sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8151_V2) 2746 CSR_WRITE_4(sc, ALC_SERDES_LOCK, 2747 CSR_READ_4(sc, ALC_SERDES_LOCK) | SERDES_MAC_CLK_SLOWDOWN | 2748 SERDES_PHY_CLK_SLOWDOWN); 2749 } 2750 2751 static int 2752 alc_init(struct ifnet *ifp) 2753 { 2754 2755 return alc_init_backend(ifp, true); 2756 } 2757 2758 static int 2759 alc_init_backend(struct ifnet *ifp, bool init) 2760 { 2761 struct alc_softc *sc = ifp->if_softc; 2762 struct mii_data *mii; 2763 uint8_t eaddr[ETHER_ADDR_LEN]; 2764 bus_addr_t paddr; 2765 uint32_t reg, rxf_hi, rxf_lo; 2766 int error; 2767 2768 /* 2769 * Cancel any pending I/O. 2770 */ 2771 alc_stop(ifp, 0); 2772 /* 2773 * Reset the chip to a known state. 2774 */ 2775 alc_reset(sc); 2776 2777 /* Initialize Rx descriptors. */ 2778 error = alc_init_rx_ring(sc, init); 2779 if (error != 0) { 2780 printf("%s: no memory for Rx buffers.\n", device_xname(sc->sc_dev)); 2781 alc_stop(ifp, 0); 2782 return (error); 2783 } 2784 alc_init_rr_ring(sc); 2785 alc_init_tx_ring(sc); 2786 alc_init_cmb(sc); 2787 alc_init_smb(sc); 2788 2789 /* Enable all clocks. */ 2790 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 2791 CSR_WRITE_4(sc, ALC_CLK_GATING_CFG, CLK_GATING_DMAW_ENB | 2792 CLK_GATING_DMAR_ENB | CLK_GATING_TXQ_ENB | 2793 CLK_GATING_RXQ_ENB | CLK_GATING_TXMAC_ENB | 2794 CLK_GATING_RXMAC_ENB); 2795 if (AR816X_REV(sc->alc_rev) >= AR816X_REV_B0) 2796 CSR_WRITE_4(sc, ALC_IDLE_DECISN_TIMER, 2797 IDLE_DECISN_TIMER_DEFAULT_1MS); 2798 } else 2799 CSR_WRITE_4(sc, ALC_CLK_GATING_CFG, 0); 2800 2801 2802 /* Reprogram the station address. */ 2803 memcpy(eaddr, CLLADDR(ifp->if_sadl), sizeof(eaddr)); 2804 CSR_WRITE_4(sc, ALC_PAR0, 2805 eaddr[2] << 24 | eaddr[3] << 16 | eaddr[4] << 8 | eaddr[5]); 2806 CSR_WRITE_4(sc, ALC_PAR1, eaddr[0] << 8 | eaddr[1]); 2807 /* 2808 * Clear WOL status and disable all WOL feature as WOL 2809 * would interfere Rx operation under normal environments. 2810 */ 2811 CSR_READ_4(sc, ALC_WOL_CFG); 2812 CSR_WRITE_4(sc, ALC_WOL_CFG, 0); 2813 /* Set Tx descriptor base addresses. */ 2814 paddr = sc->alc_rdata.alc_tx_ring_paddr; 2815 CSR_WRITE_4(sc, ALC_TX_BASE_ADDR_HI, ALC_ADDR_HI(paddr)); 2816 CSR_WRITE_4(sc, ALC_TDL_HEAD_ADDR_LO, ALC_ADDR_LO(paddr)); 2817 /* We don't use high priority ring. */ 2818 CSR_WRITE_4(sc, ALC_TDH_HEAD_ADDR_LO, 0); 2819 /* Set Tx descriptor counter. */ 2820 CSR_WRITE_4(sc, ALC_TD_RING_CNT, 2821 (ALC_TX_RING_CNT << TD_RING_CNT_SHIFT) & TD_RING_CNT_MASK); 2822 /* Set Rx descriptor base addresses. */ 2823 paddr = sc->alc_rdata.alc_rx_ring_paddr; 2824 CSR_WRITE_4(sc, ALC_RX_BASE_ADDR_HI, ALC_ADDR_HI(paddr)); 2825 CSR_WRITE_4(sc, ALC_RD0_HEAD_ADDR_LO, ALC_ADDR_LO(paddr)); 2826 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 2827 /* We use one Rx ring. */ 2828 CSR_WRITE_4(sc, ALC_RD1_HEAD_ADDR_LO, 0); 2829 CSR_WRITE_4(sc, ALC_RD2_HEAD_ADDR_LO, 0); 2830 CSR_WRITE_4(sc, ALC_RD3_HEAD_ADDR_LO, 0); 2831 } 2832 /* Set Rx descriptor counter. */ 2833 CSR_WRITE_4(sc, ALC_RD_RING_CNT, 2834 (ALC_RX_RING_CNT << RD_RING_CNT_SHIFT) & RD_RING_CNT_MASK); 2835 2836 /* 2837 * Let hardware split jumbo frames into alc_max_buf_sized chunks. 2838 * if it do not fit the buffer size. Rx return descriptor holds 2839 * a counter that indicates how many fragments were made by the 2840 * hardware. The buffer size should be multiple of 8 bytes. 2841 * Since hardware has limit on the size of buffer size, always 2842 * use the maximum value. 2843 * For strict-alignment architectures make sure to reduce buffer 2844 * size by 8 bytes to make room for alignment fixup. 2845 */ 2846 sc->alc_buf_size = RX_BUF_SIZE_MAX; 2847 CSR_WRITE_4(sc, ALC_RX_BUF_SIZE, sc->alc_buf_size); 2848 2849 paddr = sc->alc_rdata.alc_rr_ring_paddr; 2850 /* Set Rx return descriptor base addresses. */ 2851 CSR_WRITE_4(sc, ALC_RRD0_HEAD_ADDR_LO, ALC_ADDR_LO(paddr)); 2852 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 2853 /* We use one Rx return ring. */ 2854 CSR_WRITE_4(sc, ALC_RRD1_HEAD_ADDR_LO, 0); 2855 CSR_WRITE_4(sc, ALC_RRD2_HEAD_ADDR_LO, 0); 2856 CSR_WRITE_4(sc, ALC_RRD3_HEAD_ADDR_LO, 0); 2857 }\ 2858 /* Set Rx return descriptor counter. */ 2859 CSR_WRITE_4(sc, ALC_RRD_RING_CNT, 2860 (ALC_RR_RING_CNT << RRD_RING_CNT_SHIFT) & RRD_RING_CNT_MASK); 2861 paddr = sc->alc_rdata.alc_cmb_paddr; 2862 CSR_WRITE_4(sc, ALC_CMB_BASE_ADDR_LO, ALC_ADDR_LO(paddr)); 2863 paddr = sc->alc_rdata.alc_smb_paddr; 2864 CSR_WRITE_4(sc, ALC_SMB_BASE_ADDR_HI, ALC_ADDR_HI(paddr)); 2865 CSR_WRITE_4(sc, ALC_SMB_BASE_ADDR_LO, ALC_ADDR_LO(paddr)); 2866 2867 if (sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8152_B) { 2868 /* Reconfigure SRAM - Vendor magic. */ 2869 CSR_WRITE_4(sc, ALC_SRAM_RX_FIFO_LEN, 0x000002A0); 2870 CSR_WRITE_4(sc, ALC_SRAM_TX_FIFO_LEN, 0x00000100); 2871 CSR_WRITE_4(sc, ALC_SRAM_RX_FIFO_ADDR, 0x029F0000); 2872 CSR_WRITE_4(sc, ALC_SRAM_RD0_ADDR, 0x02BF02A0); 2873 CSR_WRITE_4(sc, ALC_SRAM_TX_FIFO_ADDR, 0x03BF02C0); 2874 CSR_WRITE_4(sc, ALC_SRAM_TD_ADDR, 0x03DF03C0); 2875 CSR_WRITE_4(sc, ALC_TXF_WATER_MARK, 0x00000000); 2876 CSR_WRITE_4(sc, ALC_RD_DMA_CFG, 0x00000000); 2877 } 2878 2879 /* Tell hardware that we're ready to load DMA blocks. */ 2880 CSR_WRITE_4(sc, ALC_DMA_BLOCK, DMA_BLOCK_LOAD); 2881 2882 /* Configure interrupt moderation timer. */ 2883 sc->alc_int_rx_mod = ALC_IM_RX_TIMER_DEFAULT; 2884 sc->alc_int_tx_mod = ALC_IM_TX_TIMER_DEFAULT; 2885 reg = ALC_USECS(sc->alc_int_rx_mod) << IM_TIMER_RX_SHIFT; 2886 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) 2887 reg |= ALC_USECS(sc->alc_int_tx_mod) << IM_TIMER_TX_SHIFT; 2888 CSR_WRITE_4(sc, ALC_IM_TIMER, reg); 2889 /* 2890 * We don't want to automatic interrupt clear as task queue 2891 * for the interrupt should know interrupt status. 2892 */ 2893 reg = CSR_READ_4(sc, ALC_MASTER_CFG); 2894 reg &= ~(MASTER_IM_RX_TIMER_ENB | MASTER_IM_TX_TIMER_ENB); 2895 reg |= MASTER_SA_TIMER_ENB; 2896 if (ALC_USECS(sc->alc_int_rx_mod) != 0) 2897 reg |= MASTER_IM_RX_TIMER_ENB; 2898 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0 && 2899 ALC_USECS(sc->alc_int_tx_mod) != 0) 2900 reg |= MASTER_IM_TX_TIMER_ENB; 2901 CSR_WRITE_4(sc, ALC_MASTER_CFG, reg); 2902 /* 2903 * Disable interrupt re-trigger timer. We don't want automatic 2904 * re-triggering of un-ACKed interrupts. 2905 */ 2906 CSR_WRITE_4(sc, ALC_INTR_RETRIG_TIMER, ALC_USECS(0)); 2907 /* Configure CMB. */ 2908 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 2909 CSR_WRITE_4(sc, ALC_CMB_TD_THRESH, ALC_TX_RING_CNT / 3); 2910 CSR_WRITE_4(sc, ALC_CMB_TX_TIMER, 2911 ALC_USECS(sc->alc_int_tx_mod)); 2912 } else { 2913 if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0) { 2914 CSR_WRITE_4(sc, ALC_CMB_TD_THRESH, 4); 2915 CSR_WRITE_4(sc, ALC_CMB_TX_TIMER, ALC_USECS(5000)); 2916 } else 2917 CSR_WRITE_4(sc, ALC_CMB_TX_TIMER, ALC_USECS(0)); 2918 } 2919 /* 2920 * Hardware can be configured to issue SMB interrupt based 2921 * on programmed interval. Since there is a callout that is 2922 * invoked for every hz in driver we use that instead of 2923 * relying on periodic SMB interrupt. 2924 */ 2925 CSR_WRITE_4(sc, ALC_SMB_STAT_TIMER, ALC_USECS(0)); 2926 /* Clear MAC statistics. */ 2927 alc_stats_clear(sc); 2928 2929 /* 2930 * Always use maximum frame size that controller can support. 2931 * Otherwise received frames that has larger frame length 2932 * than alc(4) MTU would be silently dropped in hardware. This 2933 * would make path-MTU discovery hard as sender wouldn't get 2934 * any responses from receiver. alc(4) supports 2935 * multi-fragmented frames on Rx path so it has no issue on 2936 * assembling fragmented frames. Using maximum frame size also 2937 * removes the need to reinitialize hardware when interface 2938 * MTU configuration was changed. 2939 * 2940 * Be conservative in what you do, be liberal in what you 2941 * accept from others - RFC 793. 2942 */ 2943 CSR_WRITE_4(sc, ALC_FRAME_SIZE, sc->alc_ident->max_framelen); 2944 2945 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 2946 /* Disable header split(?) */ 2947 CSR_WRITE_4(sc, ALC_HDS_CFG, 0); 2948 2949 /* Configure IPG/IFG parameters. */ 2950 CSR_WRITE_4(sc, ALC_IPG_IFG_CFG, 2951 ((IPG_IFG_IPGT_DEFAULT << IPG_IFG_IPGT_SHIFT) & 2952 IPG_IFG_IPGT_MASK) | 2953 ((IPG_IFG_MIFG_DEFAULT << IPG_IFG_MIFG_SHIFT) & 2954 IPG_IFG_MIFG_MASK) | 2955 ((IPG_IFG_IPG1_DEFAULT << IPG_IFG_IPG1_SHIFT) & 2956 IPG_IFG_IPG1_MASK) | 2957 ((IPG_IFG_IPG2_DEFAULT << IPG_IFG_IPG2_SHIFT) & 2958 IPG_IFG_IPG2_MASK)); 2959 /* Set parameters for half-duplex media. */ 2960 CSR_WRITE_4(sc, ALC_HDPX_CFG, 2961 ((HDPX_CFG_LCOL_DEFAULT << HDPX_CFG_LCOL_SHIFT) & 2962 HDPX_CFG_LCOL_MASK) | 2963 ((HDPX_CFG_RETRY_DEFAULT << HDPX_CFG_RETRY_SHIFT) & 2964 HDPX_CFG_RETRY_MASK) | HDPX_CFG_EXC_DEF_EN | 2965 ((HDPX_CFG_ABEBT_DEFAULT << HDPX_CFG_ABEBT_SHIFT) & 2966 HDPX_CFG_ABEBT_MASK) | 2967 ((HDPX_CFG_JAMIPG_DEFAULT << HDPX_CFG_JAMIPG_SHIFT) & 2968 HDPX_CFG_JAMIPG_MASK)); 2969 } 2970 2971 /* 2972 * Set TSO/checksum offload threshold. For frames that is 2973 * larger than this threshold, hardware wouldn't do 2974 * TSO/checksum offloading. 2975 */ 2976 reg = (sc->alc_ident->max_framelen >> TSO_OFFLOAD_THRESH_UNIT_SHIFT) & 2977 TSO_OFFLOAD_THRESH_MASK; 2978 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 2979 reg |= TSO_OFFLOAD_ERRLGPKT_DROP_ENB; 2980 CSR_WRITE_4(sc, ALC_TSO_OFFLOAD_THRESH, reg); 2981 /* Configure TxQ. */ 2982 reg = (alc_dma_burst[sc->alc_dma_rd_burst] << 2983 TXQ_CFG_TX_FIFO_BURST_SHIFT) & TXQ_CFG_TX_FIFO_BURST_MASK; 2984 if (sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8152_B || 2985 sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8152_B2) 2986 reg >>= 1; 2987 reg |= (TXQ_CFG_TD_BURST_DEFAULT << TXQ_CFG_TD_BURST_SHIFT) & 2988 TXQ_CFG_TD_BURST_MASK; 2989 reg |= TXQ_CFG_IP_OPTION_ENB | TXQ_CFG_8023_ENB; 2990 CSR_WRITE_4(sc, ALC_TXQ_CFG, reg | TXQ_CFG_ENHANCED_MODE); 2991 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 2992 reg = (TXQ_CFG_TD_BURST_DEFAULT << HQTD_CFG_Q1_BURST_SHIFT | 2993 TXQ_CFG_TD_BURST_DEFAULT << HQTD_CFG_Q2_BURST_SHIFT | 2994 TXQ_CFG_TD_BURST_DEFAULT << HQTD_CFG_Q3_BURST_SHIFT | 2995 HQTD_CFG_BURST_ENB); 2996 CSR_WRITE_4(sc, ALC_HQTD_CFG, reg); 2997 reg = WRR_PRI_RESTRICT_NONE; 2998 reg |= (WRR_PRI_DEFAULT << WRR_PRI0_SHIFT | 2999 WRR_PRI_DEFAULT << WRR_PRI1_SHIFT | 3000 WRR_PRI_DEFAULT << WRR_PRI2_SHIFT | 3001 WRR_PRI_DEFAULT << WRR_PRI3_SHIFT); 3002 CSR_WRITE_4(sc, ALC_WRR, reg); 3003 } else { 3004 /* Configure Rx free descriptor pre-fetching. */ 3005 CSR_WRITE_4(sc, ALC_RX_RD_FREE_THRESH, 3006 ((RX_RD_FREE_THRESH_HI_DEFAULT << 3007 RX_RD_FREE_THRESH_HI_SHIFT) & RX_RD_FREE_THRESH_HI_MASK) | 3008 ((RX_RD_FREE_THRESH_LO_DEFAULT << 3009 RX_RD_FREE_THRESH_LO_SHIFT) & RX_RD_FREE_THRESH_LO_MASK)); 3010 } 3011 3012 /* 3013 * Configure flow control parameters. 3014 * XON : 80% of Rx FIFO 3015 * XOFF : 30% of Rx FIFO 3016 */ 3017 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 3018 reg = CSR_READ_4(sc, ALC_SRAM_RX_FIFO_LEN); 3019 reg &= SRAM_RX_FIFO_LEN_MASK; 3020 reg *= 8; 3021 if (reg > 8 * 1024) 3022 reg -= RX_FIFO_PAUSE_816X_RSVD; 3023 else 3024 reg -= RX_BUF_SIZE_MAX; 3025 reg /= 8; 3026 CSR_WRITE_4(sc, ALC_RX_FIFO_PAUSE_THRESH, 3027 ((reg << RX_FIFO_PAUSE_THRESH_LO_SHIFT) & 3028 RX_FIFO_PAUSE_THRESH_LO_MASK) | 3029 (((RX_FIFO_PAUSE_816X_RSVD / 8) << 3030 RX_FIFO_PAUSE_THRESH_HI_SHIFT) & 3031 RX_FIFO_PAUSE_THRESH_HI_MASK)); 3032 } else if (sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8131 || 3033 sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8132) { 3034 reg = CSR_READ_4(sc, ALC_SRAM_RX_FIFO_LEN); 3035 rxf_hi = (reg * 8) / 10; 3036 rxf_lo = (reg * 3) / 10; 3037 CSR_WRITE_4(sc, ALC_RX_FIFO_PAUSE_THRESH, 3038 ((rxf_lo << RX_FIFO_PAUSE_THRESH_LO_SHIFT) & 3039 RX_FIFO_PAUSE_THRESH_LO_MASK) | 3040 ((rxf_hi << RX_FIFO_PAUSE_THRESH_HI_SHIFT) & 3041 RX_FIFO_PAUSE_THRESH_HI_MASK)); 3042 } 3043 3044 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 3045 /* Disable RSS until I understand L1C/L2C's RSS logic. */ 3046 CSR_WRITE_4(sc, ALC_RSS_IDT_TABLE0, 0); 3047 CSR_WRITE_4(sc, ALC_RSS_CPU, 0); 3048 } 3049 3050 /* Configure RxQ. */ 3051 reg = (RXQ_CFG_RD_BURST_DEFAULT << RXQ_CFG_RD_BURST_SHIFT) & 3052 RXQ_CFG_RD_BURST_MASK; 3053 reg |= RXQ_CFG_RSS_MODE_DIS; 3054 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 3055 reg |= (RXQ_CFG_816X_IDT_TBL_SIZE_DEFAULT << 3056 RXQ_CFG_816X_IDT_TBL_SIZE_SHIFT) & 3057 RXQ_CFG_816X_IDT_TBL_SIZE_MASK; 3058 if ((sc->alc_flags & ALC_FLAG_FASTETHER) == 0 && 3059 sc->alc_ident->deviceid != PCI_PRODUCT_ATTANSIC_AR8151_V2) 3060 reg |= RXQ_CFG_ASPM_THROUGHPUT_LIMIT_1M; 3061 CSR_WRITE_4(sc, ALC_RXQ_CFG, reg); 3062 3063 /* Configure DMA parameters. */ 3064 reg = DMA_CFG_OUT_ORDER | DMA_CFG_RD_REQ_PRI; 3065 reg |= sc->alc_rcb; 3066 if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0) 3067 reg |= DMA_CFG_CMB_ENB; 3068 if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0) 3069 reg |= DMA_CFG_SMB_ENB; 3070 else 3071 reg |= DMA_CFG_SMB_DIS; 3072 reg |= (sc->alc_dma_rd_burst & DMA_CFG_RD_BURST_MASK) << 3073 DMA_CFG_RD_BURST_SHIFT; 3074 reg |= (sc->alc_dma_wr_burst & DMA_CFG_WR_BURST_MASK) << 3075 DMA_CFG_WR_BURST_SHIFT; 3076 reg |= (DMA_CFG_RD_DELAY_CNT_DEFAULT << DMA_CFG_RD_DELAY_CNT_SHIFT) & 3077 DMA_CFG_RD_DELAY_CNT_MASK; 3078 reg |= (DMA_CFG_WR_DELAY_CNT_DEFAULT << DMA_CFG_WR_DELAY_CNT_SHIFT) & 3079 DMA_CFG_WR_DELAY_CNT_MASK; 3080 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 3081 switch (AR816X_REV(sc->alc_rev)) { 3082 case AR816X_REV_A0: 3083 case AR816X_REV_A1: 3084 reg |= DMA_CFG_RD_CHNL_SEL_1; 3085 break; 3086 case AR816X_REV_B0: 3087 /* FALLTHROUGH */ 3088 default: 3089 reg |= DMA_CFG_RD_CHNL_SEL_3; 3090 break; 3091 } 3092 } 3093 CSR_WRITE_4(sc, ALC_DMA_CFG, reg); 3094 3095 /* 3096 * Configure Tx/Rx MACs. 3097 * - Auto-padding for short frames. 3098 * - Enable CRC generation. 3099 * Actual reconfiguration of MAC for resolved speed/duplex 3100 * is followed after detection of link establishment. 3101 * AR813x/AR815x always does checksum computation regardless 3102 * of MAC_CFG_RXCSUM_ENB bit. Also the controller is known to 3103 * have bug in protocol field in Rx return structure so 3104 * these controllers can't handle fragmented frames. Disable 3105 * Rx checksum offloading until there is a newer controller 3106 * that has sane implementation. 3107 */ 3108 reg = MAC_CFG_TX_CRC_ENB | MAC_CFG_TX_AUTO_PAD | MAC_CFG_FULL_DUPLEX | 3109 ((MAC_CFG_PREAMBLE_DEFAULT << MAC_CFG_PREAMBLE_SHIFT) & 3110 MAC_CFG_PREAMBLE_MASK); 3111 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0 || 3112 sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8151 || 3113 sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8151_V2 || 3114 sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8152_B2) 3115 reg |= MAC_CFG_HASH_ALG_CRC32 | MAC_CFG_SPEED_MODE_SW; 3116 if ((sc->alc_flags & ALC_FLAG_FASTETHER) != 0) 3117 reg |= MAC_CFG_SPEED_10_100; 3118 else 3119 reg |= MAC_CFG_SPEED_1000; 3120 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 3121 3122 /* Set up the receive filter. */ 3123 alc_iff(sc); 3124 alc_rxvlan(sc); 3125 3126 /* Acknowledge all pending interrupts and clear it. */ 3127 CSR_WRITE_4(sc, ALC_INTR_MASK, ALC_INTRS); 3128 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0xFFFFFFFF); 3129 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0); 3130 3131 sc->alc_flags &= ~ALC_FLAG_LINK; 3132 /* Switch to the current media. */ 3133 mii = &sc->sc_miibus; 3134 mii_mediachg(mii); 3135 3136 callout_schedule(&sc->sc_tick_ch, hz); 3137 3138 ifp->if_flags |= IFF_RUNNING; 3139 ifp->if_flags &= ~IFF_OACTIVE; 3140 3141 return (0); 3142 } 3143 3144 static void 3145 alc_stop(struct ifnet *ifp, int disable) 3146 { 3147 struct alc_softc *sc = ifp->if_softc; 3148 struct alc_txdesc *txd; 3149 struct alc_rxdesc *rxd; 3150 uint32_t reg; 3151 int i; 3152 3153 callout_stop(&sc->sc_tick_ch); 3154 3155 /* 3156 * Mark the interface down and cancel the watchdog timer. 3157 */ 3158 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 3159 ifp->if_timer = 0; 3160 3161 sc->alc_flags &= ~ALC_FLAG_LINK; 3162 3163 alc_stats_update(sc); 3164 3165 mii_down(&sc->sc_miibus); 3166 3167 /* Disable interrupts. */ 3168 CSR_WRITE_4(sc, ALC_INTR_MASK, 0); 3169 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0xFFFFFFFF); 3170 3171 /* Disable DMA. */ 3172 reg = CSR_READ_4(sc, ALC_DMA_CFG); 3173 reg &= ~(DMA_CFG_CMB_ENB | DMA_CFG_SMB_ENB); 3174 reg |= DMA_CFG_SMB_DIS; 3175 CSR_WRITE_4(sc, ALC_DMA_CFG, reg); 3176 DELAY(1000); 3177 3178 /* Stop Rx/Tx MACs. */ 3179 alc_stop_mac(sc); 3180 3181 /* Disable interrupts which might be touched in taskq handler. */ 3182 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0xFFFFFFFF); 3183 3184 /* Disable L0s/L1s */ 3185 alc_aspm(sc, 0, IFM_UNKNOWN); 3186 3187 /* Reclaim Rx buffers that have been processed. */ 3188 if (sc->alc_cdata.alc_rxhead != NULL) 3189 m_freem(sc->alc_cdata.alc_rxhead); 3190 ALC_RXCHAIN_RESET(sc); 3191 /* 3192 * Free Tx/Rx mbufs still in the queues. 3193 */ 3194 for (i = 0; i < ALC_RX_RING_CNT; i++) { 3195 rxd = &sc->alc_cdata.alc_rxdesc[i]; 3196 if (rxd->rx_m != NULL) { 3197 bus_dmamap_sync(sc->sc_dmat, rxd->rx_dmamap, 0, 3198 rxd->rx_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 3199 bus_dmamap_unload(sc->sc_dmat, rxd->rx_dmamap); 3200 m_freem(rxd->rx_m); 3201 rxd->rx_m = NULL; 3202 } 3203 } 3204 for (i = 0; i < ALC_TX_RING_CNT; i++) { 3205 txd = &sc->alc_cdata.alc_txdesc[i]; 3206 if (txd->tx_m != NULL) { 3207 bus_dmamap_sync(sc->sc_dmat, txd->tx_dmamap, 0, 3208 txd->tx_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 3209 bus_dmamap_unload(sc->sc_dmat, txd->tx_dmamap); 3210 m_freem(txd->tx_m); 3211 txd->tx_m = NULL; 3212 } 3213 } 3214 } 3215 3216 static void 3217 alc_stop_mac(struct alc_softc *sc) 3218 { 3219 uint32_t reg; 3220 int i; 3221 3222 alc_stop_queue(sc); 3223 /* Disable Rx/Tx MAC. */ 3224 reg = CSR_READ_4(sc, ALC_MAC_CFG); 3225 if ((reg & (MAC_CFG_TX_ENB | MAC_CFG_RX_ENB)) != 0) { 3226 reg &= ~(MAC_CFG_TX_ENB | MAC_CFG_RX_ENB); 3227 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 3228 } 3229 for (i = ALC_TIMEOUT; i > 0; i--) { 3230 reg = CSR_READ_4(sc, ALC_IDLE_STATUS); 3231 if ((reg & (IDLE_STATUS_RXMAC | IDLE_STATUS_TXMAC)) == 0) 3232 break; 3233 DELAY(10); 3234 } 3235 if (i == 0) 3236 printf("%s: could not disable Rx/Tx MAC(0x%08x)!\n", 3237 device_xname(sc->sc_dev), reg); 3238 } 3239 3240 static void 3241 alc_start_queue(struct alc_softc *sc) 3242 { 3243 uint32_t qcfg[] = { 3244 0, 3245 RXQ_CFG_QUEUE0_ENB, 3246 RXQ_CFG_QUEUE0_ENB | RXQ_CFG_QUEUE1_ENB, 3247 RXQ_CFG_QUEUE0_ENB | RXQ_CFG_QUEUE1_ENB | RXQ_CFG_QUEUE2_ENB, 3248 RXQ_CFG_ENB 3249 }; 3250 uint32_t cfg; 3251 3252 /* Enable RxQ. */ 3253 cfg = CSR_READ_4(sc, ALC_RXQ_CFG); 3254 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 3255 cfg &= ~RXQ_CFG_ENB; 3256 cfg |= qcfg[1]; 3257 } else 3258 cfg |= RXQ_CFG_QUEUE0_ENB; 3259 CSR_WRITE_4(sc, ALC_RXQ_CFG, cfg); 3260 /* Enable TxQ. */ 3261 cfg = CSR_READ_4(sc, ALC_TXQ_CFG); 3262 cfg |= TXQ_CFG_ENB; 3263 CSR_WRITE_4(sc, ALC_TXQ_CFG, cfg); 3264 } 3265 3266 static void 3267 alc_stop_queue(struct alc_softc *sc) 3268 { 3269 uint32_t reg; 3270 int i; 3271 3272 /* Disable RxQ. */ 3273 reg = CSR_READ_4(sc, ALC_RXQ_CFG); 3274 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 3275 if ((reg & RXQ_CFG_ENB) != 0) { 3276 reg &= ~RXQ_CFG_ENB; 3277 CSR_WRITE_4(sc, ALC_RXQ_CFG, reg); 3278 } 3279 } else { 3280 if ((reg & RXQ_CFG_QUEUE0_ENB) != 0) { 3281 reg &= ~RXQ_CFG_QUEUE0_ENB; 3282 CSR_WRITE_4(sc, ALC_RXQ_CFG, reg); 3283 } 3284 } 3285 /* Disable TxQ. */ 3286 reg = CSR_READ_4(sc, ALC_TXQ_CFG); 3287 if ((reg & TXQ_CFG_ENB) != 0) { 3288 reg &= ~TXQ_CFG_ENB; 3289 CSR_WRITE_4(sc, ALC_TXQ_CFG, reg); 3290 } 3291 DELAY(40); 3292 for (i = ALC_TIMEOUT; i > 0; i--) { 3293 reg = CSR_READ_4(sc, ALC_IDLE_STATUS); 3294 if ((reg & (IDLE_STATUS_RXQ | IDLE_STATUS_TXQ)) == 0) 3295 break; 3296 DELAY(10); 3297 } 3298 if (i == 0) 3299 printf("%s: could not disable RxQ/TxQ (0x%08x)!\n", 3300 device_xname(sc->sc_dev), reg); 3301 } 3302 3303 static void 3304 alc_init_tx_ring(struct alc_softc *sc) 3305 { 3306 struct alc_ring_data *rd; 3307 struct alc_txdesc *txd; 3308 int i; 3309 3310 sc->alc_cdata.alc_tx_prod = 0; 3311 sc->alc_cdata.alc_tx_cons = 0; 3312 sc->alc_cdata.alc_tx_cnt = 0; 3313 3314 rd = &sc->alc_rdata; 3315 memset(rd->alc_tx_ring, 0, ALC_TX_RING_SZ); 3316 for (i = 0; i < ALC_TX_RING_CNT; i++) { 3317 txd = &sc->alc_cdata.alc_txdesc[i]; 3318 txd->tx_m = NULL; 3319 } 3320 3321 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_tx_ring_map, 0, 3322 sc->alc_cdata.alc_tx_ring_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 3323 } 3324 3325 static int 3326 alc_init_rx_ring(struct alc_softc *sc, bool init) 3327 { 3328 struct alc_ring_data *rd; 3329 struct alc_rxdesc *rxd; 3330 int i; 3331 3332 sc->alc_cdata.alc_rx_cons = ALC_RX_RING_CNT - 1; 3333 rd = &sc->alc_rdata; 3334 memset(rd->alc_rx_ring, 0, ALC_RX_RING_SZ); 3335 for (i = 0; i < ALC_RX_RING_CNT; i++) { 3336 rxd = &sc->alc_cdata.alc_rxdesc[i]; 3337 rxd->rx_m = NULL; 3338 rxd->rx_desc = &rd->alc_rx_ring[i]; 3339 if (alc_newbuf(sc, rxd, init) != 0) 3340 return (ENOBUFS); 3341 } 3342 3343 /* 3344 * Since controller does not update Rx descriptors, driver 3345 * does have to read Rx descriptors back so BUS_DMASYNC_PREWRITE 3346 * is enough to ensure coherence. 3347 */ 3348 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_rx_ring_map, 0, 3349 sc->alc_cdata.alc_rx_ring_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 3350 /* Let controller know availability of new Rx buffers. */ 3351 CSR_WRITE_4(sc, ALC_MBOX_RD0_PROD_IDX, sc->alc_cdata.alc_rx_cons); 3352 3353 return (0); 3354 } 3355 3356 static void 3357 alc_init_rr_ring(struct alc_softc *sc) 3358 { 3359 struct alc_ring_data *rd; 3360 3361 sc->alc_cdata.alc_rr_cons = 0; 3362 ALC_RXCHAIN_RESET(sc); 3363 3364 rd = &sc->alc_rdata; 3365 memset(rd->alc_rr_ring, 0, ALC_RR_RING_SZ); 3366 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_rr_ring_map, 0, 3367 sc->alc_cdata.alc_rr_ring_map->dm_mapsize, 3368 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3369 } 3370 3371 static void 3372 alc_init_cmb(struct alc_softc *sc) 3373 { 3374 struct alc_ring_data *rd; 3375 3376 rd = &sc->alc_rdata; 3377 memset(rd->alc_cmb, 0, ALC_CMB_SZ); 3378 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_cmb_map, 0, 3379 sc->alc_cdata.alc_cmb_map->dm_mapsize, 3380 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3381 } 3382 3383 static void 3384 alc_init_smb(struct alc_softc *sc) 3385 { 3386 struct alc_ring_data *rd; 3387 3388 rd = &sc->alc_rdata; 3389 memset(rd->alc_smb, 0, ALC_SMB_SZ); 3390 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_smb_map, 0, 3391 sc->alc_cdata.alc_smb_map->dm_mapsize, 3392 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3393 } 3394 3395 static void 3396 alc_rxvlan(struct alc_softc *sc) 3397 { 3398 uint32_t reg; 3399 3400 reg = CSR_READ_4(sc, ALC_MAC_CFG); 3401 if (sc->sc_ec.ec_capenable & ETHERCAP_VLAN_HWTAGGING) 3402 reg |= MAC_CFG_VLAN_TAG_STRIP; 3403 else 3404 reg &= ~MAC_CFG_VLAN_TAG_STRIP; 3405 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 3406 } 3407 3408 static void 3409 alc_iff(struct alc_softc *sc) 3410 { 3411 struct ethercom *ec = &sc->sc_ec; 3412 struct ifnet *ifp = &ec->ec_if; 3413 struct ether_multi *enm; 3414 struct ether_multistep step; 3415 uint32_t crc; 3416 uint32_t mchash[2]; 3417 uint32_t rxcfg; 3418 3419 rxcfg = CSR_READ_4(sc, ALC_MAC_CFG); 3420 rxcfg &= ~(MAC_CFG_ALLMULTI | MAC_CFG_BCAST | MAC_CFG_PROMISC); 3421 ifp->if_flags &= ~IFF_ALLMULTI; 3422 3423 /* 3424 * Always accept broadcast frames. 3425 */ 3426 rxcfg |= MAC_CFG_BCAST; 3427 3428 if (ifp->if_flags & IFF_PROMISC || ec->ec_multicnt > 0) { 3429 ifp->if_flags |= IFF_ALLMULTI; 3430 if (ifp->if_flags & IFF_PROMISC) 3431 rxcfg |= MAC_CFG_PROMISC; 3432 else 3433 rxcfg |= MAC_CFG_ALLMULTI; 3434 mchash[0] = mchash[1] = 0xFFFFFFFF; 3435 } else { 3436 /* Program new filter. */ 3437 memset(mchash, 0, sizeof(mchash)); 3438 3439 ETHER_FIRST_MULTI(step, ec, enm); 3440 while (enm != NULL) { 3441 crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 3442 mchash[crc >> 31] |= 1 << ((crc >> 26) & 0x1f); 3443 ETHER_NEXT_MULTI(step, enm); 3444 } 3445 } 3446 3447 CSR_WRITE_4(sc, ALC_MAR0, mchash[0]); 3448 CSR_WRITE_4(sc, ALC_MAR1, mchash[1]); 3449 CSR_WRITE_4(sc, ALC_MAC_CFG, rxcfg); 3450 } 3451 3452 MODULE(MODULE_CLASS_DRIVER, if_alc, "pci"); 3453 3454 #ifdef _MODULE 3455 #include "ioconf.c" 3456 #endif 3457 3458 static int 3459 if_alc_modcmd(modcmd_t cmd, void *opaque) 3460 { 3461 int error = 0; 3462 3463 switch (cmd) { 3464 case MODULE_CMD_INIT: 3465 #ifdef _MODULE 3466 error = config_init_component(cfdriver_ioconf_if_alc, 3467 cfattach_ioconf_if_alc, cfdata_ioconf_if_alc); 3468 #endif 3469 return error; 3470 case MODULE_CMD_FINI: 3471 #ifdef _MODULE 3472 error = config_fini_component(cfdriver_ioconf_if_alc, 3473 cfattach_ioconf_if_alc, cfdata_ioconf_if_alc); 3474 #endif 3475 return error; 3476 default: 3477 return ENOTTY; 3478 } 3479 } 3480
Indexes created Thu Sep 25 16:09:42 GMT 2025