if_alc.c revision 1.6
1 /* $OpenBSD: if_alc.c,v 1.1 2009/08/08 09:31:13 kevlo Exp $ */ 2 /*- 3 * Copyright (c) 2009, Pyun YongHyeon <yongari (at) FreeBSD.org> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice unmodified, this list of conditions, and the following 11 * disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 /* Driver for Atheros AR813x/AR815x PCIe Ethernet. */ 30 31 #ifdef _KERNEL_OPT 32 #include "vlan.h" 33 #endif 34 35 #include <sys/param.h> 36 #include <sys/proc.h> 37 #include <sys/endian.h> 38 #include <sys/systm.h> 39 #include <sys/types.h> 40 #include <sys/sockio.h> 41 #include <sys/mbuf.h> 42 #include <sys/queue.h> 43 #include <sys/kernel.h> 44 #include <sys/device.h> 45 #include <sys/callout.h> 46 #include <sys/socket.h> 47 #include <sys/module.h> 48 49 #include <sys/bus.h> 50 51 #include <net/if.h> 52 #include <net/if_dl.h> 53 #include <net/if_llc.h> 54 #include <net/if_media.h> 55 #include <net/if_ether.h> 56 57 #include <net/bpf.h> 58 59 #ifdef INET 60 #include <netinet/in.h> 61 #include <netinet/in_systm.h> 62 #include <netinet/in_var.h> 63 #include <netinet/ip.h> 64 #endif 65 66 #include <net/if_types.h> 67 #include <net/if_vlanvar.h> 68 69 #include <net/bpf.h> 70 71 #include <sys/rnd.h> 72 73 #include <dev/mii/mii.h> 74 #include <dev/mii/miivar.h> 75 76 #include <dev/pci/pcireg.h> 77 #include <dev/pci/pcivar.h> 78 #include <dev/pci/pcidevs.h> 79 80 #include <dev/pci/if_alcreg.h> 81 82 /* 83 * Devices supported by this driver. 84 */ 85 static struct alc_ident alc_ident_table[] = { 86 { PCI_VENDOR_ATTANSIC, PCI_PRODUCT_ATTANSIC_AR8131, 9 * 1024, 87 "Atheros AR8131 PCIe Gigabit Ethernet" }, 88 { PCI_VENDOR_ATTANSIC, PCI_PRODUCT_ATTANSIC_AR8132, 9 * 1024, 89 "Atheros AR8132 PCIe Fast Ethernet" }, 90 { PCI_VENDOR_ATTANSIC, PCI_PRODUCT_ATTANSIC_AR8151, 6 * 1024, 91 "Atheros AR8151 v1.0 PCIe Gigabit Ethernet" }, 92 { PCI_VENDOR_ATTANSIC, PCI_PRODUCT_ATTANSIC_AR8151_V2, 6 * 1024, 93 "Atheros AR8151 v2.0 PCIe Gigabit Ethernet" }, 94 { PCI_VENDOR_ATTANSIC, PCI_PRODUCT_ATTANSIC_AR8152_B, 6 * 1024, 95 "Atheros AR8152 v1.1 PCIe Fast Ethernet" }, 96 { PCI_VENDOR_ATTANSIC, PCI_PRODUCT_ATTANSIC_AR8152_B2, 6 * 1024, 97 "Atheros AR8152 v2.0 PCIe Fast Ethernet" }, 98 { 0, 0, 0, NULL }, 99 }; 100 101 static int alc_match(device_t, cfdata_t, void *); 102 static void alc_attach(device_t, device_t, void *); 103 static int alc_detach(device_t, int); 104 105 static int alc_init(struct ifnet *); 106 static void alc_start(struct ifnet *); 107 static int alc_ioctl(struct ifnet *, u_long, void *); 108 static void alc_watchdog(struct ifnet *); 109 static int alc_mediachange(struct ifnet *); 110 static void alc_mediastatus(struct ifnet *, struct ifmediareq *); 111 112 static void alc_aspm(struct alc_softc *, int); 113 static void alc_disable_l0s_l1(struct alc_softc *); 114 static int alc_dma_alloc(struct alc_softc *); 115 static void alc_dma_free(struct alc_softc *); 116 static int alc_encap(struct alc_softc *, struct mbuf **); 117 static struct alc_ident * 118 alc_find_ident(struct pci_attach_args *); 119 static void alc_get_macaddr(struct alc_softc *); 120 static void alc_init_cmb(struct alc_softc *); 121 static void alc_init_rr_ring(struct alc_softc *); 122 static int alc_init_rx_ring(struct alc_softc *); 123 static void alc_init_smb(struct alc_softc *); 124 static void alc_init_tx_ring(struct alc_softc *); 125 static int alc_intr(void *); 126 static void alc_mac_config(struct alc_softc *); 127 static int alc_miibus_readreg(device_t, int, int); 128 static void alc_miibus_statchg(struct ifnet *); 129 static void alc_miibus_writereg(device_t, int, int, int); 130 static int alc_newbuf(struct alc_softc *, struct alc_rxdesc *, int); 131 static void alc_phy_down(struct alc_softc *); 132 static void alc_phy_reset(struct alc_softc *); 133 static void alc_reset(struct alc_softc *); 134 static void alc_rxeof(struct alc_softc *, struct rx_rdesc *); 135 static int alc_rxintr(struct alc_softc *); 136 static void alc_iff(struct alc_softc *); 137 static void alc_rxvlan(struct alc_softc *); 138 static void alc_start_queue(struct alc_softc *); 139 static void alc_stats_clear(struct alc_softc *); 140 static void alc_stats_update(struct alc_softc *); 141 static void alc_stop(struct ifnet *, int); 142 static void alc_stop_mac(struct alc_softc *); 143 static void alc_stop_queue(struct alc_softc *); 144 static void alc_tick(void *); 145 static void alc_txeof(struct alc_softc *); 146 147 uint32_t alc_dma_burst[] = { 128, 256, 512, 1024, 2048, 4096, 0 }; 148 149 CFATTACH_DECL_NEW(alc, sizeof(struct alc_softc), 150 alc_match, alc_attach, alc_detach, NULL); 151 152 int alcdebug = 0; 153 #define DPRINTF(x) do { if (alcdebug) printf x; } while (0) 154 155 #define ETHER_ALIGN 2 156 #define ALC_CSUM_FEATURES (M_CSUM_TCPv4 | M_CSUM_UDPv4) 157 158 static int 159 alc_miibus_readreg(device_t dev, int phy, int reg) 160 { 161 struct alc_softc *sc = device_private(dev); 162 uint32_t v; 163 int i; 164 165 if (phy != sc->alc_phyaddr) 166 return (0); 167 168 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ | 169 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); 170 for (i = ALC_PHY_TIMEOUT; i > 0; i--) { 171 DELAY(5); 172 v = CSR_READ_4(sc, ALC_MDIO); 173 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) 174 break; 175 } 176 177 if (i == 0) { 178 printf("%s: phy read timeout: phy %d, reg %d\n", 179 device_xname(sc->sc_dev), phy, reg); 180 return (0); 181 } 182 183 return ((v & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT); 184 } 185 186 static void 187 alc_miibus_writereg(device_t dev, int phy, int reg, int val) 188 { 189 struct alc_softc *sc = device_private(dev); 190 uint32_t v; 191 int i; 192 193 if (phy != sc->alc_phyaddr) 194 return; 195 196 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE | 197 (val & MDIO_DATA_MASK) << MDIO_DATA_SHIFT | 198 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); 199 for (i = ALC_PHY_TIMEOUT; i > 0; i--) { 200 DELAY(5); 201 v = CSR_READ_4(sc, ALC_MDIO); 202 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) 203 break; 204 } 205 206 if (i == 0) 207 printf("%s: phy write timeout: phy %d, reg %d\n", 208 device_xname(sc->sc_dev), phy, reg); 209 } 210 211 static void 212 alc_miibus_statchg(struct ifnet *ifp) 213 { 214 struct alc_softc *sc = ifp->if_softc; 215 struct mii_data *mii = &sc->sc_miibus; 216 uint32_t reg; 217 218 if ((ifp->if_flags & IFF_RUNNING) == 0) 219 return; 220 221 sc->alc_flags &= ~ALC_FLAG_LINK; 222 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 223 (IFM_ACTIVE | IFM_AVALID)) { 224 switch (IFM_SUBTYPE(mii->mii_media_active)) { 225 case IFM_10_T: 226 case IFM_100_TX: 227 sc->alc_flags |= ALC_FLAG_LINK; 228 break; 229 case IFM_1000_T: 230 if ((sc->alc_flags & ALC_FLAG_FASTETHER) == 0) 231 sc->alc_flags |= ALC_FLAG_LINK; 232 break; 233 default: 234 break; 235 } 236 } 237 alc_stop_queue(sc); 238 /* Stop Rx/Tx MACs. */ 239 alc_stop_mac(sc); 240 241 /* Program MACs with resolved speed/duplex/flow-control. */ 242 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) { 243 alc_start_queue(sc); 244 alc_mac_config(sc); 245 /* Re-enable Tx/Rx MACs. */ 246 reg = CSR_READ_4(sc, ALC_MAC_CFG); 247 reg |= MAC_CFG_TX_ENB | MAC_CFG_RX_ENB; 248 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 249 alc_aspm(sc, IFM_SUBTYPE(mii->mii_media_active)); 250 } 251 } 252 253 static void 254 alc_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 255 { 256 struct alc_softc *sc = ifp->if_softc; 257 struct mii_data *mii = &sc->sc_miibus; 258 259 mii_pollstat(mii); 260 ifmr->ifm_status = mii->mii_media_status; 261 ifmr->ifm_active = mii->mii_media_active; 262 } 263 264 static int 265 alc_mediachange(struct ifnet *ifp) 266 { 267 struct alc_softc *sc = ifp->if_softc; 268 struct mii_data *mii = &sc->sc_miibus; 269 int error; 270 271 if (mii->mii_instance != 0) { 272 struct mii_softc *miisc; 273 274 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 275 mii_phy_reset(miisc); 276 } 277 error = mii_mediachg(mii); 278 279 return (error); 280 } 281 282 static struct alc_ident * 283 alc_find_ident(struct pci_attach_args *pa) 284 { 285 struct alc_ident *ident; 286 uint16_t vendor, devid; 287 288 vendor = PCI_VENDOR(pa->pa_id); 289 devid = PCI_PRODUCT(pa->pa_id); 290 for (ident = alc_ident_table; ident->name != NULL; ident++) { 291 if (vendor == ident->vendorid && devid == ident->deviceid) 292 return (ident); 293 } 294 295 return (NULL); 296 } 297 298 static int 299 alc_match(device_t dev, cfdata_t match, void *aux) 300 { 301 struct pci_attach_args *pa = aux; 302 303 return alc_find_ident(pa) != NULL; 304 } 305 306 static void 307 alc_get_macaddr(struct alc_softc *sc) 308 { 309 uint32_t ea[2], opt; 310 uint16_t val; 311 int eeprom, i; 312 313 eeprom = 0; 314 opt = CSR_READ_4(sc, ALC_OPT_CFG); 315 if ((CSR_READ_4(sc, ALC_MASTER_CFG) & MASTER_OTP_SEL) != 0 && 316 (CSR_READ_4(sc, ALC_TWSI_DEBUG) & TWSI_DEBUG_DEV_EXIST) != 0) { 317 /* 318 * EEPROM found, let TWSI reload EEPROM configuration. 319 * This will set ethernet address of controller. 320 */ 321 eeprom++; 322 switch (sc->alc_ident->deviceid) { 323 case PCI_PRODUCT_ATTANSIC_AR8131: 324 case PCI_PRODUCT_ATTANSIC_AR8132: 325 if ((opt & OPT_CFG_CLK_ENB) == 0) { 326 opt |= OPT_CFG_CLK_ENB; 327 CSR_WRITE_4(sc, ALC_OPT_CFG, opt); 328 CSR_READ_4(sc, ALC_OPT_CFG); 329 DELAY(1000); 330 } 331 break; 332 case PCI_PRODUCT_ATTANSIC_AR8151: 333 case PCI_PRODUCT_ATTANSIC_AR8151_V2: 334 case PCI_PRODUCT_ATTANSIC_AR8152_B: 335 case PCI_PRODUCT_ATTANSIC_AR8152_B2: 336 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 337 ALC_MII_DBG_ADDR, 0x00); 338 val = alc_miibus_readreg(sc->sc_dev, sc->alc_phyaddr, 339 ALC_MII_DBG_DATA); 340 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 341 ALC_MII_DBG_DATA, val & 0xFF7F); 342 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 343 ALC_MII_DBG_ADDR, 0x3B); 344 val = alc_miibus_readreg(sc->sc_dev, sc->alc_phyaddr, 345 ALC_MII_DBG_DATA); 346 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 347 ALC_MII_DBG_DATA, val | 0x0008); 348 DELAY(20); 349 break; 350 } 351 352 CSR_WRITE_4(sc, ALC_LTSSM_ID_CFG, 353 CSR_READ_4(sc, ALC_LTSSM_ID_CFG) & ~LTSSM_ID_WRO_ENB); 354 CSR_WRITE_4(sc, ALC_WOL_CFG, 0); 355 CSR_READ_4(sc, ALC_WOL_CFG); 356 357 CSR_WRITE_4(sc, ALC_TWSI_CFG, CSR_READ_4(sc, ALC_TWSI_CFG) | 358 TWSI_CFG_SW_LD_START); 359 for (i = 100; i > 0; i--) { 360 DELAY(1000); 361 if ((CSR_READ_4(sc, ALC_TWSI_CFG) & 362 TWSI_CFG_SW_LD_START) == 0) 363 break; 364 } 365 if (i == 0) 366 printf("%s: reloading EEPROM timeout!\n", 367 device_xname(sc->sc_dev)); 368 } else { 369 if (alcdebug) 370 printf("%s: EEPROM not found!\n", device_xname(sc->sc_dev)); 371 } 372 if (eeprom != 0) { 373 switch (sc->alc_ident->deviceid) { 374 case PCI_PRODUCT_ATTANSIC_AR8131: 375 case PCI_PRODUCT_ATTANSIC_AR8132: 376 if ((opt & OPT_CFG_CLK_ENB) != 0) { 377 opt &= ~OPT_CFG_CLK_ENB; 378 CSR_WRITE_4(sc, ALC_OPT_CFG, opt); 379 CSR_READ_4(sc, ALC_OPT_CFG); 380 DELAY(1000); 381 } 382 break; 383 case PCI_PRODUCT_ATTANSIC_AR8151: 384 case PCI_PRODUCT_ATTANSIC_AR8151_V2: 385 case PCI_PRODUCT_ATTANSIC_AR8152_B: 386 case PCI_PRODUCT_ATTANSIC_AR8152_B2: 387 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 388 ALC_MII_DBG_ADDR, 0x00); 389 val = alc_miibus_readreg(sc->sc_dev, sc->alc_phyaddr, 390 ALC_MII_DBG_DATA); 391 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 392 ALC_MII_DBG_DATA, val | 0x0080); 393 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 394 ALC_MII_DBG_ADDR, 0x3B); 395 val = alc_miibus_readreg(sc->sc_dev, sc->alc_phyaddr, 396 ALC_MII_DBG_DATA); 397 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 398 ALC_MII_DBG_DATA, val & 0xFFF7); 399 DELAY(20); 400 break; 401 } 402 } 403 404 ea[0] = CSR_READ_4(sc, ALC_PAR0); 405 ea[1] = CSR_READ_4(sc, ALC_PAR1); 406 sc->alc_eaddr[0] = (ea[1] >> 8) & 0xFF; 407 sc->alc_eaddr[1] = (ea[1] >> 0) & 0xFF; 408 sc->alc_eaddr[2] = (ea[0] >> 24) & 0xFF; 409 sc->alc_eaddr[3] = (ea[0] >> 16) & 0xFF; 410 sc->alc_eaddr[4] = (ea[0] >> 8) & 0xFF; 411 sc->alc_eaddr[5] = (ea[0] >> 0) & 0xFF; 412 } 413 414 static void 415 alc_disable_l0s_l1(struct alc_softc *sc) 416 { 417 uint32_t pmcfg; 418 419 /* Another magic from vendor. */ 420 pmcfg = CSR_READ_4(sc, ALC_PM_CFG); 421 pmcfg &= ~(PM_CFG_L1_ENTRY_TIMER_MASK | PM_CFG_CLK_SWH_L1 | 422 PM_CFG_ASPM_L0S_ENB | PM_CFG_ASPM_L1_ENB | PM_CFG_MAC_ASPM_CHK | 423 PM_CFG_SERDES_PD_EX_L1); 424 pmcfg |= PM_CFG_SERDES_BUDS_RX_L1_ENB | PM_CFG_SERDES_PLL_L1_ENB | 425 PM_CFG_SERDES_L1_ENB; 426 CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg); 427 } 428 429 static void 430 alc_phy_reset(struct alc_softc *sc) 431 { 432 uint16_t data; 433 434 /* Reset magic from Linux. */ 435 CSR_WRITE_2(sc, ALC_GPHY_CFG, 436 GPHY_CFG_HIB_EN | GPHY_CFG_HIB_PULSE | GPHY_CFG_SEL_ANA_RESET); 437 CSR_READ_2(sc, ALC_GPHY_CFG); 438 DELAY(10 * 1000); 439 440 CSR_WRITE_2(sc, ALC_GPHY_CFG, 441 GPHY_CFG_EXT_RESET | GPHY_CFG_HIB_EN | GPHY_CFG_HIB_PULSE | 442 GPHY_CFG_SEL_ANA_RESET); 443 CSR_READ_2(sc, ALC_GPHY_CFG); 444 DELAY(10 * 1000); 445 446 /* DSP fixup, Vendor magic. */ 447 if (sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8152_B) { 448 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 449 ALC_MII_DBG_ADDR, 0x000A); 450 data = alc_miibus_readreg(sc->sc_dev, sc->alc_phyaddr, 451 ALC_MII_DBG_DATA); 452 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 453 ALC_MII_DBG_DATA, data & 0xDFFF); 454 } 455 if (sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8151 || 456 sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8151_V2 || 457 sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8152_B || 458 sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8152_B2) { 459 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 460 ALC_MII_DBG_ADDR, 0x003B); 461 data = alc_miibus_readreg(sc->sc_dev, sc->alc_phyaddr, 462 ALC_MII_DBG_DATA); 463 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 464 ALC_MII_DBG_DATA, data & 0xFFF7); 465 DELAY(20 * 1000); 466 } 467 if (sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8151) { 468 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 469 ALC_MII_DBG_ADDR, 0x0029); 470 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 471 ALC_MII_DBG_DATA, 0x929D); 472 } 473 if (sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8131 || 474 sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8132 || 475 sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8151_V2 || 476 sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8152_B2) { 477 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 478 ALC_MII_DBG_ADDR, 0x0029); 479 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 480 ALC_MII_DBG_DATA, 0xB6DD); 481 } 482 483 /* Load DSP codes, vendor magic. */ 484 data = ANA_LOOP_SEL_10BT | ANA_EN_MASK_TB | ANA_EN_10BT_IDLE | 485 ((1 << ANA_INTERVAL_SEL_TIMER_SHIFT) & ANA_INTERVAL_SEL_TIMER_MASK); 486 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 487 ALC_MII_DBG_ADDR, MII_ANA_CFG18); 488 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 489 ALC_MII_DBG_DATA, data); 490 491 data = ((2 << ANA_SERDES_CDR_BW_SHIFT) & ANA_SERDES_CDR_BW_MASK) | 492 ANA_SERDES_EN_DEEM | ANA_SERDES_SEL_HSP | ANA_SERDES_EN_PLL | 493 ANA_SERDES_EN_LCKDT; 494 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 495 ALC_MII_DBG_ADDR, MII_ANA_CFG5); 496 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 497 ALC_MII_DBG_DATA, data); 498 499 data = ((44 << ANA_LONG_CABLE_TH_100_SHIFT) & 500 ANA_LONG_CABLE_TH_100_MASK) | 501 ((33 << ANA_SHORT_CABLE_TH_100_SHIFT) & 502 ANA_SHORT_CABLE_TH_100_SHIFT) | 503 ANA_BP_BAD_LINK_ACCUM | ANA_BP_SMALL_BW; 504 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 505 ALC_MII_DBG_ADDR, MII_ANA_CFG54); 506 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 507 ALC_MII_DBG_DATA, data); 508 509 data = ((11 << ANA_IECHO_ADJ_3_SHIFT) & ANA_IECHO_ADJ_3_MASK) | 510 ((11 << ANA_IECHO_ADJ_2_SHIFT) & ANA_IECHO_ADJ_2_MASK) | 511 ((8 << ANA_IECHO_ADJ_1_SHIFT) & ANA_IECHO_ADJ_1_MASK) | 512 ((8 << ANA_IECHO_ADJ_0_SHIFT) & ANA_IECHO_ADJ_0_MASK); 513 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 514 ALC_MII_DBG_ADDR, MII_ANA_CFG4); 515 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 516 ALC_MII_DBG_DATA, data); 517 518 data = ((7 & ANA_MANUL_SWICH_ON_SHIFT) & ANA_MANUL_SWICH_ON_MASK) | 519 ANA_RESTART_CAL | ANA_MAN_ENABLE | ANA_SEL_HSP | ANA_EN_HB | 520 ANA_OEN_125M; 521 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 522 ALC_MII_DBG_ADDR, MII_ANA_CFG0); 523 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 524 ALC_MII_DBG_DATA, data); 525 DELAY(1000); 526 } 527 528 static void 529 alc_phy_down(struct alc_softc *sc) 530 { 531 switch (sc->alc_ident->deviceid) { 532 case PCI_PRODUCT_ATTANSIC_AR8151: 533 case PCI_PRODUCT_ATTANSIC_AR8151_V2: 534 /* 535 * GPHY power down caused more problems on AR8151 v2.0. 536 * When driver is reloaded after GPHY power down, 537 * accesses to PHY/MAC registers hung the system. Only 538 * cold boot recovered from it. I'm not sure whether 539 * AR8151 v1.0 also requires this one though. I don't 540 * have AR8151 v1.0 controller in hand. 541 * The only option left is to isolate the PHY and 542 * initiates power down the PHY which in turn saves 543 * more power when driver is unloaded. 544 */ 545 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 546 MII_BMCR, BMCR_ISO | BMCR_PDOWN); 547 break; 548 default: 549 /* Force PHY down. */ 550 CSR_WRITE_2(sc, ALC_GPHY_CFG, 551 GPHY_CFG_EXT_RESET | GPHY_CFG_HIB_EN | GPHY_CFG_HIB_PULSE | 552 GPHY_CFG_SEL_ANA_RESET | GPHY_CFG_PHY_IDDQ | 553 GPHY_CFG_PWDOWN_HW); 554 DELAY(1000); 555 break; 556 } 557 } 558 559 static void 560 alc_aspm(struct alc_softc *sc, int media) 561 { 562 uint32_t pmcfg; 563 uint16_t linkcfg; 564 565 pmcfg = CSR_READ_4(sc, ALC_PM_CFG); 566 if ((sc->alc_flags & (ALC_FLAG_APS | ALC_FLAG_PCIE)) == 567 (ALC_FLAG_APS | ALC_FLAG_PCIE)) 568 linkcfg = CSR_READ_2(sc, sc->alc_expcap + 569 PCI_PCIE_LCSR); 570 else 571 linkcfg = 0; 572 pmcfg &= ~PM_CFG_SERDES_PD_EX_L1; 573 pmcfg &= ~(PM_CFG_L1_ENTRY_TIMER_MASK | PM_CFG_LCKDET_TIMER_MASK); 574 pmcfg |= PM_CFG_MAC_ASPM_CHK; 575 pmcfg |= (PM_CFG_LCKDET_TIMER_DEFAULT << PM_CFG_LCKDET_TIMER_SHIFT); 576 pmcfg &= ~(PM_CFG_ASPM_L1_ENB | PM_CFG_ASPM_L0S_ENB); 577 578 if ((sc->alc_flags & ALC_FLAG_APS) != 0) { 579 /* Disable extended sync except AR8152 B v1.0 */ 580 linkcfg &= ~0x80; 581 if (sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8152_B && 582 sc->alc_rev == ATHEROS_AR8152_B_V10) 583 linkcfg |= 0x80; 584 CSR_WRITE_2(sc, sc->alc_expcap + PCI_PCIE_LCSR, 585 linkcfg); 586 pmcfg &= ~(PM_CFG_EN_BUFS_RX_L0S | PM_CFG_SA_DLY_ENB | 587 PM_CFG_HOTRST); 588 pmcfg |= (PM_CFG_L1_ENTRY_TIMER_DEFAULT << 589 PM_CFG_L1_ENTRY_TIMER_SHIFT); 590 pmcfg &= ~PM_CFG_PM_REQ_TIMER_MASK; 591 pmcfg |= (PM_CFG_PM_REQ_TIMER_DEFAULT << 592 PM_CFG_PM_REQ_TIMER_SHIFT); 593 pmcfg |= PM_CFG_SERDES_PD_EX_L1 | PM_CFG_PCIE_RECV; 594 } 595 596 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) { 597 if ((sc->alc_flags & ALC_FLAG_L0S) != 0) 598 pmcfg |= PM_CFG_ASPM_L0S_ENB; 599 if ((sc->alc_flags & ALC_FLAG_L1S) != 0) 600 pmcfg |= PM_CFG_ASPM_L1_ENB; 601 if ((sc->alc_flags & ALC_FLAG_APS) != 0) { 602 if (sc->alc_ident->deviceid == 603 PCI_PRODUCT_ATTANSIC_AR8152_B) 604 pmcfg &= ~PM_CFG_ASPM_L0S_ENB; 605 pmcfg &= ~(PM_CFG_SERDES_L1_ENB | 606 PM_CFG_SERDES_PLL_L1_ENB | 607 PM_CFG_SERDES_BUDS_RX_L1_ENB); 608 pmcfg |= PM_CFG_CLK_SWH_L1; 609 if (media == IFM_100_TX || media == IFM_1000_T) { 610 pmcfg &= ~PM_CFG_L1_ENTRY_TIMER_MASK; 611 switch (sc->alc_ident->deviceid) { 612 case PCI_PRODUCT_ATTANSIC_AR8152_B: 613 pmcfg |= (7 << 614 PM_CFG_L1_ENTRY_TIMER_SHIFT); 615 break; 616 case PCI_PRODUCT_ATTANSIC_AR8152_B2: 617 case PCI_PRODUCT_ATTANSIC_AR8151_V2: 618 pmcfg |= (4 << 619 PM_CFG_L1_ENTRY_TIMER_SHIFT); 620 break; 621 default: 622 pmcfg |= (15 << 623 PM_CFG_L1_ENTRY_TIMER_SHIFT); 624 break; 625 } 626 } 627 } else { 628 pmcfg |= PM_CFG_SERDES_L1_ENB | 629 PM_CFG_SERDES_PLL_L1_ENB | 630 PM_CFG_SERDES_BUDS_RX_L1_ENB; 631 pmcfg &= ~(PM_CFG_CLK_SWH_L1 | 632 PM_CFG_ASPM_L1_ENB | PM_CFG_ASPM_L0S_ENB); 633 } 634 } else { 635 pmcfg &= ~(PM_CFG_SERDES_BUDS_RX_L1_ENB | PM_CFG_SERDES_L1_ENB | 636 PM_CFG_SERDES_PLL_L1_ENB); 637 pmcfg |= PM_CFG_CLK_SWH_L1; 638 if ((sc->alc_flags & ALC_FLAG_L1S) != 0) 639 pmcfg |= PM_CFG_ASPM_L1_ENB; 640 } 641 CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg); 642 } 643 644 static void 645 alc_attach(device_t parent, device_t self, void *aux) 646 { 647 648 struct alc_softc *sc = device_private(self); 649 struct pci_attach_args *pa = aux; 650 pci_chipset_tag_t pc = pa->pa_pc; 651 pci_intr_handle_t ih; 652 const char *intrstr; 653 struct ifnet *ifp; 654 pcireg_t memtype; 655 const char *aspm_state[] = { "L0s/L1", "L0s", "L1", "L0s/L1" }; 656 uint16_t burst; 657 int base, mii_flags, state, error = 0; 658 uint32_t cap, ctl, val; 659 660 sc->alc_ident = alc_find_ident(pa); 661 662 aprint_naive("\n"); 663 aprint_normal(": %s\n", sc->alc_ident->name); 664 665 sc->sc_dev = self; 666 sc->sc_dmat = pa->pa_dmat; 667 sc->sc_pct = pa->pa_pc; 668 sc->sc_pcitag = pa->pa_tag; 669 670 /* 671 * Allocate IO memory 672 */ 673 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, ALC_PCIR_BAR); 674 switch (memtype) { 675 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 676 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT_1M: 677 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 678 break; 679 default: 680 aprint_error_dev(self, "invalid base address register\n"); 681 break; 682 } 683 684 if (pci_mapreg_map(pa, ALC_PCIR_BAR, memtype, 0, &sc->sc_mem_bt, 685 &sc->sc_mem_bh, NULL, &sc->sc_mem_size)) { 686 aprint_error_dev(self, "could not map mem space\n"); 687 return; 688 } 689 690 if (pci_intr_map(pa, &ih) != 0) { 691 printf(": can't map interrupt\n"); 692 goto fail; 693 } 694 695 /* 696 * Allocate IRQ 697 */ 698 intrstr = pci_intr_string(sc->sc_pct, ih); 699 sc->sc_irq_handle = pci_intr_establish(pc, ih, IPL_NET, alc_intr, sc); 700 if (sc->sc_irq_handle == NULL) { 701 printf(": could not establish interrupt"); 702 if (intrstr != NULL) 703 printf(" at %s", intrstr); 704 printf("\n"); 705 goto fail; 706 } 707 aprint_normal_dev(self, "interrupting at %s\n", intrstr); 708 709 /* Set PHY address. */ 710 sc->alc_phyaddr = ALC_PHY_ADDR; 711 712 /* Initialize DMA parameters. */ 713 sc->alc_dma_rd_burst = 0; 714 sc->alc_dma_wr_burst = 0; 715 sc->alc_rcb = DMA_CFG_RCB_64; 716 if (pci_get_capability(pc, pa->pa_tag, PCI_CAP_PCIEXPRESS, 717 &base, NULL)) { 718 sc->alc_flags |= ALC_FLAG_PCIE; 719 sc->alc_expcap = base; 720 burst = pci_conf_read(sc->sc_pct, sc->sc_pcitag, 721 base + PCI_PCIE_DCSR) >> 16; 722 sc->alc_dma_rd_burst = (burst & 0x7000) >> 12; 723 sc->alc_dma_wr_burst = (burst & 0x00e0) >> 5; 724 if (alcdebug) { 725 printf("%s: Read request size : %u bytes.\n", 726 device_xname(sc->sc_dev), 727 alc_dma_burst[sc->alc_dma_rd_burst]); 728 printf("%s: TLP payload size : %u bytes.\n", 729 device_xname(sc->sc_dev), 730 alc_dma_burst[sc->alc_dma_wr_burst]); 731 } 732 /* Clear data link and flow-control protocol error. */ 733 val = CSR_READ_4(sc, ALC_PEX_UNC_ERR_SEV); 734 val &= ~(PEX_UNC_ERR_SEV_DLP | PEX_UNC_ERR_SEV_FCP); 735 CSR_WRITE_4(sc, ALC_PEX_UNC_ERR_SEV, val); 736 CSR_WRITE_4(sc, ALC_LTSSM_ID_CFG, 737 CSR_READ_4(sc, ALC_LTSSM_ID_CFG) & ~LTSSM_ID_WRO_ENB); 738 CSR_WRITE_4(sc, ALC_PCIE_PHYMISC, 739 CSR_READ_4(sc, ALC_PCIE_PHYMISC) | 740 PCIE_PHYMISC_FORCE_RCV_DET); 741 if (sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8152_B && 742 sc->alc_rev == ATHEROS_AR8152_B_V10) { 743 val = CSR_READ_4(sc, ALC_PCIE_PHYMISC2); 744 val &= ~(PCIE_PHYMISC2_SERDES_CDR_MASK | 745 PCIE_PHYMISC2_SERDES_TH_MASK); 746 val |= 3 << PCIE_PHYMISC2_SERDES_CDR_SHIFT; 747 val |= 3 << PCIE_PHYMISC2_SERDES_TH_SHIFT; 748 CSR_WRITE_4(sc, ALC_PCIE_PHYMISC2, val); 749 } 750 /* Disable ASPM L0S and L1. */ 751 cap = pci_conf_read(sc->sc_pct, sc->sc_pcitag, 752 base + PCI_PCIE_LCAP) >> 16; 753 if ((cap & 0x00000c00) != 0) { 754 ctl = pci_conf_read(sc->sc_pct, sc->sc_pcitag, 755 base + PCI_PCIE_LCSR) >> 16; 756 if ((ctl & 0x08) != 0) 757 sc->alc_rcb = DMA_CFG_RCB_128; 758 if (alcdebug) 759 printf("%s: RCB %u bytes\n", 760 device_xname(sc->sc_dev), 761 sc->alc_rcb == DMA_CFG_RCB_64 ? 64 : 128); 762 state = ctl & 0x03; 763 if (state & 0x01) 764 sc->alc_flags |= ALC_FLAG_L0S; 765 if (state & 0x02) 766 sc->alc_flags |= ALC_FLAG_L1S; 767 if (alcdebug) 768 printf("%s: ASPM %s %s\n", 769 device_xname(sc->sc_dev), 770 aspm_state[state], 771 state == 0 ? "disabled" : "enabled"); 772 alc_disable_l0s_l1(sc); 773 } else { 774 aprint_debug_dev(sc->sc_dev, "no ASPM support\n"); 775 } 776 } 777 778 /* Reset PHY. */ 779 alc_phy_reset(sc); 780 781 /* Reset the ethernet controller. */ 782 alc_reset(sc); 783 784 /* 785 * One odd thing is AR8132 uses the same PHY hardware(F1 786 * gigabit PHY) of AR8131. So atphy(4) of AR8132 reports 787 * the PHY supports 1000Mbps but that's not true. The PHY 788 * used in AR8132 can't establish gigabit link even if it 789 * shows the same PHY model/revision number of AR8131. 790 */ 791 switch (sc->alc_ident->deviceid) { 792 case PCI_PRODUCT_ATTANSIC_AR8152_B: 793 case PCI_PRODUCT_ATTANSIC_AR8152_B2: 794 sc->alc_flags |= ALC_FLAG_APS; 795 /* FALLTHROUGH */ 796 case PCI_PRODUCT_ATTANSIC_AR8132: 797 sc->alc_flags |= ALC_FLAG_FASTETHER; 798 break; 799 case PCI_PRODUCT_ATTANSIC_AR8151: 800 case PCI_PRODUCT_ATTANSIC_AR8151_V2: 801 sc->alc_flags |= ALC_FLAG_APS; 802 /* FALLTHROUGH */ 803 default: 804 break; 805 } 806 sc->alc_flags |= ALC_FLAG_JUMBO | ALC_FLAG_ASPM_MON; 807 808 /* 809 * It seems that AR813x/AR815x has silicon bug for SMB. In 810 * addition, Atheros said that enabling SMB wouldn't improve 811 * performance. However I think it's bad to access lots of 812 * registers to extract MAC statistics. 813 */ 814 sc->alc_flags |= ALC_FLAG_SMB_BUG; 815 /* 816 * Don't use Tx CMB. It is known to have silicon bug. 817 */ 818 sc->alc_flags |= ALC_FLAG_CMB_BUG; 819 sc->alc_rev = PCI_REVISION(pa->pa_class); 820 sc->alc_chip_rev = CSR_READ_4(sc, ALC_MASTER_CFG) >> 821 MASTER_CHIP_REV_SHIFT; 822 if (alcdebug) { 823 printf("%s: PCI device revision : 0x%04x\n", 824 device_xname(sc->sc_dev), sc->alc_rev); 825 printf("%s: Chip id/revision : 0x%04x\n", 826 device_xname(sc->sc_dev), sc->alc_chip_rev); 827 printf("%s: %u Tx FIFO, %u Rx FIFO\n", device_xname(sc->sc_dev), 828 CSR_READ_4(sc, ALC_SRAM_TX_FIFO_LEN) * 8, 829 CSR_READ_4(sc, ALC_SRAM_RX_FIFO_LEN) * 8); 830 } 831 832 error = alc_dma_alloc(sc); 833 if (error) 834 goto fail; 835 836 callout_init(&sc->sc_tick_ch, 0); 837 callout_setfunc(&sc->sc_tick_ch, alc_tick, sc); 838 839 /* Load station address. */ 840 alc_get_macaddr(sc); 841 842 aprint_normal_dev(self, "Ethernet address %s\n", 843 ether_sprintf(sc->alc_eaddr)); 844 845 ifp = &sc->sc_ec.ec_if; 846 ifp->if_softc = sc; 847 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 848 ifp->if_init = alc_init; 849 ifp->if_ioctl = alc_ioctl; 850 ifp->if_start = alc_start; 851 ifp->if_stop = alc_stop; 852 ifp->if_watchdog = alc_watchdog; 853 ifp->if_baudrate = IF_Gbps(1); 854 IFQ_SET_MAXLEN(&ifp->if_snd, ALC_TX_RING_CNT - 1); 855 IFQ_SET_READY(&ifp->if_snd); 856 strlcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 857 858 sc->sc_ec.ec_capabilities = ETHERCAP_VLAN_MTU; 859 860 #ifdef ALC_CHECKSUM 861 ifp->if_capabilities |= IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 862 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 863 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_TCPv4_Rx; 864 #endif 865 866 #if NVLAN > 0 867 sc->sc_ec.ec_capabilities |= ETHERCAP_VLAN_HWTAGGING; 868 #endif 869 870 /* Set up MII bus. */ 871 sc->sc_miibus.mii_ifp = ifp; 872 sc->sc_miibus.mii_readreg = alc_miibus_readreg; 873 sc->sc_miibus.mii_writereg = alc_miibus_writereg; 874 sc->sc_miibus.mii_statchg = alc_miibus_statchg; 875 876 sc->sc_ec.ec_mii = &sc->sc_miibus; 877 ifmedia_init(&sc->sc_miibus.mii_media, 0, alc_mediachange, 878 alc_mediastatus); 879 mii_flags = 0; 880 if ((sc->alc_flags & ALC_FLAG_JUMBO) != 0) 881 mii_flags |= MIIF_DOPAUSE; 882 mii_attach(self, &sc->sc_miibus, 0xffffffff, MII_PHY_ANY, 883 MII_OFFSET_ANY, mii_flags); 884 885 if (LIST_FIRST(&sc->sc_miibus.mii_phys) == NULL) { 886 printf("%s: no PHY found!\n", device_xname(sc->sc_dev)); 887 ifmedia_add(&sc->sc_miibus.mii_media, IFM_ETHER | IFM_MANUAL, 888 0, NULL); 889 ifmedia_set(&sc->sc_miibus.mii_media, IFM_ETHER | IFM_MANUAL); 890 } else 891 ifmedia_set(&sc->sc_miibus.mii_media, IFM_ETHER | IFM_AUTO); 892 893 if_attach(ifp); 894 ether_ifattach(ifp, sc->alc_eaddr); 895 896 if (!pmf_device_register(self, NULL, NULL)) 897 aprint_error_dev(self, "couldn't establish power handler\n"); 898 else 899 pmf_class_network_register(self, ifp); 900 901 return; 902 fail: 903 alc_dma_free(sc); 904 if (sc->sc_irq_handle != NULL) { 905 pci_intr_disestablish(sc->sc_pct, sc->sc_irq_handle); 906 sc->sc_irq_handle = NULL; 907 } 908 if (sc->sc_mem_size) { 909 bus_space_unmap(sc->sc_mem_bt, sc->sc_mem_bh, sc->sc_mem_size); 910 sc->sc_mem_size = 0; 911 } 912 } 913 914 static int 915 alc_detach(device_t self, int flags) 916 { 917 struct alc_softc *sc = device_private(self); 918 struct ifnet *ifp = &sc->sc_ec.ec_if; 919 int s; 920 921 s = splnet(); 922 alc_stop(ifp, 0); 923 splx(s); 924 925 mii_detach(&sc->sc_miibus, MII_PHY_ANY, MII_OFFSET_ANY); 926 927 /* Delete all remaining media. */ 928 ifmedia_delete_instance(&sc->sc_miibus.mii_media, IFM_INST_ANY); 929 930 ether_ifdetach(ifp); 931 if_detach(ifp); 932 alc_dma_free(sc); 933 934 alc_phy_down(sc); 935 if (sc->sc_irq_handle != NULL) { 936 pci_intr_disestablish(sc->sc_pct, sc->sc_irq_handle); 937 sc->sc_irq_handle = NULL; 938 } 939 if (sc->sc_mem_size) { 940 bus_space_unmap(sc->sc_mem_bt, sc->sc_mem_bh, sc->sc_mem_size); 941 sc->sc_mem_size = 0; 942 } 943 944 return (0); 945 } 946 947 static int 948 alc_dma_alloc(struct alc_softc *sc) 949 { 950 struct alc_txdesc *txd; 951 struct alc_rxdesc *rxd; 952 int nsegs, error, i; 953 954 /* 955 * Create DMA stuffs for TX ring 956 */ 957 error = bus_dmamap_create(sc->sc_dmat, ALC_TX_RING_SZ, 1, 958 ALC_TX_RING_SZ, 0, BUS_DMA_NOWAIT, &sc->alc_cdata.alc_tx_ring_map); 959 if (error) { 960 sc->alc_cdata.alc_tx_ring_map = NULL; 961 return (ENOBUFS); 962 } 963 964 /* Allocate DMA'able memory for TX ring */ 965 error = bus_dmamem_alloc(sc->sc_dmat, ALC_TX_RING_SZ, 966 ETHER_ALIGN, 0, &sc->alc_rdata.alc_tx_ring_seg, 1, 967 &nsegs, BUS_DMA_NOWAIT); 968 if (error) { 969 printf("%s: could not allocate DMA'able memory for Tx ring.\n", 970 device_xname(sc->sc_dev)); 971 return error; 972 } 973 974 error = bus_dmamem_map(sc->sc_dmat, &sc->alc_rdata.alc_tx_ring_seg, 975 nsegs, ALC_TX_RING_SZ, (void **)&sc->alc_rdata.alc_tx_ring, 976 BUS_DMA_NOWAIT); 977 if (error) 978 return (ENOBUFS); 979 980 /* Load the DMA map for Tx ring. */ 981 error = bus_dmamap_load(sc->sc_dmat, sc->alc_cdata.alc_tx_ring_map, 982 sc->alc_rdata.alc_tx_ring, ALC_TX_RING_SZ, NULL, BUS_DMA_WAITOK); 983 if (error) { 984 printf("%s: could not load DMA'able memory for Tx ring.\n", 985 device_xname(sc->sc_dev)); 986 bus_dmamem_free(sc->sc_dmat, 987 &sc->alc_rdata.alc_tx_ring_seg, 1); 988 return error; 989 } 990 991 sc->alc_rdata.alc_tx_ring_paddr = 992 sc->alc_cdata.alc_tx_ring_map->dm_segs[0].ds_addr; 993 994 /* 995 * Create DMA stuffs for RX ring 996 */ 997 error = bus_dmamap_create(sc->sc_dmat, ALC_RX_RING_SZ, 1, 998 ALC_RX_RING_SZ, 0, BUS_DMA_NOWAIT, &sc->alc_cdata.alc_rx_ring_map); 999 if (error) 1000 return (ENOBUFS); 1001 1002 /* Allocate DMA'able memory for RX ring */ 1003 error = bus_dmamem_alloc(sc->sc_dmat, ALC_RX_RING_SZ, 1004 ETHER_ALIGN, 0, &sc->alc_rdata.alc_rx_ring_seg, 1, 1005 &nsegs, BUS_DMA_NOWAIT); 1006 if (error) { 1007 printf("%s: could not allocate DMA'able memory for Rx ring.\n", 1008 device_xname(sc->sc_dev)); 1009 return error; 1010 } 1011 1012 error = bus_dmamem_map(sc->sc_dmat, &sc->alc_rdata.alc_rx_ring_seg, 1013 nsegs, ALC_RX_RING_SZ, (void **)&sc->alc_rdata.alc_rx_ring, 1014 BUS_DMA_NOWAIT); 1015 if (error) 1016 return (ENOBUFS); 1017 1018 /* Load the DMA map for Rx ring. */ 1019 error = bus_dmamap_load(sc->sc_dmat, sc->alc_cdata.alc_rx_ring_map, 1020 sc->alc_rdata.alc_rx_ring, ALC_RX_RING_SZ, NULL, BUS_DMA_WAITOK); 1021 if (error) { 1022 printf("%s: could not load DMA'able memory for Rx ring.\n", 1023 device_xname(sc->sc_dev)); 1024 bus_dmamem_free(sc->sc_dmat, 1025 &sc->alc_rdata.alc_rx_ring_seg, 1); 1026 return error; 1027 } 1028 1029 sc->alc_rdata.alc_rx_ring_paddr = 1030 sc->alc_cdata.alc_rx_ring_map->dm_segs[0].ds_addr; 1031 1032 /* 1033 * Create DMA stuffs for RX return ring 1034 */ 1035 error = bus_dmamap_create(sc->sc_dmat, ALC_RR_RING_SZ, 1, 1036 ALC_RR_RING_SZ, 0, BUS_DMA_NOWAIT, &sc->alc_cdata.alc_rr_ring_map); 1037 if (error) 1038 return (ENOBUFS); 1039 1040 /* Allocate DMA'able memory for RX return ring */ 1041 error = bus_dmamem_alloc(sc->sc_dmat, ALC_RR_RING_SZ, 1042 ETHER_ALIGN, 0, &sc->alc_rdata.alc_rr_ring_seg, 1, 1043 &nsegs, BUS_DMA_NOWAIT); 1044 if (error) { 1045 printf("%s: could not allocate DMA'able memory for Rx " 1046 "return ring.\n", device_xname(sc->sc_dev)); 1047 return error; 1048 } 1049 1050 error = bus_dmamem_map(sc->sc_dmat, &sc->alc_rdata.alc_rr_ring_seg, 1051 nsegs, ALC_RR_RING_SZ, (void **)&sc->alc_rdata.alc_rr_ring, 1052 BUS_DMA_NOWAIT); 1053 if (error) 1054 return (ENOBUFS); 1055 1056 /* Load the DMA map for Rx return ring. */ 1057 error = bus_dmamap_load(sc->sc_dmat, sc->alc_cdata.alc_rr_ring_map, 1058 sc->alc_rdata.alc_rr_ring, ALC_RR_RING_SZ, NULL, BUS_DMA_WAITOK); 1059 if (error) { 1060 printf("%s: could not load DMA'able memory for Rx return ring." 1061 "\n", device_xname(sc->sc_dev)); 1062 bus_dmamem_free(sc->sc_dmat, 1063 &sc->alc_rdata.alc_rr_ring_seg, 1); 1064 return error; 1065 } 1066 1067 sc->alc_rdata.alc_rr_ring_paddr = 1068 sc->alc_cdata.alc_rr_ring_map->dm_segs[0].ds_addr; 1069 1070 /* 1071 * Create DMA stuffs for CMB block 1072 */ 1073 error = bus_dmamap_create(sc->sc_dmat, ALC_CMB_SZ, 1, 1074 ALC_CMB_SZ, 0, BUS_DMA_NOWAIT, 1075 &sc->alc_cdata.alc_cmb_map); 1076 if (error) 1077 return (ENOBUFS); 1078 1079 /* Allocate DMA'able memory for CMB block */ 1080 error = bus_dmamem_alloc(sc->sc_dmat, ALC_CMB_SZ, 1081 ETHER_ALIGN, 0, &sc->alc_rdata.alc_cmb_seg, 1, 1082 &nsegs, BUS_DMA_NOWAIT); 1083 if (error) { 1084 printf("%s: could not allocate DMA'able memory for " 1085 "CMB block\n", device_xname(sc->sc_dev)); 1086 return error; 1087 } 1088 1089 error = bus_dmamem_map(sc->sc_dmat, &sc->alc_rdata.alc_cmb_seg, 1090 nsegs, ALC_CMB_SZ, (void **)&sc->alc_rdata.alc_cmb, 1091 BUS_DMA_NOWAIT); 1092 if (error) 1093 return (ENOBUFS); 1094 1095 /* Load the DMA map for CMB block. */ 1096 error = bus_dmamap_load(sc->sc_dmat, sc->alc_cdata.alc_cmb_map, 1097 sc->alc_rdata.alc_cmb, ALC_CMB_SZ, NULL, 1098 BUS_DMA_WAITOK); 1099 if (error) { 1100 printf("%s: could not load DMA'able memory for CMB block\n", 1101 device_xname(sc->sc_dev)); 1102 bus_dmamem_free(sc->sc_dmat, 1103 &sc->alc_rdata.alc_cmb_seg, 1); 1104 return error; 1105 } 1106 1107 sc->alc_rdata.alc_cmb_paddr = 1108 sc->alc_cdata.alc_cmb_map->dm_segs[0].ds_addr; 1109 1110 /* 1111 * Create DMA stuffs for SMB block 1112 */ 1113 error = bus_dmamap_create(sc->sc_dmat, ALC_SMB_SZ, 1, 1114 ALC_SMB_SZ, 0, BUS_DMA_NOWAIT, 1115 &sc->alc_cdata.alc_smb_map); 1116 if (error) 1117 return (ENOBUFS); 1118 1119 /* Allocate DMA'able memory for SMB block */ 1120 error = bus_dmamem_alloc(sc->sc_dmat, ALC_SMB_SZ, 1121 ETHER_ALIGN, 0, &sc->alc_rdata.alc_smb_seg, 1, 1122 &nsegs, BUS_DMA_NOWAIT); 1123 if (error) { 1124 printf("%s: could not allocate DMA'able memory for " 1125 "SMB block\n", device_xname(sc->sc_dev)); 1126 return error; 1127 } 1128 1129 error = bus_dmamem_map(sc->sc_dmat, &sc->alc_rdata.alc_smb_seg, 1130 nsegs, ALC_SMB_SZ, (void **)&sc->alc_rdata.alc_smb, 1131 BUS_DMA_NOWAIT); 1132 if (error) 1133 return (ENOBUFS); 1134 1135 /* Load the DMA map for SMB block */ 1136 error = bus_dmamap_load(sc->sc_dmat, sc->alc_cdata.alc_smb_map, 1137 sc->alc_rdata.alc_smb, ALC_SMB_SZ, NULL, 1138 BUS_DMA_WAITOK); 1139 if (error) { 1140 printf("%s: could not load DMA'able memory for SMB block\n", 1141 device_xname(sc->sc_dev)); 1142 bus_dmamem_free(sc->sc_dmat, 1143 &sc->alc_rdata.alc_smb_seg, 1); 1144 return error; 1145 } 1146 1147 sc->alc_rdata.alc_smb_paddr = 1148 sc->alc_cdata.alc_smb_map->dm_segs[0].ds_addr; 1149 1150 1151 /* Create DMA maps for Tx buffers. */ 1152 for (i = 0; i < ALC_TX_RING_CNT; i++) { 1153 txd = &sc->alc_cdata.alc_txdesc[i]; 1154 txd->tx_m = NULL; 1155 txd->tx_dmamap = NULL; 1156 error = bus_dmamap_create(sc->sc_dmat, ALC_TSO_MAXSIZE, 1157 ALC_MAXTXSEGS, ALC_TSO_MAXSEGSIZE, 0, BUS_DMA_NOWAIT, 1158 &txd->tx_dmamap); 1159 if (error) { 1160 printf("%s: could not create Tx dmamap.\n", 1161 device_xname(sc->sc_dev)); 1162 return error; 1163 } 1164 } 1165 1166 /* Create DMA maps for Rx buffers. */ 1167 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES, 0, 1168 BUS_DMA_NOWAIT, &sc->alc_cdata.alc_rx_sparemap); 1169 if (error) { 1170 printf("%s: could not create spare Rx dmamap.\n", 1171 device_xname(sc->sc_dev)); 1172 return error; 1173 } 1174 1175 for (i = 0; i < ALC_RX_RING_CNT; i++) { 1176 rxd = &sc->alc_cdata.alc_rxdesc[i]; 1177 rxd->rx_m = NULL; 1178 rxd->rx_dmamap = NULL; 1179 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 1180 MCLBYTES, 0, BUS_DMA_NOWAIT, &rxd->rx_dmamap); 1181 if (error) { 1182 printf("%s: could not create Rx dmamap.\n", 1183 device_xname(sc->sc_dev)); 1184 return error; 1185 } 1186 } 1187 1188 return (0); 1189 } 1190 1191 1192 static void 1193 alc_dma_free(struct alc_softc *sc) 1194 { 1195 struct alc_txdesc *txd; 1196 struct alc_rxdesc *rxd; 1197 int i; 1198 1199 /* Tx buffers */ 1200 for (i = 0; i < ALC_TX_RING_CNT; i++) { 1201 txd = &sc->alc_cdata.alc_txdesc[i]; 1202 if (txd->tx_dmamap != NULL) { 1203 bus_dmamap_destroy(sc->sc_dmat, txd->tx_dmamap); 1204 txd->tx_dmamap = NULL; 1205 } 1206 } 1207 /* Rx buffers */ 1208 for (i = 0; i < ALC_RX_RING_CNT; i++) { 1209 rxd = &sc->alc_cdata.alc_rxdesc[i]; 1210 if (rxd->rx_dmamap != NULL) { 1211 bus_dmamap_destroy(sc->sc_dmat, rxd->rx_dmamap); 1212 rxd->rx_dmamap = NULL; 1213 } 1214 } 1215 if (sc->alc_cdata.alc_rx_sparemap != NULL) { 1216 bus_dmamap_destroy(sc->sc_dmat, sc->alc_cdata.alc_rx_sparemap); 1217 sc->alc_cdata.alc_rx_sparemap = NULL; 1218 } 1219 1220 /* Tx ring. */ 1221 if (sc->alc_cdata.alc_tx_ring_map != NULL) 1222 bus_dmamap_unload(sc->sc_dmat, sc->alc_cdata.alc_tx_ring_map); 1223 if (sc->alc_cdata.alc_tx_ring_map != NULL && 1224 sc->alc_rdata.alc_tx_ring != NULL) 1225 bus_dmamem_free(sc->sc_dmat, 1226 &sc->alc_rdata.alc_tx_ring_seg, 1); 1227 sc->alc_rdata.alc_tx_ring = NULL; 1228 sc->alc_cdata.alc_tx_ring_map = NULL; 1229 1230 /* Rx ring. */ 1231 if (sc->alc_cdata.alc_rx_ring_map != NULL) 1232 bus_dmamap_unload(sc->sc_dmat, sc->alc_cdata.alc_rx_ring_map); 1233 if (sc->alc_cdata.alc_rx_ring_map != NULL && 1234 sc->alc_rdata.alc_rx_ring != NULL) 1235 bus_dmamem_free(sc->sc_dmat, 1236 &sc->alc_rdata.alc_rx_ring_seg, 1); 1237 sc->alc_rdata.alc_rx_ring = NULL; 1238 sc->alc_cdata.alc_rx_ring_map = NULL; 1239 1240 /* Rx return ring. */ 1241 if (sc->alc_cdata.alc_rr_ring_map != NULL) 1242 bus_dmamap_unload(sc->sc_dmat, sc->alc_cdata.alc_rr_ring_map); 1243 if (sc->alc_cdata.alc_rr_ring_map != NULL && 1244 sc->alc_rdata.alc_rr_ring != NULL) 1245 bus_dmamem_free(sc->sc_dmat, 1246 &sc->alc_rdata.alc_rr_ring_seg, 1); 1247 sc->alc_rdata.alc_rr_ring = NULL; 1248 sc->alc_cdata.alc_rr_ring_map = NULL; 1249 1250 /* CMB block */ 1251 if (sc->alc_cdata.alc_cmb_map != NULL) 1252 bus_dmamap_unload(sc->sc_dmat, sc->alc_cdata.alc_cmb_map); 1253 if (sc->alc_cdata.alc_cmb_map != NULL && 1254 sc->alc_rdata.alc_cmb != NULL) 1255 bus_dmamem_free(sc->sc_dmat, 1256 &sc->alc_rdata.alc_cmb_seg, 1); 1257 sc->alc_rdata.alc_cmb = NULL; 1258 sc->alc_cdata.alc_cmb_map = NULL; 1259 1260 /* SMB block */ 1261 if (sc->alc_cdata.alc_smb_map != NULL) 1262 bus_dmamap_unload(sc->sc_dmat, sc->alc_cdata.alc_smb_map); 1263 if (sc->alc_cdata.alc_smb_map != NULL && 1264 sc->alc_rdata.alc_smb != NULL) 1265 bus_dmamem_free(sc->sc_dmat, 1266 &sc->alc_rdata.alc_smb_seg, 1); 1267 sc->alc_rdata.alc_smb = NULL; 1268 sc->alc_cdata.alc_smb_map = NULL; 1269 } 1270 1271 static int 1272 alc_encap(struct alc_softc *sc, struct mbuf **m_head) 1273 { 1274 struct alc_txdesc *txd, *txd_last; 1275 struct tx_desc *desc; 1276 struct mbuf *m; 1277 bus_dmamap_t map; 1278 uint32_t cflags, poff, vtag; 1279 int error, idx, nsegs, prod; 1280 #if NVLAN > 0 1281 struct m_tag *mtag; 1282 #endif 1283 1284 m = *m_head; 1285 cflags = vtag = 0; 1286 poff = 0; 1287 1288 prod = sc->alc_cdata.alc_tx_prod; 1289 txd = &sc->alc_cdata.alc_txdesc[prod]; 1290 txd_last = txd; 1291 map = txd->tx_dmamap; 1292 1293 error = bus_dmamap_load_mbuf(sc->sc_dmat, map, *m_head, BUS_DMA_NOWAIT); 1294 1295 if (error == EFBIG) { 1296 error = 0; 1297 1298 *m_head = m_pullup(*m_head, MHLEN); 1299 if (*m_head == NULL) { 1300 printf("%s: can't defrag TX mbuf\n", 1301 device_xname(sc->sc_dev)); 1302 return ENOBUFS; 1303 } 1304 1305 error = bus_dmamap_load_mbuf(sc->sc_dmat, map, *m_head, 1306 BUS_DMA_NOWAIT); 1307 1308 if (error != 0) { 1309 printf("%s: could not load defragged TX mbuf\n", 1310 device_xname(sc->sc_dev)); 1311 m_freem(*m_head); 1312 *m_head = NULL; 1313 return error; 1314 } 1315 } else if (error) { 1316 printf("%s: could not load TX mbuf\n", device_xname(sc->sc_dev)); 1317 return (error); 1318 } 1319 1320 nsegs = map->dm_nsegs; 1321 1322 if (nsegs == 0) { 1323 m_freem(*m_head); 1324 *m_head = NULL; 1325 return (EIO); 1326 } 1327 1328 /* Check descriptor overrun. */ 1329 if (sc->alc_cdata.alc_tx_cnt + nsegs >= ALC_TX_RING_CNT - 3) { 1330 bus_dmamap_unload(sc->sc_dmat, map); 1331 return (ENOBUFS); 1332 } 1333 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 1334 BUS_DMASYNC_PREWRITE); 1335 1336 m = *m_head; 1337 desc = NULL; 1338 idx = 0; 1339 #if NVLAN > 0 1340 /* Configure VLAN hardware tag insertion. */ 1341 if ((mtag = VLAN_OUTPUT_TAG(&sc->sc_ec, m))) { 1342 vtag = htons(VLAN_TAG_VALUE(mtag)); 1343 vtag = (vtag << TD_VLAN_SHIFT) & TD_VLAN_MASK; 1344 cflags |= TD_INS_VLAN_TAG; 1345 } 1346 #endif 1347 /* Configure Tx checksum offload. */ 1348 if ((m->m_pkthdr.csum_flags & ALC_CSUM_FEATURES) != 0) { 1349 cflags |= TD_CUSTOM_CSUM; 1350 /* Set checksum start offset. */ 1351 cflags |= ((poff >> 1) << TD_PLOAD_OFFSET_SHIFT) & 1352 TD_PLOAD_OFFSET_MASK; 1353 } 1354 for (; idx < nsegs; idx++) { 1355 desc = &sc->alc_rdata.alc_tx_ring[prod]; 1356 desc->len = 1357 htole32(TX_BYTES(map->dm_segs[idx].ds_len) | vtag); 1358 desc->flags = htole32(cflags); 1359 desc->addr = htole64(map->dm_segs[idx].ds_addr); 1360 sc->alc_cdata.alc_tx_cnt++; 1361 ALC_DESC_INC(prod, ALC_TX_RING_CNT); 1362 } 1363 /* Update producer index. */ 1364 sc->alc_cdata.alc_tx_prod = prod; 1365 1366 /* Finally set EOP on the last descriptor. */ 1367 prod = (prod + ALC_TX_RING_CNT - 1) % ALC_TX_RING_CNT; 1368 desc = &sc->alc_rdata.alc_tx_ring[prod]; 1369 desc->flags |= htole32(TD_EOP); 1370 1371 /* Swap dmamap of the first and the last. */ 1372 txd = &sc->alc_cdata.alc_txdesc[prod]; 1373 map = txd_last->tx_dmamap; 1374 txd_last->tx_dmamap = txd->tx_dmamap; 1375 txd->tx_dmamap = map; 1376 txd->tx_m = m; 1377 1378 return (0); 1379 } 1380 1381 static void 1382 alc_start(struct ifnet *ifp) 1383 { 1384 struct alc_softc *sc = ifp->if_softc; 1385 struct mbuf *m_head; 1386 int enq; 1387 1388 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 1389 return; 1390 1391 /* Reclaim transmitted frames. */ 1392 if (sc->alc_cdata.alc_tx_cnt >= ALC_TX_DESC_HIWAT) 1393 alc_txeof(sc); 1394 1395 enq = 0; 1396 for (;;) { 1397 IFQ_DEQUEUE(&ifp->if_snd, m_head); 1398 if (m_head == NULL) 1399 break; 1400 1401 /* 1402 * Pack the data into the transmit ring. If we 1403 * don't have room, set the OACTIVE flag and wait 1404 * for the NIC to drain the ring. 1405 */ 1406 if (alc_encap(sc, &m_head)) { 1407 if (m_head == NULL) 1408 break; 1409 ifp->if_flags |= IFF_OACTIVE; 1410 break; 1411 } 1412 enq = 1; 1413 1414 /* 1415 * If there's a BPF listener, bounce a copy of this frame 1416 * to him. 1417 */ 1418 bpf_mtap(ifp, m_head); 1419 } 1420 1421 if (enq) { 1422 /* Sync descriptors. */ 1423 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_tx_ring_map, 0, 1424 sc->alc_cdata.alc_tx_ring_map->dm_mapsize, 1425 BUS_DMASYNC_PREWRITE); 1426 /* Kick. Assume we're using normal Tx priority queue. */ 1427 CSR_WRITE_4(sc, ALC_MBOX_TD_PROD_IDX, 1428 (sc->alc_cdata.alc_tx_prod << 1429 MBOX_TD_PROD_LO_IDX_SHIFT) & 1430 MBOX_TD_PROD_LO_IDX_MASK); 1431 /* Set a timeout in case the chip goes out to lunch. */ 1432 ifp->if_timer = ALC_TX_TIMEOUT; 1433 } 1434 } 1435 1436 static void 1437 alc_watchdog(struct ifnet *ifp) 1438 { 1439 struct alc_softc *sc = ifp->if_softc; 1440 1441 if ((sc->alc_flags & ALC_FLAG_LINK) == 0) { 1442 printf("%s: watchdog timeout (missed link)\n", 1443 device_xname(sc->sc_dev)); 1444 ifp->if_oerrors++; 1445 alc_init(ifp); 1446 return; 1447 } 1448 1449 printf("%s: watchdog timeout\n", device_xname(sc->sc_dev)); 1450 ifp->if_oerrors++; 1451 alc_init(ifp); 1452 1453 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 1454 alc_start(ifp); 1455 } 1456 1457 static int 1458 alc_ioctl(struct ifnet *ifp, u_long cmd, void *data) 1459 { 1460 struct alc_softc *sc = ifp->if_softc; 1461 int s, error = 0; 1462 1463 s = splnet(); 1464 1465 error = ether_ioctl(ifp, cmd, data); 1466 if (error == ENETRESET) { 1467 if (ifp->if_flags & IFF_RUNNING) 1468 alc_iff(sc); 1469 error = 0; 1470 } 1471 1472 splx(s); 1473 return (error); 1474 } 1475 1476 static void 1477 alc_mac_config(struct alc_softc *sc) 1478 { 1479 struct mii_data *mii; 1480 uint32_t reg; 1481 1482 mii = &sc->sc_miibus; 1483 reg = CSR_READ_4(sc, ALC_MAC_CFG); 1484 reg &= ~(MAC_CFG_FULL_DUPLEX | MAC_CFG_TX_FC | MAC_CFG_RX_FC | 1485 MAC_CFG_SPEED_MASK); 1486 if (sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8151 || 1487 sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8151_V2 || 1488 sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8152_B2) 1489 reg |= MAC_CFG_HASH_ALG_CRC32 | MAC_CFG_SPEED_MODE_SW; 1490 /* Reprogram MAC with resolved speed/duplex. */ 1491 switch (IFM_SUBTYPE(mii->mii_media_active)) { 1492 case IFM_10_T: 1493 case IFM_100_TX: 1494 reg |= MAC_CFG_SPEED_10_100; 1495 break; 1496 case IFM_1000_T: 1497 reg |= MAC_CFG_SPEED_1000; 1498 break; 1499 } 1500 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 1501 reg |= MAC_CFG_FULL_DUPLEX; 1502 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0) 1503 reg |= MAC_CFG_TX_FC; 1504 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0) 1505 reg |= MAC_CFG_RX_FC; 1506 } 1507 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 1508 } 1509 1510 static void 1511 alc_stats_clear(struct alc_softc *sc) 1512 { 1513 struct smb sb, *smb; 1514 uint32_t *reg; 1515 int i; 1516 1517 if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0) { 1518 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_smb_map, 0, 1519 sc->alc_cdata.alc_smb_map->dm_mapsize, 1520 BUS_DMASYNC_POSTREAD); 1521 smb = sc->alc_rdata.alc_smb; 1522 /* Update done, clear. */ 1523 smb->updated = 0; 1524 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_smb_map, 0, 1525 sc->alc_cdata.alc_smb_map->dm_mapsize, 1526 BUS_DMASYNC_PREWRITE); 1527 } else { 1528 for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered; 1529 reg++) { 1530 CSR_READ_4(sc, ALC_RX_MIB_BASE + i); 1531 i += sizeof(uint32_t); 1532 } 1533 /* Read Tx statistics. */ 1534 for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes; 1535 reg++) { 1536 CSR_READ_4(sc, ALC_TX_MIB_BASE + i); 1537 i += sizeof(uint32_t); 1538 } 1539 } 1540 } 1541 1542 static void 1543 alc_stats_update(struct alc_softc *sc) 1544 { 1545 struct ifnet *ifp = &sc->sc_ec.ec_if; 1546 struct alc_hw_stats *stat; 1547 struct smb sb, *smb; 1548 uint32_t *reg; 1549 int i; 1550 1551 stat = &sc->alc_stats; 1552 if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0) { 1553 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_smb_map, 0, 1554 sc->alc_cdata.alc_smb_map->dm_mapsize, 1555 BUS_DMASYNC_POSTREAD); 1556 smb = sc->alc_rdata.alc_smb; 1557 if (smb->updated == 0) 1558 return; 1559 } else { 1560 smb = &sb; 1561 /* Read Rx statistics. */ 1562 for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered; 1563 reg++) { 1564 *reg = CSR_READ_4(sc, ALC_RX_MIB_BASE + i); 1565 i += sizeof(uint32_t); 1566 } 1567 /* Read Tx statistics. */ 1568 for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes; 1569 reg++) { 1570 *reg = CSR_READ_4(sc, ALC_TX_MIB_BASE + i); 1571 i += sizeof(uint32_t); 1572 } 1573 } 1574 1575 /* Rx stats. */ 1576 stat->rx_frames += smb->rx_frames; 1577 stat->rx_bcast_frames += smb->rx_bcast_frames; 1578 stat->rx_mcast_frames += smb->rx_mcast_frames; 1579 stat->rx_pause_frames += smb->rx_pause_frames; 1580 stat->rx_control_frames += smb->rx_control_frames; 1581 stat->rx_crcerrs += smb->rx_crcerrs; 1582 stat->rx_lenerrs += smb->rx_lenerrs; 1583 stat->rx_bytes += smb->rx_bytes; 1584 stat->rx_runts += smb->rx_runts; 1585 stat->rx_fragments += smb->rx_fragments; 1586 stat->rx_pkts_64 += smb->rx_pkts_64; 1587 stat->rx_pkts_65_127 += smb->rx_pkts_65_127; 1588 stat->rx_pkts_128_255 += smb->rx_pkts_128_255; 1589 stat->rx_pkts_256_511 += smb->rx_pkts_256_511; 1590 stat->rx_pkts_512_1023 += smb->rx_pkts_512_1023; 1591 stat->rx_pkts_1024_1518 += smb->rx_pkts_1024_1518; 1592 stat->rx_pkts_1519_max += smb->rx_pkts_1519_max; 1593 stat->rx_pkts_truncated += smb->rx_pkts_truncated; 1594 stat->rx_fifo_oflows += smb->rx_fifo_oflows; 1595 stat->rx_rrs_errs += smb->rx_rrs_errs; 1596 stat->rx_alignerrs += smb->rx_alignerrs; 1597 stat->rx_bcast_bytes += smb->rx_bcast_bytes; 1598 stat->rx_mcast_bytes += smb->rx_mcast_bytes; 1599 stat->rx_pkts_filtered += smb->rx_pkts_filtered; 1600 1601 /* Tx stats. */ 1602 stat->tx_frames += smb->tx_frames; 1603 stat->tx_bcast_frames += smb->tx_bcast_frames; 1604 stat->tx_mcast_frames += smb->tx_mcast_frames; 1605 stat->tx_pause_frames += smb->tx_pause_frames; 1606 stat->tx_excess_defer += smb->tx_excess_defer; 1607 stat->tx_control_frames += smb->tx_control_frames; 1608 stat->tx_deferred += smb->tx_deferred; 1609 stat->tx_bytes += smb->tx_bytes; 1610 stat->tx_pkts_64 += smb->tx_pkts_64; 1611 stat->tx_pkts_65_127 += smb->tx_pkts_65_127; 1612 stat->tx_pkts_128_255 += smb->tx_pkts_128_255; 1613 stat->tx_pkts_256_511 += smb->tx_pkts_256_511; 1614 stat->tx_pkts_512_1023 += smb->tx_pkts_512_1023; 1615 stat->tx_pkts_1024_1518 += smb->tx_pkts_1024_1518; 1616 stat->tx_pkts_1519_max += smb->tx_pkts_1519_max; 1617 stat->tx_single_colls += smb->tx_single_colls; 1618 stat->tx_multi_colls += smb->tx_multi_colls; 1619 stat->tx_late_colls += smb->tx_late_colls; 1620 stat->tx_excess_colls += smb->tx_excess_colls; 1621 stat->tx_abort += smb->tx_abort; 1622 stat->tx_underrun += smb->tx_underrun; 1623 stat->tx_desc_underrun += smb->tx_desc_underrun; 1624 stat->tx_lenerrs += smb->tx_lenerrs; 1625 stat->tx_pkts_truncated += smb->tx_pkts_truncated; 1626 stat->tx_bcast_bytes += smb->tx_bcast_bytes; 1627 stat->tx_mcast_bytes += smb->tx_mcast_bytes; 1628 1629 /* Update counters in ifnet. */ 1630 ifp->if_opackets += smb->tx_frames; 1631 1632 ifp->if_collisions += smb->tx_single_colls + 1633 smb->tx_multi_colls * 2 + smb->tx_late_colls + 1634 smb->tx_abort * HDPX_CFG_RETRY_DEFAULT; 1635 1636 /* 1637 * XXX 1638 * tx_pkts_truncated counter looks suspicious. It constantly 1639 * increments with no sign of Tx errors. This may indicate 1640 * the counter name is not correct one so I've removed the 1641 * counter in output errors. 1642 */ 1643 ifp->if_oerrors += smb->tx_abort + smb->tx_late_colls + 1644 smb->tx_underrun; 1645 1646 ifp->if_ipackets += smb->rx_frames; 1647 1648 ifp->if_ierrors += smb->rx_crcerrs + smb->rx_lenerrs + 1649 smb->rx_runts + smb->rx_pkts_truncated + 1650 smb->rx_fifo_oflows + smb->rx_rrs_errs + 1651 smb->rx_alignerrs; 1652 1653 if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0) { 1654 /* Update done, clear. */ 1655 smb->updated = 0; 1656 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_smb_map, 0, 1657 sc->alc_cdata.alc_smb_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 1658 } 1659 } 1660 1661 static int 1662 alc_intr(void *arg) 1663 { 1664 struct alc_softc *sc = arg; 1665 struct ifnet *ifp = &sc->sc_ec.ec_if; 1666 uint32_t status; 1667 1668 status = CSR_READ_4(sc, ALC_INTR_STATUS); 1669 if ((status & ALC_INTRS) == 0) 1670 return (0); 1671 1672 /* Acknowledge and disable interrupts. */ 1673 CSR_WRITE_4(sc, ALC_INTR_STATUS, status | INTR_DIS_INT); 1674 1675 if (ifp->if_flags & IFF_RUNNING) { 1676 if (status & INTR_RX_PKT) { 1677 int error; 1678 1679 error = alc_rxintr(sc); 1680 if (error) { 1681 alc_init(ifp); 1682 return (0); 1683 } 1684 } 1685 1686 if (status & (INTR_DMA_RD_TO_RST | INTR_DMA_WR_TO_RST | 1687 INTR_TXQ_TO_RST)) { 1688 if (status & INTR_DMA_RD_TO_RST) 1689 printf("%s: DMA read error! -- resetting\n", 1690 device_xname(sc->sc_dev)); 1691 if (status & INTR_DMA_WR_TO_RST) 1692 printf("%s: DMA write error! -- resetting\n", 1693 device_xname(sc->sc_dev)); 1694 if (status & INTR_TXQ_TO_RST) 1695 printf("%s: TxQ reset! -- resetting\n", 1696 device_xname(sc->sc_dev)); 1697 alc_init(ifp); 1698 return (0); 1699 } 1700 1701 alc_txeof(sc); 1702 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 1703 alc_start(ifp); 1704 } 1705 1706 /* Re-enable interrupts. */ 1707 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0x7FFFFFFF); 1708 return (1); 1709 } 1710 1711 static void 1712 alc_txeof(struct alc_softc *sc) 1713 { 1714 struct ifnet *ifp = &sc->sc_ec.ec_if; 1715 struct alc_txdesc *txd; 1716 uint32_t cons, prod; 1717 int prog; 1718 1719 if (sc->alc_cdata.alc_tx_cnt == 0) 1720 return; 1721 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_tx_ring_map, 0, 1722 sc->alc_cdata.alc_tx_ring_map->dm_mapsize, 1723 BUS_DMASYNC_POSTREAD); 1724 if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0) { 1725 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_cmb_map, 0, 1726 sc->alc_cdata.alc_cmb_map->dm_mapsize, 1727 BUS_DMASYNC_POSTREAD); 1728 prod = sc->alc_rdata.alc_cmb->cons; 1729 } else 1730 prod = CSR_READ_4(sc, ALC_MBOX_TD_CONS_IDX); 1731 /* Assume we're using normal Tx priority queue. */ 1732 prod = (prod & MBOX_TD_CONS_LO_IDX_MASK) >> 1733 MBOX_TD_CONS_LO_IDX_SHIFT; 1734 cons = sc->alc_cdata.alc_tx_cons; 1735 /* 1736 * Go through our Tx list and free mbufs for those 1737 * frames which have been transmitted. 1738 */ 1739 for (prog = 0; cons != prod; prog++, 1740 ALC_DESC_INC(cons, ALC_TX_RING_CNT)) { 1741 if (sc->alc_cdata.alc_tx_cnt <= 0) 1742 break; 1743 prog++; 1744 ifp->if_flags &= ~IFF_OACTIVE; 1745 sc->alc_cdata.alc_tx_cnt--; 1746 txd = &sc->alc_cdata.alc_txdesc[cons]; 1747 if (txd->tx_m != NULL) { 1748 /* Reclaim transmitted mbufs. */ 1749 bus_dmamap_unload(sc->sc_dmat, txd->tx_dmamap); 1750 m_freem(txd->tx_m); 1751 txd->tx_m = NULL; 1752 } 1753 } 1754 1755 if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0) 1756 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_cmb_map, 0, 1757 sc->alc_cdata.alc_cmb_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 1758 sc->alc_cdata.alc_tx_cons = cons; 1759 /* 1760 * Unarm watchdog timer only when there is no pending 1761 * frames in Tx queue. 1762 */ 1763 if (sc->alc_cdata.alc_tx_cnt == 0) 1764 ifp->if_timer = 0; 1765 } 1766 1767 static int 1768 alc_newbuf(struct alc_softc *sc, struct alc_rxdesc *rxd, int init) 1769 { 1770 struct mbuf *m; 1771 bus_dmamap_t map; 1772 int error; 1773 1774 MGETHDR(m, init ? M_WAITOK : M_DONTWAIT, MT_DATA); 1775 if (m == NULL) 1776 return (ENOBUFS); 1777 MCLGET(m, init ? M_WAITOK : M_DONTWAIT); 1778 if (!(m->m_flags & M_EXT)) { 1779 m_freem(m); 1780 return (ENOBUFS); 1781 } 1782 1783 m->m_len = m->m_pkthdr.len = RX_BUF_SIZE_MAX; 1784 1785 error = bus_dmamap_load_mbuf(sc->sc_dmat, 1786 sc->alc_cdata.alc_rx_sparemap, m, BUS_DMA_NOWAIT); 1787 1788 if (error != 0) { 1789 if (!error) { 1790 bus_dmamap_unload(sc->sc_dmat, 1791 sc->alc_cdata.alc_rx_sparemap); 1792 error = EFBIG; 1793 printf("%s: too many segments?!\n", 1794 device_xname(sc->sc_dev)); 1795 } 1796 m_freem(m); 1797 1798 if (init) 1799 printf("%s: can't load RX mbuf\n", device_xname(sc->sc_dev)); 1800 1801 return (error); 1802 } 1803 1804 if (rxd->rx_m != NULL) { 1805 bus_dmamap_sync(sc->sc_dmat, rxd->rx_dmamap, 0, 1806 rxd->rx_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1807 bus_dmamap_unload(sc->sc_dmat, rxd->rx_dmamap); 1808 } 1809 map = rxd->rx_dmamap; 1810 rxd->rx_dmamap = sc->alc_cdata.alc_rx_sparemap; 1811 sc->alc_cdata.alc_rx_sparemap = map; 1812 rxd->rx_m = m; 1813 rxd->rx_desc->addr = htole64(rxd->rx_dmamap->dm_segs[0].ds_addr); 1814 return (0); 1815 } 1816 1817 static int 1818 alc_rxintr(struct alc_softc *sc) 1819 { 1820 struct ifnet *ifp = &sc->sc_ec.ec_if; 1821 struct rx_rdesc *rrd; 1822 uint32_t nsegs, status; 1823 int rr_cons, prog; 1824 1825 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_rr_ring_map, 0, 1826 sc->alc_cdata.alc_rr_ring_map->dm_mapsize, BUS_DMASYNC_POSTREAD); 1827 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_rx_ring_map, 0, 1828 sc->alc_cdata.alc_rx_ring_map->dm_mapsize, BUS_DMASYNC_POSTREAD); 1829 rr_cons = sc->alc_cdata.alc_rr_cons; 1830 for (prog = 0; (ifp->if_flags & IFF_RUNNING) != 0;) { 1831 rrd = &sc->alc_rdata.alc_rr_ring[rr_cons]; 1832 status = le32toh(rrd->status); 1833 if ((status & RRD_VALID) == 0) 1834 break; 1835 nsegs = RRD_RD_CNT(le32toh(rrd->rdinfo)); 1836 if (nsegs == 0) { 1837 /* This should not happen! */ 1838 if (alcdebug) 1839 printf("%s: unexpected segment count -- " 1840 "resetting\n", device_xname(sc->sc_dev)); 1841 return (EIO); 1842 } 1843 alc_rxeof(sc, rrd); 1844 /* Clear Rx return status. */ 1845 rrd->status = 0; 1846 ALC_DESC_INC(rr_cons, ALC_RR_RING_CNT); 1847 sc->alc_cdata.alc_rx_cons += nsegs; 1848 sc->alc_cdata.alc_rx_cons %= ALC_RR_RING_CNT; 1849 prog += nsegs; 1850 } 1851 1852 if (prog > 0) { 1853 /* Update the consumer index. */ 1854 sc->alc_cdata.alc_rr_cons = rr_cons; 1855 /* Sync Rx return descriptors. */ 1856 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_rr_ring_map, 0, 1857 sc->alc_cdata.alc_rr_ring_map->dm_mapsize, 1858 BUS_DMASYNC_PREWRITE); 1859 /* 1860 * Sync updated Rx descriptors such that controller see 1861 * modified buffer addresses. 1862 */ 1863 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_rx_ring_map, 0, 1864 sc->alc_cdata.alc_rx_ring_map->dm_mapsize, 1865 BUS_DMASYNC_PREWRITE); 1866 /* 1867 * Let controller know availability of new Rx buffers. 1868 * Since alc(4) use RXQ_CFG_RD_BURST_DEFAULT descriptors 1869 * it may be possible to update ALC_MBOX_RD0_PROD_IDX 1870 * only when Rx buffer pre-fetching is required. In 1871 * addition we already set ALC_RX_RD_FREE_THRESH to 1872 * RX_RD_FREE_THRESH_LO_DEFAULT descriptors. However 1873 * it still seems that pre-fetching needs more 1874 * experimentation. 1875 */ 1876 CSR_WRITE_4(sc, ALC_MBOX_RD0_PROD_IDX, 1877 sc->alc_cdata.alc_rx_cons); 1878 } 1879 1880 return (0); 1881 } 1882 1883 /* Receive a frame. */ 1884 static void 1885 alc_rxeof(struct alc_softc *sc, struct rx_rdesc *rrd) 1886 { 1887 struct ifnet *ifp = &sc->sc_ec.ec_if; 1888 struct alc_rxdesc *rxd; 1889 struct mbuf *mp, *m; 1890 uint32_t rdinfo, status; 1891 int count, nsegs, rx_cons; 1892 1893 status = le32toh(rrd->status); 1894 rdinfo = le32toh(rrd->rdinfo); 1895 rx_cons = RRD_RD_IDX(rdinfo); 1896 nsegs = RRD_RD_CNT(rdinfo); 1897 1898 sc->alc_cdata.alc_rxlen = RRD_BYTES(status); 1899 if (status & (RRD_ERR_SUM | RRD_ERR_LENGTH)) { 1900 /* 1901 * We want to pass the following frames to upper 1902 * layer regardless of error status of Rx return 1903 * ring. 1904 * 1905 * o IP/TCP/UDP checksum is bad. 1906 * o frame length and protocol specific length 1907 * does not match. 1908 * 1909 * Force network stack compute checksum for 1910 * errored frames. 1911 */ 1912 status |= RRD_TCP_UDPCSUM_NOK | RRD_IPCSUM_NOK; 1913 if ((status & (RRD_ERR_CRC | RRD_ERR_ALIGN | 1914 RRD_ERR_TRUNC | RRD_ERR_RUNT)) != 0) 1915 return; 1916 } 1917 1918 for (count = 0; count < nsegs; count++, 1919 ALC_DESC_INC(rx_cons, ALC_RX_RING_CNT)) { 1920 rxd = &sc->alc_cdata.alc_rxdesc[rx_cons]; 1921 mp = rxd->rx_m; 1922 /* Add a new receive buffer to the ring. */ 1923 if (alc_newbuf(sc, rxd, 0) != 0) { 1924 ifp->if_iqdrops++; 1925 /* Reuse Rx buffers. */ 1926 if (sc->alc_cdata.alc_rxhead != NULL) 1927 m_freem(sc->alc_cdata.alc_rxhead); 1928 break; 1929 } 1930 1931 /* 1932 * Assume we've received a full sized frame. 1933 * Actual size is fixed when we encounter the end of 1934 * multi-segmented frame. 1935 */ 1936 mp->m_len = sc->alc_buf_size; 1937 1938 /* Chain received mbufs. */ 1939 if (sc->alc_cdata.alc_rxhead == NULL) { 1940 sc->alc_cdata.alc_rxhead = mp; 1941 sc->alc_cdata.alc_rxtail = mp; 1942 } else { 1943 mp->m_flags &= ~M_PKTHDR; 1944 sc->alc_cdata.alc_rxprev_tail = 1945 sc->alc_cdata.alc_rxtail; 1946 sc->alc_cdata.alc_rxtail->m_next = mp; 1947 sc->alc_cdata.alc_rxtail = mp; 1948 } 1949 1950 if (count == nsegs - 1) { 1951 /* Last desc. for this frame. */ 1952 m = sc->alc_cdata.alc_rxhead; 1953 m->m_flags |= M_PKTHDR; 1954 /* 1955 * It seems that L1C/L2C controller has no way 1956 * to tell hardware to strip CRC bytes. 1957 */ 1958 m->m_pkthdr.len = 1959 sc->alc_cdata.alc_rxlen - ETHER_CRC_LEN; 1960 if (nsegs > 1) { 1961 /* Set last mbuf size. */ 1962 mp->m_len = sc->alc_cdata.alc_rxlen - 1963 (nsegs - 1) * sc->alc_buf_size; 1964 /* Remove the CRC bytes in chained mbufs. */ 1965 if (mp->m_len <= ETHER_CRC_LEN) { 1966 sc->alc_cdata.alc_rxtail = 1967 sc->alc_cdata.alc_rxprev_tail; 1968 sc->alc_cdata.alc_rxtail->m_len -= 1969 (ETHER_CRC_LEN - mp->m_len); 1970 sc->alc_cdata.alc_rxtail->m_next = NULL; 1971 m_freem(mp); 1972 } else { 1973 mp->m_len -= ETHER_CRC_LEN; 1974 } 1975 } else 1976 m->m_len = m->m_pkthdr.len; 1977 m->m_pkthdr.rcvif = ifp; 1978 #if NVLAN > 0 1979 /* 1980 * Due to hardware bugs, Rx checksum offloading 1981 * was intentionally disabled. 1982 */ 1983 if (status & RRD_VLAN_TAG) { 1984 u_int32_t vtag = RRD_VLAN(le32toh(rrd->vtag)); 1985 VLAN_INPUT_TAG(ifp, m, ntohs(vtag), ); 1986 } 1987 #endif 1988 1989 bpf_mtap(ifp, m); 1990 1991 { 1992 /* Pass it on. */ 1993 ether_input(ifp, m); 1994 } 1995 } 1996 } 1997 /* Reset mbuf chains. */ 1998 ALC_RXCHAIN_RESET(sc); 1999 } 2000 2001 static void 2002 alc_tick(void *xsc) 2003 { 2004 struct alc_softc *sc = xsc; 2005 struct mii_data *mii = &sc->sc_miibus; 2006 int s; 2007 2008 s = splnet(); 2009 mii_tick(mii); 2010 alc_stats_update(sc); 2011 splx(s); 2012 2013 callout_schedule(&sc->sc_tick_ch, hz); 2014 } 2015 2016 static void 2017 alc_reset(struct alc_softc *sc) 2018 { 2019 uint32_t reg; 2020 int i; 2021 2022 reg = CSR_READ_4(sc, ALC_MASTER_CFG) & 0xFFFF; 2023 reg |= MASTER_OOB_DIS_OFF | MASTER_RESET; 2024 CSR_WRITE_4(sc, ALC_MASTER_CFG, reg); 2025 for (i = ALC_RESET_TIMEOUT; i > 0; i--) { 2026 DELAY(10); 2027 if ((CSR_READ_4(sc, ALC_MASTER_CFG) & MASTER_RESET) == 0) 2028 break; 2029 } 2030 if (i == 0) 2031 printf("%s: master reset timeout!\n", device_xname(sc->sc_dev)); 2032 2033 for (i = ALC_RESET_TIMEOUT; i > 0; i--) { 2034 if ((reg = CSR_READ_4(sc, ALC_IDLE_STATUS)) == 0) 2035 break; 2036 DELAY(10); 2037 } 2038 2039 if (i == 0) 2040 printf("%s: reset timeout(0x%08x)!\n", device_xname(sc->sc_dev), 2041 reg); 2042 } 2043 2044 static int 2045 alc_init(struct ifnet *ifp) 2046 { 2047 struct alc_softc *sc = ifp->if_softc; 2048 struct mii_data *mii; 2049 uint8_t eaddr[ETHER_ADDR_LEN]; 2050 bus_addr_t paddr; 2051 uint32_t reg, rxf_hi, rxf_lo; 2052 int error; 2053 2054 /* 2055 * Cancel any pending I/O. 2056 */ 2057 alc_stop(ifp, 0); 2058 /* 2059 * Reset the chip to a known state. 2060 */ 2061 alc_reset(sc); 2062 2063 /* Initialize Rx descriptors. */ 2064 error = alc_init_rx_ring(sc); 2065 if (error != 0) { 2066 printf("%s: no memory for Rx buffers.\n", device_xname(sc->sc_dev)); 2067 alc_stop(ifp, 0); 2068 return (error); 2069 } 2070 alc_init_rr_ring(sc); 2071 alc_init_tx_ring(sc); 2072 alc_init_cmb(sc); 2073 alc_init_smb(sc); 2074 2075 /* Enable all clocks. */ 2076 CSR_WRITE_4(sc, ALC_CLK_GATING_CFG, 0); 2077 2078 /* Reprogram the station address. */ 2079 memcpy(eaddr, CLLADDR(ifp->if_sadl), sizeof(eaddr)); 2080 CSR_WRITE_4(sc, ALC_PAR0, 2081 eaddr[2] << 24 | eaddr[3] << 16 | eaddr[4] << 8 | eaddr[5]); 2082 CSR_WRITE_4(sc, ALC_PAR1, eaddr[0] << 8 | eaddr[1]); 2083 /* 2084 * Clear WOL status and disable all WOL feature as WOL 2085 * would interfere Rx operation under normal environments. 2086 */ 2087 CSR_READ_4(sc, ALC_WOL_CFG); 2088 CSR_WRITE_4(sc, ALC_WOL_CFG, 0); 2089 /* Set Tx descriptor base addresses. */ 2090 paddr = sc->alc_rdata.alc_tx_ring_paddr; 2091 CSR_WRITE_4(sc, ALC_TX_BASE_ADDR_HI, ALC_ADDR_HI(paddr)); 2092 CSR_WRITE_4(sc, ALC_TDL_HEAD_ADDR_LO, ALC_ADDR_LO(paddr)); 2093 /* We don't use high priority ring. */ 2094 CSR_WRITE_4(sc, ALC_TDH_HEAD_ADDR_LO, 0); 2095 /* Set Tx descriptor counter. */ 2096 CSR_WRITE_4(sc, ALC_TD_RING_CNT, 2097 (ALC_TX_RING_CNT << TD_RING_CNT_SHIFT) & TD_RING_CNT_MASK); 2098 /* Set Rx descriptor base addresses. */ 2099 paddr = sc->alc_rdata.alc_rx_ring_paddr; 2100 CSR_WRITE_4(sc, ALC_RX_BASE_ADDR_HI, ALC_ADDR_HI(paddr)); 2101 CSR_WRITE_4(sc, ALC_RD0_HEAD_ADDR_LO, ALC_ADDR_LO(paddr)); 2102 /* We use one Rx ring. */ 2103 CSR_WRITE_4(sc, ALC_RD1_HEAD_ADDR_LO, 0); 2104 CSR_WRITE_4(sc, ALC_RD2_HEAD_ADDR_LO, 0); 2105 CSR_WRITE_4(sc, ALC_RD3_HEAD_ADDR_LO, 0); 2106 /* Set Rx descriptor counter. */ 2107 CSR_WRITE_4(sc, ALC_RD_RING_CNT, 2108 (ALC_RX_RING_CNT << RD_RING_CNT_SHIFT) & RD_RING_CNT_MASK); 2109 2110 /* 2111 * Let hardware split jumbo frames into alc_max_buf_sized chunks. 2112 * if it do not fit the buffer size. Rx return descriptor holds 2113 * a counter that indicates how many fragments were made by the 2114 * hardware. The buffer size should be multiple of 8 bytes. 2115 * Since hardware has limit on the size of buffer size, always 2116 * use the maximum value. 2117 * For strict-alignment architectures make sure to reduce buffer 2118 * size by 8 bytes to make room for alignment fixup. 2119 */ 2120 sc->alc_buf_size = RX_BUF_SIZE_MAX; 2121 CSR_WRITE_4(sc, ALC_RX_BUF_SIZE, sc->alc_buf_size); 2122 2123 paddr = sc->alc_rdata.alc_rr_ring_paddr; 2124 /* Set Rx return descriptor base addresses. */ 2125 CSR_WRITE_4(sc, ALC_RRD0_HEAD_ADDR_LO, ALC_ADDR_LO(paddr)); 2126 /* We use one Rx return ring. */ 2127 CSR_WRITE_4(sc, ALC_RRD1_HEAD_ADDR_LO, 0); 2128 CSR_WRITE_4(sc, ALC_RRD2_HEAD_ADDR_LO, 0); 2129 CSR_WRITE_4(sc, ALC_RRD3_HEAD_ADDR_LO, 0); 2130 /* Set Rx return descriptor counter. */ 2131 CSR_WRITE_4(sc, ALC_RRD_RING_CNT, 2132 (ALC_RR_RING_CNT << RRD_RING_CNT_SHIFT) & RRD_RING_CNT_MASK); 2133 paddr = sc->alc_rdata.alc_cmb_paddr; 2134 CSR_WRITE_4(sc, ALC_CMB_BASE_ADDR_LO, ALC_ADDR_LO(paddr)); 2135 paddr = sc->alc_rdata.alc_smb_paddr; 2136 CSR_WRITE_4(sc, ALC_SMB_BASE_ADDR_HI, ALC_ADDR_HI(paddr)); 2137 CSR_WRITE_4(sc, ALC_SMB_BASE_ADDR_LO, ALC_ADDR_LO(paddr)); 2138 2139 if (sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8152_B) { 2140 /* Reconfigure SRAM - Vendor magic. */ 2141 CSR_WRITE_4(sc, ALC_SRAM_RX_FIFO_LEN, 0x000002A0); 2142 CSR_WRITE_4(sc, ALC_SRAM_TX_FIFO_LEN, 0x00000100); 2143 CSR_WRITE_4(sc, ALC_SRAM_RX_FIFO_ADDR, 0x029F0000); 2144 CSR_WRITE_4(sc, ALC_SRAM_RD0_ADDR, 0x02BF02A0); 2145 CSR_WRITE_4(sc, ALC_SRAM_TX_FIFO_ADDR, 0x03BF02C0); 2146 CSR_WRITE_4(sc, ALC_SRAM_TD_ADDR, 0x03DF03C0); 2147 CSR_WRITE_4(sc, ALC_TXF_WATER_MARK, 0x00000000); 2148 CSR_WRITE_4(sc, ALC_RD_DMA_CFG, 0x00000000); 2149 } 2150 2151 /* Tell hardware that we're ready to load DMA blocks. */ 2152 CSR_WRITE_4(sc, ALC_DMA_BLOCK, DMA_BLOCK_LOAD); 2153 2154 /* Configure interrupt moderation timer. */ 2155 sc->alc_int_rx_mod = ALC_IM_RX_TIMER_DEFAULT; 2156 sc->alc_int_tx_mod = ALC_IM_TX_TIMER_DEFAULT; 2157 reg = ALC_USECS(sc->alc_int_rx_mod) << IM_TIMER_RX_SHIFT; 2158 reg |= ALC_USECS(sc->alc_int_tx_mod) << IM_TIMER_TX_SHIFT; 2159 CSR_WRITE_4(sc, ALC_IM_TIMER, reg); 2160 /* 2161 * We don't want to automatic interrupt clear as task queue 2162 * for the interrupt should know interrupt status. 2163 */ 2164 reg = MASTER_SA_TIMER_ENB; 2165 if (ALC_USECS(sc->alc_int_rx_mod) != 0) 2166 reg |= MASTER_IM_RX_TIMER_ENB; 2167 if (ALC_USECS(sc->alc_int_tx_mod) != 0) 2168 reg |= MASTER_IM_TX_TIMER_ENB; 2169 CSR_WRITE_4(sc, ALC_MASTER_CFG, reg); 2170 /* 2171 * Disable interrupt re-trigger timer. We don't want automatic 2172 * re-triggering of un-ACKed interrupts. 2173 */ 2174 CSR_WRITE_4(sc, ALC_INTR_RETRIG_TIMER, ALC_USECS(0)); 2175 /* Configure CMB. */ 2176 CSR_WRITE_4(sc, ALC_CMB_TD_THRESH, 4); 2177 if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0) 2178 CSR_WRITE_4(sc, ALC_CMB_TX_TIMER, ALC_USECS(5000)); 2179 else 2180 CSR_WRITE_4(sc, ALC_CMB_TX_TIMER, ALC_USECS(0)); 2181 /* 2182 * Hardware can be configured to issue SMB interrupt based 2183 * on programmed interval. Since there is a callout that is 2184 * invoked for every hz in driver we use that instead of 2185 * relying on periodic SMB interrupt. 2186 */ 2187 CSR_WRITE_4(sc, ALC_SMB_STAT_TIMER, ALC_USECS(0)); 2188 /* Clear MAC statistics. */ 2189 alc_stats_clear(sc); 2190 2191 /* 2192 * Always use maximum frame size that controller can support. 2193 * Otherwise received frames that has larger frame length 2194 * than alc(4) MTU would be silently dropped in hardware. This 2195 * would make path-MTU discovery hard as sender wouldn't get 2196 * any responses from receiver. alc(4) supports 2197 * multi-fragmented frames on Rx path so it has no issue on 2198 * assembling fragmented frames. Using maximum frame size also 2199 * removes the need to reinitialize hardware when interface 2200 * MTU configuration was changed. 2201 * 2202 * Be conservative in what you do, be liberal in what you 2203 * accept from others - RFC 793. 2204 */ 2205 CSR_WRITE_4(sc, ALC_FRAME_SIZE, sc->alc_ident->max_framelen); 2206 2207 /* Disable header split(?) */ 2208 CSR_WRITE_4(sc, ALC_HDS_CFG, 0); 2209 2210 /* Configure IPG/IFG parameters. */ 2211 CSR_WRITE_4(sc, ALC_IPG_IFG_CFG, 2212 ((IPG_IFG_IPGT_DEFAULT << IPG_IFG_IPGT_SHIFT) & IPG_IFG_IPGT_MASK) | 2213 ((IPG_IFG_MIFG_DEFAULT << IPG_IFG_MIFG_SHIFT) & IPG_IFG_MIFG_MASK) | 2214 ((IPG_IFG_IPG1_DEFAULT << IPG_IFG_IPG1_SHIFT) & IPG_IFG_IPG1_MASK) | 2215 ((IPG_IFG_IPG2_DEFAULT << IPG_IFG_IPG2_SHIFT) & IPG_IFG_IPG2_MASK)); 2216 /* Set parameters for half-duplex media. */ 2217 CSR_WRITE_4(sc, ALC_HDPX_CFG, 2218 ((HDPX_CFG_LCOL_DEFAULT << HDPX_CFG_LCOL_SHIFT) & 2219 HDPX_CFG_LCOL_MASK) | 2220 ((HDPX_CFG_RETRY_DEFAULT << HDPX_CFG_RETRY_SHIFT) & 2221 HDPX_CFG_RETRY_MASK) | HDPX_CFG_EXC_DEF_EN | 2222 ((HDPX_CFG_ABEBT_DEFAULT << HDPX_CFG_ABEBT_SHIFT) & 2223 HDPX_CFG_ABEBT_MASK) | 2224 ((HDPX_CFG_JAMIPG_DEFAULT << HDPX_CFG_JAMIPG_SHIFT) & 2225 HDPX_CFG_JAMIPG_MASK)); 2226 /* 2227 * Set TSO/checksum offload threshold. For frames that is 2228 * larger than this threshold, hardware wouldn't do 2229 * TSO/checksum offloading. 2230 */ 2231 CSR_WRITE_4(sc, ALC_TSO_OFFLOAD_THRESH, 2232 (sc->alc_ident->max_framelen >> TSO_OFFLOAD_THRESH_UNIT_SHIFT) & 2233 TSO_OFFLOAD_THRESH_MASK); 2234 /* Configure TxQ. */ 2235 reg = (alc_dma_burst[sc->alc_dma_rd_burst] << 2236 TXQ_CFG_TX_FIFO_BURST_SHIFT) & TXQ_CFG_TX_FIFO_BURST_MASK; 2237 if (sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8152_B || 2238 sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8152_B2) 2239 reg >>= 1; 2240 reg |= (TXQ_CFG_TD_BURST_DEFAULT << TXQ_CFG_TD_BURST_SHIFT) & 2241 TXQ_CFG_TD_BURST_MASK; 2242 CSR_WRITE_4(sc, ALC_TXQ_CFG, reg | TXQ_CFG_ENHANCED_MODE); 2243 2244 /* Configure Rx free descriptor pre-fetching. */ 2245 CSR_WRITE_4(sc, ALC_RX_RD_FREE_THRESH, 2246 ((RX_RD_FREE_THRESH_HI_DEFAULT << RX_RD_FREE_THRESH_HI_SHIFT) & 2247 RX_RD_FREE_THRESH_HI_MASK) | 2248 ((RX_RD_FREE_THRESH_LO_DEFAULT << RX_RD_FREE_THRESH_LO_SHIFT) & 2249 RX_RD_FREE_THRESH_LO_MASK)); 2250 2251 /* 2252 * Configure flow control parameters. 2253 * XON : 80% of Rx FIFO 2254 * XOFF : 30% of Rx FIFO 2255 */ 2256 if (sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8131 || 2257 sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8132) { 2258 reg = CSR_READ_4(sc, ALC_SRAM_RX_FIFO_LEN); 2259 rxf_hi = (reg * 8) / 10; 2260 rxf_lo = (reg * 3) / 10; 2261 CSR_WRITE_4(sc, ALC_RX_FIFO_PAUSE_THRESH, 2262 ((rxf_lo << RX_FIFO_PAUSE_THRESH_LO_SHIFT) & 2263 RX_FIFO_PAUSE_THRESH_LO_MASK) | 2264 ((rxf_hi << RX_FIFO_PAUSE_THRESH_HI_SHIFT) & 2265 RX_FIFO_PAUSE_THRESH_HI_MASK)); 2266 } 2267 2268 if (sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8152_B || 2269 sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8151_V2) 2270 CSR_WRITE_4(sc, ALC_SERDES_LOCK, 2271 CSR_READ_4(sc, ALC_SERDES_LOCK) | SERDES_MAC_CLK_SLOWDOWN | 2272 SERDES_PHY_CLK_SLOWDOWN); 2273 2274 /* Disable RSS until I understand L1C/L2C's RSS logic. */ 2275 CSR_WRITE_4(sc, ALC_RSS_IDT_TABLE0, 0); 2276 CSR_WRITE_4(sc, ALC_RSS_CPU, 0); 2277 2278 /* Configure RxQ. */ 2279 reg = (RXQ_CFG_RD_BURST_DEFAULT << RXQ_CFG_RD_BURST_SHIFT) & 2280 RXQ_CFG_RD_BURST_MASK; 2281 reg |= RXQ_CFG_RSS_MODE_DIS; 2282 if ((sc->alc_flags & ALC_FLAG_ASPM_MON) != 0) 2283 reg |= RXQ_CFG_ASPM_THROUGHPUT_LIMIT_1M; 2284 CSR_WRITE_4(sc, ALC_RXQ_CFG, reg); 2285 2286 /* Configure DMA parameters. */ 2287 reg = DMA_CFG_OUT_ORDER | DMA_CFG_RD_REQ_PRI; 2288 reg |= sc->alc_rcb; 2289 if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0) 2290 reg |= DMA_CFG_CMB_ENB; 2291 if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0) 2292 reg |= DMA_CFG_SMB_ENB; 2293 else 2294 reg |= DMA_CFG_SMB_DIS; 2295 reg |= (sc->alc_dma_rd_burst & DMA_CFG_RD_BURST_MASK) << 2296 DMA_CFG_RD_BURST_SHIFT; 2297 reg |= (sc->alc_dma_wr_burst & DMA_CFG_WR_BURST_MASK) << 2298 DMA_CFG_WR_BURST_SHIFT; 2299 reg |= (DMA_CFG_RD_DELAY_CNT_DEFAULT << DMA_CFG_RD_DELAY_CNT_SHIFT) & 2300 DMA_CFG_RD_DELAY_CNT_MASK; 2301 reg |= (DMA_CFG_WR_DELAY_CNT_DEFAULT << DMA_CFG_WR_DELAY_CNT_SHIFT) & 2302 DMA_CFG_WR_DELAY_CNT_MASK; 2303 CSR_WRITE_4(sc, ALC_DMA_CFG, reg); 2304 2305 /* 2306 * Configure Tx/Rx MACs. 2307 * - Auto-padding for short frames. 2308 * - Enable CRC generation. 2309 * Actual reconfiguration of MAC for resolved speed/duplex 2310 * is followed after detection of link establishment. 2311 * AR813x/AR815x always does checksum computation regardless 2312 * of MAC_CFG_RXCSUM_ENB bit. Also the controller is known to 2313 * have bug in protocol field in Rx return structure so 2314 * these controllers can't handle fragmented frames. Disable 2315 * Rx checksum offloading until there is a newer controller 2316 * that has sane implementation. 2317 */ 2318 reg = MAC_CFG_TX_CRC_ENB | MAC_CFG_TX_AUTO_PAD | MAC_CFG_FULL_DUPLEX | 2319 ((MAC_CFG_PREAMBLE_DEFAULT << MAC_CFG_PREAMBLE_SHIFT) & 2320 MAC_CFG_PREAMBLE_MASK); 2321 if (sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8151 || 2322 sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8151_V2 || 2323 sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8152_B2) 2324 reg |= MAC_CFG_HASH_ALG_CRC32 | MAC_CFG_SPEED_MODE_SW; 2325 if ((sc->alc_flags & ALC_FLAG_FASTETHER) != 0) 2326 reg |= MAC_CFG_SPEED_10_100; 2327 else 2328 reg |= MAC_CFG_SPEED_1000; 2329 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 2330 2331 /* Set up the receive filter. */ 2332 alc_iff(sc); 2333 alc_rxvlan(sc); 2334 2335 /* Acknowledge all pending interrupts and clear it. */ 2336 CSR_WRITE_4(sc, ALC_INTR_MASK, ALC_INTRS); 2337 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0xFFFFFFFF); 2338 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0); 2339 2340 sc->alc_flags &= ~ALC_FLAG_LINK; 2341 /* Switch to the current media. */ 2342 mii = &sc->sc_miibus; 2343 mii_mediachg(mii); 2344 2345 callout_schedule(&sc->sc_tick_ch, hz); 2346 2347 ifp->if_flags |= IFF_RUNNING; 2348 ifp->if_flags &= ~IFF_OACTIVE; 2349 2350 return (0); 2351 } 2352 2353 static void 2354 alc_stop(struct ifnet *ifp, int disable) 2355 { 2356 struct alc_softc *sc = ifp->if_softc; 2357 struct alc_txdesc *txd; 2358 struct alc_rxdesc *rxd; 2359 uint32_t reg; 2360 int i; 2361 2362 callout_stop(&sc->sc_tick_ch); 2363 2364 /* 2365 * Mark the interface down and cancel the watchdog timer. 2366 */ 2367 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2368 ifp->if_timer = 0; 2369 2370 sc->alc_flags &= ~ALC_FLAG_LINK; 2371 2372 alc_stats_update(sc); 2373 2374 mii_down(&sc->sc_miibus); 2375 2376 /* Disable interrupts. */ 2377 CSR_WRITE_4(sc, ALC_INTR_MASK, 0); 2378 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0xFFFFFFFF); 2379 alc_stop_queue(sc); 2380 2381 /* Disable DMA. */ 2382 reg = CSR_READ_4(sc, ALC_DMA_CFG); 2383 reg &= ~(DMA_CFG_CMB_ENB | DMA_CFG_SMB_ENB); 2384 reg |= DMA_CFG_SMB_DIS; 2385 CSR_WRITE_4(sc, ALC_DMA_CFG, reg); 2386 DELAY(1000); 2387 2388 /* Stop Rx/Tx MACs. */ 2389 alc_stop_mac(sc); 2390 2391 /* Disable interrupts which might be touched in taskq handler. */ 2392 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0xFFFFFFFF); 2393 2394 /* Reclaim Rx buffers that have been processed. */ 2395 if (sc->alc_cdata.alc_rxhead != NULL) 2396 m_freem(sc->alc_cdata.alc_rxhead); 2397 ALC_RXCHAIN_RESET(sc); 2398 /* 2399 * Free Tx/Rx mbufs still in the queues. 2400 */ 2401 for (i = 0; i < ALC_RX_RING_CNT; i++) { 2402 rxd = &sc->alc_cdata.alc_rxdesc[i]; 2403 if (rxd->rx_m != NULL) { 2404 bus_dmamap_unload(sc->sc_dmat, rxd->rx_dmamap); 2405 m_freem(rxd->rx_m); 2406 rxd->rx_m = NULL; 2407 } 2408 } 2409 for (i = 0; i < ALC_TX_RING_CNT; i++) { 2410 txd = &sc->alc_cdata.alc_txdesc[i]; 2411 if (txd->tx_m != NULL) { 2412 bus_dmamap_unload(sc->sc_dmat, txd->tx_dmamap); 2413 m_freem(txd->tx_m); 2414 txd->tx_m = NULL; 2415 } 2416 } 2417 } 2418 2419 static void 2420 alc_stop_mac(struct alc_softc *sc) 2421 { 2422 uint32_t reg; 2423 int i; 2424 2425 /* Disable Rx/Tx MAC. */ 2426 reg = CSR_READ_4(sc, ALC_MAC_CFG); 2427 if ((reg & (MAC_CFG_TX_ENB | MAC_CFG_RX_ENB)) != 0) { 2428 reg &= ~(MAC_CFG_TX_ENB | MAC_CFG_RX_ENB); 2429 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 2430 } 2431 for (i = ALC_TIMEOUT; i > 0; i--) { 2432 reg = CSR_READ_4(sc, ALC_IDLE_STATUS); 2433 if (reg == 0) 2434 break; 2435 DELAY(10); 2436 } 2437 if (i == 0) 2438 printf("%s: could not disable Rx/Tx MAC(0x%08x)!\n", 2439 device_xname(sc->sc_dev), reg); 2440 } 2441 2442 static void 2443 alc_start_queue(struct alc_softc *sc) 2444 { 2445 uint32_t qcfg[] = { 2446 0, 2447 RXQ_CFG_QUEUE0_ENB, 2448 RXQ_CFG_QUEUE0_ENB | RXQ_CFG_QUEUE1_ENB, 2449 RXQ_CFG_QUEUE0_ENB | RXQ_CFG_QUEUE1_ENB | RXQ_CFG_QUEUE2_ENB, 2450 RXQ_CFG_ENB 2451 }; 2452 uint32_t cfg; 2453 2454 /* Enable RxQ. */ 2455 cfg = CSR_READ_4(sc, ALC_RXQ_CFG); 2456 cfg &= ~RXQ_CFG_ENB; 2457 cfg |= qcfg[1]; 2458 CSR_WRITE_4(sc, ALC_RXQ_CFG, cfg); 2459 /* Enable TxQ. */ 2460 cfg = CSR_READ_4(sc, ALC_TXQ_CFG); 2461 cfg |= TXQ_CFG_ENB; 2462 CSR_WRITE_4(sc, ALC_TXQ_CFG, cfg); 2463 } 2464 2465 static void 2466 alc_stop_queue(struct alc_softc *sc) 2467 { 2468 uint32_t reg; 2469 int i; 2470 2471 /* Disable RxQ. */ 2472 reg = CSR_READ_4(sc, ALC_RXQ_CFG); 2473 if ((reg & RXQ_CFG_ENB) != 0) { 2474 reg &= ~RXQ_CFG_ENB; 2475 CSR_WRITE_4(sc, ALC_RXQ_CFG, reg); 2476 } 2477 /* Disable TxQ. */ 2478 reg = CSR_READ_4(sc, ALC_TXQ_CFG); 2479 if ((reg & TXQ_CFG_ENB) != 0) { 2480 reg &= ~TXQ_CFG_ENB; 2481 CSR_WRITE_4(sc, ALC_TXQ_CFG, reg); 2482 } 2483 for (i = ALC_TIMEOUT; i > 0; i--) { 2484 reg = CSR_READ_4(sc, ALC_IDLE_STATUS); 2485 if ((reg & (IDLE_STATUS_RXQ | IDLE_STATUS_TXQ)) == 0) 2486 break; 2487 DELAY(10); 2488 } 2489 if (i == 0) 2490 printf("%s: could not disable RxQ/TxQ (0x%08x)!\n", 2491 device_xname(sc->sc_dev), reg); 2492 } 2493 2494 static void 2495 alc_init_tx_ring(struct alc_softc *sc) 2496 { 2497 struct alc_ring_data *rd; 2498 struct alc_txdesc *txd; 2499 int i; 2500 2501 sc->alc_cdata.alc_tx_prod = 0; 2502 sc->alc_cdata.alc_tx_cons = 0; 2503 sc->alc_cdata.alc_tx_cnt = 0; 2504 2505 rd = &sc->alc_rdata; 2506 memset(rd->alc_tx_ring, 0, ALC_TX_RING_SZ); 2507 for (i = 0; i < ALC_TX_RING_CNT; i++) { 2508 txd = &sc->alc_cdata.alc_txdesc[i]; 2509 txd->tx_m = NULL; 2510 } 2511 2512 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_tx_ring_map, 0, 2513 sc->alc_cdata.alc_tx_ring_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 2514 } 2515 2516 static int 2517 alc_init_rx_ring(struct alc_softc *sc) 2518 { 2519 struct alc_ring_data *rd; 2520 struct alc_rxdesc *rxd; 2521 int i; 2522 2523 sc->alc_cdata.alc_rx_cons = ALC_RX_RING_CNT - 1; 2524 rd = &sc->alc_rdata; 2525 memset(rd->alc_rx_ring, 0, ALC_RX_RING_SZ); 2526 for (i = 0; i < ALC_RX_RING_CNT; i++) { 2527 rxd = &sc->alc_cdata.alc_rxdesc[i]; 2528 rxd->rx_m = NULL; 2529 rxd->rx_desc = &rd->alc_rx_ring[i]; 2530 if (alc_newbuf(sc, rxd, 1) != 0) 2531 return (ENOBUFS); 2532 } 2533 2534 /* 2535 * Since controller does not update Rx descriptors, driver 2536 * does have to read Rx descriptors back so BUS_DMASYNC_PREWRITE 2537 * is enough to ensure coherence. 2538 */ 2539 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_rx_ring_map, 0, 2540 sc->alc_cdata.alc_rx_ring_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 2541 /* Let controller know availability of new Rx buffers. */ 2542 CSR_WRITE_4(sc, ALC_MBOX_RD0_PROD_IDX, sc->alc_cdata.alc_rx_cons); 2543 2544 return (0); 2545 } 2546 2547 static void 2548 alc_init_rr_ring(struct alc_softc *sc) 2549 { 2550 struct alc_ring_data *rd; 2551 2552 sc->alc_cdata.alc_rr_cons = 0; 2553 ALC_RXCHAIN_RESET(sc); 2554 2555 rd = &sc->alc_rdata; 2556 memset(rd->alc_rr_ring, 0, ALC_RR_RING_SZ); 2557 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_rr_ring_map, 0, 2558 sc->alc_cdata.alc_rr_ring_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 2559 } 2560 2561 static void 2562 alc_init_cmb(struct alc_softc *sc) 2563 { 2564 struct alc_ring_data *rd; 2565 2566 rd = &sc->alc_rdata; 2567 memset(rd->alc_cmb, 0, ALC_CMB_SZ); 2568 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_cmb_map, 0, 2569 sc->alc_cdata.alc_cmb_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 2570 } 2571 2572 static void 2573 alc_init_smb(struct alc_softc *sc) 2574 { 2575 struct alc_ring_data *rd; 2576 2577 rd = &sc->alc_rdata; 2578 memset(rd->alc_smb, 0, ALC_SMB_SZ); 2579 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_smb_map, 0, 2580 sc->alc_cdata.alc_smb_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 2581 } 2582 2583 static void 2584 alc_rxvlan(struct alc_softc *sc) 2585 { 2586 uint32_t reg; 2587 2588 reg = CSR_READ_4(sc, ALC_MAC_CFG); 2589 if (sc->sc_ec.ec_capenable & ETHERCAP_VLAN_HWTAGGING) 2590 reg |= MAC_CFG_VLAN_TAG_STRIP; 2591 else 2592 reg &= ~MAC_CFG_VLAN_TAG_STRIP; 2593 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 2594 } 2595 2596 static void 2597 alc_iff(struct alc_softc *sc) 2598 { 2599 struct ethercom *ec = &sc->sc_ec; 2600 struct ifnet *ifp = &ec->ec_if; 2601 struct ether_multi *enm; 2602 struct ether_multistep step; 2603 uint32_t crc; 2604 uint32_t mchash[2]; 2605 uint32_t rxcfg; 2606 2607 rxcfg = CSR_READ_4(sc, ALC_MAC_CFG); 2608 rxcfg &= ~(MAC_CFG_ALLMULTI | MAC_CFG_BCAST | MAC_CFG_PROMISC); 2609 ifp->if_flags &= ~IFF_ALLMULTI; 2610 2611 /* 2612 * Always accept broadcast frames. 2613 */ 2614 rxcfg |= MAC_CFG_BCAST; 2615 2616 if (ifp->if_flags & IFF_PROMISC || ec->ec_multicnt > 0) { 2617 ifp->if_flags |= IFF_ALLMULTI; 2618 if (ifp->if_flags & IFF_PROMISC) 2619 rxcfg |= MAC_CFG_PROMISC; 2620 else 2621 rxcfg |= MAC_CFG_ALLMULTI; 2622 mchash[0] = mchash[1] = 0xFFFFFFFF; 2623 } else { 2624 /* Program new filter. */ 2625 memset(mchash, 0, sizeof(mchash)); 2626 2627 ETHER_FIRST_MULTI(step, ec, enm); 2628 while (enm != NULL) { 2629 crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 2630 mchash[crc >> 31] |= 1 << ((crc >> 26) & 0x1f); 2631 ETHER_NEXT_MULTI(step, enm); 2632 } 2633 } 2634 2635 CSR_WRITE_4(sc, ALC_MAR0, mchash[0]); 2636 CSR_WRITE_4(sc, ALC_MAR1, mchash[1]); 2637 CSR_WRITE_4(sc, ALC_MAC_CFG, rxcfg); 2638 } 2639 2640 MODULE(MODULE_CLASS_DRIVER, if_alc, "pci"); 2641 2642 #ifdef _MODULE 2643 #include "ioconf.c" 2644 #endif 2645 2646 static int 2647 if_alc_modcmd(modcmd_t cmd, void *opaque) 2648 { 2649 int error = 0; 2650 2651 switch (cmd) { 2652 case MODULE_CMD_INIT: 2653 #ifdef _MODULE 2654 error = config_init_component(cfdriver_ioconf_if_alc, 2655 cfattach_ioconf_if_alc, cfdata_ioconf_if_alc); 2656 #endif 2657 return error; 2658 case MODULE_CMD_FINI: 2659 #ifdef _MODULE 2660 error = config_fini_component(cfdriver_ioconf_if_alc, 2661 cfattach_ioconf_if_alc, cfdata_ioconf_if_alc); 2662 #endif 2663 return error; 2664 default: 2665 return ENOTTY; 2666 } 2667 } 2668
Indexes created Fri Sep 26 20:09:58 GMT 2025