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if_alcreg.h revision 1.6.16.1
      1  1.6.16.1    martin /*	$NetBSD: if_alcreg.h,v 1.6.16.1 2020/04/08 14:08:09 martin Exp $	*/
      2       1.1  jmcneill /*	$OpenBSD: if_alcreg.h,v 1.1 2009/08/08 09:31:13 kevlo Exp $	*/
      3       1.1  jmcneill /*-
      4       1.1  jmcneill  * Copyright (c) 2009, Pyun YongHyeon <yongari (at) FreeBSD.org>
      5       1.1  jmcneill  * All rights reserved.
      6       1.1  jmcneill  *
      7       1.1  jmcneill  * Redistribution and use in source and binary forms, with or without
      8       1.1  jmcneill  * modification, are permitted provided that the following conditions
      9       1.1  jmcneill  * are met:
     10       1.1  jmcneill  * 1. Redistributions of source code must retain the above copyright
     11       1.1  jmcneill  *    notice unmodified, this list of conditions, and the following
     12       1.1  jmcneill  *    disclaimer.
     13       1.1  jmcneill  * 2. Redistributions in binary form must reproduce the above copyright
     14       1.1  jmcneill  *    notice, this list of conditions and the following disclaimer in the
     15       1.1  jmcneill  *    documentation and/or other materials provided with the distribution.
     16       1.1  jmcneill  *
     17       1.1  jmcneill  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
     18       1.1  jmcneill  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
     19       1.1  jmcneill  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
     20       1.1  jmcneill  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
     21       1.1  jmcneill  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
     22       1.1  jmcneill  * DAMATES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
     23       1.1  jmcneill  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
     24       1.1  jmcneill  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
     25       1.1  jmcneill  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
     26       1.1  jmcneill  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
     27       1.1  jmcneill  * SUCH DAMATE.
     28       1.1  jmcneill  *
     29       1.1  jmcneill  * $FreeBSD: src/sys/dev/alc/if_alcreg.h,v 1.1 2009/06/10 02:07:58 yongari Exp $
     30       1.1  jmcneill  */
     31       1.1  jmcneill 
     32       1.1  jmcneill #ifndef	_IF_ALCREG_H
     33       1.1  jmcneill #define	_IF_ALCREG_H
     34       1.1  jmcneill 
     35       1.1  jmcneill #define ALC_PCIR_BAR			0x10
     36       1.1  jmcneill 
     37       1.2  jmcneill #define ATHEROS_AR8152_B_V10		0xC0
     38       1.2  jmcneill #define ATHEROS_AR8152_B_V11		0xC1
     39       1.2  jmcneill 
     40       1.3  christos /*
     41       1.3  christos  * Atheros AR816x/AR817x revisions
     42       1.3  christos  */
     43       1.3  christos #define	AR816X_REV_A0			0
     44       1.3  christos #define	AR816X_REV_A1			1
     45       1.3  christos #define	AR816X_REV_B0			2
     46       1.3  christos #define	AR816X_REV_C0			3
     47       1.3  christos 
     48       1.3  christos #define	AR816X_REV_SHIFT		3
     49       1.3  christos #define	AR816X_REV(x)			((x) >> AR816X_REV_SHIFT)
     50       1.3  christos 
     51       1.1  jmcneill /* 0x0000 - 0x02FF : PCIe configuration space */
     52       1.1  jmcneill 
     53       1.1  jmcneill #define	ALC_PEX_UNC_ERR_SEV		0x10C
     54       1.1  jmcneill #define	PEX_UNC_ERR_SEV_TRN		0x00000001
     55       1.1  jmcneill #define	PEX_UNC_ERR_SEV_DLP		0x00000010
     56       1.1  jmcneill #define	PEX_UNC_ERR_SEV_PSN_TLP		0x00001000
     57       1.1  jmcneill #define	PEX_UNC_ERR_SEV_FCP		0x00002000
     58       1.1  jmcneill #define	PEX_UNC_ERR_SEV_CPL_TO		0x00004000
     59       1.1  jmcneill #define	PEX_UNC_ERR_SEV_CA		0x00008000
     60       1.1  jmcneill #define	PEX_UNC_ERR_SEV_UC		0x00010000
     61       1.1  jmcneill #define	PEX_UNC_ERR_SEV_ROV		0x00020000
     62       1.1  jmcneill #define	PEX_UNC_ERR_SEV_MLFP		0x00040000
     63       1.1  jmcneill #define	PEX_UNC_ERR_SEV_ECRC		0x00080000
     64       1.1  jmcneill #define	PEX_UNC_ERR_SEV_UR		0x00100000
     65       1.1  jmcneill 
     66       1.3  christos #define	ALC_EEPROM_LD			0x204	/* AR816x */
     67       1.3  christos #define	EEPROM_LD_START			0x00000001
     68       1.3  christos #define	EEPROM_LD_IDLE			0x00000010
     69       1.3  christos #define	EEPROM_LD_DONE			0x00000000
     70       1.3  christos #define	EEPROM_LD_PROGRESS		0x00000020
     71       1.3  christos #define	EEPROM_LD_EXIST			0x00000100
     72       1.3  christos #define	EEPROM_LD_EEPROM_EXIST		0x00000200
     73       1.3  christos #define	EEPROM_LD_FLASH_EXIST		0x00000400
     74       1.3  christos #define	EEPROM_LD_FLASH_END_ADDR_MASK	0x03FF0000
     75       1.3  christos #define	EEPROM_LD_FLASH_END_ADDR_SHIFT	16
     76       1.3  christos 
     77       1.1  jmcneill #define	ALC_TWSI_CFG			0x218
     78       1.1  jmcneill #define	TWSI_CFG_SW_LD_START		0x00000800
     79       1.1  jmcneill #define	TWSI_CFG_HW_LD_START		0x00001000
     80       1.1  jmcneill #define	TWSI_CFG_LD_EXIST		0x00400000
     81       1.1  jmcneill 
     82       1.3  christos #define	ALC_SLD				0x218	/* AR816x */
     83       1.3  christos #define	SLD_START			0x00000800
     84       1.3  christos #define	SLD_PROGRESS			0x00001000
     85       1.3  christos #define	SLD_IDLE			0x00002000
     86       1.3  christos #define	SLD_SLVADDR_MASK		0x007F0000
     87       1.3  christos #define	SLD_EXIST			0x00800000
     88       1.3  christos #define	SLD_FREQ_MASK			0x03000000
     89       1.3  christos #define	SLD_FREQ_100K			0x00000000
     90       1.3  christos #define	SLD_FREQ_200K			0x01000000
     91       1.3  christos #define	SLD_FREQ_300K			0x02000000
     92       1.3  christos #define	SLD_FREQ_400K			0x03000000
     93       1.3  christos 
     94       1.1  jmcneill #define	ALC_PCIE_PHYMISC		0x1000
     95       1.1  jmcneill #define	PCIE_PHYMISC_FORCE_RCV_DET	0x00000004
     96       1.1  jmcneill 
     97       1.2  jmcneill #define	ALC_PCIE_PHYMISC2		0x1004
     98       1.2  jmcneill #define	PCIE_PHYMISC2_SERDES_CDR_MASK	0x00030000
     99       1.2  jmcneill #define	PCIE_PHYMISC2_SERDES_TH_MASK	0x000C0000
    100       1.2  jmcneill #define	PCIE_PHYMISC2_SERDES_CDR_SHIFT	16
    101       1.2  jmcneill #define	PCIE_PHYMISC2_SERDES_TH_SHIFT	18
    102       1.2  jmcneill 
    103       1.1  jmcneill #define	ALC_TWSI_DEBUG			0x1108
    104       1.1  jmcneill #define	TWSI_DEBUG_DEV_EXIST		0x20000000
    105       1.1  jmcneill 
    106       1.3  christos #define	ALC_PDLL_TRNS1			0x1104
    107       1.3  christos #define	PDLL_TRNS1_D3PLLOFF_ENB		0x00000800
    108       1.3  christos 
    109       1.1  jmcneill #define	ALC_EEPROM_CFG			0x12C0
    110       1.1  jmcneill #define	EEPROM_CFG_DATA_HI_MASK		0x0000FFFF
    111       1.1  jmcneill #define	EEPROM_CFG_ADDR_MASK		0x03FF0000
    112       1.1  jmcneill #define	EEPROM_CFG_ACK			0x40000000
    113       1.1  jmcneill #define	EEPROM_CFG_RW			0x80000000
    114       1.1  jmcneill #define	EEPROM_CFG_DATA_HI_SHIFT	0
    115       1.1  jmcneill #define	EEPROM_CFG_ADDR_SHIFT		16
    116       1.1  jmcneill 
    117       1.1  jmcneill #define	ALC_EEPROM_DATA_LO		0x12C4
    118       1.1  jmcneill 
    119       1.1  jmcneill #define	ALC_OPT_CFG			0x12F0
    120       1.1  jmcneill #define	OPT_CFG_CLK_ENB			0x00000002
    121       1.1  jmcneill 
    122       1.1  jmcneill #define	ALC_PM_CFG			0x12F8
    123       1.1  jmcneill #define	PM_CFG_SERDES_ENB		0x00000001
    124       1.1  jmcneill #define	PM_CFG_RBER_ENB			0x00000002
    125       1.1  jmcneill #define	PM_CFG_CLK_REQ_ENB		0x00000004
    126       1.1  jmcneill #define	PM_CFG_ASPM_L1_ENB		0x00000008
    127       1.1  jmcneill #define	PM_CFG_SERDES_L1_ENB		0x00000010
    128       1.1  jmcneill #define	PM_CFG_SERDES_PLL_L1_ENB	0x00000020
    129       1.1  jmcneill #define	PM_CFG_SERDES_PD_EX_L1		0x00000040
    130       1.1  jmcneill #define	PM_CFG_SERDES_BUDS_RX_L1_ENB	0x00000080
    131       1.1  jmcneill #define	PM_CFG_L0S_ENTRY_TIMER_MASK	0x00000F00
    132       1.3  christos #define	PM_CFG_RX_L1_AFTER_L0S		0x00000800
    133       1.1  jmcneill #define	PM_CFG_ASPM_L0S_ENB		0x00001000
    134       1.1  jmcneill #define	PM_CFG_CLK_SWH_L1		0x00002000
    135       1.1  jmcneill #define	PM_CFG_CLK_PWM_VER1_1		0x00004000
    136       1.1  jmcneill #define	PM_CFG_PCIE_RECV		0x00008000
    137       1.1  jmcneill #define	PM_CFG_L1_ENTRY_TIMER_MASK	0x000F0000
    138       1.3  christos #define	PM_CFG_L1_ENTRY_TIMER_816X_MASK	0x00070000
    139       1.3  christos #define	PM_CFG_TX_L1_AFTER_L0S		0x00080000
    140       1.1  jmcneill #define	PM_CFG_PM_REQ_TIMER_MASK	0x00F00000
    141       1.2  jmcneill #define	PM_CFG_LCKDET_TIMER_MASK	0x0F000000
    142       1.2  jmcneill #define	PM_CFG_EN_BUFS_RX_L0S		0x10000000
    143       1.2  jmcneill #define	PM_CFG_SA_DLY_ENB		0x20000000
    144       1.1  jmcneill #define	PM_CFG_MAC_ASPM_CHK		0x40000000
    145       1.1  jmcneill #define	PM_CFG_HOTRST			0x80000000
    146       1.1  jmcneill #define	PM_CFG_L0S_ENTRY_TIMER_SHIFT	8
    147       1.1  jmcneill #define	PM_CFG_L1_ENTRY_TIMER_SHIFT	16
    148       1.1  jmcneill #define	PM_CFG_PM_REQ_TIMER_SHIFT	20
    149       1.1  jmcneill #define	PM_CFG_LCKDET_TIMER_SHIFT	24
    150       1.1  jmcneill 
    151       1.2  jmcneill #define PM_CFG_L0S_ENTRY_TIMER_DEFAULT	6
    152       1.2  jmcneill #define	PM_CFG_L1_ENTRY_TIMER_DEFAULT	1
    153       1.3  christos #define	PM_CFG_L1_ENTRY_TIMER_816X_DEFAULT	4
    154       1.2  jmcneill #define	PM_CFG_LCKDET_TIMER_DEFAULT	12
    155       1.2  jmcneill #define	PM_CFG_PM_REQ_TIMER_DEFAULT	12
    156       1.3  christos #define	PM_CFG_PM_REQ_TIMER_816X_DEFAULT	15
    157       1.2  jmcneill 
    158       1.2  jmcneill #define	ALC_LTSSM_ID_CFG		0x12FC
    159       1.2  jmcneill #define	LTSSM_ID_WRO_ENB		0x00001000
    160       1.2  jmcneill 
    161       1.1  jmcneill #define	ALC_MASTER_CFG			0x1400
    162       1.1  jmcneill #define	MASTER_RESET			0x00000001
    163       1.2  jmcneill #define	MASTER_TEST_MODE_MASK		0x0000000C
    164       1.1  jmcneill #define	MASTER_BERT_START		0x00000010
    165       1.3  christos #define	MASTER_WAKEN_25M		0x00000020
    166       1.2  jmcneill #define	MASTER_OOB_DIS_OFF		0x00000040
    167       1.2  jmcneill #define	MASTER_SA_TIMER_ENB		0x00000080
    168       1.1  jmcneill #define	MASTER_MTIMER_ENB		0x00000100
    169       1.1  jmcneill #define	MASTER_MANUAL_INTR_ENB		0x00000200
    170       1.1  jmcneill #define	MASTER_IM_TX_TIMER_ENB		0x00000400
    171       1.1  jmcneill #define	MASTER_IM_RX_TIMER_ENB		0x00000800
    172       1.1  jmcneill #define	MASTER_CLK_SEL_DIS		0x00001000
    173       1.1  jmcneill #define	MASTER_CLK_SWH_MODE		0x00002000
    174       1.1  jmcneill #define	MASTER_INTR_RD_CLR		0x00004000
    175       1.1  jmcneill #define	MASTER_CHIP_REV_MASK		0x00FF0000
    176       1.1  jmcneill #define	MASTER_CHIP_ID_MASK		0x7F000000
    177       1.1  jmcneill #define	MASTER_OTP_SEL			0x80000000
    178       1.1  jmcneill #define	MASTER_TEST_MODE_SHIFT		2
    179       1.1  jmcneill #define	MASTER_CHIP_REV_SHIFT		16
    180       1.1  jmcneill #define	MASTER_CHIP_ID_SHIFT		24
    181       1.1  jmcneill 
    182       1.2  jmcneill /* Number of ticks per usec for AR813x/AR815x. */
    183       1.1  jmcneill #define	ALC_TICK_USECS			2
    184       1.1  jmcneill #define	ALC_USECS(x)			((x) / ALC_TICK_USECS)
    185       1.1  jmcneill 
    186       1.1  jmcneill #define	ALC_MANUAL_TIMER		0x1404
    187       1.1  jmcneill 
    188       1.1  jmcneill #define	ALC_IM_TIMER			0x1408
    189       1.1  jmcneill #define	IM_TIMER_TX_MASK		0x0000FFFF
    190       1.1  jmcneill #define	IM_TIMER_RX_MASK		0xFFFF0000
    191       1.1  jmcneill #define	IM_TIMER_TX_SHIFT		0
    192       1.1  jmcneill #define	IM_TIMER_RX_SHIFT		16
    193       1.1  jmcneill #define	ALC_IM_TIMER_MIN		0
    194       1.1  jmcneill #define	ALC_IM_TIMER_MAX		130000	/* 130ms */
    195       1.1  jmcneill /*
    196       1.1  jmcneill  * 100us will ensure alc(4) wouldn't generate more than 10000 Rx
    197       1.1  jmcneill  * interrupts in a second.
    198       1.1  jmcneill  */
    199       1.1  jmcneill #define	ALC_IM_RX_TIMER_DEFAULT		100	/* 100us */
    200       1.1  jmcneill /*
    201       1.1  jmcneill  * alc(4) does not rely on Tx completion interrupts, so set it
    202       1.1  jmcneill  * somewhat large value to reduce Tx completion interrupts.
    203       1.1  jmcneill  */
    204       1.4      leot #define	ALC_IM_TX_TIMER_DEFAULT		1000	/* 1ms */
    205       1.1  jmcneill 
    206       1.3  christos #define	ALC_GPHY_CFG			0x140C	/* 16 bits, 32 bits on AR816x */
    207       1.1  jmcneill #define	GPHY_CFG_EXT_RESET		0x0001
    208       1.1  jmcneill #define	GPHY_CFG_RTL_MODE		0x0002
    209       1.1  jmcneill #define	GPHY_CFG_LED_MODE		0x0004
    210       1.1  jmcneill #define	GPHY_CFG_ANEG_NOW		0x0008
    211       1.1  jmcneill #define	GPHY_CFG_RECV_ANEG		0x0010
    212       1.1  jmcneill #define	GPHY_CFG_GATE_25M_ENB		0x0020
    213       1.1  jmcneill #define	GPHY_CFG_LPW_EXIT		0x0040
    214       1.1  jmcneill #define	GPHY_CFG_PHY_IDDQ		0x0080
    215       1.1  jmcneill #define	GPHY_CFG_PHY_IDDQ_DIS		0x0100
    216       1.1  jmcneill #define	GPHY_CFG_PCLK_SEL_DIS		0x0200
    217       1.1  jmcneill #define	GPHY_CFG_HIB_EN			0x0400
    218       1.1  jmcneill #define	GPHY_CFG_HIB_PULSE		0x0800
    219       1.1  jmcneill #define	GPHY_CFG_SEL_ANA_RESET		0x1000
    220       1.1  jmcneill #define	GPHY_CFG_PHY_PLL_ON		0x2000
    221       1.1  jmcneill #define	GPHY_CFG_PWDOWN_HW		0x4000
    222       1.1  jmcneill #define	GPHY_CFG_PHY_PLL_BYPASS		0x8000
    223       1.3  christos #define	GPHY_CFG_100AB_ENB		0x00020000
    224       1.1  jmcneill 
    225       1.1  jmcneill #define	ALC_IDLE_STATUS			0x1410
    226       1.1  jmcneill #define	IDLE_STATUS_RXMAC		0x00000001
    227       1.1  jmcneill #define	IDLE_STATUS_TXMAC		0x00000002
    228       1.1  jmcneill #define	IDLE_STATUS_RXQ			0x00000004
    229       1.1  jmcneill #define	IDLE_STATUS_TXQ			0x00000008
    230       1.1  jmcneill #define	IDLE_STATUS_DMARD		0x00000010
    231       1.1  jmcneill #define	IDLE_STATUS_DMAWR		0x00000020
    232       1.1  jmcneill #define	IDLE_STATUS_SMB			0x00000040
    233       1.1  jmcneill #define	IDLE_STATUS_CMB			0x00000080
    234       1.1  jmcneill 
    235       1.1  jmcneill #define	ALC_MDIO			0x1414
    236       1.1  jmcneill #define	MDIO_DATA_MASK			0x0000FFFF
    237       1.1  jmcneill #define	MDIO_REG_ADDR_MASK		0x001F0000
    238       1.1  jmcneill #define	MDIO_OP_READ			0x00200000
    239       1.1  jmcneill #define	MDIO_OP_WRITE			0x00000000
    240       1.1  jmcneill #define	MDIO_SUP_PREAMBLE		0x00400000
    241       1.1  jmcneill #define	MDIO_OP_EXECUTE			0x00800000
    242       1.1  jmcneill #define	MDIO_CLK_25_4			0x00000000
    243       1.1  jmcneill #define	MDIO_CLK_25_6			0x02000000
    244       1.1  jmcneill #define	MDIO_CLK_25_8			0x03000000
    245       1.1  jmcneill #define	MDIO_CLK_25_10			0x04000000
    246       1.1  jmcneill #define	MDIO_CLK_25_14			0x05000000
    247       1.1  jmcneill #define	MDIO_CLK_25_20			0x06000000
    248       1.3  christos #define	MDIO_CLK_25_128			0x07000000
    249       1.1  jmcneill #define	MDIO_OP_BUSY			0x08000000
    250       1.1  jmcneill #define	MDIO_AP_ENB			0x10000000
    251       1.3  christos #define	MDIO_MODE_EXT			0x40000000
    252       1.1  jmcneill #define	MDIO_DATA_SHIFT			0
    253       1.1  jmcneill #define	MDIO_REG_ADDR_SHIFT		16
    254       1.1  jmcneill 
    255       1.1  jmcneill #define	MDIO_REG_ADDR(x)	\
    256       1.1  jmcneill 	(((x) << MDIO_REG_ADDR_SHIFT) & MDIO_REG_ADDR_MASK)
    257       1.1  jmcneill /* Default PHY address. */
    258       1.1  jmcneill #define	ALC_PHY_ADDR			0
    259       1.1  jmcneill 
    260       1.1  jmcneill #define	ALC_PHY_STATUS			0x1418
    261       1.1  jmcneill #define	PHY_STATUS_RECV_ENB		0x00000001
    262       1.1  jmcneill #define	PHY_STATUS_GENERAL_MASK		0x0000FFFF
    263       1.1  jmcneill #define	PHY_STATUS_OE_PWSP_MASK		0x07FF0000
    264       1.1  jmcneill #define	PHY_STATUS_LPW_STATE		0x80000000
    265       1.1  jmcneill #define	PHY_STATIS_OE_PWSP_SHIFT	16
    266       1.1  jmcneill 
    267       1.1  jmcneill /* Packet memory BIST. */
    268       1.1  jmcneill #define	ALC_BIST0			0x141C
    269       1.1  jmcneill #define	BIST0_ENB			0x00000001
    270       1.1  jmcneill #define	BIST0_SRAM_FAIL			0x00000002
    271       1.1  jmcneill #define	BIST0_FUSE_FLAG			0x00000004
    272       1.1  jmcneill 
    273       1.1  jmcneill /* PCIe retry buffer BIST. */
    274       1.1  jmcneill #define	ALC_BIST1			0x1420
    275       1.1  jmcneill #define	BIST1_ENB			0x00000001
    276       1.1  jmcneill #define	BIST1_SRAM_FAIL			0x00000002
    277       1.1  jmcneill #define	BIST1_FUSE_FLAG			0x00000004
    278       1.1  jmcneill 
    279       1.1  jmcneill #define	ALC_SERDES_LOCK			0x1424
    280       1.1  jmcneill #define	SERDES_LOCK_DET			0x00000001
    281       1.1  jmcneill #define	SERDES_LOCK_DET_ENB		0x00000002
    282       1.2  jmcneill #define	SERDES_MAC_CLK_SLOWDOWN		0x00020000
    283       1.2  jmcneill #define	SERDES_PHY_CLK_SLOWDOWN		0x00040000
    284       1.1  jmcneill 
    285       1.3  christos #define	ALC_LPI_CTL			0x1440
    286       1.3  christos #define	LPI_CTL_ENB			0x00000001
    287       1.3  christos 
    288       1.3  christos #define	ALC_EXT_MDIO			0x1448
    289       1.3  christos #define	EXT_MDIO_REG_MASK		0x0000FFFF
    290       1.3  christos #define	EXT_MDIO_DEVADDR_MASK		0x001F0000
    291       1.3  christos #define	EXT_MDIO_REG_SHIFT		0
    292       1.3  christos #define	EXT_MDIO_DEVADDR_SHIFT		16
    293       1.3  christos 
    294       1.3  christos #define	EXT_MDIO_REG(x)		\
    295       1.3  christos 	(((x) << EXT_MDIO_REG_SHIFT) & EXT_MDIO_REG_MASK)
    296       1.3  christos #define	EXT_MDIO_DEVADDR(x)	\
    297       1.3  christos 	(((x) << EXT_MDIO_DEVADDR_SHIFT) & EXT_MDIO_DEVADDR_MASK)
    298       1.3  christos 
    299       1.3  christos #define	ALC_IDLE_DECISN_TIMER		0x1474
    300       1.3  christos #define	IDLE_DECISN_TIMER_DEFAULT_1MS	0x400
    301       1.3  christos 
    302       1.1  jmcneill #define	ALC_MAC_CFG			0x1480
    303       1.1  jmcneill #define	MAC_CFG_TX_ENB			0x00000001
    304       1.1  jmcneill #define	MAC_CFG_RX_ENB			0x00000002
    305       1.1  jmcneill #define	MAC_CFG_TX_FC			0x00000004
    306       1.1  jmcneill #define	MAC_CFG_RX_FC			0x00000008
    307       1.1  jmcneill #define	MAC_CFG_LOOP			0x00000010
    308       1.1  jmcneill #define	MAC_CFG_FULL_DUPLEX		0x00000020
    309       1.1  jmcneill #define	MAC_CFG_TX_CRC_ENB		0x00000040
    310       1.1  jmcneill #define	MAC_CFG_TX_AUTO_PAD		0x00000080
    311       1.1  jmcneill #define	MAC_CFG_TX_LENCHK		0x00000100
    312       1.1  jmcneill #define	MAC_CFG_RX_JUMBO_ENB		0x00000200
    313       1.1  jmcneill #define	MAC_CFG_PREAMBLE_MASK		0x00003C00
    314       1.1  jmcneill #define	MAC_CFG_VLAN_TAG_STRIP		0x00004000
    315       1.1  jmcneill #define	MAC_CFG_PROMISC			0x00008000
    316       1.1  jmcneill #define	MAC_CFG_TX_PAUSE		0x00010000
    317       1.1  jmcneill #define	MAC_CFG_SCNT			0x00020000
    318       1.1  jmcneill #define	MAC_CFG_SYNC_RST_TX		0x00040000
    319       1.1  jmcneill #define	MAC_CFG_SIM_RST_TX		0x00080000
    320       1.1  jmcneill #define	MAC_CFG_SPEED_MASK		0x00300000
    321       1.1  jmcneill #define	MAC_CFG_SPEED_10_100		0x00100000
    322       1.1  jmcneill #define	MAC_CFG_SPEED_1000		0x00200000
    323       1.1  jmcneill #define	MAC_CFG_DBG_TX_BACKOFF		0x00400000
    324       1.1  jmcneill #define	MAC_CFG_TX_JUMBO_ENB		0x00800000
    325       1.1  jmcneill #define	MAC_CFG_RXCSUM_ENB		0x01000000
    326       1.1  jmcneill #define	MAC_CFG_ALLMULTI		0x02000000
    327       1.1  jmcneill #define	MAC_CFG_BCAST			0x04000000
    328       1.1  jmcneill #define	MAC_CFG_DBG			0x08000000
    329       1.1  jmcneill #define	MAC_CFG_SINGLE_PAUSE_ENB	0x10000000
    330       1.2  jmcneill #define	MAC_CFG_HASH_ALG_CRC32		0x20000000
    331       1.2  jmcneill #define	MAC_CFG_SPEED_MODE_SW		0x40000000
    332       1.3  christos #define	MAC_CFG_FAST_PAUSE		0x80000000
    333       1.1  jmcneill #define	MAC_CFG_PREAMBLE_SHIFT		10
    334       1.1  jmcneill #define	MAC_CFG_PREAMBLE_DEFAULT	7
    335       1.1  jmcneill 
    336       1.1  jmcneill #define	ALC_IPG_IFG_CFG			0x1484
    337       1.1  jmcneill #define	IPG_IFG_IPGT_MASK		0x0000007F
    338       1.1  jmcneill #define	IPG_IFG_MIFG_MASK		0x0000FF00
    339       1.1  jmcneill #define	IPG_IFG_IPG1_MASK		0x007F0000
    340       1.1  jmcneill #define	IPG_IFG_IPG2_MASK		0x7F000000
    341       1.1  jmcneill #define	IPG_IFG_IPGT_SHIFT		0
    342       1.1  jmcneill #define	IPG_IFG_IPGT_DEFAULT		0x60
    343       1.1  jmcneill #define	IPG_IFG_MIFG_SHIFT		8
    344       1.1  jmcneill #define	IPG_IFG_MIFG_DEFAULT		0x50
    345       1.1  jmcneill #define	IPG_IFG_IPG1_SHIFT		16
    346       1.1  jmcneill #define	IPG_IFG_IPG1_DEFAULT		0x40
    347       1.1  jmcneill #define	IPG_IFG_IPG2_SHIFT		24
    348       1.1  jmcneill #define	IPG_IFG_IPG2_DEFAULT		0x60
    349       1.1  jmcneill 
    350       1.1  jmcneill /* Station address. */
    351       1.1  jmcneill #define	ALC_PAR0			0x1488
    352       1.1  jmcneill #define	ALC_PAR1			0x148C
    353       1.1  jmcneill 
    354       1.1  jmcneill /* 64bit multicast hash register. */
    355       1.1  jmcneill #define	ALC_MAR0			0x1490
    356       1.1  jmcneill #define	ALC_MAR1			0x1494
    357       1.1  jmcneill 
    358       1.1  jmcneill /* half-duplex parameter configuration. */
    359       1.1  jmcneill #define	ALC_HDPX_CFG			0x1498
    360       1.1  jmcneill #define	HDPX_CFG_LCOL_MASK		0x000003FF
    361       1.1  jmcneill #define	HDPX_CFG_RETRY_MASK		0x0000F000
    362       1.1  jmcneill #define	HDPX_CFG_EXC_DEF_EN		0x00010000
    363       1.1  jmcneill #define	HDPX_CFG_NO_BACK_C		0x00020000
    364       1.1  jmcneill #define	HDPX_CFG_NO_BACK_P		0x00040000
    365       1.1  jmcneill #define	HDPX_CFG_ABEBE			0x00080000
    366       1.1  jmcneill #define	HDPX_CFG_ABEBT_MASK		0x00F00000
    367       1.1  jmcneill #define	HDPX_CFG_JAMIPG_MASK		0x0F000000
    368       1.1  jmcneill #define	HDPX_CFG_LCOL_SHIFT		0
    369       1.1  jmcneill #define	HDPX_CFG_LCOL_DEFAULT		0x37
    370       1.1  jmcneill #define	HDPX_CFG_RETRY_SHIFT		12
    371       1.1  jmcneill #define	HDPX_CFG_RETRY_DEFAULT		0x0F
    372       1.1  jmcneill #define	HDPX_CFG_ABEBT_SHIFT		20
    373       1.1  jmcneill #define	HDPX_CFG_ABEBT_DEFAULT		0x0A
    374       1.1  jmcneill #define	HDPX_CFG_JAMIPG_SHIFT		24
    375       1.1  jmcneill #define	HDPX_CFG_JAMIPG_DEFAULT		0x07
    376       1.1  jmcneill 
    377       1.1  jmcneill #define	ALC_FRAME_SIZE			0x149C
    378       1.1  jmcneill 
    379       1.1  jmcneill #define	ALC_WOL_CFG			0x14A0
    380       1.1  jmcneill #define	WOL_CFG_PATTERN			0x00000001
    381       1.1  jmcneill #define	WOL_CFG_PATTERN_ENB		0x00000002
    382       1.1  jmcneill #define	WOL_CFG_MAGIC			0x00000004
    383       1.1  jmcneill #define	WOL_CFG_MAGIC_ENB		0x00000008
    384       1.1  jmcneill #define	WOL_CFG_LINK_CHG		0x00000010
    385       1.1  jmcneill #define	WOL_CFG_LINK_CHG_ENB		0x00000020
    386       1.1  jmcneill #define	WOL_CFG_PATTERN_DET		0x00000100
    387       1.1  jmcneill #define	WOL_CFG_MAGIC_DET		0x00000200
    388       1.1  jmcneill #define	WOL_CFG_LINK_CHG_DET		0x00000400
    389       1.1  jmcneill #define	WOL_CFG_CLK_SWITCH_ENB		0x00008000
    390       1.1  jmcneill #define	WOL_CFG_PATTERN0		0x00010000
    391       1.1  jmcneill #define	WOL_CFG_PATTERN1		0x00020000
    392       1.1  jmcneill #define	WOL_CFG_PATTERN2		0x00040000
    393       1.1  jmcneill #define	WOL_CFG_PATTERN3		0x00080000
    394       1.1  jmcneill #define	WOL_CFG_PATTERN4		0x00100000
    395       1.1  jmcneill #define	WOL_CFG_PATTERN5		0x00200000
    396       1.1  jmcneill #define	WOL_CFG_PATTERN6		0x00400000
    397       1.1  jmcneill 
    398       1.1  jmcneill /* WOL pattern length. */
    399       1.1  jmcneill #define	ALC_PATTERN_CFG0		0x14A4
    400       1.1  jmcneill #define	PATTERN_CFG_0_LEN_MASK		0x0000007F
    401       1.1  jmcneill #define	PATTERN_CFG_1_LEN_MASK		0x00007F00
    402       1.1  jmcneill #define	PATTERN_CFG_2_LEN_MASK		0x007F0000
    403       1.1  jmcneill #define	PATTERN_CFG_3_LEN_MASK		0x7F000000
    404       1.1  jmcneill 
    405       1.1  jmcneill #define	ALC_PATTERN_CFG1		0x14A8
    406       1.1  jmcneill #define	PATTERN_CFG_4_LEN_MASK		0x0000007F
    407       1.1  jmcneill #define	PATTERN_CFG_5_LEN_MASK		0x00007F00
    408       1.1  jmcneill #define	PATTERN_CFG_6_LEN_MASK		0x007F0000
    409       1.1  jmcneill 
    410       1.1  jmcneill /* RSS */
    411       1.1  jmcneill #define	ALC_RSS_KEY0			0x14B0
    412       1.1  jmcneill 
    413       1.1  jmcneill #define	ALC_RSS_KEY1			0x14B4
    414       1.1  jmcneill 
    415       1.1  jmcneill #define	ALC_RSS_KEY2			0x14B8
    416       1.1  jmcneill 
    417       1.1  jmcneill #define	ALC_RSS_KEY3			0x14BC
    418       1.1  jmcneill 
    419       1.1  jmcneill #define	ALC_RSS_KEY4			0x14C0
    420       1.1  jmcneill 
    421       1.1  jmcneill #define	ALC_RSS_KEY5			0x14C4
    422       1.1  jmcneill 
    423       1.1  jmcneill #define	ALC_RSS_KEY6			0x14C8
    424       1.1  jmcneill 
    425       1.1  jmcneill #define	ALC_RSS_KEY7			0x14CC
    426       1.1  jmcneill 
    427       1.1  jmcneill #define	ALC_RSS_KEY8			0x14D0
    428       1.1  jmcneill 
    429       1.1  jmcneill #define	ALC_RSS_KEY9			0x14D4
    430       1.1  jmcneill 
    431       1.1  jmcneill #define	ALC_RSS_IDT_TABLE0		0x14E0
    432       1.1  jmcneill 
    433       1.3  christos #define	ALC_TD_PRI2_HEAD_ADDR_LO	0x14E0	/* AR816x */
    434       1.3  christos 
    435       1.1  jmcneill #define	ALC_RSS_IDT_TABLE1		0x14E4
    436       1.1  jmcneill 
    437       1.3  christos #define	ALC_TD_PRI3_HEAD_ADDR_LO	0x14E4	/* AR816x */
    438       1.3  christos 
    439       1.1  jmcneill #define	ALC_RSS_IDT_TABLE2		0x14E8
    440       1.1  jmcneill 
    441       1.1  jmcneill #define	ALC_RSS_IDT_TABLE3		0x14EC
    442       1.1  jmcneill 
    443       1.1  jmcneill #define	ALC_RSS_IDT_TABLE4		0x14F0
    444       1.1  jmcneill 
    445       1.1  jmcneill #define	ALC_RSS_IDT_TABLE5		0x14F4
    446       1.1  jmcneill 
    447       1.1  jmcneill #define	ALC_RSS_IDT_TABLE6		0x14F8
    448       1.1  jmcneill 
    449       1.1  jmcneill #define	ALC_RSS_IDT_TABLE7		0x14FC
    450       1.1  jmcneill 
    451       1.1  jmcneill #define	ALC_SRAM_RD0_ADDR		0x1500
    452       1.1  jmcneill 
    453       1.1  jmcneill #define	ALC_SRAM_RD1_ADDR		0x1504
    454       1.1  jmcneill 
    455       1.1  jmcneill #define	ALC_SRAM_RD2_ADDR		0x1508
    456       1.1  jmcneill 
    457       1.1  jmcneill #define	ALC_SRAM_RD3_ADDR		0x150C
    458       1.1  jmcneill 
    459       1.1  jmcneill #define	RD_HEAD_ADDR_MASK		0x000003FF
    460       1.1  jmcneill #define	RD_TAIL_ADDR_MASK		0x03FF0000
    461       1.1  jmcneill #define	RD_HEAD_ADDR_SHIFT		0
    462       1.1  jmcneill #define	RD_TAIL_ADDR_SHIFT		16
    463       1.1  jmcneill 
    464       1.1  jmcneill #define	ALC_RD_NIC_LEN0			0x1510	/* 8 bytes unit */
    465       1.1  jmcneill #define	RD_NIC_LEN_MASK			0x000003FF
    466       1.1  jmcneill 
    467       1.1  jmcneill #define	ALC_RD_NIC_LEN1			0x1514
    468       1.1  jmcneill 
    469       1.1  jmcneill #define	ALC_SRAM_TD_ADDR		0x1518
    470       1.1  jmcneill #define	TD_HEAD_ADDR_MASK		0x000003FF
    471       1.1  jmcneill #define	TD_TAIL_ADDR_MASK		0x03FF0000
    472       1.1  jmcneill #define	TD_HEAD_ADDR_SHIFT		0
    473       1.1  jmcneill #define	TD_TAIL_ADDR_SHIFT		16
    474       1.1  jmcneill 
    475       1.1  jmcneill #define	ALC_SRAM_TD_LEN			0x151C	/* 8 bytes unit */
    476       1.1  jmcneill #define	SRAM_TD_LEN_MASK		0x000003FF
    477       1.1  jmcneill 
    478       1.1  jmcneill #define	ALC_SRAM_RX_FIFO_ADDR		0x1520
    479       1.1  jmcneill 
    480       1.1  jmcneill #define	ALC_SRAM_RX_FIFO_LEN		0x1524
    481       1.3  christos #define	SRAM_RX_FIFO_LEN_MASK		0x00000FFF
    482       1.3  christos #define	SRAM_RX_FIFO_LEN_SHIFT		0
    483       1.3  christos 
    484       1.1  jmcneill #define	ALC_SRAM_TX_FIFO_ADDR		0x1528
    485       1.1  jmcneill 
    486       1.1  jmcneill #define	ALC_SRAM_TX_FIFO_LEN		0x152C
    487       1.1  jmcneill 
    488       1.1  jmcneill #define	ALC_SRAM_TCPH_ADDR		0x1530
    489       1.1  jmcneill #define	SRAM_TCPH_ADDR_MASK		0x00000FFF
    490       1.1  jmcneill #define	SRAM_PATH_ADDR_MASK		0x0FFF0000
    491       1.1  jmcneill #define	SRAM_TCPH_ADDR_SHIFT		0
    492       1.1  jmcneill #define	SRAM_PKTH_ADDR_SHIFT		16
    493       1.1  jmcneill 
    494       1.1  jmcneill #define	ALC_DMA_BLOCK			0x1534
    495       1.1  jmcneill #define	DMA_BLOCK_LOAD			0x00000001
    496       1.1  jmcneill 
    497       1.1  jmcneill #define	ALC_RX_BASE_ADDR_HI		0x1540
    498       1.1  jmcneill 
    499       1.1  jmcneill #define	ALC_TX_BASE_ADDR_HI		0x1544
    500       1.1  jmcneill 
    501       1.1  jmcneill #define	ALC_SMB_BASE_ADDR_HI		0x1548
    502       1.1  jmcneill 
    503       1.1  jmcneill #define	ALC_SMB_BASE_ADDR_LO		0x154C
    504       1.1  jmcneill 
    505       1.1  jmcneill #define	ALC_RD0_HEAD_ADDR_LO		0x1550
    506       1.1  jmcneill 
    507       1.1  jmcneill #define	ALC_RD1_HEAD_ADDR_LO		0x1554
    508       1.1  jmcneill 
    509       1.1  jmcneill #define	ALC_RD2_HEAD_ADDR_LO		0x1558
    510       1.1  jmcneill 
    511       1.1  jmcneill #define	ALC_RD3_HEAD_ADDR_LO		0x155C
    512       1.1  jmcneill 
    513       1.1  jmcneill #define	ALC_RD_RING_CNT			0x1560
    514       1.1  jmcneill #define	RD_RING_CNT_MASK		0x00000FFF
    515       1.1  jmcneill #define	RD_RING_CNT_SHIFT		0
    516       1.1  jmcneill 
    517       1.1  jmcneill #define	ALC_RX_BUF_SIZE			0x1564
    518       1.1  jmcneill #define	RX_BUF_SIZE_MASK		0x0000FFFF
    519       1.1  jmcneill /*
    520       1.1  jmcneill  * If larger buffer size than 1536 is specified the controller
    521       1.1  jmcneill  * will be locked up. This is hardware limitation.
    522       1.1  jmcneill  */
    523       1.1  jmcneill #define	RX_BUF_SIZE_MAX			1536
    524       1.1  jmcneill 
    525       1.1  jmcneill #define	ALC_RRD0_HEAD_ADDR_LO		0x1568
    526       1.1  jmcneill 
    527       1.1  jmcneill #define	ALC_RRD1_HEAD_ADDR_LO		0x156C
    528       1.1  jmcneill 
    529       1.1  jmcneill #define	ALC_RRD2_HEAD_ADDR_LO		0x1570
    530       1.1  jmcneill 
    531       1.1  jmcneill #define	ALC_RRD3_HEAD_ADDR_LO		0x1574
    532       1.1  jmcneill 
    533       1.1  jmcneill #define	ALC_RRD_RING_CNT		0x1578
    534       1.1  jmcneill #define	RRD_RING_CNT_MASK		0x00000FFF
    535       1.1  jmcneill #define	RRD_RING_CNT_SHIFT		0
    536       1.1  jmcneill 
    537       1.1  jmcneill #define	ALC_TDH_HEAD_ADDR_LO		0x157C
    538       1.1  jmcneill 
    539       1.3  christos #define	ALC_TD_PRI1_HEAD_ADDR_LO	0x157C	/* AR816x */
    540       1.3  christos 
    541       1.1  jmcneill #define	ALC_TDL_HEAD_ADDR_LO		0x1580
    542       1.1  jmcneill 
    543       1.3  christos #define	ALC_TD_PRI0_HEAD_ADDR_LO	0x1580	/* AR816x */
    544       1.3  christos 
    545       1.1  jmcneill #define	ALC_TD_RING_CNT			0x1584
    546       1.1  jmcneill #define	TD_RING_CNT_MASK		0x0000FFFF
    547       1.1  jmcneill #define	TD_RING_CNT_SHIFT		0
    548       1.1  jmcneill 
    549       1.1  jmcneill #define	ALC_CMB_BASE_ADDR_LO		0x1588
    550       1.1  jmcneill 
    551       1.1  jmcneill #define	ALC_TXQ_CFG			0x1590
    552       1.1  jmcneill #define	TXQ_CFG_TD_BURST_MASK		0x0000000F
    553       1.1  jmcneill #define	TXQ_CFG_IP_OPTION_ENB		0x00000010
    554       1.1  jmcneill #define	TXQ_CFG_ENB			0x00000020
    555       1.1  jmcneill #define	TXQ_CFG_ENHANCED_MODE		0x00000040
    556       1.1  jmcneill #define	TXQ_CFG_8023_ENB		0x00000080
    557       1.1  jmcneill #define	TXQ_CFG_TX_FIFO_BURST_MASK	0xFFFF0000
    558       1.1  jmcneill #define	TXQ_CFG_TD_BURST_SHIFT		0
    559       1.1  jmcneill #define	TXQ_CFG_TD_BURST_DEFAULT	5
    560       1.1  jmcneill #define	TXQ_CFG_TX_FIFO_BURST_SHIFT	16
    561       1.1  jmcneill 
    562       1.1  jmcneill #define	ALC_TSO_OFFLOAD_THRESH		0x1594	/* 8 bytes unit */
    563       1.1  jmcneill #define	TSO_OFFLOAD_THRESH_MASK		0x000007FF
    564       1.3  christos #define	TSO_OFFLOAD_ERRLGPKT_DROP_ENB	0x00000800
    565       1.1  jmcneill #define	TSO_OFFLOAD_THRESH_SHIFT	0
    566       1.1  jmcneill #define	TSO_OFFLOAD_THRESH_UNIT		8
    567       1.1  jmcneill #define	TSO_OFFLOAD_THRESH_UNIT_SHIFT	3
    568       1.1  jmcneill 
    569       1.1  jmcneill #define	ALC_TXF_WATER_MARK		0x1598	/* 8 bytes unit */
    570       1.1  jmcneill #define	TXF_WATER_MARK_HI_MASK		0x00000FFF
    571       1.1  jmcneill #define	TXF_WATER_MARK_LO_MASK		0x0FFF0000
    572       1.1  jmcneill #define	TXF_WATER_MARK_BURST_ENB	0x80000000
    573       1.1  jmcneill #define	TXF_WATER_MARK_LO_SHIFT		0
    574       1.1  jmcneill #define	TXF_WATER_MARK_HI_SHIFT		16
    575       1.1  jmcneill 
    576       1.1  jmcneill #define	ALC_THROUGHPUT_MON		0x159C
    577       1.1  jmcneill #define	THROUGHPUT_MON_RATE_MASK	0x00000003
    578       1.1  jmcneill #define	THROUGHPUT_MON_ENB		0x00000080
    579       1.1  jmcneill #define	THROUGHPUT_MON_RATE_SHIFT	0
    580       1.1  jmcneill 
    581       1.1  jmcneill #define	ALC_RXQ_CFG			0x15A0
    582       1.1  jmcneill #define	RXQ_CFG_ASPM_THROUGHPUT_LIMIT_MASK	0x00000003
    583       1.1  jmcneill #define	RXQ_CFG_ASPM_THROUGHPUT_LIMIT_NONE	0x00000000
    584       1.1  jmcneill #define	RXQ_CFG_ASPM_THROUGHPUT_LIMIT_1M	0x00000001
    585       1.1  jmcneill #define	RXQ_CFG_ASPM_THROUGHPUT_LIMIT_10M	0x00000002
    586       1.1  jmcneill #define	RXQ_CFG_ASPM_THROUGHPUT_LIMIT_100M	0x00000003
    587       1.1  jmcneill #define	RXQ_CFG_QUEUE1_ENB		0x00000010
    588       1.1  jmcneill #define	RXQ_CFG_QUEUE2_ENB		0x00000020
    589       1.1  jmcneill #define	RXQ_CFG_QUEUE3_ENB		0x00000040
    590       1.1  jmcneill #define	RXQ_CFG_IPV6_CSUM_ENB		0x00000080
    591       1.1  jmcneill #define	RXQ_CFG_RSS_HASH_TBL_LEN_MASK	0x0000FF00
    592       1.1  jmcneill #define	RXQ_CFG_RSS_HASH_IPV4		0x00010000
    593       1.1  jmcneill #define	RXQ_CFG_RSS_HASH_IPV4_TCP	0x00020000
    594       1.1  jmcneill #define	RXQ_CFG_RSS_HASH_IPV6		0x00040000
    595       1.1  jmcneill #define	RXQ_CFG_RSS_HASH_IPV6_TCP	0x00080000
    596       1.1  jmcneill #define	RXQ_CFG_RD_BURST_MASK		0x03F00000
    597       1.1  jmcneill #define	RXQ_CFG_RSS_MODE_DIS		0x00000000
    598       1.1  jmcneill #define	RXQ_CFG_RSS_MODE_SQSINT		0x04000000
    599       1.1  jmcneill #define	RXQ_CFG_RSS_MODE_MQUESINT	0x08000000
    600       1.1  jmcneill #define	RXQ_CFG_RSS_MODE_MQUEMINT	0x0C000000
    601       1.1  jmcneill #define	RXQ_CFG_NIP_QUEUE_SEL_TBL	0x10000000
    602       1.1  jmcneill #define	RXQ_CFG_RSS_HASH_ENB		0x20000000
    603       1.1  jmcneill #define	RXQ_CFG_CUT_THROUGH_ENB		0x40000000
    604       1.1  jmcneill #define	RXQ_CFG_QUEUE0_ENB		0x80000000
    605       1.1  jmcneill #define	RXQ_CFG_RSS_HASH_TBL_LEN_SHIFT	8
    606       1.1  jmcneill #define	RXQ_CFG_RD_BURST_DEFAULT	8
    607       1.1  jmcneill #define	RXQ_CFG_RD_BURST_SHIFT		20
    608       1.1  jmcneill #define	RXQ_CFG_ENB					\
    609       1.1  jmcneill 	(RXQ_CFG_QUEUE0_ENB | RXQ_CFG_QUEUE1_ENB |	\
    610       1.1  jmcneill 	 RXQ_CFG_QUEUE2_ENB | RXQ_CFG_QUEUE3_ENB)
    611       1.1  jmcneill 
    612       1.3  christos /* AR816x specific bits */
    613       1.3  christos #define	RXQ_CFG_816X_RSS_HASH_IPV4	0x00000004
    614       1.3  christos #define	RXQ_CFG_816X_RSS_HASH_IPV4_TCP	0x00000008
    615       1.3  christos #define	RXQ_CFG_816X_RSS_HASH_IPV6	0x00000010
    616       1.3  christos #define	RXQ_CFG_816X_RSS_HASH_IPV6_TCP	0x00000020
    617       1.3  christos #define	RXQ_CFG_816X_RSS_HASH_MASK	0x0000003C
    618       1.3  christos #define	RXQ_CFG_816X_IPV6_PARSE_ENB	0x00000080
    619       1.3  christos #define	RXQ_CFG_816X_IDT_TBL_SIZE_MASK	0x0001FF00
    620       1.3  christos #define	RXQ_CFG_816X_IDT_TBL_SIZE_SHIFT	8
    621       1.3  christos #define	RXQ_CFG_816X_IDT_TBL_SIZE_DEFAULT	0x100
    622       1.3  christos 
    623       1.1  jmcneill #define	ALC_RX_RD_FREE_THRESH		0x15A4	/* 8 bytes unit. */
    624       1.1  jmcneill #define	RX_RD_FREE_THRESH_HI_MASK	0x0000003F
    625       1.1  jmcneill #define	RX_RD_FREE_THRESH_LO_MASK	0x00000FC0
    626       1.1  jmcneill #define	RX_RD_FREE_THRESH_HI_SHIFT	0
    627       1.1  jmcneill #define	RX_RD_FREE_THRESH_LO_SHIFT	6
    628       1.1  jmcneill #define	RX_RD_FREE_THRESH_HI_DEFAULT	16
    629       1.1  jmcneill #define	RX_RD_FREE_THRESH_LO_DEFAULT	8
    630       1.1  jmcneill 
    631       1.1  jmcneill #define	ALC_RX_FIFO_PAUSE_THRESH	0x15A8
    632       1.1  jmcneill #define	RX_FIFO_PAUSE_THRESH_LO_MASK	0x00000FFF
    633       1.1  jmcneill #define	RX_FIFO_PAUSE_THRESH_HI_MASK	0x0FFF0000
    634       1.1  jmcneill #define	RX_FIFO_PAUSE_THRESH_LO_SHIFT	0
    635       1.1  jmcneill #define	RX_FIFO_PAUSE_THRESH_HI_SHIFT	16
    636       1.3  christos /*
    637       1.3  christos  * Size = tx-packet(1522) + IPG(12) + SOF(8) + 64(Pause) + IPG(12) + SOF(8) +
    638       1.3  christos  *	  rx-packet(1522) + delay-of-link(64)
    639       1.3  christos  *	= 3212.
    640       1.3  christos  */
    641       1.3  christos #define	RX_FIFO_PAUSE_816X_RSVD		3212
    642       1.3  christos 
    643       1.1  jmcneill #define	ALC_RD_DMA_CFG			0x15AC
    644       1.1  jmcneill #define	RD_DMA_CFG_THRESH_MASK		0x00000FFF	/* 8 bytes unit */
    645       1.1  jmcneill #define	RD_DMA_CFG_TIMER_MASK		0xFFFF0000
    646       1.1  jmcneill #define	RD_DMA_CFG_THRESH_SHIFT		0
    647       1.1  jmcneill #define	RD_DMA_CFG_TIMER_SHIFT		16
    648       1.1  jmcneill #define	RD_DMA_CFG_THRESH_DEFAULT	0x100
    649       1.1  jmcneill #define	RD_DMA_CFG_TIMER_DEFAULT	0
    650       1.1  jmcneill #define	RD_DMA_CFG_TICK_USECS		8
    651       1.1  jmcneill #define	ALC_RD_DMA_CFG_USECS(x)		((x) / RD_DMA_CFG_TICK_USECS)
    652       1.1  jmcneill 
    653       1.1  jmcneill #define	ALC_RSS_HASH_VALUE		0x15B0
    654       1.1  jmcneill 
    655       1.1  jmcneill #define	ALC_RSS_HASH_FLAG		0x15B4
    656       1.1  jmcneill 
    657       1.1  jmcneill #define	ALC_RSS_CPU			0x15B8
    658       1.1  jmcneill 
    659       1.1  jmcneill #define	ALC_DMA_CFG			0x15C0
    660       1.1  jmcneill #define	DMA_CFG_IN_ORDER		0x00000001
    661       1.1  jmcneill #define	DMA_CFG_ENH_ORDER		0x00000002
    662       1.1  jmcneill #define	DMA_CFG_OUT_ORDER		0x00000004
    663       1.1  jmcneill #define	DMA_CFG_RCB_64			0x00000000
    664       1.1  jmcneill #define	DMA_CFG_RCB_128			0x00000008
    665       1.3  christos #define	DMA_CFG_PEND_AUTO_RST		0x00000008
    666       1.1  jmcneill #define	DMA_CFG_RD_BURST_128		0x00000000
    667       1.1  jmcneill #define	DMA_CFG_RD_BURST_256		0x00000010
    668       1.1  jmcneill #define	DMA_CFG_RD_BURST_512		0x00000020
    669       1.1  jmcneill #define	DMA_CFG_RD_BURST_1024		0x00000030
    670       1.1  jmcneill #define	DMA_CFG_RD_BURST_2048		0x00000040
    671       1.1  jmcneill #define	DMA_CFG_RD_BURST_4096		0x00000050
    672       1.1  jmcneill #define	DMA_CFG_WR_BURST_128		0x00000000
    673       1.1  jmcneill #define	DMA_CFG_WR_BURST_256		0x00000080
    674       1.1  jmcneill #define	DMA_CFG_WR_BURST_512		0x00000100
    675       1.1  jmcneill #define	DMA_CFG_WR_BURST_1024		0x00000180
    676       1.1  jmcneill #define	DMA_CFG_WR_BURST_2048		0x00000200
    677       1.1  jmcneill #define	DMA_CFG_WR_BURST_4096		0x00000280
    678       1.1  jmcneill #define	DMA_CFG_RD_REQ_PRI		0x00000400
    679       1.1  jmcneill #define	DMA_CFG_RD_DELAY_CNT_MASK	0x0000F800
    680       1.1  jmcneill #define	DMA_CFG_WR_DELAY_CNT_MASK	0x000F0000
    681       1.1  jmcneill #define	DMA_CFG_CMB_ENB			0x00100000
    682       1.1  jmcneill #define	DMA_CFG_SMB_ENB			0x00200000
    683       1.1  jmcneill #define	DMA_CFG_CMB_NOW			0x00400000
    684       1.1  jmcneill #define	DMA_CFG_SMB_DIS			0x01000000
    685       1.3  christos #define	DMA_CFG_RD_CHNL_SEL_MASK	0x0C000000
    686       1.3  christos #define	DMA_CFG_RD_CHNL_SEL_1		0x00000000
    687       1.3  christos #define	DMA_CFG_RD_CHNL_SEL_2		0x04000000
    688       1.3  christos #define	DMA_CFG_RD_CHNL_SEL_3		0x08000000
    689       1.3  christos #define	DMA_CFG_RD_CHNL_SEL_4		0x0C000000
    690       1.3  christos #define	DMA_CFG_WSRAM_RDCTL		0x10000000
    691       1.3  christos #define	DMA_CFG_RD_PEND_CLR		0x20000000
    692       1.3  christos #define	DMA_CFG_WR_PEND_CLR		0x40000000
    693       1.1  jmcneill #define	DMA_CFG_SMB_NOW			0x80000000
    694       1.1  jmcneill #define	DMA_CFG_RD_BURST_MASK		0x07
    695       1.1  jmcneill #define	DMA_CFG_RD_BURST_SHIFT		4
    696       1.1  jmcneill #define	DMA_CFG_WR_BURST_MASK		0x07
    697       1.1  jmcneill #define	DMA_CFG_WR_BURST_SHIFT		7
    698       1.1  jmcneill #define	DMA_CFG_RD_DELAY_CNT_SHIFT	11
    699       1.1  jmcneill #define	DMA_CFG_WR_DELAY_CNT_SHIFT	16
    700       1.1  jmcneill #define	DMA_CFG_RD_DELAY_CNT_DEFAULT	15
    701       1.1  jmcneill #define	DMA_CFG_WR_DELAY_CNT_DEFAULT	4
    702       1.1  jmcneill 
    703       1.1  jmcneill #define	ALC_SMB_STAT_TIMER		0x15C4
    704       1.1  jmcneill #define	SMB_STAT_TIMER_MASK		0x00FFFFFF
    705       1.1  jmcneill #define	SMB_STAT_TIMER_SHIFT		0
    706       1.1  jmcneill 
    707       1.1  jmcneill #define	ALC_CMB_TD_THRESH		0x15C8
    708       1.1  jmcneill #define	CMB_TD_THRESH_MASK		0x0000FFFF
    709       1.1  jmcneill #define	CMB_TD_THRESH_SHIFT		0
    710       1.1  jmcneill 
    711       1.1  jmcneill #define	ALC_CMB_TX_TIMER		0x15CC
    712       1.1  jmcneill #define	CMB_TX_TIMER_MASK		0x0000FFFF
    713       1.1  jmcneill #define	CMB_TX_TIMER_SHIFT		0
    714       1.1  jmcneill 
    715       1.3  christos #define	ALC_MSI_MAP_TBL1		0x15D0
    716       1.3  christos 
    717       1.3  christos #define	ALC_MSI_ID_MAP			0x15D4
    718       1.3  christos 
    719       1.3  christos #define	ALC_MSI_MAP_TBL2		0x15D8
    720       1.3  christos 
    721       1.1  jmcneill #define	ALC_MBOX_RD0_PROD_IDX		0x15E0
    722       1.1  jmcneill 
    723       1.1  jmcneill #define	ALC_MBOX_RD1_PROD_IDX		0x15E4
    724       1.1  jmcneill 
    725       1.1  jmcneill #define	ALC_MBOX_RD2_PROD_IDX		0x15E8
    726       1.1  jmcneill 
    727       1.1  jmcneill #define	ALC_MBOX_RD3_PROD_IDX		0x15EC
    728       1.1  jmcneill 
    729       1.1  jmcneill #define	ALC_MBOX_RD_PROD_MASK		0x0000FFFF
    730       1.1  jmcneill #define	MBOX_RD_PROD_SHIFT		0
    731       1.1  jmcneill 
    732       1.1  jmcneill #define	ALC_MBOX_TD_PROD_IDX		0x15F0
    733       1.1  jmcneill #define	MBOX_TD_PROD_HI_IDX_MASK	0x0000FFFF
    734       1.1  jmcneill #define	MBOX_TD_PROD_LO_IDX_MASK	0xFFFF0000
    735       1.1  jmcneill #define	MBOX_TD_PROD_HI_IDX_SHIFT	0
    736       1.1  jmcneill #define	MBOX_TD_PROD_LO_IDX_SHIFT	16
    737       1.1  jmcneill 
    738       1.3  christos #define	ALC_MBOX_TD_PRI1_PROD_IDX	0x15F0	/* 16 bits AR816x */
    739       1.3  christos 
    740       1.3  christos #define	ALC_MBOX_TD_PRI0_PROD_IDX	0x15F2	/* 16 bits AR816x */
    741       1.3  christos 
    742       1.1  jmcneill #define	ALC_MBOX_TD_CONS_IDX		0x15F4
    743       1.1  jmcneill #define	MBOX_TD_CONS_HI_IDX_MASK	0x0000FFFF
    744       1.1  jmcneill #define	MBOX_TD_CONS_LO_IDX_MASK	0xFFFF0000
    745       1.1  jmcneill #define	MBOX_TD_CONS_HI_IDX_SHIFT	0
    746       1.1  jmcneill #define	MBOX_TD_CONS_LO_IDX_SHIFT	16
    747       1.1  jmcneill 
    748       1.3  christos #define	ALC_MBOX_TD_PRI1_CONS_IDX	0x15F4	/* 16 bits AR816x */
    749       1.3  christos 
    750       1.3  christos #define	ALC_MBOX_TD_PRI0_CONS_IDX	0x15F6	/* 16 bits AR816x */
    751       1.3  christos 
    752       1.1  jmcneill #define	ALC_MBOX_RD01_CONS_IDX		0x15F8
    753       1.1  jmcneill #define	MBOX_RD0_CONS_IDX_MASK		0x0000FFFF
    754       1.1  jmcneill #define	MBOX_RD1_CONS_IDX_MASK		0xFFFF0000
    755       1.1  jmcneill #define	MBOX_RD0_CONS_IDX_SHIFT		0
    756       1.1  jmcneill #define	MBOX_RD1_CONS_IDX_SHIFT		16
    757       1.1  jmcneill 
    758       1.1  jmcneill #define	ALC_MBOX_RD23_CONS_IDX		0x15FC
    759       1.1  jmcneill #define	MBOX_RD2_CONS_IDX_MASK		0x0000FFFF
    760       1.1  jmcneill #define	MBOX_RD3_CONS_IDX_MASK		0xFFFF0000
    761       1.1  jmcneill #define	MBOX_RD2_CONS_IDX_SHIFT		0
    762       1.1  jmcneill #define	MBOX_RD3_CONS_IDX_SHIFT		16
    763       1.1  jmcneill 
    764       1.1  jmcneill #define	ALC_INTR_STATUS			0x1600
    765       1.1  jmcneill #define	INTR_SMB			0x00000001
    766       1.1  jmcneill #define	INTR_TIMER			0x00000002
    767       1.1  jmcneill #define	INTR_MANUAL_TIMER		0x00000004
    768       1.1  jmcneill #define	INTR_RX_FIFO_OFLOW		0x00000008
    769       1.1  jmcneill #define	INTR_RD0_UNDERRUN		0x00000010
    770       1.1  jmcneill #define	INTR_RD1_UNDERRUN		0x00000020
    771       1.1  jmcneill #define	INTR_RD2_UNDERRUN		0x00000040
    772       1.1  jmcneill #define	INTR_RD3_UNDERRUN		0x00000080
    773       1.1  jmcneill #define	INTR_TX_FIFO_UNDERRUN		0x00000100
    774       1.1  jmcneill #define	INTR_DMA_RD_TO_RST		0x00000200
    775       1.1  jmcneill #define	INTR_DMA_WR_TO_RST		0x00000400
    776       1.1  jmcneill #define	INTR_TX_CREDIT			0x00000800
    777       1.1  jmcneill #define	INTR_GPHY			0x00001000
    778       1.1  jmcneill #define	INTR_GPHY_LOW_PW		0x00002000
    779       1.1  jmcneill #define	INTR_TXQ_TO_RST			0x00004000
    780       1.3  christos #define	INTR_TX_PKT0			0x00008000
    781       1.1  jmcneill #define	INTR_RX_PKT0			0x00010000
    782       1.1  jmcneill #define	INTR_RX_PKT1			0x00020000
    783       1.1  jmcneill #define	INTR_RX_PKT2			0x00040000
    784       1.1  jmcneill #define	INTR_RX_PKT3			0x00080000
    785       1.1  jmcneill #define	INTR_MAC_RX			0x00100000
    786       1.1  jmcneill #define	INTR_MAC_TX			0x00200000
    787       1.1  jmcneill #define	INTR_UNDERRUN			0x00400000
    788       1.1  jmcneill #define	INTR_FRAME_ERROR		0x00800000
    789       1.1  jmcneill #define	INTR_FRAME_OK			0x01000000
    790       1.1  jmcneill #define	INTR_CSUM_ERROR			0x02000000
    791       1.1  jmcneill #define	INTR_PHY_LINK_DOWN		0x04000000
    792       1.1  jmcneill #define	INTR_DIS_INT			0x80000000
    793       1.1  jmcneill 
    794       1.3  christos /* INTR status for AR816x/AR817x  4 TX queues, 8 RX queues */
    795       1.3  christos #define	INTR_TX_PKT1			0x00000020
    796       1.3  christos #define	INTR_TX_PKT2			0x00000040
    797       1.3  christos #define	INTR_TX_PKT3			0x00000080
    798       1.3  christos #define	INTR_RX_PKT4			0x08000000
    799       1.3  christos #define	INTR_RX_PKT5			0x10000000
    800       1.3  christos #define	INTR_RX_PKT6			0x20000000
    801       1.3  christos #define	INTR_RX_PKT7			0x40000000
    802       1.3  christos 
    803       1.1  jmcneill /* Interrupt Mask Register */
    804       1.1  jmcneill #define	ALC_INTR_MASK			0x1604
    805       1.1  jmcneill 
    806       1.1  jmcneill #ifdef	notyet
    807       1.1  jmcneill #define	INTR_RX_PKT					\
    808       1.1  jmcneill 	(INTR_RX_PKT0 | INTR_RX_PKT1 | INTR_RX_PKT2 |	\
    809       1.1  jmcneill 	 INTR_RX_PKT3)
    810       1.1  jmcneill #define	INTR_RD_UNDERRUN				\
    811       1.1  jmcneill 	(INTR_RD0_UNDERRUN | INTR_RD1_UNDERRUN |	\
    812       1.1  jmcneill 	INTR_RD2_UNDERRUN | INTR_RD3_UNDERRUN)
    813       1.1  jmcneill #else
    814       1.3  christos #define	INTR_TX_PKT			INTR_TX_PKT0
    815       1.1  jmcneill #define	INTR_RX_PKT			INTR_RX_PKT0
    816       1.1  jmcneill #define	INTR_RD_UNDERRUN		INTR_RD0_UNDERRUN
    817       1.1  jmcneill #endif
    818       1.1  jmcneill 
    819       1.1  jmcneill #define	ALC_INTRS					\
    820       1.1  jmcneill 	(INTR_DMA_RD_TO_RST | INTR_DMA_WR_TO_RST |	\
    821       1.1  jmcneill 	INTR_TXQ_TO_RST	| INTR_RX_PKT | INTR_TX_PKT |	\
    822       1.1  jmcneill 	INTR_RX_FIFO_OFLOW | INTR_RD_UNDERRUN |		\
    823       1.1  jmcneill 	INTR_TX_FIFO_UNDERRUN)
    824       1.1  jmcneill 
    825       1.1  jmcneill #define	ALC_INTR_RETRIG_TIMER		0x1608
    826       1.1  jmcneill #define	INTR_RETRIG_TIMER_MASK		0x0000FFFF
    827       1.1  jmcneill #define	INTR_RETRIG_TIMER_SHIFT		0
    828       1.1  jmcneill 
    829       1.1  jmcneill #define	ALC_HDS_CFG			0x160C
    830       1.1  jmcneill #define	HDS_CFG_ENB			0x00000001
    831       1.1  jmcneill #define	HDS_CFG_BACKFILLSIZE_MASK	0x000FFF00
    832       1.1  jmcneill #define	HDS_CFG_MAX_HDRSIZE_MASK	0xFFF00000
    833       1.1  jmcneill #define	HDS_CFG_BACKFILLSIZE_SHIFT	8
    834       1.1  jmcneill #define	HDS_CFG_MAX_HDRSIZE_SHIFT	20
    835       1.1  jmcneill 
    836       1.3  christos #define	ALC_MBOX_TD_PRI3_PROD_IDX	0x1618	/* 16 bits AR816x */
    837       1.3  christos 
    838       1.3  christos #define	ALC_MBOX_TD_PRI2_PROD_IDX	0x161A	/* 16 bits AR816x */
    839       1.3  christos 
    840       1.3  christos #define	ALC_MBOX_TD_PRI3_CONS_IDX	0x161C	/* 16 bits AR816x */
    841       1.3  christos 
    842       1.3  christos #define	ALC_MBOX_TD_PRI2_CONS_IDX	0x161E	/* 16 bits AR816x */
    843       1.3  christos 
    844       1.2  jmcneill /* AR813x/AR815x registers for MAC statistics */
    845       1.1  jmcneill #define	ALC_RX_MIB_BASE			0x1700
    846       1.1  jmcneill 
    847       1.1  jmcneill #define	ALC_TX_MIB_BASE			0x1760
    848       1.1  jmcneill 
    849       1.3  christos #define	ALC_DRV				0x1804	/* AR816x */
    850       1.3  christos #define	DRV_ASPM_SPD10LMT_1M		0x00000000
    851       1.3  christos #define	DRV_ASPM_SPD10LMT_10M		0x00000001
    852       1.3  christos #define	DRV_ASPM_SPD10LMT_100M		0x00000002
    853       1.3  christos #define	DRV_ASPM_SPD10LMT_NO		0x00000003
    854       1.3  christos #define	DRV_ASPM_SPD10LMT_MASK		0x00000003
    855       1.3  christos #define	DRV_ASPM_SPD100LMT_1M		0x00000000
    856       1.3  christos #define	DRV_ASPM_SPD100LMT_10M		0x00000004
    857       1.3  christos #define	DRV_ASPM_SPD100LMT_100M		0x00000008
    858       1.3  christos #define	DRV_ASPM_SPD100LMT_NO		0x0000000C
    859       1.3  christos #define	DRV_ASPM_SPD100LMT_MASK		0x0000000C
    860       1.3  christos #define	DRV_ASPM_SPD1000LMT_100M	0x00000000
    861       1.3  christos #define	DRV_ASPM_SPD1000LMT_NO		0x00000010
    862       1.3  christos #define	DRV_ASPM_SPD1000LMT_1M		0x00000020
    863       1.3  christos #define	DRV_ASPM_SPD1000LMT_10M		0x00000030
    864       1.3  christos #define	DRV_ASPM_SPD1000LMT_MASK	0x00000000
    865       1.3  christos #define	DRV_WOLCAP_BIOS_EN		0x00000100
    866       1.3  christos #define	DRV_WOLMAGIC_EN			0x00000200
    867       1.3  christos #define	DRV_WOLLINKUP_EN		0x00000400
    868       1.3  christos #define	DRV_WOLPATTERN_EN		0x00000800
    869       1.3  christos #define	DRV_AZ_EN			0x00001000
    870       1.3  christos #define	DRV_WOLS5_BIOS_EN		0x00010000
    871       1.3  christos #define	DRV_WOLS5_EN			0x00020000
    872       1.3  christos #define	DRV_DISABLE			0x00040000
    873       1.3  christos #define	DRV_PHY_MASK			0x1FE00000
    874       1.3  christos #define	DRV_PHY_EEE			0x00200000
    875       1.3  christos #define	DRV_PHY_APAUSE			0x00400000
    876       1.3  christos #define	DRV_PHY_PAUSE			0x00800000
    877       1.3  christos #define	DRV_PHY_DUPLEX			0x01000000
    878       1.3  christos #define	DRV_PHY_10			0x02000000
    879       1.3  christos #define	DRV_PHY_100			0x04000000
    880       1.3  christos #define	DRV_PHY_1000			0x08000000
    881       1.3  christos #define	DRV_PHY_AUTO			0x10000000
    882       1.3  christos #define	DRV_PHY_SHIFT			21
    883       1.3  christos 
    884       1.2  jmcneill #define	ALC_CLK_GATING_CFG		0x1814
    885       1.2  jmcneill #define	CLK_GATING_DMAW_ENB		0x0001
    886       1.2  jmcneill #define	CLK_GATING_DMAR_ENB		0x0002
    887       1.2  jmcneill #define	CLK_GATING_TXQ_ENB		0x0004
    888       1.2  jmcneill #define	CLK_GATING_RXQ_ENB		0x0008
    889       1.2  jmcneill #define	CLK_GATING_TXMAC_ENB		0x0010
    890       1.2  jmcneill #define	CLK_GATING_RXMAC_ENB		0x0020
    891       1.2  jmcneill 
    892       1.1  jmcneill #define	ALC_DEBUG_DATA0			0x1900
    893       1.1  jmcneill 
    894       1.1  jmcneill #define	ALC_DEBUG_DATA1			0x1904
    895       1.1  jmcneill 
    896       1.3  christos #define	ALC_MSI_RETRANS_TIMER		0x1920
    897       1.3  christos #define	MSI_RETRANS_TIMER_MASK		0x0000FFFF
    898       1.3  christos #define	MSI_RETRANS_MASK_SEL_STD	0x00000000
    899       1.3  christos #define	MSI_RETRANS_MASK_SEL_LINE	0x00010000
    900       1.3  christos #define	MSI_RETRANS_TIMER_SHIFT		0
    901       1.3  christos 
    902       1.3  christos #define	ALC_WRR				0x1938
    903       1.3  christos #define	WRR_PRI0_MASK			0x0000001F
    904       1.3  christos #define	WRR_PRI1_MASK			0x00001F00
    905       1.3  christos #define	WRR_PRI2_MASK			0x001F0000
    906       1.3  christos #define	WRR_PRI3_MASK			0x1F000000
    907       1.3  christos #define	WRR_PRI_RESTRICT_MASK		0x60000000
    908       1.3  christos #define	WRR_PRI_RESTRICT_ALL		0x00000000
    909       1.3  christos #define	WRR_PRI_RESTRICT_HI		0x20000000
    910       1.3  christos #define	WRR_PRI_RESTRICT_HI2		0x40000000
    911       1.3  christos #define	WRR_PRI_RESTRICT_NONE		0x60000000
    912       1.3  christos #define	WRR_PRI0_SHIFT			0
    913       1.3  christos #define	WRR_PRI1_SHIFT			8
    914       1.3  christos #define	WRR_PRI2_SHIFT			16
    915       1.3  christos #define	WRR_PRI3_SHIFT			24
    916       1.3  christos #define	WRR_PRI_DEFAULT			4
    917       1.3  christos #define	WRR_PRI_RESTRICT_SHIFT		29
    918       1.3  christos 
    919       1.3  christos #define	ALC_HQTD_CFG			0x193C
    920       1.3  christos #define	HQTD_CFG_Q1_BURST_MASK		0x0000000F
    921       1.3  christos #define	HQTD_CFG_Q2_BURST_MASK		0x000000F0
    922       1.3  christos #define	HQTD_CFG_Q3_BURST_MASK		0x00000F00
    923       1.3  christos #define	HQTD_CFG_BURST_ENB		0x80000000
    924       1.3  christos #define	HQTD_CFG_Q1_BURST_SHIFT		0
    925       1.3  christos #define	HQTD_CFG_Q2_BURST_SHIFT		4
    926       1.3  christos #define	HQTD_CFG_Q3_BURST_SHIFT		8
    927       1.3  christos 
    928       1.3  christos #define	ALC_MISC			0x19C0
    929       1.3  christos #define	MISC_INTNLOSC_OPEN		0x00000008
    930       1.3  christos #define	MISC_ISO_ENB			0x00001000
    931       1.3  christos #define	MISC_PSW_OCP_MASK		0x00E00000
    932       1.3  christos #define	MISC_PSW_OCP_SHIFT		21
    933       1.3  christos #define	MISC_PSW_OCP_DEFAULT		7
    934       1.3  christos 
    935       1.3  christos #define	ALC_MISC2			0x19C8
    936       1.3  christos #define	MISC2_CALB_START		0x00000001
    937       1.3  christos 
    938       1.3  christos #define	ALC_MISC3			0x19CC
    939       1.3  christos #define	MISC3_25M_NOTO_INTNL		0x00000001
    940       1.3  christos #define	MISC3_25M_BY_SW			0x00000002
    941       1.3  christos 
    942       1.1  jmcneill #define	ALC_MII_DBG_ADDR		0x1D
    943       1.1  jmcneill #define	ALC_MII_DBG_DATA		0x1E
    944       1.1  jmcneill 
    945       1.1  jmcneill #define	MII_ANA_CFG0			0x00
    946       1.1  jmcneill #define	ANA_RESTART_CAL			0x0001
    947       1.1  jmcneill #define	ANA_MANUL_SWICH_ON_MASK		0x001E
    948       1.1  jmcneill #define	ANA_MAN_ENABLE			0x0020
    949       1.1  jmcneill #define	ANA_SEL_HSP			0x0040
    950       1.1  jmcneill #define	ANA_EN_HB			0x0080
    951       1.1  jmcneill #define	ANA_EN_HBIAS			0x0100
    952       1.1  jmcneill #define	ANA_OEN_125M			0x0200
    953       1.1  jmcneill #define	ANA_EN_LCKDT			0x0400
    954       1.1  jmcneill #define	ANA_LCKDT_PHY			0x0800
    955       1.1  jmcneill #define	ANA_AFE_MODE			0x1000
    956       1.1  jmcneill #define	ANA_VCO_SLOW			0x2000
    957       1.1  jmcneill #define	ANA_VCO_FAST			0x4000
    958       1.1  jmcneill #define	ANA_SEL_CLK125M_DSP		0x8000
    959       1.1  jmcneill #define	ANA_MANUL_SWICH_ON_SHIFT	1
    960       1.1  jmcneill 
    961       1.3  christos #define	MII_DBG_ANACTL			0x00
    962       1.3  christos #define	DBG_ANACTL_DEFAULT		0x02EF
    963       1.3  christos 
    964       1.1  jmcneill #define	MII_ANA_CFG4			0x04
    965       1.1  jmcneill #define	ANA_IECHO_ADJ_MASK		0x0F
    966       1.1  jmcneill #define	ANA_IECHO_ADJ_3_MASK		0x000F
    967       1.1  jmcneill #define	ANA_IECHO_ADJ_2_MASK		0x00F0
    968       1.1  jmcneill #define	ANA_IECHO_ADJ_1_MASK		0x0F00
    969       1.1  jmcneill #define	ANA_IECHO_ADJ_0_MASK		0xF000
    970       1.1  jmcneill #define	ANA_IECHO_ADJ_3_SHIFT		0
    971       1.1  jmcneill #define	ANA_IECHO_ADJ_2_SHIFT		4
    972       1.1  jmcneill #define	ANA_IECHO_ADJ_1_SHIFT		8
    973       1.1  jmcneill #define	ANA_IECHO_ADJ_0_SHIFT		12
    974       1.1  jmcneill 
    975       1.3  christos #define	MII_DBG_SYSMODCTL		0x04
    976       1.3  christos #define	DBG_SYSMODCTL_DEFAULT		0xBB8B
    977       1.3  christos 
    978       1.1  jmcneill #define	MII_ANA_CFG5			0x05
    979       1.1  jmcneill #define	ANA_SERDES_CDR_BW_MASK		0x0003
    980       1.1  jmcneill #define	ANA_MS_PAD_DBG			0x0004
    981       1.1  jmcneill #define	ANA_SPEEDUP_DBG			0x0008
    982       1.1  jmcneill #define	ANA_SERDES_TH_LOS_MASK		0x0030
    983       1.1  jmcneill #define	ANA_SERDES_EN_DEEM		0x0040
    984       1.1  jmcneill #define	ANA_SERDES_TXELECIDLE		0x0080
    985       1.1  jmcneill #define	ANA_SERDES_BEACON		0x0100
    986       1.1  jmcneill #define	ANA_SERDES_HALFTXDR		0x0200
    987       1.1  jmcneill #define	ANA_SERDES_SEL_HSP		0x0400
    988       1.1  jmcneill #define	ANA_SERDES_EN_PLL		0x0800
    989       1.1  jmcneill #define	ANA_SERDES_EN			0x1000
    990       1.1  jmcneill #define	ANA_SERDES_EN_LCKDT		0x2000
    991       1.1  jmcneill #define	ANA_SERDES_CDR_BW_SHIFT		0
    992       1.1  jmcneill #define	ANA_SERDES_TH_LOS_SHIFT		4
    993       1.1  jmcneill 
    994       1.3  christos #define	MII_DBG_SRDSYSMOD		0x05
    995       1.3  christos #define	DBG_SRDSYSMOD_DEFAULT		0x2C46
    996       1.3  christos 
    997       1.1  jmcneill #define	MII_ANA_CFG11			0x0B
    998       1.1  jmcneill #define	ANA_PS_HIB_EN			0x8000
    999       1.1  jmcneill 
   1000       1.3  christos #define	MII_DBG_HIBNEG			0x0B
   1001       1.3  christos #define	DBG_HIBNEG_HIB_PULSE		0x1000
   1002       1.3  christos #define	DBG_HIBNEG_PSHIB_EN		0x8000
   1003       1.3  christos #define	DBG_HIBNEG_DEFAULT		0xBC40
   1004       1.3  christos 
   1005       1.1  jmcneill #define	MII_ANA_CFG18			0x12
   1006       1.1  jmcneill #define	ANA_TEST_MODE_10BT_01MASK	0x0003
   1007       1.1  jmcneill #define	ANA_LOOP_SEL_10BT		0x0004
   1008       1.1  jmcneill #define	ANA_RGMII_MODE_SW		0x0008
   1009       1.1  jmcneill #define	ANA_EN_LONGECABLE		0x0010
   1010       1.1  jmcneill #define	ANA_TEST_MODE_10BT_2		0x0020
   1011       1.1  jmcneill #define	ANA_EN_10BT_IDLE		0x0400
   1012       1.1  jmcneill #define	ANA_EN_MASK_TB			0x0800
   1013       1.1  jmcneill #define	ANA_TRIGGER_SEL_TIMER_MASK	0x3000
   1014       1.1  jmcneill #define	ANA_INTERVAL_SEL_TIMER_MASK	0xC000
   1015       1.1  jmcneill #define	ANA_TEST_MODE_10BT_01SHIFT	0
   1016       1.1  jmcneill #define	ANA_TRIGGER_SEL_TIMER_SHIFT	12
   1017       1.1  jmcneill #define	ANA_INTERVAL_SEL_TIMER_SHIFT	14
   1018       1.1  jmcneill 
   1019       1.3  christos #define	MII_DBG_TST10BTCFG		0x12
   1020       1.3  christos #define	DBG_TST10BTCFG_DEFAULT		0x4C04
   1021       1.3  christos 
   1022       1.3  christos #define	MII_DBG_AZ_ANADECT		0x15
   1023       1.3  christos #define	DBG_AZ_ANADECT_DEFAULT		0x3220
   1024       1.3  christos #define	DBG_AZ_ANADECT_LONG		0x3210
   1025       1.3  christos 
   1026       1.3  christos #define	MII_DBG_MSE16DB			0x18
   1027       1.3  christos #define	DBG_MSE16DB_UP			0x05EA
   1028       1.3  christos #define	DBG_MSE16DB_DOWN		0x02EA
   1029       1.3  christos 
   1030       1.3  christos #define	MII_DBG_MSE20DB			0x1C
   1031       1.3  christos #define	DBG_MSE20DB_TH_MASK		0x01FC
   1032       1.3  christos #define	DBG_MSE20DB_TH_DEFAULT		0x2E
   1033       1.3  christos #define	DBG_MSE20DB_TH_HI		0x54
   1034       1.3  christos #define	DBG_MSE20DB_TH_SHIFT		2
   1035       1.3  christos 
   1036       1.3  christos #define	MII_DBG_AGC			0x23
   1037       1.3  christos #define	DBG_AGC_2_VGA_MASK		0x3F00
   1038       1.3  christos #define	DBG_AGC_2_VGA_SHIFT		8
   1039       1.3  christos #define	DBG_AGC_LONG1G_LIMT		40
   1040       1.3  christos #define	DBG_AGC_LONG100M_LIMT		44
   1041       1.3  christos 
   1042       1.1  jmcneill #define	MII_ANA_CFG41			0x29
   1043       1.1  jmcneill #define	ANA_TOP_PS_EN			0x8000
   1044       1.1  jmcneill 
   1045       1.3  christos #define	MII_DBG_LEGCYPS			0x29
   1046       1.3  christos #define	DBG_LEGCYPS_ENB			0x8000
   1047       1.3  christos #define	DBG_LEGCYPS_DEFAULT		0x129D
   1048       1.3  christos 
   1049       1.1  jmcneill #define	MII_ANA_CFG54			0x36
   1050       1.1  jmcneill #define	ANA_LONG_CABLE_TH_100_MASK	0x003F
   1051       1.1  jmcneill #define	ANA_DESERVED			0x0040
   1052       1.1  jmcneill #define	ANA_EN_LIT_CH			0x0080
   1053       1.1  jmcneill #define	ANA_SHORT_CABLE_TH_100_MASK	0x3F00
   1054       1.1  jmcneill #define	ANA_BP_BAD_LINK_ACCUM		0x4000
   1055       1.1  jmcneill #define	ANA_BP_SMALL_BW			0x8000
   1056       1.1  jmcneill #define	ANA_LONG_CABLE_TH_100_SHIFT	0
   1057       1.1  jmcneill #define	ANA_SHORT_CABLE_TH_100_SHIFT	8
   1058       1.1  jmcneill 
   1059       1.3  christos #define	MII_DBG_TST100BTCFG		0x36
   1060       1.3  christos #define	DBG_TST100BTCFG_DEFAULT		0xE12C
   1061       1.3  christos 
   1062       1.3  christos #define	MII_DBG_GREENCFG		0x3B
   1063       1.3  christos #define	DBG_GREENCFG_DEFAULT		0x7078
   1064       1.3  christos 
   1065       1.3  christos #define	MII_DBG_GREENCFG2		0x3D
   1066       1.3  christos #define	DBG_GREENCFG2_GATE_DFSE_EN	0x0080
   1067       1.3  christos #define	DBG_GREENCFG2_BP_GREEN		0x8000
   1068       1.3  christos 
   1069       1.3  christos /* Device addr 3 */
   1070       1.3  christos #define	MII_EXT_PCS			3
   1071       1.3  christos 
   1072       1.3  christos #define	MII_EXT_CLDCTL3			0x8003
   1073       1.3  christos #define	EXT_CLDCTL3_BP_CABLE1TH_DET_GT	0x8000
   1074       1.3  christos 
   1075       1.3  christos #define	MII_EXT_CLDCTL5			0x8005
   1076       1.3  christos #define	EXT_CLDCTL5_BP_VD_HLFBIAS	0x4000
   1077       1.3  christos 
   1078       1.3  christos #define	MII_EXT_CLDCTL6			0x8006
   1079       1.3  christos #define	EXT_CLDCTL6_CAB_LEN_MASK	0x00FF
   1080       1.3  christos #define	EXT_CLDCTL6_CAB_LEN_SHIFT	0
   1081       1.3  christos #define	EXT_CLDCTL6_CAB_LEN_SHORT1G	116
   1082       1.3  christos #define	EXT_CLDCTL6_CAB_LEN_SHORT100M	152
   1083       1.3  christos 
   1084       1.3  christos #define	MII_EXT_VDRVBIAS		0x8062
   1085       1.3  christos #define	EXT_VDRVBIAS_DEFAULT		3
   1086       1.3  christos 
   1087       1.3  christos /* Device addr 7 */
   1088       1.3  christos #define	MII_EXT_ANEG			7
   1089       1.3  christos 
   1090       1.3  christos #define	MII_EXT_ANEG_LOCAL_EEEADV	0x3C
   1091       1.3  christos #define	ANEG_LOCA_EEEADV_100BT		0x0002
   1092       1.3  christos #define	ANEG_LOCA_EEEADV_1000BT		0x0004
   1093       1.3  christos 
   1094       1.3  christos #define	MII_EXT_ANEG_AFE		0x801A
   1095       1.3  christos #define	ANEG_AFEE_10BT_100M_TH		0x0040
   1096       1.3  christos 
   1097       1.3  christos #define	MII_EXT_ANEG_S3DIG10		0x8023
   1098       1.3  christos #define	ANEG_S3DIG10_SL			0x0001
   1099       1.3  christos #define	ANEG_S3DIG10_DEFAULT		0
   1100       1.3  christos 
   1101       1.3  christos #define	MII_EXT_ANEG_NLP78		0x8027
   1102       1.3  christos #define	ANEG_NLP78_120M_DEFAULT		0x8A05
   1103       1.3  christos 
   1104       1.1  jmcneill /* Statistics counters collected by the MAC. */
   1105       1.1  jmcneill struct smb {
   1106       1.1  jmcneill 	/* Rx stats. */
   1107       1.1  jmcneill 	uint32_t rx_frames;
   1108       1.1  jmcneill 	uint32_t rx_bcast_frames;
   1109       1.1  jmcneill 	uint32_t rx_mcast_frames;
   1110       1.1  jmcneill 	uint32_t rx_pause_frames;
   1111       1.1  jmcneill 	uint32_t rx_control_frames;
   1112       1.1  jmcneill 	uint32_t rx_crcerrs;
   1113       1.1  jmcneill 	uint32_t rx_lenerrs;
   1114       1.1  jmcneill 	uint32_t rx_bytes;
   1115       1.1  jmcneill 	uint32_t rx_runts;
   1116       1.1  jmcneill 	uint32_t rx_fragments;
   1117       1.1  jmcneill 	uint32_t rx_pkts_64;
   1118       1.1  jmcneill 	uint32_t rx_pkts_65_127;
   1119       1.1  jmcneill 	uint32_t rx_pkts_128_255;
   1120       1.1  jmcneill 	uint32_t rx_pkts_256_511;
   1121       1.1  jmcneill 	uint32_t rx_pkts_512_1023;
   1122       1.1  jmcneill 	uint32_t rx_pkts_1024_1518;
   1123       1.1  jmcneill 	uint32_t rx_pkts_1519_max;
   1124       1.1  jmcneill 	uint32_t rx_pkts_truncated;
   1125       1.1  jmcneill 	uint32_t rx_fifo_oflows;
   1126       1.1  jmcneill 	uint32_t rx_rrs_errs;
   1127       1.1  jmcneill 	uint32_t rx_alignerrs;
   1128       1.1  jmcneill 	uint32_t rx_bcast_bytes;
   1129       1.1  jmcneill 	uint32_t rx_mcast_bytes;
   1130       1.1  jmcneill 	uint32_t rx_pkts_filtered;
   1131       1.1  jmcneill 	/* Tx stats. */
   1132       1.1  jmcneill 	uint32_t tx_frames;
   1133       1.1  jmcneill 	uint32_t tx_bcast_frames;
   1134       1.1  jmcneill 	uint32_t tx_mcast_frames;
   1135       1.1  jmcneill 	uint32_t tx_pause_frames;
   1136       1.1  jmcneill 	uint32_t tx_excess_defer;
   1137       1.1  jmcneill 	uint32_t tx_control_frames;
   1138       1.1  jmcneill 	uint32_t tx_deferred;
   1139       1.1  jmcneill 	uint32_t tx_bytes;
   1140       1.1  jmcneill 	uint32_t tx_pkts_64;
   1141       1.1  jmcneill 	uint32_t tx_pkts_65_127;
   1142       1.1  jmcneill 	uint32_t tx_pkts_128_255;
   1143       1.1  jmcneill 	uint32_t tx_pkts_256_511;
   1144       1.1  jmcneill 	uint32_t tx_pkts_512_1023;
   1145       1.1  jmcneill 	uint32_t tx_pkts_1024_1518;
   1146       1.1  jmcneill 	uint32_t tx_pkts_1519_max;
   1147       1.1  jmcneill 	uint32_t tx_single_colls;
   1148       1.1  jmcneill 	uint32_t tx_multi_colls;
   1149       1.1  jmcneill 	uint32_t tx_late_colls;
   1150       1.1  jmcneill 	uint32_t tx_excess_colls;
   1151       1.1  jmcneill 	uint32_t tx_underrun;
   1152       1.1  jmcneill 	uint32_t tx_desc_underrun;
   1153       1.1  jmcneill 	uint32_t tx_lenerrs;
   1154       1.1  jmcneill 	uint32_t tx_pkts_truncated;
   1155       1.1  jmcneill 	uint32_t tx_bcast_bytes;
   1156       1.1  jmcneill 	uint32_t tx_mcast_bytes;
   1157       1.1  jmcneill 	uint32_t updated;
   1158       1.1  jmcneill };
   1159       1.1  jmcneill 
   1160       1.1  jmcneill /* CMB(Coalesing message block) */
   1161       1.1  jmcneill struct cmb {
   1162       1.1  jmcneill 	uint32_t cons;
   1163       1.1  jmcneill };
   1164       1.1  jmcneill 
   1165       1.1  jmcneill /* Rx free descriptor */
   1166       1.1  jmcneill struct rx_desc {
   1167       1.1  jmcneill 	uint64_t addr;
   1168       1.1  jmcneill };
   1169       1.1  jmcneill 
   1170       1.1  jmcneill /* Rx return descriptor */
   1171       1.1  jmcneill struct rx_rdesc {
   1172       1.1  jmcneill 	uint32_t rdinfo;
   1173       1.1  jmcneill #define	RRD_CSUM_MASK			0x0000FFFF
   1174       1.1  jmcneill #define	RRD_RD_CNT_MASK			0x000F0000
   1175       1.1  jmcneill #define	RRD_RD_IDX_MASK			0xFFF00000
   1176       1.1  jmcneill #define	RRD_CSUM_SHIFT			0
   1177       1.1  jmcneill #define	RRD_RD_CNT_SHIFT		16
   1178       1.1  jmcneill #define	RRD_RD_IDX_SHIFT		20
   1179       1.1  jmcneill #define	RRD_CSUM(x)			\
   1180       1.1  jmcneill 	(((x) & RRD_CSUM_MASK) >> RRD_CSUM_SHIFT)
   1181       1.1  jmcneill #define	RRD_RD_CNT(x)			\
   1182       1.1  jmcneill 	(((x) & RRD_RD_CNT_MASK) >> RRD_RD_CNT_SHIFT)
   1183       1.1  jmcneill #define	RRD_RD_IDX(x)			\
   1184       1.1  jmcneill 	(((x) & RRD_RD_IDX_MASK) >> RRD_RD_IDX_SHIFT)
   1185       1.1  jmcneill 	uint32_t rss;
   1186       1.1  jmcneill 	uint32_t vtag;
   1187       1.1  jmcneill #define	RRD_VLAN_MASK			0x0000FFFF
   1188       1.1  jmcneill #define	RRD_HEAD_LEN_MASK		0x00FF0000
   1189       1.1  jmcneill #define	RRD_HDS_MASK			0x03000000
   1190       1.1  jmcneill #define	RRD_HDS_NONE			0x00000000
   1191       1.1  jmcneill #define	RRD_HDS_HEAD			0x01000000
   1192       1.1  jmcneill #define	RRD_HDS_DATA			0x02000000
   1193       1.1  jmcneill #define	RRD_CPU_MASK			0x0C000000
   1194       1.1  jmcneill #define	RRD_HASH_FLAG_MASK		0xF0000000
   1195       1.1  jmcneill #define	RRD_VLAN_SHIFT			0
   1196       1.1  jmcneill #define	RRD_HEAD_LEN_SHIFT		16
   1197       1.1  jmcneill #define	RRD_HDS_SHIFT			24
   1198       1.1  jmcneill #define	RRD_CPU_SHIFT			26
   1199       1.1  jmcneill #define	RRD_HASH_FLAG_SHIFT		28
   1200       1.1  jmcneill #define	RRD_VLAN(x)			\
   1201       1.1  jmcneill 	(((x) & RRD_VLAN_MASK) >> RRD_VLAN_SHIFT)
   1202       1.1  jmcneill #define	RRD_HEAD_LEN(x)			\
   1203       1.1  jmcneill 	(((x) & RRD_HEAD_LEN_MASK) >> RRD_HEAD_LEN_SHIFT)
   1204       1.1  jmcneill #define	RRD_CPU(x)			\
   1205       1.1  jmcneill 	(((x) & RRD_CPU_MASK) >> RRD_CPU_SHIFT)
   1206       1.1  jmcneill 	uint32_t status;
   1207       1.1  jmcneill #define	RRD_LEN_MASK			0x00003FFF
   1208       1.1  jmcneill #define	RRD_LEN_SHIFT			0
   1209       1.1  jmcneill #define	RRD_TCP_UDPCSUM_NOK		0x00004000
   1210       1.1  jmcneill #define	RRD_IPCSUM_NOK			0x00008000
   1211       1.1  jmcneill #define	RRD_VLAN_TAG			0x00010000
   1212       1.1  jmcneill #define	RRD_PROTO_MASK			0x000E0000
   1213       1.1  jmcneill #define	RRD_PROTO_IPV4			0x00020000
   1214       1.1  jmcneill #define	RRD_PROTO_IPV6			0x000C0000
   1215       1.1  jmcneill #define	RRD_ERR_SUM			0x00100000
   1216       1.1  jmcneill #define	RRD_ERR_CRC			0x00200000
   1217       1.1  jmcneill #define	RRD_ERR_ALIGN			0x00400000
   1218       1.1  jmcneill #define	RRD_ERR_TRUNC			0x00800000
   1219       1.1  jmcneill #define	RRD_ERR_RUNT			0x01000000
   1220       1.1  jmcneill #define	RRD_ERR_ICMP			0x02000000
   1221       1.1  jmcneill #define	RRD_BCAST			0x04000000
   1222       1.1  jmcneill #define	RRD_MCAST			0x08000000
   1223       1.1  jmcneill #define	RRD_SNAP_LLC			0x10000000
   1224       1.1  jmcneill #define	RRD_ETHER			0x00000000
   1225       1.1  jmcneill #define	RRD_FIFO_FULL			0x20000000
   1226       1.1  jmcneill #define	RRD_ERR_LENGTH			0x40000000
   1227       1.1  jmcneill #define	RRD_VALID			0x80000000
   1228       1.1  jmcneill #define	RRD_BYTES(x)			\
   1229       1.1  jmcneill 	(((x) & RRD_LEN_MASK) >> RRD_LEN_SHIFT)
   1230       1.1  jmcneill #define	RRD_IPV4(x)			\
   1231       1.1  jmcneill 	(((x) & RRD_PROTO_MASK) == RRD_PROTO_IPV4)
   1232       1.1  jmcneill };
   1233       1.1  jmcneill 
   1234       1.1  jmcneill /* Tx descriptor */
   1235       1.1  jmcneill struct tx_desc {
   1236       1.1  jmcneill 	uint32_t len;
   1237       1.1  jmcneill #define	TD_BUFLEN_MASK			0x00003FFF
   1238       1.1  jmcneill #define	TD_VLAN_MASK			0xFFFF0000
   1239       1.1  jmcneill #define	TD_BUFLEN_SHIFT			0
   1240       1.1  jmcneill #define	TX_BYTES(x)			\
   1241       1.1  jmcneill 	(((x) << TD_BUFLEN_SHIFT) & TD_BUFLEN_MASK)
   1242       1.1  jmcneill #define	TD_VLAN_SHIFT			16
   1243       1.1  jmcneill 	uint32_t flags;
   1244       1.1  jmcneill #define	TD_L4HDR_OFFSET_MASK		0x000000FF	/* byte unit */
   1245       1.1  jmcneill #define	TD_TCPHDR_OFFSET_MASK		0x000000FF	/* byte unit */
   1246       1.1  jmcneill #define	TD_PLOAD_OFFSET_MASK		0x000000FF	/* 2 bytes unit */
   1247       1.1  jmcneill #define	TD_CUSTOM_CSUM			0x00000100
   1248       1.1  jmcneill #define	TD_IPCSUM			0x00000200
   1249       1.1  jmcneill #define	TD_TCPCSUM			0x00000400
   1250       1.1  jmcneill #define	TD_UDPCSUM			0x00000800
   1251       1.1  jmcneill #define	TD_TSO				0x00001000
   1252       1.1  jmcneill #define	TD_TSO_DESCV1			0x00000000
   1253       1.1  jmcneill #define	TD_TSO_DESCV2			0x00002000
   1254       1.1  jmcneill #define	TD_CON_VLAN_TAG			0x00004000
   1255       1.1  jmcneill #define	TD_INS_VLAN_TAG			0x00008000
   1256       1.1  jmcneill #define	TD_IPV4_DESCV2			0x00010000
   1257       1.1  jmcneill #define	TD_LLC_SNAP			0x00020000
   1258       1.1  jmcneill #define	TD_ETHERNET			0x00000000
   1259       1.1  jmcneill #define	TD_CUSTOM_CSUM_OFFSET_MASK	0x03FC0000	/* 2 bytes unit */
   1260       1.1  jmcneill #define	TD_CUSTOM_CSUM_EVEN_PAD		0x40000000
   1261       1.1  jmcneill #define	TD_MSS_MASK			0x7FFC0000
   1262       1.1  jmcneill #define	TD_EOP				0x80000000
   1263       1.1  jmcneill #define	TD_L4HDR_OFFSET_SHIFT		0
   1264       1.1  jmcneill #define	TD_TCPHDR_OFFSET_SHIFT		0
   1265       1.1  jmcneill #define	TD_PLOAD_OFFSET_SHIFT		0
   1266       1.1  jmcneill #define	TD_CUSTOM_CSUM_OFFSET_SHIFT	18
   1267       1.1  jmcneill #define	TD_MSS_SHIFT			18
   1268       1.1  jmcneill 	uint64_t addr;
   1269       1.1  jmcneill };
   1270       1.1  jmcneill 
   1271       1.1  jmcneill #define	ALC_TX_RING_CNT		256
   1272       1.1  jmcneill #define	ALC_TX_RING_ALIGN	sizeof(struct tx_desc)
   1273       1.1  jmcneill #define	ALC_RX_RING_CNT		256
   1274       1.1  jmcneill #define	ALC_RX_RING_ALIGN	sizeof(struct rx_desc)
   1275       1.1  jmcneill #define	ALC_RX_BUF_ALIGN	4
   1276       1.1  jmcneill #define	ALC_RR_RING_CNT		ALC_RX_RING_CNT
   1277       1.1  jmcneill #define	ALC_RR_RING_ALIGN	sizeof(struct rx_rdesc)
   1278       1.1  jmcneill #define	ALC_CMB_ALIGN		8
   1279       1.1  jmcneill #define	ALC_SMB_ALIGN		8
   1280       1.1  jmcneill 
   1281       1.1  jmcneill #define	ALC_TSO_MAXSEGSIZE	4096
   1282       1.1  jmcneill #define	ALC_TSO_MAXSIZE		(65535 + sizeof(struct ether_vlan_header))
   1283       1.1  jmcneill #define	ALC_MAXTXSEGS		32
   1284       1.1  jmcneill 
   1285       1.1  jmcneill #define	ALC_ADDR_LO(x)		((uint64_t) (x) & 0xFFFFFFFF)
   1286       1.1  jmcneill #define	ALC_ADDR_HI(x)		((uint64_t) (x) >> 32)
   1287       1.1  jmcneill 
   1288       1.1  jmcneill #define	ALC_DESC_INC(x, y)	((x) = ((x) + 1) % (y))
   1289       1.1  jmcneill 
   1290       1.1  jmcneill /* Water mark to kick reclaiming Tx buffers. */
   1291       1.1  jmcneill #define	ALC_TX_DESC_HIWAT	((ALC_TX_RING_CNT * 6) / 10)
   1292       1.1  jmcneill 
   1293       1.3  christos /*
   1294       1.3  christos  * AR816x controllers support up to 16 messages but this driver
   1295       1.3  christos  * uses single message.
   1296       1.3  christos  */
   1297       1.1  jmcneill #define	ALC_MSI_MESSAGES	1
   1298       1.1  jmcneill #define	ALC_MSIX_MESSAGES	1
   1299       1.1  jmcneill 
   1300       1.1  jmcneill #define	ALC_TX_RING_SZ		\
   1301       1.1  jmcneill 	(sizeof(struct tx_desc) * ALC_TX_RING_CNT)
   1302       1.1  jmcneill #define	ALC_RX_RING_SZ		\
   1303       1.1  jmcneill 	(sizeof(struct rx_desc) * ALC_RX_RING_CNT)
   1304       1.1  jmcneill #define	ALC_RR_RING_SZ		\
   1305       1.1  jmcneill 	(sizeof(struct rx_rdesc) * ALC_RR_RING_CNT)
   1306       1.1  jmcneill #define	ALC_CMB_SZ		(sizeof(struct cmb))
   1307       1.1  jmcneill #define	ALC_SMB_SZ		(sizeof(struct smb))
   1308       1.1  jmcneill 
   1309       1.1  jmcneill #define	ALC_PROC_MIN		16
   1310       1.1  jmcneill #define	ALC_PROC_MAX		(ALC_RX_RING_CNT - 1)
   1311       1.1  jmcneill #define	ALC_PROC_DEFAULT	(ALC_RX_RING_CNT / 4)
   1312       1.1  jmcneill 
   1313       1.1  jmcneill /*
   1314       1.2  jmcneill  * The number of bits reserved for MSS in AR813x/AR815x controllers
   1315       1.1  jmcneill  * are 13 bits. This limits the maximum interface MTU size in TSO
   1316       1.1  jmcneill  * case(8191 + sizeof(struct ip) + sizeof(struct tcphdr)) as upper
   1317       1.1  jmcneill  * stack should not generate TCP segments with MSS greater than the
   1318       1.1  jmcneill  * limit. Also Atheros says that maximum MTU for TSO is 6KB.
   1319       1.1  jmcneill  */
   1320       1.1  jmcneill #define	ALC_TSO_MTU		(6 * 1024)
   1321       1.1  jmcneill 
   1322       1.1  jmcneill struct alc_rxdesc {
   1323       1.1  jmcneill 	struct mbuf		*rx_m;
   1324       1.1  jmcneill 	bus_dmamap_t		rx_dmamap;
   1325       1.1  jmcneill 	struct rx_desc		*rx_desc;
   1326       1.1  jmcneill };
   1327       1.1  jmcneill 
   1328       1.1  jmcneill struct alc_txdesc {
   1329       1.1  jmcneill 	struct mbuf		*tx_m;
   1330       1.1  jmcneill 	bus_dmamap_t		tx_dmamap;
   1331       1.1  jmcneill };
   1332       1.1  jmcneill 
   1333       1.1  jmcneill struct alc_ring_data {
   1334       1.1  jmcneill 	struct tx_desc		*alc_tx_ring;
   1335       1.1  jmcneill 	bus_dma_segment_t	alc_tx_ring_seg;
   1336       1.1  jmcneill 	bus_addr_t		alc_tx_ring_paddr;
   1337       1.1  jmcneill 	struct rx_desc		*alc_rx_ring;
   1338       1.1  jmcneill 	bus_dma_segment_t	alc_rx_ring_seg;
   1339       1.1  jmcneill 	bus_addr_t		alc_rx_ring_paddr;
   1340       1.1  jmcneill 	struct rx_rdesc		*alc_rr_ring;
   1341       1.1  jmcneill 	bus_dma_segment_t	alc_rr_ring_seg;
   1342       1.1  jmcneill 	bus_addr_t		alc_rr_ring_paddr;
   1343       1.1  jmcneill 	struct cmb		*alc_cmb;
   1344       1.1  jmcneill 	bus_dma_segment_t	alc_cmb_seg;
   1345       1.1  jmcneill 	bus_addr_t		alc_cmb_paddr;
   1346       1.1  jmcneill 	struct smb		*alc_smb;
   1347       1.1  jmcneill 	bus_dma_segment_t	alc_smb_seg;
   1348       1.1  jmcneill 	bus_addr_t		alc_smb_paddr;
   1349       1.1  jmcneill };
   1350       1.1  jmcneill 
   1351       1.1  jmcneill struct alc_chain_data {
   1352       1.1  jmcneill 	struct alc_txdesc	alc_txdesc[ALC_TX_RING_CNT];
   1353       1.1  jmcneill 	struct alc_rxdesc	alc_rxdesc[ALC_RX_RING_CNT];
   1354       1.1  jmcneill 	bus_dmamap_t		alc_tx_ring_map;
   1355       1.1  jmcneill 	bus_dma_segment_t	alc_tx_ring_seg;
   1356       1.1  jmcneill 	bus_dmamap_t		alc_rx_ring_map;
   1357       1.1  jmcneill 	bus_dma_segment_t	alc_rx_ring_seg;
   1358       1.1  jmcneill 	bus_dmamap_t		alc_rr_ring_map;
   1359       1.1  jmcneill 	bus_dma_segment_t	alc_rr_ring_seg;
   1360       1.1  jmcneill 	bus_dmamap_t		alc_rx_sparemap;
   1361       1.1  jmcneill 	bus_dmamap_t		alc_cmb_map;
   1362       1.1  jmcneill 	bus_dma_segment_t	alc_cmb_seg;
   1363       1.1  jmcneill 	bus_dmamap_t		alc_smb_map;
   1364       1.1  jmcneill 	bus_dma_segment_t	alc_smb_seg;
   1365       1.1  jmcneill 
   1366       1.1  jmcneill 	int			alc_tx_prod;
   1367       1.1  jmcneill 	int			alc_tx_cons;
   1368       1.1  jmcneill 	int			alc_tx_cnt;
   1369       1.1  jmcneill 	int			alc_rx_cons;
   1370       1.1  jmcneill 	int			alc_rr_cons;
   1371       1.1  jmcneill 	int			alc_rxlen;
   1372       1.1  jmcneill 
   1373       1.1  jmcneill 	struct mbuf		*alc_rxhead;
   1374       1.1  jmcneill 	struct mbuf		*alc_rxtail;
   1375       1.1  jmcneill 	struct mbuf		*alc_rxprev_tail;
   1376       1.1  jmcneill };
   1377       1.1  jmcneill 
   1378       1.1  jmcneill struct alc_hw_stats {
   1379       1.1  jmcneill 	/* Rx stats. */
   1380       1.1  jmcneill 	uint32_t rx_frames;
   1381       1.1  jmcneill 	uint32_t rx_bcast_frames;
   1382       1.1  jmcneill 	uint32_t rx_mcast_frames;
   1383       1.1  jmcneill 	uint32_t rx_pause_frames;
   1384       1.1  jmcneill 	uint32_t rx_control_frames;
   1385       1.1  jmcneill 	uint32_t rx_crcerrs;
   1386       1.1  jmcneill 	uint32_t rx_lenerrs;
   1387       1.1  jmcneill 	uint64_t rx_bytes;
   1388       1.1  jmcneill 	uint32_t rx_runts;
   1389       1.1  jmcneill 	uint32_t rx_fragments;
   1390       1.1  jmcneill 	uint32_t rx_pkts_64;
   1391       1.1  jmcneill 	uint32_t rx_pkts_65_127;
   1392       1.1  jmcneill 	uint32_t rx_pkts_128_255;
   1393       1.1  jmcneill 	uint32_t rx_pkts_256_511;
   1394       1.1  jmcneill 	uint32_t rx_pkts_512_1023;
   1395       1.1  jmcneill 	uint32_t rx_pkts_1024_1518;
   1396       1.1  jmcneill 	uint32_t rx_pkts_1519_max;
   1397       1.1  jmcneill 	uint32_t rx_pkts_truncated;
   1398       1.1  jmcneill 	uint32_t rx_fifo_oflows;
   1399       1.1  jmcneill 	uint32_t rx_rrs_errs;
   1400       1.1  jmcneill 	uint32_t rx_alignerrs;
   1401       1.1  jmcneill 	uint64_t rx_bcast_bytes;
   1402       1.1  jmcneill 	uint64_t rx_mcast_bytes;
   1403       1.1  jmcneill 	uint32_t rx_pkts_filtered;
   1404       1.1  jmcneill 	/* Tx stats. */
   1405       1.1  jmcneill 	uint32_t tx_frames;
   1406       1.1  jmcneill 	uint32_t tx_bcast_frames;
   1407       1.1  jmcneill 	uint32_t tx_mcast_frames;
   1408       1.1  jmcneill 	uint32_t tx_pause_frames;
   1409       1.1  jmcneill 	uint32_t tx_excess_defer;
   1410       1.1  jmcneill 	uint32_t tx_control_frames;
   1411       1.1  jmcneill 	uint32_t tx_deferred;
   1412       1.1  jmcneill 	uint64_t tx_bytes;
   1413       1.1  jmcneill 	uint32_t tx_pkts_64;
   1414       1.1  jmcneill 	uint32_t tx_pkts_65_127;
   1415       1.1  jmcneill 	uint32_t tx_pkts_128_255;
   1416       1.1  jmcneill 	uint32_t tx_pkts_256_511;
   1417       1.1  jmcneill 	uint32_t tx_pkts_512_1023;
   1418       1.1  jmcneill 	uint32_t tx_pkts_1024_1518;
   1419       1.1  jmcneill 	uint32_t tx_pkts_1519_max;
   1420       1.1  jmcneill 	uint32_t tx_single_colls;
   1421       1.1  jmcneill 	uint32_t tx_multi_colls;
   1422       1.1  jmcneill 	uint32_t tx_late_colls;
   1423       1.1  jmcneill 	uint32_t tx_excess_colls;
   1424       1.1  jmcneill 	uint32_t tx_underrun;
   1425       1.1  jmcneill 	uint32_t tx_desc_underrun;
   1426       1.1  jmcneill 	uint32_t tx_lenerrs;
   1427       1.1  jmcneill 	uint32_t tx_pkts_truncated;
   1428       1.1  jmcneill 	uint64_t tx_bcast_bytes;
   1429       1.1  jmcneill 	uint64_t tx_mcast_bytes;
   1430       1.1  jmcneill };
   1431       1.1  jmcneill 
   1432       1.2  jmcneill struct alc_ident {
   1433       1.2  jmcneill 	uint16_t	vendorid;
   1434       1.2  jmcneill 	uint16_t	deviceid;
   1435       1.2  jmcneill 	uint32_t	max_framelen;
   1436       1.2  jmcneill 	const char	*name;
   1437       1.2  jmcneill };
   1438       1.2  jmcneill 
   1439       1.1  jmcneill /*
   1440       1.1  jmcneill  * Software state per device.
   1441       1.1  jmcneill  */
   1442       1.1  jmcneill struct alc_softc {
   1443       1.1  jmcneill 	device_t		sc_dev;
   1444       1.1  jmcneill 	struct ethercom		sc_ec;
   1445       1.1  jmcneill 
   1446       1.1  jmcneill 	bus_space_tag_t		sc_mem_bt;
   1447       1.1  jmcneill 	bus_space_handle_t	sc_mem_bh;
   1448       1.1  jmcneill 	bus_size_t		sc_mem_size;
   1449       1.1  jmcneill 	bus_dma_tag_t		sc_dmat;
   1450       1.1  jmcneill 	pci_chipset_tag_t	sc_pct;
   1451       1.1  jmcneill 	pcitag_t		sc_pcitag;
   1452       1.1  jmcneill 
   1453       1.1  jmcneill 	void			*sc_irq_handle;
   1454  1.6.16.1    martin 	const struct alc_ident	*alc_ident;
   1455       1.1  jmcneill 	struct mii_data		sc_miibus;
   1456       1.1  jmcneill 	int			alc_rev;
   1457       1.2  jmcneill 	int			alc_expcap;
   1458       1.1  jmcneill 	int			alc_chip_rev;
   1459       1.1  jmcneill 	int			alc_phyaddr;
   1460       1.1  jmcneill 	uint8_t			alc_eaddr[ETHER_ADDR_LEN];
   1461       1.1  jmcneill 	uint32_t		alc_dma_rd_burst;
   1462       1.1  jmcneill 	uint32_t		alc_dma_wr_burst;
   1463       1.1  jmcneill 	uint32_t		alc_rcb;
   1464       1.1  jmcneill 	int			alc_flags;
   1465       1.1  jmcneill #define	ALC_FLAG_PCIE		0x0001
   1466       1.1  jmcneill #define	ALC_FLAG_PCIX		0x0002
   1467       1.1  jmcneill #define	ALC_FLAG_MSI		0x0004
   1468       1.1  jmcneill #define	ALC_FLAG_MSIX		0x0008
   1469       1.1  jmcneill #define	ALC_FLAG_FASTETHER	0x0020
   1470       1.1  jmcneill #define	ALC_FLAG_JUMBO		0x0040
   1471       1.1  jmcneill #define	ALC_FLAG_CMB_BUG	0x0100
   1472       1.1  jmcneill #define	ALC_FLAG_SMB_BUG	0x0200
   1473       1.2  jmcneill #define	ALC_FLAG_L0S		0x0400
   1474       1.2  jmcneill #define	ALC_FLAG_L1S		0x0800
   1475       1.2  jmcneill #define	ALC_FLAG_APS		0x1000
   1476       1.3  christos #define	ALC_FLAG_AR816X_FAMILY	0x2000
   1477       1.3  christos #define	ALC_FLAG_LINK_WAR	0x4000
   1478       1.1  jmcneill #define	ALC_FLAG_LINK		0x8000
   1479       1.1  jmcneill 
   1480       1.1  jmcneill 	callout_t		sc_tick_ch;
   1481       1.1  jmcneill 	struct alc_hw_stats	alc_stats;
   1482       1.1  jmcneill 	struct alc_chain_data	alc_cdata;
   1483       1.1  jmcneill 	struct alc_ring_data	alc_rdata;
   1484       1.1  jmcneill 	int			alc_int_rx_mod;
   1485       1.1  jmcneill 	int			alc_int_tx_mod;
   1486       1.1  jmcneill 	int			alc_buf_size;
   1487       1.1  jmcneill };
   1488       1.1  jmcneill 
   1489       1.1  jmcneill /* Register access macros. */
   1490       1.1  jmcneill #define	CSR_WRITE_4(_sc, reg, val)	\
   1491       1.6      leot 	bus_space_write_4((_sc)->sc_mem_bt, (_sc)->sc_mem_bh, (reg), (val))
   1492       1.1  jmcneill #define	CSR_WRITE_2(_sc, reg, val)	\
   1493       1.6      leot 	bus_space_write_2((_sc)->sc_mem_bt, (_sc)->sc_mem_bh, (reg), (val))
   1494       1.1  jmcneill #define	CSR_WRITE_1(_sc, reg, val)	\
   1495       1.6      leot 	bus_space_write_1((_sc)->sc_mem_bt, (_sc)->sc_mem_bh, (reg), (val))
   1496       1.1  jmcneill #define	CSR_READ_2(_sc, reg)		\
   1497       1.6      leot 	bus_space_read_2((_sc)->sc_mem_bt, (_sc)->sc_mem_bh, (reg))
   1498       1.1  jmcneill #define	CSR_READ_4(_sc, reg)		\
   1499       1.6      leot 	bus_space_read_4((_sc)->sc_mem_bt, (_sc)->sc_mem_bh, (reg))
   1500       1.1  jmcneill 
   1501       1.1  jmcneill #define	ALC_RXCHAIN_RESET(_sc)						\
   1502       1.1  jmcneill do {									\
   1503       1.1  jmcneill 	(_sc)->alc_cdata.alc_rxhead = NULL;				\
   1504       1.1  jmcneill 	(_sc)->alc_cdata.alc_rxtail = NULL;				\
   1505       1.1  jmcneill 	(_sc)->alc_cdata.alc_rxprev_tail = NULL;			\
   1506       1.1  jmcneill 	(_sc)->alc_cdata.alc_rxlen = 0;					\
   1507       1.1  jmcneill } while (0)
   1508       1.1  jmcneill 
   1509       1.1  jmcneill #define	ALC_TX_TIMEOUT		5
   1510       1.1  jmcneill #define	ALC_RESET_TIMEOUT	100
   1511       1.1  jmcneill #define	ALC_TIMEOUT		1000
   1512       1.1  jmcneill #define	ALC_PHY_TIMEOUT		1000
   1513       1.1  jmcneill 
   1514       1.3  christos /* For compatibility with FreeBSD */
   1515       1.3  christos #define IFM_UNKNOWN		31
   1516       1.3  christos 
   1517       1.1  jmcneill #endif	/* _IF_ALCREG_H */
   1518