if_ale.c revision 1.3.2.3
1 1.3.2.3 snj /* $NetBSD: if_ale.c,v 1.3.2.3 2009/09/10 07:26:38 snj Exp $ */ 2 1.3.2.2 snj 3 1.3.2.2 snj /*- 4 1.3.2.2 snj * Copyright (c) 2008, Pyun YongHyeon <yongari (at) FreeBSD.org> 5 1.3.2.2 snj * All rights reserved. 6 1.3.2.2 snj * 7 1.3.2.2 snj * Redistribution and use in source and binary forms, with or without 8 1.3.2.2 snj * modification, are permitted provided that the following conditions 9 1.3.2.2 snj * are met: 10 1.3.2.2 snj * 1. Redistributions of source code must retain the above copyright 11 1.3.2.2 snj * notice unmodified, this list of conditions, and the following 12 1.3.2.2 snj * disclaimer. 13 1.3.2.2 snj * 2. Redistributions in binary form must reproduce the above copyright 14 1.3.2.2 snj * notice, this list of conditions and the following disclaimer in the 15 1.3.2.2 snj * documentation and/or other materials provided with the distribution. 16 1.3.2.2 snj * 17 1.3.2.2 snj * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 1.3.2.2 snj * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 1.3.2.2 snj * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 1.3.2.2 snj * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 1.3.2.2 snj * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 1.3.2.2 snj * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 1.3.2.2 snj * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 1.3.2.2 snj * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 1.3.2.2 snj * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 1.3.2.2 snj * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 1.3.2.2 snj * SUCH DAMAGE. 28 1.3.2.2 snj * 29 1.3.2.2 snj * $FreeBSD: src/sys/dev/ale/if_ale.c,v 1.3 2008/12/03 09:01:12 yongari Exp $ 30 1.3.2.2 snj */ 31 1.3.2.2 snj 32 1.3.2.2 snj /* Driver for Atheros AR8121/AR8113/AR8114 PCIe Ethernet. */ 33 1.3.2.2 snj 34 1.3.2.2 snj #include <sys/cdefs.h> 35 1.3.2.3 snj __KERNEL_RCSID(0, "$NetBSD: if_ale.c,v 1.3.2.3 2009/09/10 07:26:38 snj Exp $"); 36 1.3.2.2 snj 37 1.3.2.2 snj #include "bpfilter.h" 38 1.3.2.2 snj #include "vlan.h" 39 1.3.2.2 snj 40 1.3.2.2 snj #include <sys/param.h> 41 1.3.2.2 snj #include <sys/proc.h> 42 1.3.2.2 snj #include <sys/endian.h> 43 1.3.2.2 snj #include <sys/systm.h> 44 1.3.2.2 snj #include <sys/types.h> 45 1.3.2.2 snj #include <sys/sockio.h> 46 1.3.2.2 snj #include <sys/mbuf.h> 47 1.3.2.2 snj #include <sys/queue.h> 48 1.3.2.2 snj #include <sys/kernel.h> 49 1.3.2.2 snj #include <sys/device.h> 50 1.3.2.2 snj #include <sys/callout.h> 51 1.3.2.2 snj #include <sys/socket.h> 52 1.3.2.2 snj 53 1.3.2.2 snj #include <sys/bus.h> 54 1.3.2.2 snj 55 1.3.2.2 snj #include <net/if.h> 56 1.3.2.2 snj #include <net/if_dl.h> 57 1.3.2.2 snj #include <net/if_llc.h> 58 1.3.2.2 snj #include <net/if_media.h> 59 1.3.2.2 snj #include <net/if_ether.h> 60 1.3.2.2 snj 61 1.3.2.2 snj #ifdef INET 62 1.3.2.2 snj #include <netinet/in.h> 63 1.3.2.2 snj #include <netinet/in_systm.h> 64 1.3.2.2 snj #include <netinet/in_var.h> 65 1.3.2.2 snj #include <netinet/ip.h> 66 1.3.2.2 snj #endif 67 1.3.2.2 snj 68 1.3.2.2 snj #include <net/if_types.h> 69 1.3.2.2 snj #include <net/if_vlanvar.h> 70 1.3.2.2 snj 71 1.3.2.2 snj #if NBPFILTER > 0 72 1.3.2.2 snj #include <net/bpf.h> 73 1.3.2.2 snj #endif 74 1.3.2.2 snj 75 1.3.2.2 snj #include <sys/rnd.h> 76 1.3.2.2 snj 77 1.3.2.2 snj #include <dev/mii/mii.h> 78 1.3.2.2 snj #include <dev/mii/miivar.h> 79 1.3.2.2 snj 80 1.3.2.2 snj #include <dev/pci/pcireg.h> 81 1.3.2.2 snj #include <dev/pci/pcivar.h> 82 1.3.2.2 snj #include <dev/pci/pcidevs.h> 83 1.3.2.2 snj 84 1.3.2.2 snj #include <dev/pci/if_alereg.h> 85 1.3.2.2 snj 86 1.3.2.2 snj static int ale_match(device_t, cfdata_t, void *); 87 1.3.2.2 snj static void ale_attach(device_t, device_t, void *); 88 1.3.2.2 snj static int ale_detach(device_t, int); 89 1.3.2.2 snj 90 1.3.2.2 snj static int ale_miibus_readreg(device_t, int, int); 91 1.3.2.2 snj static void ale_miibus_writereg(device_t, int, int, int); 92 1.3.2.2 snj static void ale_miibus_statchg(device_t); 93 1.3.2.2 snj 94 1.3.2.2 snj static int ale_init(struct ifnet *); 95 1.3.2.2 snj static void ale_start(struct ifnet *); 96 1.3.2.2 snj static int ale_ioctl(struct ifnet *, u_long, void *); 97 1.3.2.2 snj static void ale_watchdog(struct ifnet *); 98 1.3.2.2 snj static int ale_mediachange(struct ifnet *); 99 1.3.2.2 snj static void ale_mediastatus(struct ifnet *, struct ifmediareq *); 100 1.3.2.2 snj 101 1.3.2.2 snj static int ale_intr(void *); 102 1.3.2.2 snj static int ale_rxeof(struct ale_softc *sc); 103 1.3.2.2 snj static void ale_rx_update_page(struct ale_softc *, struct ale_rx_page **, 104 1.3.2.2 snj uint32_t, uint32_t *); 105 1.3.2.2 snj static void ale_rxcsum(struct ale_softc *, struct mbuf *, uint32_t); 106 1.3.2.2 snj static void ale_txeof(struct ale_softc *); 107 1.3.2.2 snj 108 1.3.2.2 snj static int ale_dma_alloc(struct ale_softc *); 109 1.3.2.2 snj static void ale_dma_free(struct ale_softc *); 110 1.3.2.2 snj static int ale_encap(struct ale_softc *, struct mbuf **); 111 1.3.2.2 snj static void ale_init_rx_pages(struct ale_softc *); 112 1.3.2.2 snj static void ale_init_tx_ring(struct ale_softc *); 113 1.3.2.2 snj 114 1.3.2.2 snj static void ale_stop(struct ifnet *, int); 115 1.3.2.2 snj static void ale_tick(void *); 116 1.3.2.2 snj static void ale_get_macaddr(struct ale_softc *); 117 1.3.2.2 snj static void ale_mac_config(struct ale_softc *); 118 1.3.2.2 snj static void ale_phy_reset(struct ale_softc *); 119 1.3.2.2 snj static void ale_reset(struct ale_softc *); 120 1.3.2.2 snj static void ale_rxfilter(struct ale_softc *); 121 1.3.2.2 snj static void ale_rxvlan(struct ale_softc *); 122 1.3.2.2 snj static void ale_stats_clear(struct ale_softc *); 123 1.3.2.2 snj static void ale_stats_update(struct ale_softc *); 124 1.3.2.2 snj static void ale_stop_mac(struct ale_softc *); 125 1.3.2.2 snj 126 1.3.2.2 snj CFATTACH_DECL_NEW(ale, sizeof(struct ale_softc), 127 1.3.2.2 snj ale_match, ale_attach, ale_detach, NULL); 128 1.3.2.2 snj 129 1.3.2.2 snj int aledebug = 0; 130 1.3.2.2 snj #define DPRINTF(x) do { if (aledebug) printf x; } while (0) 131 1.3.2.2 snj 132 1.3.2.2 snj #define ETHER_ALIGN 2 133 1.3.2.2 snj #define ALE_CSUM_FEATURES (M_CSUM_TCPv4 | M_CSUM_UDPv4) 134 1.3.2.2 snj 135 1.3.2.2 snj static int 136 1.3.2.2 snj ale_miibus_readreg(device_t dev, int phy, int reg) 137 1.3.2.2 snj { 138 1.3.2.2 snj struct ale_softc *sc = device_private(dev); 139 1.3.2.2 snj uint32_t v; 140 1.3.2.2 snj int i; 141 1.3.2.2 snj 142 1.3.2.2 snj if (phy != sc->ale_phyaddr) 143 1.3.2.2 snj return 0; 144 1.3.2.2 snj 145 1.3.2.3 snj if (sc->ale_flags & ALE_FLAG_FASTETHER) { 146 1.3.2.3 snj switch (reg) { 147 1.3.2.3 snj case MII_100T2CR: 148 1.3.2.3 snj case MII_100T2SR: 149 1.3.2.3 snj case MII_EXTSR: 150 1.3.2.3 snj return 0; 151 1.3.2.3 snj default: 152 1.3.2.3 snj break; 153 1.3.2.3 snj } 154 1.3.2.3 snj } 155 1.3.2.3 snj 156 1.3.2.2 snj CSR_WRITE_4(sc, ALE_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ | 157 1.3.2.2 snj MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); 158 1.3.2.2 snj for (i = ALE_PHY_TIMEOUT; i > 0; i--) { 159 1.3.2.2 snj DELAY(5); 160 1.3.2.2 snj v = CSR_READ_4(sc, ALE_MDIO); 161 1.3.2.2 snj if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) 162 1.3.2.2 snj break; 163 1.3.2.2 snj } 164 1.3.2.2 snj 165 1.3.2.2 snj if (i == 0) { 166 1.3.2.2 snj printf("%s: phy read timeout: phy %d, reg %d\n", 167 1.3.2.2 snj device_xname(sc->sc_dev), phy, reg); 168 1.3.2.2 snj return 0; 169 1.3.2.2 snj } 170 1.3.2.2 snj 171 1.3.2.3 snj return (v & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT; 172 1.3.2.2 snj } 173 1.3.2.2 snj 174 1.3.2.2 snj static void 175 1.3.2.2 snj ale_miibus_writereg(device_t dev, int phy, int reg, int val) 176 1.3.2.2 snj { 177 1.3.2.2 snj struct ale_softc *sc = device_private(dev); 178 1.3.2.2 snj uint32_t v; 179 1.3.2.2 snj int i; 180 1.3.2.2 snj 181 1.3.2.2 snj if (phy != sc->ale_phyaddr) 182 1.3.2.2 snj return; 183 1.3.2.2 snj 184 1.3.2.3 snj if (sc->ale_flags & ALE_FLAG_FASTETHER) { 185 1.3.2.3 snj switch (reg) { 186 1.3.2.3 snj case MII_100T2CR: 187 1.3.2.3 snj case MII_100T2SR: 188 1.3.2.3 snj case MII_EXTSR: 189 1.3.2.3 snj return; 190 1.3.2.3 snj default: 191 1.3.2.3 snj break; 192 1.3.2.3 snj } 193 1.3.2.3 snj } 194 1.3.2.3 snj 195 1.3.2.2 snj CSR_WRITE_4(sc, ALE_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE | 196 1.3.2.2 snj (val & MDIO_DATA_MASK) << MDIO_DATA_SHIFT | 197 1.3.2.2 snj MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); 198 1.3.2.2 snj for (i = ALE_PHY_TIMEOUT; i > 0; i--) { 199 1.3.2.2 snj DELAY(5); 200 1.3.2.2 snj v = CSR_READ_4(sc, ALE_MDIO); 201 1.3.2.2 snj if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) 202 1.3.2.2 snj break; 203 1.3.2.2 snj } 204 1.3.2.2 snj 205 1.3.2.2 snj if (i == 0) 206 1.3.2.2 snj printf("%s: phy write timeout: phy %d, reg %d\n", 207 1.3.2.2 snj device_xname(sc->sc_dev), phy, reg); 208 1.3.2.2 snj } 209 1.3.2.2 snj 210 1.3.2.2 snj static void 211 1.3.2.2 snj ale_miibus_statchg(device_t dev) 212 1.3.2.2 snj { 213 1.3.2.2 snj struct ale_softc *sc = device_private(dev); 214 1.3.2.2 snj struct ifnet *ifp = &sc->sc_ec.ec_if; 215 1.3.2.2 snj struct mii_data *mii; 216 1.3.2.2 snj uint32_t reg; 217 1.3.2.2 snj 218 1.3.2.2 snj if ((ifp->if_flags & IFF_RUNNING) == 0) 219 1.3.2.2 snj return; 220 1.3.2.2 snj 221 1.3.2.2 snj mii = &sc->sc_miibus; 222 1.3.2.2 snj 223 1.3.2.2 snj sc->ale_flags &= ~ALE_FLAG_LINK; 224 1.3.2.2 snj if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 225 1.3.2.2 snj (IFM_ACTIVE | IFM_AVALID)) { 226 1.3.2.2 snj switch (IFM_SUBTYPE(mii->mii_media_active)) { 227 1.3.2.2 snj case IFM_10_T: 228 1.3.2.2 snj case IFM_100_TX: 229 1.3.2.2 snj sc->ale_flags |= ALE_FLAG_LINK; 230 1.3.2.2 snj break; 231 1.3.2.2 snj 232 1.3.2.2 snj case IFM_1000_T: 233 1.3.2.2 snj if ((sc->ale_flags & ALE_FLAG_FASTETHER) == 0) 234 1.3.2.2 snj sc->ale_flags |= ALE_FLAG_LINK; 235 1.3.2.2 snj break; 236 1.3.2.2 snj 237 1.3.2.2 snj default: 238 1.3.2.2 snj break; 239 1.3.2.2 snj } 240 1.3.2.2 snj } 241 1.3.2.2 snj 242 1.3.2.2 snj /* Stop Rx/Tx MACs. */ 243 1.3.2.2 snj ale_stop_mac(sc); 244 1.3.2.2 snj 245 1.3.2.2 snj /* Program MACs with resolved speed/duplex/flow-control. */ 246 1.3.2.2 snj if ((sc->ale_flags & ALE_FLAG_LINK) != 0) { 247 1.3.2.2 snj ale_mac_config(sc); 248 1.3.2.2 snj /* Reenable Tx/Rx MACs. */ 249 1.3.2.2 snj reg = CSR_READ_4(sc, ALE_MAC_CFG); 250 1.3.2.2 snj reg |= MAC_CFG_TX_ENB | MAC_CFG_RX_ENB; 251 1.3.2.2 snj CSR_WRITE_4(sc, ALE_MAC_CFG, reg); 252 1.3.2.2 snj } 253 1.3.2.2 snj } 254 1.3.2.2 snj 255 1.3.2.2 snj void 256 1.3.2.2 snj ale_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 257 1.3.2.2 snj { 258 1.3.2.2 snj struct ale_softc *sc = ifp->if_softc; 259 1.3.2.2 snj struct mii_data *mii = &sc->sc_miibus; 260 1.3.2.2 snj 261 1.3.2.2 snj mii_pollstat(mii); 262 1.3.2.2 snj ifmr->ifm_status = mii->mii_media_status; 263 1.3.2.2 snj ifmr->ifm_active = mii->mii_media_active; 264 1.3.2.2 snj } 265 1.3.2.2 snj 266 1.3.2.2 snj int 267 1.3.2.2 snj ale_mediachange(struct ifnet *ifp) 268 1.3.2.2 snj { 269 1.3.2.2 snj struct ale_softc *sc = ifp->if_softc; 270 1.3.2.2 snj struct mii_data *mii = &sc->sc_miibus; 271 1.3.2.2 snj int error; 272 1.3.2.2 snj 273 1.3.2.2 snj if (mii->mii_instance != 0) { 274 1.3.2.2 snj struct mii_softc *miisc; 275 1.3.2.2 snj 276 1.3.2.2 snj LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 277 1.3.2.2 snj mii_phy_reset(miisc); 278 1.3.2.2 snj } 279 1.3.2.2 snj error = mii_mediachg(mii); 280 1.3.2.2 snj 281 1.3.2.2 snj return error; 282 1.3.2.2 snj } 283 1.3.2.2 snj 284 1.3.2.2 snj int 285 1.3.2.2 snj ale_match(device_t dev, cfdata_t match, void *aux) 286 1.3.2.2 snj { 287 1.3.2.2 snj struct pci_attach_args *pa = aux; 288 1.3.2.2 snj 289 1.3.2.2 snj return (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_ATTANSIC && 290 1.3.2.2 snj PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_ATTANSIC_ETHERNET_L1E); 291 1.3.2.2 snj } 292 1.3.2.2 snj 293 1.3.2.2 snj void 294 1.3.2.2 snj ale_get_macaddr(struct ale_softc *sc) 295 1.3.2.2 snj { 296 1.3.2.2 snj uint32_t ea[2], reg; 297 1.3.2.2 snj int i, vpdc; 298 1.3.2.2 snj 299 1.3.2.2 snj reg = CSR_READ_4(sc, ALE_SPI_CTRL); 300 1.3.2.2 snj if ((reg & SPI_VPD_ENB) != 0) { 301 1.3.2.2 snj reg &= ~SPI_VPD_ENB; 302 1.3.2.2 snj CSR_WRITE_4(sc, ALE_SPI_CTRL, reg); 303 1.3.2.2 snj } 304 1.3.2.2 snj 305 1.3.2.2 snj if (pci_get_capability(sc->sc_pct, sc->sc_pcitag, PCI_CAP_VPD, 306 1.3.2.2 snj &vpdc, NULL)) { 307 1.3.2.2 snj /* 308 1.3.2.2 snj * PCI VPD capability found, let TWSI reload EEPROM. 309 1.3.2.2 snj * This will set ethernet address of controller. 310 1.3.2.2 snj */ 311 1.3.2.2 snj CSR_WRITE_4(sc, ALE_TWSI_CTRL, CSR_READ_4(sc, ALE_TWSI_CTRL) | 312 1.3.2.2 snj TWSI_CTRL_SW_LD_START); 313 1.3.2.2 snj for (i = 100; i > 0; i--) { 314 1.3.2.2 snj DELAY(1000); 315 1.3.2.2 snj reg = CSR_READ_4(sc, ALE_TWSI_CTRL); 316 1.3.2.2 snj if ((reg & TWSI_CTRL_SW_LD_START) == 0) 317 1.3.2.2 snj break; 318 1.3.2.2 snj } 319 1.3.2.2 snj if (i == 0) 320 1.3.2.2 snj printf("%s: reloading EEPROM timeout!\n", 321 1.3.2.2 snj device_xname(sc->sc_dev)); 322 1.3.2.2 snj } else { 323 1.3.2.2 snj if (aledebug) 324 1.3.2.2 snj printf("%s: PCI VPD capability not found!\n", 325 1.3.2.2 snj device_xname(sc->sc_dev)); 326 1.3.2.2 snj } 327 1.3.2.2 snj 328 1.3.2.2 snj ea[0] = CSR_READ_4(sc, ALE_PAR0); 329 1.3.2.2 snj ea[1] = CSR_READ_4(sc, ALE_PAR1); 330 1.3.2.2 snj sc->ale_eaddr[0] = (ea[1] >> 8) & 0xFF; 331 1.3.2.2 snj sc->ale_eaddr[1] = (ea[1] >> 0) & 0xFF; 332 1.3.2.2 snj sc->ale_eaddr[2] = (ea[0] >> 24) & 0xFF; 333 1.3.2.2 snj sc->ale_eaddr[3] = (ea[0] >> 16) & 0xFF; 334 1.3.2.2 snj sc->ale_eaddr[4] = (ea[0] >> 8) & 0xFF; 335 1.3.2.2 snj sc->ale_eaddr[5] = (ea[0] >> 0) & 0xFF; 336 1.3.2.2 snj } 337 1.3.2.2 snj 338 1.3.2.2 snj void 339 1.3.2.2 snj ale_phy_reset(struct ale_softc *sc) 340 1.3.2.2 snj { 341 1.3.2.2 snj /* Reset magic from Linux. */ 342 1.3.2.2 snj CSR_WRITE_2(sc, ALE_GPHY_CTRL, 343 1.3.2.2 snj GPHY_CTRL_HIB_EN | GPHY_CTRL_HIB_PULSE | GPHY_CTRL_SEL_ANA_RESET | 344 1.3.2.2 snj GPHY_CTRL_PHY_PLL_ON); 345 1.3.2.2 snj DELAY(1000); 346 1.3.2.2 snj CSR_WRITE_2(sc, ALE_GPHY_CTRL, 347 1.3.2.2 snj GPHY_CTRL_EXT_RESET | GPHY_CTRL_HIB_EN | GPHY_CTRL_HIB_PULSE | 348 1.3.2.2 snj GPHY_CTRL_SEL_ANA_RESET | GPHY_CTRL_PHY_PLL_ON); 349 1.3.2.2 snj DELAY(1000); 350 1.3.2.2 snj 351 1.3.2.2 snj #define ATPHY_DBG_ADDR 0x1D 352 1.3.2.2 snj #define ATPHY_DBG_DATA 0x1E 353 1.3.2.2 snj 354 1.3.2.2 snj /* Enable hibernation mode. */ 355 1.3.2.2 snj ale_miibus_writereg(sc->sc_dev, sc->ale_phyaddr, 356 1.3.2.2 snj ATPHY_DBG_ADDR, 0x0B); 357 1.3.2.2 snj ale_miibus_writereg(sc->sc_dev, sc->ale_phyaddr, 358 1.3.2.2 snj ATPHY_DBG_DATA, 0xBC00); 359 1.3.2.2 snj /* Set Class A/B for all modes. */ 360 1.3.2.2 snj ale_miibus_writereg(sc->sc_dev, sc->ale_phyaddr, 361 1.3.2.2 snj ATPHY_DBG_ADDR, 0x00); 362 1.3.2.2 snj ale_miibus_writereg(sc->sc_dev, sc->ale_phyaddr, 363 1.3.2.2 snj ATPHY_DBG_DATA, 0x02EF); 364 1.3.2.2 snj /* Enable 10BT power saving. */ 365 1.3.2.2 snj ale_miibus_writereg(sc->sc_dev, sc->ale_phyaddr, 366 1.3.2.2 snj ATPHY_DBG_ADDR, 0x12); 367 1.3.2.2 snj ale_miibus_writereg(sc->sc_dev, sc->ale_phyaddr, 368 1.3.2.2 snj ATPHY_DBG_DATA, 0x4C04); 369 1.3.2.2 snj /* Adjust 1000T power. */ 370 1.3.2.2 snj ale_miibus_writereg(sc->sc_dev, sc->ale_phyaddr, 371 1.3.2.2 snj ATPHY_DBG_ADDR, 0x04); 372 1.3.2.2 snj ale_miibus_writereg(sc->sc_dev, sc->ale_phyaddr, 373 1.3.2.2 snj ATPHY_DBG_ADDR, 0x8BBB); 374 1.3.2.2 snj /* 10BT center tap voltage. */ 375 1.3.2.2 snj ale_miibus_writereg(sc->sc_dev, sc->ale_phyaddr, 376 1.3.2.2 snj ATPHY_DBG_ADDR, 0x05); 377 1.3.2.2 snj ale_miibus_writereg(sc->sc_dev, sc->ale_phyaddr, 378 1.3.2.2 snj ATPHY_DBG_ADDR, 0x2C46); 379 1.3.2.2 snj 380 1.3.2.2 snj #undef ATPHY_DBG_ADDR 381 1.3.2.2 snj #undef ATPHY_DBG_DATA 382 1.3.2.2 snj DELAY(1000); 383 1.3.2.2 snj } 384 1.3.2.2 snj 385 1.3.2.2 snj void 386 1.3.2.2 snj ale_attach(device_t parent, device_t self, void *aux) 387 1.3.2.2 snj { 388 1.3.2.2 snj struct ale_softc *sc = device_private(self); 389 1.3.2.2 snj struct pci_attach_args *pa = aux; 390 1.3.2.2 snj pci_chipset_tag_t pc = pa->pa_pc; 391 1.3.2.2 snj pci_intr_handle_t ih; 392 1.3.2.2 snj const char *intrstr; 393 1.3.2.2 snj struct ifnet *ifp; 394 1.3.2.2 snj pcireg_t memtype; 395 1.3.2.3 snj int mii_flags, error = 0; 396 1.3.2.2 snj uint32_t rxf_len, txf_len; 397 1.3.2.3 snj const char *chipname; 398 1.3.2.2 snj 399 1.3.2.2 snj aprint_naive("\n"); 400 1.3.2.2 snj aprint_normal(": Attansic/Atheros L1E Ethernet\n"); 401 1.3.2.2 snj 402 1.3.2.2 snj sc->sc_dev = self; 403 1.3.2.2 snj sc->sc_dmat = pa->pa_dmat; 404 1.3.2.2 snj sc->sc_pct = pa->pa_pc; 405 1.3.2.2 snj sc->sc_pcitag = pa->pa_tag; 406 1.3.2.2 snj 407 1.3.2.2 snj /* 408 1.3.2.2 snj * Allocate IO memory 409 1.3.2.2 snj */ 410 1.3.2.2 snj memtype = pci_mapreg_type(sc->sc_pct, sc->sc_pcitag, ALE_PCIR_BAR); 411 1.3.2.2 snj switch (memtype) { 412 1.3.2.2 snj case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 413 1.3.2.2 snj case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT_1M: 414 1.3.2.2 snj case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 415 1.3.2.2 snj break; 416 1.3.2.2 snj default: 417 1.3.2.2 snj aprint_error_dev(self, "invalid base address register\n"); 418 1.3.2.2 snj break; 419 1.3.2.2 snj } 420 1.3.2.2 snj 421 1.3.2.2 snj if (pci_mapreg_map(pa, ALE_PCIR_BAR, memtype, 0, &sc->sc_mem_bt, 422 1.3.2.2 snj &sc->sc_mem_bh, NULL, &sc->sc_mem_size)) { 423 1.3.2.2 snj aprint_error_dev(self, "could not map mem space\n"); 424 1.3.2.2 snj return; 425 1.3.2.2 snj } 426 1.3.2.2 snj 427 1.3.2.2 snj if (pci_intr_map(pa, &ih) != 0) { 428 1.3.2.2 snj aprint_error_dev(self, "could not map interrupt\n"); 429 1.3.2.2 snj goto fail; 430 1.3.2.2 snj } 431 1.3.2.2 snj 432 1.3.2.2 snj /* 433 1.3.2.2 snj * Allocate IRQ 434 1.3.2.2 snj */ 435 1.3.2.2 snj intrstr = pci_intr_string(sc->sc_pct, ih); 436 1.3.2.2 snj sc->sc_irq_handle = pci_intr_establish(pc, ih, IPL_NET, ale_intr, sc); 437 1.3.2.2 snj if (sc->sc_irq_handle == NULL) { 438 1.3.2.2 snj aprint_error_dev(self, "could not establish interrupt"); 439 1.3.2.2 snj if (intrstr != NULL) 440 1.3.2.2 snj aprint_error(" at %s", intrstr); 441 1.3.2.2 snj aprint_error("\n"); 442 1.3.2.2 snj goto fail; 443 1.3.2.2 snj } 444 1.3.2.2 snj 445 1.3.2.2 snj /* Set PHY address. */ 446 1.3.2.2 snj sc->ale_phyaddr = ALE_PHY_ADDR; 447 1.3.2.2 snj 448 1.3.2.2 snj /* Reset PHY. */ 449 1.3.2.2 snj ale_phy_reset(sc); 450 1.3.2.2 snj 451 1.3.2.2 snj /* Reset the ethernet controller. */ 452 1.3.2.2 snj ale_reset(sc); 453 1.3.2.2 snj 454 1.3.2.2 snj /* Get PCI and chip id/revision. */ 455 1.3.2.2 snj sc->ale_rev = PCI_REVISION(pa->pa_class); 456 1.3.2.2 snj if (sc->ale_rev >= 0xF0) { 457 1.3.2.2 snj /* L2E Rev. B. AR8114 */ 458 1.3.2.2 snj sc->ale_flags |= ALE_FLAG_FASTETHER; 459 1.3.2.3 snj chipname = "AR8114 (L2E RevB)"; 460 1.3.2.2 snj } else { 461 1.3.2.2 snj if ((CSR_READ_4(sc, ALE_PHY_STATUS) & PHY_STATUS_100M) != 0) { 462 1.3.2.2 snj /* L1E AR8121 */ 463 1.3.2.2 snj sc->ale_flags |= ALE_FLAG_JUMBO; 464 1.3.2.3 snj chipname = "AR8121 (L1E)"; 465 1.3.2.2 snj } else { 466 1.3.2.2 snj /* L2E Rev. A. AR8113 */ 467 1.3.2.2 snj sc->ale_flags |= ALE_FLAG_FASTETHER; 468 1.3.2.3 snj chipname = "AR8113 (L2E RevA)"; 469 1.3.2.2 snj } 470 1.3.2.2 snj } 471 1.3.2.3 snj aprint_normal_dev(self, "%s, %s\n", chipname, intrstr); 472 1.3.2.2 snj 473 1.3.2.2 snj /* 474 1.3.2.2 snj * All known controllers seems to require 4 bytes alignment 475 1.3.2.2 snj * of Tx buffers to make Tx checksum offload with custom 476 1.3.2.2 snj * checksum generation method work. 477 1.3.2.2 snj */ 478 1.3.2.2 snj sc->ale_flags |= ALE_FLAG_TXCSUM_BUG; 479 1.3.2.2 snj 480 1.3.2.2 snj /* 481 1.3.2.2 snj * All known controllers seems to have issues on Rx checksum 482 1.3.2.2 snj * offload for fragmented IP datagrams. 483 1.3.2.2 snj */ 484 1.3.2.2 snj sc->ale_flags |= ALE_FLAG_RXCSUM_BUG; 485 1.3.2.2 snj 486 1.3.2.2 snj /* 487 1.3.2.2 snj * Don't use Tx CMB. It is known to cause RRS update failure 488 1.3.2.2 snj * under certain circumstances. Typical phenomenon of the 489 1.3.2.2 snj * issue would be unexpected sequence number encountered in 490 1.3.2.2 snj * Rx handler. 491 1.3.2.2 snj */ 492 1.3.2.2 snj sc->ale_flags |= ALE_FLAG_TXCMB_BUG; 493 1.3.2.2 snj sc->ale_chip_rev = CSR_READ_4(sc, ALE_MASTER_CFG) >> 494 1.3.2.2 snj MASTER_CHIP_REV_SHIFT; 495 1.3.2.2 snj aprint_debug_dev(self, "PCI device revision : 0x%04x\n", sc->ale_rev); 496 1.3.2.2 snj aprint_debug_dev(self, "Chip id/revision : 0x%04x\n", sc->ale_chip_rev); 497 1.3.2.2 snj 498 1.3.2.2 snj /* 499 1.3.2.2 snj * Uninitialized hardware returns an invalid chip id/revision 500 1.3.2.2 snj * as well as 0xFFFFFFFF for Tx/Rx fifo length. 501 1.3.2.2 snj */ 502 1.3.2.2 snj txf_len = CSR_READ_4(sc, ALE_SRAM_TX_FIFO_LEN); 503 1.3.2.2 snj rxf_len = CSR_READ_4(sc, ALE_SRAM_RX_FIFO_LEN); 504 1.3.2.2 snj if (sc->ale_chip_rev == 0xFFFF || txf_len == 0xFFFFFFFF || 505 1.3.2.2 snj rxf_len == 0xFFFFFFF) { 506 1.3.2.2 snj aprint_error_dev(self, "chip revision : 0x%04x, %u Tx FIFO " 507 1.3.2.2 snj "%u Rx FIFO -- not initialized?\n", 508 1.3.2.2 snj sc->ale_chip_rev, txf_len, rxf_len); 509 1.3.2.2 snj goto fail; 510 1.3.2.2 snj } 511 1.3.2.2 snj 512 1.3.2.2 snj if (aledebug) { 513 1.3.2.2 snj printf("%s: %u Tx FIFO, %u Rx FIFO\n", device_xname(sc->sc_dev), 514 1.3.2.2 snj txf_len, rxf_len); 515 1.3.2.2 snj } 516 1.3.2.2 snj 517 1.3.2.2 snj /* Set max allowable DMA size. */ 518 1.3.2.2 snj sc->ale_dma_rd_burst = DMA_CFG_RD_BURST_128; 519 1.3.2.2 snj sc->ale_dma_wr_burst = DMA_CFG_WR_BURST_128; 520 1.3.2.2 snj 521 1.3.2.2 snj callout_init(&sc->sc_tick_ch, 0); 522 1.3.2.2 snj callout_setfunc(&sc->sc_tick_ch, ale_tick, sc); 523 1.3.2.2 snj 524 1.3.2.2 snj error = ale_dma_alloc(sc); 525 1.3.2.2 snj if (error) 526 1.3.2.2 snj goto fail; 527 1.3.2.2 snj 528 1.3.2.2 snj /* Load station address. */ 529 1.3.2.2 snj ale_get_macaddr(sc); 530 1.3.2.2 snj 531 1.3.2.2 snj aprint_normal_dev(self, "Ethernet address %s\n", 532 1.3.2.2 snj ether_sprintf(sc->ale_eaddr)); 533 1.3.2.2 snj 534 1.3.2.2 snj ifp = &sc->sc_ec.ec_if; 535 1.3.2.2 snj ifp->if_softc = sc; 536 1.3.2.2 snj ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 537 1.3.2.2 snj ifp->if_init = ale_init; 538 1.3.2.2 snj ifp->if_ioctl = ale_ioctl; 539 1.3.2.2 snj ifp->if_start = ale_start; 540 1.3.2.2 snj ifp->if_stop = ale_stop; 541 1.3.2.2 snj ifp->if_watchdog = ale_watchdog; 542 1.3.2.2 snj IFQ_SET_MAXLEN(&ifp->if_snd, ALE_TX_RING_CNT - 1); 543 1.3.2.2 snj IFQ_SET_READY(&ifp->if_snd); 544 1.3.2.2 snj strlcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 545 1.3.2.2 snj 546 1.3.2.2 snj sc->sc_ec.ec_capabilities = ETHERCAP_VLAN_MTU; 547 1.3.2.2 snj 548 1.3.2.2 snj #ifdef ALE_CHECKSUM 549 1.3.2.2 snj ifp->if_capabilities |= IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 550 1.3.2.2 snj IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 551 1.3.2.2 snj IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_TCPv4_Rx; 552 1.3.2.2 snj #endif 553 1.3.2.2 snj 554 1.3.2.2 snj #if NVLAN > 0 555 1.3.2.2 snj sc->sc_ec.ec_capabilities |= ETHERCAP_VLAN_HWTAGGING; 556 1.3.2.2 snj #endif 557 1.3.2.2 snj 558 1.3.2.2 snj /* Set up MII bus. */ 559 1.3.2.2 snj sc->sc_miibus.mii_ifp = ifp; 560 1.3.2.2 snj sc->sc_miibus.mii_readreg = ale_miibus_readreg; 561 1.3.2.2 snj sc->sc_miibus.mii_writereg = ale_miibus_writereg; 562 1.3.2.2 snj sc->sc_miibus.mii_statchg = ale_miibus_statchg; 563 1.3.2.2 snj 564 1.3.2.2 snj sc->sc_ec.ec_mii = &sc->sc_miibus; 565 1.3.2.2 snj ifmedia_init(&sc->sc_miibus.mii_media, 0, ale_mediachange, 566 1.3.2.2 snj ale_mediastatus); 567 1.3.2.3 snj mii_flags = 0; 568 1.3.2.3 snj if ((sc->ale_flags & ALE_FLAG_JUMBO) != 0) 569 1.3.2.3 snj mii_flags |= MIIF_DOPAUSE; 570 1.3.2.2 snj mii_attach(self, &sc->sc_miibus, 0xffffffff, MII_PHY_ANY, 571 1.3.2.3 snj MII_OFFSET_ANY, mii_flags); 572 1.3.2.2 snj 573 1.3.2.2 snj if (LIST_FIRST(&sc->sc_miibus.mii_phys) == NULL) { 574 1.3.2.2 snj aprint_error_dev(self, "no PHY found!\n"); 575 1.3.2.2 snj ifmedia_add(&sc->sc_miibus.mii_media, IFM_ETHER | IFM_MANUAL, 576 1.3.2.2 snj 0, NULL); 577 1.3.2.2 snj ifmedia_set(&sc->sc_miibus.mii_media, IFM_ETHER | IFM_MANUAL); 578 1.3.2.2 snj } else 579 1.3.2.2 snj ifmedia_set(&sc->sc_miibus.mii_media, IFM_ETHER | IFM_AUTO); 580 1.3.2.2 snj 581 1.3.2.2 snj if_attach(ifp); 582 1.3.2.2 snj ether_ifattach(ifp, sc->ale_eaddr); 583 1.3.2.2 snj 584 1.3.2.2 snj if (!pmf_device_register(self, NULL, NULL)) 585 1.3.2.2 snj aprint_error_dev(self, "couldn't establish power handler\n"); 586 1.3.2.2 snj else 587 1.3.2.2 snj pmf_class_network_register(self, ifp); 588 1.3.2.2 snj 589 1.3.2.2 snj return; 590 1.3.2.2 snj fail: 591 1.3.2.2 snj ale_dma_free(sc); 592 1.3.2.2 snj if (sc->sc_irq_handle != NULL) { 593 1.3.2.2 snj pci_intr_disestablish(pc, sc->sc_irq_handle); 594 1.3.2.2 snj sc->sc_irq_handle = NULL; 595 1.3.2.2 snj } 596 1.3.2.2 snj if (sc->sc_mem_size) { 597 1.3.2.2 snj bus_space_unmap(sc->sc_mem_bt, sc->sc_mem_bh, sc->sc_mem_size); 598 1.3.2.2 snj sc->sc_mem_size = 0; 599 1.3.2.2 snj } 600 1.3.2.2 snj } 601 1.3.2.2 snj 602 1.3.2.2 snj static int 603 1.3.2.2 snj ale_detach(device_t self, int flags) 604 1.3.2.2 snj { 605 1.3.2.2 snj struct ale_softc *sc = device_private(self); 606 1.3.2.2 snj struct ifnet *ifp = &sc->sc_ec.ec_if; 607 1.3.2.2 snj int s; 608 1.3.2.2 snj 609 1.3.2.2 snj pmf_device_deregister(self); 610 1.3.2.2 snj s = splnet(); 611 1.3.2.2 snj ale_stop(ifp, 0); 612 1.3.2.2 snj splx(s); 613 1.3.2.2 snj 614 1.3.2.2 snj mii_detach(&sc->sc_miibus, MII_PHY_ANY, MII_OFFSET_ANY); 615 1.3.2.2 snj 616 1.3.2.2 snj /* Delete all remaining media. */ 617 1.3.2.2 snj ifmedia_delete_instance(&sc->sc_miibus.mii_media, IFM_INST_ANY); 618 1.3.2.2 snj 619 1.3.2.2 snj ether_ifdetach(ifp); 620 1.3.2.2 snj if_detach(ifp); 621 1.3.2.2 snj ale_dma_free(sc); 622 1.3.2.2 snj 623 1.3.2.2 snj if (sc->sc_irq_handle != NULL) { 624 1.3.2.2 snj pci_intr_disestablish(sc->sc_pct, sc->sc_irq_handle); 625 1.3.2.2 snj sc->sc_irq_handle = NULL; 626 1.3.2.2 snj } 627 1.3.2.2 snj if (sc->sc_mem_size) { 628 1.3.2.2 snj bus_space_unmap(sc->sc_mem_bt, sc->sc_mem_bh, sc->sc_mem_size); 629 1.3.2.2 snj sc->sc_mem_size = 0; 630 1.3.2.2 snj } 631 1.3.2.2 snj 632 1.3.2.2 snj return 0; 633 1.3.2.2 snj } 634 1.3.2.2 snj 635 1.3.2.2 snj 636 1.3.2.2 snj static int 637 1.3.2.2 snj ale_dma_alloc(struct ale_softc *sc) 638 1.3.2.2 snj { 639 1.3.2.2 snj struct ale_txdesc *txd; 640 1.3.2.2 snj int nsegs, error, guard_size, i; 641 1.3.2.2 snj 642 1.3.2.2 snj if ((sc->ale_flags & ALE_FLAG_JUMBO) != 0) 643 1.3.2.2 snj guard_size = ALE_JUMBO_FRAMELEN; 644 1.3.2.2 snj else 645 1.3.2.2 snj guard_size = ALE_MAX_FRAMELEN; 646 1.3.2.2 snj sc->ale_pagesize = roundup(guard_size + ALE_RX_PAGE_SZ, 647 1.3.2.2 snj ALE_RX_PAGE_ALIGN); 648 1.3.2.2 snj 649 1.3.2.2 snj /* 650 1.3.2.2 snj * Create DMA stuffs for TX ring 651 1.3.2.2 snj */ 652 1.3.2.2 snj error = bus_dmamap_create(sc->sc_dmat, ALE_TX_RING_SZ, 1, 653 1.3.2.2 snj ALE_TX_RING_SZ, 0, BUS_DMA_NOWAIT, &sc->ale_cdata.ale_tx_ring_map); 654 1.3.2.2 snj if (error) { 655 1.3.2.2 snj sc->ale_cdata.ale_tx_ring_map = NULL; 656 1.3.2.2 snj return ENOBUFS; 657 1.3.2.2 snj } 658 1.3.2.2 snj 659 1.3.2.2 snj /* Allocate DMA'able memory for TX ring */ 660 1.3.2.2 snj error = bus_dmamem_alloc(sc->sc_dmat, ALE_TX_RING_SZ, 661 1.3.2.2 snj 0, 0, &sc->ale_cdata.ale_tx_ring_seg, 1, 662 1.3.2.2 snj &nsegs, BUS_DMA_WAITOK); 663 1.3.2.2 snj if (error) { 664 1.3.2.2 snj printf("%s: could not allocate DMA'able memory for Tx ring, " 665 1.3.2.2 snj "error = %i\n", device_xname(sc->sc_dev), error); 666 1.3.2.2 snj return error; 667 1.3.2.2 snj } 668 1.3.2.2 snj 669 1.3.2.2 snj error = bus_dmamem_map(sc->sc_dmat, &sc->ale_cdata.ale_tx_ring_seg, 670 1.3.2.2 snj nsegs, ALE_TX_RING_SZ, (void **)&sc->ale_cdata.ale_tx_ring, 671 1.3.2.2 snj BUS_DMA_NOWAIT); 672 1.3.2.2 snj if (error) 673 1.3.2.2 snj return ENOBUFS; 674 1.3.2.2 snj 675 1.3.2.2 snj memset(sc->ale_cdata.ale_tx_ring, 0, ALE_TX_RING_SZ); 676 1.3.2.2 snj 677 1.3.2.2 snj /* Load the DMA map for Tx ring. */ 678 1.3.2.2 snj error = bus_dmamap_load(sc->sc_dmat, sc->ale_cdata.ale_tx_ring_map, 679 1.3.2.2 snj sc->ale_cdata.ale_tx_ring, ALE_TX_RING_SZ, NULL, BUS_DMA_WAITOK); 680 1.3.2.2 snj if (error) { 681 1.3.2.2 snj printf("%s: could not load DMA'able memory for Tx ring.\n", 682 1.3.2.2 snj device_xname(sc->sc_dev)); 683 1.3.2.2 snj bus_dmamem_free(sc->sc_dmat, 684 1.3.2.2 snj &sc->ale_cdata.ale_tx_ring_seg, 1); 685 1.3.2.2 snj return error; 686 1.3.2.2 snj } 687 1.3.2.2 snj sc->ale_cdata.ale_tx_ring_paddr = 688 1.3.2.2 snj sc->ale_cdata.ale_tx_ring_map->dm_segs[0].ds_addr; 689 1.3.2.2 snj 690 1.3.2.2 snj for (i = 0; i < ALE_RX_PAGES; i++) { 691 1.3.2.2 snj /* 692 1.3.2.2 snj * Create DMA stuffs for RX pages 693 1.3.2.2 snj */ 694 1.3.2.2 snj error = bus_dmamap_create(sc->sc_dmat, sc->ale_pagesize, 1, 695 1.3.2.2 snj sc->ale_pagesize, 0, BUS_DMA_NOWAIT, 696 1.3.2.2 snj &sc->ale_cdata.ale_rx_page[i].page_map); 697 1.3.2.2 snj if (error) { 698 1.3.2.2 snj sc->ale_cdata.ale_rx_page[i].page_map = NULL; 699 1.3.2.2 snj return ENOBUFS; 700 1.3.2.2 snj } 701 1.3.2.2 snj 702 1.3.2.2 snj /* Allocate DMA'able memory for RX pages */ 703 1.3.2.2 snj error = bus_dmamem_alloc(sc->sc_dmat, sc->ale_pagesize, 704 1.3.2.2 snj ETHER_ALIGN, 0, &sc->ale_cdata.ale_rx_page[i].page_seg, 705 1.3.2.2 snj 1, &nsegs, BUS_DMA_WAITOK); 706 1.3.2.2 snj if (error) { 707 1.3.2.2 snj printf("%s: could not allocate DMA'able memory for " 708 1.3.2.2 snj "Rx ring.\n", device_xname(sc->sc_dev)); 709 1.3.2.2 snj return error; 710 1.3.2.2 snj } 711 1.3.2.2 snj error = bus_dmamem_map(sc->sc_dmat, 712 1.3.2.2 snj &sc->ale_cdata.ale_rx_page[i].page_seg, nsegs, 713 1.3.2.2 snj sc->ale_pagesize, 714 1.3.2.2 snj (void **)&sc->ale_cdata.ale_rx_page[i].page_addr, 715 1.3.2.2 snj BUS_DMA_NOWAIT); 716 1.3.2.2 snj if (error) 717 1.3.2.2 snj return ENOBUFS; 718 1.3.2.2 snj 719 1.3.2.2 snj memset(sc->ale_cdata.ale_rx_page[i].page_addr, 0, 720 1.3.2.2 snj sc->ale_pagesize); 721 1.3.2.2 snj 722 1.3.2.2 snj /* Load the DMA map for Rx pages. */ 723 1.3.2.2 snj error = bus_dmamap_load(sc->sc_dmat, 724 1.3.2.2 snj sc->ale_cdata.ale_rx_page[i].page_map, 725 1.3.2.2 snj sc->ale_cdata.ale_rx_page[i].page_addr, 726 1.3.2.2 snj sc->ale_pagesize, NULL, BUS_DMA_WAITOK); 727 1.3.2.2 snj if (error) { 728 1.3.2.2 snj printf("%s: could not load DMA'able memory for " 729 1.3.2.2 snj "Rx pages.\n", device_xname(sc->sc_dev)); 730 1.3.2.2 snj bus_dmamem_free(sc->sc_dmat, 731 1.3.2.2 snj &sc->ale_cdata.ale_rx_page[i].page_seg, 1); 732 1.3.2.2 snj return error; 733 1.3.2.2 snj } 734 1.3.2.2 snj sc->ale_cdata.ale_rx_page[i].page_paddr = 735 1.3.2.2 snj sc->ale_cdata.ale_rx_page[i].page_map->dm_segs[0].ds_addr; 736 1.3.2.2 snj } 737 1.3.2.2 snj 738 1.3.2.2 snj /* 739 1.3.2.2 snj * Create DMA stuffs for Tx CMB. 740 1.3.2.2 snj */ 741 1.3.2.2 snj error = bus_dmamap_create(sc->sc_dmat, ALE_TX_CMB_SZ, 1, 742 1.3.2.2 snj ALE_TX_CMB_SZ, 0, BUS_DMA_NOWAIT, &sc->ale_cdata.ale_tx_cmb_map); 743 1.3.2.2 snj if (error) { 744 1.3.2.2 snj sc->ale_cdata.ale_tx_cmb_map = NULL; 745 1.3.2.2 snj return ENOBUFS; 746 1.3.2.2 snj } 747 1.3.2.2 snj 748 1.3.2.2 snj /* Allocate DMA'able memory for Tx CMB. */ 749 1.3.2.2 snj error = bus_dmamem_alloc(sc->sc_dmat, ALE_TX_CMB_SZ, ETHER_ALIGN, 0, 750 1.3.2.2 snj &sc->ale_cdata.ale_tx_cmb_seg, 1, &nsegs, BUS_DMA_WAITOK); 751 1.3.2.2 snj 752 1.3.2.2 snj if (error) { 753 1.3.2.2 snj printf("%s: could not allocate DMA'able memory for Tx CMB.\n", 754 1.3.2.2 snj device_xname(sc->sc_dev)); 755 1.3.2.2 snj return error; 756 1.3.2.2 snj } 757 1.3.2.2 snj 758 1.3.2.2 snj error = bus_dmamem_map(sc->sc_dmat, &sc->ale_cdata.ale_tx_cmb_seg, 759 1.3.2.2 snj nsegs, ALE_TX_CMB_SZ, (void **)&sc->ale_cdata.ale_tx_cmb, 760 1.3.2.2 snj BUS_DMA_NOWAIT); 761 1.3.2.2 snj if (error) 762 1.3.2.2 snj return ENOBUFS; 763 1.3.2.2 snj 764 1.3.2.2 snj memset(sc->ale_cdata.ale_tx_cmb, 0, ALE_TX_CMB_SZ); 765 1.3.2.2 snj 766 1.3.2.2 snj /* Load the DMA map for Tx CMB. */ 767 1.3.2.2 snj error = bus_dmamap_load(sc->sc_dmat, sc->ale_cdata.ale_tx_cmb_map, 768 1.3.2.2 snj sc->ale_cdata.ale_tx_cmb, ALE_TX_CMB_SZ, NULL, BUS_DMA_WAITOK); 769 1.3.2.2 snj if (error) { 770 1.3.2.2 snj printf("%s: could not load DMA'able memory for Tx CMB.\n", 771 1.3.2.2 snj device_xname(sc->sc_dev)); 772 1.3.2.2 snj bus_dmamem_free(sc->sc_dmat, 773 1.3.2.2 snj &sc->ale_cdata.ale_tx_cmb_seg, 1); 774 1.3.2.2 snj return error; 775 1.3.2.2 snj } 776 1.3.2.2 snj 777 1.3.2.2 snj sc->ale_cdata.ale_tx_cmb_paddr = 778 1.3.2.2 snj sc->ale_cdata.ale_tx_cmb_map->dm_segs[0].ds_addr; 779 1.3.2.2 snj 780 1.3.2.2 snj for (i = 0; i < ALE_RX_PAGES; i++) { 781 1.3.2.2 snj /* 782 1.3.2.2 snj * Create DMA stuffs for Rx CMB. 783 1.3.2.2 snj */ 784 1.3.2.2 snj error = bus_dmamap_create(sc->sc_dmat, ALE_RX_CMB_SZ, 1, 785 1.3.2.2 snj ALE_RX_CMB_SZ, 0, BUS_DMA_NOWAIT, 786 1.3.2.2 snj &sc->ale_cdata.ale_rx_page[i].cmb_map); 787 1.3.2.2 snj if (error) { 788 1.3.2.2 snj sc->ale_cdata.ale_rx_page[i].cmb_map = NULL; 789 1.3.2.2 snj return ENOBUFS; 790 1.3.2.2 snj } 791 1.3.2.2 snj 792 1.3.2.2 snj /* Allocate DMA'able memory for Rx CMB */ 793 1.3.2.2 snj error = bus_dmamem_alloc(sc->sc_dmat, ALE_RX_CMB_SZ, 794 1.3.2.2 snj ETHER_ALIGN, 0, &sc->ale_cdata.ale_rx_page[i].cmb_seg, 1, 795 1.3.2.2 snj &nsegs, BUS_DMA_WAITOK); 796 1.3.2.2 snj if (error) { 797 1.3.2.2 snj printf("%s: could not allocate DMA'able memory for " 798 1.3.2.2 snj "Rx CMB\n", device_xname(sc->sc_dev)); 799 1.3.2.2 snj return error; 800 1.3.2.2 snj } 801 1.3.2.2 snj error = bus_dmamem_map(sc->sc_dmat, 802 1.3.2.2 snj &sc->ale_cdata.ale_rx_page[i].cmb_seg, nsegs, 803 1.3.2.2 snj ALE_RX_CMB_SZ, 804 1.3.2.2 snj (void **)&sc->ale_cdata.ale_rx_page[i].cmb_addr, 805 1.3.2.2 snj BUS_DMA_NOWAIT); 806 1.3.2.2 snj if (error) 807 1.3.2.2 snj return ENOBUFS; 808 1.3.2.2 snj 809 1.3.2.2 snj memset(sc->ale_cdata.ale_rx_page[i].cmb_addr, 0, ALE_RX_CMB_SZ); 810 1.3.2.2 snj 811 1.3.2.2 snj /* Load the DMA map for Rx CMB */ 812 1.3.2.2 snj error = bus_dmamap_load(sc->sc_dmat, 813 1.3.2.2 snj sc->ale_cdata.ale_rx_page[i].cmb_map, 814 1.3.2.2 snj sc->ale_cdata.ale_rx_page[i].cmb_addr, 815 1.3.2.2 snj ALE_RX_CMB_SZ, NULL, BUS_DMA_WAITOK); 816 1.3.2.2 snj if (error) { 817 1.3.2.2 snj printf("%s: could not load DMA'able memory for Rx CMB" 818 1.3.2.2 snj "\n", device_xname(sc->sc_dev)); 819 1.3.2.2 snj bus_dmamem_free(sc->sc_dmat, 820 1.3.2.2 snj &sc->ale_cdata.ale_rx_page[i].cmb_seg, 1); 821 1.3.2.2 snj return error; 822 1.3.2.2 snj } 823 1.3.2.2 snj sc->ale_cdata.ale_rx_page[i].cmb_paddr = 824 1.3.2.2 snj sc->ale_cdata.ale_rx_page[i].cmb_map->dm_segs[0].ds_addr; 825 1.3.2.2 snj } 826 1.3.2.2 snj 827 1.3.2.2 snj 828 1.3.2.2 snj /* Create DMA maps for Tx buffers. */ 829 1.3.2.2 snj for (i = 0; i < ALE_TX_RING_CNT; i++) { 830 1.3.2.2 snj txd = &sc->ale_cdata.ale_txdesc[i]; 831 1.3.2.2 snj txd->tx_m = NULL; 832 1.3.2.2 snj txd->tx_dmamap = NULL; 833 1.3.2.2 snj error = bus_dmamap_create(sc->sc_dmat, ALE_TSO_MAXSIZE, 834 1.3.2.2 snj ALE_MAXTXSEGS, ALE_TSO_MAXSEGSIZE, 0, BUS_DMA_NOWAIT, 835 1.3.2.2 snj &txd->tx_dmamap); 836 1.3.2.2 snj if (error) { 837 1.3.2.2 snj txd->tx_dmamap = NULL; 838 1.3.2.2 snj printf("%s: could not create Tx dmamap.\n", 839 1.3.2.2 snj device_xname(sc->sc_dev)); 840 1.3.2.2 snj return error; 841 1.3.2.2 snj } 842 1.3.2.2 snj } 843 1.3.2.2 snj 844 1.3.2.2 snj return 0; 845 1.3.2.2 snj } 846 1.3.2.2 snj 847 1.3.2.2 snj static void 848 1.3.2.2 snj ale_dma_free(struct ale_softc *sc) 849 1.3.2.2 snj { 850 1.3.2.2 snj struct ale_txdesc *txd; 851 1.3.2.2 snj int i; 852 1.3.2.2 snj 853 1.3.2.2 snj /* Tx buffers. */ 854 1.3.2.2 snj for (i = 0; i < ALE_TX_RING_CNT; i++) { 855 1.3.2.2 snj txd = &sc->ale_cdata.ale_txdesc[i]; 856 1.3.2.2 snj if (txd->tx_dmamap != NULL) { 857 1.3.2.2 snj bus_dmamap_destroy(sc->sc_dmat, txd->tx_dmamap); 858 1.3.2.2 snj txd->tx_dmamap = NULL; 859 1.3.2.2 snj } 860 1.3.2.2 snj } 861 1.3.2.2 snj 862 1.3.2.2 snj /* Tx descriptor ring. */ 863 1.3.2.2 snj if (sc->ale_cdata.ale_tx_ring_map != NULL) 864 1.3.2.2 snj bus_dmamap_unload(sc->sc_dmat, sc->ale_cdata.ale_tx_ring_map); 865 1.3.2.2 snj if (sc->ale_cdata.ale_tx_ring_map != NULL && 866 1.3.2.2 snj sc->ale_cdata.ale_tx_ring != NULL) 867 1.3.2.2 snj bus_dmamem_free(sc->sc_dmat, 868 1.3.2.2 snj &sc->ale_cdata.ale_tx_ring_seg, 1); 869 1.3.2.2 snj sc->ale_cdata.ale_tx_ring = NULL; 870 1.3.2.2 snj sc->ale_cdata.ale_tx_ring_map = NULL; 871 1.3.2.2 snj 872 1.3.2.2 snj /* Rx page block. */ 873 1.3.2.2 snj for (i = 0; i < ALE_RX_PAGES; i++) { 874 1.3.2.2 snj if (sc->ale_cdata.ale_rx_page[i].page_map != NULL) 875 1.3.2.2 snj bus_dmamap_unload(sc->sc_dmat, 876 1.3.2.2 snj sc->ale_cdata.ale_rx_page[i].page_map); 877 1.3.2.2 snj if (sc->ale_cdata.ale_rx_page[i].page_map != NULL && 878 1.3.2.2 snj sc->ale_cdata.ale_rx_page[i].page_addr != NULL) 879 1.3.2.2 snj bus_dmamem_free(sc->sc_dmat, 880 1.3.2.2 snj &sc->ale_cdata.ale_rx_page[i].page_seg, 1); 881 1.3.2.2 snj sc->ale_cdata.ale_rx_page[i].page_addr = NULL; 882 1.3.2.2 snj sc->ale_cdata.ale_rx_page[i].page_map = NULL; 883 1.3.2.2 snj } 884 1.3.2.2 snj 885 1.3.2.2 snj /* Rx CMB. */ 886 1.3.2.2 snj for (i = 0; i < ALE_RX_PAGES; i++) { 887 1.3.2.2 snj if (sc->ale_cdata.ale_rx_page[i].cmb_map != NULL) 888 1.3.2.2 snj bus_dmamap_unload(sc->sc_dmat, 889 1.3.2.2 snj sc->ale_cdata.ale_rx_page[i].cmb_map); 890 1.3.2.2 snj if (sc->ale_cdata.ale_rx_page[i].cmb_map != NULL && 891 1.3.2.2 snj sc->ale_cdata.ale_rx_page[i].cmb_addr != NULL) 892 1.3.2.2 snj bus_dmamem_free(sc->sc_dmat, 893 1.3.2.2 snj &sc->ale_cdata.ale_rx_page[i].cmb_seg, 1); 894 1.3.2.2 snj sc->ale_cdata.ale_rx_page[i].cmb_addr = NULL; 895 1.3.2.2 snj sc->ale_cdata.ale_rx_page[i].cmb_map = NULL; 896 1.3.2.2 snj } 897 1.3.2.2 snj 898 1.3.2.2 snj /* Tx CMB. */ 899 1.3.2.2 snj if (sc->ale_cdata.ale_tx_cmb_map != NULL) 900 1.3.2.2 snj bus_dmamap_unload(sc->sc_dmat, sc->ale_cdata.ale_tx_cmb_map); 901 1.3.2.2 snj if (sc->ale_cdata.ale_tx_cmb_map != NULL && 902 1.3.2.2 snj sc->ale_cdata.ale_tx_cmb != NULL) 903 1.3.2.2 snj bus_dmamem_free(sc->sc_dmat, 904 1.3.2.2 snj &sc->ale_cdata.ale_tx_cmb_seg, 1); 905 1.3.2.2 snj sc->ale_cdata.ale_tx_cmb = NULL; 906 1.3.2.2 snj sc->ale_cdata.ale_tx_cmb_map = NULL; 907 1.3.2.2 snj 908 1.3.2.2 snj } 909 1.3.2.2 snj 910 1.3.2.2 snj static int 911 1.3.2.2 snj ale_encap(struct ale_softc *sc, struct mbuf **m_head) 912 1.3.2.2 snj { 913 1.3.2.2 snj struct ale_txdesc *txd, *txd_last; 914 1.3.2.2 snj struct tx_desc *desc; 915 1.3.2.2 snj struct mbuf *m; 916 1.3.2.2 snj bus_dmamap_t map; 917 1.3.2.2 snj uint32_t cflags, poff, vtag; 918 1.3.2.2 snj int error, i, nsegs, prod; 919 1.3.2.2 snj #if NVLAN > 0 920 1.3.2.2 snj struct m_tag *mtag; 921 1.3.2.2 snj #endif 922 1.3.2.2 snj 923 1.3.2.2 snj m = *m_head; 924 1.3.2.2 snj cflags = vtag = 0; 925 1.3.2.2 snj poff = 0; 926 1.3.2.2 snj 927 1.3.2.2 snj prod = sc->ale_cdata.ale_tx_prod; 928 1.3.2.2 snj txd = &sc->ale_cdata.ale_txdesc[prod]; 929 1.3.2.2 snj txd_last = txd; 930 1.3.2.2 snj map = txd->tx_dmamap; 931 1.3.2.2 snj 932 1.3.2.2 snj error = bus_dmamap_load_mbuf(sc->sc_dmat, map, *m_head, BUS_DMA_NOWAIT); 933 1.3.2.2 snj if (error == EFBIG) { 934 1.3.2.2 snj error = 0; 935 1.3.2.2 snj 936 1.3.2.2 snj MGETHDR(m, M_DONTWAIT, MT_DATA); 937 1.3.2.2 snj if (m == NULL) { 938 1.3.2.2 snj printf("%s: can't defrag TX mbuf\n", 939 1.3.2.2 snj device_xname(sc->sc_dev)); 940 1.3.2.2 snj m_freem(*m_head); 941 1.3.2.2 snj *m_head = NULL; 942 1.3.2.2 snj return ENOBUFS; 943 1.3.2.2 snj } 944 1.3.2.2 snj 945 1.3.2.2 snj M_COPY_PKTHDR(m, *m_head); 946 1.3.2.2 snj if ((*m_head)->m_pkthdr.len > MHLEN) { 947 1.3.2.2 snj MCLGET(m, M_DONTWAIT); 948 1.3.2.2 snj if (!(m->m_flags & M_EXT)) { 949 1.3.2.2 snj m_freem(*m_head); 950 1.3.2.2 snj m_freem(m); 951 1.3.2.2 snj *m_head = NULL; 952 1.3.2.2 snj return ENOBUFS; 953 1.3.2.2 snj } 954 1.3.2.2 snj } 955 1.3.2.2 snj m_copydata(*m_head, 0, (*m_head)->m_pkthdr.len, 956 1.3.2.2 snj mtod(m, void *)); 957 1.3.2.2 snj m_freem(*m_head); 958 1.3.2.2 snj m->m_len = m->m_pkthdr.len; 959 1.3.2.2 snj *m_head = m; 960 1.3.2.2 snj 961 1.3.2.2 snj error = bus_dmamap_load_mbuf(sc->sc_dmat, map, *m_head, 962 1.3.2.2 snj BUS_DMA_NOWAIT); 963 1.3.2.2 snj 964 1.3.2.2 snj if (error != 0) { 965 1.3.2.2 snj printf("%s: could not load defragged TX mbuf\n", 966 1.3.2.2 snj device_xname(sc->sc_dev)); 967 1.3.2.2 snj if (!error) { 968 1.3.2.2 snj bus_dmamap_unload(sc->sc_dmat, map); 969 1.3.2.2 snj error = EFBIG; 970 1.3.2.2 snj } 971 1.3.2.2 snj m_freem(*m_head); 972 1.3.2.2 snj *m_head = NULL; 973 1.3.2.2 snj return error; 974 1.3.2.2 snj } 975 1.3.2.2 snj } else if (error) { 976 1.3.2.2 snj printf("%s: could not load TX mbuf\n", device_xname(sc->sc_dev)); 977 1.3.2.2 snj return error; 978 1.3.2.2 snj } 979 1.3.2.2 snj 980 1.3.2.2 snj nsegs = map->dm_nsegs; 981 1.3.2.2 snj 982 1.3.2.2 snj if (nsegs == 0) { 983 1.3.2.2 snj m_freem(*m_head); 984 1.3.2.2 snj *m_head = NULL; 985 1.3.2.2 snj return EIO; 986 1.3.2.2 snj } 987 1.3.2.2 snj 988 1.3.2.2 snj /* Check descriptor overrun. */ 989 1.3.2.2 snj if (sc->ale_cdata.ale_tx_cnt + nsegs >= ALE_TX_RING_CNT - 2) { 990 1.3.2.2 snj bus_dmamap_unload(sc->sc_dmat, map); 991 1.3.2.2 snj return ENOBUFS; 992 1.3.2.2 snj } 993 1.3.2.2 snj bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 994 1.3.2.2 snj BUS_DMASYNC_PREWRITE); 995 1.3.2.2 snj 996 1.3.2.2 snj m = *m_head; 997 1.3.2.2 snj /* Configure Tx checksum offload. */ 998 1.3.2.2 snj if ((m->m_pkthdr.csum_flags & ALE_CSUM_FEATURES) != 0) { 999 1.3.2.2 snj /* 1000 1.3.2.2 snj * AR81xx supports Tx custom checksum offload feature 1001 1.3.2.2 snj * that offloads single 16bit checksum computation. 1002 1.3.2.2 snj * So you can choose one among IP, TCP and UDP. 1003 1.3.2.2 snj * Normally driver sets checksum start/insertion 1004 1.3.2.2 snj * position from the information of TCP/UDP frame as 1005 1.3.2.2 snj * TCP/UDP checksum takes more time than that of IP. 1006 1.3.2.2 snj * However it seems that custom checksum offload 1007 1.3.2.2 snj * requires 4 bytes aligned Tx buffers due to hardware 1008 1.3.2.2 snj * bug. 1009 1.3.2.2 snj * AR81xx also supports explicit Tx checksum computation 1010 1.3.2.2 snj * if it is told that the size of IP header and TCP 1011 1.3.2.2 snj * header(for UDP, the header size does not matter 1012 1.3.2.2 snj * because it's fixed length). However with this scheme 1013 1.3.2.2 snj * TSO does not work so you have to choose one either 1014 1.3.2.2 snj * TSO or explicit Tx checksum offload. I chosen TSO 1015 1.3.2.2 snj * plus custom checksum offload with work-around which 1016 1.3.2.2 snj * will cover most common usage for this consumer 1017 1.3.2.2 snj * ethernet controller. The work-around takes a lot of 1018 1.3.2.2 snj * CPU cycles if Tx buffer is not aligned on 4 bytes 1019 1.3.2.2 snj * boundary, though. 1020 1.3.2.2 snj */ 1021 1.3.2.2 snj cflags |= ALE_TD_CXSUM; 1022 1.3.2.2 snj /* Set checksum start offset. */ 1023 1.3.2.2 snj cflags |= (poff << ALE_TD_CSUM_PLOADOFFSET_SHIFT); 1024 1.3.2.2 snj } 1025 1.3.2.2 snj 1026 1.3.2.2 snj #if NVLAN > 0 1027 1.3.2.2 snj /* Configure VLAN hardware tag insertion. */ 1028 1.3.2.2 snj if ((mtag = VLAN_OUTPUT_TAG(&sc->sc_ec, m))) { 1029 1.3.2.2 snj vtag = ALE_TX_VLAN_TAG(htons(VLAN_TAG_VALUE(mtag))); 1030 1.3.2.2 snj vtag = ((vtag << ALE_TD_VLAN_SHIFT) & ALE_TD_VLAN_MASK); 1031 1.3.2.2 snj cflags |= ALE_TD_INSERT_VLAN_TAG; 1032 1.3.2.2 snj } 1033 1.3.2.2 snj #endif 1034 1.3.2.2 snj 1035 1.3.2.2 snj desc = NULL; 1036 1.3.2.2 snj for (i = 0; i < nsegs; i++) { 1037 1.3.2.2 snj desc = &sc->ale_cdata.ale_tx_ring[prod]; 1038 1.3.2.2 snj desc->addr = htole64(map->dm_segs[i].ds_addr); 1039 1.3.2.2 snj desc->len = 1040 1.3.2.2 snj htole32(ALE_TX_BYTES(map->dm_segs[i].ds_len) | vtag); 1041 1.3.2.2 snj desc->flags = htole32(cflags); 1042 1.3.2.2 snj sc->ale_cdata.ale_tx_cnt++; 1043 1.3.2.2 snj ALE_DESC_INC(prod, ALE_TX_RING_CNT); 1044 1.3.2.2 snj } 1045 1.3.2.2 snj /* Update producer index. */ 1046 1.3.2.2 snj sc->ale_cdata.ale_tx_prod = prod; 1047 1.3.2.2 snj 1048 1.3.2.2 snj /* Finally set EOP on the last descriptor. */ 1049 1.3.2.2 snj prod = (prod + ALE_TX_RING_CNT - 1) % ALE_TX_RING_CNT; 1050 1.3.2.2 snj desc = &sc->ale_cdata.ale_tx_ring[prod]; 1051 1.3.2.2 snj desc->flags |= htole32(ALE_TD_EOP); 1052 1.3.2.2 snj 1053 1.3.2.2 snj /* Swap dmamap of the first and the last. */ 1054 1.3.2.2 snj txd = &sc->ale_cdata.ale_txdesc[prod]; 1055 1.3.2.2 snj map = txd_last->tx_dmamap; 1056 1.3.2.2 snj txd_last->tx_dmamap = txd->tx_dmamap; 1057 1.3.2.2 snj txd->tx_dmamap = map; 1058 1.3.2.2 snj txd->tx_m = m; 1059 1.3.2.2 snj 1060 1.3.2.2 snj /* Sync descriptors. */ 1061 1.3.2.2 snj bus_dmamap_sync(sc->sc_dmat, sc->ale_cdata.ale_tx_ring_map, 0, 1062 1.3.2.2 snj sc->ale_cdata.ale_tx_ring_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 1063 1.3.2.2 snj 1064 1.3.2.2 snj return 0; 1065 1.3.2.2 snj } 1066 1.3.2.2 snj 1067 1.3.2.2 snj static void 1068 1.3.2.2 snj ale_start(struct ifnet *ifp) 1069 1.3.2.2 snj { 1070 1.3.2.2 snj struct ale_softc *sc = ifp->if_softc; 1071 1.3.2.2 snj struct mbuf *m_head; 1072 1.3.2.2 snj int enq; 1073 1.3.2.2 snj 1074 1.3.2.2 snj if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 1075 1.3.2.2 snj return; 1076 1.3.2.2 snj 1077 1.3.2.2 snj /* Reclaim transmitted frames. */ 1078 1.3.2.2 snj if (sc->ale_cdata.ale_tx_cnt >= ALE_TX_DESC_HIWAT) 1079 1.3.2.2 snj ale_txeof(sc); 1080 1.3.2.2 snj 1081 1.3.2.2 snj enq = 0; 1082 1.3.2.2 snj for (;;) { 1083 1.3.2.2 snj IFQ_DEQUEUE(&ifp->if_snd, m_head); 1084 1.3.2.2 snj if (m_head == NULL) 1085 1.3.2.2 snj break; 1086 1.3.2.2 snj 1087 1.3.2.2 snj /* 1088 1.3.2.2 snj * Pack the data into the transmit ring. If we 1089 1.3.2.2 snj * don't have room, set the OACTIVE flag and wait 1090 1.3.2.2 snj * for the NIC to drain the ring. 1091 1.3.2.2 snj */ 1092 1.3.2.2 snj if (ale_encap(sc, &m_head)) { 1093 1.3.2.2 snj if (m_head == NULL) 1094 1.3.2.2 snj break; 1095 1.3.2.2 snj ifp->if_flags |= IFF_OACTIVE; 1096 1.3.2.2 snj break; 1097 1.3.2.2 snj } 1098 1.3.2.2 snj enq = 1; 1099 1.3.2.2 snj 1100 1.3.2.2 snj #if NBPFILTER > 0 1101 1.3.2.2 snj /* 1102 1.3.2.2 snj * If there's a BPF listener, bounce a copy of this frame 1103 1.3.2.2 snj * to him. 1104 1.3.2.2 snj */ 1105 1.3.2.2 snj if (ifp->if_bpf != NULL) 1106 1.3.2.2 snj bpf_mtap(ifp->if_bpf, m_head); 1107 1.3.2.2 snj #endif 1108 1.3.2.2 snj } 1109 1.3.2.2 snj 1110 1.3.2.2 snj if (enq) { 1111 1.3.2.2 snj /* Kick. */ 1112 1.3.2.2 snj CSR_WRITE_4(sc, ALE_MBOX_TPD_PROD_IDX, 1113 1.3.2.2 snj sc->ale_cdata.ale_tx_prod); 1114 1.3.2.2 snj 1115 1.3.2.2 snj /* Set a timeout in case the chip goes out to lunch. */ 1116 1.3.2.2 snj ifp->if_timer = ALE_TX_TIMEOUT; 1117 1.3.2.2 snj } 1118 1.3.2.2 snj } 1119 1.3.2.2 snj 1120 1.3.2.2 snj static void 1121 1.3.2.2 snj ale_watchdog(struct ifnet *ifp) 1122 1.3.2.2 snj { 1123 1.3.2.2 snj struct ale_softc *sc = ifp->if_softc; 1124 1.3.2.2 snj 1125 1.3.2.2 snj if ((sc->ale_flags & ALE_FLAG_LINK) == 0) { 1126 1.3.2.2 snj printf("%s: watchdog timeout (missed link)\n", 1127 1.3.2.2 snj device_xname(sc->sc_dev)); 1128 1.3.2.2 snj ifp->if_oerrors++; 1129 1.3.2.2 snj ale_init(ifp); 1130 1.3.2.2 snj return; 1131 1.3.2.2 snj } 1132 1.3.2.2 snj 1133 1.3.2.2 snj printf("%s: watchdog timeout\n", device_xname(sc->sc_dev)); 1134 1.3.2.2 snj ifp->if_oerrors++; 1135 1.3.2.2 snj ale_init(ifp); 1136 1.3.2.2 snj 1137 1.3.2.2 snj if (!IFQ_IS_EMPTY(&ifp->if_snd)) 1138 1.3.2.2 snj ale_start(ifp); 1139 1.3.2.2 snj } 1140 1.3.2.2 snj 1141 1.3.2.2 snj static int 1142 1.3.2.2 snj ale_ioctl(struct ifnet *ifp, u_long cmd, void *data) 1143 1.3.2.2 snj { 1144 1.3.2.2 snj struct ale_softc *sc = ifp->if_softc; 1145 1.3.2.2 snj int s, error; 1146 1.3.2.2 snj 1147 1.3.2.2 snj s = splnet(); 1148 1.3.2.2 snj 1149 1.3.2.2 snj error = ether_ioctl(ifp, cmd, data); 1150 1.3.2.2 snj if (error == ENETRESET) { 1151 1.3.2.2 snj if (ifp->if_flags & IFF_RUNNING) 1152 1.3.2.2 snj ale_rxfilter(sc); 1153 1.3.2.2 snj error = 0; 1154 1.3.2.2 snj } 1155 1.3.2.2 snj 1156 1.3.2.2 snj splx(s); 1157 1.3.2.2 snj return error; 1158 1.3.2.2 snj } 1159 1.3.2.2 snj 1160 1.3.2.2 snj static void 1161 1.3.2.2 snj ale_mac_config(struct ale_softc *sc) 1162 1.3.2.2 snj { 1163 1.3.2.2 snj struct mii_data *mii; 1164 1.3.2.2 snj uint32_t reg; 1165 1.3.2.2 snj 1166 1.3.2.2 snj mii = &sc->sc_miibus; 1167 1.3.2.2 snj reg = CSR_READ_4(sc, ALE_MAC_CFG); 1168 1.3.2.2 snj reg &= ~(MAC_CFG_FULL_DUPLEX | MAC_CFG_TX_FC | MAC_CFG_RX_FC | 1169 1.3.2.2 snj MAC_CFG_SPEED_MASK); 1170 1.3.2.2 snj 1171 1.3.2.2 snj /* Reprogram MAC with resolved speed/duplex. */ 1172 1.3.2.2 snj switch (IFM_SUBTYPE(mii->mii_media_active)) { 1173 1.3.2.2 snj case IFM_10_T: 1174 1.3.2.2 snj case IFM_100_TX: 1175 1.3.2.2 snj reg |= MAC_CFG_SPEED_10_100; 1176 1.3.2.2 snj break; 1177 1.3.2.2 snj case IFM_1000_T: 1178 1.3.2.2 snj reg |= MAC_CFG_SPEED_1000; 1179 1.3.2.2 snj break; 1180 1.3.2.2 snj } 1181 1.3.2.2 snj if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 1182 1.3.2.2 snj reg |= MAC_CFG_FULL_DUPLEX; 1183 1.3.2.2 snj if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0) 1184 1.3.2.2 snj reg |= MAC_CFG_TX_FC; 1185 1.3.2.2 snj if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0) 1186 1.3.2.2 snj reg |= MAC_CFG_RX_FC; 1187 1.3.2.2 snj } 1188 1.3.2.2 snj CSR_WRITE_4(sc, ALE_MAC_CFG, reg); 1189 1.3.2.2 snj } 1190 1.3.2.2 snj 1191 1.3.2.2 snj static void 1192 1.3.2.2 snj ale_stats_clear(struct ale_softc *sc) 1193 1.3.2.2 snj { 1194 1.3.2.2 snj struct smb sb; 1195 1.3.2.2 snj uint32_t *reg; 1196 1.3.2.2 snj int i; 1197 1.3.2.2 snj 1198 1.3.2.2 snj for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered; reg++) { 1199 1.3.2.2 snj CSR_READ_4(sc, ALE_RX_MIB_BASE + i); 1200 1.3.2.2 snj i += sizeof(uint32_t); 1201 1.3.2.2 snj } 1202 1.3.2.2 snj /* Read Tx statistics. */ 1203 1.3.2.2 snj for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes; reg++) { 1204 1.3.2.2 snj CSR_READ_4(sc, ALE_TX_MIB_BASE + i); 1205 1.3.2.2 snj i += sizeof(uint32_t); 1206 1.3.2.2 snj } 1207 1.3.2.2 snj } 1208 1.3.2.2 snj 1209 1.3.2.2 snj static void 1210 1.3.2.2 snj ale_stats_update(struct ale_softc *sc) 1211 1.3.2.2 snj { 1212 1.3.2.2 snj struct ifnet *ifp = &sc->sc_ec.ec_if; 1213 1.3.2.2 snj struct ale_hw_stats *stat; 1214 1.3.2.2 snj struct smb sb, *smb; 1215 1.3.2.2 snj uint32_t *reg; 1216 1.3.2.2 snj int i; 1217 1.3.2.2 snj 1218 1.3.2.2 snj stat = &sc->ale_stats; 1219 1.3.2.2 snj smb = &sb; 1220 1.3.2.2 snj 1221 1.3.2.2 snj /* Read Rx statistics. */ 1222 1.3.2.2 snj for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered; reg++) { 1223 1.3.2.2 snj *reg = CSR_READ_4(sc, ALE_RX_MIB_BASE + i); 1224 1.3.2.2 snj i += sizeof(uint32_t); 1225 1.3.2.2 snj } 1226 1.3.2.2 snj /* Read Tx statistics. */ 1227 1.3.2.2 snj for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes; reg++) { 1228 1.3.2.2 snj *reg = CSR_READ_4(sc, ALE_TX_MIB_BASE + i); 1229 1.3.2.2 snj i += sizeof(uint32_t); 1230 1.3.2.2 snj } 1231 1.3.2.2 snj 1232 1.3.2.2 snj /* Rx stats. */ 1233 1.3.2.2 snj stat->rx_frames += smb->rx_frames; 1234 1.3.2.2 snj stat->rx_bcast_frames += smb->rx_bcast_frames; 1235 1.3.2.2 snj stat->rx_mcast_frames += smb->rx_mcast_frames; 1236 1.3.2.2 snj stat->rx_pause_frames += smb->rx_pause_frames; 1237 1.3.2.2 snj stat->rx_control_frames += smb->rx_control_frames; 1238 1.3.2.2 snj stat->rx_crcerrs += smb->rx_crcerrs; 1239 1.3.2.2 snj stat->rx_lenerrs += smb->rx_lenerrs; 1240 1.3.2.2 snj stat->rx_bytes += smb->rx_bytes; 1241 1.3.2.2 snj stat->rx_runts += smb->rx_runts; 1242 1.3.2.2 snj stat->rx_fragments += smb->rx_fragments; 1243 1.3.2.2 snj stat->rx_pkts_64 += smb->rx_pkts_64; 1244 1.3.2.2 snj stat->rx_pkts_65_127 += smb->rx_pkts_65_127; 1245 1.3.2.2 snj stat->rx_pkts_128_255 += smb->rx_pkts_128_255; 1246 1.3.2.2 snj stat->rx_pkts_256_511 += smb->rx_pkts_256_511; 1247 1.3.2.2 snj stat->rx_pkts_512_1023 += smb->rx_pkts_512_1023; 1248 1.3.2.2 snj stat->rx_pkts_1024_1518 += smb->rx_pkts_1024_1518; 1249 1.3.2.2 snj stat->rx_pkts_1519_max += smb->rx_pkts_1519_max; 1250 1.3.2.2 snj stat->rx_pkts_truncated += smb->rx_pkts_truncated; 1251 1.3.2.2 snj stat->rx_fifo_oflows += smb->rx_fifo_oflows; 1252 1.3.2.2 snj stat->rx_rrs_errs += smb->rx_rrs_errs; 1253 1.3.2.2 snj stat->rx_alignerrs += smb->rx_alignerrs; 1254 1.3.2.2 snj stat->rx_bcast_bytes += smb->rx_bcast_bytes; 1255 1.3.2.2 snj stat->rx_mcast_bytes += smb->rx_mcast_bytes; 1256 1.3.2.2 snj stat->rx_pkts_filtered += smb->rx_pkts_filtered; 1257 1.3.2.2 snj 1258 1.3.2.2 snj /* Tx stats. */ 1259 1.3.2.2 snj stat->tx_frames += smb->tx_frames; 1260 1.3.2.2 snj stat->tx_bcast_frames += smb->tx_bcast_frames; 1261 1.3.2.2 snj stat->tx_mcast_frames += smb->tx_mcast_frames; 1262 1.3.2.2 snj stat->tx_pause_frames += smb->tx_pause_frames; 1263 1.3.2.2 snj stat->tx_excess_defer += smb->tx_excess_defer; 1264 1.3.2.2 snj stat->tx_control_frames += smb->tx_control_frames; 1265 1.3.2.2 snj stat->tx_deferred += smb->tx_deferred; 1266 1.3.2.2 snj stat->tx_bytes += smb->tx_bytes; 1267 1.3.2.2 snj stat->tx_pkts_64 += smb->tx_pkts_64; 1268 1.3.2.2 snj stat->tx_pkts_65_127 += smb->tx_pkts_65_127; 1269 1.3.2.2 snj stat->tx_pkts_128_255 += smb->tx_pkts_128_255; 1270 1.3.2.2 snj stat->tx_pkts_256_511 += smb->tx_pkts_256_511; 1271 1.3.2.2 snj stat->tx_pkts_512_1023 += smb->tx_pkts_512_1023; 1272 1.3.2.2 snj stat->tx_pkts_1024_1518 += smb->tx_pkts_1024_1518; 1273 1.3.2.2 snj stat->tx_pkts_1519_max += smb->tx_pkts_1519_max; 1274 1.3.2.2 snj stat->tx_single_colls += smb->tx_single_colls; 1275 1.3.2.2 snj stat->tx_multi_colls += smb->tx_multi_colls; 1276 1.3.2.2 snj stat->tx_late_colls += smb->tx_late_colls; 1277 1.3.2.2 snj stat->tx_excess_colls += smb->tx_excess_colls; 1278 1.3.2.2 snj stat->tx_abort += smb->tx_abort; 1279 1.3.2.2 snj stat->tx_underrun += smb->tx_underrun; 1280 1.3.2.2 snj stat->tx_desc_underrun += smb->tx_desc_underrun; 1281 1.3.2.2 snj stat->tx_lenerrs += smb->tx_lenerrs; 1282 1.3.2.2 snj stat->tx_pkts_truncated += smb->tx_pkts_truncated; 1283 1.3.2.2 snj stat->tx_bcast_bytes += smb->tx_bcast_bytes; 1284 1.3.2.2 snj stat->tx_mcast_bytes += smb->tx_mcast_bytes; 1285 1.3.2.2 snj 1286 1.3.2.2 snj /* Update counters in ifnet. */ 1287 1.3.2.2 snj ifp->if_opackets += smb->tx_frames; 1288 1.3.2.2 snj 1289 1.3.2.2 snj ifp->if_collisions += smb->tx_single_colls + 1290 1.3.2.2 snj smb->tx_multi_colls * 2 + smb->tx_late_colls + 1291 1.3.2.2 snj smb->tx_abort * HDPX_CFG_RETRY_DEFAULT; 1292 1.3.2.2 snj 1293 1.3.2.2 snj /* 1294 1.3.2.2 snj * XXX 1295 1.3.2.2 snj * tx_pkts_truncated counter looks suspicious. It constantly 1296 1.3.2.2 snj * increments with no sign of Tx errors. This may indicate 1297 1.3.2.2 snj * the counter name is not correct one so I've removed the 1298 1.3.2.2 snj * counter in output errors. 1299 1.3.2.2 snj */ 1300 1.3.2.2 snj ifp->if_oerrors += smb->tx_abort + smb->tx_late_colls + 1301 1.3.2.2 snj smb->tx_underrun; 1302 1.3.2.2 snj 1303 1.3.2.2 snj ifp->if_ipackets += smb->rx_frames; 1304 1.3.2.2 snj 1305 1.3.2.2 snj ifp->if_ierrors += smb->rx_crcerrs + smb->rx_lenerrs + 1306 1.3.2.2 snj smb->rx_runts + smb->rx_pkts_truncated + 1307 1.3.2.2 snj smb->rx_fifo_oflows + smb->rx_rrs_errs + 1308 1.3.2.2 snj smb->rx_alignerrs; 1309 1.3.2.2 snj } 1310 1.3.2.2 snj 1311 1.3.2.2 snj static int 1312 1.3.2.2 snj ale_intr(void *xsc) 1313 1.3.2.2 snj { 1314 1.3.2.2 snj struct ale_softc *sc = xsc; 1315 1.3.2.2 snj struct ifnet *ifp = &sc->sc_ec.ec_if; 1316 1.3.2.2 snj uint32_t status; 1317 1.3.2.2 snj 1318 1.3.2.2 snj status = CSR_READ_4(sc, ALE_INTR_STATUS); 1319 1.3.2.2 snj if ((status & ALE_INTRS) == 0) 1320 1.3.2.2 snj return 0; 1321 1.3.2.2 snj 1322 1.3.2.2 snj /* Acknowledge and disable interrupts. */ 1323 1.3.2.2 snj CSR_WRITE_4(sc, ALE_INTR_STATUS, status | INTR_DIS_INT); 1324 1.3.2.2 snj 1325 1.3.2.2 snj if (ifp->if_flags & IFF_RUNNING) { 1326 1.3.2.2 snj int error; 1327 1.3.2.2 snj 1328 1.3.2.2 snj error = ale_rxeof(sc); 1329 1.3.2.2 snj if (error) { 1330 1.3.2.2 snj sc->ale_stats.reset_brk_seq++; 1331 1.3.2.2 snj ale_init(ifp); 1332 1.3.2.2 snj return 0; 1333 1.3.2.2 snj } 1334 1.3.2.2 snj 1335 1.3.2.2 snj if (status & (INTR_DMA_RD_TO_RST | INTR_DMA_WR_TO_RST)) { 1336 1.3.2.2 snj if (status & INTR_DMA_RD_TO_RST) 1337 1.3.2.2 snj printf("%s: DMA read error! -- resetting\n", 1338 1.3.2.2 snj device_xname(sc->sc_dev)); 1339 1.3.2.2 snj if (status & INTR_DMA_WR_TO_RST) 1340 1.3.2.2 snj printf("%s: DMA write error! -- resetting\n", 1341 1.3.2.2 snj device_xname(sc->sc_dev)); 1342 1.3.2.2 snj ale_init(ifp); 1343 1.3.2.2 snj return 0; 1344 1.3.2.2 snj } 1345 1.3.2.2 snj 1346 1.3.2.2 snj ale_txeof(sc); 1347 1.3.2.2 snj if (!IFQ_IS_EMPTY(&ifp->if_snd)) 1348 1.3.2.2 snj ale_start(ifp); 1349 1.3.2.2 snj } 1350 1.3.2.2 snj 1351 1.3.2.2 snj /* Re-enable interrupts. */ 1352 1.3.2.2 snj CSR_WRITE_4(sc, ALE_INTR_STATUS, 0x7FFFFFFF); 1353 1.3.2.2 snj return 1; 1354 1.3.2.2 snj } 1355 1.3.2.2 snj 1356 1.3.2.2 snj static void 1357 1.3.2.2 snj ale_txeof(struct ale_softc *sc) 1358 1.3.2.2 snj { 1359 1.3.2.2 snj struct ifnet *ifp = &sc->sc_ec.ec_if; 1360 1.3.2.2 snj struct ale_txdesc *txd; 1361 1.3.2.2 snj uint32_t cons, prod; 1362 1.3.2.2 snj int prog; 1363 1.3.2.2 snj 1364 1.3.2.2 snj if (sc->ale_cdata.ale_tx_cnt == 0) 1365 1.3.2.2 snj return; 1366 1.3.2.2 snj 1367 1.3.2.2 snj bus_dmamap_sync(sc->sc_dmat, sc->ale_cdata.ale_tx_ring_map, 0, 1368 1.3.2.2 snj sc->ale_cdata.ale_tx_ring_map->dm_mapsize, BUS_DMASYNC_POSTREAD); 1369 1.3.2.2 snj if ((sc->ale_flags & ALE_FLAG_TXCMB_BUG) == 0) { 1370 1.3.2.2 snj bus_dmamap_sync(sc->sc_dmat, sc->ale_cdata.ale_tx_cmb_map, 0, 1371 1.3.2.2 snj sc->ale_cdata.ale_tx_cmb_map->dm_mapsize, 1372 1.3.2.2 snj BUS_DMASYNC_POSTREAD); 1373 1.3.2.2 snj prod = *sc->ale_cdata.ale_tx_cmb & TPD_CNT_MASK; 1374 1.3.2.2 snj } else 1375 1.3.2.2 snj prod = CSR_READ_2(sc, ALE_TPD_CONS_IDX); 1376 1.3.2.2 snj cons = sc->ale_cdata.ale_tx_cons; 1377 1.3.2.2 snj /* 1378 1.3.2.2 snj * Go through our Tx list and free mbufs for those 1379 1.3.2.2 snj * frames which have been transmitted. 1380 1.3.2.2 snj */ 1381 1.3.2.2 snj for (prog = 0; cons != prod; prog++, 1382 1.3.2.2 snj ALE_DESC_INC(cons, ALE_TX_RING_CNT)) { 1383 1.3.2.2 snj if (sc->ale_cdata.ale_tx_cnt <= 0) 1384 1.3.2.2 snj break; 1385 1.3.2.2 snj prog++; 1386 1.3.2.2 snj ifp->if_flags &= ~IFF_OACTIVE; 1387 1.3.2.2 snj sc->ale_cdata.ale_tx_cnt--; 1388 1.3.2.2 snj txd = &sc->ale_cdata.ale_txdesc[cons]; 1389 1.3.2.2 snj if (txd->tx_m != NULL) { 1390 1.3.2.2 snj /* Reclaim transmitted mbufs. */ 1391 1.3.2.2 snj bus_dmamap_unload(sc->sc_dmat, txd->tx_dmamap); 1392 1.3.2.2 snj m_freem(txd->tx_m); 1393 1.3.2.2 snj txd->tx_m = NULL; 1394 1.3.2.2 snj } 1395 1.3.2.2 snj } 1396 1.3.2.2 snj 1397 1.3.2.2 snj if (prog > 0) { 1398 1.3.2.2 snj sc->ale_cdata.ale_tx_cons = cons; 1399 1.3.2.2 snj /* 1400 1.3.2.2 snj * Unarm watchdog timer only when there is no pending 1401 1.3.2.2 snj * Tx descriptors in queue. 1402 1.3.2.2 snj */ 1403 1.3.2.2 snj if (sc->ale_cdata.ale_tx_cnt == 0) 1404 1.3.2.2 snj ifp->if_timer = 0; 1405 1.3.2.2 snj } 1406 1.3.2.2 snj } 1407 1.3.2.2 snj 1408 1.3.2.2 snj static void 1409 1.3.2.2 snj ale_rx_update_page(struct ale_softc *sc, struct ale_rx_page **page, 1410 1.3.2.2 snj uint32_t length, uint32_t *prod) 1411 1.3.2.2 snj { 1412 1.3.2.2 snj struct ale_rx_page *rx_page; 1413 1.3.2.2 snj 1414 1.3.2.2 snj rx_page = *page; 1415 1.3.2.2 snj /* Update consumer position. */ 1416 1.3.2.2 snj rx_page->cons += roundup(length + sizeof(struct rx_rs), 1417 1.3.2.2 snj ALE_RX_PAGE_ALIGN); 1418 1.3.2.2 snj if (rx_page->cons >= ALE_RX_PAGE_SZ) { 1419 1.3.2.2 snj /* 1420 1.3.2.2 snj * End of Rx page reached, let hardware reuse 1421 1.3.2.2 snj * this page. 1422 1.3.2.2 snj */ 1423 1.3.2.2 snj rx_page->cons = 0; 1424 1.3.2.2 snj *rx_page->cmb_addr = 0; 1425 1.3.2.2 snj bus_dmamap_sync(sc->sc_dmat, rx_page->cmb_map, 0, 1426 1.3.2.2 snj rx_page->cmb_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 1427 1.3.2.2 snj CSR_WRITE_1(sc, ALE_RXF0_PAGE0 + sc->ale_cdata.ale_rx_curp, 1428 1.3.2.2 snj RXF_VALID); 1429 1.3.2.2 snj /* Switch to alternate Rx page. */ 1430 1.3.2.2 snj sc->ale_cdata.ale_rx_curp ^= 1; 1431 1.3.2.2 snj rx_page = *page = 1432 1.3.2.2 snj &sc->ale_cdata.ale_rx_page[sc->ale_cdata.ale_rx_curp]; 1433 1.3.2.2 snj /* Page flipped, sync CMB and Rx page. */ 1434 1.3.2.2 snj bus_dmamap_sync(sc->sc_dmat, rx_page->page_map, 0, 1435 1.3.2.2 snj rx_page->page_map->dm_mapsize, BUS_DMASYNC_POSTREAD); 1436 1.3.2.2 snj bus_dmamap_sync(sc->sc_dmat, rx_page->cmb_map, 0, 1437 1.3.2.2 snj rx_page->cmb_map->dm_mapsize, BUS_DMASYNC_POSTREAD); 1438 1.3.2.2 snj /* Sync completed, cache updated producer index. */ 1439 1.3.2.2 snj *prod = *rx_page->cmb_addr; 1440 1.3.2.2 snj } 1441 1.3.2.2 snj } 1442 1.3.2.2 snj 1443 1.3.2.2 snj 1444 1.3.2.2 snj /* 1445 1.3.2.2 snj * It seems that AR81xx controller can compute partial checksum. 1446 1.3.2.2 snj * The partial checksum value can be used to accelerate checksum 1447 1.3.2.2 snj * computation for fragmented TCP/UDP packets. Upper network stack 1448 1.3.2.2 snj * already takes advantage of the partial checksum value in IP 1449 1.3.2.2 snj * reassembly stage. But I'm not sure the correctness of the 1450 1.3.2.2 snj * partial hardware checksum assistance due to lack of data sheet. 1451 1.3.2.2 snj * In addition, the Rx feature of controller that requires copying 1452 1.3.2.2 snj * for every frames effectively nullifies one of most nice offload 1453 1.3.2.2 snj * capability of controller. 1454 1.3.2.2 snj */ 1455 1.3.2.2 snj static void 1456 1.3.2.2 snj ale_rxcsum(struct ale_softc *sc, struct mbuf *m, uint32_t status) 1457 1.3.2.2 snj { 1458 1.3.2.2 snj if (status & ALE_RD_IPCSUM_NOK) 1459 1.3.2.2 snj m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 1460 1.3.2.2 snj 1461 1.3.2.2 snj if ((sc->ale_flags & ALE_FLAG_RXCSUM_BUG) == 0) { 1462 1.3.2.2 snj if (((status & ALE_RD_IPV4_FRAG) == 0) && 1463 1.3.2.2 snj ((status & (ALE_RD_TCP | ALE_RD_UDP)) != 0) && 1464 1.3.2.2 snj (status & ALE_RD_TCP_UDPCSUM_NOK)) 1465 1.3.2.2 snj { 1466 1.3.2.2 snj m->m_pkthdr.csum_flags |= M_CSUM_TCP_UDP_BAD; 1467 1.3.2.2 snj } 1468 1.3.2.2 snj } else { 1469 1.3.2.2 snj if ((status & (ALE_RD_TCP | ALE_RD_UDP)) != 0) { 1470 1.3.2.2 snj if (status & ALE_RD_TCP_UDPCSUM_NOK) { 1471 1.3.2.2 snj m->m_pkthdr.csum_flags |= M_CSUM_TCP_UDP_BAD; 1472 1.3.2.2 snj } 1473 1.3.2.2 snj } 1474 1.3.2.2 snj } 1475 1.3.2.2 snj /* 1476 1.3.2.2 snj * Don't mark bad checksum for TCP/UDP frames 1477 1.3.2.2 snj * as fragmented frames may always have set 1478 1.3.2.2 snj * bad checksummed bit of frame status. 1479 1.3.2.2 snj */ 1480 1.3.2.2 snj } 1481 1.3.2.2 snj 1482 1.3.2.2 snj /* Process received frames. */ 1483 1.3.2.2 snj static int 1484 1.3.2.2 snj ale_rxeof(struct ale_softc *sc) 1485 1.3.2.2 snj { 1486 1.3.2.2 snj struct ifnet *ifp = &sc->sc_ec.ec_if; 1487 1.3.2.2 snj struct ale_rx_page *rx_page; 1488 1.3.2.2 snj struct rx_rs *rs; 1489 1.3.2.2 snj struct mbuf *m; 1490 1.3.2.2 snj uint32_t length, prod, seqno, status; 1491 1.3.2.2 snj int prog; 1492 1.3.2.2 snj 1493 1.3.2.2 snj rx_page = &sc->ale_cdata.ale_rx_page[sc->ale_cdata.ale_rx_curp]; 1494 1.3.2.2 snj bus_dmamap_sync(sc->sc_dmat, rx_page->cmb_map, 0, 1495 1.3.2.2 snj rx_page->cmb_map->dm_mapsize, BUS_DMASYNC_POSTREAD); 1496 1.3.2.2 snj bus_dmamap_sync(sc->sc_dmat, rx_page->page_map, 0, 1497 1.3.2.2 snj rx_page->page_map->dm_mapsize, BUS_DMASYNC_POSTREAD); 1498 1.3.2.2 snj /* 1499 1.3.2.2 snj * Don't directly access producer index as hardware may 1500 1.3.2.2 snj * update it while Rx handler is in progress. It would 1501 1.3.2.2 snj * be even better if there is a way to let hardware 1502 1.3.2.2 snj * know how far driver processed its received frames. 1503 1.3.2.2 snj * Alternatively, hardware could provide a way to disable 1504 1.3.2.2 snj * CMB updates until driver acknowledges the end of CMB 1505 1.3.2.2 snj * access. 1506 1.3.2.2 snj */ 1507 1.3.2.2 snj prod = *rx_page->cmb_addr; 1508 1.3.2.2 snj for (prog = 0; ; prog++) { 1509 1.3.2.2 snj if (rx_page->cons >= prod) 1510 1.3.2.2 snj break; 1511 1.3.2.2 snj rs = (struct rx_rs *)(rx_page->page_addr + rx_page->cons); 1512 1.3.2.2 snj seqno = ALE_RX_SEQNO(le32toh(rs->seqno)); 1513 1.3.2.2 snj if (sc->ale_cdata.ale_rx_seqno != seqno) { 1514 1.3.2.2 snj /* 1515 1.3.2.2 snj * Normally I believe this should not happen unless 1516 1.3.2.2 snj * severe driver bug or corrupted memory. However 1517 1.3.2.2 snj * it seems to happen under certain conditions which 1518 1.3.2.2 snj * is triggered by abrupt Rx events such as initiation 1519 1.3.2.2 snj * of bulk transfer of remote host. It's not easy to 1520 1.3.2.2 snj * reproduce this and I doubt it could be related 1521 1.3.2.2 snj * with FIFO overflow of hardware or activity of Tx 1522 1.3.2.2 snj * CMB updates. I also remember similar behaviour 1523 1.3.2.2 snj * seen on RealTek 8139 which uses resembling Rx 1524 1.3.2.2 snj * scheme. 1525 1.3.2.2 snj */ 1526 1.3.2.2 snj if (aledebug) 1527 1.3.2.2 snj printf("%s: garbled seq: %u, expected: %u -- " 1528 1.3.2.2 snj "resetting!\n", device_xname(sc->sc_dev), 1529 1.3.2.2 snj seqno, sc->ale_cdata.ale_rx_seqno); 1530 1.3.2.2 snj return EIO; 1531 1.3.2.2 snj } 1532 1.3.2.2 snj /* Frame received. */ 1533 1.3.2.2 snj sc->ale_cdata.ale_rx_seqno++; 1534 1.3.2.2 snj length = ALE_RX_BYTES(le32toh(rs->length)); 1535 1.3.2.2 snj status = le32toh(rs->flags); 1536 1.3.2.2 snj if (status & ALE_RD_ERROR) { 1537 1.3.2.2 snj /* 1538 1.3.2.2 snj * We want to pass the following frames to upper 1539 1.3.2.2 snj * layer regardless of error status of Rx return 1540 1.3.2.2 snj * status. 1541 1.3.2.2 snj * 1542 1.3.2.2 snj * o IP/TCP/UDP checksum is bad. 1543 1.3.2.2 snj * o frame length and protocol specific length 1544 1.3.2.2 snj * does not match. 1545 1.3.2.2 snj */ 1546 1.3.2.2 snj if (status & (ALE_RD_CRC | ALE_RD_CODE | 1547 1.3.2.2 snj ALE_RD_DRIBBLE | ALE_RD_RUNT | ALE_RD_OFLOW | 1548 1.3.2.2 snj ALE_RD_TRUNC)) { 1549 1.3.2.2 snj ale_rx_update_page(sc, &rx_page, length, &prod); 1550 1.3.2.2 snj continue; 1551 1.3.2.2 snj } 1552 1.3.2.2 snj } 1553 1.3.2.2 snj /* 1554 1.3.2.2 snj * m_devget(9) is major bottle-neck of ale(4)(It comes 1555 1.3.2.2 snj * from hardware limitation). For jumbo frames we could 1556 1.3.2.2 snj * get a slightly better performance if driver use 1557 1.3.2.2 snj * m_getjcl(9) with proper buffer size argument. However 1558 1.3.2.2 snj * that would make code more complicated and I don't 1559 1.3.2.2 snj * think users would expect good Rx performance numbers 1560 1.3.2.2 snj * on these low-end consumer ethernet controller. 1561 1.3.2.2 snj */ 1562 1.3.2.2 snj m = m_devget((char *)(rs + 1), length - ETHER_CRC_LEN, 1563 1.3.2.2 snj 0, ifp, NULL); 1564 1.3.2.2 snj if (m == NULL) { 1565 1.3.2.2 snj ifp->if_iqdrops++; 1566 1.3.2.2 snj ale_rx_update_page(sc, &rx_page, length, &prod); 1567 1.3.2.2 snj continue; 1568 1.3.2.2 snj } 1569 1.3.2.2 snj if (status & ALE_RD_IPV4) 1570 1.3.2.2 snj ale_rxcsum(sc, m, status); 1571 1.3.2.2 snj #if NVLAN > 0 1572 1.3.2.2 snj if (status & ALE_RD_VLAN) { 1573 1.3.2.2 snj uint32_t vtags = ALE_RX_VLAN(le32toh(rs->vtags)); 1574 1.3.2.2 snj VLAN_INPUT_TAG(ifp, m, ALE_RX_VLAN_TAG(vtags), ); 1575 1.3.2.2 snj } 1576 1.3.2.2 snj #endif 1577 1.3.2.2 snj 1578 1.3.2.2 snj 1579 1.3.2.2 snj #if NBPFILTER > 0 1580 1.3.2.2 snj if (ifp->if_bpf) 1581 1.3.2.2 snj bpf_mtap(ifp->if_bpf, m); 1582 1.3.2.2 snj #endif 1583 1.3.2.2 snj 1584 1.3.2.2 snj /* Pass it to upper layer. */ 1585 1.3.2.2 snj ether_input(ifp, m); 1586 1.3.2.2 snj 1587 1.3.2.2 snj ale_rx_update_page(sc, &rx_page, length, &prod); 1588 1.3.2.2 snj } 1589 1.3.2.2 snj 1590 1.3.2.2 snj return 0; 1591 1.3.2.2 snj } 1592 1.3.2.2 snj 1593 1.3.2.2 snj static void 1594 1.3.2.2 snj ale_tick(void *xsc) 1595 1.3.2.2 snj { 1596 1.3.2.2 snj struct ale_softc *sc = xsc; 1597 1.3.2.2 snj struct mii_data *mii = &sc->sc_miibus; 1598 1.3.2.2 snj int s; 1599 1.3.2.2 snj 1600 1.3.2.2 snj s = splnet(); 1601 1.3.2.2 snj mii_tick(mii); 1602 1.3.2.2 snj ale_stats_update(sc); 1603 1.3.2.2 snj splx(s); 1604 1.3.2.2 snj 1605 1.3.2.2 snj callout_schedule(&sc->sc_tick_ch, hz); 1606 1.3.2.2 snj } 1607 1.3.2.2 snj 1608 1.3.2.2 snj static void 1609 1.3.2.2 snj ale_reset(struct ale_softc *sc) 1610 1.3.2.2 snj { 1611 1.3.2.2 snj uint32_t reg; 1612 1.3.2.2 snj int i; 1613 1.3.2.2 snj 1614 1.3.2.2 snj /* Initialize PCIe module. From Linux. */ 1615 1.3.2.2 snj CSR_WRITE_4(sc, 0x1008, CSR_READ_4(sc, 0x1008) | 0x8000); 1616 1.3.2.2 snj 1617 1.3.2.2 snj CSR_WRITE_4(sc, ALE_MASTER_CFG, MASTER_RESET); 1618 1.3.2.2 snj for (i = ALE_RESET_TIMEOUT; i > 0; i--) { 1619 1.3.2.2 snj DELAY(10); 1620 1.3.2.2 snj if ((CSR_READ_4(sc, ALE_MASTER_CFG) & MASTER_RESET) == 0) 1621 1.3.2.2 snj break; 1622 1.3.2.2 snj } 1623 1.3.2.2 snj if (i == 0) 1624 1.3.2.2 snj printf("%s: master reset timeout!\n", device_xname(sc->sc_dev)); 1625 1.3.2.2 snj 1626 1.3.2.2 snj for (i = ALE_RESET_TIMEOUT; i > 0; i--) { 1627 1.3.2.2 snj if ((reg = CSR_READ_4(sc, ALE_IDLE_STATUS)) == 0) 1628 1.3.2.2 snj break; 1629 1.3.2.2 snj DELAY(10); 1630 1.3.2.2 snj } 1631 1.3.2.2 snj 1632 1.3.2.2 snj if (i == 0) 1633 1.3.2.2 snj printf("%s: reset timeout(0x%08x)!\n", device_xname(sc->sc_dev), 1634 1.3.2.2 snj reg); 1635 1.3.2.2 snj } 1636 1.3.2.2 snj 1637 1.3.2.2 snj static int 1638 1.3.2.2 snj ale_init(struct ifnet *ifp) 1639 1.3.2.2 snj { 1640 1.3.2.2 snj struct ale_softc *sc = ifp->if_softc; 1641 1.3.2.2 snj struct mii_data *mii; 1642 1.3.2.2 snj uint8_t eaddr[ETHER_ADDR_LEN]; 1643 1.3.2.2 snj bus_addr_t paddr; 1644 1.3.2.2 snj uint32_t reg, rxf_hi, rxf_lo; 1645 1.3.2.2 snj 1646 1.3.2.2 snj /* 1647 1.3.2.2 snj * Cancel any pending I/O. 1648 1.3.2.2 snj */ 1649 1.3.2.2 snj ale_stop(ifp, 0); 1650 1.3.2.2 snj 1651 1.3.2.2 snj /* 1652 1.3.2.2 snj * Reset the chip to a known state. 1653 1.3.2.2 snj */ 1654 1.3.2.2 snj ale_reset(sc); 1655 1.3.2.2 snj 1656 1.3.2.2 snj /* Initialize Tx descriptors, DMA memory blocks. */ 1657 1.3.2.2 snj ale_init_rx_pages(sc); 1658 1.3.2.2 snj ale_init_tx_ring(sc); 1659 1.3.2.2 snj 1660 1.3.2.2 snj /* Reprogram the station address. */ 1661 1.3.2.2 snj memcpy(eaddr, CLLADDR(ifp->if_sadl), ETHER_ADDR_LEN); 1662 1.3.2.2 snj CSR_WRITE_4(sc, ALE_PAR0, 1663 1.3.2.2 snj eaddr[2] << 24 | eaddr[3] << 16 | eaddr[4] << 8 | eaddr[5]); 1664 1.3.2.2 snj CSR_WRITE_4(sc, ALE_PAR1, eaddr[0] << 8 | eaddr[1]); 1665 1.3.2.2 snj 1666 1.3.2.2 snj /* 1667 1.3.2.2 snj * Clear WOL status and disable all WOL feature as WOL 1668 1.3.2.2 snj * would interfere Rx operation under normal environments. 1669 1.3.2.2 snj */ 1670 1.3.2.2 snj CSR_READ_4(sc, ALE_WOL_CFG); 1671 1.3.2.2 snj CSR_WRITE_4(sc, ALE_WOL_CFG, 0); 1672 1.3.2.2 snj 1673 1.3.2.2 snj /* 1674 1.3.2.2 snj * Set Tx descriptor/RXF0/CMB base addresses. They share 1675 1.3.2.2 snj * the same high address part of DMAable region. 1676 1.3.2.2 snj */ 1677 1.3.2.2 snj paddr = sc->ale_cdata.ale_tx_ring_paddr; 1678 1.3.2.2 snj CSR_WRITE_4(sc, ALE_TPD_ADDR_HI, ALE_ADDR_HI(paddr)); 1679 1.3.2.2 snj CSR_WRITE_4(sc, ALE_TPD_ADDR_LO, ALE_ADDR_LO(paddr)); 1680 1.3.2.2 snj CSR_WRITE_4(sc, ALE_TPD_CNT, 1681 1.3.2.2 snj (ALE_TX_RING_CNT << TPD_CNT_SHIFT) & TPD_CNT_MASK); 1682 1.3.2.2 snj 1683 1.3.2.2 snj /* Set Rx page base address, note we use single queue. */ 1684 1.3.2.2 snj paddr = sc->ale_cdata.ale_rx_page[0].page_paddr; 1685 1.3.2.2 snj CSR_WRITE_4(sc, ALE_RXF0_PAGE0_ADDR_LO, ALE_ADDR_LO(paddr)); 1686 1.3.2.2 snj paddr = sc->ale_cdata.ale_rx_page[1].page_paddr; 1687 1.3.2.2 snj CSR_WRITE_4(sc, ALE_RXF0_PAGE1_ADDR_LO, ALE_ADDR_LO(paddr)); 1688 1.3.2.2 snj 1689 1.3.2.2 snj /* Set Tx/Rx CMB addresses. */ 1690 1.3.2.2 snj paddr = sc->ale_cdata.ale_tx_cmb_paddr; 1691 1.3.2.2 snj CSR_WRITE_4(sc, ALE_TX_CMB_ADDR_LO, ALE_ADDR_LO(paddr)); 1692 1.3.2.2 snj paddr = sc->ale_cdata.ale_rx_page[0].cmb_paddr; 1693 1.3.2.2 snj CSR_WRITE_4(sc, ALE_RXF0_CMB0_ADDR_LO, ALE_ADDR_LO(paddr)); 1694 1.3.2.2 snj paddr = sc->ale_cdata.ale_rx_page[1].cmb_paddr; 1695 1.3.2.2 snj CSR_WRITE_4(sc, ALE_RXF0_CMB1_ADDR_LO, ALE_ADDR_LO(paddr)); 1696 1.3.2.2 snj 1697 1.3.2.2 snj /* Mark RXF0 is valid. */ 1698 1.3.2.2 snj CSR_WRITE_1(sc, ALE_RXF0_PAGE0, RXF_VALID); 1699 1.3.2.2 snj CSR_WRITE_1(sc, ALE_RXF0_PAGE1, RXF_VALID); 1700 1.3.2.2 snj /* 1701 1.3.2.2 snj * No need to initialize RFX1/RXF2/RXF3. We don't use 1702 1.3.2.2 snj * multi-queue yet. 1703 1.3.2.2 snj */ 1704 1.3.2.2 snj 1705 1.3.2.2 snj /* Set Rx page size, excluding guard frame size. */ 1706 1.3.2.2 snj CSR_WRITE_4(sc, ALE_RXF_PAGE_SIZE, ALE_RX_PAGE_SZ); 1707 1.3.2.2 snj 1708 1.3.2.2 snj /* Tell hardware that we're ready to load DMA blocks. */ 1709 1.3.2.2 snj CSR_WRITE_4(sc, ALE_DMA_BLOCK, DMA_BLOCK_LOAD); 1710 1.3.2.2 snj 1711 1.3.2.2 snj /* Set Rx/Tx interrupt trigger threshold. */ 1712 1.3.2.2 snj CSR_WRITE_4(sc, ALE_INT_TRIG_THRESH, (1 << INT_TRIG_RX_THRESH_SHIFT) | 1713 1.3.2.2 snj (4 << INT_TRIG_TX_THRESH_SHIFT)); 1714 1.3.2.2 snj /* 1715 1.3.2.2 snj * XXX 1716 1.3.2.2 snj * Set interrupt trigger timer, its purpose and relation 1717 1.3.2.2 snj * with interrupt moderation mechanism is not clear yet. 1718 1.3.2.2 snj */ 1719 1.3.2.2 snj CSR_WRITE_4(sc, ALE_INT_TRIG_TIMER, 1720 1.3.2.2 snj ((ALE_USECS(10) << INT_TRIG_RX_TIMER_SHIFT) | 1721 1.3.2.2 snj (ALE_USECS(1000) << INT_TRIG_TX_TIMER_SHIFT))); 1722 1.3.2.2 snj 1723 1.3.2.2 snj /* Configure interrupt moderation timer. */ 1724 1.3.2.2 snj sc->ale_int_rx_mod = ALE_IM_RX_TIMER_DEFAULT; 1725 1.3.2.2 snj sc->ale_int_tx_mod = ALE_IM_TX_TIMER_DEFAULT; 1726 1.3.2.2 snj reg = ALE_USECS(sc->ale_int_rx_mod) << IM_TIMER_RX_SHIFT; 1727 1.3.2.2 snj reg |= ALE_USECS(sc->ale_int_tx_mod) << IM_TIMER_TX_SHIFT; 1728 1.3.2.2 snj CSR_WRITE_4(sc, ALE_IM_TIMER, reg); 1729 1.3.2.2 snj reg = CSR_READ_4(sc, ALE_MASTER_CFG); 1730 1.3.2.2 snj reg &= ~(MASTER_CHIP_REV_MASK | MASTER_CHIP_ID_MASK); 1731 1.3.2.2 snj reg &= ~(MASTER_IM_RX_TIMER_ENB | MASTER_IM_TX_TIMER_ENB); 1732 1.3.2.2 snj if (ALE_USECS(sc->ale_int_rx_mod) != 0) 1733 1.3.2.2 snj reg |= MASTER_IM_RX_TIMER_ENB; 1734 1.3.2.2 snj if (ALE_USECS(sc->ale_int_tx_mod) != 0) 1735 1.3.2.2 snj reg |= MASTER_IM_TX_TIMER_ENB; 1736 1.3.2.2 snj CSR_WRITE_4(sc, ALE_MASTER_CFG, reg); 1737 1.3.2.2 snj CSR_WRITE_2(sc, ALE_INTR_CLR_TIMER, ALE_USECS(1000)); 1738 1.3.2.2 snj 1739 1.3.2.2 snj /* Set Maximum frame size of controller. */ 1740 1.3.2.2 snj if (ifp->if_mtu < ETHERMTU) 1741 1.3.2.2 snj sc->ale_max_frame_size = ETHERMTU; 1742 1.3.2.2 snj else 1743 1.3.2.2 snj sc->ale_max_frame_size = ifp->if_mtu; 1744 1.3.2.2 snj sc->ale_max_frame_size += ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN + ETHER_CRC_LEN; 1745 1.3.2.2 snj CSR_WRITE_4(sc, ALE_FRAME_SIZE, sc->ale_max_frame_size); 1746 1.3.2.2 snj 1747 1.3.2.2 snj /* Configure IPG/IFG parameters. */ 1748 1.3.2.2 snj CSR_WRITE_4(sc, ALE_IPG_IFG_CFG, 1749 1.3.2.2 snj ((IPG_IFG_IPGT_DEFAULT << IPG_IFG_IPGT_SHIFT) & IPG_IFG_IPGT_MASK) | 1750 1.3.2.2 snj ((IPG_IFG_MIFG_DEFAULT << IPG_IFG_MIFG_SHIFT) & IPG_IFG_MIFG_MASK) | 1751 1.3.2.2 snj ((IPG_IFG_IPG1_DEFAULT << IPG_IFG_IPG1_SHIFT) & IPG_IFG_IPG1_MASK) | 1752 1.3.2.2 snj ((IPG_IFG_IPG2_DEFAULT << IPG_IFG_IPG2_SHIFT) & IPG_IFG_IPG2_MASK)); 1753 1.3.2.2 snj 1754 1.3.2.2 snj /* Set parameters for half-duplex media. */ 1755 1.3.2.2 snj CSR_WRITE_4(sc, ALE_HDPX_CFG, 1756 1.3.2.2 snj ((HDPX_CFG_LCOL_DEFAULT << HDPX_CFG_LCOL_SHIFT) & 1757 1.3.2.2 snj HDPX_CFG_LCOL_MASK) | 1758 1.3.2.2 snj ((HDPX_CFG_RETRY_DEFAULT << HDPX_CFG_RETRY_SHIFT) & 1759 1.3.2.2 snj HDPX_CFG_RETRY_MASK) | HDPX_CFG_EXC_DEF_EN | 1760 1.3.2.2 snj ((HDPX_CFG_ABEBT_DEFAULT << HDPX_CFG_ABEBT_SHIFT) & 1761 1.3.2.2 snj HDPX_CFG_ABEBT_MASK) | 1762 1.3.2.2 snj ((HDPX_CFG_JAMIPG_DEFAULT << HDPX_CFG_JAMIPG_SHIFT) & 1763 1.3.2.2 snj HDPX_CFG_JAMIPG_MASK)); 1764 1.3.2.2 snj 1765 1.3.2.2 snj /* Configure Tx jumbo frame parameters. */ 1766 1.3.2.2 snj if ((sc->ale_flags & ALE_FLAG_JUMBO) != 0) { 1767 1.3.2.2 snj if (ifp->if_mtu < ETHERMTU) 1768 1.3.2.2 snj reg = sc->ale_max_frame_size; 1769 1.3.2.2 snj else if (ifp->if_mtu < 6 * 1024) 1770 1.3.2.2 snj reg = (sc->ale_max_frame_size * 2) / 3; 1771 1.3.2.2 snj else 1772 1.3.2.2 snj reg = sc->ale_max_frame_size / 2; 1773 1.3.2.2 snj CSR_WRITE_4(sc, ALE_TX_JUMBO_THRESH, 1774 1.3.2.2 snj roundup(reg, TX_JUMBO_THRESH_UNIT) >> 1775 1.3.2.2 snj TX_JUMBO_THRESH_UNIT_SHIFT); 1776 1.3.2.2 snj } 1777 1.3.2.2 snj 1778 1.3.2.2 snj /* Configure TxQ. */ 1779 1.3.2.2 snj reg = (128 << (sc->ale_dma_rd_burst >> DMA_CFG_RD_BURST_SHIFT)) 1780 1.3.2.2 snj << TXQ_CFG_TX_FIFO_BURST_SHIFT; 1781 1.3.2.2 snj reg |= (TXQ_CFG_TPD_BURST_DEFAULT << TXQ_CFG_TPD_BURST_SHIFT) & 1782 1.3.2.2 snj TXQ_CFG_TPD_BURST_MASK; 1783 1.3.2.2 snj CSR_WRITE_4(sc, ALE_TXQ_CFG, reg | TXQ_CFG_ENHANCED_MODE | TXQ_CFG_ENB); 1784 1.3.2.2 snj 1785 1.3.2.2 snj /* Configure Rx jumbo frame & flow control parameters. */ 1786 1.3.2.2 snj if ((sc->ale_flags & ALE_FLAG_JUMBO) != 0) { 1787 1.3.2.2 snj reg = roundup(sc->ale_max_frame_size, RX_JUMBO_THRESH_UNIT); 1788 1.3.2.2 snj CSR_WRITE_4(sc, ALE_RX_JUMBO_THRESH, 1789 1.3.2.2 snj (((reg >> RX_JUMBO_THRESH_UNIT_SHIFT) << 1790 1.3.2.2 snj RX_JUMBO_THRESH_MASK_SHIFT) & RX_JUMBO_THRESH_MASK) | 1791 1.3.2.2 snj ((RX_JUMBO_LKAH_DEFAULT << RX_JUMBO_LKAH_SHIFT) & 1792 1.3.2.2 snj RX_JUMBO_LKAH_MASK)); 1793 1.3.2.2 snj reg = CSR_READ_4(sc, ALE_SRAM_RX_FIFO_LEN); 1794 1.3.2.2 snj rxf_hi = (reg * 7) / 10; 1795 1.3.2.2 snj rxf_lo = (reg * 3)/ 10; 1796 1.3.2.2 snj CSR_WRITE_4(sc, ALE_RX_FIFO_PAUSE_THRESH, 1797 1.3.2.2 snj ((rxf_lo << RX_FIFO_PAUSE_THRESH_LO_SHIFT) & 1798 1.3.2.2 snj RX_FIFO_PAUSE_THRESH_LO_MASK) | 1799 1.3.2.2 snj ((rxf_hi << RX_FIFO_PAUSE_THRESH_HI_SHIFT) & 1800 1.3.2.2 snj RX_FIFO_PAUSE_THRESH_HI_MASK)); 1801 1.3.2.2 snj } 1802 1.3.2.2 snj 1803 1.3.2.2 snj /* Disable RSS. */ 1804 1.3.2.2 snj CSR_WRITE_4(sc, ALE_RSS_IDT_TABLE0, 0); 1805 1.3.2.2 snj CSR_WRITE_4(sc, ALE_RSS_CPU, 0); 1806 1.3.2.2 snj 1807 1.3.2.2 snj /* Configure RxQ. */ 1808 1.3.2.2 snj CSR_WRITE_4(sc, ALE_RXQ_CFG, 1809 1.3.2.2 snj RXQ_CFG_ALIGN_32 | RXQ_CFG_CUT_THROUGH_ENB | RXQ_CFG_ENB); 1810 1.3.2.2 snj 1811 1.3.2.2 snj /* Configure DMA parameters. */ 1812 1.3.2.2 snj reg = 0; 1813 1.3.2.2 snj if ((sc->ale_flags & ALE_FLAG_TXCMB_BUG) == 0) 1814 1.3.2.2 snj reg |= DMA_CFG_TXCMB_ENB; 1815 1.3.2.2 snj CSR_WRITE_4(sc, ALE_DMA_CFG, 1816 1.3.2.2 snj DMA_CFG_OUT_ORDER | DMA_CFG_RD_REQ_PRI | DMA_CFG_RCB_64 | 1817 1.3.2.2 snj sc->ale_dma_rd_burst | reg | 1818 1.3.2.2 snj sc->ale_dma_wr_burst | DMA_CFG_RXCMB_ENB | 1819 1.3.2.2 snj ((DMA_CFG_RD_DELAY_CNT_DEFAULT << DMA_CFG_RD_DELAY_CNT_SHIFT) & 1820 1.3.2.2 snj DMA_CFG_RD_DELAY_CNT_MASK) | 1821 1.3.2.2 snj ((DMA_CFG_WR_DELAY_CNT_DEFAULT << DMA_CFG_WR_DELAY_CNT_SHIFT) & 1822 1.3.2.2 snj DMA_CFG_WR_DELAY_CNT_MASK)); 1823 1.3.2.2 snj 1824 1.3.2.2 snj /* 1825 1.3.2.2 snj * Hardware can be configured to issue SMB interrupt based 1826 1.3.2.2 snj * on programmed interval. Since there is a callout that is 1827 1.3.2.2 snj * invoked for every hz in driver we use that instead of 1828 1.3.2.2 snj * relying on periodic SMB interrupt. 1829 1.3.2.2 snj */ 1830 1.3.2.2 snj CSR_WRITE_4(sc, ALE_SMB_STAT_TIMER, ALE_USECS(0)); 1831 1.3.2.2 snj 1832 1.3.2.2 snj /* Clear MAC statistics. */ 1833 1.3.2.2 snj ale_stats_clear(sc); 1834 1.3.2.2 snj 1835 1.3.2.2 snj /* 1836 1.3.2.2 snj * Configure Tx/Rx MACs. 1837 1.3.2.2 snj * - Auto-padding for short frames. 1838 1.3.2.2 snj * - Enable CRC generation. 1839 1.3.2.2 snj * Actual reconfiguration of MAC for resolved speed/duplex 1840 1.3.2.2 snj * is followed after detection of link establishment. 1841 1.3.2.2 snj * AR81xx always does checksum computation regardless of 1842 1.3.2.2 snj * MAC_CFG_RXCSUM_ENB bit. In fact, setting the bit will 1843 1.3.2.2 snj * cause Rx handling issue for fragmented IP datagrams due 1844 1.3.2.2 snj * to silicon bug. 1845 1.3.2.2 snj */ 1846 1.3.2.2 snj reg = MAC_CFG_TX_CRC_ENB | MAC_CFG_TX_AUTO_PAD | MAC_CFG_FULL_DUPLEX | 1847 1.3.2.2 snj ((MAC_CFG_PREAMBLE_DEFAULT << MAC_CFG_PREAMBLE_SHIFT) & 1848 1.3.2.2 snj MAC_CFG_PREAMBLE_MASK); 1849 1.3.2.2 snj if ((sc->ale_flags & ALE_FLAG_FASTETHER) != 0) 1850 1.3.2.2 snj reg |= MAC_CFG_SPEED_10_100; 1851 1.3.2.2 snj else 1852 1.3.2.2 snj reg |= MAC_CFG_SPEED_1000; 1853 1.3.2.2 snj CSR_WRITE_4(sc, ALE_MAC_CFG, reg); 1854 1.3.2.2 snj 1855 1.3.2.2 snj /* Set up the receive filter. */ 1856 1.3.2.2 snj ale_rxfilter(sc); 1857 1.3.2.2 snj ale_rxvlan(sc); 1858 1.3.2.2 snj 1859 1.3.2.2 snj /* Acknowledge all pending interrupts and clear it. */ 1860 1.3.2.2 snj CSR_WRITE_4(sc, ALE_INTR_MASK, ALE_INTRS); 1861 1.3.2.2 snj CSR_WRITE_4(sc, ALE_INTR_STATUS, 0xFFFFFFFF); 1862 1.3.2.2 snj CSR_WRITE_4(sc, ALE_INTR_STATUS, 0); 1863 1.3.2.2 snj 1864 1.3.2.2 snj sc->ale_flags &= ~ALE_FLAG_LINK; 1865 1.3.2.2 snj 1866 1.3.2.2 snj /* Switch to the current media. */ 1867 1.3.2.2 snj mii = &sc->sc_miibus; 1868 1.3.2.2 snj mii_mediachg(mii); 1869 1.3.2.2 snj 1870 1.3.2.2 snj callout_schedule(&sc->sc_tick_ch, hz); 1871 1.3.2.2 snj 1872 1.3.2.2 snj ifp->if_flags |= IFF_RUNNING; 1873 1.3.2.2 snj ifp->if_flags &= ~IFF_OACTIVE; 1874 1.3.2.2 snj 1875 1.3.2.2 snj return 0; 1876 1.3.2.2 snj } 1877 1.3.2.2 snj 1878 1.3.2.2 snj static void 1879 1.3.2.2 snj ale_stop(struct ifnet *ifp, int disable) 1880 1.3.2.2 snj { 1881 1.3.2.2 snj struct ale_softc *sc = ifp->if_softc; 1882 1.3.2.2 snj struct ale_txdesc *txd; 1883 1.3.2.2 snj uint32_t reg; 1884 1.3.2.2 snj int i; 1885 1.3.2.2 snj 1886 1.3.2.2 snj callout_stop(&sc->sc_tick_ch); 1887 1.3.2.2 snj 1888 1.3.2.2 snj /* 1889 1.3.2.2 snj * Mark the interface down and cancel the watchdog timer. 1890 1.3.2.2 snj */ 1891 1.3.2.2 snj ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1892 1.3.2.2 snj ifp->if_timer = 0; 1893 1.3.2.2 snj 1894 1.3.2.2 snj sc->ale_flags &= ~ALE_FLAG_LINK; 1895 1.3.2.2 snj 1896 1.3.2.2 snj ale_stats_update(sc); 1897 1.3.2.2 snj 1898 1.3.2.2 snj mii_down(&sc->sc_miibus); 1899 1.3.2.2 snj 1900 1.3.2.2 snj /* Disable interrupts. */ 1901 1.3.2.2 snj CSR_WRITE_4(sc, ALE_INTR_MASK, 0); 1902 1.3.2.2 snj CSR_WRITE_4(sc, ALE_INTR_STATUS, 0xFFFFFFFF); 1903 1.3.2.2 snj 1904 1.3.2.2 snj /* Disable queue processing and DMA. */ 1905 1.3.2.2 snj reg = CSR_READ_4(sc, ALE_TXQ_CFG); 1906 1.3.2.2 snj reg &= ~TXQ_CFG_ENB; 1907 1.3.2.2 snj CSR_WRITE_4(sc, ALE_TXQ_CFG, reg); 1908 1.3.2.2 snj reg = CSR_READ_4(sc, ALE_RXQ_CFG); 1909 1.3.2.2 snj reg &= ~RXQ_CFG_ENB; 1910 1.3.2.2 snj CSR_WRITE_4(sc, ALE_RXQ_CFG, reg); 1911 1.3.2.2 snj reg = CSR_READ_4(sc, ALE_DMA_CFG); 1912 1.3.2.2 snj reg &= ~(DMA_CFG_TXCMB_ENB | DMA_CFG_RXCMB_ENB); 1913 1.3.2.2 snj CSR_WRITE_4(sc, ALE_DMA_CFG, reg); 1914 1.3.2.2 snj DELAY(1000); 1915 1.3.2.2 snj 1916 1.3.2.2 snj /* Stop Rx/Tx MACs. */ 1917 1.3.2.2 snj ale_stop_mac(sc); 1918 1.3.2.2 snj 1919 1.3.2.2 snj /* Disable interrupts again? XXX */ 1920 1.3.2.2 snj CSR_WRITE_4(sc, ALE_INTR_STATUS, 0xFFFFFFFF); 1921 1.3.2.2 snj 1922 1.3.2.2 snj /* 1923 1.3.2.2 snj * Free TX mbufs still in the queues. 1924 1.3.2.2 snj */ 1925 1.3.2.2 snj for (i = 0; i < ALE_TX_RING_CNT; i++) { 1926 1.3.2.2 snj txd = &sc->ale_cdata.ale_txdesc[i]; 1927 1.3.2.2 snj if (txd->tx_m != NULL) { 1928 1.3.2.2 snj bus_dmamap_unload(sc->sc_dmat, txd->tx_dmamap); 1929 1.3.2.2 snj m_freem(txd->tx_m); 1930 1.3.2.2 snj txd->tx_m = NULL; 1931 1.3.2.2 snj } 1932 1.3.2.2 snj } 1933 1.3.2.2 snj } 1934 1.3.2.2 snj 1935 1.3.2.2 snj static void 1936 1.3.2.2 snj ale_stop_mac(struct ale_softc *sc) 1937 1.3.2.2 snj { 1938 1.3.2.2 snj uint32_t reg; 1939 1.3.2.2 snj int i; 1940 1.3.2.2 snj 1941 1.3.2.2 snj reg = CSR_READ_4(sc, ALE_MAC_CFG); 1942 1.3.2.2 snj if ((reg & (MAC_CFG_TX_ENB | MAC_CFG_RX_ENB)) != 0) { 1943 1.3.2.2 snj reg &= ~MAC_CFG_TX_ENB | MAC_CFG_RX_ENB; 1944 1.3.2.2 snj CSR_WRITE_4(sc, ALE_MAC_CFG, reg); 1945 1.3.2.2 snj } 1946 1.3.2.2 snj 1947 1.3.2.2 snj for (i = ALE_TIMEOUT; i > 0; i--) { 1948 1.3.2.2 snj reg = CSR_READ_4(sc, ALE_IDLE_STATUS); 1949 1.3.2.2 snj if (reg == 0) 1950 1.3.2.2 snj break; 1951 1.3.2.2 snj DELAY(10); 1952 1.3.2.2 snj } 1953 1.3.2.2 snj if (i == 0) 1954 1.3.2.2 snj printf("%s: could not disable Tx/Rx MAC(0x%08x)!\n", 1955 1.3.2.2 snj device_xname(sc->sc_dev), reg); 1956 1.3.2.2 snj } 1957 1.3.2.2 snj 1958 1.3.2.2 snj static void 1959 1.3.2.2 snj ale_init_tx_ring(struct ale_softc *sc) 1960 1.3.2.2 snj { 1961 1.3.2.2 snj struct ale_txdesc *txd; 1962 1.3.2.2 snj int i; 1963 1.3.2.2 snj 1964 1.3.2.2 snj sc->ale_cdata.ale_tx_prod = 0; 1965 1.3.2.2 snj sc->ale_cdata.ale_tx_cons = 0; 1966 1.3.2.2 snj sc->ale_cdata.ale_tx_cnt = 0; 1967 1.3.2.2 snj 1968 1.3.2.2 snj memset(sc->ale_cdata.ale_tx_ring, 0, ALE_TX_RING_SZ); 1969 1.3.2.2 snj memset(sc->ale_cdata.ale_tx_cmb, 0, ALE_TX_CMB_SZ); 1970 1.3.2.2 snj for (i = 0; i < ALE_TX_RING_CNT; i++) { 1971 1.3.2.2 snj txd = &sc->ale_cdata.ale_txdesc[i]; 1972 1.3.2.2 snj txd->tx_m = NULL; 1973 1.3.2.2 snj } 1974 1.3.2.2 snj *sc->ale_cdata.ale_tx_cmb = 0; 1975 1.3.2.2 snj bus_dmamap_sync(sc->sc_dmat, sc->ale_cdata.ale_tx_cmb_map, 0, 1976 1.3.2.2 snj sc->ale_cdata.ale_tx_cmb_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 1977 1.3.2.2 snj bus_dmamap_sync(sc->sc_dmat, sc->ale_cdata.ale_tx_ring_map, 0, 1978 1.3.2.2 snj sc->ale_cdata.ale_tx_ring_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 1979 1.3.2.2 snj } 1980 1.3.2.2 snj 1981 1.3.2.2 snj static void 1982 1.3.2.2 snj ale_init_rx_pages(struct ale_softc *sc) 1983 1.3.2.2 snj { 1984 1.3.2.2 snj struct ale_rx_page *rx_page; 1985 1.3.2.2 snj int i; 1986 1.3.2.2 snj 1987 1.3.2.2 snj sc->ale_cdata.ale_rx_seqno = 0; 1988 1.3.2.2 snj sc->ale_cdata.ale_rx_curp = 0; 1989 1.3.2.2 snj 1990 1.3.2.2 snj for (i = 0; i < ALE_RX_PAGES; i++) { 1991 1.3.2.2 snj rx_page = &sc->ale_cdata.ale_rx_page[i]; 1992 1.3.2.2 snj memset(rx_page->page_addr, 0, sc->ale_pagesize); 1993 1.3.2.2 snj memset(rx_page->cmb_addr, 0, ALE_RX_CMB_SZ); 1994 1.3.2.2 snj rx_page->cons = 0; 1995 1.3.2.2 snj *rx_page->cmb_addr = 0; 1996 1.3.2.2 snj bus_dmamap_sync(sc->sc_dmat, rx_page->page_map, 0, 1997 1.3.2.2 snj rx_page->page_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 1998 1.3.2.2 snj bus_dmamap_sync(sc->sc_dmat, rx_page->cmb_map, 0, 1999 1.3.2.2 snj rx_page->cmb_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 2000 1.3.2.2 snj } 2001 1.3.2.2 snj } 2002 1.3.2.2 snj 2003 1.3.2.2 snj static void 2004 1.3.2.2 snj ale_rxvlan(struct ale_softc *sc) 2005 1.3.2.2 snj { 2006 1.3.2.2 snj struct ifnet *ifp = &sc->sc_ec.ec_if; 2007 1.3.2.2 snj uint32_t reg; 2008 1.3.2.2 snj 2009 1.3.2.2 snj reg = CSR_READ_4(sc, ALE_MAC_CFG); 2010 1.3.2.2 snj reg &= ~MAC_CFG_VLAN_TAG_STRIP; 2011 1.3.2.2 snj if (ifp->if_capabilities & ETHERCAP_VLAN_HWTAGGING) 2012 1.3.2.2 snj reg |= MAC_CFG_VLAN_TAG_STRIP; 2013 1.3.2.2 snj CSR_WRITE_4(sc, ALE_MAC_CFG, reg); 2014 1.3.2.2 snj } 2015 1.3.2.2 snj 2016 1.3.2.2 snj static void 2017 1.3.2.2 snj ale_rxfilter(struct ale_softc *sc) 2018 1.3.2.2 snj { 2019 1.3.2.2 snj struct ethercom *ec = &sc->sc_ec; 2020 1.3.2.2 snj struct ifnet *ifp = &ec->ec_if; 2021 1.3.2.2 snj struct ether_multi *enm; 2022 1.3.2.2 snj struct ether_multistep step; 2023 1.3.2.2 snj uint32_t crc; 2024 1.3.2.2 snj uint32_t mchash[2]; 2025 1.3.2.2 snj uint32_t rxcfg; 2026 1.3.2.2 snj 2027 1.3.2.2 snj rxcfg = CSR_READ_4(sc, ALE_MAC_CFG); 2028 1.3.2.2 snj rxcfg &= ~(MAC_CFG_ALLMULTI | MAC_CFG_BCAST | MAC_CFG_PROMISC); 2029 1.3.2.3 snj ifp->if_flags &= ~IFF_ALLMULTI; 2030 1.3.2.2 snj 2031 1.3.2.2 snj /* 2032 1.3.2.2 snj * Always accept broadcast frames. 2033 1.3.2.2 snj */ 2034 1.3.2.2 snj rxcfg |= MAC_CFG_BCAST; 2035 1.3.2.2 snj 2036 1.3.2.3 snj if (ifp->if_flags & IFF_PROMISC || ec->ec_multicnt > 0) { 2037 1.3.2.3 snj ifp->if_flags |= IFF_ALLMULTI; 2038 1.3.2.2 snj if (ifp->if_flags & IFF_PROMISC) 2039 1.3.2.2 snj rxcfg |= MAC_CFG_PROMISC; 2040 1.3.2.2 snj else 2041 1.3.2.2 snj rxcfg |= MAC_CFG_ALLMULTI; 2042 1.3.2.2 snj mchash[0] = mchash[1] = 0xFFFFFFFF; 2043 1.3.2.2 snj } else { 2044 1.3.2.2 snj /* Program new filter. */ 2045 1.3.2.2 snj memset(mchash, 0, sizeof(mchash)); 2046 1.3.2.2 snj 2047 1.3.2.2 snj ETHER_FIRST_MULTI(step, ec, enm); 2048 1.3.2.2 snj while (enm != NULL) { 2049 1.3.2.2 snj crc = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN); 2050 1.3.2.2 snj mchash[crc >> 31] |= 1 << ((crc >> 26) & 0x1f); 2051 1.3.2.2 snj ETHER_NEXT_MULTI(step, enm); 2052 1.3.2.2 snj } 2053 1.3.2.2 snj } 2054 1.3.2.2 snj 2055 1.3.2.2 snj CSR_WRITE_4(sc, ALE_MAR0, mchash[0]); 2056 1.3.2.2 snj CSR_WRITE_4(sc, ALE_MAR1, mchash[1]); 2057 1.3.2.2 snj CSR_WRITE_4(sc, ALE_MAC_CFG, rxcfg); 2058 1.3.2.2 snj } 2059
Indexes created Fri Oct 03 02:09:57 GMT 2025