if_ale.c revision 1.1
1 /*- 2 * Copyright (c) 2008, Pyun YongHyeon <yongari (at) FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice unmodified, this list of conditions, and the following 10 * disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 * $FreeBSD: src/sys/dev/ale/if_ale.c,v 1.3 2008/12/03 09:01:12 yongari Exp $ 28 */ 29 30 /* Driver for Atheros AR8121/AR8113/AR8114 PCIe Ethernet. */ 31 32 #include "bpfilter.h" 33 #include "vlan.h" 34 35 #include <sys/param.h> 36 #include <sys/proc.h> 37 #include <sys/endian.h> 38 #include <sys/systm.h> 39 #include <sys/types.h> 40 #include <sys/sockio.h> 41 #include <sys/mbuf.h> 42 #include <sys/queue.h> 43 #include <sys/kernel.h> 44 #include <sys/device.h> 45 #include <sys/callout.h> 46 #include <sys/socket.h> 47 48 #include <sys/bus.h> 49 50 #include <net/if.h> 51 #include <net/if_dl.h> 52 #include <net/if_llc.h> 53 #include <net/if_media.h> 54 #include <net/if_ether.h> 55 56 #ifdef INET 57 #include <netinet/in.h> 58 #include <netinet/in_systm.h> 59 #include <netinet/in_var.h> 60 #include <netinet/ip.h> 61 #endif 62 63 #include <net/if_types.h> 64 #include <net/if_vlanvar.h> 65 66 #if NBPFILTER > 0 67 #include <net/bpf.h> 68 #endif 69 70 #include <sys/rnd.h> 71 72 #include <dev/mii/mii.h> 73 #include <dev/mii/miivar.h> 74 75 #include <dev/pci/pcireg.h> 76 #include <dev/pci/pcivar.h> 77 #include <dev/pci/pcidevs.h> 78 79 #include <dev/pci/if_alereg.h> 80 81 static int ale_match(device_t, cfdata_t, void *); 82 static void ale_attach(device_t, device_t, void *); 83 static int ale_detach(device_t, int); 84 85 static int ale_miibus_readreg(device_t, int, int); 86 static void ale_miibus_writereg(device_t, int, int, int); 87 static void ale_miibus_statchg(device_t); 88 89 static int ale_init(struct ifnet *); 90 static void ale_start(struct ifnet *); 91 static int ale_ioctl(struct ifnet *, u_long, void *); 92 static void ale_watchdog(struct ifnet *); 93 static int ale_mediachange(struct ifnet *); 94 static void ale_mediastatus(struct ifnet *, struct ifmediareq *); 95 96 static int ale_intr(void *); 97 static int ale_rxeof(struct ale_softc *sc); 98 static void ale_rx_update_page(struct ale_softc *, struct ale_rx_page **, 99 uint32_t, uint32_t *); 100 static void ale_rxcsum(struct ale_softc *, struct mbuf *, uint32_t); 101 static void ale_txeof(struct ale_softc *); 102 103 static int ale_dma_alloc(struct ale_softc *); 104 static void ale_dma_free(struct ale_softc *); 105 static int ale_encap(struct ale_softc *, struct mbuf **); 106 static void ale_init_rx_pages(struct ale_softc *); 107 static void ale_init_tx_ring(struct ale_softc *); 108 109 static void ale_stop(struct ifnet *, int); 110 static void ale_tick(void *); 111 static void ale_get_macaddr(struct ale_softc *); 112 static void ale_mac_config(struct ale_softc *); 113 static void ale_phy_reset(struct ale_softc *); 114 static void ale_reset(struct ale_softc *); 115 static void ale_rxfilter(struct ale_softc *); 116 static void ale_rxvlan(struct ale_softc *); 117 static void ale_stats_clear(struct ale_softc *); 118 static void ale_stats_update(struct ale_softc *); 119 static void ale_stop_mac(struct ale_softc *); 120 121 CFATTACH_DECL_NEW(ale, sizeof(struct ale_softc), 122 ale_match, ale_attach, ale_detach, NULL); 123 124 int aledebug = 0; 125 #define DPRINTF(x) do { if (aledebug) printf x; } while (0) 126 127 #define ETHER_ALIGN 2 128 #define ALE_CSUM_FEATURES (M_CSUM_TCPv4 | M_CSUM_UDPv4) 129 130 static int 131 ale_miibus_readreg(device_t dev, int phy, int reg) 132 { 133 struct ale_softc *sc = device_private(dev); 134 uint32_t v; 135 int i; 136 137 if (phy != sc->ale_phyaddr) 138 return 0; 139 140 CSR_WRITE_4(sc, ALE_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ | 141 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); 142 for (i = ALE_PHY_TIMEOUT; i > 0; i--) { 143 DELAY(5); 144 v = CSR_READ_4(sc, ALE_MDIO); 145 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) 146 break; 147 } 148 149 if (i == 0) { 150 printf("%s: phy read timeout: phy %d, reg %d\n", 151 device_xname(sc->sc_dev), phy, reg); 152 return 0; 153 } 154 155 return ((v & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT); 156 } 157 158 static void 159 ale_miibus_writereg(device_t dev, int phy, int reg, int val) 160 { 161 struct ale_softc *sc = device_private(dev); 162 uint32_t v; 163 int i; 164 165 if (phy != sc->ale_phyaddr) 166 return; 167 168 CSR_WRITE_4(sc, ALE_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE | 169 (val & MDIO_DATA_MASK) << MDIO_DATA_SHIFT | 170 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); 171 for (i = ALE_PHY_TIMEOUT; i > 0; i--) { 172 DELAY(5); 173 v = CSR_READ_4(sc, ALE_MDIO); 174 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) 175 break; 176 } 177 178 if (i == 0) 179 printf("%s: phy write timeout: phy %d, reg %d\n", 180 device_xname(sc->sc_dev), phy, reg); 181 } 182 183 static void 184 ale_miibus_statchg(device_t dev) 185 { 186 struct ale_softc *sc = device_private(dev); 187 struct ifnet *ifp = &sc->sc_ec.ec_if; 188 struct mii_data *mii; 189 uint32_t reg; 190 191 if ((ifp->if_flags & IFF_RUNNING) == 0) 192 return; 193 194 mii = &sc->sc_miibus; 195 196 sc->ale_flags &= ~ALE_FLAG_LINK; 197 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 198 (IFM_ACTIVE | IFM_AVALID)) { 199 switch (IFM_SUBTYPE(mii->mii_media_active)) { 200 case IFM_10_T: 201 case IFM_100_TX: 202 sc->ale_flags |= ALE_FLAG_LINK; 203 break; 204 205 case IFM_1000_T: 206 if ((sc->ale_flags & ALE_FLAG_FASTETHER) == 0) 207 sc->ale_flags |= ALE_FLAG_LINK; 208 break; 209 210 default: 211 break; 212 } 213 } 214 215 /* Stop Rx/Tx MACs. */ 216 ale_stop_mac(sc); 217 218 /* Program MACs with resolved speed/duplex/flow-control. */ 219 if ((sc->ale_flags & ALE_FLAG_LINK) != 0) { 220 ale_mac_config(sc); 221 /* Reenable Tx/Rx MACs. */ 222 reg = CSR_READ_4(sc, ALE_MAC_CFG); 223 reg |= MAC_CFG_TX_ENB | MAC_CFG_RX_ENB; 224 CSR_WRITE_4(sc, ALE_MAC_CFG, reg); 225 } 226 } 227 228 void 229 ale_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 230 { 231 struct ale_softc *sc = ifp->if_softc; 232 struct mii_data *mii = &sc->sc_miibus; 233 234 mii_pollstat(mii); 235 ifmr->ifm_status = mii->mii_media_status; 236 ifmr->ifm_active = mii->mii_media_active; 237 } 238 239 int 240 ale_mediachange(struct ifnet *ifp) 241 { 242 struct ale_softc *sc = ifp->if_softc; 243 struct mii_data *mii = &sc->sc_miibus; 244 int error; 245 246 if (mii->mii_instance != 0) { 247 struct mii_softc *miisc; 248 249 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 250 mii_phy_reset(miisc); 251 } 252 error = mii_mediachg(mii); 253 254 return error; 255 } 256 257 int 258 ale_match(device_t dev, cfdata_t match, void *aux) 259 { 260 struct pci_attach_args *pa = aux; 261 262 return (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_ATTANSIC && 263 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_ATTANSIC_ETHERNET_L1E); 264 } 265 266 void 267 ale_get_macaddr(struct ale_softc *sc) 268 { 269 uint32_t ea[2], reg; 270 int i, vpdc; 271 272 reg = CSR_READ_4(sc, ALE_SPI_CTRL); 273 if ((reg & SPI_VPD_ENB) != 0) { 274 reg &= ~SPI_VPD_ENB; 275 CSR_WRITE_4(sc, ALE_SPI_CTRL, reg); 276 } 277 278 if (pci_get_capability(sc->sc_pct, sc->sc_pcitag, PCI_CAP_VPD, 279 &vpdc, NULL)) { 280 /* 281 * PCI VPD capability found, let TWSI reload EEPROM. 282 * This will set ethernet address of controller. 283 */ 284 CSR_WRITE_4(sc, ALE_TWSI_CTRL, CSR_READ_4(sc, ALE_TWSI_CTRL) | 285 TWSI_CTRL_SW_LD_START); 286 for (i = 100; i > 0; i--) { 287 DELAY(1000); 288 reg = CSR_READ_4(sc, ALE_TWSI_CTRL); 289 if ((reg & TWSI_CTRL_SW_LD_START) == 0) 290 break; 291 } 292 if (i == 0) 293 printf("%s: reloading EEPROM timeout!\n", 294 device_xname(sc->sc_dev)); 295 } else { 296 if (aledebug) 297 printf("%s: PCI VPD capability not found!\n", 298 device_xname(sc->sc_dev)); 299 } 300 301 ea[0] = CSR_READ_4(sc, ALE_PAR0); 302 ea[1] = CSR_READ_4(sc, ALE_PAR1); 303 sc->ale_eaddr[0] = (ea[1] >> 8) & 0xFF; 304 sc->ale_eaddr[1] = (ea[1] >> 0) & 0xFF; 305 sc->ale_eaddr[2] = (ea[0] >> 24) & 0xFF; 306 sc->ale_eaddr[3] = (ea[0] >> 16) & 0xFF; 307 sc->ale_eaddr[4] = (ea[0] >> 8) & 0xFF; 308 sc->ale_eaddr[5] = (ea[0] >> 0) & 0xFF; 309 } 310 311 void 312 ale_phy_reset(struct ale_softc *sc) 313 { 314 /* Reset magic from Linux. */ 315 CSR_WRITE_2(sc, ALE_GPHY_CTRL, 316 GPHY_CTRL_HIB_EN | GPHY_CTRL_HIB_PULSE | GPHY_CTRL_SEL_ANA_RESET | 317 GPHY_CTRL_PHY_PLL_ON); 318 DELAY(1000); 319 CSR_WRITE_2(sc, ALE_GPHY_CTRL, 320 GPHY_CTRL_EXT_RESET | GPHY_CTRL_HIB_EN | GPHY_CTRL_HIB_PULSE | 321 GPHY_CTRL_SEL_ANA_RESET | GPHY_CTRL_PHY_PLL_ON); 322 DELAY(1000); 323 324 #define ATPHY_DBG_ADDR 0x1D 325 #define ATPHY_DBG_DATA 0x1E 326 327 /* Enable hibernation mode. */ 328 ale_miibus_writereg(sc->sc_dev, sc->ale_phyaddr, 329 ATPHY_DBG_ADDR, 0x0B); 330 ale_miibus_writereg(sc->sc_dev, sc->ale_phyaddr, 331 ATPHY_DBG_DATA, 0xBC00); 332 /* Set Class A/B for all modes. */ 333 ale_miibus_writereg(sc->sc_dev, sc->ale_phyaddr, 334 ATPHY_DBG_ADDR, 0x00); 335 ale_miibus_writereg(sc->sc_dev, sc->ale_phyaddr, 336 ATPHY_DBG_DATA, 0x02EF); 337 /* Enable 10BT power saving. */ 338 ale_miibus_writereg(sc->sc_dev, sc->ale_phyaddr, 339 ATPHY_DBG_ADDR, 0x12); 340 ale_miibus_writereg(sc->sc_dev, sc->ale_phyaddr, 341 ATPHY_DBG_DATA, 0x4C04); 342 /* Adjust 1000T power. */ 343 ale_miibus_writereg(sc->sc_dev, sc->ale_phyaddr, 344 ATPHY_DBG_ADDR, 0x04); 345 ale_miibus_writereg(sc->sc_dev, sc->ale_phyaddr, 346 ATPHY_DBG_ADDR, 0x8BBB); 347 /* 10BT center tap voltage. */ 348 ale_miibus_writereg(sc->sc_dev, sc->ale_phyaddr, 349 ATPHY_DBG_ADDR, 0x05); 350 ale_miibus_writereg(sc->sc_dev, sc->ale_phyaddr, 351 ATPHY_DBG_ADDR, 0x2C46); 352 353 #undef ATPHY_DBG_ADDR 354 #undef ATPHY_DBG_DATA 355 DELAY(1000); 356 } 357 358 void 359 ale_attach(device_t parent, device_t self, void *aux) 360 { 361 struct ale_softc *sc = device_private(self); 362 struct pci_attach_args *pa = aux; 363 pci_chipset_tag_t pc = pa->pa_pc; 364 pci_intr_handle_t ih; 365 const char *intrstr; 366 struct ifnet *ifp; 367 pcireg_t memtype; 368 int error = 0; 369 uint32_t rxf_len, txf_len; 370 371 aprint_naive("\n"); 372 aprint_normal(": Attansic/Atheros L1E Ethernet\n"); 373 374 sc->sc_dev = self; 375 sc->sc_dmat = pa->pa_dmat; 376 sc->sc_pct = pa->pa_pc; 377 sc->sc_pcitag = pa->pa_tag; 378 379 /* 380 * Allocate IO memory 381 */ 382 memtype = pci_mapreg_type(sc->sc_pct, sc->sc_pcitag, ALE_PCIR_BAR); 383 switch (memtype) { 384 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 385 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT_1M: 386 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 387 break; 388 default: 389 aprint_error_dev(self, "invalid base address register\n"); 390 break; 391 } 392 393 if (pci_mapreg_map(pa, ALE_PCIR_BAR, memtype, 0, &sc->sc_mem_bt, 394 &sc->sc_mem_bh, NULL, &sc->sc_mem_size)) { 395 aprint_error_dev(self, "could not map mem space\n"); 396 return; 397 } 398 399 if (pci_intr_map(pa, &ih) != 0) { 400 aprint_error_dev(self, "could not map interrupt\n"); 401 goto fail; 402 } 403 404 /* 405 * Allocate IRQ 406 */ 407 intrstr = pci_intr_string(sc->sc_pct, ih); 408 sc->sc_irq_handle = pci_intr_establish(pc, ih, IPL_NET, ale_intr, sc); 409 if (sc->sc_irq_handle == NULL) { 410 aprint_error_dev(self, "could not establish interrupt"); 411 if (intrstr != NULL) 412 aprint_error(" at %s", intrstr); 413 aprint_error("\n"); 414 goto fail; 415 } 416 aprint_normal_dev(self, "%s\n", intrstr); 417 418 /* Set PHY address. */ 419 sc->ale_phyaddr = ALE_PHY_ADDR; 420 421 /* Reset PHY. */ 422 ale_phy_reset(sc); 423 424 /* Reset the ethernet controller. */ 425 ale_reset(sc); 426 427 /* Get PCI and chip id/revision. */ 428 sc->ale_rev = PCI_REVISION(pa->pa_class); 429 if (sc->ale_rev >= 0xF0) { 430 /* L2E Rev. B. AR8114 */ 431 sc->ale_flags |= ALE_FLAG_FASTETHER; 432 } else { 433 if ((CSR_READ_4(sc, ALE_PHY_STATUS) & PHY_STATUS_100M) != 0) { 434 /* L1E AR8121 */ 435 sc->ale_flags |= ALE_FLAG_JUMBO; 436 } else { 437 /* L2E Rev. A. AR8113 */ 438 sc->ale_flags |= ALE_FLAG_FASTETHER; 439 } 440 } 441 442 /* 443 * All known controllers seems to require 4 bytes alignment 444 * of Tx buffers to make Tx checksum offload with custom 445 * checksum generation method work. 446 */ 447 sc->ale_flags |= ALE_FLAG_TXCSUM_BUG; 448 449 /* 450 * All known controllers seems to have issues on Rx checksum 451 * offload for fragmented IP datagrams. 452 */ 453 sc->ale_flags |= ALE_FLAG_RXCSUM_BUG; 454 455 /* 456 * Don't use Tx CMB. It is known to cause RRS update failure 457 * under certain circumstances. Typical phenomenon of the 458 * issue would be unexpected sequence number encountered in 459 * Rx handler. 460 */ 461 sc->ale_flags |= ALE_FLAG_TXCMB_BUG; 462 sc->ale_chip_rev = CSR_READ_4(sc, ALE_MASTER_CFG) >> 463 MASTER_CHIP_REV_SHIFT; 464 aprint_debug_dev(self, "PCI device revision : 0x%04x\n", sc->ale_rev); 465 aprint_debug_dev(self, "Chip id/revision : 0x%04x\n", sc->ale_chip_rev); 466 467 /* 468 * Uninitialized hardware returns an invalid chip id/revision 469 * as well as 0xFFFFFFFF for Tx/Rx fifo length. 470 */ 471 txf_len = CSR_READ_4(sc, ALE_SRAM_TX_FIFO_LEN); 472 rxf_len = CSR_READ_4(sc, ALE_SRAM_RX_FIFO_LEN); 473 if (sc->ale_chip_rev == 0xFFFF || txf_len == 0xFFFFFFFF || 474 rxf_len == 0xFFFFFFF) { 475 aprint_error_dev(self, "chip revision : 0x%04x, %u Tx FIFO " 476 "%u Rx FIFO -- not initialized?\n", 477 sc->ale_chip_rev, txf_len, rxf_len); 478 goto fail; 479 } 480 481 if (aledebug) { 482 printf("%s: %u Tx FIFO, %u Rx FIFO\n", device_xname(sc->sc_dev), 483 txf_len, rxf_len); 484 } 485 486 /* Set max allowable DMA size. */ 487 sc->ale_dma_rd_burst = DMA_CFG_RD_BURST_128; 488 sc->ale_dma_wr_burst = DMA_CFG_WR_BURST_128; 489 490 callout_init(&sc->sc_tick_ch, 0); 491 callout_setfunc(&sc->sc_tick_ch, ale_tick, sc); 492 493 error = ale_dma_alloc(sc); 494 if (error) 495 goto fail; 496 497 /* Load station address. */ 498 ale_get_macaddr(sc); 499 500 aprint_normal_dev(self, "Ethernet address %s\n", 501 ether_sprintf(sc->ale_eaddr)); 502 503 ifp = &sc->sc_ec.ec_if; 504 ifp->if_softc = sc; 505 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 506 ifp->if_init = ale_init; 507 ifp->if_ioctl = ale_ioctl; 508 ifp->if_start = ale_start; 509 ifp->if_stop = ale_stop; 510 ifp->if_watchdog = ale_watchdog; 511 IFQ_SET_MAXLEN(&ifp->if_snd, ALE_TX_RING_CNT - 1); 512 IFQ_SET_READY(&ifp->if_snd); 513 strlcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 514 515 sc->sc_ec.ec_capabilities = ETHERCAP_VLAN_MTU; 516 517 #ifdef ALE_CHECKSUM 518 ifp->if_capabilities |= IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 519 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 520 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_TCPv4_Rx; 521 #endif 522 523 #if NVLAN > 0 524 sc->sc_ec.ec_capabilities |= ETHERCAP_VLAN_HWTAGGING; 525 #endif 526 527 /* Set up MII bus. */ 528 sc->sc_miibus.mii_ifp = ifp; 529 sc->sc_miibus.mii_readreg = ale_miibus_readreg; 530 sc->sc_miibus.mii_writereg = ale_miibus_writereg; 531 sc->sc_miibus.mii_statchg = ale_miibus_statchg; 532 533 sc->sc_ec.ec_mii = &sc->sc_miibus; 534 ifmedia_init(&sc->sc_miibus.mii_media, 0, ale_mediachange, 535 ale_mediastatus); 536 mii_attach(self, &sc->sc_miibus, 0xffffffff, MII_PHY_ANY, 537 MII_OFFSET_ANY, 0); 538 539 if (LIST_FIRST(&sc->sc_miibus.mii_phys) == NULL) { 540 aprint_error_dev(self, "no PHY found!\n"); 541 ifmedia_add(&sc->sc_miibus.mii_media, IFM_ETHER | IFM_MANUAL, 542 0, NULL); 543 ifmedia_set(&sc->sc_miibus.mii_media, IFM_ETHER | IFM_MANUAL); 544 } else 545 ifmedia_set(&sc->sc_miibus.mii_media, IFM_ETHER | IFM_AUTO); 546 547 if_attach(ifp); 548 ether_ifattach(ifp, sc->ale_eaddr); 549 550 if (!pmf_device_register(self, NULL, NULL)) 551 aprint_error_dev(self, "couldn't establish power handler\n"); 552 else 553 pmf_class_network_register(self, ifp); 554 555 return; 556 fail: 557 ale_dma_free(sc); 558 if (sc->sc_irq_handle != NULL) { 559 pci_intr_disestablish(pc, sc->sc_irq_handle); 560 sc->sc_irq_handle = NULL; 561 } 562 if (sc->sc_mem_size) { 563 bus_space_unmap(sc->sc_mem_bt, sc->sc_mem_bh, sc->sc_mem_size); 564 sc->sc_mem_size = 0; 565 } 566 } 567 568 static int 569 ale_detach(device_t self, int flags) 570 { 571 struct ale_softc *sc = device_private(self); 572 struct ifnet *ifp = &sc->sc_ec.ec_if; 573 int s; 574 575 s = splnet(); 576 ale_stop(ifp, 0); 577 splx(s); 578 579 mii_detach(&sc->sc_miibus, MII_PHY_ANY, MII_OFFSET_ANY); 580 581 /* Delete all remaining media. */ 582 ifmedia_delete_instance(&sc->sc_miibus.mii_media, IFM_INST_ANY); 583 584 ether_ifdetach(ifp); 585 if_detach(ifp); 586 ale_dma_free(sc); 587 588 if (sc->sc_irq_handle != NULL) { 589 pci_intr_disestablish(sc->sc_pct, sc->sc_irq_handle); 590 sc->sc_irq_handle = NULL; 591 } 592 if (sc->sc_mem_size) { 593 bus_space_unmap(sc->sc_mem_bt, sc->sc_mem_bh, sc->sc_mem_size); 594 sc->sc_mem_size = 0; 595 } 596 597 return 0; 598 } 599 600 601 static int 602 ale_dma_alloc(struct ale_softc *sc) 603 { 604 struct ale_txdesc *txd; 605 int nsegs, error, guard_size, i; 606 607 if ((sc->ale_flags & ALE_FLAG_JUMBO) != 0) 608 guard_size = ALE_JUMBO_FRAMELEN; 609 else 610 guard_size = ALE_MAX_FRAMELEN; 611 sc->ale_pagesize = roundup(guard_size + ALE_RX_PAGE_SZ, 612 ALE_RX_PAGE_ALIGN); 613 614 /* 615 * Create DMA stuffs for TX ring 616 */ 617 error = bus_dmamap_create(sc->sc_dmat, ALE_TX_RING_SZ, 1, 618 ALE_TX_RING_SZ, 0, BUS_DMA_NOWAIT, &sc->ale_cdata.ale_tx_ring_map); 619 if (error) { 620 sc->ale_cdata.ale_tx_ring_map = NULL; 621 return ENOBUFS; 622 } 623 624 /* Allocate DMA'able memory for TX ring */ 625 error = bus_dmamem_alloc(sc->sc_dmat, ALE_TX_RING_SZ, 626 0, 0, &sc->ale_cdata.ale_tx_ring_seg, 1, 627 &nsegs, BUS_DMA_WAITOK); 628 if (error) { 629 printf("%s: could not allocate DMA'able memory for Tx ring, " 630 "error = %i\n", device_xname(sc->sc_dev), error); 631 return error; 632 } 633 634 error = bus_dmamem_map(sc->sc_dmat, &sc->ale_cdata.ale_tx_ring_seg, 635 nsegs, ALE_TX_RING_SZ, (void **)&sc->ale_cdata.ale_tx_ring, 636 BUS_DMA_NOWAIT); 637 if (error) 638 return ENOBUFS; 639 640 memset(sc->ale_cdata.ale_tx_ring, 0, ALE_TX_RING_SZ); 641 642 /* Load the DMA map for Tx ring. */ 643 error = bus_dmamap_load(sc->sc_dmat, sc->ale_cdata.ale_tx_ring_map, 644 sc->ale_cdata.ale_tx_ring, ALE_TX_RING_SZ, NULL, BUS_DMA_WAITOK); 645 if (error) { 646 printf("%s: could not load DMA'able memory for Tx ring.\n", 647 device_xname(sc->sc_dev)); 648 bus_dmamem_free(sc->sc_dmat, 649 &sc->ale_cdata.ale_tx_ring_seg, 1); 650 return error; 651 } 652 sc->ale_cdata.ale_tx_ring_paddr = 653 sc->ale_cdata.ale_tx_ring_map->dm_segs[0].ds_addr; 654 655 for (i = 0; i < ALE_RX_PAGES; i++) { 656 /* 657 * Create DMA stuffs for RX pages 658 */ 659 error = bus_dmamap_create(sc->sc_dmat, sc->ale_pagesize, 1, 660 sc->ale_pagesize, 0, BUS_DMA_NOWAIT, 661 &sc->ale_cdata.ale_rx_page[i].page_map); 662 if (error) { 663 sc->ale_cdata.ale_rx_page[i].page_map = NULL; 664 return ENOBUFS; 665 } 666 667 /* Allocate DMA'able memory for RX pages */ 668 error = bus_dmamem_alloc(sc->sc_dmat, sc->ale_pagesize, 669 ETHER_ALIGN, 0, &sc->ale_cdata.ale_rx_page[i].page_seg, 670 1, &nsegs, BUS_DMA_WAITOK); 671 if (error) { 672 printf("%s: could not allocate DMA'able memory for " 673 "Rx ring.\n", device_xname(sc->sc_dev)); 674 return error; 675 } 676 error = bus_dmamem_map(sc->sc_dmat, 677 &sc->ale_cdata.ale_rx_page[i].page_seg, nsegs, 678 sc->ale_pagesize, 679 (void **)&sc->ale_cdata.ale_rx_page[i].page_addr, 680 BUS_DMA_NOWAIT); 681 if (error) 682 return ENOBUFS; 683 684 memset(sc->ale_cdata.ale_rx_page[i].page_addr, 0, 685 sc->ale_pagesize); 686 687 /* Load the DMA map for Rx pages. */ 688 error = bus_dmamap_load(sc->sc_dmat, 689 sc->ale_cdata.ale_rx_page[i].page_map, 690 sc->ale_cdata.ale_rx_page[i].page_addr, 691 sc->ale_pagesize, NULL, BUS_DMA_WAITOK); 692 if (error) { 693 printf("%s: could not load DMA'able memory for " 694 "Rx pages.\n", device_xname(sc->sc_dev)); 695 bus_dmamem_free(sc->sc_dmat, 696 &sc->ale_cdata.ale_rx_page[i].page_seg, 1); 697 return error; 698 } 699 sc->ale_cdata.ale_rx_page[i].page_paddr = 700 sc->ale_cdata.ale_rx_page[i].page_map->dm_segs[0].ds_addr; 701 } 702 703 /* 704 * Create DMA stuffs for Tx CMB. 705 */ 706 error = bus_dmamap_create(sc->sc_dmat, ALE_TX_CMB_SZ, 1, 707 ALE_TX_CMB_SZ, 0, BUS_DMA_NOWAIT, &sc->ale_cdata.ale_tx_cmb_map); 708 if (error) { 709 sc->ale_cdata.ale_tx_cmb_map = NULL; 710 return ENOBUFS; 711 } 712 713 /* Allocate DMA'able memory for Tx CMB. */ 714 error = bus_dmamem_alloc(sc->sc_dmat, ALE_TX_CMB_SZ, ETHER_ALIGN, 0, 715 &sc->ale_cdata.ale_tx_cmb_seg, 1, &nsegs, BUS_DMA_WAITOK); 716 717 if (error) { 718 printf("%s: could not allocate DMA'able memory for Tx CMB.\n", 719 device_xname(sc->sc_dev)); 720 return error; 721 } 722 723 error = bus_dmamem_map(sc->sc_dmat, &sc->ale_cdata.ale_tx_cmb_seg, 724 nsegs, ALE_TX_CMB_SZ, (void **)&sc->ale_cdata.ale_tx_cmb, 725 BUS_DMA_NOWAIT); 726 if (error) 727 return ENOBUFS; 728 729 memset(sc->ale_cdata.ale_tx_cmb, 0, ALE_TX_CMB_SZ); 730 731 /* Load the DMA map for Tx CMB. */ 732 error = bus_dmamap_load(sc->sc_dmat, sc->ale_cdata.ale_tx_cmb_map, 733 sc->ale_cdata.ale_tx_cmb, ALE_TX_CMB_SZ, NULL, BUS_DMA_WAITOK); 734 if (error) { 735 printf("%s: could not load DMA'able memory for Tx CMB.\n", 736 device_xname(sc->sc_dev)); 737 bus_dmamem_free(sc->sc_dmat, 738 &sc->ale_cdata.ale_tx_cmb_seg, 1); 739 return error; 740 } 741 742 sc->ale_cdata.ale_tx_cmb_paddr = 743 sc->ale_cdata.ale_tx_cmb_map->dm_segs[0].ds_addr; 744 745 for (i = 0; i < ALE_RX_PAGES; i++) { 746 /* 747 * Create DMA stuffs for Rx CMB. 748 */ 749 error = bus_dmamap_create(sc->sc_dmat, ALE_RX_CMB_SZ, 1, 750 ALE_RX_CMB_SZ, 0, BUS_DMA_NOWAIT, 751 &sc->ale_cdata.ale_rx_page[i].cmb_map); 752 if (error) { 753 sc->ale_cdata.ale_rx_page[i].cmb_map = NULL; 754 return ENOBUFS; 755 } 756 757 /* Allocate DMA'able memory for Rx CMB */ 758 error = bus_dmamem_alloc(sc->sc_dmat, ALE_RX_CMB_SZ, 759 ETHER_ALIGN, 0, &sc->ale_cdata.ale_rx_page[i].cmb_seg, 1, 760 &nsegs, BUS_DMA_WAITOK); 761 if (error) { 762 printf("%s: could not allocate DMA'able memory for " 763 "Rx CMB\n", device_xname(sc->sc_dev)); 764 return error; 765 } 766 error = bus_dmamem_map(sc->sc_dmat, 767 &sc->ale_cdata.ale_rx_page[i].cmb_seg, nsegs, 768 ALE_RX_CMB_SZ, 769 (void **)&sc->ale_cdata.ale_rx_page[i].cmb_addr, 770 BUS_DMA_NOWAIT); 771 if (error) 772 return ENOBUFS; 773 774 memset(sc->ale_cdata.ale_rx_page[i].cmb_addr, 0, ALE_RX_CMB_SZ); 775 776 /* Load the DMA map for Rx CMB */ 777 error = bus_dmamap_load(sc->sc_dmat, 778 sc->ale_cdata.ale_rx_page[i].cmb_map, 779 sc->ale_cdata.ale_rx_page[i].cmb_addr, 780 ALE_RX_CMB_SZ, NULL, BUS_DMA_WAITOK); 781 if (error) { 782 printf("%s: could not load DMA'able memory for Rx CMB" 783 "\n", device_xname(sc->sc_dev)); 784 bus_dmamem_free(sc->sc_dmat, 785 &sc->ale_cdata.ale_rx_page[i].cmb_seg, 1); 786 return error; 787 } 788 sc->ale_cdata.ale_rx_page[i].cmb_paddr = 789 sc->ale_cdata.ale_rx_page[i].cmb_map->dm_segs[0].ds_addr; 790 } 791 792 793 /* Create DMA maps for Tx buffers. */ 794 for (i = 0; i < ALE_TX_RING_CNT; i++) { 795 txd = &sc->ale_cdata.ale_txdesc[i]; 796 txd->tx_m = NULL; 797 txd->tx_dmamap = NULL; 798 error = bus_dmamap_create(sc->sc_dmat, ALE_TSO_MAXSIZE, 799 ALE_MAXTXSEGS, ALE_TSO_MAXSEGSIZE, 0, BUS_DMA_NOWAIT, 800 &txd->tx_dmamap); 801 if (error) { 802 txd->tx_dmamap = NULL; 803 printf("%s: could not create Tx dmamap.\n", 804 device_xname(sc->sc_dev)); 805 return error; 806 } 807 } 808 809 return 0; 810 } 811 812 static void 813 ale_dma_free(struct ale_softc *sc) 814 { 815 struct ale_txdesc *txd; 816 int i; 817 818 /* Tx buffers. */ 819 for (i = 0; i < ALE_TX_RING_CNT; i++) { 820 txd = &sc->ale_cdata.ale_txdesc[i]; 821 if (txd->tx_dmamap != NULL) { 822 bus_dmamap_destroy(sc->sc_dmat, txd->tx_dmamap); 823 txd->tx_dmamap = NULL; 824 } 825 } 826 827 /* Tx descriptor ring. */ 828 if (sc->ale_cdata.ale_tx_ring_map != NULL) 829 bus_dmamap_unload(sc->sc_dmat, sc->ale_cdata.ale_tx_ring_map); 830 if (sc->ale_cdata.ale_tx_ring_map != NULL && 831 sc->ale_cdata.ale_tx_ring != NULL) 832 bus_dmamem_free(sc->sc_dmat, 833 &sc->ale_cdata.ale_tx_ring_seg, 1); 834 sc->ale_cdata.ale_tx_ring = NULL; 835 sc->ale_cdata.ale_tx_ring_map = NULL; 836 837 /* Rx page block. */ 838 for (i = 0; i < ALE_RX_PAGES; i++) { 839 if (sc->ale_cdata.ale_rx_page[i].page_map != NULL) 840 bus_dmamap_unload(sc->sc_dmat, 841 sc->ale_cdata.ale_rx_page[i].page_map); 842 if (sc->ale_cdata.ale_rx_page[i].page_map != NULL && 843 sc->ale_cdata.ale_rx_page[i].page_addr != NULL) 844 bus_dmamem_free(sc->sc_dmat, 845 &sc->ale_cdata.ale_rx_page[i].page_seg, 1); 846 sc->ale_cdata.ale_rx_page[i].page_addr = NULL; 847 sc->ale_cdata.ale_rx_page[i].page_map = NULL; 848 } 849 850 /* Rx CMB. */ 851 for (i = 0; i < ALE_RX_PAGES; i++) { 852 if (sc->ale_cdata.ale_rx_page[i].cmb_map != NULL) 853 bus_dmamap_unload(sc->sc_dmat, 854 sc->ale_cdata.ale_rx_page[i].cmb_map); 855 if (sc->ale_cdata.ale_rx_page[i].cmb_map != NULL && 856 sc->ale_cdata.ale_rx_page[i].cmb_addr != NULL) 857 bus_dmamem_free(sc->sc_dmat, 858 &sc->ale_cdata.ale_rx_page[i].cmb_seg, 1); 859 sc->ale_cdata.ale_rx_page[i].cmb_addr = NULL; 860 sc->ale_cdata.ale_rx_page[i].cmb_map = NULL; 861 } 862 863 /* Tx CMB. */ 864 if (sc->ale_cdata.ale_tx_cmb_map != NULL) 865 bus_dmamap_unload(sc->sc_dmat, sc->ale_cdata.ale_tx_cmb_map); 866 if (sc->ale_cdata.ale_tx_cmb_map != NULL && 867 sc->ale_cdata.ale_tx_cmb != NULL) 868 bus_dmamem_free(sc->sc_dmat, 869 &sc->ale_cdata.ale_tx_cmb_seg, 1); 870 sc->ale_cdata.ale_tx_cmb = NULL; 871 sc->ale_cdata.ale_tx_cmb_map = NULL; 872 873 } 874 875 static int 876 ale_encap(struct ale_softc *sc, struct mbuf **m_head) 877 { 878 struct ale_txdesc *txd, *txd_last; 879 struct tx_desc *desc; 880 struct mbuf *m; 881 bus_dmamap_t map; 882 uint32_t cflags, poff, vtag; 883 int error, i, nsegs, prod; 884 #if NVLAN > 0 885 struct m_tag *mtag; 886 #endif 887 888 m = *m_head; 889 cflags = vtag = 0; 890 poff = 0; 891 892 prod = sc->ale_cdata.ale_tx_prod; 893 txd = &sc->ale_cdata.ale_txdesc[prod]; 894 txd_last = txd; 895 map = txd->tx_dmamap; 896 897 error = bus_dmamap_load_mbuf(sc->sc_dmat, map, *m_head, BUS_DMA_NOWAIT); 898 if (error == EFBIG) { 899 error = 0; 900 901 MGETHDR(m, M_DONTWAIT, MT_DATA); 902 if (m == NULL) { 903 printf("%s: can't defrag TX mbuf\n", 904 device_xname(sc->sc_dev)); 905 m_freem(*m_head); 906 *m_head = NULL; 907 return ENOBUFS; 908 } 909 910 M_COPY_PKTHDR(m, *m_head); 911 if ((*m_head)->m_pkthdr.len > MHLEN) { 912 MCLGET(m, M_DONTWAIT); 913 if (!(m->m_flags & M_EXT)) { 914 m_freem(*m_head); 915 m_freem(m); 916 *m_head = NULL; 917 return ENOBUFS; 918 } 919 } 920 m_copydata(*m_head, 0, (*m_head)->m_pkthdr.len, 921 mtod(m, void *)); 922 m_freem(*m_head); 923 m->m_len = m->m_pkthdr.len; 924 *m_head = m; 925 926 error = bus_dmamap_load_mbuf(sc->sc_dmat, map, *m_head, 927 BUS_DMA_NOWAIT); 928 929 if (error != 0) { 930 printf("%s: could not load defragged TX mbuf\n", 931 device_xname(sc->sc_dev)); 932 if (!error) { 933 bus_dmamap_unload(sc->sc_dmat, map); 934 error = EFBIG; 935 } 936 m_freem(*m_head); 937 *m_head = NULL; 938 return error; 939 } 940 } else if (error) { 941 printf("%s: could not load TX mbuf\n", device_xname(sc->sc_dev)); 942 return error; 943 } 944 945 nsegs = map->dm_nsegs; 946 947 if (nsegs == 0) { 948 m_freem(*m_head); 949 *m_head = NULL; 950 return EIO; 951 } 952 953 /* Check descriptor overrun. */ 954 if (sc->ale_cdata.ale_tx_cnt + nsegs >= ALE_TX_RING_CNT - 2) { 955 bus_dmamap_unload(sc->sc_dmat, map); 956 return ENOBUFS; 957 } 958 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 959 BUS_DMASYNC_PREWRITE); 960 961 m = *m_head; 962 /* Configure Tx checksum offload. */ 963 if ((m->m_pkthdr.csum_flags & ALE_CSUM_FEATURES) != 0) { 964 /* 965 * AR81xx supports Tx custom checksum offload feature 966 * that offloads single 16bit checksum computation. 967 * So you can choose one among IP, TCP and UDP. 968 * Normally driver sets checksum start/insertion 969 * position from the information of TCP/UDP frame as 970 * TCP/UDP checksum takes more time than that of IP. 971 * However it seems that custom checksum offload 972 * requires 4 bytes aligned Tx buffers due to hardware 973 * bug. 974 * AR81xx also supports explicit Tx checksum computation 975 * if it is told that the size of IP header and TCP 976 * header(for UDP, the header size does not matter 977 * because it's fixed length). However with this scheme 978 * TSO does not work so you have to choose one either 979 * TSO or explicit Tx checksum offload. I chosen TSO 980 * plus custom checksum offload with work-around which 981 * will cover most common usage for this consumer 982 * ethernet controller. The work-around takes a lot of 983 * CPU cycles if Tx buffer is not aligned on 4 bytes 984 * boundary, though. 985 */ 986 cflags |= ALE_TD_CXSUM; 987 /* Set checksum start offset. */ 988 cflags |= (poff << ALE_TD_CSUM_PLOADOFFSET_SHIFT); 989 } 990 991 #if NVLAN > 0 992 /* Configure VLAN hardware tag insertion. */ 993 if ((mtag = VLAN_OUTPUT_TAG(&sc->sc_ec, m))) { 994 vtag = ALE_TX_VLAN_TAG(htons(VLAN_TAG_VALUE(mtag))); 995 vtag = ((vtag << ALE_TD_VLAN_SHIFT) & ALE_TD_VLAN_MASK); 996 cflags |= ALE_TD_INSERT_VLAN_TAG; 997 } 998 #endif 999 1000 desc = NULL; 1001 for (i = 0; i < nsegs; i++) { 1002 desc = &sc->ale_cdata.ale_tx_ring[prod]; 1003 desc->addr = htole64(map->dm_segs[i].ds_addr); 1004 desc->len = 1005 htole32(ALE_TX_BYTES(map->dm_segs[i].ds_len) | vtag); 1006 desc->flags = htole32(cflags); 1007 sc->ale_cdata.ale_tx_cnt++; 1008 ALE_DESC_INC(prod, ALE_TX_RING_CNT); 1009 } 1010 /* Update producer index. */ 1011 sc->ale_cdata.ale_tx_prod = prod; 1012 1013 /* Finally set EOP on the last descriptor. */ 1014 prod = (prod + ALE_TX_RING_CNT - 1) % ALE_TX_RING_CNT; 1015 desc = &sc->ale_cdata.ale_tx_ring[prod]; 1016 desc->flags |= htole32(ALE_TD_EOP); 1017 1018 /* Swap dmamap of the first and the last. */ 1019 txd = &sc->ale_cdata.ale_txdesc[prod]; 1020 map = txd_last->tx_dmamap; 1021 txd_last->tx_dmamap = txd->tx_dmamap; 1022 txd->tx_dmamap = map; 1023 txd->tx_m = m; 1024 1025 /* Sync descriptors. */ 1026 bus_dmamap_sync(sc->sc_dmat, sc->ale_cdata.ale_tx_ring_map, 0, 1027 sc->ale_cdata.ale_tx_ring_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 1028 1029 return 0; 1030 } 1031 1032 static void 1033 ale_start(struct ifnet *ifp) 1034 { 1035 struct ale_softc *sc = ifp->if_softc; 1036 struct mbuf *m_head; 1037 int enq; 1038 1039 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 1040 return; 1041 1042 /* Reclaim transmitted frames. */ 1043 if (sc->ale_cdata.ale_tx_cnt >= ALE_TX_DESC_HIWAT) 1044 ale_txeof(sc); 1045 1046 enq = 0; 1047 for (;;) { 1048 IFQ_DEQUEUE(&ifp->if_snd, m_head); 1049 if (m_head == NULL) 1050 break; 1051 1052 /* 1053 * Pack the data into the transmit ring. If we 1054 * don't have room, set the OACTIVE flag and wait 1055 * for the NIC to drain the ring. 1056 */ 1057 if (ale_encap(sc, &m_head)) { 1058 if (m_head == NULL) 1059 break; 1060 ifp->if_flags |= IFF_OACTIVE; 1061 break; 1062 } 1063 enq = 1; 1064 1065 #if NBPFILTER > 0 1066 /* 1067 * If there's a BPF listener, bounce a copy of this frame 1068 * to him. 1069 */ 1070 if (ifp->if_bpf != NULL) 1071 bpf_mtap(ifp->if_bpf, m_head); 1072 #endif 1073 } 1074 1075 if (enq) { 1076 /* Kick. */ 1077 CSR_WRITE_4(sc, ALE_MBOX_TPD_PROD_IDX, 1078 sc->ale_cdata.ale_tx_prod); 1079 1080 /* Set a timeout in case the chip goes out to lunch. */ 1081 ifp->if_timer = ALE_TX_TIMEOUT; 1082 } 1083 } 1084 1085 static void 1086 ale_watchdog(struct ifnet *ifp) 1087 { 1088 struct ale_softc *sc = ifp->if_softc; 1089 1090 if ((sc->ale_flags & ALE_FLAG_LINK) == 0) { 1091 printf("%s: watchdog timeout (missed link)\n", 1092 device_xname(sc->sc_dev)); 1093 ifp->if_oerrors++; 1094 ale_init(ifp); 1095 return; 1096 } 1097 1098 printf("%s: watchdog timeout\n", device_xname(sc->sc_dev)); 1099 ifp->if_oerrors++; 1100 ale_init(ifp); 1101 1102 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 1103 ale_start(ifp); 1104 } 1105 1106 static int 1107 ale_ioctl(struct ifnet *ifp, u_long cmd, void *data) 1108 { 1109 struct ale_softc *sc = ifp->if_softc; 1110 int s, error; 1111 1112 s = splnet(); 1113 1114 error = ether_ioctl(ifp, cmd, data); 1115 if (error == ENETRESET) { 1116 if (ifp->if_flags & IFF_RUNNING) 1117 ale_rxfilter(sc); 1118 error = 0; 1119 } 1120 1121 splx(s); 1122 return error; 1123 } 1124 1125 static void 1126 ale_mac_config(struct ale_softc *sc) 1127 { 1128 struct mii_data *mii; 1129 uint32_t reg; 1130 1131 mii = &sc->sc_miibus; 1132 reg = CSR_READ_4(sc, ALE_MAC_CFG); 1133 reg &= ~(MAC_CFG_FULL_DUPLEX | MAC_CFG_TX_FC | MAC_CFG_RX_FC | 1134 MAC_CFG_SPEED_MASK); 1135 1136 /* Reprogram MAC with resolved speed/duplex. */ 1137 switch (IFM_SUBTYPE(mii->mii_media_active)) { 1138 case IFM_10_T: 1139 case IFM_100_TX: 1140 reg |= MAC_CFG_SPEED_10_100; 1141 break; 1142 case IFM_1000_T: 1143 reg |= MAC_CFG_SPEED_1000; 1144 break; 1145 } 1146 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 1147 reg |= MAC_CFG_FULL_DUPLEX; 1148 #ifdef notyet 1149 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0) 1150 reg |= MAC_CFG_TX_FC; 1151 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0) 1152 reg |= MAC_CFG_RX_FC; 1153 #endif 1154 } 1155 CSR_WRITE_4(sc, ALE_MAC_CFG, reg); 1156 } 1157 1158 static void 1159 ale_stats_clear(struct ale_softc *sc) 1160 { 1161 struct smb sb; 1162 uint32_t *reg; 1163 int i; 1164 1165 for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered; reg++) { 1166 CSR_READ_4(sc, ALE_RX_MIB_BASE + i); 1167 i += sizeof(uint32_t); 1168 } 1169 /* Read Tx statistics. */ 1170 for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes; reg++) { 1171 CSR_READ_4(sc, ALE_TX_MIB_BASE + i); 1172 i += sizeof(uint32_t); 1173 } 1174 } 1175 1176 static void 1177 ale_stats_update(struct ale_softc *sc) 1178 { 1179 struct ifnet *ifp = &sc->sc_ec.ec_if; 1180 struct ale_hw_stats *stat; 1181 struct smb sb, *smb; 1182 uint32_t *reg; 1183 int i; 1184 1185 stat = &sc->ale_stats; 1186 smb = &sb; 1187 1188 /* Read Rx statistics. */ 1189 for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered; reg++) { 1190 *reg = CSR_READ_4(sc, ALE_RX_MIB_BASE + i); 1191 i += sizeof(uint32_t); 1192 } 1193 /* Read Tx statistics. */ 1194 for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes; reg++) { 1195 *reg = CSR_READ_4(sc, ALE_TX_MIB_BASE + i); 1196 i += sizeof(uint32_t); 1197 } 1198 1199 /* Rx stats. */ 1200 stat->rx_frames += smb->rx_frames; 1201 stat->rx_bcast_frames += smb->rx_bcast_frames; 1202 stat->rx_mcast_frames += smb->rx_mcast_frames; 1203 stat->rx_pause_frames += smb->rx_pause_frames; 1204 stat->rx_control_frames += smb->rx_control_frames; 1205 stat->rx_crcerrs += smb->rx_crcerrs; 1206 stat->rx_lenerrs += smb->rx_lenerrs; 1207 stat->rx_bytes += smb->rx_bytes; 1208 stat->rx_runts += smb->rx_runts; 1209 stat->rx_fragments += smb->rx_fragments; 1210 stat->rx_pkts_64 += smb->rx_pkts_64; 1211 stat->rx_pkts_65_127 += smb->rx_pkts_65_127; 1212 stat->rx_pkts_128_255 += smb->rx_pkts_128_255; 1213 stat->rx_pkts_256_511 += smb->rx_pkts_256_511; 1214 stat->rx_pkts_512_1023 += smb->rx_pkts_512_1023; 1215 stat->rx_pkts_1024_1518 += smb->rx_pkts_1024_1518; 1216 stat->rx_pkts_1519_max += smb->rx_pkts_1519_max; 1217 stat->rx_pkts_truncated += smb->rx_pkts_truncated; 1218 stat->rx_fifo_oflows += smb->rx_fifo_oflows; 1219 stat->rx_rrs_errs += smb->rx_rrs_errs; 1220 stat->rx_alignerrs += smb->rx_alignerrs; 1221 stat->rx_bcast_bytes += smb->rx_bcast_bytes; 1222 stat->rx_mcast_bytes += smb->rx_mcast_bytes; 1223 stat->rx_pkts_filtered += smb->rx_pkts_filtered; 1224 1225 /* Tx stats. */ 1226 stat->tx_frames += smb->tx_frames; 1227 stat->tx_bcast_frames += smb->tx_bcast_frames; 1228 stat->tx_mcast_frames += smb->tx_mcast_frames; 1229 stat->tx_pause_frames += smb->tx_pause_frames; 1230 stat->tx_excess_defer += smb->tx_excess_defer; 1231 stat->tx_control_frames += smb->tx_control_frames; 1232 stat->tx_deferred += smb->tx_deferred; 1233 stat->tx_bytes += smb->tx_bytes; 1234 stat->tx_pkts_64 += smb->tx_pkts_64; 1235 stat->tx_pkts_65_127 += smb->tx_pkts_65_127; 1236 stat->tx_pkts_128_255 += smb->tx_pkts_128_255; 1237 stat->tx_pkts_256_511 += smb->tx_pkts_256_511; 1238 stat->tx_pkts_512_1023 += smb->tx_pkts_512_1023; 1239 stat->tx_pkts_1024_1518 += smb->tx_pkts_1024_1518; 1240 stat->tx_pkts_1519_max += smb->tx_pkts_1519_max; 1241 stat->tx_single_colls += smb->tx_single_colls; 1242 stat->tx_multi_colls += smb->tx_multi_colls; 1243 stat->tx_late_colls += smb->tx_late_colls; 1244 stat->tx_excess_colls += smb->tx_excess_colls; 1245 stat->tx_abort += smb->tx_abort; 1246 stat->tx_underrun += smb->tx_underrun; 1247 stat->tx_desc_underrun += smb->tx_desc_underrun; 1248 stat->tx_lenerrs += smb->tx_lenerrs; 1249 stat->tx_pkts_truncated += smb->tx_pkts_truncated; 1250 stat->tx_bcast_bytes += smb->tx_bcast_bytes; 1251 stat->tx_mcast_bytes += smb->tx_mcast_bytes; 1252 1253 /* Update counters in ifnet. */ 1254 ifp->if_opackets += smb->tx_frames; 1255 1256 ifp->if_collisions += smb->tx_single_colls + 1257 smb->tx_multi_colls * 2 + smb->tx_late_colls + 1258 smb->tx_abort * HDPX_CFG_RETRY_DEFAULT; 1259 1260 /* 1261 * XXX 1262 * tx_pkts_truncated counter looks suspicious. It constantly 1263 * increments with no sign of Tx errors. This may indicate 1264 * the counter name is not correct one so I've removed the 1265 * counter in output errors. 1266 */ 1267 ifp->if_oerrors += smb->tx_abort + smb->tx_late_colls + 1268 smb->tx_underrun; 1269 1270 ifp->if_ipackets += smb->rx_frames; 1271 1272 ifp->if_ierrors += smb->rx_crcerrs + smb->rx_lenerrs + 1273 smb->rx_runts + smb->rx_pkts_truncated + 1274 smb->rx_fifo_oflows + smb->rx_rrs_errs + 1275 smb->rx_alignerrs; 1276 } 1277 1278 static int 1279 ale_intr(void *xsc) 1280 { 1281 struct ale_softc *sc = xsc; 1282 struct ifnet *ifp = &sc->sc_ec.ec_if; 1283 uint32_t status; 1284 1285 status = CSR_READ_4(sc, ALE_INTR_STATUS); 1286 if ((status & ALE_INTRS) == 0) 1287 return 0; 1288 1289 /* Acknowledge and disable interrupts. */ 1290 CSR_WRITE_4(sc, ALE_INTR_STATUS, status | INTR_DIS_INT); 1291 1292 if (ifp->if_flags & IFF_RUNNING) { 1293 int error; 1294 1295 error = ale_rxeof(sc); 1296 if (error) { 1297 sc->ale_stats.reset_brk_seq++; 1298 ale_init(ifp); 1299 return 0; 1300 } 1301 1302 if (status & (INTR_DMA_RD_TO_RST | INTR_DMA_WR_TO_RST)) { 1303 if (status & INTR_DMA_RD_TO_RST) 1304 printf("%s: DMA read error! -- resetting\n", 1305 device_xname(sc->sc_dev)); 1306 if (status & INTR_DMA_WR_TO_RST) 1307 printf("%s: DMA write error! -- resetting\n", 1308 device_xname(sc->sc_dev)); 1309 ale_init(ifp); 1310 return 0; 1311 } 1312 1313 ale_txeof(sc); 1314 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 1315 ale_start(ifp); 1316 } 1317 1318 /* Re-enable interrupts. */ 1319 CSR_WRITE_4(sc, ALE_INTR_STATUS, 0x7FFFFFFF); 1320 return 1; 1321 } 1322 1323 static void 1324 ale_txeof(struct ale_softc *sc) 1325 { 1326 struct ifnet *ifp = &sc->sc_ec.ec_if; 1327 struct ale_txdesc *txd; 1328 uint32_t cons, prod; 1329 int prog; 1330 1331 if (sc->ale_cdata.ale_tx_cnt == 0) 1332 return; 1333 1334 bus_dmamap_sync(sc->sc_dmat, sc->ale_cdata.ale_tx_ring_map, 0, 1335 sc->ale_cdata.ale_tx_ring_map->dm_mapsize, BUS_DMASYNC_POSTREAD); 1336 if ((sc->ale_flags & ALE_FLAG_TXCMB_BUG) == 0) { 1337 bus_dmamap_sync(sc->sc_dmat, sc->ale_cdata.ale_tx_cmb_map, 0, 1338 sc->ale_cdata.ale_tx_cmb_map->dm_mapsize, 1339 BUS_DMASYNC_POSTREAD); 1340 prod = *sc->ale_cdata.ale_tx_cmb & TPD_CNT_MASK; 1341 } else 1342 prod = CSR_READ_2(sc, ALE_TPD_CONS_IDX); 1343 cons = sc->ale_cdata.ale_tx_cons; 1344 /* 1345 * Go through our Tx list and free mbufs for those 1346 * frames which have been transmitted. 1347 */ 1348 for (prog = 0; cons != prod; prog++, 1349 ALE_DESC_INC(cons, ALE_TX_RING_CNT)) { 1350 if (sc->ale_cdata.ale_tx_cnt <= 0) 1351 break; 1352 prog++; 1353 ifp->if_flags &= ~IFF_OACTIVE; 1354 sc->ale_cdata.ale_tx_cnt--; 1355 txd = &sc->ale_cdata.ale_txdesc[cons]; 1356 if (txd->tx_m != NULL) { 1357 /* Reclaim transmitted mbufs. */ 1358 bus_dmamap_unload(sc->sc_dmat, txd->tx_dmamap); 1359 m_freem(txd->tx_m); 1360 txd->tx_m = NULL; 1361 } 1362 } 1363 1364 if (prog > 0) { 1365 sc->ale_cdata.ale_tx_cons = cons; 1366 /* 1367 * Unarm watchdog timer only when there is no pending 1368 * Tx descriptors in queue. 1369 */ 1370 if (sc->ale_cdata.ale_tx_cnt == 0) 1371 ifp->if_timer = 0; 1372 } 1373 } 1374 1375 static void 1376 ale_rx_update_page(struct ale_softc *sc, struct ale_rx_page **page, 1377 uint32_t length, uint32_t *prod) 1378 { 1379 struct ale_rx_page *rx_page; 1380 1381 rx_page = *page; 1382 /* Update consumer position. */ 1383 rx_page->cons += roundup(length + sizeof(struct rx_rs), 1384 ALE_RX_PAGE_ALIGN); 1385 if (rx_page->cons >= ALE_RX_PAGE_SZ) { 1386 /* 1387 * End of Rx page reached, let hardware reuse 1388 * this page. 1389 */ 1390 rx_page->cons = 0; 1391 *rx_page->cmb_addr = 0; 1392 bus_dmamap_sync(sc->sc_dmat, rx_page->cmb_map, 0, 1393 rx_page->cmb_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 1394 CSR_WRITE_1(sc, ALE_RXF0_PAGE0 + sc->ale_cdata.ale_rx_curp, 1395 RXF_VALID); 1396 /* Switch to alternate Rx page. */ 1397 sc->ale_cdata.ale_rx_curp ^= 1; 1398 rx_page = *page = 1399 &sc->ale_cdata.ale_rx_page[sc->ale_cdata.ale_rx_curp]; 1400 /* Page flipped, sync CMB and Rx page. */ 1401 bus_dmamap_sync(sc->sc_dmat, rx_page->page_map, 0, 1402 rx_page->page_map->dm_mapsize, BUS_DMASYNC_POSTREAD); 1403 bus_dmamap_sync(sc->sc_dmat, rx_page->cmb_map, 0, 1404 rx_page->cmb_map->dm_mapsize, BUS_DMASYNC_POSTREAD); 1405 /* Sync completed, cache updated producer index. */ 1406 *prod = *rx_page->cmb_addr; 1407 } 1408 } 1409 1410 1411 /* 1412 * It seems that AR81xx controller can compute partial checksum. 1413 * The partial checksum value can be used to accelerate checksum 1414 * computation for fragmented TCP/UDP packets. Upper network stack 1415 * already takes advantage of the partial checksum value in IP 1416 * reassembly stage. But I'm not sure the correctness of the 1417 * partial hardware checksum assistance due to lack of data sheet. 1418 * In addition, the Rx feature of controller that requires copying 1419 * for every frames effectively nullifies one of most nice offload 1420 * capability of controller. 1421 */ 1422 static void 1423 ale_rxcsum(struct ale_softc *sc, struct mbuf *m, uint32_t status) 1424 { 1425 if (status & ALE_RD_IPCSUM_NOK) 1426 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 1427 1428 if ((sc->ale_flags & ALE_FLAG_RXCSUM_BUG) == 0) { 1429 if (((status & ALE_RD_IPV4_FRAG) == 0) && 1430 ((status & (ALE_RD_TCP | ALE_RD_UDP)) != 0) && 1431 (status & ALE_RD_TCP_UDPCSUM_NOK)) 1432 { 1433 m->m_pkthdr.csum_flags |= M_CSUM_TCP_UDP_BAD; 1434 } 1435 } else { 1436 if ((status & (ALE_RD_TCP | ALE_RD_UDP)) != 0) { 1437 if (status & ALE_RD_TCP_UDPCSUM_NOK) { 1438 m->m_pkthdr.csum_flags |= M_CSUM_TCP_UDP_BAD; 1439 } 1440 } 1441 } 1442 /* 1443 * Don't mark bad checksum for TCP/UDP frames 1444 * as fragmented frames may always have set 1445 * bad checksummed bit of frame status. 1446 */ 1447 } 1448 1449 /* Process received frames. */ 1450 static int 1451 ale_rxeof(struct ale_softc *sc) 1452 { 1453 struct ifnet *ifp = &sc->sc_ec.ec_if; 1454 struct ale_rx_page *rx_page; 1455 struct rx_rs *rs; 1456 struct mbuf *m; 1457 uint32_t length, prod, seqno, status; 1458 int prog; 1459 1460 rx_page = &sc->ale_cdata.ale_rx_page[sc->ale_cdata.ale_rx_curp]; 1461 bus_dmamap_sync(sc->sc_dmat, rx_page->cmb_map, 0, 1462 rx_page->cmb_map->dm_mapsize, BUS_DMASYNC_POSTREAD); 1463 bus_dmamap_sync(sc->sc_dmat, rx_page->page_map, 0, 1464 rx_page->page_map->dm_mapsize, BUS_DMASYNC_POSTREAD); 1465 /* 1466 * Don't directly access producer index as hardware may 1467 * update it while Rx handler is in progress. It would 1468 * be even better if there is a way to let hardware 1469 * know how far driver processed its received frames. 1470 * Alternatively, hardware could provide a way to disable 1471 * CMB updates until driver acknowledges the end of CMB 1472 * access. 1473 */ 1474 prod = *rx_page->cmb_addr; 1475 for (prog = 0; ; prog++) { 1476 if (rx_page->cons >= prod) 1477 break; 1478 rs = (struct rx_rs *)(rx_page->page_addr + rx_page->cons); 1479 seqno = ALE_RX_SEQNO(le32toh(rs->seqno)); 1480 if (sc->ale_cdata.ale_rx_seqno != seqno) { 1481 /* 1482 * Normally I believe this should not happen unless 1483 * severe driver bug or corrupted memory. However 1484 * it seems to happen under certain conditions which 1485 * is triggered by abrupt Rx events such as initiation 1486 * of bulk transfer of remote host. It's not easy to 1487 * reproduce this and I doubt it could be related 1488 * with FIFO overflow of hardware or activity of Tx 1489 * CMB updates. I also remember similar behaviour 1490 * seen on RealTek 8139 which uses resembling Rx 1491 * scheme. 1492 */ 1493 if (aledebug) 1494 printf("%s: garbled seq: %u, expected: %u -- " 1495 "resetting!\n", device_xname(sc->sc_dev), 1496 seqno, sc->ale_cdata.ale_rx_seqno); 1497 return EIO; 1498 } 1499 /* Frame received. */ 1500 sc->ale_cdata.ale_rx_seqno++; 1501 length = ALE_RX_BYTES(le32toh(rs->length)); 1502 status = le32toh(rs->flags); 1503 if (status & ALE_RD_ERROR) { 1504 /* 1505 * We want to pass the following frames to upper 1506 * layer regardless of error status of Rx return 1507 * status. 1508 * 1509 * o IP/TCP/UDP checksum is bad. 1510 * o frame length and protocol specific length 1511 * does not match. 1512 */ 1513 if (status & (ALE_RD_CRC | ALE_RD_CODE | 1514 ALE_RD_DRIBBLE | ALE_RD_RUNT | ALE_RD_OFLOW | 1515 ALE_RD_TRUNC)) { 1516 ale_rx_update_page(sc, &rx_page, length, &prod); 1517 continue; 1518 } 1519 } 1520 /* 1521 * m_devget(9) is major bottle-neck of ale(4)(It comes 1522 * from hardware limitation). For jumbo frames we could 1523 * get a slightly better performance if driver use 1524 * m_getjcl(9) with proper buffer size argument. However 1525 * that would make code more complicated and I don't 1526 * think users would expect good Rx performance numbers 1527 * on these low-end consumer ethernet controller. 1528 */ 1529 m = m_devget((char *)(rs + 1), length - ETHER_CRC_LEN, 1530 0, ifp, NULL); 1531 if (m == NULL) { 1532 ifp->if_iqdrops++; 1533 ale_rx_update_page(sc, &rx_page, length, &prod); 1534 continue; 1535 } 1536 if (status & ALE_RD_IPV4) 1537 ale_rxcsum(sc, m, status); 1538 #if NVLAN > 0 1539 if (status & ALE_RD_VLAN) { 1540 uint32_t vtags = ALE_RX_VLAN(le32toh(rs->vtags)); 1541 VLAN_INPUT_TAG(ifp, m, ALE_RX_VLAN_TAG(vtags), ); 1542 } 1543 #endif 1544 1545 1546 #if NBPFILTER > 0 1547 if (ifp->if_bpf) 1548 bpf_mtap(ifp->if_bpf, m); 1549 #endif 1550 1551 /* Pass it to upper layer. */ 1552 ether_input(ifp, m); 1553 1554 ale_rx_update_page(sc, &rx_page, length, &prod); 1555 } 1556 1557 return 0; 1558 } 1559 1560 static void 1561 ale_tick(void *xsc) 1562 { 1563 struct ale_softc *sc = xsc; 1564 struct mii_data *mii = &sc->sc_miibus; 1565 int s; 1566 1567 s = splnet(); 1568 mii_tick(mii); 1569 ale_stats_update(sc); 1570 splx(s); 1571 1572 callout_schedule(&sc->sc_tick_ch, hz); 1573 } 1574 1575 static void 1576 ale_reset(struct ale_softc *sc) 1577 { 1578 uint32_t reg; 1579 int i; 1580 1581 /* Initialize PCIe module. From Linux. */ 1582 CSR_WRITE_4(sc, 0x1008, CSR_READ_4(sc, 0x1008) | 0x8000); 1583 1584 CSR_WRITE_4(sc, ALE_MASTER_CFG, MASTER_RESET); 1585 for (i = ALE_RESET_TIMEOUT; i > 0; i--) { 1586 DELAY(10); 1587 if ((CSR_READ_4(sc, ALE_MASTER_CFG) & MASTER_RESET) == 0) 1588 break; 1589 } 1590 if (i == 0) 1591 printf("%s: master reset timeout!\n", device_xname(sc->sc_dev)); 1592 1593 for (i = ALE_RESET_TIMEOUT; i > 0; i--) { 1594 if ((reg = CSR_READ_4(sc, ALE_IDLE_STATUS)) == 0) 1595 break; 1596 DELAY(10); 1597 } 1598 1599 if (i == 0) 1600 printf("%s: reset timeout(0x%08x)!\n", device_xname(sc->sc_dev), 1601 reg); 1602 } 1603 1604 static int 1605 ale_init(struct ifnet *ifp) 1606 { 1607 struct ale_softc *sc = ifp->if_softc; 1608 struct mii_data *mii; 1609 uint8_t eaddr[ETHER_ADDR_LEN]; 1610 bus_addr_t paddr; 1611 uint32_t reg, rxf_hi, rxf_lo; 1612 1613 /* 1614 * Cancel any pending I/O. 1615 */ 1616 ale_stop(ifp, 0); 1617 1618 /* 1619 * Reset the chip to a known state. 1620 */ 1621 ale_reset(sc); 1622 1623 /* Initialize Tx descriptors, DMA memory blocks. */ 1624 ale_init_rx_pages(sc); 1625 ale_init_tx_ring(sc); 1626 1627 /* Reprogram the station address. */ 1628 memcpy(eaddr, CLLADDR(ifp->if_sadl), ETHER_ADDR_LEN); 1629 CSR_WRITE_4(sc, ALE_PAR0, 1630 eaddr[2] << 24 | eaddr[3] << 16 | eaddr[4] << 8 | eaddr[5]); 1631 CSR_WRITE_4(sc, ALE_PAR1, eaddr[0] << 8 | eaddr[1]); 1632 1633 /* 1634 * Clear WOL status and disable all WOL feature as WOL 1635 * would interfere Rx operation under normal environments. 1636 */ 1637 CSR_READ_4(sc, ALE_WOL_CFG); 1638 CSR_WRITE_4(sc, ALE_WOL_CFG, 0); 1639 1640 /* 1641 * Set Tx descriptor/RXF0/CMB base addresses. They share 1642 * the same high address part of DMAable region. 1643 */ 1644 paddr = sc->ale_cdata.ale_tx_ring_paddr; 1645 CSR_WRITE_4(sc, ALE_TPD_ADDR_HI, ALE_ADDR_HI(paddr)); 1646 CSR_WRITE_4(sc, ALE_TPD_ADDR_LO, ALE_ADDR_LO(paddr)); 1647 CSR_WRITE_4(sc, ALE_TPD_CNT, 1648 (ALE_TX_RING_CNT << TPD_CNT_SHIFT) & TPD_CNT_MASK); 1649 1650 /* Set Rx page base address, note we use single queue. */ 1651 paddr = sc->ale_cdata.ale_rx_page[0].page_paddr; 1652 CSR_WRITE_4(sc, ALE_RXF0_PAGE0_ADDR_LO, ALE_ADDR_LO(paddr)); 1653 paddr = sc->ale_cdata.ale_rx_page[1].page_paddr; 1654 CSR_WRITE_4(sc, ALE_RXF0_PAGE1_ADDR_LO, ALE_ADDR_LO(paddr)); 1655 1656 /* Set Tx/Rx CMB addresses. */ 1657 paddr = sc->ale_cdata.ale_tx_cmb_paddr; 1658 CSR_WRITE_4(sc, ALE_TX_CMB_ADDR_LO, ALE_ADDR_LO(paddr)); 1659 paddr = sc->ale_cdata.ale_rx_page[0].cmb_paddr; 1660 CSR_WRITE_4(sc, ALE_RXF0_CMB0_ADDR_LO, ALE_ADDR_LO(paddr)); 1661 paddr = sc->ale_cdata.ale_rx_page[1].cmb_paddr; 1662 CSR_WRITE_4(sc, ALE_RXF0_CMB1_ADDR_LO, ALE_ADDR_LO(paddr)); 1663 1664 /* Mark RXF0 is valid. */ 1665 CSR_WRITE_1(sc, ALE_RXF0_PAGE0, RXF_VALID); 1666 CSR_WRITE_1(sc, ALE_RXF0_PAGE1, RXF_VALID); 1667 /* 1668 * No need to initialize RFX1/RXF2/RXF3. We don't use 1669 * multi-queue yet. 1670 */ 1671 1672 /* Set Rx page size, excluding guard frame size. */ 1673 CSR_WRITE_4(sc, ALE_RXF_PAGE_SIZE, ALE_RX_PAGE_SZ); 1674 1675 /* Tell hardware that we're ready to load DMA blocks. */ 1676 CSR_WRITE_4(sc, ALE_DMA_BLOCK, DMA_BLOCK_LOAD); 1677 1678 /* Set Rx/Tx interrupt trigger threshold. */ 1679 CSR_WRITE_4(sc, ALE_INT_TRIG_THRESH, (1 << INT_TRIG_RX_THRESH_SHIFT) | 1680 (4 << INT_TRIG_TX_THRESH_SHIFT)); 1681 /* 1682 * XXX 1683 * Set interrupt trigger timer, its purpose and relation 1684 * with interrupt moderation mechanism is not clear yet. 1685 */ 1686 CSR_WRITE_4(sc, ALE_INT_TRIG_TIMER, 1687 ((ALE_USECS(10) << INT_TRIG_RX_TIMER_SHIFT) | 1688 (ALE_USECS(1000) << INT_TRIG_TX_TIMER_SHIFT))); 1689 1690 /* Configure interrupt moderation timer. */ 1691 sc->ale_int_rx_mod = ALE_IM_RX_TIMER_DEFAULT; 1692 sc->ale_int_tx_mod = ALE_IM_TX_TIMER_DEFAULT; 1693 reg = ALE_USECS(sc->ale_int_rx_mod) << IM_TIMER_RX_SHIFT; 1694 reg |= ALE_USECS(sc->ale_int_tx_mod) << IM_TIMER_TX_SHIFT; 1695 CSR_WRITE_4(sc, ALE_IM_TIMER, reg); 1696 reg = CSR_READ_4(sc, ALE_MASTER_CFG); 1697 reg &= ~(MASTER_CHIP_REV_MASK | MASTER_CHIP_ID_MASK); 1698 reg &= ~(MASTER_IM_RX_TIMER_ENB | MASTER_IM_TX_TIMER_ENB); 1699 if (ALE_USECS(sc->ale_int_rx_mod) != 0) 1700 reg |= MASTER_IM_RX_TIMER_ENB; 1701 if (ALE_USECS(sc->ale_int_tx_mod) != 0) 1702 reg |= MASTER_IM_TX_TIMER_ENB; 1703 CSR_WRITE_4(sc, ALE_MASTER_CFG, reg); 1704 CSR_WRITE_2(sc, ALE_INTR_CLR_TIMER, ALE_USECS(1000)); 1705 1706 /* Set Maximum frame size of controller. */ 1707 if (ifp->if_mtu < ETHERMTU) 1708 sc->ale_max_frame_size = ETHERMTU; 1709 else 1710 sc->ale_max_frame_size = ifp->if_mtu; 1711 sc->ale_max_frame_size += ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN + ETHER_CRC_LEN; 1712 CSR_WRITE_4(sc, ALE_FRAME_SIZE, sc->ale_max_frame_size); 1713 1714 /* Configure IPG/IFG parameters. */ 1715 CSR_WRITE_4(sc, ALE_IPG_IFG_CFG, 1716 ((IPG_IFG_IPGT_DEFAULT << IPG_IFG_IPGT_SHIFT) & IPG_IFG_IPGT_MASK) | 1717 ((IPG_IFG_MIFG_DEFAULT << IPG_IFG_MIFG_SHIFT) & IPG_IFG_MIFG_MASK) | 1718 ((IPG_IFG_IPG1_DEFAULT << IPG_IFG_IPG1_SHIFT) & IPG_IFG_IPG1_MASK) | 1719 ((IPG_IFG_IPG2_DEFAULT << IPG_IFG_IPG2_SHIFT) & IPG_IFG_IPG2_MASK)); 1720 1721 /* Set parameters for half-duplex media. */ 1722 CSR_WRITE_4(sc, ALE_HDPX_CFG, 1723 ((HDPX_CFG_LCOL_DEFAULT << HDPX_CFG_LCOL_SHIFT) & 1724 HDPX_CFG_LCOL_MASK) | 1725 ((HDPX_CFG_RETRY_DEFAULT << HDPX_CFG_RETRY_SHIFT) & 1726 HDPX_CFG_RETRY_MASK) | HDPX_CFG_EXC_DEF_EN | 1727 ((HDPX_CFG_ABEBT_DEFAULT << HDPX_CFG_ABEBT_SHIFT) & 1728 HDPX_CFG_ABEBT_MASK) | 1729 ((HDPX_CFG_JAMIPG_DEFAULT << HDPX_CFG_JAMIPG_SHIFT) & 1730 HDPX_CFG_JAMIPG_MASK)); 1731 1732 /* Configure Tx jumbo frame parameters. */ 1733 if ((sc->ale_flags & ALE_FLAG_JUMBO) != 0) { 1734 if (ifp->if_mtu < ETHERMTU) 1735 reg = sc->ale_max_frame_size; 1736 else if (ifp->if_mtu < 6 * 1024) 1737 reg = (sc->ale_max_frame_size * 2) / 3; 1738 else 1739 reg = sc->ale_max_frame_size / 2; 1740 CSR_WRITE_4(sc, ALE_TX_JUMBO_THRESH, 1741 roundup(reg, TX_JUMBO_THRESH_UNIT) >> 1742 TX_JUMBO_THRESH_UNIT_SHIFT); 1743 } 1744 1745 /* Configure TxQ. */ 1746 reg = (128 << (sc->ale_dma_rd_burst >> DMA_CFG_RD_BURST_SHIFT)) 1747 << TXQ_CFG_TX_FIFO_BURST_SHIFT; 1748 reg |= (TXQ_CFG_TPD_BURST_DEFAULT << TXQ_CFG_TPD_BURST_SHIFT) & 1749 TXQ_CFG_TPD_BURST_MASK; 1750 CSR_WRITE_4(sc, ALE_TXQ_CFG, reg | TXQ_CFG_ENHANCED_MODE | TXQ_CFG_ENB); 1751 1752 /* Configure Rx jumbo frame & flow control parameters. */ 1753 if ((sc->ale_flags & ALE_FLAG_JUMBO) != 0) { 1754 reg = roundup(sc->ale_max_frame_size, RX_JUMBO_THRESH_UNIT); 1755 CSR_WRITE_4(sc, ALE_RX_JUMBO_THRESH, 1756 (((reg >> RX_JUMBO_THRESH_UNIT_SHIFT) << 1757 RX_JUMBO_THRESH_MASK_SHIFT) & RX_JUMBO_THRESH_MASK) | 1758 ((RX_JUMBO_LKAH_DEFAULT << RX_JUMBO_LKAH_SHIFT) & 1759 RX_JUMBO_LKAH_MASK)); 1760 reg = CSR_READ_4(sc, ALE_SRAM_RX_FIFO_LEN); 1761 rxf_hi = (reg * 7) / 10; 1762 rxf_lo = (reg * 3)/ 10; 1763 CSR_WRITE_4(sc, ALE_RX_FIFO_PAUSE_THRESH, 1764 ((rxf_lo << RX_FIFO_PAUSE_THRESH_LO_SHIFT) & 1765 RX_FIFO_PAUSE_THRESH_LO_MASK) | 1766 ((rxf_hi << RX_FIFO_PAUSE_THRESH_HI_SHIFT) & 1767 RX_FIFO_PAUSE_THRESH_HI_MASK)); 1768 } 1769 1770 /* Disable RSS. */ 1771 CSR_WRITE_4(sc, ALE_RSS_IDT_TABLE0, 0); 1772 CSR_WRITE_4(sc, ALE_RSS_CPU, 0); 1773 1774 /* Configure RxQ. */ 1775 CSR_WRITE_4(sc, ALE_RXQ_CFG, 1776 RXQ_CFG_ALIGN_32 | RXQ_CFG_CUT_THROUGH_ENB | RXQ_CFG_ENB); 1777 1778 /* Configure DMA parameters. */ 1779 reg = 0; 1780 if ((sc->ale_flags & ALE_FLAG_TXCMB_BUG) == 0) 1781 reg |= DMA_CFG_TXCMB_ENB; 1782 CSR_WRITE_4(sc, ALE_DMA_CFG, 1783 DMA_CFG_OUT_ORDER | DMA_CFG_RD_REQ_PRI | DMA_CFG_RCB_64 | 1784 sc->ale_dma_rd_burst | reg | 1785 sc->ale_dma_wr_burst | DMA_CFG_RXCMB_ENB | 1786 ((DMA_CFG_RD_DELAY_CNT_DEFAULT << DMA_CFG_RD_DELAY_CNT_SHIFT) & 1787 DMA_CFG_RD_DELAY_CNT_MASK) | 1788 ((DMA_CFG_WR_DELAY_CNT_DEFAULT << DMA_CFG_WR_DELAY_CNT_SHIFT) & 1789 DMA_CFG_WR_DELAY_CNT_MASK)); 1790 1791 /* 1792 * Hardware can be configured to issue SMB interrupt based 1793 * on programmed interval. Since there is a callout that is 1794 * invoked for every hz in driver we use that instead of 1795 * relying on periodic SMB interrupt. 1796 */ 1797 CSR_WRITE_4(sc, ALE_SMB_STAT_TIMER, ALE_USECS(0)); 1798 1799 /* Clear MAC statistics. */ 1800 ale_stats_clear(sc); 1801 1802 /* 1803 * Configure Tx/Rx MACs. 1804 * - Auto-padding for short frames. 1805 * - Enable CRC generation. 1806 * Actual reconfiguration of MAC for resolved speed/duplex 1807 * is followed after detection of link establishment. 1808 * AR81xx always does checksum computation regardless of 1809 * MAC_CFG_RXCSUM_ENB bit. In fact, setting the bit will 1810 * cause Rx handling issue for fragmented IP datagrams due 1811 * to silicon bug. 1812 */ 1813 reg = MAC_CFG_TX_CRC_ENB | MAC_CFG_TX_AUTO_PAD | MAC_CFG_FULL_DUPLEX | 1814 ((MAC_CFG_PREAMBLE_DEFAULT << MAC_CFG_PREAMBLE_SHIFT) & 1815 MAC_CFG_PREAMBLE_MASK); 1816 if ((sc->ale_flags & ALE_FLAG_FASTETHER) != 0) 1817 reg |= MAC_CFG_SPEED_10_100; 1818 else 1819 reg |= MAC_CFG_SPEED_1000; 1820 CSR_WRITE_4(sc, ALE_MAC_CFG, reg); 1821 1822 /* Set up the receive filter. */ 1823 ale_rxfilter(sc); 1824 ale_rxvlan(sc); 1825 1826 /* Acknowledge all pending interrupts and clear it. */ 1827 CSR_WRITE_4(sc, ALE_INTR_MASK, ALE_INTRS); 1828 CSR_WRITE_4(sc, ALE_INTR_STATUS, 0xFFFFFFFF); 1829 CSR_WRITE_4(sc, ALE_INTR_STATUS, 0); 1830 1831 sc->ale_flags &= ~ALE_FLAG_LINK; 1832 1833 /* Switch to the current media. */ 1834 mii = &sc->sc_miibus; 1835 mii_mediachg(mii); 1836 1837 callout_schedule(&sc->sc_tick_ch, hz); 1838 1839 ifp->if_flags |= IFF_RUNNING; 1840 ifp->if_flags &= ~IFF_OACTIVE; 1841 1842 return 0; 1843 } 1844 1845 static void 1846 ale_stop(struct ifnet *ifp, int disable) 1847 { 1848 struct ale_softc *sc = ifp->if_softc; 1849 struct ale_txdesc *txd; 1850 uint32_t reg; 1851 int i; 1852 1853 callout_stop(&sc->sc_tick_ch); 1854 1855 /* 1856 * Mark the interface down and cancel the watchdog timer. 1857 */ 1858 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1859 ifp->if_timer = 0; 1860 1861 sc->ale_flags &= ~ALE_FLAG_LINK; 1862 1863 ale_stats_update(sc); 1864 1865 mii_down(&sc->sc_miibus); 1866 1867 /* Disable interrupts. */ 1868 CSR_WRITE_4(sc, ALE_INTR_MASK, 0); 1869 CSR_WRITE_4(sc, ALE_INTR_STATUS, 0xFFFFFFFF); 1870 1871 /* Disable queue processing and DMA. */ 1872 reg = CSR_READ_4(sc, ALE_TXQ_CFG); 1873 reg &= ~TXQ_CFG_ENB; 1874 CSR_WRITE_4(sc, ALE_TXQ_CFG, reg); 1875 reg = CSR_READ_4(sc, ALE_RXQ_CFG); 1876 reg &= ~RXQ_CFG_ENB; 1877 CSR_WRITE_4(sc, ALE_RXQ_CFG, reg); 1878 reg = CSR_READ_4(sc, ALE_DMA_CFG); 1879 reg &= ~(DMA_CFG_TXCMB_ENB | DMA_CFG_RXCMB_ENB); 1880 CSR_WRITE_4(sc, ALE_DMA_CFG, reg); 1881 DELAY(1000); 1882 1883 /* Stop Rx/Tx MACs. */ 1884 ale_stop_mac(sc); 1885 1886 /* Disable interrupts again? XXX */ 1887 CSR_WRITE_4(sc, ALE_INTR_STATUS, 0xFFFFFFFF); 1888 1889 /* 1890 * Free TX mbufs still in the queues. 1891 */ 1892 for (i = 0; i < ALE_TX_RING_CNT; i++) { 1893 txd = &sc->ale_cdata.ale_txdesc[i]; 1894 if (txd->tx_m != NULL) { 1895 bus_dmamap_unload(sc->sc_dmat, txd->tx_dmamap); 1896 m_freem(txd->tx_m); 1897 txd->tx_m = NULL; 1898 } 1899 } 1900 } 1901 1902 static void 1903 ale_stop_mac(struct ale_softc *sc) 1904 { 1905 uint32_t reg; 1906 int i; 1907 1908 reg = CSR_READ_4(sc, ALE_MAC_CFG); 1909 if ((reg & (MAC_CFG_TX_ENB | MAC_CFG_RX_ENB)) != 0) { 1910 reg &= ~MAC_CFG_TX_ENB | MAC_CFG_RX_ENB; 1911 CSR_WRITE_4(sc, ALE_MAC_CFG, reg); 1912 } 1913 1914 for (i = ALE_TIMEOUT; i > 0; i--) { 1915 reg = CSR_READ_4(sc, ALE_IDLE_STATUS); 1916 if (reg == 0) 1917 break; 1918 DELAY(10); 1919 } 1920 if (i == 0) 1921 printf("%s: could not disable Tx/Rx MAC(0x%08x)!\n", 1922 device_xname(sc->sc_dev), reg); 1923 } 1924 1925 static void 1926 ale_init_tx_ring(struct ale_softc *sc) 1927 { 1928 struct ale_txdesc *txd; 1929 int i; 1930 1931 sc->ale_cdata.ale_tx_prod = 0; 1932 sc->ale_cdata.ale_tx_cons = 0; 1933 sc->ale_cdata.ale_tx_cnt = 0; 1934 1935 memset(sc->ale_cdata.ale_tx_ring, 0, ALE_TX_RING_SZ); 1936 memset(sc->ale_cdata.ale_tx_cmb, 0, ALE_TX_CMB_SZ); 1937 for (i = 0; i < ALE_TX_RING_CNT; i++) { 1938 txd = &sc->ale_cdata.ale_txdesc[i]; 1939 txd->tx_m = NULL; 1940 } 1941 *sc->ale_cdata.ale_tx_cmb = 0; 1942 bus_dmamap_sync(sc->sc_dmat, sc->ale_cdata.ale_tx_cmb_map, 0, 1943 sc->ale_cdata.ale_tx_cmb_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 1944 bus_dmamap_sync(sc->sc_dmat, sc->ale_cdata.ale_tx_ring_map, 0, 1945 sc->ale_cdata.ale_tx_ring_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 1946 } 1947 1948 static void 1949 ale_init_rx_pages(struct ale_softc *sc) 1950 { 1951 struct ale_rx_page *rx_page; 1952 int i; 1953 1954 sc->ale_cdata.ale_rx_seqno = 0; 1955 sc->ale_cdata.ale_rx_curp = 0; 1956 1957 for (i = 0; i < ALE_RX_PAGES; i++) { 1958 rx_page = &sc->ale_cdata.ale_rx_page[i]; 1959 memset(rx_page->page_addr, 0, sc->ale_pagesize); 1960 memset(rx_page->cmb_addr, 0, ALE_RX_CMB_SZ); 1961 rx_page->cons = 0; 1962 *rx_page->cmb_addr = 0; 1963 bus_dmamap_sync(sc->sc_dmat, rx_page->page_map, 0, 1964 rx_page->page_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 1965 bus_dmamap_sync(sc->sc_dmat, rx_page->cmb_map, 0, 1966 rx_page->cmb_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 1967 } 1968 } 1969 1970 static void 1971 ale_rxvlan(struct ale_softc *sc) 1972 { 1973 struct ifnet *ifp = &sc->sc_ec.ec_if; 1974 uint32_t reg; 1975 1976 reg = CSR_READ_4(sc, ALE_MAC_CFG); 1977 reg &= ~MAC_CFG_VLAN_TAG_STRIP; 1978 if (ifp->if_capabilities & ETHERCAP_VLAN_HWTAGGING) 1979 reg |= MAC_CFG_VLAN_TAG_STRIP; 1980 CSR_WRITE_4(sc, ALE_MAC_CFG, reg); 1981 } 1982 1983 static void 1984 ale_rxfilter(struct ale_softc *sc) 1985 { 1986 struct ethercom *ec = &sc->sc_ec; 1987 struct ifnet *ifp = &ec->ec_if; 1988 struct ether_multi *enm; 1989 struct ether_multistep step; 1990 uint32_t crc; 1991 uint32_t mchash[2]; 1992 uint32_t rxcfg; 1993 1994 rxcfg = CSR_READ_4(sc, ALE_MAC_CFG); 1995 rxcfg &= ~(MAC_CFG_ALLMULTI | MAC_CFG_BCAST | MAC_CFG_PROMISC); 1996 1997 /* 1998 * Always accept broadcast frames. 1999 */ 2000 rxcfg |= MAC_CFG_BCAST; 2001 2002 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC || 2003 ec->ec_multicnt > 0) { 2004 allmulti: 2005 if (ifp->if_flags & IFF_PROMISC) 2006 rxcfg |= MAC_CFG_PROMISC; 2007 else 2008 rxcfg |= MAC_CFG_ALLMULTI; 2009 mchash[0] = mchash[1] = 0xFFFFFFFF; 2010 } else { 2011 /* Program new filter. */ 2012 memset(mchash, 0, sizeof(mchash)); 2013 2014 ETHER_FIRST_MULTI(step, ec, enm); 2015 while (enm != NULL) { 2016 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 2017 ETHER_ADDR_LEN)) { 2018 ifp->if_flags |= IFF_ALLMULTI; 2019 goto allmulti; 2020 } 2021 crc = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN); 2022 2023 mchash[crc >> 31] |= 1 << ((crc >> 26) & 0x1f); 2024 ETHER_NEXT_MULTI(step, enm); 2025 } 2026 } 2027 2028 CSR_WRITE_4(sc, ALE_MAR0, mchash[0]); 2029 CSR_WRITE_4(sc, ALE_MAR1, mchash[1]); 2030 CSR_WRITE_4(sc, ALE_MAC_CFG, rxcfg); 2031 } 2032
Indexes created Tue Sep 30 11:09:46 GMT 2025