if_ale.c revision 1.11
1 /* $NetBSD: if_ale.c,v 1.11 2010/04/05 07:20:25 joerg Exp $ */ 2 3 /*- 4 * Copyright (c) 2008, Pyun YongHyeon <yongari (at) FreeBSD.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice unmodified, this list of conditions, and the following 12 * disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * 29 * $FreeBSD: src/sys/dev/ale/if_ale.c,v 1.3 2008/12/03 09:01:12 yongari Exp $ 30 */ 31 32 /* Driver for Atheros AR8121/AR8113/AR8114 PCIe Ethernet. */ 33 34 #include <sys/cdefs.h> 35 __KERNEL_RCSID(0, "$NetBSD: if_ale.c,v 1.11 2010/04/05 07:20:25 joerg Exp $"); 36 37 #include "vlan.h" 38 39 #include <sys/param.h> 40 #include <sys/proc.h> 41 #include <sys/endian.h> 42 #include <sys/systm.h> 43 #include <sys/types.h> 44 #include <sys/sockio.h> 45 #include <sys/mbuf.h> 46 #include <sys/queue.h> 47 #include <sys/kernel.h> 48 #include <sys/device.h> 49 #include <sys/callout.h> 50 #include <sys/socket.h> 51 52 #include <sys/bus.h> 53 54 #include <net/if.h> 55 #include <net/if_dl.h> 56 #include <net/if_llc.h> 57 #include <net/if_media.h> 58 #include <net/if_ether.h> 59 60 #ifdef INET 61 #include <netinet/in.h> 62 #include <netinet/in_systm.h> 63 #include <netinet/in_var.h> 64 #include <netinet/ip.h> 65 #endif 66 67 #include <net/if_types.h> 68 #include <net/if_vlanvar.h> 69 70 #include <net/bpf.h> 71 72 #include <sys/rnd.h> 73 74 #include <dev/mii/mii.h> 75 #include <dev/mii/miivar.h> 76 77 #include <dev/pci/pcireg.h> 78 #include <dev/pci/pcivar.h> 79 #include <dev/pci/pcidevs.h> 80 81 #include <dev/pci/if_alereg.h> 82 83 static int ale_match(device_t, cfdata_t, void *); 84 static void ale_attach(device_t, device_t, void *); 85 static int ale_detach(device_t, int); 86 87 static int ale_miibus_readreg(device_t, int, int); 88 static void ale_miibus_writereg(device_t, int, int, int); 89 static void ale_miibus_statchg(device_t); 90 91 static int ale_init(struct ifnet *); 92 static void ale_start(struct ifnet *); 93 static int ale_ioctl(struct ifnet *, u_long, void *); 94 static void ale_watchdog(struct ifnet *); 95 static int ale_mediachange(struct ifnet *); 96 static void ale_mediastatus(struct ifnet *, struct ifmediareq *); 97 98 static int ale_intr(void *); 99 static int ale_rxeof(struct ale_softc *sc); 100 static void ale_rx_update_page(struct ale_softc *, struct ale_rx_page **, 101 uint32_t, uint32_t *); 102 static void ale_rxcsum(struct ale_softc *, struct mbuf *, uint32_t); 103 static void ale_txeof(struct ale_softc *); 104 105 static int ale_dma_alloc(struct ale_softc *); 106 static void ale_dma_free(struct ale_softc *); 107 static int ale_encap(struct ale_softc *, struct mbuf **); 108 static void ale_init_rx_pages(struct ale_softc *); 109 static void ale_init_tx_ring(struct ale_softc *); 110 111 static void ale_stop(struct ifnet *, int); 112 static void ale_tick(void *); 113 static void ale_get_macaddr(struct ale_softc *); 114 static void ale_mac_config(struct ale_softc *); 115 static void ale_phy_reset(struct ale_softc *); 116 static void ale_reset(struct ale_softc *); 117 static void ale_rxfilter(struct ale_softc *); 118 static void ale_rxvlan(struct ale_softc *); 119 static void ale_stats_clear(struct ale_softc *); 120 static void ale_stats_update(struct ale_softc *); 121 static void ale_stop_mac(struct ale_softc *); 122 123 CFATTACH_DECL_NEW(ale, sizeof(struct ale_softc), 124 ale_match, ale_attach, ale_detach, NULL); 125 126 int aledebug = 0; 127 #define DPRINTF(x) do { if (aledebug) printf x; } while (0) 128 129 #define ETHER_ALIGN 2 130 #define ALE_CSUM_FEATURES (M_CSUM_TCPv4 | M_CSUM_UDPv4) 131 132 static int 133 ale_miibus_readreg(device_t dev, int phy, int reg) 134 { 135 struct ale_softc *sc = device_private(dev); 136 uint32_t v; 137 int i; 138 139 if (phy != sc->ale_phyaddr) 140 return 0; 141 142 if (sc->ale_flags & ALE_FLAG_FASTETHER) { 143 switch (reg) { 144 case MII_100T2CR: 145 case MII_100T2SR: 146 case MII_EXTSR: 147 return 0; 148 default: 149 break; 150 } 151 } 152 153 CSR_WRITE_4(sc, ALE_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ | 154 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); 155 for (i = ALE_PHY_TIMEOUT; i > 0; i--) { 156 DELAY(5); 157 v = CSR_READ_4(sc, ALE_MDIO); 158 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) 159 break; 160 } 161 162 if (i == 0) { 163 printf("%s: phy read timeout: phy %d, reg %d\n", 164 device_xname(sc->sc_dev), phy, reg); 165 return 0; 166 } 167 168 return (v & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT; 169 } 170 171 static void 172 ale_miibus_writereg(device_t dev, int phy, int reg, int val) 173 { 174 struct ale_softc *sc = device_private(dev); 175 uint32_t v; 176 int i; 177 178 if (phy != sc->ale_phyaddr) 179 return; 180 181 if (sc->ale_flags & ALE_FLAG_FASTETHER) { 182 switch (reg) { 183 case MII_100T2CR: 184 case MII_100T2SR: 185 case MII_EXTSR: 186 return; 187 default: 188 break; 189 } 190 } 191 192 CSR_WRITE_4(sc, ALE_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE | 193 (val & MDIO_DATA_MASK) << MDIO_DATA_SHIFT | 194 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); 195 for (i = ALE_PHY_TIMEOUT; i > 0; i--) { 196 DELAY(5); 197 v = CSR_READ_4(sc, ALE_MDIO); 198 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) 199 break; 200 } 201 202 if (i == 0) 203 printf("%s: phy write timeout: phy %d, reg %d\n", 204 device_xname(sc->sc_dev), phy, reg); 205 } 206 207 static void 208 ale_miibus_statchg(device_t dev) 209 { 210 struct ale_softc *sc = device_private(dev); 211 struct ifnet *ifp = &sc->sc_ec.ec_if; 212 struct mii_data *mii; 213 uint32_t reg; 214 215 if ((ifp->if_flags & IFF_RUNNING) == 0) 216 return; 217 218 mii = &sc->sc_miibus; 219 220 sc->ale_flags &= ~ALE_FLAG_LINK; 221 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 222 (IFM_ACTIVE | IFM_AVALID)) { 223 switch (IFM_SUBTYPE(mii->mii_media_active)) { 224 case IFM_10_T: 225 case IFM_100_TX: 226 sc->ale_flags |= ALE_FLAG_LINK; 227 break; 228 229 case IFM_1000_T: 230 if ((sc->ale_flags & ALE_FLAG_FASTETHER) == 0) 231 sc->ale_flags |= ALE_FLAG_LINK; 232 break; 233 234 default: 235 break; 236 } 237 } 238 239 /* Stop Rx/Tx MACs. */ 240 ale_stop_mac(sc); 241 242 /* Program MACs with resolved speed/duplex/flow-control. */ 243 if ((sc->ale_flags & ALE_FLAG_LINK) != 0) { 244 ale_mac_config(sc); 245 /* Reenable Tx/Rx MACs. */ 246 reg = CSR_READ_4(sc, ALE_MAC_CFG); 247 reg |= MAC_CFG_TX_ENB | MAC_CFG_RX_ENB; 248 CSR_WRITE_4(sc, ALE_MAC_CFG, reg); 249 } 250 } 251 252 void 253 ale_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 254 { 255 struct ale_softc *sc = ifp->if_softc; 256 struct mii_data *mii = &sc->sc_miibus; 257 258 mii_pollstat(mii); 259 ifmr->ifm_status = mii->mii_media_status; 260 ifmr->ifm_active = mii->mii_media_active; 261 } 262 263 int 264 ale_mediachange(struct ifnet *ifp) 265 { 266 struct ale_softc *sc = ifp->if_softc; 267 struct mii_data *mii = &sc->sc_miibus; 268 int error; 269 270 if (mii->mii_instance != 0) { 271 struct mii_softc *miisc; 272 273 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 274 mii_phy_reset(miisc); 275 } 276 error = mii_mediachg(mii); 277 278 return error; 279 } 280 281 int 282 ale_match(device_t dev, cfdata_t match, void *aux) 283 { 284 struct pci_attach_args *pa = aux; 285 286 return (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_ATTANSIC && 287 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_ATTANSIC_ETHERNET_L1E); 288 } 289 290 void 291 ale_get_macaddr(struct ale_softc *sc) 292 { 293 uint32_t ea[2], reg; 294 int i, vpdc; 295 296 reg = CSR_READ_4(sc, ALE_SPI_CTRL); 297 if ((reg & SPI_VPD_ENB) != 0) { 298 reg &= ~SPI_VPD_ENB; 299 CSR_WRITE_4(sc, ALE_SPI_CTRL, reg); 300 } 301 302 if (pci_get_capability(sc->sc_pct, sc->sc_pcitag, PCI_CAP_VPD, 303 &vpdc, NULL)) { 304 /* 305 * PCI VPD capability found, let TWSI reload EEPROM. 306 * This will set ethernet address of controller. 307 */ 308 CSR_WRITE_4(sc, ALE_TWSI_CTRL, CSR_READ_4(sc, ALE_TWSI_CTRL) | 309 TWSI_CTRL_SW_LD_START); 310 for (i = 100; i > 0; i--) { 311 DELAY(1000); 312 reg = CSR_READ_4(sc, ALE_TWSI_CTRL); 313 if ((reg & TWSI_CTRL_SW_LD_START) == 0) 314 break; 315 } 316 if (i == 0) 317 printf("%s: reloading EEPROM timeout!\n", 318 device_xname(sc->sc_dev)); 319 } else { 320 if (aledebug) 321 printf("%s: PCI VPD capability not found!\n", 322 device_xname(sc->sc_dev)); 323 } 324 325 ea[0] = CSR_READ_4(sc, ALE_PAR0); 326 ea[1] = CSR_READ_4(sc, ALE_PAR1); 327 sc->ale_eaddr[0] = (ea[1] >> 8) & 0xFF; 328 sc->ale_eaddr[1] = (ea[1] >> 0) & 0xFF; 329 sc->ale_eaddr[2] = (ea[0] >> 24) & 0xFF; 330 sc->ale_eaddr[3] = (ea[0] >> 16) & 0xFF; 331 sc->ale_eaddr[4] = (ea[0] >> 8) & 0xFF; 332 sc->ale_eaddr[5] = (ea[0] >> 0) & 0xFF; 333 } 334 335 void 336 ale_phy_reset(struct ale_softc *sc) 337 { 338 /* Reset magic from Linux. */ 339 CSR_WRITE_2(sc, ALE_GPHY_CTRL, 340 GPHY_CTRL_HIB_EN | GPHY_CTRL_HIB_PULSE | GPHY_CTRL_SEL_ANA_RESET | 341 GPHY_CTRL_PHY_PLL_ON); 342 DELAY(1000); 343 CSR_WRITE_2(sc, ALE_GPHY_CTRL, 344 GPHY_CTRL_EXT_RESET | GPHY_CTRL_HIB_EN | GPHY_CTRL_HIB_PULSE | 345 GPHY_CTRL_SEL_ANA_RESET | GPHY_CTRL_PHY_PLL_ON); 346 DELAY(1000); 347 348 #define ATPHY_DBG_ADDR 0x1D 349 #define ATPHY_DBG_DATA 0x1E 350 351 /* Enable hibernation mode. */ 352 ale_miibus_writereg(sc->sc_dev, sc->ale_phyaddr, 353 ATPHY_DBG_ADDR, 0x0B); 354 ale_miibus_writereg(sc->sc_dev, sc->ale_phyaddr, 355 ATPHY_DBG_DATA, 0xBC00); 356 /* Set Class A/B for all modes. */ 357 ale_miibus_writereg(sc->sc_dev, sc->ale_phyaddr, 358 ATPHY_DBG_ADDR, 0x00); 359 ale_miibus_writereg(sc->sc_dev, sc->ale_phyaddr, 360 ATPHY_DBG_DATA, 0x02EF); 361 /* Enable 10BT power saving. */ 362 ale_miibus_writereg(sc->sc_dev, sc->ale_phyaddr, 363 ATPHY_DBG_ADDR, 0x12); 364 ale_miibus_writereg(sc->sc_dev, sc->ale_phyaddr, 365 ATPHY_DBG_DATA, 0x4C04); 366 /* Adjust 1000T power. */ 367 ale_miibus_writereg(sc->sc_dev, sc->ale_phyaddr, 368 ATPHY_DBG_ADDR, 0x04); 369 ale_miibus_writereg(sc->sc_dev, sc->ale_phyaddr, 370 ATPHY_DBG_ADDR, 0x8BBB); 371 /* 10BT center tap voltage. */ 372 ale_miibus_writereg(sc->sc_dev, sc->ale_phyaddr, 373 ATPHY_DBG_ADDR, 0x05); 374 ale_miibus_writereg(sc->sc_dev, sc->ale_phyaddr, 375 ATPHY_DBG_ADDR, 0x2C46); 376 377 #undef ATPHY_DBG_ADDR 378 #undef ATPHY_DBG_DATA 379 DELAY(1000); 380 } 381 382 void 383 ale_attach(device_t parent, device_t self, void *aux) 384 { 385 struct ale_softc *sc = device_private(self); 386 struct pci_attach_args *pa = aux; 387 pci_chipset_tag_t pc = pa->pa_pc; 388 pci_intr_handle_t ih; 389 const char *intrstr; 390 struct ifnet *ifp; 391 pcireg_t memtype; 392 int mii_flags, error = 0; 393 uint32_t rxf_len, txf_len; 394 const char *chipname; 395 396 aprint_naive("\n"); 397 aprint_normal(": Attansic/Atheros L1E Ethernet\n"); 398 399 sc->sc_dev = self; 400 sc->sc_dmat = pa->pa_dmat; 401 sc->sc_pct = pa->pa_pc; 402 sc->sc_pcitag = pa->pa_tag; 403 404 /* 405 * Allocate IO memory 406 */ 407 memtype = pci_mapreg_type(sc->sc_pct, sc->sc_pcitag, ALE_PCIR_BAR); 408 switch (memtype) { 409 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 410 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT_1M: 411 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 412 break; 413 default: 414 aprint_error_dev(self, "invalid base address register\n"); 415 break; 416 } 417 418 if (pci_mapreg_map(pa, ALE_PCIR_BAR, memtype, 0, &sc->sc_mem_bt, 419 &sc->sc_mem_bh, NULL, &sc->sc_mem_size)) { 420 aprint_error_dev(self, "could not map mem space\n"); 421 return; 422 } 423 424 if (pci_intr_map(pa, &ih) != 0) { 425 aprint_error_dev(self, "could not map interrupt\n"); 426 goto fail; 427 } 428 429 /* 430 * Allocate IRQ 431 */ 432 intrstr = pci_intr_string(sc->sc_pct, ih); 433 sc->sc_irq_handle = pci_intr_establish(pc, ih, IPL_NET, ale_intr, sc); 434 if (sc->sc_irq_handle == NULL) { 435 aprint_error_dev(self, "could not establish interrupt"); 436 if (intrstr != NULL) 437 aprint_error(" at %s", intrstr); 438 aprint_error("\n"); 439 goto fail; 440 } 441 442 /* Set PHY address. */ 443 sc->ale_phyaddr = ALE_PHY_ADDR; 444 445 /* Reset PHY. */ 446 ale_phy_reset(sc); 447 448 /* Reset the ethernet controller. */ 449 ale_reset(sc); 450 451 /* Get PCI and chip id/revision. */ 452 sc->ale_rev = PCI_REVISION(pa->pa_class); 453 if (sc->ale_rev >= 0xF0) { 454 /* L2E Rev. B. AR8114 */ 455 sc->ale_flags |= ALE_FLAG_FASTETHER; 456 chipname = "AR8114 (L2E RevB)"; 457 } else { 458 if ((CSR_READ_4(sc, ALE_PHY_STATUS) & PHY_STATUS_100M) != 0) { 459 /* L1E AR8121 */ 460 sc->ale_flags |= ALE_FLAG_JUMBO; 461 chipname = "AR8121 (L1E)"; 462 } else { 463 /* L2E Rev. A. AR8113 */ 464 sc->ale_flags |= ALE_FLAG_FASTETHER; 465 chipname = "AR8113 (L2E RevA)"; 466 } 467 } 468 aprint_normal_dev(self, "%s, %s\n", chipname, intrstr); 469 470 /* 471 * All known controllers seems to require 4 bytes alignment 472 * of Tx buffers to make Tx checksum offload with custom 473 * checksum generation method work. 474 */ 475 sc->ale_flags |= ALE_FLAG_TXCSUM_BUG; 476 477 /* 478 * All known controllers seems to have issues on Rx checksum 479 * offload for fragmented IP datagrams. 480 */ 481 sc->ale_flags |= ALE_FLAG_RXCSUM_BUG; 482 483 /* 484 * Don't use Tx CMB. It is known to cause RRS update failure 485 * under certain circumstances. Typical phenomenon of the 486 * issue would be unexpected sequence number encountered in 487 * Rx handler. 488 */ 489 sc->ale_flags |= ALE_FLAG_TXCMB_BUG; 490 sc->ale_chip_rev = CSR_READ_4(sc, ALE_MASTER_CFG) >> 491 MASTER_CHIP_REV_SHIFT; 492 aprint_debug_dev(self, "PCI device revision : 0x%04x\n", sc->ale_rev); 493 aprint_debug_dev(self, "Chip id/revision : 0x%04x\n", sc->ale_chip_rev); 494 495 /* 496 * Uninitialized hardware returns an invalid chip id/revision 497 * as well as 0xFFFFFFFF for Tx/Rx fifo length. 498 */ 499 txf_len = CSR_READ_4(sc, ALE_SRAM_TX_FIFO_LEN); 500 rxf_len = CSR_READ_4(sc, ALE_SRAM_RX_FIFO_LEN); 501 if (sc->ale_chip_rev == 0xFFFF || txf_len == 0xFFFFFFFF || 502 rxf_len == 0xFFFFFFF) { 503 aprint_error_dev(self, "chip revision : 0x%04x, %u Tx FIFO " 504 "%u Rx FIFO -- not initialized?\n", 505 sc->ale_chip_rev, txf_len, rxf_len); 506 goto fail; 507 } 508 509 if (aledebug) { 510 printf("%s: %u Tx FIFO, %u Rx FIFO\n", device_xname(sc->sc_dev), 511 txf_len, rxf_len); 512 } 513 514 /* Set max allowable DMA size. */ 515 sc->ale_dma_rd_burst = DMA_CFG_RD_BURST_128; 516 sc->ale_dma_wr_burst = DMA_CFG_WR_BURST_128; 517 518 callout_init(&sc->sc_tick_ch, 0); 519 callout_setfunc(&sc->sc_tick_ch, ale_tick, sc); 520 521 error = ale_dma_alloc(sc); 522 if (error) 523 goto fail; 524 525 /* Load station address. */ 526 ale_get_macaddr(sc); 527 528 aprint_normal_dev(self, "Ethernet address %s\n", 529 ether_sprintf(sc->ale_eaddr)); 530 531 ifp = &sc->sc_ec.ec_if; 532 ifp->if_softc = sc; 533 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 534 ifp->if_init = ale_init; 535 ifp->if_ioctl = ale_ioctl; 536 ifp->if_start = ale_start; 537 ifp->if_stop = ale_stop; 538 ifp->if_watchdog = ale_watchdog; 539 IFQ_SET_MAXLEN(&ifp->if_snd, ALE_TX_RING_CNT - 1); 540 IFQ_SET_READY(&ifp->if_snd); 541 strlcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 542 543 sc->sc_ec.ec_capabilities = ETHERCAP_VLAN_MTU; 544 545 #ifdef ALE_CHECKSUM 546 ifp->if_capabilities |= IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 547 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 548 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_TCPv4_Rx; 549 #endif 550 551 #if NVLAN > 0 552 sc->sc_ec.ec_capabilities |= ETHERCAP_VLAN_HWTAGGING; 553 #endif 554 555 /* Set up MII bus. */ 556 sc->sc_miibus.mii_ifp = ifp; 557 sc->sc_miibus.mii_readreg = ale_miibus_readreg; 558 sc->sc_miibus.mii_writereg = ale_miibus_writereg; 559 sc->sc_miibus.mii_statchg = ale_miibus_statchg; 560 561 sc->sc_ec.ec_mii = &sc->sc_miibus; 562 ifmedia_init(&sc->sc_miibus.mii_media, 0, ale_mediachange, 563 ale_mediastatus); 564 mii_flags = 0; 565 if ((sc->ale_flags & ALE_FLAG_JUMBO) != 0) 566 mii_flags |= MIIF_DOPAUSE; 567 mii_attach(self, &sc->sc_miibus, 0xffffffff, MII_PHY_ANY, 568 MII_OFFSET_ANY, mii_flags); 569 570 if (LIST_FIRST(&sc->sc_miibus.mii_phys) == NULL) { 571 aprint_error_dev(self, "no PHY found!\n"); 572 ifmedia_add(&sc->sc_miibus.mii_media, IFM_ETHER | IFM_MANUAL, 573 0, NULL); 574 ifmedia_set(&sc->sc_miibus.mii_media, IFM_ETHER | IFM_MANUAL); 575 } else 576 ifmedia_set(&sc->sc_miibus.mii_media, IFM_ETHER | IFM_AUTO); 577 578 if_attach(ifp); 579 ether_ifattach(ifp, sc->ale_eaddr); 580 581 if (pmf_device_register(self, NULL, NULL)) 582 pmf_class_network_register(self, ifp); 583 else 584 aprint_error_dev(self, "couldn't establish power handler\n"); 585 586 return; 587 fail: 588 ale_dma_free(sc); 589 if (sc->sc_irq_handle != NULL) { 590 pci_intr_disestablish(pc, sc->sc_irq_handle); 591 sc->sc_irq_handle = NULL; 592 } 593 if (sc->sc_mem_size) { 594 bus_space_unmap(sc->sc_mem_bt, sc->sc_mem_bh, sc->sc_mem_size); 595 sc->sc_mem_size = 0; 596 } 597 } 598 599 static int 600 ale_detach(device_t self, int flags) 601 { 602 struct ale_softc *sc = device_private(self); 603 struct ifnet *ifp = &sc->sc_ec.ec_if; 604 int s; 605 606 pmf_device_deregister(self); 607 s = splnet(); 608 ale_stop(ifp, 0); 609 splx(s); 610 611 mii_detach(&sc->sc_miibus, MII_PHY_ANY, MII_OFFSET_ANY); 612 613 /* Delete all remaining media. */ 614 ifmedia_delete_instance(&sc->sc_miibus.mii_media, IFM_INST_ANY); 615 616 ether_ifdetach(ifp); 617 if_detach(ifp); 618 ale_dma_free(sc); 619 620 if (sc->sc_irq_handle != NULL) { 621 pci_intr_disestablish(sc->sc_pct, sc->sc_irq_handle); 622 sc->sc_irq_handle = NULL; 623 } 624 if (sc->sc_mem_size) { 625 bus_space_unmap(sc->sc_mem_bt, sc->sc_mem_bh, sc->sc_mem_size); 626 sc->sc_mem_size = 0; 627 } 628 629 return 0; 630 } 631 632 633 static int 634 ale_dma_alloc(struct ale_softc *sc) 635 { 636 struct ale_txdesc *txd; 637 int nsegs, error, guard_size, i; 638 639 if ((sc->ale_flags & ALE_FLAG_JUMBO) != 0) 640 guard_size = ALE_JUMBO_FRAMELEN; 641 else 642 guard_size = ALE_MAX_FRAMELEN; 643 sc->ale_pagesize = roundup(guard_size + ALE_RX_PAGE_SZ, 644 ALE_RX_PAGE_ALIGN); 645 646 /* 647 * Create DMA stuffs for TX ring 648 */ 649 error = bus_dmamap_create(sc->sc_dmat, ALE_TX_RING_SZ, 1, 650 ALE_TX_RING_SZ, 0, BUS_DMA_NOWAIT, &sc->ale_cdata.ale_tx_ring_map); 651 if (error) { 652 sc->ale_cdata.ale_tx_ring_map = NULL; 653 return ENOBUFS; 654 } 655 656 /* Allocate DMA'able memory for TX ring */ 657 error = bus_dmamem_alloc(sc->sc_dmat, ALE_TX_RING_SZ, 658 0, 0, &sc->ale_cdata.ale_tx_ring_seg, 1, 659 &nsegs, BUS_DMA_WAITOK); 660 if (error) { 661 printf("%s: could not allocate DMA'able memory for Tx ring, " 662 "error = %i\n", device_xname(sc->sc_dev), error); 663 return error; 664 } 665 666 error = bus_dmamem_map(sc->sc_dmat, &sc->ale_cdata.ale_tx_ring_seg, 667 nsegs, ALE_TX_RING_SZ, (void **)&sc->ale_cdata.ale_tx_ring, 668 BUS_DMA_NOWAIT); 669 if (error) 670 return ENOBUFS; 671 672 memset(sc->ale_cdata.ale_tx_ring, 0, ALE_TX_RING_SZ); 673 674 /* Load the DMA map for Tx ring. */ 675 error = bus_dmamap_load(sc->sc_dmat, sc->ale_cdata.ale_tx_ring_map, 676 sc->ale_cdata.ale_tx_ring, ALE_TX_RING_SZ, NULL, BUS_DMA_WAITOK); 677 if (error) { 678 printf("%s: could not load DMA'able memory for Tx ring.\n", 679 device_xname(sc->sc_dev)); 680 bus_dmamem_free(sc->sc_dmat, 681 &sc->ale_cdata.ale_tx_ring_seg, 1); 682 return error; 683 } 684 sc->ale_cdata.ale_tx_ring_paddr = 685 sc->ale_cdata.ale_tx_ring_map->dm_segs[0].ds_addr; 686 687 for (i = 0; i < ALE_RX_PAGES; i++) { 688 /* 689 * Create DMA stuffs for RX pages 690 */ 691 error = bus_dmamap_create(sc->sc_dmat, sc->ale_pagesize, 1, 692 sc->ale_pagesize, 0, BUS_DMA_NOWAIT, 693 &sc->ale_cdata.ale_rx_page[i].page_map); 694 if (error) { 695 sc->ale_cdata.ale_rx_page[i].page_map = NULL; 696 return ENOBUFS; 697 } 698 699 /* Allocate DMA'able memory for RX pages */ 700 error = bus_dmamem_alloc(sc->sc_dmat, sc->ale_pagesize, 701 ETHER_ALIGN, 0, &sc->ale_cdata.ale_rx_page[i].page_seg, 702 1, &nsegs, BUS_DMA_WAITOK); 703 if (error) { 704 printf("%s: could not allocate DMA'able memory for " 705 "Rx ring.\n", device_xname(sc->sc_dev)); 706 return error; 707 } 708 error = bus_dmamem_map(sc->sc_dmat, 709 &sc->ale_cdata.ale_rx_page[i].page_seg, nsegs, 710 sc->ale_pagesize, 711 (void **)&sc->ale_cdata.ale_rx_page[i].page_addr, 712 BUS_DMA_NOWAIT); 713 if (error) 714 return ENOBUFS; 715 716 memset(sc->ale_cdata.ale_rx_page[i].page_addr, 0, 717 sc->ale_pagesize); 718 719 /* Load the DMA map for Rx pages. */ 720 error = bus_dmamap_load(sc->sc_dmat, 721 sc->ale_cdata.ale_rx_page[i].page_map, 722 sc->ale_cdata.ale_rx_page[i].page_addr, 723 sc->ale_pagesize, NULL, BUS_DMA_WAITOK); 724 if (error) { 725 printf("%s: could not load DMA'able memory for " 726 "Rx pages.\n", device_xname(sc->sc_dev)); 727 bus_dmamem_free(sc->sc_dmat, 728 &sc->ale_cdata.ale_rx_page[i].page_seg, 1); 729 return error; 730 } 731 sc->ale_cdata.ale_rx_page[i].page_paddr = 732 sc->ale_cdata.ale_rx_page[i].page_map->dm_segs[0].ds_addr; 733 } 734 735 /* 736 * Create DMA stuffs for Tx CMB. 737 */ 738 error = bus_dmamap_create(sc->sc_dmat, ALE_TX_CMB_SZ, 1, 739 ALE_TX_CMB_SZ, 0, BUS_DMA_NOWAIT, &sc->ale_cdata.ale_tx_cmb_map); 740 if (error) { 741 sc->ale_cdata.ale_tx_cmb_map = NULL; 742 return ENOBUFS; 743 } 744 745 /* Allocate DMA'able memory for Tx CMB. */ 746 error = bus_dmamem_alloc(sc->sc_dmat, ALE_TX_CMB_SZ, ETHER_ALIGN, 0, 747 &sc->ale_cdata.ale_tx_cmb_seg, 1, &nsegs, BUS_DMA_WAITOK); 748 749 if (error) { 750 printf("%s: could not allocate DMA'able memory for Tx CMB.\n", 751 device_xname(sc->sc_dev)); 752 return error; 753 } 754 755 error = bus_dmamem_map(sc->sc_dmat, &sc->ale_cdata.ale_tx_cmb_seg, 756 nsegs, ALE_TX_CMB_SZ, (void **)&sc->ale_cdata.ale_tx_cmb, 757 BUS_DMA_NOWAIT); 758 if (error) 759 return ENOBUFS; 760 761 memset(sc->ale_cdata.ale_tx_cmb, 0, ALE_TX_CMB_SZ); 762 763 /* Load the DMA map for Tx CMB. */ 764 error = bus_dmamap_load(sc->sc_dmat, sc->ale_cdata.ale_tx_cmb_map, 765 sc->ale_cdata.ale_tx_cmb, ALE_TX_CMB_SZ, NULL, BUS_DMA_WAITOK); 766 if (error) { 767 printf("%s: could not load DMA'able memory for Tx CMB.\n", 768 device_xname(sc->sc_dev)); 769 bus_dmamem_free(sc->sc_dmat, 770 &sc->ale_cdata.ale_tx_cmb_seg, 1); 771 return error; 772 } 773 774 sc->ale_cdata.ale_tx_cmb_paddr = 775 sc->ale_cdata.ale_tx_cmb_map->dm_segs[0].ds_addr; 776 777 for (i = 0; i < ALE_RX_PAGES; i++) { 778 /* 779 * Create DMA stuffs for Rx CMB. 780 */ 781 error = bus_dmamap_create(sc->sc_dmat, ALE_RX_CMB_SZ, 1, 782 ALE_RX_CMB_SZ, 0, BUS_DMA_NOWAIT, 783 &sc->ale_cdata.ale_rx_page[i].cmb_map); 784 if (error) { 785 sc->ale_cdata.ale_rx_page[i].cmb_map = NULL; 786 return ENOBUFS; 787 } 788 789 /* Allocate DMA'able memory for Rx CMB */ 790 error = bus_dmamem_alloc(sc->sc_dmat, ALE_RX_CMB_SZ, 791 ETHER_ALIGN, 0, &sc->ale_cdata.ale_rx_page[i].cmb_seg, 1, 792 &nsegs, BUS_DMA_WAITOK); 793 if (error) { 794 printf("%s: could not allocate DMA'able memory for " 795 "Rx CMB\n", device_xname(sc->sc_dev)); 796 return error; 797 } 798 error = bus_dmamem_map(sc->sc_dmat, 799 &sc->ale_cdata.ale_rx_page[i].cmb_seg, nsegs, 800 ALE_RX_CMB_SZ, 801 (void **)&sc->ale_cdata.ale_rx_page[i].cmb_addr, 802 BUS_DMA_NOWAIT); 803 if (error) 804 return ENOBUFS; 805 806 memset(sc->ale_cdata.ale_rx_page[i].cmb_addr, 0, ALE_RX_CMB_SZ); 807 808 /* Load the DMA map for Rx CMB */ 809 error = bus_dmamap_load(sc->sc_dmat, 810 sc->ale_cdata.ale_rx_page[i].cmb_map, 811 sc->ale_cdata.ale_rx_page[i].cmb_addr, 812 ALE_RX_CMB_SZ, NULL, BUS_DMA_WAITOK); 813 if (error) { 814 printf("%s: could not load DMA'able memory for Rx CMB" 815 "\n", device_xname(sc->sc_dev)); 816 bus_dmamem_free(sc->sc_dmat, 817 &sc->ale_cdata.ale_rx_page[i].cmb_seg, 1); 818 return error; 819 } 820 sc->ale_cdata.ale_rx_page[i].cmb_paddr = 821 sc->ale_cdata.ale_rx_page[i].cmb_map->dm_segs[0].ds_addr; 822 } 823 824 825 /* Create DMA maps for Tx buffers. */ 826 for (i = 0; i < ALE_TX_RING_CNT; i++) { 827 txd = &sc->ale_cdata.ale_txdesc[i]; 828 txd->tx_m = NULL; 829 txd->tx_dmamap = NULL; 830 error = bus_dmamap_create(sc->sc_dmat, ALE_TSO_MAXSIZE, 831 ALE_MAXTXSEGS, ALE_TSO_MAXSEGSIZE, 0, BUS_DMA_NOWAIT, 832 &txd->tx_dmamap); 833 if (error) { 834 txd->tx_dmamap = NULL; 835 printf("%s: could not create Tx dmamap.\n", 836 device_xname(sc->sc_dev)); 837 return error; 838 } 839 } 840 841 return 0; 842 } 843 844 static void 845 ale_dma_free(struct ale_softc *sc) 846 { 847 struct ale_txdesc *txd; 848 int i; 849 850 /* Tx buffers. */ 851 for (i = 0; i < ALE_TX_RING_CNT; i++) { 852 txd = &sc->ale_cdata.ale_txdesc[i]; 853 if (txd->tx_dmamap != NULL) { 854 bus_dmamap_destroy(sc->sc_dmat, txd->tx_dmamap); 855 txd->tx_dmamap = NULL; 856 } 857 } 858 859 /* Tx descriptor ring. */ 860 if (sc->ale_cdata.ale_tx_ring_map != NULL) 861 bus_dmamap_unload(sc->sc_dmat, sc->ale_cdata.ale_tx_ring_map); 862 if (sc->ale_cdata.ale_tx_ring_map != NULL && 863 sc->ale_cdata.ale_tx_ring != NULL) 864 bus_dmamem_free(sc->sc_dmat, 865 &sc->ale_cdata.ale_tx_ring_seg, 1); 866 sc->ale_cdata.ale_tx_ring = NULL; 867 sc->ale_cdata.ale_tx_ring_map = NULL; 868 869 /* Rx page block. */ 870 for (i = 0; i < ALE_RX_PAGES; i++) { 871 if (sc->ale_cdata.ale_rx_page[i].page_map != NULL) 872 bus_dmamap_unload(sc->sc_dmat, 873 sc->ale_cdata.ale_rx_page[i].page_map); 874 if (sc->ale_cdata.ale_rx_page[i].page_map != NULL && 875 sc->ale_cdata.ale_rx_page[i].page_addr != NULL) 876 bus_dmamem_free(sc->sc_dmat, 877 &sc->ale_cdata.ale_rx_page[i].page_seg, 1); 878 sc->ale_cdata.ale_rx_page[i].page_addr = NULL; 879 sc->ale_cdata.ale_rx_page[i].page_map = NULL; 880 } 881 882 /* Rx CMB. */ 883 for (i = 0; i < ALE_RX_PAGES; i++) { 884 if (sc->ale_cdata.ale_rx_page[i].cmb_map != NULL) 885 bus_dmamap_unload(sc->sc_dmat, 886 sc->ale_cdata.ale_rx_page[i].cmb_map); 887 if (sc->ale_cdata.ale_rx_page[i].cmb_map != NULL && 888 sc->ale_cdata.ale_rx_page[i].cmb_addr != NULL) 889 bus_dmamem_free(sc->sc_dmat, 890 &sc->ale_cdata.ale_rx_page[i].cmb_seg, 1); 891 sc->ale_cdata.ale_rx_page[i].cmb_addr = NULL; 892 sc->ale_cdata.ale_rx_page[i].cmb_map = NULL; 893 } 894 895 /* Tx CMB. */ 896 if (sc->ale_cdata.ale_tx_cmb_map != NULL) 897 bus_dmamap_unload(sc->sc_dmat, sc->ale_cdata.ale_tx_cmb_map); 898 if (sc->ale_cdata.ale_tx_cmb_map != NULL && 899 sc->ale_cdata.ale_tx_cmb != NULL) 900 bus_dmamem_free(sc->sc_dmat, 901 &sc->ale_cdata.ale_tx_cmb_seg, 1); 902 sc->ale_cdata.ale_tx_cmb = NULL; 903 sc->ale_cdata.ale_tx_cmb_map = NULL; 904 905 } 906 907 static int 908 ale_encap(struct ale_softc *sc, struct mbuf **m_head) 909 { 910 struct ale_txdesc *txd, *txd_last; 911 struct tx_desc *desc; 912 struct mbuf *m; 913 bus_dmamap_t map; 914 uint32_t cflags, poff, vtag; 915 int error, i, nsegs, prod; 916 #if NVLAN > 0 917 struct m_tag *mtag; 918 #endif 919 920 m = *m_head; 921 cflags = vtag = 0; 922 poff = 0; 923 924 prod = sc->ale_cdata.ale_tx_prod; 925 txd = &sc->ale_cdata.ale_txdesc[prod]; 926 txd_last = txd; 927 map = txd->tx_dmamap; 928 929 error = bus_dmamap_load_mbuf(sc->sc_dmat, map, *m_head, BUS_DMA_NOWAIT); 930 if (error == EFBIG) { 931 error = 0; 932 933 *m_head = m_pullup(*m_head, MHLEN); 934 if (*m_head == NULL) { 935 printf("%s: can't defrag TX mbuf\n", 936 device_xname(sc->sc_dev)); 937 return ENOBUFS; 938 } 939 940 error = bus_dmamap_load_mbuf(sc->sc_dmat, map, *m_head, 941 BUS_DMA_NOWAIT); 942 943 if (error != 0) { 944 printf("%s: could not load defragged TX mbuf\n", 945 device_xname(sc->sc_dev)); 946 m_freem(*m_head); 947 *m_head = NULL; 948 return error; 949 } 950 } else if (error) { 951 printf("%s: could not load TX mbuf\n", device_xname(sc->sc_dev)); 952 return error; 953 } 954 955 nsegs = map->dm_nsegs; 956 957 if (nsegs == 0) { 958 m_freem(*m_head); 959 *m_head = NULL; 960 return EIO; 961 } 962 963 /* Check descriptor overrun. */ 964 if (sc->ale_cdata.ale_tx_cnt + nsegs >= ALE_TX_RING_CNT - 2) { 965 bus_dmamap_unload(sc->sc_dmat, map); 966 return ENOBUFS; 967 } 968 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 969 BUS_DMASYNC_PREWRITE); 970 971 m = *m_head; 972 /* Configure Tx checksum offload. */ 973 if ((m->m_pkthdr.csum_flags & ALE_CSUM_FEATURES) != 0) { 974 /* 975 * AR81xx supports Tx custom checksum offload feature 976 * that offloads single 16bit checksum computation. 977 * So you can choose one among IP, TCP and UDP. 978 * Normally driver sets checksum start/insertion 979 * position from the information of TCP/UDP frame as 980 * TCP/UDP checksum takes more time than that of IP. 981 * However it seems that custom checksum offload 982 * requires 4 bytes aligned Tx buffers due to hardware 983 * bug. 984 * AR81xx also supports explicit Tx checksum computation 985 * if it is told that the size of IP header and TCP 986 * header(for UDP, the header size does not matter 987 * because it's fixed length). However with this scheme 988 * TSO does not work so you have to choose one either 989 * TSO or explicit Tx checksum offload. I chosen TSO 990 * plus custom checksum offload with work-around which 991 * will cover most common usage for this consumer 992 * ethernet controller. The work-around takes a lot of 993 * CPU cycles if Tx buffer is not aligned on 4 bytes 994 * boundary, though. 995 */ 996 cflags |= ALE_TD_CXSUM; 997 /* Set checksum start offset. */ 998 cflags |= (poff << ALE_TD_CSUM_PLOADOFFSET_SHIFT); 999 } 1000 1001 #if NVLAN > 0 1002 /* Configure VLAN hardware tag insertion. */ 1003 if ((mtag = VLAN_OUTPUT_TAG(&sc->sc_ec, m))) { 1004 vtag = ALE_TX_VLAN_TAG(htons(VLAN_TAG_VALUE(mtag))); 1005 vtag = ((vtag << ALE_TD_VLAN_SHIFT) & ALE_TD_VLAN_MASK); 1006 cflags |= ALE_TD_INSERT_VLAN_TAG; 1007 } 1008 #endif 1009 1010 desc = NULL; 1011 for (i = 0; i < nsegs; i++) { 1012 desc = &sc->ale_cdata.ale_tx_ring[prod]; 1013 desc->addr = htole64(map->dm_segs[i].ds_addr); 1014 desc->len = 1015 htole32(ALE_TX_BYTES(map->dm_segs[i].ds_len) | vtag); 1016 desc->flags = htole32(cflags); 1017 sc->ale_cdata.ale_tx_cnt++; 1018 ALE_DESC_INC(prod, ALE_TX_RING_CNT); 1019 } 1020 /* Update producer index. */ 1021 sc->ale_cdata.ale_tx_prod = prod; 1022 1023 /* Finally set EOP on the last descriptor. */ 1024 prod = (prod + ALE_TX_RING_CNT - 1) % ALE_TX_RING_CNT; 1025 desc = &sc->ale_cdata.ale_tx_ring[prod]; 1026 desc->flags |= htole32(ALE_TD_EOP); 1027 1028 /* Swap dmamap of the first and the last. */ 1029 txd = &sc->ale_cdata.ale_txdesc[prod]; 1030 map = txd_last->tx_dmamap; 1031 txd_last->tx_dmamap = txd->tx_dmamap; 1032 txd->tx_dmamap = map; 1033 txd->tx_m = m; 1034 1035 /* Sync descriptors. */ 1036 bus_dmamap_sync(sc->sc_dmat, sc->ale_cdata.ale_tx_ring_map, 0, 1037 sc->ale_cdata.ale_tx_ring_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 1038 1039 return 0; 1040 } 1041 1042 static void 1043 ale_start(struct ifnet *ifp) 1044 { 1045 struct ale_softc *sc = ifp->if_softc; 1046 struct mbuf *m_head; 1047 int enq; 1048 1049 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 1050 return; 1051 1052 /* Reclaim transmitted frames. */ 1053 if (sc->ale_cdata.ale_tx_cnt >= ALE_TX_DESC_HIWAT) 1054 ale_txeof(sc); 1055 1056 enq = 0; 1057 for (;;) { 1058 IFQ_DEQUEUE(&ifp->if_snd, m_head); 1059 if (m_head == NULL) 1060 break; 1061 1062 /* 1063 * Pack the data into the transmit ring. If we 1064 * don't have room, set the OACTIVE flag and wait 1065 * for the NIC to drain the ring. 1066 */ 1067 if (ale_encap(sc, &m_head)) { 1068 if (m_head == NULL) 1069 break; 1070 IF_PREPEND(&ifp->if_snd, m_head); 1071 ifp->if_flags |= IFF_OACTIVE; 1072 break; 1073 } 1074 enq = 1; 1075 1076 /* 1077 * If there's a BPF listener, bounce a copy of this frame 1078 * to him. 1079 */ 1080 bpf_mtap(ifp, m_head); 1081 } 1082 1083 if (enq) { 1084 /* Kick. */ 1085 CSR_WRITE_4(sc, ALE_MBOX_TPD_PROD_IDX, 1086 sc->ale_cdata.ale_tx_prod); 1087 1088 /* Set a timeout in case the chip goes out to lunch. */ 1089 ifp->if_timer = ALE_TX_TIMEOUT; 1090 } 1091 } 1092 1093 static void 1094 ale_watchdog(struct ifnet *ifp) 1095 { 1096 struct ale_softc *sc = ifp->if_softc; 1097 1098 if ((sc->ale_flags & ALE_FLAG_LINK) == 0) { 1099 printf("%s: watchdog timeout (missed link)\n", 1100 device_xname(sc->sc_dev)); 1101 ifp->if_oerrors++; 1102 ale_init(ifp); 1103 return; 1104 } 1105 1106 printf("%s: watchdog timeout\n", device_xname(sc->sc_dev)); 1107 ifp->if_oerrors++; 1108 ale_init(ifp); 1109 1110 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 1111 ale_start(ifp); 1112 } 1113 1114 static int 1115 ale_ioctl(struct ifnet *ifp, u_long cmd, void *data) 1116 { 1117 struct ale_softc *sc = ifp->if_softc; 1118 int s, error; 1119 1120 s = splnet(); 1121 1122 error = ether_ioctl(ifp, cmd, data); 1123 if (error == ENETRESET) { 1124 if (ifp->if_flags & IFF_RUNNING) 1125 ale_rxfilter(sc); 1126 error = 0; 1127 } 1128 1129 splx(s); 1130 return error; 1131 } 1132 1133 static void 1134 ale_mac_config(struct ale_softc *sc) 1135 { 1136 struct mii_data *mii; 1137 uint32_t reg; 1138 1139 mii = &sc->sc_miibus; 1140 reg = CSR_READ_4(sc, ALE_MAC_CFG); 1141 reg &= ~(MAC_CFG_FULL_DUPLEX | MAC_CFG_TX_FC | MAC_CFG_RX_FC | 1142 MAC_CFG_SPEED_MASK); 1143 1144 /* Reprogram MAC with resolved speed/duplex. */ 1145 switch (IFM_SUBTYPE(mii->mii_media_active)) { 1146 case IFM_10_T: 1147 case IFM_100_TX: 1148 reg |= MAC_CFG_SPEED_10_100; 1149 break; 1150 case IFM_1000_T: 1151 reg |= MAC_CFG_SPEED_1000; 1152 break; 1153 } 1154 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 1155 reg |= MAC_CFG_FULL_DUPLEX; 1156 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0) 1157 reg |= MAC_CFG_TX_FC; 1158 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0) 1159 reg |= MAC_CFG_RX_FC; 1160 } 1161 CSR_WRITE_4(sc, ALE_MAC_CFG, reg); 1162 } 1163 1164 static void 1165 ale_stats_clear(struct ale_softc *sc) 1166 { 1167 struct smb sb; 1168 uint32_t *reg; 1169 int i; 1170 1171 for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered; reg++) { 1172 CSR_READ_4(sc, ALE_RX_MIB_BASE + i); 1173 i += sizeof(uint32_t); 1174 } 1175 /* Read Tx statistics. */ 1176 for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes; reg++) { 1177 CSR_READ_4(sc, ALE_TX_MIB_BASE + i); 1178 i += sizeof(uint32_t); 1179 } 1180 } 1181 1182 static void 1183 ale_stats_update(struct ale_softc *sc) 1184 { 1185 struct ifnet *ifp = &sc->sc_ec.ec_if; 1186 struct ale_hw_stats *stat; 1187 struct smb sb, *smb; 1188 uint32_t *reg; 1189 int i; 1190 1191 stat = &sc->ale_stats; 1192 smb = &sb; 1193 1194 /* Read Rx statistics. */ 1195 for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered; reg++) { 1196 *reg = CSR_READ_4(sc, ALE_RX_MIB_BASE + i); 1197 i += sizeof(uint32_t); 1198 } 1199 /* Read Tx statistics. */ 1200 for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes; reg++) { 1201 *reg = CSR_READ_4(sc, ALE_TX_MIB_BASE + i); 1202 i += sizeof(uint32_t); 1203 } 1204 1205 /* Rx stats. */ 1206 stat->rx_frames += smb->rx_frames; 1207 stat->rx_bcast_frames += smb->rx_bcast_frames; 1208 stat->rx_mcast_frames += smb->rx_mcast_frames; 1209 stat->rx_pause_frames += smb->rx_pause_frames; 1210 stat->rx_control_frames += smb->rx_control_frames; 1211 stat->rx_crcerrs += smb->rx_crcerrs; 1212 stat->rx_lenerrs += smb->rx_lenerrs; 1213 stat->rx_bytes += smb->rx_bytes; 1214 stat->rx_runts += smb->rx_runts; 1215 stat->rx_fragments += smb->rx_fragments; 1216 stat->rx_pkts_64 += smb->rx_pkts_64; 1217 stat->rx_pkts_65_127 += smb->rx_pkts_65_127; 1218 stat->rx_pkts_128_255 += smb->rx_pkts_128_255; 1219 stat->rx_pkts_256_511 += smb->rx_pkts_256_511; 1220 stat->rx_pkts_512_1023 += smb->rx_pkts_512_1023; 1221 stat->rx_pkts_1024_1518 += smb->rx_pkts_1024_1518; 1222 stat->rx_pkts_1519_max += smb->rx_pkts_1519_max; 1223 stat->rx_pkts_truncated += smb->rx_pkts_truncated; 1224 stat->rx_fifo_oflows += smb->rx_fifo_oflows; 1225 stat->rx_rrs_errs += smb->rx_rrs_errs; 1226 stat->rx_alignerrs += smb->rx_alignerrs; 1227 stat->rx_bcast_bytes += smb->rx_bcast_bytes; 1228 stat->rx_mcast_bytes += smb->rx_mcast_bytes; 1229 stat->rx_pkts_filtered += smb->rx_pkts_filtered; 1230 1231 /* Tx stats. */ 1232 stat->tx_frames += smb->tx_frames; 1233 stat->tx_bcast_frames += smb->tx_bcast_frames; 1234 stat->tx_mcast_frames += smb->tx_mcast_frames; 1235 stat->tx_pause_frames += smb->tx_pause_frames; 1236 stat->tx_excess_defer += smb->tx_excess_defer; 1237 stat->tx_control_frames += smb->tx_control_frames; 1238 stat->tx_deferred += smb->tx_deferred; 1239 stat->tx_bytes += smb->tx_bytes; 1240 stat->tx_pkts_64 += smb->tx_pkts_64; 1241 stat->tx_pkts_65_127 += smb->tx_pkts_65_127; 1242 stat->tx_pkts_128_255 += smb->tx_pkts_128_255; 1243 stat->tx_pkts_256_511 += smb->tx_pkts_256_511; 1244 stat->tx_pkts_512_1023 += smb->tx_pkts_512_1023; 1245 stat->tx_pkts_1024_1518 += smb->tx_pkts_1024_1518; 1246 stat->tx_pkts_1519_max += smb->tx_pkts_1519_max; 1247 stat->tx_single_colls += smb->tx_single_colls; 1248 stat->tx_multi_colls += smb->tx_multi_colls; 1249 stat->tx_late_colls += smb->tx_late_colls; 1250 stat->tx_excess_colls += smb->tx_excess_colls; 1251 stat->tx_abort += smb->tx_abort; 1252 stat->tx_underrun += smb->tx_underrun; 1253 stat->tx_desc_underrun += smb->tx_desc_underrun; 1254 stat->tx_lenerrs += smb->tx_lenerrs; 1255 stat->tx_pkts_truncated += smb->tx_pkts_truncated; 1256 stat->tx_bcast_bytes += smb->tx_bcast_bytes; 1257 stat->tx_mcast_bytes += smb->tx_mcast_bytes; 1258 1259 /* Update counters in ifnet. */ 1260 ifp->if_opackets += smb->tx_frames; 1261 1262 ifp->if_collisions += smb->tx_single_colls + 1263 smb->tx_multi_colls * 2 + smb->tx_late_colls + 1264 smb->tx_abort * HDPX_CFG_RETRY_DEFAULT; 1265 1266 /* 1267 * XXX 1268 * tx_pkts_truncated counter looks suspicious. It constantly 1269 * increments with no sign of Tx errors. This may indicate 1270 * the counter name is not correct one so I've removed the 1271 * counter in output errors. 1272 */ 1273 ifp->if_oerrors += smb->tx_abort + smb->tx_late_colls + 1274 smb->tx_underrun; 1275 1276 ifp->if_ipackets += smb->rx_frames; 1277 1278 ifp->if_ierrors += smb->rx_crcerrs + smb->rx_lenerrs + 1279 smb->rx_runts + smb->rx_pkts_truncated + 1280 smb->rx_fifo_oflows + smb->rx_rrs_errs + 1281 smb->rx_alignerrs; 1282 } 1283 1284 static int 1285 ale_intr(void *xsc) 1286 { 1287 struct ale_softc *sc = xsc; 1288 struct ifnet *ifp = &sc->sc_ec.ec_if; 1289 uint32_t status; 1290 1291 status = CSR_READ_4(sc, ALE_INTR_STATUS); 1292 if ((status & ALE_INTRS) == 0) 1293 return 0; 1294 1295 /* Acknowledge and disable interrupts. */ 1296 CSR_WRITE_4(sc, ALE_INTR_STATUS, status | INTR_DIS_INT); 1297 1298 if (ifp->if_flags & IFF_RUNNING) { 1299 int error; 1300 1301 error = ale_rxeof(sc); 1302 if (error) { 1303 sc->ale_stats.reset_brk_seq++; 1304 ale_init(ifp); 1305 return 0; 1306 } 1307 1308 if (status & (INTR_DMA_RD_TO_RST | INTR_DMA_WR_TO_RST)) { 1309 if (status & INTR_DMA_RD_TO_RST) 1310 printf("%s: DMA read error! -- resetting\n", 1311 device_xname(sc->sc_dev)); 1312 if (status & INTR_DMA_WR_TO_RST) 1313 printf("%s: DMA write error! -- resetting\n", 1314 device_xname(sc->sc_dev)); 1315 ale_init(ifp); 1316 return 0; 1317 } 1318 1319 ale_txeof(sc); 1320 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 1321 ale_start(ifp); 1322 } 1323 1324 /* Re-enable interrupts. */ 1325 CSR_WRITE_4(sc, ALE_INTR_STATUS, 0x7FFFFFFF); 1326 return 1; 1327 } 1328 1329 static void 1330 ale_txeof(struct ale_softc *sc) 1331 { 1332 struct ifnet *ifp = &sc->sc_ec.ec_if; 1333 struct ale_txdesc *txd; 1334 uint32_t cons, prod; 1335 int prog; 1336 1337 if (sc->ale_cdata.ale_tx_cnt == 0) 1338 return; 1339 1340 bus_dmamap_sync(sc->sc_dmat, sc->ale_cdata.ale_tx_ring_map, 0, 1341 sc->ale_cdata.ale_tx_ring_map->dm_mapsize, BUS_DMASYNC_POSTREAD); 1342 if ((sc->ale_flags & ALE_FLAG_TXCMB_BUG) == 0) { 1343 bus_dmamap_sync(sc->sc_dmat, sc->ale_cdata.ale_tx_cmb_map, 0, 1344 sc->ale_cdata.ale_tx_cmb_map->dm_mapsize, 1345 BUS_DMASYNC_POSTREAD); 1346 prod = *sc->ale_cdata.ale_tx_cmb & TPD_CNT_MASK; 1347 } else 1348 prod = CSR_READ_2(sc, ALE_TPD_CONS_IDX); 1349 cons = sc->ale_cdata.ale_tx_cons; 1350 /* 1351 * Go through our Tx list and free mbufs for those 1352 * frames which have been transmitted. 1353 */ 1354 for (prog = 0; cons != prod; prog++, 1355 ALE_DESC_INC(cons, ALE_TX_RING_CNT)) { 1356 if (sc->ale_cdata.ale_tx_cnt <= 0) 1357 break; 1358 prog++; 1359 ifp->if_flags &= ~IFF_OACTIVE; 1360 sc->ale_cdata.ale_tx_cnt--; 1361 txd = &sc->ale_cdata.ale_txdesc[cons]; 1362 if (txd->tx_m != NULL) { 1363 /* Reclaim transmitted mbufs. */ 1364 bus_dmamap_unload(sc->sc_dmat, txd->tx_dmamap); 1365 m_freem(txd->tx_m); 1366 txd->tx_m = NULL; 1367 } 1368 } 1369 1370 if (prog > 0) { 1371 sc->ale_cdata.ale_tx_cons = cons; 1372 /* 1373 * Unarm watchdog timer only when there is no pending 1374 * Tx descriptors in queue. 1375 */ 1376 if (sc->ale_cdata.ale_tx_cnt == 0) 1377 ifp->if_timer = 0; 1378 } 1379 } 1380 1381 static void 1382 ale_rx_update_page(struct ale_softc *sc, struct ale_rx_page **page, 1383 uint32_t length, uint32_t *prod) 1384 { 1385 struct ale_rx_page *rx_page; 1386 1387 rx_page = *page; 1388 /* Update consumer position. */ 1389 rx_page->cons += roundup(length + sizeof(struct rx_rs), 1390 ALE_RX_PAGE_ALIGN); 1391 if (rx_page->cons >= ALE_RX_PAGE_SZ) { 1392 /* 1393 * End of Rx page reached, let hardware reuse 1394 * this page. 1395 */ 1396 rx_page->cons = 0; 1397 *rx_page->cmb_addr = 0; 1398 bus_dmamap_sync(sc->sc_dmat, rx_page->cmb_map, 0, 1399 rx_page->cmb_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 1400 CSR_WRITE_1(sc, ALE_RXF0_PAGE0 + sc->ale_cdata.ale_rx_curp, 1401 RXF_VALID); 1402 /* Switch to alternate Rx page. */ 1403 sc->ale_cdata.ale_rx_curp ^= 1; 1404 rx_page = *page = 1405 &sc->ale_cdata.ale_rx_page[sc->ale_cdata.ale_rx_curp]; 1406 /* Page flipped, sync CMB and Rx page. */ 1407 bus_dmamap_sync(sc->sc_dmat, rx_page->page_map, 0, 1408 rx_page->page_map->dm_mapsize, BUS_DMASYNC_POSTREAD); 1409 bus_dmamap_sync(sc->sc_dmat, rx_page->cmb_map, 0, 1410 rx_page->cmb_map->dm_mapsize, BUS_DMASYNC_POSTREAD); 1411 /* Sync completed, cache updated producer index. */ 1412 *prod = *rx_page->cmb_addr; 1413 } 1414 } 1415 1416 1417 /* 1418 * It seems that AR81xx controller can compute partial checksum. 1419 * The partial checksum value can be used to accelerate checksum 1420 * computation for fragmented TCP/UDP packets. Upper network stack 1421 * already takes advantage of the partial checksum value in IP 1422 * reassembly stage. But I'm not sure the correctness of the 1423 * partial hardware checksum assistance due to lack of data sheet. 1424 * In addition, the Rx feature of controller that requires copying 1425 * for every frames effectively nullifies one of most nice offload 1426 * capability of controller. 1427 */ 1428 static void 1429 ale_rxcsum(struct ale_softc *sc, struct mbuf *m, uint32_t status) 1430 { 1431 if (status & ALE_RD_IPCSUM_NOK) 1432 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 1433 1434 if ((sc->ale_flags & ALE_FLAG_RXCSUM_BUG) == 0) { 1435 if (((status & ALE_RD_IPV4_FRAG) == 0) && 1436 ((status & (ALE_RD_TCP | ALE_RD_UDP)) != 0) && 1437 (status & ALE_RD_TCP_UDPCSUM_NOK)) 1438 { 1439 m->m_pkthdr.csum_flags |= M_CSUM_TCP_UDP_BAD; 1440 } 1441 } else { 1442 if ((status & (ALE_RD_TCP | ALE_RD_UDP)) != 0) { 1443 if (status & ALE_RD_TCP_UDPCSUM_NOK) { 1444 m->m_pkthdr.csum_flags |= M_CSUM_TCP_UDP_BAD; 1445 } 1446 } 1447 } 1448 /* 1449 * Don't mark bad checksum for TCP/UDP frames 1450 * as fragmented frames may always have set 1451 * bad checksummed bit of frame status. 1452 */ 1453 } 1454 1455 /* Process received frames. */ 1456 static int 1457 ale_rxeof(struct ale_softc *sc) 1458 { 1459 struct ifnet *ifp = &sc->sc_ec.ec_if; 1460 struct ale_rx_page *rx_page; 1461 struct rx_rs *rs; 1462 struct mbuf *m; 1463 uint32_t length, prod, seqno, status; 1464 int prog; 1465 1466 rx_page = &sc->ale_cdata.ale_rx_page[sc->ale_cdata.ale_rx_curp]; 1467 bus_dmamap_sync(sc->sc_dmat, rx_page->cmb_map, 0, 1468 rx_page->cmb_map->dm_mapsize, BUS_DMASYNC_POSTREAD); 1469 bus_dmamap_sync(sc->sc_dmat, rx_page->page_map, 0, 1470 rx_page->page_map->dm_mapsize, BUS_DMASYNC_POSTREAD); 1471 /* 1472 * Don't directly access producer index as hardware may 1473 * update it while Rx handler is in progress. It would 1474 * be even better if there is a way to let hardware 1475 * know how far driver processed its received frames. 1476 * Alternatively, hardware could provide a way to disable 1477 * CMB updates until driver acknowledges the end of CMB 1478 * access. 1479 */ 1480 prod = *rx_page->cmb_addr; 1481 for (prog = 0; ; prog++) { 1482 if (rx_page->cons >= prod) 1483 break; 1484 rs = (struct rx_rs *)(rx_page->page_addr + rx_page->cons); 1485 seqno = ALE_RX_SEQNO(le32toh(rs->seqno)); 1486 if (sc->ale_cdata.ale_rx_seqno != seqno) { 1487 /* 1488 * Normally I believe this should not happen unless 1489 * severe driver bug or corrupted memory. However 1490 * it seems to happen under certain conditions which 1491 * is triggered by abrupt Rx events such as initiation 1492 * of bulk transfer of remote host. It's not easy to 1493 * reproduce this and I doubt it could be related 1494 * with FIFO overflow of hardware or activity of Tx 1495 * CMB updates. I also remember similar behaviour 1496 * seen on RealTek 8139 which uses resembling Rx 1497 * scheme. 1498 */ 1499 if (aledebug) 1500 printf("%s: garbled seq: %u, expected: %u -- " 1501 "resetting!\n", device_xname(sc->sc_dev), 1502 seqno, sc->ale_cdata.ale_rx_seqno); 1503 return EIO; 1504 } 1505 /* Frame received. */ 1506 sc->ale_cdata.ale_rx_seqno++; 1507 length = ALE_RX_BYTES(le32toh(rs->length)); 1508 status = le32toh(rs->flags); 1509 if (status & ALE_RD_ERROR) { 1510 /* 1511 * We want to pass the following frames to upper 1512 * layer regardless of error status of Rx return 1513 * status. 1514 * 1515 * o IP/TCP/UDP checksum is bad. 1516 * o frame length and protocol specific length 1517 * does not match. 1518 */ 1519 if (status & (ALE_RD_CRC | ALE_RD_CODE | 1520 ALE_RD_DRIBBLE | ALE_RD_RUNT | ALE_RD_OFLOW | 1521 ALE_RD_TRUNC)) { 1522 ale_rx_update_page(sc, &rx_page, length, &prod); 1523 continue; 1524 } 1525 } 1526 /* 1527 * m_devget(9) is major bottle-neck of ale(4)(It comes 1528 * from hardware limitation). For jumbo frames we could 1529 * get a slightly better performance if driver use 1530 * m_getjcl(9) with proper buffer size argument. However 1531 * that would make code more complicated and I don't 1532 * think users would expect good Rx performance numbers 1533 * on these low-end consumer ethernet controller. 1534 */ 1535 m = m_devget((char *)(rs + 1), length - ETHER_CRC_LEN, 1536 0, ifp, NULL); 1537 if (m == NULL) { 1538 ifp->if_iqdrops++; 1539 ale_rx_update_page(sc, &rx_page, length, &prod); 1540 continue; 1541 } 1542 if (status & ALE_RD_IPV4) 1543 ale_rxcsum(sc, m, status); 1544 #if NVLAN > 0 1545 if (status & ALE_RD_VLAN) { 1546 uint32_t vtags = ALE_RX_VLAN(le32toh(rs->vtags)); 1547 VLAN_INPUT_TAG(ifp, m, ALE_RX_VLAN_TAG(vtags), ); 1548 } 1549 #endif 1550 1551 1552 bpf_mtap(ifp, m); 1553 1554 /* Pass it to upper layer. */ 1555 ether_input(ifp, m); 1556 1557 ale_rx_update_page(sc, &rx_page, length, &prod); 1558 } 1559 1560 return 0; 1561 } 1562 1563 static void 1564 ale_tick(void *xsc) 1565 { 1566 struct ale_softc *sc = xsc; 1567 struct mii_data *mii = &sc->sc_miibus; 1568 int s; 1569 1570 s = splnet(); 1571 mii_tick(mii); 1572 ale_stats_update(sc); 1573 splx(s); 1574 1575 callout_schedule(&sc->sc_tick_ch, hz); 1576 } 1577 1578 static void 1579 ale_reset(struct ale_softc *sc) 1580 { 1581 uint32_t reg; 1582 int i; 1583 1584 /* Initialize PCIe module. From Linux. */ 1585 CSR_WRITE_4(sc, 0x1008, CSR_READ_4(sc, 0x1008) | 0x8000); 1586 1587 CSR_WRITE_4(sc, ALE_MASTER_CFG, MASTER_RESET); 1588 for (i = ALE_RESET_TIMEOUT; i > 0; i--) { 1589 DELAY(10); 1590 if ((CSR_READ_4(sc, ALE_MASTER_CFG) & MASTER_RESET) == 0) 1591 break; 1592 } 1593 if (i == 0) 1594 printf("%s: master reset timeout!\n", device_xname(sc->sc_dev)); 1595 1596 for (i = ALE_RESET_TIMEOUT; i > 0; i--) { 1597 if ((reg = CSR_READ_4(sc, ALE_IDLE_STATUS)) == 0) 1598 break; 1599 DELAY(10); 1600 } 1601 1602 if (i == 0) 1603 printf("%s: reset timeout(0x%08x)!\n", device_xname(sc->sc_dev), 1604 reg); 1605 } 1606 1607 static int 1608 ale_init(struct ifnet *ifp) 1609 { 1610 struct ale_softc *sc = ifp->if_softc; 1611 struct mii_data *mii; 1612 uint8_t eaddr[ETHER_ADDR_LEN]; 1613 bus_addr_t paddr; 1614 uint32_t reg, rxf_hi, rxf_lo; 1615 1616 /* 1617 * Cancel any pending I/O. 1618 */ 1619 ale_stop(ifp, 0); 1620 1621 /* 1622 * Reset the chip to a known state. 1623 */ 1624 ale_reset(sc); 1625 1626 /* Initialize Tx descriptors, DMA memory blocks. */ 1627 ale_init_rx_pages(sc); 1628 ale_init_tx_ring(sc); 1629 1630 /* Reprogram the station address. */ 1631 memcpy(eaddr, CLLADDR(ifp->if_sadl), ETHER_ADDR_LEN); 1632 CSR_WRITE_4(sc, ALE_PAR0, 1633 eaddr[2] << 24 | eaddr[3] << 16 | eaddr[4] << 8 | eaddr[5]); 1634 CSR_WRITE_4(sc, ALE_PAR1, eaddr[0] << 8 | eaddr[1]); 1635 1636 /* 1637 * Clear WOL status and disable all WOL feature as WOL 1638 * would interfere Rx operation under normal environments. 1639 */ 1640 CSR_READ_4(sc, ALE_WOL_CFG); 1641 CSR_WRITE_4(sc, ALE_WOL_CFG, 0); 1642 1643 /* 1644 * Set Tx descriptor/RXF0/CMB base addresses. They share 1645 * the same high address part of DMAable region. 1646 */ 1647 paddr = sc->ale_cdata.ale_tx_ring_paddr; 1648 CSR_WRITE_4(sc, ALE_TPD_ADDR_HI, ALE_ADDR_HI(paddr)); 1649 CSR_WRITE_4(sc, ALE_TPD_ADDR_LO, ALE_ADDR_LO(paddr)); 1650 CSR_WRITE_4(sc, ALE_TPD_CNT, 1651 (ALE_TX_RING_CNT << TPD_CNT_SHIFT) & TPD_CNT_MASK); 1652 1653 /* Set Rx page base address, note we use single queue. */ 1654 paddr = sc->ale_cdata.ale_rx_page[0].page_paddr; 1655 CSR_WRITE_4(sc, ALE_RXF0_PAGE0_ADDR_LO, ALE_ADDR_LO(paddr)); 1656 paddr = sc->ale_cdata.ale_rx_page[1].page_paddr; 1657 CSR_WRITE_4(sc, ALE_RXF0_PAGE1_ADDR_LO, ALE_ADDR_LO(paddr)); 1658 1659 /* Set Tx/Rx CMB addresses. */ 1660 paddr = sc->ale_cdata.ale_tx_cmb_paddr; 1661 CSR_WRITE_4(sc, ALE_TX_CMB_ADDR_LO, ALE_ADDR_LO(paddr)); 1662 paddr = sc->ale_cdata.ale_rx_page[0].cmb_paddr; 1663 CSR_WRITE_4(sc, ALE_RXF0_CMB0_ADDR_LO, ALE_ADDR_LO(paddr)); 1664 paddr = sc->ale_cdata.ale_rx_page[1].cmb_paddr; 1665 CSR_WRITE_4(sc, ALE_RXF0_CMB1_ADDR_LO, ALE_ADDR_LO(paddr)); 1666 1667 /* Mark RXF0 is valid. */ 1668 CSR_WRITE_1(sc, ALE_RXF0_PAGE0, RXF_VALID); 1669 CSR_WRITE_1(sc, ALE_RXF0_PAGE1, RXF_VALID); 1670 /* 1671 * No need to initialize RFX1/RXF2/RXF3. We don't use 1672 * multi-queue yet. 1673 */ 1674 1675 /* Set Rx page size, excluding guard frame size. */ 1676 CSR_WRITE_4(sc, ALE_RXF_PAGE_SIZE, ALE_RX_PAGE_SZ); 1677 1678 /* Tell hardware that we're ready to load DMA blocks. */ 1679 CSR_WRITE_4(sc, ALE_DMA_BLOCK, DMA_BLOCK_LOAD); 1680 1681 /* Set Rx/Tx interrupt trigger threshold. */ 1682 CSR_WRITE_4(sc, ALE_INT_TRIG_THRESH, (1 << INT_TRIG_RX_THRESH_SHIFT) | 1683 (4 << INT_TRIG_TX_THRESH_SHIFT)); 1684 /* 1685 * XXX 1686 * Set interrupt trigger timer, its purpose and relation 1687 * with interrupt moderation mechanism is not clear yet. 1688 */ 1689 CSR_WRITE_4(sc, ALE_INT_TRIG_TIMER, 1690 ((ALE_USECS(10) << INT_TRIG_RX_TIMER_SHIFT) | 1691 (ALE_USECS(1000) << INT_TRIG_TX_TIMER_SHIFT))); 1692 1693 /* Configure interrupt moderation timer. */ 1694 sc->ale_int_rx_mod = ALE_IM_RX_TIMER_DEFAULT; 1695 sc->ale_int_tx_mod = ALE_IM_TX_TIMER_DEFAULT; 1696 reg = ALE_USECS(sc->ale_int_rx_mod) << IM_TIMER_RX_SHIFT; 1697 reg |= ALE_USECS(sc->ale_int_tx_mod) << IM_TIMER_TX_SHIFT; 1698 CSR_WRITE_4(sc, ALE_IM_TIMER, reg); 1699 reg = CSR_READ_4(sc, ALE_MASTER_CFG); 1700 reg &= ~(MASTER_CHIP_REV_MASK | MASTER_CHIP_ID_MASK); 1701 reg &= ~(MASTER_IM_RX_TIMER_ENB | MASTER_IM_TX_TIMER_ENB); 1702 if (ALE_USECS(sc->ale_int_rx_mod) != 0) 1703 reg |= MASTER_IM_RX_TIMER_ENB; 1704 if (ALE_USECS(sc->ale_int_tx_mod) != 0) 1705 reg |= MASTER_IM_TX_TIMER_ENB; 1706 CSR_WRITE_4(sc, ALE_MASTER_CFG, reg); 1707 CSR_WRITE_2(sc, ALE_INTR_CLR_TIMER, ALE_USECS(1000)); 1708 1709 /* Set Maximum frame size of controller. */ 1710 if (ifp->if_mtu < ETHERMTU) 1711 sc->ale_max_frame_size = ETHERMTU; 1712 else 1713 sc->ale_max_frame_size = ifp->if_mtu; 1714 sc->ale_max_frame_size += ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN + ETHER_CRC_LEN; 1715 CSR_WRITE_4(sc, ALE_FRAME_SIZE, sc->ale_max_frame_size); 1716 1717 /* Configure IPG/IFG parameters. */ 1718 CSR_WRITE_4(sc, ALE_IPG_IFG_CFG, 1719 ((IPG_IFG_IPGT_DEFAULT << IPG_IFG_IPGT_SHIFT) & IPG_IFG_IPGT_MASK) | 1720 ((IPG_IFG_MIFG_DEFAULT << IPG_IFG_MIFG_SHIFT) & IPG_IFG_MIFG_MASK) | 1721 ((IPG_IFG_IPG1_DEFAULT << IPG_IFG_IPG1_SHIFT) & IPG_IFG_IPG1_MASK) | 1722 ((IPG_IFG_IPG2_DEFAULT << IPG_IFG_IPG2_SHIFT) & IPG_IFG_IPG2_MASK)); 1723 1724 /* Set parameters for half-duplex media. */ 1725 CSR_WRITE_4(sc, ALE_HDPX_CFG, 1726 ((HDPX_CFG_LCOL_DEFAULT << HDPX_CFG_LCOL_SHIFT) & 1727 HDPX_CFG_LCOL_MASK) | 1728 ((HDPX_CFG_RETRY_DEFAULT << HDPX_CFG_RETRY_SHIFT) & 1729 HDPX_CFG_RETRY_MASK) | HDPX_CFG_EXC_DEF_EN | 1730 ((HDPX_CFG_ABEBT_DEFAULT << HDPX_CFG_ABEBT_SHIFT) & 1731 HDPX_CFG_ABEBT_MASK) | 1732 ((HDPX_CFG_JAMIPG_DEFAULT << HDPX_CFG_JAMIPG_SHIFT) & 1733 HDPX_CFG_JAMIPG_MASK)); 1734 1735 /* Configure Tx jumbo frame parameters. */ 1736 if ((sc->ale_flags & ALE_FLAG_JUMBO) != 0) { 1737 if (ifp->if_mtu < ETHERMTU) 1738 reg = sc->ale_max_frame_size; 1739 else if (ifp->if_mtu < 6 * 1024) 1740 reg = (sc->ale_max_frame_size * 2) / 3; 1741 else 1742 reg = sc->ale_max_frame_size / 2; 1743 CSR_WRITE_4(sc, ALE_TX_JUMBO_THRESH, 1744 roundup(reg, TX_JUMBO_THRESH_UNIT) >> 1745 TX_JUMBO_THRESH_UNIT_SHIFT); 1746 } 1747 1748 /* Configure TxQ. */ 1749 reg = (128 << (sc->ale_dma_rd_burst >> DMA_CFG_RD_BURST_SHIFT)) 1750 << TXQ_CFG_TX_FIFO_BURST_SHIFT; 1751 reg |= (TXQ_CFG_TPD_BURST_DEFAULT << TXQ_CFG_TPD_BURST_SHIFT) & 1752 TXQ_CFG_TPD_BURST_MASK; 1753 CSR_WRITE_4(sc, ALE_TXQ_CFG, reg | TXQ_CFG_ENHANCED_MODE | TXQ_CFG_ENB); 1754 1755 /* Configure Rx jumbo frame & flow control parameters. */ 1756 if ((sc->ale_flags & ALE_FLAG_JUMBO) != 0) { 1757 reg = roundup(sc->ale_max_frame_size, RX_JUMBO_THRESH_UNIT); 1758 CSR_WRITE_4(sc, ALE_RX_JUMBO_THRESH, 1759 (((reg >> RX_JUMBO_THRESH_UNIT_SHIFT) << 1760 RX_JUMBO_THRESH_MASK_SHIFT) & RX_JUMBO_THRESH_MASK) | 1761 ((RX_JUMBO_LKAH_DEFAULT << RX_JUMBO_LKAH_SHIFT) & 1762 RX_JUMBO_LKAH_MASK)); 1763 reg = CSR_READ_4(sc, ALE_SRAM_RX_FIFO_LEN); 1764 rxf_hi = (reg * 7) / 10; 1765 rxf_lo = (reg * 3)/ 10; 1766 CSR_WRITE_4(sc, ALE_RX_FIFO_PAUSE_THRESH, 1767 ((rxf_lo << RX_FIFO_PAUSE_THRESH_LO_SHIFT) & 1768 RX_FIFO_PAUSE_THRESH_LO_MASK) | 1769 ((rxf_hi << RX_FIFO_PAUSE_THRESH_HI_SHIFT) & 1770 RX_FIFO_PAUSE_THRESH_HI_MASK)); 1771 } 1772 1773 /* Disable RSS. */ 1774 CSR_WRITE_4(sc, ALE_RSS_IDT_TABLE0, 0); 1775 CSR_WRITE_4(sc, ALE_RSS_CPU, 0); 1776 1777 /* Configure RxQ. */ 1778 CSR_WRITE_4(sc, ALE_RXQ_CFG, 1779 RXQ_CFG_ALIGN_32 | RXQ_CFG_CUT_THROUGH_ENB | RXQ_CFG_ENB); 1780 1781 /* Configure DMA parameters. */ 1782 reg = 0; 1783 if ((sc->ale_flags & ALE_FLAG_TXCMB_BUG) == 0) 1784 reg |= DMA_CFG_TXCMB_ENB; 1785 CSR_WRITE_4(sc, ALE_DMA_CFG, 1786 DMA_CFG_OUT_ORDER | DMA_CFG_RD_REQ_PRI | DMA_CFG_RCB_64 | 1787 sc->ale_dma_rd_burst | reg | 1788 sc->ale_dma_wr_burst | DMA_CFG_RXCMB_ENB | 1789 ((DMA_CFG_RD_DELAY_CNT_DEFAULT << DMA_CFG_RD_DELAY_CNT_SHIFT) & 1790 DMA_CFG_RD_DELAY_CNT_MASK) | 1791 ((DMA_CFG_WR_DELAY_CNT_DEFAULT << DMA_CFG_WR_DELAY_CNT_SHIFT) & 1792 DMA_CFG_WR_DELAY_CNT_MASK)); 1793 1794 /* 1795 * Hardware can be configured to issue SMB interrupt based 1796 * on programmed interval. Since there is a callout that is 1797 * invoked for every hz in driver we use that instead of 1798 * relying on periodic SMB interrupt. 1799 */ 1800 CSR_WRITE_4(sc, ALE_SMB_STAT_TIMER, ALE_USECS(0)); 1801 1802 /* Clear MAC statistics. */ 1803 ale_stats_clear(sc); 1804 1805 /* 1806 * Configure Tx/Rx MACs. 1807 * - Auto-padding for short frames. 1808 * - Enable CRC generation. 1809 * Actual reconfiguration of MAC for resolved speed/duplex 1810 * is followed after detection of link establishment. 1811 * AR81xx always does checksum computation regardless of 1812 * MAC_CFG_RXCSUM_ENB bit. In fact, setting the bit will 1813 * cause Rx handling issue for fragmented IP datagrams due 1814 * to silicon bug. 1815 */ 1816 reg = MAC_CFG_TX_CRC_ENB | MAC_CFG_TX_AUTO_PAD | MAC_CFG_FULL_DUPLEX | 1817 ((MAC_CFG_PREAMBLE_DEFAULT << MAC_CFG_PREAMBLE_SHIFT) & 1818 MAC_CFG_PREAMBLE_MASK); 1819 if ((sc->ale_flags & ALE_FLAG_FASTETHER) != 0) 1820 reg |= MAC_CFG_SPEED_10_100; 1821 else 1822 reg |= MAC_CFG_SPEED_1000; 1823 CSR_WRITE_4(sc, ALE_MAC_CFG, reg); 1824 1825 /* Set up the receive filter. */ 1826 ale_rxfilter(sc); 1827 ale_rxvlan(sc); 1828 1829 /* Acknowledge all pending interrupts and clear it. */ 1830 CSR_WRITE_4(sc, ALE_INTR_MASK, ALE_INTRS); 1831 CSR_WRITE_4(sc, ALE_INTR_STATUS, 0xFFFFFFFF); 1832 CSR_WRITE_4(sc, ALE_INTR_STATUS, 0); 1833 1834 sc->ale_flags &= ~ALE_FLAG_LINK; 1835 1836 /* Switch to the current media. */ 1837 mii = &sc->sc_miibus; 1838 mii_mediachg(mii); 1839 1840 callout_schedule(&sc->sc_tick_ch, hz); 1841 1842 ifp->if_flags |= IFF_RUNNING; 1843 ifp->if_flags &= ~IFF_OACTIVE; 1844 1845 return 0; 1846 } 1847 1848 static void 1849 ale_stop(struct ifnet *ifp, int disable) 1850 { 1851 struct ale_softc *sc = ifp->if_softc; 1852 struct ale_txdesc *txd; 1853 uint32_t reg; 1854 int i; 1855 1856 callout_stop(&sc->sc_tick_ch); 1857 1858 /* 1859 * Mark the interface down and cancel the watchdog timer. 1860 */ 1861 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1862 ifp->if_timer = 0; 1863 1864 sc->ale_flags &= ~ALE_FLAG_LINK; 1865 1866 ale_stats_update(sc); 1867 1868 mii_down(&sc->sc_miibus); 1869 1870 /* Disable interrupts. */ 1871 CSR_WRITE_4(sc, ALE_INTR_MASK, 0); 1872 CSR_WRITE_4(sc, ALE_INTR_STATUS, 0xFFFFFFFF); 1873 1874 /* Disable queue processing and DMA. */ 1875 reg = CSR_READ_4(sc, ALE_TXQ_CFG); 1876 reg &= ~TXQ_CFG_ENB; 1877 CSR_WRITE_4(sc, ALE_TXQ_CFG, reg); 1878 reg = CSR_READ_4(sc, ALE_RXQ_CFG); 1879 reg &= ~RXQ_CFG_ENB; 1880 CSR_WRITE_4(sc, ALE_RXQ_CFG, reg); 1881 reg = CSR_READ_4(sc, ALE_DMA_CFG); 1882 reg &= ~(DMA_CFG_TXCMB_ENB | DMA_CFG_RXCMB_ENB); 1883 CSR_WRITE_4(sc, ALE_DMA_CFG, reg); 1884 DELAY(1000); 1885 1886 /* Stop Rx/Tx MACs. */ 1887 ale_stop_mac(sc); 1888 1889 /* Disable interrupts again? XXX */ 1890 CSR_WRITE_4(sc, ALE_INTR_STATUS, 0xFFFFFFFF); 1891 1892 /* 1893 * Free TX mbufs still in the queues. 1894 */ 1895 for (i = 0; i < ALE_TX_RING_CNT; i++) { 1896 txd = &sc->ale_cdata.ale_txdesc[i]; 1897 if (txd->tx_m != NULL) { 1898 bus_dmamap_unload(sc->sc_dmat, txd->tx_dmamap); 1899 m_freem(txd->tx_m); 1900 txd->tx_m = NULL; 1901 } 1902 } 1903 } 1904 1905 static void 1906 ale_stop_mac(struct ale_softc *sc) 1907 { 1908 uint32_t reg; 1909 int i; 1910 1911 reg = CSR_READ_4(sc, ALE_MAC_CFG); 1912 if ((reg & (MAC_CFG_TX_ENB | MAC_CFG_RX_ENB)) != 0) { 1913 reg &= ~MAC_CFG_TX_ENB | MAC_CFG_RX_ENB; 1914 CSR_WRITE_4(sc, ALE_MAC_CFG, reg); 1915 } 1916 1917 for (i = ALE_TIMEOUT; i > 0; i--) { 1918 reg = CSR_READ_4(sc, ALE_IDLE_STATUS); 1919 if (reg == 0) 1920 break; 1921 DELAY(10); 1922 } 1923 if (i == 0) 1924 printf("%s: could not disable Tx/Rx MAC(0x%08x)!\n", 1925 device_xname(sc->sc_dev), reg); 1926 } 1927 1928 static void 1929 ale_init_tx_ring(struct ale_softc *sc) 1930 { 1931 struct ale_txdesc *txd; 1932 int i; 1933 1934 sc->ale_cdata.ale_tx_prod = 0; 1935 sc->ale_cdata.ale_tx_cons = 0; 1936 sc->ale_cdata.ale_tx_cnt = 0; 1937 1938 memset(sc->ale_cdata.ale_tx_ring, 0, ALE_TX_RING_SZ); 1939 memset(sc->ale_cdata.ale_tx_cmb, 0, ALE_TX_CMB_SZ); 1940 for (i = 0; i < ALE_TX_RING_CNT; i++) { 1941 txd = &sc->ale_cdata.ale_txdesc[i]; 1942 txd->tx_m = NULL; 1943 } 1944 *sc->ale_cdata.ale_tx_cmb = 0; 1945 bus_dmamap_sync(sc->sc_dmat, sc->ale_cdata.ale_tx_cmb_map, 0, 1946 sc->ale_cdata.ale_tx_cmb_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 1947 bus_dmamap_sync(sc->sc_dmat, sc->ale_cdata.ale_tx_ring_map, 0, 1948 sc->ale_cdata.ale_tx_ring_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 1949 } 1950 1951 static void 1952 ale_init_rx_pages(struct ale_softc *sc) 1953 { 1954 struct ale_rx_page *rx_page; 1955 int i; 1956 1957 sc->ale_cdata.ale_rx_seqno = 0; 1958 sc->ale_cdata.ale_rx_curp = 0; 1959 1960 for (i = 0; i < ALE_RX_PAGES; i++) { 1961 rx_page = &sc->ale_cdata.ale_rx_page[i]; 1962 memset(rx_page->page_addr, 0, sc->ale_pagesize); 1963 memset(rx_page->cmb_addr, 0, ALE_RX_CMB_SZ); 1964 rx_page->cons = 0; 1965 *rx_page->cmb_addr = 0; 1966 bus_dmamap_sync(sc->sc_dmat, rx_page->page_map, 0, 1967 rx_page->page_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 1968 bus_dmamap_sync(sc->sc_dmat, rx_page->cmb_map, 0, 1969 rx_page->cmb_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 1970 } 1971 } 1972 1973 static void 1974 ale_rxvlan(struct ale_softc *sc) 1975 { 1976 struct ifnet *ifp = &sc->sc_ec.ec_if; 1977 uint32_t reg; 1978 1979 reg = CSR_READ_4(sc, ALE_MAC_CFG); 1980 reg &= ~MAC_CFG_VLAN_TAG_STRIP; 1981 if (ifp->if_capabilities & ETHERCAP_VLAN_HWTAGGING) 1982 reg |= MAC_CFG_VLAN_TAG_STRIP; 1983 CSR_WRITE_4(sc, ALE_MAC_CFG, reg); 1984 } 1985 1986 static void 1987 ale_rxfilter(struct ale_softc *sc) 1988 { 1989 struct ethercom *ec = &sc->sc_ec; 1990 struct ifnet *ifp = &ec->ec_if; 1991 struct ether_multi *enm; 1992 struct ether_multistep step; 1993 uint32_t crc; 1994 uint32_t mchash[2]; 1995 uint32_t rxcfg; 1996 1997 rxcfg = CSR_READ_4(sc, ALE_MAC_CFG); 1998 rxcfg &= ~(MAC_CFG_ALLMULTI | MAC_CFG_BCAST | MAC_CFG_PROMISC); 1999 ifp->if_flags &= ~IFF_ALLMULTI; 2000 2001 /* 2002 * Always accept broadcast frames. 2003 */ 2004 rxcfg |= MAC_CFG_BCAST; 2005 2006 if (ifp->if_flags & IFF_PROMISC || ec->ec_multicnt > 0) { 2007 ifp->if_flags |= IFF_ALLMULTI; 2008 if (ifp->if_flags & IFF_PROMISC) 2009 rxcfg |= MAC_CFG_PROMISC; 2010 else 2011 rxcfg |= MAC_CFG_ALLMULTI; 2012 mchash[0] = mchash[1] = 0xFFFFFFFF; 2013 } else { 2014 /* Program new filter. */ 2015 memset(mchash, 0, sizeof(mchash)); 2016 2017 ETHER_FIRST_MULTI(step, ec, enm); 2018 while (enm != NULL) { 2019 crc = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN); 2020 mchash[crc >> 31] |= 1 << ((crc >> 26) & 0x1f); 2021 ETHER_NEXT_MULTI(step, enm); 2022 } 2023 } 2024 2025 CSR_WRITE_4(sc, ALE_MAR0, mchash[0]); 2026 CSR_WRITE_4(sc, ALE_MAR1, mchash[1]); 2027 CSR_WRITE_4(sc, ALE_MAC_CFG, rxcfg); 2028 } 2029
Indexes created Tue Sep 30 11:09:46 GMT 2025