if_ale.c revision 1.14
1 /* $NetBSD: if_ale.c,v 1.14 2012/07/22 14:33:01 matt Exp $ */ 2 3 /*- 4 * Copyright (c) 2008, Pyun YongHyeon <yongari (at) FreeBSD.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice unmodified, this list of conditions, and the following 12 * disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * 29 * $FreeBSD: src/sys/dev/ale/if_ale.c,v 1.3 2008/12/03 09:01:12 yongari Exp $ 30 */ 31 32 /* Driver for Atheros AR8121/AR8113/AR8114 PCIe Ethernet. */ 33 34 #include <sys/cdefs.h> 35 __KERNEL_RCSID(0, "$NetBSD: if_ale.c,v 1.14 2012/07/22 14:33:01 matt Exp $"); 36 37 #include "vlan.h" 38 39 #include <sys/param.h> 40 #include <sys/proc.h> 41 #include <sys/endian.h> 42 #include <sys/systm.h> 43 #include <sys/types.h> 44 #include <sys/sockio.h> 45 #include <sys/mbuf.h> 46 #include <sys/queue.h> 47 #include <sys/kernel.h> 48 #include <sys/device.h> 49 #include <sys/callout.h> 50 #include <sys/socket.h> 51 52 #include <sys/bus.h> 53 54 #include <net/if.h> 55 #include <net/if_dl.h> 56 #include <net/if_llc.h> 57 #include <net/if_media.h> 58 #include <net/if_ether.h> 59 60 #ifdef INET 61 #include <netinet/in.h> 62 #include <netinet/in_systm.h> 63 #include <netinet/in_var.h> 64 #include <netinet/ip.h> 65 #endif 66 67 #include <net/if_types.h> 68 #include <net/if_vlanvar.h> 69 70 #include <net/bpf.h> 71 72 #include <sys/rnd.h> 73 74 #include <dev/mii/mii.h> 75 #include <dev/mii/miivar.h> 76 77 #include <dev/pci/pcireg.h> 78 #include <dev/pci/pcivar.h> 79 #include <dev/pci/pcidevs.h> 80 81 #include <dev/pci/if_alereg.h> 82 83 static int ale_match(device_t, cfdata_t, void *); 84 static void ale_attach(device_t, device_t, void *); 85 static int ale_detach(device_t, int); 86 87 static int ale_miibus_readreg(device_t, int, int); 88 static void ale_miibus_writereg(device_t, int, int, int); 89 static void ale_miibus_statchg(struct ifnet *); 90 91 static int ale_init(struct ifnet *); 92 static void ale_start(struct ifnet *); 93 static int ale_ioctl(struct ifnet *, u_long, void *); 94 static void ale_watchdog(struct ifnet *); 95 static int ale_mediachange(struct ifnet *); 96 static void ale_mediastatus(struct ifnet *, struct ifmediareq *); 97 98 static int ale_intr(void *); 99 static int ale_rxeof(struct ale_softc *sc); 100 static void ale_rx_update_page(struct ale_softc *, struct ale_rx_page **, 101 uint32_t, uint32_t *); 102 static void ale_rxcsum(struct ale_softc *, struct mbuf *, uint32_t); 103 static void ale_txeof(struct ale_softc *); 104 105 static int ale_dma_alloc(struct ale_softc *); 106 static void ale_dma_free(struct ale_softc *); 107 static int ale_encap(struct ale_softc *, struct mbuf **); 108 static void ale_init_rx_pages(struct ale_softc *); 109 static void ale_init_tx_ring(struct ale_softc *); 110 111 static void ale_stop(struct ifnet *, int); 112 static void ale_tick(void *); 113 static void ale_get_macaddr(struct ale_softc *); 114 static void ale_mac_config(struct ale_softc *); 115 static void ale_phy_reset(struct ale_softc *); 116 static void ale_reset(struct ale_softc *); 117 static void ale_rxfilter(struct ale_softc *); 118 static void ale_rxvlan(struct ale_softc *); 119 static void ale_stats_clear(struct ale_softc *); 120 static void ale_stats_update(struct ale_softc *); 121 static void ale_stop_mac(struct ale_softc *); 122 123 CFATTACH_DECL_NEW(ale, sizeof(struct ale_softc), 124 ale_match, ale_attach, ale_detach, NULL); 125 126 int aledebug = 0; 127 #define DPRINTF(x) do { if (aledebug) printf x; } while (0) 128 129 #define ETHER_ALIGN 2 130 #define ALE_CSUM_FEATURES (M_CSUM_TCPv4 | M_CSUM_UDPv4) 131 132 static int 133 ale_miibus_readreg(device_t dev, int phy, int reg) 134 { 135 struct ale_softc *sc = device_private(dev); 136 uint32_t v; 137 int i; 138 139 if (phy != sc->ale_phyaddr) 140 return 0; 141 142 if (sc->ale_flags & ALE_FLAG_FASTETHER) { 143 switch (reg) { 144 case MII_100T2CR: 145 case MII_100T2SR: 146 case MII_EXTSR: 147 return 0; 148 default: 149 break; 150 } 151 } 152 153 CSR_WRITE_4(sc, ALE_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ | 154 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); 155 for (i = ALE_PHY_TIMEOUT; i > 0; i--) { 156 DELAY(5); 157 v = CSR_READ_4(sc, ALE_MDIO); 158 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) 159 break; 160 } 161 162 if (i == 0) { 163 printf("%s: phy read timeout: phy %d, reg %d\n", 164 device_xname(sc->sc_dev), phy, reg); 165 return 0; 166 } 167 168 return (v & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT; 169 } 170 171 static void 172 ale_miibus_writereg(device_t dev, int phy, int reg, int val) 173 { 174 struct ale_softc *sc = device_private(dev); 175 uint32_t v; 176 int i; 177 178 if (phy != sc->ale_phyaddr) 179 return; 180 181 if (sc->ale_flags & ALE_FLAG_FASTETHER) { 182 switch (reg) { 183 case MII_100T2CR: 184 case MII_100T2SR: 185 case MII_EXTSR: 186 return; 187 default: 188 break; 189 } 190 } 191 192 CSR_WRITE_4(sc, ALE_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE | 193 (val & MDIO_DATA_MASK) << MDIO_DATA_SHIFT | 194 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); 195 for (i = ALE_PHY_TIMEOUT; i > 0; i--) { 196 DELAY(5); 197 v = CSR_READ_4(sc, ALE_MDIO); 198 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) 199 break; 200 } 201 202 if (i == 0) 203 printf("%s: phy write timeout: phy %d, reg %d\n", 204 device_xname(sc->sc_dev), phy, reg); 205 } 206 207 static void 208 ale_miibus_statchg(struct ifnet *ifp) 209 { 210 struct ale_softc *sc = ifp->if_softc; 211 struct mii_data *mii = &sc->sc_miibus; 212 uint32_t reg; 213 214 if ((ifp->if_flags & IFF_RUNNING) == 0) 215 return; 216 217 sc->ale_flags &= ~ALE_FLAG_LINK; 218 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 219 (IFM_ACTIVE | IFM_AVALID)) { 220 switch (IFM_SUBTYPE(mii->mii_media_active)) { 221 case IFM_10_T: 222 case IFM_100_TX: 223 sc->ale_flags |= ALE_FLAG_LINK; 224 break; 225 226 case IFM_1000_T: 227 if ((sc->ale_flags & ALE_FLAG_FASTETHER) == 0) 228 sc->ale_flags |= ALE_FLAG_LINK; 229 break; 230 231 default: 232 break; 233 } 234 } 235 236 /* Stop Rx/Tx MACs. */ 237 ale_stop_mac(sc); 238 239 /* Program MACs with resolved speed/duplex/flow-control. */ 240 if ((sc->ale_flags & ALE_FLAG_LINK) != 0) { 241 ale_mac_config(sc); 242 /* Reenable Tx/Rx MACs. */ 243 reg = CSR_READ_4(sc, ALE_MAC_CFG); 244 reg |= MAC_CFG_TX_ENB | MAC_CFG_RX_ENB; 245 CSR_WRITE_4(sc, ALE_MAC_CFG, reg); 246 } 247 } 248 249 void 250 ale_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 251 { 252 struct ale_softc *sc = ifp->if_softc; 253 struct mii_data *mii = &sc->sc_miibus; 254 255 mii_pollstat(mii); 256 ifmr->ifm_status = mii->mii_media_status; 257 ifmr->ifm_active = mii->mii_media_active; 258 } 259 260 int 261 ale_mediachange(struct ifnet *ifp) 262 { 263 struct ale_softc *sc = ifp->if_softc; 264 struct mii_data *mii = &sc->sc_miibus; 265 int error; 266 267 if (mii->mii_instance != 0) { 268 struct mii_softc *miisc; 269 270 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 271 mii_phy_reset(miisc); 272 } 273 error = mii_mediachg(mii); 274 275 return error; 276 } 277 278 int 279 ale_match(device_t dev, cfdata_t match, void *aux) 280 { 281 struct pci_attach_args *pa = aux; 282 283 return (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_ATTANSIC && 284 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_ATTANSIC_ETHERNET_L1E); 285 } 286 287 void 288 ale_get_macaddr(struct ale_softc *sc) 289 { 290 uint32_t ea[2], reg; 291 int i, vpdc; 292 293 reg = CSR_READ_4(sc, ALE_SPI_CTRL); 294 if ((reg & SPI_VPD_ENB) != 0) { 295 reg &= ~SPI_VPD_ENB; 296 CSR_WRITE_4(sc, ALE_SPI_CTRL, reg); 297 } 298 299 if (pci_get_capability(sc->sc_pct, sc->sc_pcitag, PCI_CAP_VPD, 300 &vpdc, NULL)) { 301 /* 302 * PCI VPD capability found, let TWSI reload EEPROM. 303 * This will set ethernet address of controller. 304 */ 305 CSR_WRITE_4(sc, ALE_TWSI_CTRL, CSR_READ_4(sc, ALE_TWSI_CTRL) | 306 TWSI_CTRL_SW_LD_START); 307 for (i = 100; i > 0; i--) { 308 DELAY(1000); 309 reg = CSR_READ_4(sc, ALE_TWSI_CTRL); 310 if ((reg & TWSI_CTRL_SW_LD_START) == 0) 311 break; 312 } 313 if (i == 0) 314 printf("%s: reloading EEPROM timeout!\n", 315 device_xname(sc->sc_dev)); 316 } else { 317 if (aledebug) 318 printf("%s: PCI VPD capability not found!\n", 319 device_xname(sc->sc_dev)); 320 } 321 322 ea[0] = CSR_READ_4(sc, ALE_PAR0); 323 ea[1] = CSR_READ_4(sc, ALE_PAR1); 324 sc->ale_eaddr[0] = (ea[1] >> 8) & 0xFF; 325 sc->ale_eaddr[1] = (ea[1] >> 0) & 0xFF; 326 sc->ale_eaddr[2] = (ea[0] >> 24) & 0xFF; 327 sc->ale_eaddr[3] = (ea[0] >> 16) & 0xFF; 328 sc->ale_eaddr[4] = (ea[0] >> 8) & 0xFF; 329 sc->ale_eaddr[5] = (ea[0] >> 0) & 0xFF; 330 } 331 332 void 333 ale_phy_reset(struct ale_softc *sc) 334 { 335 /* Reset magic from Linux. */ 336 CSR_WRITE_2(sc, ALE_GPHY_CTRL, 337 GPHY_CTRL_HIB_EN | GPHY_CTRL_HIB_PULSE | GPHY_CTRL_SEL_ANA_RESET | 338 GPHY_CTRL_PHY_PLL_ON); 339 DELAY(1000); 340 CSR_WRITE_2(sc, ALE_GPHY_CTRL, 341 GPHY_CTRL_EXT_RESET | GPHY_CTRL_HIB_EN | GPHY_CTRL_HIB_PULSE | 342 GPHY_CTRL_SEL_ANA_RESET | GPHY_CTRL_PHY_PLL_ON); 343 DELAY(1000); 344 345 #define ATPHY_DBG_ADDR 0x1D 346 #define ATPHY_DBG_DATA 0x1E 347 348 /* Enable hibernation mode. */ 349 ale_miibus_writereg(sc->sc_dev, sc->ale_phyaddr, 350 ATPHY_DBG_ADDR, 0x0B); 351 ale_miibus_writereg(sc->sc_dev, sc->ale_phyaddr, 352 ATPHY_DBG_DATA, 0xBC00); 353 /* Set Class A/B for all modes. */ 354 ale_miibus_writereg(sc->sc_dev, sc->ale_phyaddr, 355 ATPHY_DBG_ADDR, 0x00); 356 ale_miibus_writereg(sc->sc_dev, sc->ale_phyaddr, 357 ATPHY_DBG_DATA, 0x02EF); 358 /* Enable 10BT power saving. */ 359 ale_miibus_writereg(sc->sc_dev, sc->ale_phyaddr, 360 ATPHY_DBG_ADDR, 0x12); 361 ale_miibus_writereg(sc->sc_dev, sc->ale_phyaddr, 362 ATPHY_DBG_DATA, 0x4C04); 363 /* Adjust 1000T power. */ 364 ale_miibus_writereg(sc->sc_dev, sc->ale_phyaddr, 365 ATPHY_DBG_ADDR, 0x04); 366 ale_miibus_writereg(sc->sc_dev, sc->ale_phyaddr, 367 ATPHY_DBG_DATA, 0x8BBB); 368 /* 10BT center tap voltage. */ 369 ale_miibus_writereg(sc->sc_dev, sc->ale_phyaddr, 370 ATPHY_DBG_ADDR, 0x05); 371 ale_miibus_writereg(sc->sc_dev, sc->ale_phyaddr, 372 ATPHY_DBG_DATA, 0x2C46); 373 374 #undef ATPHY_DBG_ADDR 375 #undef ATPHY_DBG_DATA 376 DELAY(1000); 377 } 378 379 void 380 ale_attach(device_t parent, device_t self, void *aux) 381 { 382 struct ale_softc *sc = device_private(self); 383 struct pci_attach_args *pa = aux; 384 pci_chipset_tag_t pc = pa->pa_pc; 385 pci_intr_handle_t ih; 386 const char *intrstr; 387 struct ifnet *ifp; 388 pcireg_t memtype; 389 int mii_flags, error = 0; 390 uint32_t rxf_len, txf_len; 391 const char *chipname; 392 393 aprint_naive("\n"); 394 aprint_normal(": Attansic/Atheros L1E Ethernet\n"); 395 396 sc->sc_dev = self; 397 sc->sc_dmat = pa->pa_dmat; 398 sc->sc_pct = pa->pa_pc; 399 sc->sc_pcitag = pa->pa_tag; 400 401 /* 402 * Allocate IO memory 403 */ 404 memtype = pci_mapreg_type(sc->sc_pct, sc->sc_pcitag, ALE_PCIR_BAR); 405 switch (memtype) { 406 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 407 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT_1M: 408 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 409 break; 410 default: 411 aprint_error_dev(self, "invalid base address register\n"); 412 break; 413 } 414 415 if (pci_mapreg_map(pa, ALE_PCIR_BAR, memtype, 0, &sc->sc_mem_bt, 416 &sc->sc_mem_bh, NULL, &sc->sc_mem_size)) { 417 aprint_error_dev(self, "could not map mem space\n"); 418 return; 419 } 420 421 if (pci_intr_map(pa, &ih) != 0) { 422 aprint_error_dev(self, "could not map interrupt\n"); 423 goto fail; 424 } 425 426 /* 427 * Allocate IRQ 428 */ 429 intrstr = pci_intr_string(sc->sc_pct, ih); 430 sc->sc_irq_handle = pci_intr_establish(pc, ih, IPL_NET, ale_intr, sc); 431 if (sc->sc_irq_handle == NULL) { 432 aprint_error_dev(self, "could not establish interrupt"); 433 if (intrstr != NULL) 434 aprint_error(" at %s", intrstr); 435 aprint_error("\n"); 436 goto fail; 437 } 438 439 /* Set PHY address. */ 440 sc->ale_phyaddr = ALE_PHY_ADDR; 441 442 /* Reset PHY. */ 443 ale_phy_reset(sc); 444 445 /* Reset the ethernet controller. */ 446 ale_reset(sc); 447 448 /* Get PCI and chip id/revision. */ 449 sc->ale_rev = PCI_REVISION(pa->pa_class); 450 if (sc->ale_rev >= 0xF0) { 451 /* L2E Rev. B. AR8114 */ 452 sc->ale_flags |= ALE_FLAG_FASTETHER; 453 chipname = "AR8114 (L2E RevB)"; 454 } else { 455 if ((CSR_READ_4(sc, ALE_PHY_STATUS) & PHY_STATUS_100M) != 0) { 456 /* L1E AR8121 */ 457 sc->ale_flags |= ALE_FLAG_JUMBO; 458 chipname = "AR8121 (L1E)"; 459 } else { 460 /* L2E Rev. A. AR8113 */ 461 sc->ale_flags |= ALE_FLAG_FASTETHER; 462 chipname = "AR8113 (L2E RevA)"; 463 } 464 } 465 aprint_normal_dev(self, "%s, %s\n", chipname, intrstr); 466 467 /* 468 * All known controllers seems to require 4 bytes alignment 469 * of Tx buffers to make Tx checksum offload with custom 470 * checksum generation method work. 471 */ 472 sc->ale_flags |= ALE_FLAG_TXCSUM_BUG; 473 474 /* 475 * All known controllers seems to have issues on Rx checksum 476 * offload for fragmented IP datagrams. 477 */ 478 sc->ale_flags |= ALE_FLAG_RXCSUM_BUG; 479 480 /* 481 * Don't use Tx CMB. It is known to cause RRS update failure 482 * under certain circumstances. Typical phenomenon of the 483 * issue would be unexpected sequence number encountered in 484 * Rx handler. 485 */ 486 sc->ale_flags |= ALE_FLAG_TXCMB_BUG; 487 sc->ale_chip_rev = CSR_READ_4(sc, ALE_MASTER_CFG) >> 488 MASTER_CHIP_REV_SHIFT; 489 aprint_debug_dev(self, "PCI device revision : 0x%04x\n", sc->ale_rev); 490 aprint_debug_dev(self, "Chip id/revision : 0x%04x\n", sc->ale_chip_rev); 491 492 /* 493 * Uninitialized hardware returns an invalid chip id/revision 494 * as well as 0xFFFFFFFF for Tx/Rx fifo length. 495 */ 496 txf_len = CSR_READ_4(sc, ALE_SRAM_TX_FIFO_LEN); 497 rxf_len = CSR_READ_4(sc, ALE_SRAM_RX_FIFO_LEN); 498 if (sc->ale_chip_rev == 0xFFFF || txf_len == 0xFFFFFFFF || 499 rxf_len == 0xFFFFFFF) { 500 aprint_error_dev(self, "chip revision : 0x%04x, %u Tx FIFO " 501 "%u Rx FIFO -- not initialized?\n", 502 sc->ale_chip_rev, txf_len, rxf_len); 503 goto fail; 504 } 505 506 if (aledebug) { 507 printf("%s: %u Tx FIFO, %u Rx FIFO\n", device_xname(sc->sc_dev), 508 txf_len, rxf_len); 509 } 510 511 /* Set max allowable DMA size. */ 512 sc->ale_dma_rd_burst = DMA_CFG_RD_BURST_128; 513 sc->ale_dma_wr_burst = DMA_CFG_WR_BURST_128; 514 515 callout_init(&sc->sc_tick_ch, 0); 516 callout_setfunc(&sc->sc_tick_ch, ale_tick, sc); 517 518 error = ale_dma_alloc(sc); 519 if (error) 520 goto fail; 521 522 /* Load station address. */ 523 ale_get_macaddr(sc); 524 525 aprint_normal_dev(self, "Ethernet address %s\n", 526 ether_sprintf(sc->ale_eaddr)); 527 528 ifp = &sc->sc_ec.ec_if; 529 ifp->if_softc = sc; 530 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 531 ifp->if_init = ale_init; 532 ifp->if_ioctl = ale_ioctl; 533 ifp->if_start = ale_start; 534 ifp->if_stop = ale_stop; 535 ifp->if_watchdog = ale_watchdog; 536 IFQ_SET_MAXLEN(&ifp->if_snd, ALE_TX_RING_CNT - 1); 537 IFQ_SET_READY(&ifp->if_snd); 538 strlcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 539 540 sc->sc_ec.ec_capabilities = ETHERCAP_VLAN_MTU; 541 542 #ifdef ALE_CHECKSUM 543 ifp->if_capabilities |= IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 544 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 545 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_TCPv4_Rx; 546 #endif 547 548 #if NVLAN > 0 549 sc->sc_ec.ec_capabilities |= ETHERCAP_VLAN_HWTAGGING; 550 #endif 551 552 /* Set up MII bus. */ 553 sc->sc_miibus.mii_ifp = ifp; 554 sc->sc_miibus.mii_readreg = ale_miibus_readreg; 555 sc->sc_miibus.mii_writereg = ale_miibus_writereg; 556 sc->sc_miibus.mii_statchg = ale_miibus_statchg; 557 558 sc->sc_ec.ec_mii = &sc->sc_miibus; 559 ifmedia_init(&sc->sc_miibus.mii_media, 0, ale_mediachange, 560 ale_mediastatus); 561 mii_flags = 0; 562 if ((sc->ale_flags & ALE_FLAG_JUMBO) != 0) 563 mii_flags |= MIIF_DOPAUSE; 564 mii_attach(self, &sc->sc_miibus, 0xffffffff, MII_PHY_ANY, 565 MII_OFFSET_ANY, mii_flags); 566 567 if (LIST_FIRST(&sc->sc_miibus.mii_phys) == NULL) { 568 aprint_error_dev(self, "no PHY found!\n"); 569 ifmedia_add(&sc->sc_miibus.mii_media, IFM_ETHER | IFM_MANUAL, 570 0, NULL); 571 ifmedia_set(&sc->sc_miibus.mii_media, IFM_ETHER | IFM_MANUAL); 572 } else 573 ifmedia_set(&sc->sc_miibus.mii_media, IFM_ETHER | IFM_AUTO); 574 575 if_attach(ifp); 576 ether_ifattach(ifp, sc->ale_eaddr); 577 578 if (pmf_device_register(self, NULL, NULL)) 579 pmf_class_network_register(self, ifp); 580 else 581 aprint_error_dev(self, "couldn't establish power handler\n"); 582 583 return; 584 fail: 585 ale_dma_free(sc); 586 if (sc->sc_irq_handle != NULL) { 587 pci_intr_disestablish(pc, sc->sc_irq_handle); 588 sc->sc_irq_handle = NULL; 589 } 590 if (sc->sc_mem_size) { 591 bus_space_unmap(sc->sc_mem_bt, sc->sc_mem_bh, sc->sc_mem_size); 592 sc->sc_mem_size = 0; 593 } 594 } 595 596 static int 597 ale_detach(device_t self, int flags) 598 { 599 struct ale_softc *sc = device_private(self); 600 struct ifnet *ifp = &sc->sc_ec.ec_if; 601 int s; 602 603 pmf_device_deregister(self); 604 s = splnet(); 605 ale_stop(ifp, 0); 606 splx(s); 607 608 mii_detach(&sc->sc_miibus, MII_PHY_ANY, MII_OFFSET_ANY); 609 610 /* Delete all remaining media. */ 611 ifmedia_delete_instance(&sc->sc_miibus.mii_media, IFM_INST_ANY); 612 613 ether_ifdetach(ifp); 614 if_detach(ifp); 615 ale_dma_free(sc); 616 617 if (sc->sc_irq_handle != NULL) { 618 pci_intr_disestablish(sc->sc_pct, sc->sc_irq_handle); 619 sc->sc_irq_handle = NULL; 620 } 621 if (sc->sc_mem_size) { 622 bus_space_unmap(sc->sc_mem_bt, sc->sc_mem_bh, sc->sc_mem_size); 623 sc->sc_mem_size = 0; 624 } 625 626 return 0; 627 } 628 629 630 static int 631 ale_dma_alloc(struct ale_softc *sc) 632 { 633 struct ale_txdesc *txd; 634 int nsegs, error, guard_size, i; 635 636 if ((sc->ale_flags & ALE_FLAG_JUMBO) != 0) 637 guard_size = ALE_JUMBO_FRAMELEN; 638 else 639 guard_size = ALE_MAX_FRAMELEN; 640 sc->ale_pagesize = roundup(guard_size + ALE_RX_PAGE_SZ, 641 ALE_RX_PAGE_ALIGN); 642 643 /* 644 * Create DMA stuffs for TX ring 645 */ 646 error = bus_dmamap_create(sc->sc_dmat, ALE_TX_RING_SZ, 1, 647 ALE_TX_RING_SZ, 0, BUS_DMA_NOWAIT, &sc->ale_cdata.ale_tx_ring_map); 648 if (error) { 649 sc->ale_cdata.ale_tx_ring_map = NULL; 650 return ENOBUFS; 651 } 652 653 /* Allocate DMA'able memory for TX ring */ 654 error = bus_dmamem_alloc(sc->sc_dmat, ALE_TX_RING_SZ, 655 0, 0, &sc->ale_cdata.ale_tx_ring_seg, 1, 656 &nsegs, BUS_DMA_WAITOK); 657 if (error) { 658 printf("%s: could not allocate DMA'able memory for Tx ring, " 659 "error = %i\n", device_xname(sc->sc_dev), error); 660 return error; 661 } 662 663 error = bus_dmamem_map(sc->sc_dmat, &sc->ale_cdata.ale_tx_ring_seg, 664 nsegs, ALE_TX_RING_SZ, (void **)&sc->ale_cdata.ale_tx_ring, 665 BUS_DMA_NOWAIT); 666 if (error) 667 return ENOBUFS; 668 669 memset(sc->ale_cdata.ale_tx_ring, 0, ALE_TX_RING_SZ); 670 671 /* Load the DMA map for Tx ring. */ 672 error = bus_dmamap_load(sc->sc_dmat, sc->ale_cdata.ale_tx_ring_map, 673 sc->ale_cdata.ale_tx_ring, ALE_TX_RING_SZ, NULL, BUS_DMA_WAITOK); 674 if (error) { 675 printf("%s: could not load DMA'able memory for Tx ring.\n", 676 device_xname(sc->sc_dev)); 677 bus_dmamem_free(sc->sc_dmat, 678 &sc->ale_cdata.ale_tx_ring_seg, 1); 679 return error; 680 } 681 sc->ale_cdata.ale_tx_ring_paddr = 682 sc->ale_cdata.ale_tx_ring_map->dm_segs[0].ds_addr; 683 684 for (i = 0; i < ALE_RX_PAGES; i++) { 685 /* 686 * Create DMA stuffs for RX pages 687 */ 688 error = bus_dmamap_create(sc->sc_dmat, sc->ale_pagesize, 1, 689 sc->ale_pagesize, 0, BUS_DMA_NOWAIT, 690 &sc->ale_cdata.ale_rx_page[i].page_map); 691 if (error) { 692 sc->ale_cdata.ale_rx_page[i].page_map = NULL; 693 return ENOBUFS; 694 } 695 696 /* Allocate DMA'able memory for RX pages */ 697 error = bus_dmamem_alloc(sc->sc_dmat, sc->ale_pagesize, 698 ETHER_ALIGN, 0, &sc->ale_cdata.ale_rx_page[i].page_seg, 699 1, &nsegs, BUS_DMA_WAITOK); 700 if (error) { 701 printf("%s: could not allocate DMA'able memory for " 702 "Rx ring.\n", device_xname(sc->sc_dev)); 703 return error; 704 } 705 error = bus_dmamem_map(sc->sc_dmat, 706 &sc->ale_cdata.ale_rx_page[i].page_seg, nsegs, 707 sc->ale_pagesize, 708 (void **)&sc->ale_cdata.ale_rx_page[i].page_addr, 709 BUS_DMA_NOWAIT); 710 if (error) 711 return ENOBUFS; 712 713 memset(sc->ale_cdata.ale_rx_page[i].page_addr, 0, 714 sc->ale_pagesize); 715 716 /* Load the DMA map for Rx pages. */ 717 error = bus_dmamap_load(sc->sc_dmat, 718 sc->ale_cdata.ale_rx_page[i].page_map, 719 sc->ale_cdata.ale_rx_page[i].page_addr, 720 sc->ale_pagesize, NULL, BUS_DMA_WAITOK); 721 if (error) { 722 printf("%s: could not load DMA'able memory for " 723 "Rx pages.\n", device_xname(sc->sc_dev)); 724 bus_dmamem_free(sc->sc_dmat, 725 &sc->ale_cdata.ale_rx_page[i].page_seg, 1); 726 return error; 727 } 728 sc->ale_cdata.ale_rx_page[i].page_paddr = 729 sc->ale_cdata.ale_rx_page[i].page_map->dm_segs[0].ds_addr; 730 } 731 732 /* 733 * Create DMA stuffs for Tx CMB. 734 */ 735 error = bus_dmamap_create(sc->sc_dmat, ALE_TX_CMB_SZ, 1, 736 ALE_TX_CMB_SZ, 0, BUS_DMA_NOWAIT, &sc->ale_cdata.ale_tx_cmb_map); 737 if (error) { 738 sc->ale_cdata.ale_tx_cmb_map = NULL; 739 return ENOBUFS; 740 } 741 742 /* Allocate DMA'able memory for Tx CMB. */ 743 error = bus_dmamem_alloc(sc->sc_dmat, ALE_TX_CMB_SZ, ETHER_ALIGN, 0, 744 &sc->ale_cdata.ale_tx_cmb_seg, 1, &nsegs, BUS_DMA_WAITOK); 745 746 if (error) { 747 printf("%s: could not allocate DMA'able memory for Tx CMB.\n", 748 device_xname(sc->sc_dev)); 749 return error; 750 } 751 752 error = bus_dmamem_map(sc->sc_dmat, &sc->ale_cdata.ale_tx_cmb_seg, 753 nsegs, ALE_TX_CMB_SZ, (void **)&sc->ale_cdata.ale_tx_cmb, 754 BUS_DMA_NOWAIT); 755 if (error) 756 return ENOBUFS; 757 758 memset(sc->ale_cdata.ale_tx_cmb, 0, ALE_TX_CMB_SZ); 759 760 /* Load the DMA map for Tx CMB. */ 761 error = bus_dmamap_load(sc->sc_dmat, sc->ale_cdata.ale_tx_cmb_map, 762 sc->ale_cdata.ale_tx_cmb, ALE_TX_CMB_SZ, NULL, BUS_DMA_WAITOK); 763 if (error) { 764 printf("%s: could not load DMA'able memory for Tx CMB.\n", 765 device_xname(sc->sc_dev)); 766 bus_dmamem_free(sc->sc_dmat, 767 &sc->ale_cdata.ale_tx_cmb_seg, 1); 768 return error; 769 } 770 771 sc->ale_cdata.ale_tx_cmb_paddr = 772 sc->ale_cdata.ale_tx_cmb_map->dm_segs[0].ds_addr; 773 774 for (i = 0; i < ALE_RX_PAGES; i++) { 775 /* 776 * Create DMA stuffs for Rx CMB. 777 */ 778 error = bus_dmamap_create(sc->sc_dmat, ALE_RX_CMB_SZ, 1, 779 ALE_RX_CMB_SZ, 0, BUS_DMA_NOWAIT, 780 &sc->ale_cdata.ale_rx_page[i].cmb_map); 781 if (error) { 782 sc->ale_cdata.ale_rx_page[i].cmb_map = NULL; 783 return ENOBUFS; 784 } 785 786 /* Allocate DMA'able memory for Rx CMB */ 787 error = bus_dmamem_alloc(sc->sc_dmat, ALE_RX_CMB_SZ, 788 ETHER_ALIGN, 0, &sc->ale_cdata.ale_rx_page[i].cmb_seg, 1, 789 &nsegs, BUS_DMA_WAITOK); 790 if (error) { 791 printf("%s: could not allocate DMA'able memory for " 792 "Rx CMB\n", device_xname(sc->sc_dev)); 793 return error; 794 } 795 error = bus_dmamem_map(sc->sc_dmat, 796 &sc->ale_cdata.ale_rx_page[i].cmb_seg, nsegs, 797 ALE_RX_CMB_SZ, 798 (void **)&sc->ale_cdata.ale_rx_page[i].cmb_addr, 799 BUS_DMA_NOWAIT); 800 if (error) 801 return ENOBUFS; 802 803 memset(sc->ale_cdata.ale_rx_page[i].cmb_addr, 0, ALE_RX_CMB_SZ); 804 805 /* Load the DMA map for Rx CMB */ 806 error = bus_dmamap_load(sc->sc_dmat, 807 sc->ale_cdata.ale_rx_page[i].cmb_map, 808 sc->ale_cdata.ale_rx_page[i].cmb_addr, 809 ALE_RX_CMB_SZ, NULL, BUS_DMA_WAITOK); 810 if (error) { 811 printf("%s: could not load DMA'able memory for Rx CMB" 812 "\n", device_xname(sc->sc_dev)); 813 bus_dmamem_free(sc->sc_dmat, 814 &sc->ale_cdata.ale_rx_page[i].cmb_seg, 1); 815 return error; 816 } 817 sc->ale_cdata.ale_rx_page[i].cmb_paddr = 818 sc->ale_cdata.ale_rx_page[i].cmb_map->dm_segs[0].ds_addr; 819 } 820 821 822 /* Create DMA maps for Tx buffers. */ 823 for (i = 0; i < ALE_TX_RING_CNT; i++) { 824 txd = &sc->ale_cdata.ale_txdesc[i]; 825 txd->tx_m = NULL; 826 txd->tx_dmamap = NULL; 827 error = bus_dmamap_create(sc->sc_dmat, ALE_TSO_MAXSIZE, 828 ALE_MAXTXSEGS, ALE_TSO_MAXSEGSIZE, 0, BUS_DMA_NOWAIT, 829 &txd->tx_dmamap); 830 if (error) { 831 txd->tx_dmamap = NULL; 832 printf("%s: could not create Tx dmamap.\n", 833 device_xname(sc->sc_dev)); 834 return error; 835 } 836 } 837 838 return 0; 839 } 840 841 static void 842 ale_dma_free(struct ale_softc *sc) 843 { 844 struct ale_txdesc *txd; 845 int i; 846 847 /* Tx buffers. */ 848 for (i = 0; i < ALE_TX_RING_CNT; i++) { 849 txd = &sc->ale_cdata.ale_txdesc[i]; 850 if (txd->tx_dmamap != NULL) { 851 bus_dmamap_destroy(sc->sc_dmat, txd->tx_dmamap); 852 txd->tx_dmamap = NULL; 853 } 854 } 855 856 /* Tx descriptor ring. */ 857 if (sc->ale_cdata.ale_tx_ring_map != NULL) 858 bus_dmamap_unload(sc->sc_dmat, sc->ale_cdata.ale_tx_ring_map); 859 if (sc->ale_cdata.ale_tx_ring_map != NULL && 860 sc->ale_cdata.ale_tx_ring != NULL) 861 bus_dmamem_free(sc->sc_dmat, 862 &sc->ale_cdata.ale_tx_ring_seg, 1); 863 sc->ale_cdata.ale_tx_ring = NULL; 864 sc->ale_cdata.ale_tx_ring_map = NULL; 865 866 /* Rx page block. */ 867 for (i = 0; i < ALE_RX_PAGES; i++) { 868 if (sc->ale_cdata.ale_rx_page[i].page_map != NULL) 869 bus_dmamap_unload(sc->sc_dmat, 870 sc->ale_cdata.ale_rx_page[i].page_map); 871 if (sc->ale_cdata.ale_rx_page[i].page_map != NULL && 872 sc->ale_cdata.ale_rx_page[i].page_addr != NULL) 873 bus_dmamem_free(sc->sc_dmat, 874 &sc->ale_cdata.ale_rx_page[i].page_seg, 1); 875 sc->ale_cdata.ale_rx_page[i].page_addr = NULL; 876 sc->ale_cdata.ale_rx_page[i].page_map = NULL; 877 } 878 879 /* Rx CMB. */ 880 for (i = 0; i < ALE_RX_PAGES; i++) { 881 if (sc->ale_cdata.ale_rx_page[i].cmb_map != NULL) 882 bus_dmamap_unload(sc->sc_dmat, 883 sc->ale_cdata.ale_rx_page[i].cmb_map); 884 if (sc->ale_cdata.ale_rx_page[i].cmb_map != NULL && 885 sc->ale_cdata.ale_rx_page[i].cmb_addr != NULL) 886 bus_dmamem_free(sc->sc_dmat, 887 &sc->ale_cdata.ale_rx_page[i].cmb_seg, 1); 888 sc->ale_cdata.ale_rx_page[i].cmb_addr = NULL; 889 sc->ale_cdata.ale_rx_page[i].cmb_map = NULL; 890 } 891 892 /* Tx CMB. */ 893 if (sc->ale_cdata.ale_tx_cmb_map != NULL) 894 bus_dmamap_unload(sc->sc_dmat, sc->ale_cdata.ale_tx_cmb_map); 895 if (sc->ale_cdata.ale_tx_cmb_map != NULL && 896 sc->ale_cdata.ale_tx_cmb != NULL) 897 bus_dmamem_free(sc->sc_dmat, 898 &sc->ale_cdata.ale_tx_cmb_seg, 1); 899 sc->ale_cdata.ale_tx_cmb = NULL; 900 sc->ale_cdata.ale_tx_cmb_map = NULL; 901 902 } 903 904 static int 905 ale_encap(struct ale_softc *sc, struct mbuf **m_head) 906 { 907 struct ale_txdesc *txd, *txd_last; 908 struct tx_desc *desc; 909 struct mbuf *m; 910 bus_dmamap_t map; 911 uint32_t cflags, poff, vtag; 912 int error, i, nsegs, prod; 913 #if NVLAN > 0 914 struct m_tag *mtag; 915 #endif 916 917 m = *m_head; 918 cflags = vtag = 0; 919 poff = 0; 920 921 prod = sc->ale_cdata.ale_tx_prod; 922 txd = &sc->ale_cdata.ale_txdesc[prod]; 923 txd_last = txd; 924 map = txd->tx_dmamap; 925 926 error = bus_dmamap_load_mbuf(sc->sc_dmat, map, *m_head, BUS_DMA_NOWAIT); 927 if (error == EFBIG) { 928 error = 0; 929 930 *m_head = m_pullup(*m_head, MHLEN); 931 if (*m_head == NULL) { 932 printf("%s: can't defrag TX mbuf\n", 933 device_xname(sc->sc_dev)); 934 return ENOBUFS; 935 } 936 937 error = bus_dmamap_load_mbuf(sc->sc_dmat, map, *m_head, 938 BUS_DMA_NOWAIT); 939 940 if (error != 0) { 941 printf("%s: could not load defragged TX mbuf\n", 942 device_xname(sc->sc_dev)); 943 m_freem(*m_head); 944 *m_head = NULL; 945 return error; 946 } 947 } else if (error) { 948 printf("%s: could not load TX mbuf\n", device_xname(sc->sc_dev)); 949 return error; 950 } 951 952 nsegs = map->dm_nsegs; 953 954 if (nsegs == 0) { 955 m_freem(*m_head); 956 *m_head = NULL; 957 return EIO; 958 } 959 960 /* Check descriptor overrun. */ 961 if (sc->ale_cdata.ale_tx_cnt + nsegs >= ALE_TX_RING_CNT - 2) { 962 bus_dmamap_unload(sc->sc_dmat, map); 963 return ENOBUFS; 964 } 965 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 966 BUS_DMASYNC_PREWRITE); 967 968 m = *m_head; 969 /* Configure Tx checksum offload. */ 970 if ((m->m_pkthdr.csum_flags & ALE_CSUM_FEATURES) != 0) { 971 /* 972 * AR81xx supports Tx custom checksum offload feature 973 * that offloads single 16bit checksum computation. 974 * So you can choose one among IP, TCP and UDP. 975 * Normally driver sets checksum start/insertion 976 * position from the information of TCP/UDP frame as 977 * TCP/UDP checksum takes more time than that of IP. 978 * However it seems that custom checksum offload 979 * requires 4 bytes aligned Tx buffers due to hardware 980 * bug. 981 * AR81xx also supports explicit Tx checksum computation 982 * if it is told that the size of IP header and TCP 983 * header(for UDP, the header size does not matter 984 * because it's fixed length). However with this scheme 985 * TSO does not work so you have to choose one either 986 * TSO or explicit Tx checksum offload. I chosen TSO 987 * plus custom checksum offload with work-around which 988 * will cover most common usage for this consumer 989 * ethernet controller. The work-around takes a lot of 990 * CPU cycles if Tx buffer is not aligned on 4 bytes 991 * boundary, though. 992 */ 993 cflags |= ALE_TD_CXSUM; 994 /* Set checksum start offset. */ 995 cflags |= (poff << ALE_TD_CSUM_PLOADOFFSET_SHIFT); 996 } 997 998 #if NVLAN > 0 999 /* Configure VLAN hardware tag insertion. */ 1000 if ((mtag = VLAN_OUTPUT_TAG(&sc->sc_ec, m))) { 1001 vtag = ALE_TX_VLAN_TAG(htons(VLAN_TAG_VALUE(mtag))); 1002 vtag = ((vtag << ALE_TD_VLAN_SHIFT) & ALE_TD_VLAN_MASK); 1003 cflags |= ALE_TD_INSERT_VLAN_TAG; 1004 } 1005 #endif 1006 1007 desc = NULL; 1008 for (i = 0; i < nsegs; i++) { 1009 desc = &sc->ale_cdata.ale_tx_ring[prod]; 1010 desc->addr = htole64(map->dm_segs[i].ds_addr); 1011 desc->len = 1012 htole32(ALE_TX_BYTES(map->dm_segs[i].ds_len) | vtag); 1013 desc->flags = htole32(cflags); 1014 sc->ale_cdata.ale_tx_cnt++; 1015 ALE_DESC_INC(prod, ALE_TX_RING_CNT); 1016 } 1017 /* Update producer index. */ 1018 sc->ale_cdata.ale_tx_prod = prod; 1019 1020 /* Finally set EOP on the last descriptor. */ 1021 prod = (prod + ALE_TX_RING_CNT - 1) % ALE_TX_RING_CNT; 1022 desc = &sc->ale_cdata.ale_tx_ring[prod]; 1023 desc->flags |= htole32(ALE_TD_EOP); 1024 1025 /* Swap dmamap of the first and the last. */ 1026 txd = &sc->ale_cdata.ale_txdesc[prod]; 1027 map = txd_last->tx_dmamap; 1028 txd_last->tx_dmamap = txd->tx_dmamap; 1029 txd->tx_dmamap = map; 1030 txd->tx_m = m; 1031 1032 /* Sync descriptors. */ 1033 bus_dmamap_sync(sc->sc_dmat, sc->ale_cdata.ale_tx_ring_map, 0, 1034 sc->ale_cdata.ale_tx_ring_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 1035 1036 return 0; 1037 } 1038 1039 static void 1040 ale_start(struct ifnet *ifp) 1041 { 1042 struct ale_softc *sc = ifp->if_softc; 1043 struct mbuf *m_head; 1044 int enq; 1045 1046 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 1047 return; 1048 1049 /* Reclaim transmitted frames. */ 1050 if (sc->ale_cdata.ale_tx_cnt >= ALE_TX_DESC_HIWAT) 1051 ale_txeof(sc); 1052 1053 enq = 0; 1054 for (;;) { 1055 IFQ_DEQUEUE(&ifp->if_snd, m_head); 1056 if (m_head == NULL) 1057 break; 1058 1059 /* 1060 * Pack the data into the transmit ring. If we 1061 * don't have room, set the OACTIVE flag and wait 1062 * for the NIC to drain the ring. 1063 */ 1064 if (ale_encap(sc, &m_head)) { 1065 if (m_head == NULL) 1066 break; 1067 IF_PREPEND(&ifp->if_snd, m_head); 1068 ifp->if_flags |= IFF_OACTIVE; 1069 break; 1070 } 1071 enq = 1; 1072 1073 /* 1074 * If there's a BPF listener, bounce a copy of this frame 1075 * to him. 1076 */ 1077 bpf_mtap(ifp, m_head); 1078 } 1079 1080 if (enq) { 1081 /* Kick. */ 1082 CSR_WRITE_4(sc, ALE_MBOX_TPD_PROD_IDX, 1083 sc->ale_cdata.ale_tx_prod); 1084 1085 /* Set a timeout in case the chip goes out to lunch. */ 1086 ifp->if_timer = ALE_TX_TIMEOUT; 1087 } 1088 } 1089 1090 static void 1091 ale_watchdog(struct ifnet *ifp) 1092 { 1093 struct ale_softc *sc = ifp->if_softc; 1094 1095 if ((sc->ale_flags & ALE_FLAG_LINK) == 0) { 1096 printf("%s: watchdog timeout (missed link)\n", 1097 device_xname(sc->sc_dev)); 1098 ifp->if_oerrors++; 1099 ale_init(ifp); 1100 return; 1101 } 1102 1103 printf("%s: watchdog timeout\n", device_xname(sc->sc_dev)); 1104 ifp->if_oerrors++; 1105 ale_init(ifp); 1106 1107 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 1108 ale_start(ifp); 1109 } 1110 1111 static int 1112 ale_ioctl(struct ifnet *ifp, u_long cmd, void *data) 1113 { 1114 struct ale_softc *sc = ifp->if_softc; 1115 int s, error; 1116 1117 s = splnet(); 1118 1119 error = ether_ioctl(ifp, cmd, data); 1120 if (error == ENETRESET) { 1121 if (ifp->if_flags & IFF_RUNNING) 1122 ale_rxfilter(sc); 1123 error = 0; 1124 } 1125 1126 splx(s); 1127 return error; 1128 } 1129 1130 static void 1131 ale_mac_config(struct ale_softc *sc) 1132 { 1133 struct mii_data *mii; 1134 uint32_t reg; 1135 1136 mii = &sc->sc_miibus; 1137 reg = CSR_READ_4(sc, ALE_MAC_CFG); 1138 reg &= ~(MAC_CFG_FULL_DUPLEX | MAC_CFG_TX_FC | MAC_CFG_RX_FC | 1139 MAC_CFG_SPEED_MASK); 1140 1141 /* Reprogram MAC with resolved speed/duplex. */ 1142 switch (IFM_SUBTYPE(mii->mii_media_active)) { 1143 case IFM_10_T: 1144 case IFM_100_TX: 1145 reg |= MAC_CFG_SPEED_10_100; 1146 break; 1147 case IFM_1000_T: 1148 reg |= MAC_CFG_SPEED_1000; 1149 break; 1150 } 1151 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 1152 reg |= MAC_CFG_FULL_DUPLEX; 1153 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0) 1154 reg |= MAC_CFG_TX_FC; 1155 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0) 1156 reg |= MAC_CFG_RX_FC; 1157 } 1158 CSR_WRITE_4(sc, ALE_MAC_CFG, reg); 1159 } 1160 1161 static void 1162 ale_stats_clear(struct ale_softc *sc) 1163 { 1164 struct smb sb; 1165 uint32_t *reg; 1166 int i; 1167 1168 for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered; reg++) { 1169 CSR_READ_4(sc, ALE_RX_MIB_BASE + i); 1170 i += sizeof(uint32_t); 1171 } 1172 /* Read Tx statistics. */ 1173 for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes; reg++) { 1174 CSR_READ_4(sc, ALE_TX_MIB_BASE + i); 1175 i += sizeof(uint32_t); 1176 } 1177 } 1178 1179 static void 1180 ale_stats_update(struct ale_softc *sc) 1181 { 1182 struct ifnet *ifp = &sc->sc_ec.ec_if; 1183 struct ale_hw_stats *stat; 1184 struct smb sb, *smb; 1185 uint32_t *reg; 1186 int i; 1187 1188 stat = &sc->ale_stats; 1189 smb = &sb; 1190 1191 /* Read Rx statistics. */ 1192 for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered; reg++) { 1193 *reg = CSR_READ_4(sc, ALE_RX_MIB_BASE + i); 1194 i += sizeof(uint32_t); 1195 } 1196 /* Read Tx statistics. */ 1197 for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes; reg++) { 1198 *reg = CSR_READ_4(sc, ALE_TX_MIB_BASE + i); 1199 i += sizeof(uint32_t); 1200 } 1201 1202 /* Rx stats. */ 1203 stat->rx_frames += smb->rx_frames; 1204 stat->rx_bcast_frames += smb->rx_bcast_frames; 1205 stat->rx_mcast_frames += smb->rx_mcast_frames; 1206 stat->rx_pause_frames += smb->rx_pause_frames; 1207 stat->rx_control_frames += smb->rx_control_frames; 1208 stat->rx_crcerrs += smb->rx_crcerrs; 1209 stat->rx_lenerrs += smb->rx_lenerrs; 1210 stat->rx_bytes += smb->rx_bytes; 1211 stat->rx_runts += smb->rx_runts; 1212 stat->rx_fragments += smb->rx_fragments; 1213 stat->rx_pkts_64 += smb->rx_pkts_64; 1214 stat->rx_pkts_65_127 += smb->rx_pkts_65_127; 1215 stat->rx_pkts_128_255 += smb->rx_pkts_128_255; 1216 stat->rx_pkts_256_511 += smb->rx_pkts_256_511; 1217 stat->rx_pkts_512_1023 += smb->rx_pkts_512_1023; 1218 stat->rx_pkts_1024_1518 += smb->rx_pkts_1024_1518; 1219 stat->rx_pkts_1519_max += smb->rx_pkts_1519_max; 1220 stat->rx_pkts_truncated += smb->rx_pkts_truncated; 1221 stat->rx_fifo_oflows += smb->rx_fifo_oflows; 1222 stat->rx_rrs_errs += smb->rx_rrs_errs; 1223 stat->rx_alignerrs += smb->rx_alignerrs; 1224 stat->rx_bcast_bytes += smb->rx_bcast_bytes; 1225 stat->rx_mcast_bytes += smb->rx_mcast_bytes; 1226 stat->rx_pkts_filtered += smb->rx_pkts_filtered; 1227 1228 /* Tx stats. */ 1229 stat->tx_frames += smb->tx_frames; 1230 stat->tx_bcast_frames += smb->tx_bcast_frames; 1231 stat->tx_mcast_frames += smb->tx_mcast_frames; 1232 stat->tx_pause_frames += smb->tx_pause_frames; 1233 stat->tx_excess_defer += smb->tx_excess_defer; 1234 stat->tx_control_frames += smb->tx_control_frames; 1235 stat->tx_deferred += smb->tx_deferred; 1236 stat->tx_bytes += smb->tx_bytes; 1237 stat->tx_pkts_64 += smb->tx_pkts_64; 1238 stat->tx_pkts_65_127 += smb->tx_pkts_65_127; 1239 stat->tx_pkts_128_255 += smb->tx_pkts_128_255; 1240 stat->tx_pkts_256_511 += smb->tx_pkts_256_511; 1241 stat->tx_pkts_512_1023 += smb->tx_pkts_512_1023; 1242 stat->tx_pkts_1024_1518 += smb->tx_pkts_1024_1518; 1243 stat->tx_pkts_1519_max += smb->tx_pkts_1519_max; 1244 stat->tx_single_colls += smb->tx_single_colls; 1245 stat->tx_multi_colls += smb->tx_multi_colls; 1246 stat->tx_late_colls += smb->tx_late_colls; 1247 stat->tx_excess_colls += smb->tx_excess_colls; 1248 stat->tx_abort += smb->tx_abort; 1249 stat->tx_underrun += smb->tx_underrun; 1250 stat->tx_desc_underrun += smb->tx_desc_underrun; 1251 stat->tx_lenerrs += smb->tx_lenerrs; 1252 stat->tx_pkts_truncated += smb->tx_pkts_truncated; 1253 stat->tx_bcast_bytes += smb->tx_bcast_bytes; 1254 stat->tx_mcast_bytes += smb->tx_mcast_bytes; 1255 1256 /* Update counters in ifnet. */ 1257 ifp->if_opackets += smb->tx_frames; 1258 1259 ifp->if_collisions += smb->tx_single_colls + 1260 smb->tx_multi_colls * 2 + smb->tx_late_colls + 1261 smb->tx_abort * HDPX_CFG_RETRY_DEFAULT; 1262 1263 /* 1264 * XXX 1265 * tx_pkts_truncated counter looks suspicious. It constantly 1266 * increments with no sign of Tx errors. This may indicate 1267 * the counter name is not correct one so I've removed the 1268 * counter in output errors. 1269 */ 1270 ifp->if_oerrors += smb->tx_abort + smb->tx_late_colls + 1271 smb->tx_underrun; 1272 1273 ifp->if_ipackets += smb->rx_frames; 1274 1275 ifp->if_ierrors += smb->rx_crcerrs + smb->rx_lenerrs + 1276 smb->rx_runts + smb->rx_pkts_truncated + 1277 smb->rx_fifo_oflows + smb->rx_rrs_errs + 1278 smb->rx_alignerrs; 1279 } 1280 1281 static int 1282 ale_intr(void *xsc) 1283 { 1284 struct ale_softc *sc = xsc; 1285 struct ifnet *ifp = &sc->sc_ec.ec_if; 1286 uint32_t status; 1287 1288 status = CSR_READ_4(sc, ALE_INTR_STATUS); 1289 if ((status & ALE_INTRS) == 0) 1290 return 0; 1291 1292 /* Acknowledge and disable interrupts. */ 1293 CSR_WRITE_4(sc, ALE_INTR_STATUS, status | INTR_DIS_INT); 1294 1295 if (ifp->if_flags & IFF_RUNNING) { 1296 int error; 1297 1298 error = ale_rxeof(sc); 1299 if (error) { 1300 sc->ale_stats.reset_brk_seq++; 1301 ale_init(ifp); 1302 return 0; 1303 } 1304 1305 if (status & (INTR_DMA_RD_TO_RST | INTR_DMA_WR_TO_RST)) { 1306 if (status & INTR_DMA_RD_TO_RST) 1307 printf("%s: DMA read error! -- resetting\n", 1308 device_xname(sc->sc_dev)); 1309 if (status & INTR_DMA_WR_TO_RST) 1310 printf("%s: DMA write error! -- resetting\n", 1311 device_xname(sc->sc_dev)); 1312 ale_init(ifp); 1313 return 0; 1314 } 1315 1316 ale_txeof(sc); 1317 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 1318 ale_start(ifp); 1319 } 1320 1321 /* Re-enable interrupts. */ 1322 CSR_WRITE_4(sc, ALE_INTR_STATUS, 0x7FFFFFFF); 1323 return 1; 1324 } 1325 1326 static void 1327 ale_txeof(struct ale_softc *sc) 1328 { 1329 struct ifnet *ifp = &sc->sc_ec.ec_if; 1330 struct ale_txdesc *txd; 1331 uint32_t cons, prod; 1332 int prog; 1333 1334 if (sc->ale_cdata.ale_tx_cnt == 0) 1335 return; 1336 1337 bus_dmamap_sync(sc->sc_dmat, sc->ale_cdata.ale_tx_ring_map, 0, 1338 sc->ale_cdata.ale_tx_ring_map->dm_mapsize, BUS_DMASYNC_POSTREAD); 1339 if ((sc->ale_flags & ALE_FLAG_TXCMB_BUG) == 0) { 1340 bus_dmamap_sync(sc->sc_dmat, sc->ale_cdata.ale_tx_cmb_map, 0, 1341 sc->ale_cdata.ale_tx_cmb_map->dm_mapsize, 1342 BUS_DMASYNC_POSTREAD); 1343 prod = *sc->ale_cdata.ale_tx_cmb & TPD_CNT_MASK; 1344 } else 1345 prod = CSR_READ_2(sc, ALE_TPD_CONS_IDX); 1346 cons = sc->ale_cdata.ale_tx_cons; 1347 /* 1348 * Go through our Tx list and free mbufs for those 1349 * frames which have been transmitted. 1350 */ 1351 for (prog = 0; cons != prod; prog++, 1352 ALE_DESC_INC(cons, ALE_TX_RING_CNT)) { 1353 if (sc->ale_cdata.ale_tx_cnt <= 0) 1354 break; 1355 prog++; 1356 ifp->if_flags &= ~IFF_OACTIVE; 1357 sc->ale_cdata.ale_tx_cnt--; 1358 txd = &sc->ale_cdata.ale_txdesc[cons]; 1359 if (txd->tx_m != NULL) { 1360 /* Reclaim transmitted mbufs. */ 1361 bus_dmamap_unload(sc->sc_dmat, txd->tx_dmamap); 1362 m_freem(txd->tx_m); 1363 txd->tx_m = NULL; 1364 } 1365 } 1366 1367 if (prog > 0) { 1368 sc->ale_cdata.ale_tx_cons = cons; 1369 /* 1370 * Unarm watchdog timer only when there is no pending 1371 * Tx descriptors in queue. 1372 */ 1373 if (sc->ale_cdata.ale_tx_cnt == 0) 1374 ifp->if_timer = 0; 1375 } 1376 } 1377 1378 static void 1379 ale_rx_update_page(struct ale_softc *sc, struct ale_rx_page **page, 1380 uint32_t length, uint32_t *prod) 1381 { 1382 struct ale_rx_page *rx_page; 1383 1384 rx_page = *page; 1385 /* Update consumer position. */ 1386 rx_page->cons += roundup(length + sizeof(struct rx_rs), 1387 ALE_RX_PAGE_ALIGN); 1388 if (rx_page->cons >= ALE_RX_PAGE_SZ) { 1389 /* 1390 * End of Rx page reached, let hardware reuse 1391 * this page. 1392 */ 1393 rx_page->cons = 0; 1394 *rx_page->cmb_addr = 0; 1395 bus_dmamap_sync(sc->sc_dmat, rx_page->cmb_map, 0, 1396 rx_page->cmb_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 1397 CSR_WRITE_1(sc, ALE_RXF0_PAGE0 + sc->ale_cdata.ale_rx_curp, 1398 RXF_VALID); 1399 /* Switch to alternate Rx page. */ 1400 sc->ale_cdata.ale_rx_curp ^= 1; 1401 rx_page = *page = 1402 &sc->ale_cdata.ale_rx_page[sc->ale_cdata.ale_rx_curp]; 1403 /* Page flipped, sync CMB and Rx page. */ 1404 bus_dmamap_sync(sc->sc_dmat, rx_page->page_map, 0, 1405 rx_page->page_map->dm_mapsize, BUS_DMASYNC_POSTREAD); 1406 bus_dmamap_sync(sc->sc_dmat, rx_page->cmb_map, 0, 1407 rx_page->cmb_map->dm_mapsize, BUS_DMASYNC_POSTREAD); 1408 /* Sync completed, cache updated producer index. */ 1409 *prod = *rx_page->cmb_addr; 1410 } 1411 } 1412 1413 1414 /* 1415 * It seems that AR81xx controller can compute partial checksum. 1416 * The partial checksum value can be used to accelerate checksum 1417 * computation for fragmented TCP/UDP packets. Upper network stack 1418 * already takes advantage of the partial checksum value in IP 1419 * reassembly stage. But I'm not sure the correctness of the 1420 * partial hardware checksum assistance due to lack of data sheet. 1421 * In addition, the Rx feature of controller that requires copying 1422 * for every frames effectively nullifies one of most nice offload 1423 * capability of controller. 1424 */ 1425 static void 1426 ale_rxcsum(struct ale_softc *sc, struct mbuf *m, uint32_t status) 1427 { 1428 if (status & ALE_RD_IPCSUM_NOK) 1429 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 1430 1431 if ((sc->ale_flags & ALE_FLAG_RXCSUM_BUG) == 0) { 1432 if (((status & ALE_RD_IPV4_FRAG) == 0) && 1433 ((status & (ALE_RD_TCP | ALE_RD_UDP)) != 0) && 1434 (status & ALE_RD_TCP_UDPCSUM_NOK)) 1435 { 1436 m->m_pkthdr.csum_flags |= M_CSUM_TCP_UDP_BAD; 1437 } 1438 } else { 1439 if ((status & (ALE_RD_TCP | ALE_RD_UDP)) != 0) { 1440 if (status & ALE_RD_TCP_UDPCSUM_NOK) { 1441 m->m_pkthdr.csum_flags |= M_CSUM_TCP_UDP_BAD; 1442 } 1443 } 1444 } 1445 /* 1446 * Don't mark bad checksum for TCP/UDP frames 1447 * as fragmented frames may always have set 1448 * bad checksummed bit of frame status. 1449 */ 1450 } 1451 1452 /* Process received frames. */ 1453 static int 1454 ale_rxeof(struct ale_softc *sc) 1455 { 1456 struct ifnet *ifp = &sc->sc_ec.ec_if; 1457 struct ale_rx_page *rx_page; 1458 struct rx_rs *rs; 1459 struct mbuf *m; 1460 uint32_t length, prod, seqno, status; 1461 int prog; 1462 1463 rx_page = &sc->ale_cdata.ale_rx_page[sc->ale_cdata.ale_rx_curp]; 1464 bus_dmamap_sync(sc->sc_dmat, rx_page->cmb_map, 0, 1465 rx_page->cmb_map->dm_mapsize, BUS_DMASYNC_POSTREAD); 1466 bus_dmamap_sync(sc->sc_dmat, rx_page->page_map, 0, 1467 rx_page->page_map->dm_mapsize, BUS_DMASYNC_POSTREAD); 1468 /* 1469 * Don't directly access producer index as hardware may 1470 * update it while Rx handler is in progress. It would 1471 * be even better if there is a way to let hardware 1472 * know how far driver processed its received frames. 1473 * Alternatively, hardware could provide a way to disable 1474 * CMB updates until driver acknowledges the end of CMB 1475 * access. 1476 */ 1477 prod = *rx_page->cmb_addr; 1478 for (prog = 0; ; prog++) { 1479 if (rx_page->cons >= prod) 1480 break; 1481 rs = (struct rx_rs *)(rx_page->page_addr + rx_page->cons); 1482 seqno = ALE_RX_SEQNO(le32toh(rs->seqno)); 1483 if (sc->ale_cdata.ale_rx_seqno != seqno) { 1484 /* 1485 * Normally I believe this should not happen unless 1486 * severe driver bug or corrupted memory. However 1487 * it seems to happen under certain conditions which 1488 * is triggered by abrupt Rx events such as initiation 1489 * of bulk transfer of remote host. It's not easy to 1490 * reproduce this and I doubt it could be related 1491 * with FIFO overflow of hardware or activity of Tx 1492 * CMB updates. I also remember similar behaviour 1493 * seen on RealTek 8139 which uses resembling Rx 1494 * scheme. 1495 */ 1496 if (aledebug) 1497 printf("%s: garbled seq: %u, expected: %u -- " 1498 "resetting!\n", device_xname(sc->sc_dev), 1499 seqno, sc->ale_cdata.ale_rx_seqno); 1500 return EIO; 1501 } 1502 /* Frame received. */ 1503 sc->ale_cdata.ale_rx_seqno++; 1504 length = ALE_RX_BYTES(le32toh(rs->length)); 1505 status = le32toh(rs->flags); 1506 if (status & ALE_RD_ERROR) { 1507 /* 1508 * We want to pass the following frames to upper 1509 * layer regardless of error status of Rx return 1510 * status. 1511 * 1512 * o IP/TCP/UDP checksum is bad. 1513 * o frame length and protocol specific length 1514 * does not match. 1515 */ 1516 if (status & (ALE_RD_CRC | ALE_RD_CODE | 1517 ALE_RD_DRIBBLE | ALE_RD_RUNT | ALE_RD_OFLOW | 1518 ALE_RD_TRUNC)) { 1519 ale_rx_update_page(sc, &rx_page, length, &prod); 1520 continue; 1521 } 1522 } 1523 /* 1524 * m_devget(9) is major bottle-neck of ale(4)(It comes 1525 * from hardware limitation). For jumbo frames we could 1526 * get a slightly better performance if driver use 1527 * m_getjcl(9) with proper buffer size argument. However 1528 * that would make code more complicated and I don't 1529 * think users would expect good Rx performance numbers 1530 * on these low-end consumer ethernet controller. 1531 */ 1532 m = m_devget((char *)(rs + 1), length - ETHER_CRC_LEN, 1533 0, ifp, NULL); 1534 if (m == NULL) { 1535 ifp->if_iqdrops++; 1536 ale_rx_update_page(sc, &rx_page, length, &prod); 1537 continue; 1538 } 1539 if (status & ALE_RD_IPV4) 1540 ale_rxcsum(sc, m, status); 1541 #if NVLAN > 0 1542 if (status & ALE_RD_VLAN) { 1543 uint32_t vtags = ALE_RX_VLAN(le32toh(rs->vtags)); 1544 VLAN_INPUT_TAG(ifp, m, ALE_RX_VLAN_TAG(vtags), ); 1545 } 1546 #endif 1547 1548 1549 bpf_mtap(ifp, m); 1550 1551 /* Pass it to upper layer. */ 1552 ether_input(ifp, m); 1553 1554 ale_rx_update_page(sc, &rx_page, length, &prod); 1555 } 1556 1557 return 0; 1558 } 1559 1560 static void 1561 ale_tick(void *xsc) 1562 { 1563 struct ale_softc *sc = xsc; 1564 struct mii_data *mii = &sc->sc_miibus; 1565 int s; 1566 1567 s = splnet(); 1568 mii_tick(mii); 1569 ale_stats_update(sc); 1570 splx(s); 1571 1572 callout_schedule(&sc->sc_tick_ch, hz); 1573 } 1574 1575 static void 1576 ale_reset(struct ale_softc *sc) 1577 { 1578 uint32_t reg; 1579 int i; 1580 1581 /* Initialize PCIe module. From Linux. */ 1582 CSR_WRITE_4(sc, 0x1008, CSR_READ_4(sc, 0x1008) | 0x8000); 1583 1584 CSR_WRITE_4(sc, ALE_MASTER_CFG, MASTER_RESET); 1585 for (i = ALE_RESET_TIMEOUT; i > 0; i--) { 1586 DELAY(10); 1587 if ((CSR_READ_4(sc, ALE_MASTER_CFG) & MASTER_RESET) == 0) 1588 break; 1589 } 1590 if (i == 0) 1591 printf("%s: master reset timeout!\n", device_xname(sc->sc_dev)); 1592 1593 for (i = ALE_RESET_TIMEOUT; i > 0; i--) { 1594 if ((reg = CSR_READ_4(sc, ALE_IDLE_STATUS)) == 0) 1595 break; 1596 DELAY(10); 1597 } 1598 1599 if (i == 0) 1600 printf("%s: reset timeout(0x%08x)!\n", device_xname(sc->sc_dev), 1601 reg); 1602 } 1603 1604 static int 1605 ale_init(struct ifnet *ifp) 1606 { 1607 struct ale_softc *sc = ifp->if_softc; 1608 struct mii_data *mii; 1609 uint8_t eaddr[ETHER_ADDR_LEN]; 1610 bus_addr_t paddr; 1611 uint32_t reg, rxf_hi, rxf_lo; 1612 1613 /* 1614 * Cancel any pending I/O. 1615 */ 1616 ale_stop(ifp, 0); 1617 1618 /* 1619 * Reset the chip to a known state. 1620 */ 1621 ale_reset(sc); 1622 1623 /* Initialize Tx descriptors, DMA memory blocks. */ 1624 ale_init_rx_pages(sc); 1625 ale_init_tx_ring(sc); 1626 1627 /* Reprogram the station address. */ 1628 memcpy(eaddr, CLLADDR(ifp->if_sadl), ETHER_ADDR_LEN); 1629 CSR_WRITE_4(sc, ALE_PAR0, 1630 eaddr[2] << 24 | eaddr[3] << 16 | eaddr[4] << 8 | eaddr[5]); 1631 CSR_WRITE_4(sc, ALE_PAR1, eaddr[0] << 8 | eaddr[1]); 1632 1633 /* 1634 * Clear WOL status and disable all WOL feature as WOL 1635 * would interfere Rx operation under normal environments. 1636 */ 1637 CSR_READ_4(sc, ALE_WOL_CFG); 1638 CSR_WRITE_4(sc, ALE_WOL_CFG, 0); 1639 1640 /* 1641 * Set Tx descriptor/RXF0/CMB base addresses. They share 1642 * the same high address part of DMAable region. 1643 */ 1644 paddr = sc->ale_cdata.ale_tx_ring_paddr; 1645 CSR_WRITE_4(sc, ALE_TPD_ADDR_HI, ALE_ADDR_HI(paddr)); 1646 CSR_WRITE_4(sc, ALE_TPD_ADDR_LO, ALE_ADDR_LO(paddr)); 1647 CSR_WRITE_4(sc, ALE_TPD_CNT, 1648 (ALE_TX_RING_CNT << TPD_CNT_SHIFT) & TPD_CNT_MASK); 1649 1650 /* Set Rx page base address, note we use single queue. */ 1651 paddr = sc->ale_cdata.ale_rx_page[0].page_paddr; 1652 CSR_WRITE_4(sc, ALE_RXF0_PAGE0_ADDR_LO, ALE_ADDR_LO(paddr)); 1653 paddr = sc->ale_cdata.ale_rx_page[1].page_paddr; 1654 CSR_WRITE_4(sc, ALE_RXF0_PAGE1_ADDR_LO, ALE_ADDR_LO(paddr)); 1655 1656 /* Set Tx/Rx CMB addresses. */ 1657 paddr = sc->ale_cdata.ale_tx_cmb_paddr; 1658 CSR_WRITE_4(sc, ALE_TX_CMB_ADDR_LO, ALE_ADDR_LO(paddr)); 1659 paddr = sc->ale_cdata.ale_rx_page[0].cmb_paddr; 1660 CSR_WRITE_4(sc, ALE_RXF0_CMB0_ADDR_LO, ALE_ADDR_LO(paddr)); 1661 paddr = sc->ale_cdata.ale_rx_page[1].cmb_paddr; 1662 CSR_WRITE_4(sc, ALE_RXF0_CMB1_ADDR_LO, ALE_ADDR_LO(paddr)); 1663 1664 /* Mark RXF0 is valid. */ 1665 CSR_WRITE_1(sc, ALE_RXF0_PAGE0, RXF_VALID); 1666 CSR_WRITE_1(sc, ALE_RXF0_PAGE1, RXF_VALID); 1667 /* 1668 * No need to initialize RFX1/RXF2/RXF3. We don't use 1669 * multi-queue yet. 1670 */ 1671 1672 /* Set Rx page size, excluding guard frame size. */ 1673 CSR_WRITE_4(sc, ALE_RXF_PAGE_SIZE, ALE_RX_PAGE_SZ); 1674 1675 /* Tell hardware that we're ready to load DMA blocks. */ 1676 CSR_WRITE_4(sc, ALE_DMA_BLOCK, DMA_BLOCK_LOAD); 1677 1678 /* Set Rx/Tx interrupt trigger threshold. */ 1679 CSR_WRITE_4(sc, ALE_INT_TRIG_THRESH, (1 << INT_TRIG_RX_THRESH_SHIFT) | 1680 (4 << INT_TRIG_TX_THRESH_SHIFT)); 1681 /* 1682 * XXX 1683 * Set interrupt trigger timer, its purpose and relation 1684 * with interrupt moderation mechanism is not clear yet. 1685 */ 1686 CSR_WRITE_4(sc, ALE_INT_TRIG_TIMER, 1687 ((ALE_USECS(10) << INT_TRIG_RX_TIMER_SHIFT) | 1688 (ALE_USECS(1000) << INT_TRIG_TX_TIMER_SHIFT))); 1689 1690 /* Configure interrupt moderation timer. */ 1691 sc->ale_int_rx_mod = ALE_IM_RX_TIMER_DEFAULT; 1692 sc->ale_int_tx_mod = ALE_IM_TX_TIMER_DEFAULT; 1693 reg = ALE_USECS(sc->ale_int_rx_mod) << IM_TIMER_RX_SHIFT; 1694 reg |= ALE_USECS(sc->ale_int_tx_mod) << IM_TIMER_TX_SHIFT; 1695 CSR_WRITE_4(sc, ALE_IM_TIMER, reg); 1696 reg = CSR_READ_4(sc, ALE_MASTER_CFG); 1697 reg &= ~(MASTER_CHIP_REV_MASK | MASTER_CHIP_ID_MASK); 1698 reg &= ~(MASTER_IM_RX_TIMER_ENB | MASTER_IM_TX_TIMER_ENB); 1699 if (ALE_USECS(sc->ale_int_rx_mod) != 0) 1700 reg |= MASTER_IM_RX_TIMER_ENB; 1701 if (ALE_USECS(sc->ale_int_tx_mod) != 0) 1702 reg |= MASTER_IM_TX_TIMER_ENB; 1703 CSR_WRITE_4(sc, ALE_MASTER_CFG, reg); 1704 CSR_WRITE_2(sc, ALE_INTR_CLR_TIMER, ALE_USECS(1000)); 1705 1706 /* Set Maximum frame size of controller. */ 1707 if (ifp->if_mtu < ETHERMTU) 1708 sc->ale_max_frame_size = ETHERMTU; 1709 else 1710 sc->ale_max_frame_size = ifp->if_mtu; 1711 sc->ale_max_frame_size += ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN + ETHER_CRC_LEN; 1712 CSR_WRITE_4(sc, ALE_FRAME_SIZE, sc->ale_max_frame_size); 1713 1714 /* Configure IPG/IFG parameters. */ 1715 CSR_WRITE_4(sc, ALE_IPG_IFG_CFG, 1716 ((IPG_IFG_IPGT_DEFAULT << IPG_IFG_IPGT_SHIFT) & IPG_IFG_IPGT_MASK) | 1717 ((IPG_IFG_MIFG_DEFAULT << IPG_IFG_MIFG_SHIFT) & IPG_IFG_MIFG_MASK) | 1718 ((IPG_IFG_IPG1_DEFAULT << IPG_IFG_IPG1_SHIFT) & IPG_IFG_IPG1_MASK) | 1719 ((IPG_IFG_IPG2_DEFAULT << IPG_IFG_IPG2_SHIFT) & IPG_IFG_IPG2_MASK)); 1720 1721 /* Set parameters for half-duplex media. */ 1722 CSR_WRITE_4(sc, ALE_HDPX_CFG, 1723 ((HDPX_CFG_LCOL_DEFAULT << HDPX_CFG_LCOL_SHIFT) & 1724 HDPX_CFG_LCOL_MASK) | 1725 ((HDPX_CFG_RETRY_DEFAULT << HDPX_CFG_RETRY_SHIFT) & 1726 HDPX_CFG_RETRY_MASK) | HDPX_CFG_EXC_DEF_EN | 1727 ((HDPX_CFG_ABEBT_DEFAULT << HDPX_CFG_ABEBT_SHIFT) & 1728 HDPX_CFG_ABEBT_MASK) | 1729 ((HDPX_CFG_JAMIPG_DEFAULT << HDPX_CFG_JAMIPG_SHIFT) & 1730 HDPX_CFG_JAMIPG_MASK)); 1731 1732 /* Configure Tx jumbo frame parameters. */ 1733 if ((sc->ale_flags & ALE_FLAG_JUMBO) != 0) { 1734 if (ifp->if_mtu < ETHERMTU) 1735 reg = sc->ale_max_frame_size; 1736 else if (ifp->if_mtu < 6 * 1024) 1737 reg = (sc->ale_max_frame_size * 2) / 3; 1738 else 1739 reg = sc->ale_max_frame_size / 2; 1740 CSR_WRITE_4(sc, ALE_TX_JUMBO_THRESH, 1741 roundup(reg, TX_JUMBO_THRESH_UNIT) >> 1742 TX_JUMBO_THRESH_UNIT_SHIFT); 1743 } 1744 1745 /* Configure TxQ. */ 1746 reg = (128 << (sc->ale_dma_rd_burst >> DMA_CFG_RD_BURST_SHIFT)) 1747 << TXQ_CFG_TX_FIFO_BURST_SHIFT; 1748 reg |= (TXQ_CFG_TPD_BURST_DEFAULT << TXQ_CFG_TPD_BURST_SHIFT) & 1749 TXQ_CFG_TPD_BURST_MASK; 1750 CSR_WRITE_4(sc, ALE_TXQ_CFG, reg | TXQ_CFG_ENHANCED_MODE | TXQ_CFG_ENB); 1751 1752 /* Configure Rx jumbo frame & flow control parameters. */ 1753 if ((sc->ale_flags & ALE_FLAG_JUMBO) != 0) { 1754 reg = roundup(sc->ale_max_frame_size, RX_JUMBO_THRESH_UNIT); 1755 CSR_WRITE_4(sc, ALE_RX_JUMBO_THRESH, 1756 (((reg >> RX_JUMBO_THRESH_UNIT_SHIFT) << 1757 RX_JUMBO_THRESH_MASK_SHIFT) & RX_JUMBO_THRESH_MASK) | 1758 ((RX_JUMBO_LKAH_DEFAULT << RX_JUMBO_LKAH_SHIFT) & 1759 RX_JUMBO_LKAH_MASK)); 1760 reg = CSR_READ_4(sc, ALE_SRAM_RX_FIFO_LEN); 1761 rxf_hi = (reg * 7) / 10; 1762 rxf_lo = (reg * 3)/ 10; 1763 CSR_WRITE_4(sc, ALE_RX_FIFO_PAUSE_THRESH, 1764 ((rxf_lo << RX_FIFO_PAUSE_THRESH_LO_SHIFT) & 1765 RX_FIFO_PAUSE_THRESH_LO_MASK) | 1766 ((rxf_hi << RX_FIFO_PAUSE_THRESH_HI_SHIFT) & 1767 RX_FIFO_PAUSE_THRESH_HI_MASK)); 1768 } 1769 1770 /* Disable RSS. */ 1771 CSR_WRITE_4(sc, ALE_RSS_IDT_TABLE0, 0); 1772 CSR_WRITE_4(sc, ALE_RSS_CPU, 0); 1773 1774 /* Configure RxQ. */ 1775 CSR_WRITE_4(sc, ALE_RXQ_CFG, 1776 RXQ_CFG_ALIGN_32 | RXQ_CFG_CUT_THROUGH_ENB | RXQ_CFG_ENB); 1777 1778 /* Configure DMA parameters. */ 1779 reg = 0; 1780 if ((sc->ale_flags & ALE_FLAG_TXCMB_BUG) == 0) 1781 reg |= DMA_CFG_TXCMB_ENB; 1782 CSR_WRITE_4(sc, ALE_DMA_CFG, 1783 DMA_CFG_OUT_ORDER | DMA_CFG_RD_REQ_PRI | DMA_CFG_RCB_64 | 1784 sc->ale_dma_rd_burst | reg | 1785 sc->ale_dma_wr_burst | DMA_CFG_RXCMB_ENB | 1786 ((DMA_CFG_RD_DELAY_CNT_DEFAULT << DMA_CFG_RD_DELAY_CNT_SHIFT) & 1787 DMA_CFG_RD_DELAY_CNT_MASK) | 1788 ((DMA_CFG_WR_DELAY_CNT_DEFAULT << DMA_CFG_WR_DELAY_CNT_SHIFT) & 1789 DMA_CFG_WR_DELAY_CNT_MASK)); 1790 1791 /* 1792 * Hardware can be configured to issue SMB interrupt based 1793 * on programmed interval. Since there is a callout that is 1794 * invoked for every hz in driver we use that instead of 1795 * relying on periodic SMB interrupt. 1796 */ 1797 CSR_WRITE_4(sc, ALE_SMB_STAT_TIMER, ALE_USECS(0)); 1798 1799 /* Clear MAC statistics. */ 1800 ale_stats_clear(sc); 1801 1802 /* 1803 * Configure Tx/Rx MACs. 1804 * - Auto-padding for short frames. 1805 * - Enable CRC generation. 1806 * Actual reconfiguration of MAC for resolved speed/duplex 1807 * is followed after detection of link establishment. 1808 * AR81xx always does checksum computation regardless of 1809 * MAC_CFG_RXCSUM_ENB bit. In fact, setting the bit will 1810 * cause Rx handling issue for fragmented IP datagrams due 1811 * to silicon bug. 1812 */ 1813 reg = MAC_CFG_TX_CRC_ENB | MAC_CFG_TX_AUTO_PAD | MAC_CFG_FULL_DUPLEX | 1814 ((MAC_CFG_PREAMBLE_DEFAULT << MAC_CFG_PREAMBLE_SHIFT) & 1815 MAC_CFG_PREAMBLE_MASK); 1816 if ((sc->ale_flags & ALE_FLAG_FASTETHER) != 0) 1817 reg |= MAC_CFG_SPEED_10_100; 1818 else 1819 reg |= MAC_CFG_SPEED_1000; 1820 CSR_WRITE_4(sc, ALE_MAC_CFG, reg); 1821 1822 /* Set up the receive filter. */ 1823 ale_rxfilter(sc); 1824 ale_rxvlan(sc); 1825 1826 /* Acknowledge all pending interrupts and clear it. */ 1827 CSR_WRITE_4(sc, ALE_INTR_MASK, ALE_INTRS); 1828 CSR_WRITE_4(sc, ALE_INTR_STATUS, 0xFFFFFFFF); 1829 CSR_WRITE_4(sc, ALE_INTR_STATUS, 0); 1830 1831 sc->ale_flags &= ~ALE_FLAG_LINK; 1832 1833 /* Switch to the current media. */ 1834 mii = &sc->sc_miibus; 1835 mii_mediachg(mii); 1836 1837 callout_schedule(&sc->sc_tick_ch, hz); 1838 1839 ifp->if_flags |= IFF_RUNNING; 1840 ifp->if_flags &= ~IFF_OACTIVE; 1841 1842 return 0; 1843 } 1844 1845 static void 1846 ale_stop(struct ifnet *ifp, int disable) 1847 { 1848 struct ale_softc *sc = ifp->if_softc; 1849 struct ale_txdesc *txd; 1850 uint32_t reg; 1851 int i; 1852 1853 callout_stop(&sc->sc_tick_ch); 1854 1855 /* 1856 * Mark the interface down and cancel the watchdog timer. 1857 */ 1858 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1859 ifp->if_timer = 0; 1860 1861 sc->ale_flags &= ~ALE_FLAG_LINK; 1862 1863 ale_stats_update(sc); 1864 1865 mii_down(&sc->sc_miibus); 1866 1867 /* Disable interrupts. */ 1868 CSR_WRITE_4(sc, ALE_INTR_MASK, 0); 1869 CSR_WRITE_4(sc, ALE_INTR_STATUS, 0xFFFFFFFF); 1870 1871 /* Disable queue processing and DMA. */ 1872 reg = CSR_READ_4(sc, ALE_TXQ_CFG); 1873 reg &= ~TXQ_CFG_ENB; 1874 CSR_WRITE_4(sc, ALE_TXQ_CFG, reg); 1875 reg = CSR_READ_4(sc, ALE_RXQ_CFG); 1876 reg &= ~RXQ_CFG_ENB; 1877 CSR_WRITE_4(sc, ALE_RXQ_CFG, reg); 1878 reg = CSR_READ_4(sc, ALE_DMA_CFG); 1879 reg &= ~(DMA_CFG_TXCMB_ENB | DMA_CFG_RXCMB_ENB); 1880 CSR_WRITE_4(sc, ALE_DMA_CFG, reg); 1881 DELAY(1000); 1882 1883 /* Stop Rx/Tx MACs. */ 1884 ale_stop_mac(sc); 1885 1886 /* Disable interrupts again? XXX */ 1887 CSR_WRITE_4(sc, ALE_INTR_STATUS, 0xFFFFFFFF); 1888 1889 /* 1890 * Free TX mbufs still in the queues. 1891 */ 1892 for (i = 0; i < ALE_TX_RING_CNT; i++) { 1893 txd = &sc->ale_cdata.ale_txdesc[i]; 1894 if (txd->tx_m != NULL) { 1895 bus_dmamap_unload(sc->sc_dmat, txd->tx_dmamap); 1896 m_freem(txd->tx_m); 1897 txd->tx_m = NULL; 1898 } 1899 } 1900 } 1901 1902 static void 1903 ale_stop_mac(struct ale_softc *sc) 1904 { 1905 uint32_t reg; 1906 int i; 1907 1908 reg = CSR_READ_4(sc, ALE_MAC_CFG); 1909 if ((reg & (MAC_CFG_TX_ENB | MAC_CFG_RX_ENB)) != 0) { 1910 reg &= ~(MAC_CFG_TX_ENB | MAC_CFG_RX_ENB); 1911 CSR_WRITE_4(sc, ALE_MAC_CFG, reg); 1912 } 1913 1914 for (i = ALE_TIMEOUT; i > 0; i--) { 1915 reg = CSR_READ_4(sc, ALE_IDLE_STATUS); 1916 if (reg == 0) 1917 break; 1918 DELAY(10); 1919 } 1920 if (i == 0) 1921 printf("%s: could not disable Tx/Rx MAC(0x%08x)!\n", 1922 device_xname(sc->sc_dev), reg); 1923 } 1924 1925 static void 1926 ale_init_tx_ring(struct ale_softc *sc) 1927 { 1928 struct ale_txdesc *txd; 1929 int i; 1930 1931 sc->ale_cdata.ale_tx_prod = 0; 1932 sc->ale_cdata.ale_tx_cons = 0; 1933 sc->ale_cdata.ale_tx_cnt = 0; 1934 1935 memset(sc->ale_cdata.ale_tx_ring, 0, ALE_TX_RING_SZ); 1936 memset(sc->ale_cdata.ale_tx_cmb, 0, ALE_TX_CMB_SZ); 1937 for (i = 0; i < ALE_TX_RING_CNT; i++) { 1938 txd = &sc->ale_cdata.ale_txdesc[i]; 1939 txd->tx_m = NULL; 1940 } 1941 *sc->ale_cdata.ale_tx_cmb = 0; 1942 bus_dmamap_sync(sc->sc_dmat, sc->ale_cdata.ale_tx_cmb_map, 0, 1943 sc->ale_cdata.ale_tx_cmb_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 1944 bus_dmamap_sync(sc->sc_dmat, sc->ale_cdata.ale_tx_ring_map, 0, 1945 sc->ale_cdata.ale_tx_ring_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 1946 } 1947 1948 static void 1949 ale_init_rx_pages(struct ale_softc *sc) 1950 { 1951 struct ale_rx_page *rx_page; 1952 int i; 1953 1954 sc->ale_cdata.ale_rx_seqno = 0; 1955 sc->ale_cdata.ale_rx_curp = 0; 1956 1957 for (i = 0; i < ALE_RX_PAGES; i++) { 1958 rx_page = &sc->ale_cdata.ale_rx_page[i]; 1959 memset(rx_page->page_addr, 0, sc->ale_pagesize); 1960 memset(rx_page->cmb_addr, 0, ALE_RX_CMB_SZ); 1961 rx_page->cons = 0; 1962 *rx_page->cmb_addr = 0; 1963 bus_dmamap_sync(sc->sc_dmat, rx_page->page_map, 0, 1964 rx_page->page_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 1965 bus_dmamap_sync(sc->sc_dmat, rx_page->cmb_map, 0, 1966 rx_page->cmb_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 1967 } 1968 } 1969 1970 static void 1971 ale_rxvlan(struct ale_softc *sc) 1972 { 1973 uint32_t reg; 1974 1975 reg = CSR_READ_4(sc, ALE_MAC_CFG); 1976 reg &= ~MAC_CFG_VLAN_TAG_STRIP; 1977 if (sc->sc_ec.ec_capenable & ETHERCAP_VLAN_HWTAGGING) 1978 reg |= MAC_CFG_VLAN_TAG_STRIP; 1979 CSR_WRITE_4(sc, ALE_MAC_CFG, reg); 1980 } 1981 1982 static void 1983 ale_rxfilter(struct ale_softc *sc) 1984 { 1985 struct ethercom *ec = &sc->sc_ec; 1986 struct ifnet *ifp = &ec->ec_if; 1987 struct ether_multi *enm; 1988 struct ether_multistep step; 1989 uint32_t crc; 1990 uint32_t mchash[2]; 1991 uint32_t rxcfg; 1992 1993 rxcfg = CSR_READ_4(sc, ALE_MAC_CFG); 1994 rxcfg &= ~(MAC_CFG_ALLMULTI | MAC_CFG_BCAST | MAC_CFG_PROMISC); 1995 ifp->if_flags &= ~IFF_ALLMULTI; 1996 1997 /* 1998 * Always accept broadcast frames. 1999 */ 2000 rxcfg |= MAC_CFG_BCAST; 2001 2002 if (ifp->if_flags & IFF_PROMISC || ec->ec_multicnt > 0) { 2003 ifp->if_flags |= IFF_ALLMULTI; 2004 if (ifp->if_flags & IFF_PROMISC) 2005 rxcfg |= MAC_CFG_PROMISC; 2006 else 2007 rxcfg |= MAC_CFG_ALLMULTI; 2008 mchash[0] = mchash[1] = 0xFFFFFFFF; 2009 } else { 2010 /* Program new filter. */ 2011 memset(mchash, 0, sizeof(mchash)); 2012 2013 ETHER_FIRST_MULTI(step, ec, enm); 2014 while (enm != NULL) { 2015 crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 2016 mchash[crc >> 31] |= 1 << ((crc >> 26) & 0x1f); 2017 ETHER_NEXT_MULTI(step, enm); 2018 } 2019 } 2020 2021 CSR_WRITE_4(sc, ALE_MAR0, mchash[0]); 2022 CSR_WRITE_4(sc, ALE_MAR1, mchash[1]); 2023 CSR_WRITE_4(sc, ALE_MAC_CFG, rxcfg); 2024 } 2025
Indexes created Tue Sep 30 11:09:46 GMT 2025