if_ale.c revision 1.32
1 /* $NetBSD: if_ale.c,v 1.32 2019/05/28 09:24:33 msaitoh Exp $ */ 2 3 /*- 4 * Copyright (c) 2008, Pyun YongHyeon <yongari (at) FreeBSD.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice unmodified, this list of conditions, and the following 12 * disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * 29 * $FreeBSD: src/sys/dev/ale/if_ale.c,v 1.3 2008/12/03 09:01:12 yongari Exp $ 30 */ 31 32 /* Driver for Atheros AR8121/AR8113/AR8114 PCIe Ethernet. */ 33 34 #include <sys/cdefs.h> 35 __KERNEL_RCSID(0, "$NetBSD: if_ale.c,v 1.32 2019/05/28 09:24:33 msaitoh Exp $"); 36 37 #include "vlan.h" 38 39 #include <sys/param.h> 40 #include <sys/proc.h> 41 #include <sys/endian.h> 42 #include <sys/systm.h> 43 #include <sys/types.h> 44 #include <sys/sockio.h> 45 #include <sys/mbuf.h> 46 #include <sys/queue.h> 47 #include <sys/kernel.h> 48 #include <sys/device.h> 49 #include <sys/callout.h> 50 #include <sys/socket.h> 51 52 #include <sys/bus.h> 53 54 #include <net/if.h> 55 #include <net/if_dl.h> 56 #include <net/if_llc.h> 57 #include <net/if_media.h> 58 #include <net/if_ether.h> 59 60 #ifdef INET 61 #include <netinet/in.h> 62 #include <netinet/in_systm.h> 63 #include <netinet/in_var.h> 64 #include <netinet/ip.h> 65 #endif 66 67 #include <net/if_types.h> 68 #include <net/if_vlanvar.h> 69 70 #include <net/bpf.h> 71 72 #include <dev/mii/mii.h> 73 #include <dev/mii/miivar.h> 74 75 #include <dev/pci/pcireg.h> 76 #include <dev/pci/pcivar.h> 77 #include <dev/pci/pcidevs.h> 78 79 #include <dev/pci/if_alereg.h> 80 81 static int ale_match(device_t, cfdata_t, void *); 82 static void ale_attach(device_t, device_t, void *); 83 static int ale_detach(device_t, int); 84 85 static int ale_miibus_readreg(device_t, int, int, uint16_t *); 86 static int ale_miibus_writereg(device_t, int, int, uint16_t); 87 static void ale_miibus_statchg(struct ifnet *); 88 89 static int ale_init(struct ifnet *); 90 static void ale_start(struct ifnet *); 91 static int ale_ioctl(struct ifnet *, u_long, void *); 92 static void ale_watchdog(struct ifnet *); 93 static int ale_mediachange(struct ifnet *); 94 static void ale_mediastatus(struct ifnet *, struct ifmediareq *); 95 96 static int ale_intr(void *); 97 static int ale_rxeof(struct ale_softc *sc); 98 static void ale_rx_update_page(struct ale_softc *, struct ale_rx_page **, 99 uint32_t, uint32_t *); 100 static void ale_rxcsum(struct ale_softc *, struct mbuf *, uint32_t); 101 static void ale_txeof(struct ale_softc *); 102 103 static int ale_dma_alloc(struct ale_softc *); 104 static void ale_dma_free(struct ale_softc *); 105 static int ale_encap(struct ale_softc *, struct mbuf **); 106 static void ale_init_rx_pages(struct ale_softc *); 107 static void ale_init_tx_ring(struct ale_softc *); 108 109 static void ale_stop(struct ifnet *, int); 110 static void ale_tick(void *); 111 static void ale_get_macaddr(struct ale_softc *); 112 static void ale_mac_config(struct ale_softc *); 113 static void ale_phy_reset(struct ale_softc *); 114 static void ale_reset(struct ale_softc *); 115 static void ale_rxfilter(struct ale_softc *); 116 static void ale_rxvlan(struct ale_softc *); 117 static void ale_stats_clear(struct ale_softc *); 118 static void ale_stats_update(struct ale_softc *); 119 static void ale_stop_mac(struct ale_softc *); 120 121 CFATTACH_DECL_NEW(ale, sizeof(struct ale_softc), 122 ale_match, ale_attach, ale_detach, NULL); 123 124 int aledebug = 0; 125 #define DPRINTF(x) do { if (aledebug) printf x; } while (0) 126 127 #define ALE_CSUM_FEATURES (M_CSUM_TCPv4 | M_CSUM_UDPv4) 128 129 static int 130 ale_miibus_readreg(device_t dev, int phy, int reg, uint16_t *val) 131 { 132 struct ale_softc *sc = device_private(dev); 133 uint32_t v; 134 int i; 135 136 if (phy != sc->ale_phyaddr) 137 return -1; 138 139 if (sc->ale_flags & ALE_FLAG_FASTETHER) { 140 switch (reg) { 141 case MII_100T2CR: 142 case MII_100T2SR: 143 case MII_EXTSR: 144 *val = 0; 145 return 0; 146 default: 147 break; 148 } 149 } 150 151 CSR_WRITE_4(sc, ALE_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ | 152 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); 153 for (i = ALE_PHY_TIMEOUT; i > 0; i--) { 154 DELAY(5); 155 v = CSR_READ_4(sc, ALE_MDIO); 156 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) 157 break; 158 } 159 160 if (i == 0) { 161 printf("%s: phy read timeout: phy %d, reg %d\n", 162 device_xname(sc->sc_dev), phy, reg); 163 return ETIMEDOUT; 164 } 165 166 *val = (v & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT; 167 return 0; 168 } 169 170 static int 171 ale_miibus_writereg(device_t dev, int phy, int reg, uint16_t val) 172 { 173 struct ale_softc *sc = device_private(dev); 174 uint32_t v; 175 int i; 176 177 if (phy != sc->ale_phyaddr) 178 return -1; 179 180 if (sc->ale_flags & ALE_FLAG_FASTETHER) { 181 switch (reg) { 182 case MII_100T2CR: 183 case MII_100T2SR: 184 case MII_EXTSR: 185 return 0; 186 default: 187 break; 188 } 189 } 190 191 CSR_WRITE_4(sc, ALE_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE | 192 (val & MDIO_DATA_MASK) << MDIO_DATA_SHIFT | 193 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); 194 for (i = ALE_PHY_TIMEOUT; i > 0; i--) { 195 DELAY(5); 196 v = CSR_READ_4(sc, ALE_MDIO); 197 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) 198 break; 199 } 200 201 if (i == 0) { 202 printf("%s: phy write timeout: phy %d, reg %d\n", 203 device_xname(sc->sc_dev), phy, reg); 204 return ETIMEDOUT; 205 } 206 207 return 0; 208 } 209 210 static void 211 ale_miibus_statchg(struct ifnet *ifp) 212 { 213 struct ale_softc *sc = ifp->if_softc; 214 struct mii_data *mii = &sc->sc_miibus; 215 uint32_t reg; 216 217 if ((ifp->if_flags & IFF_RUNNING) == 0) 218 return; 219 220 sc->ale_flags &= ~ALE_FLAG_LINK; 221 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 222 (IFM_ACTIVE | IFM_AVALID)) { 223 switch (IFM_SUBTYPE(mii->mii_media_active)) { 224 case IFM_10_T: 225 case IFM_100_TX: 226 sc->ale_flags |= ALE_FLAG_LINK; 227 break; 228 229 case IFM_1000_T: 230 if ((sc->ale_flags & ALE_FLAG_FASTETHER) == 0) 231 sc->ale_flags |= ALE_FLAG_LINK; 232 break; 233 234 default: 235 break; 236 } 237 } 238 239 /* Stop Rx/Tx MACs. */ 240 ale_stop_mac(sc); 241 242 /* Program MACs with resolved speed/duplex/flow-control. */ 243 if ((sc->ale_flags & ALE_FLAG_LINK) != 0) { 244 ale_mac_config(sc); 245 /* Reenable Tx/Rx MACs. */ 246 reg = CSR_READ_4(sc, ALE_MAC_CFG); 247 reg |= MAC_CFG_TX_ENB | MAC_CFG_RX_ENB; 248 CSR_WRITE_4(sc, ALE_MAC_CFG, reg); 249 } 250 } 251 252 void 253 ale_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 254 { 255 struct ale_softc *sc = ifp->if_softc; 256 struct mii_data *mii = &sc->sc_miibus; 257 258 mii_pollstat(mii); 259 ifmr->ifm_status = mii->mii_media_status; 260 ifmr->ifm_active = mii->mii_media_active; 261 } 262 263 int 264 ale_mediachange(struct ifnet *ifp) 265 { 266 struct ale_softc *sc = ifp->if_softc; 267 struct mii_data *mii = &sc->sc_miibus; 268 int error; 269 270 if (mii->mii_instance != 0) { 271 struct mii_softc *miisc; 272 273 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 274 mii_phy_reset(miisc); 275 } 276 error = mii_mediachg(mii); 277 278 return error; 279 } 280 281 int 282 ale_match(device_t dev, cfdata_t match, void *aux) 283 { 284 struct pci_attach_args *pa = aux; 285 286 return (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_ATTANSIC && 287 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_ATTANSIC_ETHERNET_L1E); 288 } 289 290 void 291 ale_get_macaddr(struct ale_softc *sc) 292 { 293 uint32_t ea[2], reg; 294 int i, vpdc; 295 296 reg = CSR_READ_4(sc, ALE_SPI_CTRL); 297 if ((reg & SPI_VPD_ENB) != 0) { 298 reg &= ~SPI_VPD_ENB; 299 CSR_WRITE_4(sc, ALE_SPI_CTRL, reg); 300 } 301 302 if (pci_get_capability(sc->sc_pct, sc->sc_pcitag, PCI_CAP_VPD, 303 &vpdc, NULL)) { 304 /* 305 * PCI VPD capability found, let TWSI reload EEPROM. 306 * This will set ethernet address of controller. 307 */ 308 CSR_WRITE_4(sc, ALE_TWSI_CTRL, CSR_READ_4(sc, ALE_TWSI_CTRL) | 309 TWSI_CTRL_SW_LD_START); 310 for (i = 100; i > 0; i--) { 311 DELAY(1000); 312 reg = CSR_READ_4(sc, ALE_TWSI_CTRL); 313 if ((reg & TWSI_CTRL_SW_LD_START) == 0) 314 break; 315 } 316 if (i == 0) 317 printf("%s: reloading EEPROM timeout!\n", 318 device_xname(sc->sc_dev)); 319 } else { 320 if (aledebug) 321 printf("%s: PCI VPD capability not found!\n", 322 device_xname(sc->sc_dev)); 323 } 324 325 ea[0] = CSR_READ_4(sc, ALE_PAR0); 326 ea[1] = CSR_READ_4(sc, ALE_PAR1); 327 sc->ale_eaddr[0] = (ea[1] >> 8) & 0xFF; 328 sc->ale_eaddr[1] = (ea[1] >> 0) & 0xFF; 329 sc->ale_eaddr[2] = (ea[0] >> 24) & 0xFF; 330 sc->ale_eaddr[3] = (ea[0] >> 16) & 0xFF; 331 sc->ale_eaddr[4] = (ea[0] >> 8) & 0xFF; 332 sc->ale_eaddr[5] = (ea[0] >> 0) & 0xFF; 333 } 334 335 void 336 ale_phy_reset(struct ale_softc *sc) 337 { 338 /* Reset magic from Linux. */ 339 CSR_WRITE_2(sc, ALE_GPHY_CTRL, 340 GPHY_CTRL_HIB_EN | GPHY_CTRL_HIB_PULSE | GPHY_CTRL_SEL_ANA_RESET | 341 GPHY_CTRL_PHY_PLL_ON); 342 DELAY(1000); 343 CSR_WRITE_2(sc, ALE_GPHY_CTRL, 344 GPHY_CTRL_EXT_RESET | GPHY_CTRL_HIB_EN | GPHY_CTRL_HIB_PULSE | 345 GPHY_CTRL_SEL_ANA_RESET | GPHY_CTRL_PHY_PLL_ON); 346 DELAY(1000); 347 348 #define ATPHY_DBG_ADDR 0x1D 349 #define ATPHY_DBG_DATA 0x1E 350 351 /* Enable hibernation mode. */ 352 ale_miibus_writereg(sc->sc_dev, sc->ale_phyaddr, 353 ATPHY_DBG_ADDR, 0x0B); 354 ale_miibus_writereg(sc->sc_dev, sc->ale_phyaddr, 355 ATPHY_DBG_DATA, 0xBC00); 356 /* Set Class A/B for all modes. */ 357 ale_miibus_writereg(sc->sc_dev, sc->ale_phyaddr, 358 ATPHY_DBG_ADDR, 0x00); 359 ale_miibus_writereg(sc->sc_dev, sc->ale_phyaddr, 360 ATPHY_DBG_DATA, 0x02EF); 361 /* Enable 10BT power saving. */ 362 ale_miibus_writereg(sc->sc_dev, sc->ale_phyaddr, 363 ATPHY_DBG_ADDR, 0x12); 364 ale_miibus_writereg(sc->sc_dev, sc->ale_phyaddr, 365 ATPHY_DBG_DATA, 0x4C04); 366 /* Adjust 1000T power. */ 367 ale_miibus_writereg(sc->sc_dev, sc->ale_phyaddr, 368 ATPHY_DBG_ADDR, 0x04); 369 ale_miibus_writereg(sc->sc_dev, sc->ale_phyaddr, 370 ATPHY_DBG_DATA, 0x8BBB); 371 /* 10BT center tap voltage. */ 372 ale_miibus_writereg(sc->sc_dev, sc->ale_phyaddr, 373 ATPHY_DBG_ADDR, 0x05); 374 ale_miibus_writereg(sc->sc_dev, sc->ale_phyaddr, 375 ATPHY_DBG_DATA, 0x2C46); 376 377 #undef ATPHY_DBG_ADDR 378 #undef ATPHY_DBG_DATA 379 DELAY(1000); 380 } 381 382 void 383 ale_attach(device_t parent, device_t self, void *aux) 384 { 385 struct ale_softc *sc = device_private(self); 386 struct pci_attach_args *pa = aux; 387 pci_chipset_tag_t pc = pa->pa_pc; 388 pci_intr_handle_t ih; 389 const char *intrstr; 390 struct ifnet *ifp; 391 struct mii_data * const mii = &sc->sc_miibus; 392 pcireg_t memtype; 393 int mii_flags, error = 0; 394 uint32_t rxf_len, txf_len; 395 const char *chipname; 396 char intrbuf[PCI_INTRSTR_LEN]; 397 398 aprint_naive("\n"); 399 aprint_normal(": Attansic/Atheros L1E Ethernet\n"); 400 401 sc->sc_dev = self; 402 sc->sc_dmat = pa->pa_dmat; 403 sc->sc_pct = pa->pa_pc; 404 sc->sc_pcitag = pa->pa_tag; 405 406 /* 407 * Allocate IO memory 408 */ 409 memtype = pci_mapreg_type(sc->sc_pct, sc->sc_pcitag, ALE_PCIR_BAR); 410 switch (memtype) { 411 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 412 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT_1M: 413 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 414 break; 415 default: 416 aprint_error_dev(self, "invalid base address register\n"); 417 break; 418 } 419 420 if (pci_mapreg_map(pa, ALE_PCIR_BAR, memtype, 0, &sc->sc_mem_bt, 421 &sc->sc_mem_bh, NULL, &sc->sc_mem_size)) { 422 aprint_error_dev(self, "could not map mem space\n"); 423 return; 424 } 425 426 if (pci_intr_map(pa, &ih) != 0) { 427 aprint_error_dev(self, "could not map interrupt\n"); 428 goto fail; 429 } 430 431 /* 432 * Allocate IRQ 433 */ 434 intrstr = pci_intr_string(sc->sc_pct, ih, intrbuf, sizeof(intrbuf)); 435 sc->sc_irq_handle = pci_intr_establish_xname(pc, ih, IPL_NET, ale_intr, 436 sc, device_xname(self)); 437 if (sc->sc_irq_handle == NULL) { 438 aprint_error_dev(self, "could not establish interrupt"); 439 if (intrstr != NULL) 440 aprint_error(" at %s", intrstr); 441 aprint_error("\n"); 442 goto fail; 443 } 444 445 /* Set PHY address. */ 446 sc->ale_phyaddr = ALE_PHY_ADDR; 447 448 /* Reset PHY. */ 449 ale_phy_reset(sc); 450 451 /* Reset the ethernet controller. */ 452 ale_reset(sc); 453 454 /* Get PCI and chip id/revision. */ 455 sc->ale_rev = PCI_REVISION(pa->pa_class); 456 if (sc->ale_rev >= 0xF0) { 457 /* L2E Rev. B. AR8114 */ 458 sc->ale_flags |= ALE_FLAG_FASTETHER; 459 chipname = "AR8114 (L2E RevB)"; 460 } else { 461 if ((CSR_READ_4(sc, ALE_PHY_STATUS) & PHY_STATUS_100M) != 0) { 462 /* L1E AR8121 */ 463 sc->ale_flags |= ALE_FLAG_JUMBO; 464 chipname = "AR8121 (L1E)"; 465 } else { 466 /* L2E Rev. A. AR8113 */ 467 sc->ale_flags |= ALE_FLAG_FASTETHER; 468 chipname = "AR8113 (L2E RevA)"; 469 } 470 } 471 aprint_normal_dev(self, "%s, %s\n", chipname, intrstr); 472 473 /* 474 * All known controllers seems to require 4 bytes alignment 475 * of Tx buffers to make Tx checksum offload with custom 476 * checksum generation method work. 477 */ 478 sc->ale_flags |= ALE_FLAG_TXCSUM_BUG; 479 480 /* 481 * All known controllers seems to have issues on Rx checksum 482 * offload for fragmented IP datagrams. 483 */ 484 sc->ale_flags |= ALE_FLAG_RXCSUM_BUG; 485 486 /* 487 * Don't use Tx CMB. It is known to cause RRS update failure 488 * under certain circumstances. Typical phenomenon of the 489 * issue would be unexpected sequence number encountered in 490 * Rx handler. 491 */ 492 sc->ale_flags |= ALE_FLAG_TXCMB_BUG; 493 sc->ale_chip_rev = CSR_READ_4(sc, ALE_MASTER_CFG) >> 494 MASTER_CHIP_REV_SHIFT; 495 aprint_debug_dev(self, "PCI device revision : 0x%04x\n", sc->ale_rev); 496 aprint_debug_dev(self, "Chip id/revision : 0x%04x\n", sc->ale_chip_rev); 497 498 /* 499 * Uninitialized hardware returns an invalid chip id/revision 500 * as well as 0xFFFFFFFF for Tx/Rx fifo length. 501 */ 502 txf_len = CSR_READ_4(sc, ALE_SRAM_TX_FIFO_LEN); 503 rxf_len = CSR_READ_4(sc, ALE_SRAM_RX_FIFO_LEN); 504 if (sc->ale_chip_rev == 0xFFFF || txf_len == 0xFFFFFFFF || 505 rxf_len == 0xFFFFFFF) { 506 aprint_error_dev(self, "chip revision : 0x%04x, %u Tx FIFO " 507 "%u Rx FIFO -- not initialized?\n", 508 sc->ale_chip_rev, txf_len, rxf_len); 509 goto fail; 510 } 511 512 if (aledebug) { 513 printf("%s: %u Tx FIFO, %u Rx FIFO\n", device_xname(sc->sc_dev), 514 txf_len, rxf_len); 515 } 516 517 /* Set max allowable DMA size. */ 518 sc->ale_dma_rd_burst = DMA_CFG_RD_BURST_128; 519 sc->ale_dma_wr_burst = DMA_CFG_WR_BURST_128; 520 521 callout_init(&sc->sc_tick_ch, 0); 522 callout_setfunc(&sc->sc_tick_ch, ale_tick, sc); 523 524 error = ale_dma_alloc(sc); 525 if (error) 526 goto fail; 527 528 /* Load station address. */ 529 ale_get_macaddr(sc); 530 531 aprint_normal_dev(self, "Ethernet address %s\n", 532 ether_sprintf(sc->ale_eaddr)); 533 534 ifp = &sc->sc_ec.ec_if; 535 ifp->if_softc = sc; 536 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 537 ifp->if_init = ale_init; 538 ifp->if_ioctl = ale_ioctl; 539 ifp->if_start = ale_start; 540 ifp->if_stop = ale_stop; 541 ifp->if_watchdog = ale_watchdog; 542 IFQ_SET_MAXLEN(&ifp->if_snd, ALE_TX_RING_CNT - 1); 543 IFQ_SET_READY(&ifp->if_snd); 544 strlcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 545 546 sc->sc_ec.ec_capabilities = ETHERCAP_VLAN_MTU; 547 548 #ifdef ALE_CHECKSUM 549 ifp->if_capabilities |= IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 550 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 551 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 552 #endif 553 554 #if NVLAN > 0 555 sc->sc_ec.ec_capabilities |= ETHERCAP_VLAN_HWTAGGING; 556 #endif 557 558 /* Set up MII bus. */ 559 mii->mii_ifp = ifp; 560 mii->mii_readreg = ale_miibus_readreg; 561 mii->mii_writereg = ale_miibus_writereg; 562 mii->mii_statchg = ale_miibus_statchg; 563 564 sc->sc_ec.ec_mii = mii; 565 ifmedia_init(&mii->mii_media, 0, ale_mediachange, ale_mediastatus); 566 mii_flags = 0; 567 if ((sc->ale_flags & ALE_FLAG_JUMBO) != 0) 568 mii_flags |= MIIF_DOPAUSE; 569 mii_attach(self, mii, 0xffffffff, MII_PHY_ANY, 570 MII_OFFSET_ANY, mii_flags); 571 572 if (LIST_FIRST(&mii->mii_phys) == NULL) { 573 aprint_error_dev(self, "no PHY found!\n"); 574 ifmedia_add(&mii->mii_media, IFM_ETHER | IFM_MANUAL, 0, NULL); 575 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_MANUAL); 576 } else 577 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_AUTO); 578 579 if_attach(ifp); 580 if_deferred_start_init(ifp, NULL); 581 ether_ifattach(ifp, sc->ale_eaddr); 582 583 if (pmf_device_register(self, NULL, NULL)) 584 pmf_class_network_register(self, ifp); 585 else 586 aprint_error_dev(self, "couldn't establish power handler\n"); 587 588 return; 589 fail: 590 ale_dma_free(sc); 591 if (sc->sc_irq_handle != NULL) { 592 pci_intr_disestablish(pc, sc->sc_irq_handle); 593 sc->sc_irq_handle = NULL; 594 } 595 if (sc->sc_mem_size) { 596 bus_space_unmap(sc->sc_mem_bt, sc->sc_mem_bh, sc->sc_mem_size); 597 sc->sc_mem_size = 0; 598 } 599 } 600 601 static int 602 ale_detach(device_t self, int flags) 603 { 604 struct ale_softc *sc = device_private(self); 605 struct ifnet *ifp = &sc->sc_ec.ec_if; 606 int s; 607 608 pmf_device_deregister(self); 609 s = splnet(); 610 ale_stop(ifp, 0); 611 splx(s); 612 613 mii_detach(&sc->sc_miibus, MII_PHY_ANY, MII_OFFSET_ANY); 614 615 /* Delete all remaining media. */ 616 ifmedia_delete_instance(&sc->sc_miibus.mii_media, IFM_INST_ANY); 617 618 ether_ifdetach(ifp); 619 if_detach(ifp); 620 ale_dma_free(sc); 621 622 if (sc->sc_irq_handle != NULL) { 623 pci_intr_disestablish(sc->sc_pct, sc->sc_irq_handle); 624 sc->sc_irq_handle = NULL; 625 } 626 if (sc->sc_mem_size) { 627 bus_space_unmap(sc->sc_mem_bt, sc->sc_mem_bh, sc->sc_mem_size); 628 sc->sc_mem_size = 0; 629 } 630 631 return 0; 632 } 633 634 635 static int 636 ale_dma_alloc(struct ale_softc *sc) 637 { 638 struct ale_txdesc *txd; 639 int nsegs, error, guard_size, i; 640 641 if ((sc->ale_flags & ALE_FLAG_JUMBO) != 0) 642 guard_size = ALE_JUMBO_FRAMELEN; 643 else 644 guard_size = ALE_MAX_FRAMELEN; 645 sc->ale_pagesize = roundup(guard_size + ALE_RX_PAGE_SZ, 646 ALE_RX_PAGE_ALIGN); 647 648 /* 649 * Create DMA stuffs for TX ring 650 */ 651 error = bus_dmamap_create(sc->sc_dmat, ALE_TX_RING_SZ, 1, 652 ALE_TX_RING_SZ, 0, BUS_DMA_NOWAIT, &sc->ale_cdata.ale_tx_ring_map); 653 if (error) { 654 sc->ale_cdata.ale_tx_ring_map = NULL; 655 return ENOBUFS; 656 } 657 658 /* Allocate DMA'able memory for TX ring */ 659 error = bus_dmamem_alloc(sc->sc_dmat, ALE_TX_RING_SZ, 660 0, 0, &sc->ale_cdata.ale_tx_ring_seg, 1, 661 &nsegs, BUS_DMA_WAITOK); 662 if (error) { 663 printf("%s: could not allocate DMA'able memory for Tx ring, " 664 "error = %i\n", device_xname(sc->sc_dev), error); 665 return error; 666 } 667 668 error = bus_dmamem_map(sc->sc_dmat, &sc->ale_cdata.ale_tx_ring_seg, 669 nsegs, ALE_TX_RING_SZ, (void **)&sc->ale_cdata.ale_tx_ring, 670 BUS_DMA_NOWAIT); 671 if (error) 672 return ENOBUFS; 673 674 memset(sc->ale_cdata.ale_tx_ring, 0, ALE_TX_RING_SZ); 675 676 /* Load the DMA map for Tx ring. */ 677 error = bus_dmamap_load(sc->sc_dmat, sc->ale_cdata.ale_tx_ring_map, 678 sc->ale_cdata.ale_tx_ring, ALE_TX_RING_SZ, NULL, BUS_DMA_WAITOK); 679 if (error) { 680 printf("%s: could not load DMA'able memory for Tx ring.\n", 681 device_xname(sc->sc_dev)); 682 bus_dmamem_free(sc->sc_dmat, 683 &sc->ale_cdata.ale_tx_ring_seg, 1); 684 return error; 685 } 686 sc->ale_cdata.ale_tx_ring_paddr = 687 sc->ale_cdata.ale_tx_ring_map->dm_segs[0].ds_addr; 688 689 for (i = 0; i < ALE_RX_PAGES; i++) { 690 /* 691 * Create DMA stuffs for RX pages 692 */ 693 error = bus_dmamap_create(sc->sc_dmat, sc->ale_pagesize, 1, 694 sc->ale_pagesize, 0, BUS_DMA_NOWAIT, 695 &sc->ale_cdata.ale_rx_page[i].page_map); 696 if (error) { 697 sc->ale_cdata.ale_rx_page[i].page_map = NULL; 698 return ENOBUFS; 699 } 700 701 /* Allocate DMA'able memory for RX pages */ 702 error = bus_dmamem_alloc(sc->sc_dmat, sc->ale_pagesize, 703 ETHER_ALIGN, 0, &sc->ale_cdata.ale_rx_page[i].page_seg, 704 1, &nsegs, BUS_DMA_WAITOK); 705 if (error) { 706 printf("%s: could not allocate DMA'able memory for " 707 "Rx ring.\n", device_xname(sc->sc_dev)); 708 return error; 709 } 710 error = bus_dmamem_map(sc->sc_dmat, 711 &sc->ale_cdata.ale_rx_page[i].page_seg, nsegs, 712 sc->ale_pagesize, 713 (void **)&sc->ale_cdata.ale_rx_page[i].page_addr, 714 BUS_DMA_NOWAIT); 715 if (error) 716 return ENOBUFS; 717 718 memset(sc->ale_cdata.ale_rx_page[i].page_addr, 0, 719 sc->ale_pagesize); 720 721 /* Load the DMA map for Rx pages. */ 722 error = bus_dmamap_load(sc->sc_dmat, 723 sc->ale_cdata.ale_rx_page[i].page_map, 724 sc->ale_cdata.ale_rx_page[i].page_addr, 725 sc->ale_pagesize, NULL, BUS_DMA_WAITOK); 726 if (error) { 727 printf("%s: could not load DMA'able memory for " 728 "Rx pages.\n", device_xname(sc->sc_dev)); 729 bus_dmamem_free(sc->sc_dmat, 730 &sc->ale_cdata.ale_rx_page[i].page_seg, 1); 731 return error; 732 } 733 sc->ale_cdata.ale_rx_page[i].page_paddr = 734 sc->ale_cdata.ale_rx_page[i].page_map->dm_segs[0].ds_addr; 735 } 736 737 /* 738 * Create DMA stuffs for Tx CMB. 739 */ 740 error = bus_dmamap_create(sc->sc_dmat, ALE_TX_CMB_SZ, 1, 741 ALE_TX_CMB_SZ, 0, BUS_DMA_NOWAIT, &sc->ale_cdata.ale_tx_cmb_map); 742 if (error) { 743 sc->ale_cdata.ale_tx_cmb_map = NULL; 744 return ENOBUFS; 745 } 746 747 /* Allocate DMA'able memory for Tx CMB. */ 748 error = bus_dmamem_alloc(sc->sc_dmat, ALE_TX_CMB_SZ, ETHER_ALIGN, 0, 749 &sc->ale_cdata.ale_tx_cmb_seg, 1, &nsegs, BUS_DMA_WAITOK); 750 751 if (error) { 752 printf("%s: could not allocate DMA'able memory for Tx CMB.\n", 753 device_xname(sc->sc_dev)); 754 return error; 755 } 756 757 error = bus_dmamem_map(sc->sc_dmat, &sc->ale_cdata.ale_tx_cmb_seg, 758 nsegs, ALE_TX_CMB_SZ, (void **)&sc->ale_cdata.ale_tx_cmb, 759 BUS_DMA_NOWAIT); 760 if (error) 761 return ENOBUFS; 762 763 memset(sc->ale_cdata.ale_tx_cmb, 0, ALE_TX_CMB_SZ); 764 765 /* Load the DMA map for Tx CMB. */ 766 error = bus_dmamap_load(sc->sc_dmat, sc->ale_cdata.ale_tx_cmb_map, 767 sc->ale_cdata.ale_tx_cmb, ALE_TX_CMB_SZ, NULL, BUS_DMA_WAITOK); 768 if (error) { 769 printf("%s: could not load DMA'able memory for Tx CMB.\n", 770 device_xname(sc->sc_dev)); 771 bus_dmamem_free(sc->sc_dmat, 772 &sc->ale_cdata.ale_tx_cmb_seg, 1); 773 return error; 774 } 775 776 sc->ale_cdata.ale_tx_cmb_paddr = 777 sc->ale_cdata.ale_tx_cmb_map->dm_segs[0].ds_addr; 778 779 for (i = 0; i < ALE_RX_PAGES; i++) { 780 /* 781 * Create DMA stuffs for Rx CMB. 782 */ 783 error = bus_dmamap_create(sc->sc_dmat, ALE_RX_CMB_SZ, 1, 784 ALE_RX_CMB_SZ, 0, BUS_DMA_NOWAIT, 785 &sc->ale_cdata.ale_rx_page[i].cmb_map); 786 if (error) { 787 sc->ale_cdata.ale_rx_page[i].cmb_map = NULL; 788 return ENOBUFS; 789 } 790 791 /* Allocate DMA'able memory for Rx CMB */ 792 error = bus_dmamem_alloc(sc->sc_dmat, ALE_RX_CMB_SZ, 793 ETHER_ALIGN, 0, &sc->ale_cdata.ale_rx_page[i].cmb_seg, 1, 794 &nsegs, BUS_DMA_WAITOK); 795 if (error) { 796 printf("%s: could not allocate DMA'able memory for " 797 "Rx CMB\n", device_xname(sc->sc_dev)); 798 return error; 799 } 800 error = bus_dmamem_map(sc->sc_dmat, 801 &sc->ale_cdata.ale_rx_page[i].cmb_seg, nsegs, 802 ALE_RX_CMB_SZ, 803 (void **)&sc->ale_cdata.ale_rx_page[i].cmb_addr, 804 BUS_DMA_NOWAIT); 805 if (error) 806 return ENOBUFS; 807 808 memset(sc->ale_cdata.ale_rx_page[i].cmb_addr, 0, ALE_RX_CMB_SZ); 809 810 /* Load the DMA map for Rx CMB */ 811 error = bus_dmamap_load(sc->sc_dmat, 812 sc->ale_cdata.ale_rx_page[i].cmb_map, 813 sc->ale_cdata.ale_rx_page[i].cmb_addr, 814 ALE_RX_CMB_SZ, NULL, BUS_DMA_WAITOK); 815 if (error) { 816 printf("%s: could not load DMA'able memory for Rx CMB" 817 "\n", device_xname(sc->sc_dev)); 818 bus_dmamem_free(sc->sc_dmat, 819 &sc->ale_cdata.ale_rx_page[i].cmb_seg, 1); 820 return error; 821 } 822 sc->ale_cdata.ale_rx_page[i].cmb_paddr = 823 sc->ale_cdata.ale_rx_page[i].cmb_map->dm_segs[0].ds_addr; 824 } 825 826 827 /* Create DMA maps for Tx buffers. */ 828 for (i = 0; i < ALE_TX_RING_CNT; i++) { 829 txd = &sc->ale_cdata.ale_txdesc[i]; 830 txd->tx_m = NULL; 831 txd->tx_dmamap = NULL; 832 error = bus_dmamap_create(sc->sc_dmat, ALE_TSO_MAXSIZE, 833 ALE_MAXTXSEGS, ALE_TSO_MAXSEGSIZE, 0, BUS_DMA_NOWAIT, 834 &txd->tx_dmamap); 835 if (error) { 836 txd->tx_dmamap = NULL; 837 printf("%s: could not create Tx dmamap.\n", 838 device_xname(sc->sc_dev)); 839 return error; 840 } 841 } 842 843 return 0; 844 } 845 846 static void 847 ale_dma_free(struct ale_softc *sc) 848 { 849 struct ale_txdesc *txd; 850 int i; 851 852 /* Tx buffers. */ 853 for (i = 0; i < ALE_TX_RING_CNT; i++) { 854 txd = &sc->ale_cdata.ale_txdesc[i]; 855 if (txd->tx_dmamap != NULL) { 856 bus_dmamap_destroy(sc->sc_dmat, txd->tx_dmamap); 857 txd->tx_dmamap = NULL; 858 } 859 } 860 861 /* Tx descriptor ring. */ 862 if (sc->ale_cdata.ale_tx_ring_map != NULL) 863 bus_dmamap_unload(sc->sc_dmat, sc->ale_cdata.ale_tx_ring_map); 864 if (sc->ale_cdata.ale_tx_ring_map != NULL && 865 sc->ale_cdata.ale_tx_ring != NULL) 866 bus_dmamem_free(sc->sc_dmat, 867 &sc->ale_cdata.ale_tx_ring_seg, 1); 868 sc->ale_cdata.ale_tx_ring = NULL; 869 sc->ale_cdata.ale_tx_ring_map = NULL; 870 871 /* Rx page block. */ 872 for (i = 0; i < ALE_RX_PAGES; i++) { 873 if (sc->ale_cdata.ale_rx_page[i].page_map != NULL) 874 bus_dmamap_unload(sc->sc_dmat, 875 sc->ale_cdata.ale_rx_page[i].page_map); 876 if (sc->ale_cdata.ale_rx_page[i].page_map != NULL && 877 sc->ale_cdata.ale_rx_page[i].page_addr != NULL) 878 bus_dmamem_free(sc->sc_dmat, 879 &sc->ale_cdata.ale_rx_page[i].page_seg, 1); 880 sc->ale_cdata.ale_rx_page[i].page_addr = NULL; 881 sc->ale_cdata.ale_rx_page[i].page_map = NULL; 882 } 883 884 /* Rx CMB. */ 885 for (i = 0; i < ALE_RX_PAGES; i++) { 886 if (sc->ale_cdata.ale_rx_page[i].cmb_map != NULL) 887 bus_dmamap_unload(sc->sc_dmat, 888 sc->ale_cdata.ale_rx_page[i].cmb_map); 889 if (sc->ale_cdata.ale_rx_page[i].cmb_map != NULL && 890 sc->ale_cdata.ale_rx_page[i].cmb_addr != NULL) 891 bus_dmamem_free(sc->sc_dmat, 892 &sc->ale_cdata.ale_rx_page[i].cmb_seg, 1); 893 sc->ale_cdata.ale_rx_page[i].cmb_addr = NULL; 894 sc->ale_cdata.ale_rx_page[i].cmb_map = NULL; 895 } 896 897 /* Tx CMB. */ 898 if (sc->ale_cdata.ale_tx_cmb_map != NULL) 899 bus_dmamap_unload(sc->sc_dmat, sc->ale_cdata.ale_tx_cmb_map); 900 if (sc->ale_cdata.ale_tx_cmb_map != NULL && 901 sc->ale_cdata.ale_tx_cmb != NULL) 902 bus_dmamem_free(sc->sc_dmat, 903 &sc->ale_cdata.ale_tx_cmb_seg, 1); 904 sc->ale_cdata.ale_tx_cmb = NULL; 905 sc->ale_cdata.ale_tx_cmb_map = NULL; 906 907 } 908 909 static int 910 ale_encap(struct ale_softc *sc, struct mbuf **m_head) 911 { 912 struct ale_txdesc *txd, *txd_last; 913 struct tx_desc *desc; 914 struct mbuf *m; 915 bus_dmamap_t map; 916 uint32_t cflags, poff, vtag; 917 int error, i, nsegs, prod; 918 919 m = *m_head; 920 cflags = vtag = 0; 921 poff = 0; 922 923 prod = sc->ale_cdata.ale_tx_prod; 924 txd = &sc->ale_cdata.ale_txdesc[prod]; 925 txd_last = txd; 926 map = txd->tx_dmamap; 927 928 error = bus_dmamap_load_mbuf(sc->sc_dmat, map, *m_head, BUS_DMA_NOWAIT); 929 if (error == EFBIG) { 930 error = 0; 931 932 *m_head = m_pullup(*m_head, MHLEN); 933 if (*m_head == NULL) { 934 printf("%s: can't defrag TX mbuf\n", 935 device_xname(sc->sc_dev)); 936 return ENOBUFS; 937 } 938 939 error = bus_dmamap_load_mbuf(sc->sc_dmat, map, *m_head, 940 BUS_DMA_NOWAIT); 941 942 if (error != 0) { 943 printf("%s: could not load defragged TX mbuf\n", 944 device_xname(sc->sc_dev)); 945 m_freem(*m_head); 946 *m_head = NULL; 947 return error; 948 } 949 } else if (error) { 950 printf("%s: could not load TX mbuf\n", device_xname(sc->sc_dev)); 951 return error; 952 } 953 954 nsegs = map->dm_nsegs; 955 956 if (nsegs == 0) { 957 m_freem(*m_head); 958 *m_head = NULL; 959 return EIO; 960 } 961 962 /* Check descriptor overrun. */ 963 if (sc->ale_cdata.ale_tx_cnt + nsegs >= ALE_TX_RING_CNT - 2) { 964 bus_dmamap_unload(sc->sc_dmat, map); 965 return ENOBUFS; 966 } 967 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 968 BUS_DMASYNC_PREWRITE); 969 970 m = *m_head; 971 /* Configure Tx checksum offload. */ 972 if ((m->m_pkthdr.csum_flags & ALE_CSUM_FEATURES) != 0) { 973 /* 974 * AR81xx supports Tx custom checksum offload feature 975 * that offloads single 16bit checksum computation. 976 * So you can choose one among IP, TCP and UDP. 977 * Normally driver sets checksum start/insertion 978 * position from the information of TCP/UDP frame as 979 * TCP/UDP checksum takes more time than that of IP. 980 * However it seems that custom checksum offload 981 * requires 4 bytes aligned Tx buffers due to hardware 982 * bug. 983 * AR81xx also supports explicit Tx checksum computation 984 * if it is told that the size of IP header and TCP 985 * header(for UDP, the header size does not matter 986 * because it's fixed length). However with this scheme 987 * TSO does not work so you have to choose one either 988 * TSO or explicit Tx checksum offload. I chosen TSO 989 * plus custom checksum offload with work-around which 990 * will cover most common usage for this consumer 991 * ethernet controller. The work-around takes a lot of 992 * CPU cycles if Tx buffer is not aligned on 4 bytes 993 * boundary, though. 994 */ 995 cflags |= ALE_TD_CXSUM; 996 /* Set checksum start offset. */ 997 cflags |= (poff << ALE_TD_CSUM_PLOADOFFSET_SHIFT); 998 } 999 1000 #if NVLAN > 0 1001 /* Configure VLAN hardware tag insertion. */ 1002 if (vlan_has_tag(m)) { 1003 vtag = ALE_TX_VLAN_TAG(htons(vlan_get_tag(m))); 1004 vtag = ((vtag << ALE_TD_VLAN_SHIFT) & ALE_TD_VLAN_MASK); 1005 cflags |= ALE_TD_INSERT_VLAN_TAG; 1006 } 1007 #endif 1008 1009 desc = NULL; 1010 for (i = 0; i < nsegs; i++) { 1011 desc = &sc->ale_cdata.ale_tx_ring[prod]; 1012 desc->addr = htole64(map->dm_segs[i].ds_addr); 1013 desc->len = 1014 htole32(ALE_TX_BYTES(map->dm_segs[i].ds_len) | vtag); 1015 desc->flags = htole32(cflags); 1016 sc->ale_cdata.ale_tx_cnt++; 1017 ALE_DESC_INC(prod, ALE_TX_RING_CNT); 1018 } 1019 /* Update producer index. */ 1020 sc->ale_cdata.ale_tx_prod = prod; 1021 1022 /* Finally set EOP on the last descriptor. */ 1023 prod = (prod + ALE_TX_RING_CNT - 1) % ALE_TX_RING_CNT; 1024 desc = &sc->ale_cdata.ale_tx_ring[prod]; 1025 desc->flags |= htole32(ALE_TD_EOP); 1026 1027 /* Swap dmamap of the first and the last. */ 1028 txd = &sc->ale_cdata.ale_txdesc[prod]; 1029 map = txd_last->tx_dmamap; 1030 txd_last->tx_dmamap = txd->tx_dmamap; 1031 txd->tx_dmamap = map; 1032 txd->tx_m = m; 1033 1034 /* Sync descriptors. */ 1035 bus_dmamap_sync(sc->sc_dmat, sc->ale_cdata.ale_tx_ring_map, 0, 1036 sc->ale_cdata.ale_tx_ring_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 1037 1038 return 0; 1039 } 1040 1041 static void 1042 ale_start(struct ifnet *ifp) 1043 { 1044 struct ale_softc *sc = ifp->if_softc; 1045 struct mbuf *m_head; 1046 int enq; 1047 1048 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 1049 return; 1050 1051 /* Reclaim transmitted frames. */ 1052 if (sc->ale_cdata.ale_tx_cnt >= ALE_TX_DESC_HIWAT) 1053 ale_txeof(sc); 1054 1055 enq = 0; 1056 for (;;) { 1057 IFQ_DEQUEUE(&ifp->if_snd, m_head); 1058 if (m_head == NULL) 1059 break; 1060 1061 /* 1062 * Pack the data into the transmit ring. If we 1063 * don't have room, set the OACTIVE flag and wait 1064 * for the NIC to drain the ring. 1065 */ 1066 if (ale_encap(sc, &m_head)) { 1067 if (m_head == NULL) 1068 break; 1069 IF_PREPEND(&ifp->if_snd, m_head); 1070 ifp->if_flags |= IFF_OACTIVE; 1071 break; 1072 } 1073 enq = 1; 1074 1075 /* 1076 * If there's a BPF listener, bounce a copy of this frame 1077 * to him. 1078 */ 1079 bpf_mtap(ifp, m_head, BPF_D_OUT); 1080 } 1081 1082 if (enq) { 1083 /* Kick. */ 1084 CSR_WRITE_4(sc, ALE_MBOX_TPD_PROD_IDX, 1085 sc->ale_cdata.ale_tx_prod); 1086 1087 /* Set a timeout in case the chip goes out to lunch. */ 1088 ifp->if_timer = ALE_TX_TIMEOUT; 1089 } 1090 } 1091 1092 static void 1093 ale_watchdog(struct ifnet *ifp) 1094 { 1095 struct ale_softc *sc = ifp->if_softc; 1096 1097 if ((sc->ale_flags & ALE_FLAG_LINK) == 0) { 1098 printf("%s: watchdog timeout (missed link)\n", 1099 device_xname(sc->sc_dev)); 1100 ifp->if_oerrors++; 1101 ale_init(ifp); 1102 return; 1103 } 1104 1105 printf("%s: watchdog timeout\n", device_xname(sc->sc_dev)); 1106 ifp->if_oerrors++; 1107 ale_init(ifp); 1108 1109 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 1110 ale_start(ifp); 1111 } 1112 1113 static int 1114 ale_ioctl(struct ifnet *ifp, u_long cmd, void *data) 1115 { 1116 struct ale_softc *sc = ifp->if_softc; 1117 int s, error; 1118 1119 s = splnet(); 1120 1121 error = ether_ioctl(ifp, cmd, data); 1122 if (error == ENETRESET) { 1123 if (ifp->if_flags & IFF_RUNNING) 1124 ale_rxfilter(sc); 1125 error = 0; 1126 } 1127 1128 splx(s); 1129 return error; 1130 } 1131 1132 static void 1133 ale_mac_config(struct ale_softc *sc) 1134 { 1135 struct mii_data *mii; 1136 uint32_t reg; 1137 1138 mii = &sc->sc_miibus; 1139 reg = CSR_READ_4(sc, ALE_MAC_CFG); 1140 reg &= ~(MAC_CFG_FULL_DUPLEX | MAC_CFG_TX_FC | MAC_CFG_RX_FC | 1141 MAC_CFG_SPEED_MASK); 1142 1143 /* Reprogram MAC with resolved speed/duplex. */ 1144 switch (IFM_SUBTYPE(mii->mii_media_active)) { 1145 case IFM_10_T: 1146 case IFM_100_TX: 1147 reg |= MAC_CFG_SPEED_10_100; 1148 break; 1149 case IFM_1000_T: 1150 reg |= MAC_CFG_SPEED_1000; 1151 break; 1152 } 1153 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 1154 reg |= MAC_CFG_FULL_DUPLEX; 1155 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0) 1156 reg |= MAC_CFG_TX_FC; 1157 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0) 1158 reg |= MAC_CFG_RX_FC; 1159 } 1160 CSR_WRITE_4(sc, ALE_MAC_CFG, reg); 1161 } 1162 1163 static void 1164 ale_stats_clear(struct ale_softc *sc) 1165 { 1166 struct smb sb; 1167 uint32_t *reg; 1168 int i; 1169 1170 for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered; reg++) { 1171 CSR_READ_4(sc, ALE_RX_MIB_BASE + i); 1172 i += sizeof(uint32_t); 1173 } 1174 /* Read Tx statistics. */ 1175 for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes; reg++) { 1176 CSR_READ_4(sc, ALE_TX_MIB_BASE + i); 1177 i += sizeof(uint32_t); 1178 } 1179 } 1180 1181 static void 1182 ale_stats_update(struct ale_softc *sc) 1183 { 1184 struct ifnet *ifp = &sc->sc_ec.ec_if; 1185 struct ale_hw_stats *stat; 1186 struct smb sb, *smb; 1187 uint32_t *reg; 1188 int i; 1189 1190 stat = &sc->ale_stats; 1191 smb = &sb; 1192 1193 /* Read Rx statistics. */ 1194 for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered; reg++) { 1195 *reg = CSR_READ_4(sc, ALE_RX_MIB_BASE + i); 1196 i += sizeof(uint32_t); 1197 } 1198 /* Read Tx statistics. */ 1199 for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes; reg++) { 1200 *reg = CSR_READ_4(sc, ALE_TX_MIB_BASE + i); 1201 i += sizeof(uint32_t); 1202 } 1203 1204 /* Rx stats. */ 1205 stat->rx_frames += smb->rx_frames; 1206 stat->rx_bcast_frames += smb->rx_bcast_frames; 1207 stat->rx_mcast_frames += smb->rx_mcast_frames; 1208 stat->rx_pause_frames += smb->rx_pause_frames; 1209 stat->rx_control_frames += smb->rx_control_frames; 1210 stat->rx_crcerrs += smb->rx_crcerrs; 1211 stat->rx_lenerrs += smb->rx_lenerrs; 1212 stat->rx_bytes += smb->rx_bytes; 1213 stat->rx_runts += smb->rx_runts; 1214 stat->rx_fragments += smb->rx_fragments; 1215 stat->rx_pkts_64 += smb->rx_pkts_64; 1216 stat->rx_pkts_65_127 += smb->rx_pkts_65_127; 1217 stat->rx_pkts_128_255 += smb->rx_pkts_128_255; 1218 stat->rx_pkts_256_511 += smb->rx_pkts_256_511; 1219 stat->rx_pkts_512_1023 += smb->rx_pkts_512_1023; 1220 stat->rx_pkts_1024_1518 += smb->rx_pkts_1024_1518; 1221 stat->rx_pkts_1519_max += smb->rx_pkts_1519_max; 1222 stat->rx_pkts_truncated += smb->rx_pkts_truncated; 1223 stat->rx_fifo_oflows += smb->rx_fifo_oflows; 1224 stat->rx_rrs_errs += smb->rx_rrs_errs; 1225 stat->rx_alignerrs += smb->rx_alignerrs; 1226 stat->rx_bcast_bytes += smb->rx_bcast_bytes; 1227 stat->rx_mcast_bytes += smb->rx_mcast_bytes; 1228 stat->rx_pkts_filtered += smb->rx_pkts_filtered; 1229 1230 /* Tx stats. */ 1231 stat->tx_frames += smb->tx_frames; 1232 stat->tx_bcast_frames += smb->tx_bcast_frames; 1233 stat->tx_mcast_frames += smb->tx_mcast_frames; 1234 stat->tx_pause_frames += smb->tx_pause_frames; 1235 stat->tx_excess_defer += smb->tx_excess_defer; 1236 stat->tx_control_frames += smb->tx_control_frames; 1237 stat->tx_deferred += smb->tx_deferred; 1238 stat->tx_bytes += smb->tx_bytes; 1239 stat->tx_pkts_64 += smb->tx_pkts_64; 1240 stat->tx_pkts_65_127 += smb->tx_pkts_65_127; 1241 stat->tx_pkts_128_255 += smb->tx_pkts_128_255; 1242 stat->tx_pkts_256_511 += smb->tx_pkts_256_511; 1243 stat->tx_pkts_512_1023 += smb->tx_pkts_512_1023; 1244 stat->tx_pkts_1024_1518 += smb->tx_pkts_1024_1518; 1245 stat->tx_pkts_1519_max += smb->tx_pkts_1519_max; 1246 stat->tx_single_colls += smb->tx_single_colls; 1247 stat->tx_multi_colls += smb->tx_multi_colls; 1248 stat->tx_late_colls += smb->tx_late_colls; 1249 stat->tx_excess_colls += smb->tx_excess_colls; 1250 stat->tx_abort += smb->tx_abort; 1251 stat->tx_underrun += smb->tx_underrun; 1252 stat->tx_desc_underrun += smb->tx_desc_underrun; 1253 stat->tx_lenerrs += smb->tx_lenerrs; 1254 stat->tx_pkts_truncated += smb->tx_pkts_truncated; 1255 stat->tx_bcast_bytes += smb->tx_bcast_bytes; 1256 stat->tx_mcast_bytes += smb->tx_mcast_bytes; 1257 1258 /* Update counters in ifnet. */ 1259 ifp->if_opackets += smb->tx_frames; 1260 1261 ifp->if_collisions += smb->tx_single_colls + 1262 smb->tx_multi_colls * 2 + smb->tx_late_colls + 1263 smb->tx_abort * HDPX_CFG_RETRY_DEFAULT; 1264 1265 /* 1266 * XXX 1267 * tx_pkts_truncated counter looks suspicious. It constantly 1268 * increments with no sign of Tx errors. This may indicate 1269 * the counter name is not correct one so I've removed the 1270 * counter in output errors. 1271 */ 1272 ifp->if_oerrors += smb->tx_abort + smb->tx_late_colls + 1273 smb->tx_underrun; 1274 1275 ifp->if_ipackets += smb->rx_frames; 1276 1277 ifp->if_ierrors += smb->rx_crcerrs + smb->rx_lenerrs + 1278 smb->rx_runts + smb->rx_pkts_truncated + 1279 smb->rx_fifo_oflows + smb->rx_rrs_errs + 1280 smb->rx_alignerrs; 1281 } 1282 1283 static int 1284 ale_intr(void *xsc) 1285 { 1286 struct ale_softc *sc = xsc; 1287 struct ifnet *ifp = &sc->sc_ec.ec_if; 1288 uint32_t status; 1289 1290 status = CSR_READ_4(sc, ALE_INTR_STATUS); 1291 if ((status & ALE_INTRS) == 0) 1292 return 0; 1293 1294 /* Acknowledge and disable interrupts. */ 1295 CSR_WRITE_4(sc, ALE_INTR_STATUS, status | INTR_DIS_INT); 1296 1297 if (ifp->if_flags & IFF_RUNNING) { 1298 int error; 1299 1300 error = ale_rxeof(sc); 1301 if (error) { 1302 sc->ale_stats.reset_brk_seq++; 1303 ale_init(ifp); 1304 return 0; 1305 } 1306 1307 if (status & (INTR_DMA_RD_TO_RST | INTR_DMA_WR_TO_RST)) { 1308 if (status & INTR_DMA_RD_TO_RST) 1309 printf("%s: DMA read error! -- resetting\n", 1310 device_xname(sc->sc_dev)); 1311 if (status & INTR_DMA_WR_TO_RST) 1312 printf("%s: DMA write error! -- resetting\n", 1313 device_xname(sc->sc_dev)); 1314 ale_init(ifp); 1315 return 0; 1316 } 1317 1318 ale_txeof(sc); 1319 if_schedule_deferred_start(ifp); 1320 } 1321 1322 /* Re-enable interrupts. */ 1323 CSR_WRITE_4(sc, ALE_INTR_STATUS, 0x7FFFFFFF); 1324 return 1; 1325 } 1326 1327 static void 1328 ale_txeof(struct ale_softc *sc) 1329 { 1330 struct ifnet *ifp = &sc->sc_ec.ec_if; 1331 struct ale_txdesc *txd; 1332 uint32_t cons, prod; 1333 int prog; 1334 1335 if (sc->ale_cdata.ale_tx_cnt == 0) 1336 return; 1337 1338 bus_dmamap_sync(sc->sc_dmat, sc->ale_cdata.ale_tx_ring_map, 0, 1339 sc->ale_cdata.ale_tx_ring_map->dm_mapsize, BUS_DMASYNC_POSTREAD); 1340 if ((sc->ale_flags & ALE_FLAG_TXCMB_BUG) == 0) { 1341 bus_dmamap_sync(sc->sc_dmat, sc->ale_cdata.ale_tx_cmb_map, 0, 1342 sc->ale_cdata.ale_tx_cmb_map->dm_mapsize, 1343 BUS_DMASYNC_POSTREAD); 1344 prod = *sc->ale_cdata.ale_tx_cmb & TPD_CNT_MASK; 1345 } else 1346 prod = CSR_READ_2(sc, ALE_TPD_CONS_IDX); 1347 cons = sc->ale_cdata.ale_tx_cons; 1348 /* 1349 * Go through our Tx list and free mbufs for those 1350 * frames which have been transmitted. 1351 */ 1352 for (prog = 0; cons != prod; prog++, 1353 ALE_DESC_INC(cons, ALE_TX_RING_CNT)) { 1354 if (sc->ale_cdata.ale_tx_cnt <= 0) 1355 break; 1356 prog++; 1357 ifp->if_flags &= ~IFF_OACTIVE; 1358 sc->ale_cdata.ale_tx_cnt--; 1359 txd = &sc->ale_cdata.ale_txdesc[cons]; 1360 if (txd->tx_m != NULL) { 1361 /* Reclaim transmitted mbufs. */ 1362 bus_dmamap_unload(sc->sc_dmat, txd->tx_dmamap); 1363 m_freem(txd->tx_m); 1364 txd->tx_m = NULL; 1365 } 1366 } 1367 1368 if (prog > 0) { 1369 sc->ale_cdata.ale_tx_cons = cons; 1370 /* 1371 * Unarm watchdog timer only when there is no pending 1372 * Tx descriptors in queue. 1373 */ 1374 if (sc->ale_cdata.ale_tx_cnt == 0) 1375 ifp->if_timer = 0; 1376 } 1377 } 1378 1379 static void 1380 ale_rx_update_page(struct ale_softc *sc, struct ale_rx_page **page, 1381 uint32_t length, uint32_t *prod) 1382 { 1383 struct ale_rx_page *rx_page; 1384 1385 rx_page = *page; 1386 /* Update consumer position. */ 1387 rx_page->cons += roundup(length + sizeof(struct rx_rs), 1388 ALE_RX_PAGE_ALIGN); 1389 if (rx_page->cons >= ALE_RX_PAGE_SZ) { 1390 /* 1391 * End of Rx page reached, let hardware reuse 1392 * this page. 1393 */ 1394 rx_page->cons = 0; 1395 *rx_page->cmb_addr = 0; 1396 bus_dmamap_sync(sc->sc_dmat, rx_page->cmb_map, 0, 1397 rx_page->cmb_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 1398 CSR_WRITE_1(sc, ALE_RXF0_PAGE0 + sc->ale_cdata.ale_rx_curp, 1399 RXF_VALID); 1400 /* Switch to alternate Rx page. */ 1401 sc->ale_cdata.ale_rx_curp ^= 1; 1402 rx_page = *page = 1403 &sc->ale_cdata.ale_rx_page[sc->ale_cdata.ale_rx_curp]; 1404 /* Page flipped, sync CMB and Rx page. */ 1405 bus_dmamap_sync(sc->sc_dmat, rx_page->page_map, 0, 1406 rx_page->page_map->dm_mapsize, BUS_DMASYNC_POSTREAD); 1407 bus_dmamap_sync(sc->sc_dmat, rx_page->cmb_map, 0, 1408 rx_page->cmb_map->dm_mapsize, BUS_DMASYNC_POSTREAD); 1409 /* Sync completed, cache updated producer index. */ 1410 *prod = *rx_page->cmb_addr; 1411 } 1412 } 1413 1414 1415 /* 1416 * It seems that AR81xx controller can compute partial checksum. 1417 * The partial checksum value can be used to accelerate checksum 1418 * computation for fragmented TCP/UDP packets. Upper network stack 1419 * already takes advantage of the partial checksum value in IP 1420 * reassembly stage. But I'm not sure the correctness of the 1421 * partial hardware checksum assistance due to lack of data sheet. 1422 * In addition, the Rx feature of controller that requires copying 1423 * for every frames effectively nullifies one of most nice offload 1424 * capability of controller. 1425 */ 1426 static void 1427 ale_rxcsum(struct ale_softc *sc, struct mbuf *m, uint32_t status) 1428 { 1429 if (status & ALE_RD_IPCSUM_NOK) 1430 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 1431 1432 if ((sc->ale_flags & ALE_FLAG_RXCSUM_BUG) == 0) { 1433 if (((status & ALE_RD_IPV4_FRAG) == 0) && 1434 ((status & (ALE_RD_TCP | ALE_RD_UDP)) != 0) && 1435 (status & ALE_RD_TCP_UDPCSUM_NOK)) 1436 { 1437 m->m_pkthdr.csum_flags |= M_CSUM_TCP_UDP_BAD; 1438 } 1439 } else { 1440 if ((status & (ALE_RD_TCP | ALE_RD_UDP)) != 0) { 1441 if (status & ALE_RD_TCP_UDPCSUM_NOK) { 1442 m->m_pkthdr.csum_flags |= M_CSUM_TCP_UDP_BAD; 1443 } 1444 } 1445 } 1446 /* 1447 * Don't mark bad checksum for TCP/UDP frames 1448 * as fragmented frames may always have set 1449 * bad checksummed bit of frame status. 1450 */ 1451 } 1452 1453 /* Process received frames. */ 1454 static int 1455 ale_rxeof(struct ale_softc *sc) 1456 { 1457 struct ifnet *ifp = &sc->sc_ec.ec_if; 1458 struct ale_rx_page *rx_page; 1459 struct rx_rs *rs; 1460 struct mbuf *m; 1461 uint32_t length, prod, seqno, status; 1462 int prog; 1463 1464 rx_page = &sc->ale_cdata.ale_rx_page[sc->ale_cdata.ale_rx_curp]; 1465 bus_dmamap_sync(sc->sc_dmat, rx_page->cmb_map, 0, 1466 rx_page->cmb_map->dm_mapsize, BUS_DMASYNC_POSTREAD); 1467 bus_dmamap_sync(sc->sc_dmat, rx_page->page_map, 0, 1468 rx_page->page_map->dm_mapsize, BUS_DMASYNC_POSTREAD); 1469 /* 1470 * Don't directly access producer index as hardware may 1471 * update it while Rx handler is in progress. It would 1472 * be even better if there is a way to let hardware 1473 * know how far driver processed its received frames. 1474 * Alternatively, hardware could provide a way to disable 1475 * CMB updates until driver acknowledges the end of CMB 1476 * access. 1477 */ 1478 prod = *rx_page->cmb_addr; 1479 for (prog = 0; ; prog++) { 1480 if (rx_page->cons >= prod) 1481 break; 1482 rs = (struct rx_rs *)(rx_page->page_addr + rx_page->cons); 1483 seqno = ALE_RX_SEQNO(le32toh(rs->seqno)); 1484 if (sc->ale_cdata.ale_rx_seqno != seqno) { 1485 /* 1486 * Normally I believe this should not happen unless 1487 * severe driver bug or corrupted memory. However 1488 * it seems to happen under certain conditions which 1489 * is triggered by abrupt Rx events such as initiation 1490 * of bulk transfer of remote host. It's not easy to 1491 * reproduce this and I doubt it could be related 1492 * with FIFO overflow of hardware or activity of Tx 1493 * CMB updates. I also remember similar behaviour 1494 * seen on RealTek 8139 which uses resembling Rx 1495 * scheme. 1496 */ 1497 if (aledebug) 1498 printf("%s: garbled seq: %u, expected: %u -- " 1499 "resetting!\n", device_xname(sc->sc_dev), 1500 seqno, sc->ale_cdata.ale_rx_seqno); 1501 return EIO; 1502 } 1503 /* Frame received. */ 1504 sc->ale_cdata.ale_rx_seqno++; 1505 length = ALE_RX_BYTES(le32toh(rs->length)); 1506 status = le32toh(rs->flags); 1507 if (status & ALE_RD_ERROR) { 1508 /* 1509 * We want to pass the following frames to upper 1510 * layer regardless of error status of Rx return 1511 * status. 1512 * 1513 * o IP/TCP/UDP checksum is bad. 1514 * o frame length and protocol specific length 1515 * does not match. 1516 */ 1517 if (status & (ALE_RD_CRC | ALE_RD_CODE | 1518 ALE_RD_DRIBBLE | ALE_RD_RUNT | ALE_RD_OFLOW | 1519 ALE_RD_TRUNC)) { 1520 ale_rx_update_page(sc, &rx_page, length, &prod); 1521 continue; 1522 } 1523 } 1524 /* 1525 * m_devget(9) is major bottle-neck of ale(4)(It comes 1526 * from hardware limitation). For jumbo frames we could 1527 * get a slightly better performance if driver use 1528 * m_getjcl(9) with proper buffer size argument. However 1529 * that would make code more complicated and I don't 1530 * think users would expect good Rx performance numbers 1531 * on these low-end consumer ethernet controller. 1532 */ 1533 m = m_devget((char *)(rs + 1), length - ETHER_CRC_LEN, 1534 0, ifp); 1535 if (m == NULL) { 1536 ifp->if_iqdrops++; 1537 ale_rx_update_page(sc, &rx_page, length, &prod); 1538 continue; 1539 } 1540 if (status & ALE_RD_IPV4) 1541 ale_rxcsum(sc, m, status); 1542 #if NVLAN > 0 1543 if (status & ALE_RD_VLAN) { 1544 uint32_t vtags = ALE_RX_VLAN(le32toh(rs->vtags)); 1545 vlan_set_tag(m, ALE_RX_VLAN_TAG(vtags)); 1546 } 1547 #endif 1548 1549 /* Pass it to upper layer. */ 1550 if_percpuq_enqueue(ifp->if_percpuq, m); 1551 1552 ale_rx_update_page(sc, &rx_page, length, &prod); 1553 } 1554 1555 return 0; 1556 } 1557 1558 static void 1559 ale_tick(void *xsc) 1560 { 1561 struct ale_softc *sc = xsc; 1562 struct mii_data *mii = &sc->sc_miibus; 1563 int s; 1564 1565 s = splnet(); 1566 mii_tick(mii); 1567 ale_stats_update(sc); 1568 splx(s); 1569 1570 callout_schedule(&sc->sc_tick_ch, hz); 1571 } 1572 1573 static void 1574 ale_reset(struct ale_softc *sc) 1575 { 1576 uint32_t reg; 1577 int i; 1578 1579 /* Initialize PCIe module. From Linux. */ 1580 CSR_WRITE_4(sc, 0x1008, CSR_READ_4(sc, 0x1008) | 0x8000); 1581 1582 CSR_WRITE_4(sc, ALE_MASTER_CFG, MASTER_RESET); 1583 for (i = ALE_RESET_TIMEOUT; i > 0; i--) { 1584 DELAY(10); 1585 if ((CSR_READ_4(sc, ALE_MASTER_CFG) & MASTER_RESET) == 0) 1586 break; 1587 } 1588 if (i == 0) 1589 printf("%s: master reset timeout!\n", device_xname(sc->sc_dev)); 1590 1591 for (i = ALE_RESET_TIMEOUT; i > 0; i--) { 1592 if ((reg = CSR_READ_4(sc, ALE_IDLE_STATUS)) == 0) 1593 break; 1594 DELAY(10); 1595 } 1596 1597 if (i == 0) 1598 printf("%s: reset timeout(0x%08x)!\n", device_xname(sc->sc_dev), 1599 reg); 1600 } 1601 1602 static int 1603 ale_init(struct ifnet *ifp) 1604 { 1605 struct ale_softc *sc = ifp->if_softc; 1606 struct mii_data *mii; 1607 uint8_t eaddr[ETHER_ADDR_LEN]; 1608 bus_addr_t paddr; 1609 uint32_t reg, rxf_hi, rxf_lo; 1610 1611 /* 1612 * Cancel any pending I/O. 1613 */ 1614 ale_stop(ifp, 0); 1615 1616 /* 1617 * Reset the chip to a known state. 1618 */ 1619 ale_reset(sc); 1620 1621 /* Initialize Tx descriptors, DMA memory blocks. */ 1622 ale_init_rx_pages(sc); 1623 ale_init_tx_ring(sc); 1624 1625 /* Reprogram the station address. */ 1626 memcpy(eaddr, CLLADDR(ifp->if_sadl), ETHER_ADDR_LEN); 1627 CSR_WRITE_4(sc, ALE_PAR0, 1628 eaddr[2] << 24 | eaddr[3] << 16 | eaddr[4] << 8 | eaddr[5]); 1629 CSR_WRITE_4(sc, ALE_PAR1, eaddr[0] << 8 | eaddr[1]); 1630 1631 /* 1632 * Clear WOL status and disable all WOL feature as WOL 1633 * would interfere Rx operation under normal environments. 1634 */ 1635 CSR_READ_4(sc, ALE_WOL_CFG); 1636 CSR_WRITE_4(sc, ALE_WOL_CFG, 0); 1637 1638 /* 1639 * Set Tx descriptor/RXF0/CMB base addresses. They share 1640 * the same high address part of DMAable region. 1641 */ 1642 paddr = sc->ale_cdata.ale_tx_ring_paddr; 1643 CSR_WRITE_4(sc, ALE_TPD_ADDR_HI, ALE_ADDR_HI(paddr)); 1644 CSR_WRITE_4(sc, ALE_TPD_ADDR_LO, ALE_ADDR_LO(paddr)); 1645 CSR_WRITE_4(sc, ALE_TPD_CNT, 1646 (ALE_TX_RING_CNT << TPD_CNT_SHIFT) & TPD_CNT_MASK); 1647 1648 /* Set Rx page base address, note we use single queue. */ 1649 paddr = sc->ale_cdata.ale_rx_page[0].page_paddr; 1650 CSR_WRITE_4(sc, ALE_RXF0_PAGE0_ADDR_LO, ALE_ADDR_LO(paddr)); 1651 paddr = sc->ale_cdata.ale_rx_page[1].page_paddr; 1652 CSR_WRITE_4(sc, ALE_RXF0_PAGE1_ADDR_LO, ALE_ADDR_LO(paddr)); 1653 1654 /* Set Tx/Rx CMB addresses. */ 1655 paddr = sc->ale_cdata.ale_tx_cmb_paddr; 1656 CSR_WRITE_4(sc, ALE_TX_CMB_ADDR_LO, ALE_ADDR_LO(paddr)); 1657 paddr = sc->ale_cdata.ale_rx_page[0].cmb_paddr; 1658 CSR_WRITE_4(sc, ALE_RXF0_CMB0_ADDR_LO, ALE_ADDR_LO(paddr)); 1659 paddr = sc->ale_cdata.ale_rx_page[1].cmb_paddr; 1660 CSR_WRITE_4(sc, ALE_RXF0_CMB1_ADDR_LO, ALE_ADDR_LO(paddr)); 1661 1662 /* Mark RXF0 is valid. */ 1663 CSR_WRITE_1(sc, ALE_RXF0_PAGE0, RXF_VALID); 1664 CSR_WRITE_1(sc, ALE_RXF0_PAGE1, RXF_VALID); 1665 /* 1666 * No need to initialize RFX1/RXF2/RXF3. We don't use 1667 * multi-queue yet. 1668 */ 1669 1670 /* Set Rx page size, excluding guard frame size. */ 1671 CSR_WRITE_4(sc, ALE_RXF_PAGE_SIZE, ALE_RX_PAGE_SZ); 1672 1673 /* Tell hardware that we're ready to load DMA blocks. */ 1674 CSR_WRITE_4(sc, ALE_DMA_BLOCK, DMA_BLOCK_LOAD); 1675 1676 /* Set Rx/Tx interrupt trigger threshold. */ 1677 CSR_WRITE_4(sc, ALE_INT_TRIG_THRESH, (1 << INT_TRIG_RX_THRESH_SHIFT) | 1678 (4 << INT_TRIG_TX_THRESH_SHIFT)); 1679 /* 1680 * XXX 1681 * Set interrupt trigger timer, its purpose and relation 1682 * with interrupt moderation mechanism is not clear yet. 1683 */ 1684 CSR_WRITE_4(sc, ALE_INT_TRIG_TIMER, 1685 ((ALE_USECS(10) << INT_TRIG_RX_TIMER_SHIFT) | 1686 (ALE_USECS(1000) << INT_TRIG_TX_TIMER_SHIFT))); 1687 1688 /* Configure interrupt moderation timer. */ 1689 sc->ale_int_rx_mod = ALE_IM_RX_TIMER_DEFAULT; 1690 sc->ale_int_tx_mod = ALE_IM_TX_TIMER_DEFAULT; 1691 reg = ALE_USECS(sc->ale_int_rx_mod) << IM_TIMER_RX_SHIFT; 1692 reg |= ALE_USECS(sc->ale_int_tx_mod) << IM_TIMER_TX_SHIFT; 1693 CSR_WRITE_4(sc, ALE_IM_TIMER, reg); 1694 reg = CSR_READ_4(sc, ALE_MASTER_CFG); 1695 reg &= ~(MASTER_CHIP_REV_MASK | MASTER_CHIP_ID_MASK); 1696 reg &= ~(MASTER_IM_RX_TIMER_ENB | MASTER_IM_TX_TIMER_ENB); 1697 if (ALE_USECS(sc->ale_int_rx_mod) != 0) 1698 reg |= MASTER_IM_RX_TIMER_ENB; 1699 if (ALE_USECS(sc->ale_int_tx_mod) != 0) 1700 reg |= MASTER_IM_TX_TIMER_ENB; 1701 CSR_WRITE_4(sc, ALE_MASTER_CFG, reg); 1702 CSR_WRITE_2(sc, ALE_INTR_CLR_TIMER, ALE_USECS(1000)); 1703 1704 /* Set Maximum frame size of controller. */ 1705 if (ifp->if_mtu < ETHERMTU) 1706 sc->ale_max_frame_size = ETHERMTU; 1707 else 1708 sc->ale_max_frame_size = ifp->if_mtu; 1709 sc->ale_max_frame_size += ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN + ETHER_CRC_LEN; 1710 CSR_WRITE_4(sc, ALE_FRAME_SIZE, sc->ale_max_frame_size); 1711 1712 /* Configure IPG/IFG parameters. */ 1713 CSR_WRITE_4(sc, ALE_IPG_IFG_CFG, 1714 ((IPG_IFG_IPGT_DEFAULT << IPG_IFG_IPGT_SHIFT) & IPG_IFG_IPGT_MASK) | 1715 ((IPG_IFG_MIFG_DEFAULT << IPG_IFG_MIFG_SHIFT) & IPG_IFG_MIFG_MASK) | 1716 ((IPG_IFG_IPG1_DEFAULT << IPG_IFG_IPG1_SHIFT) & IPG_IFG_IPG1_MASK) | 1717 ((IPG_IFG_IPG2_DEFAULT << IPG_IFG_IPG2_SHIFT) & IPG_IFG_IPG2_MASK)); 1718 1719 /* Set parameters for half-duplex media. */ 1720 CSR_WRITE_4(sc, ALE_HDPX_CFG, 1721 ((HDPX_CFG_LCOL_DEFAULT << HDPX_CFG_LCOL_SHIFT) & 1722 HDPX_CFG_LCOL_MASK) | 1723 ((HDPX_CFG_RETRY_DEFAULT << HDPX_CFG_RETRY_SHIFT) & 1724 HDPX_CFG_RETRY_MASK) | HDPX_CFG_EXC_DEF_EN | 1725 ((HDPX_CFG_ABEBT_DEFAULT << HDPX_CFG_ABEBT_SHIFT) & 1726 HDPX_CFG_ABEBT_MASK) | 1727 ((HDPX_CFG_JAMIPG_DEFAULT << HDPX_CFG_JAMIPG_SHIFT) & 1728 HDPX_CFG_JAMIPG_MASK)); 1729 1730 /* Configure Tx jumbo frame parameters. */ 1731 if ((sc->ale_flags & ALE_FLAG_JUMBO) != 0) { 1732 if (ifp->if_mtu < ETHERMTU) 1733 reg = sc->ale_max_frame_size; 1734 else if (ifp->if_mtu < 6 * 1024) 1735 reg = (sc->ale_max_frame_size * 2) / 3; 1736 else 1737 reg = sc->ale_max_frame_size / 2; 1738 CSR_WRITE_4(sc, ALE_TX_JUMBO_THRESH, 1739 roundup(reg, TX_JUMBO_THRESH_UNIT) >> 1740 TX_JUMBO_THRESH_UNIT_SHIFT); 1741 } 1742 1743 /* Configure TxQ. */ 1744 reg = (128 << (sc->ale_dma_rd_burst >> DMA_CFG_RD_BURST_SHIFT)) 1745 << TXQ_CFG_TX_FIFO_BURST_SHIFT; 1746 reg |= (TXQ_CFG_TPD_BURST_DEFAULT << TXQ_CFG_TPD_BURST_SHIFT) & 1747 TXQ_CFG_TPD_BURST_MASK; 1748 CSR_WRITE_4(sc, ALE_TXQ_CFG, reg | TXQ_CFG_ENHANCED_MODE | TXQ_CFG_ENB); 1749 1750 /* Configure Rx jumbo frame & flow control parameters. */ 1751 if ((sc->ale_flags & ALE_FLAG_JUMBO) != 0) { 1752 reg = roundup(sc->ale_max_frame_size, RX_JUMBO_THRESH_UNIT); 1753 CSR_WRITE_4(sc, ALE_RX_JUMBO_THRESH, 1754 (((reg >> RX_JUMBO_THRESH_UNIT_SHIFT) << 1755 RX_JUMBO_THRESH_MASK_SHIFT) & RX_JUMBO_THRESH_MASK) | 1756 ((RX_JUMBO_LKAH_DEFAULT << RX_JUMBO_LKAH_SHIFT) & 1757 RX_JUMBO_LKAH_MASK)); 1758 reg = CSR_READ_4(sc, ALE_SRAM_RX_FIFO_LEN); 1759 rxf_hi = (reg * 7) / 10; 1760 rxf_lo = (reg * 3)/ 10; 1761 CSR_WRITE_4(sc, ALE_RX_FIFO_PAUSE_THRESH, 1762 ((rxf_lo << RX_FIFO_PAUSE_THRESH_LO_SHIFT) & 1763 RX_FIFO_PAUSE_THRESH_LO_MASK) | 1764 ((rxf_hi << RX_FIFO_PAUSE_THRESH_HI_SHIFT) & 1765 RX_FIFO_PAUSE_THRESH_HI_MASK)); 1766 } 1767 1768 /* Disable RSS. */ 1769 CSR_WRITE_4(sc, ALE_RSS_IDT_TABLE0, 0); 1770 CSR_WRITE_4(sc, ALE_RSS_CPU, 0); 1771 1772 /* Configure RxQ. */ 1773 CSR_WRITE_4(sc, ALE_RXQ_CFG, 1774 RXQ_CFG_ALIGN_32 | RXQ_CFG_CUT_THROUGH_ENB | RXQ_CFG_ENB); 1775 1776 /* Configure DMA parameters. */ 1777 reg = 0; 1778 if ((sc->ale_flags & ALE_FLAG_TXCMB_BUG) == 0) 1779 reg |= DMA_CFG_TXCMB_ENB; 1780 CSR_WRITE_4(sc, ALE_DMA_CFG, 1781 DMA_CFG_OUT_ORDER | DMA_CFG_RD_REQ_PRI | DMA_CFG_RCB_64 | 1782 sc->ale_dma_rd_burst | reg | 1783 sc->ale_dma_wr_burst | DMA_CFG_RXCMB_ENB | 1784 ((DMA_CFG_RD_DELAY_CNT_DEFAULT << DMA_CFG_RD_DELAY_CNT_SHIFT) & 1785 DMA_CFG_RD_DELAY_CNT_MASK) | 1786 ((DMA_CFG_WR_DELAY_CNT_DEFAULT << DMA_CFG_WR_DELAY_CNT_SHIFT) & 1787 DMA_CFG_WR_DELAY_CNT_MASK)); 1788 1789 /* 1790 * Hardware can be configured to issue SMB interrupt based 1791 * on programmed interval. Since there is a callout that is 1792 * invoked for every hz in driver we use that instead of 1793 * relying on periodic SMB interrupt. 1794 */ 1795 CSR_WRITE_4(sc, ALE_SMB_STAT_TIMER, ALE_USECS(0)); 1796 1797 /* Clear MAC statistics. */ 1798 ale_stats_clear(sc); 1799 1800 /* 1801 * Configure Tx/Rx MACs. 1802 * - Auto-padding for short frames. 1803 * - Enable CRC generation. 1804 * Actual reconfiguration of MAC for resolved speed/duplex 1805 * is followed after detection of link establishment. 1806 * AR81xx always does checksum computation regardless of 1807 * MAC_CFG_RXCSUM_ENB bit. In fact, setting the bit will 1808 * cause Rx handling issue for fragmented IP datagrams due 1809 * to silicon bug. 1810 */ 1811 reg = MAC_CFG_TX_CRC_ENB | MAC_CFG_TX_AUTO_PAD | MAC_CFG_FULL_DUPLEX | 1812 ((MAC_CFG_PREAMBLE_DEFAULT << MAC_CFG_PREAMBLE_SHIFT) & 1813 MAC_CFG_PREAMBLE_MASK); 1814 if ((sc->ale_flags & ALE_FLAG_FASTETHER) != 0) 1815 reg |= MAC_CFG_SPEED_10_100; 1816 else 1817 reg |= MAC_CFG_SPEED_1000; 1818 CSR_WRITE_4(sc, ALE_MAC_CFG, reg); 1819 1820 /* Set up the receive filter. */ 1821 ale_rxfilter(sc); 1822 ale_rxvlan(sc); 1823 1824 /* Acknowledge all pending interrupts and clear it. */ 1825 CSR_WRITE_4(sc, ALE_INTR_MASK, ALE_INTRS); 1826 CSR_WRITE_4(sc, ALE_INTR_STATUS, 0xFFFFFFFF); 1827 CSR_WRITE_4(sc, ALE_INTR_STATUS, 0); 1828 1829 sc->ale_flags &= ~ALE_FLAG_LINK; 1830 1831 /* Switch to the current media. */ 1832 mii = &sc->sc_miibus; 1833 mii_mediachg(mii); 1834 1835 callout_schedule(&sc->sc_tick_ch, hz); 1836 1837 ifp->if_flags |= IFF_RUNNING; 1838 ifp->if_flags &= ~IFF_OACTIVE; 1839 1840 return 0; 1841 } 1842 1843 static void 1844 ale_stop(struct ifnet *ifp, int disable) 1845 { 1846 struct ale_softc *sc = ifp->if_softc; 1847 struct ale_txdesc *txd; 1848 uint32_t reg; 1849 int i; 1850 1851 callout_stop(&sc->sc_tick_ch); 1852 1853 /* 1854 * Mark the interface down and cancel the watchdog timer. 1855 */ 1856 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1857 ifp->if_timer = 0; 1858 1859 sc->ale_flags &= ~ALE_FLAG_LINK; 1860 1861 ale_stats_update(sc); 1862 1863 mii_down(&sc->sc_miibus); 1864 1865 /* Disable interrupts. */ 1866 CSR_WRITE_4(sc, ALE_INTR_MASK, 0); 1867 CSR_WRITE_4(sc, ALE_INTR_STATUS, 0xFFFFFFFF); 1868 1869 /* Disable queue processing and DMA. */ 1870 reg = CSR_READ_4(sc, ALE_TXQ_CFG); 1871 reg &= ~TXQ_CFG_ENB; 1872 CSR_WRITE_4(sc, ALE_TXQ_CFG, reg); 1873 reg = CSR_READ_4(sc, ALE_RXQ_CFG); 1874 reg &= ~RXQ_CFG_ENB; 1875 CSR_WRITE_4(sc, ALE_RXQ_CFG, reg); 1876 reg = CSR_READ_4(sc, ALE_DMA_CFG); 1877 reg &= ~(DMA_CFG_TXCMB_ENB | DMA_CFG_RXCMB_ENB); 1878 CSR_WRITE_4(sc, ALE_DMA_CFG, reg); 1879 DELAY(1000); 1880 1881 /* Stop Rx/Tx MACs. */ 1882 ale_stop_mac(sc); 1883 1884 /* Disable interrupts again? XXX */ 1885 CSR_WRITE_4(sc, ALE_INTR_STATUS, 0xFFFFFFFF); 1886 1887 /* 1888 * Free TX mbufs still in the queues. 1889 */ 1890 for (i = 0; i < ALE_TX_RING_CNT; i++) { 1891 txd = &sc->ale_cdata.ale_txdesc[i]; 1892 if (txd->tx_m != NULL) { 1893 bus_dmamap_unload(sc->sc_dmat, txd->tx_dmamap); 1894 m_freem(txd->tx_m); 1895 txd->tx_m = NULL; 1896 } 1897 } 1898 } 1899 1900 static void 1901 ale_stop_mac(struct ale_softc *sc) 1902 { 1903 uint32_t reg; 1904 int i; 1905 1906 reg = CSR_READ_4(sc, ALE_MAC_CFG); 1907 if ((reg & (MAC_CFG_TX_ENB | MAC_CFG_RX_ENB)) != 0) { 1908 reg &= ~(MAC_CFG_TX_ENB | MAC_CFG_RX_ENB); 1909 CSR_WRITE_4(sc, ALE_MAC_CFG, reg); 1910 } 1911 1912 for (i = ALE_TIMEOUT; i > 0; i--) { 1913 reg = CSR_READ_4(sc, ALE_IDLE_STATUS); 1914 if (reg == 0) 1915 break; 1916 DELAY(10); 1917 } 1918 if (i == 0) 1919 printf("%s: could not disable Tx/Rx MAC(0x%08x)!\n", 1920 device_xname(sc->sc_dev), reg); 1921 } 1922 1923 static void 1924 ale_init_tx_ring(struct ale_softc *sc) 1925 { 1926 struct ale_txdesc *txd; 1927 int i; 1928 1929 sc->ale_cdata.ale_tx_prod = 0; 1930 sc->ale_cdata.ale_tx_cons = 0; 1931 sc->ale_cdata.ale_tx_cnt = 0; 1932 1933 memset(sc->ale_cdata.ale_tx_ring, 0, ALE_TX_RING_SZ); 1934 memset(sc->ale_cdata.ale_tx_cmb, 0, ALE_TX_CMB_SZ); 1935 for (i = 0; i < ALE_TX_RING_CNT; i++) { 1936 txd = &sc->ale_cdata.ale_txdesc[i]; 1937 txd->tx_m = NULL; 1938 } 1939 *sc->ale_cdata.ale_tx_cmb = 0; 1940 bus_dmamap_sync(sc->sc_dmat, sc->ale_cdata.ale_tx_cmb_map, 0, 1941 sc->ale_cdata.ale_tx_cmb_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 1942 bus_dmamap_sync(sc->sc_dmat, sc->ale_cdata.ale_tx_ring_map, 0, 1943 sc->ale_cdata.ale_tx_ring_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 1944 } 1945 1946 static void 1947 ale_init_rx_pages(struct ale_softc *sc) 1948 { 1949 struct ale_rx_page *rx_page; 1950 int i; 1951 1952 sc->ale_cdata.ale_rx_seqno = 0; 1953 sc->ale_cdata.ale_rx_curp = 0; 1954 1955 for (i = 0; i < ALE_RX_PAGES; i++) { 1956 rx_page = &sc->ale_cdata.ale_rx_page[i]; 1957 memset(rx_page->page_addr, 0, sc->ale_pagesize); 1958 memset(rx_page->cmb_addr, 0, ALE_RX_CMB_SZ); 1959 rx_page->cons = 0; 1960 *rx_page->cmb_addr = 0; 1961 bus_dmamap_sync(sc->sc_dmat, rx_page->page_map, 0, 1962 rx_page->page_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 1963 bus_dmamap_sync(sc->sc_dmat, rx_page->cmb_map, 0, 1964 rx_page->cmb_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 1965 } 1966 } 1967 1968 static void 1969 ale_rxvlan(struct ale_softc *sc) 1970 { 1971 uint32_t reg; 1972 1973 reg = CSR_READ_4(sc, ALE_MAC_CFG); 1974 reg &= ~MAC_CFG_VLAN_TAG_STRIP; 1975 if (sc->sc_ec.ec_capenable & ETHERCAP_VLAN_HWTAGGING) 1976 reg |= MAC_CFG_VLAN_TAG_STRIP; 1977 CSR_WRITE_4(sc, ALE_MAC_CFG, reg); 1978 } 1979 1980 static void 1981 ale_rxfilter(struct ale_softc *sc) 1982 { 1983 struct ethercom *ec = &sc->sc_ec; 1984 struct ifnet *ifp = &ec->ec_if; 1985 struct ether_multi *enm; 1986 struct ether_multistep step; 1987 uint32_t crc; 1988 uint32_t mchash[2]; 1989 uint32_t rxcfg; 1990 1991 rxcfg = CSR_READ_4(sc, ALE_MAC_CFG); 1992 rxcfg &= ~(MAC_CFG_ALLMULTI | MAC_CFG_BCAST | MAC_CFG_PROMISC); 1993 ifp->if_flags &= ~IFF_ALLMULTI; 1994 1995 /* 1996 * Always accept broadcast frames. 1997 */ 1998 rxcfg |= MAC_CFG_BCAST; 1999 2000 if (ifp->if_flags & IFF_PROMISC || ec->ec_multicnt > 0) { 2001 ifp->if_flags |= IFF_ALLMULTI; 2002 if (ifp->if_flags & IFF_PROMISC) 2003 rxcfg |= MAC_CFG_PROMISC; 2004 else 2005 rxcfg |= MAC_CFG_ALLMULTI; 2006 mchash[0] = mchash[1] = 0xFFFFFFFF; 2007 } else { 2008 /* Program new filter. */ 2009 memset(mchash, 0, sizeof(mchash)); 2010 2011 ETHER_LOCK(ec); 2012 ETHER_FIRST_MULTI(step, ec, enm); 2013 while (enm != NULL) { 2014 crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 2015 mchash[crc >> 31] |= 1 << ((crc >> 26) & 0x1f); 2016 ETHER_NEXT_MULTI(step, enm); 2017 } 2018 ETHER_UNLOCK(ec); 2019 } 2020 2021 CSR_WRITE_4(sc, ALE_MAR0, mchash[0]); 2022 CSR_WRITE_4(sc, ALE_MAR1, mchash[1]); 2023 CSR_WRITE_4(sc, ALE_MAC_CFG, rxcfg); 2024 } 2025
Indexes created Tue Sep 30 11:09:46 GMT 2025