if_ale.c revision 1.41
1 /* $NetBSD: if_ale.c,v 1.41 2022/08/22 15:39:26 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 2008, Pyun YongHyeon <yongari (at) FreeBSD.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice unmodified, this list of conditions, and the following 12 * disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * 29 * $FreeBSD: src/sys/dev/ale/if_ale.c,v 1.3 2008/12/03 09:01:12 yongari Exp $ 30 */ 31 32 /* Driver for Atheros AR8121/AR8113/AR8114 PCIe Ethernet. */ 33 34 #include <sys/cdefs.h> 35 __KERNEL_RCSID(0, "$NetBSD: if_ale.c,v 1.41 2022/08/22 15:39:26 thorpej Exp $"); 36 37 #include "vlan.h" 38 39 #include <sys/param.h> 40 #include <sys/proc.h> 41 #include <sys/endian.h> 42 #include <sys/systm.h> 43 #include <sys/types.h> 44 #include <sys/sockio.h> 45 #include <sys/mbuf.h> 46 #include <sys/queue.h> 47 #include <sys/kernel.h> 48 #include <sys/device.h> 49 #include <sys/callout.h> 50 #include <sys/socket.h> 51 52 #include <sys/bus.h> 53 54 #include <net/if.h> 55 #include <net/if_dl.h> 56 #include <net/if_llc.h> 57 #include <net/if_media.h> 58 #include <net/if_ether.h> 59 60 #ifdef INET 61 #include <netinet/in.h> 62 #include <netinet/in_systm.h> 63 #include <netinet/in_var.h> 64 #include <netinet/ip.h> 65 #endif 66 67 #include <net/if_types.h> 68 #include <net/if_vlanvar.h> 69 70 #include <net/bpf.h> 71 72 #include <dev/mii/mii.h> 73 #include <dev/mii/miivar.h> 74 75 #include <dev/pci/pcireg.h> 76 #include <dev/pci/pcivar.h> 77 #include <dev/pci/pcidevs.h> 78 79 #include <dev/pci/if_alereg.h> 80 81 static int ale_match(device_t, cfdata_t, void *); 82 static void ale_attach(device_t, device_t, void *); 83 static int ale_detach(device_t, int); 84 85 static int ale_miibus_readreg(device_t, int, int, uint16_t *); 86 static int ale_miibus_writereg(device_t, int, int, uint16_t); 87 static void ale_miibus_statchg(struct ifnet *); 88 89 static int ale_init(struct ifnet *); 90 static void ale_start(struct ifnet *); 91 static int ale_ioctl(struct ifnet *, u_long, void *); 92 static void ale_watchdog(struct ifnet *); 93 static int ale_mediachange(struct ifnet *); 94 static void ale_mediastatus(struct ifnet *, struct ifmediareq *); 95 96 static int ale_intr(void *); 97 static int ale_rxeof(struct ale_softc *sc); 98 static void ale_rx_update_page(struct ale_softc *, struct ale_rx_page **, 99 uint32_t, uint32_t *); 100 static void ale_rxcsum(struct ale_softc *, struct mbuf *, uint32_t); 101 static void ale_txeof(struct ale_softc *); 102 103 static int ale_dma_alloc(struct ale_softc *); 104 static void ale_dma_free(struct ale_softc *); 105 static int ale_encap(struct ale_softc *, struct mbuf *); 106 static void ale_init_rx_pages(struct ale_softc *); 107 static void ale_init_tx_ring(struct ale_softc *); 108 109 static void ale_stop(struct ifnet *, int); 110 static void ale_tick(void *); 111 static void ale_get_macaddr(struct ale_softc *); 112 static void ale_mac_config(struct ale_softc *); 113 static void ale_phy_reset(struct ale_softc *); 114 static void ale_reset(struct ale_softc *); 115 static void ale_rxfilter(struct ale_softc *); 116 static void ale_rxvlan(struct ale_softc *); 117 static void ale_stats_clear(struct ale_softc *); 118 static void ale_stats_update(struct ale_softc *); 119 static void ale_stop_mac(struct ale_softc *); 120 121 CFATTACH_DECL_NEW(ale, sizeof(struct ale_softc), 122 ale_match, ale_attach, ale_detach, NULL); 123 124 int aledebug = 0; 125 #define DPRINTF(x) do { if (aledebug) printf x; } while (0) 126 127 #define ALE_CSUM_FEATURES (M_CSUM_TCPv4 | M_CSUM_UDPv4) 128 129 static int 130 ale_miibus_readreg(device_t dev, int phy, int reg, uint16_t *val) 131 { 132 struct ale_softc *sc = device_private(dev); 133 uint32_t v; 134 int i; 135 136 if (phy != sc->ale_phyaddr) 137 return -1; 138 139 if (sc->ale_flags & ALE_FLAG_FASTETHER) { 140 switch (reg) { 141 case MII_100T2CR: 142 case MII_100T2SR: 143 case MII_EXTSR: 144 *val = 0; 145 return 0; 146 default: 147 break; 148 } 149 } 150 151 CSR_WRITE_4(sc, ALE_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ | 152 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); 153 for (i = ALE_PHY_TIMEOUT; i > 0; i--) { 154 DELAY(5); 155 v = CSR_READ_4(sc, ALE_MDIO); 156 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) 157 break; 158 } 159 160 if (i == 0) { 161 printf("%s: phy read timeout: phy %d, reg %d\n", 162 device_xname(sc->sc_dev), phy, reg); 163 return ETIMEDOUT; 164 } 165 166 *val = (v & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT; 167 return 0; 168 } 169 170 static int 171 ale_miibus_writereg(device_t dev, int phy, int reg, uint16_t val) 172 { 173 struct ale_softc *sc = device_private(dev); 174 uint32_t v; 175 int i; 176 177 if (phy != sc->ale_phyaddr) 178 return -1; 179 180 if (sc->ale_flags & ALE_FLAG_FASTETHER) { 181 switch (reg) { 182 case MII_100T2CR: 183 case MII_100T2SR: 184 case MII_EXTSR: 185 return 0; 186 default: 187 break; 188 } 189 } 190 191 CSR_WRITE_4(sc, ALE_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE | 192 (val & MDIO_DATA_MASK) << MDIO_DATA_SHIFT | 193 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); 194 for (i = ALE_PHY_TIMEOUT; i > 0; i--) { 195 DELAY(5); 196 v = CSR_READ_4(sc, ALE_MDIO); 197 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) 198 break; 199 } 200 201 if (i == 0) { 202 printf("%s: phy write timeout: phy %d, reg %d\n", 203 device_xname(sc->sc_dev), phy, reg); 204 return ETIMEDOUT; 205 } 206 207 return 0; 208 } 209 210 static void 211 ale_miibus_statchg(struct ifnet *ifp) 212 { 213 struct ale_softc *sc = ifp->if_softc; 214 struct mii_data *mii = &sc->sc_miibus; 215 uint32_t reg; 216 217 if ((ifp->if_flags & IFF_RUNNING) == 0) 218 return; 219 220 sc->ale_flags &= ~ALE_FLAG_LINK; 221 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 222 (IFM_ACTIVE | IFM_AVALID)) { 223 switch (IFM_SUBTYPE(mii->mii_media_active)) { 224 case IFM_10_T: 225 case IFM_100_TX: 226 sc->ale_flags |= ALE_FLAG_LINK; 227 break; 228 229 case IFM_1000_T: 230 if ((sc->ale_flags & ALE_FLAG_FASTETHER) == 0) 231 sc->ale_flags |= ALE_FLAG_LINK; 232 break; 233 234 default: 235 break; 236 } 237 } 238 239 /* Stop Rx/Tx MACs. */ 240 ale_stop_mac(sc); 241 242 /* Program MACs with resolved speed/duplex/flow-control. */ 243 if ((sc->ale_flags & ALE_FLAG_LINK) != 0) { 244 ale_mac_config(sc); 245 /* Reenable Tx/Rx MACs. */ 246 reg = CSR_READ_4(sc, ALE_MAC_CFG); 247 reg |= MAC_CFG_TX_ENB | MAC_CFG_RX_ENB; 248 CSR_WRITE_4(sc, ALE_MAC_CFG, reg); 249 } 250 } 251 252 void 253 ale_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 254 { 255 struct ale_softc *sc = ifp->if_softc; 256 struct mii_data *mii = &sc->sc_miibus; 257 258 mii_pollstat(mii); 259 ifmr->ifm_status = mii->mii_media_status; 260 ifmr->ifm_active = mii->mii_media_active; 261 } 262 263 int 264 ale_mediachange(struct ifnet *ifp) 265 { 266 struct ale_softc *sc = ifp->if_softc; 267 struct mii_data *mii = &sc->sc_miibus; 268 int error; 269 270 if (mii->mii_instance != 0) { 271 struct mii_softc *miisc; 272 273 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 274 mii_phy_reset(miisc); 275 } 276 error = mii_mediachg(mii); 277 278 return error; 279 } 280 281 int 282 ale_match(device_t dev, cfdata_t match, void *aux) 283 { 284 struct pci_attach_args *pa = aux; 285 286 return (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_ATTANSIC && 287 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_ATTANSIC_ETHERNET_L1E); 288 } 289 290 void 291 ale_get_macaddr(struct ale_softc *sc) 292 { 293 uint32_t ea[2], reg; 294 int i, vpdc; 295 296 reg = CSR_READ_4(sc, ALE_SPI_CTRL); 297 if ((reg & SPI_VPD_ENB) != 0) { 298 reg &= ~SPI_VPD_ENB; 299 CSR_WRITE_4(sc, ALE_SPI_CTRL, reg); 300 } 301 302 if (pci_get_capability(sc->sc_pct, sc->sc_pcitag, PCI_CAP_VPD, 303 &vpdc, NULL)) { 304 /* 305 * PCI VPD capability found, let TWSI reload EEPROM. 306 * This will set ethernet address of controller. 307 */ 308 CSR_WRITE_4(sc, ALE_TWSI_CTRL, CSR_READ_4(sc, ALE_TWSI_CTRL) | 309 TWSI_CTRL_SW_LD_START); 310 for (i = 100; i > 0; i--) { 311 DELAY(1000); 312 reg = CSR_READ_4(sc, ALE_TWSI_CTRL); 313 if ((reg & TWSI_CTRL_SW_LD_START) == 0) 314 break; 315 } 316 if (i == 0) 317 printf("%s: reloading EEPROM timeout!\n", 318 device_xname(sc->sc_dev)); 319 } else { 320 if (aledebug) 321 printf("%s: PCI VPD capability not found!\n", 322 device_xname(sc->sc_dev)); 323 } 324 325 ea[0] = CSR_READ_4(sc, ALE_PAR0); 326 ea[1] = CSR_READ_4(sc, ALE_PAR1); 327 sc->ale_eaddr[0] = (ea[1] >> 8) & 0xFF; 328 sc->ale_eaddr[1] = (ea[1] >> 0) & 0xFF; 329 sc->ale_eaddr[2] = (ea[0] >> 24) & 0xFF; 330 sc->ale_eaddr[3] = (ea[0] >> 16) & 0xFF; 331 sc->ale_eaddr[4] = (ea[0] >> 8) & 0xFF; 332 sc->ale_eaddr[5] = (ea[0] >> 0) & 0xFF; 333 } 334 335 void 336 ale_phy_reset(struct ale_softc *sc) 337 { 338 /* Reset magic from Linux. */ 339 CSR_WRITE_2(sc, ALE_GPHY_CTRL, 340 GPHY_CTRL_HIB_EN | GPHY_CTRL_HIB_PULSE | GPHY_CTRL_SEL_ANA_RESET | 341 GPHY_CTRL_PHY_PLL_ON); 342 DELAY(1000); 343 CSR_WRITE_2(sc, ALE_GPHY_CTRL, 344 GPHY_CTRL_EXT_RESET | GPHY_CTRL_HIB_EN | GPHY_CTRL_HIB_PULSE | 345 GPHY_CTRL_SEL_ANA_RESET | GPHY_CTRL_PHY_PLL_ON); 346 DELAY(1000); 347 348 #define ATPHY_DBG_ADDR 0x1D 349 #define ATPHY_DBG_DATA 0x1E 350 351 /* Enable hibernation mode. */ 352 ale_miibus_writereg(sc->sc_dev, sc->ale_phyaddr, 353 ATPHY_DBG_ADDR, 0x0B); 354 ale_miibus_writereg(sc->sc_dev, sc->ale_phyaddr, 355 ATPHY_DBG_DATA, 0xBC00); 356 /* Set Class A/B for all modes. */ 357 ale_miibus_writereg(sc->sc_dev, sc->ale_phyaddr, 358 ATPHY_DBG_ADDR, 0x00); 359 ale_miibus_writereg(sc->sc_dev, sc->ale_phyaddr, 360 ATPHY_DBG_DATA, 0x02EF); 361 /* Enable 10BT power saving. */ 362 ale_miibus_writereg(sc->sc_dev, sc->ale_phyaddr, 363 ATPHY_DBG_ADDR, 0x12); 364 ale_miibus_writereg(sc->sc_dev, sc->ale_phyaddr, 365 ATPHY_DBG_DATA, 0x4C04); 366 /* Adjust 1000T power. */ 367 ale_miibus_writereg(sc->sc_dev, sc->ale_phyaddr, 368 ATPHY_DBG_ADDR, 0x04); 369 ale_miibus_writereg(sc->sc_dev, sc->ale_phyaddr, 370 ATPHY_DBG_DATA, 0x8BBB); 371 /* 10BT center tap voltage. */ 372 ale_miibus_writereg(sc->sc_dev, sc->ale_phyaddr, 373 ATPHY_DBG_ADDR, 0x05); 374 ale_miibus_writereg(sc->sc_dev, sc->ale_phyaddr, 375 ATPHY_DBG_DATA, 0x2C46); 376 377 #undef ATPHY_DBG_ADDR 378 #undef ATPHY_DBG_DATA 379 DELAY(1000); 380 } 381 382 void 383 ale_attach(device_t parent, device_t self, void *aux) 384 { 385 struct ale_softc *sc = device_private(self); 386 struct pci_attach_args *pa = aux; 387 pci_chipset_tag_t pc = pa->pa_pc; 388 pci_intr_handle_t ih; 389 const char *intrstr; 390 struct ifnet *ifp; 391 struct mii_data * const mii = &sc->sc_miibus; 392 pcireg_t memtype; 393 int mii_flags, error = 0; 394 uint32_t rxf_len, txf_len; 395 const char *chipname; 396 char intrbuf[PCI_INTRSTR_LEN]; 397 398 aprint_naive("\n"); 399 aprint_normal(": Attansic/Atheros L1E Ethernet\n"); 400 401 sc->sc_dev = self; 402 sc->sc_dmat = pa->pa_dmat; 403 sc->sc_pct = pa->pa_pc; 404 sc->sc_pcitag = pa->pa_tag; 405 406 /* 407 * Allocate IO memory 408 */ 409 memtype = pci_mapreg_type(sc->sc_pct, sc->sc_pcitag, ALE_PCIR_BAR); 410 switch (memtype) { 411 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 412 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT_1M: 413 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 414 break; 415 default: 416 aprint_error_dev(self, "invalid base address register\n"); 417 break; 418 } 419 420 if (pci_mapreg_map(pa, ALE_PCIR_BAR, memtype, 0, &sc->sc_mem_bt, 421 &sc->sc_mem_bh, NULL, &sc->sc_mem_size)) { 422 aprint_error_dev(self, "could not map mem space\n"); 423 return; 424 } 425 426 if (pci_intr_map(pa, &ih) != 0) { 427 aprint_error_dev(self, "could not map interrupt\n"); 428 goto fail; 429 } 430 431 /* 432 * Allocate IRQ 433 */ 434 intrstr = pci_intr_string(sc->sc_pct, ih, intrbuf, sizeof(intrbuf)); 435 sc->sc_irq_handle = pci_intr_establish_xname(pc, ih, IPL_NET, ale_intr, 436 sc, device_xname(self)); 437 if (sc->sc_irq_handle == NULL) { 438 aprint_error_dev(self, "could not establish interrupt"); 439 if (intrstr != NULL) 440 aprint_error(" at %s", intrstr); 441 aprint_error("\n"); 442 goto fail; 443 } 444 445 /* Set PHY address. */ 446 sc->ale_phyaddr = ALE_PHY_ADDR; 447 448 /* Reset PHY. */ 449 ale_phy_reset(sc); 450 451 /* Reset the ethernet controller. */ 452 ale_reset(sc); 453 454 /* Get PCI and chip id/revision. */ 455 sc->ale_rev = PCI_REVISION(pa->pa_class); 456 if (sc->ale_rev >= 0xF0) { 457 /* L2E Rev. B. AR8114 */ 458 sc->ale_flags |= ALE_FLAG_FASTETHER; 459 chipname = "AR8114 (L2E RevB)"; 460 } else { 461 if ((CSR_READ_4(sc, ALE_PHY_STATUS) & PHY_STATUS_100M) != 0) { 462 /* L1E AR8121 */ 463 sc->ale_flags |= ALE_FLAG_JUMBO; 464 chipname = "AR8121 (L1E)"; 465 } else { 466 /* L2E Rev. A. AR8113 */ 467 sc->ale_flags |= ALE_FLAG_FASTETHER; 468 chipname = "AR8113 (L2E RevA)"; 469 } 470 } 471 aprint_normal_dev(self, "%s, %s\n", chipname, intrstr); 472 473 /* 474 * All known controllers seems to require 4 bytes alignment 475 * of Tx buffers to make Tx checksum offload with custom 476 * checksum generation method work. 477 */ 478 sc->ale_flags |= ALE_FLAG_TXCSUM_BUG; 479 480 /* 481 * All known controllers seems to have issues on Rx checksum 482 * offload for fragmented IP datagrams. 483 */ 484 sc->ale_flags |= ALE_FLAG_RXCSUM_BUG; 485 486 /* 487 * Don't use Tx CMB. It is known to cause RRS update failure 488 * under certain circumstances. Typical phenomenon of the 489 * issue would be unexpected sequence number encountered in 490 * Rx handler. 491 */ 492 sc->ale_flags |= ALE_FLAG_TXCMB_BUG; 493 sc->ale_chip_rev = CSR_READ_4(sc, ALE_MASTER_CFG) >> 494 MASTER_CHIP_REV_SHIFT; 495 aprint_debug_dev(self, "PCI device revision : 0x%04x\n", sc->ale_rev); 496 aprint_debug_dev(self, "Chip id/revision : 0x%04x\n", sc->ale_chip_rev); 497 498 /* 499 * Uninitialized hardware returns an invalid chip id/revision 500 * as well as 0xFFFFFFFF for Tx/Rx fifo length. 501 */ 502 txf_len = CSR_READ_4(sc, ALE_SRAM_TX_FIFO_LEN); 503 rxf_len = CSR_READ_4(sc, ALE_SRAM_RX_FIFO_LEN); 504 if (sc->ale_chip_rev == 0xFFFF || txf_len == 0xFFFFFFFF || 505 rxf_len == 0xFFFFFFF) { 506 aprint_error_dev(self, "chip revision : 0x%04x, %u Tx FIFO " 507 "%u Rx FIFO -- not initialized?\n", 508 sc->ale_chip_rev, txf_len, rxf_len); 509 goto fail; 510 } 511 512 if (aledebug) { 513 printf("%s: %u Tx FIFO, %u Rx FIFO\n", device_xname(sc->sc_dev), 514 txf_len, rxf_len); 515 } 516 517 /* Set max allowable DMA size. */ 518 sc->ale_dma_rd_burst = DMA_CFG_RD_BURST_128; 519 sc->ale_dma_wr_burst = DMA_CFG_WR_BURST_128; 520 521 callout_init(&sc->sc_tick_ch, 0); 522 callout_setfunc(&sc->sc_tick_ch, ale_tick, sc); 523 524 error = ale_dma_alloc(sc); 525 if (error) 526 goto fail; 527 528 /* Load station address. */ 529 ale_get_macaddr(sc); 530 531 aprint_normal_dev(self, "Ethernet address %s\n", 532 ether_sprintf(sc->ale_eaddr)); 533 534 ifp = &sc->sc_ec.ec_if; 535 ifp->if_softc = sc; 536 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 537 ifp->if_init = ale_init; 538 ifp->if_ioctl = ale_ioctl; 539 ifp->if_start = ale_start; 540 ifp->if_stop = ale_stop; 541 ifp->if_watchdog = ale_watchdog; 542 IFQ_SET_MAXLEN(&ifp->if_snd, ALE_TX_RING_CNT - 1); 543 IFQ_SET_READY(&ifp->if_snd); 544 strlcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 545 546 sc->sc_ec.ec_capabilities = ETHERCAP_VLAN_MTU; 547 548 #ifdef ALE_CHECKSUM 549 ifp->if_capabilities |= IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 550 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 551 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 552 #endif 553 554 #if NVLAN > 0 555 sc->sc_ec.ec_capabilities |= ETHERCAP_VLAN_HWTAGGING; 556 sc->sc_ec.ec_capenable |= ETHERCAP_VLAN_HWTAGGING; 557 #endif 558 559 /* Set up MII bus. */ 560 mii->mii_ifp = ifp; 561 mii->mii_readreg = ale_miibus_readreg; 562 mii->mii_writereg = ale_miibus_writereg; 563 mii->mii_statchg = ale_miibus_statchg; 564 565 sc->sc_ec.ec_mii = mii; 566 ifmedia_init(&mii->mii_media, 0, ale_mediachange, ale_mediastatus); 567 mii_flags = 0; 568 if ((sc->ale_flags & ALE_FLAG_JUMBO) != 0) 569 mii_flags |= MIIF_DOPAUSE; 570 mii_attach(self, mii, 0xffffffff, MII_PHY_ANY, 571 MII_OFFSET_ANY, mii_flags); 572 573 if (LIST_FIRST(&mii->mii_phys) == NULL) { 574 aprint_error_dev(self, "no PHY found!\n"); 575 ifmedia_add(&mii->mii_media, IFM_ETHER | IFM_MANUAL, 0, NULL); 576 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_MANUAL); 577 } else 578 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_AUTO); 579 580 if_attach(ifp); 581 if_deferred_start_init(ifp, NULL); 582 ether_ifattach(ifp, sc->ale_eaddr); 583 584 if (pmf_device_register(self, NULL, NULL)) 585 pmf_class_network_register(self, ifp); 586 else 587 aprint_error_dev(self, "couldn't establish power handler\n"); 588 589 return; 590 fail: 591 ale_dma_free(sc); 592 if (sc->sc_irq_handle != NULL) { 593 pci_intr_disestablish(pc, sc->sc_irq_handle); 594 sc->sc_irq_handle = NULL; 595 } 596 if (sc->sc_mem_size) { 597 bus_space_unmap(sc->sc_mem_bt, sc->sc_mem_bh, sc->sc_mem_size); 598 sc->sc_mem_size = 0; 599 } 600 } 601 602 static int 603 ale_detach(device_t self, int flags) 604 { 605 struct ale_softc *sc = device_private(self); 606 struct ifnet *ifp = &sc->sc_ec.ec_if; 607 int s; 608 609 pmf_device_deregister(self); 610 s = splnet(); 611 ale_stop(ifp, 0); 612 splx(s); 613 614 mii_detach(&sc->sc_miibus, MII_PHY_ANY, MII_OFFSET_ANY); 615 616 ether_ifdetach(ifp); 617 if_detach(ifp); 618 ale_dma_free(sc); 619 620 /* Delete all remaining media. */ 621 ifmedia_fini(&sc->sc_miibus.mii_media); 622 623 if (sc->sc_irq_handle != NULL) { 624 pci_intr_disestablish(sc->sc_pct, sc->sc_irq_handle); 625 sc->sc_irq_handle = NULL; 626 } 627 if (sc->sc_mem_size) { 628 bus_space_unmap(sc->sc_mem_bt, sc->sc_mem_bh, sc->sc_mem_size); 629 sc->sc_mem_size = 0; 630 } 631 632 return 0; 633 } 634 635 636 static int 637 ale_dma_alloc(struct ale_softc *sc) 638 { 639 struct ale_txdesc *txd; 640 int nsegs, error, guard_size, i; 641 642 if ((sc->ale_flags & ALE_FLAG_JUMBO) != 0) 643 guard_size = ALE_JUMBO_FRAMELEN; 644 else 645 guard_size = ALE_MAX_FRAMELEN; 646 sc->ale_pagesize = roundup(guard_size + ALE_RX_PAGE_SZ, 647 ALE_RX_PAGE_ALIGN); 648 649 /* 650 * Create DMA stuffs for TX ring 651 */ 652 error = bus_dmamap_create(sc->sc_dmat, ALE_TX_RING_SZ, 1, 653 ALE_TX_RING_SZ, 0, BUS_DMA_NOWAIT, &sc->ale_cdata.ale_tx_ring_map); 654 if (error) { 655 sc->ale_cdata.ale_tx_ring_map = NULL; 656 return ENOBUFS; 657 } 658 659 /* Allocate DMA'able memory for TX ring */ 660 error = bus_dmamem_alloc(sc->sc_dmat, ALE_TX_RING_SZ, 661 PAGE_SIZE, 0, &sc->ale_cdata.ale_tx_ring_seg, 1, 662 &nsegs, BUS_DMA_WAITOK); 663 if (error) { 664 printf("%s: could not allocate DMA'able memory for Tx ring, " 665 "error = %i\n", device_xname(sc->sc_dev), error); 666 return error; 667 } 668 669 error = bus_dmamem_map(sc->sc_dmat, &sc->ale_cdata.ale_tx_ring_seg, 670 nsegs, ALE_TX_RING_SZ, (void **)&sc->ale_cdata.ale_tx_ring, 671 BUS_DMA_NOWAIT); 672 if (error) 673 return ENOBUFS; 674 675 memset(sc->ale_cdata.ale_tx_ring, 0, ALE_TX_RING_SZ); 676 677 /* Load the DMA map for Tx ring. */ 678 error = bus_dmamap_load(sc->sc_dmat, sc->ale_cdata.ale_tx_ring_map, 679 sc->ale_cdata.ale_tx_ring, ALE_TX_RING_SZ, NULL, BUS_DMA_WAITOK); 680 if (error) { 681 printf("%s: could not load DMA'able memory for Tx ring.\n", 682 device_xname(sc->sc_dev)); 683 bus_dmamem_free(sc->sc_dmat, 684 &sc->ale_cdata.ale_tx_ring_seg, 1); 685 return error; 686 } 687 sc->ale_cdata.ale_tx_ring_paddr = 688 sc->ale_cdata.ale_tx_ring_map->dm_segs[0].ds_addr; 689 690 for (i = 0; i < ALE_RX_PAGES; i++) { 691 /* 692 * Create DMA stuffs for RX pages 693 */ 694 error = bus_dmamap_create(sc->sc_dmat, sc->ale_pagesize, 1, 695 sc->ale_pagesize, 0, BUS_DMA_NOWAIT, 696 &sc->ale_cdata.ale_rx_page[i].page_map); 697 if (error) { 698 sc->ale_cdata.ale_rx_page[i].page_map = NULL; 699 return ENOBUFS; 700 } 701 702 /* Allocate DMA'able memory for RX pages */ 703 error = bus_dmamem_alloc(sc->sc_dmat, sc->ale_pagesize, 704 PAGE_SIZE, 0, &sc->ale_cdata.ale_rx_page[i].page_seg, 705 1, &nsegs, BUS_DMA_WAITOK); 706 if (error) { 707 printf("%s: could not allocate DMA'able memory for " 708 "Rx ring.\n", device_xname(sc->sc_dev)); 709 return error; 710 } 711 error = bus_dmamem_map(sc->sc_dmat, 712 &sc->ale_cdata.ale_rx_page[i].page_seg, nsegs, 713 sc->ale_pagesize, 714 (void **)&sc->ale_cdata.ale_rx_page[i].page_addr, 715 BUS_DMA_NOWAIT); 716 if (error) 717 return ENOBUFS; 718 719 memset(sc->ale_cdata.ale_rx_page[i].page_addr, 0, 720 sc->ale_pagesize); 721 722 /* Load the DMA map for Rx pages. */ 723 error = bus_dmamap_load(sc->sc_dmat, 724 sc->ale_cdata.ale_rx_page[i].page_map, 725 sc->ale_cdata.ale_rx_page[i].page_addr, 726 sc->ale_pagesize, NULL, BUS_DMA_WAITOK); 727 if (error) { 728 printf("%s: could not load DMA'able memory for " 729 "Rx pages.\n", device_xname(sc->sc_dev)); 730 bus_dmamem_free(sc->sc_dmat, 731 &sc->ale_cdata.ale_rx_page[i].page_seg, 1); 732 return error; 733 } 734 sc->ale_cdata.ale_rx_page[i].page_paddr = 735 sc->ale_cdata.ale_rx_page[i].page_map->dm_segs[0].ds_addr; 736 } 737 738 /* 739 * Create DMA stuffs for Tx CMB. 740 */ 741 error = bus_dmamap_create(sc->sc_dmat, ALE_TX_CMB_SZ, 1, 742 ALE_TX_CMB_SZ, 0, BUS_DMA_NOWAIT, &sc->ale_cdata.ale_tx_cmb_map); 743 if (error) { 744 sc->ale_cdata.ale_tx_cmb_map = NULL; 745 return ENOBUFS; 746 } 747 748 /* Allocate DMA'able memory for Tx CMB. */ 749 error = bus_dmamem_alloc(sc->sc_dmat, ALE_TX_CMB_SZ, PAGE_SIZE, 0, 750 &sc->ale_cdata.ale_tx_cmb_seg, 1, &nsegs, BUS_DMA_WAITOK); 751 752 if (error) { 753 printf("%s: could not allocate DMA'able memory for Tx CMB.\n", 754 device_xname(sc->sc_dev)); 755 return error; 756 } 757 758 error = bus_dmamem_map(sc->sc_dmat, &sc->ale_cdata.ale_tx_cmb_seg, 759 nsegs, ALE_TX_CMB_SZ, (void **)&sc->ale_cdata.ale_tx_cmb, 760 BUS_DMA_NOWAIT); 761 if (error) 762 return ENOBUFS; 763 764 memset(sc->ale_cdata.ale_tx_cmb, 0, ALE_TX_CMB_SZ); 765 766 /* Load the DMA map for Tx CMB. */ 767 error = bus_dmamap_load(sc->sc_dmat, sc->ale_cdata.ale_tx_cmb_map, 768 sc->ale_cdata.ale_tx_cmb, ALE_TX_CMB_SZ, NULL, BUS_DMA_WAITOK); 769 if (error) { 770 printf("%s: could not load DMA'able memory for Tx CMB.\n", 771 device_xname(sc->sc_dev)); 772 bus_dmamem_free(sc->sc_dmat, 773 &sc->ale_cdata.ale_tx_cmb_seg, 1); 774 return error; 775 } 776 777 sc->ale_cdata.ale_tx_cmb_paddr = 778 sc->ale_cdata.ale_tx_cmb_map->dm_segs[0].ds_addr; 779 780 for (i = 0; i < ALE_RX_PAGES; i++) { 781 /* 782 * Create DMA stuffs for Rx CMB. 783 */ 784 error = bus_dmamap_create(sc->sc_dmat, ALE_RX_CMB_SZ, 1, 785 ALE_RX_CMB_SZ, 0, BUS_DMA_NOWAIT, 786 &sc->ale_cdata.ale_rx_page[i].cmb_map); 787 if (error) { 788 sc->ale_cdata.ale_rx_page[i].cmb_map = NULL; 789 return ENOBUFS; 790 } 791 792 /* Allocate DMA'able memory for Rx CMB */ 793 error = bus_dmamem_alloc(sc->sc_dmat, ALE_RX_CMB_SZ, 794 PAGE_SIZE, 0, &sc->ale_cdata.ale_rx_page[i].cmb_seg, 1, 795 &nsegs, BUS_DMA_WAITOK); 796 if (error) { 797 printf("%s: could not allocate DMA'able memory for " 798 "Rx CMB\n", device_xname(sc->sc_dev)); 799 return error; 800 } 801 error = bus_dmamem_map(sc->sc_dmat, 802 &sc->ale_cdata.ale_rx_page[i].cmb_seg, nsegs, 803 ALE_RX_CMB_SZ, 804 (void **)&sc->ale_cdata.ale_rx_page[i].cmb_addr, 805 BUS_DMA_NOWAIT); 806 if (error) 807 return ENOBUFS; 808 809 memset(sc->ale_cdata.ale_rx_page[i].cmb_addr, 0, ALE_RX_CMB_SZ); 810 811 /* Load the DMA map for Rx CMB */ 812 error = bus_dmamap_load(sc->sc_dmat, 813 sc->ale_cdata.ale_rx_page[i].cmb_map, 814 sc->ale_cdata.ale_rx_page[i].cmb_addr, 815 ALE_RX_CMB_SZ, NULL, BUS_DMA_WAITOK); 816 if (error) { 817 printf("%s: could not load DMA'able memory for Rx CMB" 818 "\n", device_xname(sc->sc_dev)); 819 bus_dmamem_free(sc->sc_dmat, 820 &sc->ale_cdata.ale_rx_page[i].cmb_seg, 1); 821 return error; 822 } 823 sc->ale_cdata.ale_rx_page[i].cmb_paddr = 824 sc->ale_cdata.ale_rx_page[i].cmb_map->dm_segs[0].ds_addr; 825 } 826 827 828 /* Create DMA maps for Tx buffers. */ 829 for (i = 0; i < ALE_TX_RING_CNT; i++) { 830 txd = &sc->ale_cdata.ale_txdesc[i]; 831 txd->tx_m = NULL; 832 txd->tx_dmamap = NULL; 833 error = bus_dmamap_create(sc->sc_dmat, ALE_TSO_MAXSIZE, 834 ALE_MAXTXSEGS, ALE_TSO_MAXSEGSIZE, 0, BUS_DMA_NOWAIT, 835 &txd->tx_dmamap); 836 if (error) { 837 txd->tx_dmamap = NULL; 838 printf("%s: could not create Tx dmamap.\n", 839 device_xname(sc->sc_dev)); 840 return error; 841 } 842 } 843 844 return 0; 845 } 846 847 static void 848 ale_dma_free(struct ale_softc *sc) 849 { 850 struct ale_txdesc *txd; 851 int i; 852 853 /* Tx buffers. */ 854 for (i = 0; i < ALE_TX_RING_CNT; i++) { 855 txd = &sc->ale_cdata.ale_txdesc[i]; 856 if (txd->tx_dmamap != NULL) { 857 bus_dmamap_destroy(sc->sc_dmat, txd->tx_dmamap); 858 txd->tx_dmamap = NULL; 859 } 860 } 861 862 /* Tx descriptor ring. */ 863 if (sc->ale_cdata.ale_tx_ring_map != NULL) 864 bus_dmamap_unload(sc->sc_dmat, sc->ale_cdata.ale_tx_ring_map); 865 if (sc->ale_cdata.ale_tx_ring_map != NULL && 866 sc->ale_cdata.ale_tx_ring != NULL) 867 bus_dmamem_free(sc->sc_dmat, 868 &sc->ale_cdata.ale_tx_ring_seg, 1); 869 sc->ale_cdata.ale_tx_ring = NULL; 870 sc->ale_cdata.ale_tx_ring_map = NULL; 871 872 /* Rx page block. */ 873 for (i = 0; i < ALE_RX_PAGES; i++) { 874 if (sc->ale_cdata.ale_rx_page[i].page_map != NULL) 875 bus_dmamap_unload(sc->sc_dmat, 876 sc->ale_cdata.ale_rx_page[i].page_map); 877 if (sc->ale_cdata.ale_rx_page[i].page_map != NULL && 878 sc->ale_cdata.ale_rx_page[i].page_addr != NULL) 879 bus_dmamem_free(sc->sc_dmat, 880 &sc->ale_cdata.ale_rx_page[i].page_seg, 1); 881 sc->ale_cdata.ale_rx_page[i].page_addr = NULL; 882 sc->ale_cdata.ale_rx_page[i].page_map = NULL; 883 } 884 885 /* Rx CMB. */ 886 for (i = 0; i < ALE_RX_PAGES; i++) { 887 if (sc->ale_cdata.ale_rx_page[i].cmb_map != NULL) 888 bus_dmamap_unload(sc->sc_dmat, 889 sc->ale_cdata.ale_rx_page[i].cmb_map); 890 if (sc->ale_cdata.ale_rx_page[i].cmb_map != NULL && 891 sc->ale_cdata.ale_rx_page[i].cmb_addr != NULL) 892 bus_dmamem_free(sc->sc_dmat, 893 &sc->ale_cdata.ale_rx_page[i].cmb_seg, 1); 894 sc->ale_cdata.ale_rx_page[i].cmb_addr = NULL; 895 sc->ale_cdata.ale_rx_page[i].cmb_map = NULL; 896 } 897 898 /* Tx CMB. */ 899 if (sc->ale_cdata.ale_tx_cmb_map != NULL) 900 bus_dmamap_unload(sc->sc_dmat, sc->ale_cdata.ale_tx_cmb_map); 901 if (sc->ale_cdata.ale_tx_cmb_map != NULL && 902 sc->ale_cdata.ale_tx_cmb != NULL) 903 bus_dmamem_free(sc->sc_dmat, 904 &sc->ale_cdata.ale_tx_cmb_seg, 1); 905 sc->ale_cdata.ale_tx_cmb = NULL; 906 sc->ale_cdata.ale_tx_cmb_map = NULL; 907 908 } 909 910 static int 911 ale_encap(struct ale_softc *sc, struct mbuf * const m) 912 { 913 struct ale_txdesc *txd, *txd_last; 914 struct tx_desc *desc; 915 bus_dmamap_t map; 916 uint32_t cflags, poff, vtag; 917 int error, i, nsegs, prod; 918 919 cflags = vtag = 0; 920 poff = 0; 921 922 prod = sc->ale_cdata.ale_tx_prod; 923 txd = &sc->ale_cdata.ale_txdesc[prod]; 924 txd_last = txd; 925 map = txd->tx_dmamap; 926 927 error = bus_dmamap_load_mbuf(sc->sc_dmat, map, m, BUS_DMA_NOWAIT); 928 if (error == EFBIG) { 929 struct mbuf *mnew = m_defrag(m, M_NOWAIT); 930 if (mnew != NULL) { 931 KASSERT(m == mnew); 932 error = bus_dmamap_load_mbuf(sc->sc_dmat, map, mnew, 933 BUS_DMA_NOWAIT); 934 } 935 if (mnew == NULL || error == EFBIG) { 936 printf("%s: Tx packet consumes too many " 937 "DMA segments, dropping...\n", 938 device_xname(sc->sc_dev)); 939 return EFBIG; 940 } 941 } else if (error != 0) { 942 return error; 943 } 944 945 nsegs = map->dm_nsegs; 946 KASSERT(nsegs != 0); 947 948 /* Check descriptor overrun. */ 949 if (sc->ale_cdata.ale_tx_cnt + nsegs >= ALE_TX_RING_CNT - 2) { 950 bus_dmamap_unload(sc->sc_dmat, map); 951 return ENOBUFS; 952 } 953 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 954 BUS_DMASYNC_PREWRITE); 955 956 /* Configure Tx checksum offload. */ 957 if ((m->m_pkthdr.csum_flags & ALE_CSUM_FEATURES) != 0) { 958 /* 959 * AR81xx supports Tx custom checksum offload feature 960 * that offloads single 16bit checksum computation. 961 * So you can choose one among IP, TCP and UDP. 962 * Normally driver sets checksum start/insertion 963 * position from the information of TCP/UDP frame as 964 * TCP/UDP checksum takes more time than that of IP. 965 * However it seems that custom checksum offload 966 * requires 4 bytes aligned Tx buffers due to hardware 967 * bug. 968 * AR81xx also supports explicit Tx checksum computation 969 * if it is told that the size of IP header and TCP 970 * header(for UDP, the header size does not matter 971 * because it's fixed length). However with this scheme 972 * TSO does not work so you have to choose one either 973 * TSO or explicit Tx checksum offload. I chosen TSO 974 * plus custom checksum offload with work-around which 975 * will cover most common usage for this consumer 976 * ethernet controller. The work-around takes a lot of 977 * CPU cycles if Tx buffer is not aligned on 4 bytes 978 * boundary, though. 979 */ 980 cflags |= ALE_TD_CXSUM; 981 /* Set checksum start offset. */ 982 cflags |= (poff << ALE_TD_CSUM_PLOADOFFSET_SHIFT); 983 } 984 985 #if NVLAN > 0 986 /* Configure VLAN hardware tag insertion. */ 987 if (vlan_has_tag(m)) { 988 vtag = ALE_TX_VLAN_TAG(htons(vlan_get_tag(m))); 989 vtag = ((vtag << ALE_TD_VLAN_SHIFT) & ALE_TD_VLAN_MASK); 990 cflags |= ALE_TD_INSERT_VLAN_TAG; 991 } 992 #endif 993 994 desc = NULL; 995 for (i = 0; i < nsegs; i++) { 996 desc = &sc->ale_cdata.ale_tx_ring[prod]; 997 desc->addr = htole64(map->dm_segs[i].ds_addr); 998 desc->len = 999 htole32(ALE_TX_BYTES(map->dm_segs[i].ds_len) | vtag); 1000 desc->flags = htole32(cflags); 1001 sc->ale_cdata.ale_tx_cnt++; 1002 ALE_DESC_INC(prod, ALE_TX_RING_CNT); 1003 } 1004 /* Update producer index. */ 1005 sc->ale_cdata.ale_tx_prod = prod; 1006 1007 /* Finally set EOP on the last descriptor. */ 1008 prod = (prod + ALE_TX_RING_CNT - 1) % ALE_TX_RING_CNT; 1009 desc = &sc->ale_cdata.ale_tx_ring[prod]; 1010 desc->flags |= htole32(ALE_TD_EOP); 1011 1012 /* Swap dmamap of the first and the last. */ 1013 txd = &sc->ale_cdata.ale_txdesc[prod]; 1014 map = txd_last->tx_dmamap; 1015 txd_last->tx_dmamap = txd->tx_dmamap; 1016 txd->tx_dmamap = map; 1017 txd->tx_m = m; 1018 1019 /* Sync descriptors. */ 1020 bus_dmamap_sync(sc->sc_dmat, sc->ale_cdata.ale_tx_ring_map, 0, 1021 sc->ale_cdata.ale_tx_ring_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 1022 1023 return 0; 1024 } 1025 1026 static void 1027 ale_start(struct ifnet *ifp) 1028 { 1029 struct ale_softc *sc = ifp->if_softc; 1030 struct mbuf *m_head; 1031 int enq, error; 1032 1033 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 1034 return; 1035 1036 /* Reclaim transmitted frames. */ 1037 if (sc->ale_cdata.ale_tx_cnt >= ALE_TX_DESC_HIWAT) 1038 ale_txeof(sc); 1039 1040 enq = 0; 1041 for (;;) { 1042 IFQ_DEQUEUE(&ifp->if_snd, m_head); 1043 if (m_head == NULL) 1044 break; 1045 1046 /* 1047 * Pack the data into the transmit ring. If we 1048 * don't have room, set the OACTIVE flag and wait 1049 * for the NIC to drain the ring. 1050 */ 1051 if ((error = ale_encap(sc, m_head)) != 0) { 1052 if (error == EFBIG) { 1053 /* This is fatal for the packet. */ 1054 m_freem(m_head); 1055 if_statinc(ifp, if_oerrors); 1056 continue; 1057 } 1058 IF_PREPEND(&ifp->if_snd, m_head); 1059 ifp->if_flags |= IFF_OACTIVE; 1060 break; 1061 } 1062 enq = 1; 1063 1064 /* 1065 * If there's a BPF listener, bounce a copy of this frame 1066 * to him. 1067 */ 1068 bpf_mtap(ifp, m_head, BPF_D_OUT); 1069 } 1070 1071 if (enq) { 1072 /* Kick. */ 1073 CSR_WRITE_4(sc, ALE_MBOX_TPD_PROD_IDX, 1074 sc->ale_cdata.ale_tx_prod); 1075 1076 /* Set a timeout in case the chip goes out to lunch. */ 1077 ifp->if_timer = ALE_TX_TIMEOUT; 1078 } 1079 } 1080 1081 static void 1082 ale_watchdog(struct ifnet *ifp) 1083 { 1084 struct ale_softc *sc = ifp->if_softc; 1085 1086 if ((sc->ale_flags & ALE_FLAG_LINK) == 0) { 1087 printf("%s: watchdog timeout (missed link)\n", 1088 device_xname(sc->sc_dev)); 1089 if_statinc(ifp, if_oerrors); 1090 ale_init(ifp); 1091 return; 1092 } 1093 1094 printf("%s: watchdog timeout\n", device_xname(sc->sc_dev)); 1095 if_statinc(ifp, if_oerrors); 1096 ale_init(ifp); 1097 1098 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 1099 ale_start(ifp); 1100 } 1101 1102 static int 1103 ale_ioctl(struct ifnet *ifp, u_long cmd, void *data) 1104 { 1105 struct ale_softc *sc = ifp->if_softc; 1106 int s, error; 1107 1108 s = splnet(); 1109 1110 error = ether_ioctl(ifp, cmd, data); 1111 if (error == ENETRESET) { 1112 if (ifp->if_flags & IFF_RUNNING) 1113 ale_rxfilter(sc); 1114 error = 0; 1115 } 1116 1117 splx(s); 1118 return error; 1119 } 1120 1121 static void 1122 ale_mac_config(struct ale_softc *sc) 1123 { 1124 struct mii_data *mii; 1125 uint32_t reg; 1126 1127 mii = &sc->sc_miibus; 1128 reg = CSR_READ_4(sc, ALE_MAC_CFG); 1129 reg &= ~(MAC_CFG_FULL_DUPLEX | MAC_CFG_TX_FC | MAC_CFG_RX_FC | 1130 MAC_CFG_SPEED_MASK); 1131 1132 /* Reprogram MAC with resolved speed/duplex. */ 1133 switch (IFM_SUBTYPE(mii->mii_media_active)) { 1134 case IFM_10_T: 1135 case IFM_100_TX: 1136 reg |= MAC_CFG_SPEED_10_100; 1137 break; 1138 case IFM_1000_T: 1139 reg |= MAC_CFG_SPEED_1000; 1140 break; 1141 } 1142 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 1143 reg |= MAC_CFG_FULL_DUPLEX; 1144 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0) 1145 reg |= MAC_CFG_TX_FC; 1146 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0) 1147 reg |= MAC_CFG_RX_FC; 1148 } 1149 CSR_WRITE_4(sc, ALE_MAC_CFG, reg); 1150 } 1151 1152 static void 1153 ale_stats_clear(struct ale_softc *sc) 1154 { 1155 struct smb sb; 1156 uint32_t *reg; 1157 int i; 1158 1159 for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered; reg++) { 1160 CSR_READ_4(sc, ALE_RX_MIB_BASE + i); 1161 i += sizeof(uint32_t); 1162 } 1163 /* Read Tx statistics. */ 1164 for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes; reg++) { 1165 CSR_READ_4(sc, ALE_TX_MIB_BASE + i); 1166 i += sizeof(uint32_t); 1167 } 1168 } 1169 1170 static void 1171 ale_stats_update(struct ale_softc *sc) 1172 { 1173 struct ifnet *ifp = &sc->sc_ec.ec_if; 1174 struct ale_hw_stats *stat; 1175 struct smb sb, *smb; 1176 uint32_t *reg; 1177 int i; 1178 1179 stat = &sc->ale_stats; 1180 smb = &sb; 1181 1182 /* Read Rx statistics. */ 1183 for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered; reg++) { 1184 *reg = CSR_READ_4(sc, ALE_RX_MIB_BASE + i); 1185 i += sizeof(uint32_t); 1186 } 1187 /* Read Tx statistics. */ 1188 for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes; reg++) { 1189 *reg = CSR_READ_4(sc, ALE_TX_MIB_BASE + i); 1190 i += sizeof(uint32_t); 1191 } 1192 1193 /* Rx stats. */ 1194 stat->rx_frames += smb->rx_frames; 1195 stat->rx_bcast_frames += smb->rx_bcast_frames; 1196 stat->rx_mcast_frames += smb->rx_mcast_frames; 1197 stat->rx_pause_frames += smb->rx_pause_frames; 1198 stat->rx_control_frames += smb->rx_control_frames; 1199 stat->rx_crcerrs += smb->rx_crcerrs; 1200 stat->rx_lenerrs += smb->rx_lenerrs; 1201 stat->rx_bytes += smb->rx_bytes; 1202 stat->rx_runts += smb->rx_runts; 1203 stat->rx_fragments += smb->rx_fragments; 1204 stat->rx_pkts_64 += smb->rx_pkts_64; 1205 stat->rx_pkts_65_127 += smb->rx_pkts_65_127; 1206 stat->rx_pkts_128_255 += smb->rx_pkts_128_255; 1207 stat->rx_pkts_256_511 += smb->rx_pkts_256_511; 1208 stat->rx_pkts_512_1023 += smb->rx_pkts_512_1023; 1209 stat->rx_pkts_1024_1518 += smb->rx_pkts_1024_1518; 1210 stat->rx_pkts_1519_max += smb->rx_pkts_1519_max; 1211 stat->rx_pkts_truncated += smb->rx_pkts_truncated; 1212 stat->rx_fifo_oflows += smb->rx_fifo_oflows; 1213 stat->rx_rrs_errs += smb->rx_rrs_errs; 1214 stat->rx_alignerrs += smb->rx_alignerrs; 1215 stat->rx_bcast_bytes += smb->rx_bcast_bytes; 1216 stat->rx_mcast_bytes += smb->rx_mcast_bytes; 1217 stat->rx_pkts_filtered += smb->rx_pkts_filtered; 1218 1219 /* Tx stats. */ 1220 stat->tx_frames += smb->tx_frames; 1221 stat->tx_bcast_frames += smb->tx_bcast_frames; 1222 stat->tx_mcast_frames += smb->tx_mcast_frames; 1223 stat->tx_pause_frames += smb->tx_pause_frames; 1224 stat->tx_excess_defer += smb->tx_excess_defer; 1225 stat->tx_control_frames += smb->tx_control_frames; 1226 stat->tx_deferred += smb->tx_deferred; 1227 stat->tx_bytes += smb->tx_bytes; 1228 stat->tx_pkts_64 += smb->tx_pkts_64; 1229 stat->tx_pkts_65_127 += smb->tx_pkts_65_127; 1230 stat->tx_pkts_128_255 += smb->tx_pkts_128_255; 1231 stat->tx_pkts_256_511 += smb->tx_pkts_256_511; 1232 stat->tx_pkts_512_1023 += smb->tx_pkts_512_1023; 1233 stat->tx_pkts_1024_1518 += smb->tx_pkts_1024_1518; 1234 stat->tx_pkts_1519_max += smb->tx_pkts_1519_max; 1235 stat->tx_single_colls += smb->tx_single_colls; 1236 stat->tx_multi_colls += smb->tx_multi_colls; 1237 stat->tx_late_colls += smb->tx_late_colls; 1238 stat->tx_excess_colls += smb->tx_excess_colls; 1239 stat->tx_abort += smb->tx_abort; 1240 stat->tx_underrun += smb->tx_underrun; 1241 stat->tx_desc_underrun += smb->tx_desc_underrun; 1242 stat->tx_lenerrs += smb->tx_lenerrs; 1243 stat->tx_pkts_truncated += smb->tx_pkts_truncated; 1244 stat->tx_bcast_bytes += smb->tx_bcast_bytes; 1245 stat->tx_mcast_bytes += smb->tx_mcast_bytes; 1246 1247 /* Update counters in ifnet. */ 1248 net_stat_ref_t nsr = IF_STAT_GETREF(ifp); 1249 1250 if_statadd_ref(nsr, if_opackets, smb->tx_frames); 1251 1252 if_statadd_ref(nsr, if_collisions, 1253 smb->tx_single_colls + 1254 smb->tx_multi_colls * 2 + smb->tx_late_colls + 1255 smb->tx_abort * HDPX_CFG_RETRY_DEFAULT); 1256 1257 /* 1258 * XXX 1259 * tx_pkts_truncated counter looks suspicious. It constantly 1260 * increments with no sign of Tx errors. This may indicate 1261 * the counter name is not correct one so I've removed the 1262 * counter in output errors. 1263 */ 1264 if_statadd_ref(nsr, if_oerrors, 1265 smb->tx_abort + smb->tx_late_colls + 1266 smb->tx_underrun); 1267 1268 if_statadd_ref(nsr, if_ierrors, 1269 smb->rx_crcerrs + smb->rx_lenerrs + 1270 smb->rx_runts + smb->rx_pkts_truncated + 1271 smb->rx_fifo_oflows + smb->rx_rrs_errs + 1272 smb->rx_alignerrs); 1273 1274 IF_STAT_PUTREF(ifp); 1275 } 1276 1277 static int 1278 ale_intr(void *xsc) 1279 { 1280 struct ale_softc *sc = xsc; 1281 struct ifnet *ifp = &sc->sc_ec.ec_if; 1282 uint32_t status; 1283 1284 status = CSR_READ_4(sc, ALE_INTR_STATUS); 1285 if ((status & ALE_INTRS) == 0) 1286 return 0; 1287 1288 /* Acknowledge and disable interrupts. */ 1289 CSR_WRITE_4(sc, ALE_INTR_STATUS, status | INTR_DIS_INT); 1290 1291 if (ifp->if_flags & IFF_RUNNING) { 1292 int error; 1293 1294 error = ale_rxeof(sc); 1295 if (error) { 1296 sc->ale_stats.reset_brk_seq++; 1297 ale_init(ifp); 1298 return 0; 1299 } 1300 1301 if (status & (INTR_DMA_RD_TO_RST | INTR_DMA_WR_TO_RST)) { 1302 if (status & INTR_DMA_RD_TO_RST) 1303 printf("%s: DMA read error! -- resetting\n", 1304 device_xname(sc->sc_dev)); 1305 if (status & INTR_DMA_WR_TO_RST) 1306 printf("%s: DMA write error! -- resetting\n", 1307 device_xname(sc->sc_dev)); 1308 ale_init(ifp); 1309 return 0; 1310 } 1311 1312 ale_txeof(sc); 1313 if_schedule_deferred_start(ifp); 1314 } 1315 1316 /* Re-enable interrupts. */ 1317 CSR_WRITE_4(sc, ALE_INTR_STATUS, 0x7FFFFFFF); 1318 return 1; 1319 } 1320 1321 static void 1322 ale_txeof(struct ale_softc *sc) 1323 { 1324 struct ifnet *ifp = &sc->sc_ec.ec_if; 1325 struct ale_txdesc *txd; 1326 uint32_t cons, prod; 1327 int prog; 1328 1329 if (sc->ale_cdata.ale_tx_cnt == 0) 1330 return; 1331 1332 bus_dmamap_sync(sc->sc_dmat, sc->ale_cdata.ale_tx_ring_map, 0, 1333 sc->ale_cdata.ale_tx_ring_map->dm_mapsize, BUS_DMASYNC_POSTREAD); 1334 if ((sc->ale_flags & ALE_FLAG_TXCMB_BUG) == 0) { 1335 bus_dmamap_sync(sc->sc_dmat, sc->ale_cdata.ale_tx_cmb_map, 0, 1336 sc->ale_cdata.ale_tx_cmb_map->dm_mapsize, 1337 BUS_DMASYNC_POSTREAD); 1338 prod = *sc->ale_cdata.ale_tx_cmb & TPD_CNT_MASK; 1339 } else 1340 prod = CSR_READ_2(sc, ALE_TPD_CONS_IDX); 1341 cons = sc->ale_cdata.ale_tx_cons; 1342 /* 1343 * Go through our Tx list and free mbufs for those 1344 * frames which have been transmitted. 1345 */ 1346 for (prog = 0; cons != prod; prog++, 1347 ALE_DESC_INC(cons, ALE_TX_RING_CNT)) { 1348 if (sc->ale_cdata.ale_tx_cnt <= 0) 1349 break; 1350 prog++; 1351 ifp->if_flags &= ~IFF_OACTIVE; 1352 sc->ale_cdata.ale_tx_cnt--; 1353 txd = &sc->ale_cdata.ale_txdesc[cons]; 1354 if (txd->tx_m != NULL) { 1355 /* Reclaim transmitted mbufs. */ 1356 bus_dmamap_unload(sc->sc_dmat, txd->tx_dmamap); 1357 m_freem(txd->tx_m); 1358 txd->tx_m = NULL; 1359 } 1360 } 1361 1362 if (prog > 0) { 1363 sc->ale_cdata.ale_tx_cons = cons; 1364 /* 1365 * Unarm watchdog timer only when there is no pending 1366 * Tx descriptors in queue. 1367 */ 1368 if (sc->ale_cdata.ale_tx_cnt == 0) 1369 ifp->if_timer = 0; 1370 } 1371 } 1372 1373 static void 1374 ale_rx_update_page(struct ale_softc *sc, struct ale_rx_page **page, 1375 uint32_t length, uint32_t *prod) 1376 { 1377 struct ale_rx_page *rx_page; 1378 1379 rx_page = *page; 1380 /* Update consumer position. */ 1381 rx_page->cons += roundup(length + sizeof(struct rx_rs), 1382 ALE_RX_PAGE_ALIGN); 1383 if (rx_page->cons >= ALE_RX_PAGE_SZ) { 1384 /* 1385 * End of Rx page reached, let hardware reuse 1386 * this page. 1387 */ 1388 rx_page->cons = 0; 1389 *rx_page->cmb_addr = 0; 1390 bus_dmamap_sync(sc->sc_dmat, rx_page->cmb_map, 0, 1391 rx_page->cmb_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 1392 CSR_WRITE_1(sc, ALE_RXF0_PAGE0 + sc->ale_cdata.ale_rx_curp, 1393 RXF_VALID); 1394 /* Switch to alternate Rx page. */ 1395 sc->ale_cdata.ale_rx_curp ^= 1; 1396 rx_page = *page = 1397 &sc->ale_cdata.ale_rx_page[sc->ale_cdata.ale_rx_curp]; 1398 /* Page flipped, sync CMB and Rx page. */ 1399 bus_dmamap_sync(sc->sc_dmat, rx_page->page_map, 0, 1400 rx_page->page_map->dm_mapsize, BUS_DMASYNC_POSTREAD); 1401 bus_dmamap_sync(sc->sc_dmat, rx_page->cmb_map, 0, 1402 rx_page->cmb_map->dm_mapsize, BUS_DMASYNC_POSTREAD); 1403 /* Sync completed, cache updated producer index. */ 1404 *prod = *rx_page->cmb_addr; 1405 } 1406 } 1407 1408 1409 /* 1410 * It seems that AR81xx controller can compute partial checksum. 1411 * The partial checksum value can be used to accelerate checksum 1412 * computation for fragmented TCP/UDP packets. Upper network stack 1413 * already takes advantage of the partial checksum value in IP 1414 * reassembly stage. But I'm not sure the correctness of the 1415 * partial hardware checksum assistance due to lack of data sheet. 1416 * In addition, the Rx feature of controller that requires copying 1417 * for every frames effectively nullifies one of most nice offload 1418 * capability of controller. 1419 */ 1420 static void 1421 ale_rxcsum(struct ale_softc *sc, struct mbuf *m, uint32_t status) 1422 { 1423 if (status & ALE_RD_IPCSUM_NOK) 1424 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 1425 1426 if ((sc->ale_flags & ALE_FLAG_RXCSUM_BUG) == 0) { 1427 if (((status & ALE_RD_IPV4_FRAG) == 0) && 1428 ((status & (ALE_RD_TCP | ALE_RD_UDP)) != 0) && 1429 (status & ALE_RD_TCP_UDPCSUM_NOK)) 1430 { 1431 m->m_pkthdr.csum_flags |= M_CSUM_TCP_UDP_BAD; 1432 } 1433 } else { 1434 if ((status & (ALE_RD_TCP | ALE_RD_UDP)) != 0) { 1435 if (status & ALE_RD_TCP_UDPCSUM_NOK) { 1436 m->m_pkthdr.csum_flags |= M_CSUM_TCP_UDP_BAD; 1437 } 1438 } 1439 } 1440 /* 1441 * Don't mark bad checksum for TCP/UDP frames 1442 * as fragmented frames may always have set 1443 * bad checksummed bit of frame status. 1444 */ 1445 } 1446 1447 /* Process received frames. */ 1448 static int 1449 ale_rxeof(struct ale_softc *sc) 1450 { 1451 struct ifnet *ifp = &sc->sc_ec.ec_if; 1452 struct ale_rx_page *rx_page; 1453 struct rx_rs *rs; 1454 struct mbuf *m; 1455 uint32_t length, prod, seqno, status; 1456 int prog; 1457 1458 rx_page = &sc->ale_cdata.ale_rx_page[sc->ale_cdata.ale_rx_curp]; 1459 bus_dmamap_sync(sc->sc_dmat, rx_page->cmb_map, 0, 1460 rx_page->cmb_map->dm_mapsize, BUS_DMASYNC_POSTREAD); 1461 bus_dmamap_sync(sc->sc_dmat, rx_page->page_map, 0, 1462 rx_page->page_map->dm_mapsize, BUS_DMASYNC_POSTREAD); 1463 /* 1464 * Don't directly access producer index as hardware may 1465 * update it while Rx handler is in progress. It would 1466 * be even better if there is a way to let hardware 1467 * know how far driver processed its received frames. 1468 * Alternatively, hardware could provide a way to disable 1469 * CMB updates until driver acknowledges the end of CMB 1470 * access. 1471 */ 1472 prod = *rx_page->cmb_addr; 1473 for (prog = 0; ; prog++) { 1474 if (rx_page->cons >= prod) 1475 break; 1476 rs = (struct rx_rs *)(rx_page->page_addr + rx_page->cons); 1477 seqno = ALE_RX_SEQNO(le32toh(rs->seqno)); 1478 if (sc->ale_cdata.ale_rx_seqno != seqno) { 1479 /* 1480 * Normally I believe this should not happen unless 1481 * severe driver bug or corrupted memory. However 1482 * it seems to happen under certain conditions which 1483 * is triggered by abrupt Rx events such as initiation 1484 * of bulk transfer of remote host. It's not easy to 1485 * reproduce this and I doubt it could be related 1486 * with FIFO overflow of hardware or activity of Tx 1487 * CMB updates. I also remember similar behaviour 1488 * seen on RealTek 8139 which uses resembling Rx 1489 * scheme. 1490 */ 1491 if (aledebug) 1492 printf("%s: garbled seq: %u, expected: %u -- " 1493 "resetting!\n", device_xname(sc->sc_dev), 1494 seqno, sc->ale_cdata.ale_rx_seqno); 1495 return EIO; 1496 } 1497 /* Frame received. */ 1498 sc->ale_cdata.ale_rx_seqno++; 1499 length = ALE_RX_BYTES(le32toh(rs->length)); 1500 status = le32toh(rs->flags); 1501 if (status & ALE_RD_ERROR) { 1502 /* 1503 * We want to pass the following frames to upper 1504 * layer regardless of error status of Rx return 1505 * status. 1506 * 1507 * o IP/TCP/UDP checksum is bad. 1508 * o frame length and protocol specific length 1509 * does not match. 1510 */ 1511 if (status & (ALE_RD_CRC | ALE_RD_CODE | 1512 ALE_RD_DRIBBLE | ALE_RD_RUNT | ALE_RD_OFLOW | 1513 ALE_RD_TRUNC)) { 1514 ale_rx_update_page(sc, &rx_page, length, &prod); 1515 continue; 1516 } 1517 } 1518 /* 1519 * m_devget(9) is major bottle-neck of ale(4)(It comes 1520 * from hardware limitation). For jumbo frames we could 1521 * get a slightly better performance if driver use 1522 * m_getjcl(9) with proper buffer size argument. However 1523 * that would make code more complicated and I don't 1524 * think users would expect good Rx performance numbers 1525 * on these low-end consumer ethernet controller. 1526 */ 1527 m = m_devget((char *)(rs + 1), length - ETHER_CRC_LEN, 1528 0, ifp); 1529 if (m == NULL) { 1530 if_statinc(ifp, if_iqdrops); 1531 ale_rx_update_page(sc, &rx_page, length, &prod); 1532 continue; 1533 } 1534 if (status & ALE_RD_IPV4) 1535 ale_rxcsum(sc, m, status); 1536 #if NVLAN > 0 1537 if (status & ALE_RD_VLAN) { 1538 uint32_t vtags = ALE_RX_VLAN(le32toh(rs->vtags)); 1539 vlan_set_tag(m, ALE_RX_VLAN_TAG(vtags)); 1540 } 1541 #endif 1542 1543 /* Pass it to upper layer. */ 1544 if_percpuq_enqueue(ifp->if_percpuq, m); 1545 1546 ale_rx_update_page(sc, &rx_page, length, &prod); 1547 } 1548 1549 return 0; 1550 } 1551 1552 static void 1553 ale_tick(void *xsc) 1554 { 1555 struct ale_softc *sc = xsc; 1556 struct mii_data *mii = &sc->sc_miibus; 1557 int s; 1558 1559 s = splnet(); 1560 mii_tick(mii); 1561 ale_stats_update(sc); 1562 splx(s); 1563 1564 callout_schedule(&sc->sc_tick_ch, hz); 1565 } 1566 1567 static void 1568 ale_reset(struct ale_softc *sc) 1569 { 1570 uint32_t reg; 1571 int i; 1572 1573 /* Initialize PCIe module. From Linux. */ 1574 CSR_WRITE_4(sc, 0x1008, CSR_READ_4(sc, 0x1008) | 0x8000); 1575 1576 CSR_WRITE_4(sc, ALE_MASTER_CFG, MASTER_RESET); 1577 for (i = ALE_RESET_TIMEOUT; i > 0; i--) { 1578 DELAY(10); 1579 if ((CSR_READ_4(sc, ALE_MASTER_CFG) & MASTER_RESET) == 0) 1580 break; 1581 } 1582 if (i == 0) 1583 printf("%s: master reset timeout!\n", device_xname(sc->sc_dev)); 1584 1585 for (i = ALE_RESET_TIMEOUT; i > 0; i--) { 1586 if ((reg = CSR_READ_4(sc, ALE_IDLE_STATUS)) == 0) 1587 break; 1588 DELAY(10); 1589 } 1590 1591 if (i == 0) 1592 printf("%s: reset timeout(0x%08x)!\n", device_xname(sc->sc_dev), 1593 reg); 1594 } 1595 1596 static int 1597 ale_init(struct ifnet *ifp) 1598 { 1599 struct ale_softc *sc = ifp->if_softc; 1600 struct mii_data *mii; 1601 uint8_t eaddr[ETHER_ADDR_LEN]; 1602 bus_addr_t paddr; 1603 uint32_t reg, rxf_hi, rxf_lo; 1604 1605 /* 1606 * Cancel any pending I/O. 1607 */ 1608 ale_stop(ifp, 0); 1609 1610 /* 1611 * Reset the chip to a known state. 1612 */ 1613 ale_reset(sc); 1614 1615 /* Initialize Tx descriptors, DMA memory blocks. */ 1616 ale_init_rx_pages(sc); 1617 ale_init_tx_ring(sc); 1618 1619 /* Reprogram the station address. */ 1620 memcpy(eaddr, CLLADDR(ifp->if_sadl), ETHER_ADDR_LEN); 1621 CSR_WRITE_4(sc, ALE_PAR0, 1622 eaddr[2] << 24 | eaddr[3] << 16 | eaddr[4] << 8 | eaddr[5]); 1623 CSR_WRITE_4(sc, ALE_PAR1, eaddr[0] << 8 | eaddr[1]); 1624 1625 /* 1626 * Clear WOL status and disable all WOL feature as WOL 1627 * would interfere Rx operation under normal environments. 1628 */ 1629 CSR_READ_4(sc, ALE_WOL_CFG); 1630 CSR_WRITE_4(sc, ALE_WOL_CFG, 0); 1631 1632 /* 1633 * Set Tx descriptor/RXF0/CMB base addresses. They share 1634 * the same high address part of DMAable region. 1635 */ 1636 paddr = sc->ale_cdata.ale_tx_ring_paddr; 1637 CSR_WRITE_4(sc, ALE_TPD_ADDR_HI, ALE_ADDR_HI(paddr)); 1638 CSR_WRITE_4(sc, ALE_TPD_ADDR_LO, ALE_ADDR_LO(paddr)); 1639 CSR_WRITE_4(sc, ALE_TPD_CNT, 1640 (ALE_TX_RING_CNT << TPD_CNT_SHIFT) & TPD_CNT_MASK); 1641 1642 /* Set Rx page base address, note we use single queue. */ 1643 paddr = sc->ale_cdata.ale_rx_page[0].page_paddr; 1644 CSR_WRITE_4(sc, ALE_RXF0_PAGE0_ADDR_LO, ALE_ADDR_LO(paddr)); 1645 paddr = sc->ale_cdata.ale_rx_page[1].page_paddr; 1646 CSR_WRITE_4(sc, ALE_RXF0_PAGE1_ADDR_LO, ALE_ADDR_LO(paddr)); 1647 1648 /* Set Tx/Rx CMB addresses. */ 1649 paddr = sc->ale_cdata.ale_tx_cmb_paddr; 1650 CSR_WRITE_4(sc, ALE_TX_CMB_ADDR_LO, ALE_ADDR_LO(paddr)); 1651 paddr = sc->ale_cdata.ale_rx_page[0].cmb_paddr; 1652 CSR_WRITE_4(sc, ALE_RXF0_CMB0_ADDR_LO, ALE_ADDR_LO(paddr)); 1653 paddr = sc->ale_cdata.ale_rx_page[1].cmb_paddr; 1654 CSR_WRITE_4(sc, ALE_RXF0_CMB1_ADDR_LO, ALE_ADDR_LO(paddr)); 1655 1656 /* Mark RXF0 is valid. */ 1657 CSR_WRITE_1(sc, ALE_RXF0_PAGE0, RXF_VALID); 1658 CSR_WRITE_1(sc, ALE_RXF0_PAGE1, RXF_VALID); 1659 /* 1660 * No need to initialize RFX1/RXF2/RXF3. We don't use 1661 * multi-queue yet. 1662 */ 1663 1664 /* Set Rx page size, excluding guard frame size. */ 1665 CSR_WRITE_4(sc, ALE_RXF_PAGE_SIZE, ALE_RX_PAGE_SZ); 1666 1667 /* Tell hardware that we're ready to load DMA blocks. */ 1668 CSR_WRITE_4(sc, ALE_DMA_BLOCK, DMA_BLOCK_LOAD); 1669 1670 /* Set Rx/Tx interrupt trigger threshold. */ 1671 CSR_WRITE_4(sc, ALE_INT_TRIG_THRESH, (1 << INT_TRIG_RX_THRESH_SHIFT) | 1672 (4 << INT_TRIG_TX_THRESH_SHIFT)); 1673 /* 1674 * XXX 1675 * Set interrupt trigger timer, its purpose and relation 1676 * with interrupt moderation mechanism is not clear yet. 1677 */ 1678 CSR_WRITE_4(sc, ALE_INT_TRIG_TIMER, 1679 ((ALE_USECS(10) << INT_TRIG_RX_TIMER_SHIFT) | 1680 (ALE_USECS(1000) << INT_TRIG_TX_TIMER_SHIFT))); 1681 1682 /* Configure interrupt moderation timer. */ 1683 sc->ale_int_rx_mod = ALE_IM_RX_TIMER_DEFAULT; 1684 sc->ale_int_tx_mod = ALE_IM_TX_TIMER_DEFAULT; 1685 reg = ALE_USECS(sc->ale_int_rx_mod) << IM_TIMER_RX_SHIFT; 1686 reg |= ALE_USECS(sc->ale_int_tx_mod) << IM_TIMER_TX_SHIFT; 1687 CSR_WRITE_4(sc, ALE_IM_TIMER, reg); 1688 reg = CSR_READ_4(sc, ALE_MASTER_CFG); 1689 reg &= ~(MASTER_CHIP_REV_MASK | MASTER_CHIP_ID_MASK); 1690 reg &= ~(MASTER_IM_RX_TIMER_ENB | MASTER_IM_TX_TIMER_ENB); 1691 if (ALE_USECS(sc->ale_int_rx_mod) != 0) 1692 reg |= MASTER_IM_RX_TIMER_ENB; 1693 if (ALE_USECS(sc->ale_int_tx_mod) != 0) 1694 reg |= MASTER_IM_TX_TIMER_ENB; 1695 CSR_WRITE_4(sc, ALE_MASTER_CFG, reg); 1696 CSR_WRITE_2(sc, ALE_INTR_CLR_TIMER, ALE_USECS(1000)); 1697 1698 /* Set Maximum frame size of controller. */ 1699 if (ifp->if_mtu < ETHERMTU) 1700 sc->ale_max_frame_size = ETHERMTU; 1701 else 1702 sc->ale_max_frame_size = ifp->if_mtu; 1703 sc->ale_max_frame_size += ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN + ETHER_CRC_LEN; 1704 CSR_WRITE_4(sc, ALE_FRAME_SIZE, sc->ale_max_frame_size); 1705 1706 /* Configure IPG/IFG parameters. */ 1707 CSR_WRITE_4(sc, ALE_IPG_IFG_CFG, 1708 ((IPG_IFG_IPGT_DEFAULT << IPG_IFG_IPGT_SHIFT) & IPG_IFG_IPGT_MASK) | 1709 ((IPG_IFG_MIFG_DEFAULT << IPG_IFG_MIFG_SHIFT) & IPG_IFG_MIFG_MASK) | 1710 ((IPG_IFG_IPG1_DEFAULT << IPG_IFG_IPG1_SHIFT) & IPG_IFG_IPG1_MASK) | 1711 ((IPG_IFG_IPG2_DEFAULT << IPG_IFG_IPG2_SHIFT) & IPG_IFG_IPG2_MASK)); 1712 1713 /* Set parameters for half-duplex media. */ 1714 CSR_WRITE_4(sc, ALE_HDPX_CFG, 1715 ((HDPX_CFG_LCOL_DEFAULT << HDPX_CFG_LCOL_SHIFT) & 1716 HDPX_CFG_LCOL_MASK) | 1717 ((HDPX_CFG_RETRY_DEFAULT << HDPX_CFG_RETRY_SHIFT) & 1718 HDPX_CFG_RETRY_MASK) | HDPX_CFG_EXC_DEF_EN | 1719 ((HDPX_CFG_ABEBT_DEFAULT << HDPX_CFG_ABEBT_SHIFT) & 1720 HDPX_CFG_ABEBT_MASK) | 1721 ((HDPX_CFG_JAMIPG_DEFAULT << HDPX_CFG_JAMIPG_SHIFT) & 1722 HDPX_CFG_JAMIPG_MASK)); 1723 1724 /* Configure Tx jumbo frame parameters. */ 1725 if ((sc->ale_flags & ALE_FLAG_JUMBO) != 0) { 1726 if (ifp->if_mtu < ETHERMTU) 1727 reg = sc->ale_max_frame_size; 1728 else if (ifp->if_mtu < 6 * 1024) 1729 reg = (sc->ale_max_frame_size * 2) / 3; 1730 else 1731 reg = sc->ale_max_frame_size / 2; 1732 CSR_WRITE_4(sc, ALE_TX_JUMBO_THRESH, 1733 roundup(reg, TX_JUMBO_THRESH_UNIT) >> 1734 TX_JUMBO_THRESH_UNIT_SHIFT); 1735 } 1736 1737 /* Configure TxQ. */ 1738 reg = (128 << (sc->ale_dma_rd_burst >> DMA_CFG_RD_BURST_SHIFT)) 1739 << TXQ_CFG_TX_FIFO_BURST_SHIFT; 1740 reg |= (TXQ_CFG_TPD_BURST_DEFAULT << TXQ_CFG_TPD_BURST_SHIFT) & 1741 TXQ_CFG_TPD_BURST_MASK; 1742 CSR_WRITE_4(sc, ALE_TXQ_CFG, reg | TXQ_CFG_ENHANCED_MODE | TXQ_CFG_ENB); 1743 1744 /* Configure Rx jumbo frame & flow control parameters. */ 1745 if ((sc->ale_flags & ALE_FLAG_JUMBO) != 0) { 1746 reg = roundup(sc->ale_max_frame_size, RX_JUMBO_THRESH_UNIT); 1747 CSR_WRITE_4(sc, ALE_RX_JUMBO_THRESH, 1748 (((reg >> RX_JUMBO_THRESH_UNIT_SHIFT) << 1749 RX_JUMBO_THRESH_MASK_SHIFT) & RX_JUMBO_THRESH_MASK) | 1750 ((RX_JUMBO_LKAH_DEFAULT << RX_JUMBO_LKAH_SHIFT) & 1751 RX_JUMBO_LKAH_MASK)); 1752 reg = CSR_READ_4(sc, ALE_SRAM_RX_FIFO_LEN); 1753 rxf_hi = (reg * 7) / 10; 1754 rxf_lo = (reg * 3)/ 10; 1755 CSR_WRITE_4(sc, ALE_RX_FIFO_PAUSE_THRESH, 1756 ((rxf_lo << RX_FIFO_PAUSE_THRESH_LO_SHIFT) & 1757 RX_FIFO_PAUSE_THRESH_LO_MASK) | 1758 ((rxf_hi << RX_FIFO_PAUSE_THRESH_HI_SHIFT) & 1759 RX_FIFO_PAUSE_THRESH_HI_MASK)); 1760 } 1761 1762 /* Disable RSS. */ 1763 CSR_WRITE_4(sc, ALE_RSS_IDT_TABLE0, 0); 1764 CSR_WRITE_4(sc, ALE_RSS_CPU, 0); 1765 1766 /* Configure RxQ. */ 1767 CSR_WRITE_4(sc, ALE_RXQ_CFG, 1768 RXQ_CFG_ALIGN_32 | RXQ_CFG_CUT_THROUGH_ENB | RXQ_CFG_ENB); 1769 1770 /* Configure DMA parameters. */ 1771 reg = 0; 1772 if ((sc->ale_flags & ALE_FLAG_TXCMB_BUG) == 0) 1773 reg |= DMA_CFG_TXCMB_ENB; 1774 CSR_WRITE_4(sc, ALE_DMA_CFG, 1775 DMA_CFG_OUT_ORDER | DMA_CFG_RD_REQ_PRI | DMA_CFG_RCB_64 | 1776 sc->ale_dma_rd_burst | reg | 1777 sc->ale_dma_wr_burst | DMA_CFG_RXCMB_ENB | 1778 ((DMA_CFG_RD_DELAY_CNT_DEFAULT << DMA_CFG_RD_DELAY_CNT_SHIFT) & 1779 DMA_CFG_RD_DELAY_CNT_MASK) | 1780 ((DMA_CFG_WR_DELAY_CNT_DEFAULT << DMA_CFG_WR_DELAY_CNT_SHIFT) & 1781 DMA_CFG_WR_DELAY_CNT_MASK)); 1782 1783 /* 1784 * Hardware can be configured to issue SMB interrupt based 1785 * on programmed interval. Since there is a callout that is 1786 * invoked for every hz in driver we use that instead of 1787 * relying on periodic SMB interrupt. 1788 */ 1789 CSR_WRITE_4(sc, ALE_SMB_STAT_TIMER, ALE_USECS(0)); 1790 1791 /* Clear MAC statistics. */ 1792 ale_stats_clear(sc); 1793 1794 /* 1795 * Configure Tx/Rx MACs. 1796 * - Auto-padding for short frames. 1797 * - Enable CRC generation. 1798 * Actual reconfiguration of MAC for resolved speed/duplex 1799 * is followed after detection of link establishment. 1800 * AR81xx always does checksum computation regardless of 1801 * MAC_CFG_RXCSUM_ENB bit. In fact, setting the bit will 1802 * cause Rx handling issue for fragmented IP datagrams due 1803 * to silicon bug. 1804 */ 1805 reg = MAC_CFG_TX_CRC_ENB | MAC_CFG_TX_AUTO_PAD | MAC_CFG_FULL_DUPLEX | 1806 ((MAC_CFG_PREAMBLE_DEFAULT << MAC_CFG_PREAMBLE_SHIFT) & 1807 MAC_CFG_PREAMBLE_MASK); 1808 if ((sc->ale_flags & ALE_FLAG_FASTETHER) != 0) 1809 reg |= MAC_CFG_SPEED_10_100; 1810 else 1811 reg |= MAC_CFG_SPEED_1000; 1812 CSR_WRITE_4(sc, ALE_MAC_CFG, reg); 1813 1814 /* Set up the receive filter. */ 1815 ale_rxfilter(sc); 1816 ale_rxvlan(sc); 1817 1818 /* Acknowledge all pending interrupts and clear it. */ 1819 CSR_WRITE_4(sc, ALE_INTR_MASK, ALE_INTRS); 1820 CSR_WRITE_4(sc, ALE_INTR_STATUS, 0xFFFFFFFF); 1821 CSR_WRITE_4(sc, ALE_INTR_STATUS, 0); 1822 1823 sc->ale_flags &= ~ALE_FLAG_LINK; 1824 1825 /* Switch to the current media. */ 1826 mii = &sc->sc_miibus; 1827 mii_mediachg(mii); 1828 1829 callout_schedule(&sc->sc_tick_ch, hz); 1830 1831 ifp->if_flags |= IFF_RUNNING; 1832 ifp->if_flags &= ~IFF_OACTIVE; 1833 1834 return 0; 1835 } 1836 1837 static void 1838 ale_stop(struct ifnet *ifp, int disable) 1839 { 1840 struct ale_softc *sc = ifp->if_softc; 1841 struct ale_txdesc *txd; 1842 uint32_t reg; 1843 int i; 1844 1845 callout_stop(&sc->sc_tick_ch); 1846 1847 /* 1848 * Mark the interface down and cancel the watchdog timer. 1849 */ 1850 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1851 ifp->if_timer = 0; 1852 1853 sc->ale_flags &= ~ALE_FLAG_LINK; 1854 1855 ale_stats_update(sc); 1856 1857 mii_down(&sc->sc_miibus); 1858 1859 /* Disable interrupts. */ 1860 CSR_WRITE_4(sc, ALE_INTR_MASK, 0); 1861 CSR_WRITE_4(sc, ALE_INTR_STATUS, 0xFFFFFFFF); 1862 1863 /* Disable queue processing and DMA. */ 1864 reg = CSR_READ_4(sc, ALE_TXQ_CFG); 1865 reg &= ~TXQ_CFG_ENB; 1866 CSR_WRITE_4(sc, ALE_TXQ_CFG, reg); 1867 reg = CSR_READ_4(sc, ALE_RXQ_CFG); 1868 reg &= ~RXQ_CFG_ENB; 1869 CSR_WRITE_4(sc, ALE_RXQ_CFG, reg); 1870 reg = CSR_READ_4(sc, ALE_DMA_CFG); 1871 reg &= ~(DMA_CFG_TXCMB_ENB | DMA_CFG_RXCMB_ENB); 1872 CSR_WRITE_4(sc, ALE_DMA_CFG, reg); 1873 DELAY(1000); 1874 1875 /* Stop Rx/Tx MACs. */ 1876 ale_stop_mac(sc); 1877 1878 /* Disable interrupts again? XXX */ 1879 CSR_WRITE_4(sc, ALE_INTR_STATUS, 0xFFFFFFFF); 1880 1881 /* 1882 * Free TX mbufs still in the queues. 1883 */ 1884 for (i = 0; i < ALE_TX_RING_CNT; i++) { 1885 txd = &sc->ale_cdata.ale_txdesc[i]; 1886 if (txd->tx_m != NULL) { 1887 bus_dmamap_unload(sc->sc_dmat, txd->tx_dmamap); 1888 m_freem(txd->tx_m); 1889 txd->tx_m = NULL; 1890 } 1891 } 1892 } 1893 1894 static void 1895 ale_stop_mac(struct ale_softc *sc) 1896 { 1897 uint32_t reg; 1898 int i; 1899 1900 reg = CSR_READ_4(sc, ALE_MAC_CFG); 1901 if ((reg & (MAC_CFG_TX_ENB | MAC_CFG_RX_ENB)) != 0) { 1902 reg &= ~(MAC_CFG_TX_ENB | MAC_CFG_RX_ENB); 1903 CSR_WRITE_4(sc, ALE_MAC_CFG, reg); 1904 } 1905 1906 for (i = ALE_TIMEOUT; i > 0; i--) { 1907 reg = CSR_READ_4(sc, ALE_IDLE_STATUS); 1908 if (reg == 0) 1909 break; 1910 DELAY(10); 1911 } 1912 if (i == 0) 1913 printf("%s: could not disable Tx/Rx MAC(0x%08x)!\n", 1914 device_xname(sc->sc_dev), reg); 1915 } 1916 1917 static void 1918 ale_init_tx_ring(struct ale_softc *sc) 1919 { 1920 struct ale_txdesc *txd; 1921 int i; 1922 1923 sc->ale_cdata.ale_tx_prod = 0; 1924 sc->ale_cdata.ale_tx_cons = 0; 1925 sc->ale_cdata.ale_tx_cnt = 0; 1926 1927 memset(sc->ale_cdata.ale_tx_ring, 0, ALE_TX_RING_SZ); 1928 memset(sc->ale_cdata.ale_tx_cmb, 0, ALE_TX_CMB_SZ); 1929 for (i = 0; i < ALE_TX_RING_CNT; i++) { 1930 txd = &sc->ale_cdata.ale_txdesc[i]; 1931 txd->tx_m = NULL; 1932 } 1933 *sc->ale_cdata.ale_tx_cmb = 0; 1934 bus_dmamap_sync(sc->sc_dmat, sc->ale_cdata.ale_tx_cmb_map, 0, 1935 sc->ale_cdata.ale_tx_cmb_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 1936 bus_dmamap_sync(sc->sc_dmat, sc->ale_cdata.ale_tx_ring_map, 0, 1937 sc->ale_cdata.ale_tx_ring_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 1938 } 1939 1940 static void 1941 ale_init_rx_pages(struct ale_softc *sc) 1942 { 1943 struct ale_rx_page *rx_page; 1944 int i; 1945 1946 sc->ale_cdata.ale_rx_seqno = 0; 1947 sc->ale_cdata.ale_rx_curp = 0; 1948 1949 for (i = 0; i < ALE_RX_PAGES; i++) { 1950 rx_page = &sc->ale_cdata.ale_rx_page[i]; 1951 memset(rx_page->page_addr, 0, sc->ale_pagesize); 1952 memset(rx_page->cmb_addr, 0, ALE_RX_CMB_SZ); 1953 rx_page->cons = 0; 1954 *rx_page->cmb_addr = 0; 1955 bus_dmamap_sync(sc->sc_dmat, rx_page->page_map, 0, 1956 rx_page->page_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 1957 bus_dmamap_sync(sc->sc_dmat, rx_page->cmb_map, 0, 1958 rx_page->cmb_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 1959 } 1960 } 1961 1962 static void 1963 ale_rxvlan(struct ale_softc *sc) 1964 { 1965 uint32_t reg; 1966 1967 reg = CSR_READ_4(sc, ALE_MAC_CFG); 1968 reg &= ~MAC_CFG_VLAN_TAG_STRIP; 1969 if (sc->sc_ec.ec_capenable & ETHERCAP_VLAN_HWTAGGING) 1970 reg |= MAC_CFG_VLAN_TAG_STRIP; 1971 CSR_WRITE_4(sc, ALE_MAC_CFG, reg); 1972 } 1973 1974 static void 1975 ale_rxfilter(struct ale_softc *sc) 1976 { 1977 struct ethercom *ec = &sc->sc_ec; 1978 struct ifnet *ifp = &ec->ec_if; 1979 struct ether_multi *enm; 1980 struct ether_multistep step; 1981 uint32_t crc; 1982 uint32_t mchash[2]; 1983 uint32_t rxcfg; 1984 1985 rxcfg = CSR_READ_4(sc, ALE_MAC_CFG); 1986 rxcfg &= ~(MAC_CFG_ALLMULTI | MAC_CFG_BCAST | MAC_CFG_PROMISC); 1987 ifp->if_flags &= ~IFF_ALLMULTI; 1988 1989 /* 1990 * Always accept broadcast frames. 1991 */ 1992 rxcfg |= MAC_CFG_BCAST; 1993 1994 /* Program new filter. */ 1995 if ((ifp->if_flags & IFF_PROMISC) != 0) 1996 goto update; 1997 1998 memset(mchash, 0, sizeof(mchash)); 1999 2000 ETHER_LOCK(ec); 2001 ETHER_FIRST_MULTI(step, ec, enm); 2002 while (enm != NULL) { 2003 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 2004 /* XXX Use ETHER_F_ALLMULTI in future. */ 2005 ifp->if_flags |= IFF_ALLMULTI; 2006 ETHER_UNLOCK(ec); 2007 goto update; 2008 } 2009 crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 2010 mchash[crc >> 31] |= 1U << ((crc >> 26) & 0x1f); 2011 ETHER_NEXT_MULTI(step, enm); 2012 } 2013 ETHER_UNLOCK(ec); 2014 2015 update: 2016 if ((ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) != 0) { 2017 if (ifp->if_flags & IFF_PROMISC) { 2018 rxcfg |= MAC_CFG_PROMISC; 2019 /* XXX Use ETHER_F_ALLMULTI in future. */ 2020 ifp->if_flags |= IFF_ALLMULTI; 2021 } else 2022 rxcfg |= MAC_CFG_ALLMULTI; 2023 mchash[0] = mchash[1] = 0xFFFFFFFF; 2024 } 2025 CSR_WRITE_4(sc, ALE_MAR0, mchash[0]); 2026 CSR_WRITE_4(sc, ALE_MAR1, mchash[1]); 2027 CSR_WRITE_4(sc, ALE_MAC_CFG, rxcfg); 2028 } 2029
Indexes created Tue Sep 30 11:09:46 GMT 2025