if_an_pci.c revision 1.35
11.35Schristos/* $NetBSD: if_an_pci.c,v 1.35 2014/03/29 19:28:24 christos Exp $ */ 21.1Sonoe 31.1Sonoe/* 41.1Sonoe * Copyright (c) 2000 The NetBSD Foundation, Inc. 51.1Sonoe * All rights reserved. 61.1Sonoe * 71.1Sonoe * This code is derived from software contributed to The NetBSD Foundation 81.1Sonoe * by Atsushi Onoe. 91.1Sonoe * 101.1Sonoe * Redistribution and use in source and binary forms, with or without 111.1Sonoe * modification, are permitted provided that the following conditions 121.1Sonoe * are met: 131.1Sonoe * 1. Redistributions of source code must retain the above copyright 141.1Sonoe * notice, this list of conditions and the following disclaimer. 151.1Sonoe * 2. Redistributions in binary form must reproduce the above copyright 161.1Sonoe * notice, this list of conditions and the following disclaimer in the 171.1Sonoe * documentation and/or other materials provided with the distribution. 181.1Sonoe * 191.1Sonoe * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 201.1Sonoe * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 211.1Sonoe * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 221.1Sonoe * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 231.1Sonoe * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 241.1Sonoe * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 251.1Sonoe * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 261.1Sonoe * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 271.1Sonoe * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 281.1Sonoe * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 291.1Sonoe * POSSIBILITY OF SUCH DAMAGE. 301.1Sonoe */ 311.1Sonoe 321.1Sonoe/* 331.1Sonoe * PCI bus front-end for the Aironet PC4500/PC4800 Wireless LAN Adapter. 341.1Sonoe * Unlike WaveLAN, this adapter attached as PCI device using a PLX 9050 351.1Sonoe * PCI to "dumb bus" bridge chip. 361.1Sonoe */ 371.6Slukem 381.6Slukem#include <sys/cdefs.h> 391.35Schristos__KERNEL_RCSID(0, "$NetBSD: if_an_pci.c,v 1.35 2014/03/29 19:28:24 christos Exp $"); 401.1Sonoe 411.1Sonoe#include <sys/param.h> 421.17Sperry#include <sys/systm.h> 431.17Sperry#include <sys/mbuf.h> 441.1Sonoe#include <sys/malloc.h> 451.1Sonoe#include <sys/kernel.h> 461.1Sonoe#include <sys/socket.h> 471.1Sonoe#include <sys/ioctl.h> 481.1Sonoe#include <sys/errno.h> 491.1Sonoe#include <sys/device.h> 501.1Sonoe#include <sys/callout.h> 511.1Sonoe 521.1Sonoe#include <machine/endian.h> 531.17Sperry 541.1Sonoe#include <net/if.h> 551.1Sonoe#include <net/if_dl.h> 561.1Sonoe#include <net/if_media.h> 571.1Sonoe#include <net/if_ether.h> 581.11Sdyoung 591.18Sdyoung#include <net80211/ieee80211_netbsd.h> 601.11Sdyoung#include <net80211/ieee80211_var.h> 611.1Sonoe 621.23Sad#include <sys/bus.h> 631.23Sad#include <sys/intr.h> 641.1Sonoe 651.1Sonoe#include <dev/ic/anreg.h> 661.1Sonoe#include <dev/ic/anvar.h> 671.1Sonoe 681.1Sonoe#include <dev/pci/pcivar.h> 691.1Sonoe#include <dev/pci/pcireg.h> 701.1Sonoe#include <dev/pci/pcidevs.h> 711.1Sonoe 721.1Sonoe#define AN_PCI_PLX_IOBA 0x14 /* i/o base for PLX chip */ 731.32Sdyoung#define AN_PCI_IOBA PCI_BAR(2) /* i/o base */ 741.1Sonoe 751.1Sonoestruct an_pci_softc { 761.1Sonoe struct an_softc sc_an; /* real "an" softc */ 771.24Sjmcneill pci_chipset_tag_t sc_pct; 781.24Sjmcneill pcitag_t sc_pcitag; 791.1Sonoe 801.1Sonoe /* PCI-specific goo. */ 811.1Sonoe void *sc_ih; /* interrupt handle */ 821.1Sonoe}; 831.1Sonoe 841.29Sceggerstatic int an_pci_match(device_t, cfdata_t, void *); 851.29Sceggerstatic void an_pci_attach(device_t, device_t, void *); 861.1Sonoe 871.27SdrochnerCFATTACH_DECL_NEW(an_pci, sizeof(struct an_pci_softc), 881.9Sthorpej an_pci_match, an_pci_attach, NULL, NULL); 891.1Sonoe 901.16Sthorpejstatic const struct an_pci_product { 911.1Sonoe u_int32_t app_vendor; /* PCI vendor ID */ 921.1Sonoe u_int32_t app_product; /* PCI product ID */ 931.1Sonoe} an_pci_products[] = { 941.1Sonoe { PCI_VENDOR_AIRONET, PCI_PRODUCT_AIRONET_PC4xxx }, 951.1Sonoe { PCI_VENDOR_AIRONET, PCI_PRODUCT_AIRONET_PC4500 }, 961.1Sonoe { PCI_VENDOR_AIRONET, PCI_PRODUCT_AIRONET_PC4800 }, 971.15Smycroft { PCI_VENDOR_AIRONET, PCI_PRODUCT_AIRONET_PCI350 }, 981.34Schs { PCI_VENDOR_AIRONET, PCI_PRODUCT_AIRONET_MPI350 }, 991.1Sonoe { 0, 0 } 1001.1Sonoe}; 1011.1Sonoe 1021.16Sthorpejstatic int 1031.29Sceggeran_pci_match(device_t parent, cfdata_t match, void *aux) 1041.1Sonoe{ 1051.1Sonoe struct pci_attach_args *pa = aux; 1061.1Sonoe const struct an_pci_product *app; 1071.1Sonoe 1081.1Sonoe for (app = an_pci_products; app->app_vendor != 0; app++) { 1091.1Sonoe if (PCI_VENDOR(pa->pa_id) == app->app_vendor && 1101.1Sonoe PCI_PRODUCT(pa->pa_id) == app->app_product) 1111.1Sonoe return 1; 1121.1Sonoe } 1131.1Sonoe return 0; 1141.1Sonoe} 1151.1Sonoe 1161.16Sthorpejstatic void 1171.29Sceggeran_pci_attach(device_t parent, device_t self, void *aux) 1181.1Sonoe{ 1191.1Sonoe struct pci_attach_args *pa = (struct pci_attach_args *)aux; 1201.27Sdrochner struct an_pci_softc *psc = device_private(self); 1211.1Sonoe struct an_softc *sc = &psc->sc_an; 1221.1Sonoe char const *intrstr; 1231.1Sonoe pci_intr_handle_t ih; 1241.22Srumble bus_size_t iosize; 1251.1Sonoe u_int32_t csr; 1261.35Schristos char intrbuf[PCI_INTRSTR_LEN]; 1271.1Sonoe 1281.27Sdrochner sc->sc_dev = self; 1291.24Sjmcneill psc->sc_pct = pa->pa_pc; 1301.24Sjmcneill psc->sc_pcitag = pa->pa_tag; 1311.24Sjmcneill 1321.33Sdrochner pci_aprint_devinfo(pa, "802.11 controller"); 1331.1Sonoe 1341.1Sonoe /* Map I/O registers */ 1351.1Sonoe if (pci_mapreg_map(pa, AN_PCI_IOBA, PCI_MAPREG_TYPE_IO, 0, 1361.22Srumble &sc->sc_iot, &sc->sc_ioh, NULL, &iosize) != 0) { 1371.25Scegger aprint_error_dev(self, "unable to map registers\n"); 1381.1Sonoe return; 1391.1Sonoe } 1401.1Sonoe 1411.1Sonoe /* Enable the device. */ 1421.1Sonoe csr = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 1431.1Sonoe pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 1441.1Sonoe csr | PCI_COMMAND_MASTER_ENABLE); 1451.1Sonoe 1461.1Sonoe /* Map and establish the interrupt. */ 1471.2Ssommerfe if (pci_intr_map(pa, &ih)) { 1481.25Scegger aprint_error_dev(self, "unable to map interrupt\n"); 1491.1Sonoe return; 1501.1Sonoe } 1511.35Schristos intrstr = pci_intr_string(pa->pa_pc, ih, intrbuf, sizeof(intrbuf)); 1521.1Sonoe psc->sc_ih = pci_intr_establish(pa->pa_pc, ih, IPL_NET, an_intr, sc); 1531.1Sonoe if (psc->sc_ih == NULL) { 1541.25Scegger aprint_error_dev(self, "unable to establish interrupt"); 1551.1Sonoe if (intrstr != NULL) 1561.31Snjoly aprint_error(" at %s", intrstr); 1571.31Snjoly aprint_error("\n"); 1581.1Sonoe return; 1591.1Sonoe } 1601.25Scegger aprint_normal_dev(self, "interrupting at %s\n", intrstr); 1611.1Sonoe sc->sc_enabled = 1; 1621.1Sonoe 1631.1Sonoe if (an_attach(sc) != 0) { 1641.25Scegger aprint_error_dev(self, "failed to attach controller\n"); 1651.1Sonoe pci_intr_disestablish(pa->pa_pc, psc->sc_ih); 1661.22Srumble bus_space_unmap(sc->sc_iot, sc->sc_ioh, iosize); 1671.1Sonoe } 1681.24Sjmcneill 1691.30Stsutsui if (pmf_device_register(self, NULL, NULL)) 1701.30Stsutsui pmf_class_network_register(self, &sc->sc_if); 1711.30Stsutsui else 1721.24Sjmcneill aprint_error_dev(self, "couldn't establish power handler\n"); 1731.1Sonoe} 174