if_an_pci.c revision 1.38
11.38Sthorpej/*	$NetBSD: if_an_pci.c,v 1.38 2022/09/25 17:52:25 thorpej Exp $	*/
21.1Sonoe
31.1Sonoe/*
41.1Sonoe * Copyright (c) 2000 The NetBSD Foundation, Inc.
51.1Sonoe * All rights reserved.
61.1Sonoe *
71.1Sonoe * This code is derived from software contributed to The NetBSD Foundation
81.1Sonoe * by Atsushi Onoe.
91.1Sonoe *
101.1Sonoe * Redistribution and use in source and binary forms, with or without
111.1Sonoe * modification, are permitted provided that the following conditions
121.1Sonoe * are met:
131.1Sonoe * 1. Redistributions of source code must retain the above copyright
141.1Sonoe *    notice, this list of conditions and the following disclaimer.
151.1Sonoe * 2. Redistributions in binary form must reproduce the above copyright
161.1Sonoe *    notice, this list of conditions and the following disclaimer in the
171.1Sonoe *    documentation and/or other materials provided with the distribution.
181.1Sonoe *
191.1Sonoe * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
201.1Sonoe * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
211.1Sonoe * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
221.1Sonoe * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
231.1Sonoe * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
241.1Sonoe * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
251.1Sonoe * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
261.1Sonoe * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
271.1Sonoe * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
281.1Sonoe * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
291.1Sonoe * POSSIBILITY OF SUCH DAMAGE.
301.1Sonoe */
311.1Sonoe
321.1Sonoe/*
331.1Sonoe * PCI bus front-end for the Aironet PC4500/PC4800 Wireless LAN Adapter.
341.1Sonoe * Unlike WaveLAN, this adapter attached as PCI device using a PLX 9050
351.1Sonoe * PCI to "dumb bus" bridge chip.
361.1Sonoe */
371.6Slukem
381.6Slukem#include <sys/cdefs.h>
391.38Sthorpej__KERNEL_RCSID(0, "$NetBSD: if_an_pci.c,v 1.38 2022/09/25 17:52:25 thorpej Exp $");
401.1Sonoe
411.1Sonoe#include <sys/param.h>
421.17Sperry#include <sys/systm.h>
431.17Sperry#include <sys/mbuf.h>
441.1Sonoe#include <sys/kernel.h>
451.1Sonoe#include <sys/socket.h>
461.1Sonoe#include <sys/ioctl.h>
471.1Sonoe#include <sys/errno.h>
481.1Sonoe#include <sys/device.h>
491.1Sonoe#include <sys/callout.h>
501.1Sonoe
511.1Sonoe#include <machine/endian.h>
521.17Sperry
531.1Sonoe#include <net/if.h>
541.1Sonoe#include <net/if_dl.h>
551.1Sonoe#include <net/if_media.h>
561.1Sonoe#include <net/if_ether.h>
571.11Sdyoung
581.18Sdyoung#include <net80211/ieee80211_netbsd.h>
591.11Sdyoung#include <net80211/ieee80211_var.h>
601.1Sonoe
611.23Sad#include <sys/bus.h>
621.23Sad#include <sys/intr.h>
631.1Sonoe
641.1Sonoe#include <dev/ic/anreg.h>
651.1Sonoe#include <dev/ic/anvar.h>
661.1Sonoe
671.1Sonoe#include <dev/pci/pcivar.h>
681.1Sonoe#include <dev/pci/pcireg.h>
691.1Sonoe#include <dev/pci/pcidevs.h>
701.1Sonoe
711.1Sonoe#define	AN_PCI_PLX_IOBA		0x14	/* i/o base for PLX chip */
721.32Sdyoung#define AN_PCI_IOBA PCI_BAR(2)	/* i/o base */
731.1Sonoe
741.1Sonoestruct an_pci_softc {
751.1Sonoe	struct an_softc sc_an;		/* real "an" softc */
761.24Sjmcneill	pci_chipset_tag_t sc_pct;
771.24Sjmcneill	pcitag_t sc_pcitag;
781.1Sonoe
791.1Sonoe	/* PCI-specific goo. */
801.1Sonoe	void	*sc_ih;			/* interrupt handle */
811.1Sonoe};
821.1Sonoe
831.29Sceggerstatic int	an_pci_match(device_t, cfdata_t, void *);
841.29Sceggerstatic void	an_pci_attach(device_t, device_t, void *);
851.1Sonoe
861.27SdrochnerCFATTACH_DECL_NEW(an_pci, sizeof(struct an_pci_softc),
871.9Sthorpej    an_pci_match, an_pci_attach, NULL, NULL);
881.1Sonoe
891.16Sthorpejstatic const struct an_pci_product {
901.1Sonoe	u_int32_t	app_vendor;	/* PCI vendor ID */
911.1Sonoe	u_int32_t	app_product;	/* PCI product ID */
921.1Sonoe} an_pci_products[] = {
931.1Sonoe	{ PCI_VENDOR_AIRONET,		PCI_PRODUCT_AIRONET_PC4xxx },
941.1Sonoe	{ PCI_VENDOR_AIRONET,		PCI_PRODUCT_AIRONET_PC4500 },
951.1Sonoe	{ PCI_VENDOR_AIRONET,		PCI_PRODUCT_AIRONET_PC4800 },
961.15Smycroft	{ PCI_VENDOR_AIRONET,		PCI_PRODUCT_AIRONET_PCI350 },
971.34Schs	{ PCI_VENDOR_AIRONET,		PCI_PRODUCT_AIRONET_MPI350 },
981.1Sonoe	{ 0,				0			   }
991.1Sonoe};
1001.1Sonoe
1011.16Sthorpejstatic int
1021.29Sceggeran_pci_match(device_t parent, cfdata_t match, void *aux)
1031.1Sonoe{
1041.1Sonoe	struct pci_attach_args *pa = aux;
1051.1Sonoe	const struct an_pci_product *app;
1061.1Sonoe
1071.1Sonoe	for (app = an_pci_products; app->app_vendor != 0; app++) {
1081.1Sonoe		if (PCI_VENDOR(pa->pa_id) == app->app_vendor &&
1091.1Sonoe		    PCI_PRODUCT(pa->pa_id) == app->app_product)
1101.1Sonoe			return 1;
1111.1Sonoe	}
1121.1Sonoe	return 0;
1131.1Sonoe}
1141.1Sonoe
1151.16Sthorpejstatic void
1161.29Sceggeran_pci_attach(device_t parent, device_t self, void *aux)
1171.1Sonoe{
1181.37Smsaitoh	struct pci_attach_args *pa = (struct pci_attach_args *)aux;
1191.27Sdrochner	struct an_pci_softc *psc = device_private(self);
1201.1Sonoe	struct an_softc *sc = &psc->sc_an;
1211.1Sonoe	char const *intrstr;
1221.1Sonoe	pci_intr_handle_t ih;
1231.22Srumble	bus_size_t iosize;
1241.1Sonoe	u_int32_t csr;
1251.35Schristos	char intrbuf[PCI_INTRSTR_LEN];
1261.1Sonoe
1271.27Sdrochner	sc->sc_dev = self;
1281.24Sjmcneill	psc->sc_pct = pa->pa_pc;
1291.24Sjmcneill	psc->sc_pcitag = pa->pa_tag;
1301.24Sjmcneill
1311.33Sdrochner	pci_aprint_devinfo(pa, "802.11 controller");
1321.1Sonoe
1331.37Smsaitoh	/* Map I/O registers */
1341.37Smsaitoh	if (pci_mapreg_map(pa, AN_PCI_IOBA, PCI_MAPREG_TYPE_IO, 0,
1351.22Srumble	    &sc->sc_iot, &sc->sc_ioh, NULL, &iosize) != 0) {
1361.37Smsaitoh		aprint_error_dev(self, "unable to map registers\n");
1371.37Smsaitoh		return;
1381.37Smsaitoh	}
1391.37Smsaitoh
1401.37Smsaitoh	/* Enable the device. */
1411.37Smsaitoh	csr = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG);
1421.37Smsaitoh	pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG,
1431.37Smsaitoh	    csr | PCI_COMMAND_MASTER_ENABLE);
1441.1Sonoe
1451.1Sonoe	/* Map and establish the interrupt. */
1461.2Ssommerfe	if (pci_intr_map(pa, &ih)) {
1471.37Smsaitoh		aprint_error_dev(self, "unable to map interrupt\n");
1481.1Sonoe		return;
1491.1Sonoe	}
1501.35Schristos	intrstr = pci_intr_string(pa->pa_pc, ih, intrbuf, sizeof(intrbuf));
1511.36Sjdolecek	psc->sc_ih = pci_intr_establish_xname(pa->pa_pc, ih, IPL_NET, an_intr,
1521.36Sjdolecek	    sc, device_xname(self));
1531.1Sonoe	if (psc->sc_ih == NULL) {
1541.25Scegger		aprint_error_dev(self, "unable to establish interrupt");
1551.1Sonoe		if (intrstr != NULL)
1561.31Snjoly			aprint_error(" at %s", intrstr);
1571.31Snjoly		aprint_error("\n");
1581.1Sonoe		return;
1591.1Sonoe	}
1601.25Scegger	aprint_normal_dev(self, "interrupting at %s\n", intrstr);
1611.1Sonoe	sc->sc_enabled = 1;
1621.1Sonoe
1631.1Sonoe	if (an_attach(sc) != 0) {
1641.25Scegger		aprint_error_dev(self, "failed to attach controller\n");
1651.1Sonoe		pci_intr_disestablish(pa->pa_pc, psc->sc_ih);
1661.22Srumble		bus_space_unmap(sc->sc_iot, sc->sc_ioh, iosize);
1671.1Sonoe	}
1681.24Sjmcneill
1691.30Stsutsui	if (pmf_device_register(self, NULL, NULL))
1701.30Stsutsui		pmf_class_network_register(self, &sc->sc_if);
1711.30Stsutsui	else
1721.24Sjmcneill		aprint_error_dev(self, "couldn't establish power handler\n");
1731.1Sonoe}
174