if_athn_pci.c revision 1.12.18.2
1 /* $NetBSD: if_athn_pci.c,v 1.12.18.2 2019/06/10 22:07:16 christos Exp $ */ 2 /* $OpenBSD: if_athn_pci.c,v 1.11 2011/01/08 10:02:32 damien Exp $ */ 3 4 /*- 5 * Copyright (c) 2009 Damien Bergamini <damien.bergamini (at) free.fr> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 /* 21 * PCI front-end for Atheros 802.11a/g/n chipsets. 22 */ 23 24 #include <sys/cdefs.h> 25 __KERNEL_RCSID(0, "$NetBSD: if_athn_pci.c,v 1.12.18.2 2019/06/10 22:07:16 christos Exp $"); 26 27 #include "opt_inet.h" 28 29 #include <sys/param.h> 30 #include <sys/sockio.h> 31 #include <sys/mbuf.h> 32 #include <sys/kernel.h> 33 #include <sys/socket.h> 34 #include <sys/systm.h> 35 #include <sys/malloc.h> 36 #include <sys/callout.h> 37 #include <sys/device.h> 38 39 #include <sys/bus.h> 40 #include <sys/intr.h> 41 42 #include <net/if.h> 43 #include <net/if_ether.h> 44 #include <net/if_media.h> 45 #include <net/route.h> 46 47 #include <net80211/ieee80211_var.h> 48 #include <net80211/ieee80211_amrr.h> 49 #include <net80211/ieee80211_radiotap.h> 50 51 #include <dev/ic/athnreg.h> 52 #include <dev/ic/athnvar.h> 53 54 #include <dev/pci/pcireg.h> 55 #include <dev/pci/pcivar.h> 56 #include <dev/pci/pcidevs.h> 57 58 #define PCI_SUBSYSID_ATHEROS_COEX2WIRE 0x309b 59 #define PCI_SUBSYSID_ATHEROS_COEX3WIRE_SA 0x30aa 60 #define PCI_SUBSYSID_ATHEROS_COEX3WIRE_DA 0x30ab 61 62 #define ATHN_PCI_MMBA PCI_BAR(0) /* memory mapped base */ 63 64 struct athn_pci_softc { 65 struct athn_softc psc_sc; 66 67 /* PCI specific goo. */ 68 pci_chipset_tag_t psc_pc; 69 pcitag_t psc_tag; 70 pci_intr_handle_t psc_pih; 71 void *psc_ih; 72 bus_space_tag_t psc_iot; 73 bus_space_handle_t psc_ioh; 74 bus_size_t psc_mapsz; 75 int psc_cap_off; 76 }; 77 78 #define Static static 79 80 Static int athn_pci_match(device_t, cfdata_t, void *); 81 Static void athn_pci_attach(device_t, device_t, void *); 82 Static int athn_pci_detach(device_t, int); 83 Static int athn_pci_activate(device_t, enum devact); 84 85 CFATTACH_DECL_NEW(athn_pci, sizeof(struct athn_pci_softc), athn_pci_match, 86 athn_pci_attach, athn_pci_detach, athn_pci_activate); 87 88 Static bool athn_pci_resume(device_t, const pmf_qual_t *); 89 Static bool athn_pci_suspend(device_t, const pmf_qual_t *); 90 Static uint32_t athn_pci_read(struct athn_softc *, uint32_t); 91 Static void athn_pci_write(struct athn_softc *, uint32_t, uint32_t); 92 Static void athn_pci_write_barrier(struct athn_softc *); 93 Static void athn_pci_disable_aspm(struct athn_softc *); 94 95 Static int 96 athn_pci_match(device_t parent, cfdata_t match, void *aux) 97 { 98 static const struct { 99 pci_vendor_id_t apd_vendor; 100 pci_product_id_t apd_product; 101 } athn_pci_devices[] = { 102 { PCI_VENDOR_ATHEROS, PCI_PRODUCT_ATHEROS_AR5416 }, 103 { PCI_VENDOR_ATHEROS, PCI_PRODUCT_ATHEROS_AR5418 }, 104 { PCI_VENDOR_ATHEROS, PCI_PRODUCT_ATHEROS_AR9160 }, 105 { PCI_VENDOR_ATHEROS, PCI_PRODUCT_ATHEROS_AR9280 }, 106 { PCI_VENDOR_ATHEROS, PCI_PRODUCT_ATHEROS_AR9281 }, 107 { PCI_VENDOR_ATHEROS, PCI_PRODUCT_ATHEROS_AR9285 }, 108 { PCI_VENDOR_ATHEROS, PCI_PRODUCT_ATHEROS_AR2427 }, 109 { PCI_VENDOR_ATHEROS, PCI_PRODUCT_ATHEROS_AR9227 }, 110 { PCI_VENDOR_ATHEROS, PCI_PRODUCT_ATHEROS_AR9287 }, 111 { PCI_VENDOR_ATHEROS, PCI_PRODUCT_ATHEROS_AR9300 } 112 }; 113 struct pci_attach_args *pa = aux; 114 size_t i; 115 116 for (i = 0; i < __arraycount(athn_pci_devices); i++) { 117 if (PCI_VENDOR(pa->pa_id) == athn_pci_devices[i].apd_vendor && 118 PCI_PRODUCT(pa->pa_id) == athn_pci_devices[i].apd_product) 119 /* 120 * Match better than 1, we prefer this driver 121 * over ath(4) 122 */ 123 return 10; 124 } 125 return 0; 126 } 127 128 Static void 129 athn_pci_attach(device_t parent, device_t self, void *aux) 130 { 131 struct athn_pci_softc *psc = device_private(self); 132 struct athn_softc *sc = &psc->psc_sc; 133 struct ieee80211com *ic = &sc->sc_ic; 134 struct pci_attach_args *pa = aux; 135 const char *intrstr; 136 pcireg_t memtype, reg; 137 pci_product_id_t subsysid; 138 int error; 139 char intrbuf[PCI_INTRSTR_LEN]; 140 141 sc->sc_dev = self; 142 sc->sc_dmat = pa->pa_dmat; 143 psc->psc_pc = pa->pa_pc; 144 psc->psc_tag = pa->pa_tag; 145 146 sc->sc_ops.read = athn_pci_read; 147 sc->sc_ops.write = athn_pci_write; 148 sc->sc_ops.write_barrier = athn_pci_write_barrier; 149 150 /* 151 * Get the offset of the PCI Express Capability Structure in PCI 152 * Configuration Space (Linux hardcodes it as 0x60.) 153 */ 154 error = pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_PCIEXPRESS, 155 &psc->psc_cap_off, NULL); 156 if (error != 0) { /* Found. */ 157 sc->sc_disable_aspm = athn_pci_disable_aspm; 158 sc->sc_flags |= ATHN_FLAG_PCIE; 159 } 160 /* 161 * Noone knows why this shit is necessary but there are claims that 162 * not doing this may cause very frequent PCI FATAL interrupts from 163 * the card: http://bugzilla.kernel.org/show_bug.cgi?id=13483 164 */ 165 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, 0x40); 166 if (reg & 0xff00) 167 pci_conf_write(pa->pa_pc, pa->pa_tag, 0x40, reg & ~0xff00); 168 169 /* Change latency timer; default value yields poor results. */ 170 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG); 171 reg &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT); 172 reg |= 168 << PCI_LATTIMER_SHIFT; 173 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG, reg); 174 175 /* Determine if bluetooth is also supported (combo chip.) */ 176 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 177 subsysid = PCI_PRODUCT(reg); 178 if (subsysid == PCI_SUBSYSID_ATHEROS_COEX3WIRE_SA || 179 subsysid == PCI_SUBSYSID_ATHEROS_COEX3WIRE_DA) 180 sc->sc_flags |= ATHN_FLAG_BTCOEX3WIRE; 181 else if (subsysid == PCI_SUBSYSID_ATHEROS_COEX2WIRE) 182 sc->sc_flags |= ATHN_FLAG_BTCOEX2WIRE; 183 184 /* 185 * Setup memory-mapping of PCI registers. 186 */ 187 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, ATHN_PCI_MMBA); 188 if (memtype != PCI_MAPREG_TYPE_MEM && 189 memtype != PCI_MAPREG_MEM_TYPE_64BIT) { 190 aprint_error_dev(self, "bad pci register type %d\n", 191 (int)memtype); 192 goto fail; 193 } 194 error = pci_mapreg_map(pa, ATHN_PCI_MMBA, memtype, 0, &psc->psc_iot, 195 &psc->psc_ioh, NULL, &psc->psc_mapsz); 196 if (error != 0) { 197 aprint_error_dev(self, "cannot map register space\n"); 198 goto fail; 199 } 200 201 /* 202 * Arrange interrupt line. 203 */ 204 if (pci_intr_map(pa, &psc->psc_pih) != 0) { 205 aprint_error_dev(self, "couldn't map interrupt\n"); 206 goto fail1; 207 } 208 209 intrstr = pci_intr_string(psc->psc_pc, psc->psc_pih, intrbuf, sizeof(intrbuf)); 210 psc->psc_ih = pci_intr_establish_xname(psc->psc_pc, psc->psc_pih, 211 IPL_NET, athn_intr, sc, device_xname(self)); 212 if (psc->psc_ih == NULL) { 213 aprint_error_dev(self, "couldn't map interrupt\n"); 214 goto fail1; 215 } 216 217 #if notyet 218 /* NNN -- Does ic_vaps have anything yet???? */ 219 TAILQ_FIRST(&(sc->sc_ic.ic_vaps))->iv_ifp = &sc->sc_if; 220 #endif 221 222 if (athn_attach(sc) != 0) 223 goto fail2; 224 225 aprint_verbose_dev(self, "interrupting at %s\n", intrstr); 226 227 if (pmf_device_register(self, athn_pci_suspend, athn_pci_resume)) { 228 pmf_class_network_register(self, &sc->sc_if); 229 pmf_device_suspend(self, &sc->sc_qual); 230 } 231 else 232 aprint_error_dev(self, "couldn't establish power handler\n"); 233 234 ieee80211_announce(ic); 235 return; 236 237 fail2: 238 pci_intr_disestablish(psc->psc_pc, psc->psc_ih); 239 psc->psc_ih = NULL; 240 fail1: 241 bus_space_unmap(psc->psc_iot, psc->psc_ioh, psc->psc_mapsz); 242 psc->psc_mapsz = 0; 243 fail: 244 return; 245 } 246 247 Static int 248 athn_pci_detach(device_t self, int flags) 249 { 250 struct athn_pci_softc *psc = device_private(self); 251 struct athn_softc *sc = &psc->psc_sc; 252 253 if (psc->psc_ih != NULL) { 254 athn_detach(sc); 255 pci_intr_disestablish(psc->psc_pc, psc->psc_ih); 256 psc->psc_ih = NULL; 257 } 258 if (psc->psc_mapsz > 0) { 259 bus_space_unmap(psc->psc_iot, psc->psc_ioh, psc->psc_mapsz); 260 psc->psc_mapsz = 0; 261 } 262 return 0; 263 } 264 265 Static int 266 athn_pci_activate(device_t self, enum devact act) 267 { 268 struct athn_pci_softc *psc = device_private(self); 269 struct athn_softc *sc = &psc->psc_sc; 270 271 switch (act) { 272 case DVACT_DEACTIVATE: 273 if_deactivate(TAILQ_FIRST(&(sc->sc_ic.ic_vaps))->iv_ifp); 274 break; 275 } 276 return 0; 277 } 278 279 Static bool 280 athn_pci_suspend(device_t self, const pmf_qual_t *qual) 281 { 282 struct athn_pci_softc *psc = device_private(self); 283 struct athn_softc *sc = &psc->psc_sc; 284 285 athn_suspend(sc); 286 if (psc->psc_ih != NULL) { 287 pci_intr_disestablish(psc->psc_pc, psc->psc_ih); 288 psc->psc_ih = NULL; 289 } 290 return true; 291 } 292 293 Static bool 294 athn_pci_resume(device_t self, const pmf_qual_t *qual) 295 { 296 struct athn_pci_softc *psc = device_private(self); 297 struct athn_softc *sc = &psc->psc_sc; 298 pcireg_t reg; 299 300 /* 301 * XXX: see comment in athn_attach(). 302 */ 303 reg = pci_conf_read(psc->psc_pc, psc->psc_tag, 0x40); 304 if (reg & 0xff00) 305 pci_conf_write(psc->psc_pc, psc->psc_tag, 0x40, reg & ~0xff00); 306 307 /* XXX re-establishing interrupt shouldn't be needed */ 308 psc->psc_ih = pci_intr_establish_xname(psc->psc_pc, psc->psc_pih, 309 IPL_NET, athn_intr, sc, device_xname(self)); 310 if (psc->psc_ih == NULL) { 311 aprint_error_dev(self, "couldn't map interrupt\n"); 312 return false; 313 } 314 return athn_resume(sc); 315 } 316 317 Static uint32_t 318 athn_pci_read(struct athn_softc *sc, uint32_t addr) 319 { 320 struct athn_pci_softc *psc = (struct athn_pci_softc *)sc; 321 322 return bus_space_read_4(psc->psc_iot, psc->psc_ioh, addr); 323 } 324 325 Static void 326 athn_pci_write(struct athn_softc *sc, uint32_t addr, uint32_t val) 327 { 328 struct athn_pci_softc *psc = (struct athn_pci_softc *)sc; 329 330 bus_space_write_4(psc->psc_iot, psc->psc_ioh, addr, val); 331 } 332 333 Static void 334 athn_pci_write_barrier(struct athn_softc *sc) 335 { 336 struct athn_pci_softc *psc = (struct athn_pci_softc *)sc; 337 338 bus_space_barrier(psc->psc_iot, psc->psc_ioh, 0, psc->psc_mapsz, 339 BUS_SPACE_BARRIER_WRITE); 340 } 341 342 Static void 343 athn_pci_disable_aspm(struct athn_softc *sc) 344 { 345 struct athn_pci_softc *psc = (struct athn_pci_softc *)sc; 346 pcireg_t reg; 347 348 /* Disable PCIe Active State Power Management (ASPM). */ 349 reg = pci_conf_read(psc->psc_pc, psc->psc_tag, 350 psc->psc_cap_off + PCIE_LCSR); 351 reg &= ~(PCIE_LCSR_ASPM_L0S | PCIE_LCSR_ASPM_L1); 352 pci_conf_write(psc->psc_pc, psc->psc_tag, 353 psc->psc_cap_off + PCIE_LCSR, reg); 354 } 355
Indexes created Sun Sep 28 16:09:52 GMT 2025