if_athn_pci.c revision 1.4
1 /* $NetBSD: if_athn_pci.c,v 1.4 2013/03/31 11:38:36 martin Exp $ */ 2 /* $OpenBSD: if_athn_pci.c,v 1.11 2011/01/08 10:02:32 damien Exp $ */ 3 4 /*- 5 * Copyright (c) 2009 Damien Bergamini <damien.bergamini (at) free.fr> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 /* 21 * PCI front-end for Atheros 802.11a/g/n chipsets. 22 */ 23 24 #include <sys/cdefs.h> 25 __KERNEL_RCSID(0, "$NetBSD: if_athn_pci.c,v 1.4 2013/03/31 11:38:36 martin Exp $"); 26 27 #include "opt_inet.h" 28 29 #include <sys/param.h> 30 #include <sys/sockio.h> 31 #include <sys/mbuf.h> 32 #include <sys/kernel.h> 33 #include <sys/socket.h> 34 #include <sys/systm.h> 35 #include <sys/malloc.h> 36 #include <sys/callout.h> 37 #include <sys/device.h> 38 39 #include <sys/bus.h> 40 #include <sys/intr.h> 41 42 #include <net/if.h> 43 #include <net/if_media.h> 44 45 #include <net80211/ieee80211_var.h> 46 #include <net80211/ieee80211_amrr.h> 47 #include <net80211/ieee80211_radiotap.h> 48 49 #include <dev/ic/athnreg.h> 50 #include <dev/ic/athnvar.h> 51 52 #include <dev/pci/pcireg.h> 53 #include <dev/pci/pcivar.h> 54 #include <dev/pci/pcidevs.h> 55 56 #define PCI_SUBSYSID_ATHEROS_COEX2WIRE 0x309b 57 #define PCI_SUBSYSID_ATHEROS_COEX3WIRE_SA 0x30aa 58 #define PCI_SUBSYSID_ATHEROS_COEX3WIRE_DA 0x30ab 59 60 #define ATHN_PCI_MMBA PCI_BAR(0) /* memory mapped base */ 61 62 struct athn_pci_softc { 63 struct athn_softc psc_sc; 64 65 /* PCI specific goo. */ 66 pci_chipset_tag_t psc_pc; 67 pcitag_t psc_tag; 68 pci_intr_handle_t psc_pih; 69 void *psc_ih; 70 bus_space_tag_t psc_iot; 71 bus_space_handle_t psc_ioh; 72 bus_size_t psc_mapsz; 73 int psc_cap_off; 74 }; 75 76 #define Static static 77 78 Static int athn_pci_match(device_t, cfdata_t, void *); 79 Static void athn_pci_attach(device_t, device_t, void *); 80 Static int athn_pci_detach(device_t, int); 81 Static int athn_pci_activate(device_t, enum devact); 82 83 CFATTACH_DECL_NEW(athn_pci, sizeof(struct athn_pci_softc), athn_pci_match, 84 athn_pci_attach, athn_pci_detach, athn_pci_activate); 85 86 Static bool athn_pci_resume(device_t, const pmf_qual_t *); 87 Static bool athn_pci_suspend(device_t, const pmf_qual_t *); 88 Static uint32_t athn_pci_read(struct athn_softc *, uint32_t); 89 Static void athn_pci_write(struct athn_softc *, uint32_t, uint32_t); 90 Static void athn_pci_write_barrier(struct athn_softc *); 91 Static void athn_pci_disable_aspm(struct athn_softc *); 92 93 Static int 94 athn_pci_match(device_t parent, cfdata_t match, void *aux) 95 { 96 static const struct { 97 pci_vendor_id_t apd_vendor; 98 pci_product_id_t apd_product; 99 } athn_pci_devices[] = { 100 { PCI_VENDOR_ATHEROS, PCI_PRODUCT_ATHEROS_AR5416 }, 101 { PCI_VENDOR_ATHEROS, PCI_PRODUCT_ATHEROS_AR5418 }, 102 { PCI_VENDOR_ATHEROS, PCI_PRODUCT_ATHEROS_AR9160 }, 103 { PCI_VENDOR_ATHEROS, PCI_PRODUCT_ATHEROS_AR9280 }, 104 { PCI_VENDOR_ATHEROS, PCI_PRODUCT_ATHEROS_AR9281 }, 105 { PCI_VENDOR_ATHEROS, PCI_PRODUCT_ATHEROS_AR9285 }, 106 { PCI_VENDOR_ATHEROS, PCI_PRODUCT_ATHEROS_AR2427 }, 107 { PCI_VENDOR_ATHEROS, PCI_PRODUCT_ATHEROS_AR9227 }, 108 { PCI_VENDOR_ATHEROS, PCI_PRODUCT_ATHEROS_AR9287 }, 109 { PCI_VENDOR_ATHEROS, PCI_PRODUCT_ATHEROS_AR9300 } 110 }; 111 struct pci_attach_args *pa = aux; 112 size_t i; 113 114 for (i = 0; i < __arraycount(athn_pci_devices); i++) { 115 if (PCI_VENDOR(pa->pa_id) == athn_pci_devices[i].apd_vendor && 116 PCI_PRODUCT(pa->pa_id) == athn_pci_devices[i].apd_product) 117 return 1; 118 } 119 return 0; 120 } 121 122 Static void 123 athn_pci_attach(device_t parent, device_t self, void *aux) 124 { 125 struct athn_pci_softc *psc = device_private(self); 126 struct athn_softc *sc = &psc->psc_sc; 127 struct ieee80211com *ic = &sc->sc_ic; 128 struct pci_attach_args *pa = aux; 129 const char *intrstr; 130 pcireg_t memtype, reg; 131 pci_product_id_t subsysid; 132 int error; 133 134 sc->sc_dev = self; 135 sc->sc_dmat = pa->pa_dmat; 136 psc->psc_pc = pa->pa_pc; 137 psc->psc_tag = pa->pa_tag; 138 139 sc->sc_ops.read = athn_pci_read; 140 sc->sc_ops.write = athn_pci_write; 141 sc->sc_ops.write_barrier = athn_pci_write_barrier; 142 143 /* 144 * Get the offset of the PCI Express Capability Structure in PCI 145 * Configuration Space (Linux hardcodes it as 0x60.) 146 */ 147 error = pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_PCIEXPRESS, 148 &psc->psc_cap_off, NULL); 149 if (error != 0) { /* Found. */ 150 sc->sc_disable_aspm = athn_pci_disable_aspm; 151 sc->sc_flags |= ATHN_FLAG_PCIE; 152 } 153 /* 154 * Noone knows why this shit is necessary but there are claims that 155 * not doing this may cause very frequent PCI FATAL interrupts from 156 * the card: http://bugzilla.kernel.org/show_bug.cgi?id=13483 157 */ 158 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, 0x40); 159 if (reg & 0xff00) 160 pci_conf_write(pa->pa_pc, pa->pa_tag, 0x40, reg & ~0xff00); 161 162 /* Change latency timer; default value yields poor results. */ 163 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG); 164 reg &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT); 165 reg |= 168 << PCI_LATTIMER_SHIFT; 166 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG, reg); 167 168 /* Determine if bluetooth is also supported (combo chip.) */ 169 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 170 subsysid = PCI_PRODUCT(reg); 171 if (subsysid == PCI_SUBSYSID_ATHEROS_COEX3WIRE_SA || 172 subsysid == PCI_SUBSYSID_ATHEROS_COEX3WIRE_DA) 173 sc->sc_flags |= ATHN_FLAG_BTCOEX3WIRE; 174 else if (subsysid == PCI_SUBSYSID_ATHEROS_COEX2WIRE) 175 sc->sc_flags |= ATHN_FLAG_BTCOEX2WIRE; 176 177 /* 178 * Setup memory-mapping of PCI registers. 179 */ 180 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, ATHN_PCI_MMBA); 181 if (memtype != PCI_MAPREG_TYPE_MEM && 182 memtype != PCI_MAPREG_MEM_TYPE_64BIT) { 183 aprint_error_dev(self, "bad pci register type %d\n", 184 (int)memtype); 185 goto fail; 186 } 187 error = pci_mapreg_map(pa, PCI_MAPREG_START, memtype, 0, &psc->psc_iot, 188 &psc->psc_ioh, NULL, &psc->psc_mapsz); 189 if (error != 0) { 190 aprint_error_dev(self, "cannot map register space\n"); 191 goto fail; 192 } 193 194 /* 195 * Arrange interrupt line. 196 */ 197 if (pci_intr_map(pa, &psc->psc_pih) != 0) { 198 aprint_error_dev(self, "couldn't map interrupt\n"); 199 goto fail1; 200 } 201 202 intrstr = pci_intr_string(psc->psc_pc, psc->psc_pih); 203 psc->psc_ih = pci_intr_establish(psc->psc_pc, psc->psc_pih, IPL_NET, 204 athn_intr, sc); 205 if (psc->psc_ih == NULL) { 206 aprint_error_dev(self, "couldn't map interrupt\n"); 207 goto fail1; 208 } 209 aprint_verbose_dev(self, "interrupting at %s\n", intrstr); 210 211 ic->ic_ifp = &sc->sc_if; 212 if (athn_attach(sc) != 0) 213 goto fail2; 214 215 if (pmf_device_register(self, athn_pci_suspend, athn_pci_resume)) { 216 pmf_class_network_register(self, &sc->sc_if); 217 pmf_device_suspend(self, &sc->sc_qual); 218 } 219 else 220 aprint_error_dev(self, "couldn't establish power handler\n"); 221 222 ieee80211_announce(ic); 223 return; 224 225 fail2: 226 pci_intr_disestablish(psc->psc_pc, psc->psc_ih); 227 psc->psc_ih = NULL; 228 fail1: 229 bus_space_unmap(psc->psc_iot, psc->psc_ioh, psc->psc_mapsz); 230 psc->psc_mapsz = 0; 231 fail: 232 return; 233 } 234 235 Static int 236 athn_pci_detach(device_t self, int flags) 237 { 238 struct athn_pci_softc *psc = device_private(self); 239 struct athn_softc *sc = &psc->psc_sc; 240 241 if (psc->psc_ih != NULL) { 242 athn_detach(sc); 243 pci_intr_disestablish(psc->psc_pc, psc->psc_ih); 244 psc->psc_ih = NULL; 245 } 246 if (psc->psc_mapsz > 0) { 247 bus_space_unmap(psc->psc_iot, psc->psc_ioh, psc->psc_mapsz); 248 psc->psc_mapsz = 0; 249 } 250 return 0; 251 } 252 253 Static int 254 athn_pci_activate(device_t self, enum devact act) 255 { 256 struct athn_pci_softc *psc = device_private(self); 257 struct athn_softc *sc = &psc->psc_sc; 258 259 switch (act) { 260 case DVACT_DEACTIVATE: 261 if_deactivate(sc->sc_ic.ic_ifp); 262 break; 263 } 264 return 0; 265 } 266 267 Static bool 268 athn_pci_suspend(device_t self, const pmf_qual_t *qual) 269 { 270 struct athn_pci_softc *psc = device_private(self); 271 struct athn_softc *sc = &psc->psc_sc; 272 273 athn_suspend(sc); 274 if (psc->psc_ih != NULL) { 275 pci_intr_disestablish(psc->psc_pc, psc->psc_ih); 276 psc->psc_ih = NULL; 277 } 278 return true; 279 } 280 281 Static bool 282 athn_pci_resume(device_t self, const pmf_qual_t *qual) 283 { 284 struct athn_pci_softc *psc = device_private(self); 285 struct athn_softc *sc = &psc->psc_sc; 286 pcireg_t reg; 287 288 /* 289 * XXX: see comment in athn_attach(). 290 */ 291 reg = pci_conf_read(psc->psc_pc, psc->psc_tag, 0x40); 292 if (reg & 0xff00) 293 pci_conf_write(psc->psc_pc, psc->psc_tag, 0x40, reg & ~0xff00); 294 295 psc->psc_ih = pci_intr_establish(psc->psc_pc, psc->psc_pih, IPL_NET, 296 athn_intr, sc); 297 if (psc->psc_ih == NULL) { 298 aprint_error_dev(self, "couldn't map interrupt\n"); 299 return false; 300 } 301 return athn_resume(sc); 302 } 303 304 Static uint32_t 305 athn_pci_read(struct athn_softc *sc, uint32_t addr) 306 { 307 struct athn_pci_softc *psc = (struct athn_pci_softc *)sc; 308 309 return bus_space_read_4(psc->psc_iot, psc->psc_ioh, addr); 310 } 311 312 Static void 313 athn_pci_write(struct athn_softc *sc, uint32_t addr, uint32_t val) 314 { 315 struct athn_pci_softc *psc = (struct athn_pci_softc *)sc; 316 317 bus_space_write_4(psc->psc_iot, psc->psc_ioh, addr, val); 318 } 319 320 Static void 321 athn_pci_write_barrier(struct athn_softc *sc) 322 { 323 struct athn_pci_softc *psc = (struct athn_pci_softc *)sc; 324 325 bus_space_barrier(psc->psc_iot, psc->psc_ioh, 0, psc->psc_mapsz, 326 BUS_SPACE_BARRIER_WRITE); 327 } 328 329 Static void 330 athn_pci_disable_aspm(struct athn_softc *sc) 331 { 332 struct athn_pci_softc *psc = (struct athn_pci_softc *)sc; 333 pcireg_t reg; 334 335 /* Disable PCIe Active State Power Management (ASPM). */ 336 reg = pci_conf_read(psc->psc_pc, psc->psc_tag, 337 psc->psc_cap_off + PCI_PCIE_LCSR); 338 reg &= ~(PCI_PCIE_LCSR_ASPM_L0S | PCI_PCIE_LCSR_ASPM_L1); 339 pci_conf_write(psc->psc_pc, psc->psc_tag, 340 psc->psc_cap_off + PCI_PCIE_LCSR, reg); 341 } 342
Indexes created Thu Sep 25 16:09:42 GMT 2025