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if_bcereg.h revision 1.1
      1  1.1  mrg /* $NetBSD: if_bcereg.h,v 1.1 2003/09/27 13:13:28 mrg Exp $	 */
      2  1.1  mrg 
      3  1.1  mrg /*
      4  1.1  mrg  * Copyright (c) 2003 Clifford Wright. All rights reserved.
      5  1.1  mrg  *
      6  1.1  mrg  * Redistribution and use in source and binary forms, with or without
      7  1.1  mrg  * modification, are permitted provided that the following conditions
      8  1.1  mrg  * are met:
      9  1.1  mrg  * 1. Redistributions of source code must retain the above copyright
     10  1.1  mrg  *    notice, this list of conditions and the following disclaimer.
     11  1.1  mrg  * 2. Redistributions in binary form must reproduce the above copyright
     12  1.1  mrg  *    notice, this list of conditions and the following disclaimer in the
     13  1.1  mrg  *    documentation and/or other materials provided with the distribution.
     14  1.1  mrg  * 3. The name of the author may not be used to endorse or promote products
     15  1.1  mrg  *    derived from this software without specific prior written permission.
     16  1.1  mrg  *
     17  1.1  mrg  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
     18  1.1  mrg  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
     19  1.1  mrg  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
     20  1.1  mrg  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
     21  1.1  mrg  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
     22  1.1  mrg  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
     23  1.1  mrg  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
     24  1.1  mrg  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
     25  1.1  mrg  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
     26  1.1  mrg  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
     27  1.1  mrg  * SUCH DAMAGE.
     28  1.1  mrg  */
     29  1.1  mrg 
     30  1.1  mrg /* Broadcom BCM440x */
     31  1.1  mrg 
     32  1.1  mrg /* PCI registers defined in the PCI 2.2 spec. */
     33  1.1  mrg #define BCE_PCI_BAR0			0x10
     34  1.1  mrg 
     35  1.1  mrg /* Sonics SB register access */
     36  1.1  mrg #define BCE_REG_WIN			0x80
     37  1.1  mrg #define BCE_SONICS_WIN			0x18002000
     38  1.1  mrg 
     39  1.1  mrg /* Sonics PCI control */
     40  1.1  mrg #define BCE_SPCI_TR2			0x0108	/* Sonics to PCI translation
     41  1.1  mrg 						 * 2 */
     42  1.1  mrg /* bit defines */
     43  1.1  mrg #define SBTOPCI_PREF			0x4	/* prefetch enable */
     44  1.1  mrg #define SBTOPCI_BURST			0x8	/* burst enable */
     45  1.1  mrg #define BCE_SBINTVEC			0x0f94
     46  1.1  mrg /* interrupt bits */
     47  1.1  mrg #define SBIV_ENET0			0x02	/* enable for enet 0 */
     48  1.1  mrg #define SBIV_ENET1			0x40	/* enable for enet 1 */
     49  1.1  mrg 
     50  1.1  mrg 
     51  1.1  mrg /* Host Interface Registers */
     52  1.1  mrg 
     53  1.1  mrg #define BCE_DEVCTL			0x0000	/* device control */
     54  1.1  mrg /* device control bits */
     55  1.1  mrg #define BCE_DC_IP			0x00000400	/* internal phy present */
     56  1.1  mrg #define BCE_DC_ER			0x00008000	/* ephy reset */
     57  1.1  mrg /* Interrupt Control */
     58  1.1  mrg #define BCE_INT_STS			0x0020
     59  1.1  mrg #define BCE_INT_MASK			0x0024
     60  1.1  mrg /* bits for both status, and mask */
     61  1.1  mrg #define I_TO				0x00000080	/* general timeout */
     62  1.1  mrg #define I_PC				0x00000400	/* descriptor error */
     63  1.1  mrg #define I_PD				0x00000800	/* data error */
     64  1.1  mrg #define I_DE				0x00001000	/* desc. protocol error */
     65  1.1  mrg #define I_RU				0x00002000	/* rx desc. underflow */
     66  1.1  mrg #define I_RO				0x00004000	/* rx fifo overflow */
     67  1.1  mrg #define I_XU				0x00008000	/* tx fifo underflow */
     68  1.1  mrg #define I_RI				0x00010000	/* receive interrupt */
     69  1.1  mrg #define I_XI				0x01000000	/* transmit interrupt */
     70  1.1  mrg 
     71  1.1  mrg /* Ethernet MAC Control */
     72  1.1  mrg #define BCE_MACCTL			0x00A8	/* ethernet mac control */
     73  1.1  mrg /* mac control bits */
     74  1.1  mrg #define BCE_EMC_CG				0x00000001	/* crc32 generation */
     75  1.1  mrg 
     76  1.1  mrg /* DMA Interrupt control */
     77  1.1  mrg #define BCE_DMAI_CTL			0x0100
     78  1.1  mrg 
     79  1.1  mrg /* DMA registers */
     80  1.1  mrg #define BCE_DMA_TXCTL			0x0200	/* transmit control */
     81  1.1  mrg /* transmit control bits */
     82  1.1  mrg #define XC_XE				0x1	/* transmit enable */
     83  1.1  mrg #define XC_LE				0x4	/* loopback enable */
     84  1.1  mrg #define BCE_DMA_TXADDR			0x0204	/* tx ring base address */
     85  1.1  mrg #define BCE_DMA_DPTR			0x0208	/* last tx descriptor */
     86  1.1  mrg #define BCE_DMA_TXSTATUS		0x020C	/* active desc, etc */
     87  1.1  mrg #define BCE_DMA_RXCTL			0x0210	/* enable, etc */
     88  1.1  mrg #define BCE_DMA_RXADDR			0x0214	/* rx ring base address */
     89  1.1  mrg #define BCE_DMA_RXDPTR			0x0218	/* last descriptor */
     90  1.1  mrg #define BCE_DMA_RXSTATUS		0x021C	/* active desc, etc */
     91  1.1  mrg /* receive status bits */
     92  1.1  mrg #define RS_CD_MASK			0x0fff	/* current descriptor pointer */
     93  1.1  mrg 
     94  1.1  mrg /* Ethernet MAC control registers */
     95  1.1  mrg #define BCE_RX_CTL			0x0400	/* receive config */
     96  1.1  mrg /* config bits */
     97  1.1  mrg #define ERC_DB				0x00000001	/* disable broadcast */
     98  1.1  mrg #define ERC_AM				0x00000002	/* rx all multicast */
     99  1.1  mrg #define ERC_PE				0x00000008	/* promiscuous enable */
    100  1.1  mrg 
    101  1.1  mrg #define BCE_RX_MAX			0x0404	/* max packet length */
    102  1.1  mrg #define BCE_TX_MAX			0x0408
    103  1.1  mrg #define BCE_MI_CTL			0x0410
    104  1.1  mrg #define BCE_MI_COMM			0x0414
    105  1.1  mrg #define BCE_MI_STS			0x041C
    106  1.1  mrg /* mii status bits */
    107  1.1  mrg #define BCE_MIINTR			0x00000001	/* mii mdio interrupt */
    108  1.1  mrg 
    109  1.1  mrg #define BCE_FILT_LOW			0x0420	/* mac low 4 bytes */
    110  1.1  mrg #define BCE_FILT_HI			0x0424	/* mac hi 2 bytes */
    111  1.1  mrg #define BCE_FILT_CTL			0x0428	/* packet filter ctrl */
    112  1.1  mrg #define BCE_ENET_CTL			0x042C
    113  1.1  mrg /* bits for mac control */
    114  1.1  mrg #define EC_EE				0x00000001	/* emac enable */
    115  1.1  mrg #define EC_ED				0x00000002	/* disable emac */
    116  1.1  mrg #define EC_ES				0x00000004	/* soft reset emac */
    117  1.1  mrg #define EC_EP				0x00000008	/* external phy */
    118  1.1  mrg #define BCE_TX_CTL			0x0430
    119  1.1  mrg /* bits for transmit control */
    120  1.1  mrg #define EXC_FD				0x00000001	/* full duplex */
    121  1.1  mrg #define BCE_TX_WATER			0x0434	/* tx watermark */
    122  1.1  mrg 
    123  1.1  mrg /* statistics counters */
    124  1.1  mrg #define BCE_RX_PKTS			0x058C
    125  1.1  mrg 
    126  1.1  mrg /* SiliconBackplane registers */
    127  1.1  mrg #define BCE_SBIMSTATE			0x0f90
    128  1.1  mrg #define BCE_SBTMSTATELOW		0x0f98
    129  1.1  mrg #define BCE_SBTMSTATEHI			0x0f9C
    130  1.1  mrg #define SBTML_RESET     0x1	/* reset */
    131  1.1  mrg #define SBTML_REJ       0x2	/* reject */
    132  1.1  mrg #define SBTML_CLK       0x10000	/* clock enable */
    133  1.1  mrg #define SBTML_FGC       0x20000	/* force gated clocks on */
    134  1.1  mrg 
    135  1.1  mrg /* MI communication register */
    136  1.1  mrg #define BCE_MICOMM_DATA			0x0000FFFF
    137  1.1  mrg 
    138  1.1  mrg 
    139  1.1  mrg #define BCE_MIREG(x)	((x & 0x1F) << 18)
    140  1.1  mrg #define BCE_MIPHY(x)	((x & 0x1F) << 23)
    141  1.1  mrg 
    142  1.1  mrg /* transmit buffer max frags allowed */
    143  1.1  mrg #define BCE_NTXFRAGS	16
    144  1.1  mrg 
    145  1.1  mrg /* ring descriptor */
    146  1.1  mrg struct bce_dma_slot {
    147  1.1  mrg 	unsigned long   ctrl;
    148  1.1  mrg 	unsigned long   addr;
    149  1.1  mrg };
    150  1.1  mrg #define CTRL_BC_MASK	0x1fff	/* buffer byte count */
    151  1.1  mrg #define CTRL_EOT	0x10000000	/* end of descriptor table */
    152  1.1  mrg #define CTRL_IOC	0x20000000	/* interrupt on completion */
    153  1.1  mrg #define CTRL_EOF	0x40000000	/* end of frame */
    154  1.1  mrg #define CTRL_SOF	0x80000000	/* start of frame */
    155  1.1  mrg 
    156  1.1  mrg /* Packet status is returned in a pre-packet header */
    157  1.1  mrg struct rx_pph {
    158  1.1  mrg 	unsigned short  len;
    159  1.1  mrg 	unsigned short  flags;
    160  1.1  mrg 	unsigned short  pad[12];
    161  1.1  mrg };
    162  1.1  mrg 
    163  1.1  mrg /* packet status flags bits */
    164  1.1  mrg #define RXF_NO				0x8	/* odd number of nibbles */
    165  1.1  mrg #define RXF_RXER			0x4	/* receive symbol error */
    166  1.1  mrg #define RXF_CRC				0x2	/* crc error */
    167  1.1  mrg #define RXF_OV				0x1	/* fifo overflow */
    168  1.1  mrg 
    169  1.1  mrg /* number of descriptors used in a ring */
    170  1.1  mrg #define BCE_NRXDESC		128
    171  1.1  mrg #define BCE_NTXDESC		128
    172  1.1  mrg 
    173  1.1  mrg /*
    174  1.1  mrg  * Mbuf pointers. We need these to keep track of the virtual addresses
    175  1.1  mrg  * of our mbuf chains since we can only convert from physical to virtual,
    176  1.1  mrg  * not the other way around.
    177  1.1  mrg  */
    178  1.1  mrg struct bce_chain_data {
    179  1.1  mrg 	struct mbuf    *bce_tx_chain[BCE_NTXDESC];
    180  1.1  mrg 	struct mbuf    *bce_rx_chain[BCE_NRXDESC];
    181  1.1  mrg 	bus_dmamap_t    bce_tx_map[BCE_NTXDESC];
    182  1.1  mrg 	bus_dmamap_t    bce_rx_map[BCE_NRXDESC];
    183  1.1  mrg };
    184  1.1  mrg 
    185  1.1  mrg #define BCE_TIMEOUT		100	/* # 10us for mii read/write */
    186  1.1  mrg 
    187  1.1  mrg struct bce_softc {
    188  1.1  mrg 	struct device   bce_dev;
    189  1.1  mrg 	struct ethercom ethercom;	/* interface info */
    190  1.1  mrg 	bus_space_handle_t bce_bhandle;
    191  1.1  mrg 	bus_space_tag_t bce_btag;
    192  1.1  mrg 	void           *bce_intrhand;
    193  1.1  mrg 	struct pci_attach_args bce_pa;
    194  1.1  mrg 	struct mii_data bce_mii;
    195  1.1  mrg 	u_int32_t       bce_phy;/* eeprom indicated phy */
    196  1.1  mrg 	struct ifmedia  bce_ifmedia;	/* media info *//* Check */
    197  1.1  mrg 	bus_dma_tag_t   bce_dmatag;
    198  1.1  mrg 	u_int8_t        enaddr[ETHER_ADDR_LEN];
    199  1.1  mrg 	struct bce_dma_slot *bce_rx_ring;	/* receive ring */
    200  1.1  mrg 	struct bce_dma_slot *bce_tx_ring;	/* transmit ring */
    201  1.1  mrg 	struct bce_chain_data bce_cdata;	/* mbufs */
    202  1.1  mrg 	bus_dmamap_t    bce_ring_map;
    203  1.1  mrg 	u_int32_t       bce_rxin;	/* last rx descriptor seen */
    204  1.1  mrg 	u_int32_t       bce_txin;	/* last tx descriptor seen */
    205  1.1  mrg 	int             bce_txsfree;	/* no. tx slots available */
    206  1.1  mrg 	int             bce_txsnext;	/* next available tx slot */
    207  1.1  mrg 	struct callout  bce_timeout;
    208  1.1  mrg };
    209