if_bcereg.h revision 1.1
1 /* $NetBSD: if_bcereg.h,v 1.1 2003/09/27 13:13:28 mrg Exp $ */ 2 3 /* 4 * Copyright (c) 2003 Clifford Wright. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. The name of the author may not be used to endorse or promote products 15 * derived from this software without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 22 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 23 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 24 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 25 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 /* Broadcom BCM440x */ 31 32 /* PCI registers defined in the PCI 2.2 spec. */ 33 #define BCE_PCI_BAR0 0x10 34 35 /* Sonics SB register access */ 36 #define BCE_REG_WIN 0x80 37 #define BCE_SONICS_WIN 0x18002000 38 39 /* Sonics PCI control */ 40 #define BCE_SPCI_TR2 0x0108 /* Sonics to PCI translation 41 * 2 */ 42 /* bit defines */ 43 #define SBTOPCI_PREF 0x4 /* prefetch enable */ 44 #define SBTOPCI_BURST 0x8 /* burst enable */ 45 #define BCE_SBINTVEC 0x0f94 46 /* interrupt bits */ 47 #define SBIV_ENET0 0x02 /* enable for enet 0 */ 48 #define SBIV_ENET1 0x40 /* enable for enet 1 */ 49 50 51 /* Host Interface Registers */ 52 53 #define BCE_DEVCTL 0x0000 /* device control */ 54 /* device control bits */ 55 #define BCE_DC_IP 0x00000400 /* internal phy present */ 56 #define BCE_DC_ER 0x00008000 /* ephy reset */ 57 /* Interrupt Control */ 58 #define BCE_INT_STS 0x0020 59 #define BCE_INT_MASK 0x0024 60 /* bits for both status, and mask */ 61 #define I_TO 0x00000080 /* general timeout */ 62 #define I_PC 0x00000400 /* descriptor error */ 63 #define I_PD 0x00000800 /* data error */ 64 #define I_DE 0x00001000 /* desc. protocol error */ 65 #define I_RU 0x00002000 /* rx desc. underflow */ 66 #define I_RO 0x00004000 /* rx fifo overflow */ 67 #define I_XU 0x00008000 /* tx fifo underflow */ 68 #define I_RI 0x00010000 /* receive interrupt */ 69 #define I_XI 0x01000000 /* transmit interrupt */ 70 71 /* Ethernet MAC Control */ 72 #define BCE_MACCTL 0x00A8 /* ethernet mac control */ 73 /* mac control bits */ 74 #define BCE_EMC_CG 0x00000001 /* crc32 generation */ 75 76 /* DMA Interrupt control */ 77 #define BCE_DMAI_CTL 0x0100 78 79 /* DMA registers */ 80 #define BCE_DMA_TXCTL 0x0200 /* transmit control */ 81 /* transmit control bits */ 82 #define XC_XE 0x1 /* transmit enable */ 83 #define XC_LE 0x4 /* loopback enable */ 84 #define BCE_DMA_TXADDR 0x0204 /* tx ring base address */ 85 #define BCE_DMA_DPTR 0x0208 /* last tx descriptor */ 86 #define BCE_DMA_TXSTATUS 0x020C /* active desc, etc */ 87 #define BCE_DMA_RXCTL 0x0210 /* enable, etc */ 88 #define BCE_DMA_RXADDR 0x0214 /* rx ring base address */ 89 #define BCE_DMA_RXDPTR 0x0218 /* last descriptor */ 90 #define BCE_DMA_RXSTATUS 0x021C /* active desc, etc */ 91 /* receive status bits */ 92 #define RS_CD_MASK 0x0fff /* current descriptor pointer */ 93 94 /* Ethernet MAC control registers */ 95 #define BCE_RX_CTL 0x0400 /* receive config */ 96 /* config bits */ 97 #define ERC_DB 0x00000001 /* disable broadcast */ 98 #define ERC_AM 0x00000002 /* rx all multicast */ 99 #define ERC_PE 0x00000008 /* promiscuous enable */ 100 101 #define BCE_RX_MAX 0x0404 /* max packet length */ 102 #define BCE_TX_MAX 0x0408 103 #define BCE_MI_CTL 0x0410 104 #define BCE_MI_COMM 0x0414 105 #define BCE_MI_STS 0x041C 106 /* mii status bits */ 107 #define BCE_MIINTR 0x00000001 /* mii mdio interrupt */ 108 109 #define BCE_FILT_LOW 0x0420 /* mac low 4 bytes */ 110 #define BCE_FILT_HI 0x0424 /* mac hi 2 bytes */ 111 #define BCE_FILT_CTL 0x0428 /* packet filter ctrl */ 112 #define BCE_ENET_CTL 0x042C 113 /* bits for mac control */ 114 #define EC_EE 0x00000001 /* emac enable */ 115 #define EC_ED 0x00000002 /* disable emac */ 116 #define EC_ES 0x00000004 /* soft reset emac */ 117 #define EC_EP 0x00000008 /* external phy */ 118 #define BCE_TX_CTL 0x0430 119 /* bits for transmit control */ 120 #define EXC_FD 0x00000001 /* full duplex */ 121 #define BCE_TX_WATER 0x0434 /* tx watermark */ 122 123 /* statistics counters */ 124 #define BCE_RX_PKTS 0x058C 125 126 /* SiliconBackplane registers */ 127 #define BCE_SBIMSTATE 0x0f90 128 #define BCE_SBTMSTATELOW 0x0f98 129 #define BCE_SBTMSTATEHI 0x0f9C 130 #define SBTML_RESET 0x1 /* reset */ 131 #define SBTML_REJ 0x2 /* reject */ 132 #define SBTML_CLK 0x10000 /* clock enable */ 133 #define SBTML_FGC 0x20000 /* force gated clocks on */ 134 135 /* MI communication register */ 136 #define BCE_MICOMM_DATA 0x0000FFFF 137 138 139 #define BCE_MIREG(x) ((x & 0x1F) << 18) 140 #define BCE_MIPHY(x) ((x & 0x1F) << 23) 141 142 /* transmit buffer max frags allowed */ 143 #define BCE_NTXFRAGS 16 144 145 /* ring descriptor */ 146 struct bce_dma_slot { 147 unsigned long ctrl; 148 unsigned long addr; 149 }; 150 #define CTRL_BC_MASK 0x1fff /* buffer byte count */ 151 #define CTRL_EOT 0x10000000 /* end of descriptor table */ 152 #define CTRL_IOC 0x20000000 /* interrupt on completion */ 153 #define CTRL_EOF 0x40000000 /* end of frame */ 154 #define CTRL_SOF 0x80000000 /* start of frame */ 155 156 /* Packet status is returned in a pre-packet header */ 157 struct rx_pph { 158 unsigned short len; 159 unsigned short flags; 160 unsigned short pad[12]; 161 }; 162 163 /* packet status flags bits */ 164 #define RXF_NO 0x8 /* odd number of nibbles */ 165 #define RXF_RXER 0x4 /* receive symbol error */ 166 #define RXF_CRC 0x2 /* crc error */ 167 #define RXF_OV 0x1 /* fifo overflow */ 168 169 /* number of descriptors used in a ring */ 170 #define BCE_NRXDESC 128 171 #define BCE_NTXDESC 128 172 173 /* 174 * Mbuf pointers. We need these to keep track of the virtual addresses 175 * of our mbuf chains since we can only convert from physical to virtual, 176 * not the other way around. 177 */ 178 struct bce_chain_data { 179 struct mbuf *bce_tx_chain[BCE_NTXDESC]; 180 struct mbuf *bce_rx_chain[BCE_NRXDESC]; 181 bus_dmamap_t bce_tx_map[BCE_NTXDESC]; 182 bus_dmamap_t bce_rx_map[BCE_NRXDESC]; 183 }; 184 185 #define BCE_TIMEOUT 100 /* # 10us for mii read/write */ 186 187 struct bce_softc { 188 struct device bce_dev; 189 struct ethercom ethercom; /* interface info */ 190 bus_space_handle_t bce_bhandle; 191 bus_space_tag_t bce_btag; 192 void *bce_intrhand; 193 struct pci_attach_args bce_pa; 194 struct mii_data bce_mii; 195 u_int32_t bce_phy;/* eeprom indicated phy */ 196 struct ifmedia bce_ifmedia; /* media info *//* Check */ 197 bus_dma_tag_t bce_dmatag; 198 u_int8_t enaddr[ETHER_ADDR_LEN]; 199 struct bce_dma_slot *bce_rx_ring; /* receive ring */ 200 struct bce_dma_slot *bce_tx_ring; /* transmit ring */ 201 struct bce_chain_data bce_cdata; /* mbufs */ 202 bus_dmamap_t bce_ring_map; 203 u_int32_t bce_rxin; /* last rx descriptor seen */ 204 u_int32_t bce_txin; /* last tx descriptor seen */ 205 int bce_txsfree; /* no. tx slots available */ 206 int bce_txsnext; /* next available tx slot */ 207 struct callout bce_timeout; 208 }; 209
Indexes created Tue Sep 30 20:09:53 GMT 2025