if_bge.c revision 1.103 1 1.103 rpaulo /* $NetBSD: if_bge.c,v 1.103 2006/02/22 15:18:55 rpaulo Exp $ */
2 1.8 thorpej
3 1.1 fvdl /*
4 1.1 fvdl * Copyright (c) 2001 Wind River Systems
5 1.1 fvdl * Copyright (c) 1997, 1998, 1999, 2001
6 1.1 fvdl * Bill Paul <wpaul (at) windriver.com>. All rights reserved.
7 1.1 fvdl *
8 1.1 fvdl * Redistribution and use in source and binary forms, with or without
9 1.1 fvdl * modification, are permitted provided that the following conditions
10 1.1 fvdl * are met:
11 1.1 fvdl * 1. Redistributions of source code must retain the above copyright
12 1.1 fvdl * notice, this list of conditions and the following disclaimer.
13 1.1 fvdl * 2. Redistributions in binary form must reproduce the above copyright
14 1.1 fvdl * notice, this list of conditions and the following disclaimer in the
15 1.1 fvdl * documentation and/or other materials provided with the distribution.
16 1.1 fvdl * 3. All advertising materials mentioning features or use of this software
17 1.1 fvdl * must display the following acknowledgement:
18 1.1 fvdl * This product includes software developed by Bill Paul.
19 1.1 fvdl * 4. Neither the name of the author nor the names of any co-contributors
20 1.1 fvdl * may be used to endorse or promote products derived from this software
21 1.1 fvdl * without specific prior written permission.
22 1.1 fvdl *
23 1.1 fvdl * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
24 1.1 fvdl * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
25 1.1 fvdl * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
26 1.1 fvdl * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
27 1.1 fvdl * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
28 1.1 fvdl * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
29 1.1 fvdl * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
30 1.1 fvdl * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
31 1.1 fvdl * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
32 1.1 fvdl * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
33 1.1 fvdl * THE POSSIBILITY OF SUCH DAMAGE.
34 1.1 fvdl *
35 1.1 fvdl * $FreeBSD: if_bge.c,v 1.13 2002/04/04 06:01:31 wpaul Exp $
36 1.1 fvdl */
37 1.1 fvdl
38 1.1 fvdl /*
39 1.12 thorpej * Broadcom BCM570x family gigabit ethernet driver for NetBSD.
40 1.1 fvdl *
41 1.12 thorpej * NetBSD version by:
42 1.12 thorpej *
43 1.12 thorpej * Frank van der Linden <fvdl (at) wasabisystems.com>
44 1.12 thorpej * Jason Thorpe <thorpej (at) wasabisystems.com>
45 1.32 tron * Jonathan Stone <jonathan (at) dsg.stanford.edu>
46 1.12 thorpej *
47 1.12 thorpej * Originally written for FreeBSD by Bill Paul <wpaul (at) windriver.com>
48 1.1 fvdl * Senior Engineer, Wind River Systems
49 1.1 fvdl */
50 1.1 fvdl
51 1.1 fvdl /*
52 1.1 fvdl * The Broadcom BCM5700 is based on technology originally developed by
53 1.1 fvdl * Alteon Networks as part of the Tigon I and Tigon II gigabit ethernet
54 1.1 fvdl * MAC chips. The BCM5700, sometimes refered to as the Tigon III, has
55 1.1 fvdl * two on-board MIPS R4000 CPUs and can have as much as 16MB of external
56 1.1 fvdl * SSRAM. The BCM5700 supports TCP, UDP and IP checksum offload, jumbo
57 1.1 fvdl * frames, highly configurable RX filtering, and 16 RX and TX queues
58 1.1 fvdl * (which, along with RX filter rules, can be used for QOS applications).
59 1.1 fvdl * Other features, such as TCP segmentation, may be available as part
60 1.1 fvdl * of value-added firmware updates. Unlike the Tigon I and Tigon II,
61 1.1 fvdl * firmware images can be stored in hardware and need not be compiled
62 1.1 fvdl * into the driver.
63 1.1 fvdl *
64 1.1 fvdl * The BCM5700 supports the PCI v2.2 and PCI-X v1.0 standards, and will
65 1.33 tsutsui * function in a 32-bit/64-bit 33/66MHz bus, or a 64-bit/133MHz bus.
66 1.1 fvdl *
67 1.1 fvdl * The BCM5701 is a single-chip solution incorporating both the BCM5700
68 1.25 jonathan * MAC and a BCM5401 10/100/1000 PHY. Unlike the BCM5700, the BCM5701
69 1.1 fvdl * does not support external SSRAM.
70 1.1 fvdl *
71 1.1 fvdl * Broadcom also produces a variation of the BCM5700 under the "Altima"
72 1.1 fvdl * brand name, which is functionally similar but lacks PCI-X support.
73 1.1 fvdl *
74 1.1 fvdl * Without external SSRAM, you can only have at most 4 TX rings,
75 1.1 fvdl * and the use of the mini RX ring is disabled. This seems to imply
76 1.1 fvdl * that these features are simply not available on the BCM5701. As a
77 1.1 fvdl * result, this driver does not implement any support for the mini RX
78 1.1 fvdl * ring.
79 1.1 fvdl */
80 1.43 lukem
81 1.43 lukem #include <sys/cdefs.h>
82 1.103 rpaulo __KERNEL_RCSID(0, "$NetBSD: if_bge.c,v 1.103 2006/02/22 15:18:55 rpaulo Exp $");
83 1.1 fvdl
84 1.1 fvdl #include "bpfilter.h"
85 1.1 fvdl #include "vlan.h"
86 1.1 fvdl
87 1.1 fvdl #include <sys/param.h>
88 1.1 fvdl #include <sys/systm.h>
89 1.1 fvdl #include <sys/callout.h>
90 1.1 fvdl #include <sys/sockio.h>
91 1.1 fvdl #include <sys/mbuf.h>
92 1.1 fvdl #include <sys/malloc.h>
93 1.1 fvdl #include <sys/kernel.h>
94 1.1 fvdl #include <sys/device.h>
95 1.1 fvdl #include <sys/socket.h>
96 1.64 jonathan #include <sys/sysctl.h>
97 1.1 fvdl
98 1.1 fvdl #include <net/if.h>
99 1.1 fvdl #include <net/if_dl.h>
100 1.1 fvdl #include <net/if_media.h>
101 1.1 fvdl #include <net/if_ether.h>
102 1.1 fvdl
103 1.1 fvdl #ifdef INET
104 1.1 fvdl #include <netinet/in.h>
105 1.1 fvdl #include <netinet/in_systm.h>
106 1.1 fvdl #include <netinet/in_var.h>
107 1.1 fvdl #include <netinet/ip.h>
108 1.1 fvdl #endif
109 1.1 fvdl
110 1.95 jonathan /* Headers for TCP Segmentation Offload (TSO) */
111 1.95 jonathan #include <netinet/in_systm.h> /* n_time for <netinet/ip.h>... */
112 1.95 jonathan #include <netinet/in.h> /* ip_{src,dst}, for <netinet/ip.h> */
113 1.95 jonathan #include <netinet/ip.h> /* for struct ip */
114 1.95 jonathan #include <netinet/tcp.h> /* for struct tcphdr */
115 1.95 jonathan
116 1.95 jonathan
117 1.1 fvdl #if NBPFILTER > 0
118 1.1 fvdl #include <net/bpf.h>
119 1.1 fvdl #endif
120 1.1 fvdl
121 1.1 fvdl #include <dev/pci/pcireg.h>
122 1.1 fvdl #include <dev/pci/pcivar.h>
123 1.1 fvdl #include <dev/pci/pcidevs.h>
124 1.1 fvdl
125 1.1 fvdl #include <dev/mii/mii.h>
126 1.1 fvdl #include <dev/mii/miivar.h>
127 1.1 fvdl #include <dev/mii/miidevs.h>
128 1.1 fvdl #include <dev/mii/brgphyreg.h>
129 1.1 fvdl
130 1.1 fvdl #include <dev/pci/if_bgereg.h>
131 1.1 fvdl
132 1.1 fvdl #include <uvm/uvm_extern.h>
133 1.1 fvdl
134 1.46 jonathan #define ETHER_MIN_NOPAD (ETHER_MIN_LEN - ETHER_CRC_LEN) /* i.e., 60 */
135 1.46 jonathan
136 1.63 jonathan
137 1.63 jonathan /*
138 1.63 jonathan * Tunable thresholds for rx-side bge interrupt mitigation.
139 1.63 jonathan */
140 1.63 jonathan
141 1.63 jonathan /*
142 1.63 jonathan * The pairs of values below were obtained from empirical measurement
143 1.63 jonathan * on bcm5700 rev B2; they ar designed to give roughly 1 receive
144 1.63 jonathan * interrupt for every N packets received, where N is, approximately,
145 1.63 jonathan * the second value (rx_max_bds) in each pair. The values are chosen
146 1.63 jonathan * such that moving from one pair to the succeeding pair was observed
147 1.63 jonathan * to roughly halve interrupt rate under sustained input packet load.
148 1.63 jonathan * The values were empirically chosen to avoid overflowing internal
149 1.63 jonathan * limits on the bcm5700: inreasing rx_ticks much beyond 600
150 1.63 jonathan * results in internal wrapping and higher interrupt rates.
151 1.63 jonathan * The limit of 46 frames was chosen to match NFS workloads.
152 1.87 perry *
153 1.63 jonathan * These values also work well on bcm5701, bcm5704C, and (less
154 1.63 jonathan * tested) bcm5703. On other chipsets, (including the Altima chip
155 1.63 jonathan * family), the larger values may overflow internal chip limits,
156 1.63 jonathan * leading to increasing interrupt rates rather than lower interrupt
157 1.63 jonathan * rates.
158 1.63 jonathan *
159 1.63 jonathan * Applications using heavy interrupt mitigation (interrupting every
160 1.63 jonathan * 32 or 46 frames) in both directions may need to increase the TCP
161 1.63 jonathan * windowsize to above 131072 bytes (e.g., to 199608 bytes) to sustain
162 1.87 perry * full link bandwidth, due to ACKs and window updates lingering
163 1.63 jonathan * in the RX queue during the 30-to-40-frame interrupt-mitigation window.
164 1.63 jonathan */
165 1.63 jonathan struct bge_load_rx_thresh {
166 1.63 jonathan int rx_ticks;
167 1.63 jonathan int rx_max_bds; }
168 1.63 jonathan bge_rx_threshes[] = {
169 1.63 jonathan { 32, 2 },
170 1.63 jonathan { 50, 4 },
171 1.63 jonathan { 100, 8 },
172 1.63 jonathan { 192, 16 },
173 1.63 jonathan { 416, 32 },
174 1.63 jonathan { 598, 46 }
175 1.63 jonathan };
176 1.63 jonathan #define NBGE_RX_THRESH (sizeof(bge_rx_threshes) / sizeof(bge_rx_threshes[0]))
177 1.63 jonathan
178 1.63 jonathan /* XXX patchable; should be sysctl'able */
179 1.64 jonathan static int bge_auto_thresh = 1;
180 1.64 jonathan static int bge_rx_thresh_lvl;
181 1.64 jonathan
182 1.64 jonathan #ifdef __NetBSD__
183 1.64 jonathan static int bge_rxthresh_nodenum;
184 1.64 jonathan #endif /* __NetBSD__ */
185 1.63 jonathan
186 1.1 fvdl int bge_probe(struct device *, struct cfdata *, void *);
187 1.1 fvdl void bge_attach(struct device *, struct device *, void *);
188 1.82 jmcneill void bge_powerhook(int, void *);
189 1.1 fvdl void bge_release_resources(struct bge_softc *);
190 1.1 fvdl void bge_txeof(struct bge_softc *);
191 1.1 fvdl void bge_rxeof(struct bge_softc *);
192 1.1 fvdl
193 1.1 fvdl void bge_tick(void *);
194 1.1 fvdl void bge_stats_update(struct bge_softc *);
195 1.1 fvdl int bge_encap(struct bge_softc *, struct mbuf *, u_int32_t *);
196 1.102 perry static inline int bge_cksum_pad(struct mbuf *pkt);
197 1.102 perry static inline int bge_compact_dma_runt(struct mbuf *pkt);
198 1.1 fvdl
199 1.1 fvdl int bge_intr(void *);
200 1.1 fvdl void bge_start(struct ifnet *);
201 1.1 fvdl int bge_ioctl(struct ifnet *, u_long, caddr_t);
202 1.1 fvdl int bge_init(struct ifnet *);
203 1.1 fvdl void bge_stop(struct bge_softc *);
204 1.1 fvdl void bge_watchdog(struct ifnet *);
205 1.1 fvdl void bge_shutdown(void *);
206 1.1 fvdl int bge_ifmedia_upd(struct ifnet *);
207 1.1 fvdl void bge_ifmedia_sts(struct ifnet *, struct ifmediareq *);
208 1.1 fvdl
209 1.1 fvdl u_int8_t bge_eeprom_getbyte(struct bge_softc *, int, u_int8_t *);
210 1.1 fvdl int bge_read_eeprom(struct bge_softc *, caddr_t, int, int);
211 1.1 fvdl
212 1.1 fvdl void bge_setmulti(struct bge_softc *);
213 1.1 fvdl
214 1.1 fvdl void bge_handle_events(struct bge_softc *);
215 1.1 fvdl int bge_alloc_jumbo_mem(struct bge_softc *);
216 1.1 fvdl void bge_free_jumbo_mem(struct bge_softc *);
217 1.1 fvdl void *bge_jalloc(struct bge_softc *);
218 1.31 thorpej void bge_jfree(struct mbuf *, caddr_t, size_t, void *);
219 1.1 fvdl int bge_newbuf_std(struct bge_softc *, int, struct mbuf *, bus_dmamap_t);
220 1.1 fvdl int bge_newbuf_jumbo(struct bge_softc *, int, struct mbuf *);
221 1.1 fvdl int bge_init_rx_ring_std(struct bge_softc *);
222 1.1 fvdl void bge_free_rx_ring_std(struct bge_softc *);
223 1.1 fvdl int bge_init_rx_ring_jumbo(struct bge_softc *);
224 1.1 fvdl void bge_free_rx_ring_jumbo(struct bge_softc *);
225 1.1 fvdl void bge_free_tx_ring(struct bge_softc *);
226 1.1 fvdl int bge_init_tx_ring(struct bge_softc *);
227 1.1 fvdl
228 1.1 fvdl int bge_chipinit(struct bge_softc *);
229 1.1 fvdl int bge_blockinit(struct bge_softc *);
230 1.25 jonathan int bge_setpowerstate(struct bge_softc *, int);
231 1.1 fvdl
232 1.1 fvdl #ifdef notdef
233 1.1 fvdl u_int8_t bge_vpd_readbyte(struct bge_softc *, int);
234 1.1 fvdl void bge_vpd_read_res(struct bge_softc *, struct vpd_res *, int);
235 1.1 fvdl void bge_vpd_read(struct bge_softc *);
236 1.1 fvdl #endif
237 1.1 fvdl
238 1.1 fvdl u_int32_t bge_readmem_ind(struct bge_softc *, int);
239 1.1 fvdl void bge_writemem_ind(struct bge_softc *, int, int);
240 1.1 fvdl #ifdef notdef
241 1.1 fvdl u_int32_t bge_readreg_ind(struct bge_softc *, int);
242 1.1 fvdl #endif
243 1.1 fvdl void bge_writereg_ind(struct bge_softc *, int, int);
244 1.1 fvdl
245 1.1 fvdl int bge_miibus_readreg(struct device *, int, int);
246 1.1 fvdl void bge_miibus_writereg(struct device *, int, int, int);
247 1.1 fvdl void bge_miibus_statchg(struct device *);
248 1.1 fvdl
249 1.1 fvdl void bge_reset(struct bge_softc *);
250 1.1 fvdl
251 1.63 jonathan void bge_set_thresh(struct ifnet * /*ifp*/, int /*lvl*/);
252 1.63 jonathan void bge_update_all_threshes(int /*lvl*/);
253 1.63 jonathan
254 1.1 fvdl void bge_dump_status(struct bge_softc *);
255 1.1 fvdl void bge_dump_rxbd(struct bge_rx_bd *);
256 1.1 fvdl
257 1.95 jonathan
258 1.1 fvdl #define BGE_DEBUG
259 1.1 fvdl #ifdef BGE_DEBUG
260 1.1 fvdl #define DPRINTF(x) if (bgedebug) printf x
261 1.1 fvdl #define DPRINTFN(n,x) if (bgedebug >= (n)) printf x
262 1.95 jonathan #define BGE_TSO_PRINTF(x) do { if (bge_tso_debug) printf x ;} while (0)
263 1.1 fvdl int bgedebug = 0;
264 1.95 jonathan int bge_tso_debug = 0;
265 1.1 fvdl #else
266 1.1 fvdl #define DPRINTF(x)
267 1.1 fvdl #define DPRINTFN(n,x)
268 1.95 jonathan #define BGE_TSO_PRINTF(x)
269 1.1 fvdl #endif
270 1.1 fvdl
271 1.72 thorpej #ifdef BGE_EVENT_COUNTERS
272 1.72 thorpej #define BGE_EVCNT_INCR(ev) (ev).ev_count++
273 1.72 thorpej #define BGE_EVCNT_ADD(ev, val) (ev).ev_count += (val)
274 1.72 thorpej #define BGE_EVCNT_UPD(ev, val) (ev).ev_count = (val)
275 1.72 thorpej #else
276 1.72 thorpej #define BGE_EVCNT_INCR(ev) /* nothing */
277 1.72 thorpej #define BGE_EVCNT_ADD(ev, val) /* nothing */
278 1.72 thorpej #define BGE_EVCNT_UPD(ev, val) /* nothing */
279 1.72 thorpej #endif
280 1.72 thorpej
281 1.17 thorpej /* Various chip quirks. */
282 1.17 thorpej #define BGE_QUIRK_LINK_STATE_BROKEN 0x00000001
283 1.18 thorpej #define BGE_QUIRK_CSUM_BROKEN 0x00000002
284 1.24 matt #define BGE_QUIRK_ONLY_PHY_1 0x00000004
285 1.25 jonathan #define BGE_QUIRK_5700_SMALLDMA 0x00000008
286 1.25 jonathan #define BGE_QUIRK_5700_PCIX_REG_BUG 0x00000010
287 1.36 jonathan #define BGE_QUIRK_PRODUCER_BUG 0x00000020
288 1.37 jonathan #define BGE_QUIRK_PCIX_DMA_ALIGN_BUG 0x00000040
289 1.44 hannken #define BGE_QUIRK_5705_CORE 0x00000080
290 1.54 fvdl #define BGE_QUIRK_FEWER_MBUFS 0x00000100
291 1.25 jonathan
292 1.95 jonathan /*
293 1.95 jonathan * XXX: how to handle variants based on 5750 and derivatives:
294 1.95 jonathan * 5750 5751, 5721, possibly 5714, 5752, and 5708?, which
295 1.95 jonathan * in general behave like a 5705, except with additional quirks.
296 1.95 jonathan * This driver's current handling of the 5721 is wrong;
297 1.95 jonathan * how we map ASIC revision to "quirks" needs more thought.
298 1.95 jonathan * (defined here until the thought is done).
299 1.95 jonathan */
300 1.99 jonathan #define BGE_IS_5714_FAMILY(sc) \
301 1.99 jonathan (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5714 || \
302 1.99 jonathan BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5780 || \
303 1.99 jonathan BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5715 )
304 1.99 jonathan
305 1.95 jonathan #define BGE_IS_5750_OR_BEYOND(sc) \
306 1.99 jonathan (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5750 || \
307 1.99 jonathan BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5752 || \
308 1.99 jonathan BGE_IS_5714_FAMILY(sc) )
309 1.95 jonathan
310 1.95 jonathan #define BGE_IS_5705_OR_BEYOND(sc) \
311 1.95 jonathan ( ((sc)->bge_quirks & BGE_QUIRK_5705_CORE) || \
312 1.95 jonathan BGE_IS_5750_OR_BEYOND(sc) )
313 1.95 jonathan
314 1.95 jonathan
315 1.25 jonathan /* following bugs are common to bcm5700 rev B, all flavours */
316 1.25 jonathan #define BGE_QUIRK_5700_COMMON \
317 1.25 jonathan (BGE_QUIRK_5700_SMALLDMA|BGE_QUIRK_PRODUCER_BUG)
318 1.17 thorpej
319 1.21 thorpej CFATTACH_DECL(bge, sizeof(struct bge_softc),
320 1.22 thorpej bge_probe, bge_attach, NULL, NULL);
321 1.1 fvdl
322 1.1 fvdl u_int32_t
323 1.1 fvdl bge_readmem_ind(sc, off)
324 1.1 fvdl struct bge_softc *sc;
325 1.1 fvdl int off;
326 1.1 fvdl {
327 1.1 fvdl struct pci_attach_args *pa = &(sc->bge_pa);
328 1.1 fvdl pcireg_t val;
329 1.1 fvdl
330 1.1 fvdl pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_MEMWIN_BASEADDR, off);
331 1.1 fvdl val = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_MEMWIN_DATA);
332 1.1 fvdl return val;
333 1.1 fvdl }
334 1.1 fvdl
335 1.1 fvdl void
336 1.1 fvdl bge_writemem_ind(sc, off, val)
337 1.1 fvdl struct bge_softc *sc;
338 1.1 fvdl int off, val;
339 1.1 fvdl {
340 1.1 fvdl struct pci_attach_args *pa = &(sc->bge_pa);
341 1.1 fvdl
342 1.1 fvdl pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_MEMWIN_BASEADDR, off);
343 1.1 fvdl pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_MEMWIN_DATA, val);
344 1.1 fvdl }
345 1.1 fvdl
346 1.1 fvdl #ifdef notdef
347 1.1 fvdl u_int32_t
348 1.1 fvdl bge_readreg_ind(sc, off)
349 1.1 fvdl struct bge_softc *sc;
350 1.1 fvdl int off;
351 1.1 fvdl {
352 1.1 fvdl struct pci_attach_args *pa = &(sc->bge_pa);
353 1.1 fvdl
354 1.1 fvdl pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_REG_BASEADDR, off);
355 1.1 fvdl return(pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_REG_DATA));
356 1.1 fvdl }
357 1.1 fvdl #endif
358 1.1 fvdl
359 1.1 fvdl void
360 1.1 fvdl bge_writereg_ind(sc, off, val)
361 1.1 fvdl struct bge_softc *sc;
362 1.1 fvdl int off, val;
363 1.1 fvdl {
364 1.1 fvdl struct pci_attach_args *pa = &(sc->bge_pa);
365 1.1 fvdl
366 1.1 fvdl pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_REG_BASEADDR, off);
367 1.1 fvdl pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_REG_DATA, val);
368 1.1 fvdl }
369 1.1 fvdl
370 1.1 fvdl #ifdef notdef
371 1.1 fvdl u_int8_t
372 1.1 fvdl bge_vpd_readbyte(sc, addr)
373 1.1 fvdl struct bge_softc *sc;
374 1.1 fvdl int addr;
375 1.1 fvdl {
376 1.1 fvdl int i;
377 1.1 fvdl u_int32_t val;
378 1.1 fvdl struct pci_attach_args *pa = &(sc->bge_pa);
379 1.1 fvdl
380 1.1 fvdl pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_VPD_ADDR, addr);
381 1.1 fvdl for (i = 0; i < BGE_TIMEOUT * 10; i++) {
382 1.1 fvdl DELAY(10);
383 1.1 fvdl if (pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_VPD_ADDR) &
384 1.1 fvdl BGE_VPD_FLAG)
385 1.1 fvdl break;
386 1.1 fvdl }
387 1.1 fvdl
388 1.1 fvdl if (i == BGE_TIMEOUT) {
389 1.1 fvdl printf("%s: VPD read timed out\n", sc->bge_dev.dv_xname);
390 1.1 fvdl return(0);
391 1.1 fvdl }
392 1.1 fvdl
393 1.1 fvdl val = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_VPD_DATA);
394 1.1 fvdl
395 1.1 fvdl return((val >> ((addr % 4) * 8)) & 0xFF);
396 1.1 fvdl }
397 1.1 fvdl
398 1.1 fvdl void
399 1.1 fvdl bge_vpd_read_res(sc, res, addr)
400 1.1 fvdl struct bge_softc *sc;
401 1.1 fvdl struct vpd_res *res;
402 1.1 fvdl int addr;
403 1.1 fvdl {
404 1.1 fvdl int i;
405 1.1 fvdl u_int8_t *ptr;
406 1.1 fvdl
407 1.1 fvdl ptr = (u_int8_t *)res;
408 1.1 fvdl for (i = 0; i < sizeof(struct vpd_res); i++)
409 1.1 fvdl ptr[i] = bge_vpd_readbyte(sc, i + addr);
410 1.1 fvdl }
411 1.1 fvdl
412 1.1 fvdl void
413 1.1 fvdl bge_vpd_read(sc)
414 1.1 fvdl struct bge_softc *sc;
415 1.1 fvdl {
416 1.1 fvdl int pos = 0, i;
417 1.1 fvdl struct vpd_res res;
418 1.1 fvdl
419 1.1 fvdl if (sc->bge_vpd_prodname != NULL)
420 1.1 fvdl free(sc->bge_vpd_prodname, M_DEVBUF);
421 1.1 fvdl if (sc->bge_vpd_readonly != NULL)
422 1.1 fvdl free(sc->bge_vpd_readonly, M_DEVBUF);
423 1.1 fvdl sc->bge_vpd_prodname = NULL;
424 1.1 fvdl sc->bge_vpd_readonly = NULL;
425 1.1 fvdl
426 1.1 fvdl bge_vpd_read_res(sc, &res, pos);
427 1.1 fvdl
428 1.1 fvdl if (res.vr_id != VPD_RES_ID) {
429 1.1 fvdl printf("%s: bad VPD resource id: expected %x got %x\n",
430 1.1 fvdl sc->bge_dev.dv_xname, VPD_RES_ID, res.vr_id);
431 1.1 fvdl return;
432 1.1 fvdl }
433 1.1 fvdl
434 1.1 fvdl pos += sizeof(res);
435 1.1 fvdl sc->bge_vpd_prodname = malloc(res.vr_len + 1, M_DEVBUF, M_NOWAIT);
436 1.1 fvdl if (sc->bge_vpd_prodname == NULL)
437 1.1 fvdl panic("bge_vpd_read");
438 1.1 fvdl for (i = 0; i < res.vr_len; i++)
439 1.1 fvdl sc->bge_vpd_prodname[i] = bge_vpd_readbyte(sc, i + pos);
440 1.1 fvdl sc->bge_vpd_prodname[i] = '\0';
441 1.1 fvdl pos += i;
442 1.1 fvdl
443 1.1 fvdl bge_vpd_read_res(sc, &res, pos);
444 1.1 fvdl
445 1.1 fvdl if (res.vr_id != VPD_RES_READ) {
446 1.1 fvdl printf("%s: bad VPD resource id: expected %x got %x\n",
447 1.1 fvdl sc->bge_dev.dv_xname, VPD_RES_READ, res.vr_id);
448 1.1 fvdl return;
449 1.1 fvdl }
450 1.1 fvdl
451 1.1 fvdl pos += sizeof(res);
452 1.1 fvdl sc->bge_vpd_readonly = malloc(res.vr_len, M_DEVBUF, M_NOWAIT);
453 1.1 fvdl if (sc->bge_vpd_readonly == NULL)
454 1.1 fvdl panic("bge_vpd_read");
455 1.1 fvdl for (i = 0; i < res.vr_len + 1; i++)
456 1.1 fvdl sc->bge_vpd_readonly[i] = bge_vpd_readbyte(sc, i + pos);
457 1.1 fvdl }
458 1.1 fvdl #endif
459 1.1 fvdl
460 1.1 fvdl /*
461 1.1 fvdl * Read a byte of data stored in the EEPROM at address 'addr.' The
462 1.1 fvdl * BCM570x supports both the traditional bitbang interface and an
463 1.1 fvdl * auto access interface for reading the EEPROM. We use the auto
464 1.1 fvdl * access method.
465 1.1 fvdl */
466 1.1 fvdl u_int8_t
467 1.1 fvdl bge_eeprom_getbyte(sc, addr, dest)
468 1.1 fvdl struct bge_softc *sc;
469 1.1 fvdl int addr;
470 1.1 fvdl u_int8_t *dest;
471 1.1 fvdl {
472 1.1 fvdl int i;
473 1.1 fvdl u_int32_t byte = 0;
474 1.1 fvdl
475 1.1 fvdl /*
476 1.1 fvdl * Enable use of auto EEPROM access so we can avoid
477 1.1 fvdl * having to use the bitbang method.
478 1.1 fvdl */
479 1.1 fvdl BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM);
480 1.1 fvdl
481 1.1 fvdl /* Reset the EEPROM, load the clock period. */
482 1.1 fvdl CSR_WRITE_4(sc, BGE_EE_ADDR,
483 1.1 fvdl BGE_EEADDR_RESET|BGE_EEHALFCLK(BGE_HALFCLK_384SCL));
484 1.1 fvdl DELAY(20);
485 1.1 fvdl
486 1.1 fvdl /* Issue the read EEPROM command. */
487 1.1 fvdl CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr);
488 1.1 fvdl
489 1.1 fvdl /* Wait for completion */
490 1.1 fvdl for(i = 0; i < BGE_TIMEOUT * 10; i++) {
491 1.1 fvdl DELAY(10);
492 1.1 fvdl if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE)
493 1.1 fvdl break;
494 1.1 fvdl }
495 1.1 fvdl
496 1.1 fvdl if (i == BGE_TIMEOUT) {
497 1.1 fvdl printf("%s: eeprom read timed out\n", sc->bge_dev.dv_xname);
498 1.1 fvdl return(0);
499 1.1 fvdl }
500 1.1 fvdl
501 1.1 fvdl /* Get result. */
502 1.1 fvdl byte = CSR_READ_4(sc, BGE_EE_DATA);
503 1.1 fvdl
504 1.1 fvdl *dest = (byte >> ((addr % 4) * 8)) & 0xFF;
505 1.1 fvdl
506 1.1 fvdl return(0);
507 1.1 fvdl }
508 1.1 fvdl
509 1.1 fvdl /*
510 1.1 fvdl * Read a sequence of bytes from the EEPROM.
511 1.1 fvdl */
512 1.1 fvdl int
513 1.1 fvdl bge_read_eeprom(sc, dest, off, cnt)
514 1.1 fvdl struct bge_softc *sc;
515 1.1 fvdl caddr_t dest;
516 1.1 fvdl int off;
517 1.1 fvdl int cnt;
518 1.1 fvdl {
519 1.1 fvdl int err = 0, i;
520 1.1 fvdl u_int8_t byte = 0;
521 1.1 fvdl
522 1.1 fvdl for (i = 0; i < cnt; i++) {
523 1.1 fvdl err = bge_eeprom_getbyte(sc, off + i, &byte);
524 1.1 fvdl if (err)
525 1.1 fvdl break;
526 1.1 fvdl *(dest + i) = byte;
527 1.1 fvdl }
528 1.1 fvdl
529 1.1 fvdl return(err ? 1 : 0);
530 1.1 fvdl }
531 1.1 fvdl
532 1.1 fvdl int
533 1.1 fvdl bge_miibus_readreg(dev, phy, reg)
534 1.1 fvdl struct device *dev;
535 1.1 fvdl int phy, reg;
536 1.1 fvdl {
537 1.1 fvdl struct bge_softc *sc = (struct bge_softc *)dev;
538 1.1 fvdl u_int32_t val;
539 1.25 jonathan u_int32_t saved_autopoll;
540 1.1 fvdl int i;
541 1.1 fvdl
542 1.25 jonathan /*
543 1.25 jonathan * Several chips with builtin PHYs will incorrectly answer to
544 1.25 jonathan * other PHY instances than the builtin PHY at id 1.
545 1.25 jonathan */
546 1.24 matt if (phy != 1 && (sc->bge_quirks & BGE_QUIRK_ONLY_PHY_1))
547 1.1 fvdl return(0);
548 1.1 fvdl
549 1.25 jonathan /* Reading with autopolling on may trigger PCI errors */
550 1.25 jonathan saved_autopoll = CSR_READ_4(sc, BGE_MI_MODE);
551 1.25 jonathan if (saved_autopoll & BGE_MIMODE_AUTOPOLL) {
552 1.25 jonathan CSR_WRITE_4(sc, BGE_MI_MODE,
553 1.29 itojun saved_autopoll &~ BGE_MIMODE_AUTOPOLL);
554 1.25 jonathan DELAY(40);
555 1.25 jonathan }
556 1.25 jonathan
557 1.1 fvdl CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_READ|BGE_MICOMM_BUSY|
558 1.1 fvdl BGE_MIPHY(phy)|BGE_MIREG(reg));
559 1.1 fvdl
560 1.1 fvdl for (i = 0; i < BGE_TIMEOUT; i++) {
561 1.1 fvdl val = CSR_READ_4(sc, BGE_MI_COMM);
562 1.1 fvdl if (!(val & BGE_MICOMM_BUSY))
563 1.1 fvdl break;
564 1.9 thorpej delay(10);
565 1.1 fvdl }
566 1.1 fvdl
567 1.1 fvdl if (i == BGE_TIMEOUT) {
568 1.1 fvdl printf("%s: PHY read timed out\n", sc->bge_dev.dv_xname);
569 1.29 itojun val = 0;
570 1.25 jonathan goto done;
571 1.1 fvdl }
572 1.1 fvdl
573 1.1 fvdl val = CSR_READ_4(sc, BGE_MI_COMM);
574 1.1 fvdl
575 1.25 jonathan done:
576 1.25 jonathan if (saved_autopoll & BGE_MIMODE_AUTOPOLL) {
577 1.25 jonathan CSR_WRITE_4(sc, BGE_MI_MODE, saved_autopoll);
578 1.25 jonathan DELAY(40);
579 1.25 jonathan }
580 1.29 itojun
581 1.1 fvdl if (val & BGE_MICOMM_READFAIL)
582 1.1 fvdl return(0);
583 1.1 fvdl
584 1.1 fvdl return(val & 0xFFFF);
585 1.1 fvdl }
586 1.1 fvdl
587 1.1 fvdl void
588 1.1 fvdl bge_miibus_writereg(dev, phy, reg, val)
589 1.1 fvdl struct device *dev;
590 1.1 fvdl int phy, reg, val;
591 1.1 fvdl {
592 1.1 fvdl struct bge_softc *sc = (struct bge_softc *)dev;
593 1.29 itojun u_int32_t saved_autopoll;
594 1.29 itojun int i;
595 1.1 fvdl
596 1.29 itojun /* Touching the PHY while autopolling is on may trigger PCI errors */
597 1.25 jonathan saved_autopoll = CSR_READ_4(sc, BGE_MI_MODE);
598 1.25 jonathan if (saved_autopoll & BGE_MIMODE_AUTOPOLL) {
599 1.25 jonathan delay(40);
600 1.25 jonathan CSR_WRITE_4(sc, BGE_MI_MODE,
601 1.25 jonathan saved_autopoll & (~BGE_MIMODE_AUTOPOLL));
602 1.25 jonathan delay(10); /* 40 usec is supposed to be adequate */
603 1.25 jonathan }
604 1.29 itojun
605 1.1 fvdl CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_WRITE|BGE_MICOMM_BUSY|
606 1.1 fvdl BGE_MIPHY(phy)|BGE_MIREG(reg)|val);
607 1.1 fvdl
608 1.1 fvdl for (i = 0; i < BGE_TIMEOUT; i++) {
609 1.1 fvdl if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY))
610 1.1 fvdl break;
611 1.9 thorpej delay(10);
612 1.1 fvdl }
613 1.1 fvdl
614 1.25 jonathan if (saved_autopoll & BGE_MIMODE_AUTOPOLL) {
615 1.25 jonathan CSR_WRITE_4(sc, BGE_MI_MODE, saved_autopoll);
616 1.25 jonathan delay(40);
617 1.25 jonathan }
618 1.29 itojun
619 1.1 fvdl if (i == BGE_TIMEOUT) {
620 1.1 fvdl printf("%s: PHY read timed out\n", sc->bge_dev.dv_xname);
621 1.1 fvdl }
622 1.1 fvdl }
623 1.1 fvdl
624 1.1 fvdl void
625 1.1 fvdl bge_miibus_statchg(dev)
626 1.1 fvdl struct device *dev;
627 1.1 fvdl {
628 1.1 fvdl struct bge_softc *sc = (struct bge_softc *)dev;
629 1.1 fvdl struct mii_data *mii = &sc->bge_mii;
630 1.1 fvdl
631 1.69 thorpej /*
632 1.69 thorpej * Get flow control negotiation result.
633 1.69 thorpej */
634 1.69 thorpej if (IFM_SUBTYPE(mii->mii_media.ifm_cur->ifm_media) == IFM_AUTO &&
635 1.69 thorpej (mii->mii_media_active & IFM_ETH_FMASK) != sc->bge_flowflags) {
636 1.69 thorpej sc->bge_flowflags = mii->mii_media_active & IFM_ETH_FMASK;
637 1.69 thorpej mii->mii_media_active &= ~IFM_ETH_FMASK;
638 1.69 thorpej }
639 1.69 thorpej
640 1.1 fvdl BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_PORTMODE);
641 1.1 fvdl if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) {
642 1.1 fvdl BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_GMII);
643 1.1 fvdl } else {
644 1.1 fvdl BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_MII);
645 1.1 fvdl }
646 1.1 fvdl
647 1.1 fvdl if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
648 1.1 fvdl BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX);
649 1.1 fvdl } else {
650 1.1 fvdl BGE_SETBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX);
651 1.1 fvdl }
652 1.69 thorpej
653 1.69 thorpej /*
654 1.69 thorpej * 802.3x flow control
655 1.69 thorpej */
656 1.69 thorpej if (sc->bge_flowflags & IFM_ETH_RXPAUSE) {
657 1.69 thorpej BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_FLOWCTL_ENABLE);
658 1.69 thorpej } else {
659 1.69 thorpej BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_FLOWCTL_ENABLE);
660 1.69 thorpej }
661 1.69 thorpej if (sc->bge_flowflags & IFM_ETH_TXPAUSE) {
662 1.69 thorpej BGE_SETBIT(sc, BGE_TX_MODE, BGE_TXMODE_FLOWCTL_ENABLE);
663 1.69 thorpej } else {
664 1.69 thorpej BGE_CLRBIT(sc, BGE_TX_MODE, BGE_TXMODE_FLOWCTL_ENABLE);
665 1.69 thorpej }
666 1.1 fvdl }
667 1.1 fvdl
668 1.1 fvdl /*
669 1.63 jonathan * Update rx threshold levels to values in a particular slot
670 1.63 jonathan * of the interrupt-mitigation table bge_rx_threshes.
671 1.63 jonathan */
672 1.63 jonathan void
673 1.63 jonathan bge_set_thresh(struct ifnet *ifp, int lvl)
674 1.63 jonathan {
675 1.63 jonathan struct bge_softc *sc = ifp->if_softc;
676 1.63 jonathan int s;
677 1.63 jonathan
678 1.63 jonathan /* For now, just save the new Rx-intr thresholds and record
679 1.63 jonathan * that a threshold update is pending. Updating the hardware
680 1.63 jonathan * registers here (even at splhigh()) is observed to
681 1.63 jonathan * occasionaly cause glitches where Rx-interrupts are not
682 1.68 keihan * honoured for up to 10 seconds. jonathan (at) NetBSD.org, 2003-04-05
683 1.63 jonathan */
684 1.63 jonathan s = splnet();
685 1.63 jonathan sc->bge_rx_coal_ticks = bge_rx_threshes[lvl].rx_ticks;
686 1.63 jonathan sc->bge_rx_max_coal_bds = bge_rx_threshes[lvl].rx_max_bds;
687 1.63 jonathan sc->bge_pending_rxintr_change = 1;
688 1.63 jonathan splx(s);
689 1.63 jonathan
690 1.63 jonathan return;
691 1.63 jonathan }
692 1.63 jonathan
693 1.63 jonathan
694 1.63 jonathan /*
695 1.63 jonathan * Update Rx thresholds of all bge devices
696 1.63 jonathan */
697 1.63 jonathan void
698 1.63 jonathan bge_update_all_threshes(int lvl)
699 1.63 jonathan {
700 1.63 jonathan struct ifnet *ifp;
701 1.63 jonathan const char * const namebuf = "bge";
702 1.63 jonathan int namelen;
703 1.63 jonathan
704 1.63 jonathan if (lvl < 0)
705 1.63 jonathan lvl = 0;
706 1.63 jonathan else if( lvl >= NBGE_RX_THRESH)
707 1.63 jonathan lvl = NBGE_RX_THRESH - 1;
708 1.87 perry
709 1.63 jonathan namelen = strlen(namebuf);
710 1.63 jonathan /*
711 1.63 jonathan * Now search all the interfaces for this name/number
712 1.63 jonathan */
713 1.81 matt IFNET_FOREACH(ifp) {
714 1.67 jonathan if (strncmp(ifp->if_xname, namebuf, namelen) != 0)
715 1.63 jonathan continue;
716 1.63 jonathan /* We got a match: update if doing auto-threshold-tuning */
717 1.63 jonathan if (bge_auto_thresh)
718 1.67 jonathan bge_set_thresh(ifp, lvl);
719 1.63 jonathan }
720 1.63 jonathan }
721 1.63 jonathan
722 1.63 jonathan /*
723 1.1 fvdl * Handle events that have triggered interrupts.
724 1.1 fvdl */
725 1.1 fvdl void
726 1.1 fvdl bge_handle_events(sc)
727 1.1 fvdl struct bge_softc *sc;
728 1.1 fvdl {
729 1.1 fvdl
730 1.1 fvdl return;
731 1.1 fvdl }
732 1.1 fvdl
733 1.1 fvdl /*
734 1.1 fvdl * Memory management for jumbo frames.
735 1.1 fvdl */
736 1.1 fvdl
737 1.1 fvdl int
738 1.1 fvdl bge_alloc_jumbo_mem(sc)
739 1.1 fvdl struct bge_softc *sc;
740 1.1 fvdl {
741 1.1 fvdl caddr_t ptr, kva;
742 1.1 fvdl bus_dma_segment_t seg;
743 1.1 fvdl int i, rseg, state, error;
744 1.1 fvdl struct bge_jpool_entry *entry;
745 1.1 fvdl
746 1.1 fvdl state = error = 0;
747 1.1 fvdl
748 1.1 fvdl /* Grab a big chunk o' storage. */
749 1.1 fvdl if (bus_dmamem_alloc(sc->bge_dmatag, BGE_JMEM, PAGE_SIZE, 0,
750 1.1 fvdl &seg, 1, &rseg, BUS_DMA_NOWAIT)) {
751 1.1 fvdl printf("%s: can't alloc rx buffers\n", sc->bge_dev.dv_xname);
752 1.1 fvdl return ENOBUFS;
753 1.1 fvdl }
754 1.1 fvdl
755 1.1 fvdl state = 1;
756 1.1 fvdl if (bus_dmamem_map(sc->bge_dmatag, &seg, rseg, BGE_JMEM, &kva,
757 1.1 fvdl BUS_DMA_NOWAIT)) {
758 1.39 wiz printf("%s: can't map DMA buffers (%d bytes)\n",
759 1.1 fvdl sc->bge_dev.dv_xname, (int)BGE_JMEM);
760 1.1 fvdl error = ENOBUFS;
761 1.1 fvdl goto out;
762 1.1 fvdl }
763 1.1 fvdl
764 1.1 fvdl state = 2;
765 1.1 fvdl if (bus_dmamap_create(sc->bge_dmatag, BGE_JMEM, 1, BGE_JMEM, 0,
766 1.1 fvdl BUS_DMA_NOWAIT, &sc->bge_cdata.bge_rx_jumbo_map)) {
767 1.39 wiz printf("%s: can't create DMA map\n", sc->bge_dev.dv_xname);
768 1.1 fvdl error = ENOBUFS;
769 1.1 fvdl goto out;
770 1.1 fvdl }
771 1.1 fvdl
772 1.1 fvdl state = 3;
773 1.1 fvdl if (bus_dmamap_load(sc->bge_dmatag, sc->bge_cdata.bge_rx_jumbo_map,
774 1.1 fvdl kva, BGE_JMEM, NULL, BUS_DMA_NOWAIT)) {
775 1.39 wiz printf("%s: can't load DMA map\n", sc->bge_dev.dv_xname);
776 1.1 fvdl error = ENOBUFS;
777 1.1 fvdl goto out;
778 1.1 fvdl }
779 1.1 fvdl
780 1.1 fvdl state = 4;
781 1.1 fvdl sc->bge_cdata.bge_jumbo_buf = (caddr_t)kva;
782 1.89 christos DPRINTFN(1,("bge_jumbo_buf = %p\n", sc->bge_cdata.bge_jumbo_buf));
783 1.1 fvdl
784 1.1 fvdl SLIST_INIT(&sc->bge_jfree_listhead);
785 1.1 fvdl SLIST_INIT(&sc->bge_jinuse_listhead);
786 1.1 fvdl
787 1.1 fvdl /*
788 1.1 fvdl * Now divide it up into 9K pieces and save the addresses
789 1.1 fvdl * in an array.
790 1.1 fvdl */
791 1.1 fvdl ptr = sc->bge_cdata.bge_jumbo_buf;
792 1.1 fvdl for (i = 0; i < BGE_JSLOTS; i++) {
793 1.1 fvdl sc->bge_cdata.bge_jslots[i] = ptr;
794 1.1 fvdl ptr += BGE_JLEN;
795 1.1 fvdl entry = malloc(sizeof(struct bge_jpool_entry),
796 1.1 fvdl M_DEVBUF, M_NOWAIT);
797 1.1 fvdl if (entry == NULL) {
798 1.1 fvdl printf("%s: no memory for jumbo buffer queue!\n",
799 1.1 fvdl sc->bge_dev.dv_xname);
800 1.1 fvdl error = ENOBUFS;
801 1.1 fvdl goto out;
802 1.1 fvdl }
803 1.1 fvdl entry->slot = i;
804 1.1 fvdl SLIST_INSERT_HEAD(&sc->bge_jfree_listhead,
805 1.1 fvdl entry, jpool_entries);
806 1.1 fvdl }
807 1.1 fvdl out:
808 1.1 fvdl if (error != 0) {
809 1.1 fvdl switch (state) {
810 1.1 fvdl case 4:
811 1.1 fvdl bus_dmamap_unload(sc->bge_dmatag,
812 1.1 fvdl sc->bge_cdata.bge_rx_jumbo_map);
813 1.1 fvdl case 3:
814 1.1 fvdl bus_dmamap_destroy(sc->bge_dmatag,
815 1.1 fvdl sc->bge_cdata.bge_rx_jumbo_map);
816 1.1 fvdl case 2:
817 1.1 fvdl bus_dmamem_unmap(sc->bge_dmatag, kva, BGE_JMEM);
818 1.1 fvdl case 1:
819 1.1 fvdl bus_dmamem_free(sc->bge_dmatag, &seg, rseg);
820 1.1 fvdl break;
821 1.1 fvdl default:
822 1.1 fvdl break;
823 1.1 fvdl }
824 1.1 fvdl }
825 1.1 fvdl
826 1.1 fvdl return error;
827 1.1 fvdl }
828 1.1 fvdl
829 1.1 fvdl /*
830 1.1 fvdl * Allocate a jumbo buffer.
831 1.1 fvdl */
832 1.1 fvdl void *
833 1.1 fvdl bge_jalloc(sc)
834 1.1 fvdl struct bge_softc *sc;
835 1.1 fvdl {
836 1.1 fvdl struct bge_jpool_entry *entry;
837 1.1 fvdl
838 1.1 fvdl entry = SLIST_FIRST(&sc->bge_jfree_listhead);
839 1.1 fvdl
840 1.1 fvdl if (entry == NULL) {
841 1.1 fvdl printf("%s: no free jumbo buffers\n", sc->bge_dev.dv_xname);
842 1.1 fvdl return(NULL);
843 1.1 fvdl }
844 1.1 fvdl
845 1.1 fvdl SLIST_REMOVE_HEAD(&sc->bge_jfree_listhead, jpool_entries);
846 1.1 fvdl SLIST_INSERT_HEAD(&sc->bge_jinuse_listhead, entry, jpool_entries);
847 1.1 fvdl return(sc->bge_cdata.bge_jslots[entry->slot]);
848 1.1 fvdl }
849 1.1 fvdl
850 1.1 fvdl /*
851 1.1 fvdl * Release a jumbo buffer.
852 1.1 fvdl */
853 1.1 fvdl void
854 1.1 fvdl bge_jfree(m, buf, size, arg)
855 1.1 fvdl struct mbuf *m;
856 1.1 fvdl caddr_t buf;
857 1.31 thorpej size_t size;
858 1.1 fvdl void *arg;
859 1.1 fvdl {
860 1.1 fvdl struct bge_jpool_entry *entry;
861 1.1 fvdl struct bge_softc *sc;
862 1.1 fvdl int i, s;
863 1.1 fvdl
864 1.1 fvdl /* Extract the softc struct pointer. */
865 1.1 fvdl sc = (struct bge_softc *)arg;
866 1.1 fvdl
867 1.1 fvdl if (sc == NULL)
868 1.1 fvdl panic("bge_jfree: can't find softc pointer!");
869 1.1 fvdl
870 1.1 fvdl /* calculate the slot this buffer belongs to */
871 1.1 fvdl
872 1.1 fvdl i = ((caddr_t)buf
873 1.1 fvdl - (caddr_t)sc->bge_cdata.bge_jumbo_buf) / BGE_JLEN;
874 1.1 fvdl
875 1.1 fvdl if ((i < 0) || (i >= BGE_JSLOTS))
876 1.1 fvdl panic("bge_jfree: asked to free buffer that we don't manage!");
877 1.1 fvdl
878 1.1 fvdl s = splvm();
879 1.1 fvdl entry = SLIST_FIRST(&sc->bge_jinuse_listhead);
880 1.1 fvdl if (entry == NULL)
881 1.1 fvdl panic("bge_jfree: buffer not in use!");
882 1.1 fvdl entry->slot = i;
883 1.1 fvdl SLIST_REMOVE_HEAD(&sc->bge_jinuse_listhead, jpool_entries);
884 1.1 fvdl SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, entry, jpool_entries);
885 1.1 fvdl
886 1.1 fvdl if (__predict_true(m != NULL))
887 1.1 fvdl pool_cache_put(&mbpool_cache, m);
888 1.1 fvdl splx(s);
889 1.1 fvdl }
890 1.1 fvdl
891 1.1 fvdl
892 1.1 fvdl /*
893 1.1 fvdl * Intialize a standard receive ring descriptor.
894 1.1 fvdl */
895 1.1 fvdl int
896 1.1 fvdl bge_newbuf_std(sc, i, m, dmamap)
897 1.1 fvdl struct bge_softc *sc;
898 1.1 fvdl int i;
899 1.1 fvdl struct mbuf *m;
900 1.1 fvdl bus_dmamap_t dmamap;
901 1.1 fvdl {
902 1.1 fvdl struct mbuf *m_new = NULL;
903 1.1 fvdl struct bge_rx_bd *r;
904 1.1 fvdl int error;
905 1.1 fvdl
906 1.1 fvdl if (dmamap == NULL) {
907 1.1 fvdl error = bus_dmamap_create(sc->bge_dmatag, MCLBYTES, 1,
908 1.1 fvdl MCLBYTES, 0, BUS_DMA_NOWAIT, &dmamap);
909 1.1 fvdl if (error != 0)
910 1.1 fvdl return error;
911 1.1 fvdl }
912 1.1 fvdl
913 1.1 fvdl sc->bge_cdata.bge_rx_std_map[i] = dmamap;
914 1.1 fvdl
915 1.1 fvdl if (m == NULL) {
916 1.1 fvdl MGETHDR(m_new, M_DONTWAIT, MT_DATA);
917 1.1 fvdl if (m_new == NULL) {
918 1.1 fvdl return(ENOBUFS);
919 1.1 fvdl }
920 1.1 fvdl
921 1.1 fvdl MCLGET(m_new, M_DONTWAIT);
922 1.1 fvdl if (!(m_new->m_flags & M_EXT)) {
923 1.1 fvdl m_freem(m_new);
924 1.1 fvdl return(ENOBUFS);
925 1.1 fvdl }
926 1.1 fvdl m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
927 1.37 jonathan if (!sc->bge_rx_alignment_bug)
928 1.37 jonathan m_adj(m_new, ETHER_ALIGN);
929 1.1 fvdl
930 1.1 fvdl if (bus_dmamap_load_mbuf(sc->bge_dmatag, dmamap, m_new,
931 1.1 fvdl BUS_DMA_READ|BUS_DMA_NOWAIT))
932 1.1 fvdl return(ENOBUFS);
933 1.1 fvdl } else {
934 1.1 fvdl m_new = m;
935 1.1 fvdl m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
936 1.1 fvdl m_new->m_data = m_new->m_ext.ext_buf;
937 1.37 jonathan if (!sc->bge_rx_alignment_bug)
938 1.37 jonathan m_adj(m_new, ETHER_ALIGN);
939 1.1 fvdl }
940 1.1 fvdl
941 1.1 fvdl sc->bge_cdata.bge_rx_std_chain[i] = m_new;
942 1.1 fvdl r = &sc->bge_rdata->bge_rx_std_ring[i];
943 1.1 fvdl bge_set_hostaddr(&r->bge_addr,
944 1.10 fvdl dmamap->dm_segs[0].ds_addr);
945 1.1 fvdl r->bge_flags = BGE_RXBDFLAG_END;
946 1.1 fvdl r->bge_len = m_new->m_len;
947 1.1 fvdl r->bge_idx = i;
948 1.1 fvdl
949 1.1 fvdl bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map,
950 1.1 fvdl offsetof(struct bge_ring_data, bge_rx_std_ring) +
951 1.1 fvdl i * sizeof (struct bge_rx_bd),
952 1.1 fvdl sizeof (struct bge_rx_bd),
953 1.1 fvdl BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD);
954 1.1 fvdl
955 1.1 fvdl return(0);
956 1.1 fvdl }
957 1.1 fvdl
958 1.1 fvdl /*
959 1.1 fvdl * Initialize a jumbo receive ring descriptor. This allocates
960 1.1 fvdl * a jumbo buffer from the pool managed internally by the driver.
961 1.1 fvdl */
962 1.1 fvdl int
963 1.1 fvdl bge_newbuf_jumbo(sc, i, m)
964 1.1 fvdl struct bge_softc *sc;
965 1.1 fvdl int i;
966 1.1 fvdl struct mbuf *m;
967 1.1 fvdl {
968 1.1 fvdl struct mbuf *m_new = NULL;
969 1.1 fvdl struct bge_rx_bd *r;
970 1.1 fvdl
971 1.1 fvdl if (m == NULL) {
972 1.75 yamt caddr_t buf = NULL;
973 1.1 fvdl
974 1.1 fvdl /* Allocate the mbuf. */
975 1.1 fvdl MGETHDR(m_new, M_DONTWAIT, MT_DATA);
976 1.1 fvdl if (m_new == NULL) {
977 1.1 fvdl return(ENOBUFS);
978 1.1 fvdl }
979 1.1 fvdl
980 1.1 fvdl /* Allocate the jumbo buffer */
981 1.1 fvdl buf = bge_jalloc(sc);
982 1.1 fvdl if (buf == NULL) {
983 1.1 fvdl m_freem(m_new);
984 1.1 fvdl printf("%s: jumbo allocation failed "
985 1.1 fvdl "-- packet dropped!\n", sc->bge_dev.dv_xname);
986 1.1 fvdl return(ENOBUFS);
987 1.1 fvdl }
988 1.1 fvdl
989 1.1 fvdl /* Attach the buffer to the mbuf. */
990 1.1 fvdl m_new->m_len = m_new->m_pkthdr.len = BGE_JUMBO_FRAMELEN;
991 1.1 fvdl MEXTADD(m_new, buf, BGE_JUMBO_FRAMELEN, M_DEVBUF,
992 1.1 fvdl bge_jfree, sc);
993 1.74 yamt m_new->m_flags |= M_EXT_RW;
994 1.1 fvdl } else {
995 1.1 fvdl m_new = m;
996 1.1 fvdl m_new->m_data = m_new->m_ext.ext_buf;
997 1.1 fvdl m_new->m_ext.ext_size = BGE_JUMBO_FRAMELEN;
998 1.1 fvdl }
999 1.1 fvdl
1000 1.37 jonathan if (!sc->bge_rx_alignment_bug)
1001 1.37 jonathan m_adj(m_new, ETHER_ALIGN);
1002 1.1 fvdl /* Set up the descriptor. */
1003 1.1 fvdl r = &sc->bge_rdata->bge_rx_jumbo_ring[i];
1004 1.1 fvdl sc->bge_cdata.bge_rx_jumbo_chain[i] = m_new;
1005 1.1 fvdl bge_set_hostaddr(&r->bge_addr, BGE_JUMBO_DMA_ADDR(sc, m_new));
1006 1.1 fvdl r->bge_flags = BGE_RXBDFLAG_END|BGE_RXBDFLAG_JUMBO_RING;
1007 1.1 fvdl r->bge_len = m_new->m_len;
1008 1.1 fvdl r->bge_idx = i;
1009 1.1 fvdl
1010 1.1 fvdl bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map,
1011 1.1 fvdl offsetof(struct bge_ring_data, bge_rx_jumbo_ring) +
1012 1.1 fvdl i * sizeof (struct bge_rx_bd),
1013 1.1 fvdl sizeof (struct bge_rx_bd),
1014 1.1 fvdl BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD);
1015 1.1 fvdl
1016 1.1 fvdl return(0);
1017 1.1 fvdl }
1018 1.1 fvdl
1019 1.1 fvdl /*
1020 1.1 fvdl * The standard receive ring has 512 entries in it. At 2K per mbuf cluster,
1021 1.1 fvdl * that's 1MB or memory, which is a lot. For now, we fill only the first
1022 1.1 fvdl * 256 ring entries and hope that our CPU is fast enough to keep up with
1023 1.1 fvdl * the NIC.
1024 1.1 fvdl */
1025 1.1 fvdl int
1026 1.1 fvdl bge_init_rx_ring_std(sc)
1027 1.1 fvdl struct bge_softc *sc;
1028 1.1 fvdl {
1029 1.1 fvdl int i;
1030 1.1 fvdl
1031 1.1 fvdl if (sc->bge_flags & BGE_RXRING_VALID)
1032 1.1 fvdl return 0;
1033 1.1 fvdl
1034 1.1 fvdl for (i = 0; i < BGE_SSLOTS; i++) {
1035 1.1 fvdl if (bge_newbuf_std(sc, i, NULL, 0) == ENOBUFS)
1036 1.1 fvdl return(ENOBUFS);
1037 1.1 fvdl }
1038 1.1 fvdl
1039 1.1 fvdl sc->bge_std = i - 1;
1040 1.1 fvdl CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std);
1041 1.1 fvdl
1042 1.1 fvdl sc->bge_flags |= BGE_RXRING_VALID;
1043 1.1 fvdl
1044 1.1 fvdl return(0);
1045 1.1 fvdl }
1046 1.1 fvdl
1047 1.1 fvdl void
1048 1.1 fvdl bge_free_rx_ring_std(sc)
1049 1.1 fvdl struct bge_softc *sc;
1050 1.1 fvdl {
1051 1.1 fvdl int i;
1052 1.1 fvdl
1053 1.1 fvdl if (!(sc->bge_flags & BGE_RXRING_VALID))
1054 1.1 fvdl return;
1055 1.1 fvdl
1056 1.1 fvdl for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
1057 1.1 fvdl if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) {
1058 1.1 fvdl m_freem(sc->bge_cdata.bge_rx_std_chain[i]);
1059 1.1 fvdl sc->bge_cdata.bge_rx_std_chain[i] = NULL;
1060 1.87 perry bus_dmamap_destroy(sc->bge_dmatag,
1061 1.1 fvdl sc->bge_cdata.bge_rx_std_map[i]);
1062 1.1 fvdl }
1063 1.1 fvdl memset((char *)&sc->bge_rdata->bge_rx_std_ring[i], 0,
1064 1.1 fvdl sizeof(struct bge_rx_bd));
1065 1.1 fvdl }
1066 1.1 fvdl
1067 1.1 fvdl sc->bge_flags &= ~BGE_RXRING_VALID;
1068 1.1 fvdl }
1069 1.1 fvdl
1070 1.1 fvdl int
1071 1.1 fvdl bge_init_rx_ring_jumbo(sc)
1072 1.1 fvdl struct bge_softc *sc;
1073 1.1 fvdl {
1074 1.1 fvdl int i;
1075 1.34 jonathan volatile struct bge_rcb *rcb;
1076 1.1 fvdl
1077 1.59 martin if (sc->bge_flags & BGE_JUMBO_RXRING_VALID)
1078 1.59 martin return 0;
1079 1.59 martin
1080 1.1 fvdl for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
1081 1.1 fvdl if (bge_newbuf_jumbo(sc, i, NULL) == ENOBUFS)
1082 1.1 fvdl return(ENOBUFS);
1083 1.1 fvdl };
1084 1.1 fvdl
1085 1.1 fvdl sc->bge_jumbo = i - 1;
1086 1.59 martin sc->bge_flags |= BGE_JUMBO_RXRING_VALID;
1087 1.1 fvdl
1088 1.1 fvdl rcb = &sc->bge_rdata->bge_info.bge_jumbo_rx_rcb;
1089 1.34 jonathan rcb->bge_maxlen_flags = 0;
1090 1.34 jonathan CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags);
1091 1.1 fvdl
1092 1.1 fvdl CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo);
1093 1.1 fvdl
1094 1.1 fvdl return(0);
1095 1.1 fvdl }
1096 1.1 fvdl
1097 1.1 fvdl void
1098 1.1 fvdl bge_free_rx_ring_jumbo(sc)
1099 1.1 fvdl struct bge_softc *sc;
1100 1.1 fvdl {
1101 1.1 fvdl int i;
1102 1.1 fvdl
1103 1.1 fvdl if (!(sc->bge_flags & BGE_JUMBO_RXRING_VALID))
1104 1.1 fvdl return;
1105 1.1 fvdl
1106 1.1 fvdl for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
1107 1.1 fvdl if (sc->bge_cdata.bge_rx_jumbo_chain[i] != NULL) {
1108 1.1 fvdl m_freem(sc->bge_cdata.bge_rx_jumbo_chain[i]);
1109 1.1 fvdl sc->bge_cdata.bge_rx_jumbo_chain[i] = NULL;
1110 1.1 fvdl }
1111 1.1 fvdl memset((char *)&sc->bge_rdata->bge_rx_jumbo_ring[i], 0,
1112 1.1 fvdl sizeof(struct bge_rx_bd));
1113 1.1 fvdl }
1114 1.1 fvdl
1115 1.1 fvdl sc->bge_flags &= ~BGE_JUMBO_RXRING_VALID;
1116 1.1 fvdl }
1117 1.1 fvdl
1118 1.1 fvdl void
1119 1.1 fvdl bge_free_tx_ring(sc)
1120 1.1 fvdl struct bge_softc *sc;
1121 1.1 fvdl {
1122 1.1 fvdl int i, freed;
1123 1.1 fvdl struct txdmamap_pool_entry *dma;
1124 1.1 fvdl
1125 1.1 fvdl if (!(sc->bge_flags & BGE_TXRING_VALID))
1126 1.1 fvdl return;
1127 1.1 fvdl
1128 1.1 fvdl freed = 0;
1129 1.1 fvdl
1130 1.1 fvdl for (i = 0; i < BGE_TX_RING_CNT; i++) {
1131 1.1 fvdl if (sc->bge_cdata.bge_tx_chain[i] != NULL) {
1132 1.1 fvdl freed++;
1133 1.1 fvdl m_freem(sc->bge_cdata.bge_tx_chain[i]);
1134 1.1 fvdl sc->bge_cdata.bge_tx_chain[i] = NULL;
1135 1.1 fvdl SLIST_INSERT_HEAD(&sc->txdma_list, sc->txdma[i],
1136 1.1 fvdl link);
1137 1.1 fvdl sc->txdma[i] = 0;
1138 1.1 fvdl }
1139 1.1 fvdl memset((char *)&sc->bge_rdata->bge_tx_ring[i], 0,
1140 1.1 fvdl sizeof(struct bge_tx_bd));
1141 1.1 fvdl }
1142 1.1 fvdl
1143 1.1 fvdl while ((dma = SLIST_FIRST(&sc->txdma_list))) {
1144 1.1 fvdl SLIST_REMOVE_HEAD(&sc->txdma_list, link);
1145 1.1 fvdl bus_dmamap_destroy(sc->bge_dmatag, dma->dmamap);
1146 1.1 fvdl free(dma, M_DEVBUF);
1147 1.1 fvdl }
1148 1.1 fvdl
1149 1.1 fvdl sc->bge_flags &= ~BGE_TXRING_VALID;
1150 1.1 fvdl }
1151 1.1 fvdl
1152 1.1 fvdl int
1153 1.1 fvdl bge_init_tx_ring(sc)
1154 1.1 fvdl struct bge_softc *sc;
1155 1.1 fvdl {
1156 1.1 fvdl int i;
1157 1.1 fvdl bus_dmamap_t dmamap;
1158 1.1 fvdl struct txdmamap_pool_entry *dma;
1159 1.1 fvdl
1160 1.1 fvdl if (sc->bge_flags & BGE_TXRING_VALID)
1161 1.1 fvdl return 0;
1162 1.1 fvdl
1163 1.1 fvdl sc->bge_txcnt = 0;
1164 1.1 fvdl sc->bge_tx_saved_considx = 0;
1165 1.94 jonathan
1166 1.94 jonathan /* Initialize transmit producer index for host-memory send ring. */
1167 1.94 jonathan sc->bge_tx_prodidx = 0;
1168 1.94 jonathan CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx);
1169 1.25 jonathan if (sc->bge_quirks & BGE_QUIRK_PRODUCER_BUG) /* 5700 b2 errata */
1170 1.94 jonathan CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx);
1171 1.25 jonathan
1172 1.94 jonathan /* NIC-memory send ring not used; initialize to zero. */
1173 1.1 fvdl CSR_WRITE_4(sc, BGE_MBX_TX_NIC_PROD0_LO, 0);
1174 1.25 jonathan if (sc->bge_quirks & BGE_QUIRK_PRODUCER_BUG) /* 5700 b2 errata */
1175 1.25 jonathan CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, 0);
1176 1.1 fvdl
1177 1.1 fvdl SLIST_INIT(&sc->txdma_list);
1178 1.1 fvdl for (i = 0; i < BGE_RSLOTS; i++) {
1179 1.95 jonathan if (bus_dmamap_create(sc->bge_dmatag, BGE_TXDMA_MAX,
1180 1.1 fvdl BGE_NTXSEG, ETHER_MAX_LEN_JUMBO, 0, BUS_DMA_NOWAIT,
1181 1.1 fvdl &dmamap))
1182 1.1 fvdl return(ENOBUFS);
1183 1.1 fvdl if (dmamap == NULL)
1184 1.1 fvdl panic("dmamap NULL in bge_init_tx_ring");
1185 1.1 fvdl dma = malloc(sizeof(*dma), M_DEVBUF, M_NOWAIT);
1186 1.1 fvdl if (dma == NULL) {
1187 1.1 fvdl printf("%s: can't alloc txdmamap_pool_entry\n",
1188 1.1 fvdl sc->bge_dev.dv_xname);
1189 1.1 fvdl bus_dmamap_destroy(sc->bge_dmatag, dmamap);
1190 1.1 fvdl return (ENOMEM);
1191 1.1 fvdl }
1192 1.1 fvdl dma->dmamap = dmamap;
1193 1.1 fvdl SLIST_INSERT_HEAD(&sc->txdma_list, dma, link);
1194 1.1 fvdl }
1195 1.1 fvdl
1196 1.1 fvdl sc->bge_flags |= BGE_TXRING_VALID;
1197 1.1 fvdl
1198 1.1 fvdl return(0);
1199 1.1 fvdl }
1200 1.1 fvdl
1201 1.1 fvdl void
1202 1.1 fvdl bge_setmulti(sc)
1203 1.1 fvdl struct bge_softc *sc;
1204 1.1 fvdl {
1205 1.1 fvdl struct ethercom *ac = &sc->ethercom;
1206 1.1 fvdl struct ifnet *ifp = &ac->ec_if;
1207 1.1 fvdl struct ether_multi *enm;
1208 1.1 fvdl struct ether_multistep step;
1209 1.1 fvdl u_int32_t hashes[4] = { 0, 0, 0, 0 };
1210 1.1 fvdl u_int32_t h;
1211 1.1 fvdl int i;
1212 1.1 fvdl
1213 1.13 thorpej if (ifp->if_flags & IFF_PROMISC)
1214 1.13 thorpej goto allmulti;
1215 1.1 fvdl
1216 1.1 fvdl /* Now program new ones. */
1217 1.1 fvdl ETHER_FIRST_MULTI(step, ac, enm);
1218 1.1 fvdl while (enm != NULL) {
1219 1.13 thorpej if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) {
1220 1.13 thorpej /*
1221 1.13 thorpej * We must listen to a range of multicast addresses.
1222 1.13 thorpej * For now, just accept all multicasts, rather than
1223 1.13 thorpej * trying to set only those filter bits needed to match
1224 1.13 thorpej * the range. (At this time, the only use of address
1225 1.13 thorpej * ranges is for IP multicast routing, for which the
1226 1.13 thorpej * range is big enough to require all bits set.)
1227 1.13 thorpej */
1228 1.13 thorpej goto allmulti;
1229 1.13 thorpej }
1230 1.13 thorpej
1231 1.13 thorpej h = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN);
1232 1.13 thorpej
1233 1.13 thorpej /* Just want the 7 least-significant bits. */
1234 1.13 thorpej h &= 0x7f;
1235 1.13 thorpej
1236 1.1 fvdl hashes[(h & 0x60) >> 5] |= 1 << (h & 0x1F);
1237 1.1 fvdl ETHER_NEXT_MULTI(step, enm);
1238 1.1 fvdl }
1239 1.1 fvdl
1240 1.13 thorpej ifp->if_flags &= ~IFF_ALLMULTI;
1241 1.13 thorpej goto setit;
1242 1.13 thorpej
1243 1.13 thorpej allmulti:
1244 1.13 thorpej ifp->if_flags |= IFF_ALLMULTI;
1245 1.13 thorpej hashes[0] = hashes[1] = hashes[2] = hashes[3] = 0xffffffff;
1246 1.13 thorpej
1247 1.13 thorpej setit:
1248 1.1 fvdl for (i = 0; i < 4; i++)
1249 1.1 fvdl CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]);
1250 1.1 fvdl }
1251 1.1 fvdl
1252 1.24 matt const int bge_swapbits[] = {
1253 1.1 fvdl 0,
1254 1.1 fvdl BGE_MODECTL_BYTESWAP_DATA,
1255 1.1 fvdl BGE_MODECTL_WORDSWAP_DATA,
1256 1.1 fvdl BGE_MODECTL_BYTESWAP_NONFRAME,
1257 1.1 fvdl BGE_MODECTL_WORDSWAP_NONFRAME,
1258 1.1 fvdl
1259 1.1 fvdl BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA,
1260 1.1 fvdl BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_BYTESWAP_NONFRAME,
1261 1.1 fvdl BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_NONFRAME,
1262 1.1 fvdl
1263 1.1 fvdl BGE_MODECTL_WORDSWAP_DATA|BGE_MODECTL_BYTESWAP_NONFRAME,
1264 1.1 fvdl BGE_MODECTL_WORDSWAP_DATA|BGE_MODECTL_WORDSWAP_NONFRAME,
1265 1.1 fvdl
1266 1.1 fvdl BGE_MODECTL_BYTESWAP_NONFRAME|BGE_MODECTL_WORDSWAP_NONFRAME,
1267 1.1 fvdl
1268 1.1 fvdl BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA|
1269 1.1 fvdl BGE_MODECTL_BYTESWAP_NONFRAME,
1270 1.1 fvdl BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA|
1271 1.1 fvdl BGE_MODECTL_WORDSWAP_NONFRAME,
1272 1.1 fvdl BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_BYTESWAP_NONFRAME|
1273 1.1 fvdl BGE_MODECTL_WORDSWAP_NONFRAME,
1274 1.1 fvdl BGE_MODECTL_WORDSWAP_DATA|BGE_MODECTL_BYTESWAP_NONFRAME|
1275 1.1 fvdl BGE_MODECTL_WORDSWAP_NONFRAME,
1276 1.1 fvdl
1277 1.1 fvdl BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA|
1278 1.1 fvdl BGE_MODECTL_BYTESWAP_NONFRAME|BGE_MODECTL_WORDSWAP_NONFRAME,
1279 1.1 fvdl };
1280 1.1 fvdl
1281 1.1 fvdl int bge_swapindex = 0;
1282 1.1 fvdl
1283 1.1 fvdl /*
1284 1.1 fvdl * Do endian, PCI and DMA initialization. Also check the on-board ROM
1285 1.1 fvdl * self-test results.
1286 1.1 fvdl */
1287 1.1 fvdl int
1288 1.1 fvdl bge_chipinit(sc)
1289 1.1 fvdl struct bge_softc *sc;
1290 1.1 fvdl {
1291 1.1 fvdl u_int32_t cachesize;
1292 1.1 fvdl int i;
1293 1.25 jonathan u_int32_t dma_rw_ctl;
1294 1.1 fvdl struct pci_attach_args *pa = &(sc->bge_pa);
1295 1.1 fvdl
1296 1.1 fvdl
1297 1.1 fvdl /* Set endianness before we access any non-PCI registers. */
1298 1.1 fvdl pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_MISC_CTL,
1299 1.1 fvdl BGE_INIT);
1300 1.1 fvdl
1301 1.25 jonathan /* Set power state to D0. */
1302 1.25 jonathan bge_setpowerstate(sc, 0);
1303 1.87 perry
1304 1.1 fvdl /*
1305 1.1 fvdl * Check the 'ROM failed' bit on the RX CPU to see if
1306 1.1 fvdl * self-tests passed.
1307 1.1 fvdl */
1308 1.1 fvdl if (CSR_READ_4(sc, BGE_RXCPU_MODE) & BGE_RXCPUMODE_ROMFAIL) {
1309 1.1 fvdl printf("%s: RX CPU self-diagnostics failed!\n",
1310 1.1 fvdl sc->bge_dev.dv_xname);
1311 1.1 fvdl return(ENODEV);
1312 1.1 fvdl }
1313 1.1 fvdl
1314 1.1 fvdl /* Clear the MAC control register */
1315 1.1 fvdl CSR_WRITE_4(sc, BGE_MAC_MODE, 0);
1316 1.1 fvdl
1317 1.1 fvdl /*
1318 1.1 fvdl * Clear the MAC statistics block in the NIC's
1319 1.1 fvdl * internal memory.
1320 1.1 fvdl */
1321 1.1 fvdl for (i = BGE_STATS_BLOCK;
1322 1.1 fvdl i < BGE_STATS_BLOCK_END + 1; i += sizeof(u_int32_t))
1323 1.1 fvdl BGE_MEMWIN_WRITE(pa->pa_pc, pa->pa_tag, i, 0);
1324 1.1 fvdl
1325 1.1 fvdl for (i = BGE_STATUS_BLOCK;
1326 1.1 fvdl i < BGE_STATUS_BLOCK_END + 1; i += sizeof(u_int32_t))
1327 1.1 fvdl BGE_MEMWIN_WRITE(pa->pa_pc, pa->pa_tag, i, 0);
1328 1.1 fvdl
1329 1.1 fvdl /* Set up the PCI DMA control register. */
1330 1.76 cube if (sc->bge_pcie) {
1331 1.95 jonathan u_int32_t device_ctl;
1332 1.95 jonathan
1333 1.76 cube /* From FreeBSD */
1334 1.76 cube DPRINTFN(4, ("(%s: PCI-Express DMA setting)\n",
1335 1.76 cube sc->bge_dev.dv_xname));
1336 1.76 cube dma_rw_ctl = (BGE_PCI_READ_CMD | BGE_PCI_WRITE_CMD |
1337 1.76 cube (0xf << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
1338 1.76 cube (0x2 << BGE_PCIDMARWCTL_WR_WAT_SHIFT));
1339 1.95 jonathan
1340 1.95 jonathan /* jonathan: alternative from Linux driver */
1341 1.95 jonathan #define DMA_CTRL_WRITE_PCIE_H20MARK_128 0x00180000
1342 1.95 jonathan #define DMA_CTRL_WRITE_PCIE_H20MARK_256 0x00380000
1343 1.95 jonathan
1344 1.95 jonathan dma_rw_ctl = 0x76000000; /* XXX XXX XXX */;
1345 1.95 jonathan device_ctl = pci_conf_read(pa->pa_pc, pa->pa_tag,
1346 1.95 jonathan BGE_PCI_CONF_DEV_CTRL);
1347 1.95 jonathan printf("%s: pcie mode=0x%x\n", sc->bge_dev.dv_xname, device_ctl);
1348 1.95 jonathan
1349 1.95 jonathan if ((device_ctl & 0x00e0) && 0) {
1350 1.95 jonathan /*
1351 1.95 jonathan * XXX jonathan (at) NetBSD.org:
1352 1.95 jonathan * This clause is exactly what the Broadcom-supplied
1353 1.95 jonathan * Linux does; but given overall register programming
1354 1.95 jonathan * by if_bge(4), this larger DMA-write watermark
1355 1.95 jonathan * value causes bcm5721 chips to totally wedge.
1356 1.95 jonathan */
1357 1.95 jonathan dma_rw_ctl |= BGE_PCIDMA_RWCTL_PCIE_WRITE_WATRMARK_256;
1358 1.95 jonathan } else {
1359 1.95 jonathan dma_rw_ctl |= BGE_PCIDMA_RWCTL_PCIE_WRITE_WATRMARK_128;
1360 1.95 jonathan }
1361 1.76 cube } else if (pci_conf_read(pa->pa_pc, pa->pa_tag,BGE_PCI_PCISTATE) &
1362 1.25 jonathan BGE_PCISTATE_PCI_BUSMODE) {
1363 1.25 jonathan /* Conventional PCI bus */
1364 1.39 wiz DPRINTFN(4, ("(%s: PCI 2.2 DMA setting)\n", sc->bge_dev.dv_xname));
1365 1.25 jonathan dma_rw_ctl = (BGE_PCI_READ_CMD | BGE_PCI_WRITE_CMD |
1366 1.25 jonathan (0x7 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
1367 1.44 hannken (0x7 << BGE_PCIDMARWCTL_WR_WAT_SHIFT));
1368 1.44 hannken if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) {
1369 1.44 hannken dma_rw_ctl |= 0x0F;
1370 1.44 hannken }
1371 1.25 jonathan } else {
1372 1.39 wiz DPRINTFN(4, ("(:%s: PCI-X DMA setting)\n", sc->bge_dev.dv_xname));
1373 1.25 jonathan /* PCI-X bus */
1374 1.25 jonathan dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
1375 1.25 jonathan (0x3 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
1376 1.25 jonathan (0x3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT) |
1377 1.25 jonathan (0x0F);
1378 1.25 jonathan /*
1379 1.25 jonathan * 5703 and 5704 need ONEDMA_AT_ONCE as a workaround
1380 1.25 jonathan * for hardware bugs, which means we should also clear
1381 1.25 jonathan * the low-order MINDMA bits. In addition, the 5704
1382 1.25 jonathan * uses a different encoding of read/write watermarks.
1383 1.25 jonathan */
1384 1.57 jonathan if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) {
1385 1.25 jonathan dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
1386 1.25 jonathan /* should be 0x1f0000 */
1387 1.25 jonathan (0x7 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
1388 1.25 jonathan (0x3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT);
1389 1.25 jonathan dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE;
1390 1.25 jonathan }
1391 1.57 jonathan else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5703) {
1392 1.25 jonathan dma_rw_ctl &= 0xfffffff0;
1393 1.25 jonathan dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE;
1394 1.25 jonathan }
1395 1.99 jonathan else if (BGE_IS_5714_FAMILY(sc)) {
1396 1.99 jonathan dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD;
1397 1.99 jonathan dma_rw_ctl &= ~BGE_PCIDMARWCTL_ONEDMA_ATONCE; /* XXX */
1398 1.99 jonathan /* XXX magic values, Broadcom-supplied Linux driver */
1399 1.99 jonathan if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5780)
1400 1.99 jonathan dma_rw_ctl |= (1 << 20) | (1 << 18) |
1401 1.99 jonathan BGE_PCIDMARWCTL_ONEDMA_ATONCE;
1402 1.99 jonathan else
1403 1.99 jonathan dma_rw_ctl |= (1<<20) | (1<<18) | (1 << 15);
1404 1.99 jonathan }
1405 1.25 jonathan }
1406 1.25 jonathan
1407 1.25 jonathan pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_DMA_RW_CTL, dma_rw_ctl);
1408 1.1 fvdl
1409 1.1 fvdl /*
1410 1.1 fvdl * Set up general mode register.
1411 1.1 fvdl */
1412 1.1 fvdl CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS|
1413 1.1 fvdl BGE_MODECTL_MAC_ATTN_INTR|BGE_MODECTL_HOST_SEND_BDS|
1414 1.54 fvdl BGE_MODECTL_TX_NO_PHDR_CSUM|BGE_MODECTL_RX_NO_PHDR_CSUM);
1415 1.1 fvdl
1416 1.1 fvdl /* Get cache line size. */
1417 1.1 fvdl cachesize = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_CACHESZ);
1418 1.1 fvdl
1419 1.1 fvdl /*
1420 1.1 fvdl * Avoid violating PCI spec on certain chip revs.
1421 1.1 fvdl */
1422 1.1 fvdl if (pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_CMD) &
1423 1.1 fvdl PCIM_CMD_MWIEN) {
1424 1.1 fvdl switch(cachesize) {
1425 1.1 fvdl case 1:
1426 1.1 fvdl PCI_SETBIT(pa->pa_pc, pa->pa_tag, BGE_PCI_DMA_RW_CTL,
1427 1.1 fvdl BGE_PCI_WRITE_BNDRY_16BYTES);
1428 1.1 fvdl break;
1429 1.1 fvdl case 2:
1430 1.1 fvdl PCI_SETBIT(pa->pa_pc, pa->pa_tag, BGE_PCI_DMA_RW_CTL,
1431 1.1 fvdl BGE_PCI_WRITE_BNDRY_32BYTES);
1432 1.1 fvdl break;
1433 1.1 fvdl case 4:
1434 1.1 fvdl PCI_SETBIT(pa->pa_pc, pa->pa_tag, BGE_PCI_DMA_RW_CTL,
1435 1.1 fvdl BGE_PCI_WRITE_BNDRY_64BYTES);
1436 1.1 fvdl break;
1437 1.1 fvdl case 8:
1438 1.1 fvdl PCI_SETBIT(pa->pa_pc, pa->pa_tag, BGE_PCI_DMA_RW_CTL,
1439 1.1 fvdl BGE_PCI_WRITE_BNDRY_128BYTES);
1440 1.1 fvdl break;
1441 1.1 fvdl case 16:
1442 1.1 fvdl PCI_SETBIT(pa->pa_pc, pa->pa_tag, BGE_PCI_DMA_RW_CTL,
1443 1.1 fvdl BGE_PCI_WRITE_BNDRY_256BYTES);
1444 1.1 fvdl break;
1445 1.1 fvdl case 32:
1446 1.1 fvdl PCI_SETBIT(pa->pa_pc, pa->pa_tag, BGE_PCI_DMA_RW_CTL,
1447 1.1 fvdl BGE_PCI_WRITE_BNDRY_512BYTES);
1448 1.1 fvdl break;
1449 1.1 fvdl case 64:
1450 1.1 fvdl PCI_SETBIT(pa->pa_pc, pa->pa_tag, BGE_PCI_DMA_RW_CTL,
1451 1.1 fvdl BGE_PCI_WRITE_BNDRY_1024BYTES);
1452 1.1 fvdl break;
1453 1.1 fvdl default:
1454 1.1 fvdl /* Disable PCI memory write and invalidate. */
1455 1.1 fvdl #if 0
1456 1.1 fvdl if (bootverbose)
1457 1.1 fvdl printf("%s: cache line size %d not "
1458 1.1 fvdl "supported; disabling PCI MWI\n",
1459 1.1 fvdl sc->bge_dev.dv_xname, cachesize);
1460 1.1 fvdl #endif
1461 1.1 fvdl PCI_CLRBIT(pa->pa_pc, pa->pa_tag, BGE_PCI_CMD,
1462 1.1 fvdl PCIM_CMD_MWIEN);
1463 1.1 fvdl break;
1464 1.1 fvdl }
1465 1.1 fvdl }
1466 1.1 fvdl
1467 1.25 jonathan /*
1468 1.25 jonathan * Disable memory write invalidate. Apparently it is not supported
1469 1.25 jonathan * properly by these devices.
1470 1.25 jonathan */
1471 1.25 jonathan PCI_CLRBIT(pa->pa_pc, pa->pa_tag, BGE_PCI_CMD, PCIM_CMD_MWIEN);
1472 1.25 jonathan
1473 1.25 jonathan
1474 1.1 fvdl #ifdef __brokenalpha__
1475 1.1 fvdl /*
1476 1.1 fvdl * Must insure that we do not cross an 8K (bytes) boundary
1477 1.1 fvdl * for DMA reads. Our highest limit is 1K bytes. This is a
1478 1.1 fvdl * restriction on some ALPHA platforms with early revision
1479 1.1 fvdl * 21174 PCI chipsets, such as the AlphaPC 164lx
1480 1.1 fvdl */
1481 1.1 fvdl PCI_SETBIT(sc, BGE_PCI_DMA_RW_CTL, BGE_PCI_READ_BNDRY_1024, 4);
1482 1.1 fvdl #endif
1483 1.1 fvdl
1484 1.33 tsutsui /* Set the timer prescaler (always 66MHz) */
1485 1.1 fvdl CSR_WRITE_4(sc, BGE_MISC_CFG, 65 << 1/*BGE_32BITTIME_66MHZ*/);
1486 1.1 fvdl
1487 1.1 fvdl return(0);
1488 1.1 fvdl }
1489 1.1 fvdl
1490 1.1 fvdl int
1491 1.1 fvdl bge_blockinit(sc)
1492 1.1 fvdl struct bge_softc *sc;
1493 1.1 fvdl {
1494 1.34 jonathan volatile struct bge_rcb *rcb;
1495 1.1 fvdl bus_size_t rcb_addr;
1496 1.1 fvdl int i;
1497 1.1 fvdl struct ifnet *ifp = &sc->ethercom.ec_if;
1498 1.1 fvdl bge_hostaddr taddr;
1499 1.1 fvdl
1500 1.1 fvdl /*
1501 1.1 fvdl * Initialize the memory window pointer register so that
1502 1.1 fvdl * we can access the first 32K of internal NIC RAM. This will
1503 1.1 fvdl * allow us to set up the TX send ring RCBs and the RX return
1504 1.1 fvdl * ring RCBs, plus other things which live in NIC memory.
1505 1.1 fvdl */
1506 1.1 fvdl
1507 1.1 fvdl pci_conf_write(sc->bge_pa.pa_pc, sc->bge_pa.pa_tag,
1508 1.1 fvdl BGE_PCI_MEMWIN_BASEADDR, 0);
1509 1.1 fvdl
1510 1.1 fvdl /* Configure mbuf memory pool */
1511 1.44 hannken if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) {
1512 1.44 hannken if (sc->bge_extram) {
1513 1.44 hannken CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR,
1514 1.44 hannken BGE_EXT_SSRAM);
1515 1.54 fvdl if ((sc->bge_quirks & BGE_QUIRK_FEWER_MBUFS) != 0)
1516 1.54 fvdl CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000);
1517 1.54 fvdl else
1518 1.54 fvdl CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000);
1519 1.44 hannken } else {
1520 1.44 hannken CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR,
1521 1.44 hannken BGE_BUFFPOOL_1);
1522 1.54 fvdl if ((sc->bge_quirks & BGE_QUIRK_FEWER_MBUFS) != 0)
1523 1.54 fvdl CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000);
1524 1.54 fvdl else
1525 1.54 fvdl CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000);
1526 1.44 hannken }
1527 1.44 hannken
1528 1.44 hannken /* Configure DMA resource pool */
1529 1.44 hannken CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_BASEADDR,
1530 1.44 hannken BGE_DMA_DESCRIPTORS);
1531 1.44 hannken CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LEN, 0x2000);
1532 1.1 fvdl }
1533 1.1 fvdl
1534 1.1 fvdl /* Configure mbuf pool watermarks */
1535 1.25 jonathan #ifdef ORIG_WPAUL_VALUES
1536 1.1 fvdl CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 24);
1537 1.1 fvdl CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 24);
1538 1.1 fvdl CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 48);
1539 1.25 jonathan #else
1540 1.25 jonathan /* new broadcom docs strongly recommend these: */
1541 1.44 hannken if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) {
1542 1.71 thorpej if (ifp->if_mtu > ETHER_MAX_LEN) {
1543 1.71 thorpej CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x50);
1544 1.71 thorpej CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x20);
1545 1.71 thorpej CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60);
1546 1.71 thorpej } else {
1547 1.71 thorpej /* Values from Linux driver... */
1548 1.71 thorpej CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 304);
1549 1.71 thorpej CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 152);
1550 1.71 thorpej CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 380);
1551 1.71 thorpej }
1552 1.44 hannken } else {
1553 1.44 hannken CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0);
1554 1.44 hannken CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x10);
1555 1.71 thorpej CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60);
1556 1.44 hannken }
1557 1.25 jonathan #endif
1558 1.1 fvdl
1559 1.1 fvdl /* Configure DMA resource watermarks */
1560 1.1 fvdl CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5);
1561 1.1 fvdl CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10);
1562 1.1 fvdl
1563 1.1 fvdl /* Enable buffer manager */
1564 1.44 hannken if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) {
1565 1.44 hannken CSR_WRITE_4(sc, BGE_BMAN_MODE,
1566 1.44 hannken BGE_BMANMODE_ENABLE|BGE_BMANMODE_LOMBUF_ATTN);
1567 1.44 hannken
1568 1.44 hannken /* Poll for buffer manager start indication */
1569 1.44 hannken for (i = 0; i < BGE_TIMEOUT; i++) {
1570 1.44 hannken if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE)
1571 1.44 hannken break;
1572 1.44 hannken DELAY(10);
1573 1.44 hannken }
1574 1.1 fvdl
1575 1.44 hannken if (i == BGE_TIMEOUT) {
1576 1.44 hannken printf("%s: buffer manager failed to start\n",
1577 1.44 hannken sc->bge_dev.dv_xname);
1578 1.44 hannken return(ENXIO);
1579 1.44 hannken }
1580 1.1 fvdl }
1581 1.1 fvdl
1582 1.1 fvdl /* Enable flow-through queues */
1583 1.1 fvdl CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF);
1584 1.1 fvdl CSR_WRITE_4(sc, BGE_FTQ_RESET, 0);
1585 1.1 fvdl
1586 1.1 fvdl /* Wait until queue initialization is complete */
1587 1.1 fvdl for (i = 0; i < BGE_TIMEOUT; i++) {
1588 1.1 fvdl if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0)
1589 1.1 fvdl break;
1590 1.1 fvdl DELAY(10);
1591 1.1 fvdl }
1592 1.1 fvdl
1593 1.1 fvdl if (i == BGE_TIMEOUT) {
1594 1.1 fvdl printf("%s: flow-through queue init failed\n",
1595 1.1 fvdl sc->bge_dev.dv_xname);
1596 1.1 fvdl return(ENXIO);
1597 1.1 fvdl }
1598 1.1 fvdl
1599 1.1 fvdl /* Initialize the standard RX ring control block */
1600 1.1 fvdl rcb = &sc->bge_rdata->bge_info.bge_std_rx_rcb;
1601 1.1 fvdl bge_set_hostaddr(&rcb->bge_hostaddr,
1602 1.1 fvdl BGE_RING_DMA_ADDR(sc, bge_rx_std_ring));
1603 1.44 hannken if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) {
1604 1.44 hannken rcb->bge_maxlen_flags =
1605 1.44 hannken BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 0);
1606 1.44 hannken } else {
1607 1.44 hannken rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(512, 0);
1608 1.44 hannken }
1609 1.1 fvdl if (sc->bge_extram)
1610 1.1 fvdl rcb->bge_nicaddr = BGE_EXT_STD_RX_RINGS;
1611 1.1 fvdl else
1612 1.1 fvdl rcb->bge_nicaddr = BGE_STD_RX_RINGS;
1613 1.34 jonathan CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcb->bge_hostaddr.bge_addr_hi);
1614 1.34 jonathan CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcb->bge_hostaddr.bge_addr_lo);
1615 1.34 jonathan CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags);
1616 1.34 jonathan CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcb->bge_nicaddr);
1617 1.1 fvdl
1618 1.44 hannken if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) {
1619 1.44 hannken sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT;
1620 1.44 hannken } else {
1621 1.44 hannken sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT_5705;
1622 1.44 hannken }
1623 1.44 hannken
1624 1.1 fvdl /*
1625 1.1 fvdl * Initialize the jumbo RX ring control block
1626 1.1 fvdl * We set the 'ring disabled' bit in the flags
1627 1.1 fvdl * field until we're actually ready to start
1628 1.1 fvdl * using this ring (i.e. once we set the MTU
1629 1.1 fvdl * high enough to require it).
1630 1.1 fvdl */
1631 1.44 hannken if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) {
1632 1.44 hannken rcb = &sc->bge_rdata->bge_info.bge_jumbo_rx_rcb;
1633 1.44 hannken bge_set_hostaddr(&rcb->bge_hostaddr,
1634 1.44 hannken BGE_RING_DMA_ADDR(sc, bge_rx_jumbo_ring));
1635 1.87 perry rcb->bge_maxlen_flags =
1636 1.44 hannken BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN,
1637 1.44 hannken BGE_RCB_FLAG_RING_DISABLED);
1638 1.44 hannken if (sc->bge_extram)
1639 1.44 hannken rcb->bge_nicaddr = BGE_EXT_JUMBO_RX_RINGS;
1640 1.44 hannken else
1641 1.44 hannken rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS;
1642 1.87 perry
1643 1.44 hannken CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI,
1644 1.44 hannken rcb->bge_hostaddr.bge_addr_hi);
1645 1.44 hannken CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO,
1646 1.44 hannken rcb->bge_hostaddr.bge_addr_lo);
1647 1.44 hannken CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS,
1648 1.44 hannken rcb->bge_maxlen_flags);
1649 1.44 hannken CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcb->bge_nicaddr);
1650 1.44 hannken
1651 1.44 hannken /* Set up dummy disabled mini ring RCB */
1652 1.44 hannken rcb = &sc->bge_rdata->bge_info.bge_mini_rx_rcb;
1653 1.44 hannken rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0,
1654 1.44 hannken BGE_RCB_FLAG_RING_DISABLED);
1655 1.44 hannken CSR_WRITE_4(sc, BGE_RX_MINI_RCB_MAXLEN_FLAGS,
1656 1.44 hannken rcb->bge_maxlen_flags);
1657 1.1 fvdl
1658 1.44 hannken bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map,
1659 1.44 hannken offsetof(struct bge_ring_data, bge_info),
1660 1.44 hannken sizeof (struct bge_gib),
1661 1.44 hannken BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
1662 1.44 hannken }
1663 1.1 fvdl
1664 1.1 fvdl /*
1665 1.1 fvdl * Set the BD ring replentish thresholds. The recommended
1666 1.1 fvdl * values are 1/8th the number of descriptors allocated to
1667 1.1 fvdl * each ring.
1668 1.1 fvdl */
1669 1.1 fvdl CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, BGE_STD_RX_RING_CNT/8);
1670 1.1 fvdl CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH, BGE_JUMBO_RX_RING_CNT/8);
1671 1.1 fvdl
1672 1.1 fvdl /*
1673 1.1 fvdl * Disable all unused send rings by setting the 'ring disabled'
1674 1.1 fvdl * bit in the flags field of all the TX send ring control blocks.
1675 1.1 fvdl * These are located in NIC memory.
1676 1.1 fvdl */
1677 1.1 fvdl rcb_addr = BGE_MEMWIN_START + BGE_SEND_RING_RCB;
1678 1.1 fvdl for (i = 0; i < BGE_TX_RINGS_EXTSSRAM_MAX; i++) {
1679 1.34 jonathan RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags,
1680 1.34 jonathan BGE_RCB_MAXLEN_FLAGS(0,BGE_RCB_FLAG_RING_DISABLED));
1681 1.1 fvdl RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 0);
1682 1.1 fvdl rcb_addr += sizeof(struct bge_rcb);
1683 1.1 fvdl }
1684 1.1 fvdl
1685 1.1 fvdl /* Configure TX RCB 0 (we use only the first ring) */
1686 1.1 fvdl rcb_addr = BGE_MEMWIN_START + BGE_SEND_RING_RCB;
1687 1.1 fvdl bge_set_hostaddr(&taddr, BGE_RING_DMA_ADDR(sc, bge_tx_ring));
1688 1.1 fvdl RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi);
1689 1.1 fvdl RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo);
1690 1.1 fvdl RCB_WRITE_4(sc, rcb_addr, bge_nicaddr,
1691 1.1 fvdl BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT));
1692 1.44 hannken if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) {
1693 1.87 perry RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags,
1694 1.44 hannken BGE_RCB_MAXLEN_FLAGS(BGE_TX_RING_CNT, 0));
1695 1.44 hannken }
1696 1.1 fvdl
1697 1.1 fvdl /* Disable all unused RX return rings */
1698 1.1 fvdl rcb_addr = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB;
1699 1.1 fvdl for (i = 0; i < BGE_RX_RINGS_MAX; i++) {
1700 1.1 fvdl RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_hi, 0);
1701 1.1 fvdl RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_lo, 0);
1702 1.87 perry RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags,
1703 1.44 hannken BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt,
1704 1.34 jonathan BGE_RCB_FLAG_RING_DISABLED));
1705 1.1 fvdl RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 0);
1706 1.1 fvdl CSR_WRITE_4(sc, BGE_MBX_RX_CONS0_LO +
1707 1.1 fvdl (i * (sizeof(u_int64_t))), 0);
1708 1.1 fvdl rcb_addr += sizeof(struct bge_rcb);
1709 1.1 fvdl }
1710 1.1 fvdl
1711 1.1 fvdl /* Initialize RX ring indexes */
1712 1.1 fvdl CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, 0);
1713 1.1 fvdl CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0);
1714 1.1 fvdl CSR_WRITE_4(sc, BGE_MBX_RX_MINI_PROD_LO, 0);
1715 1.1 fvdl
1716 1.1 fvdl /*
1717 1.1 fvdl * Set up RX return ring 0
1718 1.1 fvdl * Note that the NIC address for RX return rings is 0x00000000.
1719 1.1 fvdl * The return rings live entirely within the host, so the
1720 1.1 fvdl * nicaddr field in the RCB isn't used.
1721 1.1 fvdl */
1722 1.1 fvdl rcb_addr = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB;
1723 1.1 fvdl bge_set_hostaddr(&taddr, BGE_RING_DMA_ADDR(sc, bge_rx_return_ring));
1724 1.1 fvdl RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi);
1725 1.1 fvdl RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo);
1726 1.1 fvdl RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 0x00000000);
1727 1.34 jonathan RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags,
1728 1.44 hannken BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 0));
1729 1.1 fvdl
1730 1.1 fvdl /* Set random backoff seed for TX */
1731 1.1 fvdl CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF,
1732 1.1 fvdl LLADDR(ifp->if_sadl)[0] + LLADDR(ifp->if_sadl)[1] +
1733 1.1 fvdl LLADDR(ifp->if_sadl)[2] + LLADDR(ifp->if_sadl)[3] +
1734 1.1 fvdl LLADDR(ifp->if_sadl)[4] + LLADDR(ifp->if_sadl)[5] +
1735 1.1 fvdl BGE_TX_BACKOFF_SEED_MASK);
1736 1.1 fvdl
1737 1.1 fvdl /* Set inter-packet gap */
1738 1.1 fvdl CSR_WRITE_4(sc, BGE_TX_LENGTHS, 0x2620);
1739 1.1 fvdl
1740 1.1 fvdl /*
1741 1.1 fvdl * Specify which ring to use for packets that don't match
1742 1.1 fvdl * any RX rules.
1743 1.1 fvdl */
1744 1.1 fvdl CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08);
1745 1.1 fvdl
1746 1.1 fvdl /*
1747 1.1 fvdl * Configure number of RX lists. One interrupt distribution
1748 1.1 fvdl * list, sixteen active lists, one bad frames class.
1749 1.1 fvdl */
1750 1.1 fvdl CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181);
1751 1.1 fvdl
1752 1.1 fvdl /* Inialize RX list placement stats mask. */
1753 1.1 fvdl CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF);
1754 1.1 fvdl CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1);
1755 1.1 fvdl
1756 1.1 fvdl /* Disable host coalescing until we get it set up */
1757 1.1 fvdl CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000);
1758 1.1 fvdl
1759 1.1 fvdl /* Poll to make sure it's shut down. */
1760 1.1 fvdl for (i = 0; i < BGE_TIMEOUT; i++) {
1761 1.1 fvdl if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE))
1762 1.1 fvdl break;
1763 1.1 fvdl DELAY(10);
1764 1.1 fvdl }
1765 1.1 fvdl
1766 1.1 fvdl if (i == BGE_TIMEOUT) {
1767 1.1 fvdl printf("%s: host coalescing engine failed to idle\n",
1768 1.1 fvdl sc->bge_dev.dv_xname);
1769 1.1 fvdl return(ENXIO);
1770 1.1 fvdl }
1771 1.1 fvdl
1772 1.1 fvdl /* Set up host coalescing defaults */
1773 1.1 fvdl CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bge_rx_coal_ticks);
1774 1.1 fvdl CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bge_tx_coal_ticks);
1775 1.1 fvdl CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bge_rx_max_coal_bds);
1776 1.1 fvdl CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bge_tx_max_coal_bds);
1777 1.44 hannken if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) {
1778 1.44 hannken CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT, 0);
1779 1.44 hannken CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT, 0);
1780 1.44 hannken }
1781 1.1 fvdl CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 0);
1782 1.1 fvdl CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 0);
1783 1.1 fvdl
1784 1.1 fvdl /* Set up address of statistics block */
1785 1.44 hannken if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) {
1786 1.44 hannken bge_set_hostaddr(&taddr,
1787 1.44 hannken BGE_RING_DMA_ADDR(sc, bge_info.bge_stats));
1788 1.44 hannken CSR_WRITE_4(sc, BGE_HCC_STATS_TICKS, sc->bge_stat_ticks);
1789 1.44 hannken CSR_WRITE_4(sc, BGE_HCC_STATS_BASEADDR, BGE_STATS_BLOCK);
1790 1.44 hannken CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_HI, taddr.bge_addr_hi);
1791 1.44 hannken CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_LO, taddr.bge_addr_lo);
1792 1.44 hannken }
1793 1.1 fvdl
1794 1.1 fvdl /* Set up address of status block */
1795 1.1 fvdl bge_set_hostaddr(&taddr, BGE_RING_DMA_ADDR(sc, bge_status_block));
1796 1.1 fvdl CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_BASEADDR, BGE_STATUS_BLOCK);
1797 1.1 fvdl CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI, taddr.bge_addr_hi);
1798 1.1 fvdl CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO, taddr.bge_addr_lo);
1799 1.1 fvdl sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx = 0;
1800 1.1 fvdl sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx = 0;
1801 1.1 fvdl
1802 1.1 fvdl /* Turn on host coalescing state machine */
1803 1.1 fvdl CSR_WRITE_4(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE);
1804 1.1 fvdl
1805 1.1 fvdl /* Turn on RX BD completion state machine and enable attentions */
1806 1.1 fvdl CSR_WRITE_4(sc, BGE_RBDC_MODE,
1807 1.1 fvdl BGE_RBDCMODE_ENABLE|BGE_RBDCMODE_ATTN);
1808 1.1 fvdl
1809 1.1 fvdl /* Turn on RX list placement state machine */
1810 1.1 fvdl CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);
1811 1.1 fvdl
1812 1.1 fvdl /* Turn on RX list selector state machine. */
1813 1.44 hannken if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) {
1814 1.44 hannken CSR_WRITE_4(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE);
1815 1.44 hannken }
1816 1.1 fvdl
1817 1.1 fvdl /* Turn on DMA, clear stats */
1818 1.1 fvdl CSR_WRITE_4(sc, BGE_MAC_MODE, BGE_MACMODE_TXDMA_ENB|
1819 1.1 fvdl BGE_MACMODE_RXDMA_ENB|BGE_MACMODE_RX_STATS_CLEAR|
1820 1.1 fvdl BGE_MACMODE_TX_STATS_CLEAR|BGE_MACMODE_RX_STATS_ENB|
1821 1.1 fvdl BGE_MACMODE_TX_STATS_ENB|BGE_MACMODE_FRMHDR_DMA_ENB|
1822 1.1 fvdl (sc->bge_tbi ? BGE_PORTMODE_TBI : BGE_PORTMODE_MII));
1823 1.1 fvdl
1824 1.1 fvdl /* Set misc. local control, enable interrupts on attentions */
1825 1.25 jonathan sc->bge_local_ctrl_reg = BGE_MLC_INTR_ONATTN | BGE_MLC_AUTO_EEPROM;
1826 1.1 fvdl
1827 1.1 fvdl #ifdef notdef
1828 1.1 fvdl /* Assert GPIO pins for PHY reset */
1829 1.1 fvdl BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUT0|
1830 1.1 fvdl BGE_MLC_MISCIO_OUT1|BGE_MLC_MISCIO_OUT2);
1831 1.1 fvdl BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUTEN0|
1832 1.1 fvdl BGE_MLC_MISCIO_OUTEN1|BGE_MLC_MISCIO_OUTEN2);
1833 1.1 fvdl #endif
1834 1.1 fvdl
1835 1.25 jonathan #if defined(not_quite_yet)
1836 1.25 jonathan /* Linux driver enables enable gpio pin #1 on 5700s */
1837 1.51 fvdl if (sc->bge_chipid == BGE_CHIPID_BCM5700) {
1838 1.87 perry sc->bge_local_ctrl_reg |=
1839 1.25 jonathan (BGE_MLC_MISCIO_OUT1|BGE_MLC_MISCIO_OUTEN1);
1840 1.25 jonathan }
1841 1.87 perry #endif
1842 1.25 jonathan CSR_WRITE_4(sc, BGE_MISC_LOCAL_CTL, sc->bge_local_ctrl_reg);
1843 1.25 jonathan
1844 1.1 fvdl /* Turn on DMA completion state machine */
1845 1.44 hannken if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) {
1846 1.44 hannken CSR_WRITE_4(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE);
1847 1.44 hannken }
1848 1.1 fvdl
1849 1.1 fvdl /* Turn on write DMA state machine */
1850 1.1 fvdl CSR_WRITE_4(sc, BGE_WDMA_MODE,
1851 1.1 fvdl BGE_WDMAMODE_ENABLE|BGE_WDMAMODE_ALL_ATTNS);
1852 1.1 fvdl
1853 1.1 fvdl /* Turn on read DMA state machine */
1854 1.95 jonathan {
1855 1.95 jonathan uint32_t dma_read_modebits;
1856 1.95 jonathan
1857 1.95 jonathan dma_read_modebits =
1858 1.95 jonathan BGE_RDMAMODE_ENABLE | BGE_RDMAMODE_ALL_ATTNS;
1859 1.95 jonathan
1860 1.95 jonathan if (sc->bge_pcie && 0) {
1861 1.95 jonathan dma_read_modebits |= BGE_RDMA_MODE_FIFO_LONG_BURST;
1862 1.95 jonathan } else if ((sc->bge_quirks & BGE_QUIRK_5705_CORE)) {
1863 1.95 jonathan dma_read_modebits |= BGE_RDMA_MODE_FIFO_SIZE_128;
1864 1.95 jonathan }
1865 1.95 jonathan
1866 1.95 jonathan /* XXX broadcom-supplied linux driver; undocumented */
1867 1.95 jonathan if (BGE_IS_5750_OR_BEYOND(sc)) {
1868 1.95 jonathan /*
1869 1.95 jonathan * XXX: magic values.
1870 1.95 jonathan * From Broadcom-supplied Linux driver; apparently
1871 1.95 jonathan * required to workaround a DMA bug affecting TSO
1872 1.95 jonathan * on bcm575x/bcm5721?
1873 1.95 jonathan */
1874 1.95 jonathan dma_read_modebits |= (1 << 27);
1875 1.95 jonathan }
1876 1.95 jonathan CSR_WRITE_4(sc, BGE_RDMA_MODE, dma_read_modebits);
1877 1.95 jonathan }
1878 1.1 fvdl
1879 1.1 fvdl /* Turn on RX data completion state machine */
1880 1.1 fvdl CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);
1881 1.1 fvdl
1882 1.1 fvdl /* Turn on RX BD initiator state machine */
1883 1.1 fvdl CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE);
1884 1.1 fvdl
1885 1.1 fvdl /* Turn on RX data and RX BD initiator state machine */
1886 1.1 fvdl CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE);
1887 1.1 fvdl
1888 1.1 fvdl /* Turn on Mbuf cluster free state machine */
1889 1.44 hannken if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) {
1890 1.44 hannken CSR_WRITE_4(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE);
1891 1.44 hannken }
1892 1.1 fvdl
1893 1.1 fvdl /* Turn on send BD completion state machine */
1894 1.1 fvdl CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);
1895 1.1 fvdl
1896 1.1 fvdl /* Turn on send data completion state machine */
1897 1.1 fvdl CSR_WRITE_4(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE);
1898 1.1 fvdl
1899 1.1 fvdl /* Turn on send data initiator state machine */
1900 1.95 jonathan if (BGE_IS_5750_OR_BEYOND(sc)) {
1901 1.95 jonathan /* XXX: magic value from Linux driver */
1902 1.95 jonathan CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE | 0x08);
1903 1.95 jonathan } else {
1904 1.95 jonathan CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE);
1905 1.95 jonathan }
1906 1.1 fvdl
1907 1.1 fvdl /* Turn on send BD initiator state machine */
1908 1.1 fvdl CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE);
1909 1.1 fvdl
1910 1.1 fvdl /* Turn on send BD selector state machine */
1911 1.1 fvdl CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE);
1912 1.1 fvdl
1913 1.1 fvdl CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF);
1914 1.1 fvdl CSR_WRITE_4(sc, BGE_SDI_STATS_CTL,
1915 1.1 fvdl BGE_SDISTATSCTL_ENABLE|BGE_SDISTATSCTL_FASTER);
1916 1.1 fvdl
1917 1.1 fvdl /* ack/clear link change events */
1918 1.1 fvdl CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED|
1919 1.1 fvdl BGE_MACSTAT_CFG_CHANGED);
1920 1.1 fvdl CSR_WRITE_4(sc, BGE_MI_STS, 0);
1921 1.1 fvdl
1922 1.1 fvdl /* Enable PHY auto polling (for MII/GMII only) */
1923 1.1 fvdl if (sc->bge_tbi) {
1924 1.1 fvdl CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK);
1925 1.1 fvdl } else {
1926 1.1 fvdl BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL|10<<16);
1927 1.17 thorpej if (sc->bge_quirks & BGE_QUIRK_LINK_STATE_BROKEN)
1928 1.1 fvdl CSR_WRITE_4(sc, BGE_MAC_EVT_ENB,
1929 1.1 fvdl BGE_EVTENB_MI_INTERRUPT);
1930 1.1 fvdl }
1931 1.1 fvdl
1932 1.1 fvdl /* Enable link state change attentions. */
1933 1.1 fvdl BGE_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED);
1934 1.1 fvdl
1935 1.1 fvdl return(0);
1936 1.1 fvdl }
1937 1.1 fvdl
1938 1.16 thorpej static const struct bge_revision {
1939 1.51 fvdl uint32_t br_chipid;
1940 1.16 thorpej uint32_t br_quirks;
1941 1.16 thorpej const char *br_name;
1942 1.16 thorpej } bge_revisions[] = {
1943 1.51 fvdl { BGE_CHIPID_BCM5700_A0,
1944 1.17 thorpej BGE_QUIRK_LINK_STATE_BROKEN,
1945 1.16 thorpej "BCM5700 A0" },
1946 1.16 thorpej
1947 1.51 fvdl { BGE_CHIPID_BCM5700_A1,
1948 1.17 thorpej BGE_QUIRK_LINK_STATE_BROKEN,
1949 1.16 thorpej "BCM5700 A1" },
1950 1.16 thorpej
1951 1.51 fvdl { BGE_CHIPID_BCM5700_B0,
1952 1.26 jonathan BGE_QUIRK_LINK_STATE_BROKEN|BGE_QUIRK_CSUM_BROKEN|BGE_QUIRK_5700_COMMON,
1953 1.16 thorpej "BCM5700 B0" },
1954 1.16 thorpej
1955 1.51 fvdl { BGE_CHIPID_BCM5700_B1,
1956 1.26 jonathan BGE_QUIRK_LINK_STATE_BROKEN|BGE_QUIRK_5700_COMMON,
1957 1.16 thorpej "BCM5700 B1" },
1958 1.16 thorpej
1959 1.51 fvdl { BGE_CHIPID_BCM5700_B2,
1960 1.26 jonathan BGE_QUIRK_LINK_STATE_BROKEN|BGE_QUIRK_5700_COMMON,
1961 1.16 thorpej "BCM5700 B2" },
1962 1.16 thorpej
1963 1.17 thorpej /* This is treated like a BCM5700 Bx */
1964 1.51 fvdl { BGE_CHIPID_BCM5700_ALTIMA,
1965 1.26 jonathan BGE_QUIRK_LINK_STATE_BROKEN|BGE_QUIRK_5700_COMMON,
1966 1.16 thorpej "BCM5700 Altima" },
1967 1.16 thorpej
1968 1.51 fvdl { BGE_CHIPID_BCM5700_C0,
1969 1.16 thorpej 0,
1970 1.16 thorpej "BCM5700 C0" },
1971 1.16 thorpej
1972 1.51 fvdl { BGE_CHIPID_BCM5701_A0,
1973 1.37 jonathan 0, /*XXX really, just not known */
1974 1.16 thorpej "BCM5701 A0" },
1975 1.16 thorpej
1976 1.51 fvdl { BGE_CHIPID_BCM5701_B0,
1977 1.37 jonathan BGE_QUIRK_PCIX_DMA_ALIGN_BUG,
1978 1.16 thorpej "BCM5701 B0" },
1979 1.16 thorpej
1980 1.51 fvdl { BGE_CHIPID_BCM5701_B2,
1981 1.37 jonathan BGE_QUIRK_PCIX_DMA_ALIGN_BUG,
1982 1.16 thorpej "BCM5701 B2" },
1983 1.16 thorpej
1984 1.51 fvdl { BGE_CHIPID_BCM5701_B5,
1985 1.37 jonathan BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_PCIX_DMA_ALIGN_BUG,
1986 1.16 thorpej "BCM5701 B5" },
1987 1.16 thorpej
1988 1.51 fvdl { BGE_CHIPID_BCM5703_A0,
1989 1.16 thorpej 0,
1990 1.16 thorpej "BCM5703 A0" },
1991 1.16 thorpej
1992 1.51 fvdl { BGE_CHIPID_BCM5703_A1,
1993 1.16 thorpej 0,
1994 1.16 thorpej "BCM5703 A1" },
1995 1.16 thorpej
1996 1.51 fvdl { BGE_CHIPID_BCM5703_A2,
1997 1.24 matt BGE_QUIRK_ONLY_PHY_1,
1998 1.16 thorpej "BCM5703 A2" },
1999 1.16 thorpej
2000 1.55 pooka { BGE_CHIPID_BCM5703_A3,
2001 1.55 pooka BGE_QUIRK_ONLY_PHY_1,
2002 1.55 pooka "BCM5703 A3" },
2003 1.55 pooka
2004 1.51 fvdl { BGE_CHIPID_BCM5704_A0,
2005 1.54 fvdl BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_FEWER_MBUFS,
2006 1.25 jonathan "BCM5704 A0" },
2007 1.40 fvdl
2008 1.51 fvdl { BGE_CHIPID_BCM5704_A1,
2009 1.54 fvdl BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_FEWER_MBUFS,
2010 1.40 fvdl "BCM5704 A1" },
2011 1.40 fvdl
2012 1.51 fvdl { BGE_CHIPID_BCM5704_A2,
2013 1.54 fvdl BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_FEWER_MBUFS,
2014 1.40 fvdl "BCM5704 A2" },
2015 1.49 fvdl
2016 1.51 fvdl { BGE_CHIPID_BCM5704_A3,
2017 1.54 fvdl BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_FEWER_MBUFS,
2018 1.49 fvdl "BCM5704 A3" },
2019 1.25 jonathan
2020 1.51 fvdl { BGE_CHIPID_BCM5705_A0,
2021 1.51 fvdl BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_5705_CORE,
2022 1.51 fvdl "BCM5705 A0" },
2023 1.51 fvdl
2024 1.51 fvdl { BGE_CHIPID_BCM5705_A1,
2025 1.44 hannken BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_5705_CORE,
2026 1.44 hannken "BCM5705 A1" },
2027 1.44 hannken
2028 1.51 fvdl { BGE_CHIPID_BCM5705_A2,
2029 1.51 fvdl BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_5705_CORE,
2030 1.51 fvdl "BCM5705 A2" },
2031 1.51 fvdl
2032 1.51 fvdl { BGE_CHIPID_BCM5705_A3,
2033 1.51 fvdl BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_5705_CORE,
2034 1.51 fvdl "BCM5705 A3" },
2035 1.51 fvdl
2036 1.76 cube { BGE_CHIPID_BCM5750_A0,
2037 1.76 cube BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_5705_CORE,
2038 1.76 cube "BCM5750 A1" },
2039 1.76 cube
2040 1.76 cube { BGE_CHIPID_BCM5750_A1,
2041 1.76 cube BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_5705_CORE,
2042 1.76 cube "BCM5750 A1" },
2043 1.76 cube
2044 1.92 gavan { BGE_CHIPID_BCM5751_A1,
2045 1.92 gavan BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_5705_CORE,
2046 1.92 gavan "BCM5751 A1" },
2047 1.92 gavan
2048 1.16 thorpej { 0, 0, NULL }
2049 1.16 thorpej };
2050 1.16 thorpej
2051 1.51 fvdl /*
2052 1.51 fvdl * Some defaults for major revisions, so that newer steppings
2053 1.51 fvdl * that we don't know about have a shot at working.
2054 1.51 fvdl */
2055 1.51 fvdl static const struct bge_revision bge_majorrevs[] = {
2056 1.51 fvdl { BGE_ASICREV_BCM5700,
2057 1.51 fvdl BGE_QUIRK_LINK_STATE_BROKEN,
2058 1.51 fvdl "unknown BCM5700" },
2059 1.51 fvdl
2060 1.51 fvdl { BGE_ASICREV_BCM5701,
2061 1.51 fvdl BGE_QUIRK_PCIX_DMA_ALIGN_BUG,
2062 1.51 fvdl "unknown BCM5701" },
2063 1.51 fvdl
2064 1.51 fvdl { BGE_ASICREV_BCM5703,
2065 1.51 fvdl 0,
2066 1.51 fvdl "unknown BCM5703" },
2067 1.51 fvdl
2068 1.51 fvdl { BGE_ASICREV_BCM5704,
2069 1.51 fvdl BGE_QUIRK_ONLY_PHY_1,
2070 1.51 fvdl "unknown BCM5704" },
2071 1.51 fvdl
2072 1.51 fvdl { BGE_ASICREV_BCM5705,
2073 1.51 fvdl BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_5705_CORE,
2074 1.51 fvdl "unknown BCM5705" },
2075 1.51 fvdl
2076 1.76 cube { BGE_ASICREV_BCM5750,
2077 1.76 cube BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_5705_CORE,
2078 1.98 jonathan "unknown BCM575x family" },
2079 1.98 jonathan
2080 1.98 jonathan { BGE_ASICREV_BCM5714,
2081 1.98 jonathan BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_5705_CORE,
2082 1.98 jonathan "unknown BCM5714" },
2083 1.98 jonathan
2084 1.98 jonathan { BGE_ASICREV_BCM5752,
2085 1.98 jonathan BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_5705_CORE,
2086 1.98 jonathan "unknown BCM5752 family" },
2087 1.98 jonathan
2088 1.98 jonathan
2089 1.98 jonathan { BGE_ASICREV_BCM5715,
2090 1.98 jonathan BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_5705_CORE,
2091 1.98 jonathan "unknown BCM5715" },
2092 1.76 cube
2093 1.51 fvdl { 0,
2094 1.51 fvdl 0,
2095 1.51 fvdl NULL }
2096 1.51 fvdl };
2097 1.51 fvdl
2098 1.51 fvdl
2099 1.16 thorpej static const struct bge_revision *
2100 1.51 fvdl bge_lookup_rev(uint32_t chipid)
2101 1.16 thorpej {
2102 1.16 thorpej const struct bge_revision *br;
2103 1.16 thorpej
2104 1.16 thorpej for (br = bge_revisions; br->br_name != NULL; br++) {
2105 1.51 fvdl if (br->br_chipid == chipid)
2106 1.51 fvdl return (br);
2107 1.51 fvdl }
2108 1.51 fvdl
2109 1.51 fvdl for (br = bge_majorrevs; br->br_name != NULL; br++) {
2110 1.51 fvdl if (br->br_chipid == BGE_ASICREV(chipid))
2111 1.16 thorpej return (br);
2112 1.16 thorpej }
2113 1.16 thorpej
2114 1.16 thorpej return (NULL);
2115 1.16 thorpej }
2116 1.16 thorpej
2117 1.7 thorpej static const struct bge_product {
2118 1.7 thorpej pci_vendor_id_t bp_vendor;
2119 1.7 thorpej pci_product_id_t bp_product;
2120 1.7 thorpej const char *bp_name;
2121 1.7 thorpej } bge_products[] = {
2122 1.7 thorpej /*
2123 1.7 thorpej * The BCM5700 documentation seems to indicate that the hardware
2124 1.7 thorpej * still has the Alteon vendor ID burned into it, though it
2125 1.7 thorpej * should always be overridden by the value in the EEPROM. We'll
2126 1.7 thorpej * check for it anyway.
2127 1.7 thorpej */
2128 1.7 thorpej { PCI_VENDOR_ALTEON,
2129 1.7 thorpej PCI_PRODUCT_ALTEON_BCM5700,
2130 1.51 fvdl "Broadcom BCM5700 Gigabit Ethernet",
2131 1.51 fvdl },
2132 1.7 thorpej { PCI_VENDOR_ALTEON,
2133 1.7 thorpej PCI_PRODUCT_ALTEON_BCM5701,
2134 1.51 fvdl "Broadcom BCM5701 Gigabit Ethernet",
2135 1.51 fvdl },
2136 1.7 thorpej
2137 1.7 thorpej { PCI_VENDOR_ALTIMA,
2138 1.7 thorpej PCI_PRODUCT_ALTIMA_AC1000,
2139 1.51 fvdl "Altima AC1000 Gigabit Ethernet",
2140 1.51 fvdl },
2141 1.14 enami { PCI_VENDOR_ALTIMA,
2142 1.14 enami PCI_PRODUCT_ALTIMA_AC1001,
2143 1.51 fvdl "Altima AC1001 Gigabit Ethernet",
2144 1.51 fvdl },
2145 1.7 thorpej { PCI_VENDOR_ALTIMA,
2146 1.7 thorpej PCI_PRODUCT_ALTIMA_AC9100,
2147 1.51 fvdl "Altima AC9100 Gigabit Ethernet",
2148 1.51 fvdl },
2149 1.7 thorpej
2150 1.7 thorpej { PCI_VENDOR_BROADCOM,
2151 1.7 thorpej PCI_PRODUCT_BROADCOM_BCM5700,
2152 1.51 fvdl "Broadcom BCM5700 Gigabit Ethernet",
2153 1.51 fvdl },
2154 1.7 thorpej { PCI_VENDOR_BROADCOM,
2155 1.7 thorpej PCI_PRODUCT_BROADCOM_BCM5701,
2156 1.51 fvdl "Broadcom BCM5701 Gigabit Ethernet",
2157 1.51 fvdl },
2158 1.24 matt { PCI_VENDOR_BROADCOM,
2159 1.24 matt PCI_PRODUCT_BROADCOM_BCM5702,
2160 1.51 fvdl "Broadcom BCM5702 Gigabit Ethernet",
2161 1.51 fvdl },
2162 1.24 matt { PCI_VENDOR_BROADCOM,
2163 1.24 matt PCI_PRODUCT_BROADCOM_BCM5702X,
2164 1.24 matt "Broadcom BCM5702X Gigabit Ethernet" },
2165 1.51 fvdl
2166 1.24 matt { PCI_VENDOR_BROADCOM,
2167 1.24 matt PCI_PRODUCT_BROADCOM_BCM5703,
2168 1.51 fvdl "Broadcom BCM5703 Gigabit Ethernet",
2169 1.51 fvdl },
2170 1.24 matt { PCI_VENDOR_BROADCOM,
2171 1.24 matt PCI_PRODUCT_BROADCOM_BCM5703X,
2172 1.51 fvdl "Broadcom BCM5703X Gigabit Ethernet",
2173 1.51 fvdl },
2174 1.55 pooka { PCI_VENDOR_BROADCOM,
2175 1.55 pooka PCI_PRODUCT_BROADCOM_BCM5703A3,
2176 1.55 pooka "Broadcom BCM5703A3 Gigabit Ethernet",
2177 1.55 pooka },
2178 1.51 fvdl
2179 1.25 jonathan { PCI_VENDOR_BROADCOM,
2180 1.25 jonathan PCI_PRODUCT_BROADCOM_BCM5704C,
2181 1.51 fvdl "Broadcom BCM5704C Dual Gigabit Ethernet",
2182 1.51 fvdl },
2183 1.25 jonathan { PCI_VENDOR_BROADCOM,
2184 1.25 jonathan PCI_PRODUCT_BROADCOM_BCM5704S,
2185 1.51 fvdl "Broadcom BCM5704S Dual Gigabit Ethernet",
2186 1.51 fvdl },
2187 1.51 fvdl
2188 1.51 fvdl { PCI_VENDOR_BROADCOM,
2189 1.51 fvdl PCI_PRODUCT_BROADCOM_BCM5705,
2190 1.51 fvdl "Broadcom BCM5705 Gigabit Ethernet",
2191 1.51 fvdl },
2192 1.51 fvdl { PCI_VENDOR_BROADCOM,
2193 1.79 jmmv PCI_PRODUCT_BROADCOM_BCM5705K,
2194 1.78 tacha "Broadcom BCM5705K Gigabit Ethernet",
2195 1.78 tacha },
2196 1.78 tacha { PCI_VENDOR_BROADCOM,
2197 1.51 fvdl PCI_PRODUCT_BROADCOM_BCM5705_ALT,
2198 1.51 fvdl "Broadcom BCM5705 Gigabit Ethernet",
2199 1.51 fvdl },
2200 1.44 hannken { PCI_VENDOR_BROADCOM,
2201 1.44 hannken PCI_PRODUCT_BROADCOM_BCM5705M,
2202 1.51 fvdl "Broadcom BCM5705M Gigabit Ethernet",
2203 1.51 fvdl },
2204 1.51 fvdl
2205 1.76 cube { PCI_VENDOR_BROADCOM,
2206 1.98 jonathan PCI_PRODUCT_BROADCOM_BCM5714,
2207 1.98 jonathan "Broadcom BCM5714/5715 Gigabit Ethernet",
2208 1.98 jonathan },
2209 1.98 jonathan
2210 1.98 jonathan { PCI_VENDOR_BROADCOM,
2211 1.80 fredb PCI_PRODUCT_BROADCOM_BCM5721,
2212 1.80 fredb "Broadcom BCM5721 Gigabit Ethernet",
2213 1.80 fredb },
2214 1.80 fredb
2215 1.80 fredb { PCI_VENDOR_BROADCOM,
2216 1.76 cube PCI_PRODUCT_BROADCOM_BCM5750,
2217 1.76 cube "Broadcom BCM5750 Gigabit Ethernet",
2218 1.76 cube },
2219 1.76 cube
2220 1.76 cube { PCI_VENDOR_BROADCOM,
2221 1.76 cube PCI_PRODUCT_BROADCOM_BCM5750M,
2222 1.76 cube "Broadcom BCM5750M Gigabit Ethernet",
2223 1.76 cube },
2224 1.76 cube
2225 1.76 cube { PCI_VENDOR_BROADCOM,
2226 1.76 cube PCI_PRODUCT_BROADCOM_BCM5751,
2227 1.76 cube "Broadcom BCM5751 Gigabit Ethernet",
2228 1.76 cube },
2229 1.76 cube
2230 1.91 gavan { PCI_VENDOR_BROADCOM,
2231 1.91 gavan PCI_PRODUCT_BROADCOM_BCM5751M,
2232 1.91 gavan "Broadcom BCM5751M Gigabit Ethernet",
2233 1.91 gavan },
2234 1.91 gavan
2235 1.98 jonathan { PCI_VENDOR_BROADCOM,
2236 1.98 jonathan PCI_PRODUCT_BROADCOM_BCM5752,
2237 1.98 jonathan "Broadcom BCM5752 Gigabit Ethernet",
2238 1.98 jonathan },
2239 1.98 jonathan
2240 1.51 fvdl { PCI_VENDOR_BROADCOM,
2241 1.70 tron PCI_PRODUCT_BROADCOM_BCM5782,
2242 1.70 tron "Broadcom BCM5782 Gigabit Ethernet",
2243 1.70 tron },
2244 1.70 tron { PCI_VENDOR_BROADCOM,
2245 1.70 tron PCI_PRODUCT_BROADCOM_BCM5788,
2246 1.70 tron "Broadcom BCM5788 Gigabit Ethernet",
2247 1.70 tron },
2248 1.97 fvdl { PCI_VENDOR_BROADCOM,
2249 1.97 fvdl PCI_PRODUCT_BROADCOM_BCM5789,
2250 1.97 fvdl "Broadcom BCM5789 Gigabit Ethernet",
2251 1.97 fvdl },
2252 1.70 tron
2253 1.70 tron { PCI_VENDOR_BROADCOM,
2254 1.51 fvdl PCI_PRODUCT_BROADCOM_BCM5901,
2255 1.51 fvdl "Broadcom BCM5901 Fast Ethernet",
2256 1.51 fvdl },
2257 1.51 fvdl { PCI_VENDOR_BROADCOM,
2258 1.51 fvdl PCI_PRODUCT_BROADCOM_BCM5901A2,
2259 1.51 fvdl "Broadcom BCM5901A2 Fast Ethernet",
2260 1.51 fvdl },
2261 1.51 fvdl
2262 1.7 thorpej { PCI_VENDOR_SCHNEIDERKOCH,
2263 1.7 thorpej PCI_PRODUCT_SCHNEIDERKOCH_SK_9DX1,
2264 1.51 fvdl "SysKonnect SK-9Dx1 Gigabit Ethernet",
2265 1.51 fvdl },
2266 1.7 thorpej
2267 1.7 thorpej { PCI_VENDOR_3COM,
2268 1.7 thorpej PCI_PRODUCT_3COM_3C996,
2269 1.51 fvdl "3Com 3c996 Gigabit Ethernet",
2270 1.51 fvdl },
2271 1.7 thorpej
2272 1.7 thorpej { 0,
2273 1.7 thorpej 0,
2274 1.7 thorpej NULL },
2275 1.7 thorpej };
2276 1.7 thorpej
2277 1.7 thorpej static const struct bge_product *
2278 1.7 thorpej bge_lookup(const struct pci_attach_args *pa)
2279 1.7 thorpej {
2280 1.7 thorpej const struct bge_product *bp;
2281 1.7 thorpej
2282 1.7 thorpej for (bp = bge_products; bp->bp_name != NULL; bp++) {
2283 1.7 thorpej if (PCI_VENDOR(pa->pa_id) == bp->bp_vendor &&
2284 1.7 thorpej PCI_PRODUCT(pa->pa_id) == bp->bp_product)
2285 1.7 thorpej return (bp);
2286 1.7 thorpej }
2287 1.7 thorpej
2288 1.7 thorpej return (NULL);
2289 1.7 thorpej }
2290 1.7 thorpej
2291 1.25 jonathan int
2292 1.25 jonathan bge_setpowerstate(sc, powerlevel)
2293 1.25 jonathan struct bge_softc *sc;
2294 1.25 jonathan int powerlevel;
2295 1.25 jonathan {
2296 1.25 jonathan #ifdef NOTYET
2297 1.25 jonathan u_int32_t pm_ctl = 0;
2298 1.25 jonathan
2299 1.25 jonathan /* XXX FIXME: make sure indirect accesses enabled? */
2300 1.25 jonathan pm_ctl = pci_conf_read(sc->bge_dev, BGE_PCI_MISC_CTL, 4);
2301 1.25 jonathan pm_ctl |= BGE_PCIMISCCTL_INDIRECT_ACCESS;
2302 1.25 jonathan pci_write_config(sc->bge_dev, BGE_PCI_MISC_CTL, pm_ctl, 4);
2303 1.25 jonathan
2304 1.25 jonathan /* clear the PME_assert bit and power state bits, enable PME */
2305 1.25 jonathan pm_ctl = pci_conf_read(sc->bge_dev, BGE_PCI_PWRMGMT_CMD, 2);
2306 1.25 jonathan pm_ctl &= ~PCIM_PSTAT_DMASK;
2307 1.25 jonathan pm_ctl |= (1 << 8);
2308 1.25 jonathan
2309 1.25 jonathan if (powerlevel == 0) {
2310 1.25 jonathan pm_ctl |= PCIM_PSTAT_D0;
2311 1.25 jonathan pci_write_config(sc->bge_dev, BGE_PCI_PWRMGMT_CMD,
2312 1.25 jonathan pm_ctl, 2);
2313 1.25 jonathan DELAY(10000);
2314 1.27 jonathan CSR_WRITE_4(sc, BGE_MISC_LOCAL_CTL, sc->bge_local_ctrl_reg);
2315 1.25 jonathan DELAY(10000);
2316 1.25 jonathan
2317 1.25 jonathan #ifdef NOTYET
2318 1.25 jonathan /* XXX FIXME: write 0x02 to phy aux_Ctrl reg */
2319 1.25 jonathan bge_miibus_writereg(sc->bge_dev, 1, 0x18, 0x02);
2320 1.25 jonathan #endif
2321 1.25 jonathan DELAY(40); DELAY(40); DELAY(40);
2322 1.25 jonathan DELAY(10000); /* above not quite adequate on 5700 */
2323 1.25 jonathan return 0;
2324 1.25 jonathan }
2325 1.25 jonathan
2326 1.25 jonathan
2327 1.25 jonathan /*
2328 1.25 jonathan * Entering ACPI power states D1-D3 is achieved by wiggling
2329 1.25 jonathan * GMII gpio pins. Example code assumes all hardware vendors
2330 1.25 jonathan * followed Broadom's sample pcb layout. Until we verify that
2331 1.25 jonathan * for all supported OEM cards, states D1-D3 are unsupported.
2332 1.25 jonathan */
2333 1.25 jonathan printf("%s: power state %d unimplemented; check GPIO pins\n",
2334 1.25 jonathan sc->bge_dev.dv_xname, powerlevel);
2335 1.25 jonathan #endif
2336 1.25 jonathan return EOPNOTSUPP;
2337 1.25 jonathan }
2338 1.25 jonathan
2339 1.25 jonathan
2340 1.1 fvdl /*
2341 1.1 fvdl * Probe for a Broadcom chip. Check the PCI vendor and device IDs
2342 1.1 fvdl * against our list and return its name if we find a match. Note
2343 1.1 fvdl * that since the Broadcom controller contains VPD support, we
2344 1.1 fvdl * can get the device name string from the controller itself instead
2345 1.1 fvdl * of the compiled-in string. This is a little slow, but it guarantees
2346 1.1 fvdl * we'll always announce the right product name.
2347 1.1 fvdl */
2348 1.1 fvdl int
2349 1.1 fvdl bge_probe(parent, match, aux)
2350 1.1 fvdl struct device *parent;
2351 1.1 fvdl struct cfdata *match;
2352 1.1 fvdl void *aux;
2353 1.1 fvdl {
2354 1.1 fvdl struct pci_attach_args *pa = (struct pci_attach_args *)aux;
2355 1.1 fvdl
2356 1.7 thorpej if (bge_lookup(pa) != NULL)
2357 1.1 fvdl return (1);
2358 1.1 fvdl
2359 1.1 fvdl return (0);
2360 1.1 fvdl }
2361 1.1 fvdl
2362 1.1 fvdl void
2363 1.1 fvdl bge_attach(parent, self, aux)
2364 1.1 fvdl struct device *parent, *self;
2365 1.1 fvdl void *aux;
2366 1.1 fvdl {
2367 1.1 fvdl struct bge_softc *sc = (struct bge_softc *)self;
2368 1.1 fvdl struct pci_attach_args *pa = aux;
2369 1.7 thorpej const struct bge_product *bp;
2370 1.16 thorpej const struct bge_revision *br;
2371 1.1 fvdl pci_chipset_tag_t pc = pa->pa_pc;
2372 1.1 fvdl pci_intr_handle_t ih;
2373 1.1 fvdl const char *intrstr = NULL;
2374 1.1 fvdl bus_dma_segment_t seg;
2375 1.1 fvdl int rseg;
2376 1.1 fvdl u_int32_t hwcfg = 0;
2377 1.24 matt u_int32_t mac_addr = 0;
2378 1.1 fvdl u_int32_t command;
2379 1.1 fvdl struct ifnet *ifp;
2380 1.1 fvdl caddr_t kva;
2381 1.1 fvdl u_char eaddr[ETHER_ADDR_LEN];
2382 1.1 fvdl pcireg_t memtype;
2383 1.1 fvdl bus_addr_t memaddr;
2384 1.1 fvdl bus_size_t memsize;
2385 1.25 jonathan u_int32_t pm_ctl;
2386 1.87 perry
2387 1.7 thorpej bp = bge_lookup(pa);
2388 1.7 thorpej KASSERT(bp != NULL);
2389 1.7 thorpej
2390 1.1 fvdl sc->bge_pa = *pa;
2391 1.1 fvdl
2392 1.30 thorpej aprint_naive(": Ethernet controller\n");
2393 1.30 thorpej aprint_normal(": %s\n", bp->bp_name);
2394 1.1 fvdl
2395 1.1 fvdl /*
2396 1.1 fvdl * Map control/status registers.
2397 1.1 fvdl */
2398 1.1 fvdl DPRINTFN(5, ("Map control/status regs\n"));
2399 1.1 fvdl command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG);
2400 1.1 fvdl command |= PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_MASTER_ENABLE;
2401 1.1 fvdl pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, command);
2402 1.1 fvdl command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG);
2403 1.1 fvdl
2404 1.1 fvdl if (!(command & PCI_COMMAND_MEM_ENABLE)) {
2405 1.30 thorpej aprint_error("%s: failed to enable memory mapping!\n",
2406 1.1 fvdl sc->bge_dev.dv_xname);
2407 1.1 fvdl return;
2408 1.1 fvdl }
2409 1.1 fvdl
2410 1.1 fvdl DPRINTFN(5, ("pci_mem_find\n"));
2411 1.1 fvdl memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, BGE_PCI_BAR0);
2412 1.1 fvdl switch (memtype) {
2413 1.29 itojun case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT:
2414 1.29 itojun case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT:
2415 1.1 fvdl if (pci_mapreg_map(pa, BGE_PCI_BAR0,
2416 1.29 itojun memtype, 0, &sc->bge_btag, &sc->bge_bhandle,
2417 1.1 fvdl &memaddr, &memsize) == 0)
2418 1.1 fvdl break;
2419 1.1 fvdl default:
2420 1.30 thorpej aprint_error("%s: can't find mem space\n",
2421 1.1 fvdl sc->bge_dev.dv_xname);
2422 1.1 fvdl return;
2423 1.1 fvdl }
2424 1.1 fvdl
2425 1.1 fvdl DPRINTFN(5, ("pci_intr_map\n"));
2426 1.1 fvdl if (pci_intr_map(pa, &ih)) {
2427 1.30 thorpej aprint_error("%s: couldn't map interrupt\n",
2428 1.1 fvdl sc->bge_dev.dv_xname);
2429 1.1 fvdl return;
2430 1.1 fvdl }
2431 1.1 fvdl
2432 1.1 fvdl DPRINTFN(5, ("pci_intr_string\n"));
2433 1.1 fvdl intrstr = pci_intr_string(pc, ih);
2434 1.1 fvdl
2435 1.1 fvdl DPRINTFN(5, ("pci_intr_establish\n"));
2436 1.1 fvdl sc->bge_intrhand = pci_intr_establish(pc, ih, IPL_NET, bge_intr, sc);
2437 1.1 fvdl
2438 1.1 fvdl if (sc->bge_intrhand == NULL) {
2439 1.30 thorpej aprint_error("%s: couldn't establish interrupt",
2440 1.1 fvdl sc->bge_dev.dv_xname);
2441 1.1 fvdl if (intrstr != NULL)
2442 1.30 thorpej aprint_normal(" at %s", intrstr);
2443 1.30 thorpej aprint_normal("\n");
2444 1.1 fvdl return;
2445 1.1 fvdl }
2446 1.30 thorpej aprint_normal("%s: interrupting at %s\n",
2447 1.30 thorpej sc->bge_dev.dv_xname, intrstr);
2448 1.1 fvdl
2449 1.25 jonathan /*
2450 1.25 jonathan * Kludge for 5700 Bx bug: a hardware bug (PCIX byte enable?)
2451 1.25 jonathan * can clobber the chip's PCI config-space power control registers,
2452 1.25 jonathan * leaving the card in D3 powersave state.
2453 1.25 jonathan * We do not have memory-mapped registers in this state,
2454 1.25 jonathan * so force device into D0 state before starting initialization.
2455 1.25 jonathan */
2456 1.25 jonathan pm_ctl = pci_conf_read(pc, pa->pa_tag, BGE_PCI_PWRMGMT_CMD);
2457 1.25 jonathan pm_ctl &= ~(PCI_PWR_D0|PCI_PWR_D1|PCI_PWR_D2|PCI_PWR_D3);
2458 1.25 jonathan pm_ctl |= (1 << 8) | PCI_PWR_D0 ; /* D0 state */
2459 1.25 jonathan pci_conf_write(pc, pa->pa_tag, BGE_PCI_PWRMGMT_CMD, pm_ctl);
2460 1.25 jonathan DELAY(1000); /* 27 usec is allegedly sufficent */
2461 1.25 jonathan
2462 1.76 cube /*
2463 1.76 cube * Save ASIC rev. Look up any quirks associated with this
2464 1.76 cube * ASIC.
2465 1.76 cube */
2466 1.76 cube sc->bge_chipid =
2467 1.76 cube pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_MISC_CTL) &
2468 1.76 cube BGE_PCIMISCCTL_ASICREV;
2469 1.76 cube
2470 1.76 cube /*
2471 1.76 cube * Detect PCI-Express devices
2472 1.76 cube * XXX: guessed from Linux/FreeBSD; no documentation
2473 1.76 cube */
2474 1.76 cube if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5750 &&
2475 1.76 cube pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_PCIEXPRESS,
2476 1.76 cube NULL, NULL) != 0)
2477 1.76 cube sc->bge_pcie = 1;
2478 1.76 cube else
2479 1.76 cube sc->bge_pcie = 0;
2480 1.76 cube
2481 1.1 fvdl /* Try to reset the chip. */
2482 1.1 fvdl DPRINTFN(5, ("bge_reset\n"));
2483 1.1 fvdl bge_reset(sc);
2484 1.1 fvdl
2485 1.1 fvdl if (bge_chipinit(sc)) {
2486 1.30 thorpej aprint_error("%s: chip initialization failed\n",
2487 1.1 fvdl sc->bge_dev.dv_xname);
2488 1.1 fvdl bge_release_resources(sc);
2489 1.1 fvdl return;
2490 1.1 fvdl }
2491 1.1 fvdl
2492 1.1 fvdl /*
2493 1.1 fvdl * Get station address from the EEPROM.
2494 1.1 fvdl */
2495 1.24 matt mac_addr = bge_readmem_ind(sc, 0x0c14);
2496 1.24 matt if ((mac_addr >> 16) == 0x484b) {
2497 1.24 matt eaddr[0] = (u_char)(mac_addr >> 8);
2498 1.24 matt eaddr[1] = (u_char)(mac_addr >> 0);
2499 1.24 matt mac_addr = bge_readmem_ind(sc, 0x0c18);
2500 1.24 matt eaddr[2] = (u_char)(mac_addr >> 24);
2501 1.24 matt eaddr[3] = (u_char)(mac_addr >> 16);
2502 1.24 matt eaddr[4] = (u_char)(mac_addr >> 8);
2503 1.24 matt eaddr[5] = (u_char)(mac_addr >> 0);
2504 1.24 matt } else if (bge_read_eeprom(sc, (caddr_t)eaddr,
2505 1.1 fvdl BGE_EE_MAC_OFFSET + 2, ETHER_ADDR_LEN)) {
2506 1.30 thorpej aprint_error("%s: failed to read station address\n",
2507 1.23 kristerw sc->bge_dev.dv_xname);
2508 1.1 fvdl bge_release_resources(sc);
2509 1.1 fvdl return;
2510 1.1 fvdl }
2511 1.1 fvdl
2512 1.51 fvdl br = bge_lookup_rev(sc->bge_chipid);
2513 1.30 thorpej aprint_normal("%s: ", sc->bge_dev.dv_xname);
2514 1.51 fvdl
2515 1.16 thorpej if (br == NULL) {
2516 1.56 pooka aprint_normal("unknown ASIC (0x%04x)", sc->bge_chipid >> 16);
2517 1.52 fvdl sc->bge_quirks = 0;
2518 1.16 thorpej } else {
2519 1.56 pooka aprint_normal("ASIC %s (0x%04x)",
2520 1.56 pooka br->br_name, sc->bge_chipid >> 16);
2521 1.51 fvdl sc->bge_quirks |= br->br_quirks;
2522 1.16 thorpej }
2523 1.30 thorpej aprint_normal(", Ethernet address %s\n", ether_sprintf(eaddr));
2524 1.1 fvdl
2525 1.1 fvdl /* Allocate the general information block and ring buffers. */
2526 1.41 fvdl if (pci_dma64_available(pa))
2527 1.41 fvdl sc->bge_dmatag = pa->pa_dmat64;
2528 1.41 fvdl else
2529 1.41 fvdl sc->bge_dmatag = pa->pa_dmat;
2530 1.1 fvdl DPRINTFN(5, ("bus_dmamem_alloc\n"));
2531 1.1 fvdl if (bus_dmamem_alloc(sc->bge_dmatag, sizeof(struct bge_ring_data),
2532 1.1 fvdl PAGE_SIZE, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) {
2533 1.30 thorpej aprint_error("%s: can't alloc rx buffers\n",
2534 1.30 thorpej sc->bge_dev.dv_xname);
2535 1.1 fvdl return;
2536 1.1 fvdl }
2537 1.1 fvdl DPRINTFN(5, ("bus_dmamem_map\n"));
2538 1.1 fvdl if (bus_dmamem_map(sc->bge_dmatag, &seg, rseg,
2539 1.1 fvdl sizeof(struct bge_ring_data), &kva,
2540 1.1 fvdl BUS_DMA_NOWAIT)) {
2541 1.39 wiz aprint_error("%s: can't map DMA buffers (%d bytes)\n",
2542 1.1 fvdl sc->bge_dev.dv_xname, (int)sizeof(struct bge_ring_data));
2543 1.1 fvdl bus_dmamem_free(sc->bge_dmatag, &seg, rseg);
2544 1.1 fvdl return;
2545 1.1 fvdl }
2546 1.1 fvdl DPRINTFN(5, ("bus_dmamem_create\n"));
2547 1.1 fvdl if (bus_dmamap_create(sc->bge_dmatag, sizeof(struct bge_ring_data), 1,
2548 1.1 fvdl sizeof(struct bge_ring_data), 0,
2549 1.1 fvdl BUS_DMA_NOWAIT, &sc->bge_ring_map)) {
2550 1.39 wiz aprint_error("%s: can't create DMA map\n",
2551 1.30 thorpej sc->bge_dev.dv_xname);
2552 1.1 fvdl bus_dmamem_unmap(sc->bge_dmatag, kva,
2553 1.1 fvdl sizeof(struct bge_ring_data));
2554 1.1 fvdl bus_dmamem_free(sc->bge_dmatag, &seg, rseg);
2555 1.1 fvdl return;
2556 1.1 fvdl }
2557 1.1 fvdl DPRINTFN(5, ("bus_dmamem_load\n"));
2558 1.1 fvdl if (bus_dmamap_load(sc->bge_dmatag, sc->bge_ring_map, kva,
2559 1.1 fvdl sizeof(struct bge_ring_data), NULL,
2560 1.1 fvdl BUS_DMA_NOWAIT)) {
2561 1.1 fvdl bus_dmamap_destroy(sc->bge_dmatag, sc->bge_ring_map);
2562 1.1 fvdl bus_dmamem_unmap(sc->bge_dmatag, kva,
2563 1.1 fvdl sizeof(struct bge_ring_data));
2564 1.1 fvdl bus_dmamem_free(sc->bge_dmatag, &seg, rseg);
2565 1.1 fvdl return;
2566 1.1 fvdl }
2567 1.1 fvdl
2568 1.1 fvdl DPRINTFN(5, ("bzero\n"));
2569 1.1 fvdl sc->bge_rdata = (struct bge_ring_data *)kva;
2570 1.1 fvdl
2571 1.19 mjl memset(sc->bge_rdata, 0, sizeof(struct bge_ring_data));
2572 1.1 fvdl
2573 1.1 fvdl /* Try to allocate memory for jumbo buffers. */
2574 1.44 hannken if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) {
2575 1.44 hannken if (bge_alloc_jumbo_mem(sc)) {
2576 1.44 hannken aprint_error("%s: jumbo buffer allocation failed\n",
2577 1.44 hannken sc->bge_dev.dv_xname);
2578 1.44 hannken } else
2579 1.44 hannken sc->ethercom.ec_capabilities |= ETHERCAP_JUMBO_MTU;
2580 1.44 hannken }
2581 1.1 fvdl
2582 1.1 fvdl /* Set default tuneable values. */
2583 1.1 fvdl sc->bge_stat_ticks = BGE_TICKS_PER_SEC;
2584 1.1 fvdl sc->bge_rx_coal_ticks = 150;
2585 1.25 jonathan sc->bge_rx_max_coal_bds = 64;
2586 1.25 jonathan #ifdef ORIG_WPAUL_VALUES
2587 1.1 fvdl sc->bge_tx_coal_ticks = 150;
2588 1.1 fvdl sc->bge_tx_max_coal_bds = 128;
2589 1.25 jonathan #else
2590 1.25 jonathan sc->bge_tx_coal_ticks = 300;
2591 1.25 jonathan sc->bge_tx_max_coal_bds = 400;
2592 1.25 jonathan #endif
2593 1.95 jonathan if (sc->bge_quirks & BGE_QUIRK_5705_CORE) {
2594 1.95 jonathan sc->bge_tx_coal_ticks = (12 * 5);
2595 1.95 jonathan sc->bge_rx_max_coal_bds = (12 * 5);
2596 1.95 jonathan aprint_error("%s: setting short Tx thresholds\n",
2597 1.95 jonathan sc->bge_dev.dv_xname);
2598 1.95 jonathan }
2599 1.1 fvdl
2600 1.1 fvdl /* Set up ifnet structure */
2601 1.1 fvdl ifp = &sc->ethercom.ec_if;
2602 1.1 fvdl ifp->if_softc = sc;
2603 1.1 fvdl ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
2604 1.1 fvdl ifp->if_ioctl = bge_ioctl;
2605 1.1 fvdl ifp->if_start = bge_start;
2606 1.1 fvdl ifp->if_init = bge_init;
2607 1.1 fvdl ifp->if_watchdog = bge_watchdog;
2608 1.42 ragge IFQ_SET_MAXLEN(&ifp->if_snd, max(BGE_TX_RING_CNT - 1, IFQ_MAXLEN));
2609 1.1 fvdl IFQ_SET_READY(&ifp->if_snd);
2610 1.1 fvdl DPRINTFN(5, ("bcopy\n"));
2611 1.1 fvdl strcpy(ifp->if_xname, sc->bge_dev.dv_xname);
2612 1.1 fvdl
2613 1.18 thorpej if ((sc->bge_quirks & BGE_QUIRK_CSUM_BROKEN) == 0)
2614 1.18 thorpej sc->ethercom.ec_if.if_capabilities |=
2615 1.88 yamt IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx |
2616 1.88 yamt IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx |
2617 1.88 yamt IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx;
2618 1.87 perry sc->ethercom.ec_capabilities |=
2619 1.1 fvdl ETHERCAP_VLAN_HWTAGGING | ETHERCAP_VLAN_MTU;
2620 1.1 fvdl
2621 1.95 jonathan if (sc->bge_pcie)
2622 1.95 jonathan sc->ethercom.ec_if.if_capabilities |= IFCAP_TSOv4;
2623 1.95 jonathan
2624 1.1 fvdl /*
2625 1.1 fvdl * Do MII setup.
2626 1.1 fvdl */
2627 1.1 fvdl DPRINTFN(5, ("mii setup\n"));
2628 1.1 fvdl sc->bge_mii.mii_ifp = ifp;
2629 1.1 fvdl sc->bge_mii.mii_readreg = bge_miibus_readreg;
2630 1.1 fvdl sc->bge_mii.mii_writereg = bge_miibus_writereg;
2631 1.1 fvdl sc->bge_mii.mii_statchg = bge_miibus_statchg;
2632 1.1 fvdl
2633 1.1 fvdl /*
2634 1.1 fvdl * Figure out what sort of media we have by checking the
2635 1.35 jonathan * hardware config word in the first 32k of NIC internal memory,
2636 1.35 jonathan * or fall back to the config word in the EEPROM. Note: on some BCM5700
2637 1.1 fvdl * cards, this value appears to be unset. If that's the
2638 1.1 fvdl * case, we have to rely on identifying the NIC by its PCI
2639 1.1 fvdl * subsystem ID, as we do below for the SysKonnect SK-9D41.
2640 1.1 fvdl */
2641 1.35 jonathan if (bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_SIG) == BGE_MAGIC_NUMBER) {
2642 1.35 jonathan hwcfg = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_NICCFG);
2643 1.35 jonathan } else {
2644 1.35 jonathan bge_read_eeprom(sc, (caddr_t)&hwcfg,
2645 1.1 fvdl BGE_EE_HWCFG_OFFSET, sizeof(hwcfg));
2646 1.35 jonathan hwcfg = be32toh(hwcfg);
2647 1.35 jonathan }
2648 1.35 jonathan if ((hwcfg & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER)
2649 1.1 fvdl sc->bge_tbi = 1;
2650 1.1 fvdl
2651 1.1 fvdl /* The SysKonnect SK-9D41 is a 1000baseSX card. */
2652 1.1 fvdl if ((pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_SUBSYS) >> 16) ==
2653 1.1 fvdl SK_SUBSYSID_9D41)
2654 1.1 fvdl sc->bge_tbi = 1;
2655 1.1 fvdl
2656 1.1 fvdl if (sc->bge_tbi) {
2657 1.1 fvdl ifmedia_init(&sc->bge_ifmedia, IFM_IMASK, bge_ifmedia_upd,
2658 1.1 fvdl bge_ifmedia_sts);
2659 1.1 fvdl ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL);
2660 1.1 fvdl ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_1000_SX|IFM_FDX,
2661 1.1 fvdl 0, NULL);
2662 1.1 fvdl ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL);
2663 1.1 fvdl ifmedia_set(&sc->bge_ifmedia, IFM_ETHER|IFM_AUTO);
2664 1.1 fvdl } else {
2665 1.1 fvdl /*
2666 1.1 fvdl * Do transceiver setup.
2667 1.1 fvdl */
2668 1.1 fvdl ifmedia_init(&sc->bge_mii.mii_media, 0, bge_ifmedia_upd,
2669 1.1 fvdl bge_ifmedia_sts);
2670 1.1 fvdl mii_attach(&sc->bge_dev, &sc->bge_mii, 0xffffffff,
2671 1.69 thorpej MII_PHY_ANY, MII_OFFSET_ANY,
2672 1.69 thorpej MIIF_FORCEANEG|MIIF_DOPAUSE);
2673 1.87 perry
2674 1.1 fvdl if (LIST_FIRST(&sc->bge_mii.mii_phys) == NULL) {
2675 1.1 fvdl printf("%s: no PHY found!\n", sc->bge_dev.dv_xname);
2676 1.1 fvdl ifmedia_add(&sc->bge_mii.mii_media,
2677 1.1 fvdl IFM_ETHER|IFM_MANUAL, 0, NULL);
2678 1.1 fvdl ifmedia_set(&sc->bge_mii.mii_media,
2679 1.1 fvdl IFM_ETHER|IFM_MANUAL);
2680 1.1 fvdl } else
2681 1.1 fvdl ifmedia_set(&sc->bge_mii.mii_media,
2682 1.1 fvdl IFM_ETHER|IFM_AUTO);
2683 1.1 fvdl }
2684 1.1 fvdl
2685 1.1 fvdl /*
2686 1.37 jonathan * When using the BCM5701 in PCI-X mode, data corruption has
2687 1.37 jonathan * been observed in the first few bytes of some received packets.
2688 1.37 jonathan * Aligning the packet buffer in memory eliminates the corruption.
2689 1.37 jonathan * Unfortunately, this misaligns the packet payloads. On platforms
2690 1.37 jonathan * which do not support unaligned accesses, we will realign the
2691 1.37 jonathan * payloads by copying the received packets.
2692 1.37 jonathan */
2693 1.37 jonathan if (sc->bge_quirks & BGE_QUIRK_PCIX_DMA_ALIGN_BUG) {
2694 1.37 jonathan /* If in PCI-X mode, work around the alignment bug. */
2695 1.37 jonathan if ((pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_PCISTATE) &
2696 1.37 jonathan (BGE_PCISTATE_PCI_BUSMODE | BGE_PCISTATE_PCI_BUSSPEED)) ==
2697 1.37 jonathan BGE_PCISTATE_PCI_BUSSPEED)
2698 1.37 jonathan sc->bge_rx_alignment_bug = 1;
2699 1.37 jonathan }
2700 1.37 jonathan
2701 1.37 jonathan /*
2702 1.1 fvdl * Call MI attach routine.
2703 1.1 fvdl */
2704 1.1 fvdl DPRINTFN(5, ("if_attach\n"));
2705 1.1 fvdl if_attach(ifp);
2706 1.1 fvdl DPRINTFN(5, ("ether_ifattach\n"));
2707 1.1 fvdl ether_ifattach(ifp, eaddr);
2708 1.72 thorpej #ifdef BGE_EVENT_COUNTERS
2709 1.72 thorpej /*
2710 1.72 thorpej * Attach event counters.
2711 1.72 thorpej */
2712 1.72 thorpej evcnt_attach_dynamic(&sc->bge_ev_intr, EVCNT_TYPE_INTR,
2713 1.72 thorpej NULL, sc->bge_dev.dv_xname, "intr");
2714 1.72 thorpej evcnt_attach_dynamic(&sc->bge_ev_tx_xoff, EVCNT_TYPE_MISC,
2715 1.72 thorpej NULL, sc->bge_dev.dv_xname, "tx_xoff");
2716 1.72 thorpej evcnt_attach_dynamic(&sc->bge_ev_tx_xon, EVCNT_TYPE_MISC,
2717 1.72 thorpej NULL, sc->bge_dev.dv_xname, "tx_xon");
2718 1.72 thorpej evcnt_attach_dynamic(&sc->bge_ev_rx_xoff, EVCNT_TYPE_MISC,
2719 1.72 thorpej NULL, sc->bge_dev.dv_xname, "rx_xoff");
2720 1.72 thorpej evcnt_attach_dynamic(&sc->bge_ev_rx_xon, EVCNT_TYPE_MISC,
2721 1.72 thorpej NULL, sc->bge_dev.dv_xname, "rx_xon");
2722 1.72 thorpej evcnt_attach_dynamic(&sc->bge_ev_rx_macctl, EVCNT_TYPE_MISC,
2723 1.72 thorpej NULL, sc->bge_dev.dv_xname, "rx_macctl");
2724 1.72 thorpej evcnt_attach_dynamic(&sc->bge_ev_xoffentered, EVCNT_TYPE_MISC,
2725 1.72 thorpej NULL, sc->bge_dev.dv_xname, "xoffentered");
2726 1.72 thorpej #endif /* BGE_EVENT_COUNTERS */
2727 1.1 fvdl DPRINTFN(5, ("callout_init\n"));
2728 1.1 fvdl callout_init(&sc->bge_timeout);
2729 1.82 jmcneill
2730 1.82 jmcneill sc->bge_powerhook = powerhook_establish(bge_powerhook, sc);
2731 1.82 jmcneill if (sc->bge_powerhook == NULL)
2732 1.82 jmcneill printf("%s: WARNING: unable to establish PCI power hook\n",
2733 1.82 jmcneill sc->bge_dev.dv_xname);
2734 1.1 fvdl }
2735 1.1 fvdl
2736 1.1 fvdl void
2737 1.1 fvdl bge_release_resources(sc)
2738 1.1 fvdl struct bge_softc *sc;
2739 1.1 fvdl {
2740 1.1 fvdl if (sc->bge_vpd_prodname != NULL)
2741 1.1 fvdl free(sc->bge_vpd_prodname, M_DEVBUF);
2742 1.1 fvdl
2743 1.1 fvdl if (sc->bge_vpd_readonly != NULL)
2744 1.1 fvdl free(sc->bge_vpd_readonly, M_DEVBUF);
2745 1.1 fvdl }
2746 1.1 fvdl
2747 1.1 fvdl void
2748 1.1 fvdl bge_reset(sc)
2749 1.1 fvdl struct bge_softc *sc;
2750 1.1 fvdl {
2751 1.1 fvdl struct pci_attach_args *pa = &sc->bge_pa;
2752 1.61 jonathan u_int32_t cachesize, command, pcistate, new_pcistate;
2753 1.76 cube int i, val;
2754 1.1 fvdl
2755 1.1 fvdl /* Save some important PCI state. */
2756 1.1 fvdl cachesize = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_CACHESZ);
2757 1.1 fvdl command = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_CMD);
2758 1.1 fvdl pcistate = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_PCISTATE);
2759 1.1 fvdl
2760 1.1 fvdl pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_MISC_CTL,
2761 1.1 fvdl BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR|
2762 1.1 fvdl BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_PCISTATE_RW);
2763 1.1 fvdl
2764 1.76 cube val = BGE_MISCCFG_RESET_CORE_CLOCKS | (65<<1);
2765 1.76 cube /*
2766 1.76 cube * XXX: from FreeBSD/Linux; no documentation
2767 1.76 cube */
2768 1.76 cube if (sc->bge_pcie) {
2769 1.76 cube if (CSR_READ_4(sc, BGE_PCIE_CTL1) == 0x60)
2770 1.76 cube CSR_WRITE_4(sc, BGE_PCIE_CTL1, 0x20);
2771 1.76 cube if (sc->bge_chipid != BGE_CHIPID_BCM5750_A0) {
2772 1.76 cube /* No idea what that actually means */
2773 1.76 cube CSR_WRITE_4(sc, BGE_MISC_CFG, 1 << 29);
2774 1.76 cube val |= (1<<29);
2775 1.76 cube }
2776 1.76 cube }
2777 1.76 cube
2778 1.1 fvdl /* Issue global reset */
2779 1.76 cube bge_writereg_ind(sc, BGE_MISC_CFG, val);
2780 1.1 fvdl
2781 1.1 fvdl DELAY(1000);
2782 1.1 fvdl
2783 1.76 cube /*
2784 1.76 cube * XXX: from FreeBSD/Linux; no documentation
2785 1.76 cube */
2786 1.76 cube if (sc->bge_pcie) {
2787 1.76 cube if (sc->bge_chipid == BGE_CHIPID_BCM5750_A0) {
2788 1.76 cube pcireg_t reg;
2789 1.76 cube
2790 1.76 cube DELAY(500000);
2791 1.76 cube /* XXX: Magic Numbers */
2792 1.76 cube reg = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_UNKNOWN0);
2793 1.76 cube pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_UNKNOWN0,
2794 1.76 cube reg | (1 << 15));
2795 1.76 cube }
2796 1.95 jonathan /*
2797 1.95 jonathan * XXX: Magic Numbers.
2798 1.95 jonathan * Sets maximal PCI-e payload and clears any PCI-e errors.
2799 1.95 jonathan * Should be replaced with references to PCI config-space
2800 1.95 jonathan * capability block for PCI-Express.
2801 1.95 jonathan */
2802 1.95 jonathan pci_conf_write(pa->pa_pc, pa->pa_tag,
2803 1.95 jonathan BGE_PCI_CONF_DEV_CTRL, 0xf5000);
2804 1.95 jonathan
2805 1.76 cube }
2806 1.76 cube
2807 1.1 fvdl /* Reset some of the PCI state that got zapped by reset */
2808 1.1 fvdl pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_MISC_CTL,
2809 1.1 fvdl BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR|
2810 1.1 fvdl BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_PCISTATE_RW);
2811 1.1 fvdl pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_CMD, command);
2812 1.1 fvdl pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_CACHESZ, cachesize);
2813 1.1 fvdl bge_writereg_ind(sc, BGE_MISC_CFG, (65 << 1));
2814 1.1 fvdl
2815 1.1 fvdl /* Enable memory arbiter. */
2816 1.44 hannken if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) {
2817 1.99 jonathan uint32_t marbmode = 0;
2818 1.99 jonathan if (BGE_IS_5714_FAMILY(sc)) {
2819 1.100 jonathan marbmode = CSR_READ_4(sc, BGE_MARB_MODE);
2820 1.99 jonathan }
2821 1.99 jonathan CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE | marbmode);
2822 1.44 hannken }
2823 1.1 fvdl
2824 1.1 fvdl /*
2825 1.1 fvdl * Prevent PXE restart: write a magic number to the
2826 1.1 fvdl * general communications memory at 0xB50.
2827 1.1 fvdl */
2828 1.1 fvdl bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM, BGE_MAGIC_NUMBER);
2829 1.1 fvdl
2830 1.1 fvdl /*
2831 1.1 fvdl * Poll the value location we just wrote until
2832 1.1 fvdl * we see the 1's complement of the magic number.
2833 1.1 fvdl * This indicates that the firmware initialization
2834 1.1 fvdl * is complete.
2835 1.1 fvdl */
2836 1.95 jonathan for (i = 0; i < BGE_TIMEOUT; i++) {
2837 1.1 fvdl val = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM);
2838 1.1 fvdl if (val == ~BGE_MAGIC_NUMBER)
2839 1.1 fvdl break;
2840 1.1 fvdl DELAY(1000);
2841 1.1 fvdl }
2842 1.1 fvdl
2843 1.95 jonathan if (i >= BGE_TIMEOUT) {
2844 1.1 fvdl printf("%s: firmware handshake timed out, val = %x\n",
2845 1.1 fvdl sc->bge_dev.dv_xname, val);
2846 1.95 jonathan /*
2847 1.95 jonathan * XXX: occasionally fired on bcm5721, but without
2848 1.95 jonathan * apparent harm. For now, keep going if we timeout
2849 1.95 jonathan * against PCI-E devices.
2850 1.95 jonathan */
2851 1.95 jonathan if (!sc->bge_pcie)
2852 1.95 jonathan return;
2853 1.1 fvdl }
2854 1.1 fvdl
2855 1.1 fvdl /*
2856 1.1 fvdl * XXX Wait for the value of the PCISTATE register to
2857 1.1 fvdl * return to its original pre-reset state. This is a
2858 1.1 fvdl * fairly good indicator of reset completion. If we don't
2859 1.1 fvdl * wait for the reset to fully complete, trying to read
2860 1.1 fvdl * from the device's non-PCI registers may yield garbage
2861 1.1 fvdl * results.
2862 1.1 fvdl */
2863 1.1 fvdl for (i = 0; i < BGE_TIMEOUT; i++) {
2864 1.61 jonathan new_pcistate = pci_conf_read(pa->pa_pc, pa->pa_tag,
2865 1.61 jonathan BGE_PCI_PCISTATE);
2866 1.87 perry if ((new_pcistate & ~BGE_PCISTATE_RESERVED) ==
2867 1.62 jonathan (pcistate & ~BGE_PCISTATE_RESERVED))
2868 1.1 fvdl break;
2869 1.1 fvdl DELAY(10);
2870 1.1 fvdl }
2871 1.87 perry if ((new_pcistate & ~BGE_PCISTATE_RESERVED) !=
2872 1.62 jonathan (pcistate & ~BGE_PCISTATE_RESERVED)) {
2873 1.61 jonathan printf("%s: pcistate failed to revert\n",
2874 1.61 jonathan sc->bge_dev.dv_xname);
2875 1.61 jonathan }
2876 1.1 fvdl
2877 1.76 cube /* XXX: from FreeBSD/Linux; no documentation */
2878 1.76 cube if (sc->bge_pcie && sc->bge_chipid != BGE_CHIPID_BCM5750_A0)
2879 1.76 cube CSR_WRITE_4(sc, BGE_PCIE_CTL0, CSR_READ_4(sc, BGE_PCIE_CTL0) | (1<<25));
2880 1.76 cube
2881 1.1 fvdl /* Enable memory arbiter. */
2882 1.44 hannken if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) {
2883 1.99 jonathan uint32_t marbmode = 0;
2884 1.99 jonathan if (BGE_IS_5714_FAMILY(sc)) {
2885 1.100 jonathan marbmode = CSR_READ_4(sc, BGE_MARB_MODE);
2886 1.99 jonathan }
2887 1.99 jonathan CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE | marbmode);
2888 1.44 hannken }
2889 1.1 fvdl
2890 1.1 fvdl /* Fix up byte swapping */
2891 1.1 fvdl CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS);
2892 1.1 fvdl
2893 1.1 fvdl CSR_WRITE_4(sc, BGE_MAC_MODE, 0);
2894 1.1 fvdl
2895 1.1 fvdl DELAY(10000);
2896 1.1 fvdl }
2897 1.1 fvdl
2898 1.1 fvdl /*
2899 1.1 fvdl * Frame reception handling. This is called if there's a frame
2900 1.1 fvdl * on the receive return list.
2901 1.1 fvdl *
2902 1.1 fvdl * Note: we have to be able to handle two possibilities here:
2903 1.1 fvdl * 1) the frame is from the jumbo recieve ring
2904 1.1 fvdl * 2) the frame is from the standard receive ring
2905 1.1 fvdl */
2906 1.1 fvdl
2907 1.1 fvdl void
2908 1.1 fvdl bge_rxeof(sc)
2909 1.1 fvdl struct bge_softc *sc;
2910 1.1 fvdl {
2911 1.1 fvdl struct ifnet *ifp;
2912 1.1 fvdl int stdcnt = 0, jumbocnt = 0;
2913 1.1 fvdl bus_dmamap_t dmamap;
2914 1.1 fvdl bus_addr_t offset, toff;
2915 1.1 fvdl bus_size_t tlen;
2916 1.1 fvdl int tosync;
2917 1.1 fvdl
2918 1.1 fvdl ifp = &sc->ethercom.ec_if;
2919 1.1 fvdl
2920 1.1 fvdl bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map,
2921 1.1 fvdl offsetof(struct bge_ring_data, bge_status_block),
2922 1.1 fvdl sizeof (struct bge_status_block),
2923 1.1 fvdl BUS_DMASYNC_POSTREAD);
2924 1.1 fvdl
2925 1.1 fvdl offset = offsetof(struct bge_ring_data, bge_rx_return_ring);
2926 1.87 perry tosync = sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx -
2927 1.1 fvdl sc->bge_rx_saved_considx;
2928 1.1 fvdl
2929 1.1 fvdl toff = offset + (sc->bge_rx_saved_considx * sizeof (struct bge_rx_bd));
2930 1.1 fvdl
2931 1.1 fvdl if (tosync < 0) {
2932 1.44 hannken tlen = (sc->bge_return_ring_cnt - sc->bge_rx_saved_considx) *
2933 1.1 fvdl sizeof (struct bge_rx_bd);
2934 1.1 fvdl bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map,
2935 1.1 fvdl toff, tlen, BUS_DMASYNC_POSTREAD);
2936 1.1 fvdl tosync = -tosync;
2937 1.1 fvdl }
2938 1.1 fvdl
2939 1.1 fvdl bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map,
2940 1.1 fvdl offset, tosync * sizeof (struct bge_rx_bd),
2941 1.1 fvdl BUS_DMASYNC_POSTREAD);
2942 1.1 fvdl
2943 1.1 fvdl while(sc->bge_rx_saved_considx !=
2944 1.1 fvdl sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx) {
2945 1.1 fvdl struct bge_rx_bd *cur_rx;
2946 1.1 fvdl u_int32_t rxidx;
2947 1.1 fvdl struct mbuf *m = NULL;
2948 1.1 fvdl
2949 1.1 fvdl cur_rx = &sc->bge_rdata->
2950 1.1 fvdl bge_rx_return_ring[sc->bge_rx_saved_considx];
2951 1.1 fvdl
2952 1.1 fvdl rxidx = cur_rx->bge_idx;
2953 1.44 hannken BGE_INC(sc->bge_rx_saved_considx, sc->bge_return_ring_cnt);
2954 1.1 fvdl
2955 1.1 fvdl if (cur_rx->bge_flags & BGE_RXBDFLAG_JUMBO_RING) {
2956 1.1 fvdl BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT);
2957 1.1 fvdl m = sc->bge_cdata.bge_rx_jumbo_chain[rxidx];
2958 1.1 fvdl sc->bge_cdata.bge_rx_jumbo_chain[rxidx] = NULL;
2959 1.1 fvdl jumbocnt++;
2960 1.1 fvdl if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) {
2961 1.1 fvdl ifp->if_ierrors++;
2962 1.1 fvdl bge_newbuf_jumbo(sc, sc->bge_jumbo, m);
2963 1.1 fvdl continue;
2964 1.1 fvdl }
2965 1.1 fvdl if (bge_newbuf_jumbo(sc, sc->bge_jumbo,
2966 1.1 fvdl NULL)== ENOBUFS) {
2967 1.1 fvdl ifp->if_ierrors++;
2968 1.1 fvdl bge_newbuf_jumbo(sc, sc->bge_jumbo, m);
2969 1.1 fvdl continue;
2970 1.1 fvdl }
2971 1.1 fvdl } else {
2972 1.1 fvdl BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT);
2973 1.1 fvdl m = sc->bge_cdata.bge_rx_std_chain[rxidx];
2974 1.1 fvdl sc->bge_cdata.bge_rx_std_chain[rxidx] = NULL;
2975 1.1 fvdl stdcnt++;
2976 1.1 fvdl dmamap = sc->bge_cdata.bge_rx_std_map[rxidx];
2977 1.1 fvdl sc->bge_cdata.bge_rx_std_map[rxidx] = 0;
2978 1.1 fvdl if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) {
2979 1.1 fvdl ifp->if_ierrors++;
2980 1.1 fvdl bge_newbuf_std(sc, sc->bge_std, m, dmamap);
2981 1.1 fvdl continue;
2982 1.1 fvdl }
2983 1.1 fvdl if (bge_newbuf_std(sc, sc->bge_std,
2984 1.1 fvdl NULL, dmamap) == ENOBUFS) {
2985 1.1 fvdl ifp->if_ierrors++;
2986 1.1 fvdl bge_newbuf_std(sc, sc->bge_std, m, dmamap);
2987 1.1 fvdl continue;
2988 1.1 fvdl }
2989 1.1 fvdl }
2990 1.1 fvdl
2991 1.1 fvdl ifp->if_ipackets++;
2992 1.37 jonathan #ifndef __NO_STRICT_ALIGNMENT
2993 1.37 jonathan /*
2994 1.37 jonathan * XXX: if the 5701 PCIX-Rx-DMA workaround is in effect,
2995 1.37 jonathan * the Rx buffer has the layer-2 header unaligned.
2996 1.37 jonathan * If our CPU requires alignment, re-align by copying.
2997 1.37 jonathan */
2998 1.37 jonathan if (sc->bge_rx_alignment_bug) {
2999 1.37 jonathan memmove(mtod(m, caddr_t) + ETHER_ALIGN, m->m_data,
3000 1.37 jonathan cur_rx->bge_len);
3001 1.37 jonathan m->m_data += ETHER_ALIGN;
3002 1.37 jonathan }
3003 1.37 jonathan #endif
3004 1.87 perry
3005 1.54 fvdl m->m_pkthdr.len = m->m_len = cur_rx->bge_len - ETHER_CRC_LEN;
3006 1.1 fvdl m->m_pkthdr.rcvif = ifp;
3007 1.1 fvdl
3008 1.1 fvdl #if NBPFILTER > 0
3009 1.1 fvdl /*
3010 1.1 fvdl * Handle BPF listeners. Let the BPF user see the packet.
3011 1.1 fvdl */
3012 1.1 fvdl if (ifp->if_bpf)
3013 1.1 fvdl bpf_mtap(ifp->if_bpf, m);
3014 1.1 fvdl #endif
3015 1.1 fvdl
3016 1.60 drochner m->m_pkthdr.csum_flags = M_CSUM_IPv4;
3017 1.46 jonathan
3018 1.46 jonathan if ((cur_rx->bge_ip_csum ^ 0xffff) != 0)
3019 1.46 jonathan m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD;
3020 1.46 jonathan /*
3021 1.46 jonathan * Rx transport checksum-offload may also
3022 1.46 jonathan * have bugs with packets which, when transmitted,
3023 1.46 jonathan * were `runts' requiring padding.
3024 1.46 jonathan */
3025 1.46 jonathan if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM &&
3026 1.46 jonathan (/* (sc->_bge_quirks & BGE_QUIRK_SHORT_CKSUM_BUG) == 0 ||*/
3027 1.46 jonathan m->m_pkthdr.len >= ETHER_MIN_NOPAD)) {
3028 1.46 jonathan m->m_pkthdr.csum_data =
3029 1.46 jonathan cur_rx->bge_tcp_udp_csum;
3030 1.46 jonathan m->m_pkthdr.csum_flags |=
3031 1.46 jonathan (M_CSUM_TCPv4|M_CSUM_UDPv4|
3032 1.46 jonathan M_CSUM_DATA|M_CSUM_NO_PSEUDOHDR);
3033 1.1 fvdl }
3034 1.1 fvdl
3035 1.1 fvdl /*
3036 1.1 fvdl * If we received a packet with a vlan tag, pass it
3037 1.1 fvdl * to vlan_input() instead of ether_input().
3038 1.1 fvdl */
3039 1.85 jdolecek if (cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG)
3040 1.85 jdolecek VLAN_INPUT_TAG(ifp, m, cur_rx->bge_vlan_tag, continue);
3041 1.1 fvdl
3042 1.1 fvdl (*ifp->if_input)(ifp, m);
3043 1.1 fvdl }
3044 1.1 fvdl
3045 1.1 fvdl CSR_WRITE_4(sc, BGE_MBX_RX_CONS0_LO, sc->bge_rx_saved_considx);
3046 1.1 fvdl if (stdcnt)
3047 1.1 fvdl CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std);
3048 1.1 fvdl if (jumbocnt)
3049 1.1 fvdl CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo);
3050 1.1 fvdl }
3051 1.1 fvdl
3052 1.1 fvdl void
3053 1.1 fvdl bge_txeof(sc)
3054 1.1 fvdl struct bge_softc *sc;
3055 1.1 fvdl {
3056 1.1 fvdl struct bge_tx_bd *cur_tx = NULL;
3057 1.1 fvdl struct ifnet *ifp;
3058 1.1 fvdl struct txdmamap_pool_entry *dma;
3059 1.1 fvdl bus_addr_t offset, toff;
3060 1.1 fvdl bus_size_t tlen;
3061 1.1 fvdl int tosync;
3062 1.1 fvdl struct mbuf *m;
3063 1.1 fvdl
3064 1.1 fvdl ifp = &sc->ethercom.ec_if;
3065 1.1 fvdl
3066 1.1 fvdl bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map,
3067 1.1 fvdl offsetof(struct bge_ring_data, bge_status_block),
3068 1.1 fvdl sizeof (struct bge_status_block),
3069 1.1 fvdl BUS_DMASYNC_POSTREAD);
3070 1.1 fvdl
3071 1.1 fvdl offset = offsetof(struct bge_ring_data, bge_tx_ring);
3072 1.87 perry tosync = sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx -
3073 1.1 fvdl sc->bge_tx_saved_considx;
3074 1.1 fvdl
3075 1.1 fvdl toff = offset + (sc->bge_tx_saved_considx * sizeof (struct bge_tx_bd));
3076 1.1 fvdl
3077 1.1 fvdl if (tosync < 0) {
3078 1.1 fvdl tlen = (BGE_TX_RING_CNT - sc->bge_tx_saved_considx) *
3079 1.1 fvdl sizeof (struct bge_tx_bd);
3080 1.1 fvdl bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map,
3081 1.1 fvdl toff, tlen, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
3082 1.1 fvdl tosync = -tosync;
3083 1.1 fvdl }
3084 1.1 fvdl
3085 1.1 fvdl bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map,
3086 1.1 fvdl offset, tosync * sizeof (struct bge_tx_bd),
3087 1.1 fvdl BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
3088 1.1 fvdl
3089 1.1 fvdl /*
3090 1.1 fvdl * Go through our tx ring and free mbufs for those
3091 1.1 fvdl * frames that have been sent.
3092 1.1 fvdl */
3093 1.1 fvdl while (sc->bge_tx_saved_considx !=
3094 1.1 fvdl sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx) {
3095 1.1 fvdl u_int32_t idx = 0;
3096 1.1 fvdl
3097 1.1 fvdl idx = sc->bge_tx_saved_considx;
3098 1.1 fvdl cur_tx = &sc->bge_rdata->bge_tx_ring[idx];
3099 1.1 fvdl if (cur_tx->bge_flags & BGE_TXBDFLAG_END)
3100 1.1 fvdl ifp->if_opackets++;
3101 1.1 fvdl m = sc->bge_cdata.bge_tx_chain[idx];
3102 1.1 fvdl if (m != NULL) {
3103 1.1 fvdl sc->bge_cdata.bge_tx_chain[idx] = NULL;
3104 1.1 fvdl dma = sc->txdma[idx];
3105 1.1 fvdl bus_dmamap_sync(sc->bge_dmatag, dma->dmamap, 0,
3106 1.1 fvdl dma->dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE);
3107 1.1 fvdl bus_dmamap_unload(sc->bge_dmatag, dma->dmamap);
3108 1.1 fvdl SLIST_INSERT_HEAD(&sc->txdma_list, dma, link);
3109 1.1 fvdl sc->txdma[idx] = NULL;
3110 1.1 fvdl
3111 1.1 fvdl m_freem(m);
3112 1.1 fvdl }
3113 1.1 fvdl sc->bge_txcnt--;
3114 1.1 fvdl BGE_INC(sc->bge_tx_saved_considx, BGE_TX_RING_CNT);
3115 1.1 fvdl ifp->if_timer = 0;
3116 1.1 fvdl }
3117 1.1 fvdl
3118 1.1 fvdl if (cur_tx != NULL)
3119 1.1 fvdl ifp->if_flags &= ~IFF_OACTIVE;
3120 1.1 fvdl }
3121 1.1 fvdl
3122 1.1 fvdl int
3123 1.1 fvdl bge_intr(xsc)
3124 1.1 fvdl void *xsc;
3125 1.1 fvdl {
3126 1.1 fvdl struct bge_softc *sc;
3127 1.1 fvdl struct ifnet *ifp;
3128 1.1 fvdl
3129 1.1 fvdl sc = xsc;
3130 1.1 fvdl ifp = &sc->ethercom.ec_if;
3131 1.1 fvdl
3132 1.1 fvdl #ifdef notdef
3133 1.1 fvdl /* Avoid this for now -- checking this register is expensive. */
3134 1.1 fvdl /* Make sure this is really our interrupt. */
3135 1.1 fvdl if (!(CSR_READ_4(sc, BGE_MISC_LOCAL_CTL) & BGE_MLC_INTR_STATE))
3136 1.1 fvdl return (0);
3137 1.1 fvdl #endif
3138 1.1 fvdl /* Ack interrupt and stop others from occuring. */
3139 1.1 fvdl CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 1);
3140 1.1 fvdl
3141 1.72 thorpej BGE_EVCNT_INCR(sc->bge_ev_intr);
3142 1.72 thorpej
3143 1.1 fvdl /*
3144 1.1 fvdl * Process link state changes.
3145 1.1 fvdl * Grrr. The link status word in the status block does
3146 1.1 fvdl * not work correctly on the BCM5700 rev AX and BX chips,
3147 1.101 skrll * according to all available information. Hence, we have
3148 1.1 fvdl * to enable MII interrupts in order to properly obtain
3149 1.1 fvdl * async link changes. Unfortunately, this also means that
3150 1.1 fvdl * we have to read the MAC status register to detect link
3151 1.1 fvdl * changes, thereby adding an additional register access to
3152 1.1 fvdl * the interrupt handler.
3153 1.1 fvdl */
3154 1.1 fvdl
3155 1.17 thorpej if (sc->bge_quirks & BGE_QUIRK_LINK_STATE_BROKEN) {
3156 1.1 fvdl u_int32_t status;
3157 1.1 fvdl
3158 1.1 fvdl status = CSR_READ_4(sc, BGE_MAC_STS);
3159 1.1 fvdl if (status & BGE_MACSTAT_MI_INTERRUPT) {
3160 1.1 fvdl sc->bge_link = 0;
3161 1.1 fvdl callout_stop(&sc->bge_timeout);
3162 1.1 fvdl bge_tick(sc);
3163 1.1 fvdl /* Clear the interrupt */
3164 1.1 fvdl CSR_WRITE_4(sc, BGE_MAC_EVT_ENB,
3165 1.1 fvdl BGE_EVTENB_MI_INTERRUPT);
3166 1.1 fvdl bge_miibus_readreg(&sc->bge_dev, 1, BRGPHY_MII_ISR);
3167 1.1 fvdl bge_miibus_writereg(&sc->bge_dev, 1, BRGPHY_MII_IMR,
3168 1.1 fvdl BRGPHY_INTRS);
3169 1.1 fvdl }
3170 1.1 fvdl } else {
3171 1.1 fvdl if (sc->bge_rdata->bge_status_block.bge_status &
3172 1.1 fvdl BGE_STATFLAG_LINKSTATE_CHANGED) {
3173 1.1 fvdl sc->bge_link = 0;
3174 1.1 fvdl callout_stop(&sc->bge_timeout);
3175 1.1 fvdl bge_tick(sc);
3176 1.1 fvdl /* Clear the interrupt */
3177 1.1 fvdl CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED|
3178 1.44 hannken BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE|
3179 1.44 hannken BGE_MACSTAT_LINK_CHANGED);
3180 1.1 fvdl }
3181 1.1 fvdl }
3182 1.1 fvdl
3183 1.1 fvdl if (ifp->if_flags & IFF_RUNNING) {
3184 1.1 fvdl /* Check RX return ring producer/consumer */
3185 1.1 fvdl bge_rxeof(sc);
3186 1.1 fvdl
3187 1.1 fvdl /* Check TX ring producer/consumer */
3188 1.1 fvdl bge_txeof(sc);
3189 1.1 fvdl }
3190 1.1 fvdl
3191 1.58 jonathan if (sc->bge_pending_rxintr_change) {
3192 1.58 jonathan uint32_t rx_ticks = sc->bge_rx_coal_ticks;
3193 1.58 jonathan uint32_t rx_bds = sc->bge_rx_max_coal_bds;
3194 1.58 jonathan uint32_t junk;
3195 1.58 jonathan
3196 1.58 jonathan CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, rx_ticks);
3197 1.58 jonathan DELAY(10);
3198 1.58 jonathan junk = CSR_READ_4(sc, BGE_HCC_RX_COAL_TICKS);
3199 1.87 perry
3200 1.58 jonathan CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, rx_bds);
3201 1.58 jonathan DELAY(10);
3202 1.58 jonathan junk = CSR_READ_4(sc, BGE_HCC_RX_MAX_COAL_BDS);
3203 1.58 jonathan
3204 1.58 jonathan sc->bge_pending_rxintr_change = 0;
3205 1.58 jonathan }
3206 1.1 fvdl bge_handle_events(sc);
3207 1.1 fvdl
3208 1.1 fvdl /* Re-enable interrupts. */
3209 1.1 fvdl CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 0);
3210 1.1 fvdl
3211 1.1 fvdl if (ifp->if_flags & IFF_RUNNING && !IFQ_IS_EMPTY(&ifp->if_snd))
3212 1.1 fvdl bge_start(ifp);
3213 1.1 fvdl
3214 1.1 fvdl return (1);
3215 1.1 fvdl }
3216 1.1 fvdl
3217 1.1 fvdl void
3218 1.1 fvdl bge_tick(xsc)
3219 1.1 fvdl void *xsc;
3220 1.1 fvdl {
3221 1.1 fvdl struct bge_softc *sc = xsc;
3222 1.1 fvdl struct mii_data *mii = &sc->bge_mii;
3223 1.1 fvdl struct ifmedia *ifm = NULL;
3224 1.1 fvdl struct ifnet *ifp = &sc->ethercom.ec_if;
3225 1.1 fvdl int s;
3226 1.1 fvdl
3227 1.1 fvdl s = splnet();
3228 1.1 fvdl
3229 1.1 fvdl bge_stats_update(sc);
3230 1.1 fvdl callout_reset(&sc->bge_timeout, hz, bge_tick, sc);
3231 1.1 fvdl if (sc->bge_link) {
3232 1.1 fvdl splx(s);
3233 1.1 fvdl return;
3234 1.1 fvdl }
3235 1.1 fvdl
3236 1.1 fvdl if (sc->bge_tbi) {
3237 1.1 fvdl ifm = &sc->bge_ifmedia;
3238 1.1 fvdl if (CSR_READ_4(sc, BGE_MAC_STS) &
3239 1.1 fvdl BGE_MACSTAT_TBI_PCS_SYNCHED) {
3240 1.1 fvdl sc->bge_link++;
3241 1.1 fvdl CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF);
3242 1.1 fvdl if (!IFQ_IS_EMPTY(&ifp->if_snd))
3243 1.1 fvdl bge_start(ifp);
3244 1.1 fvdl }
3245 1.1 fvdl splx(s);
3246 1.1 fvdl return;
3247 1.1 fvdl }
3248 1.1 fvdl
3249 1.1 fvdl mii_tick(mii);
3250 1.1 fvdl
3251 1.1 fvdl if (!sc->bge_link && mii->mii_media_status & IFM_ACTIVE &&
3252 1.1 fvdl IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
3253 1.1 fvdl sc->bge_link++;
3254 1.1 fvdl if (!IFQ_IS_EMPTY(&ifp->if_snd))
3255 1.1 fvdl bge_start(ifp);
3256 1.1 fvdl }
3257 1.1 fvdl
3258 1.1 fvdl splx(s);
3259 1.1 fvdl }
3260 1.1 fvdl
3261 1.1 fvdl void
3262 1.1 fvdl bge_stats_update(sc)
3263 1.1 fvdl struct bge_softc *sc;
3264 1.1 fvdl {
3265 1.1 fvdl struct ifnet *ifp = &sc->ethercom.ec_if;
3266 1.1 fvdl bus_size_t stats = BGE_MEMWIN_START + BGE_STATS_BLOCK;
3267 1.44 hannken bus_size_t rstats = BGE_RX_STATS;
3268 1.44 hannken
3269 1.44 hannken #define READ_RSTAT(sc, stats, stat) \
3270 1.44 hannken CSR_READ_4(sc, stats + offsetof(struct bge_mac_stats_regs, stat))
3271 1.1 fvdl
3272 1.44 hannken if (sc->bge_quirks & BGE_QUIRK_5705_CORE) {
3273 1.44 hannken ifp->if_collisions +=
3274 1.44 hannken READ_RSTAT(sc, rstats, dot3StatsSingleCollisionFrames) +
3275 1.44 hannken READ_RSTAT(sc, rstats, dot3StatsMultipleCollisionFrames) +
3276 1.44 hannken READ_RSTAT(sc, rstats, dot3StatsExcessiveCollisions) +
3277 1.44 hannken READ_RSTAT(sc, rstats, dot3StatsLateCollisions);
3278 1.72 thorpej
3279 1.72 thorpej BGE_EVCNT_ADD(sc->bge_ev_tx_xoff,
3280 1.72 thorpej READ_RSTAT(sc, rstats, outXoffSent));
3281 1.72 thorpej BGE_EVCNT_ADD(sc->bge_ev_tx_xon,
3282 1.72 thorpej READ_RSTAT(sc, rstats, outXonSent));
3283 1.72 thorpej BGE_EVCNT_ADD(sc->bge_ev_rx_xoff,
3284 1.72 thorpej READ_RSTAT(sc, rstats, xoffPauseFramesReceived));
3285 1.72 thorpej BGE_EVCNT_ADD(sc->bge_ev_rx_xon,
3286 1.72 thorpej READ_RSTAT(sc, rstats, xonPauseFramesReceived));
3287 1.72 thorpej BGE_EVCNT_ADD(sc->bge_ev_rx_macctl,
3288 1.72 thorpej READ_RSTAT(sc, rstats, macControlFramesReceived));
3289 1.72 thorpej BGE_EVCNT_ADD(sc->bge_ev_xoffentered,
3290 1.72 thorpej READ_RSTAT(sc, rstats, xoffStateEntered));
3291 1.44 hannken return;
3292 1.44 hannken }
3293 1.44 hannken
3294 1.44 hannken #undef READ_RSTAT
3295 1.1 fvdl #define READ_STAT(sc, stats, stat) \
3296 1.1 fvdl CSR_READ_4(sc, stats + offsetof(struct bge_stats, stat))
3297 1.1 fvdl
3298 1.1 fvdl ifp->if_collisions +=
3299 1.1 fvdl (READ_STAT(sc, stats, dot3StatsSingleCollisionFrames.bge_addr_lo) +
3300 1.1 fvdl READ_STAT(sc, stats, dot3StatsMultipleCollisionFrames.bge_addr_lo) +
3301 1.1 fvdl READ_STAT(sc, stats, dot3StatsExcessiveCollisions.bge_addr_lo) +
3302 1.1 fvdl READ_STAT(sc, stats, dot3StatsLateCollisions.bge_addr_lo)) -
3303 1.1 fvdl ifp->if_collisions;
3304 1.1 fvdl
3305 1.72 thorpej BGE_EVCNT_UPD(sc->bge_ev_tx_xoff,
3306 1.72 thorpej READ_STAT(sc, stats, outXoffSent.bge_addr_lo));
3307 1.72 thorpej BGE_EVCNT_UPD(sc->bge_ev_tx_xon,
3308 1.72 thorpej READ_STAT(sc, stats, outXonSent.bge_addr_lo));
3309 1.72 thorpej BGE_EVCNT_UPD(sc->bge_ev_rx_xoff,
3310 1.72 thorpej READ_STAT(sc, stats,
3311 1.72 thorpej xoffPauseFramesReceived.bge_addr_lo));
3312 1.72 thorpej BGE_EVCNT_UPD(sc->bge_ev_rx_xon,
3313 1.72 thorpej READ_STAT(sc, stats, xonPauseFramesReceived.bge_addr_lo));
3314 1.72 thorpej BGE_EVCNT_UPD(sc->bge_ev_rx_macctl,
3315 1.72 thorpej READ_STAT(sc, stats,
3316 1.72 thorpej macControlFramesReceived.bge_addr_lo));
3317 1.72 thorpej BGE_EVCNT_UPD(sc->bge_ev_xoffentered,
3318 1.72 thorpej READ_STAT(sc, stats, xoffStateEntered.bge_addr_lo));
3319 1.72 thorpej
3320 1.1 fvdl #undef READ_STAT
3321 1.1 fvdl
3322 1.1 fvdl #ifdef notdef
3323 1.1 fvdl ifp->if_collisions +=
3324 1.1 fvdl (sc->bge_rdata->bge_info.bge_stats.dot3StatsSingleCollisionFrames +
3325 1.1 fvdl sc->bge_rdata->bge_info.bge_stats.dot3StatsMultipleCollisionFrames +
3326 1.1 fvdl sc->bge_rdata->bge_info.bge_stats.dot3StatsExcessiveCollisions +
3327 1.1 fvdl sc->bge_rdata->bge_info.bge_stats.dot3StatsLateCollisions) -
3328 1.1 fvdl ifp->if_collisions;
3329 1.1 fvdl #endif
3330 1.1 fvdl }
3331 1.1 fvdl
3332 1.46 jonathan /*
3333 1.46 jonathan * Pad outbound frame to ETHER_MIN_NOPAD for an unusual reason.
3334 1.46 jonathan * The bge hardware will pad out Tx runts to ETHER_MIN_NOPAD,
3335 1.46 jonathan * but when such padded frames employ the bge IP/TCP checksum offload,
3336 1.46 jonathan * the hardware checksum assist gives incorrect results (possibly
3337 1.46 jonathan * from incorporating its own padding into the UDP/TCP checksum; who knows).
3338 1.46 jonathan * If we pad such runts with zeros, the onboard checksum comes out correct.
3339 1.46 jonathan */
3340 1.102 perry static inline int
3341 1.46 jonathan bge_cksum_pad(struct mbuf *pkt)
3342 1.46 jonathan {
3343 1.46 jonathan struct mbuf *last = NULL;
3344 1.46 jonathan int padlen;
3345 1.46 jonathan
3346 1.46 jonathan padlen = ETHER_MIN_NOPAD - pkt->m_pkthdr.len;
3347 1.46 jonathan
3348 1.46 jonathan /* if there's only the packet-header and we can pad there, use it. */
3349 1.46 jonathan if (pkt->m_pkthdr.len == pkt->m_len &&
3350 1.46 jonathan !M_READONLY(pkt) && M_TRAILINGSPACE(pkt) >= padlen) {
3351 1.46 jonathan last = pkt;
3352 1.46 jonathan } else {
3353 1.46 jonathan /*
3354 1.46 jonathan * Walk packet chain to find last mbuf. We will either
3355 1.87 perry * pad there, or append a new mbuf and pad it
3356 1.46 jonathan * (thus perhaps avoiding the bcm5700 dma-min bug).
3357 1.46 jonathan */
3358 1.46 jonathan for (last = pkt; last->m_next != NULL; last = last->m_next) {
3359 1.46 jonathan (void) 0; /* do nothing*/
3360 1.46 jonathan }
3361 1.46 jonathan
3362 1.46 jonathan /* `last' now points to last in chain. */
3363 1.46 jonathan if (!M_READONLY(last) && M_TRAILINGSPACE(last) >= padlen) {
3364 1.46 jonathan (void) 0; /* we can pad here, in-place. */
3365 1.46 jonathan } else {
3366 1.46 jonathan /* Allocate new empty mbuf, pad it. Compact later. */
3367 1.46 jonathan struct mbuf *n;
3368 1.46 jonathan MGET(n, M_DONTWAIT, MT_DATA);
3369 1.46 jonathan n->m_len = 0;
3370 1.46 jonathan last->m_next = n;
3371 1.46 jonathan last = n;
3372 1.46 jonathan }
3373 1.46 jonathan }
3374 1.46 jonathan
3375 1.46 jonathan #ifdef DEBUG
3376 1.48 hannken /*KASSERT(M_WRITABLE(last), ("to-pad mbuf not writeable\n"));*/
3377 1.47 cjep KASSERT(M_TRAILINGSPACE(last) >= padlen /*, ("insufficient space to pad\n")*/ );
3378 1.46 jonathan #endif
3379 1.46 jonathan /* Now zero the pad area, to avoid the bge cksum-assist bug */
3380 1.46 jonathan memset(mtod(last, caddr_t) + last->m_len, 0, padlen);
3381 1.46 jonathan last->m_len += padlen;
3382 1.46 jonathan pkt->m_pkthdr.len += padlen;
3383 1.46 jonathan return 0;
3384 1.46 jonathan }
3385 1.45 jonathan
3386 1.45 jonathan /*
3387 1.45 jonathan * Compact outbound packets to avoid bug with DMA segments less than 8 bytes.
3388 1.45 jonathan */
3389 1.102 perry static inline int
3390 1.45 jonathan bge_compact_dma_runt(struct mbuf *pkt)
3391 1.45 jonathan {
3392 1.45 jonathan struct mbuf *m, *prev;
3393 1.45 jonathan int totlen, prevlen;
3394 1.45 jonathan
3395 1.45 jonathan prev = NULL;
3396 1.45 jonathan totlen = 0;
3397 1.45 jonathan prevlen = -1;
3398 1.45 jonathan
3399 1.45 jonathan for (m = pkt; m != NULL; prev = m,m = m->m_next) {
3400 1.45 jonathan int mlen = m->m_len;
3401 1.45 jonathan int shortfall = 8 - mlen ;
3402 1.45 jonathan
3403 1.45 jonathan totlen += mlen;
3404 1.45 jonathan if (mlen == 0) {
3405 1.45 jonathan continue;
3406 1.45 jonathan }
3407 1.45 jonathan if (mlen >= 8)
3408 1.45 jonathan continue;
3409 1.45 jonathan
3410 1.45 jonathan /* If we get here, mbuf data is too small for DMA engine.
3411 1.45 jonathan * Try to fix by shuffling data to prev or next in chain.
3412 1.45 jonathan * If that fails, do a compacting deep-copy of the whole chain.
3413 1.45 jonathan */
3414 1.45 jonathan
3415 1.45 jonathan /* Internal frag. If fits in prev, copy it there. */
3416 1.45 jonathan if (prev && !M_READONLY(prev) &&
3417 1.45 jonathan M_TRAILINGSPACE(prev) >= m->m_len) {
3418 1.45 jonathan bcopy(m->m_data,
3419 1.45 jonathan prev->m_data+prev->m_len,
3420 1.45 jonathan mlen);
3421 1.45 jonathan prev->m_len += mlen;
3422 1.45 jonathan m->m_len = 0;
3423 1.45 jonathan /* XXX stitch chain */
3424 1.45 jonathan prev->m_next = m_free(m);
3425 1.45 jonathan m = prev;
3426 1.45 jonathan continue;
3427 1.45 jonathan }
3428 1.45 jonathan else if (m->m_next != NULL && !M_READONLY(m) &&
3429 1.45 jonathan M_TRAILINGSPACE(m) >= shortfall &&
3430 1.45 jonathan m->m_next->m_len >= (8 + shortfall)) {
3431 1.45 jonathan /* m is writable and have enough data in next, pull up. */
3432 1.45 jonathan
3433 1.45 jonathan bcopy(m->m_next->m_data,
3434 1.45 jonathan m->m_data+m->m_len,
3435 1.45 jonathan shortfall);
3436 1.45 jonathan m->m_len += shortfall;
3437 1.45 jonathan m->m_next->m_len -= shortfall;
3438 1.45 jonathan m->m_next->m_data += shortfall;
3439 1.45 jonathan }
3440 1.45 jonathan else if (m->m_next == NULL || 1) {
3441 1.45 jonathan /* Got a runt at the very end of the packet.
3442 1.45 jonathan * borrow data from the tail of the preceding mbuf and
3443 1.45 jonathan * update its length in-place. (The original data is still
3444 1.45 jonathan * valid, so we can do this even if prev is not writable.)
3445 1.45 jonathan */
3446 1.45 jonathan
3447 1.45 jonathan /* if we'd make prev a runt, just move all of its data. */
3448 1.45 jonathan #ifdef DEBUG
3449 1.45 jonathan KASSERT(prev != NULL /*, ("runt but null PREV")*/);
3450 1.45 jonathan KASSERT(prev->m_len >= 8 /*, ("runt prev")*/);
3451 1.45 jonathan #endif
3452 1.45 jonathan if ((prev->m_len - shortfall) < 8)
3453 1.45 jonathan shortfall = prev->m_len;
3454 1.87 perry
3455 1.45 jonathan #ifdef notyet /* just do the safe slow thing for now */
3456 1.45 jonathan if (!M_READONLY(m)) {
3457 1.45 jonathan if (M_LEADINGSPACE(m) < shorfall) {
3458 1.45 jonathan void *m_dat;
3459 1.45 jonathan m_dat = (m->m_flags & M_PKTHDR) ?
3460 1.45 jonathan m->m_pktdat : m->dat;
3461 1.45 jonathan memmove(m_dat, mtod(m, void*), m->m_len);
3462 1.45 jonathan m->m_data = m_dat;
3463 1.45 jonathan }
3464 1.45 jonathan } else
3465 1.45 jonathan #endif /* just do the safe slow thing */
3466 1.45 jonathan {
3467 1.45 jonathan struct mbuf * n = NULL;
3468 1.45 jonathan int newprevlen = prev->m_len - shortfall;
3469 1.45 jonathan
3470 1.45 jonathan MGET(n, M_NOWAIT, MT_DATA);
3471 1.45 jonathan if (n == NULL)
3472 1.45 jonathan return ENOBUFS;
3473 1.45 jonathan KASSERT(m->m_len + shortfall < MLEN
3474 1.45 jonathan /*,
3475 1.45 jonathan ("runt %d +prev %d too big\n", m->m_len, shortfall)*/);
3476 1.45 jonathan
3477 1.45 jonathan /* first copy the data we're stealing from prev */
3478 1.45 jonathan bcopy(prev->m_data + newprevlen, n->m_data, shortfall);
3479 1.45 jonathan
3480 1.45 jonathan /* update prev->m_len accordingly */
3481 1.45 jonathan prev->m_len -= shortfall;
3482 1.45 jonathan
3483 1.45 jonathan /* copy data from runt m */
3484 1.45 jonathan bcopy(m->m_data, n->m_data + shortfall, m->m_len);
3485 1.45 jonathan
3486 1.45 jonathan /* n holds what we stole from prev, plus m */
3487 1.45 jonathan n->m_len = shortfall + m->m_len;
3488 1.45 jonathan
3489 1.45 jonathan /* stitch n into chain and free m */
3490 1.45 jonathan n->m_next = m->m_next;
3491 1.45 jonathan prev->m_next = n;
3492 1.45 jonathan /* KASSERT(m->m_next == NULL); */
3493 1.45 jonathan m->m_next = NULL;
3494 1.45 jonathan m_free(m);
3495 1.45 jonathan m = n; /* for continuing loop */
3496 1.45 jonathan }
3497 1.45 jonathan }
3498 1.45 jonathan prevlen = m->m_len;
3499 1.45 jonathan }
3500 1.45 jonathan return 0;
3501 1.45 jonathan }
3502 1.45 jonathan
3503 1.1 fvdl /*
3504 1.1 fvdl * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data
3505 1.1 fvdl * pointers to descriptors.
3506 1.1 fvdl */
3507 1.1 fvdl int
3508 1.1 fvdl bge_encap(sc, m_head, txidx)
3509 1.1 fvdl struct bge_softc *sc;
3510 1.1 fvdl struct mbuf *m_head;
3511 1.1 fvdl u_int32_t *txidx;
3512 1.1 fvdl {
3513 1.1 fvdl struct bge_tx_bd *f = NULL;
3514 1.1 fvdl u_int32_t frag, cur, cnt = 0;
3515 1.1 fvdl u_int16_t csum_flags = 0;
3516 1.95 jonathan u_int16_t txbd_tso_flags = 0;
3517 1.1 fvdl struct txdmamap_pool_entry *dma;
3518 1.1 fvdl bus_dmamap_t dmamap;
3519 1.1 fvdl int i = 0;
3520 1.29 itojun struct m_tag *mtag;
3521 1.95 jonathan int use_tso, maxsegsize, error;
3522 1.95 jonathan
3523 1.1 fvdl cur = frag = *txidx;
3524 1.1 fvdl
3525 1.1 fvdl if (m_head->m_pkthdr.csum_flags) {
3526 1.1 fvdl if (m_head->m_pkthdr.csum_flags & M_CSUM_IPv4)
3527 1.1 fvdl csum_flags |= BGE_TXBDFLAG_IP_CSUM;
3528 1.8 thorpej if (m_head->m_pkthdr.csum_flags & (M_CSUM_TCPv4|M_CSUM_UDPv4))
3529 1.1 fvdl csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM;
3530 1.1 fvdl }
3531 1.1 fvdl
3532 1.87 perry /*
3533 1.46 jonathan * If we were asked to do an outboard checksum, and the NIC
3534 1.46 jonathan * has the bug where it sometimes adds in the Ethernet padding,
3535 1.46 jonathan * explicitly pad with zeros so the cksum will be correct either way.
3536 1.46 jonathan * (For now, do this for all chip versions, until newer
3537 1.46 jonathan * are confirmed to not require the workaround.)
3538 1.46 jonathan */
3539 1.46 jonathan if ((csum_flags & BGE_TXBDFLAG_TCP_UDP_CSUM) == 0 ||
3540 1.46 jonathan #ifdef notyet
3541 1.46 jonathan (sc->bge_quirks & BGE_QUIRK_SHORT_CKSUM_BUG) == 0 ||
3542 1.87 perry #endif
3543 1.46 jonathan m_head->m_pkthdr.len >= ETHER_MIN_NOPAD)
3544 1.46 jonathan goto check_dma_bug;
3545 1.46 jonathan
3546 1.95 jonathan if (bge_cksum_pad(m_head) != 0) {
3547 1.46 jonathan return ENOBUFS;
3548 1.95 jonathan }
3549 1.46 jonathan
3550 1.46 jonathan check_dma_bug:
3551 1.25 jonathan if (!(sc->bge_quirks & BGE_QUIRK_5700_SMALLDMA))
3552 1.29 itojun goto doit;
3553 1.25 jonathan /*
3554 1.25 jonathan * bcm5700 Revision B silicon cannot handle DMA descriptors with
3555 1.87 perry * less than eight bytes. If we encounter a teeny mbuf
3556 1.25 jonathan * at the end of a chain, we can pad. Otherwise, copy.
3557 1.25 jonathan */
3558 1.45 jonathan if (bge_compact_dma_runt(m_head) != 0)
3559 1.45 jonathan return ENOBUFS;
3560 1.25 jonathan
3561 1.25 jonathan doit:
3562 1.1 fvdl dma = SLIST_FIRST(&sc->txdma_list);
3563 1.1 fvdl if (dma == NULL)
3564 1.1 fvdl return ENOBUFS;
3565 1.1 fvdl dmamap = dma->dmamap;
3566 1.1 fvdl
3567 1.1 fvdl /*
3568 1.95 jonathan * Set up any necessary TSO state before we start packing...
3569 1.95 jonathan */
3570 1.95 jonathan use_tso = (m_head->m_pkthdr.csum_flags & M_CSUM_TSOv4) != 0;
3571 1.95 jonathan if (!use_tso) {
3572 1.95 jonathan maxsegsize = 0;
3573 1.95 jonathan } else { /* TSO setup */
3574 1.95 jonathan unsigned mss;
3575 1.95 jonathan struct ether_header *eh;
3576 1.95 jonathan unsigned ip_tcp_hlen, iptcp_opt_words, tcp_seg_flags, offset;
3577 1.95 jonathan struct mbuf * m0 = m_head;
3578 1.95 jonathan struct ip *ip;
3579 1.95 jonathan struct tcphdr *th;
3580 1.95 jonathan int iphl, hlen;
3581 1.95 jonathan
3582 1.95 jonathan /*
3583 1.95 jonathan * XXX It would be nice if the mbuf pkthdr had offset
3584 1.95 jonathan * fields for the protocol headers.
3585 1.95 jonathan */
3586 1.95 jonathan
3587 1.95 jonathan eh = mtod(m0, struct ether_header *);
3588 1.95 jonathan switch (htons(eh->ether_type)) {
3589 1.95 jonathan case ETHERTYPE_IP:
3590 1.95 jonathan offset = ETHER_HDR_LEN;
3591 1.95 jonathan break;
3592 1.95 jonathan
3593 1.95 jonathan case ETHERTYPE_VLAN:
3594 1.95 jonathan offset = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN;
3595 1.95 jonathan break;
3596 1.95 jonathan
3597 1.95 jonathan default:
3598 1.95 jonathan /*
3599 1.95 jonathan * Don't support this protocol or encapsulation.
3600 1.95 jonathan */
3601 1.95 jonathan return (ENOBUFS);
3602 1.95 jonathan }
3603 1.95 jonathan
3604 1.95 jonathan /*
3605 1.95 jonathan * TCP/IP headers are in the first mbuf; we can do
3606 1.95 jonathan * this the easy way.
3607 1.95 jonathan */
3608 1.95 jonathan iphl = M_CSUM_DATA_IPv4_IPHL(m0->m_pkthdr.csum_data);
3609 1.95 jonathan hlen = iphl + offset;
3610 1.95 jonathan if (__predict_false(m0->m_len <
3611 1.95 jonathan (hlen + sizeof(struct tcphdr)))) {
3612 1.95 jonathan
3613 1.95 jonathan printf("TSO: hard case m0->m_len == %d <"
3614 1.96 martin " ip/tcp hlen %zd, not handled yet\n",
3615 1.95 jonathan m0->m_len, hlen+ sizeof(struct tcphdr));
3616 1.95 jonathan #ifdef NOTYET
3617 1.95 jonathan /*
3618 1.95 jonathan * XXX jonathan (at) NetBSD.org: untested.
3619 1.95 jonathan * how to force this branch to be taken?
3620 1.95 jonathan */
3621 1.95 jonathan BGE_EVCNT_INCR(&sc->sc_ev_txtsopain);
3622 1.95 jonathan
3623 1.95 jonathan m_copydata(m0, offset, sizeof(ip), &ip);
3624 1.95 jonathan m_copydata(m0, hlen, sizeof(th), &th);
3625 1.95 jonathan
3626 1.95 jonathan ip.ip_len = 0;
3627 1.95 jonathan
3628 1.95 jonathan m_copyback(m0, hlen + offsetof(struct ip, ip_len),
3629 1.95 jonathan sizeof(ip.ip_len), &ip.ip_len);
3630 1.95 jonathan
3631 1.95 jonathan th.th_sum = in_cksum_phdr(ip.ip_src.s_addr,
3632 1.95 jonathan ip.ip_dst.s_addr, htons(IPPROTO_TCP));
3633 1.95 jonathan
3634 1.95 jonathan m_copyback(m0, hlen + offsetof(struct tcphdr, th_sum),
3635 1.95 jonathan sizeof(th.th_sum), &th.th_sum);
3636 1.95 jonathan
3637 1.95 jonathan hlen += th.th_off << 2;
3638 1.95 jonathan iptcp_opt_words = hlen;
3639 1.95 jonathan #else
3640 1.95 jonathan /*
3641 1.95 jonathan * if_wm "hard" case not yet supported, can we not
3642 1.95 jonathan * mandate it out of existence?
3643 1.95 jonathan */
3644 1.95 jonathan (void) ip; (void)th; (void) ip_tcp_hlen;
3645 1.95 jonathan
3646 1.95 jonathan return ENOBUFS;
3647 1.95 jonathan #endif
3648 1.95 jonathan } else {
3649 1.95 jonathan ip = (struct ip *) (mtod(m0, caddr_t) + offset);
3650 1.95 jonathan th = (struct tcphdr *) (mtod(m0, caddr_t) + hlen);
3651 1.95 jonathan ip_tcp_hlen = iphl + (th->th_off << 2);
3652 1.95 jonathan
3653 1.95 jonathan /* Total IP/TCP options, in 32-bit words */
3654 1.95 jonathan iptcp_opt_words = (ip_tcp_hlen
3655 1.95 jonathan - sizeof(struct tcphdr)
3656 1.95 jonathan - sizeof(struct ip)) >> 2;
3657 1.95 jonathan }
3658 1.95 jonathan if (BGE_IS_5750_OR_BEYOND(sc)) {
3659 1.95 jonathan th->th_sum = 0;
3660 1.95 jonathan csum_flags &= ~(BGE_TXBDFLAG_TCP_UDP_CSUM);
3661 1.95 jonathan } else {
3662 1.95 jonathan /*
3663 1.95 jonathan * XXX jonathan (at) NetBSD.org: 5705 untested.
3664 1.95 jonathan * Requires TSO firmware patch for 5701/5703/5704.
3665 1.95 jonathan */
3666 1.95 jonathan th->th_sum = in_cksum_phdr(ip->ip_src.s_addr,
3667 1.95 jonathan ip->ip_dst.s_addr, htons(IPPROTO_TCP));
3668 1.95 jonathan }
3669 1.95 jonathan
3670 1.95 jonathan mss = m_head->m_pkthdr.segsz;
3671 1.95 jonathan txbd_tso_flags |=
3672 1.95 jonathan BGE_TXBDFLAG_CPU_PRE_DMA |
3673 1.95 jonathan BGE_TXBDFLAG_CPU_POST_DMA;
3674 1.95 jonathan
3675 1.95 jonathan /*
3676 1.95 jonathan * Our NIC TSO-assist assumes TSO has standard, optionless
3677 1.95 jonathan * IPv4 and TCP headers, which total 40 bytes. By default,
3678 1.95 jonathan * the NIC copies 40 bytes of IP/TCP header from the
3679 1.95 jonathan * supplied header into the IP/TCP header portion of
3680 1.95 jonathan * each post-TSO-segment. If the supplied packet has IP or
3681 1.95 jonathan * TCP options, we need to tell the NIC to copy those extra
3682 1.95 jonathan * bytes into each post-TSO header, in addition to the normal
3683 1.95 jonathan * 40-byte IP/TCP header (and to leave space accordingly).
3684 1.95 jonathan * Unfortunately, the driver encoding of option length
3685 1.95 jonathan * varies across different ASIC families.
3686 1.95 jonathan */
3687 1.95 jonathan tcp_seg_flags = 0;
3688 1.95 jonathan if (iptcp_opt_words) {
3689 1.95 jonathan if ( BGE_IS_5705_OR_BEYOND(sc)) {
3690 1.95 jonathan tcp_seg_flags =
3691 1.95 jonathan iptcp_opt_words << 11;
3692 1.95 jonathan } else {
3693 1.95 jonathan txbd_tso_flags |=
3694 1.95 jonathan iptcp_opt_words << 12;
3695 1.95 jonathan }
3696 1.95 jonathan }
3697 1.95 jonathan maxsegsize = mss | tcp_seg_flags;
3698 1.95 jonathan ip->ip_len = htons(mss + ip_tcp_hlen);
3699 1.95 jonathan
3700 1.95 jonathan } /* TSO setup */
3701 1.95 jonathan
3702 1.95 jonathan /*
3703 1.1 fvdl * Start packing the mbufs in this chain into
3704 1.1 fvdl * the fragment pointers. Stop when we run out
3705 1.1 fvdl * of fragments or hit the end of the mbuf chain.
3706 1.1 fvdl */
3707 1.95 jonathan error = bus_dmamap_load_mbuf(sc->bge_dmatag, dmamap, m_head,
3708 1.95 jonathan BUS_DMA_NOWAIT);
3709 1.95 jonathan if (error) {
3710 1.1 fvdl return(ENOBUFS);
3711 1.95 jonathan }
3712 1.95 jonathan
3713 1.95 jonathan mtag = sc->ethercom.ec_nvlans ?
3714 1.95 jonathan m_tag_find(m_head, PACKET_TAG_VLAN, NULL) : NULL;
3715 1.1 fvdl
3716 1.6 thorpej
3717 1.95 jonathan /* Iterate over dmap-map fragments. */
3718 1.1 fvdl for (i = 0; i < dmamap->dm_nsegs; i++) {
3719 1.1 fvdl f = &sc->bge_rdata->bge_tx_ring[frag];
3720 1.1 fvdl if (sc->bge_cdata.bge_tx_chain[frag] != NULL)
3721 1.1 fvdl break;
3722 1.95 jonathan
3723 1.1 fvdl bge_set_hostaddr(&f->bge_addr, dmamap->dm_segs[i].ds_addr);
3724 1.1 fvdl f->bge_len = dmamap->dm_segs[i].ds_len;
3725 1.95 jonathan
3726 1.95 jonathan /*
3727 1.95 jonathan * For 5751 and follow-ons, for TSO we must turn
3728 1.95 jonathan * off checksum-assist flag in the tx-descr, and
3729 1.95 jonathan * supply the ASIC-revision-specific encoding
3730 1.95 jonathan * of TSO flags and segsize.
3731 1.95 jonathan */
3732 1.95 jonathan if (use_tso) {
3733 1.95 jonathan if (BGE_IS_5750_OR_BEYOND(sc) || i == 0) {
3734 1.95 jonathan f->bge_rsvd = maxsegsize;
3735 1.95 jonathan f->bge_flags = csum_flags | txbd_tso_flags;
3736 1.95 jonathan } else {
3737 1.95 jonathan f->bge_rsvd = 0;
3738 1.95 jonathan f->bge_flags =
3739 1.95 jonathan (csum_flags | txbd_tso_flags) & 0x0fff;
3740 1.95 jonathan }
3741 1.95 jonathan } else {
3742 1.95 jonathan f->bge_rsvd = 0;
3743 1.95 jonathan f->bge_flags = csum_flags;
3744 1.95 jonathan }
3745 1.1 fvdl
3746 1.28 itojun if (mtag != NULL) {
3747 1.1 fvdl f->bge_flags |= BGE_TXBDFLAG_VLAN_TAG;
3748 1.85 jdolecek f->bge_vlan_tag = VLAN_TAG_VALUE(mtag);
3749 1.1 fvdl } else {
3750 1.1 fvdl f->bge_vlan_tag = 0;
3751 1.1 fvdl }
3752 1.1 fvdl /*
3753 1.1 fvdl * Sanity check: avoid coming within 16 descriptors
3754 1.1 fvdl * of the end of the ring.
3755 1.1 fvdl */
3756 1.95 jonathan if ((BGE_TX_RING_CNT - (sc->bge_txcnt + cnt)) < 16) {
3757 1.95 jonathan BGE_TSO_PRINTF(("%s: "
3758 1.95 jonathan " dmamap_load_mbuf too close to ring wrap\n",
3759 1.95 jonathan sc->bge_dev.dv_xname));
3760 1.1 fvdl return(ENOBUFS);
3761 1.95 jonathan }
3762 1.1 fvdl cur = frag;
3763 1.1 fvdl BGE_INC(frag, BGE_TX_RING_CNT);
3764 1.1 fvdl cnt++;
3765 1.1 fvdl }
3766 1.1 fvdl
3767 1.95 jonathan if (i < dmamap->dm_nsegs) {
3768 1.95 jonathan BGE_TSO_PRINTF(("%s: reached %d < dm_nsegs %d\n",
3769 1.95 jonathan sc->bge_dev.dv_xname, i, dmamap->dm_nsegs));
3770 1.1 fvdl return ENOBUFS;
3771 1.95 jonathan }
3772 1.1 fvdl
3773 1.1 fvdl bus_dmamap_sync(sc->bge_dmatag, dmamap, 0, dmamap->dm_mapsize,
3774 1.1 fvdl BUS_DMASYNC_PREWRITE);
3775 1.1 fvdl
3776 1.95 jonathan if (frag == sc->bge_tx_saved_considx) {
3777 1.95 jonathan BGE_TSO_PRINTF(("%s: frag %d = wrapped id %d?\n",
3778 1.95 jonathan sc->bge_dev.dv_xname, frag, sc->bge_tx_saved_considx));
3779 1.95 jonathan
3780 1.1 fvdl return(ENOBUFS);
3781 1.95 jonathan }
3782 1.1 fvdl
3783 1.1 fvdl sc->bge_rdata->bge_tx_ring[cur].bge_flags |= BGE_TXBDFLAG_END;
3784 1.1 fvdl sc->bge_cdata.bge_tx_chain[cur] = m_head;
3785 1.1 fvdl SLIST_REMOVE_HEAD(&sc->txdma_list, link);
3786 1.1 fvdl sc->txdma[cur] = dma;
3787 1.1 fvdl sc->bge_txcnt += cnt;
3788 1.1 fvdl
3789 1.1 fvdl *txidx = frag;
3790 1.1 fvdl
3791 1.1 fvdl return(0);
3792 1.1 fvdl }
3793 1.1 fvdl
3794 1.1 fvdl /*
3795 1.1 fvdl * Main transmit routine. To avoid having to do mbuf copies, we put pointers
3796 1.1 fvdl * to the mbuf data regions directly in the transmit descriptors.
3797 1.1 fvdl */
3798 1.1 fvdl void
3799 1.1 fvdl bge_start(ifp)
3800 1.1 fvdl struct ifnet *ifp;
3801 1.1 fvdl {
3802 1.1 fvdl struct bge_softc *sc;
3803 1.1 fvdl struct mbuf *m_head = NULL;
3804 1.94 jonathan u_int32_t prodidx;
3805 1.1 fvdl int pkts = 0;
3806 1.1 fvdl
3807 1.1 fvdl sc = ifp->if_softc;
3808 1.1 fvdl
3809 1.1 fvdl if (!sc->bge_link && ifp->if_snd.ifq_len < 10)
3810 1.1 fvdl return;
3811 1.1 fvdl
3812 1.94 jonathan prodidx = sc->bge_tx_prodidx;
3813 1.1 fvdl
3814 1.1 fvdl while(sc->bge_cdata.bge_tx_chain[prodidx] == NULL) {
3815 1.1 fvdl IFQ_POLL(&ifp->if_snd, m_head);
3816 1.1 fvdl if (m_head == NULL)
3817 1.1 fvdl break;
3818 1.1 fvdl
3819 1.1 fvdl #if 0
3820 1.1 fvdl /*
3821 1.1 fvdl * XXX
3822 1.1 fvdl * safety overkill. If this is a fragmented packet chain
3823 1.1 fvdl * with delayed TCP/UDP checksums, then only encapsulate
3824 1.1 fvdl * it if we have enough descriptors to handle the entire
3825 1.1 fvdl * chain at once.
3826 1.1 fvdl * (paranoia -- may not actually be needed)
3827 1.1 fvdl */
3828 1.1 fvdl if (m_head->m_flags & M_FIRSTFRAG &&
3829 1.1 fvdl m_head->m_pkthdr.csum_flags & (CSUM_DELAY_DATA)) {
3830 1.1 fvdl if ((BGE_TX_RING_CNT - sc->bge_txcnt) <
3831 1.86 thorpej M_CSUM_DATA_IPv4_OFFSET(m_head->m_pkthdr.csum_data) + 16) {
3832 1.1 fvdl ifp->if_flags |= IFF_OACTIVE;
3833 1.1 fvdl break;
3834 1.1 fvdl }
3835 1.1 fvdl }
3836 1.1 fvdl #endif
3837 1.1 fvdl
3838 1.1 fvdl /*
3839 1.1 fvdl * Pack the data into the transmit ring. If we
3840 1.1 fvdl * don't have room, set the OACTIVE flag and wait
3841 1.1 fvdl * for the NIC to drain the ring.
3842 1.1 fvdl */
3843 1.1 fvdl if (bge_encap(sc, m_head, &prodidx)) {
3844 1.95 jonathan printf("bge: failed on len %d?\n", m_head->m_pkthdr.len);
3845 1.1 fvdl ifp->if_flags |= IFF_OACTIVE;
3846 1.1 fvdl break;
3847 1.1 fvdl }
3848 1.1 fvdl
3849 1.1 fvdl /* now we are committed to transmit the packet */
3850 1.1 fvdl IFQ_DEQUEUE(&ifp->if_snd, m_head);
3851 1.1 fvdl pkts++;
3852 1.1 fvdl
3853 1.1 fvdl #if NBPFILTER > 0
3854 1.1 fvdl /*
3855 1.1 fvdl * If there's a BPF listener, bounce a copy of this frame
3856 1.1 fvdl * to him.
3857 1.1 fvdl */
3858 1.1 fvdl if (ifp->if_bpf)
3859 1.1 fvdl bpf_mtap(ifp->if_bpf, m_head);
3860 1.1 fvdl #endif
3861 1.1 fvdl }
3862 1.1 fvdl if (pkts == 0)
3863 1.1 fvdl return;
3864 1.1 fvdl
3865 1.1 fvdl /* Transmit */
3866 1.1 fvdl CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx);
3867 1.29 itojun if (sc->bge_quirks & BGE_QUIRK_PRODUCER_BUG) /* 5700 b2 errata */
3868 1.29 itojun CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx);
3869 1.1 fvdl
3870 1.94 jonathan sc->bge_tx_prodidx = prodidx;
3871 1.94 jonathan
3872 1.1 fvdl /*
3873 1.1 fvdl * Set a timeout in case the chip goes out to lunch.
3874 1.1 fvdl */
3875 1.1 fvdl ifp->if_timer = 5;
3876 1.1 fvdl }
3877 1.1 fvdl
3878 1.1 fvdl int
3879 1.1 fvdl bge_init(ifp)
3880 1.1 fvdl struct ifnet *ifp;
3881 1.1 fvdl {
3882 1.1 fvdl struct bge_softc *sc = ifp->if_softc;
3883 1.1 fvdl u_int16_t *m;
3884 1.1 fvdl int s, error;
3885 1.1 fvdl
3886 1.1 fvdl s = splnet();
3887 1.1 fvdl
3888 1.1 fvdl ifp = &sc->ethercom.ec_if;
3889 1.1 fvdl
3890 1.1 fvdl /* Cancel pending I/O and flush buffers. */
3891 1.1 fvdl bge_stop(sc);
3892 1.1 fvdl bge_reset(sc);
3893 1.1 fvdl bge_chipinit(sc);
3894 1.1 fvdl
3895 1.1 fvdl /*
3896 1.1 fvdl * Init the various state machines, ring
3897 1.1 fvdl * control blocks and firmware.
3898 1.1 fvdl */
3899 1.1 fvdl error = bge_blockinit(sc);
3900 1.1 fvdl if (error != 0) {
3901 1.1 fvdl printf("%s: initialization error %d\n", sc->bge_dev.dv_xname,
3902 1.1 fvdl error);
3903 1.1 fvdl splx(s);
3904 1.1 fvdl return error;
3905 1.1 fvdl }
3906 1.1 fvdl
3907 1.1 fvdl ifp = &sc->ethercom.ec_if;
3908 1.1 fvdl
3909 1.1 fvdl /* Specify MTU. */
3910 1.1 fvdl CSR_WRITE_4(sc, BGE_RX_MTU, ifp->if_mtu +
3911 1.93 tsarna ETHER_HDR_LEN + ETHER_CRC_LEN + ETHER_VLAN_ENCAP_LEN);
3912 1.1 fvdl
3913 1.1 fvdl /* Load our MAC address. */
3914 1.1 fvdl m = (u_int16_t *)&(LLADDR(ifp->if_sadl)[0]);
3915 1.1 fvdl CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0]));
3916 1.1 fvdl CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, (htons(m[1]) << 16) | htons(m[2]));
3917 1.1 fvdl
3918 1.1 fvdl /* Enable or disable promiscuous mode as needed. */
3919 1.1 fvdl if (ifp->if_flags & IFF_PROMISC) {
3920 1.1 fvdl BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC);
3921 1.1 fvdl } else {
3922 1.1 fvdl BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC);
3923 1.1 fvdl }
3924 1.1 fvdl
3925 1.1 fvdl /* Program multicast filter. */
3926 1.1 fvdl bge_setmulti(sc);
3927 1.1 fvdl
3928 1.1 fvdl /* Init RX ring. */
3929 1.1 fvdl bge_init_rx_ring_std(sc);
3930 1.1 fvdl
3931 1.1 fvdl /* Init jumbo RX ring. */
3932 1.1 fvdl if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN))
3933 1.1 fvdl bge_init_rx_ring_jumbo(sc);
3934 1.1 fvdl
3935 1.1 fvdl /* Init our RX return ring index */
3936 1.1 fvdl sc->bge_rx_saved_considx = 0;
3937 1.1 fvdl
3938 1.1 fvdl /* Init TX ring. */
3939 1.1 fvdl bge_init_tx_ring(sc);
3940 1.1 fvdl
3941 1.1 fvdl /* Turn on transmitter */
3942 1.1 fvdl BGE_SETBIT(sc, BGE_TX_MODE, BGE_TXMODE_ENABLE);
3943 1.1 fvdl
3944 1.1 fvdl /* Turn on receiver */
3945 1.1 fvdl BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE);
3946 1.1 fvdl
3947 1.71 thorpej CSR_WRITE_4(sc, BGE_MAX_RX_FRAME_LOWAT, 2);
3948 1.71 thorpej
3949 1.1 fvdl /* Tell firmware we're alive. */
3950 1.1 fvdl BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
3951 1.1 fvdl
3952 1.1 fvdl /* Enable host interrupts. */
3953 1.1 fvdl BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA);
3954 1.1 fvdl BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR);
3955 1.1 fvdl CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 0);
3956 1.1 fvdl
3957 1.1 fvdl bge_ifmedia_upd(ifp);
3958 1.1 fvdl
3959 1.1 fvdl ifp->if_flags |= IFF_RUNNING;
3960 1.1 fvdl ifp->if_flags &= ~IFF_OACTIVE;
3961 1.1 fvdl
3962 1.1 fvdl splx(s);
3963 1.1 fvdl
3964 1.1 fvdl callout_reset(&sc->bge_timeout, hz, bge_tick, sc);
3965 1.1 fvdl
3966 1.1 fvdl return 0;
3967 1.1 fvdl }
3968 1.1 fvdl
3969 1.1 fvdl /*
3970 1.1 fvdl * Set media options.
3971 1.1 fvdl */
3972 1.1 fvdl int
3973 1.1 fvdl bge_ifmedia_upd(ifp)
3974 1.1 fvdl struct ifnet *ifp;
3975 1.1 fvdl {
3976 1.1 fvdl struct bge_softc *sc = ifp->if_softc;
3977 1.1 fvdl struct mii_data *mii = &sc->bge_mii;
3978 1.1 fvdl struct ifmedia *ifm = &sc->bge_ifmedia;
3979 1.1 fvdl
3980 1.1 fvdl /* If this is a 1000baseX NIC, enable the TBI port. */
3981 1.1 fvdl if (sc->bge_tbi) {
3982 1.1 fvdl if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
3983 1.1 fvdl return(EINVAL);
3984 1.1 fvdl switch(IFM_SUBTYPE(ifm->ifm_media)) {
3985 1.1 fvdl case IFM_AUTO:
3986 1.1 fvdl break;
3987 1.1 fvdl case IFM_1000_SX:
3988 1.1 fvdl if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) {
3989 1.1 fvdl BGE_CLRBIT(sc, BGE_MAC_MODE,
3990 1.1 fvdl BGE_MACMODE_HALF_DUPLEX);
3991 1.1 fvdl } else {
3992 1.1 fvdl BGE_SETBIT(sc, BGE_MAC_MODE,
3993 1.1 fvdl BGE_MACMODE_HALF_DUPLEX);
3994 1.1 fvdl }
3995 1.1 fvdl break;
3996 1.1 fvdl default:
3997 1.1 fvdl return(EINVAL);
3998 1.1 fvdl }
3999 1.69 thorpej /* XXX 802.3x flow control for 1000BASE-SX */
4000 1.1 fvdl return(0);
4001 1.1 fvdl }
4002 1.1 fvdl
4003 1.1 fvdl sc->bge_link = 0;
4004 1.1 fvdl mii_mediachg(mii);
4005 1.1 fvdl
4006 1.1 fvdl return(0);
4007 1.1 fvdl }
4008 1.1 fvdl
4009 1.1 fvdl /*
4010 1.1 fvdl * Report current media status.
4011 1.1 fvdl */
4012 1.1 fvdl void
4013 1.1 fvdl bge_ifmedia_sts(ifp, ifmr)
4014 1.1 fvdl struct ifnet *ifp;
4015 1.1 fvdl struct ifmediareq *ifmr;
4016 1.1 fvdl {
4017 1.1 fvdl struct bge_softc *sc = ifp->if_softc;
4018 1.1 fvdl struct mii_data *mii = &sc->bge_mii;
4019 1.1 fvdl
4020 1.1 fvdl if (sc->bge_tbi) {
4021 1.1 fvdl ifmr->ifm_status = IFM_AVALID;
4022 1.1 fvdl ifmr->ifm_active = IFM_ETHER;
4023 1.1 fvdl if (CSR_READ_4(sc, BGE_MAC_STS) &
4024 1.1 fvdl BGE_MACSTAT_TBI_PCS_SYNCHED)
4025 1.1 fvdl ifmr->ifm_status |= IFM_ACTIVE;
4026 1.1 fvdl ifmr->ifm_active |= IFM_1000_SX;
4027 1.1 fvdl if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX)
4028 1.1 fvdl ifmr->ifm_active |= IFM_HDX;
4029 1.1 fvdl else
4030 1.1 fvdl ifmr->ifm_active |= IFM_FDX;
4031 1.1 fvdl return;
4032 1.1 fvdl }
4033 1.1 fvdl
4034 1.1 fvdl mii_pollstat(mii);
4035 1.1 fvdl ifmr->ifm_status = mii->mii_media_status;
4036 1.69 thorpej ifmr->ifm_active = (mii->mii_media_active & ~IFM_ETH_FMASK) |
4037 1.69 thorpej sc->bge_flowflags;
4038 1.1 fvdl }
4039 1.1 fvdl
4040 1.1 fvdl int
4041 1.1 fvdl bge_ioctl(ifp, command, data)
4042 1.1 fvdl struct ifnet *ifp;
4043 1.1 fvdl u_long command;
4044 1.1 fvdl caddr_t data;
4045 1.1 fvdl {
4046 1.1 fvdl struct bge_softc *sc = ifp->if_softc;
4047 1.1 fvdl struct ifreq *ifr = (struct ifreq *) data;
4048 1.1 fvdl int s, error = 0;
4049 1.1 fvdl struct mii_data *mii;
4050 1.1 fvdl
4051 1.1 fvdl s = splnet();
4052 1.1 fvdl
4053 1.1 fvdl switch(command) {
4054 1.1 fvdl case SIOCSIFFLAGS:
4055 1.1 fvdl if (ifp->if_flags & IFF_UP) {
4056 1.1 fvdl /*
4057 1.1 fvdl * If only the state of the PROMISC flag changed,
4058 1.1 fvdl * then just use the 'set promisc mode' command
4059 1.1 fvdl * instead of reinitializing the entire NIC. Doing
4060 1.1 fvdl * a full re-init means reloading the firmware and
4061 1.1 fvdl * waiting for it to start up, which may take a
4062 1.1 fvdl * second or two.
4063 1.1 fvdl */
4064 1.1 fvdl if (ifp->if_flags & IFF_RUNNING &&
4065 1.1 fvdl ifp->if_flags & IFF_PROMISC &&
4066 1.1 fvdl !(sc->bge_if_flags & IFF_PROMISC)) {
4067 1.1 fvdl BGE_SETBIT(sc, BGE_RX_MODE,
4068 1.1 fvdl BGE_RXMODE_RX_PROMISC);
4069 1.1 fvdl } else if (ifp->if_flags & IFF_RUNNING &&
4070 1.1 fvdl !(ifp->if_flags & IFF_PROMISC) &&
4071 1.1 fvdl sc->bge_if_flags & IFF_PROMISC) {
4072 1.1 fvdl BGE_CLRBIT(sc, BGE_RX_MODE,
4073 1.1 fvdl BGE_RXMODE_RX_PROMISC);
4074 1.103 rpaulo } else if (!(sc->bge_if_flags & IFF_UP))
4075 1.1 fvdl bge_init(ifp);
4076 1.1 fvdl } else {
4077 1.1 fvdl if (ifp->if_flags & IFF_RUNNING) {
4078 1.1 fvdl bge_stop(sc);
4079 1.1 fvdl }
4080 1.1 fvdl }
4081 1.1 fvdl sc->bge_if_flags = ifp->if_flags;
4082 1.1 fvdl error = 0;
4083 1.1 fvdl break;
4084 1.1 fvdl case SIOCSIFMEDIA:
4085 1.69 thorpej /* XXX Flow control is not supported for 1000BASE-SX */
4086 1.69 thorpej if (sc->bge_tbi) {
4087 1.69 thorpej ifr->ifr_media &= ~IFM_ETH_FMASK;
4088 1.69 thorpej sc->bge_flowflags = 0;
4089 1.69 thorpej }
4090 1.69 thorpej
4091 1.69 thorpej /* Flow control requires full-duplex mode. */
4092 1.69 thorpej if (IFM_SUBTYPE(ifr->ifr_media) == IFM_AUTO ||
4093 1.69 thorpej (ifr->ifr_media & IFM_FDX) == 0) {
4094 1.69 thorpej ifr->ifr_media &= ~IFM_ETH_FMASK;
4095 1.69 thorpej }
4096 1.69 thorpej if (IFM_SUBTYPE(ifr->ifr_media) != IFM_AUTO) {
4097 1.69 thorpej if ((ifr->ifr_media & IFM_ETH_FMASK) == IFM_FLOW) {
4098 1.69 thorpej /* We an do both TXPAUSE and RXPAUSE. */
4099 1.69 thorpej ifr->ifr_media |=
4100 1.69 thorpej IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE;
4101 1.69 thorpej }
4102 1.69 thorpej sc->bge_flowflags = ifr->ifr_media & IFM_ETH_FMASK;
4103 1.69 thorpej }
4104 1.69 thorpej /* FALLTHROUGH */
4105 1.1 fvdl case SIOCGIFMEDIA:
4106 1.1 fvdl if (sc->bge_tbi) {
4107 1.1 fvdl error = ifmedia_ioctl(ifp, ifr, &sc->bge_ifmedia,
4108 1.1 fvdl command);
4109 1.1 fvdl } else {
4110 1.1 fvdl mii = &sc->bge_mii;
4111 1.1 fvdl error = ifmedia_ioctl(ifp, ifr, &mii->mii_media,
4112 1.1 fvdl command);
4113 1.1 fvdl }
4114 1.1 fvdl break;
4115 1.1 fvdl default:
4116 1.1 fvdl error = ether_ioctl(ifp, command, data);
4117 1.1 fvdl if (error == ENETRESET) {
4118 1.77 thorpej if (ifp->if_flags & IFF_RUNNING)
4119 1.77 thorpej bge_setmulti(sc);
4120 1.1 fvdl error = 0;
4121 1.1 fvdl }
4122 1.1 fvdl break;
4123 1.1 fvdl }
4124 1.1 fvdl
4125 1.1 fvdl splx(s);
4126 1.1 fvdl
4127 1.1 fvdl return(error);
4128 1.1 fvdl }
4129 1.1 fvdl
4130 1.1 fvdl void
4131 1.1 fvdl bge_watchdog(ifp)
4132 1.1 fvdl struct ifnet *ifp;
4133 1.1 fvdl {
4134 1.1 fvdl struct bge_softc *sc;
4135 1.1 fvdl
4136 1.1 fvdl sc = ifp->if_softc;
4137 1.1 fvdl
4138 1.1 fvdl printf("%s: watchdog timeout -- resetting\n", sc->bge_dev.dv_xname);
4139 1.1 fvdl
4140 1.1 fvdl ifp->if_flags &= ~IFF_RUNNING;
4141 1.1 fvdl bge_init(ifp);
4142 1.1 fvdl
4143 1.1 fvdl ifp->if_oerrors++;
4144 1.1 fvdl }
4145 1.1 fvdl
4146 1.11 thorpej static void
4147 1.11 thorpej bge_stop_block(struct bge_softc *sc, bus_addr_t reg, uint32_t bit)
4148 1.11 thorpej {
4149 1.11 thorpej int i;
4150 1.11 thorpej
4151 1.11 thorpej BGE_CLRBIT(sc, reg, bit);
4152 1.11 thorpej
4153 1.11 thorpej for (i = 0; i < BGE_TIMEOUT; i++) {
4154 1.11 thorpej if ((CSR_READ_4(sc, reg) & bit) == 0)
4155 1.11 thorpej return;
4156 1.11 thorpej delay(100);
4157 1.95 jonathan if (sc->bge_pcie)
4158 1.95 jonathan DELAY(1000);
4159 1.11 thorpej }
4160 1.11 thorpej
4161 1.11 thorpej printf("%s: block failed to stop: reg 0x%lx, bit 0x%08x\n",
4162 1.11 thorpej sc->bge_dev.dv_xname, (u_long) reg, bit);
4163 1.11 thorpej }
4164 1.11 thorpej
4165 1.1 fvdl /*
4166 1.1 fvdl * Stop the adapter and free any mbufs allocated to the
4167 1.1 fvdl * RX and TX lists.
4168 1.1 fvdl */
4169 1.1 fvdl void
4170 1.1 fvdl bge_stop(sc)
4171 1.1 fvdl struct bge_softc *sc;
4172 1.1 fvdl {
4173 1.1 fvdl struct ifnet *ifp = &sc->ethercom.ec_if;
4174 1.1 fvdl
4175 1.1 fvdl callout_stop(&sc->bge_timeout);
4176 1.1 fvdl
4177 1.1 fvdl /*
4178 1.1 fvdl * Disable all of the receiver blocks
4179 1.1 fvdl */
4180 1.11 thorpej bge_stop_block(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE);
4181 1.11 thorpej bge_stop_block(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE);
4182 1.11 thorpej bge_stop_block(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);
4183 1.44 hannken if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) {
4184 1.44 hannken bge_stop_block(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE);
4185 1.44 hannken }
4186 1.11 thorpej bge_stop_block(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE);
4187 1.11 thorpej bge_stop_block(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);
4188 1.11 thorpej bge_stop_block(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE);
4189 1.1 fvdl
4190 1.1 fvdl /*
4191 1.1 fvdl * Disable all of the transmit blocks
4192 1.1 fvdl */
4193 1.11 thorpej bge_stop_block(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE);
4194 1.11 thorpej bge_stop_block(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE);
4195 1.11 thorpej bge_stop_block(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE);
4196 1.11 thorpej bge_stop_block(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE);
4197 1.11 thorpej bge_stop_block(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE);
4198 1.44 hannken if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) {
4199 1.44 hannken bge_stop_block(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE);
4200 1.44 hannken }
4201 1.11 thorpej bge_stop_block(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);
4202 1.1 fvdl
4203 1.1 fvdl /*
4204 1.1 fvdl * Shut down all of the memory managers and related
4205 1.1 fvdl * state machines.
4206 1.1 fvdl */
4207 1.11 thorpej bge_stop_block(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE);
4208 1.11 thorpej bge_stop_block(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE);
4209 1.44 hannken if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) {
4210 1.44 hannken bge_stop_block(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE);
4211 1.44 hannken }
4212 1.11 thorpej
4213 1.1 fvdl CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF);
4214 1.1 fvdl CSR_WRITE_4(sc, BGE_FTQ_RESET, 0);
4215 1.11 thorpej
4216 1.44 hannken if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) {
4217 1.44 hannken bge_stop_block(sc, BGE_BMAN_MODE, BGE_BMANMODE_ENABLE);
4218 1.44 hannken bge_stop_block(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE);
4219 1.44 hannken }
4220 1.1 fvdl
4221 1.1 fvdl /* Disable host interrupts. */
4222 1.1 fvdl BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR);
4223 1.1 fvdl CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 1);
4224 1.1 fvdl
4225 1.1 fvdl /*
4226 1.1 fvdl * Tell firmware we're shutting down.
4227 1.1 fvdl */
4228 1.1 fvdl BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
4229 1.1 fvdl
4230 1.1 fvdl /* Free the RX lists. */
4231 1.1 fvdl bge_free_rx_ring_std(sc);
4232 1.1 fvdl
4233 1.1 fvdl /* Free jumbo RX list. */
4234 1.1 fvdl bge_free_rx_ring_jumbo(sc);
4235 1.1 fvdl
4236 1.1 fvdl /* Free TX buffers. */
4237 1.1 fvdl bge_free_tx_ring(sc);
4238 1.1 fvdl
4239 1.1 fvdl /*
4240 1.1 fvdl * Isolate/power down the PHY.
4241 1.1 fvdl */
4242 1.1 fvdl if (!sc->bge_tbi)
4243 1.1 fvdl mii_down(&sc->bge_mii);
4244 1.1 fvdl
4245 1.1 fvdl sc->bge_link = 0;
4246 1.1 fvdl
4247 1.1 fvdl sc->bge_tx_saved_considx = BGE_TXCONS_UNSET;
4248 1.1 fvdl
4249 1.1 fvdl ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
4250 1.1 fvdl }
4251 1.1 fvdl
4252 1.1 fvdl /*
4253 1.1 fvdl * Stop all chip I/O so that the kernel's probe routines don't
4254 1.1 fvdl * get confused by errant DMAs when rebooting.
4255 1.1 fvdl */
4256 1.1 fvdl void
4257 1.1 fvdl bge_shutdown(xsc)
4258 1.1 fvdl void *xsc;
4259 1.1 fvdl {
4260 1.1 fvdl struct bge_softc *sc = (struct bge_softc *)xsc;
4261 1.1 fvdl
4262 1.1 fvdl bge_stop(sc);
4263 1.1 fvdl bge_reset(sc);
4264 1.1 fvdl }
4265 1.64 jonathan
4266 1.64 jonathan
4267 1.64 jonathan static int
4268 1.64 jonathan sysctl_bge_verify(SYSCTLFN_ARGS)
4269 1.64 jonathan {
4270 1.64 jonathan int error, t;
4271 1.64 jonathan struct sysctlnode node;
4272 1.64 jonathan
4273 1.64 jonathan node = *rnode;
4274 1.64 jonathan t = *(int*)rnode->sysctl_data;
4275 1.64 jonathan node.sysctl_data = &t;
4276 1.64 jonathan error = sysctl_lookup(SYSCTLFN_CALL(&node));
4277 1.64 jonathan if (error || newp == NULL)
4278 1.64 jonathan return (error);
4279 1.64 jonathan
4280 1.64 jonathan #if 0
4281 1.64 jonathan DPRINTF2(("%s: t = %d, nodenum = %d, rnodenum = %d\n", __func__, t,
4282 1.64 jonathan node.sysctl_num, rnode->sysctl_num));
4283 1.64 jonathan #endif
4284 1.64 jonathan
4285 1.64 jonathan if (node.sysctl_num == bge_rxthresh_nodenum) {
4286 1.64 jonathan if (t < 0 || t >= NBGE_RX_THRESH)
4287 1.64 jonathan return (EINVAL);
4288 1.64 jonathan bge_update_all_threshes(t);
4289 1.64 jonathan } else
4290 1.64 jonathan return (EINVAL);
4291 1.64 jonathan
4292 1.64 jonathan *(int*)rnode->sysctl_data = t;
4293 1.64 jonathan
4294 1.64 jonathan return (0);
4295 1.64 jonathan }
4296 1.64 jonathan
4297 1.64 jonathan /*
4298 1.65 atatat * Set up sysctl(3) MIB, hw.bge.*.
4299 1.64 jonathan *
4300 1.64 jonathan * TBD condition SYSCTL_PERMANENT on being an LKM or not
4301 1.64 jonathan */
4302 1.64 jonathan SYSCTL_SETUP(sysctl_bge, "sysctl bge subtree setup")
4303 1.64 jonathan {
4304 1.66 atatat int rc, bge_root_num;
4305 1.90 atatat const struct sysctlnode *node;
4306 1.64 jonathan
4307 1.64 jonathan if ((rc = sysctl_createv(clog, 0, NULL, NULL,
4308 1.64 jonathan CTLFLAG_PERMANENT, CTLTYPE_NODE, "hw", NULL,
4309 1.64 jonathan NULL, 0, NULL, 0, CTL_HW, CTL_EOL)) != 0) {
4310 1.64 jonathan goto err;
4311 1.64 jonathan }
4312 1.64 jonathan
4313 1.64 jonathan if ((rc = sysctl_createv(clog, 0, NULL, &node,
4314 1.73 atatat CTLFLAG_PERMANENT, CTLTYPE_NODE, "bge",
4315 1.73 atatat SYSCTL_DESCR("BGE interface controls"),
4316 1.64 jonathan NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL)) != 0) {
4317 1.64 jonathan goto err;
4318 1.64 jonathan }
4319 1.64 jonathan
4320 1.66 atatat bge_root_num = node->sysctl_num;
4321 1.66 atatat
4322 1.64 jonathan /* BGE Rx interrupt mitigation level */
4323 1.87 perry if ((rc = sysctl_createv(clog, 0, NULL, &node,
4324 1.64 jonathan CTLFLAG_PERMANENT|CTLFLAG_READWRITE,
4325 1.73 atatat CTLTYPE_INT, "rx_lvl",
4326 1.73 atatat SYSCTL_DESCR("BGE receive interrupt mitigation level"),
4327 1.73 atatat sysctl_bge_verify, 0,
4328 1.64 jonathan &bge_rx_thresh_lvl,
4329 1.66 atatat 0, CTL_HW, bge_root_num, CTL_CREATE,
4330 1.64 jonathan CTL_EOL)) != 0) {
4331 1.64 jonathan goto err;
4332 1.64 jonathan }
4333 1.64 jonathan
4334 1.64 jonathan bge_rxthresh_nodenum = node->sysctl_num;
4335 1.64 jonathan
4336 1.64 jonathan return;
4337 1.64 jonathan
4338 1.64 jonathan err:
4339 1.64 jonathan printf("%s: sysctl_createv failed (rc = %d)\n", __func__, rc);
4340 1.64 jonathan }
4341 1.82 jmcneill
4342 1.82 jmcneill void
4343 1.82 jmcneill bge_powerhook(int why, void *hdl)
4344 1.82 jmcneill {
4345 1.82 jmcneill struct bge_softc *sc = (struct bge_softc *)hdl;
4346 1.82 jmcneill struct ifnet *ifp = &sc->ethercom.ec_if;
4347 1.82 jmcneill struct pci_attach_args *pa = &(sc->bge_pa);
4348 1.82 jmcneill pci_chipset_tag_t pc = pa->pa_pc;
4349 1.82 jmcneill pcitag_t tag = pa->pa_tag;
4350 1.82 jmcneill
4351 1.82 jmcneill switch (why) {
4352 1.82 jmcneill case PWR_SOFTSUSPEND:
4353 1.82 jmcneill case PWR_SOFTSTANDBY:
4354 1.82 jmcneill bge_shutdown(sc);
4355 1.82 jmcneill break;
4356 1.82 jmcneill case PWR_SOFTRESUME:
4357 1.82 jmcneill if (ifp->if_flags & IFF_UP) {
4358 1.82 jmcneill ifp->if_flags &= ~IFF_RUNNING;
4359 1.82 jmcneill bge_init(ifp);
4360 1.82 jmcneill }
4361 1.82 jmcneill break;
4362 1.82 jmcneill case PWR_SUSPEND:
4363 1.82 jmcneill case PWR_STANDBY:
4364 1.82 jmcneill pci_conf_capture(pc, tag, &sc->bge_pciconf);
4365 1.83 jmcneill break;
4366 1.82 jmcneill case PWR_RESUME:
4367 1.82 jmcneill pci_conf_restore(pc, tag, &sc->bge_pciconf);
4368 1.82 jmcneill break;
4369 1.82 jmcneill }
4370 1.82 jmcneill
4371 1.82 jmcneill return;
4372 1.82 jmcneill }
4373