if_bge.c revision 1.26 1 1.26 jonathan /* $NetBSD: if_bge.c,v 1.26 2003/01/17 00:11:00 jonathan Exp $ */
2 1.8 thorpej
3 1.1 fvdl /*
4 1.1 fvdl * Copyright (c) 2001 Wind River Systems
5 1.1 fvdl * Copyright (c) 1997, 1998, 1999, 2001
6 1.1 fvdl * Bill Paul <wpaul (at) windriver.com>. All rights reserved.
7 1.1 fvdl *
8 1.1 fvdl * Redistribution and use in source and binary forms, with or without
9 1.1 fvdl * modification, are permitted provided that the following conditions
10 1.1 fvdl * are met:
11 1.1 fvdl * 1. Redistributions of source code must retain the above copyright
12 1.1 fvdl * notice, this list of conditions and the following disclaimer.
13 1.1 fvdl * 2. Redistributions in binary form must reproduce the above copyright
14 1.1 fvdl * notice, this list of conditions and the following disclaimer in the
15 1.1 fvdl * documentation and/or other materials provided with the distribution.
16 1.1 fvdl * 3. All advertising materials mentioning features or use of this software
17 1.1 fvdl * must display the following acknowledgement:
18 1.1 fvdl * This product includes software developed by Bill Paul.
19 1.1 fvdl * 4. Neither the name of the author nor the names of any co-contributors
20 1.1 fvdl * may be used to endorse or promote products derived from this software
21 1.1 fvdl * without specific prior written permission.
22 1.1 fvdl *
23 1.1 fvdl * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
24 1.1 fvdl * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
25 1.1 fvdl * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
26 1.1 fvdl * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
27 1.1 fvdl * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
28 1.1 fvdl * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
29 1.1 fvdl * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
30 1.1 fvdl * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
31 1.1 fvdl * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
32 1.1 fvdl * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
33 1.1 fvdl * THE POSSIBILITY OF SUCH DAMAGE.
34 1.1 fvdl *
35 1.1 fvdl * $FreeBSD: if_bge.c,v 1.13 2002/04/04 06:01:31 wpaul Exp $
36 1.1 fvdl */
37 1.1 fvdl
38 1.1 fvdl /*
39 1.12 thorpej * Broadcom BCM570x family gigabit ethernet driver for NetBSD.
40 1.1 fvdl *
41 1.12 thorpej * NetBSD version by:
42 1.12 thorpej *
43 1.12 thorpej * Frank van der Linden <fvdl (at) wasabisystems.com>
44 1.12 thorpej * Jason Thorpe <thorpej (at) wasabisystems.com>
45 1.25 jonathan * jonathan Stone <joanthan (at) dsg.stanford.edu>
46 1.12 thorpej *
47 1.12 thorpej * Originally written for FreeBSD by Bill Paul <wpaul (at) windriver.com>
48 1.1 fvdl * Senior Engineer, Wind River Systems
49 1.1 fvdl */
50 1.1 fvdl
51 1.1 fvdl /*
52 1.1 fvdl * The Broadcom BCM5700 is based on technology originally developed by
53 1.1 fvdl * Alteon Networks as part of the Tigon I and Tigon II gigabit ethernet
54 1.1 fvdl * MAC chips. The BCM5700, sometimes refered to as the Tigon III, has
55 1.1 fvdl * two on-board MIPS R4000 CPUs and can have as much as 16MB of external
56 1.1 fvdl * SSRAM. The BCM5700 supports TCP, UDP and IP checksum offload, jumbo
57 1.1 fvdl * frames, highly configurable RX filtering, and 16 RX and TX queues
58 1.1 fvdl * (which, along with RX filter rules, can be used for QOS applications).
59 1.1 fvdl * Other features, such as TCP segmentation, may be available as part
60 1.1 fvdl * of value-added firmware updates. Unlike the Tigon I and Tigon II,
61 1.1 fvdl * firmware images can be stored in hardware and need not be compiled
62 1.1 fvdl * into the driver.
63 1.1 fvdl *
64 1.1 fvdl * The BCM5700 supports the PCI v2.2 and PCI-X v1.0 standards, and will
65 1.1 fvdl * function in a 32-bit/64-bit 33/66Mhz bus, or a 64-bit/133Mhz bus.
66 1.1 fvdl *
67 1.1 fvdl * The BCM5701 is a single-chip solution incorporating both the BCM5700
68 1.25 jonathan * MAC and a BCM5401 10/100/1000 PHY. Unlike the BCM5700, the BCM5701
69 1.1 fvdl * does not support external SSRAM.
70 1.1 fvdl *
71 1.1 fvdl * Broadcom also produces a variation of the BCM5700 under the "Altima"
72 1.1 fvdl * brand name, which is functionally similar but lacks PCI-X support.
73 1.1 fvdl *
74 1.1 fvdl * Without external SSRAM, you can only have at most 4 TX rings,
75 1.1 fvdl * and the use of the mini RX ring is disabled. This seems to imply
76 1.1 fvdl * that these features are simply not available on the BCM5701. As a
77 1.1 fvdl * result, this driver does not implement any support for the mini RX
78 1.1 fvdl * ring.
79 1.1 fvdl */
80 1.1 fvdl
81 1.1 fvdl #include "bpfilter.h"
82 1.1 fvdl #include "vlan.h"
83 1.1 fvdl
84 1.1 fvdl #include <sys/param.h>
85 1.1 fvdl #include <sys/systm.h>
86 1.1 fvdl #include <sys/callout.h>
87 1.1 fvdl #include <sys/sockio.h>
88 1.1 fvdl #include <sys/mbuf.h>
89 1.1 fvdl #include <sys/malloc.h>
90 1.1 fvdl #include <sys/kernel.h>
91 1.1 fvdl #include <sys/device.h>
92 1.1 fvdl #include <sys/socket.h>
93 1.1 fvdl
94 1.1 fvdl #include <net/if.h>
95 1.1 fvdl #include <net/if_dl.h>
96 1.1 fvdl #include <net/if_media.h>
97 1.1 fvdl #include <net/if_ether.h>
98 1.1 fvdl
99 1.1 fvdl #ifdef INET
100 1.1 fvdl #include <netinet/in.h>
101 1.1 fvdl #include <netinet/in_systm.h>
102 1.1 fvdl #include <netinet/in_var.h>
103 1.1 fvdl #include <netinet/ip.h>
104 1.1 fvdl #endif
105 1.1 fvdl
106 1.1 fvdl #if NBPFILTER > 0
107 1.1 fvdl #include <net/bpf.h>
108 1.1 fvdl #endif
109 1.1 fvdl
110 1.1 fvdl #include <dev/pci/pcireg.h>
111 1.1 fvdl #include <dev/pci/pcivar.h>
112 1.1 fvdl #include <dev/pci/pcidevs.h>
113 1.1 fvdl
114 1.1 fvdl #include <dev/mii/mii.h>
115 1.1 fvdl #include <dev/mii/miivar.h>
116 1.1 fvdl #include <dev/mii/miidevs.h>
117 1.1 fvdl #include <dev/mii/brgphyreg.h>
118 1.1 fvdl
119 1.1 fvdl #include <dev/pci/if_bgereg.h>
120 1.1 fvdl
121 1.1 fvdl #include <uvm/uvm_extern.h>
122 1.1 fvdl
123 1.1 fvdl int bge_probe(struct device *, struct cfdata *, void *);
124 1.1 fvdl void bge_attach(struct device *, struct device *, void *);
125 1.1 fvdl void bge_release_resources(struct bge_softc *);
126 1.1 fvdl void bge_txeof(struct bge_softc *);
127 1.1 fvdl void bge_rxeof(struct bge_softc *);
128 1.1 fvdl
129 1.1 fvdl void bge_tick(void *);
130 1.1 fvdl void bge_stats_update(struct bge_softc *);
131 1.1 fvdl int bge_encap(struct bge_softc *, struct mbuf *, u_int32_t *);
132 1.1 fvdl
133 1.1 fvdl int bge_intr(void *);
134 1.1 fvdl void bge_start(struct ifnet *);
135 1.1 fvdl int bge_ioctl(struct ifnet *, u_long, caddr_t);
136 1.1 fvdl int bge_init(struct ifnet *);
137 1.1 fvdl void bge_stop(struct bge_softc *);
138 1.1 fvdl void bge_watchdog(struct ifnet *);
139 1.1 fvdl void bge_shutdown(void *);
140 1.1 fvdl int bge_ifmedia_upd(struct ifnet *);
141 1.1 fvdl void bge_ifmedia_sts(struct ifnet *, struct ifmediareq *);
142 1.1 fvdl
143 1.1 fvdl u_int8_t bge_eeprom_getbyte(struct bge_softc *, int, u_int8_t *);
144 1.1 fvdl int bge_read_eeprom(struct bge_softc *, caddr_t, int, int);
145 1.1 fvdl
146 1.1 fvdl void bge_setmulti(struct bge_softc *);
147 1.1 fvdl
148 1.1 fvdl void bge_handle_events(struct bge_softc *);
149 1.1 fvdl int bge_alloc_jumbo_mem(struct bge_softc *);
150 1.1 fvdl void bge_free_jumbo_mem(struct bge_softc *);
151 1.1 fvdl void *bge_jalloc(struct bge_softc *);
152 1.1 fvdl void bge_jfree(struct mbuf *, caddr_t, u_int, void *);
153 1.1 fvdl int bge_newbuf_std(struct bge_softc *, int, struct mbuf *, bus_dmamap_t);
154 1.1 fvdl int bge_newbuf_jumbo(struct bge_softc *, int, struct mbuf *);
155 1.1 fvdl int bge_init_rx_ring_std(struct bge_softc *);
156 1.1 fvdl void bge_free_rx_ring_std(struct bge_softc *);
157 1.1 fvdl int bge_init_rx_ring_jumbo(struct bge_softc *);
158 1.1 fvdl void bge_free_rx_ring_jumbo(struct bge_softc *);
159 1.1 fvdl void bge_free_tx_ring(struct bge_softc *);
160 1.1 fvdl int bge_init_tx_ring(struct bge_softc *);
161 1.1 fvdl
162 1.1 fvdl int bge_chipinit(struct bge_softc *);
163 1.1 fvdl int bge_blockinit(struct bge_softc *);
164 1.25 jonathan int bge_setpowerstate(struct bge_softc *, int);
165 1.1 fvdl
166 1.1 fvdl #ifdef notdef
167 1.1 fvdl u_int8_t bge_vpd_readbyte(struct bge_softc *, int);
168 1.1 fvdl void bge_vpd_read_res(struct bge_softc *, struct vpd_res *, int);
169 1.1 fvdl void bge_vpd_read(struct bge_softc *);
170 1.1 fvdl #endif
171 1.1 fvdl
172 1.1 fvdl u_int32_t bge_readmem_ind(struct bge_softc *, int);
173 1.1 fvdl void bge_writemem_ind(struct bge_softc *, int, int);
174 1.1 fvdl #ifdef notdef
175 1.1 fvdl u_int32_t bge_readreg_ind(struct bge_softc *, int);
176 1.1 fvdl #endif
177 1.1 fvdl void bge_writereg_ind(struct bge_softc *, int, int);
178 1.1 fvdl
179 1.1 fvdl int bge_miibus_readreg(struct device *, int, int);
180 1.1 fvdl void bge_miibus_writereg(struct device *, int, int, int);
181 1.1 fvdl void bge_miibus_statchg(struct device *);
182 1.1 fvdl
183 1.1 fvdl void bge_reset(struct bge_softc *);
184 1.1 fvdl
185 1.1 fvdl void bge_dump_status(struct bge_softc *);
186 1.1 fvdl void bge_dump_rxbd(struct bge_rx_bd *);
187 1.1 fvdl
188 1.1 fvdl #define BGE_DEBUG
189 1.1 fvdl #ifdef BGE_DEBUG
190 1.1 fvdl #define DPRINTF(x) if (bgedebug) printf x
191 1.1 fvdl #define DPRINTFN(n,x) if (bgedebug >= (n)) printf x
192 1.1 fvdl int bgedebug = 0;
193 1.1 fvdl #else
194 1.1 fvdl #define DPRINTF(x)
195 1.1 fvdl #define DPRINTFN(n,x)
196 1.1 fvdl #endif
197 1.1 fvdl
198 1.17 thorpej /* Various chip quirks. */
199 1.17 thorpej #define BGE_QUIRK_LINK_STATE_BROKEN 0x00000001
200 1.18 thorpej #define BGE_QUIRK_CSUM_BROKEN 0x00000002
201 1.24 matt #define BGE_QUIRK_ONLY_PHY_1 0x00000004
202 1.25 jonathan #define BGE_QUIRK_5700_SMALLDMA 0x00000008
203 1.25 jonathan #define BGE_QUIRK_5700_PCIX_REG_BUG 0x00000010
204 1.25 jonathan #define BGE_QUIRK_5700_PRODUCER_BUG 0x00000011
205 1.25 jonathan
206 1.25 jonathan /* following bugs are common to bcm5700 rev B, all flavours */
207 1.25 jonathan #define BGE_QUIRK_5700_COMMON \
208 1.25 jonathan (BGE_QUIRK_5700_SMALLDMA|BGE_QUIRK_PRODUCER_BUG)
209 1.17 thorpej
210 1.21 thorpej CFATTACH_DECL(bge, sizeof(struct bge_softc),
211 1.22 thorpej bge_probe, bge_attach, NULL, NULL);
212 1.1 fvdl
213 1.1 fvdl u_int32_t
214 1.1 fvdl bge_readmem_ind(sc, off)
215 1.1 fvdl struct bge_softc *sc;
216 1.1 fvdl int off;
217 1.1 fvdl {
218 1.1 fvdl struct pci_attach_args *pa = &(sc->bge_pa);
219 1.1 fvdl pcireg_t val;
220 1.1 fvdl
221 1.1 fvdl pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_MEMWIN_BASEADDR, off);
222 1.1 fvdl val = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_MEMWIN_DATA);
223 1.1 fvdl return val;
224 1.1 fvdl }
225 1.1 fvdl
226 1.1 fvdl void
227 1.1 fvdl bge_writemem_ind(sc, off, val)
228 1.1 fvdl struct bge_softc *sc;
229 1.1 fvdl int off, val;
230 1.1 fvdl {
231 1.1 fvdl struct pci_attach_args *pa = &(sc->bge_pa);
232 1.1 fvdl
233 1.1 fvdl pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_MEMWIN_BASEADDR, off);
234 1.1 fvdl pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_MEMWIN_DATA, val);
235 1.1 fvdl }
236 1.1 fvdl
237 1.1 fvdl #ifdef notdef
238 1.1 fvdl u_int32_t
239 1.1 fvdl bge_readreg_ind(sc, off)
240 1.1 fvdl struct bge_softc *sc;
241 1.1 fvdl int off;
242 1.1 fvdl {
243 1.1 fvdl struct pci_attach_args *pa = &(sc->bge_pa);
244 1.1 fvdl
245 1.1 fvdl pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_REG_BASEADDR, off);
246 1.1 fvdl return(pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_REG_DATA));
247 1.1 fvdl }
248 1.1 fvdl #endif
249 1.1 fvdl
250 1.1 fvdl void
251 1.1 fvdl bge_writereg_ind(sc, off, val)
252 1.1 fvdl struct bge_softc *sc;
253 1.1 fvdl int off, val;
254 1.1 fvdl {
255 1.1 fvdl struct pci_attach_args *pa = &(sc->bge_pa);
256 1.1 fvdl
257 1.1 fvdl pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_REG_BASEADDR, off);
258 1.1 fvdl pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_REG_DATA, val);
259 1.1 fvdl }
260 1.1 fvdl
261 1.1 fvdl #ifdef notdef
262 1.1 fvdl u_int8_t
263 1.1 fvdl bge_vpd_readbyte(sc, addr)
264 1.1 fvdl struct bge_softc *sc;
265 1.1 fvdl int addr;
266 1.1 fvdl {
267 1.1 fvdl int i;
268 1.1 fvdl u_int32_t val;
269 1.1 fvdl struct pci_attach_args *pa = &(sc->bge_pa);
270 1.1 fvdl
271 1.1 fvdl pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_VPD_ADDR, addr);
272 1.1 fvdl for (i = 0; i < BGE_TIMEOUT * 10; i++) {
273 1.1 fvdl DELAY(10);
274 1.1 fvdl if (pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_VPD_ADDR) &
275 1.1 fvdl BGE_VPD_FLAG)
276 1.1 fvdl break;
277 1.1 fvdl }
278 1.1 fvdl
279 1.1 fvdl if (i == BGE_TIMEOUT) {
280 1.1 fvdl printf("%s: VPD read timed out\n", sc->bge_dev.dv_xname);
281 1.1 fvdl return(0);
282 1.1 fvdl }
283 1.1 fvdl
284 1.1 fvdl val = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_VPD_DATA);
285 1.1 fvdl
286 1.1 fvdl return((val >> ((addr % 4) * 8)) & 0xFF);
287 1.1 fvdl }
288 1.1 fvdl
289 1.1 fvdl void
290 1.1 fvdl bge_vpd_read_res(sc, res, addr)
291 1.1 fvdl struct bge_softc *sc;
292 1.1 fvdl struct vpd_res *res;
293 1.1 fvdl int addr;
294 1.1 fvdl {
295 1.1 fvdl int i;
296 1.1 fvdl u_int8_t *ptr;
297 1.1 fvdl
298 1.1 fvdl ptr = (u_int8_t *)res;
299 1.1 fvdl for (i = 0; i < sizeof(struct vpd_res); i++)
300 1.1 fvdl ptr[i] = bge_vpd_readbyte(sc, i + addr);
301 1.1 fvdl }
302 1.1 fvdl
303 1.1 fvdl void
304 1.1 fvdl bge_vpd_read(sc)
305 1.1 fvdl struct bge_softc *sc;
306 1.1 fvdl {
307 1.1 fvdl int pos = 0, i;
308 1.1 fvdl struct vpd_res res;
309 1.1 fvdl
310 1.1 fvdl if (sc->bge_vpd_prodname != NULL)
311 1.1 fvdl free(sc->bge_vpd_prodname, M_DEVBUF);
312 1.1 fvdl if (sc->bge_vpd_readonly != NULL)
313 1.1 fvdl free(sc->bge_vpd_readonly, M_DEVBUF);
314 1.1 fvdl sc->bge_vpd_prodname = NULL;
315 1.1 fvdl sc->bge_vpd_readonly = NULL;
316 1.1 fvdl
317 1.1 fvdl bge_vpd_read_res(sc, &res, pos);
318 1.1 fvdl
319 1.1 fvdl if (res.vr_id != VPD_RES_ID) {
320 1.1 fvdl printf("%s: bad VPD resource id: expected %x got %x\n",
321 1.1 fvdl sc->bge_dev.dv_xname, VPD_RES_ID, res.vr_id);
322 1.1 fvdl return;
323 1.1 fvdl }
324 1.1 fvdl
325 1.1 fvdl pos += sizeof(res);
326 1.1 fvdl sc->bge_vpd_prodname = malloc(res.vr_len + 1, M_DEVBUF, M_NOWAIT);
327 1.1 fvdl if (sc->bge_vpd_prodname == NULL)
328 1.1 fvdl panic("bge_vpd_read");
329 1.1 fvdl for (i = 0; i < res.vr_len; i++)
330 1.1 fvdl sc->bge_vpd_prodname[i] = bge_vpd_readbyte(sc, i + pos);
331 1.1 fvdl sc->bge_vpd_prodname[i] = '\0';
332 1.1 fvdl pos += i;
333 1.1 fvdl
334 1.1 fvdl bge_vpd_read_res(sc, &res, pos);
335 1.1 fvdl
336 1.1 fvdl if (res.vr_id != VPD_RES_READ) {
337 1.1 fvdl printf("%s: bad VPD resource id: expected %x got %x\n",
338 1.1 fvdl sc->bge_dev.dv_xname, VPD_RES_READ, res.vr_id);
339 1.1 fvdl return;
340 1.1 fvdl }
341 1.1 fvdl
342 1.1 fvdl pos += sizeof(res);
343 1.1 fvdl sc->bge_vpd_readonly = malloc(res.vr_len, M_DEVBUF, M_NOWAIT);
344 1.1 fvdl if (sc->bge_vpd_readonly == NULL)
345 1.1 fvdl panic("bge_vpd_read");
346 1.1 fvdl for (i = 0; i < res.vr_len + 1; i++)
347 1.1 fvdl sc->bge_vpd_readonly[i] = bge_vpd_readbyte(sc, i + pos);
348 1.1 fvdl }
349 1.1 fvdl #endif
350 1.1 fvdl
351 1.1 fvdl /*
352 1.1 fvdl * Read a byte of data stored in the EEPROM at address 'addr.' The
353 1.1 fvdl * BCM570x supports both the traditional bitbang interface and an
354 1.1 fvdl * auto access interface for reading the EEPROM. We use the auto
355 1.1 fvdl * access method.
356 1.1 fvdl */
357 1.1 fvdl u_int8_t
358 1.1 fvdl bge_eeprom_getbyte(sc, addr, dest)
359 1.1 fvdl struct bge_softc *sc;
360 1.1 fvdl int addr;
361 1.1 fvdl u_int8_t *dest;
362 1.1 fvdl {
363 1.1 fvdl int i;
364 1.1 fvdl u_int32_t byte = 0;
365 1.1 fvdl
366 1.1 fvdl /*
367 1.1 fvdl * Enable use of auto EEPROM access so we can avoid
368 1.1 fvdl * having to use the bitbang method.
369 1.1 fvdl */
370 1.1 fvdl BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM);
371 1.1 fvdl
372 1.1 fvdl /* Reset the EEPROM, load the clock period. */
373 1.1 fvdl CSR_WRITE_4(sc, BGE_EE_ADDR,
374 1.1 fvdl BGE_EEADDR_RESET|BGE_EEHALFCLK(BGE_HALFCLK_384SCL));
375 1.1 fvdl DELAY(20);
376 1.1 fvdl
377 1.1 fvdl /* Issue the read EEPROM command. */
378 1.1 fvdl CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr);
379 1.1 fvdl
380 1.1 fvdl /* Wait for completion */
381 1.1 fvdl for(i = 0; i < BGE_TIMEOUT * 10; i++) {
382 1.1 fvdl DELAY(10);
383 1.1 fvdl if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE)
384 1.1 fvdl break;
385 1.1 fvdl }
386 1.1 fvdl
387 1.1 fvdl if (i == BGE_TIMEOUT) {
388 1.1 fvdl printf("%s: eeprom read timed out\n", sc->bge_dev.dv_xname);
389 1.1 fvdl return(0);
390 1.1 fvdl }
391 1.1 fvdl
392 1.1 fvdl /* Get result. */
393 1.1 fvdl byte = CSR_READ_4(sc, BGE_EE_DATA);
394 1.1 fvdl
395 1.1 fvdl *dest = (byte >> ((addr % 4) * 8)) & 0xFF;
396 1.1 fvdl
397 1.1 fvdl return(0);
398 1.1 fvdl }
399 1.1 fvdl
400 1.1 fvdl /*
401 1.1 fvdl * Read a sequence of bytes from the EEPROM.
402 1.1 fvdl */
403 1.1 fvdl int
404 1.1 fvdl bge_read_eeprom(sc, dest, off, cnt)
405 1.1 fvdl struct bge_softc *sc;
406 1.1 fvdl caddr_t dest;
407 1.1 fvdl int off;
408 1.1 fvdl int cnt;
409 1.1 fvdl {
410 1.1 fvdl int err = 0, i;
411 1.1 fvdl u_int8_t byte = 0;
412 1.1 fvdl
413 1.1 fvdl for (i = 0; i < cnt; i++) {
414 1.1 fvdl err = bge_eeprom_getbyte(sc, off + i, &byte);
415 1.1 fvdl if (err)
416 1.1 fvdl break;
417 1.1 fvdl *(dest + i) = byte;
418 1.1 fvdl }
419 1.1 fvdl
420 1.1 fvdl return(err ? 1 : 0);
421 1.1 fvdl }
422 1.1 fvdl
423 1.1 fvdl int
424 1.1 fvdl bge_miibus_readreg(dev, phy, reg)
425 1.1 fvdl struct device *dev;
426 1.1 fvdl int phy, reg;
427 1.1 fvdl {
428 1.1 fvdl struct bge_softc *sc = (struct bge_softc *)dev;
429 1.1 fvdl struct ifnet *ifp;
430 1.1 fvdl u_int32_t val;
431 1.25 jonathan u_int32_t saved_autopoll;
432 1.1 fvdl int i;
433 1.1 fvdl
434 1.1 fvdl ifp = &sc->ethercom.ec_if;
435 1.1 fvdl
436 1.25 jonathan /*
437 1.25 jonathan * Several chips with builtin PHYs will incorrectly answer to
438 1.25 jonathan * other PHY instances than the builtin PHY at id 1.
439 1.25 jonathan */
440 1.24 matt if (phy != 1 && (sc->bge_quirks & BGE_QUIRK_ONLY_PHY_1))
441 1.1 fvdl return(0);
442 1.1 fvdl
443 1.25 jonathan /* Reading with autopolling on may trigger PCI errors */
444 1.25 jonathan saved_autopoll = CSR_READ_4(sc, BGE_MI_MODE);
445 1.25 jonathan if (saved_autopoll & BGE_MIMODE_AUTOPOLL) {
446 1.25 jonathan CSR_WRITE_4(sc, BGE_MI_MODE,
447 1.25 jonathan saved_autopoll &~ BGE_MIMODE_AUTOPOLL);
448 1.25 jonathan DELAY(40);
449 1.25 jonathan }
450 1.25 jonathan
451 1.1 fvdl CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_READ|BGE_MICOMM_BUSY|
452 1.1 fvdl BGE_MIPHY(phy)|BGE_MIREG(reg));
453 1.1 fvdl
454 1.1 fvdl for (i = 0; i < BGE_TIMEOUT; i++) {
455 1.1 fvdl val = CSR_READ_4(sc, BGE_MI_COMM);
456 1.1 fvdl if (!(val & BGE_MICOMM_BUSY))
457 1.1 fvdl break;
458 1.9 thorpej delay(10);
459 1.1 fvdl }
460 1.1 fvdl
461 1.1 fvdl if (i == BGE_TIMEOUT) {
462 1.1 fvdl printf("%s: PHY read timed out\n", sc->bge_dev.dv_xname);
463 1.25 jonathan val = 0;
464 1.25 jonathan goto done;
465 1.1 fvdl }
466 1.1 fvdl
467 1.1 fvdl val = CSR_READ_4(sc, BGE_MI_COMM);
468 1.1 fvdl
469 1.25 jonathan done:
470 1.25 jonathan if (saved_autopoll & BGE_MIMODE_AUTOPOLL) {
471 1.25 jonathan CSR_WRITE_4(sc, BGE_MI_MODE, saved_autopoll);
472 1.25 jonathan DELAY(40);
473 1.25 jonathan }
474 1.25 jonathan
475 1.1 fvdl if (val & BGE_MICOMM_READFAIL)
476 1.1 fvdl return(0);
477 1.1 fvdl
478 1.1 fvdl return(val & 0xFFFF);
479 1.1 fvdl }
480 1.1 fvdl
481 1.1 fvdl void
482 1.1 fvdl bge_miibus_writereg(dev, phy, reg, val)
483 1.1 fvdl struct device *dev;
484 1.1 fvdl int phy, reg, val;
485 1.1 fvdl {
486 1.1 fvdl struct bge_softc *sc = (struct bge_softc *)dev;
487 1.25 jonathan u_int32_t saved_autopoll;
488 1.25 jonathan int i;
489 1.1 fvdl
490 1.25 jonathan /* Touching the PHY while autopolling is on may trigger PCI errors */
491 1.25 jonathan saved_autopoll = CSR_READ_4(sc, BGE_MI_MODE);
492 1.25 jonathan if (saved_autopoll & BGE_MIMODE_AUTOPOLL) {
493 1.25 jonathan delay(40);
494 1.25 jonathan CSR_WRITE_4(sc, BGE_MI_MODE,
495 1.25 jonathan saved_autopoll & (~BGE_MIMODE_AUTOPOLL));
496 1.25 jonathan delay(10); /* 40 usec is supposed to be adequate */
497 1.25 jonathan }
498 1.25 jonathan
499 1.1 fvdl CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_WRITE|BGE_MICOMM_BUSY|
500 1.1 fvdl BGE_MIPHY(phy)|BGE_MIREG(reg)|val);
501 1.1 fvdl
502 1.1 fvdl for (i = 0; i < BGE_TIMEOUT; i++) {
503 1.1 fvdl if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY))
504 1.1 fvdl break;
505 1.9 thorpej delay(10);
506 1.1 fvdl }
507 1.1 fvdl
508 1.25 jonathan if (saved_autopoll & BGE_MIMODE_AUTOPOLL) {
509 1.25 jonathan CSR_WRITE_4(sc, BGE_MI_MODE, saved_autopoll);
510 1.25 jonathan delay(40);
511 1.25 jonathan }
512 1.25 jonathan
513 1.1 fvdl if (i == BGE_TIMEOUT) {
514 1.1 fvdl printf("%s: PHY read timed out\n", sc->bge_dev.dv_xname);
515 1.1 fvdl }
516 1.1 fvdl }
517 1.1 fvdl
518 1.1 fvdl void
519 1.1 fvdl bge_miibus_statchg(dev)
520 1.1 fvdl struct device *dev;
521 1.1 fvdl {
522 1.1 fvdl struct bge_softc *sc = (struct bge_softc *)dev;
523 1.1 fvdl struct mii_data *mii = &sc->bge_mii;
524 1.1 fvdl
525 1.1 fvdl BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_PORTMODE);
526 1.1 fvdl if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) {
527 1.1 fvdl BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_GMII);
528 1.1 fvdl } else {
529 1.1 fvdl BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_MII);
530 1.1 fvdl }
531 1.1 fvdl
532 1.1 fvdl if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
533 1.1 fvdl BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX);
534 1.1 fvdl } else {
535 1.1 fvdl BGE_SETBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX);
536 1.1 fvdl }
537 1.1 fvdl }
538 1.1 fvdl
539 1.1 fvdl /*
540 1.1 fvdl * Handle events that have triggered interrupts.
541 1.1 fvdl */
542 1.1 fvdl void
543 1.1 fvdl bge_handle_events(sc)
544 1.1 fvdl struct bge_softc *sc;
545 1.1 fvdl {
546 1.1 fvdl
547 1.1 fvdl return;
548 1.1 fvdl }
549 1.1 fvdl
550 1.1 fvdl /*
551 1.1 fvdl * Memory management for jumbo frames.
552 1.1 fvdl */
553 1.1 fvdl
554 1.1 fvdl int
555 1.1 fvdl bge_alloc_jumbo_mem(sc)
556 1.1 fvdl struct bge_softc *sc;
557 1.1 fvdl {
558 1.1 fvdl caddr_t ptr, kva;
559 1.1 fvdl bus_dma_segment_t seg;
560 1.1 fvdl int i, rseg, state, error;
561 1.1 fvdl struct bge_jpool_entry *entry;
562 1.1 fvdl
563 1.1 fvdl state = error = 0;
564 1.1 fvdl
565 1.1 fvdl /* Grab a big chunk o' storage. */
566 1.1 fvdl if (bus_dmamem_alloc(sc->bge_dmatag, BGE_JMEM, PAGE_SIZE, 0,
567 1.1 fvdl &seg, 1, &rseg, BUS_DMA_NOWAIT)) {
568 1.1 fvdl printf("%s: can't alloc rx buffers\n", sc->bge_dev.dv_xname);
569 1.1 fvdl return ENOBUFS;
570 1.1 fvdl }
571 1.1 fvdl
572 1.1 fvdl state = 1;
573 1.1 fvdl if (bus_dmamem_map(sc->bge_dmatag, &seg, rseg, BGE_JMEM, &kva,
574 1.1 fvdl BUS_DMA_NOWAIT)) {
575 1.1 fvdl printf("%s: can't map dma buffers (%d bytes)\n",
576 1.1 fvdl sc->bge_dev.dv_xname, (int)BGE_JMEM);
577 1.1 fvdl error = ENOBUFS;
578 1.1 fvdl goto out;
579 1.1 fvdl }
580 1.1 fvdl
581 1.1 fvdl state = 2;
582 1.1 fvdl if (bus_dmamap_create(sc->bge_dmatag, BGE_JMEM, 1, BGE_JMEM, 0,
583 1.1 fvdl BUS_DMA_NOWAIT, &sc->bge_cdata.bge_rx_jumbo_map)) {
584 1.1 fvdl printf("%s: can't create dma map\n", sc->bge_dev.dv_xname);
585 1.1 fvdl error = ENOBUFS;
586 1.1 fvdl goto out;
587 1.1 fvdl }
588 1.1 fvdl
589 1.1 fvdl state = 3;
590 1.1 fvdl if (bus_dmamap_load(sc->bge_dmatag, sc->bge_cdata.bge_rx_jumbo_map,
591 1.1 fvdl kva, BGE_JMEM, NULL, BUS_DMA_NOWAIT)) {
592 1.1 fvdl printf("%s: can't load dma map\n", sc->bge_dev.dv_xname);
593 1.1 fvdl error = ENOBUFS;
594 1.1 fvdl goto out;
595 1.1 fvdl }
596 1.1 fvdl
597 1.1 fvdl state = 4;
598 1.1 fvdl sc->bge_cdata.bge_jumbo_buf = (caddr_t)kva;
599 1.1 fvdl DPRINTFN(1,("bge_jumbo_buf = 0x%p\n", sc->bge_cdata.bge_jumbo_buf));
600 1.1 fvdl
601 1.1 fvdl SLIST_INIT(&sc->bge_jfree_listhead);
602 1.1 fvdl SLIST_INIT(&sc->bge_jinuse_listhead);
603 1.1 fvdl
604 1.1 fvdl /*
605 1.1 fvdl * Now divide it up into 9K pieces and save the addresses
606 1.1 fvdl * in an array.
607 1.1 fvdl */
608 1.1 fvdl ptr = sc->bge_cdata.bge_jumbo_buf;
609 1.1 fvdl for (i = 0; i < BGE_JSLOTS; i++) {
610 1.1 fvdl sc->bge_cdata.bge_jslots[i] = ptr;
611 1.1 fvdl ptr += BGE_JLEN;
612 1.1 fvdl entry = malloc(sizeof(struct bge_jpool_entry),
613 1.1 fvdl M_DEVBUF, M_NOWAIT);
614 1.1 fvdl if (entry == NULL) {
615 1.1 fvdl printf("%s: no memory for jumbo buffer queue!\n",
616 1.1 fvdl sc->bge_dev.dv_xname);
617 1.1 fvdl error = ENOBUFS;
618 1.1 fvdl goto out;
619 1.1 fvdl }
620 1.1 fvdl entry->slot = i;
621 1.1 fvdl SLIST_INSERT_HEAD(&sc->bge_jfree_listhead,
622 1.1 fvdl entry, jpool_entries);
623 1.1 fvdl }
624 1.1 fvdl out:
625 1.1 fvdl if (error != 0) {
626 1.1 fvdl switch (state) {
627 1.1 fvdl case 4:
628 1.1 fvdl bus_dmamap_unload(sc->bge_dmatag,
629 1.1 fvdl sc->bge_cdata.bge_rx_jumbo_map);
630 1.1 fvdl case 3:
631 1.1 fvdl bus_dmamap_destroy(sc->bge_dmatag,
632 1.1 fvdl sc->bge_cdata.bge_rx_jumbo_map);
633 1.1 fvdl case 2:
634 1.1 fvdl bus_dmamem_unmap(sc->bge_dmatag, kva, BGE_JMEM);
635 1.1 fvdl case 1:
636 1.1 fvdl bus_dmamem_free(sc->bge_dmatag, &seg, rseg);
637 1.1 fvdl break;
638 1.1 fvdl default:
639 1.1 fvdl break;
640 1.1 fvdl }
641 1.1 fvdl }
642 1.1 fvdl
643 1.1 fvdl return error;
644 1.1 fvdl }
645 1.1 fvdl
646 1.1 fvdl /*
647 1.1 fvdl * Allocate a jumbo buffer.
648 1.1 fvdl */
649 1.1 fvdl void *
650 1.1 fvdl bge_jalloc(sc)
651 1.1 fvdl struct bge_softc *sc;
652 1.1 fvdl {
653 1.1 fvdl struct bge_jpool_entry *entry;
654 1.1 fvdl
655 1.1 fvdl entry = SLIST_FIRST(&sc->bge_jfree_listhead);
656 1.1 fvdl
657 1.1 fvdl if (entry == NULL) {
658 1.1 fvdl printf("%s: no free jumbo buffers\n", sc->bge_dev.dv_xname);
659 1.1 fvdl return(NULL);
660 1.1 fvdl }
661 1.1 fvdl
662 1.1 fvdl SLIST_REMOVE_HEAD(&sc->bge_jfree_listhead, jpool_entries);
663 1.1 fvdl SLIST_INSERT_HEAD(&sc->bge_jinuse_listhead, entry, jpool_entries);
664 1.1 fvdl return(sc->bge_cdata.bge_jslots[entry->slot]);
665 1.1 fvdl }
666 1.1 fvdl
667 1.1 fvdl /*
668 1.1 fvdl * Release a jumbo buffer.
669 1.1 fvdl */
670 1.1 fvdl void
671 1.1 fvdl bge_jfree(m, buf, size, arg)
672 1.1 fvdl struct mbuf *m;
673 1.1 fvdl caddr_t buf;
674 1.1 fvdl u_int size;
675 1.1 fvdl void *arg;
676 1.1 fvdl {
677 1.1 fvdl struct bge_jpool_entry *entry;
678 1.1 fvdl struct bge_softc *sc;
679 1.1 fvdl int i, s;
680 1.1 fvdl
681 1.1 fvdl /* Extract the softc struct pointer. */
682 1.1 fvdl sc = (struct bge_softc *)arg;
683 1.1 fvdl
684 1.1 fvdl if (sc == NULL)
685 1.1 fvdl panic("bge_jfree: can't find softc pointer!");
686 1.1 fvdl
687 1.1 fvdl /* calculate the slot this buffer belongs to */
688 1.1 fvdl
689 1.1 fvdl i = ((caddr_t)buf
690 1.1 fvdl - (caddr_t)sc->bge_cdata.bge_jumbo_buf) / BGE_JLEN;
691 1.1 fvdl
692 1.1 fvdl if ((i < 0) || (i >= BGE_JSLOTS))
693 1.1 fvdl panic("bge_jfree: asked to free buffer that we don't manage!");
694 1.1 fvdl
695 1.1 fvdl s = splvm();
696 1.1 fvdl entry = SLIST_FIRST(&sc->bge_jinuse_listhead);
697 1.1 fvdl if (entry == NULL)
698 1.1 fvdl panic("bge_jfree: buffer not in use!");
699 1.1 fvdl entry->slot = i;
700 1.1 fvdl SLIST_REMOVE_HEAD(&sc->bge_jinuse_listhead, jpool_entries);
701 1.1 fvdl SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, entry, jpool_entries);
702 1.1 fvdl
703 1.1 fvdl if (__predict_true(m != NULL))
704 1.1 fvdl pool_cache_put(&mbpool_cache, m);
705 1.1 fvdl splx(s);
706 1.1 fvdl }
707 1.1 fvdl
708 1.1 fvdl
709 1.1 fvdl /*
710 1.1 fvdl * Intialize a standard receive ring descriptor.
711 1.1 fvdl */
712 1.1 fvdl int
713 1.1 fvdl bge_newbuf_std(sc, i, m, dmamap)
714 1.1 fvdl struct bge_softc *sc;
715 1.1 fvdl int i;
716 1.1 fvdl struct mbuf *m;
717 1.1 fvdl bus_dmamap_t dmamap;
718 1.1 fvdl {
719 1.1 fvdl struct mbuf *m_new = NULL;
720 1.1 fvdl struct bge_rx_bd *r;
721 1.1 fvdl int error;
722 1.1 fvdl
723 1.1 fvdl if (dmamap == NULL) {
724 1.1 fvdl error = bus_dmamap_create(sc->bge_dmatag, MCLBYTES, 1,
725 1.1 fvdl MCLBYTES, 0, BUS_DMA_NOWAIT, &dmamap);
726 1.1 fvdl if (error != 0)
727 1.1 fvdl return error;
728 1.1 fvdl }
729 1.1 fvdl
730 1.1 fvdl sc->bge_cdata.bge_rx_std_map[i] = dmamap;
731 1.1 fvdl
732 1.1 fvdl if (m == NULL) {
733 1.1 fvdl MGETHDR(m_new, M_DONTWAIT, MT_DATA);
734 1.1 fvdl if (m_new == NULL) {
735 1.1 fvdl return(ENOBUFS);
736 1.1 fvdl }
737 1.1 fvdl
738 1.1 fvdl MCLGET(m_new, M_DONTWAIT);
739 1.1 fvdl if (!(m_new->m_flags & M_EXT)) {
740 1.1 fvdl m_freem(m_new);
741 1.1 fvdl return(ENOBUFS);
742 1.1 fvdl }
743 1.1 fvdl m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
744 1.10 fvdl m_adj(m_new, ETHER_ALIGN);
745 1.1 fvdl
746 1.1 fvdl if (bus_dmamap_load_mbuf(sc->bge_dmatag, dmamap, m_new,
747 1.1 fvdl BUS_DMA_READ|BUS_DMA_NOWAIT))
748 1.1 fvdl return(ENOBUFS);
749 1.1 fvdl } else {
750 1.1 fvdl m_new = m;
751 1.1 fvdl m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
752 1.1 fvdl m_new->m_data = m_new->m_ext.ext_buf;
753 1.10 fvdl m_adj(m_new, ETHER_ALIGN);
754 1.1 fvdl }
755 1.1 fvdl
756 1.1 fvdl sc->bge_cdata.bge_rx_std_chain[i] = m_new;
757 1.1 fvdl r = &sc->bge_rdata->bge_rx_std_ring[i];
758 1.1 fvdl bge_set_hostaddr(&r->bge_addr,
759 1.10 fvdl dmamap->dm_segs[0].ds_addr);
760 1.1 fvdl r->bge_flags = BGE_RXBDFLAG_END;
761 1.1 fvdl r->bge_len = m_new->m_len;
762 1.1 fvdl r->bge_idx = i;
763 1.1 fvdl
764 1.1 fvdl bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map,
765 1.1 fvdl offsetof(struct bge_ring_data, bge_rx_std_ring) +
766 1.1 fvdl i * sizeof (struct bge_rx_bd),
767 1.1 fvdl sizeof (struct bge_rx_bd),
768 1.1 fvdl BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD);
769 1.1 fvdl
770 1.1 fvdl return(0);
771 1.1 fvdl }
772 1.1 fvdl
773 1.1 fvdl /*
774 1.1 fvdl * Initialize a jumbo receive ring descriptor. This allocates
775 1.1 fvdl * a jumbo buffer from the pool managed internally by the driver.
776 1.1 fvdl */
777 1.1 fvdl int
778 1.1 fvdl bge_newbuf_jumbo(sc, i, m)
779 1.1 fvdl struct bge_softc *sc;
780 1.1 fvdl int i;
781 1.1 fvdl struct mbuf *m;
782 1.1 fvdl {
783 1.1 fvdl struct mbuf *m_new = NULL;
784 1.1 fvdl struct bge_rx_bd *r;
785 1.1 fvdl
786 1.1 fvdl if (m == NULL) {
787 1.1 fvdl caddr_t *buf = NULL;
788 1.1 fvdl
789 1.1 fvdl /* Allocate the mbuf. */
790 1.1 fvdl MGETHDR(m_new, M_DONTWAIT, MT_DATA);
791 1.1 fvdl if (m_new == NULL) {
792 1.1 fvdl return(ENOBUFS);
793 1.1 fvdl }
794 1.1 fvdl
795 1.1 fvdl /* Allocate the jumbo buffer */
796 1.1 fvdl buf = bge_jalloc(sc);
797 1.1 fvdl if (buf == NULL) {
798 1.1 fvdl m_freem(m_new);
799 1.1 fvdl printf("%s: jumbo allocation failed "
800 1.1 fvdl "-- packet dropped!\n", sc->bge_dev.dv_xname);
801 1.1 fvdl return(ENOBUFS);
802 1.1 fvdl }
803 1.1 fvdl
804 1.1 fvdl /* Attach the buffer to the mbuf. */
805 1.1 fvdl m_new->m_len = m_new->m_pkthdr.len = BGE_JUMBO_FRAMELEN;
806 1.1 fvdl MEXTADD(m_new, buf, BGE_JUMBO_FRAMELEN, M_DEVBUF,
807 1.1 fvdl bge_jfree, sc);
808 1.1 fvdl } else {
809 1.1 fvdl m_new = m;
810 1.1 fvdl m_new->m_data = m_new->m_ext.ext_buf;
811 1.1 fvdl m_new->m_ext.ext_size = BGE_JUMBO_FRAMELEN;
812 1.1 fvdl }
813 1.1 fvdl
814 1.1 fvdl m_adj(m_new, ETHER_ALIGN);
815 1.1 fvdl /* Set up the descriptor. */
816 1.1 fvdl r = &sc->bge_rdata->bge_rx_jumbo_ring[i];
817 1.1 fvdl sc->bge_cdata.bge_rx_jumbo_chain[i] = m_new;
818 1.1 fvdl bge_set_hostaddr(&r->bge_addr, BGE_JUMBO_DMA_ADDR(sc, m_new));
819 1.1 fvdl r->bge_flags = BGE_RXBDFLAG_END|BGE_RXBDFLAG_JUMBO_RING;
820 1.1 fvdl r->bge_len = m_new->m_len;
821 1.1 fvdl r->bge_idx = i;
822 1.1 fvdl
823 1.1 fvdl bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map,
824 1.1 fvdl offsetof(struct bge_ring_data, bge_rx_jumbo_ring) +
825 1.1 fvdl i * sizeof (struct bge_rx_bd),
826 1.1 fvdl sizeof (struct bge_rx_bd),
827 1.1 fvdl BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD);
828 1.1 fvdl
829 1.1 fvdl return(0);
830 1.1 fvdl }
831 1.1 fvdl
832 1.1 fvdl /*
833 1.1 fvdl * The standard receive ring has 512 entries in it. At 2K per mbuf cluster,
834 1.1 fvdl * that's 1MB or memory, which is a lot. For now, we fill only the first
835 1.1 fvdl * 256 ring entries and hope that our CPU is fast enough to keep up with
836 1.1 fvdl * the NIC.
837 1.1 fvdl */
838 1.1 fvdl int
839 1.1 fvdl bge_init_rx_ring_std(sc)
840 1.1 fvdl struct bge_softc *sc;
841 1.1 fvdl {
842 1.1 fvdl int i;
843 1.1 fvdl
844 1.1 fvdl if (sc->bge_flags & BGE_RXRING_VALID)
845 1.1 fvdl return 0;
846 1.1 fvdl
847 1.1 fvdl for (i = 0; i < BGE_SSLOTS; i++) {
848 1.1 fvdl if (bge_newbuf_std(sc, i, NULL, 0) == ENOBUFS)
849 1.1 fvdl return(ENOBUFS);
850 1.1 fvdl }
851 1.1 fvdl
852 1.1 fvdl sc->bge_std = i - 1;
853 1.1 fvdl CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std);
854 1.1 fvdl
855 1.1 fvdl sc->bge_flags |= BGE_RXRING_VALID;
856 1.1 fvdl
857 1.1 fvdl return(0);
858 1.1 fvdl }
859 1.1 fvdl
860 1.1 fvdl void
861 1.1 fvdl bge_free_rx_ring_std(sc)
862 1.1 fvdl struct bge_softc *sc;
863 1.1 fvdl {
864 1.1 fvdl int i;
865 1.1 fvdl
866 1.1 fvdl if (!(sc->bge_flags & BGE_RXRING_VALID))
867 1.1 fvdl return;
868 1.1 fvdl
869 1.1 fvdl for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
870 1.1 fvdl if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) {
871 1.1 fvdl m_freem(sc->bge_cdata.bge_rx_std_chain[i]);
872 1.1 fvdl sc->bge_cdata.bge_rx_std_chain[i] = NULL;
873 1.1 fvdl bus_dmamap_destroy(sc->bge_dmatag,
874 1.1 fvdl sc->bge_cdata.bge_rx_std_map[i]);
875 1.1 fvdl }
876 1.1 fvdl memset((char *)&sc->bge_rdata->bge_rx_std_ring[i], 0,
877 1.1 fvdl sizeof(struct bge_rx_bd));
878 1.1 fvdl }
879 1.1 fvdl
880 1.1 fvdl sc->bge_flags &= ~BGE_RXRING_VALID;
881 1.1 fvdl }
882 1.1 fvdl
883 1.1 fvdl int
884 1.1 fvdl bge_init_rx_ring_jumbo(sc)
885 1.1 fvdl struct bge_softc *sc;
886 1.1 fvdl {
887 1.1 fvdl int i;
888 1.1 fvdl struct bge_rcb *rcb;
889 1.1 fvdl struct bge_rcb_opaque *rcbo;
890 1.1 fvdl
891 1.1 fvdl for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
892 1.1 fvdl if (bge_newbuf_jumbo(sc, i, NULL) == ENOBUFS)
893 1.1 fvdl return(ENOBUFS);
894 1.1 fvdl };
895 1.1 fvdl
896 1.1 fvdl sc->bge_jumbo = i - 1;
897 1.1 fvdl
898 1.1 fvdl rcb = &sc->bge_rdata->bge_info.bge_jumbo_rx_rcb;
899 1.1 fvdl rcbo = (struct bge_rcb_opaque *)rcb;
900 1.1 fvdl rcb->bge_flags = 0;
901 1.1 fvdl CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcbo->bge_reg2);
902 1.1 fvdl
903 1.1 fvdl CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo);
904 1.1 fvdl
905 1.1 fvdl return(0);
906 1.1 fvdl }
907 1.1 fvdl
908 1.1 fvdl void
909 1.1 fvdl bge_free_rx_ring_jumbo(sc)
910 1.1 fvdl struct bge_softc *sc;
911 1.1 fvdl {
912 1.1 fvdl int i;
913 1.1 fvdl
914 1.1 fvdl if (!(sc->bge_flags & BGE_JUMBO_RXRING_VALID))
915 1.1 fvdl return;
916 1.1 fvdl
917 1.1 fvdl for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
918 1.1 fvdl if (sc->bge_cdata.bge_rx_jumbo_chain[i] != NULL) {
919 1.1 fvdl m_freem(sc->bge_cdata.bge_rx_jumbo_chain[i]);
920 1.1 fvdl sc->bge_cdata.bge_rx_jumbo_chain[i] = NULL;
921 1.1 fvdl }
922 1.1 fvdl memset((char *)&sc->bge_rdata->bge_rx_jumbo_ring[i], 0,
923 1.1 fvdl sizeof(struct bge_rx_bd));
924 1.1 fvdl }
925 1.1 fvdl
926 1.1 fvdl sc->bge_flags &= ~BGE_JUMBO_RXRING_VALID;
927 1.1 fvdl }
928 1.1 fvdl
929 1.1 fvdl void
930 1.1 fvdl bge_free_tx_ring(sc)
931 1.1 fvdl struct bge_softc *sc;
932 1.1 fvdl {
933 1.1 fvdl int i, freed;
934 1.1 fvdl struct txdmamap_pool_entry *dma;
935 1.1 fvdl
936 1.1 fvdl if (!(sc->bge_flags & BGE_TXRING_VALID))
937 1.1 fvdl return;
938 1.1 fvdl
939 1.1 fvdl freed = 0;
940 1.1 fvdl
941 1.1 fvdl for (i = 0; i < BGE_TX_RING_CNT; i++) {
942 1.1 fvdl if (sc->bge_cdata.bge_tx_chain[i] != NULL) {
943 1.1 fvdl freed++;
944 1.1 fvdl m_freem(sc->bge_cdata.bge_tx_chain[i]);
945 1.1 fvdl sc->bge_cdata.bge_tx_chain[i] = NULL;
946 1.1 fvdl SLIST_INSERT_HEAD(&sc->txdma_list, sc->txdma[i],
947 1.1 fvdl link);
948 1.1 fvdl sc->txdma[i] = 0;
949 1.1 fvdl }
950 1.1 fvdl memset((char *)&sc->bge_rdata->bge_tx_ring[i], 0,
951 1.1 fvdl sizeof(struct bge_tx_bd));
952 1.1 fvdl }
953 1.1 fvdl
954 1.1 fvdl while ((dma = SLIST_FIRST(&sc->txdma_list))) {
955 1.1 fvdl SLIST_REMOVE_HEAD(&sc->txdma_list, link);
956 1.1 fvdl bus_dmamap_destroy(sc->bge_dmatag, dma->dmamap);
957 1.1 fvdl free(dma, M_DEVBUF);
958 1.1 fvdl }
959 1.1 fvdl
960 1.1 fvdl sc->bge_flags &= ~BGE_TXRING_VALID;
961 1.1 fvdl }
962 1.1 fvdl
963 1.1 fvdl int
964 1.1 fvdl bge_init_tx_ring(sc)
965 1.1 fvdl struct bge_softc *sc;
966 1.1 fvdl {
967 1.1 fvdl int i;
968 1.1 fvdl bus_dmamap_t dmamap;
969 1.1 fvdl struct txdmamap_pool_entry *dma;
970 1.1 fvdl
971 1.1 fvdl if (sc->bge_flags & BGE_TXRING_VALID)
972 1.1 fvdl return 0;
973 1.1 fvdl
974 1.1 fvdl sc->bge_txcnt = 0;
975 1.1 fvdl sc->bge_tx_saved_considx = 0;
976 1.1 fvdl CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, 0);
977 1.25 jonathan if (sc->bge_quirks & BGE_QUIRK_PRODUCER_BUG) /* 5700 b2 errata */
978 1.25 jonathan CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, 0);
979 1.25 jonathan
980 1.1 fvdl CSR_WRITE_4(sc, BGE_MBX_TX_NIC_PROD0_LO, 0);
981 1.25 jonathan if (sc->bge_quirks & BGE_QUIRK_PRODUCER_BUG) /* 5700 b2 errata */
982 1.25 jonathan CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, 0);
983 1.1 fvdl
984 1.1 fvdl SLIST_INIT(&sc->txdma_list);
985 1.1 fvdl for (i = 0; i < BGE_RSLOTS; i++) {
986 1.1 fvdl if (bus_dmamap_create(sc->bge_dmatag, ETHER_MAX_LEN_JUMBO,
987 1.1 fvdl BGE_NTXSEG, ETHER_MAX_LEN_JUMBO, 0, BUS_DMA_NOWAIT,
988 1.1 fvdl &dmamap))
989 1.1 fvdl return(ENOBUFS);
990 1.1 fvdl if (dmamap == NULL)
991 1.1 fvdl panic("dmamap NULL in bge_init_tx_ring");
992 1.1 fvdl dma = malloc(sizeof(*dma), M_DEVBUF, M_NOWAIT);
993 1.1 fvdl if (dma == NULL) {
994 1.1 fvdl printf("%s: can't alloc txdmamap_pool_entry\n",
995 1.1 fvdl sc->bge_dev.dv_xname);
996 1.1 fvdl bus_dmamap_destroy(sc->bge_dmatag, dmamap);
997 1.1 fvdl return (ENOMEM);
998 1.1 fvdl }
999 1.1 fvdl dma->dmamap = dmamap;
1000 1.1 fvdl SLIST_INSERT_HEAD(&sc->txdma_list, dma, link);
1001 1.1 fvdl }
1002 1.1 fvdl
1003 1.1 fvdl sc->bge_flags |= BGE_TXRING_VALID;
1004 1.1 fvdl
1005 1.1 fvdl return(0);
1006 1.1 fvdl }
1007 1.1 fvdl
1008 1.1 fvdl void
1009 1.1 fvdl bge_setmulti(sc)
1010 1.1 fvdl struct bge_softc *sc;
1011 1.1 fvdl {
1012 1.1 fvdl struct ethercom *ac = &sc->ethercom;
1013 1.1 fvdl struct ifnet *ifp = &ac->ec_if;
1014 1.1 fvdl struct ether_multi *enm;
1015 1.1 fvdl struct ether_multistep step;
1016 1.1 fvdl u_int32_t hashes[4] = { 0, 0, 0, 0 };
1017 1.1 fvdl u_int32_t h;
1018 1.1 fvdl int i;
1019 1.1 fvdl
1020 1.13 thorpej if (ifp->if_flags & IFF_PROMISC)
1021 1.13 thorpej goto allmulti;
1022 1.1 fvdl
1023 1.1 fvdl /* Now program new ones. */
1024 1.1 fvdl ETHER_FIRST_MULTI(step, ac, enm);
1025 1.1 fvdl while (enm != NULL) {
1026 1.13 thorpej if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) {
1027 1.13 thorpej /*
1028 1.13 thorpej * We must listen to a range of multicast addresses.
1029 1.13 thorpej * For now, just accept all multicasts, rather than
1030 1.13 thorpej * trying to set only those filter bits needed to match
1031 1.13 thorpej * the range. (At this time, the only use of address
1032 1.13 thorpej * ranges is for IP multicast routing, for which the
1033 1.13 thorpej * range is big enough to require all bits set.)
1034 1.13 thorpej */
1035 1.13 thorpej goto allmulti;
1036 1.13 thorpej }
1037 1.13 thorpej
1038 1.13 thorpej h = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN);
1039 1.13 thorpej
1040 1.13 thorpej /* Just want the 7 least-significant bits. */
1041 1.13 thorpej h &= 0x7f;
1042 1.13 thorpej
1043 1.1 fvdl hashes[(h & 0x60) >> 5] |= 1 << (h & 0x1F);
1044 1.1 fvdl ETHER_NEXT_MULTI(step, enm);
1045 1.1 fvdl }
1046 1.1 fvdl
1047 1.13 thorpej ifp->if_flags &= ~IFF_ALLMULTI;
1048 1.13 thorpej goto setit;
1049 1.13 thorpej
1050 1.13 thorpej allmulti:
1051 1.13 thorpej ifp->if_flags |= IFF_ALLMULTI;
1052 1.13 thorpej hashes[0] = hashes[1] = hashes[2] = hashes[3] = 0xffffffff;
1053 1.13 thorpej
1054 1.13 thorpej setit:
1055 1.1 fvdl for (i = 0; i < 4; i++)
1056 1.1 fvdl CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]);
1057 1.1 fvdl }
1058 1.1 fvdl
1059 1.24 matt const int bge_swapbits[] = {
1060 1.1 fvdl 0,
1061 1.1 fvdl BGE_MODECTL_BYTESWAP_DATA,
1062 1.1 fvdl BGE_MODECTL_WORDSWAP_DATA,
1063 1.1 fvdl BGE_MODECTL_BYTESWAP_NONFRAME,
1064 1.1 fvdl BGE_MODECTL_WORDSWAP_NONFRAME,
1065 1.1 fvdl
1066 1.1 fvdl BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA,
1067 1.1 fvdl BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_BYTESWAP_NONFRAME,
1068 1.1 fvdl BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_NONFRAME,
1069 1.1 fvdl
1070 1.1 fvdl BGE_MODECTL_WORDSWAP_DATA|BGE_MODECTL_BYTESWAP_NONFRAME,
1071 1.1 fvdl BGE_MODECTL_WORDSWAP_DATA|BGE_MODECTL_WORDSWAP_NONFRAME,
1072 1.1 fvdl
1073 1.1 fvdl BGE_MODECTL_BYTESWAP_NONFRAME|BGE_MODECTL_WORDSWAP_NONFRAME,
1074 1.1 fvdl
1075 1.1 fvdl BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA|
1076 1.1 fvdl BGE_MODECTL_BYTESWAP_NONFRAME,
1077 1.1 fvdl BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA|
1078 1.1 fvdl BGE_MODECTL_WORDSWAP_NONFRAME,
1079 1.1 fvdl BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_BYTESWAP_NONFRAME|
1080 1.1 fvdl BGE_MODECTL_WORDSWAP_NONFRAME,
1081 1.1 fvdl BGE_MODECTL_WORDSWAP_DATA|BGE_MODECTL_BYTESWAP_NONFRAME|
1082 1.1 fvdl BGE_MODECTL_WORDSWAP_NONFRAME,
1083 1.1 fvdl
1084 1.1 fvdl BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA|
1085 1.1 fvdl BGE_MODECTL_BYTESWAP_NONFRAME|BGE_MODECTL_WORDSWAP_NONFRAME,
1086 1.1 fvdl };
1087 1.1 fvdl
1088 1.1 fvdl int bge_swapindex = 0;
1089 1.1 fvdl
1090 1.1 fvdl /*
1091 1.1 fvdl * Do endian, PCI and DMA initialization. Also check the on-board ROM
1092 1.1 fvdl * self-test results.
1093 1.1 fvdl */
1094 1.1 fvdl int
1095 1.1 fvdl bge_chipinit(sc)
1096 1.1 fvdl struct bge_softc *sc;
1097 1.1 fvdl {
1098 1.1 fvdl u_int32_t cachesize;
1099 1.1 fvdl int i;
1100 1.25 jonathan u_int32_t dma_rw_ctl;
1101 1.1 fvdl struct pci_attach_args *pa = &(sc->bge_pa);
1102 1.1 fvdl
1103 1.1 fvdl
1104 1.1 fvdl /* Set endianness before we access any non-PCI registers. */
1105 1.1 fvdl pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_MISC_CTL,
1106 1.1 fvdl BGE_INIT);
1107 1.1 fvdl
1108 1.25 jonathan /* Set power state to D0. */
1109 1.25 jonathan bge_setpowerstate(sc, 0);
1110 1.25 jonathan
1111 1.1 fvdl /*
1112 1.1 fvdl * Check the 'ROM failed' bit on the RX CPU to see if
1113 1.1 fvdl * self-tests passed.
1114 1.1 fvdl */
1115 1.1 fvdl if (CSR_READ_4(sc, BGE_RXCPU_MODE) & BGE_RXCPUMODE_ROMFAIL) {
1116 1.1 fvdl printf("%s: RX CPU self-diagnostics failed!\n",
1117 1.1 fvdl sc->bge_dev.dv_xname);
1118 1.1 fvdl return(ENODEV);
1119 1.1 fvdl }
1120 1.1 fvdl
1121 1.1 fvdl /* Clear the MAC control register */
1122 1.1 fvdl CSR_WRITE_4(sc, BGE_MAC_MODE, 0);
1123 1.1 fvdl
1124 1.1 fvdl /*
1125 1.1 fvdl * Clear the MAC statistics block in the NIC's
1126 1.1 fvdl * internal memory.
1127 1.1 fvdl */
1128 1.1 fvdl for (i = BGE_STATS_BLOCK;
1129 1.1 fvdl i < BGE_STATS_BLOCK_END + 1; i += sizeof(u_int32_t))
1130 1.1 fvdl BGE_MEMWIN_WRITE(pa->pa_pc, pa->pa_tag, i, 0);
1131 1.1 fvdl
1132 1.1 fvdl for (i = BGE_STATUS_BLOCK;
1133 1.1 fvdl i < BGE_STATUS_BLOCK_END + 1; i += sizeof(u_int32_t))
1134 1.1 fvdl BGE_MEMWIN_WRITE(pa->pa_pc, pa->pa_tag, i, 0);
1135 1.1 fvdl
1136 1.1 fvdl /* Set up the PCI DMA control register. */
1137 1.25 jonathan if (pci_conf_read(pa->pa_pc, pa->pa_tag,BGE_PCI_PCISTATE) &
1138 1.25 jonathan BGE_PCISTATE_PCI_BUSMODE) {
1139 1.25 jonathan /* Conventional PCI bus */
1140 1.25 jonathan DPRINTFN(4, ("(%s: PCI 2.2 dma setting)\n", sc->bge_dev.dv_xname));
1141 1.25 jonathan dma_rw_ctl = (BGE_PCI_READ_CMD | BGE_PCI_WRITE_CMD |
1142 1.25 jonathan (0x7 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
1143 1.25 jonathan (0x7 << BGE_PCIDMARWCTL_WR_WAT_SHIFT) |
1144 1.25 jonathan (0x0F));
1145 1.25 jonathan } else {
1146 1.25 jonathan DPRINTFN(4, ("(:%s: PCI-X dma setting)\n", sc->bge_dev.dv_xname));
1147 1.25 jonathan /* PCI-X bus */
1148 1.25 jonathan dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
1149 1.25 jonathan (0x3 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
1150 1.25 jonathan (0x3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT) |
1151 1.25 jonathan (0x0F);
1152 1.25 jonathan /*
1153 1.25 jonathan * 5703 and 5704 need ONEDMA_AT_ONCE as a workaround
1154 1.25 jonathan * for hardware bugs, which means we should also clear
1155 1.25 jonathan * the low-order MINDMA bits. In addition, the 5704
1156 1.25 jonathan * uses a different encoding of read/write watermarks.
1157 1.25 jonathan */
1158 1.25 jonathan if (sc->bge_asicrev == BGE_ASICREV_BCM5704_A0) {
1159 1.25 jonathan dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
1160 1.25 jonathan /* should be 0x1f0000 */
1161 1.25 jonathan (0x7 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
1162 1.25 jonathan (0x3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT);
1163 1.25 jonathan dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE;
1164 1.25 jonathan }
1165 1.25 jonathan else if ((sc->bge_asicrev >> 28) ==
1166 1.25 jonathan (BGE_ASICREV_BCM5703_A0 >> 28)) {
1167 1.25 jonathan dma_rw_ctl &= 0xfffffff0;
1168 1.25 jonathan dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE;
1169 1.25 jonathan }
1170 1.25 jonathan }
1171 1.25 jonathan
1172 1.25 jonathan pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_DMA_RW_CTL, dma_rw_ctl);
1173 1.1 fvdl
1174 1.1 fvdl /*
1175 1.1 fvdl * Set up general mode register.
1176 1.1 fvdl */
1177 1.1 fvdl CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS|
1178 1.1 fvdl BGE_MODECTL_MAC_ATTN_INTR|BGE_MODECTL_HOST_SEND_BDS|
1179 1.1 fvdl BGE_MODECTL_NO_RX_CRC|BGE_MODECTL_TX_NO_PHDR_CSUM|
1180 1.1 fvdl BGE_MODECTL_RX_NO_PHDR_CSUM);
1181 1.1 fvdl
1182 1.1 fvdl /* Get cache line size. */
1183 1.1 fvdl cachesize = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_CACHESZ);
1184 1.1 fvdl
1185 1.1 fvdl /*
1186 1.1 fvdl * Avoid violating PCI spec on certain chip revs.
1187 1.1 fvdl */
1188 1.1 fvdl if (pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_CMD) &
1189 1.1 fvdl PCIM_CMD_MWIEN) {
1190 1.1 fvdl switch(cachesize) {
1191 1.1 fvdl case 1:
1192 1.1 fvdl PCI_SETBIT(pa->pa_pc, pa->pa_tag, BGE_PCI_DMA_RW_CTL,
1193 1.1 fvdl BGE_PCI_WRITE_BNDRY_16BYTES);
1194 1.1 fvdl break;
1195 1.1 fvdl case 2:
1196 1.1 fvdl PCI_SETBIT(pa->pa_pc, pa->pa_tag, BGE_PCI_DMA_RW_CTL,
1197 1.1 fvdl BGE_PCI_WRITE_BNDRY_32BYTES);
1198 1.1 fvdl break;
1199 1.1 fvdl case 4:
1200 1.1 fvdl PCI_SETBIT(pa->pa_pc, pa->pa_tag, BGE_PCI_DMA_RW_CTL,
1201 1.1 fvdl BGE_PCI_WRITE_BNDRY_64BYTES);
1202 1.1 fvdl break;
1203 1.1 fvdl case 8:
1204 1.1 fvdl PCI_SETBIT(pa->pa_pc, pa->pa_tag, BGE_PCI_DMA_RW_CTL,
1205 1.1 fvdl BGE_PCI_WRITE_BNDRY_128BYTES);
1206 1.1 fvdl break;
1207 1.1 fvdl case 16:
1208 1.1 fvdl PCI_SETBIT(pa->pa_pc, pa->pa_tag, BGE_PCI_DMA_RW_CTL,
1209 1.1 fvdl BGE_PCI_WRITE_BNDRY_256BYTES);
1210 1.1 fvdl break;
1211 1.1 fvdl case 32:
1212 1.1 fvdl PCI_SETBIT(pa->pa_pc, pa->pa_tag, BGE_PCI_DMA_RW_CTL,
1213 1.1 fvdl BGE_PCI_WRITE_BNDRY_512BYTES);
1214 1.1 fvdl break;
1215 1.1 fvdl case 64:
1216 1.1 fvdl PCI_SETBIT(pa->pa_pc, pa->pa_tag, BGE_PCI_DMA_RW_CTL,
1217 1.1 fvdl BGE_PCI_WRITE_BNDRY_1024BYTES);
1218 1.1 fvdl break;
1219 1.1 fvdl default:
1220 1.1 fvdl /* Disable PCI memory write and invalidate. */
1221 1.1 fvdl #if 0
1222 1.1 fvdl if (bootverbose)
1223 1.1 fvdl printf("%s: cache line size %d not "
1224 1.1 fvdl "supported; disabling PCI MWI\n",
1225 1.1 fvdl sc->bge_dev.dv_xname, cachesize);
1226 1.1 fvdl #endif
1227 1.1 fvdl PCI_CLRBIT(pa->pa_pc, pa->pa_tag, BGE_PCI_CMD,
1228 1.1 fvdl PCIM_CMD_MWIEN);
1229 1.1 fvdl break;
1230 1.1 fvdl }
1231 1.1 fvdl }
1232 1.1 fvdl
1233 1.25 jonathan /*
1234 1.25 jonathan * Disable memory write invalidate. Apparently it is not supported
1235 1.25 jonathan * properly by these devices.
1236 1.25 jonathan */
1237 1.25 jonathan PCI_CLRBIT(pa->pa_pc, pa->pa_tag, BGE_PCI_CMD, PCIM_CMD_MWIEN);
1238 1.25 jonathan
1239 1.25 jonathan
1240 1.1 fvdl #ifdef __brokenalpha__
1241 1.1 fvdl /*
1242 1.1 fvdl * Must insure that we do not cross an 8K (bytes) boundary
1243 1.1 fvdl * for DMA reads. Our highest limit is 1K bytes. This is a
1244 1.1 fvdl * restriction on some ALPHA platforms with early revision
1245 1.1 fvdl * 21174 PCI chipsets, such as the AlphaPC 164lx
1246 1.1 fvdl */
1247 1.1 fvdl PCI_SETBIT(sc, BGE_PCI_DMA_RW_CTL, BGE_PCI_READ_BNDRY_1024, 4);
1248 1.1 fvdl #endif
1249 1.1 fvdl
1250 1.1 fvdl /* Set the timer prescaler (always 66Mhz) */
1251 1.1 fvdl CSR_WRITE_4(sc, BGE_MISC_CFG, 65 << 1/*BGE_32BITTIME_66MHZ*/);
1252 1.1 fvdl
1253 1.1 fvdl return(0);
1254 1.1 fvdl }
1255 1.1 fvdl
1256 1.1 fvdl int
1257 1.1 fvdl bge_blockinit(sc)
1258 1.1 fvdl struct bge_softc *sc;
1259 1.1 fvdl {
1260 1.1 fvdl struct bge_rcb *rcb;
1261 1.1 fvdl struct bge_rcb_opaque *rcbo;
1262 1.1 fvdl bus_size_t rcb_addr;
1263 1.1 fvdl int i;
1264 1.1 fvdl struct ifnet *ifp = &sc->ethercom.ec_if;
1265 1.1 fvdl bge_hostaddr taddr;
1266 1.1 fvdl
1267 1.1 fvdl /*
1268 1.1 fvdl * Initialize the memory window pointer register so that
1269 1.1 fvdl * we can access the first 32K of internal NIC RAM. This will
1270 1.1 fvdl * allow us to set up the TX send ring RCBs and the RX return
1271 1.1 fvdl * ring RCBs, plus other things which live in NIC memory.
1272 1.1 fvdl */
1273 1.1 fvdl
1274 1.1 fvdl pci_conf_write(sc->bge_pa.pa_pc, sc->bge_pa.pa_tag,
1275 1.1 fvdl BGE_PCI_MEMWIN_BASEADDR, 0);
1276 1.1 fvdl
1277 1.1 fvdl /* Configure mbuf memory pool */
1278 1.1 fvdl if (sc->bge_extram) {
1279 1.1 fvdl CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, BGE_EXT_SSRAM);
1280 1.1 fvdl CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000);
1281 1.1 fvdl } else {
1282 1.1 fvdl CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, BGE_BUFFPOOL_1);
1283 1.1 fvdl CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000);
1284 1.1 fvdl }
1285 1.1 fvdl
1286 1.1 fvdl /* Configure DMA resource pool */
1287 1.1 fvdl CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_BASEADDR, BGE_DMA_DESCRIPTORS);
1288 1.1 fvdl CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LEN, 0x2000);
1289 1.1 fvdl
1290 1.1 fvdl /* Configure mbuf pool watermarks */
1291 1.25 jonathan #ifdef ORIG_WPAUL_VALUES
1292 1.1 fvdl CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 24);
1293 1.1 fvdl CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 24);
1294 1.1 fvdl CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 48);
1295 1.25 jonathan #else
1296 1.25 jonathan /* new broadcom docs strongly recommend these: */
1297 1.25 jonathan CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x50);
1298 1.25 jonathan CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x20);
1299 1.25 jonathan CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60);
1300 1.25 jonathan #endif
1301 1.1 fvdl
1302 1.1 fvdl /* Configure DMA resource watermarks */
1303 1.1 fvdl CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5);
1304 1.1 fvdl CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10);
1305 1.1 fvdl
1306 1.1 fvdl /* Enable buffer manager */
1307 1.1 fvdl CSR_WRITE_4(sc, BGE_BMAN_MODE,
1308 1.1 fvdl BGE_BMANMODE_ENABLE|BGE_BMANMODE_LOMBUF_ATTN);
1309 1.1 fvdl
1310 1.1 fvdl /* Poll for buffer manager start indication */
1311 1.1 fvdl for (i = 0; i < BGE_TIMEOUT; i++) {
1312 1.1 fvdl if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE)
1313 1.1 fvdl break;
1314 1.1 fvdl DELAY(10);
1315 1.1 fvdl }
1316 1.1 fvdl
1317 1.1 fvdl if (i == BGE_TIMEOUT) {
1318 1.1 fvdl printf("%s: buffer manager failed to start\n",
1319 1.1 fvdl sc->bge_dev.dv_xname);
1320 1.1 fvdl return(ENXIO);
1321 1.1 fvdl }
1322 1.1 fvdl
1323 1.1 fvdl /* Enable flow-through queues */
1324 1.1 fvdl CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF);
1325 1.1 fvdl CSR_WRITE_4(sc, BGE_FTQ_RESET, 0);
1326 1.1 fvdl
1327 1.1 fvdl /* Wait until queue initialization is complete */
1328 1.1 fvdl for (i = 0; i < BGE_TIMEOUT; i++) {
1329 1.1 fvdl if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0)
1330 1.1 fvdl break;
1331 1.1 fvdl DELAY(10);
1332 1.1 fvdl }
1333 1.1 fvdl
1334 1.1 fvdl if (i == BGE_TIMEOUT) {
1335 1.1 fvdl printf("%s: flow-through queue init failed\n",
1336 1.1 fvdl sc->bge_dev.dv_xname);
1337 1.1 fvdl return(ENXIO);
1338 1.1 fvdl }
1339 1.1 fvdl
1340 1.1 fvdl /* Initialize the standard RX ring control block */
1341 1.1 fvdl rcb = &sc->bge_rdata->bge_info.bge_std_rx_rcb;
1342 1.1 fvdl bge_set_hostaddr(&rcb->bge_hostaddr,
1343 1.1 fvdl BGE_RING_DMA_ADDR(sc, bge_rx_std_ring));
1344 1.1 fvdl rcb->bge_max_len = BGE_MAX_FRAMELEN;
1345 1.1 fvdl if (sc->bge_extram)
1346 1.1 fvdl rcb->bge_nicaddr = BGE_EXT_STD_RX_RINGS;
1347 1.1 fvdl else
1348 1.1 fvdl rcb->bge_nicaddr = BGE_STD_RX_RINGS;
1349 1.1 fvdl rcb->bge_flags = 0;
1350 1.1 fvdl rcbo = (struct bge_rcb_opaque *)rcb;
1351 1.1 fvdl CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcbo->bge_reg0);
1352 1.1 fvdl CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcbo->bge_reg1);
1353 1.1 fvdl CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcbo->bge_reg2);
1354 1.1 fvdl CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcbo->bge_reg3);
1355 1.1 fvdl
1356 1.1 fvdl /*
1357 1.1 fvdl * Initialize the jumbo RX ring control block
1358 1.1 fvdl * We set the 'ring disabled' bit in the flags
1359 1.1 fvdl * field until we're actually ready to start
1360 1.1 fvdl * using this ring (i.e. once we set the MTU
1361 1.1 fvdl * high enough to require it).
1362 1.1 fvdl */
1363 1.1 fvdl rcb = &sc->bge_rdata->bge_info.bge_jumbo_rx_rcb;
1364 1.1 fvdl bge_set_hostaddr(&rcb->bge_hostaddr,
1365 1.1 fvdl BGE_RING_DMA_ADDR(sc, bge_rx_jumbo_ring));
1366 1.1 fvdl rcb->bge_max_len = BGE_MAX_FRAMELEN;
1367 1.1 fvdl if (sc->bge_extram)
1368 1.1 fvdl rcb->bge_nicaddr = BGE_EXT_JUMBO_RX_RINGS;
1369 1.1 fvdl else
1370 1.1 fvdl rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS;
1371 1.1 fvdl rcb->bge_flags = BGE_RCB_FLAG_RING_DISABLED;
1372 1.1 fvdl
1373 1.1 fvdl rcbo = (struct bge_rcb_opaque *)rcb;
1374 1.1 fvdl CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI, rcbo->bge_reg0);
1375 1.1 fvdl CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO, rcbo->bge_reg1);
1376 1.1 fvdl CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcbo->bge_reg2);
1377 1.1 fvdl CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcbo->bge_reg3);
1378 1.1 fvdl
1379 1.1 fvdl /* Set up dummy disabled mini ring RCB */
1380 1.1 fvdl rcb = &sc->bge_rdata->bge_info.bge_mini_rx_rcb;
1381 1.1 fvdl rcb->bge_flags = BGE_RCB_FLAG_RING_DISABLED;
1382 1.1 fvdl rcbo = (struct bge_rcb_opaque *)rcb;
1383 1.1 fvdl CSR_WRITE_4(sc, BGE_RX_MINI_RCB_MAXLEN_FLAGS, rcbo->bge_reg2);
1384 1.1 fvdl
1385 1.1 fvdl bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map,
1386 1.1 fvdl offsetof(struct bge_ring_data, bge_info), sizeof (struct bge_gib),
1387 1.1 fvdl BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
1388 1.1 fvdl
1389 1.1 fvdl /*
1390 1.1 fvdl * Set the BD ring replentish thresholds. The recommended
1391 1.1 fvdl * values are 1/8th the number of descriptors allocated to
1392 1.1 fvdl * each ring.
1393 1.1 fvdl */
1394 1.1 fvdl CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, BGE_STD_RX_RING_CNT/8);
1395 1.1 fvdl CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH, BGE_JUMBO_RX_RING_CNT/8);
1396 1.1 fvdl
1397 1.1 fvdl /*
1398 1.1 fvdl * Disable all unused send rings by setting the 'ring disabled'
1399 1.1 fvdl * bit in the flags field of all the TX send ring control blocks.
1400 1.1 fvdl * These are located in NIC memory.
1401 1.1 fvdl */
1402 1.1 fvdl rcb_addr = BGE_MEMWIN_START + BGE_SEND_RING_RCB;
1403 1.1 fvdl for (i = 0; i < BGE_TX_RINGS_EXTSSRAM_MAX; i++) {
1404 1.1 fvdl RCB_WRITE_2(sc, rcb_addr, bge_flags,
1405 1.1 fvdl BGE_RCB_FLAG_RING_DISABLED);
1406 1.1 fvdl RCB_WRITE_2(sc, rcb_addr, bge_max_len, 0);
1407 1.1 fvdl RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 0);
1408 1.1 fvdl rcb_addr += sizeof(struct bge_rcb);
1409 1.1 fvdl }
1410 1.1 fvdl
1411 1.1 fvdl /* Configure TX RCB 0 (we use only the first ring) */
1412 1.1 fvdl rcb_addr = BGE_MEMWIN_START + BGE_SEND_RING_RCB;
1413 1.1 fvdl bge_set_hostaddr(&taddr, BGE_RING_DMA_ADDR(sc, bge_tx_ring));
1414 1.1 fvdl RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi);
1415 1.1 fvdl RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo);
1416 1.1 fvdl RCB_WRITE_4(sc, rcb_addr, bge_nicaddr,
1417 1.1 fvdl BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT));
1418 1.1 fvdl RCB_WRITE_2(sc, rcb_addr, bge_max_len, BGE_TX_RING_CNT);
1419 1.1 fvdl RCB_WRITE_2(sc, rcb_addr, bge_flags, 0);
1420 1.1 fvdl
1421 1.1 fvdl /* Disable all unused RX return rings */
1422 1.1 fvdl rcb_addr = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB;
1423 1.1 fvdl for (i = 0; i < BGE_RX_RINGS_MAX; i++) {
1424 1.1 fvdl RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_hi, 0);
1425 1.1 fvdl RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_lo, 0);
1426 1.1 fvdl RCB_WRITE_2(sc, rcb_addr, bge_flags,
1427 1.1 fvdl BGE_RCB_FLAG_RING_DISABLED);
1428 1.1 fvdl RCB_WRITE_2(sc, rcb_addr, bge_max_len, BGE_RETURN_RING_CNT);
1429 1.1 fvdl RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 0);
1430 1.1 fvdl CSR_WRITE_4(sc, BGE_MBX_RX_CONS0_LO +
1431 1.1 fvdl (i * (sizeof(u_int64_t))), 0);
1432 1.1 fvdl rcb_addr += sizeof(struct bge_rcb);
1433 1.1 fvdl }
1434 1.1 fvdl
1435 1.1 fvdl /* Initialize RX ring indexes */
1436 1.1 fvdl CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, 0);
1437 1.1 fvdl CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0);
1438 1.1 fvdl CSR_WRITE_4(sc, BGE_MBX_RX_MINI_PROD_LO, 0);
1439 1.1 fvdl
1440 1.1 fvdl /*
1441 1.1 fvdl * Set up RX return ring 0
1442 1.1 fvdl * Note that the NIC address for RX return rings is 0x00000000.
1443 1.1 fvdl * The return rings live entirely within the host, so the
1444 1.1 fvdl * nicaddr field in the RCB isn't used.
1445 1.1 fvdl */
1446 1.1 fvdl rcb_addr = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB;
1447 1.1 fvdl bge_set_hostaddr(&taddr, BGE_RING_DMA_ADDR(sc, bge_rx_return_ring));
1448 1.1 fvdl RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi);
1449 1.1 fvdl RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo);
1450 1.1 fvdl RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 0x00000000);
1451 1.1 fvdl RCB_WRITE_2(sc, rcb_addr, bge_max_len, BGE_RETURN_RING_CNT);
1452 1.1 fvdl RCB_WRITE_2(sc, rcb_addr, bge_flags, 0);
1453 1.1 fvdl
1454 1.1 fvdl /* Set random backoff seed for TX */
1455 1.1 fvdl CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF,
1456 1.1 fvdl LLADDR(ifp->if_sadl)[0] + LLADDR(ifp->if_sadl)[1] +
1457 1.1 fvdl LLADDR(ifp->if_sadl)[2] + LLADDR(ifp->if_sadl)[3] +
1458 1.1 fvdl LLADDR(ifp->if_sadl)[4] + LLADDR(ifp->if_sadl)[5] +
1459 1.1 fvdl BGE_TX_BACKOFF_SEED_MASK);
1460 1.1 fvdl
1461 1.1 fvdl /* Set inter-packet gap */
1462 1.1 fvdl CSR_WRITE_4(sc, BGE_TX_LENGTHS, 0x2620);
1463 1.1 fvdl
1464 1.1 fvdl /*
1465 1.1 fvdl * Specify which ring to use for packets that don't match
1466 1.1 fvdl * any RX rules.
1467 1.1 fvdl */
1468 1.1 fvdl CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08);
1469 1.1 fvdl
1470 1.1 fvdl /*
1471 1.1 fvdl * Configure number of RX lists. One interrupt distribution
1472 1.1 fvdl * list, sixteen active lists, one bad frames class.
1473 1.1 fvdl */
1474 1.1 fvdl CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181);
1475 1.1 fvdl
1476 1.1 fvdl /* Inialize RX list placement stats mask. */
1477 1.1 fvdl CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF);
1478 1.1 fvdl CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1);
1479 1.1 fvdl
1480 1.1 fvdl /* Disable host coalescing until we get it set up */
1481 1.1 fvdl CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000);
1482 1.1 fvdl
1483 1.1 fvdl /* Poll to make sure it's shut down. */
1484 1.1 fvdl for (i = 0; i < BGE_TIMEOUT; i++) {
1485 1.1 fvdl if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE))
1486 1.1 fvdl break;
1487 1.1 fvdl DELAY(10);
1488 1.1 fvdl }
1489 1.1 fvdl
1490 1.1 fvdl if (i == BGE_TIMEOUT) {
1491 1.1 fvdl printf("%s: host coalescing engine failed to idle\n",
1492 1.1 fvdl sc->bge_dev.dv_xname);
1493 1.1 fvdl return(ENXIO);
1494 1.1 fvdl }
1495 1.1 fvdl
1496 1.1 fvdl /* Set up host coalescing defaults */
1497 1.1 fvdl CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bge_rx_coal_ticks);
1498 1.1 fvdl CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bge_tx_coal_ticks);
1499 1.1 fvdl CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bge_rx_max_coal_bds);
1500 1.1 fvdl CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bge_tx_max_coal_bds);
1501 1.1 fvdl CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT, 0);
1502 1.1 fvdl CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT, 0);
1503 1.1 fvdl CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 0);
1504 1.1 fvdl CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 0);
1505 1.1 fvdl CSR_WRITE_4(sc, BGE_HCC_STATS_TICKS, sc->bge_stat_ticks);
1506 1.1 fvdl
1507 1.1 fvdl /* Set up address of statistics block */
1508 1.1 fvdl bge_set_hostaddr(&taddr, BGE_RING_DMA_ADDR(sc, bge_info.bge_stats));
1509 1.1 fvdl CSR_WRITE_4(sc, BGE_HCC_STATS_BASEADDR, BGE_STATS_BLOCK);
1510 1.1 fvdl CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_HI, taddr.bge_addr_hi);
1511 1.1 fvdl CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_LO, taddr.bge_addr_lo);
1512 1.1 fvdl
1513 1.1 fvdl /* Set up address of status block */
1514 1.1 fvdl bge_set_hostaddr(&taddr, BGE_RING_DMA_ADDR(sc, bge_status_block));
1515 1.1 fvdl CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_BASEADDR, BGE_STATUS_BLOCK);
1516 1.1 fvdl CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI, taddr.bge_addr_hi);
1517 1.1 fvdl CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO, taddr.bge_addr_lo);
1518 1.1 fvdl sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx = 0;
1519 1.1 fvdl sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx = 0;
1520 1.1 fvdl
1521 1.1 fvdl /* Turn on host coalescing state machine */
1522 1.1 fvdl CSR_WRITE_4(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE);
1523 1.1 fvdl
1524 1.1 fvdl /* Turn on RX BD completion state machine and enable attentions */
1525 1.1 fvdl CSR_WRITE_4(sc, BGE_RBDC_MODE,
1526 1.1 fvdl BGE_RBDCMODE_ENABLE|BGE_RBDCMODE_ATTN);
1527 1.1 fvdl
1528 1.1 fvdl /* Turn on RX list placement state machine */
1529 1.1 fvdl CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);
1530 1.1 fvdl
1531 1.1 fvdl /* Turn on RX list selector state machine. */
1532 1.1 fvdl CSR_WRITE_4(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE);
1533 1.1 fvdl
1534 1.1 fvdl /* Turn on DMA, clear stats */
1535 1.1 fvdl CSR_WRITE_4(sc, BGE_MAC_MODE, BGE_MACMODE_TXDMA_ENB|
1536 1.1 fvdl BGE_MACMODE_RXDMA_ENB|BGE_MACMODE_RX_STATS_CLEAR|
1537 1.1 fvdl BGE_MACMODE_TX_STATS_CLEAR|BGE_MACMODE_RX_STATS_ENB|
1538 1.1 fvdl BGE_MACMODE_TX_STATS_ENB|BGE_MACMODE_FRMHDR_DMA_ENB|
1539 1.1 fvdl (sc->bge_tbi ? BGE_PORTMODE_TBI : BGE_PORTMODE_MII));
1540 1.1 fvdl
1541 1.1 fvdl /* Set misc. local control, enable interrupts on attentions */
1542 1.25 jonathan sc->bge_local_ctrl_reg = BGE_MLC_INTR_ONATTN | BGE_MLC_AUTO_EEPROM;
1543 1.1 fvdl
1544 1.1 fvdl #ifdef notdef
1545 1.1 fvdl /* Assert GPIO pins for PHY reset */
1546 1.1 fvdl BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUT0|
1547 1.1 fvdl BGE_MLC_MISCIO_OUT1|BGE_MLC_MISCIO_OUT2);
1548 1.1 fvdl BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUTEN0|
1549 1.1 fvdl BGE_MLC_MISCIO_OUTEN1|BGE_MLC_MISCIO_OUTEN2);
1550 1.1 fvdl #endif
1551 1.1 fvdl
1552 1.25 jonathan #if defined(not_quite_yet)
1553 1.25 jonathan /* Linux driver enables enable gpio pin #1 on 5700s */
1554 1.25 jonathan if (sc->bge_asicrev == BGE_ASICREV_BCM5700) {
1555 1.25 jonathan sc->bge_local_ctrl_reg |=
1556 1.25 jonathan (BGE_MLC_MISCIO_OUT1|BGE_MLC_MISCIO_OUTEN1);
1557 1.25 jonathan }
1558 1.25 jonathan #endif
1559 1.25 jonathan CSR_WRITE_4(sc, BGE_MISC_LOCAL_CTL, sc->bge_local_ctrl_reg);
1560 1.25 jonathan
1561 1.1 fvdl /* Turn on DMA completion state machine */
1562 1.1 fvdl CSR_WRITE_4(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE);
1563 1.1 fvdl
1564 1.1 fvdl /* Turn on write DMA state machine */
1565 1.1 fvdl CSR_WRITE_4(sc, BGE_WDMA_MODE,
1566 1.1 fvdl BGE_WDMAMODE_ENABLE|BGE_WDMAMODE_ALL_ATTNS);
1567 1.1 fvdl
1568 1.1 fvdl /* Turn on read DMA state machine */
1569 1.1 fvdl CSR_WRITE_4(sc, BGE_RDMA_MODE,
1570 1.1 fvdl BGE_RDMAMODE_ENABLE|BGE_RDMAMODE_ALL_ATTNS);
1571 1.1 fvdl
1572 1.1 fvdl /* Turn on RX data completion state machine */
1573 1.1 fvdl CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);
1574 1.1 fvdl
1575 1.1 fvdl /* Turn on RX BD initiator state machine */
1576 1.1 fvdl CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE);
1577 1.1 fvdl
1578 1.1 fvdl /* Turn on RX data and RX BD initiator state machine */
1579 1.1 fvdl CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE);
1580 1.1 fvdl
1581 1.1 fvdl /* Turn on Mbuf cluster free state machine */
1582 1.1 fvdl CSR_WRITE_4(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE);
1583 1.1 fvdl
1584 1.1 fvdl /* Turn on send BD completion state machine */
1585 1.1 fvdl CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);
1586 1.1 fvdl
1587 1.1 fvdl /* Turn on send data completion state machine */
1588 1.1 fvdl CSR_WRITE_4(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE);
1589 1.1 fvdl
1590 1.1 fvdl /* Turn on send data initiator state machine */
1591 1.1 fvdl CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE);
1592 1.1 fvdl
1593 1.1 fvdl /* Turn on send BD initiator state machine */
1594 1.1 fvdl CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE);
1595 1.1 fvdl
1596 1.1 fvdl /* Turn on send BD selector state machine */
1597 1.1 fvdl CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE);
1598 1.1 fvdl
1599 1.1 fvdl CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF);
1600 1.1 fvdl CSR_WRITE_4(sc, BGE_SDI_STATS_CTL,
1601 1.1 fvdl BGE_SDISTATSCTL_ENABLE|BGE_SDISTATSCTL_FASTER);
1602 1.1 fvdl
1603 1.1 fvdl /* init LED register */
1604 1.1 fvdl CSR_WRITE_4(sc, BGE_MAC_LED_CTL, 0x00000000);
1605 1.1 fvdl
1606 1.1 fvdl /* ack/clear link change events */
1607 1.1 fvdl CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED|
1608 1.1 fvdl BGE_MACSTAT_CFG_CHANGED);
1609 1.1 fvdl CSR_WRITE_4(sc, BGE_MI_STS, 0);
1610 1.1 fvdl
1611 1.1 fvdl /* Enable PHY auto polling (for MII/GMII only) */
1612 1.1 fvdl if (sc->bge_tbi) {
1613 1.1 fvdl CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK);
1614 1.1 fvdl } else {
1615 1.1 fvdl BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL|10<<16);
1616 1.17 thorpej if (sc->bge_quirks & BGE_QUIRK_LINK_STATE_BROKEN)
1617 1.1 fvdl CSR_WRITE_4(sc, BGE_MAC_EVT_ENB,
1618 1.1 fvdl BGE_EVTENB_MI_INTERRUPT);
1619 1.1 fvdl }
1620 1.1 fvdl
1621 1.1 fvdl /* Enable link state change attentions. */
1622 1.1 fvdl BGE_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED);
1623 1.1 fvdl
1624 1.1 fvdl return(0);
1625 1.1 fvdl }
1626 1.1 fvdl
1627 1.16 thorpej static const struct bge_revision {
1628 1.16 thorpej uint32_t br_asicrev;
1629 1.16 thorpej uint32_t br_quirks;
1630 1.16 thorpej const char *br_name;
1631 1.16 thorpej } bge_revisions[] = {
1632 1.16 thorpej { BGE_ASICREV_BCM5700_A0,
1633 1.17 thorpej BGE_QUIRK_LINK_STATE_BROKEN,
1634 1.16 thorpej "BCM5700 A0" },
1635 1.16 thorpej
1636 1.16 thorpej { BGE_ASICREV_BCM5700_A1,
1637 1.17 thorpej BGE_QUIRK_LINK_STATE_BROKEN,
1638 1.16 thorpej "BCM5700 A1" },
1639 1.16 thorpej
1640 1.16 thorpej { BGE_ASICREV_BCM5700_B0,
1641 1.26 jonathan BGE_QUIRK_LINK_STATE_BROKEN|BGE_QUIRK_CSUM_BROKEN|BGE_QUIRK_5700_COMMON,
1642 1.16 thorpej "BCM5700 B0" },
1643 1.16 thorpej
1644 1.16 thorpej { BGE_ASICREV_BCM5700_B1,
1645 1.26 jonathan BGE_QUIRK_LINK_STATE_BROKEN|BGE_QUIRK_5700_COMMON,
1646 1.16 thorpej "BCM5700 B1" },
1647 1.16 thorpej
1648 1.16 thorpej { BGE_ASICREV_BCM5700_B2,
1649 1.26 jonathan BGE_QUIRK_LINK_STATE_BROKEN|BGE_QUIRK_5700_COMMON,
1650 1.16 thorpej "BCM5700 B2" },
1651 1.16 thorpej
1652 1.17 thorpej /* This is treated like a BCM5700 Bx */
1653 1.16 thorpej { BGE_ASICREV_BCM5700_ALTIMA,
1654 1.26 jonathan BGE_QUIRK_LINK_STATE_BROKEN|BGE_QUIRK_5700_COMMON,
1655 1.16 thorpej "BCM5700 Altima" },
1656 1.16 thorpej
1657 1.16 thorpej { BGE_ASICREV_BCM5700_C0,
1658 1.16 thorpej 0,
1659 1.16 thorpej "BCM5700 C0" },
1660 1.16 thorpej
1661 1.16 thorpej { BGE_ASICREV_BCM5701_A0,
1662 1.16 thorpej 0,
1663 1.16 thorpej "BCM5701 A0" },
1664 1.16 thorpej
1665 1.16 thorpej { BGE_ASICREV_BCM5701_B0,
1666 1.16 thorpej 0,
1667 1.16 thorpej "BCM5701 B0" },
1668 1.16 thorpej
1669 1.16 thorpej { BGE_ASICREV_BCM5701_B2,
1670 1.16 thorpej 0,
1671 1.16 thorpej "BCM5701 B2" },
1672 1.16 thorpej
1673 1.16 thorpej { BGE_ASICREV_BCM5701_B5,
1674 1.24 matt BGE_QUIRK_ONLY_PHY_1,
1675 1.16 thorpej "BCM5701 B5" },
1676 1.16 thorpej
1677 1.16 thorpej { BGE_ASICREV_BCM5703_A0,
1678 1.16 thorpej 0,
1679 1.16 thorpej "BCM5703 A0" },
1680 1.16 thorpej
1681 1.16 thorpej { BGE_ASICREV_BCM5703_A1,
1682 1.16 thorpej 0,
1683 1.16 thorpej "BCM5703 A1" },
1684 1.16 thorpej
1685 1.16 thorpej { BGE_ASICREV_BCM5703_A2,
1686 1.24 matt BGE_QUIRK_ONLY_PHY_1,
1687 1.16 thorpej "BCM5703 A2" },
1688 1.16 thorpej
1689 1.25 jonathan { BGE_ASICREV_BCM5704_A0,
1690 1.25 jonathan BGE_QUIRK_ONLY_PHY_1,
1691 1.25 jonathan "BCM5704 A0" },
1692 1.25 jonathan
1693 1.16 thorpej { 0, 0, NULL }
1694 1.16 thorpej };
1695 1.16 thorpej
1696 1.16 thorpej static const struct bge_revision *
1697 1.16 thorpej bge_lookup_rev(uint32_t asicrev)
1698 1.16 thorpej {
1699 1.16 thorpej const struct bge_revision *br;
1700 1.16 thorpej
1701 1.16 thorpej for (br = bge_revisions; br->br_name != NULL; br++) {
1702 1.16 thorpej if (br->br_asicrev == asicrev)
1703 1.16 thorpej return (br);
1704 1.16 thorpej }
1705 1.16 thorpej
1706 1.16 thorpej return (NULL);
1707 1.16 thorpej }
1708 1.16 thorpej
1709 1.7 thorpej static const struct bge_product {
1710 1.7 thorpej pci_vendor_id_t bp_vendor;
1711 1.7 thorpej pci_product_id_t bp_product;
1712 1.7 thorpej const char *bp_name;
1713 1.7 thorpej } bge_products[] = {
1714 1.7 thorpej /*
1715 1.7 thorpej * The BCM5700 documentation seems to indicate that the hardware
1716 1.7 thorpej * still has the Alteon vendor ID burned into it, though it
1717 1.7 thorpej * should always be overridden by the value in the EEPROM. We'll
1718 1.7 thorpej * check for it anyway.
1719 1.7 thorpej */
1720 1.7 thorpej { PCI_VENDOR_ALTEON,
1721 1.7 thorpej PCI_PRODUCT_ALTEON_BCM5700,
1722 1.7 thorpej "Broadcom BCM5700 Gigabit Ethernet" },
1723 1.7 thorpej { PCI_VENDOR_ALTEON,
1724 1.7 thorpej PCI_PRODUCT_ALTEON_BCM5701,
1725 1.7 thorpej "Broadcom BCM5701 Gigabit Ethernet" },
1726 1.7 thorpej
1727 1.7 thorpej { PCI_VENDOR_ALTIMA,
1728 1.7 thorpej PCI_PRODUCT_ALTIMA_AC1000,
1729 1.7 thorpej "Altima AC1000 Gigabit Ethernet" },
1730 1.14 enami { PCI_VENDOR_ALTIMA,
1731 1.14 enami PCI_PRODUCT_ALTIMA_AC1001,
1732 1.14 enami "Altima AC1001 Gigabit Ethernet" },
1733 1.7 thorpej { PCI_VENDOR_ALTIMA,
1734 1.7 thorpej PCI_PRODUCT_ALTIMA_AC9100,
1735 1.7 thorpej "Altima AC9100 Gigabit Ethernet" },
1736 1.7 thorpej
1737 1.7 thorpej { PCI_VENDOR_BROADCOM,
1738 1.7 thorpej PCI_PRODUCT_BROADCOM_BCM5700,
1739 1.7 thorpej "Broadcom BCM5700 Gigabit Ethernet" },
1740 1.7 thorpej { PCI_VENDOR_BROADCOM,
1741 1.7 thorpej PCI_PRODUCT_BROADCOM_BCM5701,
1742 1.24 matt "Broadcom BCM5701 Gigabit Ethernet" },
1743 1.24 matt { PCI_VENDOR_BROADCOM,
1744 1.24 matt PCI_PRODUCT_BROADCOM_BCM5702,
1745 1.24 matt "Broadcom BCM5702 Gigabit Ethernet" },
1746 1.24 matt { PCI_VENDOR_BROADCOM,
1747 1.24 matt PCI_PRODUCT_BROADCOM_BCM5702X,
1748 1.24 matt "Broadcom BCM5702X Gigabit Ethernet" },
1749 1.24 matt { PCI_VENDOR_BROADCOM,
1750 1.24 matt PCI_PRODUCT_BROADCOM_BCM5703,
1751 1.24 matt "Broadcom BCM5703 Gigabit Ethernet" },
1752 1.24 matt { PCI_VENDOR_BROADCOM,
1753 1.24 matt PCI_PRODUCT_BROADCOM_BCM5703X,
1754 1.24 matt "Broadcom BCM5703X Gigabit Ethernet" },
1755 1.25 jonathan { PCI_VENDOR_BROADCOM,
1756 1.25 jonathan PCI_PRODUCT_BROADCOM_BCM5704C,
1757 1.25 jonathan "Broadcom BCM5704C Dual Gigabit Ethernet" },
1758 1.25 jonathan { PCI_VENDOR_BROADCOM,
1759 1.25 jonathan PCI_PRODUCT_BROADCOM_BCM5704S,
1760 1.25 jonathan "Broadcom BCM5704S Dual Gigabit Ethernet" },
1761 1.25 jonathan
1762 1.7 thorpej
1763 1.7 thorpej { PCI_VENDOR_SCHNEIDERKOCH,
1764 1.7 thorpej PCI_PRODUCT_SCHNEIDERKOCH_SK_9DX1,
1765 1.8 thorpej "SysKonnect SK-9Dx1 Gigabit Ethernet" },
1766 1.7 thorpej
1767 1.7 thorpej { PCI_VENDOR_3COM,
1768 1.7 thorpej PCI_PRODUCT_3COM_3C996,
1769 1.7 thorpej "3Com 3c996 Gigabit Ethernet" },
1770 1.7 thorpej
1771 1.7 thorpej { 0,
1772 1.7 thorpej 0,
1773 1.7 thorpej NULL },
1774 1.7 thorpej };
1775 1.7 thorpej
1776 1.7 thorpej static const struct bge_product *
1777 1.7 thorpej bge_lookup(const struct pci_attach_args *pa)
1778 1.7 thorpej {
1779 1.7 thorpej const struct bge_product *bp;
1780 1.7 thorpej
1781 1.7 thorpej for (bp = bge_products; bp->bp_name != NULL; bp++) {
1782 1.7 thorpej if (PCI_VENDOR(pa->pa_id) == bp->bp_vendor &&
1783 1.7 thorpej PCI_PRODUCT(pa->pa_id) == bp->bp_product)
1784 1.7 thorpej return (bp);
1785 1.7 thorpej }
1786 1.7 thorpej
1787 1.7 thorpej return (NULL);
1788 1.7 thorpej }
1789 1.7 thorpej
1790 1.25 jonathan int
1791 1.25 jonathan bge_setpowerstate(sc, powerlevel)
1792 1.25 jonathan struct bge_softc *sc;
1793 1.25 jonathan int powerlevel;
1794 1.25 jonathan {
1795 1.25 jonathan #ifdef NOTYET
1796 1.25 jonathan u_int32_t pm_ctl = 0;
1797 1.25 jonathan
1798 1.25 jonathan /* XXX FIXME: make sure indirect accesses enabled? */
1799 1.25 jonathan pm_ctl = pci_conf_read(sc->bge_dev, BGE_PCI_MISC_CTL, 4);
1800 1.25 jonathan pm_ctl |= BGE_PCIMISCCTL_INDIRECT_ACCESS;
1801 1.25 jonathan pci_write_config(sc->bge_dev, BGE_PCI_MISC_CTL, pm_ctl, 4);
1802 1.25 jonathan
1803 1.25 jonathan /* clear the PME_assert bit and power state bits, enable PME */
1804 1.25 jonathan pm_ctl = pci_conf_read(sc->bge_dev, BGE_PCI_PWRMGMT_CMD, 2);
1805 1.25 jonathan pm_ctl &= ~PCIM_PSTAT_DMASK;
1806 1.25 jonathan pm_ctl |= (1 << 8);
1807 1.25 jonathan
1808 1.25 jonathan if (powerlevel == 0) {
1809 1.25 jonathan pm_ctl |= PCIM_PSTAT_D0;
1810 1.25 jonathan pci_write_config(sc->bge_dev, BGE_PCI_PWRMGMT_CMD,
1811 1.25 jonathan pm_ctl, 2);
1812 1.25 jonathan DELAY(10000);
1813 1.25 jonathan CSR_WRITE_4(sc, BGE_MISC_LOCAL_CTL,
1814 1.25 jonathan sc->bge_local_ctrl_reg);
1815 1.25 jonathan DELAY(10000);
1816 1.25 jonathan
1817 1.25 jonathan #ifdef NOTYET
1818 1.25 jonathan /* XXX FIXME: write 0x02 to phy aux_Ctrl reg */
1819 1.25 jonathan bge_miibus_writereg(sc->bge_dev, 1, 0x18, 0x02);
1820 1.25 jonathan #endif
1821 1.25 jonathan DELAY(40); DELAY(40); DELAY(40);
1822 1.25 jonathan DELAY(10000); /* above not quite adequate on 5700 */
1823 1.25 jonathan return 0;
1824 1.25 jonathan }
1825 1.25 jonathan
1826 1.25 jonathan
1827 1.25 jonathan /*
1828 1.25 jonathan * Entering ACPI power states D1-D3 is achieved by wiggling
1829 1.25 jonathan * GMII gpio pins. Example code assumes all hardware vendors
1830 1.25 jonathan * followed Broadom's sample pcb layout. Until we verify that
1831 1.25 jonathan * for all supported OEM cards, states D1-D3 are unsupported.
1832 1.25 jonathan */
1833 1.25 jonathan printf("%s: power state %d unimplemented; check GPIO pins\n",
1834 1.25 jonathan sc->bge_dev.dv_xname, powerlevel);
1835 1.25 jonathan #endif
1836 1.25 jonathan return EOPNOTSUPP;
1837 1.25 jonathan }
1838 1.25 jonathan
1839 1.25 jonathan
1840 1.1 fvdl /*
1841 1.1 fvdl * Probe for a Broadcom chip. Check the PCI vendor and device IDs
1842 1.1 fvdl * against our list and return its name if we find a match. Note
1843 1.1 fvdl * that since the Broadcom controller contains VPD support, we
1844 1.1 fvdl * can get the device name string from the controller itself instead
1845 1.1 fvdl * of the compiled-in string. This is a little slow, but it guarantees
1846 1.1 fvdl * we'll always announce the right product name.
1847 1.1 fvdl */
1848 1.1 fvdl int
1849 1.1 fvdl bge_probe(parent, match, aux)
1850 1.1 fvdl struct device *parent;
1851 1.1 fvdl struct cfdata *match;
1852 1.1 fvdl void *aux;
1853 1.1 fvdl {
1854 1.1 fvdl struct pci_attach_args *pa = (struct pci_attach_args *)aux;
1855 1.1 fvdl
1856 1.7 thorpej if (bge_lookup(pa) != NULL)
1857 1.1 fvdl return (1);
1858 1.1 fvdl
1859 1.1 fvdl return (0);
1860 1.1 fvdl }
1861 1.1 fvdl
1862 1.1 fvdl void
1863 1.1 fvdl bge_attach(parent, self, aux)
1864 1.1 fvdl struct device *parent, *self;
1865 1.1 fvdl void *aux;
1866 1.1 fvdl {
1867 1.1 fvdl struct bge_softc *sc = (struct bge_softc *)self;
1868 1.1 fvdl struct pci_attach_args *pa = aux;
1869 1.7 thorpej const struct bge_product *bp;
1870 1.16 thorpej const struct bge_revision *br;
1871 1.1 fvdl pci_chipset_tag_t pc = pa->pa_pc;
1872 1.1 fvdl pci_intr_handle_t ih;
1873 1.1 fvdl const char *intrstr = NULL;
1874 1.1 fvdl bus_dma_segment_t seg;
1875 1.1 fvdl int rseg;
1876 1.1 fvdl u_int32_t hwcfg = 0;
1877 1.24 matt u_int32_t mac_addr = 0;
1878 1.1 fvdl u_int32_t command;
1879 1.1 fvdl struct ifnet *ifp;
1880 1.1 fvdl caddr_t kva;
1881 1.1 fvdl u_char eaddr[ETHER_ADDR_LEN];
1882 1.1 fvdl pcireg_t memtype;
1883 1.1 fvdl bus_addr_t memaddr;
1884 1.1 fvdl bus_size_t memsize;
1885 1.25 jonathan u_int32_t pm_ctl;
1886 1.25 jonathan
1887 1.7 thorpej bp = bge_lookup(pa);
1888 1.7 thorpej KASSERT(bp != NULL);
1889 1.7 thorpej
1890 1.1 fvdl sc->bge_pa = *pa;
1891 1.1 fvdl
1892 1.16 thorpej printf(": %s\n", bp->bp_name);
1893 1.1 fvdl
1894 1.1 fvdl /*
1895 1.1 fvdl * Map control/status registers.
1896 1.1 fvdl */
1897 1.1 fvdl DPRINTFN(5, ("Map control/status regs\n"));
1898 1.1 fvdl command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG);
1899 1.1 fvdl command |= PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_MASTER_ENABLE;
1900 1.1 fvdl pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, command);
1901 1.1 fvdl command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG);
1902 1.1 fvdl
1903 1.1 fvdl if (!(command & PCI_COMMAND_MEM_ENABLE)) {
1904 1.1 fvdl printf("%s: failed to enable memory mapping!\n",
1905 1.1 fvdl sc->bge_dev.dv_xname);
1906 1.1 fvdl return;
1907 1.1 fvdl }
1908 1.1 fvdl
1909 1.1 fvdl DPRINTFN(5, ("pci_mem_find\n"));
1910 1.1 fvdl memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, BGE_PCI_BAR0);
1911 1.1 fvdl switch (memtype) {
1912 1.1 fvdl case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT:
1913 1.1 fvdl case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT:
1914 1.1 fvdl if (pci_mapreg_map(pa, BGE_PCI_BAR0,
1915 1.1 fvdl memtype, 0, &sc->bge_btag, &sc->bge_bhandle,
1916 1.1 fvdl &memaddr, &memsize) == 0)
1917 1.1 fvdl break;
1918 1.1 fvdl default:
1919 1.1 fvdl printf("%s: can't find mem space\n",
1920 1.1 fvdl sc->bge_dev.dv_xname);
1921 1.1 fvdl return;
1922 1.1 fvdl }
1923 1.1 fvdl
1924 1.1 fvdl DPRINTFN(5, ("pci_intr_map\n"));
1925 1.1 fvdl if (pci_intr_map(pa, &ih)) {
1926 1.1 fvdl printf("%s: couldn't map interrupt\n",
1927 1.1 fvdl sc->bge_dev.dv_xname);
1928 1.1 fvdl return;
1929 1.1 fvdl }
1930 1.1 fvdl
1931 1.1 fvdl DPRINTFN(5, ("pci_intr_string\n"));
1932 1.1 fvdl intrstr = pci_intr_string(pc, ih);
1933 1.1 fvdl
1934 1.1 fvdl DPRINTFN(5, ("pci_intr_establish\n"));
1935 1.1 fvdl sc->bge_intrhand = pci_intr_establish(pc, ih, IPL_NET, bge_intr, sc);
1936 1.1 fvdl
1937 1.1 fvdl if (sc->bge_intrhand == NULL) {
1938 1.1 fvdl printf("%s: couldn't establish interrupt",
1939 1.1 fvdl sc->bge_dev.dv_xname);
1940 1.1 fvdl if (intrstr != NULL)
1941 1.1 fvdl printf(" at %s", intrstr);
1942 1.1 fvdl printf("\n");
1943 1.1 fvdl return;
1944 1.1 fvdl }
1945 1.1 fvdl printf("%s: interrupting at %s\n", sc->bge_dev.dv_xname, intrstr);
1946 1.1 fvdl
1947 1.25 jonathan /*
1948 1.25 jonathan * Kludge for 5700 Bx bug: a hardware bug (PCIX byte enable?)
1949 1.25 jonathan * can clobber the chip's PCI config-space power control registers,
1950 1.25 jonathan * leaving the card in D3 powersave state.
1951 1.25 jonathan * We do not have memory-mapped registers in this state,
1952 1.25 jonathan * so force device into D0 state before starting initialization.
1953 1.25 jonathan */
1954 1.25 jonathan pm_ctl = pci_conf_read(pc, pa->pa_tag, BGE_PCI_PWRMGMT_CMD);
1955 1.25 jonathan pm_ctl &= ~(PCI_PWR_D0|PCI_PWR_D1|PCI_PWR_D2|PCI_PWR_D3);
1956 1.25 jonathan pm_ctl |= (1 << 8) | PCI_PWR_D0 ; /* D0 state */
1957 1.25 jonathan pci_conf_write(pc, pa->pa_tag, BGE_PCI_PWRMGMT_CMD, pm_ctl);
1958 1.25 jonathan DELAY(1000); /* 27 usec is allegedly sufficent */
1959 1.25 jonathan
1960 1.1 fvdl /* Try to reset the chip. */
1961 1.1 fvdl DPRINTFN(5, ("bge_reset\n"));
1962 1.1 fvdl bge_reset(sc);
1963 1.1 fvdl
1964 1.1 fvdl if (bge_chipinit(sc)) {
1965 1.25 jonathan printf("%s: chip initialization failed\n",
1966 1.1 fvdl sc->bge_dev.dv_xname);
1967 1.1 fvdl bge_release_resources(sc);
1968 1.1 fvdl return;
1969 1.1 fvdl }
1970 1.1 fvdl
1971 1.1 fvdl /*
1972 1.1 fvdl * Get station address from the EEPROM.
1973 1.1 fvdl */
1974 1.24 matt mac_addr = bge_readmem_ind(sc, 0x0c14);
1975 1.24 matt if ((mac_addr >> 16) == 0x484b) {
1976 1.24 matt eaddr[0] = (u_char)(mac_addr >> 8);
1977 1.24 matt eaddr[1] = (u_char)(mac_addr >> 0);
1978 1.24 matt mac_addr = bge_readmem_ind(sc, 0x0c18);
1979 1.24 matt eaddr[2] = (u_char)(mac_addr >> 24);
1980 1.24 matt eaddr[3] = (u_char)(mac_addr >> 16);
1981 1.24 matt eaddr[4] = (u_char)(mac_addr >> 8);
1982 1.24 matt eaddr[5] = (u_char)(mac_addr >> 0);
1983 1.24 matt } else if (bge_read_eeprom(sc, (caddr_t)eaddr,
1984 1.1 fvdl BGE_EE_MAC_OFFSET + 2, ETHER_ADDR_LEN)) {
1985 1.23 kristerw printf("%s: failed to read station address\n",
1986 1.23 kristerw sc->bge_dev.dv_xname);
1987 1.1 fvdl bge_release_resources(sc);
1988 1.1 fvdl return;
1989 1.1 fvdl }
1990 1.1 fvdl
1991 1.1 fvdl /*
1992 1.16 thorpej * Save ASIC rev. Look up any quirks associated with this
1993 1.16 thorpej * ASIC.
1994 1.1 fvdl */
1995 1.16 thorpej sc->bge_asicrev =
1996 1.16 thorpej pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_MISC_CTL) &
1997 1.16 thorpej BGE_PCIMISCCTL_ASICREV;
1998 1.16 thorpej br = bge_lookup_rev(sc->bge_asicrev);
1999 1.16 thorpej
2000 1.16 thorpej printf("%s: ", sc->bge_dev.dv_xname);
2001 1.16 thorpej if (br == NULL) {
2002 1.16 thorpej printf("unknown ASIC 0x%08x", sc->bge_asicrev);
2003 1.16 thorpej sc->bge_quirks = 0;
2004 1.16 thorpej } else {
2005 1.16 thorpej printf("ASIC %s", br->br_name);
2006 1.16 thorpej sc->bge_quirks = br->br_quirks;
2007 1.16 thorpej }
2008 1.16 thorpej printf(", Ethernet address %s\n", ether_sprintf(eaddr));
2009 1.1 fvdl
2010 1.1 fvdl /* Allocate the general information block and ring buffers. */
2011 1.1 fvdl sc->bge_dmatag = pa->pa_dmat;
2012 1.1 fvdl DPRINTFN(5, ("bus_dmamem_alloc\n"));
2013 1.1 fvdl if (bus_dmamem_alloc(sc->bge_dmatag, sizeof(struct bge_ring_data),
2014 1.1 fvdl PAGE_SIZE, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) {
2015 1.1 fvdl printf("%s: can't alloc rx buffers\n", sc->bge_dev.dv_xname);
2016 1.1 fvdl return;
2017 1.1 fvdl }
2018 1.1 fvdl DPRINTFN(5, ("bus_dmamem_map\n"));
2019 1.1 fvdl if (bus_dmamem_map(sc->bge_dmatag, &seg, rseg,
2020 1.1 fvdl sizeof(struct bge_ring_data), &kva,
2021 1.1 fvdl BUS_DMA_NOWAIT)) {
2022 1.1 fvdl printf("%s: can't map dma buffers (%d bytes)\n",
2023 1.1 fvdl sc->bge_dev.dv_xname, (int)sizeof(struct bge_ring_data));
2024 1.1 fvdl bus_dmamem_free(sc->bge_dmatag, &seg, rseg);
2025 1.1 fvdl return;
2026 1.1 fvdl }
2027 1.1 fvdl DPRINTFN(5, ("bus_dmamem_create\n"));
2028 1.1 fvdl if (bus_dmamap_create(sc->bge_dmatag, sizeof(struct bge_ring_data), 1,
2029 1.1 fvdl sizeof(struct bge_ring_data), 0,
2030 1.1 fvdl BUS_DMA_NOWAIT, &sc->bge_ring_map)) {
2031 1.1 fvdl printf("%s: can't create dma map\n", sc->bge_dev.dv_xname);
2032 1.1 fvdl bus_dmamem_unmap(sc->bge_dmatag, kva,
2033 1.1 fvdl sizeof(struct bge_ring_data));
2034 1.1 fvdl bus_dmamem_free(sc->bge_dmatag, &seg, rseg);
2035 1.1 fvdl return;
2036 1.1 fvdl }
2037 1.1 fvdl DPRINTFN(5, ("bus_dmamem_load\n"));
2038 1.1 fvdl if (bus_dmamap_load(sc->bge_dmatag, sc->bge_ring_map, kva,
2039 1.1 fvdl sizeof(struct bge_ring_data), NULL,
2040 1.1 fvdl BUS_DMA_NOWAIT)) {
2041 1.1 fvdl bus_dmamap_destroy(sc->bge_dmatag, sc->bge_ring_map);
2042 1.1 fvdl bus_dmamem_unmap(sc->bge_dmatag, kva,
2043 1.1 fvdl sizeof(struct bge_ring_data));
2044 1.1 fvdl bus_dmamem_free(sc->bge_dmatag, &seg, rseg);
2045 1.1 fvdl return;
2046 1.1 fvdl }
2047 1.1 fvdl
2048 1.1 fvdl DPRINTFN(5, ("bzero\n"));
2049 1.1 fvdl sc->bge_rdata = (struct bge_ring_data *)kva;
2050 1.1 fvdl
2051 1.19 mjl memset(sc->bge_rdata, 0, sizeof(struct bge_ring_data));
2052 1.1 fvdl
2053 1.1 fvdl /* Try to allocate memory for jumbo buffers. */
2054 1.1 fvdl if (bge_alloc_jumbo_mem(sc)) {
2055 1.1 fvdl printf("%s: jumbo buffer allocation failed\n",
2056 1.1 fvdl sc->bge_dev.dv_xname);
2057 1.8 thorpej } else
2058 1.8 thorpej sc->ethercom.ec_capabilities |= ETHERCAP_JUMBO_MTU;
2059 1.1 fvdl
2060 1.1 fvdl /* Set default tuneable values. */
2061 1.1 fvdl sc->bge_stat_ticks = BGE_TICKS_PER_SEC;
2062 1.1 fvdl sc->bge_rx_coal_ticks = 150;
2063 1.25 jonathan sc->bge_rx_max_coal_bds = 64;
2064 1.25 jonathan #ifdef ORIG_WPAUL_VALUES
2065 1.1 fvdl sc->bge_tx_coal_ticks = 150;
2066 1.1 fvdl sc->bge_tx_max_coal_bds = 128;
2067 1.25 jonathan #else
2068 1.25 jonathan sc->bge_tx_coal_ticks = 300;
2069 1.25 jonathan sc->bge_tx_max_coal_bds = 400;
2070 1.25 jonathan #endif
2071 1.1 fvdl
2072 1.1 fvdl /* Set up ifnet structure */
2073 1.1 fvdl ifp = &sc->ethercom.ec_if;
2074 1.1 fvdl ifp->if_softc = sc;
2075 1.1 fvdl ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
2076 1.1 fvdl ifp->if_ioctl = bge_ioctl;
2077 1.1 fvdl ifp->if_start = bge_start;
2078 1.1 fvdl ifp->if_init = bge_init;
2079 1.1 fvdl ifp->if_watchdog = bge_watchdog;
2080 1.1 fvdl IFQ_SET_MAXLEN(&ifp->if_snd, BGE_TX_RING_CNT - 1);
2081 1.1 fvdl IFQ_SET_READY(&ifp->if_snd);
2082 1.1 fvdl DPRINTFN(5, ("bcopy\n"));
2083 1.1 fvdl strcpy(ifp->if_xname, sc->bge_dev.dv_xname);
2084 1.1 fvdl
2085 1.18 thorpej if ((sc->bge_quirks & BGE_QUIRK_CSUM_BROKEN) == 0)
2086 1.18 thorpej sc->ethercom.ec_if.if_capabilities |=
2087 1.18 thorpej IFCAP_CSUM_IPv4 | IFCAP_CSUM_TCPv4 | IFCAP_CSUM_UDPv4;
2088 1.1 fvdl sc->ethercom.ec_capabilities |=
2089 1.1 fvdl ETHERCAP_VLAN_HWTAGGING | ETHERCAP_VLAN_MTU;
2090 1.1 fvdl
2091 1.1 fvdl /*
2092 1.1 fvdl * Do MII setup.
2093 1.1 fvdl */
2094 1.1 fvdl DPRINTFN(5, ("mii setup\n"));
2095 1.1 fvdl sc->bge_mii.mii_ifp = ifp;
2096 1.1 fvdl sc->bge_mii.mii_readreg = bge_miibus_readreg;
2097 1.1 fvdl sc->bge_mii.mii_writereg = bge_miibus_writereg;
2098 1.1 fvdl sc->bge_mii.mii_statchg = bge_miibus_statchg;
2099 1.1 fvdl
2100 1.1 fvdl /*
2101 1.1 fvdl * Figure out what sort of media we have by checking the
2102 1.1 fvdl * hardware config word in the EEPROM. Note: on some BCM5700
2103 1.1 fvdl * cards, this value appears to be unset. If that's the
2104 1.1 fvdl * case, we have to rely on identifying the NIC by its PCI
2105 1.1 fvdl * subsystem ID, as we do below for the SysKonnect SK-9D41.
2106 1.1 fvdl */
2107 1.1 fvdl bge_read_eeprom(sc, (caddr_t)&hwcfg,
2108 1.1 fvdl BGE_EE_HWCFG_OFFSET, sizeof(hwcfg));
2109 1.1 fvdl if ((be32toh(hwcfg) & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER)
2110 1.1 fvdl sc->bge_tbi = 1;
2111 1.1 fvdl
2112 1.1 fvdl /* The SysKonnect SK-9D41 is a 1000baseSX card. */
2113 1.1 fvdl if ((pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_SUBSYS) >> 16) ==
2114 1.1 fvdl SK_SUBSYSID_9D41)
2115 1.1 fvdl sc->bge_tbi = 1;
2116 1.1 fvdl
2117 1.1 fvdl if (sc->bge_tbi) {
2118 1.1 fvdl ifmedia_init(&sc->bge_ifmedia, IFM_IMASK, bge_ifmedia_upd,
2119 1.1 fvdl bge_ifmedia_sts);
2120 1.1 fvdl ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL);
2121 1.1 fvdl ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_1000_SX|IFM_FDX,
2122 1.1 fvdl 0, NULL);
2123 1.1 fvdl ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL);
2124 1.1 fvdl ifmedia_set(&sc->bge_ifmedia, IFM_ETHER|IFM_AUTO);
2125 1.1 fvdl } else {
2126 1.1 fvdl /*
2127 1.1 fvdl * Do transceiver setup.
2128 1.1 fvdl */
2129 1.1 fvdl ifmedia_init(&sc->bge_mii.mii_media, 0, bge_ifmedia_upd,
2130 1.1 fvdl bge_ifmedia_sts);
2131 1.1 fvdl mii_attach(&sc->bge_dev, &sc->bge_mii, 0xffffffff,
2132 1.1 fvdl MII_PHY_ANY, MII_OFFSET_ANY, 0);
2133 1.1 fvdl
2134 1.1 fvdl if (LIST_FIRST(&sc->bge_mii.mii_phys) == NULL) {
2135 1.1 fvdl printf("%s: no PHY found!\n", sc->bge_dev.dv_xname);
2136 1.1 fvdl ifmedia_add(&sc->bge_mii.mii_media,
2137 1.1 fvdl IFM_ETHER|IFM_MANUAL, 0, NULL);
2138 1.1 fvdl ifmedia_set(&sc->bge_mii.mii_media,
2139 1.1 fvdl IFM_ETHER|IFM_MANUAL);
2140 1.1 fvdl } else
2141 1.1 fvdl ifmedia_set(&sc->bge_mii.mii_media,
2142 1.1 fvdl IFM_ETHER|IFM_AUTO);
2143 1.1 fvdl }
2144 1.1 fvdl
2145 1.1 fvdl /*
2146 1.1 fvdl * Call MI attach routine.
2147 1.1 fvdl */
2148 1.1 fvdl DPRINTFN(5, ("if_attach\n"));
2149 1.1 fvdl if_attach(ifp);
2150 1.1 fvdl DPRINTFN(5, ("ether_ifattach\n"));
2151 1.1 fvdl ether_ifattach(ifp, eaddr);
2152 1.1 fvdl DPRINTFN(5, ("callout_init\n"));
2153 1.1 fvdl callout_init(&sc->bge_timeout);
2154 1.1 fvdl }
2155 1.1 fvdl
2156 1.1 fvdl void
2157 1.1 fvdl bge_release_resources(sc)
2158 1.1 fvdl struct bge_softc *sc;
2159 1.1 fvdl {
2160 1.1 fvdl if (sc->bge_vpd_prodname != NULL)
2161 1.1 fvdl free(sc->bge_vpd_prodname, M_DEVBUF);
2162 1.1 fvdl
2163 1.1 fvdl if (sc->bge_vpd_readonly != NULL)
2164 1.1 fvdl free(sc->bge_vpd_readonly, M_DEVBUF);
2165 1.1 fvdl }
2166 1.1 fvdl
2167 1.1 fvdl void
2168 1.1 fvdl bge_reset(sc)
2169 1.1 fvdl struct bge_softc *sc;
2170 1.1 fvdl {
2171 1.1 fvdl struct pci_attach_args *pa = &sc->bge_pa;
2172 1.1 fvdl u_int32_t cachesize, command, pcistate;
2173 1.1 fvdl int i, val = 0;
2174 1.1 fvdl
2175 1.1 fvdl /* Save some important PCI state. */
2176 1.1 fvdl cachesize = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_CACHESZ);
2177 1.1 fvdl command = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_CMD);
2178 1.1 fvdl pcistate = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_PCISTATE);
2179 1.1 fvdl
2180 1.1 fvdl pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_MISC_CTL,
2181 1.1 fvdl BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR|
2182 1.1 fvdl BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_PCISTATE_RW);
2183 1.1 fvdl
2184 1.1 fvdl /* Issue global reset */
2185 1.1 fvdl bge_writereg_ind(sc, BGE_MISC_CFG,
2186 1.1 fvdl BGE_MISCCFG_RESET_CORE_CLOCKS|(65<<1));
2187 1.1 fvdl
2188 1.1 fvdl DELAY(1000);
2189 1.1 fvdl
2190 1.1 fvdl /* Reset some of the PCI state that got zapped by reset */
2191 1.1 fvdl pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_MISC_CTL,
2192 1.1 fvdl BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR|
2193 1.1 fvdl BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_PCISTATE_RW);
2194 1.1 fvdl pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_CMD, command);
2195 1.1 fvdl pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_CACHESZ, cachesize);
2196 1.1 fvdl bge_writereg_ind(sc, BGE_MISC_CFG, (65 << 1));
2197 1.1 fvdl
2198 1.1 fvdl /* Enable memory arbiter. */
2199 1.1 fvdl CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE);
2200 1.1 fvdl
2201 1.1 fvdl /*
2202 1.1 fvdl * Prevent PXE restart: write a magic number to the
2203 1.1 fvdl * general communications memory at 0xB50.
2204 1.1 fvdl */
2205 1.1 fvdl bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM, BGE_MAGIC_NUMBER);
2206 1.1 fvdl
2207 1.1 fvdl /*
2208 1.1 fvdl * Poll the value location we just wrote until
2209 1.1 fvdl * we see the 1's complement of the magic number.
2210 1.1 fvdl * This indicates that the firmware initialization
2211 1.1 fvdl * is complete.
2212 1.1 fvdl */
2213 1.1 fvdl for (i = 0; i < 750; i++) {
2214 1.1 fvdl val = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM);
2215 1.1 fvdl if (val == ~BGE_MAGIC_NUMBER)
2216 1.1 fvdl break;
2217 1.1 fvdl DELAY(1000);
2218 1.1 fvdl }
2219 1.1 fvdl
2220 1.8 thorpej if (i == 750) {
2221 1.1 fvdl printf("%s: firmware handshake timed out, val = %x\n",
2222 1.1 fvdl sc->bge_dev.dv_xname, val);
2223 1.1 fvdl return;
2224 1.1 fvdl }
2225 1.1 fvdl
2226 1.1 fvdl /*
2227 1.1 fvdl * XXX Wait for the value of the PCISTATE register to
2228 1.1 fvdl * return to its original pre-reset state. This is a
2229 1.1 fvdl * fairly good indicator of reset completion. If we don't
2230 1.1 fvdl * wait for the reset to fully complete, trying to read
2231 1.1 fvdl * from the device's non-PCI registers may yield garbage
2232 1.1 fvdl * results.
2233 1.1 fvdl */
2234 1.1 fvdl for (i = 0; i < BGE_TIMEOUT; i++) {
2235 1.1 fvdl if (pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_PCISTATE) ==
2236 1.1 fvdl pcistate)
2237 1.1 fvdl break;
2238 1.1 fvdl DELAY(10);
2239 1.1 fvdl }
2240 1.1 fvdl
2241 1.1 fvdl /* Enable memory arbiter. */
2242 1.1 fvdl CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE);
2243 1.1 fvdl
2244 1.1 fvdl /* Fix up byte swapping */
2245 1.1 fvdl CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS);
2246 1.1 fvdl
2247 1.1 fvdl CSR_WRITE_4(sc, BGE_MAC_MODE, 0);
2248 1.1 fvdl
2249 1.1 fvdl DELAY(10000);
2250 1.1 fvdl }
2251 1.1 fvdl
2252 1.1 fvdl /*
2253 1.1 fvdl * Frame reception handling. This is called if there's a frame
2254 1.1 fvdl * on the receive return list.
2255 1.1 fvdl *
2256 1.1 fvdl * Note: we have to be able to handle two possibilities here:
2257 1.1 fvdl * 1) the frame is from the jumbo recieve ring
2258 1.1 fvdl * 2) the frame is from the standard receive ring
2259 1.1 fvdl */
2260 1.1 fvdl
2261 1.1 fvdl void
2262 1.1 fvdl bge_rxeof(sc)
2263 1.1 fvdl struct bge_softc *sc;
2264 1.1 fvdl {
2265 1.1 fvdl struct ifnet *ifp;
2266 1.1 fvdl int stdcnt = 0, jumbocnt = 0;
2267 1.1 fvdl int have_tag = 0;
2268 1.1 fvdl u_int16_t vlan_tag = 0;
2269 1.1 fvdl bus_dmamap_t dmamap;
2270 1.1 fvdl bus_addr_t offset, toff;
2271 1.1 fvdl bus_size_t tlen;
2272 1.1 fvdl int tosync;
2273 1.1 fvdl
2274 1.1 fvdl ifp = &sc->ethercom.ec_if;
2275 1.1 fvdl
2276 1.1 fvdl bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map,
2277 1.1 fvdl offsetof(struct bge_ring_data, bge_status_block),
2278 1.1 fvdl sizeof (struct bge_status_block),
2279 1.1 fvdl BUS_DMASYNC_POSTREAD);
2280 1.1 fvdl
2281 1.1 fvdl offset = offsetof(struct bge_ring_data, bge_rx_return_ring);
2282 1.1 fvdl tosync = sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx -
2283 1.1 fvdl sc->bge_rx_saved_considx;
2284 1.1 fvdl
2285 1.1 fvdl toff = offset + (sc->bge_rx_saved_considx * sizeof (struct bge_rx_bd));
2286 1.1 fvdl
2287 1.1 fvdl if (tosync < 0) {
2288 1.1 fvdl tlen = (BGE_RETURN_RING_CNT - sc->bge_rx_saved_considx) *
2289 1.1 fvdl sizeof (struct bge_rx_bd);
2290 1.1 fvdl bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map,
2291 1.1 fvdl toff, tlen, BUS_DMASYNC_POSTREAD);
2292 1.1 fvdl tosync = -tosync;
2293 1.1 fvdl }
2294 1.1 fvdl
2295 1.1 fvdl bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map,
2296 1.1 fvdl offset, tosync * sizeof (struct bge_rx_bd),
2297 1.1 fvdl BUS_DMASYNC_POSTREAD);
2298 1.1 fvdl
2299 1.1 fvdl while(sc->bge_rx_saved_considx !=
2300 1.1 fvdl sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx) {
2301 1.1 fvdl struct bge_rx_bd *cur_rx;
2302 1.1 fvdl u_int32_t rxidx;
2303 1.1 fvdl struct mbuf *m = NULL;
2304 1.1 fvdl
2305 1.1 fvdl cur_rx = &sc->bge_rdata->
2306 1.1 fvdl bge_rx_return_ring[sc->bge_rx_saved_considx];
2307 1.1 fvdl
2308 1.1 fvdl rxidx = cur_rx->bge_idx;
2309 1.1 fvdl BGE_INC(sc->bge_rx_saved_considx, BGE_RETURN_RING_CNT);
2310 1.1 fvdl
2311 1.1 fvdl if (cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) {
2312 1.1 fvdl have_tag = 1;
2313 1.1 fvdl vlan_tag = cur_rx->bge_vlan_tag;
2314 1.1 fvdl }
2315 1.1 fvdl
2316 1.1 fvdl if (cur_rx->bge_flags & BGE_RXBDFLAG_JUMBO_RING) {
2317 1.1 fvdl BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT);
2318 1.1 fvdl m = sc->bge_cdata.bge_rx_jumbo_chain[rxidx];
2319 1.1 fvdl sc->bge_cdata.bge_rx_jumbo_chain[rxidx] = NULL;
2320 1.1 fvdl jumbocnt++;
2321 1.1 fvdl if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) {
2322 1.1 fvdl ifp->if_ierrors++;
2323 1.1 fvdl bge_newbuf_jumbo(sc, sc->bge_jumbo, m);
2324 1.1 fvdl continue;
2325 1.1 fvdl }
2326 1.1 fvdl if (bge_newbuf_jumbo(sc, sc->bge_jumbo,
2327 1.1 fvdl NULL)== ENOBUFS) {
2328 1.1 fvdl ifp->if_ierrors++;
2329 1.1 fvdl bge_newbuf_jumbo(sc, sc->bge_jumbo, m);
2330 1.1 fvdl continue;
2331 1.1 fvdl }
2332 1.1 fvdl } else {
2333 1.1 fvdl BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT);
2334 1.1 fvdl m = sc->bge_cdata.bge_rx_std_chain[rxidx];
2335 1.1 fvdl sc->bge_cdata.bge_rx_std_chain[rxidx] = NULL;
2336 1.1 fvdl stdcnt++;
2337 1.1 fvdl dmamap = sc->bge_cdata.bge_rx_std_map[rxidx];
2338 1.1 fvdl sc->bge_cdata.bge_rx_std_map[rxidx] = 0;
2339 1.1 fvdl if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) {
2340 1.1 fvdl ifp->if_ierrors++;
2341 1.1 fvdl bge_newbuf_std(sc, sc->bge_std, m, dmamap);
2342 1.1 fvdl continue;
2343 1.1 fvdl }
2344 1.1 fvdl if (bge_newbuf_std(sc, sc->bge_std,
2345 1.1 fvdl NULL, dmamap) == ENOBUFS) {
2346 1.1 fvdl ifp->if_ierrors++;
2347 1.1 fvdl bge_newbuf_std(sc, sc->bge_std, m, dmamap);
2348 1.1 fvdl continue;
2349 1.1 fvdl }
2350 1.1 fvdl }
2351 1.1 fvdl
2352 1.1 fvdl ifp->if_ipackets++;
2353 1.1 fvdl m->m_pkthdr.len = m->m_len = cur_rx->bge_len;
2354 1.1 fvdl m->m_pkthdr.rcvif = ifp;
2355 1.1 fvdl
2356 1.1 fvdl #if NBPFILTER > 0
2357 1.1 fvdl /*
2358 1.1 fvdl * Handle BPF listeners. Let the BPF user see the packet.
2359 1.1 fvdl */
2360 1.1 fvdl if (ifp->if_bpf)
2361 1.1 fvdl bpf_mtap(ifp->if_bpf, m);
2362 1.1 fvdl #endif
2363 1.1 fvdl
2364 1.18 thorpej if ((sc->bge_quirks & BGE_QUIRK_CSUM_BROKEN) == 0) {
2365 1.2 fvdl m->m_pkthdr.csum_flags |= M_CSUM_IPv4;
2366 1.2 fvdl if ((cur_rx->bge_ip_csum ^ 0xffff) != 0)
2367 1.2 fvdl m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD;
2368 1.4 fvdl #if 0 /* XXX appears to be broken */
2369 1.2 fvdl if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM) {
2370 1.2 fvdl m->m_pkthdr.csum_data =
2371 1.2 fvdl cur_rx->bge_tcp_udp_csum;
2372 1.2 fvdl m->m_pkthdr.csum_flags |=
2373 1.2 fvdl (M_CSUM_TCPv4|M_CSUM_UDPv4|M_CSUM_DATA);
2374 1.2 fvdl }
2375 1.4 fvdl #endif
2376 1.1 fvdl }
2377 1.1 fvdl
2378 1.1 fvdl /*
2379 1.1 fvdl * If we received a packet with a vlan tag, pass it
2380 1.1 fvdl * to vlan_input() instead of ether_input().
2381 1.1 fvdl */
2382 1.1 fvdl if (have_tag) {
2383 1.1 fvdl struct mbuf *n;
2384 1.1 fvdl
2385 1.1 fvdl n = m_aux_add(m, AF_LINK, ETHERTYPE_VLAN);
2386 1.1 fvdl if (n != NULL) {
2387 1.1 fvdl *mtod(n, int *) = vlan_tag;
2388 1.1 fvdl n->m_len = sizeof(int);
2389 1.1 fvdl have_tag = vlan_tag = 0;
2390 1.1 fvdl } else {
2391 1.1 fvdl printf("%s: no mbuf for tag\n", ifp->if_xname);
2392 1.1 fvdl m_freem(m);
2393 1.1 fvdl have_tag = vlan_tag = 0;
2394 1.1 fvdl continue;
2395 1.1 fvdl }
2396 1.1 fvdl }
2397 1.1 fvdl (*ifp->if_input)(ifp, m);
2398 1.1 fvdl }
2399 1.1 fvdl
2400 1.1 fvdl CSR_WRITE_4(sc, BGE_MBX_RX_CONS0_LO, sc->bge_rx_saved_considx);
2401 1.1 fvdl if (stdcnt)
2402 1.1 fvdl CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std);
2403 1.1 fvdl if (jumbocnt)
2404 1.1 fvdl CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo);
2405 1.1 fvdl }
2406 1.1 fvdl
2407 1.1 fvdl void
2408 1.1 fvdl bge_txeof(sc)
2409 1.1 fvdl struct bge_softc *sc;
2410 1.1 fvdl {
2411 1.1 fvdl struct bge_tx_bd *cur_tx = NULL;
2412 1.1 fvdl struct ifnet *ifp;
2413 1.1 fvdl struct txdmamap_pool_entry *dma;
2414 1.1 fvdl bus_addr_t offset, toff;
2415 1.1 fvdl bus_size_t tlen;
2416 1.1 fvdl int tosync;
2417 1.1 fvdl struct mbuf *m;
2418 1.1 fvdl
2419 1.1 fvdl ifp = &sc->ethercom.ec_if;
2420 1.1 fvdl
2421 1.1 fvdl bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map,
2422 1.1 fvdl offsetof(struct bge_ring_data, bge_status_block),
2423 1.1 fvdl sizeof (struct bge_status_block),
2424 1.1 fvdl BUS_DMASYNC_POSTREAD);
2425 1.1 fvdl
2426 1.1 fvdl offset = offsetof(struct bge_ring_data, bge_tx_ring);
2427 1.1 fvdl tosync = sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx -
2428 1.1 fvdl sc->bge_tx_saved_considx;
2429 1.1 fvdl
2430 1.1 fvdl toff = offset + (sc->bge_tx_saved_considx * sizeof (struct bge_tx_bd));
2431 1.1 fvdl
2432 1.1 fvdl if (tosync < 0) {
2433 1.1 fvdl tlen = (BGE_TX_RING_CNT - sc->bge_tx_saved_considx) *
2434 1.1 fvdl sizeof (struct bge_tx_bd);
2435 1.1 fvdl bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map,
2436 1.1 fvdl toff, tlen, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
2437 1.1 fvdl tosync = -tosync;
2438 1.1 fvdl }
2439 1.1 fvdl
2440 1.1 fvdl bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map,
2441 1.1 fvdl offset, tosync * sizeof (struct bge_tx_bd),
2442 1.1 fvdl BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
2443 1.1 fvdl
2444 1.1 fvdl /*
2445 1.1 fvdl * Go through our tx ring and free mbufs for those
2446 1.1 fvdl * frames that have been sent.
2447 1.1 fvdl */
2448 1.1 fvdl while (sc->bge_tx_saved_considx !=
2449 1.1 fvdl sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx) {
2450 1.1 fvdl u_int32_t idx = 0;
2451 1.1 fvdl
2452 1.1 fvdl idx = sc->bge_tx_saved_considx;
2453 1.1 fvdl cur_tx = &sc->bge_rdata->bge_tx_ring[idx];
2454 1.1 fvdl if (cur_tx->bge_flags & BGE_TXBDFLAG_END)
2455 1.1 fvdl ifp->if_opackets++;
2456 1.1 fvdl m = sc->bge_cdata.bge_tx_chain[idx];
2457 1.1 fvdl if (m != NULL) {
2458 1.1 fvdl sc->bge_cdata.bge_tx_chain[idx] = NULL;
2459 1.1 fvdl dma = sc->txdma[idx];
2460 1.1 fvdl bus_dmamap_sync(sc->bge_dmatag, dma->dmamap, 0,
2461 1.1 fvdl dma->dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE);
2462 1.1 fvdl bus_dmamap_unload(sc->bge_dmatag, dma->dmamap);
2463 1.1 fvdl SLIST_INSERT_HEAD(&sc->txdma_list, dma, link);
2464 1.1 fvdl sc->txdma[idx] = NULL;
2465 1.1 fvdl
2466 1.1 fvdl m_freem(m);
2467 1.1 fvdl }
2468 1.1 fvdl sc->bge_txcnt--;
2469 1.1 fvdl BGE_INC(sc->bge_tx_saved_considx, BGE_TX_RING_CNT);
2470 1.1 fvdl ifp->if_timer = 0;
2471 1.1 fvdl }
2472 1.1 fvdl
2473 1.1 fvdl if (cur_tx != NULL)
2474 1.1 fvdl ifp->if_flags &= ~IFF_OACTIVE;
2475 1.1 fvdl }
2476 1.1 fvdl
2477 1.1 fvdl int
2478 1.1 fvdl bge_intr(xsc)
2479 1.1 fvdl void *xsc;
2480 1.1 fvdl {
2481 1.1 fvdl struct bge_softc *sc;
2482 1.1 fvdl struct ifnet *ifp;
2483 1.1 fvdl
2484 1.1 fvdl sc = xsc;
2485 1.1 fvdl ifp = &sc->ethercom.ec_if;
2486 1.1 fvdl
2487 1.1 fvdl #ifdef notdef
2488 1.1 fvdl /* Avoid this for now -- checking this register is expensive. */
2489 1.1 fvdl /* Make sure this is really our interrupt. */
2490 1.1 fvdl if (!(CSR_READ_4(sc, BGE_MISC_LOCAL_CTL) & BGE_MLC_INTR_STATE))
2491 1.1 fvdl return (0);
2492 1.1 fvdl #endif
2493 1.1 fvdl /* Ack interrupt and stop others from occuring. */
2494 1.1 fvdl CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 1);
2495 1.1 fvdl
2496 1.1 fvdl /*
2497 1.1 fvdl * Process link state changes.
2498 1.1 fvdl * Grrr. The link status word in the status block does
2499 1.1 fvdl * not work correctly on the BCM5700 rev AX and BX chips,
2500 1.1 fvdl * according to all avaibable information. Hence, we have
2501 1.1 fvdl * to enable MII interrupts in order to properly obtain
2502 1.1 fvdl * async link changes. Unfortunately, this also means that
2503 1.1 fvdl * we have to read the MAC status register to detect link
2504 1.1 fvdl * changes, thereby adding an additional register access to
2505 1.1 fvdl * the interrupt handler.
2506 1.1 fvdl */
2507 1.1 fvdl
2508 1.17 thorpej if (sc->bge_quirks & BGE_QUIRK_LINK_STATE_BROKEN) {
2509 1.1 fvdl u_int32_t status;
2510 1.1 fvdl
2511 1.1 fvdl status = CSR_READ_4(sc, BGE_MAC_STS);
2512 1.1 fvdl if (status & BGE_MACSTAT_MI_INTERRUPT) {
2513 1.1 fvdl sc->bge_link = 0;
2514 1.1 fvdl callout_stop(&sc->bge_timeout);
2515 1.1 fvdl bge_tick(sc);
2516 1.1 fvdl /* Clear the interrupt */
2517 1.1 fvdl CSR_WRITE_4(sc, BGE_MAC_EVT_ENB,
2518 1.1 fvdl BGE_EVTENB_MI_INTERRUPT);
2519 1.1 fvdl bge_miibus_readreg(&sc->bge_dev, 1, BRGPHY_MII_ISR);
2520 1.1 fvdl bge_miibus_writereg(&sc->bge_dev, 1, BRGPHY_MII_IMR,
2521 1.1 fvdl BRGPHY_INTRS);
2522 1.1 fvdl }
2523 1.1 fvdl } else {
2524 1.1 fvdl if (sc->bge_rdata->bge_status_block.bge_status &
2525 1.1 fvdl BGE_STATFLAG_LINKSTATE_CHANGED) {
2526 1.1 fvdl sc->bge_link = 0;
2527 1.1 fvdl callout_stop(&sc->bge_timeout);
2528 1.1 fvdl bge_tick(sc);
2529 1.1 fvdl /* Clear the interrupt */
2530 1.1 fvdl CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED|
2531 1.1 fvdl BGE_MACSTAT_CFG_CHANGED);
2532 1.1 fvdl }
2533 1.1 fvdl }
2534 1.1 fvdl
2535 1.1 fvdl if (ifp->if_flags & IFF_RUNNING) {
2536 1.1 fvdl /* Check RX return ring producer/consumer */
2537 1.1 fvdl bge_rxeof(sc);
2538 1.1 fvdl
2539 1.1 fvdl /* Check TX ring producer/consumer */
2540 1.1 fvdl bge_txeof(sc);
2541 1.1 fvdl }
2542 1.1 fvdl
2543 1.1 fvdl bge_handle_events(sc);
2544 1.1 fvdl
2545 1.1 fvdl /* Re-enable interrupts. */
2546 1.1 fvdl CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 0);
2547 1.1 fvdl
2548 1.1 fvdl if (ifp->if_flags & IFF_RUNNING && !IFQ_IS_EMPTY(&ifp->if_snd))
2549 1.1 fvdl bge_start(ifp);
2550 1.1 fvdl
2551 1.1 fvdl return (1);
2552 1.1 fvdl }
2553 1.1 fvdl
2554 1.1 fvdl void
2555 1.1 fvdl bge_tick(xsc)
2556 1.1 fvdl void *xsc;
2557 1.1 fvdl {
2558 1.1 fvdl struct bge_softc *sc = xsc;
2559 1.1 fvdl struct mii_data *mii = &sc->bge_mii;
2560 1.1 fvdl struct ifmedia *ifm = NULL;
2561 1.1 fvdl struct ifnet *ifp = &sc->ethercom.ec_if;
2562 1.1 fvdl int s;
2563 1.1 fvdl
2564 1.1 fvdl s = splnet();
2565 1.1 fvdl
2566 1.1 fvdl bge_stats_update(sc);
2567 1.1 fvdl callout_reset(&sc->bge_timeout, hz, bge_tick, sc);
2568 1.1 fvdl if (sc->bge_link) {
2569 1.1 fvdl splx(s);
2570 1.1 fvdl return;
2571 1.1 fvdl }
2572 1.1 fvdl
2573 1.1 fvdl if (sc->bge_tbi) {
2574 1.1 fvdl ifm = &sc->bge_ifmedia;
2575 1.1 fvdl if (CSR_READ_4(sc, BGE_MAC_STS) &
2576 1.1 fvdl BGE_MACSTAT_TBI_PCS_SYNCHED) {
2577 1.1 fvdl sc->bge_link++;
2578 1.1 fvdl CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF);
2579 1.1 fvdl printf("%s: gigabit link up\n", sc->bge_dev.dv_xname);
2580 1.1 fvdl if (!IFQ_IS_EMPTY(&ifp->if_snd))
2581 1.1 fvdl bge_start(ifp);
2582 1.1 fvdl }
2583 1.1 fvdl splx(s);
2584 1.1 fvdl return;
2585 1.1 fvdl }
2586 1.1 fvdl
2587 1.1 fvdl mii_tick(mii);
2588 1.1 fvdl
2589 1.1 fvdl if (!sc->bge_link && mii->mii_media_status & IFM_ACTIVE &&
2590 1.1 fvdl IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
2591 1.1 fvdl sc->bge_link++;
2592 1.1 fvdl if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T ||
2593 1.1 fvdl IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX)
2594 1.1 fvdl printf("%s: gigabit link up\n", sc->bge_dev.dv_xname);
2595 1.1 fvdl if (!IFQ_IS_EMPTY(&ifp->if_snd))
2596 1.1 fvdl bge_start(ifp);
2597 1.1 fvdl }
2598 1.1 fvdl
2599 1.1 fvdl splx(s);
2600 1.1 fvdl }
2601 1.1 fvdl
2602 1.1 fvdl void
2603 1.1 fvdl bge_stats_update(sc)
2604 1.1 fvdl struct bge_softc *sc;
2605 1.1 fvdl {
2606 1.1 fvdl struct ifnet *ifp = &sc->ethercom.ec_if;
2607 1.1 fvdl bus_size_t stats = BGE_MEMWIN_START + BGE_STATS_BLOCK;
2608 1.1 fvdl
2609 1.1 fvdl #define READ_STAT(sc, stats, stat) \
2610 1.1 fvdl CSR_READ_4(sc, stats + offsetof(struct bge_stats, stat))
2611 1.1 fvdl
2612 1.1 fvdl ifp->if_collisions +=
2613 1.1 fvdl (READ_STAT(sc, stats, dot3StatsSingleCollisionFrames.bge_addr_lo) +
2614 1.1 fvdl READ_STAT(sc, stats, dot3StatsMultipleCollisionFrames.bge_addr_lo) +
2615 1.1 fvdl READ_STAT(sc, stats, dot3StatsExcessiveCollisions.bge_addr_lo) +
2616 1.1 fvdl READ_STAT(sc, stats, dot3StatsLateCollisions.bge_addr_lo)) -
2617 1.1 fvdl ifp->if_collisions;
2618 1.1 fvdl
2619 1.1 fvdl #undef READ_STAT
2620 1.1 fvdl
2621 1.1 fvdl #ifdef notdef
2622 1.1 fvdl ifp->if_collisions +=
2623 1.1 fvdl (sc->bge_rdata->bge_info.bge_stats.dot3StatsSingleCollisionFrames +
2624 1.1 fvdl sc->bge_rdata->bge_info.bge_stats.dot3StatsMultipleCollisionFrames +
2625 1.1 fvdl sc->bge_rdata->bge_info.bge_stats.dot3StatsExcessiveCollisions +
2626 1.1 fvdl sc->bge_rdata->bge_info.bge_stats.dot3StatsLateCollisions) -
2627 1.1 fvdl ifp->if_collisions;
2628 1.1 fvdl #endif
2629 1.1 fvdl }
2630 1.1 fvdl
2631 1.1 fvdl /*
2632 1.1 fvdl * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data
2633 1.1 fvdl * pointers to descriptors.
2634 1.1 fvdl */
2635 1.1 fvdl int
2636 1.1 fvdl bge_encap(sc, m_head, txidx)
2637 1.1 fvdl struct bge_softc *sc;
2638 1.1 fvdl struct mbuf *m_head;
2639 1.1 fvdl u_int32_t *txidx;
2640 1.1 fvdl {
2641 1.1 fvdl struct bge_tx_bd *f = NULL;
2642 1.1 fvdl u_int32_t frag, cur, cnt = 0;
2643 1.1 fvdl u_int16_t csum_flags = 0;
2644 1.1 fvdl struct txdmamap_pool_entry *dma;
2645 1.1 fvdl bus_dmamap_t dmamap;
2646 1.1 fvdl int i = 0;
2647 1.1 fvdl struct mbuf *n;
2648 1.25 jonathan struct mbuf *prev, *m;
2649 1.25 jonathan int totlen, prevlen;
2650 1.1 fvdl
2651 1.1 fvdl cur = frag = *txidx;
2652 1.1 fvdl
2653 1.1 fvdl if (m_head->m_pkthdr.csum_flags) {
2654 1.1 fvdl if (m_head->m_pkthdr.csum_flags & M_CSUM_IPv4)
2655 1.1 fvdl csum_flags |= BGE_TXBDFLAG_IP_CSUM;
2656 1.8 thorpej if (m_head->m_pkthdr.csum_flags & (M_CSUM_TCPv4|M_CSUM_UDPv4))
2657 1.1 fvdl csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM;
2658 1.1 fvdl }
2659 1.1 fvdl
2660 1.25 jonathan if (!(sc->bge_quirks & BGE_QUIRK_5700_SMALLDMA))
2661 1.25 jonathan goto doit;
2662 1.25 jonathan /*
2663 1.25 jonathan * bcm5700 Revision B silicon cannot handle DMA descriptors with
2664 1.25 jonathan * less than eight bytes. If we encounter a teeny mbuf
2665 1.25 jonathan * at the end of a chain, we can pad. Otherwise, copy.
2666 1.25 jonathan */
2667 1.25 jonathan prev = NULL;
2668 1.25 jonathan totlen = 0;
2669 1.25 jonathan for (m = m_head; m != NULL; prev = m,m = m->m_next) {
2670 1.25 jonathan int mlen = m->m_len;
2671 1.25 jonathan
2672 1.25 jonathan totlen += mlen;
2673 1.25 jonathan if (mlen == 0) {
2674 1.25 jonathan /* print a warning? */
2675 1.25 jonathan continue;
2676 1.25 jonathan }
2677 1.25 jonathan if (mlen >= 8)
2678 1.25 jonathan continue;
2679 1.25 jonathan
2680 1.25 jonathan /* If we get here, mbuf data is too small for DMA engine. */
2681 1.25 jonathan if (m->m_next != 0) {
2682 1.25 jonathan /* Internal frag. If fits in prev, copy it there. */
2683 1.25 jonathan if (prev && M_TRAILINGSPACE(prev) >= m->m_len &&
2684 1.25 jonathan !M_READONLY(prev)) {
2685 1.25 jonathan bcopy(m->m_data,
2686 1.25 jonathan prev->m_data+prev->m_len,
2687 1.25 jonathan mlen);
2688 1.25 jonathan prev->m_len += mlen;
2689 1.25 jonathan m->m_len = 0;
2690 1.25 jonathan MFREE(m, prev->m_next); /* XXX stitch chain */
2691 1.25 jonathan m = prev;
2692 1.25 jonathan continue;
2693 1.25 jonathan } else {
2694 1.25 jonathan struct mbuf *n;
2695 1.25 jonathan /* slow copy */
2696 1.25 jonathan slowcopy:
2697 1.25 jonathan n = m_dup(m_head, 0, M_COPYALL, M_DONTWAIT);
2698 1.25 jonathan m_freem(m_head);
2699 1.25 jonathan if (n == 0)
2700 1.25 jonathan return 0;
2701 1.25 jonathan m_head = n;
2702 1.25 jonathan goto doit;
2703 1.25 jonathan }
2704 1.25 jonathan } else if ((totlen -mlen +8) >= 1500) {
2705 1.25 jonathan goto slowcopy;
2706 1.25 jonathan }
2707 1.25 jonathan prevlen = m->m_len;
2708 1.25 jonathan }
2709 1.25 jonathan
2710 1.25 jonathan doit:
2711 1.1 fvdl dma = SLIST_FIRST(&sc->txdma_list);
2712 1.1 fvdl if (dma == NULL)
2713 1.1 fvdl return ENOBUFS;
2714 1.1 fvdl dmamap = dma->dmamap;
2715 1.1 fvdl
2716 1.1 fvdl /*
2717 1.1 fvdl * Start packing the mbufs in this chain into
2718 1.1 fvdl * the fragment pointers. Stop when we run out
2719 1.1 fvdl * of fragments or hit the end of the mbuf chain.
2720 1.1 fvdl */
2721 1.1 fvdl if (bus_dmamap_load_mbuf(sc->bge_dmatag, dmamap, m_head,
2722 1.1 fvdl BUS_DMA_NOWAIT))
2723 1.1 fvdl return(ENOBUFS);
2724 1.1 fvdl
2725 1.6 thorpej n = sc->ethercom.ec_nvlans ?
2726 1.6 thorpej m_aux_find(m_head, AF_LINK, ETHERTYPE_VLAN) : NULL;
2727 1.6 thorpej
2728 1.1 fvdl for (i = 0; i < dmamap->dm_nsegs; i++) {
2729 1.1 fvdl f = &sc->bge_rdata->bge_tx_ring[frag];
2730 1.1 fvdl if (sc->bge_cdata.bge_tx_chain[frag] != NULL)
2731 1.1 fvdl break;
2732 1.1 fvdl bge_set_hostaddr(&f->bge_addr, dmamap->dm_segs[i].ds_addr);
2733 1.1 fvdl f->bge_len = dmamap->dm_segs[i].ds_len;
2734 1.1 fvdl f->bge_flags = csum_flags;
2735 1.1 fvdl
2736 1.1 fvdl if (n != NULL) {
2737 1.1 fvdl f->bge_flags |= BGE_TXBDFLAG_VLAN_TAG;
2738 1.1 fvdl f->bge_vlan_tag = *mtod(n, int *);
2739 1.1 fvdl } else {
2740 1.1 fvdl f->bge_vlan_tag = 0;
2741 1.1 fvdl }
2742 1.1 fvdl /*
2743 1.1 fvdl * Sanity check: avoid coming within 16 descriptors
2744 1.1 fvdl * of the end of the ring.
2745 1.1 fvdl */
2746 1.1 fvdl if ((BGE_TX_RING_CNT - (sc->bge_txcnt + cnt)) < 16)
2747 1.1 fvdl return(ENOBUFS);
2748 1.1 fvdl cur = frag;
2749 1.1 fvdl BGE_INC(frag, BGE_TX_RING_CNT);
2750 1.1 fvdl cnt++;
2751 1.1 fvdl }
2752 1.1 fvdl
2753 1.1 fvdl if (i < dmamap->dm_nsegs)
2754 1.1 fvdl return ENOBUFS;
2755 1.1 fvdl
2756 1.1 fvdl bus_dmamap_sync(sc->bge_dmatag, dmamap, 0, dmamap->dm_mapsize,
2757 1.1 fvdl BUS_DMASYNC_PREWRITE);
2758 1.1 fvdl
2759 1.1 fvdl if (frag == sc->bge_tx_saved_considx)
2760 1.1 fvdl return(ENOBUFS);
2761 1.1 fvdl
2762 1.1 fvdl sc->bge_rdata->bge_tx_ring[cur].bge_flags |= BGE_TXBDFLAG_END;
2763 1.1 fvdl sc->bge_cdata.bge_tx_chain[cur] = m_head;
2764 1.1 fvdl SLIST_REMOVE_HEAD(&sc->txdma_list, link);
2765 1.1 fvdl sc->txdma[cur] = dma;
2766 1.1 fvdl sc->bge_txcnt += cnt;
2767 1.1 fvdl
2768 1.1 fvdl *txidx = frag;
2769 1.1 fvdl
2770 1.1 fvdl return(0);
2771 1.1 fvdl }
2772 1.1 fvdl
2773 1.1 fvdl /*
2774 1.1 fvdl * Main transmit routine. To avoid having to do mbuf copies, we put pointers
2775 1.1 fvdl * to the mbuf data regions directly in the transmit descriptors.
2776 1.1 fvdl */
2777 1.1 fvdl void
2778 1.1 fvdl bge_start(ifp)
2779 1.1 fvdl struct ifnet *ifp;
2780 1.1 fvdl {
2781 1.1 fvdl struct bge_softc *sc;
2782 1.1 fvdl struct mbuf *m_head = NULL;
2783 1.1 fvdl u_int32_t prodidx = 0;
2784 1.1 fvdl int pkts = 0;
2785 1.1 fvdl
2786 1.1 fvdl sc = ifp->if_softc;
2787 1.1 fvdl
2788 1.1 fvdl if (!sc->bge_link && ifp->if_snd.ifq_len < 10)
2789 1.1 fvdl return;
2790 1.1 fvdl
2791 1.1 fvdl prodidx = CSR_READ_4(sc, BGE_MBX_TX_HOST_PROD0_LO);
2792 1.1 fvdl
2793 1.1 fvdl while(sc->bge_cdata.bge_tx_chain[prodidx] == NULL) {
2794 1.1 fvdl IFQ_POLL(&ifp->if_snd, m_head);
2795 1.1 fvdl if (m_head == NULL)
2796 1.1 fvdl break;
2797 1.1 fvdl
2798 1.1 fvdl #if 0
2799 1.1 fvdl /*
2800 1.1 fvdl * XXX
2801 1.1 fvdl * safety overkill. If this is a fragmented packet chain
2802 1.1 fvdl * with delayed TCP/UDP checksums, then only encapsulate
2803 1.1 fvdl * it if we have enough descriptors to handle the entire
2804 1.1 fvdl * chain at once.
2805 1.1 fvdl * (paranoia -- may not actually be needed)
2806 1.1 fvdl */
2807 1.1 fvdl if (m_head->m_flags & M_FIRSTFRAG &&
2808 1.1 fvdl m_head->m_pkthdr.csum_flags & (CSUM_DELAY_DATA)) {
2809 1.1 fvdl if ((BGE_TX_RING_CNT - sc->bge_txcnt) <
2810 1.1 fvdl m_head->m_pkthdr.csum_data + 16) {
2811 1.1 fvdl ifp->if_flags |= IFF_OACTIVE;
2812 1.1 fvdl break;
2813 1.1 fvdl }
2814 1.1 fvdl }
2815 1.1 fvdl #endif
2816 1.1 fvdl
2817 1.1 fvdl /*
2818 1.1 fvdl * Pack the data into the transmit ring. If we
2819 1.1 fvdl * don't have room, set the OACTIVE flag and wait
2820 1.1 fvdl * for the NIC to drain the ring.
2821 1.1 fvdl */
2822 1.1 fvdl if (bge_encap(sc, m_head, &prodidx)) {
2823 1.1 fvdl ifp->if_flags |= IFF_OACTIVE;
2824 1.1 fvdl break;
2825 1.1 fvdl }
2826 1.1 fvdl
2827 1.1 fvdl /* now we are committed to transmit the packet */
2828 1.1 fvdl IFQ_DEQUEUE(&ifp->if_snd, m_head);
2829 1.1 fvdl pkts++;
2830 1.1 fvdl
2831 1.1 fvdl #if NBPFILTER > 0
2832 1.1 fvdl /*
2833 1.1 fvdl * If there's a BPF listener, bounce a copy of this frame
2834 1.1 fvdl * to him.
2835 1.1 fvdl */
2836 1.1 fvdl if (ifp->if_bpf)
2837 1.1 fvdl bpf_mtap(ifp->if_bpf, m_head);
2838 1.1 fvdl #endif
2839 1.1 fvdl }
2840 1.1 fvdl if (pkts == 0)
2841 1.1 fvdl return;
2842 1.1 fvdl
2843 1.1 fvdl /* Transmit */
2844 1.1 fvdl CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx);
2845 1.25 jonathan if (sc->bge_quirks & BGE_QUIRK_PRODUCER_BUG) /* 5700 b2 errata */
2846 1.25 jonathan CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx);
2847 1.1 fvdl
2848 1.1 fvdl /*
2849 1.1 fvdl * Set a timeout in case the chip goes out to lunch.
2850 1.1 fvdl */
2851 1.1 fvdl ifp->if_timer = 5;
2852 1.1 fvdl }
2853 1.1 fvdl
2854 1.1 fvdl int
2855 1.1 fvdl bge_init(ifp)
2856 1.1 fvdl struct ifnet *ifp;
2857 1.1 fvdl {
2858 1.1 fvdl struct bge_softc *sc = ifp->if_softc;
2859 1.1 fvdl u_int16_t *m;
2860 1.1 fvdl int s, error;
2861 1.1 fvdl
2862 1.1 fvdl s = splnet();
2863 1.1 fvdl
2864 1.1 fvdl ifp = &sc->ethercom.ec_if;
2865 1.1 fvdl
2866 1.1 fvdl /* Cancel pending I/O and flush buffers. */
2867 1.1 fvdl bge_stop(sc);
2868 1.1 fvdl bge_reset(sc);
2869 1.1 fvdl bge_chipinit(sc);
2870 1.1 fvdl
2871 1.1 fvdl /*
2872 1.1 fvdl * Init the various state machines, ring
2873 1.1 fvdl * control blocks and firmware.
2874 1.1 fvdl */
2875 1.1 fvdl error = bge_blockinit(sc);
2876 1.1 fvdl if (error != 0) {
2877 1.1 fvdl printf("%s: initialization error %d\n", sc->bge_dev.dv_xname,
2878 1.1 fvdl error);
2879 1.1 fvdl splx(s);
2880 1.1 fvdl return error;
2881 1.1 fvdl }
2882 1.1 fvdl
2883 1.1 fvdl ifp = &sc->ethercom.ec_if;
2884 1.1 fvdl
2885 1.1 fvdl /* Specify MTU. */
2886 1.1 fvdl CSR_WRITE_4(sc, BGE_RX_MTU, ifp->if_mtu +
2887 1.1 fvdl ETHER_HDR_LEN + ETHER_CRC_LEN);
2888 1.1 fvdl
2889 1.1 fvdl /* Load our MAC address. */
2890 1.1 fvdl m = (u_int16_t *)&(LLADDR(ifp->if_sadl)[0]);
2891 1.1 fvdl CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0]));
2892 1.1 fvdl CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, (htons(m[1]) << 16) | htons(m[2]));
2893 1.1 fvdl
2894 1.1 fvdl /* Enable or disable promiscuous mode as needed. */
2895 1.1 fvdl if (ifp->if_flags & IFF_PROMISC) {
2896 1.1 fvdl BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC);
2897 1.1 fvdl } else {
2898 1.1 fvdl BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC);
2899 1.1 fvdl }
2900 1.1 fvdl
2901 1.1 fvdl /* Program multicast filter. */
2902 1.1 fvdl bge_setmulti(sc);
2903 1.1 fvdl
2904 1.1 fvdl /* Init RX ring. */
2905 1.1 fvdl bge_init_rx_ring_std(sc);
2906 1.1 fvdl
2907 1.1 fvdl /* Init jumbo RX ring. */
2908 1.1 fvdl if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN))
2909 1.1 fvdl bge_init_rx_ring_jumbo(sc);
2910 1.1 fvdl
2911 1.1 fvdl /* Init our RX return ring index */
2912 1.1 fvdl sc->bge_rx_saved_considx = 0;
2913 1.1 fvdl
2914 1.1 fvdl /* Init TX ring. */
2915 1.1 fvdl bge_init_tx_ring(sc);
2916 1.1 fvdl
2917 1.1 fvdl /* Turn on transmitter */
2918 1.1 fvdl BGE_SETBIT(sc, BGE_TX_MODE, BGE_TXMODE_ENABLE);
2919 1.1 fvdl
2920 1.1 fvdl /* Turn on receiver */
2921 1.1 fvdl BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE);
2922 1.1 fvdl
2923 1.1 fvdl /* Tell firmware we're alive. */
2924 1.1 fvdl BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
2925 1.1 fvdl
2926 1.1 fvdl /* Enable host interrupts. */
2927 1.1 fvdl BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA);
2928 1.1 fvdl BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR);
2929 1.1 fvdl CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 0);
2930 1.1 fvdl
2931 1.1 fvdl bge_ifmedia_upd(ifp);
2932 1.1 fvdl
2933 1.1 fvdl ifp->if_flags |= IFF_RUNNING;
2934 1.1 fvdl ifp->if_flags &= ~IFF_OACTIVE;
2935 1.1 fvdl
2936 1.1 fvdl splx(s);
2937 1.1 fvdl
2938 1.1 fvdl callout_reset(&sc->bge_timeout, hz, bge_tick, sc);
2939 1.1 fvdl
2940 1.1 fvdl return 0;
2941 1.1 fvdl }
2942 1.1 fvdl
2943 1.1 fvdl /*
2944 1.1 fvdl * Set media options.
2945 1.1 fvdl */
2946 1.1 fvdl int
2947 1.1 fvdl bge_ifmedia_upd(ifp)
2948 1.1 fvdl struct ifnet *ifp;
2949 1.1 fvdl {
2950 1.1 fvdl struct bge_softc *sc = ifp->if_softc;
2951 1.1 fvdl struct mii_data *mii = &sc->bge_mii;
2952 1.1 fvdl struct ifmedia *ifm = &sc->bge_ifmedia;
2953 1.1 fvdl
2954 1.1 fvdl /* If this is a 1000baseX NIC, enable the TBI port. */
2955 1.1 fvdl if (sc->bge_tbi) {
2956 1.1 fvdl if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
2957 1.1 fvdl return(EINVAL);
2958 1.1 fvdl switch(IFM_SUBTYPE(ifm->ifm_media)) {
2959 1.1 fvdl case IFM_AUTO:
2960 1.1 fvdl break;
2961 1.1 fvdl case IFM_1000_SX:
2962 1.1 fvdl if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) {
2963 1.1 fvdl BGE_CLRBIT(sc, BGE_MAC_MODE,
2964 1.1 fvdl BGE_MACMODE_HALF_DUPLEX);
2965 1.1 fvdl } else {
2966 1.1 fvdl BGE_SETBIT(sc, BGE_MAC_MODE,
2967 1.1 fvdl BGE_MACMODE_HALF_DUPLEX);
2968 1.1 fvdl }
2969 1.1 fvdl break;
2970 1.1 fvdl default:
2971 1.1 fvdl return(EINVAL);
2972 1.1 fvdl }
2973 1.1 fvdl return(0);
2974 1.1 fvdl }
2975 1.1 fvdl
2976 1.1 fvdl sc->bge_link = 0;
2977 1.1 fvdl mii_mediachg(mii);
2978 1.1 fvdl
2979 1.1 fvdl return(0);
2980 1.1 fvdl }
2981 1.1 fvdl
2982 1.1 fvdl /*
2983 1.1 fvdl * Report current media status.
2984 1.1 fvdl */
2985 1.1 fvdl void
2986 1.1 fvdl bge_ifmedia_sts(ifp, ifmr)
2987 1.1 fvdl struct ifnet *ifp;
2988 1.1 fvdl struct ifmediareq *ifmr;
2989 1.1 fvdl {
2990 1.1 fvdl struct bge_softc *sc = ifp->if_softc;
2991 1.1 fvdl struct mii_data *mii = &sc->bge_mii;
2992 1.1 fvdl
2993 1.1 fvdl if (sc->bge_tbi) {
2994 1.1 fvdl ifmr->ifm_status = IFM_AVALID;
2995 1.1 fvdl ifmr->ifm_active = IFM_ETHER;
2996 1.1 fvdl if (CSR_READ_4(sc, BGE_MAC_STS) &
2997 1.1 fvdl BGE_MACSTAT_TBI_PCS_SYNCHED)
2998 1.1 fvdl ifmr->ifm_status |= IFM_ACTIVE;
2999 1.1 fvdl ifmr->ifm_active |= IFM_1000_SX;
3000 1.1 fvdl if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX)
3001 1.1 fvdl ifmr->ifm_active |= IFM_HDX;
3002 1.1 fvdl else
3003 1.1 fvdl ifmr->ifm_active |= IFM_FDX;
3004 1.1 fvdl return;
3005 1.1 fvdl }
3006 1.1 fvdl
3007 1.1 fvdl mii_pollstat(mii);
3008 1.1 fvdl ifmr->ifm_active = mii->mii_media_active;
3009 1.1 fvdl ifmr->ifm_status = mii->mii_media_status;
3010 1.1 fvdl }
3011 1.1 fvdl
3012 1.1 fvdl int
3013 1.1 fvdl bge_ioctl(ifp, command, data)
3014 1.1 fvdl struct ifnet *ifp;
3015 1.1 fvdl u_long command;
3016 1.1 fvdl caddr_t data;
3017 1.1 fvdl {
3018 1.1 fvdl struct bge_softc *sc = ifp->if_softc;
3019 1.1 fvdl struct ifreq *ifr = (struct ifreq *) data;
3020 1.1 fvdl int s, error = 0;
3021 1.1 fvdl struct mii_data *mii;
3022 1.1 fvdl
3023 1.1 fvdl s = splnet();
3024 1.1 fvdl
3025 1.1 fvdl switch(command) {
3026 1.1 fvdl case SIOCSIFFLAGS:
3027 1.1 fvdl if (ifp->if_flags & IFF_UP) {
3028 1.1 fvdl /*
3029 1.1 fvdl * If only the state of the PROMISC flag changed,
3030 1.1 fvdl * then just use the 'set promisc mode' command
3031 1.1 fvdl * instead of reinitializing the entire NIC. Doing
3032 1.1 fvdl * a full re-init means reloading the firmware and
3033 1.1 fvdl * waiting for it to start up, which may take a
3034 1.1 fvdl * second or two.
3035 1.1 fvdl */
3036 1.1 fvdl if (ifp->if_flags & IFF_RUNNING &&
3037 1.1 fvdl ifp->if_flags & IFF_PROMISC &&
3038 1.1 fvdl !(sc->bge_if_flags & IFF_PROMISC)) {
3039 1.1 fvdl BGE_SETBIT(sc, BGE_RX_MODE,
3040 1.1 fvdl BGE_RXMODE_RX_PROMISC);
3041 1.1 fvdl } else if (ifp->if_flags & IFF_RUNNING &&
3042 1.1 fvdl !(ifp->if_flags & IFF_PROMISC) &&
3043 1.1 fvdl sc->bge_if_flags & IFF_PROMISC) {
3044 1.1 fvdl BGE_CLRBIT(sc, BGE_RX_MODE,
3045 1.1 fvdl BGE_RXMODE_RX_PROMISC);
3046 1.1 fvdl } else
3047 1.1 fvdl bge_init(ifp);
3048 1.1 fvdl } else {
3049 1.1 fvdl if (ifp->if_flags & IFF_RUNNING) {
3050 1.1 fvdl bge_stop(sc);
3051 1.1 fvdl }
3052 1.1 fvdl }
3053 1.1 fvdl sc->bge_if_flags = ifp->if_flags;
3054 1.1 fvdl error = 0;
3055 1.1 fvdl break;
3056 1.1 fvdl case SIOCSIFMEDIA:
3057 1.1 fvdl case SIOCGIFMEDIA:
3058 1.1 fvdl if (sc->bge_tbi) {
3059 1.1 fvdl error = ifmedia_ioctl(ifp, ifr, &sc->bge_ifmedia,
3060 1.1 fvdl command);
3061 1.1 fvdl } else {
3062 1.1 fvdl mii = &sc->bge_mii;
3063 1.1 fvdl error = ifmedia_ioctl(ifp, ifr, &mii->mii_media,
3064 1.1 fvdl command);
3065 1.1 fvdl }
3066 1.1 fvdl error = 0;
3067 1.1 fvdl break;
3068 1.1 fvdl default:
3069 1.1 fvdl error = ether_ioctl(ifp, command, data);
3070 1.1 fvdl if (error == ENETRESET) {
3071 1.1 fvdl bge_setmulti(sc);
3072 1.1 fvdl error = 0;
3073 1.1 fvdl }
3074 1.1 fvdl break;
3075 1.1 fvdl }
3076 1.1 fvdl
3077 1.1 fvdl splx(s);
3078 1.1 fvdl
3079 1.1 fvdl return(error);
3080 1.1 fvdl }
3081 1.1 fvdl
3082 1.1 fvdl void
3083 1.1 fvdl bge_watchdog(ifp)
3084 1.1 fvdl struct ifnet *ifp;
3085 1.1 fvdl {
3086 1.1 fvdl struct bge_softc *sc;
3087 1.1 fvdl
3088 1.1 fvdl sc = ifp->if_softc;
3089 1.1 fvdl
3090 1.1 fvdl printf("%s: watchdog timeout -- resetting\n", sc->bge_dev.dv_xname);
3091 1.1 fvdl
3092 1.1 fvdl ifp->if_flags &= ~IFF_RUNNING;
3093 1.1 fvdl bge_init(ifp);
3094 1.1 fvdl
3095 1.1 fvdl ifp->if_oerrors++;
3096 1.1 fvdl }
3097 1.1 fvdl
3098 1.11 thorpej static void
3099 1.11 thorpej bge_stop_block(struct bge_softc *sc, bus_addr_t reg, uint32_t bit)
3100 1.11 thorpej {
3101 1.11 thorpej int i;
3102 1.11 thorpej
3103 1.11 thorpej BGE_CLRBIT(sc, reg, bit);
3104 1.11 thorpej
3105 1.11 thorpej for (i = 0; i < BGE_TIMEOUT; i++) {
3106 1.11 thorpej if ((CSR_READ_4(sc, reg) & bit) == 0)
3107 1.11 thorpej return;
3108 1.11 thorpej delay(100);
3109 1.11 thorpej }
3110 1.11 thorpej
3111 1.11 thorpej printf("%s: block failed to stop: reg 0x%lx, bit 0x%08x\n",
3112 1.11 thorpej sc->bge_dev.dv_xname, (u_long) reg, bit);
3113 1.11 thorpej }
3114 1.11 thorpej
3115 1.1 fvdl /*
3116 1.1 fvdl * Stop the adapter and free any mbufs allocated to the
3117 1.1 fvdl * RX and TX lists.
3118 1.1 fvdl */
3119 1.1 fvdl void
3120 1.1 fvdl bge_stop(sc)
3121 1.1 fvdl struct bge_softc *sc;
3122 1.1 fvdl {
3123 1.1 fvdl struct ifnet *ifp = &sc->ethercom.ec_if;
3124 1.1 fvdl
3125 1.1 fvdl callout_stop(&sc->bge_timeout);
3126 1.1 fvdl
3127 1.1 fvdl /*
3128 1.1 fvdl * Disable all of the receiver blocks
3129 1.1 fvdl */
3130 1.11 thorpej bge_stop_block(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE);
3131 1.11 thorpej bge_stop_block(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE);
3132 1.11 thorpej bge_stop_block(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);
3133 1.11 thorpej bge_stop_block(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE);
3134 1.11 thorpej bge_stop_block(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE);
3135 1.11 thorpej bge_stop_block(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);
3136 1.11 thorpej bge_stop_block(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE);
3137 1.1 fvdl
3138 1.1 fvdl /*
3139 1.1 fvdl * Disable all of the transmit blocks
3140 1.1 fvdl */
3141 1.11 thorpej bge_stop_block(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE);
3142 1.11 thorpej bge_stop_block(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE);
3143 1.11 thorpej bge_stop_block(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE);
3144 1.11 thorpej bge_stop_block(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE);
3145 1.11 thorpej bge_stop_block(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE);
3146 1.11 thorpej bge_stop_block(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE);
3147 1.11 thorpej bge_stop_block(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);
3148 1.1 fvdl
3149 1.1 fvdl /*
3150 1.1 fvdl * Shut down all of the memory managers and related
3151 1.1 fvdl * state machines.
3152 1.1 fvdl */
3153 1.11 thorpej bge_stop_block(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE);
3154 1.11 thorpej bge_stop_block(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE);
3155 1.11 thorpej bge_stop_block(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE);
3156 1.11 thorpej
3157 1.1 fvdl CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF);
3158 1.1 fvdl CSR_WRITE_4(sc, BGE_FTQ_RESET, 0);
3159 1.11 thorpej
3160 1.11 thorpej bge_stop_block(sc, BGE_BMAN_MODE, BGE_BMANMODE_ENABLE);
3161 1.11 thorpej bge_stop_block(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE);
3162 1.1 fvdl
3163 1.1 fvdl /* Disable host interrupts. */
3164 1.1 fvdl BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR);
3165 1.1 fvdl CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 1);
3166 1.1 fvdl
3167 1.1 fvdl /*
3168 1.1 fvdl * Tell firmware we're shutting down.
3169 1.1 fvdl */
3170 1.1 fvdl BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
3171 1.1 fvdl
3172 1.1 fvdl /* Free the RX lists. */
3173 1.1 fvdl bge_free_rx_ring_std(sc);
3174 1.1 fvdl
3175 1.1 fvdl /* Free jumbo RX list. */
3176 1.1 fvdl bge_free_rx_ring_jumbo(sc);
3177 1.1 fvdl
3178 1.1 fvdl /* Free TX buffers. */
3179 1.1 fvdl bge_free_tx_ring(sc);
3180 1.1 fvdl
3181 1.1 fvdl /*
3182 1.1 fvdl * Isolate/power down the PHY.
3183 1.1 fvdl */
3184 1.1 fvdl if (!sc->bge_tbi)
3185 1.1 fvdl mii_down(&sc->bge_mii);
3186 1.1 fvdl
3187 1.1 fvdl sc->bge_link = 0;
3188 1.1 fvdl
3189 1.1 fvdl sc->bge_tx_saved_considx = BGE_TXCONS_UNSET;
3190 1.1 fvdl
3191 1.1 fvdl ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
3192 1.1 fvdl }
3193 1.1 fvdl
3194 1.1 fvdl /*
3195 1.1 fvdl * Stop all chip I/O so that the kernel's probe routines don't
3196 1.1 fvdl * get confused by errant DMAs when rebooting.
3197 1.1 fvdl */
3198 1.1 fvdl void
3199 1.1 fvdl bge_shutdown(xsc)
3200 1.1 fvdl void *xsc;
3201 1.1 fvdl {
3202 1.1 fvdl struct bge_softc *sc = (struct bge_softc *)xsc;
3203 1.1 fvdl
3204 1.1 fvdl bge_stop(sc);
3205 1.1 fvdl bge_reset(sc);
3206 1.1 fvdl }
3207