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if_bge.c revision 1.385
      1  1.385     skrll /*	$NetBSD: if_bge.c,v 1.385 2022/09/04 08:42:02 skrll Exp $	*/
      2    1.8   thorpej 
      3    1.1      fvdl /*
      4    1.1      fvdl  * Copyright (c) 2001 Wind River Systems
      5    1.1      fvdl  * Copyright (c) 1997, 1998, 1999, 2001
      6    1.1      fvdl  *	Bill Paul <wpaul (at) windriver.com>.  All rights reserved.
      7    1.1      fvdl  *
      8    1.1      fvdl  * Redistribution and use in source and binary forms, with or without
      9    1.1      fvdl  * modification, are permitted provided that the following conditions
     10    1.1      fvdl  * are met:
     11    1.1      fvdl  * 1. Redistributions of source code must retain the above copyright
     12    1.1      fvdl  *    notice, this list of conditions and the following disclaimer.
     13    1.1      fvdl  * 2. Redistributions in binary form must reproduce the above copyright
     14    1.1      fvdl  *    notice, this list of conditions and the following disclaimer in the
     15    1.1      fvdl  *    documentation and/or other materials provided with the distribution.
     16    1.1      fvdl  * 3. All advertising materials mentioning features or use of this software
     17    1.1      fvdl  *    must display the following acknowledgement:
     18    1.1      fvdl  *	This product includes software developed by Bill Paul.
     19    1.1      fvdl  * 4. Neither the name of the author nor the names of any co-contributors
     20    1.1      fvdl  *    may be used to endorse or promote products derived from this software
     21    1.1      fvdl  *    without specific prior written permission.
     22    1.1      fvdl  *
     23    1.1      fvdl  * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
     24    1.1      fvdl  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
     25    1.1      fvdl  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
     26    1.1      fvdl  * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
     27    1.1      fvdl  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
     28    1.1      fvdl  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
     29    1.1      fvdl  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
     30    1.1      fvdl  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
     31    1.1      fvdl  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
     32    1.1      fvdl  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
     33    1.1      fvdl  * THE POSSIBILITY OF SUCH DAMAGE.
     34    1.1      fvdl  *
     35    1.1      fvdl  * $FreeBSD: if_bge.c,v 1.13 2002/04/04 06:01:31 wpaul Exp $
     36    1.1      fvdl  */
     37    1.1      fvdl 
     38    1.1      fvdl /*
     39   1.12   thorpej  * Broadcom BCM570x family gigabit ethernet driver for NetBSD.
     40    1.1      fvdl  *
     41   1.12   thorpej  * NetBSD version by:
     42   1.12   thorpej  *
     43   1.12   thorpej  *	Frank van der Linden <fvdl (at) wasabisystems.com>
     44   1.12   thorpej  *	Jason Thorpe <thorpej (at) wasabisystems.com>
     45   1.32      tron  *	Jonathan Stone <jonathan (at) dsg.stanford.edu>
     46   1.12   thorpej  *
     47   1.12   thorpej  * Originally written for FreeBSD by Bill Paul <wpaul (at) windriver.com>
     48    1.1      fvdl  * Senior Engineer, Wind River Systems
     49    1.1      fvdl  */
     50    1.1      fvdl 
     51    1.1      fvdl /*
     52    1.1      fvdl  * The Broadcom BCM5700 is based on technology originally developed by
     53    1.1      fvdl  * Alteon Networks as part of the Tigon I and Tigon II gigabit ethernet
     54  1.203   msaitoh  * MAC chips. The BCM5700, sometimes referred to as the Tigon III, has
     55    1.1      fvdl  * two on-board MIPS R4000 CPUs and can have as much as 16MB of external
     56    1.1      fvdl  * SSRAM. The BCM5700 supports TCP, UDP and IP checksum offload, jumbo
     57    1.1      fvdl  * frames, highly configurable RX filtering, and 16 RX and TX queues
     58    1.1      fvdl  * (which, along with RX filter rules, can be used for QOS applications).
     59    1.1      fvdl  * Other features, such as TCP segmentation, may be available as part
     60    1.1      fvdl  * of value-added firmware updates. Unlike the Tigon I and Tigon II,
     61    1.1      fvdl  * firmware images can be stored in hardware and need not be compiled
     62    1.1      fvdl  * into the driver.
     63    1.1      fvdl  *
     64    1.1      fvdl  * The BCM5700 supports the PCI v2.2 and PCI-X v1.0 standards, and will
     65   1.33   tsutsui  * function in a 32-bit/64-bit 33/66MHz bus, or a 64-bit/133MHz bus.
     66    1.1      fvdl  *
     67    1.1      fvdl  * The BCM5701 is a single-chip solution incorporating both the BCM5700
     68   1.25  jonathan  * MAC and a BCM5401 10/100/1000 PHY. Unlike the BCM5700, the BCM5701
     69    1.1      fvdl  * does not support external SSRAM.
     70    1.1      fvdl  *
     71    1.1      fvdl  * Broadcom also produces a variation of the BCM5700 under the "Altima"
     72    1.1      fvdl  * brand name, which is functionally similar but lacks PCI-X support.
     73    1.1      fvdl  *
     74    1.1      fvdl  * Without external SSRAM, you can only have at most 4 TX rings,
     75    1.1      fvdl  * and the use of the mini RX ring is disabled. This seems to imply
     76    1.1      fvdl  * that these features are simply not available on the BCM5701. As a
     77    1.1      fvdl  * result, this driver does not implement any support for the mini RX
     78    1.1      fvdl  * ring.
     79    1.1      fvdl  */
     80   1.43     lukem 
     81   1.43     lukem #include <sys/cdefs.h>
     82  1.385     skrll __KERNEL_RCSID(0, "$NetBSD: if_bge.c,v 1.385 2022/09/04 08:42:02 skrll Exp $");
     83    1.1      fvdl 
     84    1.1      fvdl #include <sys/param.h>
     85  1.370     skrll #include <sys/types.h>
     86  1.355     skrll 
     87    1.1      fvdl #include <sys/callout.h>
     88  1.355     skrll #include <sys/device.h>
     89  1.364     skrll #include <sys/kernel.h>
     90  1.366     skrll #include <sys/kmem.h>
     91    1.1      fvdl #include <sys/mbuf.h>
     92  1.355     skrll #include <sys/rndsource.h>
     93    1.1      fvdl #include <sys/socket.h>
     94  1.355     skrll #include <sys/sockio.h>
     95   1.64  jonathan #include <sys/sysctl.h>
     96  1.355     skrll #include <sys/systm.h>
     97    1.1      fvdl 
     98    1.1      fvdl #include <net/if.h>
     99    1.1      fvdl #include <net/if_dl.h>
    100    1.1      fvdl #include <net/if_media.h>
    101    1.1      fvdl #include <net/if_ether.h>
    102  1.330   msaitoh #include <net/bpf.h>
    103  1.148   mlelstv 
    104  1.247   msaitoh /* Headers for TCP Segmentation Offload (TSO) */
    105   1.95  jonathan #include <netinet/in_systm.h>		/* n_time for <netinet/ip.h>... */
    106   1.95  jonathan #include <netinet/in.h>			/* ip_{src,dst}, for <netinet/ip.h> */
    107   1.95  jonathan #include <netinet/ip.h>			/* for struct ip */
    108   1.95  jonathan #include <netinet/tcp.h>		/* for struct tcphdr */
    109   1.95  jonathan 
    110    1.1      fvdl #include <dev/pci/pcireg.h>
    111    1.1      fvdl #include <dev/pci/pcivar.h>
    112    1.1      fvdl #include <dev/pci/pcidevs.h>
    113    1.1      fvdl 
    114    1.1      fvdl #include <dev/mii/mii.h>
    115    1.1      fvdl #include <dev/mii/miivar.h>
    116    1.1      fvdl #include <dev/mii/miidevs.h>
    117    1.1      fvdl #include <dev/mii/brgphyreg.h>
    118    1.1      fvdl 
    119    1.1      fvdl #include <dev/pci/if_bgereg.h>
    120  1.164   msaitoh #include <dev/pci/if_bgevar.h>
    121    1.1      fvdl 
    122  1.164   msaitoh #include <prop/proplib.h>
    123    1.1      fvdl 
    124   1.46  jonathan #define ETHER_MIN_NOPAD (ETHER_MIN_LEN - ETHER_CRC_LEN) /* i.e., 60 */
    125   1.46  jonathan 
    126   1.63  jonathan 
    127   1.63  jonathan /*
    128   1.63  jonathan  * Tunable thresholds for rx-side bge interrupt mitigation.
    129   1.63  jonathan  */
    130   1.63  jonathan 
    131   1.63  jonathan /*
    132   1.63  jonathan  * The pairs of values below were obtained from empirical measurement
    133   1.63  jonathan  * on bcm5700 rev B2; they ar designed to give roughly 1 receive
    134   1.63  jonathan  * interrupt for every N packets received, where N is, approximately,
    135   1.63  jonathan  * the second value (rx_max_bds) in each pair.  The values are chosen
    136   1.63  jonathan  * such that moving from one pair to the succeeding pair was observed
    137   1.63  jonathan  * to roughly halve interrupt rate under sustained input packet load.
    138   1.63  jonathan  * The values were empirically chosen to avoid overflowing internal
    139  1.184     njoly  * limits on the  bcm5700: increasing rx_ticks much beyond 600
    140   1.63  jonathan  * results in internal wrapping and higher interrupt rates.
    141   1.63  jonathan  * The limit of 46 frames was chosen to match NFS workloads.
    142   1.87     perry  *
    143   1.63  jonathan  * These values also work well on bcm5701, bcm5704C, and (less
    144   1.63  jonathan  * tested) bcm5703.  On other chipsets, (including the Altima chip
    145   1.63  jonathan  * family), the larger values may overflow internal chip limits,
    146   1.63  jonathan  * leading to increasing interrupt rates rather than lower interrupt
    147   1.63  jonathan  * rates.
    148   1.63  jonathan  *
    149   1.63  jonathan  * Applications using heavy interrupt mitigation (interrupting every
    150   1.63  jonathan  * 32 or 46 frames) in both directions may need to increase the TCP
    151   1.63  jonathan  * windowsize to above 131072 bytes (e.g., to 199608 bytes) to sustain
    152   1.87     perry  * full link bandwidth, due to ACKs and window updates lingering
    153   1.63  jonathan  * in the RX queue during the 30-to-40-frame interrupt-mitigation window.
    154   1.63  jonathan  */
    155  1.104   thorpej static const struct bge_load_rx_thresh {
    156   1.63  jonathan 	int rx_ticks;
    157   1.63  jonathan 	int rx_max_bds; }
    158   1.63  jonathan bge_rx_threshes[] = {
    159  1.330   msaitoh 	{ 16,	1 },	/* rx_max_bds = 1 disables interrupt mitigation */
    160  1.330   msaitoh 	{ 32,	2 },
    161  1.330   msaitoh 	{ 50,	4 },
    162  1.330   msaitoh 	{ 100,	8 },
    163   1.63  jonathan 	{ 192, 16 },
    164   1.63  jonathan 	{ 416, 32 },
    165   1.63  jonathan 	{ 598, 46 }
    166   1.63  jonathan };
    167   1.63  jonathan #define NBGE_RX_THRESH (sizeof(bge_rx_threshes) / sizeof(bge_rx_threshes[0]))
    168   1.63  jonathan 
    169   1.63  jonathan /* XXX patchable; should be sysctl'able */
    170  1.177   msaitoh static int bge_auto_thresh = 1;
    171  1.177   msaitoh static int bge_rx_thresh_lvl;
    172   1.64  jonathan 
    173  1.177   msaitoh static int bge_rxthresh_nodenum;
    174    1.1      fvdl 
    175  1.170   msaitoh typedef int (*bge_eaddr_fcn_t)(struct bge_softc *, uint8_t[]);
    176  1.151    cegger 
    177  1.237   msaitoh static uint32_t bge_chipid(const struct pci_attach_args *);
    178  1.288   msaitoh static int bge_can_use_msi(struct bge_softc *);
    179  1.177   msaitoh static int bge_probe(device_t, cfdata_t, void *);
    180  1.177   msaitoh static void bge_attach(device_t, device_t, void *);
    181  1.227   msaitoh static int bge_detach(device_t, int);
    182  1.177   msaitoh static void bge_release_resources(struct bge_softc *);
    183  1.177   msaitoh 
    184  1.177   msaitoh static int bge_get_eaddr_fw(struct bge_softc *, uint8_t[]);
    185  1.177   msaitoh static int bge_get_eaddr_mem(struct bge_softc *, uint8_t[]);
    186  1.177   msaitoh static int bge_get_eaddr_nvram(struct bge_softc *, uint8_t[]);
    187  1.177   msaitoh static int bge_get_eaddr_eeprom(struct bge_softc *, uint8_t[]);
    188  1.177   msaitoh static int bge_get_eaddr(struct bge_softc *, uint8_t[]);
    189  1.177   msaitoh 
    190  1.177   msaitoh static void bge_txeof(struct bge_softc *);
    191  1.219   msaitoh static void bge_rxcsum(struct bge_softc *, struct bge_rx_bd *, struct mbuf *);
    192  1.177   msaitoh static void bge_rxeof(struct bge_softc *);
    193  1.177   msaitoh 
    194  1.177   msaitoh static void bge_asf_driver_up (struct bge_softc *);
    195  1.177   msaitoh static void bge_tick(void *);
    196  1.177   msaitoh static void bge_stats_update(struct bge_softc *);
    197  1.177   msaitoh static void bge_stats_update_regs(struct bge_softc *);
    198  1.177   msaitoh static int bge_encap(struct bge_softc *, struct mbuf *, uint32_t *);
    199  1.177   msaitoh 
    200  1.177   msaitoh static int bge_intr(void *);
    201  1.177   msaitoh static void bge_start(struct ifnet *);
    202  1.375     skrll static void bge_start_locked(struct ifnet *);
    203  1.186   msaitoh static int bge_ifflags_cb(struct ethercom *);
    204  1.177   msaitoh static int bge_ioctl(struct ifnet *, u_long, void *);
    205  1.177   msaitoh static int bge_init(struct ifnet *);
    206  1.375     skrll static int bge_init_locked(struct ifnet *);
    207  1.177   msaitoh static void bge_stop(struct ifnet *, int);
    208  1.375     skrll static void bge_stop_locked(struct ifnet *, int);
    209  1.375     skrll static bool bge_watchdog(struct ifnet *);
    210  1.177   msaitoh static int bge_ifmedia_upd(struct ifnet *);
    211  1.177   msaitoh static void bge_ifmedia_sts(struct ifnet *, struct ifmediareq *);
    212  1.375     skrll static void bge_handle_reset_work(struct work *, void *);
    213  1.177   msaitoh 
    214  1.177   msaitoh static uint8_t bge_nvram_getbyte(struct bge_softc *, int, uint8_t *);
    215  1.177   msaitoh static int bge_read_nvram(struct bge_softc *, uint8_t *, int, int);
    216  1.177   msaitoh 
    217  1.177   msaitoh static uint8_t bge_eeprom_getbyte(struct bge_softc *, int, uint8_t *);
    218  1.177   msaitoh static int bge_read_eeprom(struct bge_softc *, void *, int, int);
    219  1.177   msaitoh static void bge_setmulti(struct bge_softc *);
    220  1.104   thorpej 
    221  1.177   msaitoh static void bge_handle_events(struct bge_softc *);
    222  1.177   msaitoh static int bge_alloc_jumbo_mem(struct bge_softc *);
    223  1.177   msaitoh static void bge_free_jumbo_mem(struct bge_softc *);
    224  1.177   msaitoh static void *bge_jalloc(struct bge_softc *);
    225  1.177   msaitoh static void bge_jfree(struct mbuf *, void *, size_t, void *);
    226  1.177   msaitoh static int bge_newbuf_jumbo(struct bge_softc *, int, struct mbuf *);
    227  1.177   msaitoh static int bge_init_rx_ring_jumbo(struct bge_softc *);
    228  1.177   msaitoh static void bge_free_rx_ring_jumbo(struct bge_softc *);
    229  1.376     skrll 
    230  1.376     skrll static int bge_newbuf_std(struct bge_softc *, int);
    231  1.376     skrll static int bge_init_rx_ring_std(struct bge_softc *);
    232  1.376     skrll static void bge_fill_rx_ring_std(struct bge_softc *);
    233  1.376     skrll static void bge_free_rx_ring_std(struct bge_softc *m);
    234  1.376     skrll 
    235  1.320    bouyer static void bge_free_tx_ring(struct bge_softc *m, bool);
    236  1.177   msaitoh static int bge_init_tx_ring(struct bge_softc *);
    237  1.177   msaitoh 
    238  1.177   msaitoh static int bge_chipinit(struct bge_softc *);
    239  1.177   msaitoh static int bge_blockinit(struct bge_softc *);
    240  1.216   msaitoh static int bge_phy_addr(struct bge_softc *);
    241  1.177   msaitoh static uint32_t bge_readmem_ind(struct bge_softc *, int);
    242  1.177   msaitoh static void bge_writemem_ind(struct bge_softc *, int, int);
    243  1.177   msaitoh static void bge_writembx(struct bge_softc *, int, int);
    244  1.211   msaitoh static void bge_writembx_flush(struct bge_softc *, int, int);
    245  1.177   msaitoh static void bge_writemem_direct(struct bge_softc *, int, int);
    246  1.177   msaitoh static void bge_writereg_ind(struct bge_softc *, int, int);
    247  1.177   msaitoh static void bge_set_max_readrq(struct bge_softc *);
    248  1.177   msaitoh 
    249  1.322   msaitoh static int bge_miibus_readreg(device_t, int, int, uint16_t *);
    250  1.322   msaitoh static int bge_miibus_writereg(device_t, int, int, uint16_t);
    251  1.201      matt static void bge_miibus_statchg(struct ifnet *);
    252  1.177   msaitoh 
    253  1.216   msaitoh #define BGE_RESET_SHUTDOWN	0
    254  1.216   msaitoh #define	BGE_RESET_START		1
    255  1.216   msaitoh #define	BGE_RESET_SUSPEND	2
    256  1.177   msaitoh static void bge_sig_post_reset(struct bge_softc *, int);
    257  1.177   msaitoh static void bge_sig_legacy(struct bge_softc *, int);
    258  1.177   msaitoh static void bge_sig_pre_reset(struct bge_softc *, int);
    259  1.216   msaitoh static void bge_wait_for_event_ack(struct bge_softc *);
    260  1.177   msaitoh static void bge_stop_fw(struct bge_softc *);
    261  1.177   msaitoh static int bge_reset(struct bge_softc *);
    262  1.177   msaitoh static void bge_link_upd(struct bge_softc *);
    263  1.207   msaitoh static void bge_sysctl_init(struct bge_softc *);
    264  1.207   msaitoh static int bge_sysctl_verify(SYSCTLFN_PROTO);
    265   1.95  jonathan 
    266  1.216   msaitoh static void bge_ape_lock_init(struct bge_softc *);
    267  1.216   msaitoh static void bge_ape_read_fw_ver(struct bge_softc *);
    268  1.216   msaitoh static int bge_ape_lock(struct bge_softc *, int);
    269  1.216   msaitoh static void bge_ape_unlock(struct bge_softc *, int);
    270  1.216   msaitoh static void bge_ape_send_event(struct bge_softc *, uint32_t);
    271  1.216   msaitoh static void bge_ape_driver_state_change(struct bge_softc *, int);
    272  1.216   msaitoh 
    273    1.1      fvdl #ifdef BGE_DEBUG
    274    1.1      fvdl #define DPRINTF(x)	if (bgedebug) printf x
    275  1.331   msaitoh #define DPRINTFN(n, x)	if (bgedebug >= (n)) printf x
    276   1.95  jonathan #define BGE_TSO_PRINTF(x)  do { if (bge_tso_debug) printf x ;} while (0)
    277    1.1      fvdl int	bgedebug = 0;
    278   1.95  jonathan int	bge_tso_debug = 0;
    279  1.369     skrll void	bge_debug_info(struct bge_softc *);
    280    1.1      fvdl #else
    281    1.1      fvdl #define DPRINTF(x)
    282  1.331   msaitoh #define DPRINTFN(n, x)
    283   1.95  jonathan #define BGE_TSO_PRINTF(x)
    284    1.1      fvdl #endif
    285    1.1      fvdl 
    286   1.72   thorpej #ifdef BGE_EVENT_COUNTERS
    287   1.72   thorpej #define	BGE_EVCNT_INCR(ev)	(ev).ev_count++
    288   1.72   thorpej #define	BGE_EVCNT_ADD(ev, val)	(ev).ev_count += (val)
    289   1.72   thorpej #define	BGE_EVCNT_UPD(ev, val)	(ev).ev_count = (val)
    290   1.72   thorpej #else
    291   1.72   thorpej #define	BGE_EVCNT_INCR(ev)	/* nothing */
    292   1.72   thorpej #define	BGE_EVCNT_ADD(ev, val)	/* nothing */
    293   1.72   thorpej #define	BGE_EVCNT_UPD(ev, val)	/* nothing */
    294   1.72   thorpej #endif
    295   1.72   thorpej 
    296  1.325   msaitoh #define VIDDID(a, b) PCI_VENDOR_ ## a, PCI_PRODUCT_ ## a ## _ ## b
    297  1.325   msaitoh /*
    298  1.325   msaitoh  * The BCM5700 documentation seems to indicate that the hardware still has the
    299  1.325   msaitoh  * Alteon vendor ID burned into it, though it should always be overridden by
    300  1.325   msaitoh  * the value in the EEPROM.  We'll check for it anyway.
    301  1.325   msaitoh  */
    302  1.158   msaitoh static const struct bge_product {
    303  1.158   msaitoh 	pci_vendor_id_t		bp_vendor;
    304  1.158   msaitoh 	pci_product_id_t	bp_product;
    305  1.158   msaitoh 	const char		*bp_name;
    306  1.158   msaitoh } bge_products[] = {
    307  1.325   msaitoh 	{ VIDDID(ALTEON,   BCM5700),	"Broadcom BCM5700 Gigabit" },
    308  1.325   msaitoh 	{ VIDDID(ALTEON,   BCM5701),	"Broadcom BCM5701 Gigabit" },
    309  1.325   msaitoh 	{ VIDDID(ALTIMA,   AC1000),	"Altima AC1000 Gigabit" },
    310  1.325   msaitoh 	{ VIDDID(ALTIMA,   AC1001),	"Altima AC1001 Gigabit" },
    311  1.325   msaitoh 	{ VIDDID(ALTIMA,   AC1003),	"Altima AC1003 Gigabit" },
    312  1.325   msaitoh 	{ VIDDID(ALTIMA,   AC9100),	"Altima AC9100 Gigabit" },
    313  1.325   msaitoh 	{ VIDDID(APPLE,	   BCM5701),	"APPLE BCM5701 Gigabit" },
    314  1.325   msaitoh 	{ VIDDID(BROADCOM, BCM5700),	"Broadcom BCM5700 Gigabit" },
    315  1.325   msaitoh 	{ VIDDID(BROADCOM, BCM5701),	"Broadcom BCM5701 Gigabit" },
    316  1.325   msaitoh 	{ VIDDID(BROADCOM, BCM5702),	"Broadcom BCM5702 Gigabit" },
    317  1.326   msaitoh 	{ VIDDID(BROADCOM, BCM5702FE),	"Broadcom BCM5702FE Fast" },
    318  1.325   msaitoh 	{ VIDDID(BROADCOM, BCM5702X),	"Broadcom BCM5702X Gigabit" },
    319  1.325   msaitoh 	{ VIDDID(BROADCOM, BCM5703),	"Broadcom BCM5703 Gigabit" },
    320  1.325   msaitoh 	{ VIDDID(BROADCOM, BCM5703X),	"Broadcom BCM5703X Gigabit" },
    321  1.325   msaitoh 	{ VIDDID(BROADCOM, BCM5703_ALT),"Broadcom BCM5703 Gigabit" },
    322  1.325   msaitoh 	{ VIDDID(BROADCOM, BCM5704C),	"Broadcom BCM5704C Dual Gigabit" },
    323  1.325   msaitoh 	{ VIDDID(BROADCOM, BCM5704S),	"Broadcom BCM5704S Dual Gigabit" },
    324  1.326   msaitoh 	{ VIDDID(BROADCOM, BCM5704S_ALT),"Broadcom BCM5704S Dual Gigabit" },
    325  1.325   msaitoh 	{ VIDDID(BROADCOM, BCM5705),	"Broadcom BCM5705 Gigabit" },
    326  1.325   msaitoh 	{ VIDDID(BROADCOM, BCM5705F),	"Broadcom BCM5705F Gigabit" },
    327  1.325   msaitoh 	{ VIDDID(BROADCOM, BCM5705K),	"Broadcom BCM5705K Gigabit" },
    328  1.325   msaitoh 	{ VIDDID(BROADCOM, BCM5705M),	"Broadcom BCM5705M Gigabit" },
    329  1.325   msaitoh 	{ VIDDID(BROADCOM, BCM5705M_ALT),"Broadcom BCM5705M Gigabit" },
    330  1.325   msaitoh 	{ VIDDID(BROADCOM, BCM5714),	"Broadcom BCM5714 Gigabit" },
    331  1.325   msaitoh 	{ VIDDID(BROADCOM, BCM5714S),	"Broadcom BCM5714S Gigabit" },
    332  1.325   msaitoh 	{ VIDDID(BROADCOM, BCM5715),	"Broadcom BCM5715 Gigabit" },
    333  1.325   msaitoh 	{ VIDDID(BROADCOM, BCM5715S),	"Broadcom BCM5715S Gigabit" },
    334  1.325   msaitoh 	{ VIDDID(BROADCOM, BCM5717),	"Broadcom BCM5717 Gigabit" },
    335  1.325   msaitoh 	{ VIDDID(BROADCOM, BCM5717C),	"Broadcom BCM5717 Gigabit" },
    336  1.325   msaitoh 	{ VIDDID(BROADCOM, BCM5718),	"Broadcom BCM5718 Gigabit" },
    337  1.325   msaitoh 	{ VIDDID(BROADCOM, BCM5719),	"Broadcom BCM5719 Gigabit" },
    338  1.325   msaitoh 	{ VIDDID(BROADCOM, BCM5720),	"Broadcom BCM5720 Gigabit" },
    339  1.325   msaitoh 	{ VIDDID(BROADCOM, BCM5721),	"Broadcom BCM5721 Gigabit" },
    340  1.325   msaitoh 	{ VIDDID(BROADCOM, BCM5722),	"Broadcom BCM5722 Gigabit" },
    341  1.325   msaitoh 	{ VIDDID(BROADCOM, BCM5723),	"Broadcom BCM5723 Gigabit" },
    342  1.327   msaitoh 	{ VIDDID(BROADCOM, BCM5725),	"Broadcom BCM5725 Gigabit" },
    343  1.327   msaitoh 	{ VIDDID(BROADCOM, BCM5727),	"Broadcom BCM5727 Gigabit" },
    344  1.325   msaitoh 	{ VIDDID(BROADCOM, BCM5750),	"Broadcom BCM5750 Gigabit" },
    345  1.325   msaitoh 	{ VIDDID(BROADCOM, BCM5751),	"Broadcom BCM5751 Gigabit" },
    346  1.325   msaitoh 	{ VIDDID(BROADCOM, BCM5751F),	"Broadcom BCM5751F Gigabit" },
    347  1.325   msaitoh 	{ VIDDID(BROADCOM, BCM5751M),	"Broadcom BCM5751M Gigabit" },
    348  1.325   msaitoh 	{ VIDDID(BROADCOM, BCM5752),	"Broadcom BCM5752 Gigabit" },
    349  1.325   msaitoh 	{ VIDDID(BROADCOM, BCM5752M),	"Broadcom BCM5752M Gigabit" },
    350  1.325   msaitoh 	{ VIDDID(BROADCOM, BCM5753),	"Broadcom BCM5753 Gigabit" },
    351  1.325   msaitoh 	{ VIDDID(BROADCOM, BCM5753F),	"Broadcom BCM5753F Gigabit" },
    352  1.325   msaitoh 	{ VIDDID(BROADCOM, BCM5753M),	"Broadcom BCM5753M Gigabit" },
    353  1.325   msaitoh 	{ VIDDID(BROADCOM, BCM5754),	"Broadcom BCM5754 Gigabit" },
    354  1.325   msaitoh 	{ VIDDID(BROADCOM, BCM5754M),	"Broadcom BCM5754M Gigabit" },
    355  1.325   msaitoh 	{ VIDDID(BROADCOM, BCM5755),	"Broadcom BCM5755 Gigabit" },
    356  1.325   msaitoh 	{ VIDDID(BROADCOM, BCM5755M),	"Broadcom BCM5755M Gigabit" },
    357  1.325   msaitoh 	{ VIDDID(BROADCOM, BCM5756),	"Broadcom BCM5756 Gigabit" },
    358  1.325   msaitoh 	{ VIDDID(BROADCOM, BCM5761),	"Broadcom BCM5761 Gigabit" },
    359  1.325   msaitoh 	{ VIDDID(BROADCOM, BCM5761E),	"Broadcom BCM5761E Gigabit" },
    360  1.325   msaitoh 	{ VIDDID(BROADCOM, BCM5761S),	"Broadcom BCM5761S Gigabit" },
    361  1.325   msaitoh 	{ VIDDID(BROADCOM, BCM5761SE),	"Broadcom BCM5761SE Gigabit" },
    362  1.327   msaitoh 	{ VIDDID(BROADCOM, BCM5762),	"Broadcom BCM5762 Gigabit" },
    363  1.325   msaitoh 	{ VIDDID(BROADCOM, BCM5764),	"Broadcom BCM5764 Gigabit" },
    364  1.325   msaitoh 	{ VIDDID(BROADCOM, BCM5780),	"Broadcom BCM5780 Gigabit" },
    365  1.325   msaitoh 	{ VIDDID(BROADCOM, BCM5780S),	"Broadcom BCM5780S Gigabit" },
    366  1.325   msaitoh 	{ VIDDID(BROADCOM, BCM5781),	"Broadcom BCM5781 Gigabit" },
    367  1.325   msaitoh 	{ VIDDID(BROADCOM, BCM5782),	"Broadcom BCM5782 Gigabit" },
    368  1.325   msaitoh 	{ VIDDID(BROADCOM, BCM5784M),	"BCM5784M NetLink 1000baseT" },
    369  1.325   msaitoh 	{ VIDDID(BROADCOM, BCM5785F),	"BCM5785F NetLink 10/100" },
    370  1.325   msaitoh 	{ VIDDID(BROADCOM, BCM5785G),	"BCM5785G NetLink 1000baseT" },
    371  1.325   msaitoh 	{ VIDDID(BROADCOM, BCM5786),	"Broadcom BCM5786 Gigabit" },
    372  1.325   msaitoh 	{ VIDDID(BROADCOM, BCM5787),	"Broadcom BCM5787 Gigabit" },
    373  1.325   msaitoh 	{ VIDDID(BROADCOM, BCM5787F),	"Broadcom BCM5787F 10/100" },
    374  1.325   msaitoh 	{ VIDDID(BROADCOM, BCM5787M),	"Broadcom BCM5787M Gigabit" },
    375  1.325   msaitoh 	{ VIDDID(BROADCOM, BCM5788),	"Broadcom BCM5788 Gigabit" },
    376  1.325   msaitoh 	{ VIDDID(BROADCOM, BCM5789),	"Broadcom BCM5789 Gigabit" },
    377  1.325   msaitoh 	{ VIDDID(BROADCOM, BCM5901),	"Broadcom BCM5901 Fast" },
    378  1.325   msaitoh 	{ VIDDID(BROADCOM, BCM5901A2),	"Broadcom BCM5901A2 Fast" },
    379  1.325   msaitoh 	{ VIDDID(BROADCOM, BCM5903M),	"Broadcom BCM5903M Fast" },
    380  1.325   msaitoh 	{ VIDDID(BROADCOM, BCM5906),	"Broadcom BCM5906 Fast" },
    381  1.325   msaitoh 	{ VIDDID(BROADCOM, BCM5906M),	"Broadcom BCM5906M Fast" },
    382  1.325   msaitoh 	{ VIDDID(BROADCOM, BCM57760),	"Broadcom BCM57760 Gigabit" },
    383  1.325   msaitoh 	{ VIDDID(BROADCOM, BCM57761),	"Broadcom BCM57761 Gigabit" },
    384  1.325   msaitoh 	{ VIDDID(BROADCOM, BCM57762),	"Broadcom BCM57762 Gigabit" },
    385  1.327   msaitoh 	{ VIDDID(BROADCOM, BCM57764),	"Broadcom BCM57764 Gigabit" },
    386  1.325   msaitoh 	{ VIDDID(BROADCOM, BCM57765),	"Broadcom BCM57765 Gigabit" },
    387  1.325   msaitoh 	{ VIDDID(BROADCOM, BCM57766),	"Broadcom BCM57766 Gigabit" },
    388  1.327   msaitoh 	{ VIDDID(BROADCOM, BCM57767),	"Broadcom BCM57767 Gigabit" },
    389  1.325   msaitoh 	{ VIDDID(BROADCOM, BCM57780),	"Broadcom BCM57780 Gigabit" },
    390  1.325   msaitoh 	{ VIDDID(BROADCOM, BCM57781),	"Broadcom BCM57781 Gigabit" },
    391  1.325   msaitoh 	{ VIDDID(BROADCOM, BCM57782),	"Broadcom BCM57782 Gigabit" },
    392  1.325   msaitoh 	{ VIDDID(BROADCOM, BCM57785),	"Broadcom BCM57785 Gigabit" },
    393  1.325   msaitoh 	{ VIDDID(BROADCOM, BCM57786),	"Broadcom BCM57786 Gigabit" },
    394  1.327   msaitoh 	{ VIDDID(BROADCOM, BCM57787),	"Broadcom BCM57787 Gigabit" },
    395  1.325   msaitoh 	{ VIDDID(BROADCOM, BCM57788),	"Broadcom BCM57788 Gigabit" },
    396  1.325   msaitoh 	{ VIDDID(BROADCOM, BCM57790),	"Broadcom BCM57790 Gigabit" },
    397  1.325   msaitoh 	{ VIDDID(BROADCOM, BCM57791),	"Broadcom BCM57791 Gigabit" },
    398  1.325   msaitoh 	{ VIDDID(BROADCOM, BCM57795),	"Broadcom BCM57795 Gigabit" },
    399  1.325   msaitoh 	{ VIDDID(SCHNEIDERKOCH, SK_9DX1),"SysKonnect SK-9Dx1 Gigabit" },
    400  1.326   msaitoh 	{ VIDDID(SCHNEIDERKOCH, SK_9MXX),"SysKonnect SK-9Mxx Gigabit" },
    401  1.325   msaitoh 	{ VIDDID(3COM, 3C996),		"3Com 3c996 Gigabit" },
    402  1.325   msaitoh 	{ VIDDID(FUJITSU4, PW008GE4),	"Fujitsu PW008GE4 Gigabit" },
    403  1.325   msaitoh 	{ VIDDID(FUJITSU4, PW008GE5),	"Fujitsu PW008GE5 Gigabit" },
    404  1.325   msaitoh 	{ VIDDID(FUJITSU4, PP250_450_LAN),"Fujitsu Primepower 250/450 Gigabit" },
    405  1.325   msaitoh 	{ 0, 0, NULL },
    406  1.158   msaitoh };
    407  1.158   msaitoh 
    408  1.261   msaitoh #define BGE_IS_JUMBO_CAPABLE(sc)	((sc)->bge_flags & BGEF_JUMBO_CAPABLE)
    409  1.261   msaitoh #define BGE_IS_5700_FAMILY(sc)		((sc)->bge_flags & BGEF_5700_FAMILY)
    410  1.261   msaitoh #define BGE_IS_5705_PLUS(sc)		((sc)->bge_flags & BGEF_5705_PLUS)
    411  1.261   msaitoh #define BGE_IS_5714_FAMILY(sc)		((sc)->bge_flags & BGEF_5714_FAMILY)
    412  1.261   msaitoh #define BGE_IS_575X_PLUS(sc)		((sc)->bge_flags & BGEF_575X_PLUS)
    413  1.261   msaitoh #define BGE_IS_5755_PLUS(sc)		((sc)->bge_flags & BGEF_5755_PLUS)
    414  1.261   msaitoh #define BGE_IS_57765_FAMILY(sc)		((sc)->bge_flags & BGEF_57765_FAMILY)
    415  1.261   msaitoh #define BGE_IS_57765_PLUS(sc)		((sc)->bge_flags & BGEF_57765_PLUS)
    416  1.261   msaitoh #define BGE_IS_5717_PLUS(sc)		((sc)->bge_flags & BGEF_5717_PLUS)
    417  1.166   msaitoh 
    418  1.158   msaitoh static const struct bge_revision {
    419  1.158   msaitoh 	uint32_t		br_chipid;
    420  1.158   msaitoh 	const char		*br_name;
    421  1.158   msaitoh } bge_revisions[] = {
    422  1.158   msaitoh 	{ BGE_CHIPID_BCM5700_A0, "BCM5700 A0" },
    423  1.158   msaitoh 	{ BGE_CHIPID_BCM5700_A1, "BCM5700 A1" },
    424  1.158   msaitoh 	{ BGE_CHIPID_BCM5700_B0, "BCM5700 B0" },
    425  1.158   msaitoh 	{ BGE_CHIPID_BCM5700_B1, "BCM5700 B1" },
    426  1.158   msaitoh 	{ BGE_CHIPID_BCM5700_B2, "BCM5700 B2" },
    427  1.158   msaitoh 	{ BGE_CHIPID_BCM5700_B3, "BCM5700 B3" },
    428  1.158   msaitoh 	{ BGE_CHIPID_BCM5700_ALTIMA, "BCM5700 Altima" },
    429  1.158   msaitoh 	{ BGE_CHIPID_BCM5700_C0, "BCM5700 C0" },
    430  1.158   msaitoh 	{ BGE_CHIPID_BCM5701_A0, "BCM5701 A0" },
    431  1.158   msaitoh 	{ BGE_CHIPID_BCM5701_B0, "BCM5701 B0" },
    432  1.158   msaitoh 	{ BGE_CHIPID_BCM5701_B2, "BCM5701 B2" },
    433  1.158   msaitoh 	{ BGE_CHIPID_BCM5701_B5, "BCM5701 B5" },
    434  1.172   msaitoh 	{ BGE_CHIPID_BCM5703_A0, "BCM5702/5703 A0" },
    435  1.172   msaitoh 	{ BGE_CHIPID_BCM5703_A1, "BCM5702/5703 A1" },
    436  1.172   msaitoh 	{ BGE_CHIPID_BCM5703_A2, "BCM5702/5703 A2" },
    437  1.172   msaitoh 	{ BGE_CHIPID_BCM5703_A3, "BCM5702/5703 A3" },
    438  1.172   msaitoh 	{ BGE_CHIPID_BCM5703_B0, "BCM5702/5703 B0" },
    439  1.158   msaitoh 	{ BGE_CHIPID_BCM5704_A0, "BCM5704 A0" },
    440  1.158   msaitoh 	{ BGE_CHIPID_BCM5704_A1, "BCM5704 A1" },
    441  1.158   msaitoh 	{ BGE_CHIPID_BCM5704_A2, "BCM5704 A2" },
    442  1.158   msaitoh 	{ BGE_CHIPID_BCM5704_A3, "BCM5704 A3" },
    443  1.159   msaitoh 	{ BGE_CHIPID_BCM5704_B0, "BCM5704 B0" },
    444  1.158   msaitoh 	{ BGE_CHIPID_BCM5705_A0, "BCM5705 A0" },
    445  1.158   msaitoh 	{ BGE_CHIPID_BCM5705_A1, "BCM5705 A1" },
    446  1.158   msaitoh 	{ BGE_CHIPID_BCM5705_A2, "BCM5705 A2" },
    447  1.158   msaitoh 	{ BGE_CHIPID_BCM5705_A3, "BCM5705 A3" },
    448  1.158   msaitoh 	{ BGE_CHIPID_BCM5750_A0, "BCM5750 A0" },
    449  1.158   msaitoh 	{ BGE_CHIPID_BCM5750_A1, "BCM5750 A1" },
    450  1.161   msaitoh 	{ BGE_CHIPID_BCM5750_A3, "BCM5750 A3" },
    451  1.161   msaitoh 	{ BGE_CHIPID_BCM5750_B0, "BCM5750 B0" },
    452  1.161   msaitoh 	{ BGE_CHIPID_BCM5750_B1, "BCM5750 B1" },
    453  1.161   msaitoh 	{ BGE_CHIPID_BCM5750_C0, "BCM5750 C0" },
    454  1.161   msaitoh 	{ BGE_CHIPID_BCM5750_C1, "BCM5750 C1" },
    455  1.161   msaitoh 	{ BGE_CHIPID_BCM5750_C2, "BCM5750 C2" },
    456  1.158   msaitoh 	{ BGE_CHIPID_BCM5752_A0, "BCM5752 A0" },
    457  1.158   msaitoh 	{ BGE_CHIPID_BCM5752_A1, "BCM5752 A1" },
    458  1.158   msaitoh 	{ BGE_CHIPID_BCM5752_A2, "BCM5752 A2" },
    459  1.159   msaitoh 	{ BGE_CHIPID_BCM5714_A0, "BCM5714 A0" },
    460  1.159   msaitoh 	{ BGE_CHIPID_BCM5714_B0, "BCM5714 B0" },
    461  1.159   msaitoh 	{ BGE_CHIPID_BCM5714_B3, "BCM5714 B3" },
    462  1.159   msaitoh 	{ BGE_CHIPID_BCM5715_A0, "BCM5715 A0" },
    463  1.159   msaitoh 	{ BGE_CHIPID_BCM5715_A1, "BCM5715 A1" },
    464  1.159   msaitoh 	{ BGE_CHIPID_BCM5715_A3, "BCM5715 A3" },
    465  1.216   msaitoh 	{ BGE_CHIPID_BCM5717_A0, "BCM5717 A0" },
    466  1.216   msaitoh 	{ BGE_CHIPID_BCM5717_B0, "BCM5717 B0" },
    467  1.216   msaitoh 	{ BGE_CHIPID_BCM5719_A0, "BCM5719 A0" },
    468  1.216   msaitoh 	{ BGE_CHIPID_BCM5720_A0, "BCM5720 A0" },
    469  1.158   msaitoh 	{ BGE_CHIPID_BCM5755_A0, "BCM5755 A0" },
    470  1.158   msaitoh 	{ BGE_CHIPID_BCM5755_A1, "BCM5755 A1" },
    471  1.158   msaitoh 	{ BGE_CHIPID_BCM5755_A2, "BCM5755 A2" },
    472  1.158   msaitoh 	{ BGE_CHIPID_BCM5755_C0, "BCM5755 C0" },
    473  1.172   msaitoh 	{ BGE_CHIPID_BCM5761_A0, "BCM5761 A0" },
    474  1.172   msaitoh 	{ BGE_CHIPID_BCM5761_A1, "BCM5761 A1" },
    475  1.327   msaitoh 	{ BGE_CHIPID_BCM5762_A0, "BCM5762 A0" },
    476  1.327   msaitoh 	{ BGE_CHIPID_BCM5762_B0, "BCM5762 B0" },
    477  1.172   msaitoh 	{ BGE_CHIPID_BCM5784_A0, "BCM5784 A0" },
    478  1.172   msaitoh 	{ BGE_CHIPID_BCM5784_A1, "BCM5784 A1" },
    479  1.284   msaitoh 	{ BGE_CHIPID_BCM5784_B0, "BCM5784 B0" },
    480  1.172   msaitoh 	/* 5754 and 5787 share the same ASIC ID */
    481  1.158   msaitoh 	{ BGE_CHIPID_BCM5787_A0, "BCM5754/5787 A0" },
    482  1.158   msaitoh 	{ BGE_CHIPID_BCM5787_A1, "BCM5754/5787 A1" },
    483  1.158   msaitoh 	{ BGE_CHIPID_BCM5787_A2, "BCM5754/5787 A2" },
    484  1.206   msaitoh 	{ BGE_CHIPID_BCM5906_A0, "BCM5906 A0" },
    485  1.161   msaitoh 	{ BGE_CHIPID_BCM5906_A1, "BCM5906 A1" },
    486  1.161   msaitoh 	{ BGE_CHIPID_BCM5906_A2, "BCM5906 A2" },
    487  1.214   msaitoh 	{ BGE_CHIPID_BCM57765_A0, "BCM57765 A0" },
    488  1.214   msaitoh 	{ BGE_CHIPID_BCM57765_B0, "BCM57765 B0" },
    489  1.305   msaitoh 	{ BGE_CHIPID_BCM57766_A0, "BCM57766 A0" },
    490  1.172   msaitoh 	{ BGE_CHIPID_BCM57780_A0, "BCM57780 A0" },
    491  1.172   msaitoh 	{ BGE_CHIPID_BCM57780_A1, "BCM57780 A1" },
    492  1.172   msaitoh 
    493  1.158   msaitoh 	{ 0, NULL }
    494  1.158   msaitoh };
    495  1.158   msaitoh 
    496  1.158   msaitoh /*
    497  1.158   msaitoh  * Some defaults for major revisions, so that newer steppings
    498  1.158   msaitoh  * that we don't know about have a shot at working.
    499  1.158   msaitoh  */
    500  1.158   msaitoh static const struct bge_revision bge_majorrevs[] = {
    501  1.158   msaitoh 	{ BGE_ASICREV_BCM5700, "unknown BCM5700" },
    502  1.158   msaitoh 	{ BGE_ASICREV_BCM5701, "unknown BCM5701" },
    503  1.158   msaitoh 	{ BGE_ASICREV_BCM5703, "unknown BCM5703" },
    504  1.158   msaitoh 	{ BGE_ASICREV_BCM5704, "unknown BCM5704" },
    505  1.158   msaitoh 	{ BGE_ASICREV_BCM5705, "unknown BCM5705" },
    506  1.162   msaitoh 	{ BGE_ASICREV_BCM5750, "unknown BCM5750" },
    507  1.216   msaitoh 	{ BGE_ASICREV_BCM5714, "unknown BCM5714" },
    508  1.158   msaitoh 	{ BGE_ASICREV_BCM5714_A0, "unknown BCM5714" },
    509  1.172   msaitoh 	{ BGE_ASICREV_BCM5752, "unknown BCM5752" },
    510  1.172   msaitoh 	{ BGE_ASICREV_BCM5780, "unknown BCM5780" },
    511  1.158   msaitoh 	{ BGE_ASICREV_BCM5755, "unknown BCM5755" },
    512  1.172   msaitoh 	{ BGE_ASICREV_BCM5761, "unknown BCM5761" },
    513  1.172   msaitoh 	{ BGE_ASICREV_BCM5784, "unknown BCM5784" },
    514  1.172   msaitoh 	{ BGE_ASICREV_BCM5785, "unknown BCM5785" },
    515  1.162   msaitoh 	/* 5754 and 5787 share the same ASIC ID */
    516  1.166   msaitoh 	{ BGE_ASICREV_BCM5787, "unknown BCM5754/5787" },
    517  1.172   msaitoh 	{ BGE_ASICREV_BCM5906, "unknown BCM5906" },
    518  1.216   msaitoh 	{ BGE_ASICREV_BCM57765, "unknown BCM57765" },
    519  1.216   msaitoh 	{ BGE_ASICREV_BCM57766, "unknown BCM57766" },
    520  1.172   msaitoh 	{ BGE_ASICREV_BCM57780, "unknown BCM57780" },
    521  1.172   msaitoh 	{ BGE_ASICREV_BCM5717, "unknown BCM5717" },
    522  1.216   msaitoh 	{ BGE_ASICREV_BCM5719, "unknown BCM5719" },
    523  1.216   msaitoh 	{ BGE_ASICREV_BCM5720, "unknown BCM5720" },
    524  1.327   msaitoh 	{ BGE_ASICREV_BCM5762, "unknown BCM5762" },
    525  1.172   msaitoh 
    526  1.158   msaitoh 	{ 0, NULL }
    527  1.158   msaitoh };
    528   1.17   thorpej 
    529  1.177   msaitoh static int bge_allow_asf = 1;
    530  1.177   msaitoh 
    531  1.375     skrll #ifndef BGE_WATCHDOG_TIMEOUT
    532  1.375     skrll #define BGE_WATCHDOG_TIMEOUT 5
    533  1.375     skrll #endif
    534  1.375     skrll static int bge_watchdog_timeout = BGE_WATCHDOG_TIMEOUT;
    535  1.375     skrll 
    536  1.375     skrll 
    537  1.227   msaitoh CFATTACH_DECL3_NEW(bge, sizeof(struct bge_softc),
    538  1.227   msaitoh     bge_probe, bge_attach, bge_detach, NULL, NULL, NULL, DVF_DETACH_SHUTDOWN);
    539    1.1      fvdl 
    540  1.170   msaitoh static uint32_t
    541  1.104   thorpej bge_readmem_ind(struct bge_softc *sc, int off)
    542    1.1      fvdl {
    543    1.1      fvdl 	pcireg_t val;
    544    1.1      fvdl 
    545  1.216   msaitoh 	if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906 &&
    546  1.216   msaitoh 	    off >= BGE_STATS_BLOCK && off < BGE_SEND_RING_1_TO_4)
    547  1.216   msaitoh 		return 0;
    548  1.216   msaitoh 
    549  1.141  jmcneill 	pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_BASEADDR, off);
    550  1.141  jmcneill 	val = pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_DATA);
    551  1.216   msaitoh 	pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_BASEADDR, 0);
    552    1.1      fvdl 	return val;
    553    1.1      fvdl }
    554    1.1      fvdl 
    555  1.104   thorpej static void
    556  1.104   thorpej bge_writemem_ind(struct bge_softc *sc, int off, int val)
    557    1.1      fvdl {
    558  1.216   msaitoh 
    559  1.141  jmcneill 	pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_BASEADDR, off);
    560  1.141  jmcneill 	pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_DATA, val);
    561  1.216   msaitoh 	pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_BASEADDR, 0);
    562    1.1      fvdl }
    563    1.1      fvdl 
    564  1.177   msaitoh /*
    565  1.177   msaitoh  * PCI Express only
    566  1.177   msaitoh  */
    567  1.177   msaitoh static void
    568  1.177   msaitoh bge_set_max_readrq(struct bge_softc *sc)
    569  1.177   msaitoh {
    570  1.177   msaitoh 	pcireg_t val;
    571  1.177   msaitoh 
    572  1.180   msaitoh 	val = pci_conf_read(sc->sc_pc, sc->sc_pcitag, sc->bge_pciecap
    573  1.238   msaitoh 	    + PCIE_DCSR);
    574  1.238   msaitoh 	val &= ~PCIE_DCSR_MAX_READ_REQ;
    575  1.216   msaitoh 	switch (sc->bge_expmrq) {
    576  1.216   msaitoh 	case 2048:
    577  1.216   msaitoh 		val |= BGE_PCIE_DEVCTL_MAX_READRQ_2048;
    578  1.216   msaitoh 		break;
    579  1.216   msaitoh 	case 4096:
    580  1.177   msaitoh 		val |= BGE_PCIE_DEVCTL_MAX_READRQ_4096;
    581  1.216   msaitoh 		break;
    582  1.216   msaitoh 	default:
    583  1.216   msaitoh 		panic("incorrect expmrq value(%d)", sc->bge_expmrq);
    584  1.216   msaitoh 		break;
    585  1.177   msaitoh 	}
    586  1.216   msaitoh 	pci_conf_write(sc->sc_pc, sc->sc_pcitag, sc->bge_pciecap
    587  1.238   msaitoh 	    + PCIE_DCSR, val);
    588  1.177   msaitoh }
    589  1.177   msaitoh 
    590    1.1      fvdl #ifdef notdef
    591  1.170   msaitoh static uint32_t
    592  1.104   thorpej bge_readreg_ind(struct bge_softc *sc, int off)
    593    1.1      fvdl {
    594  1.141  jmcneill 	pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_REG_BASEADDR, off);
    595  1.362     skrll 	return pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_REG_DATA);
    596    1.1      fvdl }
    597    1.1      fvdl #endif
    598    1.1      fvdl 
    599  1.104   thorpej static void
    600  1.104   thorpej bge_writereg_ind(struct bge_softc *sc, int off, int val)
    601    1.1      fvdl {
    602  1.141  jmcneill 	pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_REG_BASEADDR, off);
    603  1.141  jmcneill 	pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_REG_DATA, val);
    604    1.1      fvdl }
    605    1.1      fvdl 
    606  1.151    cegger static void
    607  1.151    cegger bge_writemem_direct(struct bge_softc *sc, int off, int val)
    608  1.151    cegger {
    609  1.151    cegger 	CSR_WRITE_4(sc, off, val);
    610  1.151    cegger }
    611  1.151    cegger 
    612  1.151    cegger static void
    613  1.151    cegger bge_writembx(struct bge_softc *sc, int off, int val)
    614  1.151    cegger {
    615  1.151    cegger 	if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906)
    616  1.151    cegger 		off += BGE_LPMBX_IRQ0_HI - BGE_MBX_IRQ0_HI;
    617  1.151    cegger 
    618  1.151    cegger 	CSR_WRITE_4(sc, off, val);
    619  1.151    cegger }
    620  1.151    cegger 
    621  1.211   msaitoh static void
    622  1.211   msaitoh bge_writembx_flush(struct bge_softc *sc, int off, int val)
    623  1.211   msaitoh {
    624  1.211   msaitoh 	if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906)
    625  1.211   msaitoh 		off += BGE_LPMBX_IRQ0_HI - BGE_MBX_IRQ0_HI;
    626  1.211   msaitoh 
    627  1.211   msaitoh 	CSR_WRITE_4_FLUSH(sc, off, val);
    628  1.211   msaitoh }
    629  1.211   msaitoh 
    630  1.216   msaitoh /*
    631  1.216   msaitoh  * Clear all stale locks and select the lock for this driver instance.
    632  1.216   msaitoh  */
    633  1.216   msaitoh void
    634  1.216   msaitoh bge_ape_lock_init(struct bge_softc *sc)
    635  1.216   msaitoh {
    636  1.216   msaitoh 	struct pci_attach_args *pa = &(sc->bge_pa);
    637  1.216   msaitoh 	uint32_t bit, regbase;
    638  1.216   msaitoh 	int i;
    639  1.216   msaitoh 
    640  1.216   msaitoh 	if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761)
    641  1.216   msaitoh 		regbase = BGE_APE_LOCK_GRANT;
    642  1.216   msaitoh 	else
    643  1.216   msaitoh 		regbase = BGE_APE_PER_LOCK_GRANT;
    644  1.216   msaitoh 
    645  1.216   msaitoh 	/* Clear any stale locks. */
    646  1.216   msaitoh 	for (i = BGE_APE_LOCK_PHY0; i <= BGE_APE_LOCK_GPIO; i++) {
    647  1.216   msaitoh 		switch (i) {
    648  1.216   msaitoh 		case BGE_APE_LOCK_PHY0:
    649  1.216   msaitoh 		case BGE_APE_LOCK_PHY1:
    650  1.216   msaitoh 		case BGE_APE_LOCK_PHY2:
    651  1.216   msaitoh 		case BGE_APE_LOCK_PHY3:
    652  1.216   msaitoh 			bit = BGE_APE_LOCK_GRANT_DRIVER0;
    653  1.216   msaitoh 			break;
    654  1.216   msaitoh 		default:
    655  1.231   msaitoh 			if (pa->pa_function == 0)
    656  1.216   msaitoh 				bit = BGE_APE_LOCK_GRANT_DRIVER0;
    657  1.216   msaitoh 			else
    658  1.216   msaitoh 				bit = (1 << pa->pa_function);
    659  1.216   msaitoh 		}
    660  1.216   msaitoh 		APE_WRITE_4(sc, regbase + 4 * i, bit);
    661  1.216   msaitoh 	}
    662  1.216   msaitoh 
    663  1.216   msaitoh 	/* Select the PHY lock based on the device's function number. */
    664  1.216   msaitoh 	switch (pa->pa_function) {
    665  1.216   msaitoh 	case 0:
    666  1.216   msaitoh 		sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY0;
    667  1.216   msaitoh 		break;
    668  1.216   msaitoh 	case 1:
    669  1.216   msaitoh 		sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY1;
    670  1.216   msaitoh 		break;
    671  1.216   msaitoh 	case 2:
    672  1.216   msaitoh 		sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY2;
    673  1.216   msaitoh 		break;
    674  1.216   msaitoh 	case 3:
    675  1.216   msaitoh 		sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY3;
    676  1.216   msaitoh 		break;
    677  1.216   msaitoh 	default:
    678  1.216   msaitoh 		printf("%s: PHY lock not supported on function\n",
    679  1.216   msaitoh 		    device_xname(sc->bge_dev));
    680  1.216   msaitoh 		break;
    681  1.216   msaitoh 	}
    682  1.216   msaitoh }
    683  1.216   msaitoh 
    684  1.216   msaitoh /*
    685  1.216   msaitoh  * Check for APE firmware, set flags, and print version info.
    686  1.216   msaitoh  */
    687  1.216   msaitoh void
    688  1.216   msaitoh bge_ape_read_fw_ver(struct bge_softc *sc)
    689  1.216   msaitoh {
    690  1.216   msaitoh 	const char *fwtype;
    691  1.216   msaitoh 	uint32_t apedata, features;
    692  1.216   msaitoh 
    693  1.216   msaitoh 	/* Check for a valid APE signature in shared memory. */
    694  1.216   msaitoh 	apedata = APE_READ_4(sc, BGE_APE_SEG_SIG);
    695  1.216   msaitoh 	if (apedata != BGE_APE_SEG_SIG_MAGIC) {
    696  1.216   msaitoh 		sc->bge_mfw_flags &= ~ BGE_MFW_ON_APE;
    697  1.216   msaitoh 		return;
    698  1.216   msaitoh 	}
    699  1.216   msaitoh 
    700  1.216   msaitoh 	/* Check if APE firmware is running. */
    701  1.216   msaitoh 	apedata = APE_READ_4(sc, BGE_APE_FW_STATUS);
    702  1.216   msaitoh 	if ((apedata & BGE_APE_FW_STATUS_READY) == 0) {
    703  1.216   msaitoh 		printf("%s: APE signature found but FW status not ready! "
    704  1.216   msaitoh 		    "0x%08x\n", device_xname(sc->bge_dev), apedata);
    705  1.216   msaitoh 		return;
    706  1.216   msaitoh 	}
    707  1.216   msaitoh 
    708  1.216   msaitoh 	sc->bge_mfw_flags |= BGE_MFW_ON_APE;
    709  1.216   msaitoh 
    710  1.216   msaitoh 	/* Fetch the APE firwmare type and version. */
    711  1.216   msaitoh 	apedata = APE_READ_4(sc, BGE_APE_FW_VERSION);
    712  1.216   msaitoh 	features = APE_READ_4(sc, BGE_APE_FW_FEATURES);
    713  1.216   msaitoh 	if ((features & BGE_APE_FW_FEATURE_NCSI) != 0) {
    714  1.216   msaitoh 		sc->bge_mfw_flags |= BGE_MFW_TYPE_NCSI;
    715  1.216   msaitoh 		fwtype = "NCSI";
    716  1.216   msaitoh 	} else if ((features & BGE_APE_FW_FEATURE_DASH) != 0) {
    717  1.216   msaitoh 		sc->bge_mfw_flags |= BGE_MFW_TYPE_DASH;
    718  1.216   msaitoh 		fwtype = "DASH";
    719  1.216   msaitoh 	} else
    720  1.216   msaitoh 		fwtype = "UNKN";
    721  1.216   msaitoh 
    722  1.216   msaitoh 	/* Print the APE firmware version. */
    723  1.271   msaitoh 	aprint_normal_dev(sc->bge_dev, "APE firmware %s %d.%d.%d.%d\n", fwtype,
    724  1.216   msaitoh 	    (apedata & BGE_APE_FW_VERSION_MAJMSK) >> BGE_APE_FW_VERSION_MAJSFT,
    725  1.216   msaitoh 	    (apedata & BGE_APE_FW_VERSION_MINMSK) >> BGE_APE_FW_VERSION_MINSFT,
    726  1.216   msaitoh 	    (apedata & BGE_APE_FW_VERSION_REVMSK) >> BGE_APE_FW_VERSION_REVSFT,
    727  1.216   msaitoh 	    (apedata & BGE_APE_FW_VERSION_BLDMSK));
    728  1.216   msaitoh }
    729  1.216   msaitoh 
    730  1.216   msaitoh int
    731  1.216   msaitoh bge_ape_lock(struct bge_softc *sc, int locknum)
    732  1.216   msaitoh {
    733  1.216   msaitoh 	struct pci_attach_args *pa = &(sc->bge_pa);
    734  1.216   msaitoh 	uint32_t bit, gnt, req, status;
    735  1.216   msaitoh 	int i, off;
    736  1.216   msaitoh 
    737  1.216   msaitoh 	if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0)
    738  1.362     skrll 		return 0;
    739  1.216   msaitoh 
    740  1.216   msaitoh 	/* Lock request/grant registers have different bases. */
    741  1.216   msaitoh 	if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761) {
    742  1.216   msaitoh 		req = BGE_APE_LOCK_REQ;
    743  1.216   msaitoh 		gnt = BGE_APE_LOCK_GRANT;
    744  1.216   msaitoh 	} else {
    745  1.216   msaitoh 		req = BGE_APE_PER_LOCK_REQ;
    746  1.216   msaitoh 		gnt = BGE_APE_PER_LOCK_GRANT;
    747  1.216   msaitoh 	}
    748  1.216   msaitoh 
    749  1.216   msaitoh 	off = 4 * locknum;
    750  1.216   msaitoh 
    751  1.216   msaitoh 	switch (locknum) {
    752  1.216   msaitoh 	case BGE_APE_LOCK_GPIO:
    753  1.216   msaitoh 		/* Lock required when using GPIO. */
    754  1.216   msaitoh 		if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761)
    755  1.362     skrll 			return 0;
    756  1.216   msaitoh 		if (pa->pa_function == 0)
    757  1.216   msaitoh 			bit = BGE_APE_LOCK_REQ_DRIVER0;
    758  1.216   msaitoh 		else
    759  1.216   msaitoh 			bit = (1 << pa->pa_function);
    760  1.216   msaitoh 		break;
    761  1.216   msaitoh 	case BGE_APE_LOCK_GRC:
    762  1.216   msaitoh 		/* Lock required to reset the device. */
    763  1.216   msaitoh 		if (pa->pa_function == 0)
    764  1.216   msaitoh 			bit = BGE_APE_LOCK_REQ_DRIVER0;
    765  1.216   msaitoh 		else
    766  1.216   msaitoh 			bit = (1 << pa->pa_function);
    767  1.216   msaitoh 		break;
    768  1.216   msaitoh 	case BGE_APE_LOCK_MEM:
    769  1.216   msaitoh 		/* Lock required when accessing certain APE memory. */
    770  1.216   msaitoh 		if (pa->pa_function == 0)
    771  1.216   msaitoh 			bit = BGE_APE_LOCK_REQ_DRIVER0;
    772  1.216   msaitoh 		else
    773  1.216   msaitoh 			bit = (1 << pa->pa_function);
    774  1.216   msaitoh 		break;
    775  1.216   msaitoh 	case BGE_APE_LOCK_PHY0:
    776  1.216   msaitoh 	case BGE_APE_LOCK_PHY1:
    777  1.216   msaitoh 	case BGE_APE_LOCK_PHY2:
    778  1.216   msaitoh 	case BGE_APE_LOCK_PHY3:
    779  1.216   msaitoh 		/* Lock required when accessing PHYs. */
    780  1.216   msaitoh 		bit = BGE_APE_LOCK_REQ_DRIVER0;
    781  1.216   msaitoh 		break;
    782  1.216   msaitoh 	default:
    783  1.362     skrll 		return EINVAL;
    784  1.216   msaitoh 	}
    785  1.216   msaitoh 
    786  1.216   msaitoh 	/* Request a lock. */
    787  1.216   msaitoh 	APE_WRITE_4_FLUSH(sc, req + off, bit);
    788  1.216   msaitoh 
    789  1.216   msaitoh 	/* Wait up to 1 second to acquire lock. */
    790  1.216   msaitoh 	for (i = 0; i < 20000; i++) {
    791  1.216   msaitoh 		status = APE_READ_4(sc, gnt + off);
    792  1.216   msaitoh 		if (status == bit)
    793  1.216   msaitoh 			break;
    794  1.216   msaitoh 		DELAY(50);
    795  1.216   msaitoh 	}
    796  1.216   msaitoh 
    797  1.216   msaitoh 	/* Handle any errors. */
    798  1.216   msaitoh 	if (status != bit) {
    799  1.216   msaitoh 		printf("%s: APE lock %d request failed! "
    800  1.216   msaitoh 		    "request = 0x%04x[0x%04x], status = 0x%04x[0x%04x]\n",
    801  1.216   msaitoh 		    device_xname(sc->bge_dev),
    802  1.216   msaitoh 		    locknum, req + off, bit & 0xFFFF, gnt + off,
    803  1.216   msaitoh 		    status & 0xFFFF);
    804  1.216   msaitoh 		/* Revoke the lock request. */
    805  1.216   msaitoh 		APE_WRITE_4(sc, gnt + off, bit);
    806  1.362     skrll 		return EBUSY;
    807  1.216   msaitoh 	}
    808  1.216   msaitoh 
    809  1.362     skrll 	return 0;
    810  1.216   msaitoh }
    811  1.216   msaitoh 
    812  1.216   msaitoh void
    813  1.216   msaitoh bge_ape_unlock(struct bge_softc *sc, int locknum)
    814  1.216   msaitoh {
    815  1.216   msaitoh 	struct pci_attach_args *pa = &(sc->bge_pa);
    816  1.216   msaitoh 	uint32_t bit, gnt;
    817  1.216   msaitoh 	int off;
    818  1.216   msaitoh 
    819  1.216   msaitoh 	if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0)
    820  1.216   msaitoh 		return;
    821  1.216   msaitoh 
    822  1.216   msaitoh 	if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761)
    823  1.216   msaitoh 		gnt = BGE_APE_LOCK_GRANT;
    824  1.216   msaitoh 	else
    825  1.216   msaitoh 		gnt = BGE_APE_PER_LOCK_GRANT;
    826  1.216   msaitoh 
    827  1.216   msaitoh 	off = 4 * locknum;
    828  1.216   msaitoh 
    829  1.216   msaitoh 	switch (locknum) {
    830  1.216   msaitoh 	case BGE_APE_LOCK_GPIO:
    831  1.216   msaitoh 		if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761)
    832  1.216   msaitoh 			return;
    833  1.216   msaitoh 		if (pa->pa_function == 0)
    834  1.216   msaitoh 			bit = BGE_APE_LOCK_GRANT_DRIVER0;
    835  1.216   msaitoh 		else
    836  1.216   msaitoh 			bit = (1 << pa->pa_function);
    837  1.216   msaitoh 		break;
    838  1.216   msaitoh 	case BGE_APE_LOCK_GRC:
    839  1.216   msaitoh 		if (pa->pa_function == 0)
    840  1.216   msaitoh 			bit = BGE_APE_LOCK_GRANT_DRIVER0;
    841  1.216   msaitoh 		else
    842  1.216   msaitoh 			bit = (1 << pa->pa_function);
    843  1.216   msaitoh 		break;
    844  1.216   msaitoh 	case BGE_APE_LOCK_MEM:
    845  1.216   msaitoh 		if (pa->pa_function == 0)
    846  1.216   msaitoh 			bit = BGE_APE_LOCK_GRANT_DRIVER0;
    847  1.216   msaitoh 		else
    848  1.216   msaitoh 			bit = (1 << pa->pa_function);
    849  1.216   msaitoh 		break;
    850  1.216   msaitoh 	case BGE_APE_LOCK_PHY0:
    851  1.216   msaitoh 	case BGE_APE_LOCK_PHY1:
    852  1.216   msaitoh 	case BGE_APE_LOCK_PHY2:
    853  1.216   msaitoh 	case BGE_APE_LOCK_PHY3:
    854  1.216   msaitoh 		bit = BGE_APE_LOCK_GRANT_DRIVER0;
    855  1.216   msaitoh 		break;
    856  1.216   msaitoh 	default:
    857  1.216   msaitoh 		return;
    858  1.216   msaitoh 	}
    859  1.216   msaitoh 
    860  1.216   msaitoh 	/* Write and flush for consecutive bge_ape_lock() */
    861  1.216   msaitoh 	APE_WRITE_4_FLUSH(sc, gnt + off, bit);
    862  1.216   msaitoh }
    863  1.216   msaitoh 
    864  1.216   msaitoh /*
    865  1.216   msaitoh  * Send an event to the APE firmware.
    866  1.216   msaitoh  */
    867  1.216   msaitoh void
    868  1.216   msaitoh bge_ape_send_event(struct bge_softc *sc, uint32_t event)
    869  1.216   msaitoh {
    870  1.216   msaitoh 	uint32_t apedata;
    871  1.216   msaitoh 	int i;
    872  1.216   msaitoh 
    873  1.216   msaitoh 	/* NCSI does not support APE events. */
    874  1.216   msaitoh 	if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0)
    875  1.216   msaitoh 		return;
    876  1.216   msaitoh 
    877  1.216   msaitoh 	/* Wait up to 1ms for APE to service previous event. */
    878  1.216   msaitoh 	for (i = 10; i > 0; i--) {
    879  1.216   msaitoh 		if (bge_ape_lock(sc, BGE_APE_LOCK_MEM) != 0)
    880  1.216   msaitoh 			break;
    881  1.216   msaitoh 		apedata = APE_READ_4(sc, BGE_APE_EVENT_STATUS);
    882  1.216   msaitoh 		if ((apedata & BGE_APE_EVENT_STATUS_EVENT_PENDING) == 0) {
    883  1.216   msaitoh 			APE_WRITE_4(sc, BGE_APE_EVENT_STATUS, event |
    884  1.216   msaitoh 			    BGE_APE_EVENT_STATUS_EVENT_PENDING);
    885  1.216   msaitoh 			bge_ape_unlock(sc, BGE_APE_LOCK_MEM);
    886  1.216   msaitoh 			APE_WRITE_4(sc, BGE_APE_EVENT, BGE_APE_EVENT_1);
    887  1.216   msaitoh 			break;
    888  1.216   msaitoh 		}
    889  1.216   msaitoh 		bge_ape_unlock(sc, BGE_APE_LOCK_MEM);
    890  1.216   msaitoh 		DELAY(100);
    891  1.216   msaitoh 	}
    892  1.216   msaitoh 	if (i == 0) {
    893  1.216   msaitoh 		printf("%s: APE event 0x%08x send timed out\n",
    894  1.216   msaitoh 		    device_xname(sc->bge_dev), event);
    895  1.216   msaitoh 	}
    896  1.216   msaitoh }
    897  1.216   msaitoh 
    898  1.216   msaitoh void
    899  1.216   msaitoh bge_ape_driver_state_change(struct bge_softc *sc, int kind)
    900  1.216   msaitoh {
    901  1.216   msaitoh 	uint32_t apedata, event;
    902  1.216   msaitoh 
    903  1.216   msaitoh 	if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0)
    904  1.216   msaitoh 		return;
    905  1.216   msaitoh 
    906  1.216   msaitoh 	switch (kind) {
    907  1.216   msaitoh 	case BGE_RESET_START:
    908  1.216   msaitoh 		/* If this is the first load, clear the load counter. */
    909  1.216   msaitoh 		apedata = APE_READ_4(sc, BGE_APE_HOST_SEG_SIG);
    910  1.216   msaitoh 		if (apedata != BGE_APE_HOST_SEG_SIG_MAGIC)
    911  1.216   msaitoh 			APE_WRITE_4(sc, BGE_APE_HOST_INIT_COUNT, 0);
    912  1.216   msaitoh 		else {
    913  1.216   msaitoh 			apedata = APE_READ_4(sc, BGE_APE_HOST_INIT_COUNT);
    914  1.216   msaitoh 			APE_WRITE_4(sc, BGE_APE_HOST_INIT_COUNT, ++apedata);
    915  1.216   msaitoh 		}
    916  1.216   msaitoh 		APE_WRITE_4(sc, BGE_APE_HOST_SEG_SIG,
    917  1.216   msaitoh 		    BGE_APE_HOST_SEG_SIG_MAGIC);
    918  1.216   msaitoh 		APE_WRITE_4(sc, BGE_APE_HOST_SEG_LEN,
    919  1.216   msaitoh 		    BGE_APE_HOST_SEG_LEN_MAGIC);
    920  1.216   msaitoh 
    921  1.216   msaitoh 		/* Add some version info if bge(4) supports it. */
    922  1.216   msaitoh 		APE_WRITE_4(sc, BGE_APE_HOST_DRIVER_ID,
    923  1.216   msaitoh 		    BGE_APE_HOST_DRIVER_ID_MAGIC(1, 0));
    924  1.216   msaitoh 		APE_WRITE_4(sc, BGE_APE_HOST_BEHAVIOR,
    925  1.216   msaitoh 		    BGE_APE_HOST_BEHAV_NO_PHYLOCK);
    926  1.216   msaitoh 		APE_WRITE_4(sc, BGE_APE_HOST_HEARTBEAT_INT_MS,
    927  1.216   msaitoh 		    BGE_APE_HOST_HEARTBEAT_INT_DISABLE);
    928  1.216   msaitoh 		APE_WRITE_4(sc, BGE_APE_HOST_DRVR_STATE,
    929  1.216   msaitoh 		    BGE_APE_HOST_DRVR_STATE_START);
    930  1.216   msaitoh 		event = BGE_APE_EVENT_STATUS_STATE_START;
    931  1.216   msaitoh 		break;
    932  1.216   msaitoh 	case BGE_RESET_SHUTDOWN:
    933  1.216   msaitoh 		APE_WRITE_4(sc, BGE_APE_HOST_DRVR_STATE,
    934  1.216   msaitoh 		    BGE_APE_HOST_DRVR_STATE_UNLOAD);
    935  1.216   msaitoh 		event = BGE_APE_EVENT_STATUS_STATE_UNLOAD;
    936  1.216   msaitoh 		break;
    937  1.216   msaitoh 	case BGE_RESET_SUSPEND:
    938  1.216   msaitoh 		event = BGE_APE_EVENT_STATUS_STATE_SUSPEND;
    939  1.216   msaitoh 		break;
    940  1.216   msaitoh 	default:
    941  1.216   msaitoh 		return;
    942  1.216   msaitoh 	}
    943  1.216   msaitoh 
    944  1.216   msaitoh 	bge_ape_send_event(sc, event | BGE_APE_EVENT_STATUS_DRIVER_EVNT |
    945  1.216   msaitoh 	    BGE_APE_EVENT_STATUS_STATE_CHNGE);
    946  1.216   msaitoh }
    947  1.216   msaitoh 
    948  1.170   msaitoh static uint8_t
    949  1.170   msaitoh bge_nvram_getbyte(struct bge_softc *sc, int addr, uint8_t *dest)
    950  1.151    cegger {
    951  1.170   msaitoh 	uint32_t access, byte = 0;
    952  1.151    cegger 	int i;
    953  1.151    cegger 
    954  1.151    cegger 	/* Lock. */
    955  1.151    cegger 	CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_SET1);
    956  1.151    cegger 	for (i = 0; i < 8000; i++) {
    957  1.151    cegger 		if (CSR_READ_4(sc, BGE_NVRAM_SWARB) & BGE_NVRAMSWARB_GNT1)
    958  1.151    cegger 			break;
    959  1.151    cegger 		DELAY(20);
    960  1.151    cegger 	}
    961  1.151    cegger 	if (i == 8000)
    962  1.170   msaitoh 		return 1;
    963  1.151    cegger 
    964  1.151    cegger 	/* Enable access. */
    965  1.151    cegger 	access = CSR_READ_4(sc, BGE_NVRAM_ACCESS);
    966  1.151    cegger 	CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access | BGE_NVRAMACC_ENABLE);
    967  1.151    cegger 
    968  1.151    cegger 	CSR_WRITE_4(sc, BGE_NVRAM_ADDR, addr & 0xfffffffc);
    969  1.151    cegger 	CSR_WRITE_4(sc, BGE_NVRAM_CMD, BGE_NVRAM_READCMD);
    970  1.151    cegger 	for (i = 0; i < BGE_TIMEOUT * 10; i++) {
    971  1.151    cegger 		DELAY(10);
    972  1.151    cegger 		if (CSR_READ_4(sc, BGE_NVRAM_CMD) & BGE_NVRAMCMD_DONE) {
    973  1.151    cegger 			DELAY(10);
    974  1.151    cegger 			break;
    975  1.151    cegger 		}
    976  1.151    cegger 	}
    977  1.151    cegger 
    978  1.151    cegger 	if (i == BGE_TIMEOUT * 10) {
    979  1.151    cegger 		aprint_error_dev(sc->bge_dev, "nvram read timed out\n");
    980  1.170   msaitoh 		return 1;
    981  1.151    cegger 	}
    982  1.151    cegger 
    983  1.151    cegger 	/* Get result. */
    984  1.151    cegger 	byte = CSR_READ_4(sc, BGE_NVRAM_RDDATA);
    985  1.151    cegger 
    986  1.151    cegger 	*dest = (bswap32(byte) >> ((addr % 4) * 8)) & 0xFF;
    987  1.151    cegger 
    988  1.151    cegger 	/* Disable access. */
    989  1.151    cegger 	CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access);
    990  1.151    cegger 
    991  1.151    cegger 	/* Unlock. */
    992  1.211   msaitoh 	CSR_WRITE_4_FLUSH(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_CLR1);
    993  1.151    cegger 
    994  1.170   msaitoh 	return 0;
    995  1.151    cegger }
    996  1.151    cegger 
    997  1.151    cegger /*
    998  1.151    cegger  * Read a sequence of bytes from NVRAM.
    999  1.151    cegger  */
   1000  1.151    cegger static int
   1001  1.170   msaitoh bge_read_nvram(struct bge_softc *sc, uint8_t *dest, int off, int cnt)
   1002  1.151    cegger {
   1003  1.203   msaitoh 	int error = 0, i;
   1004  1.170   msaitoh 	uint8_t byte = 0;
   1005  1.151    cegger 
   1006  1.151    cegger 	if (BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5906)
   1007  1.170   msaitoh 		return 1;
   1008  1.151    cegger 
   1009  1.151    cegger 	for (i = 0; i < cnt; i++) {
   1010  1.203   msaitoh 		error = bge_nvram_getbyte(sc, off + i, &byte);
   1011  1.203   msaitoh 		if (error)
   1012  1.151    cegger 			break;
   1013  1.151    cegger 		*(dest + i) = byte;
   1014  1.151    cegger 	}
   1015  1.151    cegger 
   1016  1.362     skrll 	return error ? 1 : 0;
   1017  1.151    cegger }
   1018  1.151    cegger 
   1019    1.1      fvdl /*
   1020    1.1      fvdl  * Read a byte of data stored in the EEPROM at address 'addr.' The
   1021    1.1      fvdl  * BCM570x supports both the traditional bitbang interface and an
   1022    1.1      fvdl  * auto access interface for reading the EEPROM. We use the auto
   1023    1.1      fvdl  * access method.
   1024    1.1      fvdl  */
   1025  1.170   msaitoh static uint8_t
   1026  1.170   msaitoh bge_eeprom_getbyte(struct bge_softc *sc, int addr, uint8_t *dest)
   1027    1.1      fvdl {
   1028    1.1      fvdl 	int i;
   1029  1.170   msaitoh 	uint32_t byte = 0;
   1030    1.1      fvdl 
   1031    1.1      fvdl 	/*
   1032    1.1      fvdl 	 * Enable use of auto EEPROM access so we can avoid
   1033    1.1      fvdl 	 * having to use the bitbang method.
   1034    1.1      fvdl 	 */
   1035  1.341   msaitoh 	BGE_SETBIT_FLUSH(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM);
   1036    1.1      fvdl 
   1037    1.1      fvdl 	/* Reset the EEPROM, load the clock period. */
   1038  1.341   msaitoh 	CSR_WRITE_4_FLUSH(sc, BGE_EE_ADDR,
   1039  1.161   msaitoh 	    BGE_EEADDR_RESET | BGE_EEHALFCLK(BGE_HALFCLK_384SCL));
   1040    1.1      fvdl 	DELAY(20);
   1041    1.1      fvdl 
   1042    1.1      fvdl 	/* Issue the read EEPROM command. */
   1043    1.1      fvdl 	CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr);
   1044    1.1      fvdl 
   1045    1.1      fvdl 	/* Wait for completion */
   1046  1.170   msaitoh 	for (i = 0; i < BGE_TIMEOUT * 10; i++) {
   1047    1.1      fvdl 		DELAY(10);
   1048    1.1      fvdl 		if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE)
   1049    1.1      fvdl 			break;
   1050    1.1      fvdl 	}
   1051    1.1      fvdl 
   1052  1.172   msaitoh 	if (i == BGE_TIMEOUT * 10) {
   1053  1.138     joerg 		aprint_error_dev(sc->bge_dev, "eeprom read timed out\n");
   1054  1.177   msaitoh 		return 1;
   1055    1.1      fvdl 	}
   1056    1.1      fvdl 
   1057    1.1      fvdl 	/* Get result. */
   1058    1.1      fvdl 	byte = CSR_READ_4(sc, BGE_EE_DATA);
   1059    1.1      fvdl 
   1060    1.1      fvdl 	*dest = (byte >> ((addr % 4) * 8)) & 0xFF;
   1061    1.1      fvdl 
   1062  1.170   msaitoh 	return 0;
   1063    1.1      fvdl }
   1064    1.1      fvdl 
   1065    1.1      fvdl /*
   1066    1.1      fvdl  * Read a sequence of bytes from the EEPROM.
   1067    1.1      fvdl  */
   1068  1.104   thorpej static int
   1069  1.126  christos bge_read_eeprom(struct bge_softc *sc, void *destv, int off, int cnt)
   1070    1.1      fvdl {
   1071  1.203   msaitoh 	int error = 0, i;
   1072  1.170   msaitoh 	uint8_t byte = 0;
   1073  1.126  christos 	char *dest = destv;
   1074    1.1      fvdl 
   1075    1.1      fvdl 	for (i = 0; i < cnt; i++) {
   1076  1.203   msaitoh 		error = bge_eeprom_getbyte(sc, off + i, &byte);
   1077  1.203   msaitoh 		if (error)
   1078    1.1      fvdl 			break;
   1079    1.1      fvdl 		*(dest + i) = byte;
   1080    1.1      fvdl 	}
   1081    1.1      fvdl 
   1082  1.362     skrll 	return error ? 1 : 0;
   1083    1.1      fvdl }
   1084    1.1      fvdl 
   1085  1.104   thorpej static int
   1086  1.322   msaitoh bge_miibus_readreg(device_t dev, int phy, int reg, uint16_t *val)
   1087    1.1      fvdl {
   1088  1.354     skrll 	struct bge_softc * const sc = device_private(dev);
   1089  1.322   msaitoh 	uint32_t data;
   1090  1.172   msaitoh 	uint32_t autopoll;
   1091  1.322   msaitoh 	int rv = 0;
   1092    1.1      fvdl 	int i;
   1093    1.1      fvdl 
   1094  1.216   msaitoh 	if (bge_ape_lock(sc, sc->bge_phy_ape_lock) != 0)
   1095  1.322   msaitoh 		return -1;
   1096    1.1      fvdl 
   1097   1.25  jonathan 	/* Reading with autopolling on may trigger PCI errors */
   1098  1.172   msaitoh 	autopoll = CSR_READ_4(sc, BGE_MI_MODE);
   1099  1.172   msaitoh 	if (autopoll & BGE_MIMODE_AUTOPOLL) {
   1100  1.161   msaitoh 		BGE_STS_CLRBIT(sc, BGE_STS_AUTOPOLL);
   1101  1.211   msaitoh 		BGE_CLRBIT_FLUSH(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL);
   1102  1.216   msaitoh 		DELAY(80);
   1103   1.25  jonathan 	}
   1104   1.25  jonathan 
   1105  1.211   msaitoh 	CSR_WRITE_4_FLUSH(sc, BGE_MI_COMM, BGE_MICMD_READ | BGE_MICOMM_BUSY |
   1106  1.172   msaitoh 	    BGE_MIPHY(phy) | BGE_MIREG(reg));
   1107    1.1      fvdl 
   1108    1.1      fvdl 	for (i = 0; i < BGE_TIMEOUT; i++) {
   1109  1.216   msaitoh 		delay(10);
   1110  1.322   msaitoh 		data = CSR_READ_4(sc, BGE_MI_COMM);
   1111  1.322   msaitoh 		if (!(data & BGE_MICOMM_BUSY)) {
   1112  1.216   msaitoh 			DELAY(5);
   1113  1.322   msaitoh 			data = CSR_READ_4(sc, BGE_MI_COMM);
   1114    1.1      fvdl 			break;
   1115  1.216   msaitoh 		}
   1116    1.1      fvdl 	}
   1117    1.1      fvdl 
   1118    1.1      fvdl 	if (i == BGE_TIMEOUT) {
   1119  1.138     joerg 		aprint_error_dev(sc->bge_dev, "PHY read timed out\n");
   1120  1.322   msaitoh 		rv = ETIMEDOUT;
   1121  1.342   msaitoh 	} else if ((data & BGE_MICOMM_READFAIL) != 0) {
   1122  1.342   msaitoh 		/* XXX This error occurs on some devices while attaching. */
   1123  1.342   msaitoh 		aprint_debug_dev(sc->bge_dev, "PHY read I/O error\n");
   1124  1.342   msaitoh 		rv = EIO;
   1125  1.342   msaitoh 	} else
   1126  1.322   msaitoh 		*val = data & BGE_MICOMM_DATA;
   1127    1.1      fvdl 
   1128  1.172   msaitoh 	if (autopoll & BGE_MIMODE_AUTOPOLL) {
   1129  1.161   msaitoh 		BGE_STS_SETBIT(sc, BGE_STS_AUTOPOLL);
   1130  1.211   msaitoh 		BGE_SETBIT_FLUSH(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL);
   1131  1.216   msaitoh 		DELAY(80);
   1132   1.25  jonathan 	}
   1133   1.29    itojun 
   1134  1.216   msaitoh 	bge_ape_unlock(sc, sc->bge_phy_ape_lock);
   1135  1.216   msaitoh 
   1136  1.322   msaitoh 	return rv;
   1137    1.1      fvdl }
   1138    1.1      fvdl 
   1139  1.322   msaitoh static int
   1140  1.322   msaitoh bge_miibus_writereg(device_t dev, int phy, int reg, uint16_t val)
   1141    1.1      fvdl {
   1142  1.354     skrll 	struct bge_softc * const sc = device_private(dev);
   1143  1.342   msaitoh 	uint32_t data, autopoll;
   1144  1.342   msaitoh 	int rv = 0;
   1145   1.29    itojun 	int i;
   1146    1.1      fvdl 
   1147  1.278   msaitoh 	if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906 &&
   1148  1.321   msaitoh 	    (reg == MII_GTCR || reg == BRGPHY_MII_AUXCTL))
   1149  1.322   msaitoh 		return 0;
   1150  1.151    cegger 
   1151  1.278   msaitoh 	if (bge_ape_lock(sc, sc->bge_phy_ape_lock) != 0)
   1152  1.322   msaitoh 		return -1;
   1153  1.151    cegger 
   1154  1.161   msaitoh 	/* Reading with autopolling on may trigger PCI errors */
   1155  1.172   msaitoh 	autopoll = CSR_READ_4(sc, BGE_MI_MODE);
   1156  1.172   msaitoh 	if (autopoll & BGE_MIMODE_AUTOPOLL) {
   1157  1.161   msaitoh 		BGE_STS_CLRBIT(sc, BGE_STS_AUTOPOLL);
   1158  1.211   msaitoh 		BGE_CLRBIT_FLUSH(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL);
   1159  1.216   msaitoh 		DELAY(80);
   1160   1.25  jonathan 	}
   1161   1.29    itojun 
   1162  1.211   msaitoh 	CSR_WRITE_4_FLUSH(sc, BGE_MI_COMM, BGE_MICMD_WRITE | BGE_MICOMM_BUSY |
   1163  1.177   msaitoh 	    BGE_MIPHY(phy) | BGE_MIREG(reg) | val);
   1164    1.1      fvdl 
   1165    1.1      fvdl 	for (i = 0; i < BGE_TIMEOUT; i++) {
   1166  1.151    cegger 		delay(10);
   1167  1.342   msaitoh 		data = CSR_READ_4(sc, BGE_MI_COMM);
   1168  1.342   msaitoh 		if (!(data & BGE_MICOMM_BUSY)) {
   1169  1.151    cegger 			delay(5);
   1170  1.342   msaitoh 			data = CSR_READ_4(sc, BGE_MI_COMM);
   1171    1.1      fvdl 			break;
   1172  1.151    cegger 		}
   1173    1.1      fvdl 	}
   1174    1.1      fvdl 
   1175  1.342   msaitoh 	if (i == BGE_TIMEOUT) {
   1176  1.342   msaitoh 		aprint_error_dev(sc->bge_dev, "PHY write timed out\n");
   1177  1.342   msaitoh 		rv = ETIMEDOUT;
   1178  1.342   msaitoh 	} else if ((data & BGE_MICOMM_READFAIL) != 0) {
   1179  1.342   msaitoh 		aprint_error_dev(sc->bge_dev, "PHY write I/O error\n");
   1180  1.342   msaitoh 		rv = EIO;
   1181  1.342   msaitoh 	}
   1182  1.342   msaitoh 
   1183  1.172   msaitoh 	if (autopoll & BGE_MIMODE_AUTOPOLL) {
   1184  1.161   msaitoh 		BGE_STS_SETBIT(sc, BGE_STS_AUTOPOLL);
   1185  1.211   msaitoh 		BGE_SETBIT_FLUSH(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL);
   1186  1.216   msaitoh 		delay(80);
   1187   1.25  jonathan 	}
   1188   1.29    itojun 
   1189  1.216   msaitoh 	bge_ape_unlock(sc, sc->bge_phy_ape_lock);
   1190  1.216   msaitoh 
   1191  1.342   msaitoh 	return rv;
   1192    1.1      fvdl }
   1193    1.1      fvdl 
   1194  1.104   thorpej static void
   1195  1.201      matt bge_miibus_statchg(struct ifnet *ifp)
   1196    1.1      fvdl {
   1197  1.354     skrll 	struct bge_softc * const sc = ifp->if_softc;
   1198    1.1      fvdl 	struct mii_data *mii = &sc->bge_mii;
   1199  1.216   msaitoh 	uint32_t mac_mode, rx_mode, tx_mode;
   1200    1.1      fvdl 
   1201   1.69   thorpej 	/*
   1202   1.69   thorpej 	 * Get flow control negotiation result.
   1203   1.69   thorpej 	 */
   1204   1.69   thorpej 	if (IFM_SUBTYPE(mii->mii_media.ifm_cur->ifm_media) == IFM_AUTO &&
   1205  1.256   msaitoh 	    (mii->mii_media_active & IFM_ETH_FMASK) != sc->bge_flowflags)
   1206   1.69   thorpej 		sc->bge_flowflags = mii->mii_media_active & IFM_ETH_FMASK;
   1207  1.256   msaitoh 
   1208  1.256   msaitoh 	if (!BGE_STS_BIT(sc, BGE_STS_LINK) &&
   1209  1.256   msaitoh 	    mii->mii_media_status & IFM_ACTIVE &&
   1210  1.256   msaitoh 	    IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE)
   1211  1.256   msaitoh 		BGE_STS_SETBIT(sc, BGE_STS_LINK);
   1212  1.256   msaitoh 	else if (BGE_STS_BIT(sc, BGE_STS_LINK) &&
   1213  1.256   msaitoh 	    (!(mii->mii_media_status & IFM_ACTIVE) ||
   1214  1.256   msaitoh 	    IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE))
   1215  1.256   msaitoh 		BGE_STS_CLRBIT(sc, BGE_STS_LINK);
   1216  1.256   msaitoh 
   1217  1.256   msaitoh 	if (!BGE_STS_BIT(sc, BGE_STS_LINK))
   1218  1.256   msaitoh 		return;
   1219   1.69   thorpej 
   1220  1.216   msaitoh 	/* Set the port mode (MII/GMII) to match the link speed. */
   1221  1.216   msaitoh 	mac_mode = CSR_READ_4(sc, BGE_MAC_MODE) &
   1222  1.216   msaitoh 	    ~(BGE_MACMODE_PORTMODE | BGE_MACMODE_HALF_DUPLEX);
   1223  1.216   msaitoh 	tx_mode = CSR_READ_4(sc, BGE_TX_MODE);
   1224  1.216   msaitoh 	rx_mode = CSR_READ_4(sc, BGE_RX_MODE);
   1225  1.161   msaitoh 	if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T ||
   1226  1.161   msaitoh 	    IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX)
   1227  1.216   msaitoh 		mac_mode |= BGE_PORTMODE_GMII;
   1228  1.161   msaitoh 	else
   1229  1.216   msaitoh 		mac_mode |= BGE_PORTMODE_MII;
   1230  1.216   msaitoh 
   1231  1.216   msaitoh 	tx_mode &= ~BGE_TXMODE_FLOWCTL_ENABLE;
   1232  1.216   msaitoh 	rx_mode &= ~BGE_RXMODE_FLOWCTL_ENABLE;
   1233  1.256   msaitoh 	if ((mii->mii_media_active & IFM_FDX) != 0) {
   1234  1.216   msaitoh 		if (sc->bge_flowflags & IFM_ETH_TXPAUSE)
   1235  1.216   msaitoh 			tx_mode |= BGE_TXMODE_FLOWCTL_ENABLE;
   1236  1.216   msaitoh 		if (sc->bge_flowflags & IFM_ETH_RXPAUSE)
   1237  1.216   msaitoh 			rx_mode |= BGE_RXMODE_FLOWCTL_ENABLE;
   1238  1.216   msaitoh 	} else
   1239  1.216   msaitoh 		mac_mode |= BGE_MACMODE_HALF_DUPLEX;
   1240    1.1      fvdl 
   1241  1.216   msaitoh 	CSR_WRITE_4_FLUSH(sc, BGE_MAC_MODE, mac_mode);
   1242  1.211   msaitoh 	DELAY(40);
   1243  1.216   msaitoh 	CSR_WRITE_4(sc, BGE_TX_MODE, tx_mode);
   1244  1.216   msaitoh 	CSR_WRITE_4(sc, BGE_RX_MODE, rx_mode);
   1245    1.1      fvdl }
   1246    1.1      fvdl 
   1247    1.1      fvdl /*
   1248   1.63  jonathan  * Update rx threshold levels to values in a particular slot
   1249   1.63  jonathan  * of the interrupt-mitigation table bge_rx_threshes.
   1250   1.63  jonathan  */
   1251  1.104   thorpej static void
   1252   1.63  jonathan bge_set_thresh(struct ifnet *ifp, int lvl)
   1253   1.63  jonathan {
   1254  1.354     skrll 	struct bge_softc * const sc = ifp->if_softc;
   1255   1.63  jonathan 
   1256  1.357     skrll 	/*
   1257  1.357     skrll 	 * For now, just save the new Rx-intr thresholds and record
   1258   1.63  jonathan 	 * that a threshold update is pending.  Updating the hardware
   1259   1.63  jonathan 	 * registers here (even at splhigh()) is observed to
   1260  1.352    andvar 	 * occasionally cause glitches where Rx-interrupts are not
   1261   1.68    keihan 	 * honoured for up to 10 seconds. jonathan (at) NetBSD.org, 2003-04-05
   1262   1.63  jonathan 	 */
   1263  1.375     skrll 	mutex_enter(sc->sc_core_lock);
   1264   1.63  jonathan 	sc->bge_rx_coal_ticks = bge_rx_threshes[lvl].rx_ticks;
   1265   1.63  jonathan 	sc->bge_rx_max_coal_bds = bge_rx_threshes[lvl].rx_max_bds;
   1266  1.384     skrll 	sc->bge_pending_rxintr_change = true;
   1267  1.375     skrll 	mutex_exit(sc->sc_core_lock);
   1268   1.63  jonathan }
   1269   1.63  jonathan 
   1270   1.63  jonathan 
   1271   1.63  jonathan /*
   1272   1.63  jonathan  * Update Rx thresholds of all bge devices
   1273   1.63  jonathan  */
   1274  1.104   thorpej static void
   1275   1.63  jonathan bge_update_all_threshes(int lvl)
   1276   1.63  jonathan {
   1277  1.360     skrll 	const char * const namebuf = "bge";
   1278  1.360     skrll 	const size_t namelen = strlen(namebuf);
   1279   1.63  jonathan 	struct ifnet *ifp;
   1280   1.63  jonathan 
   1281   1.63  jonathan 	if (lvl < 0)
   1282   1.63  jonathan 		lvl = 0;
   1283  1.170   msaitoh 	else if (lvl >= NBGE_RX_THRESH)
   1284   1.63  jonathan 		lvl = NBGE_RX_THRESH - 1;
   1285   1.87     perry 
   1286   1.63  jonathan 	/*
   1287   1.63  jonathan 	 * Now search all the interfaces for this name/number
   1288   1.63  jonathan 	 */
   1289  1.360     skrll 	int s = pserialize_read_enter();
   1290  1.296     ozaki 	IFNET_READER_FOREACH(ifp) {
   1291   1.67  jonathan 		if (strncmp(ifp->if_xname, namebuf, namelen) != 0)
   1292  1.367     skrll 			continue;
   1293   1.63  jonathan 		/* We got a match: update if doing auto-threshold-tuning */
   1294   1.63  jonathan 		if (bge_auto_thresh)
   1295   1.67  jonathan 			bge_set_thresh(ifp, lvl);
   1296   1.63  jonathan 	}
   1297  1.296     ozaki 	pserialize_read_exit(s);
   1298   1.63  jonathan }
   1299   1.63  jonathan 
   1300   1.63  jonathan /*
   1301    1.1      fvdl  * Handle events that have triggered interrupts.
   1302    1.1      fvdl  */
   1303  1.104   thorpej static void
   1304  1.116  christos bge_handle_events(struct bge_softc *sc)
   1305    1.1      fvdl {
   1306    1.1      fvdl 
   1307    1.1      fvdl 	return;
   1308    1.1      fvdl }
   1309    1.1      fvdl 
   1310    1.1      fvdl /*
   1311    1.1      fvdl  * Memory management for jumbo frames.
   1312    1.1      fvdl  */
   1313    1.1      fvdl 
   1314  1.104   thorpej static int
   1315  1.104   thorpej bge_alloc_jumbo_mem(struct bge_softc *sc)
   1316    1.1      fvdl {
   1317  1.126  christos 	char *ptr, *kva;
   1318  1.375     skrll 	int i, rseg, state, error;
   1319  1.375     skrll 	struct bge_jpool_entry *entry;
   1320    1.1      fvdl 
   1321    1.1      fvdl 	state = error = 0;
   1322    1.1      fvdl 
   1323    1.1      fvdl 	/* Grab a big chunk o' storage. */
   1324    1.1      fvdl 	if (bus_dmamem_alloc(sc->bge_dmatag, BGE_JMEM, PAGE_SIZE, 0,
   1325  1.377     skrll 	    &sc->bge_cdata.bge_rx_jumbo_seg, 1, &rseg, BUS_DMA_WAITOK)) {
   1326  1.138     joerg 		aprint_error_dev(sc->bge_dev, "can't alloc rx buffers\n");
   1327    1.1      fvdl 		return ENOBUFS;
   1328    1.1      fvdl 	}
   1329    1.1      fvdl 
   1330    1.1      fvdl 	state = 1;
   1331  1.373     skrll 	if (bus_dmamem_map(sc->bge_dmatag, &sc->bge_cdata.bge_rx_jumbo_seg,
   1332  1.377     skrll 	    rseg, BGE_JMEM, (void **)&kva, BUS_DMA_WAITOK)) {
   1333  1.138     joerg 		aprint_error_dev(sc->bge_dev,
   1334  1.138     joerg 		    "can't map DMA buffers (%d bytes)\n", (int)BGE_JMEM);
   1335    1.1      fvdl 		error = ENOBUFS;
   1336    1.1      fvdl 		goto out;
   1337    1.1      fvdl 	}
   1338    1.1      fvdl 
   1339    1.1      fvdl 	state = 2;
   1340    1.1      fvdl 	if (bus_dmamap_create(sc->bge_dmatag, BGE_JMEM, 1, BGE_JMEM, 0,
   1341  1.377     skrll 	    BUS_DMA_WAITOK, &sc->bge_cdata.bge_rx_jumbo_map)) {
   1342  1.138     joerg 		aprint_error_dev(sc->bge_dev, "can't create DMA map\n");
   1343    1.1      fvdl 		error = ENOBUFS;
   1344    1.1      fvdl 		goto out;
   1345    1.1      fvdl 	}
   1346    1.1      fvdl 
   1347    1.1      fvdl 	state = 3;
   1348    1.1      fvdl 	if (bus_dmamap_load(sc->bge_dmatag, sc->bge_cdata.bge_rx_jumbo_map,
   1349  1.377     skrll 	    kva, BGE_JMEM, NULL, BUS_DMA_WAITOK)) {
   1350  1.138     joerg 		aprint_error_dev(sc->bge_dev, "can't load DMA map\n");
   1351    1.1      fvdl 		error = ENOBUFS;
   1352    1.1      fvdl 		goto out;
   1353    1.1      fvdl 	}
   1354    1.1      fvdl 
   1355    1.1      fvdl 	state = 4;
   1356  1.126  christos 	sc->bge_cdata.bge_jumbo_buf = (void *)kva;
   1357   1.89  christos 	DPRINTFN(1,("bge_jumbo_buf = %p\n", sc->bge_cdata.bge_jumbo_buf));
   1358    1.1      fvdl 
   1359    1.1      fvdl 	SLIST_INIT(&sc->bge_jfree_listhead);
   1360    1.1      fvdl 	SLIST_INIT(&sc->bge_jinuse_listhead);
   1361    1.1      fvdl 
   1362    1.1      fvdl 	/*
   1363    1.1      fvdl 	 * Now divide it up into 9K pieces and save the addresses
   1364    1.1      fvdl 	 * in an array.
   1365    1.1      fvdl 	 */
   1366    1.1      fvdl 	ptr = sc->bge_cdata.bge_jumbo_buf;
   1367    1.1      fvdl 	for (i = 0; i < BGE_JSLOTS; i++) {
   1368    1.1      fvdl 		sc->bge_cdata.bge_jslots[i] = ptr;
   1369    1.1      fvdl 		ptr += BGE_JLEN;
   1370  1.366     skrll 		entry = kmem_alloc(sizeof(*entry), KM_SLEEP);
   1371    1.1      fvdl 		entry->slot = i;
   1372    1.1      fvdl 		SLIST_INSERT_HEAD(&sc->bge_jfree_listhead,
   1373    1.1      fvdl 				 entry, jpool_entries);
   1374    1.1      fvdl 	}
   1375    1.1      fvdl out:
   1376    1.1      fvdl 	if (error != 0) {
   1377    1.1      fvdl 		switch (state) {
   1378    1.1      fvdl 		case 4:
   1379    1.1      fvdl 			bus_dmamap_unload(sc->bge_dmatag,
   1380    1.1      fvdl 			    sc->bge_cdata.bge_rx_jumbo_map);
   1381  1.323       mrg 			/* FALLTHROUGH */
   1382    1.1      fvdl 		case 3:
   1383    1.1      fvdl 			bus_dmamap_destroy(sc->bge_dmatag,
   1384    1.1      fvdl 			    sc->bge_cdata.bge_rx_jumbo_map);
   1385  1.323       mrg 			/* FALLTHROUGH */
   1386    1.1      fvdl 		case 2:
   1387    1.1      fvdl 			bus_dmamem_unmap(sc->bge_dmatag, kva, BGE_JMEM);
   1388  1.323       mrg 			/* FALLTHROUGH */
   1389    1.1      fvdl 		case 1:
   1390  1.373     skrll 			bus_dmamem_free(sc->bge_dmatag,
   1391  1.373     skrll 			    &sc->bge_cdata.bge_rx_jumbo_seg, rseg);
   1392    1.1      fvdl 			break;
   1393    1.1      fvdl 		default:
   1394    1.1      fvdl 			break;
   1395    1.1      fvdl 		}
   1396    1.1      fvdl 	}
   1397    1.1      fvdl 
   1398    1.1      fvdl 	return error;
   1399    1.1      fvdl }
   1400    1.1      fvdl 
   1401  1.373     skrll static void
   1402  1.373     skrll bge_free_jumbo_mem(struct bge_softc *sc)
   1403  1.373     skrll {
   1404  1.373     skrll 	struct bge_jpool_entry *entry, *tmp;
   1405  1.373     skrll 
   1406  1.373     skrll 	KASSERT(SLIST_EMPTY(&sc->bge_jinuse_listhead));
   1407  1.373     skrll 
   1408  1.373     skrll 	SLIST_FOREACH_SAFE(entry, &sc->bge_jfree_listhead, jpool_entries, tmp) {
   1409  1.373     skrll 		kmem_free(entry, sizeof(*entry));
   1410  1.373     skrll 	}
   1411  1.373     skrll 
   1412  1.373     skrll 	bus_dmamap_unload(sc->bge_dmatag, sc->bge_cdata.bge_rx_jumbo_map);
   1413  1.373     skrll 
   1414  1.373     skrll 	bus_dmamap_destroy(sc->bge_dmatag, sc->bge_cdata.bge_rx_jumbo_map);
   1415  1.373     skrll 
   1416  1.373     skrll 	bus_dmamem_unmap(sc->bge_dmatag, sc->bge_cdata.bge_jumbo_buf, BGE_JMEM);
   1417  1.373     skrll 
   1418  1.373     skrll 	bus_dmamem_free(sc->bge_dmatag, &sc->bge_cdata.bge_rx_jumbo_seg, 1);
   1419  1.373     skrll }
   1420  1.373     skrll 
   1421    1.1      fvdl /*
   1422    1.1      fvdl  * Allocate a jumbo buffer.
   1423    1.1      fvdl  */
   1424  1.104   thorpej static void *
   1425  1.104   thorpej bge_jalloc(struct bge_softc *sc)
   1426    1.1      fvdl {
   1427  1.330   msaitoh 	struct bge_jpool_entry	 *entry;
   1428    1.1      fvdl 
   1429    1.1      fvdl 	entry = SLIST_FIRST(&sc->bge_jfree_listhead);
   1430    1.1      fvdl 
   1431    1.1      fvdl 	if (entry == NULL) {
   1432  1.138     joerg 		aprint_error_dev(sc->bge_dev, "no free jumbo buffers\n");
   1433  1.170   msaitoh 		return NULL;
   1434    1.1      fvdl 	}
   1435    1.1      fvdl 
   1436    1.1      fvdl 	SLIST_REMOVE_HEAD(&sc->bge_jfree_listhead, jpool_entries);
   1437    1.1      fvdl 	SLIST_INSERT_HEAD(&sc->bge_jinuse_listhead, entry, jpool_entries);
   1438  1.362     skrll 	return sc->bge_cdata.bge_jslots[entry->slot];
   1439    1.1      fvdl }
   1440    1.1      fvdl 
   1441    1.1      fvdl /*
   1442    1.1      fvdl  * Release a jumbo buffer.
   1443    1.1      fvdl  */
   1444  1.104   thorpej static void
   1445  1.126  christos bge_jfree(struct mbuf *m, void *buf, size_t size, void *arg)
   1446    1.1      fvdl {
   1447    1.1      fvdl 	struct bge_jpool_entry *entry;
   1448  1.354     skrll 	struct bge_softc * const sc = arg;
   1449    1.1      fvdl 
   1450    1.1      fvdl 	if (sc == NULL)
   1451    1.1      fvdl 		panic("bge_jfree: can't find softc pointer!");
   1452    1.1      fvdl 
   1453    1.1      fvdl 	/* calculate the slot this buffer belongs to */
   1454  1.371     skrll 	int i = ((char *)buf - (char *)sc->bge_cdata.bge_jumbo_buf) / BGE_JLEN;
   1455    1.1      fvdl 
   1456  1.371     skrll 	if (i < 0 || i >= BGE_JSLOTS)
   1457    1.1      fvdl 		panic("bge_jfree: asked to free buffer that we don't manage!");
   1458    1.1      fvdl 
   1459  1.375     skrll 	mutex_enter(sc->sc_core_lock);
   1460    1.1      fvdl 	entry = SLIST_FIRST(&sc->bge_jinuse_listhead);
   1461    1.1      fvdl 	if (entry == NULL)
   1462    1.1      fvdl 		panic("bge_jfree: buffer not in use!");
   1463    1.1      fvdl 	entry->slot = i;
   1464    1.1      fvdl 	SLIST_REMOVE_HEAD(&sc->bge_jinuse_listhead, jpool_entries);
   1465    1.1      fvdl 	SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, entry, jpool_entries);
   1466  1.375     skrll 	mutex_exit(sc->sc_core_lock);
   1467    1.1      fvdl 
   1468    1.1      fvdl 	if (__predict_true(m != NULL))
   1469  1.330   msaitoh 		pool_cache_put(mb_cache, m);
   1470    1.1      fvdl }
   1471    1.1      fvdl 
   1472    1.1      fvdl 
   1473    1.1      fvdl /*
   1474  1.184     njoly  * Initialize a standard receive ring descriptor.
   1475    1.1      fvdl  */
   1476  1.104   thorpej static int
   1477  1.376     skrll bge_newbuf_std(struct bge_softc *sc, int i)
   1478    1.1      fvdl {
   1479  1.376     skrll 	const bus_dmamap_t dmamap = sc->bge_cdata.bge_rx_std_map[i];
   1480  1.376     skrll 	struct mbuf *m;
   1481    1.1      fvdl 
   1482  1.376     skrll 	MGETHDR(m, M_DONTWAIT, MT_DATA);
   1483  1.376     skrll 	if (m == NULL)
   1484  1.376     skrll 		return ENOBUFS;
   1485  1.320    bouyer 
   1486  1.376     skrll 	MCLGET(m, M_DONTWAIT);
   1487  1.376     skrll 	if (!(m->m_flags & M_EXT)) {
   1488  1.376     skrll 		m_freem(m);
   1489  1.376     skrll 		return ENOBUFS;
   1490    1.1      fvdl 	}
   1491  1.376     skrll 	m->m_len = m->m_pkthdr.len = MCLBYTES;
   1492    1.1      fvdl 
   1493  1.261   msaitoh 	if (!(sc->bge_flags & BGEF_RX_ALIGNBUG))
   1494  1.376     skrll 	    m_adj(m, ETHER_ALIGN);
   1495  1.376     skrll 	if (bus_dmamap_load_mbuf(sc->bge_dmatag, dmamap, m,
   1496  1.331   msaitoh 	    BUS_DMA_READ | BUS_DMA_NOWAIT)) {
   1497  1.376     skrll 		m_freem(m);
   1498  1.170   msaitoh 		return ENOBUFS;
   1499  1.283  christos 	}
   1500  1.178   msaitoh 	bus_dmamap_sync(sc->bge_dmatag, dmamap, 0, dmamap->dm_mapsize,
   1501  1.124    bouyer 	    BUS_DMASYNC_PREREAD);
   1502  1.376     skrll 	sc->bge_cdata.bge_rx_std_chain[i] = m;
   1503    1.1      fvdl 
   1504  1.376     skrll 	bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map,
   1505  1.376     skrll 	    offsetof(struct bge_ring_data, bge_rx_std_ring) +
   1506  1.376     skrll 		i * sizeof(struct bge_rx_bd),
   1507  1.376     skrll 	    sizeof(struct bge_rx_bd),
   1508  1.376     skrll 	    BUS_DMASYNC_POSTWRITE);
   1509  1.376     skrll 
   1510  1.376     skrll 	struct bge_rx_bd * const r = &sc->bge_rdata->bge_rx_std_ring[i];
   1511  1.172   msaitoh 	BGE_HOSTADDR(r->bge_addr, dmamap->dm_segs[0].ds_addr);
   1512    1.1      fvdl 	r->bge_flags = BGE_RXBDFLAG_END;
   1513  1.376     skrll 	r->bge_len = m->m_len;
   1514    1.1      fvdl 	r->bge_idx = i;
   1515    1.1      fvdl 
   1516    1.1      fvdl 	bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map,
   1517    1.1      fvdl 	    offsetof(struct bge_ring_data, bge_rx_std_ring) +
   1518  1.364     skrll 		i * sizeof(struct bge_rx_bd),
   1519  1.364     skrll 	    sizeof(struct bge_rx_bd),
   1520  1.376     skrll 	    BUS_DMASYNC_PREWRITE);
   1521  1.376     skrll 
   1522  1.376     skrll 	sc->bge_std_cnt++;
   1523    1.1      fvdl 
   1524  1.170   msaitoh 	return 0;
   1525    1.1      fvdl }
   1526    1.1      fvdl 
   1527    1.1      fvdl /*
   1528    1.1      fvdl  * Initialize a jumbo receive ring descriptor. This allocates
   1529    1.1      fvdl  * a jumbo buffer from the pool managed internally by the driver.
   1530    1.1      fvdl  */
   1531  1.104   thorpej static int
   1532  1.104   thorpej bge_newbuf_jumbo(struct bge_softc *sc, int i, struct mbuf *m)
   1533    1.1      fvdl {
   1534    1.1      fvdl 	struct mbuf *m_new = NULL;
   1535    1.1      fvdl 	struct bge_rx_bd *r;
   1536  1.126  christos 	void *buf = NULL;
   1537    1.1      fvdl 
   1538    1.1      fvdl 	if (m == NULL) {
   1539    1.1      fvdl 
   1540    1.1      fvdl 		/* Allocate the mbuf. */
   1541    1.1      fvdl 		MGETHDR(m_new, M_DONTWAIT, MT_DATA);
   1542  1.158   msaitoh 		if (m_new == NULL)
   1543  1.170   msaitoh 			return ENOBUFS;
   1544    1.1      fvdl 
   1545    1.1      fvdl 		/* Allocate the jumbo buffer */
   1546    1.1      fvdl 		buf = bge_jalloc(sc);
   1547    1.1      fvdl 		if (buf == NULL) {
   1548    1.1      fvdl 			m_freem(m_new);
   1549  1.138     joerg 			aprint_error_dev(sc->bge_dev,
   1550  1.138     joerg 			    "jumbo allocation failed -- packet dropped!\n");
   1551  1.170   msaitoh 			return ENOBUFS;
   1552    1.1      fvdl 		}
   1553    1.1      fvdl 
   1554    1.1      fvdl 		/* Attach the buffer to the mbuf. */
   1555    1.1      fvdl 		m_new->m_len = m_new->m_pkthdr.len = BGE_JUMBO_FRAMELEN;
   1556    1.1      fvdl 		MEXTADD(m_new, buf, BGE_JUMBO_FRAMELEN, M_DEVBUF,
   1557    1.1      fvdl 		    bge_jfree, sc);
   1558   1.74      yamt 		m_new->m_flags |= M_EXT_RW;
   1559    1.1      fvdl 	} else {
   1560    1.1      fvdl 		m_new = m;
   1561  1.124    bouyer 		buf = m_new->m_data = m_new->m_ext.ext_buf;
   1562    1.1      fvdl 		m_new->m_ext.ext_size = BGE_JUMBO_FRAMELEN;
   1563    1.1      fvdl 	}
   1564  1.261   msaitoh 	if (!(sc->bge_flags & BGEF_RX_ALIGNBUG))
   1565  1.125    bouyer 	    m_adj(m_new, ETHER_ALIGN);
   1566  1.124    bouyer 	bus_dmamap_sync(sc->bge_dmatag, sc->bge_cdata.bge_rx_jumbo_map,
   1567  1.332   msaitoh 	    mtod(m_new, char *) - (char *)sc->bge_cdata.bge_jumbo_buf,
   1568  1.332   msaitoh 	    BGE_JLEN, BUS_DMASYNC_PREREAD);
   1569  1.375     skrll 
   1570    1.1      fvdl 	/* Set up the descriptor. */
   1571    1.1      fvdl 	r = &sc->bge_rdata->bge_rx_jumbo_ring[i];
   1572    1.1      fvdl 	sc->bge_cdata.bge_rx_jumbo_chain[i] = m_new;
   1573  1.172   msaitoh 	BGE_HOSTADDR(r->bge_addr, BGE_JUMBO_DMA_ADDR(sc, m_new));
   1574  1.331   msaitoh 	r->bge_flags = BGE_RXBDFLAG_END | BGE_RXBDFLAG_JUMBO_RING;
   1575    1.1      fvdl 	r->bge_len = m_new->m_len;
   1576    1.1      fvdl 	r->bge_idx = i;
   1577    1.1      fvdl 
   1578    1.1      fvdl 	bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map,
   1579    1.1      fvdl 	    offsetof(struct bge_ring_data, bge_rx_jumbo_ring) +
   1580  1.364     skrll 		i * sizeof(struct bge_rx_bd),
   1581  1.364     skrll 	    sizeof(struct bge_rx_bd),
   1582  1.331   msaitoh 	    BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
   1583    1.1      fvdl 
   1584  1.170   msaitoh 	return 0;
   1585    1.1      fvdl }
   1586    1.1      fvdl 
   1587  1.104   thorpej static int
   1588  1.104   thorpej bge_init_rx_ring_std(struct bge_softc *sc)
   1589    1.1      fvdl {
   1590  1.376     skrll 	bus_dmamap_t dmamap;
   1591  1.376     skrll 	int error = 0;
   1592  1.376     skrll 	u_int i;
   1593    1.1      fvdl 
   1594  1.261   msaitoh 	if (sc->bge_flags & BGEF_RXRING_VALID)
   1595    1.1      fvdl 		return 0;
   1596    1.1      fvdl 
   1597  1.376     skrll 	for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
   1598  1.376     skrll 		error = bus_dmamap_create(sc->bge_dmatag, MCLBYTES, 1,
   1599  1.376     skrll 		    MCLBYTES, 0, BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, &dmamap);
   1600  1.376     skrll 		if (error)
   1601  1.376     skrll 			goto uncreate;
   1602  1.376     skrll 
   1603  1.376     skrll 		sc->bge_cdata.bge_rx_std_map[i] = dmamap;
   1604  1.376     skrll 		memset(&sc->bge_rdata->bge_rx_std_ring[i], 0,
   1605  1.376     skrll 		    sizeof(struct bge_rx_bd));
   1606    1.1      fvdl 	}
   1607    1.1      fvdl 
   1608    1.1      fvdl 	sc->bge_std = i - 1;
   1609  1.376     skrll 	sc->bge_std_cnt = 0;
   1610  1.376     skrll 	bge_fill_rx_ring_std(sc);
   1611    1.1      fvdl 
   1612  1.261   msaitoh 	sc->bge_flags |= BGEF_RXRING_VALID;
   1613    1.1      fvdl 
   1614  1.170   msaitoh 	return 0;
   1615  1.376     skrll 
   1616  1.376     skrll uncreate:
   1617  1.376     skrll 	while (--i) {
   1618  1.376     skrll 		bus_dmamap_destroy(sc->bge_dmatag,
   1619  1.376     skrll 		    sc->bge_cdata.bge_rx_std_map[i]);
   1620  1.376     skrll 	}
   1621  1.376     skrll 	return error;
   1622    1.1      fvdl }
   1623    1.1      fvdl 
   1624  1.104   thorpej static void
   1625  1.376     skrll bge_fill_rx_ring_std(struct bge_softc *sc)
   1626  1.376     skrll {
   1627  1.376     skrll 	int i = sc->bge_std;
   1628  1.376     skrll 	bool post = false;
   1629  1.376     skrll 
   1630  1.376     skrll 	while (sc->bge_std_cnt < BGE_STD_RX_RING_CNT) {
   1631  1.376     skrll 		BGE_INC(i, BGE_STD_RX_RING_CNT);
   1632  1.376     skrll 
   1633  1.376     skrll 		if (bge_newbuf_std(sc, i) != 0)
   1634  1.376     skrll 			break;
   1635  1.376     skrll 
   1636  1.376     skrll 		sc->bge_std = i;
   1637  1.376     skrll 		post = true;
   1638  1.376     skrll 	}
   1639  1.376     skrll 
   1640  1.376     skrll 	if (post)
   1641  1.376     skrll 		bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std);
   1642  1.376     skrll }
   1643  1.376     skrll 
   1644  1.376     skrll 
   1645  1.376     skrll static void
   1646  1.376     skrll bge_free_rx_ring_std(struct bge_softc *sc)
   1647    1.1      fvdl {
   1648    1.1      fvdl 
   1649  1.261   msaitoh 	if (!(sc->bge_flags & BGEF_RXRING_VALID))
   1650    1.1      fvdl 		return;
   1651    1.1      fvdl 
   1652  1.376     skrll 	for (u_int i = 0; i < BGE_STD_RX_RING_CNT; i++) {
   1653  1.376     skrll 		const bus_dmamap_t dmap = sc->bge_cdata.bge_rx_std_map[i];
   1654  1.376     skrll 		struct mbuf * const m = sc->bge_cdata.bge_rx_std_chain[i];
   1655  1.376     skrll 		if (m != NULL) {
   1656  1.376     skrll 			bus_dmamap_sync(sc->bge_dmatag, dmap, 0,
   1657  1.376     skrll 			    dmap->dm_mapsize, BUS_DMASYNC_POSTREAD);
   1658  1.376     skrll 			bus_dmamap_unload(sc->bge_dmatag, dmap);
   1659  1.376     skrll 			m_freem(m);
   1660    1.1      fvdl 			sc->bge_cdata.bge_rx_std_chain[i] = NULL;
   1661    1.1      fvdl 		}
   1662  1.376     skrll 		bus_dmamap_destroy(sc->bge_dmatag,
   1663  1.376     skrll 		    sc->bge_cdata.bge_rx_std_map[i]);
   1664  1.376     skrll 		sc->bge_cdata.bge_rx_std_map[i] = NULL;
   1665    1.1      fvdl 		memset((char *)&sc->bge_rdata->bge_rx_std_ring[i], 0,
   1666    1.1      fvdl 		    sizeof(struct bge_rx_bd));
   1667    1.1      fvdl 	}
   1668    1.1      fvdl 
   1669  1.261   msaitoh 	sc->bge_flags &= ~BGEF_RXRING_VALID;
   1670    1.1      fvdl }
   1671    1.1      fvdl 
   1672  1.104   thorpej static int
   1673  1.104   thorpej bge_init_rx_ring_jumbo(struct bge_softc *sc)
   1674    1.1      fvdl {
   1675    1.1      fvdl 	int i;
   1676   1.34  jonathan 	volatile struct bge_rcb *rcb;
   1677    1.1      fvdl 
   1678  1.261   msaitoh 	if (sc->bge_flags & BGEF_JUMBO_RXRING_VALID)
   1679   1.59    martin 		return 0;
   1680   1.59    martin 
   1681    1.1      fvdl 	for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
   1682    1.1      fvdl 		if (bge_newbuf_jumbo(sc, i, NULL) == ENOBUFS)
   1683  1.170   msaitoh 			return ENOBUFS;
   1684  1.205   msaitoh 	}
   1685    1.1      fvdl 
   1686    1.1      fvdl 	sc->bge_jumbo = i - 1;
   1687  1.261   msaitoh 	sc->bge_flags |= BGEF_JUMBO_RXRING_VALID;
   1688    1.1      fvdl 
   1689    1.1      fvdl 	rcb = &sc->bge_rdata->bge_info.bge_jumbo_rx_rcb;
   1690   1.34  jonathan 	rcb->bge_maxlen_flags = 0;
   1691   1.34  jonathan 	CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags);
   1692    1.1      fvdl 
   1693  1.151    cegger 	bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo);
   1694    1.1      fvdl 
   1695  1.170   msaitoh 	return 0;
   1696    1.1      fvdl }
   1697    1.1      fvdl 
   1698  1.104   thorpej static void
   1699  1.104   thorpej bge_free_rx_ring_jumbo(struct bge_softc *sc)
   1700    1.1      fvdl {
   1701    1.1      fvdl 	int i;
   1702    1.1      fvdl 
   1703  1.261   msaitoh 	if (!(sc->bge_flags & BGEF_JUMBO_RXRING_VALID))
   1704    1.1      fvdl 		return;
   1705    1.1      fvdl 
   1706    1.1      fvdl 	for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
   1707    1.1      fvdl 		if (sc->bge_cdata.bge_rx_jumbo_chain[i] != NULL) {
   1708    1.1      fvdl 			m_freem(sc->bge_cdata.bge_rx_jumbo_chain[i]);
   1709    1.1      fvdl 			sc->bge_cdata.bge_rx_jumbo_chain[i] = NULL;
   1710    1.1      fvdl 		}
   1711    1.1      fvdl 		memset((char *)&sc->bge_rdata->bge_rx_jumbo_ring[i], 0,
   1712    1.1      fvdl 		    sizeof(struct bge_rx_bd));
   1713    1.1      fvdl 	}
   1714    1.1      fvdl 
   1715  1.261   msaitoh 	sc->bge_flags &= ~BGEF_JUMBO_RXRING_VALID;
   1716    1.1      fvdl }
   1717    1.1      fvdl 
   1718  1.104   thorpej static void
   1719  1.320    bouyer bge_free_tx_ring(struct bge_softc *sc, bool disable)
   1720    1.1      fvdl {
   1721  1.204   msaitoh 	int i;
   1722    1.1      fvdl 	struct txdmamap_pool_entry *dma;
   1723    1.1      fvdl 
   1724  1.261   msaitoh 	if (!(sc->bge_flags & BGEF_TXRING_VALID))
   1725    1.1      fvdl 		return;
   1726    1.1      fvdl 
   1727    1.1      fvdl 	for (i = 0; i < BGE_TX_RING_CNT; i++) {
   1728    1.1      fvdl 		if (sc->bge_cdata.bge_tx_chain[i] != NULL) {
   1729    1.1      fvdl 			m_freem(sc->bge_cdata.bge_tx_chain[i]);
   1730    1.1      fvdl 			sc->bge_cdata.bge_tx_chain[i] = NULL;
   1731    1.1      fvdl 			SLIST_INSERT_HEAD(&sc->txdma_list, sc->txdma[i],
   1732    1.1      fvdl 					    link);
   1733    1.1      fvdl 			sc->txdma[i] = 0;
   1734    1.1      fvdl 		}
   1735    1.1      fvdl 		memset((char *)&sc->bge_rdata->bge_tx_ring[i], 0,
   1736    1.1      fvdl 		    sizeof(struct bge_tx_bd));
   1737    1.1      fvdl 	}
   1738    1.1      fvdl 
   1739  1.320    bouyer 	if (disable) {
   1740  1.320    bouyer 		while ((dma = SLIST_FIRST(&sc->txdma_list))) {
   1741  1.320    bouyer 			SLIST_REMOVE_HEAD(&sc->txdma_list, link);
   1742  1.320    bouyer 			bus_dmamap_destroy(sc->bge_dmatag, dma->dmamap);
   1743  1.320    bouyer 			if (sc->bge_dma64) {
   1744  1.320    bouyer 				bus_dmamap_destroy(sc->bge_dmatag32,
   1745  1.320    bouyer 				    dma->dmamap32);
   1746  1.320    bouyer 			}
   1747  1.366     skrll 			kmem_free(dma, sizeof(*dma));
   1748  1.320    bouyer 		}
   1749  1.320    bouyer 		SLIST_INIT(&sc->txdma_list);
   1750    1.1      fvdl 	}
   1751    1.1      fvdl 
   1752  1.261   msaitoh 	sc->bge_flags &= ~BGEF_TXRING_VALID;
   1753    1.1      fvdl }
   1754    1.1      fvdl 
   1755  1.104   thorpej static int
   1756  1.104   thorpej bge_init_tx_ring(struct bge_softc *sc)
   1757    1.1      fvdl {
   1758  1.354     skrll 	struct ifnet * const ifp = &sc->ethercom.ec_if;
   1759    1.1      fvdl 	int i;
   1760  1.317    bouyer 	bus_dmamap_t dmamap, dmamap32;
   1761  1.258   msaitoh 	bus_size_t maxsegsz;
   1762    1.1      fvdl 	struct txdmamap_pool_entry *dma;
   1763    1.1      fvdl 
   1764  1.261   msaitoh 	if (sc->bge_flags & BGEF_TXRING_VALID)
   1765    1.1      fvdl 		return 0;
   1766    1.1      fvdl 
   1767    1.1      fvdl 	sc->bge_txcnt = 0;
   1768    1.1      fvdl 	sc->bge_tx_saved_considx = 0;
   1769   1.94  jonathan 
   1770   1.94  jonathan 	/* Initialize transmit producer index for host-memory send ring. */
   1771   1.94  jonathan 	sc->bge_tx_prodidx = 0;
   1772  1.151    cegger 	bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx);
   1773  1.158   msaitoh 	/* 5700 b2 errata */
   1774  1.158   msaitoh 	if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX)
   1775  1.151    cegger 		bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx);
   1776   1.25  jonathan 
   1777  1.158   msaitoh 	/* NIC-memory send ring not used; initialize to zero. */
   1778  1.151    cegger 	bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0);
   1779  1.158   msaitoh 	/* 5700 b2 errata */
   1780  1.158   msaitoh 	if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX)
   1781  1.151    cegger 		bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0);
   1782    1.1      fvdl 
   1783  1.258   msaitoh 	/* Limit DMA segment size for some chips */
   1784  1.258   msaitoh 	if ((BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57766) &&
   1785  1.258   msaitoh 	    (ifp->if_mtu <= ETHERMTU))
   1786  1.258   msaitoh 		maxsegsz = 2048;
   1787  1.258   msaitoh 	else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719)
   1788  1.258   msaitoh 		maxsegsz = 4096;
   1789  1.258   msaitoh 	else
   1790  1.258   msaitoh 		maxsegsz = ETHER_MAX_LEN_JUMBO;
   1791  1.317    bouyer 
   1792  1.320    bouyer 	if (SLIST_FIRST(&sc->txdma_list) != NULL)
   1793  1.320    bouyer 		goto alloc_done;
   1794  1.320    bouyer 
   1795  1.246   msaitoh 	for (i = 0; i < BGE_TX_RING_CNT; i++) {
   1796   1.95  jonathan 		if (bus_dmamap_create(sc->bge_dmatag, BGE_TXDMA_MAX,
   1797  1.317    bouyer 		    BGE_NTXSEG, maxsegsz, 0, BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW,
   1798    1.1      fvdl 		    &dmamap))
   1799  1.170   msaitoh 			return ENOBUFS;
   1800    1.1      fvdl 		if (dmamap == NULL)
   1801    1.1      fvdl 			panic("dmamap NULL in bge_init_tx_ring");
   1802  1.317    bouyer 		if (sc->bge_dma64) {
   1803  1.317    bouyer 			if (bus_dmamap_create(sc->bge_dmatag32, BGE_TXDMA_MAX,
   1804  1.317    bouyer 			    BGE_NTXSEG, maxsegsz, 0,
   1805  1.317    bouyer 			    BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW,
   1806  1.317    bouyer 			    &dmamap32)) {
   1807  1.317    bouyer 				bus_dmamap_destroy(sc->bge_dmatag, dmamap);
   1808  1.317    bouyer 				return ENOBUFS;
   1809  1.317    bouyer 			}
   1810  1.317    bouyer 			if (dmamap32 == NULL)
   1811  1.317    bouyer 				panic("dmamap32 NULL in bge_init_tx_ring");
   1812  1.317    bouyer 		} else
   1813  1.317    bouyer 			dmamap32 = dmamap;
   1814  1.366     skrll 		dma = kmem_alloc(sizeof(*dma), KM_NOSLEEP);
   1815    1.1      fvdl 		if (dma == NULL) {
   1816  1.138     joerg 			aprint_error_dev(sc->bge_dev,
   1817  1.138     joerg 			    "can't alloc txdmamap_pool_entry\n");
   1818    1.1      fvdl 			bus_dmamap_destroy(sc->bge_dmatag, dmamap);
   1819  1.317    bouyer 			if (sc->bge_dma64)
   1820  1.317    bouyer 				bus_dmamap_destroy(sc->bge_dmatag32, dmamap32);
   1821  1.170   msaitoh 			return ENOMEM;
   1822    1.1      fvdl 		}
   1823    1.1      fvdl 		dma->dmamap = dmamap;
   1824  1.317    bouyer 		dma->dmamap32 = dmamap32;
   1825    1.1      fvdl 		SLIST_INSERT_HEAD(&sc->txdma_list, dma, link);
   1826    1.1      fvdl 	}
   1827  1.320    bouyer alloc_done:
   1828  1.261   msaitoh 	sc->bge_flags |= BGEF_TXRING_VALID;
   1829    1.1      fvdl 
   1830  1.170   msaitoh 	return 0;
   1831    1.1      fvdl }
   1832    1.1      fvdl 
   1833  1.104   thorpej static void
   1834  1.104   thorpej bge_setmulti(struct bge_softc *sc)
   1835    1.1      fvdl {
   1836  1.354     skrll 	struct ethercom * const ec = &sc->ethercom;
   1837    1.1      fvdl 	struct ether_multi	*enm;
   1838  1.330   msaitoh 	struct ether_multistep	step;
   1839  1.170   msaitoh 	uint32_t		hashes[4] = { 0, 0, 0, 0 };
   1840  1.170   msaitoh 	uint32_t		h;
   1841    1.1      fvdl 	int			i;
   1842    1.1      fvdl 
   1843  1.375     skrll 	KASSERT(mutex_owned(sc->sc_core_lock));
   1844  1.375     skrll 	if (sc->bge_if_flags & IFF_PROMISC)
   1845   1.13   thorpej 		goto allmulti;
   1846    1.1      fvdl 
   1847    1.1      fvdl 	/* Now program new ones. */
   1848  1.333   msaitoh 	ETHER_LOCK(ec);
   1849  1.332   msaitoh 	ETHER_FIRST_MULTI(step, ec, enm);
   1850    1.1      fvdl 	while (enm != NULL) {
   1851   1.13   thorpej 		if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) {
   1852   1.13   thorpej 			/*
   1853   1.13   thorpej 			 * We must listen to a range of multicast addresses.
   1854   1.13   thorpej 			 * For now, just accept all multicasts, rather than
   1855   1.13   thorpej 			 * trying to set only those filter bits needed to match
   1856   1.13   thorpej 			 * the range.  (At this time, the only use of address
   1857   1.13   thorpej 			 * ranges is for IP multicast routing, for which the
   1858   1.13   thorpej 			 * range is big enough to require all bits set.)
   1859   1.13   thorpej 			 */
   1860  1.333   msaitoh 			ETHER_UNLOCK(ec);
   1861   1.13   thorpej 			goto allmulti;
   1862   1.13   thorpej 		}
   1863   1.13   thorpej 
   1864  1.158   msaitoh 		h = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN);
   1865    1.1      fvdl 
   1866  1.158   msaitoh 		/* Just want the 7 least-significant bits. */
   1867  1.158   msaitoh 		h &= 0x7f;
   1868    1.1      fvdl 
   1869  1.336   msaitoh 		hashes[(h & 0x60) >> 5] |= 1U << (h & 0x1F);
   1870  1.158   msaitoh 		ETHER_NEXT_MULTI(step, enm);
   1871   1.25  jonathan 	}
   1872  1.375     skrll 	ec->ec_flags &= ~ETHER_F_ALLMULTI;
   1873  1.333   msaitoh 	ETHER_UNLOCK(ec);
   1874   1.25  jonathan 
   1875  1.158   msaitoh 	goto setit;
   1876    1.1      fvdl 
   1877  1.158   msaitoh  allmulti:
   1878  1.375     skrll 	ETHER_LOCK(ec);
   1879  1.375     skrll 	ec->ec_flags |= ETHER_F_ALLMULTI;
   1880  1.375     skrll 	ETHER_UNLOCK(ec);
   1881  1.158   msaitoh 	hashes[0] = hashes[1] = hashes[2] = hashes[3] = 0xffffffff;
   1882  1.133     markd 
   1883  1.158   msaitoh  setit:
   1884  1.158   msaitoh 	for (i = 0; i < 4; i++)
   1885  1.158   msaitoh 		CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]);
   1886  1.158   msaitoh }
   1887  1.133     markd 
   1888  1.177   msaitoh static void
   1889  1.178   msaitoh bge_sig_pre_reset(struct bge_softc *sc, int type)
   1890  1.177   msaitoh {
   1891  1.208   msaitoh 
   1892  1.177   msaitoh 	/*
   1893  1.177   msaitoh 	 * Some chips don't like this so only do this if ASF is enabled
   1894  1.177   msaitoh 	 */
   1895  1.177   msaitoh 	if (sc->bge_asf_mode)
   1896  1.216   msaitoh 		bge_writemem_ind(sc, BGE_SRAM_FW_MB, BGE_SRAM_FW_MB_MAGIC);
   1897    1.1      fvdl 
   1898  1.177   msaitoh 	if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) {
   1899  1.177   msaitoh 		switch (type) {
   1900  1.177   msaitoh 		case BGE_RESET_START:
   1901  1.216   msaitoh 			bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB,
   1902  1.216   msaitoh 			    BGE_FW_DRV_STATE_START);
   1903  1.216   msaitoh 			break;
   1904  1.216   msaitoh 		case BGE_RESET_SHUTDOWN:
   1905  1.216   msaitoh 			bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB,
   1906  1.216   msaitoh 			    BGE_FW_DRV_STATE_UNLOAD);
   1907  1.177   msaitoh 			break;
   1908  1.216   msaitoh 		case BGE_RESET_SUSPEND:
   1909  1.216   msaitoh 			bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB,
   1910  1.216   msaitoh 			    BGE_FW_DRV_STATE_SUSPEND);
   1911  1.177   msaitoh 			break;
   1912  1.177   msaitoh 		}
   1913  1.177   msaitoh 	}
   1914  1.216   msaitoh 
   1915  1.216   msaitoh 	if (type == BGE_RESET_START || type == BGE_RESET_SUSPEND)
   1916  1.216   msaitoh 		bge_ape_driver_state_change(sc, type);
   1917  1.177   msaitoh }
   1918  1.177   msaitoh 
   1919  1.177   msaitoh static void
   1920  1.178   msaitoh bge_sig_post_reset(struct bge_softc *sc, int type)
   1921  1.177   msaitoh {
   1922  1.178   msaitoh 
   1923  1.177   msaitoh 	if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) {
   1924  1.177   msaitoh 		switch (type) {
   1925  1.177   msaitoh 		case BGE_RESET_START:
   1926  1.216   msaitoh 			bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB,
   1927  1.216   msaitoh 			    BGE_FW_DRV_STATE_START_DONE);
   1928  1.177   msaitoh 			/* START DONE */
   1929  1.177   msaitoh 			break;
   1930  1.216   msaitoh 		case BGE_RESET_SHUTDOWN:
   1931  1.216   msaitoh 			bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB,
   1932  1.216   msaitoh 			    BGE_FW_DRV_STATE_UNLOAD_DONE);
   1933  1.177   msaitoh 			break;
   1934  1.177   msaitoh 		}
   1935  1.177   msaitoh 	}
   1936  1.216   msaitoh 
   1937  1.216   msaitoh 	if (type == BGE_RESET_SHUTDOWN)
   1938  1.216   msaitoh 		bge_ape_driver_state_change(sc, type);
   1939  1.177   msaitoh }
   1940  1.177   msaitoh 
   1941  1.177   msaitoh static void
   1942  1.178   msaitoh bge_sig_legacy(struct bge_softc *sc, int type)
   1943  1.177   msaitoh {
   1944  1.178   msaitoh 
   1945  1.177   msaitoh 	if (sc->bge_asf_mode) {
   1946  1.177   msaitoh 		switch (type) {
   1947  1.177   msaitoh 		case BGE_RESET_START:
   1948  1.216   msaitoh 			bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB,
   1949  1.216   msaitoh 			    BGE_FW_DRV_STATE_START);
   1950  1.177   msaitoh 			break;
   1951  1.216   msaitoh 		case BGE_RESET_SHUTDOWN:
   1952  1.216   msaitoh 			bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB,
   1953  1.216   msaitoh 			    BGE_FW_DRV_STATE_UNLOAD);
   1954  1.177   msaitoh 			break;
   1955  1.177   msaitoh 		}
   1956  1.177   msaitoh 	}
   1957  1.177   msaitoh }
   1958  1.177   msaitoh 
   1959  1.177   msaitoh static void
   1960  1.216   msaitoh bge_wait_for_event_ack(struct bge_softc *sc)
   1961  1.216   msaitoh {
   1962  1.216   msaitoh 	int i;
   1963  1.216   msaitoh 
   1964  1.216   msaitoh 	/* wait up to 2500usec */
   1965  1.216   msaitoh 	for (i = 0; i < 250; i++) {
   1966  1.216   msaitoh 		if (!(CSR_READ_4(sc, BGE_RX_CPU_EVENT) &
   1967  1.216   msaitoh 			BGE_RX_CPU_DRV_EVENT))
   1968  1.216   msaitoh 			break;
   1969  1.216   msaitoh 		DELAY(10);
   1970  1.216   msaitoh 	}
   1971  1.216   msaitoh }
   1972  1.216   msaitoh 
   1973  1.216   msaitoh static void
   1974  1.178   msaitoh bge_stop_fw(struct bge_softc *sc)
   1975  1.177   msaitoh {
   1976    1.1      fvdl 
   1977  1.177   msaitoh 	if (sc->bge_asf_mode) {
   1978  1.216   msaitoh 		bge_wait_for_event_ack(sc);
   1979  1.216   msaitoh 
   1980  1.216   msaitoh 		bge_writemem_ind(sc, BGE_SRAM_FW_CMD_MB, BGE_FW_CMD_PAUSE);
   1981  1.216   msaitoh 		CSR_WRITE_4_FLUSH(sc, BGE_RX_CPU_EVENT,
   1982  1.216   msaitoh 		    CSR_READ_4(sc, BGE_RX_CPU_EVENT) | BGE_RX_CPU_DRV_EVENT);
   1983  1.177   msaitoh 
   1984  1.216   msaitoh 		bge_wait_for_event_ack(sc);
   1985  1.177   msaitoh 	}
   1986  1.177   msaitoh }
   1987    1.1      fvdl 
   1988  1.180   msaitoh static int
   1989  1.180   msaitoh bge_poll_fw(struct bge_softc *sc)
   1990  1.180   msaitoh {
   1991  1.180   msaitoh 	uint32_t val;
   1992  1.180   msaitoh 	int i;
   1993  1.180   msaitoh 
   1994  1.180   msaitoh 	if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) {
   1995  1.180   msaitoh 		for (i = 0; i < BGE_TIMEOUT; i++) {
   1996  1.180   msaitoh 			val = CSR_READ_4(sc, BGE_VCPU_STATUS);
   1997  1.180   msaitoh 			if (val & BGE_VCPU_STATUS_INIT_DONE)
   1998  1.180   msaitoh 				break;
   1999  1.180   msaitoh 			DELAY(100);
   2000  1.180   msaitoh 		}
   2001  1.180   msaitoh 		if (i >= BGE_TIMEOUT) {
   2002  1.180   msaitoh 			aprint_error_dev(sc->bge_dev, "reset timed out\n");
   2003  1.180   msaitoh 			return -1;
   2004  1.180   msaitoh 		}
   2005  1.274   msaitoh 	} else {
   2006  1.180   msaitoh 		/*
   2007  1.180   msaitoh 		 * Poll the value location we just wrote until
   2008  1.180   msaitoh 		 * we see the 1's complement of the magic number.
   2009  1.180   msaitoh 		 * This indicates that the firmware initialization
   2010  1.180   msaitoh 		 * is complete.
   2011  1.180   msaitoh 		 * XXX 1000ms for Flash and 10000ms for SEEPROM.
   2012  1.180   msaitoh 		 */
   2013  1.180   msaitoh 		for (i = 0; i < BGE_TIMEOUT; i++) {
   2014  1.216   msaitoh 			val = bge_readmem_ind(sc, BGE_SRAM_FW_MB);
   2015  1.216   msaitoh 			if (val == ~BGE_SRAM_FW_MB_MAGIC)
   2016  1.180   msaitoh 				break;
   2017  1.180   msaitoh 			DELAY(10);
   2018  1.180   msaitoh 		}
   2019  1.180   msaitoh 
   2020  1.274   msaitoh 		if ((i >= BGE_TIMEOUT)
   2021  1.274   msaitoh 		    && ((sc->bge_flags & BGEF_NO_EEPROM) == 0)) {
   2022  1.180   msaitoh 			aprint_error_dev(sc->bge_dev,
   2023  1.180   msaitoh 			    "firmware handshake timed out, val = %x\n", val);
   2024  1.180   msaitoh 			return -1;
   2025  1.180   msaitoh 		}
   2026  1.180   msaitoh 	}
   2027  1.180   msaitoh 
   2028  1.214   msaitoh 	if (sc->bge_chipid == BGE_CHIPID_BCM57765_A0) {
   2029  1.214   msaitoh 		/* tg3 says we have to wait extra time */
   2030  1.214   msaitoh 		delay(10 * 1000);
   2031  1.214   msaitoh 	}
   2032  1.214   msaitoh 
   2033  1.180   msaitoh 	return 0;
   2034  1.180   msaitoh }
   2035  1.180   msaitoh 
   2036  1.216   msaitoh int
   2037  1.216   msaitoh bge_phy_addr(struct bge_softc *sc)
   2038  1.216   msaitoh {
   2039  1.216   msaitoh 	struct pci_attach_args *pa = &(sc->bge_pa);
   2040  1.216   msaitoh 	int phy_addr = 1;
   2041  1.216   msaitoh 
   2042  1.216   msaitoh 	/*
   2043  1.216   msaitoh 	 * PHY address mapping for various devices.
   2044  1.216   msaitoh 	 *
   2045  1.330   msaitoh 	 *	    | F0 Cu | F0 Sr | F1 Cu | F1 Sr |
   2046  1.216   msaitoh 	 * ---------+-------+-------+-------+-------+
   2047  1.330   msaitoh 	 * BCM57XX  |	1   |	X   |	X   |	X   |
   2048  1.330   msaitoh 	 * BCM5704  |	1   |	X   |	1   |	X   |
   2049  1.330   msaitoh 	 * BCM5717  |	1   |	8   |	2   |	9   |
   2050  1.330   msaitoh 	 * BCM5719  |	1   |	8   |	2   |	9   |
   2051  1.330   msaitoh 	 * BCM5720  |	1   |	8   |	2   |	9   |
   2052  1.216   msaitoh 	 *
   2053  1.330   msaitoh 	 *	    | F2 Cu | F2 Sr | F3 Cu | F3 Sr |
   2054  1.216   msaitoh 	 * ---------+-------+-------+-------+-------+
   2055  1.330   msaitoh 	 * BCM57XX  |	X   |	X   |	X   |	X   |
   2056  1.330   msaitoh 	 * BCM5704  |	X   |	X   |	X   |	X   |
   2057  1.330   msaitoh 	 * BCM5717  |	X   |	X   |	X   |	X   |
   2058  1.330   msaitoh 	 * BCM5719  |	3   |	10  |	4   |	11  |
   2059  1.330   msaitoh 	 * BCM5720  |	X   |	X   |	X   |	X   |
   2060  1.216   msaitoh 	 *
   2061  1.216   msaitoh 	 * Other addresses may respond but they are not
   2062  1.216   msaitoh 	 * IEEE compliant PHYs and should be ignored.
   2063  1.216   msaitoh 	 */
   2064  1.216   msaitoh 	switch (BGE_ASICREV(sc->bge_chipid)) {
   2065  1.216   msaitoh 	case BGE_ASICREV_BCM5717:
   2066  1.216   msaitoh 	case BGE_ASICREV_BCM5719:
   2067  1.216   msaitoh 	case BGE_ASICREV_BCM5720:
   2068  1.216   msaitoh 		phy_addr = pa->pa_function;
   2069  1.234   msaitoh 		if (sc->bge_chipid != BGE_CHIPID_BCM5717_A0) {
   2070  1.216   msaitoh 			phy_addr += (CSR_READ_4(sc, BGE_SGDIG_STS) &
   2071  1.216   msaitoh 			    BGE_SGDIGSTS_IS_SERDES) ? 8 : 1;
   2072  1.216   msaitoh 		} else {
   2073  1.216   msaitoh 			phy_addr += (CSR_READ_4(sc, BGE_CPMU_PHY_STRAP) &
   2074  1.216   msaitoh 			    BGE_CPMU_PHY_STRAP_IS_SERDES) ? 8 : 1;
   2075  1.216   msaitoh 		}
   2076  1.216   msaitoh 	}
   2077  1.216   msaitoh 
   2078  1.216   msaitoh 	return phy_addr;
   2079  1.216   msaitoh }
   2080  1.216   msaitoh 
   2081  1.158   msaitoh /*
   2082  1.158   msaitoh  * Do endian, PCI and DMA initialization. Also check the on-board ROM
   2083  1.158   msaitoh  * self-test results.
   2084  1.158   msaitoh  */
   2085  1.158   msaitoh static int
   2086  1.158   msaitoh bge_chipinit(struct bge_softc *sc)
   2087  1.158   msaitoh {
   2088  1.288   msaitoh 	uint32_t dma_rw_ctl, misc_ctl, mode_ctl, reg;
   2089  1.178   msaitoh 	int i;
   2090    1.1      fvdl 
   2091  1.158   msaitoh 	/* Set endianness before we access any non-PCI registers. */
   2092  1.288   msaitoh 	misc_ctl = BGE_INIT;
   2093  1.288   msaitoh 	if (sc->bge_flags & BGEF_TAGGED_STATUS)
   2094  1.288   msaitoh 		misc_ctl |= BGE_PCIMISCCTL_TAGGED_STATUS;
   2095  1.158   msaitoh 	pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MISC_CTL,
   2096  1.288   msaitoh 	    misc_ctl);
   2097    1.1      fvdl 
   2098  1.158   msaitoh 	/*
   2099  1.158   msaitoh 	 * Clear the MAC statistics block in the NIC's
   2100  1.158   msaitoh 	 * internal memory.
   2101  1.158   msaitoh 	 */
   2102  1.158   msaitoh 	for (i = BGE_STATS_BLOCK;
   2103  1.170   msaitoh 	    i < BGE_STATS_BLOCK_END + 1; i += sizeof(uint32_t))
   2104  1.158   msaitoh 		BGE_MEMWIN_WRITE(sc->sc_pc, sc->sc_pcitag, i, 0);
   2105    1.1      fvdl 
   2106  1.158   msaitoh 	for (i = BGE_STATUS_BLOCK;
   2107  1.170   msaitoh 	    i < BGE_STATUS_BLOCK_END + 1; i += sizeof(uint32_t))
   2108  1.158   msaitoh 		BGE_MEMWIN_WRITE(sc->sc_pc, sc->sc_pcitag, i, 0);
   2109    1.1      fvdl 
   2110  1.214   msaitoh 	/* 5717 workaround from tg3 */
   2111  1.214   msaitoh 	if (sc->bge_chipid == BGE_CHIPID_BCM5717_A0) {
   2112  1.214   msaitoh 		/* Save */
   2113  1.214   msaitoh 		mode_ctl = CSR_READ_4(sc, BGE_MODE_CTL);
   2114  1.214   msaitoh 
   2115  1.214   msaitoh 		/* Temporary modify MODE_CTL to control TLP */
   2116  1.214   msaitoh 		reg = mode_ctl & ~BGE_MODECTL_PCIE_TLPADDRMASK;
   2117  1.214   msaitoh 		CSR_WRITE_4(sc, BGE_MODE_CTL, reg | BGE_MODECTL_PCIE_TLPADDR1);
   2118  1.214   msaitoh 
   2119  1.214   msaitoh 		/* Control TLP */
   2120  1.214   msaitoh 		reg = CSR_READ_4(sc, BGE_TLP_CONTROL_REG +
   2121  1.214   msaitoh 		    BGE_TLP_PHYCTL1);
   2122  1.214   msaitoh 		CSR_WRITE_4(sc, BGE_TLP_CONTROL_REG + BGE_TLP_PHYCTL1,
   2123  1.214   msaitoh 		    reg | BGE_TLP_PHYCTL1_EN_L1PLLPD);
   2124  1.214   msaitoh 
   2125  1.214   msaitoh 		/* Restore */
   2126  1.214   msaitoh 		CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl);
   2127  1.214   msaitoh 	}
   2128  1.330   msaitoh 
   2129  1.257   msaitoh 	if (BGE_IS_57765_FAMILY(sc)) {
   2130  1.214   msaitoh 		if (sc->bge_chipid == BGE_CHIPID_BCM57765_A0) {
   2131  1.214   msaitoh 			/* Save */
   2132  1.214   msaitoh 			mode_ctl = CSR_READ_4(sc, BGE_MODE_CTL);
   2133  1.214   msaitoh 
   2134  1.214   msaitoh 			/* Temporary modify MODE_CTL to control TLP */
   2135  1.214   msaitoh 			reg = mode_ctl & ~BGE_MODECTL_PCIE_TLPADDRMASK;
   2136  1.214   msaitoh 			CSR_WRITE_4(sc, BGE_MODE_CTL,
   2137  1.214   msaitoh 			    reg | BGE_MODECTL_PCIE_TLPADDR1);
   2138  1.330   msaitoh 
   2139  1.214   msaitoh 			/* Control TLP */
   2140  1.214   msaitoh 			reg = CSR_READ_4(sc, BGE_TLP_CONTROL_REG +
   2141  1.214   msaitoh 			    BGE_TLP_PHYCTL5);
   2142  1.214   msaitoh 			CSR_WRITE_4(sc, BGE_TLP_CONTROL_REG + BGE_TLP_PHYCTL5,
   2143  1.214   msaitoh 			    reg | BGE_TLP_PHYCTL5_DIS_L2CLKREQ);
   2144  1.214   msaitoh 
   2145  1.214   msaitoh 			/* Restore */
   2146  1.214   msaitoh 			CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl);
   2147  1.214   msaitoh 		}
   2148  1.214   msaitoh 		if (BGE_CHIPREV(sc->bge_chipid) != BGE_CHIPREV_57765_AX) {
   2149  1.305   msaitoh 			/*
   2150  1.305   msaitoh 			 * For the 57766 and non Ax versions of 57765, bootcode
   2151  1.305   msaitoh 			 * needs to setup the PCIE Fast Training Sequence (FTS)
   2152  1.305   msaitoh 			 * value to prevent transmit hangs.
   2153  1.305   msaitoh 			 */
   2154  1.214   msaitoh 			reg = CSR_READ_4(sc, BGE_CPMU_PADRNG_CTL);
   2155  1.214   msaitoh 			CSR_WRITE_4(sc, BGE_CPMU_PADRNG_CTL,
   2156  1.214   msaitoh 			    reg | BGE_CPMU_PADRNG_CTL_RDIV2);
   2157  1.214   msaitoh 
   2158  1.214   msaitoh 			/* Save */
   2159  1.214   msaitoh 			mode_ctl = CSR_READ_4(sc, BGE_MODE_CTL);
   2160  1.214   msaitoh 
   2161  1.214   msaitoh 			/* Temporary modify MODE_CTL to control TLP */
   2162  1.214   msaitoh 			reg = mode_ctl & ~BGE_MODECTL_PCIE_TLPADDRMASK;
   2163  1.214   msaitoh 			CSR_WRITE_4(sc, BGE_MODE_CTL,
   2164  1.214   msaitoh 			    reg | BGE_MODECTL_PCIE_TLPADDR0);
   2165  1.214   msaitoh 
   2166  1.214   msaitoh 			/* Control TLP */
   2167  1.214   msaitoh 			reg = CSR_READ_4(sc, BGE_TLP_CONTROL_REG +
   2168  1.214   msaitoh 			    BGE_TLP_FTSMAX);
   2169  1.214   msaitoh 			reg &= ~BGE_TLP_FTSMAX_MSK;
   2170  1.214   msaitoh 			CSR_WRITE_4(sc, BGE_TLP_CONTROL_REG + BGE_TLP_FTSMAX,
   2171  1.214   msaitoh 			    reg | BGE_TLP_FTSMAX_VAL);
   2172  1.214   msaitoh 
   2173  1.214   msaitoh 			/* Restore */
   2174  1.214   msaitoh 			CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl);
   2175  1.214   msaitoh 		}
   2176  1.214   msaitoh 
   2177  1.214   msaitoh 		reg = CSR_READ_4(sc, BGE_CPMU_LSPD_10MB_CLK);
   2178  1.214   msaitoh 		reg &= ~BGE_CPMU_LSPD_10MB_MACCLK_MASK;
   2179  1.214   msaitoh 		reg |= BGE_CPMU_LSPD_10MB_MACCLK_6_25;
   2180  1.214   msaitoh 		CSR_WRITE_4(sc, BGE_CPMU_LSPD_10MB_CLK, reg);
   2181  1.214   msaitoh 	}
   2182  1.214   msaitoh 
   2183  1.158   msaitoh 	/* Set up the PCI DMA control register. */
   2184  1.166   msaitoh 	dma_rw_ctl = BGE_PCI_READ_CMD | BGE_PCI_WRITE_CMD;
   2185  1.261   msaitoh 	if (sc->bge_flags & BGEF_PCIE) {
   2186  1.166   msaitoh 		/* Read watermark not used, 128 bytes for write. */
   2187  1.158   msaitoh 		DPRINTFN(4, ("(%s: PCI-Express DMA setting)\n",
   2188  1.158   msaitoh 		    device_xname(sc->bge_dev)));
   2189  1.253   msaitoh 		if (sc->bge_mps >= 256)
   2190  1.253   msaitoh 			dma_rw_ctl |= BGE_PCIDMARWCTL_WR_WAT_SHIFT(7);
   2191  1.253   msaitoh 		else
   2192  1.253   msaitoh 			dma_rw_ctl |= BGE_PCIDMARWCTL_WR_WAT_SHIFT(3);
   2193  1.261   msaitoh 	} else if (sc->bge_flags & BGEF_PCIX) {
   2194  1.330   msaitoh 		DPRINTFN(4, ("(:%s: PCI-X DMA setting)\n",
   2195  1.158   msaitoh 		    device_xname(sc->bge_dev)));
   2196  1.158   msaitoh 		/* PCI-X bus */
   2197  1.172   msaitoh 		if (BGE_IS_5714_FAMILY(sc)) {
   2198  1.172   msaitoh 			/* 256 bytes for read and write. */
   2199  1.204   msaitoh 			dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(2) |
   2200  1.204   msaitoh 			    BGE_PCIDMARWCTL_WR_WAT_SHIFT(2);
   2201  1.172   msaitoh 
   2202  1.172   msaitoh 			if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5780)
   2203  1.172   msaitoh 				dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL;
   2204  1.172   msaitoh 			else
   2205  1.172   msaitoh 				dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE_LOCAL;
   2206  1.276   msaitoh 		} else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5703) {
   2207  1.276   msaitoh 			/*
   2208  1.276   msaitoh 			 * In the BCM5703, the DMA read watermark should
   2209  1.276   msaitoh 			 * be set to less than or equal to the maximum
   2210  1.276   msaitoh 			 * memory read byte count of the PCI-X command
   2211  1.276   msaitoh 			 * register.
   2212  1.276   msaitoh 			 */
   2213  1.276   msaitoh 			dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(4) |
   2214  1.276   msaitoh 			    BGE_PCIDMARWCTL_WR_WAT_SHIFT(3);
   2215  1.172   msaitoh 		} else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) {
   2216  1.172   msaitoh 			/* 1536 bytes for read, 384 bytes for write. */
   2217  1.204   msaitoh 			dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(7) |
   2218  1.204   msaitoh 			    BGE_PCIDMARWCTL_WR_WAT_SHIFT(3);
   2219  1.172   msaitoh 		} else {
   2220  1.172   msaitoh 			/* 384 bytes for read and write. */
   2221  1.204   msaitoh 			dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(3) |
   2222  1.204   msaitoh 			    BGE_PCIDMARWCTL_WR_WAT_SHIFT(3) |
   2223  1.172   msaitoh 			    (0x0F);
   2224  1.172   msaitoh 		}
   2225  1.172   msaitoh 
   2226  1.172   msaitoh 		if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5703 ||
   2227  1.172   msaitoh 		    BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) {
   2228  1.172   msaitoh 			uint32_t tmp;
   2229  1.172   msaitoh 
   2230  1.172   msaitoh 			/* Set ONEDMA_ATONCE for hardware workaround. */
   2231  1.226   msaitoh 			tmp = CSR_READ_4(sc, BGE_PCI_CLKCTL) & 0x1f;
   2232  1.172   msaitoh 			if (tmp == 6 || tmp == 7)
   2233  1.172   msaitoh 				dma_rw_ctl |=
   2234  1.172   msaitoh 				    BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL;
   2235  1.172   msaitoh 
   2236  1.172   msaitoh 			/* Set PCI-X DMA write workaround. */
   2237  1.172   msaitoh 			dma_rw_ctl |= BGE_PCIDMARWCTL_ASRT_ALL_BE;
   2238  1.158   msaitoh 		}
   2239  1.158   msaitoh 	} else {
   2240  1.172   msaitoh 		/* Conventional PCI bus: 256 bytes for read and write. */
   2241  1.330   msaitoh 		DPRINTFN(4, ("(%s: PCI 2.2 DMA setting)\n",
   2242  1.158   msaitoh 		    device_xname(sc->bge_dev)));
   2243  1.204   msaitoh 		dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(7) |
   2244  1.204   msaitoh 		    BGE_PCIDMARWCTL_WR_WAT_SHIFT(7);
   2245  1.204   msaitoh 
   2246  1.160   msaitoh 		if (BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5705 &&
   2247  1.160   msaitoh 		    BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5750)
   2248  1.158   msaitoh 			dma_rw_ctl |= 0x0F;
   2249  1.158   msaitoh 	}
   2250  1.157   msaitoh 
   2251  1.161   msaitoh 	if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 ||
   2252  1.161   msaitoh 	    BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5701)
   2253  1.161   msaitoh 		dma_rw_ctl |= BGE_PCIDMARWCTL_USE_MRM |
   2254  1.161   msaitoh 		    BGE_PCIDMARWCTL_ASRT_ALL_BE;
   2255  1.178   msaitoh 
   2256  1.161   msaitoh 	if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5703 ||
   2257  1.161   msaitoh 	    BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704)
   2258  1.161   msaitoh 		dma_rw_ctl &= ~BGE_PCIDMARWCTL_MINDMA;
   2259  1.161   msaitoh 
   2260  1.257   msaitoh 	if (BGE_IS_57765_PLUS(sc)) {
   2261  1.214   msaitoh 		dma_rw_ctl &= ~BGE_PCIDMARWCTL_DIS_CACHE_ALIGNMENT;
   2262  1.214   msaitoh 		if (sc->bge_chipid == BGE_CHIPID_BCM57765_A0)
   2263  1.214   msaitoh 			dma_rw_ctl &= ~BGE_PCIDMARWCTL_CRDRDR_RDMA_MRRS_MSK;
   2264  1.214   msaitoh 
   2265  1.214   msaitoh 		/*
   2266  1.214   msaitoh 		 * Enable HW workaround for controllers that misinterpret
   2267  1.214   msaitoh 		 * a status tag update and leave interrupts permanently
   2268  1.214   msaitoh 		 * disabled.
   2269  1.214   msaitoh 		 */
   2270  1.257   msaitoh 		if (!BGE_IS_57765_FAMILY(sc) &&
   2271  1.327   msaitoh 		    BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5717 &&
   2272  1.327   msaitoh 		    BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5762)
   2273  1.214   msaitoh 			dma_rw_ctl |= BGE_PCIDMARWCTL_TAGGED_STATUS_WA;
   2274  1.214   msaitoh 	}
   2275  1.214   msaitoh 
   2276  1.177   msaitoh 	pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_DMA_RW_CTL,
   2277  1.177   msaitoh 	    dma_rw_ctl);
   2278  1.120   tsutsui 
   2279  1.158   msaitoh 	/*
   2280  1.158   msaitoh 	 * Set up general mode register.
   2281  1.158   msaitoh 	 */
   2282  1.216   msaitoh 	mode_ctl = BGE_DMA_SWAP_OPTIONS;
   2283  1.327   msaitoh 	if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720 ||
   2284  1.327   msaitoh 	    BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5762) {
   2285  1.216   msaitoh 		/* Retain Host-2-BMC settings written by APE firmware. */
   2286  1.216   msaitoh 		mode_ctl |= CSR_READ_4(sc, BGE_MODE_CTL) &
   2287  1.216   msaitoh 		    (BGE_MODECTL_BYTESWAP_B2HRX_DATA |
   2288  1.216   msaitoh 		    BGE_MODECTL_WORDSWAP_B2HRX_DATA |
   2289  1.216   msaitoh 		    BGE_MODECTL_B2HRX_ENABLE | BGE_MODECTL_HTX2B_ENABLE);
   2290  1.216   msaitoh 	}
   2291  1.216   msaitoh 	mode_ctl |= BGE_MODECTL_MAC_ATTN_INTR | BGE_MODECTL_HOST_SEND_BDS |
   2292  1.216   msaitoh 	    BGE_MODECTL_TX_NO_PHDR_CSUM;
   2293   1.16   thorpej 
   2294  1.158   msaitoh 	/*
   2295  1.172   msaitoh 	 * BCM5701 B5 have a bug causing data corruption when using
   2296  1.172   msaitoh 	 * 64-bit DMA reads, which can be terminated early and then
   2297  1.172   msaitoh 	 * completed later as 32-bit accesses, in combination with
   2298  1.172   msaitoh 	 * certain bridges.
   2299  1.172   msaitoh 	 */
   2300  1.172   msaitoh 	if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5701 &&
   2301  1.172   msaitoh 	    sc->bge_chipid == BGE_CHIPID_BCM5701_B5)
   2302  1.216   msaitoh 		mode_ctl |= BGE_MODECTL_FORCE_PCI32;
   2303  1.172   msaitoh 
   2304  1.172   msaitoh 	/*
   2305  1.177   msaitoh 	 * Tell the firmware the driver is running
   2306  1.177   msaitoh 	 */
   2307  1.177   msaitoh 	if (sc->bge_asf_mode & ASF_STACKUP)
   2308  1.216   msaitoh 		mode_ctl |= BGE_MODECTL_STACKUP;
   2309  1.216   msaitoh 
   2310  1.216   msaitoh 	CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl);
   2311  1.177   msaitoh 
   2312  1.177   msaitoh 	/*
   2313  1.158   msaitoh 	 * Disable memory write invalidate.  Apparently it is not supported
   2314  1.158   msaitoh 	 * properly by these devices.
   2315  1.158   msaitoh 	 */
   2316  1.172   msaitoh 	PCI_CLRBIT(sc->sc_pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG,
   2317  1.172   msaitoh 		   PCI_COMMAND_INVALIDATE_ENABLE);
   2318   1.16   thorpej 
   2319  1.158   msaitoh #ifdef __brokenalpha__
   2320  1.158   msaitoh 	/*
   2321  1.158   msaitoh 	 * Must insure that we do not cross an 8K (bytes) boundary
   2322  1.158   msaitoh 	 * for DMA reads.  Our highest limit is 1K bytes.  This is a
   2323  1.158   msaitoh 	 * restriction on some ALPHA platforms with early revision
   2324  1.158   msaitoh 	 * 21174 PCI chipsets, such as the AlphaPC 164lx
   2325  1.158   msaitoh 	 */
   2326  1.158   msaitoh 	PCI_SETBIT(sc, BGE_PCI_DMA_RW_CTL, BGE_PCI_READ_BNDRY_1024, 4);
   2327  1.158   msaitoh #endif
   2328   1.16   thorpej 
   2329  1.158   msaitoh 	/* Set the timer prescaler (always 66MHz) */
   2330  1.341   msaitoh 	CSR_WRITE_4_FLUSH(sc, BGE_MISC_CFG, BGE_32BITTIME_66MHZ);
   2331   1.16   thorpej 
   2332  1.159   msaitoh 	if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) {
   2333  1.159   msaitoh 		DELAY(40);	/* XXX */
   2334  1.159   msaitoh 
   2335  1.159   msaitoh 		/* Put PHY into ready state */
   2336  1.211   msaitoh 		BGE_CLRBIT_FLUSH(sc, BGE_MISC_CFG, BGE_MISCCFG_EPHY_IDDQ);
   2337  1.159   msaitoh 		DELAY(40);
   2338  1.159   msaitoh 	}
   2339  1.159   msaitoh 
   2340  1.170   msaitoh 	return 0;
   2341  1.158   msaitoh }
   2342   1.16   thorpej 
   2343  1.158   msaitoh static int
   2344  1.158   msaitoh bge_blockinit(struct bge_softc *sc)
   2345  1.158   msaitoh {
   2346  1.177   msaitoh 	volatile struct bge_rcb	 *rcb;
   2347  1.177   msaitoh 	bus_size_t rcb_addr;
   2348  1.354     skrll 	struct ifnet * const ifp = &sc->ethercom.ec_if;
   2349  1.177   msaitoh 	bge_hostaddr taddr;
   2350  1.327   msaitoh 	uint32_t	dmactl, rdmareg, mimode, val;
   2351  1.222   msaitoh 	int		i, limit;
   2352   1.16   thorpej 
   2353  1.158   msaitoh 	/*
   2354  1.158   msaitoh 	 * Initialize the memory window pointer register so that
   2355  1.158   msaitoh 	 * we can access the first 32K of internal NIC RAM. This will
   2356  1.158   msaitoh 	 * allow us to set up the TX send ring RCBs and the RX return
   2357  1.158   msaitoh 	 * ring RCBs, plus other things which live in NIC memory.
   2358  1.158   msaitoh 	 */
   2359  1.158   msaitoh 	pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_BASEADDR, 0);
   2360  1.120   tsutsui 
   2361  1.216   msaitoh 	if (!BGE_IS_5705_PLUS(sc)) {
   2362  1.236   msaitoh 		/* 57XX step 33 */
   2363  1.236   msaitoh 		/* Configure mbuf memory pool */
   2364  1.332   msaitoh 		CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, BGE_BUFFPOOL_1);
   2365  1.172   msaitoh 
   2366  1.172   msaitoh 		if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704)
   2367  1.172   msaitoh 			CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000);
   2368  1.172   msaitoh 		else
   2369  1.172   msaitoh 			CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000);
   2370   1.40      fvdl 
   2371  1.236   msaitoh 		/* 57XX step 34 */
   2372  1.158   msaitoh 		/* Configure DMA resource pool */
   2373  1.158   msaitoh 		CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_BASEADDR,
   2374  1.158   msaitoh 		    BGE_DMA_DESCRIPTORS);
   2375  1.158   msaitoh 		CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LEN, 0x2000);
   2376  1.158   msaitoh 	}
   2377   1.40      fvdl 
   2378  1.236   msaitoh 	/* 5718 step 11, 57XX step 35 */
   2379  1.236   msaitoh 	/*
   2380  1.236   msaitoh 	 * Configure mbuf pool watermarks. New broadcom docs strongly
   2381  1.236   msaitoh 	 * recommend these.
   2382  1.236   msaitoh 	 */
   2383  1.216   msaitoh 	if (BGE_IS_5717_PLUS(sc)) {
   2384  1.202   tsutsui 		CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0);
   2385  1.316    bouyer 		if (ifp->if_mtu > ETHERMTU) {
   2386  1.316    bouyer 			CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x7e);
   2387  1.316    bouyer 			CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0xea);
   2388  1.316    bouyer 		} else {
   2389  1.316    bouyer 			CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x2a);
   2390  1.316    bouyer 			CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0xa0);
   2391  1.316    bouyer 		}
   2392  1.202   tsutsui 	} else if (BGE_IS_5705_PLUS(sc)) {
   2393  1.202   tsutsui 		CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0);
   2394  1.202   tsutsui 
   2395  1.202   tsutsui 		if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) {
   2396  1.202   tsutsui 			CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x04);
   2397  1.202   tsutsui 			CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x10);
   2398  1.202   tsutsui 		} else {
   2399  1.202   tsutsui 			CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x10);
   2400  1.202   tsutsui 			CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60);
   2401  1.202   tsutsui 		}
   2402  1.158   msaitoh 	} else {
   2403  1.218   msaitoh 		CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x50);
   2404  1.218   msaitoh 		CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x20);
   2405  1.158   msaitoh 		CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60);
   2406  1.158   msaitoh 	}
   2407   1.25  jonathan 
   2408  1.236   msaitoh 	/* 57XX step 36 */
   2409  1.236   msaitoh 	/* Configure DMA resource watermarks */
   2410  1.158   msaitoh 	CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5);
   2411  1.158   msaitoh 	CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10);
   2412   1.51      fvdl 
   2413  1.236   msaitoh 	/* 5718 step 13, 57XX step 38 */
   2414  1.236   msaitoh 	/* Enable buffer manager */
   2415  1.216   msaitoh 	val = BGE_BMANMODE_ENABLE | BGE_BMANMODE_ATTN;
   2416  1.216   msaitoh 	/*
   2417  1.216   msaitoh 	 * Change the arbitration algorithm of TXMBUF read request to
   2418  1.216   msaitoh 	 * round-robin instead of priority based for BCM5719.  When
   2419  1.216   msaitoh 	 * TXFIFO is almost empty, RDMA will hold its request until
   2420  1.216   msaitoh 	 * TXFIFO is not almost empty.
   2421  1.216   msaitoh 	 */
   2422  1.216   msaitoh 	if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719)
   2423  1.216   msaitoh 		val |= BGE_BMANMODE_NO_TX_UNDERRUN;
   2424  1.216   msaitoh 	if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5717 ||
   2425  1.216   msaitoh 		sc->bge_chipid == BGE_CHIPID_BCM5719_A0 ||
   2426  1.216   msaitoh 		sc->bge_chipid == BGE_CHIPID_BCM5720_A0)
   2427  1.216   msaitoh 		val |= BGE_BMANMODE_LOMBUF_ATTN;
   2428  1.216   msaitoh 	CSR_WRITE_4(sc, BGE_BMAN_MODE, val);
   2429   1.44   hannken 
   2430  1.236   msaitoh 	/* 57XX step 39 */
   2431  1.236   msaitoh 	/* Poll for buffer manager start indication */
   2432  1.172   msaitoh 	for (i = 0; i < BGE_TIMEOUT * 2; i++) {
   2433  1.216   msaitoh 		DELAY(10);
   2434  1.172   msaitoh 		if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE)
   2435  1.172   msaitoh 			break;
   2436  1.172   msaitoh 	}
   2437   1.51      fvdl 
   2438  1.172   msaitoh 	if (i == BGE_TIMEOUT * 2) {
   2439  1.172   msaitoh 		aprint_error_dev(sc->bge_dev,
   2440  1.172   msaitoh 		    "buffer manager failed to start\n");
   2441  1.172   msaitoh 		return ENXIO;
   2442  1.158   msaitoh 	}
   2443   1.51      fvdl 
   2444  1.236   msaitoh 	/* 57XX step 40 */
   2445  1.236   msaitoh 	/* Enable flow-through queues */
   2446  1.158   msaitoh 	CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF);
   2447  1.158   msaitoh 	CSR_WRITE_4(sc, BGE_FTQ_RESET, 0);
   2448   1.76      cube 
   2449  1.158   msaitoh 	/* Wait until queue initialization is complete */
   2450  1.172   msaitoh 	for (i = 0; i < BGE_TIMEOUT * 2; i++) {
   2451  1.158   msaitoh 		if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0)
   2452  1.158   msaitoh 			break;
   2453  1.158   msaitoh 		DELAY(10);
   2454  1.158   msaitoh 	}
   2455   1.76      cube 
   2456  1.172   msaitoh 	if (i == BGE_TIMEOUT * 2) {
   2457  1.158   msaitoh 		aprint_error_dev(sc->bge_dev,
   2458  1.158   msaitoh 		    "flow-through queue init failed\n");
   2459  1.170   msaitoh 		return ENXIO;
   2460  1.158   msaitoh 	}
   2461   1.92     gavan 
   2462  1.222   msaitoh 	/*
   2463  1.222   msaitoh 	 * Summary of rings supported by the controller:
   2464  1.222   msaitoh 	 *
   2465  1.222   msaitoh 	 * Standard Receive Producer Ring
   2466  1.222   msaitoh 	 * - This ring is used to feed receive buffers for "standard"
   2467  1.222   msaitoh 	 *   sized frames (typically 1536 bytes) to the controller.
   2468  1.222   msaitoh 	 *
   2469  1.222   msaitoh 	 * Jumbo Receive Producer Ring
   2470  1.222   msaitoh 	 * - This ring is used to feed receive buffers for jumbo sized
   2471  1.222   msaitoh 	 *   frames (i.e. anything bigger than the "standard" frames)
   2472  1.222   msaitoh 	 *   to the controller.
   2473  1.222   msaitoh 	 *
   2474  1.222   msaitoh 	 * Mini Receive Producer Ring
   2475  1.222   msaitoh 	 * - This ring is used to feed receive buffers for "mini"
   2476  1.222   msaitoh 	 *   sized frames to the controller.
   2477  1.222   msaitoh 	 * - This feature required external memory for the controller
   2478  1.222   msaitoh 	 *   but was never used in a production system.  Should always
   2479  1.222   msaitoh 	 *   be disabled.
   2480  1.222   msaitoh 	 *
   2481  1.222   msaitoh 	 * Receive Return Ring
   2482  1.222   msaitoh 	 * - After the controller has placed an incoming frame into a
   2483  1.222   msaitoh 	 *   receive buffer that buffer is moved into a receive return
   2484  1.222   msaitoh 	 *   ring.  The driver is then responsible to passing the
   2485  1.222   msaitoh 	 *   buffer up to the stack.  Many versions of the controller
   2486  1.222   msaitoh 	 *   support multiple RR rings.
   2487  1.222   msaitoh 	 *
   2488  1.222   msaitoh 	 * Send Ring
   2489  1.222   msaitoh 	 * - This ring is used for outgoing frames.  Many versions of
   2490  1.222   msaitoh 	 *   the controller support multiple send rings.
   2491  1.222   msaitoh 	 */
   2492  1.222   msaitoh 
   2493  1.236   msaitoh 	/* 5718 step 15, 57XX step 41 */
   2494  1.236   msaitoh 	/* Initialize the standard RX ring control block */
   2495  1.158   msaitoh 	rcb = &sc->bge_rdata->bge_info.bge_std_rx_rcb;
   2496  1.172   msaitoh 	BGE_HOSTADDR(rcb->bge_hostaddr, BGE_RING_DMA_ADDR(sc, bge_rx_std_ring));
   2497  1.236   msaitoh 	/* 5718 step 16 */
   2498  1.257   msaitoh 	if (BGE_IS_57765_PLUS(sc)) {
   2499  1.222   msaitoh 		/*
   2500  1.222   msaitoh 		 * Bits 31-16: Programmable ring size (2048, 1024, 512, .., 32)
   2501  1.222   msaitoh 		 * Bits 15-2 : Maximum RX frame size
   2502  1.309       snj 		 * Bit 1     : 1 = Ring Disabled, 0 = Ring Enabled
   2503  1.222   msaitoh 		 * Bit 0     : Reserved
   2504  1.222   msaitoh 		 */
   2505  1.202   tsutsui 		rcb->bge_maxlen_flags =
   2506  1.202   tsutsui 		    BGE_RCB_MAXLEN_FLAGS(512, BGE_MAX_FRAMELEN << 2);
   2507  1.222   msaitoh 	} else if (BGE_IS_5705_PLUS(sc)) {
   2508  1.222   msaitoh 		/*
   2509  1.222   msaitoh 		 * Bits 31-16: Programmable ring size (512, 256, 128, 64, 32)
   2510  1.222   msaitoh 		 * Bits 15-2 : Reserved (should be 0)
   2511  1.222   msaitoh 		 * Bit 1     : 1 = Ring Disabled, 0 = Ring Enabled
   2512  1.222   msaitoh 		 * Bit 0     : Reserved
   2513  1.222   msaitoh 		 */
   2514  1.158   msaitoh 		rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(512, 0);
   2515  1.222   msaitoh 	} else {
   2516  1.222   msaitoh 		/*
   2517  1.222   msaitoh 		 * Ring size is always XXX entries
   2518  1.222   msaitoh 		 * Bits 31-16: Maximum RX frame size
   2519  1.222   msaitoh 		 * Bits 15-2 : Reserved (should be 0)
   2520  1.222   msaitoh 		 * Bit 1     : 1 = Ring Disabled, 0 = Ring Enabled
   2521  1.222   msaitoh 		 * Bit 0     : Reserved
   2522  1.222   msaitoh 		 */
   2523  1.158   msaitoh 		rcb->bge_maxlen_flags =
   2524  1.158   msaitoh 		    BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 0);
   2525  1.222   msaitoh 	}
   2526  1.216   msaitoh 	if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5717 ||
   2527  1.216   msaitoh 	    BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719 ||
   2528  1.216   msaitoh 	    BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720)
   2529  1.216   msaitoh 		rcb->bge_nicaddr = BGE_STD_RX_RINGS_5717;
   2530  1.216   msaitoh 	else
   2531  1.216   msaitoh 		rcb->bge_nicaddr = BGE_STD_RX_RINGS;
   2532  1.222   msaitoh 	/* Write the standard receive producer ring control block. */
   2533  1.158   msaitoh 	CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcb->bge_hostaddr.bge_addr_hi);
   2534  1.158   msaitoh 	CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcb->bge_hostaddr.bge_addr_lo);
   2535  1.158   msaitoh 	CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags);
   2536  1.158   msaitoh 	CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcb->bge_nicaddr);
   2537  1.119   tsutsui 
   2538  1.222   msaitoh 	/* Reset the standard receive producer ring producer index. */
   2539  1.222   msaitoh 	bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, 0);
   2540  1.222   msaitoh 
   2541  1.236   msaitoh 	/* 57XX step 42 */
   2542  1.158   msaitoh 	/*
   2543  1.236   msaitoh 	 * Initialize the jumbo RX ring control block
   2544  1.158   msaitoh 	 * We set the 'ring disabled' bit in the flags
   2545  1.158   msaitoh 	 * field until we're actually ready to start
   2546  1.158   msaitoh 	 * using this ring (i.e. once we set the MTU
   2547  1.158   msaitoh 	 * high enough to require it).
   2548  1.158   msaitoh 	 */
   2549  1.166   msaitoh 	if (BGE_IS_JUMBO_CAPABLE(sc)) {
   2550  1.158   msaitoh 		rcb = &sc->bge_rdata->bge_info.bge_jumbo_rx_rcb;
   2551  1.172   msaitoh 		BGE_HOSTADDR(rcb->bge_hostaddr,
   2552  1.158   msaitoh 		    BGE_RING_DMA_ADDR(sc, bge_rx_jumbo_ring));
   2553  1.222   msaitoh 		rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0,
   2554  1.222   msaitoh 		    BGE_RCB_FLAG_USE_EXT_RX_BD | BGE_RCB_FLAG_RING_DISABLED);
   2555  1.216   msaitoh 		if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5717 ||
   2556  1.216   msaitoh 		    BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719 ||
   2557  1.216   msaitoh 		    BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720)
   2558  1.216   msaitoh 			rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS_5717;
   2559  1.216   msaitoh 		else
   2560  1.216   msaitoh 			rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS;
   2561  1.158   msaitoh 		CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI,
   2562  1.158   msaitoh 		    rcb->bge_hostaddr.bge_addr_hi);
   2563  1.158   msaitoh 		CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO,
   2564  1.158   msaitoh 		    rcb->bge_hostaddr.bge_addr_lo);
   2565  1.222   msaitoh 		/* Program the jumbo receive producer ring RCB parameters. */
   2566  1.158   msaitoh 		CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS,
   2567  1.158   msaitoh 		    rcb->bge_maxlen_flags);
   2568  1.158   msaitoh 		CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcb->bge_nicaddr);
   2569  1.216   msaitoh 		/* Reset the jumbo receive producer ring producer index. */
   2570  1.216   msaitoh 		bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0);
   2571  1.216   msaitoh 	}
   2572  1.149  sborrill 
   2573  1.236   msaitoh 	/* 57XX step 43 */
   2574  1.216   msaitoh 	/* Disable the mini receive producer ring RCB. */
   2575  1.216   msaitoh 	if (BGE_IS_5700_FAMILY(sc)) {
   2576  1.158   msaitoh 		/* Set up dummy disabled mini ring RCB */
   2577  1.158   msaitoh 		rcb = &sc->bge_rdata->bge_info.bge_mini_rx_rcb;
   2578  1.222   msaitoh 		rcb->bge_maxlen_flags =
   2579  1.222   msaitoh 		    BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED);
   2580  1.158   msaitoh 		CSR_WRITE_4(sc, BGE_RX_MINI_RCB_MAXLEN_FLAGS,
   2581  1.158   msaitoh 		    rcb->bge_maxlen_flags);
   2582  1.216   msaitoh 		/* Reset the mini receive producer ring producer index. */
   2583  1.216   msaitoh 		bge_writembx(sc, BGE_MBX_RX_MINI_PROD_LO, 0);
   2584  1.133     markd 
   2585  1.158   msaitoh 		bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map,
   2586  1.158   msaitoh 		    offsetof(struct bge_ring_data, bge_info),
   2587  1.364     skrll 		    sizeof(struct bge_gib),
   2588  1.331   msaitoh 		    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
   2589  1.158   msaitoh 	}
   2590  1.133     markd 
   2591  1.206   msaitoh 	/* Choose de-pipeline mode for BCM5906 A0, A1 and A2. */
   2592  1.206   msaitoh 	if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) {
   2593  1.206   msaitoh 		if (sc->bge_chipid == BGE_CHIPID_BCM5906_A0 ||
   2594  1.206   msaitoh 		    sc->bge_chipid == BGE_CHIPID_BCM5906_A1 ||
   2595  1.206   msaitoh 		    sc->bge_chipid == BGE_CHIPID_BCM5906_A2)
   2596  1.206   msaitoh 			CSR_WRITE_4(sc, BGE_ISO_PKT_TX,
   2597  1.206   msaitoh 			    (CSR_READ_4(sc, BGE_ISO_PKT_TX) & ~3) | 2);
   2598  1.206   msaitoh 	}
   2599  1.236   msaitoh 	/* 5718 step 14, 57XX step 44 */
   2600  1.158   msaitoh 	/*
   2601  1.222   msaitoh 	 * The BD ring replenish thresholds control how often the
   2602  1.222   msaitoh 	 * hardware fetches new BD's from the producer rings in host
   2603  1.222   msaitoh 	 * memory.  Setting the value too low on a busy system can
   2604  1.222   msaitoh 	 * starve the hardware and recue the throughpout.
   2605  1.222   msaitoh 	 *
   2606  1.158   msaitoh 	 * Set the BD ring replenish thresholds. The recommended
   2607  1.158   msaitoh 	 * values are 1/8th the number of descriptors allocated to
   2608  1.222   msaitoh 	 * each ring, but since we try to avoid filling the entire
   2609  1.222   msaitoh 	 * ring we set these to the minimal value of 8.  This needs to
   2610  1.222   msaitoh 	 * be done on several of the supported chip revisions anyway,
   2611  1.222   msaitoh 	 * to work around HW bugs.
   2612  1.158   msaitoh 	 */
   2613  1.222   msaitoh 	CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, 8);
   2614  1.222   msaitoh 	if (BGE_IS_JUMBO_CAPABLE(sc))
   2615  1.222   msaitoh 		CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH, 8);
   2616  1.157   msaitoh 
   2617  1.236   msaitoh 	/* 5718 step 18 */
   2618  1.216   msaitoh 	if (BGE_IS_5717_PLUS(sc)) {
   2619  1.172   msaitoh 		CSR_WRITE_4(sc, BGE_STD_REPL_LWM, 4);
   2620  1.172   msaitoh 		CSR_WRITE_4(sc, BGE_JUMBO_REPL_LWM, 4);
   2621  1.172   msaitoh 	}
   2622  1.172   msaitoh 
   2623  1.236   msaitoh 	/* 57XX step 45 */
   2624  1.158   msaitoh 	/*
   2625  1.222   msaitoh 	 * Disable all send rings by setting the 'ring disabled' bit
   2626  1.222   msaitoh 	 * in the flags field of all the TX send ring control blocks,
   2627  1.222   msaitoh 	 * located in NIC memory.
   2628  1.158   msaitoh 	 */
   2629  1.222   msaitoh 	if (BGE_IS_5700_FAMILY(sc)) {
   2630  1.222   msaitoh 		/* 5700 to 5704 had 16 send rings. */
   2631  1.222   msaitoh 		limit = BGE_TX_RINGS_EXTSSRAM_MAX;
   2632  1.258   msaitoh 	} else if (BGE_IS_5717_PLUS(sc)) {
   2633  1.258   msaitoh 		limit = BGE_TX_RINGS_5717_MAX;
   2634  1.327   msaitoh 	} else if (BGE_IS_57765_FAMILY(sc) ||
   2635  1.327   msaitoh 	    BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5762) {
   2636  1.258   msaitoh 		limit = BGE_TX_RINGS_57765_MAX;
   2637  1.222   msaitoh 	} else
   2638  1.222   msaitoh 		limit = 1;
   2639  1.158   msaitoh 	rcb_addr = BGE_MEMWIN_START + BGE_SEND_RING_RCB;
   2640  1.222   msaitoh 	for (i = 0; i < limit; i++) {
   2641  1.158   msaitoh 		RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags,
   2642  1.158   msaitoh 		    BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED));
   2643  1.158   msaitoh 		RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 0);
   2644  1.158   msaitoh 		rcb_addr += sizeof(struct bge_rcb);
   2645  1.158   msaitoh 	}
   2646  1.157   msaitoh 
   2647  1.236   msaitoh 	/* 57XX step 46 and 47 */
   2648  1.222   msaitoh 	/* Configure send ring RCB 0 (we use only the first ring) */
   2649  1.158   msaitoh 	rcb_addr = BGE_MEMWIN_START + BGE_SEND_RING_RCB;
   2650  1.172   msaitoh 	BGE_HOSTADDR(taddr, BGE_RING_DMA_ADDR(sc, bge_tx_ring));
   2651  1.158   msaitoh 	RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi);
   2652  1.158   msaitoh 	RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo);
   2653  1.216   msaitoh 	if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5717 ||
   2654  1.216   msaitoh 	    BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719 ||
   2655  1.216   msaitoh 	    BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720)
   2656  1.216   msaitoh 		RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, BGE_SEND_RING_5717);
   2657  1.216   msaitoh 	else
   2658  1.216   msaitoh 		RCB_WRITE_4(sc, rcb_addr, bge_nicaddr,
   2659  1.158   msaitoh 		    BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT));
   2660  1.222   msaitoh 	RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags,
   2661  1.222   msaitoh 	    BGE_RCB_MAXLEN_FLAGS(BGE_TX_RING_CNT, 0));
   2662  1.157   msaitoh 
   2663  1.236   msaitoh 	/* 57XX step 48 */
   2664  1.222   msaitoh 	/*
   2665  1.222   msaitoh 	 * Disable all receive return rings by setting the
   2666  1.222   msaitoh 	 * 'ring diabled' bit in the flags field of all the receive
   2667  1.222   msaitoh 	 * return ring control blocks, located in NIC memory.
   2668  1.222   msaitoh 	 */
   2669  1.257   msaitoh 	if (BGE_IS_5717_PLUS(sc)) {
   2670  1.222   msaitoh 		/* Should be 17, use 16 until we get an SRAM map. */
   2671  1.222   msaitoh 		limit = 16;
   2672  1.222   msaitoh 	} else if (BGE_IS_5700_FAMILY(sc))
   2673  1.222   msaitoh 		limit = BGE_RX_RINGS_MAX;
   2674  1.222   msaitoh 	else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5755 ||
   2675  1.327   msaitoh 	    BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5762 ||
   2676  1.257   msaitoh 	    BGE_IS_57765_FAMILY(sc))
   2677  1.222   msaitoh 		limit = 4;
   2678  1.222   msaitoh 	else
   2679  1.222   msaitoh 		limit = 1;
   2680  1.222   msaitoh 	/* Disable all receive return rings */
   2681  1.158   msaitoh 	rcb_addr = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB;
   2682  1.222   msaitoh 	for (i = 0; i < limit; i++) {
   2683  1.158   msaitoh 		RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_hi, 0);
   2684  1.158   msaitoh 		RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_lo, 0);
   2685  1.158   msaitoh 		RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags,
   2686  1.172   msaitoh 		    BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt,
   2687  1.172   msaitoh 			BGE_RCB_FLAG_RING_DISABLED));
   2688  1.158   msaitoh 		RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 0);
   2689  1.158   msaitoh 		bge_writembx(sc, BGE_MBX_RX_CONS0_LO +
   2690  1.170   msaitoh 		    (i * (sizeof(uint64_t))), 0);
   2691  1.158   msaitoh 		rcb_addr += sizeof(struct bge_rcb);
   2692  1.158   msaitoh 	}
   2693  1.157   msaitoh 
   2694  1.236   msaitoh 	/* 57XX step 49 */
   2695  1.158   msaitoh 	/*
   2696  1.222   msaitoh 	 * Set up receive return ring 0.  Note that the NIC address
   2697  1.222   msaitoh 	 * for RX return rings is 0x0.  The return rings live entirely
   2698  1.222   msaitoh 	 * within the host, so the nicaddr field in the RCB isn't used.
   2699  1.158   msaitoh 	 */
   2700  1.158   msaitoh 	rcb_addr = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB;
   2701  1.172   msaitoh 	BGE_HOSTADDR(taddr, BGE_RING_DMA_ADDR(sc, bge_rx_return_ring));
   2702  1.158   msaitoh 	RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi);
   2703  1.158   msaitoh 	RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo);
   2704  1.158   msaitoh 	RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 0x00000000);
   2705  1.158   msaitoh 	RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags,
   2706  1.158   msaitoh 	    BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 0));
   2707  1.157   msaitoh 
   2708  1.236   msaitoh 	/* 5718 step 24, 57XX step 53 */
   2709  1.158   msaitoh 	/* Set random backoff seed for TX */
   2710  1.158   msaitoh 	CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF,
   2711  1.235   msaitoh 	    (CLLADDR(ifp->if_sadl)[0] + CLLADDR(ifp->if_sadl)[1] +
   2712  1.235   msaitoh 		CLLADDR(ifp->if_sadl)[2] + CLLADDR(ifp->if_sadl)[3] +
   2713  1.235   msaitoh 		CLLADDR(ifp->if_sadl)[4] + CLLADDR(ifp->if_sadl)[5]) &
   2714  1.158   msaitoh 	    BGE_TX_BACKOFF_SEED_MASK);
   2715  1.157   msaitoh 
   2716  1.236   msaitoh 	/* 5718 step 26, 57XX step 55 */
   2717  1.158   msaitoh 	/* Set inter-packet gap */
   2718  1.216   msaitoh 	val = 0x2620;
   2719  1.327   msaitoh 	if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720 ||
   2720  1.327   msaitoh 	    BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5762)
   2721  1.216   msaitoh 		val |= CSR_READ_4(sc, BGE_TX_LENGTHS) &
   2722  1.216   msaitoh 		    (BGE_TXLEN_JMB_FRM_LEN_MSK | BGE_TXLEN_CNT_DN_VAL_MSK);
   2723  1.216   msaitoh 	CSR_WRITE_4(sc, BGE_TX_LENGTHS, val);
   2724   1.51      fvdl 
   2725  1.236   msaitoh 	/* 5718 step 27, 57XX step 56 */
   2726  1.158   msaitoh 	/*
   2727  1.158   msaitoh 	 * Specify which ring to use for packets that don't match
   2728  1.158   msaitoh 	 * any RX rules.
   2729  1.158   msaitoh 	 */
   2730  1.158   msaitoh 	CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08);
   2731  1.157   msaitoh 
   2732  1.236   msaitoh 	/* 5718 step 28, 57XX step 57 */
   2733  1.158   msaitoh 	/*
   2734  1.158   msaitoh 	 * Configure number of RX lists. One interrupt distribution
   2735  1.158   msaitoh 	 * list, sixteen active lists, one bad frames class.
   2736  1.158   msaitoh 	 */
   2737  1.158   msaitoh 	CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181);
   2738  1.157   msaitoh 
   2739  1.236   msaitoh 	/* 5718 step 29, 57XX step 58 */
   2740  1.158   msaitoh 	/* Inialize RX list placement stats mask. */
   2741  1.244   msaitoh 	if (BGE_IS_575X_PLUS(sc)) {
   2742  1.244   msaitoh 		val = CSR_READ_4(sc, BGE_RXLP_STATS_ENABLE_MASK);
   2743  1.244   msaitoh 		val &= ~BGE_RXLPSTATCONTROL_DACK_FIX;
   2744  1.244   msaitoh 		CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, val);
   2745  1.244   msaitoh 	} else
   2746  1.244   msaitoh 		CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF);
   2747  1.244   msaitoh 
   2748  1.236   msaitoh 	/* 5718 step 30, 57XX step 59 */
   2749  1.158   msaitoh 	CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1);
   2750  1.157   msaitoh 
   2751  1.236   msaitoh 	/* 5718 step 33, 57XX step 62 */
   2752  1.158   msaitoh 	/* Disable host coalescing until we get it set up */
   2753  1.158   msaitoh 	CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000);
   2754   1.51      fvdl 
   2755  1.236   msaitoh 	/* 5718 step 34, 57XX step 63 */
   2756  1.158   msaitoh 	/* Poll to make sure it's shut down. */
   2757  1.172   msaitoh 	for (i = 0; i < BGE_TIMEOUT * 2; i++) {
   2758  1.216   msaitoh 		DELAY(10);
   2759  1.158   msaitoh 		if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE))
   2760  1.158   msaitoh 			break;
   2761  1.158   msaitoh 	}
   2762  1.151    cegger 
   2763  1.172   msaitoh 	if (i == BGE_TIMEOUT * 2) {
   2764  1.158   msaitoh 		aprint_error_dev(sc->bge_dev,
   2765  1.158   msaitoh 		    "host coalescing engine failed to idle\n");
   2766  1.170   msaitoh 		return ENXIO;
   2767  1.158   msaitoh 	}
   2768   1.51      fvdl 
   2769  1.236   msaitoh 	/* 5718 step 35, 36, 37 */
   2770  1.158   msaitoh 	/* Set up host coalescing defaults */
   2771  1.158   msaitoh 	CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bge_rx_coal_ticks);
   2772  1.158   msaitoh 	CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bge_tx_coal_ticks);
   2773  1.158   msaitoh 	CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bge_rx_max_coal_bds);
   2774  1.158   msaitoh 	CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bge_tx_max_coal_bds);
   2775  1.216   msaitoh 	if (!(BGE_IS_5705_PLUS(sc))) {
   2776  1.158   msaitoh 		CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT, 0);
   2777  1.158   msaitoh 		CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT, 0);
   2778   1.51      fvdl 	}
   2779  1.158   msaitoh 	CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 0);
   2780  1.158   msaitoh 	CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 0);
   2781   1.51      fvdl 
   2782  1.158   msaitoh 	/* Set up address of statistics block */
   2783  1.172   msaitoh 	if (BGE_IS_5700_FAMILY(sc)) {
   2784  1.172   msaitoh 		BGE_HOSTADDR(taddr, BGE_RING_DMA_ADDR(sc, bge_info.bge_stats));
   2785  1.158   msaitoh 		CSR_WRITE_4(sc, BGE_HCC_STATS_TICKS, sc->bge_stat_ticks);
   2786  1.158   msaitoh 		CSR_WRITE_4(sc, BGE_HCC_STATS_BASEADDR, BGE_STATS_BLOCK);
   2787  1.158   msaitoh 		CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_HI, taddr.bge_addr_hi);
   2788  1.158   msaitoh 		CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_LO, taddr.bge_addr_lo);
   2789   1.16   thorpej 	}
   2790   1.16   thorpej 
   2791  1.236   msaitoh 	/* 5718 step 38 */
   2792  1.158   msaitoh 	/* Set up address of status block */
   2793  1.172   msaitoh 	BGE_HOSTADDR(taddr, BGE_RING_DMA_ADDR(sc, bge_status_block));
   2794  1.158   msaitoh 	CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_BASEADDR, BGE_STATUS_BLOCK);
   2795  1.158   msaitoh 	CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI, taddr.bge_addr_hi);
   2796  1.158   msaitoh 	CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO, taddr.bge_addr_lo);
   2797  1.158   msaitoh 	sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx = 0;
   2798  1.158   msaitoh 	sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx = 0;
   2799   1.16   thorpej 
   2800  1.216   msaitoh 	/* Set up status block size. */
   2801  1.216   msaitoh 	if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 &&
   2802  1.216   msaitoh 	    sc->bge_chipid != BGE_CHIPID_BCM5700_C0) {
   2803  1.216   msaitoh 		val = BGE_STATBLKSZ_FULL;
   2804  1.216   msaitoh 		bzero(&sc->bge_rdata->bge_status_block, BGE_STATUS_BLK_SZ);
   2805  1.216   msaitoh 	} else {
   2806  1.216   msaitoh 		val = BGE_STATBLKSZ_32BYTE;
   2807  1.216   msaitoh 		bzero(&sc->bge_rdata->bge_status_block, 32);
   2808  1.216   msaitoh 	}
   2809  1.216   msaitoh 
   2810  1.236   msaitoh 	/* 5718 step 39, 57XX step 73 */
   2811  1.158   msaitoh 	/* Turn on host coalescing state machine */
   2812  1.216   msaitoh 	CSR_WRITE_4(sc, BGE_HCC_MODE, val | BGE_HCCMODE_ENABLE);
   2813    1.7   thorpej 
   2814  1.236   msaitoh 	/* 5718 step 40, 57XX step 74 */
   2815  1.158   msaitoh 	/* Turn on RX BD completion state machine and enable attentions */
   2816  1.158   msaitoh 	CSR_WRITE_4(sc, BGE_RBDC_MODE,
   2817  1.161   msaitoh 	    BGE_RBDCMODE_ENABLE | BGE_RBDCMODE_ATTN);
   2818    1.7   thorpej 
   2819  1.236   msaitoh 	/* 5718 step 41, 57XX step 75 */
   2820  1.158   msaitoh 	/* Turn on RX list placement state machine */
   2821  1.158   msaitoh 	CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);
   2822   1.51      fvdl 
   2823  1.236   msaitoh 	/* 57XX step 76 */
   2824  1.158   msaitoh 	/* Turn on RX list selector state machine. */
   2825  1.216   msaitoh 	if (!(BGE_IS_5705_PLUS(sc)))
   2826  1.158   msaitoh 		CSR_WRITE_4(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE);
   2827   1.51      fvdl 
   2828  1.161   msaitoh 	val = BGE_MACMODE_TXDMA_ENB | BGE_MACMODE_RXDMA_ENB |
   2829  1.161   msaitoh 	    BGE_MACMODE_RX_STATS_CLEAR | BGE_MACMODE_TX_STATS_CLEAR |
   2830  1.161   msaitoh 	    BGE_MACMODE_RX_STATS_ENB | BGE_MACMODE_TX_STATS_ENB |
   2831  1.161   msaitoh 	    BGE_MACMODE_FRMHDR_DMA_ENB;
   2832  1.161   msaitoh 
   2833  1.261   msaitoh 	if (sc->bge_flags & BGEF_FIBER_TBI)
   2834  1.177   msaitoh 		val |= BGE_PORTMODE_TBI;
   2835  1.261   msaitoh 	else if (sc->bge_flags & BGEF_FIBER_MII)
   2836  1.177   msaitoh 		val |= BGE_PORTMODE_GMII;
   2837  1.161   msaitoh 	else
   2838  1.177   msaitoh 		val |= BGE_PORTMODE_MII;
   2839  1.161   msaitoh 
   2840  1.236   msaitoh 	/* 5718 step 42 and 43, 57XX step 77 and 78 */
   2841  1.216   msaitoh 	/* Allow APE to send/receive frames. */
   2842  1.216   msaitoh 	if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) != 0)
   2843  1.216   msaitoh 		val |= BGE_MACMODE_APE_RX_EN | BGE_MACMODE_APE_TX_EN;
   2844  1.216   msaitoh 
   2845  1.158   msaitoh 	/* Turn on DMA, clear stats */
   2846  1.211   msaitoh 	CSR_WRITE_4_FLUSH(sc, BGE_MAC_MODE, val);
   2847  1.236   msaitoh 	/* 5718 step 44 */
   2848  1.211   msaitoh 	DELAY(40);
   2849  1.161   msaitoh 
   2850  1.236   msaitoh 	/* 5718 step 45, 57XX step 79 */
   2851  1.158   msaitoh 	/* Set misc. local control, enable interrupts on attentions */
   2852  1.251   msaitoh 	BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_ONATTN);
   2853  1.224   msaitoh 	if (BGE_IS_5717_PLUS(sc)) {
   2854  1.224   msaitoh 		CSR_READ_4(sc, BGE_MISC_LOCAL_CTL); /* Flush */
   2855  1.236   msaitoh 		/* 5718 step 46 */
   2856  1.224   msaitoh 		DELAY(100);
   2857  1.224   msaitoh 	}
   2858   1.80     fredb 
   2859  1.236   msaitoh 	/* 57XX step 81 */
   2860  1.158   msaitoh 	/* Turn on DMA completion state machine */
   2861  1.216   msaitoh 	if (!(BGE_IS_5705_PLUS(sc)))
   2862  1.158   msaitoh 		CSR_WRITE_4(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE);
   2863  1.149  sborrill 
   2864  1.236   msaitoh 	/* 5718 step 47, 57XX step 82 */
   2865  1.203   msaitoh 	val = BGE_WDMAMODE_ENABLE | BGE_WDMAMODE_ALL_ATTNS;
   2866  1.203   msaitoh 
   2867  1.236   msaitoh 	/* 5718 step 48 */
   2868  1.216   msaitoh 	/* Enable host coalescing bug fix. */
   2869  1.203   msaitoh 	if (BGE_IS_5755_PLUS(sc))
   2870  1.203   msaitoh 		val |= BGE_WDMAMODE_STATUS_TAG_FIX;
   2871  1.203   msaitoh 
   2872  1.206   msaitoh 	if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785)
   2873  1.206   msaitoh 		val |= BGE_WDMAMODE_BURST_ALL_DATA;
   2874  1.206   msaitoh 
   2875  1.158   msaitoh 	/* Turn on write DMA state machine */
   2876  1.213   msaitoh 	CSR_WRITE_4_FLUSH(sc, BGE_WDMA_MODE, val);
   2877  1.236   msaitoh 	/* 5718 step 49 */
   2878  1.213   msaitoh 	DELAY(40);
   2879  1.203   msaitoh 
   2880  1.203   msaitoh 	val = BGE_RDMAMODE_ENABLE | BGE_RDMAMODE_ALL_ATTNS;
   2881  1.216   msaitoh 
   2882  1.216   msaitoh 	if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5717)
   2883  1.216   msaitoh 		val |= BGE_RDMAMODE_MULT_DMA_RD_DIS;
   2884  1.216   msaitoh 
   2885  1.203   msaitoh 	if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5784 ||
   2886  1.203   msaitoh 	    BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785 ||
   2887  1.203   msaitoh 	    BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57780)
   2888  1.203   msaitoh 		val |= BGE_RDMAMODE_BD_SBD_CRPT_ATTN |
   2889  1.203   msaitoh 		    BGE_RDMAMODE_MBUF_RBD_CRPT_ATTN |
   2890  1.203   msaitoh 		    BGE_RDMAMODE_MBUF_SBD_CRPT_ATTN;
   2891   1.76      cube 
   2892  1.261   msaitoh 	if (sc->bge_flags & BGEF_PCIE)
   2893  1.204   msaitoh 		val |= BGE_RDMAMODE_FIFO_LONG_BURST;
   2894  1.258   msaitoh 	if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57766) {
   2895  1.258   msaitoh 		if (ifp->if_mtu <= ETHERMTU)
   2896  1.258   msaitoh 			val |= BGE_RDMAMODE_JMB_2K_MMRR;
   2897  1.258   msaitoh 	}
   2898  1.316    bouyer 	if (sc->bge_flags & BGEF_TSO) {
   2899  1.203   msaitoh 		val |= BGE_RDMAMODE_TSO4_ENABLE;
   2900  1.316    bouyer 		if (BGE_IS_5717_PLUS(sc))
   2901  1.316    bouyer 			val |= BGE_RDMAMODE_TSO6_ENABLE;
   2902  1.316    bouyer 	}
   2903   1.76      cube 
   2904  1.327   msaitoh 	if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720 ||
   2905  1.327   msaitoh 	    BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5762) {
   2906  1.216   msaitoh 		val |= CSR_READ_4(sc, BGE_RDMA_MODE) &
   2907  1.216   msaitoh 		    BGE_RDMAMODE_H2BNC_VLAN_DET;
   2908  1.216   msaitoh 		/*
   2909  1.216   msaitoh 		 * Allow multiple outstanding read requests from
   2910  1.216   msaitoh 		 * non-LSO read DMA engine.
   2911  1.216   msaitoh 		 */
   2912  1.216   msaitoh 		val &= ~BGE_RDMAMODE_MULT_DMA_RD_DIS;
   2913  1.216   msaitoh 	}
   2914  1.216   msaitoh 
   2915  1.216   msaitoh 	if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761 ||
   2916  1.216   msaitoh 	    BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5784 ||
   2917  1.216   msaitoh 	    BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785 ||
   2918  1.216   msaitoh 	    BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57780 ||
   2919  1.257   msaitoh 	    BGE_IS_57765_PLUS(sc)) {
   2920  1.327   msaitoh 		if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5762)
   2921  1.327   msaitoh 			rdmareg = BGE_RDMA_RSRVCTRL_REG2;
   2922  1.327   msaitoh 		else
   2923  1.327   msaitoh 			rdmareg = BGE_RDMA_RSRVCTRL;
   2924  1.327   msaitoh 		dmactl = CSR_READ_4(sc, rdmareg);
   2925  1.216   msaitoh 		/*
   2926  1.216   msaitoh 		 * Adjust tx margin to prevent TX data corruption and
   2927  1.216   msaitoh 		 * fix internal FIFO overflow.
   2928  1.216   msaitoh 		 */
   2929  1.327   msaitoh 		if (sc->bge_chipid == BGE_CHIPID_BCM5719_A0 ||
   2930  1.327   msaitoh 		    BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5762) {
   2931  1.216   msaitoh 			dmactl &= ~(BGE_RDMA_RSRVCTRL_FIFO_LWM_MASK |
   2932  1.216   msaitoh 			    BGE_RDMA_RSRVCTRL_FIFO_HWM_MASK |
   2933  1.216   msaitoh 			    BGE_RDMA_RSRVCTRL_TXMRGN_MASK);
   2934  1.216   msaitoh 			dmactl |= BGE_RDMA_RSRVCTRL_FIFO_LWM_1_5K |
   2935  1.216   msaitoh 			    BGE_RDMA_RSRVCTRL_FIFO_HWM_1_5K |
   2936  1.216   msaitoh 			    BGE_RDMA_RSRVCTRL_TXMRGN_320B;
   2937  1.216   msaitoh 		}
   2938  1.216   msaitoh 		/*
   2939  1.216   msaitoh 		 * Enable fix for read DMA FIFO overruns.
   2940  1.216   msaitoh 		 * The fix is to limit the number of RX BDs
   2941  1.349    andvar 		 * the hardware would fetch at a time.
   2942  1.216   msaitoh 		 */
   2943  1.327   msaitoh 		CSR_WRITE_4(sc, rdmareg, dmactl |
   2944  1.216   msaitoh 		    BGE_RDMA_RSRVCTRL_FIFO_OFLW_FIX);
   2945  1.216   msaitoh 	}
   2946  1.216   msaitoh 
   2947  1.216   msaitoh 	if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719) {
   2948  1.216   msaitoh 		CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL,
   2949  1.216   msaitoh 		    CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL) |
   2950  1.216   msaitoh 		    BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_4K |
   2951  1.216   msaitoh 		    BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K);
   2952  1.216   msaitoh 	} else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) {
   2953  1.216   msaitoh 		/*
   2954  1.216   msaitoh 		 * Allow 4KB burst length reads for non-LSO frames.
   2955  1.216   msaitoh 		 * Enable 512B burst length reads for buffer descriptors.
   2956  1.216   msaitoh 		 */
   2957  1.216   msaitoh 		CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL,
   2958  1.216   msaitoh 		    CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL) |
   2959  1.216   msaitoh 		    BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_512 |
   2960  1.216   msaitoh 		    BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K);
   2961  1.327   msaitoh 	} else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5762) {
   2962  1.327   msaitoh 		CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL_REG2,
   2963  1.327   msaitoh 		    CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL_REG2) |
   2964  1.327   msaitoh 		    BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_4K |
   2965  1.327   msaitoh 		    BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K);
   2966  1.216   msaitoh 	}
   2967  1.158   msaitoh 	/* Turn on read DMA state machine */
   2968  1.211   msaitoh 	CSR_WRITE_4_FLUSH(sc, BGE_RDMA_MODE, val);
   2969  1.236   msaitoh 	/* 5718 step 52 */
   2970  1.203   msaitoh 	delay(40);
   2971  1.128      tron 
   2972  1.327   msaitoh 	if (sc->bge_flags & BGEF_RDMA_BUG) {
   2973  1.320    bouyer 		for (i = 0; i < BGE_NUM_RDMA_CHANNELS / 2; i++) {
   2974  1.320    bouyer 			val = CSR_READ_4(sc, BGE_RDMA_LENGTH + i * 4);
   2975  1.320    bouyer 			if ((val & 0xFFFF) > BGE_FRAMELEN)
   2976  1.320    bouyer 				break;
   2977  1.320    bouyer 			if (((val >> 16) & 0xFFFF) > BGE_FRAMELEN)
   2978  1.320    bouyer 				break;
   2979  1.320    bouyer 		}
   2980  1.320    bouyer 		if (i != BGE_NUM_RDMA_CHANNELS / 2) {
   2981  1.320    bouyer 			val = CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL);
   2982  1.320    bouyer 			if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719)
   2983  1.320    bouyer 				val |= BGE_RDMA_TX_LENGTH_WA_5719;
   2984  1.320    bouyer 			else
   2985  1.320    bouyer 				val |= BGE_RDMA_TX_LENGTH_WA_5720;
   2986  1.320    bouyer 			CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL, val);
   2987  1.320    bouyer 		}
   2988  1.320    bouyer 	}
   2989  1.320    bouyer 
   2990  1.236   msaitoh 	/* 5718 step 56, 57XX step 84 */
   2991  1.158   msaitoh 	/* Turn on RX data completion state machine */
   2992  1.158   msaitoh 	CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);
   2993  1.128      tron 
   2994  1.158   msaitoh 	/* Turn on RX data and RX BD initiator state machine */
   2995  1.158   msaitoh 	CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE);
   2996  1.133     markd 
   2997  1.236   msaitoh 	/* 57XX step 85 */
   2998  1.158   msaitoh 	/* Turn on Mbuf cluster free state machine */
   2999  1.216   msaitoh 	if (!BGE_IS_5705_PLUS(sc))
   3000  1.158   msaitoh 		CSR_WRITE_4(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE);
   3001  1.133     markd 
   3002  1.236   msaitoh 	/* 5718 step 57, 57XX step 86 */
   3003  1.158   msaitoh 	/* Turn on send data completion state machine */
   3004  1.172   msaitoh 	val = BGE_SDCMODE_ENABLE;
   3005  1.172   msaitoh 	if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761)
   3006  1.172   msaitoh 		val |= BGE_SDCMODE_CDELAY;
   3007  1.172   msaitoh 	CSR_WRITE_4(sc, BGE_SDC_MODE, val);
   3008  1.106  jonathan 
   3009  1.236   msaitoh 	/* 5718 step 58 */
   3010  1.225   msaitoh 	/* Turn on send BD completion state machine */
   3011  1.225   msaitoh 	CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);
   3012  1.225   msaitoh 
   3013  1.236   msaitoh 	/* 57XX step 88 */
   3014  1.225   msaitoh 	/* Turn on RX BD initiator state machine */
   3015  1.225   msaitoh 	CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE);
   3016  1.225   msaitoh 
   3017  1.236   msaitoh 	/* 5718 step 60, 57XX step 90 */
   3018  1.158   msaitoh 	/* Turn on send data initiator state machine */
   3019  1.261   msaitoh 	if (sc->bge_flags & BGEF_TSO) {
   3020  1.158   msaitoh 		/* XXX: magic value from Linux driver */
   3021  1.222   msaitoh 		CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE |
   3022  1.222   msaitoh 		    BGE_SDIMODE_HW_LSO_PRE_DMA);
   3023  1.177   msaitoh 	} else
   3024  1.158   msaitoh 		CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE);
   3025  1.106  jonathan 
   3026  1.236   msaitoh 	/* 5718 step 61, 57XX step 91 */
   3027  1.158   msaitoh 	/* Turn on send BD initiator state machine */
   3028  1.158   msaitoh 	CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE);
   3029  1.133     markd 
   3030  1.236   msaitoh 	/* 5718 step 62, 57XX step 92 */
   3031  1.158   msaitoh 	/* Turn on send BD selector state machine */
   3032  1.158   msaitoh 	CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE);
   3033  1.135      taca 
   3034  1.236   msaitoh 	/* 5718 step 31, 57XX step 60 */
   3035  1.158   msaitoh 	CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF);
   3036  1.236   msaitoh 	/* 5718 step 32, 57XX step 61 */
   3037  1.158   msaitoh 	CSR_WRITE_4(sc, BGE_SDI_STATS_CTL,
   3038  1.161   msaitoh 	    BGE_SDISTATSCTL_ENABLE | BGE_SDISTATSCTL_FASTER);
   3039  1.133     markd 
   3040  1.158   msaitoh 	/* ack/clear link change events */
   3041  1.161   msaitoh 	CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
   3042  1.161   msaitoh 	    BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE |
   3043  1.172   msaitoh 	    BGE_MACSTAT_LINK_CHANGED);
   3044  1.158   msaitoh 	CSR_WRITE_4(sc, BGE_MI_STS, 0);
   3045  1.106  jonathan 
   3046  1.216   msaitoh 	/*
   3047  1.216   msaitoh 	 * Enable attention when the link has changed state for
   3048  1.216   msaitoh 	 * devices that use auto polling.
   3049  1.216   msaitoh 	 */
   3050  1.261   msaitoh 	if (sc->bge_flags & BGEF_FIBER_TBI) {
   3051  1.158   msaitoh 		CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK);
   3052  1.178   msaitoh 	} else {
   3053  1.272   msaitoh 		if ((sc->bge_flags & BGEF_CPMU_PRESENT) != 0)
   3054  1.272   msaitoh 			mimode = BGE_MIMODE_500KHZ_CONST;
   3055  1.272   msaitoh 		else
   3056  1.272   msaitoh 			mimode = BGE_MIMODE_BASE;
   3057  1.272   msaitoh 		/* 5718 step 68. 5718 step 69 (optionally). */
   3058  1.272   msaitoh 		if (BGE_IS_5700_FAMILY(sc) ||
   3059  1.272   msaitoh 		    BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5705) {
   3060  1.272   msaitoh 			mimode |= BGE_MIMODE_AUTOPOLL;
   3061  1.272   msaitoh 			BGE_STS_SETBIT(sc, BGE_STS_AUTOPOLL);
   3062  1.272   msaitoh 		}
   3063  1.272   msaitoh 		mimode |= BGE_MIMODE_PHYADDR(sc->bge_phy_addr);
   3064  1.272   msaitoh 		CSR_WRITE_4(sc, BGE_MI_MODE, mimode);
   3065  1.158   msaitoh 		if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700)
   3066  1.158   msaitoh 			CSR_WRITE_4(sc, BGE_MAC_EVT_ENB,
   3067  1.158   msaitoh 			    BGE_EVTENB_MI_INTERRUPT);
   3068  1.158   msaitoh 	}
   3069   1.70      tron 
   3070  1.161   msaitoh 	/*
   3071  1.161   msaitoh 	 * Clear any pending link state attention.
   3072  1.161   msaitoh 	 * Otherwise some link state change events may be lost until attention
   3073  1.161   msaitoh 	 * is cleared by bge_intr() -> bge_link_upd() sequence.
   3074  1.161   msaitoh 	 * It's not necessary on newer BCM chips - perhaps enabling link
   3075  1.161   msaitoh 	 * state change attentions implies clearing pending attention.
   3076  1.161   msaitoh 	 */
   3077  1.161   msaitoh 	CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
   3078  1.161   msaitoh 	    BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE |
   3079  1.161   msaitoh 	    BGE_MACSTAT_LINK_CHANGED);
   3080  1.161   msaitoh 
   3081  1.158   msaitoh 	/* Enable link state change attentions. */
   3082  1.158   msaitoh 	BGE_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED);
   3083   1.51      fvdl 
   3084  1.170   msaitoh 	return 0;
   3085  1.158   msaitoh }
   3086    1.7   thorpej 
   3087  1.158   msaitoh static const struct bge_revision *
   3088  1.158   msaitoh bge_lookup_rev(uint32_t chipid)
   3089  1.158   msaitoh {
   3090  1.158   msaitoh 	const struct bge_revision *br;
   3091    1.7   thorpej 
   3092  1.158   msaitoh 	for (br = bge_revisions; br->br_name != NULL; br++) {
   3093  1.158   msaitoh 		if (br->br_chipid == chipid)
   3094  1.170   msaitoh 			return br;
   3095  1.158   msaitoh 	}
   3096  1.151    cegger 
   3097  1.158   msaitoh 	for (br = bge_majorrevs; br->br_name != NULL; br++) {
   3098  1.158   msaitoh 		if (br->br_chipid == BGE_ASICREV(chipid))
   3099  1.170   msaitoh 			return br;
   3100  1.158   msaitoh 	}
   3101  1.151    cegger 
   3102  1.170   msaitoh 	return NULL;
   3103  1.158   msaitoh }
   3104    1.7   thorpej 
   3105    1.7   thorpej static const struct bge_product *
   3106    1.7   thorpej bge_lookup(const struct pci_attach_args *pa)
   3107    1.7   thorpej {
   3108    1.7   thorpej 	const struct bge_product *bp;
   3109    1.7   thorpej 
   3110    1.7   thorpej 	for (bp = bge_products; bp->bp_name != NULL; bp++) {
   3111    1.7   thorpej 		if (PCI_VENDOR(pa->pa_id) == bp->bp_vendor &&
   3112    1.7   thorpej 		    PCI_PRODUCT(pa->pa_id) == bp->bp_product)
   3113  1.170   msaitoh 			return bp;
   3114    1.7   thorpej 	}
   3115    1.7   thorpej 
   3116  1.170   msaitoh 	return NULL;
   3117    1.7   thorpej }
   3118    1.7   thorpej 
   3119  1.215   msaitoh static uint32_t
   3120  1.215   msaitoh bge_chipid(const struct pci_attach_args *pa)
   3121  1.215   msaitoh {
   3122  1.215   msaitoh 	uint32_t id;
   3123  1.215   msaitoh 
   3124  1.215   msaitoh 	id = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_MISC_CTL)
   3125  1.215   msaitoh 		>> BGE_PCIMISCCTL_ASICREV_SHIFT;
   3126  1.215   msaitoh 
   3127  1.215   msaitoh 	if (BGE_ASICREV(id) == BGE_ASICREV_USE_PRODID_REG) {
   3128  1.215   msaitoh 		switch (PCI_PRODUCT(pa->pa_id)) {
   3129  1.215   msaitoh 		case PCI_PRODUCT_BROADCOM_BCM5717:
   3130  1.215   msaitoh 		case PCI_PRODUCT_BROADCOM_BCM5718:
   3131  1.216   msaitoh 		case PCI_PRODUCT_BROADCOM_BCM5719:
   3132  1.216   msaitoh 		case PCI_PRODUCT_BROADCOM_BCM5720:
   3133  1.327   msaitoh 		case PCI_PRODUCT_BROADCOM_BCM5725:
   3134  1.327   msaitoh 		case PCI_PRODUCT_BROADCOM_BCM5727:
   3135  1.327   msaitoh 		case PCI_PRODUCT_BROADCOM_BCM5762:
   3136  1.327   msaitoh 		case PCI_PRODUCT_BROADCOM_BCM57764:
   3137  1.327   msaitoh 		case PCI_PRODUCT_BROADCOM_BCM57767:
   3138  1.327   msaitoh 		case PCI_PRODUCT_BROADCOM_BCM57787:
   3139  1.215   msaitoh 			id = pci_conf_read(pa->pa_pc, pa->pa_tag,
   3140  1.215   msaitoh 			    BGE_PCI_GEN2_PRODID_ASICREV);
   3141  1.215   msaitoh 			break;
   3142  1.215   msaitoh 		case PCI_PRODUCT_BROADCOM_BCM57761:
   3143  1.215   msaitoh 		case PCI_PRODUCT_BROADCOM_BCM57762:
   3144  1.215   msaitoh 		case PCI_PRODUCT_BROADCOM_BCM57765:
   3145  1.215   msaitoh 		case PCI_PRODUCT_BROADCOM_BCM57766:
   3146  1.215   msaitoh 		case PCI_PRODUCT_BROADCOM_BCM57781:
   3147  1.305   msaitoh 		case PCI_PRODUCT_BROADCOM_BCM57782:
   3148  1.215   msaitoh 		case PCI_PRODUCT_BROADCOM_BCM57785:
   3149  1.305   msaitoh 		case PCI_PRODUCT_BROADCOM_BCM57786:
   3150  1.215   msaitoh 		case PCI_PRODUCT_BROADCOM_BCM57791:
   3151  1.215   msaitoh 		case PCI_PRODUCT_BROADCOM_BCM57795:
   3152  1.215   msaitoh 			id = pci_conf_read(pa->pa_pc, pa->pa_tag,
   3153  1.215   msaitoh 			    BGE_PCI_GEN15_PRODID_ASICREV);
   3154  1.215   msaitoh 			break;
   3155  1.215   msaitoh 		default:
   3156  1.215   msaitoh 			id = pci_conf_read(pa->pa_pc, pa->pa_tag,
   3157  1.215   msaitoh 			    BGE_PCI_PRODID_ASICREV);
   3158  1.215   msaitoh 			break;
   3159  1.215   msaitoh 		}
   3160  1.215   msaitoh 	}
   3161  1.215   msaitoh 
   3162  1.215   msaitoh 	return id;
   3163  1.215   msaitoh }
   3164   1.25  jonathan 
   3165    1.1      fvdl /*
   3166  1.288   msaitoh  * Return true if MSI can be used with this device.
   3167  1.288   msaitoh  */
   3168  1.288   msaitoh static int
   3169  1.288   msaitoh bge_can_use_msi(struct bge_softc *sc)
   3170  1.288   msaitoh {
   3171  1.288   msaitoh 	int can_use_msi = 0;
   3172  1.288   msaitoh 
   3173  1.288   msaitoh 	switch (BGE_ASICREV(sc->bge_chipid)) {
   3174  1.288   msaitoh 	case BGE_ASICREV_BCM5714_A0:
   3175  1.288   msaitoh 	case BGE_ASICREV_BCM5714:
   3176  1.288   msaitoh 		/*
   3177  1.288   msaitoh 		 * Apparently, MSI doesn't work when these chips are
   3178  1.288   msaitoh 		 * configured in single-port mode.
   3179  1.288   msaitoh 		 */
   3180  1.288   msaitoh 		break;
   3181  1.288   msaitoh 	case BGE_ASICREV_BCM5750:
   3182  1.288   msaitoh 		if (BGE_CHIPREV(sc->bge_chipid) != BGE_CHIPREV_5750_AX &&
   3183  1.288   msaitoh 		    BGE_CHIPREV(sc->bge_chipid) != BGE_CHIPREV_5750_BX)
   3184  1.288   msaitoh 			can_use_msi = 1;
   3185  1.288   msaitoh 		break;
   3186  1.288   msaitoh 	default:
   3187  1.288   msaitoh 		if (BGE_IS_575X_PLUS(sc))
   3188  1.288   msaitoh 			can_use_msi = 1;
   3189  1.288   msaitoh 	}
   3190  1.362     skrll 	return can_use_msi;
   3191  1.288   msaitoh }
   3192  1.288   msaitoh 
   3193  1.288   msaitoh /*
   3194    1.1      fvdl  * Probe for a Broadcom chip. Check the PCI vendor and device IDs
   3195    1.1      fvdl  * against our list and return its name if we find a match. Note
   3196    1.1      fvdl  * that since the Broadcom controller contains VPD support, we
   3197    1.1      fvdl  * can get the device name string from the controller itself instead
   3198    1.1      fvdl  * of the compiled-in string. This is a little slow, but it guarantees
   3199    1.1      fvdl  * we'll always announce the right product name.
   3200    1.1      fvdl  */
   3201  1.104   thorpej static int
   3202  1.116  christos bge_probe(device_t parent, cfdata_t match, void *aux)
   3203    1.1      fvdl {
   3204    1.1      fvdl 	struct pci_attach_args *pa = (struct pci_attach_args *)aux;
   3205    1.1      fvdl 
   3206    1.7   thorpej 	if (bge_lookup(pa) != NULL)
   3207  1.170   msaitoh 		return 1;
   3208    1.1      fvdl 
   3209  1.170   msaitoh 	return 0;
   3210    1.1      fvdl }
   3211    1.1      fvdl 
   3212  1.104   thorpej static void
   3213  1.116  christos bge_attach(device_t parent, device_t self, void *aux)
   3214    1.1      fvdl {
   3215  1.354     skrll 	struct bge_softc * const sc = device_private(self);
   3216  1.354     skrll 	struct pci_attach_args * const pa = aux;
   3217  1.164   msaitoh 	prop_dictionary_t dict;
   3218    1.7   thorpej 	const struct bge_product *bp;
   3219   1.16   thorpej 	const struct bge_revision *br;
   3220  1.143      tron 	pci_chipset_tag_t	pc;
   3221    1.1      fvdl 	const char		*intrstr = NULL;
   3222  1.330   msaitoh 	uint32_t		hwcfg, hwcfg2, hwcfg3, hwcfg4, hwcfg5;
   3223  1.170   msaitoh 	uint32_t		command;
   3224    1.1      fvdl 	struct ifnet		*ifp;
   3225  1.331   msaitoh 	struct mii_data * const mii = &sc->bge_mii;
   3226  1.342   msaitoh 	uint32_t		misccfg, mimode, macmode;
   3227  1.126  christos 	void *			kva;
   3228    1.1      fvdl 	u_char			eaddr[ETHER_ADDR_LEN];
   3229  1.216   msaitoh 	pcireg_t		memtype, subid, reg;
   3230    1.1      fvdl 	bus_addr_t		memaddr;
   3231  1.170   msaitoh 	uint32_t		pm_ctl;
   3232  1.174    martin 	bool			no_seeprom;
   3233  1.342   msaitoh 	int			capmask, trys;
   3234  1.269   msaitoh 	int			mii_flags;
   3235  1.273   msaitoh 	int			map_flags;
   3236  1.266  christos 	char intrbuf[PCI_INTRSTR_LEN];
   3237   1.87     perry 
   3238    1.7   thorpej 	bp = bge_lookup(pa);
   3239    1.7   thorpej 	KASSERT(bp != NULL);
   3240    1.7   thorpej 
   3241  1.141  jmcneill 	sc->sc_pc = pa->pa_pc;
   3242  1.141  jmcneill 	sc->sc_pcitag = pa->pa_tag;
   3243  1.138     joerg 	sc->bge_dev = self;
   3244    1.1      fvdl 
   3245  1.216   msaitoh 	sc->bge_pa = *pa;
   3246  1.172   msaitoh 	pc = sc->sc_pc;
   3247  1.172   msaitoh 	subid = pci_conf_read(pc, sc->sc_pcitag, PCI_SUBSYS_ID_REG);
   3248  1.172   msaitoh 
   3249   1.30   thorpej 	aprint_naive(": Ethernet controller\n");
   3250  1.325   msaitoh 	aprint_normal(": %s Ethernet\n", bp->bp_name);
   3251    1.1      fvdl 
   3252    1.1      fvdl 	/*
   3253    1.1      fvdl 	 * Map control/status registers.
   3254    1.1      fvdl 	 */
   3255    1.1      fvdl 	DPRINTFN(5, ("Map control/status regs\n"));
   3256  1.141  jmcneill 	command = pci_conf_read(pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG);
   3257    1.1      fvdl 	command |= PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_MASTER_ENABLE;
   3258  1.141  jmcneill 	pci_conf_write(pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG, command);
   3259  1.141  jmcneill 	command = pci_conf_read(pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG);
   3260    1.1      fvdl 
   3261    1.1      fvdl 	if (!(command & PCI_COMMAND_MEM_ENABLE)) {
   3262  1.138     joerg 		aprint_error_dev(sc->bge_dev,
   3263  1.138     joerg 		    "failed to enable memory mapping!\n");
   3264    1.1      fvdl 		return;
   3265    1.1      fvdl 	}
   3266    1.1      fvdl 
   3267    1.1      fvdl 	DPRINTFN(5, ("pci_mem_find\n"));
   3268  1.141  jmcneill 	memtype = pci_mapreg_type(sc->sc_pc, sc->sc_pcitag, BGE_PCI_BAR0);
   3269  1.178   msaitoh 	switch (memtype) {
   3270   1.29    itojun 	case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT:
   3271   1.29    itojun 	case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT:
   3272  1.275   msaitoh #if 0
   3273    1.1      fvdl 		if (pci_mapreg_map(pa, BGE_PCI_BAR0,
   3274   1.29    itojun 		    memtype, 0, &sc->bge_btag, &sc->bge_bhandle,
   3275  1.227   msaitoh 		    &memaddr, &sc->bge_bsize) == 0)
   3276    1.1      fvdl 			break;
   3277  1.275   msaitoh #else
   3278  1.275   msaitoh 		/*
   3279  1.275   msaitoh 		 * Workaround for PCI prefetchable bit. Some BCM5717-5720 based
   3280  1.275   msaitoh 		 * system get NMI on boot (PR#48451). This problem might not be
   3281  1.275   msaitoh 		 * the driver's bug but our PCI common part's bug. Until we
   3282  1.275   msaitoh 		 * find a real reason, we ignore the prefetchable bit.
   3283  1.275   msaitoh 		 */
   3284  1.275   msaitoh 		if (pci_mapreg_info(pa->pa_pc, pa->pa_tag, BGE_PCI_BAR0,
   3285  1.275   msaitoh 		    memtype, &memaddr, &sc->bge_bsize, &map_flags) == 0) {
   3286  1.275   msaitoh 			map_flags &= ~BUS_SPACE_MAP_PREFETCHABLE;
   3287  1.275   msaitoh 			if (bus_space_map(pa->pa_memt, memaddr, sc->bge_bsize,
   3288  1.275   msaitoh 			    map_flags, &sc->bge_bhandle) == 0) {
   3289  1.275   msaitoh 				sc->bge_btag = pa->pa_memt;
   3290  1.275   msaitoh 				break;
   3291  1.275   msaitoh 			}
   3292  1.275   msaitoh 		}
   3293  1.275   msaitoh #endif
   3294  1.323       mrg 		/* FALLTHROUGH */
   3295    1.1      fvdl 	default:
   3296  1.138     joerg 		aprint_error_dev(sc->bge_dev, "can't find mem space\n");
   3297    1.1      fvdl 		return;
   3298    1.1      fvdl 	}
   3299    1.1      fvdl 
   3300  1.215   msaitoh 	/* Save various chip information. */
   3301  1.215   msaitoh 	sc->bge_chipid = bge_chipid(pa);
   3302  1.216   msaitoh 	sc->bge_phy_addr = bge_phy_addr(sc);
   3303   1.76      cube 
   3304  1.303   msaitoh 	if (pci_get_capability(sc->sc_pc, sc->sc_pcitag, PCI_CAP_PCIEXPRESS,
   3305  1.303   msaitoh 	    &sc->bge_pciecap, NULL) != 0) {
   3306  1.171   msaitoh 		/* PCIe */
   3307  1.261   msaitoh 		sc->bge_flags |= BGEF_PCIE;
   3308  1.253   msaitoh 		/* Extract supported maximum payload size. */
   3309  1.253   msaitoh 		reg = pci_conf_read(sc->sc_pc, sc->sc_pcitag,
   3310  1.253   msaitoh 		    sc->bge_pciecap + PCIE_DCAP);
   3311  1.253   msaitoh 		sc->bge_mps = 128 << (reg & PCIE_DCAP_MAX_PAYLOAD);
   3312  1.216   msaitoh 		if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719 ||
   3313  1.216   msaitoh 		    BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720)
   3314  1.216   msaitoh 			sc->bge_expmrq = 2048;
   3315  1.216   msaitoh 		else
   3316  1.216   msaitoh 			sc->bge_expmrq = 4096;
   3317  1.177   msaitoh 		bge_set_max_readrq(sc);
   3318  1.303   msaitoh 	} else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785) {
   3319  1.303   msaitoh 		/* PCIe without PCIe cap */
   3320  1.303   msaitoh 		sc->bge_flags |= BGEF_PCIE;
   3321  1.171   msaitoh 	} else if ((pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_PCISTATE) &
   3322  1.171   msaitoh 		BGE_PCISTATE_PCI_BUSMODE) == 0) {
   3323  1.171   msaitoh 		/* PCI-X */
   3324  1.261   msaitoh 		sc->bge_flags |= BGEF_PCIX;
   3325  1.180   msaitoh 		if (pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_PCIX,
   3326  1.180   msaitoh 			&sc->bge_pcixcap, NULL) == 0)
   3327  1.180   msaitoh 			aprint_error_dev(sc->bge_dev,
   3328  1.180   msaitoh 			    "unable to find PCIX capability\n");
   3329  1.171   msaitoh 	}
   3330   1.76      cube 
   3331  1.216   msaitoh 	if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX) {
   3332  1.216   msaitoh 		/*
   3333  1.216   msaitoh 		 * Kludge for 5700 Bx bug: a hardware bug (PCIX byte enable?)
   3334  1.216   msaitoh 		 * can clobber the chip's PCI config-space power control
   3335  1.216   msaitoh 		 * registers, leaving the card in D3 powersave state. We do
   3336  1.216   msaitoh 		 * not have memory-mapped registers in this state, so force
   3337  1.216   msaitoh 		 * device into D0 state before starting initialization.
   3338  1.216   msaitoh 		 */
   3339  1.216   msaitoh 		pm_ctl = pci_conf_read(pc, sc->sc_pcitag, BGE_PCI_PWRMGMT_CMD);
   3340  1.331   msaitoh 		pm_ctl &= ~(PCI_PWR_D0 | PCI_PWR_D1 | PCI_PWR_D2 | PCI_PWR_D3);
   3341  1.216   msaitoh 		pm_ctl |= (1 << 8) | PCI_PWR_D0 ; /* D0 state */
   3342  1.216   msaitoh 		pci_conf_write(pc, sc->sc_pcitag, BGE_PCI_PWRMGMT_CMD, pm_ctl);
   3343  1.348    andvar 		DELAY(1000);	/* 27 usec is allegedly sufficient */
   3344  1.216   msaitoh 	}
   3345  1.216   msaitoh 
   3346  1.215   msaitoh 	/* Save chipset family. */
   3347  1.215   msaitoh 	switch (BGE_ASICREV(sc->bge_chipid)) {
   3348  1.215   msaitoh 	case BGE_ASICREV_BCM5717:
   3349  1.216   msaitoh 	case BGE_ASICREV_BCM5719:
   3350  1.216   msaitoh 	case BGE_ASICREV_BCM5720:
   3351  1.261   msaitoh 		sc->bge_flags |= BGEF_5717_PLUS;
   3352  1.257   msaitoh 		/* FALLTHROUGH */
   3353  1.327   msaitoh 	case BGE_ASICREV_BCM5762:
   3354  1.257   msaitoh 	case BGE_ASICREV_BCM57765:
   3355  1.257   msaitoh 	case BGE_ASICREV_BCM57766:
   3356  1.257   msaitoh 		if (!BGE_IS_5717_PLUS(sc))
   3357  1.261   msaitoh 			sc->bge_flags |= BGEF_57765_FAMILY;
   3358  1.261   msaitoh 		sc->bge_flags |= BGEF_57765_PLUS | BGEF_5755_PLUS |
   3359  1.261   msaitoh 		    BGEF_575X_PLUS | BGEF_5705_PLUS | BGEF_JUMBO_CAPABLE;
   3360  1.327   msaitoh 		if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719 ||
   3361  1.327   msaitoh 		    BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) {
   3362  1.327   msaitoh 			/*
   3363  1.327   msaitoh 			 * Enable work around for DMA engine miscalculation
   3364  1.327   msaitoh 			 * of TXMBUF available space.
   3365  1.327   msaitoh 			 */
   3366  1.327   msaitoh 			sc->bge_flags |= BGEF_RDMA_BUG;
   3367  1.327   msaitoh 
   3368  1.327   msaitoh 			if ((BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719) &&
   3369  1.327   msaitoh 			    (sc->bge_chipid == BGE_CHIPID_BCM5719_A0)) {
   3370  1.327   msaitoh 				/* Jumbo frame on BCM5719 A0 does not work. */
   3371  1.327   msaitoh 				sc->bge_flags &= ~BGEF_JUMBO_CAPABLE;
   3372  1.327   msaitoh 			}
   3373  1.327   msaitoh 		}
   3374  1.215   msaitoh 		break;
   3375  1.215   msaitoh 	case BGE_ASICREV_BCM5755:
   3376  1.215   msaitoh 	case BGE_ASICREV_BCM5761:
   3377  1.215   msaitoh 	case BGE_ASICREV_BCM5784:
   3378  1.215   msaitoh 	case BGE_ASICREV_BCM5785:
   3379  1.215   msaitoh 	case BGE_ASICREV_BCM5787:
   3380  1.215   msaitoh 	case BGE_ASICREV_BCM57780:
   3381  1.261   msaitoh 		sc->bge_flags |= BGEF_5755_PLUS | BGEF_575X_PLUS | BGEF_5705_PLUS;
   3382  1.215   msaitoh 		break;
   3383  1.215   msaitoh 	case BGE_ASICREV_BCM5700:
   3384  1.215   msaitoh 	case BGE_ASICREV_BCM5701:
   3385  1.215   msaitoh 	case BGE_ASICREV_BCM5703:
   3386  1.215   msaitoh 	case BGE_ASICREV_BCM5704:
   3387  1.261   msaitoh 		sc->bge_flags |= BGEF_5700_FAMILY | BGEF_JUMBO_CAPABLE;
   3388  1.215   msaitoh 		break;
   3389  1.215   msaitoh 	case BGE_ASICREV_BCM5714_A0:
   3390  1.215   msaitoh 	case BGE_ASICREV_BCM5780:
   3391  1.215   msaitoh 	case BGE_ASICREV_BCM5714:
   3392  1.261   msaitoh 		sc->bge_flags |= BGEF_5714_FAMILY | BGEF_JUMBO_CAPABLE;
   3393  1.215   msaitoh 		/* FALLTHROUGH */
   3394  1.215   msaitoh 	case BGE_ASICREV_BCM5750:
   3395  1.215   msaitoh 	case BGE_ASICREV_BCM5752:
   3396  1.215   msaitoh 	case BGE_ASICREV_BCM5906:
   3397  1.261   msaitoh 		sc->bge_flags |= BGEF_575X_PLUS;
   3398  1.215   msaitoh 		/* FALLTHROUGH */
   3399  1.215   msaitoh 	case BGE_ASICREV_BCM5705:
   3400  1.261   msaitoh 		sc->bge_flags |= BGEF_5705_PLUS;
   3401  1.215   msaitoh 		break;
   3402  1.215   msaitoh 	}
   3403  1.172   msaitoh 
   3404  1.216   msaitoh 	/* Identify chips with APE processor. */
   3405  1.216   msaitoh 	switch (BGE_ASICREV(sc->bge_chipid)) {
   3406  1.216   msaitoh 	case BGE_ASICREV_BCM5717:
   3407  1.216   msaitoh 	case BGE_ASICREV_BCM5719:
   3408  1.216   msaitoh 	case BGE_ASICREV_BCM5720:
   3409  1.216   msaitoh 	case BGE_ASICREV_BCM5761:
   3410  1.327   msaitoh 	case BGE_ASICREV_BCM5762:
   3411  1.261   msaitoh 		sc->bge_flags |= BGEF_APE;
   3412  1.216   msaitoh 		break;
   3413  1.216   msaitoh 	}
   3414  1.216   msaitoh 
   3415  1.262   msaitoh 	/*
   3416  1.262   msaitoh 	 * The 40bit DMA bug applies to the 5714/5715 controllers and is
   3417  1.262   msaitoh 	 * not actually a MAC controller bug but an issue with the embedded
   3418  1.262   msaitoh 	 * PCIe to PCI-X bridge in the device. Use 40bit DMA workaround.
   3419  1.262   msaitoh 	 */
   3420  1.262   msaitoh 	if (BGE_IS_5714_FAMILY(sc) && ((sc->bge_flags & BGEF_PCIX) != 0))
   3421  1.262   msaitoh 		sc->bge_flags |= BGEF_40BIT_BUG;
   3422  1.262   msaitoh 
   3423  1.216   msaitoh 	/* Chips with APE need BAR2 access for APE registers/memory. */
   3424  1.261   msaitoh 	if ((sc->bge_flags & BGEF_APE) != 0) {
   3425  1.216   msaitoh 		memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, BGE_PCI_BAR2);
   3426  1.273   msaitoh #if 0
   3427  1.216   msaitoh 		if (pci_mapreg_map(pa, BGE_PCI_BAR2, memtype, 0,
   3428  1.227   msaitoh 			&sc->bge_apetag, &sc->bge_apehandle, NULL,
   3429  1.227   msaitoh 			&sc->bge_apesize)) {
   3430  1.216   msaitoh 			aprint_error_dev(sc->bge_dev,
   3431  1.216   msaitoh 			    "couldn't map BAR2 memory\n");
   3432  1.216   msaitoh 			return;
   3433  1.216   msaitoh 		}
   3434  1.273   msaitoh #else
   3435  1.273   msaitoh 		/*
   3436  1.273   msaitoh 		 * Workaround for PCI prefetchable bit. Some BCM5717-5720 based
   3437  1.273   msaitoh 		 * system get NMI on boot (PR#48451). This problem might not be
   3438  1.273   msaitoh 		 * the driver's bug but our PCI common part's bug. Until we
   3439  1.273   msaitoh 		 * find a real reason, we ignore the prefetchable bit.
   3440  1.273   msaitoh 		 */
   3441  1.273   msaitoh 		if (pci_mapreg_info(pa->pa_pc, pa->pa_tag, BGE_PCI_BAR2,
   3442  1.273   msaitoh 		    memtype, &memaddr, &sc->bge_apesize, &map_flags) != 0) {
   3443  1.273   msaitoh 			aprint_error_dev(sc->bge_dev,
   3444  1.273   msaitoh 			    "couldn't map BAR2 memory\n");
   3445  1.273   msaitoh 			return;
   3446  1.273   msaitoh 		}
   3447  1.273   msaitoh 
   3448  1.273   msaitoh 		map_flags &= ~BUS_SPACE_MAP_PREFETCHABLE;
   3449  1.273   msaitoh 		if (bus_space_map(pa->pa_memt, memaddr,
   3450  1.273   msaitoh 		    sc->bge_apesize, map_flags, &sc->bge_apehandle) != 0) {
   3451  1.273   msaitoh 			aprint_error_dev(sc->bge_dev,
   3452  1.273   msaitoh 			    "couldn't map BAR2 memory\n");
   3453  1.273   msaitoh 			return;
   3454  1.273   msaitoh 		}
   3455  1.273   msaitoh 		sc->bge_apetag = pa->pa_memt;
   3456  1.273   msaitoh #endif
   3457  1.216   msaitoh 
   3458  1.216   msaitoh 		/* Enable APE register/memory access by host driver. */
   3459  1.216   msaitoh 		reg = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_PCISTATE);
   3460  1.216   msaitoh 		reg |= BGE_PCISTATE_ALLOW_APE_CTLSPC_WR |
   3461  1.216   msaitoh 		    BGE_PCISTATE_ALLOW_APE_SHMEM_WR |
   3462  1.216   msaitoh 		    BGE_PCISTATE_ALLOW_APE_PSPACE_WR;
   3463  1.216   msaitoh 		pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_PCISTATE, reg);
   3464  1.216   msaitoh 
   3465  1.216   msaitoh 		bge_ape_lock_init(sc);
   3466  1.216   msaitoh 		bge_ape_read_fw_ver(sc);
   3467  1.216   msaitoh 	}
   3468  1.216   msaitoh 
   3469  1.216   msaitoh 	/* Identify the chips that use an CPMU. */
   3470  1.216   msaitoh 	if (BGE_IS_5717_PLUS(sc) ||
   3471  1.216   msaitoh 	    BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5784 ||
   3472  1.216   msaitoh 	    BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761 ||
   3473  1.216   msaitoh 	    BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785 ||
   3474  1.216   msaitoh 	    BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57780)
   3475  1.261   msaitoh 		sc->bge_flags |= BGEF_CPMU_PRESENT;
   3476  1.216   msaitoh 
   3477  1.172   msaitoh 	/*
   3478  1.172   msaitoh 	 * When using the BCM5701 in PCI-X mode, data corruption has
   3479  1.172   msaitoh 	 * been observed in the first few bytes of some received packets.
   3480  1.172   msaitoh 	 * Aligning the packet buffer in memory eliminates the corruption.
   3481  1.172   msaitoh 	 * Unfortunately, this misaligns the packet payloads.  On platforms
   3482  1.172   msaitoh 	 * which do not support unaligned accesses, we will realign the
   3483  1.172   msaitoh 	 * payloads by copying the received packets.
   3484  1.172   msaitoh 	 */
   3485  1.172   msaitoh 	if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5701 &&
   3486  1.261   msaitoh 	    sc->bge_flags & BGEF_PCIX)
   3487  1.261   msaitoh 		sc->bge_flags |= BGEF_RX_ALIGNBUG;
   3488  1.172   msaitoh 
   3489  1.172   msaitoh 	if (BGE_IS_5700_FAMILY(sc))
   3490  1.261   msaitoh 		sc->bge_flags |= BGEF_JUMBO_CAPABLE;
   3491  1.172   msaitoh 
   3492  1.172   msaitoh 	misccfg = CSR_READ_4(sc, BGE_MISC_CFG);
   3493  1.172   msaitoh 	misccfg &= BGE_MISCCFG_BOARD_ID_MASK;
   3494  1.172   msaitoh 
   3495  1.172   msaitoh 	if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5705 &&
   3496  1.172   msaitoh 	    (misccfg == BGE_MISCCFG_BOARD_ID_5788 ||
   3497  1.172   msaitoh 	     misccfg == BGE_MISCCFG_BOARD_ID_5788M))
   3498  1.261   msaitoh 		sc->bge_flags |= BGEF_IS_5788;
   3499  1.172   msaitoh 
   3500  1.172   msaitoh 	/*
   3501  1.172   msaitoh 	 * Some controllers seem to require a special firmware to use
   3502  1.172   msaitoh 	 * TSO. But the firmware is not available to FreeBSD and Linux
   3503  1.172   msaitoh 	 * claims that the TSO performed by the firmware is slower than
   3504  1.172   msaitoh 	 * hardware based TSO. Moreover the firmware based TSO has one
   3505  1.172   msaitoh 	 * known bug which can't handle TSO if ethernet header + IP/TCP
   3506  1.172   msaitoh 	 * header is greater than 80 bytes. The workaround for the TSO
   3507  1.172   msaitoh 	 * bug exist but it seems it's too expensive than not using
   3508  1.172   msaitoh 	 * TSO at all. Some hardwares also have the TSO bug so limit
   3509  1.172   msaitoh 	 * the TSO to the controllers that are not affected TSO issues
   3510  1.172   msaitoh 	 * (e.g. 5755 or higher).
   3511  1.172   msaitoh 	 */
   3512  1.172   msaitoh 	if (BGE_IS_5755_PLUS(sc)) {
   3513  1.172   msaitoh 		/*
   3514  1.172   msaitoh 		 * BCM5754 and BCM5787 shares the same ASIC id so
   3515  1.172   msaitoh 		 * explicit device id check is required.
   3516  1.172   msaitoh 		 */
   3517  1.172   msaitoh 		if ((PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_BROADCOM_BCM5754) &&
   3518  1.172   msaitoh 		    (PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_BROADCOM_BCM5754M))
   3519  1.261   msaitoh 			sc->bge_flags |= BGEF_TSO;
   3520  1.316    bouyer 		/* TSO on BCM5719 A0 does not work. */
   3521  1.316    bouyer 		if ((BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719) &&
   3522  1.316    bouyer 		    (sc->bge_chipid == BGE_CHIPID_BCM5719_A0))
   3523  1.316    bouyer 			sc->bge_flags &= ~BGEF_TSO;
   3524  1.172   msaitoh 	}
   3525  1.172   msaitoh 
   3526  1.220   msaitoh 	capmask = 0xffffffff; /* XXX BMSR_DEFCAPMASK */
   3527  1.172   msaitoh 	if ((BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5703 &&
   3528  1.172   msaitoh 	     (misccfg == 0x4000 || misccfg == 0x8000)) ||
   3529  1.172   msaitoh 	    (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5705 &&
   3530  1.172   msaitoh 	     PCI_VENDOR(pa->pa_id) == PCI_VENDOR_BROADCOM &&
   3531  1.172   msaitoh 	     (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5901 ||
   3532  1.172   msaitoh 	      PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5901A2 ||
   3533  1.172   msaitoh 	      PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5705F)) ||
   3534  1.172   msaitoh 	    (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_BROADCOM &&
   3535  1.172   msaitoh 	     (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5751F ||
   3536  1.172   msaitoh 	      PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5753F ||
   3537  1.172   msaitoh 	      PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5787F)) ||
   3538  1.172   msaitoh 	    PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM57790 ||
   3539  1.216   msaitoh 	    PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM57791 ||
   3540  1.216   msaitoh 	    PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM57795 ||
   3541  1.220   msaitoh 	    BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) {
   3542  1.270   msaitoh 		/* These chips are 10/100 only. */
   3543  1.220   msaitoh 		capmask &= ~BMSR_EXTSTAT;
   3544  1.261   msaitoh 		sc->bge_phy_flags |= BGEPHYF_NO_WIRESPEED;
   3545  1.220   msaitoh 	}
   3546  1.172   msaitoh 
   3547  1.172   msaitoh 	if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 ||
   3548  1.172   msaitoh 	    (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5705 &&
   3549  1.172   msaitoh 	     (sc->bge_chipid != BGE_CHIPID_BCM5705_A0 &&
   3550  1.220   msaitoh 		 sc->bge_chipid != BGE_CHIPID_BCM5705_A1)))
   3551  1.261   msaitoh 		sc->bge_phy_flags |= BGEPHYF_NO_WIRESPEED;
   3552  1.172   msaitoh 
   3553  1.220   msaitoh 	/* Set various PHY bug flags. */
   3554  1.162   msaitoh 	if (sc->bge_chipid == BGE_CHIPID_BCM5701_A0 ||
   3555  1.162   msaitoh 	    sc->bge_chipid == BGE_CHIPID_BCM5701_B0)
   3556  1.261   msaitoh 		sc->bge_phy_flags |= BGEPHYF_CRC_BUG;
   3557  1.162   msaitoh 	if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5703_AX ||
   3558  1.162   msaitoh 	    BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5704_AX)
   3559  1.261   msaitoh 		sc->bge_phy_flags |= BGEPHYF_ADC_BUG;
   3560  1.162   msaitoh 	if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0)
   3561  1.261   msaitoh 		sc->bge_phy_flags |= BGEPHYF_5704_A0_BUG;
   3562  1.220   msaitoh 	if ((BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 ||
   3563  1.220   msaitoh 	    BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5701) &&
   3564  1.220   msaitoh 	    PCI_VENDOR(subid) == PCI_VENDOR_DELL)
   3565  1.261   msaitoh 		sc->bge_phy_flags |= BGEPHYF_NO_3LED;
   3566  1.172   msaitoh 	if (BGE_IS_5705_PLUS(sc) &&
   3567  1.172   msaitoh 	    BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5906 &&
   3568  1.172   msaitoh 	    BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5785 &&
   3569  1.216   msaitoh 	    BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM57780 &&
   3570  1.257   msaitoh 	    !BGE_IS_57765_PLUS(sc)) {
   3571  1.162   msaitoh 		if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5755 ||
   3572  1.172   msaitoh 		    BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761 ||
   3573  1.172   msaitoh 		    BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5784 ||
   3574  1.162   msaitoh 		    BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5787) {
   3575  1.162   msaitoh 			if (PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_BROADCOM_BCM5722 &&
   3576  1.162   msaitoh 			    PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_BROADCOM_BCM5756)
   3577  1.261   msaitoh 				sc->bge_phy_flags |= BGEPHYF_JITTER_BUG;
   3578  1.162   msaitoh 			if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5755M)
   3579  1.261   msaitoh 				sc->bge_phy_flags |= BGEPHYF_ADJUST_TRIM;
   3580  1.216   msaitoh 		} else
   3581  1.261   msaitoh 			sc->bge_phy_flags |= BGEPHYF_BER_BUG;
   3582  1.162   msaitoh 	}
   3583  1.162   msaitoh 
   3584  1.174    martin 	/*
   3585  1.174    martin 	 * SEEPROM check.
   3586  1.174    martin 	 * First check if firmware knows we do not have SEEPROM.
   3587  1.174    martin 	 */
   3588  1.180   msaitoh 	if (prop_dictionary_get_bool(device_properties(self),
   3589  1.367     skrll 	    "without-seeprom", &no_seeprom) && no_seeprom)
   3590  1.330   msaitoh 		sc->bge_flags |= BGEF_NO_EEPROM;
   3591  1.174    martin 
   3592  1.228   msaitoh 	else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906)
   3593  1.261   msaitoh 		sc->bge_flags |= BGEF_NO_EEPROM;
   3594  1.228   msaitoh 
   3595  1.174    martin 	/* Now check the 'ROM failed' bit on the RX CPU */
   3596  1.174    martin 	else if (CSR_READ_4(sc, BGE_RXCPU_MODE) & BGE_RXCPUMODE_ROMFAIL)
   3597  1.261   msaitoh 		sc->bge_flags |= BGEF_NO_EEPROM;
   3598  1.172   msaitoh 
   3599  1.177   msaitoh 	sc->bge_asf_mode = 0;
   3600  1.216   msaitoh 	/* No ASF if APE present. */
   3601  1.261   msaitoh 	if ((sc->bge_flags & BGEF_APE) == 0) {
   3602  1.216   msaitoh 		if (bge_allow_asf && (bge_readmem_ind(sc, BGE_SRAM_DATA_SIG) ==
   3603  1.216   msaitoh 			BGE_SRAM_DATA_SIG_MAGIC)) {
   3604  1.216   msaitoh 			if (bge_readmem_ind(sc, BGE_SRAM_DATA_CFG) &
   3605  1.216   msaitoh 			    BGE_HWCFG_ASF) {
   3606  1.216   msaitoh 				sc->bge_asf_mode |= ASF_ENABLE;
   3607  1.216   msaitoh 				sc->bge_asf_mode |= ASF_STACKUP;
   3608  1.216   msaitoh 				if (BGE_IS_575X_PLUS(sc))
   3609  1.216   msaitoh 					sc->bge_asf_mode |= ASF_NEW_HANDSHAKE;
   3610  1.177   msaitoh 			}
   3611  1.177   msaitoh 		}
   3612  1.177   msaitoh 	}
   3613  1.177   msaitoh 
   3614  1.318  jdolecek 	int counts[PCI_INTR_TYPE_SIZE] = {
   3615  1.318  jdolecek 		[PCI_INTR_TYPE_INTX] = 1,
   3616  1.318  jdolecek 		[PCI_INTR_TYPE_MSI] = 1,
   3617  1.319  jdolecek 		[PCI_INTR_TYPE_MSIX] = 1,
   3618  1.318  jdolecek 	};
   3619  1.318  jdolecek 	int max_type = PCI_INTR_TYPE_MSIX;
   3620  1.318  jdolecek 
   3621  1.318  jdolecek 	if (!bge_can_use_msi(sc)) {
   3622  1.318  jdolecek 		/* MSI broken, allow only INTx */
   3623  1.293  knakahar 		max_type = PCI_INTR_TYPE_INTX;
   3624  1.318  jdolecek 	}
   3625  1.293  knakahar 
   3626  1.293  knakahar 	if (pci_intr_alloc(pa, &sc->bge_pihp, counts, max_type) != 0) {
   3627  1.293  knakahar 		aprint_error_dev(sc->bge_dev, "couldn't alloc interrupt\n");
   3628  1.293  knakahar 		return;
   3629  1.288   msaitoh 	}
   3630  1.288   msaitoh 
   3631  1.293  knakahar 	DPRINTFN(5, ("pci_intr_string\n"));
   3632  1.288   msaitoh 	intrstr = pci_intr_string(pc, sc->bge_pihp[0], intrbuf,
   3633  1.288   msaitoh 	    sizeof(intrbuf));
   3634  1.288   msaitoh 	DPRINTFN(5, ("pci_intr_establish\n"));
   3635  1.310   msaitoh 	sc->bge_intrhand = pci_intr_establish_xname(pc, sc->bge_pihp[0],
   3636  1.310   msaitoh 	    IPL_NET, bge_intr, sc, device_xname(sc->bge_dev));
   3637  1.293  knakahar 	if (sc->bge_intrhand == NULL) {
   3638  1.293  knakahar 		pci_intr_release(pc, sc->bge_pihp, 1);
   3639  1.318  jdolecek 		sc->bge_pihp = NULL;
   3640  1.288   msaitoh 
   3641  1.318  jdolecek 		aprint_error_dev(self, "couldn't establish interrupt");
   3642  1.318  jdolecek 		if (intrstr != NULL)
   3643  1.318  jdolecek 			aprint_error(" at %s", intrstr);
   3644  1.318  jdolecek 		aprint_error("\n");
   3645  1.288   msaitoh 		return;
   3646  1.288   msaitoh 	}
   3647  1.288   msaitoh 	aprint_normal_dev(sc->bge_dev, "interrupting at %s\n", intrstr);
   3648  1.288   msaitoh 
   3649  1.318  jdolecek 	switch (pci_intr_type(pc, sc->bge_pihp[0])) {
   3650  1.318  jdolecek 	case PCI_INTR_TYPE_MSIX:
   3651  1.318  jdolecek 	case PCI_INTR_TYPE_MSI:
   3652  1.318  jdolecek 		KASSERT(bge_can_use_msi(sc));
   3653  1.318  jdolecek 		sc->bge_flags |= BGEF_MSI;
   3654  1.318  jdolecek 		break;
   3655  1.318  jdolecek 	default:
   3656  1.318  jdolecek 		/* nothing to do */
   3657  1.318  jdolecek 		break;
   3658  1.318  jdolecek 	}
   3659  1.318  jdolecek 
   3660  1.375     skrll 	char wqname[MAXCOMLEN];
   3661  1.375     skrll 	snprintf(wqname, sizeof(wqname), "%sReset", device_xname(sc->bge_dev));
   3662  1.375     skrll 	int error = workqueue_create(&sc->sc_reset_wq, wqname,
   3663  1.375     skrll 	    bge_handle_reset_work, sc, PRI_NONE, IPL_SOFTCLOCK,
   3664  1.375     skrll 	    WQ_MPSAFE);
   3665  1.375     skrll 	if (error) {
   3666  1.375     skrll 		aprint_error_dev(sc->bge_dev,
   3667  1.375     skrll 		    "unable to create reset workqueue\n");
   3668  1.375     skrll 		return;
   3669  1.375     skrll 	}
   3670  1.375     skrll 
   3671  1.375     skrll 
   3672  1.288   msaitoh 	/*
   3673  1.288   msaitoh 	 * All controllers except BCM5700 supports tagged status but
   3674  1.288   msaitoh 	 * we use tagged status only for MSI case on BCM5717. Otherwise
   3675  1.288   msaitoh 	 * MSI on BCM5717 does not work.
   3676  1.288   msaitoh 	 */
   3677  1.307   msaitoh 	if (BGE_IS_57765_PLUS(sc) && sc->bge_flags & BGEF_MSI)
   3678  1.288   msaitoh 		sc->bge_flags |= BGEF_TAGGED_STATUS;
   3679  1.288   msaitoh 
   3680  1.248   msaitoh 	/*
   3681  1.248   msaitoh 	 * Reset NVRAM before bge_reset(). It's required to acquire NVRAM
   3682  1.248   msaitoh 	 * lock in bge_reset().
   3683  1.248   msaitoh 	 */
   3684  1.341   msaitoh 	CSR_WRITE_4_FLUSH(sc, BGE_EE_ADDR,
   3685  1.248   msaitoh 	    BGE_EEADDR_RESET | BGE_EEHALFCLK(BGE_HALFCLK_384SCL));
   3686  1.248   msaitoh 	delay(1000);
   3687  1.341   msaitoh 	BGE_SETBIT_FLUSH(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM);
   3688  1.248   msaitoh 
   3689  1.248   msaitoh 	bge_stop_fw(sc);
   3690  1.353    buhrow 	bge_sig_pre_reset(sc, BGE_RESET_SHUTDOWN);
   3691  1.248   msaitoh 	if (bge_reset(sc))
   3692  1.248   msaitoh 		aprint_error_dev(sc->bge_dev, "chip reset failed\n");
   3693  1.243   msaitoh 
   3694  1.241   msaitoh 	/*
   3695  1.241   msaitoh 	 * Read the hardware config word in the first 32k of NIC internal
   3696  1.241   msaitoh 	 * memory, or fall back to the config word in the EEPROM.
   3697  1.241   msaitoh 	 * Note: on some BCM5700 cards, this value appears to be unset.
   3698  1.241   msaitoh 	 */
   3699  1.267   msaitoh 	hwcfg = hwcfg2 = hwcfg3 = hwcfg4 = hwcfg5 = 0;
   3700  1.248   msaitoh 	if (bge_readmem_ind(sc, BGE_SRAM_DATA_SIG) ==
   3701  1.241   msaitoh 	    BGE_SRAM_DATA_SIG_MAGIC) {
   3702  1.241   msaitoh 		uint32_t tmp;
   3703  1.241   msaitoh 
   3704  1.241   msaitoh 		hwcfg = bge_readmem_ind(sc, BGE_SRAM_DATA_CFG);
   3705  1.241   msaitoh 		tmp = bge_readmem_ind(sc, BGE_SRAM_DATA_VER) >>
   3706  1.241   msaitoh 		    BGE_SRAM_DATA_VER_SHIFT;
   3707  1.241   msaitoh 		if ((0 < tmp) && (tmp < 0x100))
   3708  1.241   msaitoh 			hwcfg2 = bge_readmem_ind(sc, BGE_SRAM_DATA_CFG_2);
   3709  1.261   msaitoh 		if (sc->bge_flags & BGEF_PCIE)
   3710  1.241   msaitoh 			hwcfg3 = bge_readmem_ind(sc, BGE_SRAM_DATA_CFG_3);
   3711  1.278   msaitoh 		if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785)
   3712  1.241   msaitoh 			hwcfg4 = bge_readmem_ind(sc, BGE_SRAM_DATA_CFG_4);
   3713  1.267   msaitoh 		if (BGE_IS_5717_PLUS(sc))
   3714  1.268   msaitoh 			hwcfg5 = bge_readmem_ind(sc, BGE_SRAM_DATA_CFG_5);
   3715  1.261   msaitoh 	} else if (!(sc->bge_flags & BGEF_NO_EEPROM)) {
   3716  1.241   msaitoh 		bge_read_eeprom(sc, (void *)&hwcfg,
   3717  1.241   msaitoh 		    BGE_EE_HWCFG_OFFSET, sizeof(hwcfg));
   3718  1.241   msaitoh 		hwcfg = be32toh(hwcfg);
   3719  1.241   msaitoh 	}
   3720  1.267   msaitoh 	aprint_normal_dev(sc->bge_dev,
   3721  1.267   msaitoh 	    "HW config %08x, %08x, %08x, %08x %08x\n",
   3722  1.267   msaitoh 	    hwcfg, hwcfg2, hwcfg3, hwcfg4, hwcfg5);
   3723  1.241   msaitoh 
   3724  1.353    buhrow 	bge_sig_legacy(sc, BGE_RESET_SHUTDOWN);
   3725  1.353    buhrow 	bge_sig_post_reset(sc, BGE_RESET_SHUTDOWN);
   3726  1.177   msaitoh 
   3727    1.1      fvdl 	if (bge_chipinit(sc)) {
   3728  1.138     joerg 		aprint_error_dev(sc->bge_dev, "chip initialization failed\n");
   3729    1.1      fvdl 		bge_release_resources(sc);
   3730    1.1      fvdl 		return;
   3731    1.1      fvdl 	}
   3732    1.1      fvdl 
   3733  1.342   msaitoh 	if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700) {
   3734  1.342   msaitoh 		BGE_SETBIT_FLUSH(sc, BGE_MISC_LOCAL_CTL,
   3735  1.342   msaitoh 		    BGE_MLC_MISCIO_OUT1 | BGE_MLC_MISCIO_OUTEN1);
   3736  1.342   msaitoh 		DELAY(100);
   3737  1.342   msaitoh 	}
   3738  1.342   msaitoh 
   3739  1.342   msaitoh 	/* Set MI_MODE */
   3740  1.342   msaitoh 	mimode = BGE_MIMODE_PHYADDR(sc->bge_phy_addr);
   3741  1.342   msaitoh 	if ((sc->bge_flags & BGEF_CPMU_PRESENT) != 0)
   3742  1.342   msaitoh 		mimode |= BGE_MIMODE_500KHZ_CONST;
   3743  1.342   msaitoh 	else
   3744  1.342   msaitoh 		mimode |= BGE_MIMODE_BASE;
   3745  1.342   msaitoh 	CSR_WRITE_4_FLUSH(sc, BGE_MI_MODE, mimode);
   3746  1.342   msaitoh 	DELAY(80);
   3747  1.342   msaitoh 
   3748    1.1      fvdl 	/*
   3749  1.203   msaitoh 	 * Get station address from the EEPROM.
   3750    1.1      fvdl 	 */
   3751  1.151    cegger 	if (bge_get_eaddr(sc, eaddr)) {
   3752  1.178   msaitoh 		aprint_error_dev(sc->bge_dev,
   3753  1.178   msaitoh 		    "failed to read station address\n");
   3754    1.1      fvdl 		bge_release_resources(sc);
   3755    1.1      fvdl 		return;
   3756    1.1      fvdl 	}
   3757    1.1      fvdl 
   3758   1.51      fvdl 	br = bge_lookup_rev(sc->bge_chipid);
   3759   1.51      fvdl 
   3760   1.16   thorpej 	if (br == NULL) {
   3761  1.172   msaitoh 		aprint_normal_dev(sc->bge_dev, "unknown ASIC (0x%x)",
   3762  1.172   msaitoh 		    sc->bge_chipid);
   3763   1.16   thorpej 	} else {
   3764  1.172   msaitoh 		aprint_normal_dev(sc->bge_dev, "ASIC %s (0x%x)",
   3765  1.172   msaitoh 		    br->br_name, sc->bge_chipid);
   3766   1.16   thorpej 	}
   3767   1.30   thorpej 	aprint_normal(", Ethernet address %s\n", ether_sprintf(eaddr));
   3768    1.1      fvdl 
   3769    1.1      fvdl 	/* Allocate the general information block and ring buffers. */
   3770  1.317    bouyer 	if (pci_dma64_available(pa)) {
   3771   1.41      fvdl 		sc->bge_dmatag = pa->pa_dmat64;
   3772  1.317    bouyer 		sc->bge_dmatag32 = pa->pa_dmat;
   3773  1.317    bouyer 		sc->bge_dma64 = true;
   3774  1.317    bouyer 	} else {
   3775   1.41      fvdl 		sc->bge_dmatag = pa->pa_dmat;
   3776  1.317    bouyer 		sc->bge_dmatag32 = pa->pa_dmat;
   3777  1.317    bouyer 		sc->bge_dma64 = false;
   3778  1.317    bouyer 	}
   3779  1.262   msaitoh 
   3780  1.262   msaitoh 	/* 40bit DMA workaround */
   3781  1.262   msaitoh 	if (sizeof(bus_addr_t) > 4) {
   3782  1.262   msaitoh 		if ((sc->bge_flags & BGEF_40BIT_BUG) != 0) {
   3783  1.262   msaitoh 			bus_dma_tag_t olddmatag = sc->bge_dmatag; /* save */
   3784  1.262   msaitoh 
   3785  1.351    martin 			if (bus_dmatag_subregion(olddmatag, 0,
   3786  1.351    martin 			    (bus_addr_t)__MASK(40),
   3787  1.377     skrll 			    &(sc->bge_dmatag), BUS_DMA_WAITOK) != 0) {
   3788  1.262   msaitoh 				aprint_error_dev(self,
   3789  1.262   msaitoh 				    "WARNING: failed to restrict dma range,"
   3790  1.262   msaitoh 				    " falling back to parent bus dma range\n");
   3791  1.262   msaitoh 				sc->bge_dmatag = olddmatag;
   3792  1.262   msaitoh 			}
   3793  1.262   msaitoh 		}
   3794  1.262   msaitoh 	}
   3795  1.320    bouyer 	SLIST_INIT(&sc->txdma_list);
   3796    1.1      fvdl 	DPRINTFN(5, ("bus_dmamem_alloc\n"));
   3797    1.1      fvdl 	if (bus_dmamem_alloc(sc->bge_dmatag, sizeof(struct bge_ring_data),
   3798  1.227   msaitoh 			     PAGE_SIZE, 0, &sc->bge_ring_seg, 1,
   3799  1.377     skrll 		&sc->bge_ring_rseg, BUS_DMA_WAITOK)) {
   3800  1.138     joerg 		aprint_error_dev(sc->bge_dev, "can't alloc rx buffers\n");
   3801    1.1      fvdl 		return;
   3802    1.1      fvdl 	}
   3803    1.1      fvdl 	DPRINTFN(5, ("bus_dmamem_map\n"));
   3804  1.227   msaitoh 	if (bus_dmamem_map(sc->bge_dmatag, &sc->bge_ring_seg,
   3805  1.227   msaitoh 		sc->bge_ring_rseg, sizeof(struct bge_ring_data), &kva,
   3806  1.377     skrll 			   BUS_DMA_WAITOK)) {
   3807  1.138     joerg 		aprint_error_dev(sc->bge_dev,
   3808  1.138     joerg 		    "can't map DMA buffers (%zu bytes)\n",
   3809  1.138     joerg 		    sizeof(struct bge_ring_data));
   3810  1.227   msaitoh 		bus_dmamem_free(sc->bge_dmatag, &sc->bge_ring_seg,
   3811  1.227   msaitoh 		    sc->bge_ring_rseg);
   3812    1.1      fvdl 		return;
   3813    1.1      fvdl 	}
   3814    1.1      fvdl 	DPRINTFN(5, ("bus_dmamem_create\n"));
   3815    1.1      fvdl 	if (bus_dmamap_create(sc->bge_dmatag, sizeof(struct bge_ring_data), 1,
   3816    1.1      fvdl 	    sizeof(struct bge_ring_data), 0,
   3817  1.377     skrll 	    BUS_DMA_WAITOK, &sc->bge_ring_map)) {
   3818  1.138     joerg 		aprint_error_dev(sc->bge_dev, "can't create DMA map\n");
   3819    1.1      fvdl 		bus_dmamem_unmap(sc->bge_dmatag, kva,
   3820    1.1      fvdl 				 sizeof(struct bge_ring_data));
   3821  1.227   msaitoh 		bus_dmamem_free(sc->bge_dmatag, &sc->bge_ring_seg,
   3822  1.227   msaitoh 		    sc->bge_ring_rseg);
   3823    1.1      fvdl 		return;
   3824    1.1      fvdl 	}
   3825    1.1      fvdl 	DPRINTFN(5, ("bus_dmamem_load\n"));
   3826    1.1      fvdl 	if (bus_dmamap_load(sc->bge_dmatag, sc->bge_ring_map, kva,
   3827    1.1      fvdl 			    sizeof(struct bge_ring_data), NULL,
   3828  1.377     skrll 			    BUS_DMA_WAITOK)) {
   3829    1.1      fvdl 		bus_dmamap_destroy(sc->bge_dmatag, sc->bge_ring_map);
   3830    1.1      fvdl 		bus_dmamem_unmap(sc->bge_dmatag, kva,
   3831    1.1      fvdl 				 sizeof(struct bge_ring_data));
   3832  1.227   msaitoh 		bus_dmamem_free(sc->bge_dmatag, &sc->bge_ring_seg,
   3833  1.227   msaitoh 		    sc->bge_ring_rseg);
   3834    1.1      fvdl 		return;
   3835    1.1      fvdl 	}
   3836    1.1      fvdl 
   3837    1.1      fvdl 	DPRINTFN(5, ("bzero\n"));
   3838    1.1      fvdl 	sc->bge_rdata = (struct bge_ring_data *)kva;
   3839    1.1      fvdl 
   3840   1.19       mjl 	memset(sc->bge_rdata, 0, sizeof(struct bge_ring_data));
   3841    1.1      fvdl 
   3842    1.1      fvdl 	/* Try to allocate memory for jumbo buffers. */
   3843  1.166   msaitoh 	if (BGE_IS_JUMBO_CAPABLE(sc)) {
   3844   1.44   hannken 		if (bge_alloc_jumbo_mem(sc)) {
   3845  1.138     joerg 			aprint_error_dev(sc->bge_dev,
   3846  1.138     joerg 			    "jumbo buffer allocation failed\n");
   3847   1.44   hannken 		} else
   3848   1.44   hannken 			sc->ethercom.ec_capabilities |= ETHERCAP_JUMBO_MTU;
   3849   1.44   hannken 	}
   3850    1.1      fvdl 
   3851    1.1      fvdl 	/* Set default tuneable values. */
   3852    1.1      fvdl 	sc->bge_stat_ticks = BGE_TICKS_PER_SEC;
   3853    1.1      fvdl 	sc->bge_rx_coal_ticks = 150;
   3854   1.25  jonathan 	sc->bge_rx_max_coal_bds = 64;
   3855   1.25  jonathan 	sc->bge_tx_coal_ticks = 300;
   3856   1.25  jonathan 	sc->bge_tx_max_coal_bds = 400;
   3857  1.172   msaitoh 	if (BGE_IS_5705_PLUS(sc)) {
   3858   1.95  jonathan 		sc->bge_tx_coal_ticks = (12 * 5);
   3859  1.146   mlelstv 		sc->bge_tx_max_coal_bds = (12 * 5);
   3860  1.138     joerg 			aprint_verbose_dev(sc->bge_dev,
   3861  1.138     joerg 			    "setting short Tx thresholds\n");
   3862   1.95  jonathan 	}
   3863    1.1      fvdl 
   3864  1.216   msaitoh 	if (BGE_IS_5717_PLUS(sc))
   3865  1.202   tsutsui 		sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT;
   3866  1.202   tsutsui 	else if (BGE_IS_5705_PLUS(sc))
   3867  1.172   msaitoh 		sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT_5705;
   3868  1.172   msaitoh 	else
   3869  1.172   msaitoh 		sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT;
   3870  1.172   msaitoh 
   3871  1.375     skrll 	sc->sc_core_lock = mutex_obj_alloc(MUTEX_DEFAULT, IPL_NET);
   3872  1.375     skrll 
   3873    1.1      fvdl 	/* Set up ifnet structure */
   3874    1.1      fvdl 	ifp = &sc->ethercom.ec_if;
   3875    1.1      fvdl 	ifp->if_softc = sc;
   3876    1.1      fvdl 	ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
   3877  1.375     skrll 	ifp->if_extflags = IFEF_MPSAFE;
   3878    1.1      fvdl 	ifp->if_ioctl = bge_ioctl;
   3879  1.141  jmcneill 	ifp->if_stop = bge_stop;
   3880    1.1      fvdl 	ifp->if_start = bge_start;
   3881    1.1      fvdl 	ifp->if_init = bge_init;
   3882  1.315  riastrad 	IFQ_SET_MAXLEN(&ifp->if_snd, uimax(BGE_TX_RING_CNT - 1, IFQ_MAXLEN));
   3883    1.1      fvdl 	IFQ_SET_READY(&ifp->if_snd);
   3884  1.115   tsutsui 	DPRINTFN(5, ("strcpy if_xname\n"));
   3885  1.138     joerg 	strcpy(ifp->if_xname, device_xname(sc->bge_dev));
   3886    1.1      fvdl 
   3887  1.157   msaitoh 	if (sc->bge_chipid != BGE_CHIPID_BCM5700_B0)
   3888   1.18   thorpej 		sc->ethercom.ec_if.if_capabilities |=
   3889  1.172   msaitoh 		    IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx;
   3890  1.172   msaitoh #if 1	/* XXX TCP/UDP checksum offload breaks with pf(4) */
   3891  1.172   msaitoh 		sc->ethercom.ec_if.if_capabilities |=
   3892   1.88      yamt 		    IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx |
   3893   1.88      yamt 		    IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx;
   3894  1.172   msaitoh #endif
   3895   1.87     perry 	sc->ethercom.ec_capabilities |=
   3896    1.1      fvdl 	    ETHERCAP_VLAN_HWTAGGING | ETHERCAP_VLAN_MTU;
   3897  1.335   msaitoh 	sc->ethercom.ec_capenable |= ETHERCAP_VLAN_HWTAGGING;
   3898    1.1      fvdl 
   3899  1.261   msaitoh 	if (sc->bge_flags & BGEF_TSO)
   3900   1.95  jonathan 		sc->ethercom.ec_if.if_capabilities |= IFCAP_TSOv4;
   3901   1.95  jonathan 
   3902    1.1      fvdl 	/*
   3903    1.1      fvdl 	 * Do MII setup.
   3904    1.1      fvdl 	 */
   3905    1.1      fvdl 	DPRINTFN(5, ("mii setup\n"));
   3906  1.331   msaitoh 	mii->mii_ifp = ifp;
   3907  1.331   msaitoh 	mii->mii_readreg = bge_miibus_readreg;
   3908  1.331   msaitoh 	mii->mii_writereg = bge_miibus_writereg;
   3909  1.331   msaitoh 	mii->mii_statchg = bge_miibus_statchg;
   3910    1.1      fvdl 
   3911    1.1      fvdl 	/*
   3912  1.203   msaitoh 	 * Figure out what sort of media we have by checking the hardware
   3913  1.241   msaitoh 	 * config word.  Note: on some BCM5700 cards, this value appears to be
   3914  1.241   msaitoh 	 * unset. If that's the case, we have to rely on identifying the NIC
   3915  1.241   msaitoh 	 * by its PCI subsystem ID, as we do below for the SysKonnect SK-9D41.
   3916  1.241   msaitoh 	 * The SysKonnect SK-9D41 is a 1000baseSX card.
   3917    1.1      fvdl 	 */
   3918  1.340   msaitoh 	if (PCI_PRODUCT(subid) == SK_SUBSYSID_9D41 ||
   3919  1.161   msaitoh 	    (hwcfg & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER) {
   3920  1.270   msaitoh 		if (BGE_IS_5705_PLUS(sc)) {
   3921  1.270   msaitoh 			sc->bge_flags |= BGEF_FIBER_MII;
   3922  1.270   msaitoh 			sc->bge_phy_flags |= BGEPHYF_NO_WIRESPEED;
   3923  1.270   msaitoh 		} else
   3924  1.270   msaitoh 			sc->bge_flags |= BGEF_FIBER_TBI;
   3925  1.161   msaitoh 	}
   3926    1.1      fvdl 
   3927  1.261   msaitoh 	/* Set bge_phy_flags before prop_dictionary_set_uint32() */
   3928  1.261   msaitoh 	if (BGE_IS_JUMBO_CAPABLE(sc))
   3929  1.261   msaitoh 		sc->bge_phy_flags |= BGEPHYF_JUMBO_CAPABLE;
   3930  1.261   msaitoh 
   3931  1.195       jym 	/* set phyflags and chipid before mii_attach() */
   3932  1.167   msaitoh 	dict = device_properties(self);
   3933  1.261   msaitoh 	prop_dictionary_set_uint32(dict, "phyflags", sc->bge_phy_flags);
   3934  1.195       jym 	prop_dictionary_set_uint32(dict, "chipid", sc->bge_chipid);
   3935  1.167   msaitoh 
   3936  1.342   msaitoh 	macmode = CSR_READ_4(sc, BGE_MAC_MODE);
   3937  1.342   msaitoh 	macmode &= ~BGE_MACMODE_PORTMODE;
   3938  1.334   msaitoh 	/* Initialize ifmedia structures. */
   3939  1.261   msaitoh 	if (sc->bge_flags & BGEF_FIBER_TBI) {
   3940  1.342   msaitoh 		CSR_WRITE_4_FLUSH(sc, BGE_MAC_MODE,
   3941  1.342   msaitoh 		    macmode | BGE_PORTMODE_TBI);
   3942  1.342   msaitoh 		DELAY(40);
   3943  1.342   msaitoh 
   3944  1.385     skrll 		struct ifmedia * const ifm = &sc->bge_ifmedia;
   3945  1.385     skrll 		sc->ethercom.ec_ifmedia = ifm;
   3946  1.385     skrll 		ifmedia_init(ifm, IFM_IMASK, bge_ifmedia_upd,
   3947    1.1      fvdl 		    bge_ifmedia_sts);
   3948  1.385     skrll 		ifmedia_add(ifm, IFM_ETHER | IFM_1000_SX, 0, NULL);
   3949  1.385     skrll 		ifmedia_add(ifm, IFM_ETHER | IFM_1000_SX | IFM_FDX, 0, NULL);
   3950  1.385     skrll 		ifmedia_add(ifm, IFM_ETHER | IFM_AUTO, 0, NULL);
   3951  1.385     skrll 		ifmedia_set(ifm, IFM_ETHER | IFM_AUTO);
   3952  1.155        he 		/* Pretend the user requested this setting */
   3953  1.162   msaitoh 		sc->bge_ifmedia.ifm_media = sc->bge_ifmedia.ifm_cur->ifm_media;
   3954    1.1      fvdl 	} else {
   3955  1.342   msaitoh 		uint16_t phyreg;
   3956  1.342   msaitoh 		int rv;
   3957    1.1      fvdl 		/*
   3958  1.177   msaitoh 		 * Do transceiver setup and tell the firmware the
   3959  1.177   msaitoh 		 * driver is down so we can try to get access the
   3960  1.177   msaitoh 		 * probe if ASF is running.  Retry a couple of times
   3961  1.177   msaitoh 		 * if we get a conflict with the ASF firmware accessing
   3962  1.177   msaitoh 		 * the PHY.
   3963    1.1      fvdl 		 */
   3964  1.342   msaitoh 		if (sc->bge_flags & BGEF_FIBER_MII)
   3965  1.342   msaitoh 			macmode |= BGE_PORTMODE_GMII;
   3966  1.342   msaitoh 		else
   3967  1.342   msaitoh 			macmode |= BGE_PORTMODE_MII;
   3968  1.342   msaitoh 		CSR_WRITE_4_FLUSH(sc, BGE_MAC_MODE, macmode);
   3969  1.342   msaitoh 		DELAY(40);
   3970  1.342   msaitoh 
   3971  1.342   msaitoh 		/*
   3972  1.342   msaitoh 		 * Do transceiver setup and tell the firmware the
   3973  1.342   msaitoh 		 * driver is down so we can try to get access the
   3974  1.342   msaitoh 		 * probe if ASF is running.  Retry a couple of times
   3975  1.342   msaitoh 		 * if we get a conflict with the ASF firmware accessing
   3976  1.342   msaitoh 		 * the PHY.
   3977  1.342   msaitoh 		 */
   3978  1.342   msaitoh 		trys = 0;
   3979  1.177   msaitoh 		BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
   3980  1.334   msaitoh 		sc->ethercom.ec_mii = mii;
   3981  1.331   msaitoh 		ifmedia_init(&mii->mii_media, 0, bge_ifmedia_upd,
   3982    1.1      fvdl 			     bge_ifmedia_sts);
   3983  1.269   msaitoh 		mii_flags = MIIF_DOPAUSE;
   3984  1.269   msaitoh 		if (sc->bge_flags & BGEF_FIBER_MII)
   3985  1.269   msaitoh 			mii_flags |= MIIF_HAVEFIBER;
   3986  1.342   msaitoh again:
   3987  1.342   msaitoh 		bge_asf_driver_up(sc);
   3988  1.342   msaitoh 		rv = bge_miibus_readreg(sc->bge_dev, sc->bge_phy_addr,
   3989  1.342   msaitoh 		    MII_BMCR, &phyreg);
   3990  1.342   msaitoh 		if ((rv != 0) || ((phyreg & BMCR_PDOWN) != 0)) {
   3991  1.342   msaitoh 			int i;
   3992  1.342   msaitoh 
   3993  1.342   msaitoh 			bge_miibus_writereg(sc->bge_dev, sc->bge_phy_addr,
   3994  1.342   msaitoh 			    MII_BMCR, BMCR_RESET);
   3995  1.342   msaitoh 			/* Wait up to 500ms for it to complete. */
   3996  1.342   msaitoh 			for (i = 0; i < 500; i++) {
   3997  1.342   msaitoh 				bge_miibus_readreg(sc->bge_dev,
   3998  1.342   msaitoh 				    sc->bge_phy_addr, MII_BMCR, &phyreg);
   3999  1.342   msaitoh 				if ((phyreg & BMCR_RESET) == 0)
   4000  1.342   msaitoh 					break;
   4001  1.342   msaitoh 				DELAY(1000);
   4002  1.342   msaitoh 			}
   4003  1.342   msaitoh 		}
   4004  1.342   msaitoh 
   4005  1.331   msaitoh 		mii_attach(sc->bge_dev, mii, capmask, sc->bge_phy_addr,
   4006  1.269   msaitoh 		    MII_OFFSET_ANY, mii_flags);
   4007   1.87     perry 
   4008  1.342   msaitoh 		if (LIST_EMPTY(&mii->mii_phys) && (trys++ < 4))
   4009  1.342   msaitoh 			goto again;
   4010  1.342   msaitoh 
   4011  1.331   msaitoh 		if (LIST_EMPTY(&mii->mii_phys)) {
   4012  1.138     joerg 			aprint_error_dev(sc->bge_dev, "no PHY found!\n");
   4013  1.331   msaitoh 			ifmedia_add(&mii->mii_media, IFM_ETHER | IFM_MANUAL,
   4014  1.331   msaitoh 			    0, NULL);
   4015  1.331   msaitoh 			ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_MANUAL);
   4016    1.1      fvdl 		} else
   4017  1.331   msaitoh 			ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_AUTO);
   4018  1.177   msaitoh 
   4019  1.177   msaitoh 		/*
   4020  1.177   msaitoh 		 * Now tell the firmware we are going up after probing the PHY
   4021  1.177   msaitoh 		 */
   4022  1.177   msaitoh 		if (sc->bge_asf_mode & ASF_STACKUP)
   4023  1.177   msaitoh 			BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
   4024    1.1      fvdl 	}
   4025    1.1      fvdl 
   4026    1.1      fvdl 	/*
   4027    1.1      fvdl 	 * Call MI attach routine.
   4028    1.1      fvdl 	 */
   4029  1.375     skrll 	DPRINTFN(5, ("if_initialize\n"));
   4030  1.375     skrll 	if_initialize(ifp);
   4031  1.375     skrll 	ifp->if_percpuq = if_percpuq_create(ifp);
   4032  1.299     ozaki 	if_deferred_start_init(ifp, NULL);
   4033  1.375     skrll 	if_register(ifp);
   4034  1.375     skrll 
   4035    1.1      fvdl 	DPRINTFN(5, ("ether_ifattach\n"));
   4036    1.1      fvdl 	ether_ifattach(ifp, eaddr);
   4037  1.186   msaitoh 	ether_set_ifflags_cb(&sc->ethercom, bge_ifflags_cb);
   4038  1.375     skrll 
   4039  1.148   mlelstv 	rnd_attach_source(&sc->rnd_source, device_xname(sc->bge_dev),
   4040  1.277       tls 		RND_TYPE_NET, RND_FLAG_DEFAULT);
   4041   1.72   thorpej #ifdef BGE_EVENT_COUNTERS
   4042   1.72   thorpej 	/*
   4043   1.72   thorpej 	 * Attach event counters.
   4044   1.72   thorpej 	 */
   4045   1.72   thorpej 	evcnt_attach_dynamic(&sc->bge_ev_intr, EVCNT_TYPE_INTR,
   4046  1.138     joerg 	    NULL, device_xname(sc->bge_dev), "intr");
   4047  1.302   msaitoh 	evcnt_attach_dynamic(&sc->bge_ev_intr_spurious, EVCNT_TYPE_INTR,
   4048  1.302   msaitoh 	    NULL, device_xname(sc->bge_dev), "intr_spurious");
   4049  1.302   msaitoh 	evcnt_attach_dynamic(&sc->bge_ev_intr_spurious2, EVCNT_TYPE_INTR,
   4050  1.302   msaitoh 	    NULL, device_xname(sc->bge_dev), "intr_spurious2");
   4051   1.72   thorpej 	evcnt_attach_dynamic(&sc->bge_ev_tx_xoff, EVCNT_TYPE_MISC,
   4052  1.138     joerg 	    NULL, device_xname(sc->bge_dev), "tx_xoff");
   4053   1.72   thorpej 	evcnt_attach_dynamic(&sc->bge_ev_tx_xon, EVCNT_TYPE_MISC,
   4054  1.138     joerg 	    NULL, device_xname(sc->bge_dev), "tx_xon");
   4055   1.72   thorpej 	evcnt_attach_dynamic(&sc->bge_ev_rx_xoff, EVCNT_TYPE_MISC,
   4056  1.138     joerg 	    NULL, device_xname(sc->bge_dev), "rx_xoff");
   4057   1.72   thorpej 	evcnt_attach_dynamic(&sc->bge_ev_rx_xon, EVCNT_TYPE_MISC,
   4058  1.138     joerg 	    NULL, device_xname(sc->bge_dev), "rx_xon");
   4059   1.72   thorpej 	evcnt_attach_dynamic(&sc->bge_ev_rx_macctl, EVCNT_TYPE_MISC,
   4060  1.138     joerg 	    NULL, device_xname(sc->bge_dev), "rx_macctl");
   4061   1.72   thorpej 	evcnt_attach_dynamic(&sc->bge_ev_xoffentered, EVCNT_TYPE_MISC,
   4062  1.138     joerg 	    NULL, device_xname(sc->bge_dev), "xoffentered");
   4063   1.72   thorpej #endif /* BGE_EVENT_COUNTERS */
   4064    1.1      fvdl 	DPRINTFN(5, ("callout_init\n"));
   4065  1.375     skrll 	callout_init(&sc->bge_timeout, CALLOUT_MPSAFE);
   4066  1.345   thorpej 	callout_setfunc(&sc->bge_timeout, bge_tick, sc);
   4067   1.82  jmcneill 
   4068  1.168   tsutsui 	if (pmf_device_register(self, NULL, NULL))
   4069  1.168   tsutsui 		pmf_class_network_register(self, ifp);
   4070  1.168   tsutsui 	else
   4071  1.141  jmcneill 		aprint_error_dev(self, "couldn't establish power handler\n");
   4072  1.172   msaitoh 
   4073  1.207   msaitoh 	bge_sysctl_init(sc);
   4074  1.190    jruoho 
   4075  1.172   msaitoh #ifdef BGE_DEBUG
   4076  1.172   msaitoh 	bge_debug_info(sc);
   4077  1.172   msaitoh #endif
   4078    1.1      fvdl }
   4079    1.1      fvdl 
   4080  1.227   msaitoh /*
   4081  1.227   msaitoh  * Stop all chip I/O so that the kernel's probe routines don't
   4082  1.227   msaitoh  * get confused by errant DMAs when rebooting.
   4083  1.227   msaitoh  */
   4084  1.227   msaitoh static int
   4085  1.227   msaitoh bge_detach(device_t self, int flags __unused)
   4086  1.227   msaitoh {
   4087  1.354     skrll 	struct bge_softc * const sc = device_private(self);
   4088  1.354     skrll 	struct ifnet * const ifp = &sc->ethercom.ec_if;
   4089  1.227   msaitoh 
   4090  1.227   msaitoh 	/* Stop the interface. Callouts are stopped in it. */
   4091  1.227   msaitoh 	bge_stop(ifp, 1);
   4092  1.227   msaitoh 
   4093  1.227   msaitoh 	mii_detach(&sc->bge_mii, MII_PHY_ANY, MII_OFFSET_ANY);
   4094  1.230  christos 
   4095  1.227   msaitoh 	ether_ifdetach(ifp);
   4096  1.227   msaitoh 	if_detach(ifp);
   4097  1.227   msaitoh 
   4098  1.344   thorpej 	/* Delete all remaining media. */
   4099  1.344   thorpej 	ifmedia_fini(&sc->bge_mii.mii_media);
   4100  1.344   thorpej 
   4101  1.227   msaitoh 	bge_release_resources(sc);
   4102  1.227   msaitoh 
   4103  1.227   msaitoh 	return 0;
   4104  1.227   msaitoh }
   4105  1.227   msaitoh 
   4106  1.104   thorpej static void
   4107  1.104   thorpej bge_release_resources(struct bge_softc *sc)
   4108    1.1      fvdl {
   4109    1.1      fvdl 
   4110  1.301   msaitoh 	/* Detach sysctl */
   4111  1.301   msaitoh 	if (sc->bge_log != NULL)
   4112  1.301   msaitoh 		sysctl_teardown(&sc->bge_log);
   4113  1.301   msaitoh 
   4114  1.301   msaitoh #ifdef BGE_EVENT_COUNTERS
   4115  1.301   msaitoh 	/* Detach event counters. */
   4116  1.301   msaitoh 	evcnt_detach(&sc->bge_ev_intr);
   4117  1.301   msaitoh 	evcnt_detach(&sc->bge_ev_intr_spurious);
   4118  1.301   msaitoh 	evcnt_detach(&sc->bge_ev_intr_spurious2);
   4119  1.301   msaitoh 	evcnt_detach(&sc->bge_ev_tx_xoff);
   4120  1.301   msaitoh 	evcnt_detach(&sc->bge_ev_tx_xon);
   4121  1.301   msaitoh 	evcnt_detach(&sc->bge_ev_rx_xoff);
   4122  1.301   msaitoh 	evcnt_detach(&sc->bge_ev_rx_xon);
   4123  1.301   msaitoh 	evcnt_detach(&sc->bge_ev_rx_macctl);
   4124  1.301   msaitoh 	evcnt_detach(&sc->bge_ev_xoffentered);
   4125  1.301   msaitoh #endif /* BGE_EVENT_COUNTERS */
   4126  1.301   msaitoh 
   4127  1.227   msaitoh 	/* Disestablish the interrupt handler */
   4128  1.227   msaitoh 	if (sc->bge_intrhand != NULL) {
   4129  1.227   msaitoh 		pci_intr_disestablish(sc->sc_pc, sc->bge_intrhand);
   4130  1.290   msaitoh 		pci_intr_release(sc->sc_pc, sc->bge_pihp, 1);
   4131  1.227   msaitoh 		sc->bge_intrhand = NULL;
   4132  1.227   msaitoh 	}
   4133  1.227   msaitoh 
   4134  1.373     skrll 	if (sc->bge_cdata.bge_jumbo_buf != NULL)
   4135  1.373     skrll 		bge_free_jumbo_mem(sc);
   4136  1.373     skrll 
   4137  1.239   msaitoh 	if (sc->bge_dmatag != NULL) {
   4138  1.239   msaitoh 		bus_dmamap_unload(sc->bge_dmatag, sc->bge_ring_map);
   4139  1.239   msaitoh 		bus_dmamap_destroy(sc->bge_dmatag, sc->bge_ring_map);
   4140  1.239   msaitoh 		bus_dmamem_unmap(sc->bge_dmatag, (void *)sc->bge_rdata,
   4141  1.239   msaitoh 		    sizeof(struct bge_ring_data));
   4142  1.294   msaitoh 		bus_dmamem_free(sc->bge_dmatag, &sc->bge_ring_seg,
   4143  1.294   msaitoh 		    sc->bge_ring_rseg);
   4144  1.239   msaitoh 	}
   4145  1.227   msaitoh 
   4146  1.227   msaitoh 	/* Unmap the device registers */
   4147  1.227   msaitoh 	if (sc->bge_bsize != 0) {
   4148  1.227   msaitoh 		bus_space_unmap(sc->bge_btag, sc->bge_bhandle, sc->bge_bsize);
   4149  1.227   msaitoh 		sc->bge_bsize = 0;
   4150  1.227   msaitoh 	}
   4151  1.227   msaitoh 
   4152  1.227   msaitoh 	/* Unmap the APE registers */
   4153  1.227   msaitoh 	if (sc->bge_apesize != 0) {
   4154  1.227   msaitoh 		bus_space_unmap(sc->bge_apetag, sc->bge_apehandle,
   4155  1.227   msaitoh 		    sc->bge_apesize);
   4156  1.227   msaitoh 		sc->bge_apesize = 0;
   4157  1.227   msaitoh 	}
   4158    1.1      fvdl }
   4159    1.1      fvdl 
   4160  1.177   msaitoh static int
   4161  1.104   thorpej bge_reset(struct bge_softc *sc)
   4162    1.1      fvdl {
   4163  1.216   msaitoh 	uint32_t cachesize, command;
   4164  1.216   msaitoh 	uint32_t reset, mac_mode, mac_mode_mask;
   4165  1.180   msaitoh 	pcireg_t devctl, reg;
   4166   1.76      cube 	int i, val;
   4167  1.151    cegger 	void (*write_op)(struct bge_softc *, int, int);
   4168  1.151    cegger 
   4169  1.253   msaitoh 	/* Make mask for BGE_MAC_MODE register. */
   4170  1.216   msaitoh 	mac_mode_mask = BGE_MACMODE_HALF_DUPLEX | BGE_MACMODE_PORTMODE;
   4171  1.216   msaitoh 	if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) != 0)
   4172  1.216   msaitoh 		mac_mode_mask |= BGE_MACMODE_APE_RX_EN | BGE_MACMODE_APE_TX_EN;
   4173  1.253   msaitoh 	/* Keep mac_mode_mask's bits of BGE_MAC_MODE register into mac_mode */
   4174  1.253   msaitoh 	mac_mode = CSR_READ_4(sc, BGE_MAC_MODE) & mac_mode_mask;
   4175  1.330   msaitoh 
   4176  1.216   msaitoh 	if (BGE_IS_575X_PLUS(sc) && !BGE_IS_5714_FAMILY(sc) &&
   4177  1.216   msaitoh 	    (BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5906)) {
   4178  1.330   msaitoh 		if (sc->bge_flags & BGEF_PCIE)
   4179  1.151    cegger 			write_op = bge_writemem_direct;
   4180  1.178   msaitoh 		else
   4181  1.151    cegger 			write_op = bge_writemem_ind;
   4182  1.178   msaitoh 	} else
   4183  1.151    cegger 		write_op = bge_writereg_ind;
   4184    1.1      fvdl 
   4185  1.236   msaitoh 	/* 57XX step 4 */
   4186  1.236   msaitoh 	/* Acquire the NVM lock */
   4187  1.261   msaitoh 	if ((sc->bge_flags & BGEF_NO_EEPROM) == 0 &&
   4188  1.232   msaitoh 	    BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5700 &&
   4189  1.216   msaitoh 	    BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5701) {
   4190  1.216   msaitoh 		CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_SET1);
   4191  1.216   msaitoh 		for (i = 0; i < 8000; i++) {
   4192  1.216   msaitoh 			if (CSR_READ_4(sc, BGE_NVRAM_SWARB) &
   4193  1.216   msaitoh 			    BGE_NVRAMSWARB_GNT1)
   4194  1.216   msaitoh 				break;
   4195  1.216   msaitoh 			DELAY(20);
   4196  1.216   msaitoh 		}
   4197  1.216   msaitoh 		if (i == 8000) {
   4198  1.216   msaitoh 			printf("%s: NVRAM lock timedout!\n",
   4199  1.216   msaitoh 			    device_xname(sc->bge_dev));
   4200  1.216   msaitoh 		}
   4201  1.216   msaitoh 	}
   4202  1.243   msaitoh 
   4203  1.216   msaitoh 	/* Take APE lock when performing reset. */
   4204  1.216   msaitoh 	bge_ape_lock(sc, BGE_APE_LOCK_GRC);
   4205  1.216   msaitoh 
   4206  1.236   msaitoh 	/* 57XX step 3 */
   4207    1.1      fvdl 	/* Save some important PCI state. */
   4208  1.141  jmcneill 	cachesize = pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CACHESZ);
   4209  1.236   msaitoh 	/* 5718 reset step 3 */
   4210  1.141  jmcneill 	command = pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CMD);
   4211  1.180   msaitoh 
   4212  1.236   msaitoh 	/* 5718 reset step 5, 57XX step 5b-5d */
   4213  1.141  jmcneill 	pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MISC_CTL,
   4214  1.172   msaitoh 	    BGE_PCIMISCCTL_INDIRECT_ACCESS | BGE_PCIMISCCTL_MASK_PCI_INTR |
   4215  1.172   msaitoh 	    BGE_HIF_SWAP_OPTIONS | BGE_PCIMISCCTL_PCISTATE_RW);
   4216    1.1      fvdl 
   4217  1.180   msaitoh 	/* XXX ???: Disable fastboot on controllers that support it. */
   4218  1.134     markd 	if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5752 ||
   4219  1.172   msaitoh 	    BGE_IS_5755_PLUS(sc))
   4220  1.119   tsutsui 		CSR_WRITE_4(sc, BGE_FASTBOOT_PC, 0);
   4221  1.119   tsutsui 
   4222  1.236   msaitoh 	/* 5718 reset step 2, 57XX step 6 */
   4223  1.177   msaitoh 	/*
   4224  1.236   msaitoh 	 * Write the magic number to SRAM at offset 0xB50.
   4225  1.177   msaitoh 	 * When firmware finishes its initialization it will
   4226  1.177   msaitoh 	 * write ~BGE_MAGIC_NUMBER to the same location.
   4227  1.177   msaitoh 	 */
   4228  1.216   msaitoh 	bge_writemem_ind(sc, BGE_SRAM_FW_MB, BGE_SRAM_FW_MB_MAGIC);
   4229  1.177   msaitoh 
   4230  1.304   msaitoh 	if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57780) {
   4231  1.304   msaitoh 		val = CSR_READ_4(sc, BGE_PCIE_LINKCTL);
   4232  1.304   msaitoh 		val = (val & ~BGE_PCIE_LINKCTL_L1_PLL_PDEN)
   4233  1.304   msaitoh 		    | BGE_PCIE_LINKCTL_L1_PLL_PDDIS;
   4234  1.304   msaitoh 		CSR_WRITE_4(sc, BGE_PCIE_LINKCTL, val);
   4235  1.304   msaitoh 	}
   4236  1.304   msaitoh 
   4237  1.236   msaitoh 	/* 5718 reset step 6, 57XX step 7 */
   4238  1.216   msaitoh 	reset = BGE_MISCCFG_RESET_CORE_CLOCKS | BGE_32BITTIME_66MHZ;
   4239   1.76      cube 	/*
   4240   1.76      cube 	 * XXX: from FreeBSD/Linux; no documentation
   4241   1.76      cube 	 */
   4242  1.261   msaitoh 	if (sc->bge_flags & BGEF_PCIE) {
   4243  1.278   msaitoh 		if ((BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5785) &&
   4244  1.214   msaitoh 		    !BGE_IS_57765_PLUS(sc) &&
   4245  1.216   msaitoh 		    (CSR_READ_4(sc, BGE_PHY_TEST_CTRL_REG) ==
   4246  1.214   msaitoh 			(BGE_PHY_PCIE_LTASS_MODE | BGE_PHY_PCIE_SCRAM_MODE))) {
   4247  1.157   msaitoh 			/* PCI Express 1.0 system */
   4248  1.214   msaitoh 			CSR_WRITE_4(sc, BGE_PHY_TEST_CTRL_REG,
   4249  1.214   msaitoh 			    BGE_PHY_PCIE_SCRAM_MODE);
   4250  1.214   msaitoh 		}
   4251   1.76      cube 		if (sc->bge_chipid != BGE_CHIPID_BCM5750_A0) {
   4252  1.157   msaitoh 			/*
   4253  1.157   msaitoh 			 * Prevent PCI Express link training
   4254  1.157   msaitoh 			 * during global reset.
   4255  1.157   msaitoh 			 */
   4256   1.76      cube 			CSR_WRITE_4(sc, BGE_MISC_CFG, 1 << 29);
   4257  1.222   msaitoh 			reset |= (1 << 29);
   4258   1.76      cube 		}
   4259   1.76      cube 	}
   4260   1.76      cube 
   4261  1.180   msaitoh 	if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) {
   4262  1.180   msaitoh 		i = CSR_READ_4(sc, BGE_VCPU_STATUS);
   4263  1.180   msaitoh 		CSR_WRITE_4(sc, BGE_VCPU_STATUS,
   4264  1.180   msaitoh 		    i | BGE_VCPU_STATUS_DRV_RESET);
   4265  1.180   msaitoh 		i = CSR_READ_4(sc, BGE_VCPU_EXT_CTRL);
   4266  1.180   msaitoh 		CSR_WRITE_4(sc, BGE_VCPU_EXT_CTRL,
   4267  1.180   msaitoh 		    i & ~BGE_VCPU_EXT_CTRL_HALT_CPU);
   4268  1.180   msaitoh 	}
   4269  1.180   msaitoh 
   4270  1.161   msaitoh 	/*
   4271  1.161   msaitoh 	 * Set GPHY Power Down Override to leave GPHY
   4272  1.161   msaitoh 	 * powered up in D0 uninitialized.
   4273  1.161   msaitoh 	 */
   4274  1.216   msaitoh 	if (BGE_IS_5705_PLUS(sc) &&
   4275  1.261   msaitoh 	    (sc->bge_flags & BGEF_CPMU_PRESENT) == 0)
   4276  1.216   msaitoh 		reset |= BGE_MISCCFG_GPHY_PD_OVERRIDE;
   4277  1.161   msaitoh 
   4278    1.1      fvdl 	/* Issue global reset */
   4279  1.216   msaitoh 	write_op(sc, BGE_MISC_CFG, reset);
   4280  1.151    cegger 
   4281  1.236   msaitoh 	/* 5718 reset step 7, 57XX step 8 */
   4282  1.261   msaitoh 	if (sc->bge_flags & BGEF_PCIE)
   4283  1.180   msaitoh 		delay(100*1000); /* too big */
   4284  1.180   msaitoh 	else
   4285  1.216   msaitoh 		delay(1000);
   4286  1.151    cegger 
   4287  1.261   msaitoh 	if (sc->bge_flags & BGEF_PCIE) {
   4288   1.76      cube 		if (sc->bge_chipid == BGE_CHIPID_BCM5750_A0) {
   4289   1.76      cube 			DELAY(500000);
   4290   1.76      cube 			/* XXX: Magic Numbers */
   4291  1.170   msaitoh 			reg = pci_conf_read(sc->sc_pc, sc->sc_pcitag,
   4292  1.170   msaitoh 			    BGE_PCI_UNKNOWN0);
   4293  1.170   msaitoh 			pci_conf_write(sc->sc_pc, sc->sc_pcitag,
   4294  1.170   msaitoh 			    BGE_PCI_UNKNOWN0,
   4295   1.76      cube 			    reg | (1 << 15));
   4296   1.76      cube 		}
   4297  1.177   msaitoh 		devctl = pci_conf_read(sc->sc_pc, sc->sc_pcitag,
   4298  1.238   msaitoh 		    sc->bge_pciecap + PCIE_DCSR);
   4299  1.177   msaitoh 		/* Clear enable no snoop and disable relaxed ordering. */
   4300  1.238   msaitoh 		devctl &= ~(PCIE_DCSR_ENA_RELAX_ORD |
   4301  1.238   msaitoh 		    PCIE_DCSR_ENA_NO_SNOOP);
   4302  1.216   msaitoh 
   4303  1.216   msaitoh 		/* Set PCIE max payload size to 128 for older PCIe devices */
   4304  1.261   msaitoh 		if ((sc->bge_flags & BGEF_CPMU_PRESENT) == 0)
   4305  1.216   msaitoh 			devctl &= ~(0x00e0);
   4306  1.179   msaitoh 		/* Clear device status register. Write 1b to clear */
   4307  1.238   msaitoh 		devctl |= PCIE_DCSR_URD | PCIE_DCSR_FED
   4308  1.238   msaitoh 		    | PCIE_DCSR_NFED | PCIE_DCSR_CED;
   4309  1.177   msaitoh 		pci_conf_write(sc->sc_pc, sc->sc_pcitag,
   4310  1.238   msaitoh 		    sc->bge_pciecap + PCIE_DCSR, devctl);
   4311  1.216   msaitoh 		bge_set_max_readrq(sc);
   4312  1.216   msaitoh 	}
   4313  1.216   msaitoh 
   4314  1.216   msaitoh 	/* From Linux: dummy read to flush PCI posted writes */
   4315  1.216   msaitoh 	reg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CMD);
   4316  1.216   msaitoh 
   4317  1.236   msaitoh 	/*
   4318  1.236   msaitoh 	 * Reset some of the PCI state that got zapped by reset
   4319  1.236   msaitoh 	 * To modify the PCISTATE register, BGE_PCIMISCCTL_PCISTATE_RW must be
   4320  1.236   msaitoh 	 * set, too.
   4321  1.236   msaitoh 	 */
   4322  1.216   msaitoh 	pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MISC_CTL,
   4323  1.216   msaitoh 	    BGE_PCIMISCCTL_INDIRECT_ACCESS | BGE_PCIMISCCTL_MASK_PCI_INTR |
   4324  1.216   msaitoh 	    BGE_HIF_SWAP_OPTIONS | BGE_PCIMISCCTL_PCISTATE_RW);
   4325  1.216   msaitoh 	val = BGE_PCISTATE_ROM_ENABLE | BGE_PCISTATE_ROM_RETRY_ENABLE;
   4326  1.216   msaitoh 	if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0 &&
   4327  1.261   msaitoh 	    (sc->bge_flags & BGEF_PCIX) != 0)
   4328  1.216   msaitoh 		val |= BGE_PCISTATE_RETRY_SAME_DMA;
   4329  1.216   msaitoh 	if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) != 0)
   4330  1.216   msaitoh 		val |= BGE_PCISTATE_ALLOW_APE_CTLSPC_WR |
   4331  1.216   msaitoh 		    BGE_PCISTATE_ALLOW_APE_SHMEM_WR |
   4332  1.216   msaitoh 		    BGE_PCISTATE_ALLOW_APE_PSPACE_WR;
   4333  1.216   msaitoh 	pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_PCISTATE, val);
   4334  1.216   msaitoh 	pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CACHESZ, cachesize);
   4335  1.216   msaitoh 	pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CMD, command);
   4336  1.216   msaitoh 
   4337  1.260   msaitoh 	/* 57xx step 11: disable PCI-X Relaxed Ordering. */
   4338  1.261   msaitoh 	if (sc->bge_flags & BGEF_PCIX) {
   4339  1.216   msaitoh 		reg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, sc->bge_pcixcap
   4340  1.238   msaitoh 		    + PCIX_CMD);
   4341  1.260   msaitoh 		/* Set max memory read byte count to 2K */
   4342  1.260   msaitoh 		if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5703) {
   4343  1.260   msaitoh 			reg &= ~PCIX_CMD_BYTECNT_MASK;
   4344  1.260   msaitoh 			reg |= PCIX_CMD_BCNT_2048;
   4345  1.260   msaitoh 		} else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704){
   4346  1.260   msaitoh 			/*
   4347  1.260   msaitoh 			 * For 5704, set max outstanding split transaction
   4348  1.260   msaitoh 			 * field to 0 (0 means it supports 1 request)
   4349  1.260   msaitoh 			 */
   4350  1.260   msaitoh 			reg &= ~(PCIX_CMD_SPLTRANS_MASK
   4351  1.260   msaitoh 			    | PCIX_CMD_BYTECNT_MASK);
   4352  1.260   msaitoh 			reg |= PCIX_CMD_BCNT_2048;
   4353  1.260   msaitoh 		}
   4354  1.216   msaitoh 		pci_conf_write(sc->sc_pc, sc->sc_pcitag, sc->bge_pcixcap
   4355  1.238   msaitoh 		    + PCIX_CMD, reg & ~PCIX_CMD_RELAXED_ORDER);
   4356   1.76      cube 	}
   4357   1.76      cube 
   4358  1.236   msaitoh 	/* 5718 reset step 10, 57XX step 12 */
   4359  1.236   msaitoh 	/* Enable memory arbiter. */
   4360  1.216   msaitoh 	if (BGE_IS_5714_FAMILY(sc)) {
   4361  1.216   msaitoh 		val = CSR_READ_4(sc, BGE_MARB_MODE);
   4362  1.216   msaitoh 		CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE | val);
   4363  1.216   msaitoh 	} else
   4364  1.216   msaitoh 		CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE);
   4365    1.1      fvdl 
   4366  1.180   msaitoh 	/* XXX 5721, 5751 and 5752 */
   4367  1.180   msaitoh 	if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5750) {
   4368  1.180   msaitoh 		/* Step 19: */
   4369  1.180   msaitoh 		BGE_SETBIT(sc, BGE_TLP_CONTROL_REG, 1 << 29 | 1 << 25);
   4370  1.180   msaitoh 		/* Step 20: */
   4371  1.180   msaitoh 		BGE_SETBIT(sc, BGE_TLP_CONTROL_REG, BGE_TLP_DATA_FIFO_PROTECT);
   4372   1.44   hannken 	}
   4373    1.1      fvdl 
   4374  1.274   msaitoh 	/* 5718 reset step 12, 57XX step 15 and 16 */
   4375  1.274   msaitoh 	/* Fix up byte swapping */
   4376  1.274   msaitoh 	CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS);
   4377  1.274   msaitoh 
   4378  1.253   msaitoh 	/* 5718 reset step 13, 57XX step 17 */
   4379  1.252   msaitoh 	/* Poll until the firmware initialization is complete */
   4380  1.252   msaitoh 	bge_poll_fw(sc);
   4381  1.252   msaitoh 
   4382  1.236   msaitoh 	/* 57XX step 21 */
   4383  1.181   msaitoh 	if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5704_BX) {
   4384  1.181   msaitoh 		pcireg_t msidata;
   4385  1.330   msaitoh 
   4386  1.181   msaitoh 		msidata = pci_conf_read(sc->sc_pc, sc->sc_pcitag,
   4387  1.181   msaitoh 		    BGE_PCI_MSI_DATA);
   4388  1.181   msaitoh 		msidata |= ((1 << 13 | 1 << 12 | 1 << 10) << 16);
   4389  1.181   msaitoh 		pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MSI_DATA,
   4390  1.181   msaitoh 		    msidata);
   4391  1.181   msaitoh 	}
   4392  1.151    cegger 
   4393  1.236   msaitoh 	/* 57XX step 18 */
   4394  1.253   msaitoh 	/* Write mac mode. */
   4395  1.216   msaitoh 	val = CSR_READ_4(sc, BGE_MAC_MODE);
   4396  1.253   msaitoh 	/* Restore mac_mode_mask's bits using mac_mode */
   4397  1.216   msaitoh 	val = (val & ~mac_mode_mask) | mac_mode;
   4398  1.216   msaitoh 	CSR_WRITE_4_FLUSH(sc, BGE_MAC_MODE, val);
   4399  1.216   msaitoh 	DELAY(40);
   4400    1.1      fvdl 
   4401  1.216   msaitoh 	bge_ape_unlock(sc, BGE_APE_LOCK_GRC);
   4402    1.1      fvdl 
   4403  1.161   msaitoh 	/*
   4404  1.161   msaitoh 	 * The 5704 in TBI mode apparently needs some special
   4405  1.161   msaitoh 	 * adjustment to insure the SERDES drive level is set
   4406  1.161   msaitoh 	 * to 1.2V.
   4407  1.161   msaitoh 	 */
   4408  1.261   msaitoh 	if (sc->bge_flags & BGEF_FIBER_TBI &&
   4409  1.161   msaitoh 	    BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) {
   4410  1.170   msaitoh 		uint32_t serdescfg;
   4411  1.161   msaitoh 
   4412  1.161   msaitoh 		serdescfg = CSR_READ_4(sc, BGE_SERDES_CFG);
   4413  1.161   msaitoh 		serdescfg = (serdescfg & ~0xFFF) | 0x880;
   4414  1.161   msaitoh 		CSR_WRITE_4(sc, BGE_SERDES_CFG, serdescfg);
   4415  1.161   msaitoh 	}
   4416  1.161   msaitoh 
   4417  1.261   msaitoh 	if (sc->bge_flags & BGEF_PCIE &&
   4418  1.214   msaitoh 	    !BGE_IS_57765_PLUS(sc) &&
   4419  1.172   msaitoh 	    sc->bge_chipid != BGE_CHIPID_BCM5750_A0 &&
   4420  1.214   msaitoh 	    BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5785) {
   4421  1.172   msaitoh 		uint32_t v;
   4422  1.172   msaitoh 
   4423  1.172   msaitoh 		/* Enable PCI Express bug fix */
   4424  1.217   msaitoh 		v = CSR_READ_4(sc, BGE_TLP_CONTROL_REG);
   4425  1.217   msaitoh 		CSR_WRITE_4(sc, BGE_TLP_CONTROL_REG,
   4426  1.217   msaitoh 		    v | BGE_TLP_DATA_FIFO_PROTECT);
   4427  1.172   msaitoh 	}
   4428  1.216   msaitoh 
   4429  1.216   msaitoh 	if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720)
   4430  1.216   msaitoh 		BGE_CLRBIT(sc, BGE_CPMU_CLCK_ORIDE,
   4431  1.216   msaitoh 		    CPMU_CLCK_ORIDE_MAC_ORIDE_EN);
   4432  1.177   msaitoh 
   4433  1.177   msaitoh 	return 0;
   4434    1.1      fvdl }
   4435    1.1      fvdl 
   4436    1.1      fvdl /*
   4437    1.1      fvdl  * Frame reception handling. This is called if there's a frame
   4438    1.1      fvdl  * on the receive return list.
   4439    1.1      fvdl  *
   4440    1.1      fvdl  * Note: we have to be able to handle two possibilities here:
   4441  1.184     njoly  * 1) the frame is from the jumbo receive ring
   4442    1.1      fvdl  * 2) the frame is from the standard receive ring
   4443    1.1      fvdl  */
   4444    1.1      fvdl 
   4445  1.104   thorpej static void
   4446  1.104   thorpej bge_rxeof(struct bge_softc *sc)
   4447    1.1      fvdl {
   4448  1.358     skrll 	struct ifnet * const ifp = &sc->ethercom.ec_if;
   4449  1.172   msaitoh 	uint16_t rx_prod, rx_cons;
   4450    1.1      fvdl 	int stdcnt = 0, jumbocnt = 0;
   4451    1.1      fvdl 	bus_dmamap_t dmamap;
   4452    1.1      fvdl 	bus_addr_t offset, toff;
   4453    1.1      fvdl 	bus_size_t tlen;
   4454    1.1      fvdl 	int tosync;
   4455    1.1      fvdl 
   4456  1.363     skrll 	bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map,
   4457  1.363     skrll 	    offsetof(struct bge_ring_data, bge_status_block),
   4458  1.364     skrll 	    sizeof(struct bge_status_block),
   4459  1.363     skrll 	    BUS_DMASYNC_POSTREAD);
   4460  1.363     skrll 
   4461  1.172   msaitoh 	rx_cons = sc->bge_rx_saved_considx;
   4462  1.172   msaitoh 	rx_prod = sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx;
   4463  1.172   msaitoh 
   4464  1.172   msaitoh 	/* Nothing to do */
   4465  1.172   msaitoh 	if (rx_cons == rx_prod)
   4466  1.172   msaitoh 		return;
   4467  1.172   msaitoh 
   4468    1.1      fvdl 	offset = offsetof(struct bge_ring_data, bge_rx_return_ring);
   4469  1.172   msaitoh 	tosync = rx_prod - rx_cons;
   4470    1.1      fvdl 
   4471  1.200       tls 	if (tosync != 0)
   4472  1.148   mlelstv 		rnd_add_uint32(&sc->rnd_source, tosync);
   4473  1.148   mlelstv 
   4474  1.364     skrll 	toff = offset + (rx_cons * sizeof(struct bge_rx_bd));
   4475    1.1      fvdl 
   4476    1.1      fvdl 	if (tosync < 0) {
   4477  1.172   msaitoh 		tlen = (sc->bge_return_ring_cnt - rx_cons) *
   4478  1.364     skrll 		    sizeof(struct bge_rx_bd);
   4479    1.1      fvdl 		bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map,
   4480    1.1      fvdl 		    toff, tlen, BUS_DMASYNC_POSTREAD);
   4481  1.374     skrll 		tosync = rx_prod;
   4482  1.374     skrll 		toff = offset;
   4483    1.1      fvdl 	}
   4484    1.1      fvdl 
   4485  1.347  jmcneill 	if (tosync != 0) {
   4486  1.347  jmcneill 		bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map,
   4487  1.374     skrll 		    toff, tosync * sizeof(struct bge_rx_bd),
   4488  1.347  jmcneill 		    BUS_DMASYNC_POSTREAD);
   4489  1.347  jmcneill 	}
   4490    1.1      fvdl 
   4491  1.172   msaitoh 	while (rx_cons != rx_prod) {
   4492    1.1      fvdl 		struct bge_rx_bd	*cur_rx;
   4493  1.170   msaitoh 		uint32_t		rxidx;
   4494    1.1      fvdl 		struct mbuf		*m = NULL;
   4495    1.1      fvdl 
   4496  1.172   msaitoh 		cur_rx = &sc->bge_rdata->bge_rx_return_ring[rx_cons];
   4497    1.1      fvdl 
   4498    1.1      fvdl 		rxidx = cur_rx->bge_idx;
   4499  1.172   msaitoh 		BGE_INC(rx_cons, sc->bge_return_ring_cnt);
   4500    1.1      fvdl 
   4501    1.1      fvdl 		if (cur_rx->bge_flags & BGE_RXBDFLAG_JUMBO_RING) {
   4502    1.1      fvdl 			BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT);
   4503    1.1      fvdl 			m = sc->bge_cdata.bge_rx_jumbo_chain[rxidx];
   4504    1.1      fvdl 			sc->bge_cdata.bge_rx_jumbo_chain[rxidx] = NULL;
   4505    1.1      fvdl 			jumbocnt++;
   4506  1.124    bouyer 			bus_dmamap_sync(sc->bge_dmatag,
   4507  1.124    bouyer 			    sc->bge_cdata.bge_rx_jumbo_map,
   4508  1.126  christos 			    mtod(m, char *) - (char *)sc->bge_cdata.bge_jumbo_buf,
   4509  1.125    bouyer 			    BGE_JLEN, BUS_DMASYNC_POSTREAD);
   4510    1.1      fvdl 			if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) {
   4511  1.343   thorpej 				if_statinc(ifp, if_ierrors);
   4512    1.1      fvdl 				bge_newbuf_jumbo(sc, sc->bge_jumbo, m);
   4513    1.1      fvdl 				continue;
   4514    1.1      fvdl 			}
   4515    1.1      fvdl 			if (bge_newbuf_jumbo(sc, sc->bge_jumbo,
   4516  1.367     skrll 					     NULL) == ENOBUFS) {
   4517  1.343   thorpej 				if_statinc(ifp, if_ierrors);
   4518    1.1      fvdl 				bge_newbuf_jumbo(sc, sc->bge_jumbo, m);
   4519    1.1      fvdl 				continue;
   4520    1.1      fvdl 			}
   4521    1.1      fvdl 		} else {
   4522    1.1      fvdl 			m = sc->bge_cdata.bge_rx_std_chain[rxidx];
   4523  1.376     skrll 			sc->bge_cdata.bge_rx_std_chain[rxidx] = NULL;
   4524  1.124    bouyer 
   4525    1.1      fvdl 			stdcnt++;
   4526  1.376     skrll 			sc->bge_std_cnt--;
   4527  1.376     skrll 
   4528    1.1      fvdl 			dmamap = sc->bge_cdata.bge_rx_std_map[rxidx];
   4529  1.125    bouyer 			bus_dmamap_sync(sc->bge_dmatag, dmamap, 0,
   4530  1.125    bouyer 			    dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD);
   4531  1.125    bouyer 			bus_dmamap_unload(sc->bge_dmatag, dmamap);
   4532  1.376     skrll 
   4533    1.1      fvdl 			if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) {
   4534  1.376     skrll 				m_free(m);
   4535  1.343   thorpej 				if_statinc(ifp, if_ierrors);
   4536    1.1      fvdl 				continue;
   4537    1.1      fvdl 			}
   4538    1.1      fvdl 		}
   4539    1.1      fvdl 
   4540   1.37  jonathan #ifndef __NO_STRICT_ALIGNMENT
   4541  1.178   msaitoh 		/*
   4542  1.178   msaitoh 		 * XXX: if the 5701 PCIX-Rx-DMA workaround is in effect,
   4543  1.178   msaitoh 		 * the Rx buffer has the layer-2 header unaligned.
   4544  1.178   msaitoh 		 * If our CPU requires alignment, re-align by copying.
   4545  1.178   msaitoh 		 */
   4546  1.261   msaitoh 		if (sc->bge_flags & BGEF_RX_ALIGNBUG) {
   4547  1.127   tsutsui 			memmove(mtod(m, char *) + ETHER_ALIGN, m->m_data,
   4548  1.178   msaitoh 				cur_rx->bge_len);
   4549   1.37  jonathan 			m->m_data += ETHER_ALIGN;
   4550   1.37  jonathan 		}
   4551   1.37  jonathan #endif
   4552   1.87     perry 
   4553   1.54      fvdl 		m->m_pkthdr.len = m->m_len = cur_rx->bge_len - ETHER_CRC_LEN;
   4554  1.297     ozaki 		m_set_rcvif(m, ifp);
   4555    1.1      fvdl 
   4556  1.219   msaitoh 		bge_rxcsum(sc, cur_rx, m);
   4557  1.219   msaitoh 
   4558  1.219   msaitoh 		/*
   4559  1.219   msaitoh 		 * If we received a packet with a vlan tag, pass it
   4560  1.219   msaitoh 		 * to vlan_input() instead of ether_input().
   4561  1.219   msaitoh 		 */
   4562  1.332   msaitoh 		if (cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG)
   4563  1.313   msaitoh 			vlan_set_tag(m, cur_rx->bge_vlan_tag);
   4564  1.219   msaitoh 
   4565  1.295     ozaki 		if_percpuq_enqueue(ifp->if_percpuq, m);
   4566  1.219   msaitoh 	}
   4567  1.219   msaitoh 
   4568  1.219   msaitoh 	sc->bge_rx_saved_considx = rx_cons;
   4569  1.219   msaitoh 	bge_writembx(sc, BGE_MBX_RX_CONS0_LO, sc->bge_rx_saved_considx);
   4570  1.219   msaitoh 	if (stdcnt)
   4571  1.376     skrll 		bge_fill_rx_ring_std(sc);
   4572  1.219   msaitoh 	if (jumbocnt)
   4573  1.219   msaitoh 		bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo);
   4574  1.219   msaitoh }
   4575  1.219   msaitoh 
   4576  1.219   msaitoh static void
   4577  1.219   msaitoh bge_rxcsum(struct bge_softc *sc, struct bge_rx_bd *cur_rx, struct mbuf *m)
   4578  1.219   msaitoh {
   4579   1.46  jonathan 
   4580  1.257   msaitoh 	if (BGE_IS_57765_PLUS(sc)) {
   4581  1.219   msaitoh 		if ((cur_rx->bge_flags & BGE_RXBDFLAG_IPV6) == 0) {
   4582  1.219   msaitoh 			if ((cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM) != 0)
   4583  1.219   msaitoh 				m->m_pkthdr.csum_flags = M_CSUM_IPv4;
   4584  1.216   msaitoh 			if ((cur_rx->bge_error_flag &
   4585  1.216   msaitoh 				BGE_RXERRFLAG_IP_CSUM_NOK) != 0)
   4586  1.216   msaitoh 				m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD;
   4587  1.219   msaitoh 			if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM) {
   4588  1.219   msaitoh 				m->m_pkthdr.csum_data =
   4589  1.219   msaitoh 				    cur_rx->bge_tcp_udp_csum;
   4590  1.219   msaitoh 				m->m_pkthdr.csum_flags |=
   4591  1.331   msaitoh 				    (M_CSUM_TCPv4 | M_CSUM_UDPv4 |M_CSUM_DATA);
   4592  1.219   msaitoh 			}
   4593  1.216   msaitoh 		}
   4594  1.219   msaitoh 	} else {
   4595  1.219   msaitoh 		if ((cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM) != 0)
   4596  1.219   msaitoh 			m->m_pkthdr.csum_flags = M_CSUM_IPv4;
   4597  1.219   msaitoh 		if ((cur_rx->bge_ip_csum ^ 0xffff) != 0)
   4598  1.219   msaitoh 			m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD;
   4599   1.46  jonathan 		/*
   4600   1.46  jonathan 		 * Rx transport checksum-offload may also
   4601   1.46  jonathan 		 * have bugs with packets which, when transmitted,
   4602   1.46  jonathan 		 * were `runts' requiring padding.
   4603   1.46  jonathan 		 */
   4604   1.46  jonathan 		if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM &&
   4605   1.46  jonathan 		    (/* (sc->_bge_quirks & BGE_QUIRK_SHORT_CKSUM_BUG) == 0 ||*/
   4606  1.219   msaitoh 			    m->m_pkthdr.len >= ETHER_MIN_NOPAD)) {
   4607   1.46  jonathan 			m->m_pkthdr.csum_data =
   4608   1.46  jonathan 			    cur_rx->bge_tcp_udp_csum;
   4609   1.46  jonathan 			m->m_pkthdr.csum_flags |=
   4610  1.331   msaitoh 			    (M_CSUM_TCPv4 | M_CSUM_UDPv4 | M_CSUM_DATA);
   4611    1.1      fvdl 		}
   4612    1.1      fvdl 	}
   4613    1.1      fvdl }
   4614    1.1      fvdl 
   4615  1.104   thorpej static void
   4616  1.104   thorpej bge_txeof(struct bge_softc *sc)
   4617    1.1      fvdl {
   4618  1.358     skrll 	struct ifnet * const ifp = &sc->ethercom.ec_if;
   4619    1.1      fvdl 	struct bge_tx_bd *cur_tx = NULL;
   4620    1.1      fvdl 	struct txdmamap_pool_entry *dma;
   4621    1.1      fvdl 	bus_addr_t offset, toff;
   4622    1.1      fvdl 	bus_size_t tlen;
   4623    1.1      fvdl 	int tosync;
   4624    1.1      fvdl 	struct mbuf *m;
   4625    1.1      fvdl 
   4626    1.1      fvdl 	bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map,
   4627    1.1      fvdl 	    offsetof(struct bge_ring_data, bge_status_block),
   4628  1.364     skrll 	    sizeof(struct bge_status_block),
   4629    1.1      fvdl 	    BUS_DMASYNC_POSTREAD);
   4630    1.1      fvdl 
   4631  1.374     skrll 	const uint16_t hw_cons_idx =
   4632  1.374     skrll 	    sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx;
   4633    1.1      fvdl 	offset = offsetof(struct bge_ring_data, bge_tx_ring);
   4634  1.374     skrll 	tosync = hw_cons_idx - sc->bge_tx_saved_considx;
   4635    1.1      fvdl 
   4636  1.200       tls 	if (tosync != 0)
   4637  1.148   mlelstv 		rnd_add_uint32(&sc->rnd_source, tosync);
   4638  1.148   mlelstv 
   4639  1.364     skrll 	toff = offset + (sc->bge_tx_saved_considx * sizeof(struct bge_tx_bd));
   4640    1.1      fvdl 
   4641    1.1      fvdl 	if (tosync < 0) {
   4642    1.1      fvdl 		tlen = (BGE_TX_RING_CNT - sc->bge_tx_saved_considx) *
   4643  1.364     skrll 		    sizeof(struct bge_tx_bd);
   4644    1.1      fvdl 		bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map,
   4645  1.331   msaitoh 		    toff, tlen, BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
   4646  1.374     skrll 		tosync = hw_cons_idx;
   4647  1.374     skrll 		toff = offset;
   4648    1.1      fvdl 	}
   4649    1.1      fvdl 
   4650  1.347  jmcneill 	if (tosync != 0) {
   4651  1.347  jmcneill 		bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map,
   4652  1.374     skrll 		    toff, tosync * sizeof(struct bge_tx_bd),
   4653  1.347  jmcneill 		    BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
   4654  1.347  jmcneill 	}
   4655    1.1      fvdl 
   4656    1.1      fvdl 	/*
   4657    1.1      fvdl 	 * Go through our tx ring and free mbufs for those
   4658    1.1      fvdl 	 * frames that have been sent.
   4659    1.1      fvdl 	 */
   4660  1.374     skrll 	while (sc->bge_tx_saved_considx != hw_cons_idx) {
   4661  1.359     skrll 		uint32_t idx = sc->bge_tx_saved_considx;
   4662    1.1      fvdl 		cur_tx = &sc->bge_rdata->bge_tx_ring[idx];
   4663    1.1      fvdl 		if (cur_tx->bge_flags & BGE_TXBDFLAG_END)
   4664  1.343   thorpej 			if_statinc(ifp, if_opackets);
   4665    1.1      fvdl 		m = sc->bge_cdata.bge_tx_chain[idx];
   4666    1.1      fvdl 		if (m != NULL) {
   4667    1.1      fvdl 			sc->bge_cdata.bge_tx_chain[idx] = NULL;
   4668    1.1      fvdl 			dma = sc->txdma[idx];
   4669  1.317    bouyer 			if (dma->is_dma32) {
   4670  1.317    bouyer 				bus_dmamap_sync(sc->bge_dmatag32, dma->dmamap32,
   4671  1.317    bouyer 				    0, dma->dmamap32->dm_mapsize,
   4672  1.317    bouyer 				    BUS_DMASYNC_POSTWRITE);
   4673  1.317    bouyer 				bus_dmamap_unload(
   4674  1.317    bouyer 				    sc->bge_dmatag32, dma->dmamap32);
   4675  1.317    bouyer 			} else {
   4676  1.317    bouyer 				bus_dmamap_sync(sc->bge_dmatag, dma->dmamap,
   4677  1.317    bouyer 				    0, dma->dmamap->dm_mapsize,
   4678  1.317    bouyer 				    BUS_DMASYNC_POSTWRITE);
   4679  1.317    bouyer 				bus_dmamap_unload(sc->bge_dmatag, dma->dmamap);
   4680  1.317    bouyer 			}
   4681    1.1      fvdl 			SLIST_INSERT_HEAD(&sc->txdma_list, dma, link);
   4682    1.1      fvdl 			sc->txdma[idx] = NULL;
   4683    1.1      fvdl 
   4684    1.1      fvdl 			m_freem(m);
   4685    1.1      fvdl 		}
   4686    1.1      fvdl 		sc->bge_txcnt--;
   4687    1.1      fvdl 		BGE_INC(sc->bge_tx_saved_considx, BGE_TX_RING_CNT);
   4688  1.375     skrll 		sc->bge_tx_sending = false;
   4689    1.1      fvdl 	}
   4690    1.1      fvdl }
   4691    1.1      fvdl 
   4692  1.104   thorpej static int
   4693  1.104   thorpej bge_intr(void *xsc)
   4694    1.1      fvdl {
   4695  1.354     skrll 	struct bge_softc * const sc = xsc;
   4696  1.354     skrll 	struct ifnet * const ifp = &sc->ethercom.ec_if;
   4697  1.288   msaitoh 	uint32_t pcistate, statusword, statustag;
   4698  1.247   msaitoh 	uint32_t intrmask = BGE_PCISTATE_INTR_NOT_ACTIVE;
   4699    1.1      fvdl 
   4700  1.247   msaitoh 	/* 5717 and newer chips have no BGE_PCISTATE_INTR_NOT_ACTIVE bit */
   4701  1.247   msaitoh 	if (BGE_IS_5717_PLUS(sc))
   4702  1.247   msaitoh 		intrmask = 0;
   4703  1.247   msaitoh 
   4704  1.375     skrll 	mutex_enter(sc->sc_core_lock);
   4705  1.375     skrll 
   4706  1.357     skrll 	/*
   4707  1.357     skrll 	 * It is possible for the interrupt to arrive before
   4708  1.161   msaitoh 	 * the status block is updated prior to the interrupt.
   4709  1.161   msaitoh 	 * Reading the PCI State register will confirm whether the
   4710  1.161   msaitoh 	 * interrupt is ours and will flush the status block.
   4711  1.161   msaitoh 	 */
   4712  1.288   msaitoh 	pcistate = CSR_READ_4(sc, BGE_PCI_PCISTATE);
   4713  1.144   mlelstv 
   4714  1.161   msaitoh 	/* read status word from status block */
   4715  1.240   msaitoh 	bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map,
   4716  1.240   msaitoh 	    offsetof(struct bge_ring_data, bge_status_block),
   4717  1.364     skrll 	    sizeof(struct bge_status_block),
   4718  1.240   msaitoh 	    BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
   4719  1.161   msaitoh 	statusword = sc->bge_rdata->bge_status_block.bge_status;
   4720  1.288   msaitoh 	statustag = sc->bge_rdata->bge_status_block.bge_status_tag << 24;
   4721  1.144   mlelstv 
   4722  1.288   msaitoh 	if (sc->bge_flags & BGEF_TAGGED_STATUS) {
   4723  1.288   msaitoh 		if (sc->bge_lasttag == statustag &&
   4724  1.288   msaitoh 		    (~pcistate & intrmask)) {
   4725  1.306   msaitoh 			BGE_EVCNT_INCR(sc->bge_ev_intr_spurious);
   4726  1.375     skrll 			mutex_exit(sc->sc_core_lock);
   4727  1.362     skrll 			return 0;
   4728  1.288   msaitoh 		}
   4729  1.288   msaitoh 		sc->bge_lasttag = statustag;
   4730  1.288   msaitoh 	} else {
   4731  1.288   msaitoh 		if (!(statusword & BGE_STATFLAG_UPDATED) &&
   4732  1.288   msaitoh 		    !(~pcistate & intrmask)) {
   4733  1.306   msaitoh 			BGE_EVCNT_INCR(sc->bge_ev_intr_spurious2);
   4734  1.375     skrll 			mutex_exit(sc->sc_core_lock);
   4735  1.362     skrll 			return 0;
   4736  1.288   msaitoh 		}
   4737  1.288   msaitoh 		statustag = 0;
   4738  1.288   msaitoh 	}
   4739  1.288   msaitoh 	/* Ack interrupt and stop others from occurring. */
   4740  1.288   msaitoh 	bge_writembx_flush(sc, BGE_MBX_IRQ0_LO, 1);
   4741  1.288   msaitoh 	BGE_EVCNT_INCR(sc->bge_ev_intr);
   4742  1.144   mlelstv 
   4743  1.288   msaitoh 	/* clear status word */
   4744  1.288   msaitoh 	sc->bge_rdata->bge_status_block.bge_status = 0;
   4745    1.1      fvdl 
   4746  1.288   msaitoh 	bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map,
   4747  1.288   msaitoh 	    offsetof(struct bge_ring_data, bge_status_block),
   4748  1.364     skrll 	    sizeof(struct bge_status_block),
   4749  1.288   msaitoh 	    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
   4750   1.72   thorpej 
   4751  1.288   msaitoh 	if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 ||
   4752  1.288   msaitoh 	    statusword & BGE_STATFLAG_LINKSTATE_CHANGED ||
   4753  1.288   msaitoh 	    BGE_STS_BIT(sc, BGE_STS_LINK_EVT))
   4754  1.288   msaitoh 		bge_link_upd(sc);
   4755    1.1      fvdl 
   4756  1.375     skrll 	if (sc->bge_if_flags & IFF_RUNNING) {
   4757  1.288   msaitoh 		/* Check RX return ring producer/consumer */
   4758  1.288   msaitoh 		bge_rxeof(sc);
   4759  1.144   mlelstv 
   4760  1.288   msaitoh 		/* Check TX ring producer/consumer */
   4761  1.288   msaitoh 		bge_txeof(sc);
   4762  1.288   msaitoh 	}
   4763    1.1      fvdl 
   4764  1.288   msaitoh 	if (sc->bge_pending_rxintr_change) {
   4765  1.288   msaitoh 		uint32_t rx_ticks = sc->bge_rx_coal_ticks;
   4766  1.288   msaitoh 		uint32_t rx_bds = sc->bge_rx_max_coal_bds;
   4767    1.1      fvdl 
   4768  1.288   msaitoh 		CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, rx_ticks);
   4769  1.288   msaitoh 		DELAY(10);
   4770  1.288   msaitoh 		(void)CSR_READ_4(sc, BGE_HCC_RX_COAL_TICKS);
   4771    1.1      fvdl 
   4772  1.288   msaitoh 		CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, rx_bds);
   4773  1.288   msaitoh 		DELAY(10);
   4774  1.288   msaitoh 		(void)CSR_READ_4(sc, BGE_HCC_RX_MAX_COAL_BDS);
   4775   1.58  jonathan 
   4776  1.384     skrll 		sc->bge_pending_rxintr_change = false;
   4777  1.288   msaitoh 	}
   4778  1.288   msaitoh 	bge_handle_events(sc);
   4779   1.87     perry 
   4780  1.288   msaitoh 	/* Re-enable interrupts. */
   4781  1.288   msaitoh 	bge_writembx_flush(sc, BGE_MBX_IRQ0_LO, statustag);
   4782   1.58  jonathan 
   4783  1.375     skrll 	if (sc->bge_if_flags & IFF_RUNNING)
   4784  1.299     ozaki 		if_schedule_deferred_start(ifp);
   4785    1.1      fvdl 
   4786  1.375     skrll 	mutex_exit(sc->sc_core_lock);
   4787  1.375     skrll 
   4788  1.288   msaitoh 	return 1;
   4789    1.1      fvdl }
   4790    1.1      fvdl 
   4791  1.104   thorpej static void
   4792  1.177   msaitoh bge_asf_driver_up(struct bge_softc *sc)
   4793  1.177   msaitoh {
   4794  1.177   msaitoh 	if (sc->bge_asf_mode & ASF_STACKUP) {
   4795  1.382     skrll 		/* Send ASF heartbeat approx. every 2s */
   4796  1.177   msaitoh 		if (sc->bge_asf_count)
   4797  1.177   msaitoh 			sc->bge_asf_count --;
   4798  1.177   msaitoh 		else {
   4799  1.180   msaitoh 			sc->bge_asf_count = 2;
   4800  1.216   msaitoh 
   4801  1.216   msaitoh 			bge_wait_for_event_ack(sc);
   4802  1.216   msaitoh 
   4803  1.216   msaitoh 			bge_writemem_ind(sc, BGE_SRAM_FW_CMD_MB,
   4804  1.285   msaitoh 			    BGE_FW_CMD_DRV_ALIVE3);
   4805  1.216   msaitoh 			bge_writemem_ind(sc, BGE_SRAM_FW_CMD_LEN_MB, 4);
   4806  1.216   msaitoh 			bge_writemem_ind(sc, BGE_SRAM_FW_CMD_DATA_MB,
   4807  1.216   msaitoh 			    BGE_FW_HB_TIMEOUT_SEC);
   4808  1.216   msaitoh 			CSR_WRITE_4_FLUSH(sc, BGE_RX_CPU_EVENT,
   4809  1.216   msaitoh 			    CSR_READ_4(sc, BGE_RX_CPU_EVENT) |
   4810  1.216   msaitoh 			    BGE_RX_CPU_DRV_EVENT);
   4811  1.177   msaitoh 		}
   4812  1.177   msaitoh 	}
   4813  1.177   msaitoh }
   4814  1.177   msaitoh 
   4815  1.177   msaitoh static void
   4816  1.104   thorpej bge_tick(void *xsc)
   4817    1.1      fvdl {
   4818  1.354     skrll 	struct bge_softc * const sc = xsc;
   4819  1.375     skrll 	struct ifnet * const ifp = &sc->ethercom.ec_if;
   4820  1.354     skrll 	struct mii_data * const mii = &sc->bge_mii;
   4821    1.1      fvdl 
   4822  1.375     skrll 	mutex_enter(sc->sc_core_lock);
   4823    1.1      fvdl 
   4824  1.172   msaitoh 	if (BGE_IS_5705_PLUS(sc))
   4825  1.172   msaitoh 		bge_stats_update_regs(sc);
   4826  1.172   msaitoh 	else
   4827  1.172   msaitoh 		bge_stats_update(sc);
   4828    1.1      fvdl 
   4829  1.261   msaitoh 	if (sc->bge_flags & BGEF_FIBER_TBI) {
   4830  1.161   msaitoh 		/*
   4831  1.161   msaitoh 		 * Since in TBI mode auto-polling can't be used we should poll
   4832  1.161   msaitoh 		 * link status manually. Here we register pending link event
   4833  1.161   msaitoh 		 * and trigger interrupt.
   4834  1.161   msaitoh 		 */
   4835  1.161   msaitoh 		BGE_STS_SETBIT(sc, BGE_STS_LINK_EVT);
   4836  1.161   msaitoh 		BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET);
   4837  1.161   msaitoh 	} else {
   4838  1.161   msaitoh 		/*
   4839  1.161   msaitoh 		 * Do not touch PHY if we have link up. This could break
   4840  1.161   msaitoh 		 * IPMI/ASF mode or produce extra input errors.
   4841  1.161   msaitoh 		 * (extra input errors was reported for bcm5701 & bcm5704).
   4842  1.161   msaitoh 		 */
   4843  1.161   msaitoh 		if (!BGE_STS_BIT(sc, BGE_STS_LINK))
   4844  1.161   msaitoh 			mii_tick(mii);
   4845  1.161   msaitoh 	}
   4846  1.161   msaitoh 
   4847  1.216   msaitoh 	bge_asf_driver_up(sc);
   4848  1.216   msaitoh 
   4849  1.375     skrll 	const bool ok = bge_watchdog(ifp);
   4850  1.375     skrll 
   4851  1.375     skrll 	if (ok && !sc->bge_detaching)
   4852  1.345   thorpej 		callout_schedule(&sc->bge_timeout, hz);
   4853    1.1      fvdl 
   4854  1.375     skrll 	mutex_exit(sc->sc_core_lock);
   4855    1.1      fvdl }
   4856    1.1      fvdl 
   4857  1.104   thorpej static void
   4858  1.172   msaitoh bge_stats_update_regs(struct bge_softc *sc)
   4859  1.172   msaitoh {
   4860  1.375     skrll 	struct ifnet * const ifp = &sc->ethercom.ec_if;
   4861  1.172   msaitoh 
   4862  1.343   thorpej 	net_stat_ref_t nsr = IF_STAT_GETREF(ifp);
   4863  1.343   thorpej 
   4864  1.343   thorpej 	if_statadd_ref(nsr, if_collisions,
   4865  1.343   thorpej 	    CSR_READ_4(sc, BGE_MAC_STATS +
   4866  1.343   thorpej 	    offsetof(struct bge_mac_stats_regs, etherStatsCollisions)));
   4867  1.172   msaitoh 
   4868  1.320    bouyer 	/*
   4869  1.320    bouyer 	 * On BCM5717, BCM5718, BCM5719 A0 and BCM5720 A0,
   4870  1.320    bouyer 	 * RXLP_LOCSTAT_IFIN_DROPS includes unwanted multicast frames
   4871  1.320    bouyer 	 * (silicon bug). There's no reliable workaround so just
   4872  1.320    bouyer 	 * ignore the counter
   4873  1.320    bouyer 	 */
   4874  1.320    bouyer 	if (BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5717 &&
   4875  1.328    bouyer 	    sc->bge_chipid != BGE_CHIPID_BCM5719_A0 &&
   4876  1.328    bouyer 	    sc->bge_chipid != BGE_CHIPID_BCM5720_A0) {
   4877  1.343   thorpej 		if_statadd_ref(nsr, if_ierrors,
   4878  1.343   thorpej 		    CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_DROPS));
   4879  1.320    bouyer 	}
   4880  1.343   thorpej 	if_statadd_ref(nsr, if_ierrors,
   4881  1.343   thorpej 	    CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_ERRORS));
   4882  1.343   thorpej 	if_statadd_ref(nsr, if_ierrors,
   4883  1.343   thorpej 	    CSR_READ_4(sc, BGE_RXLP_LOCSTAT_OUT_OF_BDS));
   4884  1.343   thorpej 
   4885  1.343   thorpej 	IF_STAT_PUTREF(ifp);
   4886  1.327   msaitoh 
   4887  1.327   msaitoh 	if (sc->bge_flags & BGEF_RDMA_BUG) {
   4888  1.327   msaitoh 		uint32_t val, ucast, mcast, bcast;
   4889  1.327   msaitoh 
   4890  1.327   msaitoh 		ucast = CSR_READ_4(sc, BGE_MAC_STATS +
   4891  1.327   msaitoh 		    offsetof(struct bge_mac_stats_regs, ifHCOutUcastPkts));
   4892  1.327   msaitoh 		mcast = CSR_READ_4(sc, BGE_MAC_STATS +
   4893  1.327   msaitoh 		    offsetof(struct bge_mac_stats_regs, ifHCOutMulticastPkts));
   4894  1.327   msaitoh 		bcast = CSR_READ_4(sc, BGE_MAC_STATS +
   4895  1.327   msaitoh 		    offsetof(struct bge_mac_stats_regs, ifHCOutBroadcastPkts));
   4896  1.327   msaitoh 
   4897  1.327   msaitoh 		/*
   4898  1.327   msaitoh 		 * If controller transmitted more than BGE_NUM_RDMA_CHANNELS
   4899  1.327   msaitoh 		 * frames, it's safe to disable workaround for DMA engine's
   4900  1.327   msaitoh 		 * miscalculation of TXMBUF space.
   4901  1.327   msaitoh 		 */
   4902  1.327   msaitoh 		if (ucast + mcast + bcast > BGE_NUM_RDMA_CHANNELS) {
   4903  1.327   msaitoh 			val = CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL);
   4904  1.327   msaitoh 			if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719)
   4905  1.327   msaitoh 				val &= ~BGE_RDMA_TX_LENGTH_WA_5719;
   4906  1.327   msaitoh 			else
   4907  1.327   msaitoh 				val &= ~BGE_RDMA_TX_LENGTH_WA_5720;
   4908  1.327   msaitoh 			CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL, val);
   4909  1.327   msaitoh 			sc->bge_flags &= ~BGEF_RDMA_BUG;
   4910  1.327   msaitoh 		}
   4911  1.327   msaitoh 	}
   4912  1.172   msaitoh }
   4913  1.172   msaitoh 
   4914  1.172   msaitoh static void
   4915  1.104   thorpej bge_stats_update(struct bge_softc *sc)
   4916    1.1      fvdl {
   4917  1.354     skrll 	struct ifnet * const ifp = &sc->ethercom.ec_if;
   4918    1.1      fvdl 	bus_size_t stats = BGE_MEMWIN_START + BGE_STATS_BLOCK;
   4919   1.44   hannken 
   4920    1.1      fvdl #define READ_STAT(sc, stats, stat) \
   4921    1.1      fvdl 	  CSR_READ_4(sc, stats + offsetof(struct bge_stats, stat))
   4922    1.1      fvdl 
   4923  1.343   thorpej 	uint64_t collisions =
   4924    1.1      fvdl 	  (READ_STAT(sc, stats, dot3StatsSingleCollisionFrames.bge_addr_lo) +
   4925    1.1      fvdl 	   READ_STAT(sc, stats, dot3StatsMultipleCollisionFrames.bge_addr_lo) +
   4926    1.1      fvdl 	   READ_STAT(sc, stats, dot3StatsExcessiveCollisions.bge_addr_lo) +
   4927  1.343   thorpej 	   READ_STAT(sc, stats, dot3StatsLateCollisions.bge_addr_lo));
   4928  1.343   thorpej 
   4929  1.343   thorpej 	if_statadd(ifp, if_collisions, collisions - sc->bge_if_collisions);
   4930  1.343   thorpej 	sc->bge_if_collisions = collisions;
   4931  1.343   thorpej 
   4932    1.1      fvdl 
   4933   1.72   thorpej 	BGE_EVCNT_UPD(sc->bge_ev_tx_xoff,
   4934   1.72   thorpej 		      READ_STAT(sc, stats, outXoffSent.bge_addr_lo));
   4935   1.72   thorpej 	BGE_EVCNT_UPD(sc->bge_ev_tx_xon,
   4936   1.72   thorpej 		      READ_STAT(sc, stats, outXonSent.bge_addr_lo));
   4937   1.72   thorpej 	BGE_EVCNT_UPD(sc->bge_ev_rx_xoff,
   4938   1.72   thorpej 		      READ_STAT(sc, stats,
   4939  1.330   msaitoh 				xoffPauseFramesReceived.bge_addr_lo));
   4940   1.72   thorpej 	BGE_EVCNT_UPD(sc->bge_ev_rx_xon,
   4941   1.72   thorpej 		      READ_STAT(sc, stats, xonPauseFramesReceived.bge_addr_lo));
   4942   1.72   thorpej 	BGE_EVCNT_UPD(sc->bge_ev_rx_macctl,
   4943   1.72   thorpej 		      READ_STAT(sc, stats,
   4944  1.330   msaitoh 				macControlFramesReceived.bge_addr_lo));
   4945   1.72   thorpej 	BGE_EVCNT_UPD(sc->bge_ev_xoffentered,
   4946   1.72   thorpej 		      READ_STAT(sc, stats, xoffStateEntered.bge_addr_lo));
   4947   1.72   thorpej 
   4948    1.1      fvdl #undef READ_STAT
   4949    1.1      fvdl }
   4950    1.1      fvdl 
   4951   1.46  jonathan /*
   4952   1.46  jonathan  * Pad outbound frame to ETHER_MIN_NOPAD for an unusual reason.
   4953   1.46  jonathan  * The bge hardware will pad out Tx runts to ETHER_MIN_NOPAD,
   4954   1.46  jonathan  * but when such padded frames employ the  bge IP/TCP checksum offload,
   4955   1.46  jonathan  * the hardware checksum assist gives incorrect results (possibly
   4956   1.46  jonathan  * from incorporating its own padding into the UDP/TCP checksum; who knows).
   4957   1.46  jonathan  * If we pad such runts with zeros, the onboard checksum comes out correct.
   4958   1.46  jonathan  */
   4959  1.102     perry static inline int
   4960   1.46  jonathan bge_cksum_pad(struct mbuf *pkt)
   4961   1.46  jonathan {
   4962   1.46  jonathan 	struct mbuf *last = NULL;
   4963   1.46  jonathan 	int padlen;
   4964   1.46  jonathan 
   4965   1.46  jonathan 	padlen = ETHER_MIN_NOPAD - pkt->m_pkthdr.len;
   4966   1.46  jonathan 
   4967   1.46  jonathan 	/* if there's only the packet-header and we can pad there, use it. */
   4968   1.46  jonathan 	if (pkt->m_pkthdr.len == pkt->m_len &&
   4969  1.113   tsutsui 	    M_TRAILINGSPACE(pkt) >= padlen) {
   4970   1.46  jonathan 		last = pkt;
   4971   1.46  jonathan 	} else {
   4972   1.46  jonathan 		/*
   4973   1.46  jonathan 		 * Walk packet chain to find last mbuf. We will either
   4974   1.87     perry 		 * pad there, or append a new mbuf and pad it
   4975   1.46  jonathan 		 * (thus perhaps avoiding the bcm5700 dma-min bug).
   4976   1.46  jonathan 		 */
   4977   1.46  jonathan 		for (last = pkt; last->m_next != NULL; last = last->m_next) {
   4978  1.367     skrll 			continue; /* do nothing */
   4979   1.46  jonathan 		}
   4980   1.46  jonathan 
   4981   1.46  jonathan 		/* `last' now points to last in chain. */
   4982  1.114   tsutsui 		if (M_TRAILINGSPACE(last) < padlen) {
   4983   1.46  jonathan 			/* Allocate new empty mbuf, pad it. Compact later. */
   4984   1.46  jonathan 			struct mbuf *n;
   4985   1.46  jonathan 			MGET(n, M_DONTWAIT, MT_DATA);
   4986  1.129     joerg 			if (n == NULL)
   4987  1.129     joerg 				return ENOBUFS;
   4988   1.46  jonathan 			n->m_len = 0;
   4989   1.46  jonathan 			last->m_next = n;
   4990   1.46  jonathan 			last = n;
   4991   1.46  jonathan 		}
   4992   1.46  jonathan 	}
   4993   1.46  jonathan 
   4994  1.114   tsutsui 	KDASSERT(!M_READONLY(last));
   4995  1.114   tsutsui 	KDASSERT(M_TRAILINGSPACE(last) >= padlen);
   4996  1.114   tsutsui 
   4997   1.46  jonathan 	/* Now zero the pad area, to avoid the bge cksum-assist bug */
   4998  1.126  christos 	memset(mtod(last, char *) + last->m_len, 0, padlen);
   4999   1.46  jonathan 	last->m_len += padlen;
   5000   1.46  jonathan 	pkt->m_pkthdr.len += padlen;
   5001   1.46  jonathan 	return 0;
   5002   1.46  jonathan }
   5003   1.45  jonathan 
   5004   1.45  jonathan /*
   5005   1.45  jonathan  * Compact outbound packets to avoid bug with DMA segments less than 8 bytes.
   5006   1.45  jonathan  */
   5007  1.102     perry static inline int
   5008   1.45  jonathan bge_compact_dma_runt(struct mbuf *pkt)
   5009   1.45  jonathan {
   5010   1.45  jonathan 	struct mbuf	*m, *prev;
   5011  1.330   msaitoh 	int		totlen;
   5012   1.45  jonathan 
   5013   1.45  jonathan 	prev = NULL;
   5014   1.45  jonathan 	totlen = 0;
   5015   1.45  jonathan 
   5016  1.331   msaitoh 	for (m = pkt; m != NULL; prev = m, m = m->m_next) {
   5017   1.45  jonathan 		int mlen = m->m_len;
   5018   1.45  jonathan 		int shortfall = 8 - mlen ;
   5019   1.45  jonathan 
   5020   1.45  jonathan 		totlen += mlen;
   5021  1.203   msaitoh 		if (mlen == 0)
   5022   1.45  jonathan 			continue;
   5023   1.45  jonathan 		if (mlen >= 8)
   5024   1.45  jonathan 			continue;
   5025   1.45  jonathan 
   5026  1.357     skrll 		/*
   5027  1.357     skrll 		 * If we get here, mbuf data is too small for DMA engine.
   5028   1.45  jonathan 		 * Try to fix by shuffling data to prev or next in chain.
   5029   1.45  jonathan 		 * If that fails, do a compacting deep-copy of the whole chain.
   5030   1.45  jonathan 		 */
   5031   1.45  jonathan 
   5032   1.45  jonathan 		/* Internal frag. If fits in prev, copy it there. */
   5033  1.113   tsutsui 		if (prev && M_TRAILINGSPACE(prev) >= m->m_len) {
   5034  1.330   msaitoh 			memcpy(prev->m_data + prev->m_len, m->m_data, mlen);
   5035   1.45  jonathan 			prev->m_len += mlen;
   5036   1.45  jonathan 			m->m_len = 0;
   5037   1.45  jonathan 			/* XXX stitch chain */
   5038   1.45  jonathan 			prev->m_next = m_free(m);
   5039   1.45  jonathan 			m = prev;
   5040   1.45  jonathan 			continue;
   5041  1.332   msaitoh 		} else if (m->m_next != NULL &&
   5042  1.367     skrll 			    M_TRAILINGSPACE(m) >= shortfall &&
   5043  1.367     skrll 			    m->m_next->m_len >= (8 + shortfall)) {
   5044   1.45  jonathan 		    /* m is writable and have enough data in next, pull up. */
   5045   1.45  jonathan 
   5046  1.330   msaitoh 			memcpy(m->m_data + m->m_len, m->m_next->m_data,
   5047  1.115   tsutsui 			    shortfall);
   5048   1.45  jonathan 			m->m_len += shortfall;
   5049   1.45  jonathan 			m->m_next->m_len -= shortfall;
   5050   1.45  jonathan 			m->m_next->m_data += shortfall;
   5051  1.332   msaitoh 		} else if (m->m_next == NULL || 1) {
   5052  1.357     skrll 			/*
   5053  1.357     skrll 			 * Got a runt at the very end of the packet.
   5054   1.45  jonathan 			 * borrow data from the tail of the preceding mbuf and
   5055  1.332   msaitoh 			 * update its length in-place. (The original data is
   5056  1.332   msaitoh 			 * still valid, so we can do this even if prev is not
   5057  1.332   msaitoh 			 * writable.)
   5058   1.45  jonathan 			 */
   5059   1.45  jonathan 
   5060  1.332   msaitoh 			/*
   5061  1.332   msaitoh 			 * If we'd make prev a runt, just move all of its data.
   5062  1.332   msaitoh 			 */
   5063   1.45  jonathan 			KASSERT(prev != NULL /*, ("runt but null PREV")*/);
   5064   1.45  jonathan 			KASSERT(prev->m_len >= 8 /*, ("runt prev")*/);
   5065  1.111  christos 
   5066   1.45  jonathan 			if ((prev->m_len - shortfall) < 8)
   5067   1.45  jonathan 				shortfall = prev->m_len;
   5068   1.87     perry 
   5069   1.45  jonathan #ifdef notyet	/* just do the safe slow thing for now */
   5070   1.45  jonathan 			if (!M_READONLY(m)) {
   5071   1.45  jonathan 				if (M_LEADINGSPACE(m) < shorfall) {
   5072   1.45  jonathan 					void *m_dat;
   5073  1.338      maxv 					m_dat = M_BUFADDR(m);
   5074  1.332   msaitoh 					memmove(m_dat, mtod(m, void*),
   5075  1.332   msaitoh 					    m->m_len);
   5076   1.45  jonathan 					m->m_data = m_dat;
   5077  1.332   msaitoh 				}
   5078   1.45  jonathan 			} else
   5079   1.45  jonathan #endif	/* just do the safe slow thing */
   5080   1.45  jonathan 			{
   5081   1.45  jonathan 				struct mbuf * n = NULL;
   5082   1.45  jonathan 				int newprevlen = prev->m_len - shortfall;
   5083   1.45  jonathan 
   5084   1.45  jonathan 				MGET(n, M_NOWAIT, MT_DATA);
   5085   1.45  jonathan 				if (n == NULL)
   5086   1.45  jonathan 				   return ENOBUFS;
   5087   1.45  jonathan 				KASSERT(m->m_len + shortfall < MLEN
   5088   1.45  jonathan 					/*,
   5089   1.45  jonathan 					  ("runt %d +prev %d too big\n", m->m_len, shortfall)*/);
   5090   1.45  jonathan 
   5091   1.45  jonathan 				/* first copy the data we're stealing from prev */
   5092  1.115   tsutsui 				memcpy(n->m_data, prev->m_data + newprevlen,
   5093  1.115   tsutsui 				    shortfall);
   5094   1.45  jonathan 
   5095   1.45  jonathan 				/* update prev->m_len accordingly */
   5096   1.45  jonathan 				prev->m_len -= shortfall;
   5097   1.45  jonathan 
   5098   1.45  jonathan 				/* copy data from runt m */
   5099  1.115   tsutsui 				memcpy(n->m_data + shortfall, m->m_data,
   5100  1.115   tsutsui 				    m->m_len);
   5101   1.45  jonathan 
   5102   1.45  jonathan 				/* n holds what we stole from prev, plus m */
   5103   1.45  jonathan 				n->m_len = shortfall + m->m_len;
   5104   1.45  jonathan 
   5105   1.45  jonathan 				/* stitch n into chain and free m */
   5106   1.45  jonathan 				n->m_next = m->m_next;
   5107   1.45  jonathan 				prev->m_next = n;
   5108   1.45  jonathan 				/* KASSERT(m->m_next == NULL); */
   5109   1.45  jonathan 				m->m_next = NULL;
   5110   1.45  jonathan 				m_free(m);
   5111   1.45  jonathan 				m = n;	/* for continuing loop */
   5112   1.45  jonathan 			}
   5113   1.45  jonathan 		}
   5114   1.45  jonathan 	}
   5115   1.45  jonathan 	return 0;
   5116   1.45  jonathan }
   5117   1.45  jonathan 
   5118    1.1      fvdl /*
   5119  1.207   msaitoh  * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data
   5120    1.1      fvdl  * pointers to descriptors.
   5121    1.1      fvdl  */
   5122  1.104   thorpej static int
   5123  1.170   msaitoh bge_encap(struct bge_softc *sc, struct mbuf *m_head, uint32_t *txidx)
   5124    1.1      fvdl {
   5125  1.317    bouyer 	struct bge_tx_bd	*f, *prev_f;
   5126  1.170   msaitoh 	uint32_t		frag, cur;
   5127  1.170   msaitoh 	uint16_t		csum_flags = 0;
   5128  1.170   msaitoh 	uint16_t		txbd_tso_flags = 0;
   5129    1.1      fvdl 	struct txdmamap_pool_entry *dma;
   5130    1.1      fvdl 	bus_dmamap_t dmamap;
   5131  1.317    bouyer 	bus_dma_tag_t dmatag;
   5132    1.1      fvdl 	int			i = 0;
   5133   1.95  jonathan 	int			use_tso, maxsegsize, error;
   5134  1.311  knakahar 	bool			have_vtag;
   5135  1.311  knakahar 	uint16_t		vtag;
   5136  1.330   msaitoh 	bool			remap;
   5137  1.107     blymn 
   5138    1.1      fvdl 	if (m_head->m_pkthdr.csum_flags) {
   5139    1.1      fvdl 		if (m_head->m_pkthdr.csum_flags & M_CSUM_IPv4)
   5140    1.1      fvdl 			csum_flags |= BGE_TXBDFLAG_IP_CSUM;
   5141  1.331   msaitoh 		if (m_head->m_pkthdr.csum_flags & (M_CSUM_TCPv4 |M_CSUM_UDPv4))
   5142    1.1      fvdl 			csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM;
   5143    1.1      fvdl 	}
   5144    1.1      fvdl 
   5145   1.87     perry 	/*
   5146   1.46  jonathan 	 * If we were asked to do an outboard checksum, and the NIC
   5147   1.46  jonathan 	 * has the bug where it sometimes adds in the Ethernet padding,
   5148   1.46  jonathan 	 * explicitly pad with zeros so the cksum will be correct either way.
   5149   1.46  jonathan 	 * (For now, do this for all chip versions, until newer
   5150   1.46  jonathan 	 * are confirmed to not require the workaround.)
   5151   1.46  jonathan 	 */
   5152   1.46  jonathan 	if ((csum_flags & BGE_TXBDFLAG_TCP_UDP_CSUM) == 0 ||
   5153   1.46  jonathan #ifdef notyet
   5154   1.46  jonathan 	    (sc->bge_quirks & BGE_QUIRK_SHORT_CKSUM_BUG) == 0 ||
   5155   1.87     perry #endif
   5156   1.46  jonathan 	    m_head->m_pkthdr.len >= ETHER_MIN_NOPAD)
   5157   1.46  jonathan 		goto check_dma_bug;
   5158   1.46  jonathan 
   5159  1.170   msaitoh 	if (bge_cksum_pad(m_head) != 0)
   5160  1.320    bouyer 		return ENOBUFS;
   5161   1.46  jonathan 
   5162   1.46  jonathan check_dma_bug:
   5163  1.157   msaitoh 	if (!(BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX))
   5164   1.29    itojun 		goto doit;
   5165  1.157   msaitoh 
   5166   1.25  jonathan 	/*
   5167   1.25  jonathan 	 * bcm5700 Revision B silicon cannot handle DMA descriptors with
   5168   1.87     perry 	 * less than eight bytes.  If we encounter a teeny mbuf
   5169   1.25  jonathan 	 * at the end of a chain, we can pad.  Otherwise, copy.
   5170   1.25  jonathan 	 */
   5171   1.45  jonathan 	if (bge_compact_dma_runt(m_head) != 0)
   5172   1.45  jonathan 		return ENOBUFS;
   5173   1.25  jonathan 
   5174   1.25  jonathan doit:
   5175    1.1      fvdl 	dma = SLIST_FIRST(&sc->txdma_list);
   5176  1.320    bouyer 	if (dma == NULL) {
   5177    1.1      fvdl 		return ENOBUFS;
   5178  1.320    bouyer 	}
   5179    1.1      fvdl 	dmamap = dma->dmamap;
   5180  1.317    bouyer 	dmatag = sc->bge_dmatag;
   5181  1.317    bouyer 	dma->is_dma32 = false;
   5182    1.1      fvdl 
   5183    1.1      fvdl 	/*
   5184   1.95  jonathan 	 * Set up any necessary TSO state before we start packing...
   5185   1.95  jonathan 	 */
   5186   1.95  jonathan 	use_tso = (m_head->m_pkthdr.csum_flags & M_CSUM_TSOv4) != 0;
   5187   1.95  jonathan 	if (!use_tso) {
   5188   1.95  jonathan 		maxsegsize = 0;
   5189   1.95  jonathan 	} else {	/* TSO setup */
   5190   1.95  jonathan 		unsigned  mss;
   5191   1.95  jonathan 		struct ether_header *eh;
   5192   1.95  jonathan 		unsigned ip_tcp_hlen, iptcp_opt_words, tcp_seg_flags, offset;
   5193  1.317    bouyer 		unsigned bge_hlen;
   5194   1.95  jonathan 		struct mbuf * m0 = m_head;
   5195   1.95  jonathan 		struct ip *ip;
   5196   1.95  jonathan 		struct tcphdr *th;
   5197   1.95  jonathan 		int iphl, hlen;
   5198   1.95  jonathan 
   5199   1.95  jonathan 		/*
   5200   1.95  jonathan 		 * XXX It would be nice if the mbuf pkthdr had offset
   5201   1.95  jonathan 		 * fields for the protocol headers.
   5202   1.95  jonathan 		 */
   5203   1.95  jonathan 
   5204   1.95  jonathan 		eh = mtod(m0, struct ether_header *);
   5205   1.95  jonathan 		switch (htons(eh->ether_type)) {
   5206   1.95  jonathan 		case ETHERTYPE_IP:
   5207   1.95  jonathan 			offset = ETHER_HDR_LEN;
   5208   1.95  jonathan 			break;
   5209   1.95  jonathan 
   5210   1.95  jonathan 		case ETHERTYPE_VLAN:
   5211   1.95  jonathan 			offset = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN;
   5212   1.95  jonathan 			break;
   5213   1.95  jonathan 
   5214   1.95  jonathan 		default:
   5215   1.95  jonathan 			/*
   5216   1.95  jonathan 			 * Don't support this protocol or encapsulation.
   5217   1.95  jonathan 			 */
   5218  1.170   msaitoh 			return ENOBUFS;
   5219   1.95  jonathan 		}
   5220   1.95  jonathan 
   5221   1.95  jonathan 		/*
   5222   1.95  jonathan 		 * TCP/IP headers are in the first mbuf; we can do
   5223   1.95  jonathan 		 * this the easy way.
   5224   1.95  jonathan 		 */
   5225   1.95  jonathan 		iphl = M_CSUM_DATA_IPv4_IPHL(m0->m_pkthdr.csum_data);
   5226   1.95  jonathan 		hlen = iphl + offset;
   5227   1.95  jonathan 		if (__predict_false(m0->m_len <
   5228   1.95  jonathan 				    (hlen + sizeof(struct tcphdr)))) {
   5229   1.95  jonathan 
   5230  1.316    bouyer 			aprint_error_dev(sc->bge_dev,
   5231  1.138     joerg 			    "TSO: hard case m0->m_len == %d < ip/tcp hlen %zd,"
   5232  1.138     joerg 			    "not handled yet\n",
   5233  1.367     skrll 			    m0->m_len, hlen+ sizeof(struct tcphdr));
   5234   1.95  jonathan #ifdef NOTYET
   5235   1.95  jonathan 			/*
   5236   1.95  jonathan 			 * XXX jonathan (at) NetBSD.org: untested.
   5237  1.330   msaitoh 			 * how to force this branch to be taken?
   5238   1.95  jonathan 			 */
   5239  1.267   msaitoh 			BGE_EVCNT_INCR(sc->bge_ev_txtsopain);
   5240   1.95  jonathan 
   5241   1.95  jonathan 			m_copydata(m0, offset, sizeof(ip), &ip);
   5242   1.95  jonathan 			m_copydata(m0, hlen, sizeof(th), &th);
   5243   1.95  jonathan 
   5244   1.95  jonathan 			ip.ip_len = 0;
   5245   1.95  jonathan 
   5246   1.95  jonathan 			m_copyback(m0, hlen + offsetof(struct ip, ip_len),
   5247   1.95  jonathan 			    sizeof(ip.ip_len), &ip.ip_len);
   5248   1.95  jonathan 
   5249   1.95  jonathan 			th.th_sum = in_cksum_phdr(ip.ip_src.s_addr,
   5250   1.95  jonathan 			    ip.ip_dst.s_addr, htons(IPPROTO_TCP));
   5251   1.95  jonathan 
   5252   1.95  jonathan 			m_copyback(m0, hlen + offsetof(struct tcphdr, th_sum),
   5253   1.95  jonathan 			    sizeof(th.th_sum), &th.th_sum);
   5254   1.95  jonathan 
   5255   1.95  jonathan 			hlen += th.th_off << 2;
   5256   1.95  jonathan 			iptcp_opt_words	= hlen;
   5257   1.95  jonathan #else
   5258   1.95  jonathan 			/*
   5259   1.95  jonathan 			 * if_wm "hard" case not yet supported, can we not
   5260   1.95  jonathan 			 * mandate it out of existence?
   5261   1.95  jonathan 			 */
   5262   1.95  jonathan 			(void) ip; (void)th; (void) ip_tcp_hlen;
   5263   1.95  jonathan 
   5264   1.95  jonathan 			return ENOBUFS;
   5265   1.95  jonathan #endif
   5266   1.95  jonathan 		} else {
   5267  1.126  christos 			ip = (struct ip *) (mtod(m0, char *) + offset);
   5268  1.126  christos 			th = (struct tcphdr *) (mtod(m0, char *) + hlen);
   5269   1.95  jonathan 			ip_tcp_hlen = iphl +  (th->th_off << 2);
   5270   1.95  jonathan 
   5271   1.95  jonathan 			/* Total IP/TCP options, in 32-bit words */
   5272   1.95  jonathan 			iptcp_opt_words = (ip_tcp_hlen
   5273   1.95  jonathan 					   - sizeof(struct tcphdr)
   5274   1.95  jonathan 					   - sizeof(struct ip)) >> 2;
   5275   1.95  jonathan 		}
   5276  1.207   msaitoh 		if (BGE_IS_575X_PLUS(sc)) {
   5277   1.95  jonathan 			th->th_sum = 0;
   5278  1.317    bouyer 			csum_flags = 0;
   5279   1.95  jonathan 		} else {
   5280   1.95  jonathan 			/*
   5281  1.107     blymn 			 * XXX jonathan (at) NetBSD.org: 5705 untested.
   5282   1.95  jonathan 			 * Requires TSO firmware patch for 5701/5703/5704.
   5283   1.95  jonathan 			 */
   5284   1.95  jonathan 			th->th_sum = in_cksum_phdr(ip->ip_src.s_addr,
   5285   1.95  jonathan 			    ip->ip_dst.s_addr, htons(IPPROTO_TCP));
   5286   1.95  jonathan 		}
   5287   1.95  jonathan 
   5288   1.95  jonathan 		mss = m_head->m_pkthdr.segsz;
   5289  1.107     blymn 		txbd_tso_flags |=
   5290   1.95  jonathan 		    BGE_TXBDFLAG_CPU_PRE_DMA |
   5291   1.95  jonathan 		    BGE_TXBDFLAG_CPU_POST_DMA;
   5292   1.95  jonathan 
   5293   1.95  jonathan 		/*
   5294   1.95  jonathan 		 * Our NIC TSO-assist assumes TSO has standard, optionless
   5295   1.95  jonathan 		 * IPv4 and TCP headers, which total 40 bytes. By default,
   5296   1.95  jonathan 		 * the NIC copies 40 bytes of IP/TCP header from the
   5297   1.95  jonathan 		 * supplied header into the IP/TCP header portion of
   5298   1.95  jonathan 		 * each post-TSO-segment. If the supplied packet has IP or
   5299   1.95  jonathan 		 * TCP options, we need to tell the NIC to copy those extra
   5300   1.95  jonathan 		 * bytes into each  post-TSO header, in addition to the normal
   5301   1.95  jonathan 		 * 40-byte IP/TCP header (and to leave space accordingly).
   5302   1.95  jonathan 		 * Unfortunately, the driver encoding of option length
   5303   1.95  jonathan 		 * varies across different ASIC families.
   5304   1.95  jonathan 		 */
   5305   1.95  jonathan 		tcp_seg_flags = 0;
   5306  1.317    bouyer 		bge_hlen = ip_tcp_hlen >> 2;
   5307  1.317    bouyer 		if (BGE_IS_5717_PLUS(sc)) {
   5308  1.317    bouyer 			tcp_seg_flags = (bge_hlen & 0x3) << 14;
   5309  1.317    bouyer 			txbd_tso_flags |=
   5310  1.317    bouyer 			    ((bge_hlen & 0xF8) << 7) | ((bge_hlen & 0x4) << 2);
   5311  1.317    bouyer 		} else if (BGE_IS_5705_PLUS(sc)) {
   5312  1.332   msaitoh 			tcp_seg_flags = bge_hlen << 11;
   5313  1.317    bouyer 		} else {
   5314  1.317    bouyer 			/* XXX iptcp_opt_words or bge_hlen ? */
   5315  1.332   msaitoh 			txbd_tso_flags |= iptcp_opt_words << 12;
   5316   1.95  jonathan 		}
   5317   1.95  jonathan 		maxsegsize = mss | tcp_seg_flags;
   5318   1.95  jonathan 		ip->ip_len = htons(mss + ip_tcp_hlen);
   5319  1.317    bouyer 		ip->ip_sum = 0;
   5320   1.95  jonathan 
   5321   1.95  jonathan 	}	/* TSO setup */
   5322   1.95  jonathan 
   5323  1.317    bouyer 	have_vtag = vlan_has_tag(m_head);
   5324  1.317    bouyer 	if (have_vtag)
   5325  1.317    bouyer 		vtag = vlan_get_tag(m_head);
   5326  1.317    bouyer 
   5327   1.95  jonathan 	/*
   5328    1.1      fvdl 	 * Start packing the mbufs in this chain into
   5329    1.1      fvdl 	 * the fragment pointers. Stop when we run out
   5330    1.1      fvdl 	 * of fragments or hit the end of the mbuf chain.
   5331    1.1      fvdl 	 */
   5332  1.320    bouyer 	remap = true;
   5333  1.317    bouyer load_again:
   5334  1.332   msaitoh 	error = bus_dmamap_load_mbuf(dmatag, dmamap, m_head, BUS_DMA_NOWAIT);
   5335  1.320    bouyer 	if (__predict_false(error)) {
   5336  1.332   msaitoh 		if (error == EFBIG && remap) {
   5337  1.320    bouyer 			struct mbuf *m;
   5338  1.320    bouyer 			remap = false;
   5339  1.320    bouyer 			m = m_defrag(m_head, M_NOWAIT);
   5340  1.320    bouyer 			if (m != NULL) {
   5341  1.320    bouyer 				KASSERT(m == m_head);
   5342  1.320    bouyer 				goto load_again;
   5343  1.320    bouyer 			}
   5344  1.320    bouyer 		}
   5345  1.320    bouyer 		return error;
   5346  1.320    bouyer 	}
   5347  1.118   tsutsui 	/*
   5348  1.118   tsutsui 	 * Sanity check: avoid coming within 16 descriptors
   5349  1.118   tsutsui 	 * of the end of the ring.
   5350  1.118   tsutsui 	 */
   5351  1.118   tsutsui 	if (dmamap->dm_nsegs > (BGE_TX_RING_CNT - sc->bge_txcnt - 16)) {
   5352  1.118   tsutsui 		BGE_TSO_PRINTF(("%s: "
   5353  1.118   tsutsui 		    " dmamap_load_mbuf too close to ring wrap\n",
   5354  1.138     joerg 		    device_xname(sc->bge_dev)));
   5355  1.118   tsutsui 		goto fail_unload;
   5356  1.118   tsutsui 	}
   5357   1.95  jonathan 
   5358  1.317    bouyer 	/* Iterate over dmap-map fragments. */
   5359  1.317    bouyer 	f = prev_f = NULL;
   5360  1.317    bouyer 	cur = frag = *txidx;
   5361    1.6   thorpej 
   5362    1.1      fvdl 	for (i = 0; i < dmamap->dm_nsegs; i++) {
   5363    1.1      fvdl 		f = &sc->bge_rdata->bge_tx_ring[frag];
   5364    1.1      fvdl 		if (sc->bge_cdata.bge_tx_chain[frag] != NULL)
   5365    1.1      fvdl 			break;
   5366  1.107     blymn 
   5367  1.172   msaitoh 		BGE_HOSTADDR(f->bge_addr, dmamap->dm_segs[i].ds_addr);
   5368    1.1      fvdl 		f->bge_len = dmamap->dm_segs[i].ds_len;
   5369  1.320    bouyer 		if (sizeof(bus_addr_t) > 4 && dma->is_dma32 == false && use_tso && (
   5370  1.320    bouyer 		    (dmamap->dm_segs[i].ds_addr & 0xffffffff00000000) !=
   5371  1.320    bouyer 		    ((dmamap->dm_segs[i].ds_addr + f->bge_len) & 0xffffffff00000000) ||
   5372  1.320    bouyer 		    (prev_f != NULL &&
   5373  1.320    bouyer 		     prev_f->bge_addr.bge_addr_hi != f->bge_addr.bge_addr_hi))
   5374  1.320    bouyer 		   ) {
   5375  1.317    bouyer 			/*
   5376  1.317    bouyer 			 * watchdog timeout issue was observed with TSO,
   5377  1.317    bouyer 			 * limiting DMA address space to 32bits seems to
   5378  1.317    bouyer 			 * address the issue.
   5379  1.317    bouyer 			 */
   5380  1.317    bouyer 			bus_dmamap_unload(dmatag, dmamap);
   5381  1.317    bouyer 			dmatag = sc->bge_dmatag32;
   5382  1.317    bouyer 			dmamap = dma->dmamap32;
   5383  1.317    bouyer 			dma->is_dma32 = true;
   5384  1.320    bouyer 			remap = true;
   5385  1.317    bouyer 			goto load_again;
   5386  1.317    bouyer 		}
   5387   1.95  jonathan 
   5388   1.95  jonathan 		/*
   5389   1.95  jonathan 		 * For 5751 and follow-ons, for TSO we must turn
   5390   1.95  jonathan 		 * off checksum-assist flag in the tx-descr, and
   5391   1.95  jonathan 		 * supply the ASIC-revision-specific encoding
   5392   1.95  jonathan 		 * of TSO flags and segsize.
   5393   1.95  jonathan 		 */
   5394   1.95  jonathan 		if (use_tso) {
   5395  1.207   msaitoh 			if (BGE_IS_575X_PLUS(sc) || i == 0) {
   5396   1.95  jonathan 				f->bge_rsvd = maxsegsize;
   5397   1.95  jonathan 				f->bge_flags = csum_flags | txbd_tso_flags;
   5398   1.95  jonathan 			} else {
   5399   1.95  jonathan 				f->bge_rsvd = 0;
   5400   1.95  jonathan 				f->bge_flags =
   5401   1.95  jonathan 				  (csum_flags | txbd_tso_flags) & 0x0fff;
   5402   1.95  jonathan 			}
   5403   1.95  jonathan 		} else {
   5404   1.95  jonathan 			f->bge_rsvd = 0;
   5405   1.95  jonathan 			f->bge_flags = csum_flags;
   5406   1.95  jonathan 		}
   5407    1.1      fvdl 
   5408  1.311  knakahar 		if (have_vtag) {
   5409    1.1      fvdl 			f->bge_flags |= BGE_TXBDFLAG_VLAN_TAG;
   5410  1.311  knakahar 			f->bge_vlan_tag = vtag;
   5411    1.1      fvdl 		} else {
   5412    1.1      fvdl 			f->bge_vlan_tag = 0;
   5413    1.1      fvdl 		}
   5414  1.317    bouyer 		prev_f = f;
   5415    1.1      fvdl 		cur = frag;
   5416    1.1      fvdl 		BGE_INC(frag, BGE_TX_RING_CNT);
   5417    1.1      fvdl 	}
   5418    1.1      fvdl 
   5419   1.95  jonathan 	if (i < dmamap->dm_nsegs) {
   5420   1.95  jonathan 		BGE_TSO_PRINTF(("%s: reached %d < dm_nsegs %d\n",
   5421  1.138     joerg 		    device_xname(sc->bge_dev), i, dmamap->dm_nsegs));
   5422  1.118   tsutsui 		goto fail_unload;
   5423   1.95  jonathan 	}
   5424    1.1      fvdl 
   5425  1.317    bouyer 	bus_dmamap_sync(dmatag, dmamap, 0, dmamap->dm_mapsize,
   5426    1.1      fvdl 	    BUS_DMASYNC_PREWRITE);
   5427    1.1      fvdl 
   5428   1.95  jonathan 	if (frag == sc->bge_tx_saved_considx) {
   5429   1.95  jonathan 		BGE_TSO_PRINTF(("%s: frag %d = wrapped id %d?\n",
   5430  1.138     joerg 		    device_xname(sc->bge_dev), frag, sc->bge_tx_saved_considx));
   5431   1.95  jonathan 
   5432  1.118   tsutsui 		goto fail_unload;
   5433   1.95  jonathan 	}
   5434    1.1      fvdl 
   5435    1.1      fvdl 	sc->bge_rdata->bge_tx_ring[cur].bge_flags |= BGE_TXBDFLAG_END;
   5436    1.1      fvdl 	sc->bge_cdata.bge_tx_chain[cur] = m_head;
   5437    1.1      fvdl 	SLIST_REMOVE_HEAD(&sc->txdma_list, link);
   5438    1.1      fvdl 	sc->txdma[cur] = dma;
   5439  1.118   tsutsui 	sc->bge_txcnt += dmamap->dm_nsegs;
   5440    1.1      fvdl 
   5441    1.1      fvdl 	*txidx = frag;
   5442    1.1      fvdl 
   5443  1.170   msaitoh 	return 0;
   5444  1.118   tsutsui 
   5445  1.158   msaitoh fail_unload:
   5446  1.317    bouyer 	bus_dmamap_unload(dmatag, dmamap);
   5447  1.118   tsutsui 
   5448  1.118   tsutsui 	return ENOBUFS;
   5449    1.1      fvdl }
   5450    1.1      fvdl 
   5451  1.375     skrll 
   5452  1.375     skrll static void
   5453  1.375     skrll bge_start(struct ifnet *ifp)
   5454  1.375     skrll {
   5455  1.375     skrll 	struct bge_softc * const sc = ifp->if_softc;
   5456  1.375     skrll 
   5457  1.375     skrll 	mutex_enter(sc->sc_core_lock);
   5458  1.375     skrll 	bge_start_locked(ifp);
   5459  1.375     skrll 	mutex_exit(sc->sc_core_lock);
   5460  1.375     skrll }
   5461  1.375     skrll 
   5462    1.1      fvdl /*
   5463    1.1      fvdl  * Main transmit routine. To avoid having to do mbuf copies, we put pointers
   5464    1.1      fvdl  * to the mbuf data regions directly in the transmit descriptors.
   5465    1.1      fvdl  */
   5466  1.104   thorpej static void
   5467  1.375     skrll bge_start_locked(struct ifnet *ifp)
   5468    1.1      fvdl {
   5469  1.354     skrll 	struct bge_softc * const sc = ifp->if_softc;
   5470    1.1      fvdl 	struct mbuf *m_head = NULL;
   5471  1.320    bouyer 	struct mbuf *m;
   5472  1.170   msaitoh 	uint32_t prodidx;
   5473    1.1      fvdl 	int pkts = 0;
   5474  1.320    bouyer 	int error;
   5475    1.1      fvdl 
   5476  1.375     skrll 	if ((sc->bge_if_flags & IFF_RUNNING) != IFF_RUNNING)
   5477    1.1      fvdl 		return;
   5478    1.1      fvdl 
   5479   1.94  jonathan 	prodidx = sc->bge_tx_prodidx;
   5480    1.1      fvdl 
   5481  1.170   msaitoh 	while (sc->bge_cdata.bge_tx_chain[prodidx] == NULL) {
   5482    1.1      fvdl 		IFQ_POLL(&ifp->if_snd, m_head);
   5483    1.1      fvdl 		if (m_head == NULL)
   5484    1.1      fvdl 			break;
   5485    1.1      fvdl 
   5486    1.1      fvdl #if 0
   5487    1.1      fvdl 		/*
   5488    1.1      fvdl 		 * XXX
   5489    1.1      fvdl 		 * safety overkill.  If this is a fragmented packet chain
   5490    1.1      fvdl 		 * with delayed TCP/UDP checksums, then only encapsulate
   5491    1.1      fvdl 		 * it if we have enough descriptors to handle the entire
   5492    1.1      fvdl 		 * chain at once.
   5493    1.1      fvdl 		 * (paranoia -- may not actually be needed)
   5494    1.1      fvdl 		 */
   5495    1.1      fvdl 		if (m_head->m_flags & M_FIRSTFRAG &&
   5496    1.1      fvdl 		    m_head->m_pkthdr.csum_flags & (CSUM_DELAY_DATA)) {
   5497    1.1      fvdl 			if ((BGE_TX_RING_CNT - sc->bge_txcnt) <
   5498   1.86   thorpej 			    M_CSUM_DATA_IPv4_OFFSET(m_head->m_pkthdr.csum_data) + 16) {
   5499    1.1      fvdl 				ifp->if_flags |= IFF_OACTIVE;
   5500    1.1      fvdl 				break;
   5501    1.1      fvdl 			}
   5502    1.1      fvdl 		}
   5503    1.1      fvdl #endif
   5504    1.1      fvdl 
   5505    1.1      fvdl 		/*
   5506    1.1      fvdl 		 * Pack the data into the transmit ring. If we
   5507    1.1      fvdl 		 * don't have room, set the OACTIVE flag and wait
   5508    1.1      fvdl 		 * for the NIC to drain the ring.
   5509    1.1      fvdl 		 */
   5510  1.320    bouyer 		error = bge_encap(sc, m_head, &prodidx);
   5511  1.320    bouyer 		if (__predict_false(error)) {
   5512  1.375     skrll 			if (SLIST_EMPTY(&sc->txdma_list)) {
   5513  1.320    bouyer 				/* just wait for the transmit ring to drain */
   5514  1.320    bouyer 				break;
   5515  1.320    bouyer 			}
   5516  1.320    bouyer 			IFQ_DEQUEUE(&ifp->if_snd, m);
   5517  1.320    bouyer 			KASSERT(m == m_head);
   5518  1.320    bouyer 			m_freem(m_head);
   5519  1.320    bouyer 			continue;
   5520    1.1      fvdl 		}
   5521  1.330   msaitoh 
   5522    1.1      fvdl 		/* now we are committed to transmit the packet */
   5523  1.320    bouyer 		IFQ_DEQUEUE(&ifp->if_snd, m);
   5524  1.320    bouyer 		KASSERT(m == m_head);
   5525    1.1      fvdl 		pkts++;
   5526    1.1      fvdl 
   5527    1.1      fvdl 		/*
   5528    1.1      fvdl 		 * If there's a BPF listener, bounce a copy of this frame
   5529    1.1      fvdl 		 * to him.
   5530    1.1      fvdl 		 */
   5531  1.314   msaitoh 		bpf_mtap(ifp, m_head, BPF_D_OUT);
   5532    1.1      fvdl 	}
   5533    1.1      fvdl 	if (pkts == 0)
   5534    1.1      fvdl 		return;
   5535    1.1      fvdl 
   5536    1.1      fvdl 	/* Transmit */
   5537  1.151    cegger 	bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx);
   5538  1.158   msaitoh 	/* 5700 b2 errata */
   5539  1.158   msaitoh 	if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX)
   5540  1.151    cegger 		bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx);
   5541    1.1      fvdl 
   5542   1.94  jonathan 	sc->bge_tx_prodidx = prodidx;
   5543  1.375     skrll 	sc->bge_tx_lastsent = time_uptime;
   5544  1.375     skrll 	sc->bge_tx_sending = true;
   5545  1.375     skrll }
   5546   1.94  jonathan 
   5547  1.375     skrll static int
   5548  1.375     skrll bge_init(struct ifnet *ifp)
   5549  1.375     skrll {
   5550  1.375     skrll 	struct bge_softc * const sc = ifp->if_softc;
   5551  1.375     skrll 
   5552  1.375     skrll 	mutex_enter(sc->sc_core_lock);
   5553  1.375     skrll 	int ret = bge_init_locked(ifp);
   5554  1.375     skrll 	mutex_exit(sc->sc_core_lock);
   5555  1.375     skrll 
   5556  1.375     skrll 	return ret;
   5557    1.1      fvdl }
   5558    1.1      fvdl 
   5559  1.375     skrll 
   5560  1.104   thorpej static int
   5561  1.375     skrll bge_init_locked(struct ifnet *ifp)
   5562    1.1      fvdl {
   5563  1.354     skrll 	struct bge_softc * const sc = ifp->if_softc;
   5564  1.170   msaitoh 	const uint16_t *m;
   5565  1.258   msaitoh 	uint32_t mode, reg;
   5566  1.375     skrll 	int error = 0;
   5567    1.1      fvdl 
   5568  1.375     skrll 	KASSERT(IFNET_LOCKED(ifp));
   5569  1.375     skrll 	KASSERT(mutex_owned(sc->sc_core_lock));
   5570  1.358     skrll 	KASSERT(ifp == &sc->ethercom.ec_if);
   5571    1.1      fvdl 
   5572    1.1      fvdl 	/* Cancel pending I/O and flush buffers. */
   5573  1.375     skrll 	bge_stop_locked(ifp, 0);
   5574  1.177   msaitoh 
   5575  1.177   msaitoh 	bge_stop_fw(sc);
   5576  1.177   msaitoh 	bge_sig_pre_reset(sc, BGE_RESET_START);
   5577    1.1      fvdl 	bge_reset(sc);
   5578  1.177   msaitoh 	bge_sig_legacy(sc, BGE_RESET_START);
   5579  1.287   msaitoh 
   5580  1.287   msaitoh 	if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5784_AX) {
   5581  1.287   msaitoh 		reg = CSR_READ_4(sc, BGE_CPMU_CTRL);
   5582  1.287   msaitoh 		reg &= ~(BGE_CPMU_CTRL_LINK_AWARE_MODE |
   5583  1.287   msaitoh 		    BGE_CPMU_CTRL_LINK_IDLE_MODE);
   5584  1.287   msaitoh 		CSR_WRITE_4(sc, BGE_CPMU_CTRL, reg);
   5585  1.287   msaitoh 
   5586  1.287   msaitoh 		reg = CSR_READ_4(sc, BGE_CPMU_LSPD_10MB_CLK);
   5587  1.287   msaitoh 		reg &= ~BGE_CPMU_LSPD_10MB_CLK;
   5588  1.287   msaitoh 		reg |= BGE_CPMU_LSPD_10MB_MACCLK_6_25;
   5589  1.287   msaitoh 		CSR_WRITE_4(sc, BGE_CPMU_LSPD_10MB_CLK, reg);
   5590  1.287   msaitoh 
   5591  1.287   msaitoh 		reg = CSR_READ_4(sc, BGE_CPMU_LNK_AWARE_PWRMD);
   5592  1.287   msaitoh 		reg &= ~BGE_CPMU_LNK_AWARE_MACCLK_MASK;
   5593  1.287   msaitoh 		reg |= BGE_CPMU_LNK_AWARE_MACCLK_6_25;
   5594  1.287   msaitoh 		CSR_WRITE_4(sc, BGE_CPMU_LNK_AWARE_PWRMD, reg);
   5595  1.287   msaitoh 
   5596  1.287   msaitoh 		reg = CSR_READ_4(sc, BGE_CPMU_HST_ACC);
   5597  1.287   msaitoh 		reg &= ~BGE_CPMU_HST_ACC_MACCLK_MASK;
   5598  1.287   msaitoh 		reg |= BGE_CPMU_HST_ACC_MACCLK_6_25;
   5599  1.287   msaitoh 		CSR_WRITE_4(sc, BGE_CPMU_HST_ACC, reg);
   5600  1.287   msaitoh 	}
   5601  1.287   msaitoh 
   5602  1.304   msaitoh 	if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57780) {
   5603  1.305   msaitoh 		pcireg_t aercap;
   5604  1.305   msaitoh 
   5605  1.304   msaitoh 		reg = CSR_READ_4(sc, BGE_PCIE_PWRMNG_THRESH);
   5606  1.304   msaitoh 		reg = (reg & ~BGE_PCIE_PWRMNG_L1THRESH_MASK)
   5607  1.304   msaitoh 		    | BGE_PCIE_PWRMNG_L1THRESH_4MS
   5608  1.304   msaitoh 		    | BGE_PCIE_PWRMNG_EXTASPMTMR_EN;
   5609  1.304   msaitoh 		CSR_WRITE_4(sc, BGE_PCIE_PWRMNG_THRESH, reg);
   5610  1.304   msaitoh 
   5611  1.304   msaitoh 		reg = CSR_READ_4(sc, BGE_PCIE_EIDLE_DELAY);
   5612  1.304   msaitoh 		reg = (reg & ~BGE_PCIE_EIDLE_DELAY_MASK)
   5613  1.304   msaitoh 		    | BGE_PCIE_EIDLE_DELAY_13CLK;
   5614  1.304   msaitoh 		CSR_WRITE_4(sc, BGE_PCIE_EIDLE_DELAY, reg);
   5615  1.304   msaitoh 
   5616  1.305   msaitoh 		/* Clear correctable error */
   5617  1.305   msaitoh 		if (pci_get_ext_capability(sc->sc_pc, sc->sc_pcitag,
   5618  1.305   msaitoh 		    PCI_EXTCAP_AER, &aercap, NULL) != 0)
   5619  1.305   msaitoh 			pci_conf_write(sc->sc_pc, sc->sc_pcitag,
   5620  1.305   msaitoh 			    aercap + PCI_AER_COR_STATUS, 0xffffffff);
   5621  1.304   msaitoh 
   5622  1.304   msaitoh 		reg = CSR_READ_4(sc, BGE_PCIE_LINKCTL);
   5623  1.304   msaitoh 		reg = (reg & ~BGE_PCIE_LINKCTL_L1_PLL_PDEN)
   5624  1.304   msaitoh 		    | BGE_PCIE_LINKCTL_L1_PLL_PDDIS;
   5625  1.304   msaitoh 		CSR_WRITE_4(sc, BGE_PCIE_LINKCTL, reg);
   5626  1.304   msaitoh 	}
   5627  1.304   msaitoh 
   5628  1.177   msaitoh 	bge_sig_post_reset(sc, BGE_RESET_START);
   5629  1.177   msaitoh 
   5630    1.1      fvdl 	bge_chipinit(sc);
   5631    1.1      fvdl 
   5632    1.1      fvdl 	/*
   5633    1.1      fvdl 	 * Init the various state machines, ring
   5634    1.1      fvdl 	 * control blocks and firmware.
   5635    1.1      fvdl 	 */
   5636    1.1      fvdl 	error = bge_blockinit(sc);
   5637    1.1      fvdl 	if (error != 0) {
   5638  1.138     joerg 		aprint_error_dev(sc->bge_dev, "initialization error %d\n",
   5639    1.1      fvdl 		    error);
   5640    1.1      fvdl 		return error;
   5641    1.1      fvdl 	}
   5642    1.1      fvdl 
   5643  1.236   msaitoh 	/* 5718 step 25, 57XX step 54 */
   5644    1.1      fvdl 	/* Specify MTU. */
   5645    1.1      fvdl 	CSR_WRITE_4(sc, BGE_RX_MTU, ifp->if_mtu +
   5646  1.107     blymn 	    ETHER_HDR_LEN + ETHER_CRC_LEN + ETHER_VLAN_ENCAP_LEN);
   5647    1.1      fvdl 
   5648  1.236   msaitoh 	/* 5718 step 23 */
   5649    1.1      fvdl 	/* Load our MAC address. */
   5650  1.170   msaitoh 	m = (const uint16_t *)&(CLLADDR(ifp->if_sadl)[0]);
   5651    1.1      fvdl 	CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0]));
   5652  1.336   msaitoh 	CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI,
   5653  1.336   msaitoh 	    ((uint32_t)htons(m[1]) << 16) | htons(m[2]));
   5654    1.1      fvdl 
   5655    1.1      fvdl 	/* Enable or disable promiscuous mode as needed. */
   5656  1.378     skrll 	if (ifp->if_flags & IFF_PROMISC)
   5657    1.1      fvdl 		BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC);
   5658  1.178   msaitoh 	else
   5659    1.1      fvdl 		BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC);
   5660    1.1      fvdl 
   5661    1.1      fvdl 	/* Program multicast filter. */
   5662    1.1      fvdl 	bge_setmulti(sc);
   5663    1.1      fvdl 
   5664    1.1      fvdl 	/* Init RX ring. */
   5665    1.1      fvdl 	bge_init_rx_ring_std(sc);
   5666    1.1      fvdl 
   5667  1.161   msaitoh 	/*
   5668  1.161   msaitoh 	 * Workaround for a bug in 5705 ASIC rev A0. Poll the NIC's
   5669  1.161   msaitoh 	 * memory to insure that the chip has in fact read the first
   5670  1.161   msaitoh 	 * entry of the ring.
   5671  1.161   msaitoh 	 */
   5672  1.161   msaitoh 	if (sc->bge_chipid == BGE_CHIPID_BCM5705_A0) {
   5673  1.372     skrll 		u_int i;
   5674  1.161   msaitoh 		for (i = 0; i < 10; i++) {
   5675  1.161   msaitoh 			DELAY(20);
   5676  1.372     skrll 			uint32_t v = bge_readmem_ind(sc, BGE_STD_RX_RINGS + 8);
   5677  1.161   msaitoh 			if (v == (MCLBYTES - ETHER_ALIGN))
   5678  1.161   msaitoh 				break;
   5679  1.161   msaitoh 		}
   5680  1.161   msaitoh 		if (i == 10)
   5681  1.161   msaitoh 			aprint_error_dev(sc->bge_dev,
   5682  1.161   msaitoh 			    "5705 A0 chip failed to load RX ring\n");
   5683  1.161   msaitoh 	}
   5684  1.161   msaitoh 
   5685    1.1      fvdl 	/* Init jumbo RX ring. */
   5686    1.1      fvdl 	if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN))
   5687    1.1      fvdl 		bge_init_rx_ring_jumbo(sc);
   5688    1.1      fvdl 
   5689    1.1      fvdl 	/* Init our RX return ring index */
   5690    1.1      fvdl 	sc->bge_rx_saved_considx = 0;
   5691    1.1      fvdl 
   5692    1.1      fvdl 	/* Init TX ring. */
   5693    1.1      fvdl 	bge_init_tx_ring(sc);
   5694    1.1      fvdl 
   5695  1.236   msaitoh 	/* 5718 step 63, 57XX step 94 */
   5696  1.206   msaitoh 	/* Enable TX MAC state machine lockup fix. */
   5697  1.206   msaitoh 	mode = CSR_READ_4(sc, BGE_TX_MODE);
   5698  1.206   msaitoh 	if (BGE_IS_5755_PLUS(sc) ||
   5699  1.206   msaitoh 	    BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906)
   5700  1.206   msaitoh 		mode |= BGE_TXMODE_MBUF_LOCKUP_FIX;
   5701  1.327   msaitoh 	if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720 ||
   5702  1.327   msaitoh 	    BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5762) {
   5703  1.216   msaitoh 		mode &= ~(BGE_TXMODE_JMB_FRM_LEN | BGE_TXMODE_CNT_DN_MODE);
   5704  1.216   msaitoh 		mode |= CSR_READ_4(sc, BGE_TX_MODE) &
   5705  1.216   msaitoh 		    (BGE_TXMODE_JMB_FRM_LEN | BGE_TXMODE_CNT_DN_MODE);
   5706  1.216   msaitoh 	}
   5707  1.206   msaitoh 
   5708    1.1      fvdl 	/* Turn on transmitter */
   5709  1.211   msaitoh 	CSR_WRITE_4_FLUSH(sc, BGE_TX_MODE, mode | BGE_TXMODE_ENABLE);
   5710  1.236   msaitoh 	/* 5718 step 64 */
   5711  1.206   msaitoh 	DELAY(100);
   5712    1.1      fvdl 
   5713  1.236   msaitoh 	/* 5718 step 65, 57XX step 95 */
   5714    1.1      fvdl 	/* Turn on receiver */
   5715  1.216   msaitoh 	mode = CSR_READ_4(sc, BGE_RX_MODE);
   5716  1.216   msaitoh 	if (BGE_IS_5755_PLUS(sc))
   5717  1.216   msaitoh 		mode |= BGE_RXMODE_IPV6_ENABLE;
   5718  1.327   msaitoh 	if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5762)
   5719  1.327   msaitoh 		mode |= BGE_RXMODE_IPV4_FRAG_FIX;
   5720  1.216   msaitoh 	CSR_WRITE_4_FLUSH(sc, BGE_RX_MODE, mode | BGE_RXMODE_ENABLE);
   5721  1.236   msaitoh 	/* 5718 step 66 */
   5722  1.206   msaitoh 	DELAY(10);
   5723    1.1      fvdl 
   5724  1.258   msaitoh 	/* 5718 step 12, 57XX step 37 */
   5725  1.258   msaitoh 	/*
   5726  1.258   msaitoh 	 * XXX Doucments of 5718 series and 577xx say the recommended value
   5727  1.258   msaitoh 	 * is 1, but tg3 set 1 only on 57765 series.
   5728  1.258   msaitoh 	 */
   5729  1.258   msaitoh 	if (BGE_IS_57765_PLUS(sc))
   5730  1.258   msaitoh 		reg = 1;
   5731  1.258   msaitoh 	else
   5732  1.258   msaitoh 		reg = 2;
   5733  1.258   msaitoh 	CSR_WRITE_4_FLUSH(sc, BGE_MAX_RX_FRAME_LOWAT, reg);
   5734   1.71   thorpej 
   5735    1.1      fvdl 	/* Tell firmware we're alive. */
   5736    1.1      fvdl 	BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
   5737    1.1      fvdl 
   5738    1.1      fvdl 	/* Enable host interrupts. */
   5739  1.226   msaitoh 	BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA);
   5740  1.226   msaitoh 	BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR);
   5741  1.211   msaitoh 	bge_writembx_flush(sc, BGE_MBX_IRQ0_LO, 0);
   5742    1.1      fvdl 
   5743  1.142    dyoung 	if ((error = bge_ifmedia_upd(ifp)) != 0)
   5744  1.142    dyoung 		goto out;
   5745    1.1      fvdl 
   5746  1.375     skrll 	/* IFNET_LOCKED asserted above */
   5747    1.1      fvdl 	ifp->if_flags |= IFF_RUNNING;
   5748    1.1      fvdl 
   5749  1.345   thorpej 	callout_schedule(&sc->bge_timeout, hz);
   5750  1.142    dyoung 
   5751  1.142    dyoung out:
   5752  1.186   msaitoh 	sc->bge_if_flags = ifp->if_flags;
   5753    1.1      fvdl 
   5754  1.142    dyoung 	return error;
   5755    1.1      fvdl }
   5756    1.1      fvdl 
   5757    1.1      fvdl /*
   5758    1.1      fvdl  * Set media options.
   5759    1.1      fvdl  */
   5760  1.104   thorpej static int
   5761  1.104   thorpej bge_ifmedia_upd(struct ifnet *ifp)
   5762    1.1      fvdl {
   5763  1.354     skrll 	struct bge_softc * const sc = ifp->if_softc;
   5764  1.354     skrll 	struct mii_data * const mii = &sc->bge_mii;
   5765  1.354     skrll 	struct ifmedia * const ifm = &sc->bge_ifmedia;
   5766  1.142    dyoung 	int rc;
   5767    1.1      fvdl 
   5768    1.1      fvdl 	/* If this is a 1000baseX NIC, enable the TBI port. */
   5769  1.261   msaitoh 	if (sc->bge_flags & BGEF_FIBER_TBI) {
   5770    1.1      fvdl 		if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
   5771  1.170   msaitoh 			return EINVAL;
   5772  1.170   msaitoh 		switch (IFM_SUBTYPE(ifm->ifm_media)) {
   5773    1.1      fvdl 		case IFM_AUTO:
   5774  1.161   msaitoh 			/*
   5775  1.161   msaitoh 			 * The BCM5704 ASIC appears to have a special
   5776  1.161   msaitoh 			 * mechanism for programming the autoneg
   5777  1.161   msaitoh 			 * advertisement registers in TBI mode.
   5778  1.161   msaitoh 			 */
   5779  1.161   msaitoh 			if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) {
   5780  1.170   msaitoh 				uint32_t sgdig;
   5781  1.161   msaitoh 				sgdig = CSR_READ_4(sc, BGE_SGDIG_STS);
   5782  1.161   msaitoh 				if (sgdig & BGE_SGDIGSTS_DONE) {
   5783  1.161   msaitoh 					CSR_WRITE_4(sc, BGE_TX_TBI_AUTONEG, 0);
   5784  1.161   msaitoh 					sgdig = CSR_READ_4(sc, BGE_SGDIG_CFG);
   5785  1.161   msaitoh 					sgdig |= BGE_SGDIGCFG_AUTO |
   5786  1.161   msaitoh 					    BGE_SGDIGCFG_PAUSE_CAP |
   5787  1.161   msaitoh 					    BGE_SGDIGCFG_ASYM_PAUSE;
   5788  1.211   msaitoh 					CSR_WRITE_4_FLUSH(sc, BGE_SGDIG_CFG,
   5789  1.161   msaitoh 					    sgdig | BGE_SGDIGCFG_SEND);
   5790  1.161   msaitoh 					DELAY(5);
   5791  1.211   msaitoh 					CSR_WRITE_4_FLUSH(sc, BGE_SGDIG_CFG,
   5792  1.211   msaitoh 					    sgdig);
   5793  1.161   msaitoh 				}
   5794  1.161   msaitoh 			}
   5795    1.1      fvdl 			break;
   5796    1.1      fvdl 		case IFM_1000_SX:
   5797  1.329   msaitoh 			if ((ifm->ifm_media & IFM_FDX) != 0) {
   5798  1.341   msaitoh 				BGE_CLRBIT_FLUSH(sc, BGE_MAC_MODE,
   5799    1.1      fvdl 				    BGE_MACMODE_HALF_DUPLEX);
   5800    1.1      fvdl 			} else {
   5801  1.341   msaitoh 				BGE_SETBIT_FLUSH(sc, BGE_MAC_MODE,
   5802    1.1      fvdl 				    BGE_MACMODE_HALF_DUPLEX);
   5803    1.1      fvdl 			}
   5804  1.216   msaitoh 			DELAY(40);
   5805    1.1      fvdl 			break;
   5806    1.1      fvdl 		default:
   5807  1.170   msaitoh 			return EINVAL;
   5808    1.1      fvdl 		}
   5809   1.69   thorpej 		/* XXX 802.3x flow control for 1000BASE-SX */
   5810  1.170   msaitoh 		return 0;
   5811    1.1      fvdl 	}
   5812    1.1      fvdl 
   5813  1.287   msaitoh 	if ((BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5784) &&
   5814  1.287   msaitoh 	    (BGE_CHIPREV(sc->bge_chipid) != BGE_CHIPREV_5784_AX)) {
   5815  1.287   msaitoh 		uint32_t reg;
   5816  1.287   msaitoh 
   5817  1.287   msaitoh 		reg = CSR_READ_4(sc, BGE_CPMU_CTRL);
   5818  1.287   msaitoh 		if ((reg & BGE_CPMU_CTRL_GPHY_10MB_RXONLY) != 0) {
   5819  1.287   msaitoh 			reg &= ~BGE_CPMU_CTRL_GPHY_10MB_RXONLY;
   5820  1.287   msaitoh 			CSR_WRITE_4(sc, BGE_CPMU_CTRL, reg);
   5821  1.287   msaitoh 		}
   5822  1.287   msaitoh 	}
   5823  1.287   msaitoh 
   5824  1.161   msaitoh 	BGE_STS_SETBIT(sc, BGE_STS_LINK_EVT);
   5825  1.142    dyoung 	if ((rc = mii_mediachg(mii)) == ENXIO)
   5826  1.142    dyoung 		return 0;
   5827  1.161   msaitoh 
   5828  1.287   msaitoh 	if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5784_AX) {
   5829  1.287   msaitoh 		uint32_t reg;
   5830  1.287   msaitoh 
   5831  1.287   msaitoh 		reg = CSR_READ_4(sc, BGE_CPMU_LSPD_1000MB_CLK);
   5832  1.287   msaitoh 		if ((reg & BGE_CPMU_LSPD_1000MB_MACCLK_MASK)
   5833  1.287   msaitoh 		    == (BGE_CPMU_LSPD_1000MB_MACCLK_12_5)) {
   5834  1.287   msaitoh 			reg &= ~BGE_CPMU_LSPD_1000MB_MACCLK_MASK;
   5835  1.287   msaitoh 			delay(40);
   5836  1.287   msaitoh 			CSR_WRITE_4(sc, BGE_CPMU_LSPD_1000MB_CLK, reg);
   5837  1.287   msaitoh 		}
   5838  1.287   msaitoh 	}
   5839  1.287   msaitoh 
   5840  1.161   msaitoh 	/*
   5841  1.161   msaitoh 	 * Force an interrupt so that we will call bge_link_upd
   5842  1.161   msaitoh 	 * if needed and clear any pending link state attention.
   5843  1.161   msaitoh 	 * Without this we are not getting any further interrupts
   5844  1.161   msaitoh 	 * for link state changes and thus will not UP the link and
   5845  1.161   msaitoh 	 * not be able to send in bge_start. The only way to get
   5846  1.161   msaitoh 	 * things working was to receive a packet and get a RX intr.
   5847  1.161   msaitoh 	 */
   5848  1.161   msaitoh 	if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 ||
   5849  1.261   msaitoh 	    sc->bge_flags & BGEF_IS_5788)
   5850  1.161   msaitoh 		BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET);
   5851  1.161   msaitoh 	else
   5852  1.161   msaitoh 		BGE_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW);
   5853  1.161   msaitoh 
   5854  1.142    dyoung 	return rc;
   5855    1.1      fvdl }
   5856    1.1      fvdl 
   5857    1.1      fvdl /*
   5858    1.1      fvdl  * Report current media status.
   5859    1.1      fvdl  */
   5860  1.104   thorpej static void
   5861  1.104   thorpej bge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
   5862    1.1      fvdl {
   5863  1.354     skrll 	struct bge_softc * const sc = ifp->if_softc;
   5864  1.354     skrll 	struct mii_data * const mii = &sc->bge_mii;
   5865    1.1      fvdl 
   5866  1.261   msaitoh 	if (sc->bge_flags & BGEF_FIBER_TBI) {
   5867    1.1      fvdl 		ifmr->ifm_status = IFM_AVALID;
   5868    1.1      fvdl 		ifmr->ifm_active = IFM_ETHER;
   5869    1.1      fvdl 		if (CSR_READ_4(sc, BGE_MAC_STS) &
   5870    1.1      fvdl 		    BGE_MACSTAT_TBI_PCS_SYNCHED)
   5871    1.1      fvdl 			ifmr->ifm_status |= IFM_ACTIVE;
   5872    1.1      fvdl 		ifmr->ifm_active |= IFM_1000_SX;
   5873    1.1      fvdl 		if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX)
   5874    1.1      fvdl 			ifmr->ifm_active |= IFM_HDX;
   5875    1.1      fvdl 		else
   5876    1.1      fvdl 			ifmr->ifm_active |= IFM_FDX;
   5877    1.1      fvdl 		return;
   5878    1.1      fvdl 	}
   5879    1.1      fvdl 
   5880    1.1      fvdl 	mii_pollstat(mii);
   5881    1.1      fvdl 	ifmr->ifm_status = mii->mii_media_status;
   5882   1.69   thorpej 	ifmr->ifm_active = (mii->mii_media_active & ~IFM_ETH_FMASK) |
   5883   1.69   thorpej 	    sc->bge_flowflags;
   5884    1.1      fvdl }
   5885    1.1      fvdl 
   5886  1.104   thorpej static int
   5887  1.186   msaitoh bge_ifflags_cb(struct ethercom *ec)
   5888  1.186   msaitoh {
   5889  1.354     skrll 	struct ifnet * const ifp = &ec->ec_if;
   5890  1.354     skrll 	struct bge_softc * const sc = ifp->if_softc;
   5891  1.375     skrll 	int ret = 0;
   5892  1.375     skrll 
   5893  1.375     skrll 	KASSERT(IFNET_LOCKED(ifp));
   5894  1.375     skrll 	mutex_enter(sc->sc_core_lock);
   5895  1.375     skrll 
   5896  1.337   msaitoh 	u_short change = ifp->if_flags ^ sc->bge_if_flags;
   5897  1.186   msaitoh 
   5898  1.375     skrll 	if ((change & ~(IFF_CANTCHANGE | IFF_DEBUG)) != 0) {
   5899  1.375     skrll 		ret = ENETRESET;
   5900  1.375     skrll 	} else if ((change & (IFF_PROMISC | IFF_ALLMULTI)) != 0) {
   5901  1.375     skrll 		if ((ifp->if_flags & IFF_PROMISC) == 0)
   5902  1.375     skrll 			BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC);
   5903  1.375     skrll 		else
   5904  1.375     skrll 			BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC);
   5905  1.186   msaitoh 
   5906  1.375     skrll 		bge_setmulti(sc);
   5907  1.375     skrll 	}
   5908  1.186   msaitoh 
   5909  1.375     skrll 	sc->bge_if_flags = ifp->if_flags;
   5910  1.375     skrll 	mutex_exit(sc->sc_core_lock);
   5911  1.186   msaitoh 
   5912  1.375     skrll 	return ret;
   5913  1.186   msaitoh }
   5914  1.186   msaitoh 
   5915  1.186   msaitoh static int
   5916  1.126  christos bge_ioctl(struct ifnet *ifp, u_long command, void *data)
   5917    1.1      fvdl {
   5918  1.354     skrll 	struct bge_softc * const sc = ifp->if_softc;
   5919  1.354     skrll 	struct ifreq * const ifr = (struct ifreq *) data;
   5920  1.375     skrll 	int error = 0;
   5921  1.375     skrll 
   5922  1.375     skrll 	switch (command) {
   5923  1.375     skrll 	case SIOCADDMULTI:
   5924  1.375     skrll 	case SIOCDELMULTI:
   5925  1.375     skrll 		break;
   5926  1.375     skrll 	default:
   5927  1.375     skrll 		KASSERT(IFNET_LOCKED(ifp));
   5928  1.375     skrll 	}
   5929    1.1      fvdl 
   5930  1.375     skrll 	const int s = splnet();
   5931    1.1      fvdl 
   5932  1.170   msaitoh 	switch (command) {
   5933    1.1      fvdl 	case SIOCSIFMEDIA:
   5934  1.375     skrll 		mutex_enter(sc->sc_core_lock);
   5935   1.69   thorpej 		/* XXX Flow control is not supported for 1000BASE-SX */
   5936  1.261   msaitoh 		if (sc->bge_flags & BGEF_FIBER_TBI) {
   5937   1.69   thorpej 			ifr->ifr_media &= ~IFM_ETH_FMASK;
   5938   1.69   thorpej 			sc->bge_flowflags = 0;
   5939   1.69   thorpej 		}
   5940   1.69   thorpej 
   5941   1.69   thorpej 		/* Flow control requires full-duplex mode. */
   5942   1.69   thorpej 		if (IFM_SUBTYPE(ifr->ifr_media) == IFM_AUTO ||
   5943   1.69   thorpej 		    (ifr->ifr_media & IFM_FDX) == 0) {
   5944  1.330   msaitoh 			ifr->ifr_media &= ~IFM_ETH_FMASK;
   5945   1.69   thorpej 		}
   5946   1.69   thorpej 		if (IFM_SUBTYPE(ifr->ifr_media) != IFM_AUTO) {
   5947   1.69   thorpej 			if ((ifr->ifr_media & IFM_ETH_FMASK) == IFM_FLOW) {
   5948  1.157   msaitoh 				/* We can do both TXPAUSE and RXPAUSE. */
   5949   1.69   thorpej 				ifr->ifr_media |=
   5950   1.69   thorpej 				    IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE;
   5951   1.69   thorpej 			}
   5952   1.69   thorpej 			sc->bge_flowflags = ifr->ifr_media & IFM_ETH_FMASK;
   5953   1.69   thorpej 		}
   5954  1.375     skrll 		mutex_exit(sc->sc_core_lock);
   5955  1.334   msaitoh 
   5956  1.261   msaitoh 		if (sc->bge_flags & BGEF_FIBER_TBI) {
   5957    1.1      fvdl 			error = ifmedia_ioctl(ifp, ifr, &sc->bge_ifmedia,
   5958    1.1      fvdl 			    command);
   5959    1.1      fvdl 		} else {
   5960  1.375     skrll 			struct mii_data * const mii = &sc->bge_mii;
   5961    1.1      fvdl 			error = ifmedia_ioctl(ifp, ifr, &mii->mii_media,
   5962    1.1      fvdl 			    command);
   5963    1.1      fvdl 		}
   5964    1.1      fvdl 		break;
   5965    1.1      fvdl 	default:
   5966  1.152      tron 		if ((error = ether_ioctl(ifp, command, data)) != ENETRESET)
   5967  1.152      tron 			break;
   5968  1.152      tron 
   5969  1.152      tron 		error = 0;
   5970  1.152      tron 
   5971  1.375     skrll 		if (command == SIOCADDMULTI || command == SIOCDELMULTI) {
   5972  1.375     skrll 			mutex_enter(sc->sc_core_lock);
   5973  1.375     skrll 			if (sc->bge_if_flags & IFF_RUNNING) {
   5974  1.375     skrll 				bge_setmulti(sc);
   5975  1.375     skrll 			}
   5976  1.375     skrll 			mutex_exit(sc->sc_core_lock);
   5977  1.375     skrll 		}
   5978    1.1      fvdl 		break;
   5979    1.1      fvdl 	}
   5980    1.1      fvdl 
   5981    1.1      fvdl 	splx(s);
   5982    1.1      fvdl 
   5983  1.170   msaitoh 	return error;
   5984    1.1      fvdl }
   5985    1.1      fvdl 
   5986  1.375     skrll static bool
   5987  1.375     skrll bge_watchdog_check(struct bge_softc * const sc)
   5988    1.1      fvdl {
   5989  1.375     skrll 
   5990  1.375     skrll 	KASSERT(mutex_owned(sc->sc_core_lock));
   5991  1.375     skrll 
   5992  1.375     skrll 	if (!sc->bge_tx_sending)
   5993  1.375     skrll 		return true;
   5994  1.375     skrll 
   5995  1.375     skrll 	if (time_uptime - sc->bge_tx_lastsent <= bge_watchdog_timeout)
   5996  1.375     skrll 		return true;
   5997    1.1      fvdl 
   5998  1.330   msaitoh 	/* If pause frames are active then don't reset the hardware. */
   5999  1.320    bouyer 	if ((CSR_READ_4(sc, BGE_RX_MODE) & BGE_RXMODE_FLOWCTL_ENABLE) != 0) {
   6000  1.375     skrll 		const uint32_t status = CSR_READ_4(sc, BGE_RX_STS);
   6001  1.320    bouyer 		if ((status & BGE_RXSTAT_REMOTE_XOFFED) != 0) {
   6002  1.320    bouyer 			/*
   6003  1.320    bouyer 			 * If link partner has us in XOFF state then wait for
   6004  1.320    bouyer 			 * the condition to clear.
   6005  1.320    bouyer 			 */
   6006  1.320    bouyer 			CSR_WRITE_4(sc, BGE_RX_STS, status);
   6007  1.375     skrll 			sc->bge_tx_lastsent = time_uptime;
   6008  1.375     skrll 			return true;
   6009  1.320    bouyer 		} else if ((status & BGE_RXSTAT_RCVD_XOFF) != 0 &&
   6010  1.320    bouyer 		    (status & BGE_RXSTAT_RCVD_XON) != 0) {
   6011  1.320    bouyer 			/*
   6012  1.320    bouyer 			 * If link partner has us in XOFF state then wait for
   6013  1.320    bouyer 			 * the condition to clear.
   6014  1.320    bouyer 			 */
   6015  1.320    bouyer 			CSR_WRITE_4(sc, BGE_RX_STS, status);
   6016  1.375     skrll 			sc->bge_tx_lastsent = time_uptime;
   6017  1.375     skrll 			return true;
   6018  1.320    bouyer 		}
   6019  1.320    bouyer 		/*
   6020  1.330   msaitoh 		 * Any other condition is unexpected and the controller
   6021  1.330   msaitoh 		 * should be reset.
   6022  1.320    bouyer 		 */
   6023  1.320    bouyer 	}
   6024  1.320    bouyer 
   6025  1.375     skrll 	return false;
   6026  1.375     skrll }
   6027  1.375     skrll 
   6028  1.375     skrll static bool
   6029  1.375     skrll bge_watchdog(struct ifnet *ifp)
   6030  1.375     skrll {
   6031  1.375     skrll 	struct bge_softc * const sc = ifp->if_softc;
   6032  1.375     skrll 
   6033  1.375     skrll 	KASSERT(mutex_owned(sc->sc_core_lock));
   6034  1.375     skrll 
   6035  1.379     skrll 	if (!sc->sc_trigger_reset && bge_watchdog_check(sc))
   6036  1.375     skrll 		return true;
   6037  1.375     skrll 
   6038  1.138     joerg 	aprint_error_dev(sc->bge_dev, "watchdog timeout -- resetting\n");
   6039    1.1      fvdl 
   6040  1.375     skrll 	if (atomic_swap_uint(&sc->sc_reset_pending, 1) == 0)
   6041  1.375     skrll 		workqueue_enqueue(sc->sc_reset_wq, &sc->sc_reset_work, NULL);
   6042  1.375     skrll 
   6043  1.375     skrll 	return false;
   6044  1.375     skrll }
   6045  1.375     skrll 
   6046  1.375     skrll /*
   6047  1.375     skrll  * Perform an interface watchdog reset.
   6048  1.375     skrll  */
   6049  1.375     skrll static void
   6050  1.375     skrll bge_handle_reset_work(struct work *work, void *arg)
   6051  1.375     skrll {
   6052  1.375     skrll 	struct bge_softc * const sc = arg;
   6053  1.375     skrll 	struct ifnet * const ifp = &sc->ethercom.ec_if;
   6054  1.375     skrll 
   6055  1.375     skrll 	/* Don't want ioctl operations to happen */
   6056  1.375     skrll 	IFNET_LOCK(ifp);
   6057  1.375     skrll 
   6058  1.375     skrll 	/* reset the interface. */
   6059    1.1      fvdl 	bge_init(ifp);
   6060    1.1      fvdl 
   6061  1.375     skrll 	IFNET_UNLOCK(ifp);
   6062  1.375     skrll 
   6063  1.375     skrll 	/*
   6064  1.375     skrll 	 * There are still some upper layer processing which call
   6065  1.375     skrll 	 * ifp->if_start(). e.g. ALTQ or one CPU system
   6066  1.375     skrll 	 */
   6067  1.375     skrll 	/* Try to get more packets going. */
   6068  1.375     skrll 	ifp->if_start(ifp);
   6069  1.375     skrll 
   6070  1.375     skrll 	atomic_store_relaxed(&sc->sc_reset_pending, 0);
   6071    1.1      fvdl }
   6072    1.1      fvdl 
   6073   1.11   thorpej static void
   6074   1.11   thorpej bge_stop_block(struct bge_softc *sc, bus_addr_t reg, uint32_t bit)
   6075   1.11   thorpej {
   6076   1.11   thorpej 	int i;
   6077   1.11   thorpej 
   6078  1.211   msaitoh 	BGE_CLRBIT_FLUSH(sc, reg, bit);
   6079   1.11   thorpej 
   6080  1.180   msaitoh 	for (i = 0; i < 1000; i++) {
   6081  1.216   msaitoh 		delay(100);
   6082   1.11   thorpej 		if ((CSR_READ_4(sc, reg) & bit) == 0)
   6083   1.11   thorpej 			return;
   6084   1.11   thorpej 	}
   6085   1.11   thorpej 
   6086  1.165   msaitoh 	/*
   6087  1.165   msaitoh 	 * Doesn't print only when the register is BGE_SRS_MODE. It occurs
   6088  1.165   msaitoh 	 * on some environment (and once after boot?)
   6089  1.165   msaitoh 	 */
   6090  1.165   msaitoh 	if (reg != BGE_SRS_MODE)
   6091  1.165   msaitoh 		aprint_error_dev(sc->bge_dev,
   6092  1.165   msaitoh 		    "block failed to stop: reg 0x%lx, bit 0x%08x\n",
   6093  1.165   msaitoh 		    (u_long)reg, bit);
   6094   1.11   thorpej }
   6095   1.11   thorpej 
   6096  1.375     skrll 
   6097  1.375     skrll static void
   6098  1.375     skrll bge_stop(struct ifnet *ifp, int disable)
   6099  1.375     skrll {
   6100  1.375     skrll 	struct bge_softc * const sc = ifp->if_softc;
   6101  1.375     skrll 
   6102  1.375     skrll 	ASSERT_SLEEPABLE();
   6103  1.375     skrll 
   6104  1.375     skrll 	mutex_enter(sc->sc_core_lock);
   6105  1.375     skrll 	bge_stop_locked(ifp, disable);
   6106  1.375     skrll 	mutex_exit(sc->sc_core_lock);
   6107  1.375     skrll }
   6108  1.375     skrll 
   6109    1.1      fvdl /*
   6110    1.1      fvdl  * Stop the adapter and free any mbufs allocated to the
   6111    1.1      fvdl  * RX and TX lists.
   6112    1.1      fvdl  */
   6113  1.104   thorpej static void
   6114  1.375     skrll bge_stop_locked(struct ifnet *ifp, int disable)
   6115    1.1      fvdl {
   6116  1.354     skrll 	struct bge_softc * const sc = ifp->if_softc;
   6117    1.1      fvdl 
   6118  1.375     skrll 	KASSERT(mutex_owned(sc->sc_core_lock));
   6119  1.375     skrll 
   6120  1.292    martin 	if (disable) {
   6121  1.380     skrll 		sc->bge_detaching = true;
   6122  1.281    martin 		callout_halt(&sc->bge_timeout, NULL);
   6123  1.292    martin 	} else
   6124  1.281    martin 		callout_stop(&sc->bge_timeout);
   6125    1.1      fvdl 
   6126  1.216   msaitoh 	/* Disable host interrupts. */
   6127  1.226   msaitoh 	BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR);
   6128  1.216   msaitoh 	bge_writembx_flush(sc, BGE_MBX_IRQ0_LO, 1);
   6129  1.216   msaitoh 
   6130    1.1      fvdl 	/*
   6131  1.177   msaitoh 	 * Tell firmware we're shutting down.
   6132  1.177   msaitoh 	 */
   6133  1.177   msaitoh 	bge_stop_fw(sc);
   6134  1.216   msaitoh 	bge_sig_pre_reset(sc, BGE_RESET_SHUTDOWN);
   6135  1.177   msaitoh 
   6136  1.177   msaitoh 	/*
   6137  1.208   msaitoh 	 * Disable all of the receiver blocks.
   6138    1.1      fvdl 	 */
   6139   1.11   thorpej 	bge_stop_block(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE);
   6140   1.11   thorpej 	bge_stop_block(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE);
   6141   1.11   thorpej 	bge_stop_block(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);
   6142  1.172   msaitoh 	if (BGE_IS_5700_FAMILY(sc))
   6143   1.44   hannken 		bge_stop_block(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE);
   6144   1.11   thorpej 	bge_stop_block(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE);
   6145   1.11   thorpej 	bge_stop_block(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);
   6146   1.11   thorpej 	bge_stop_block(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE);
   6147    1.1      fvdl 
   6148    1.1      fvdl 	/*
   6149  1.208   msaitoh 	 * Disable all of the transmit blocks.
   6150    1.1      fvdl 	 */
   6151   1.11   thorpej 	bge_stop_block(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE);
   6152   1.11   thorpej 	bge_stop_block(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE);
   6153   1.11   thorpej 	bge_stop_block(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE);
   6154   1.11   thorpej 	bge_stop_block(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE);
   6155   1.11   thorpej 	bge_stop_block(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE);
   6156  1.172   msaitoh 	if (BGE_IS_5700_FAMILY(sc))
   6157   1.44   hannken 		bge_stop_block(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE);
   6158   1.11   thorpej 	bge_stop_block(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);
   6159    1.1      fvdl 
   6160  1.216   msaitoh 	BGE_CLRBIT_FLUSH(sc, BGE_MAC_MODE, BGE_MACMODE_TXDMA_ENB);
   6161  1.216   msaitoh 	delay(40);
   6162  1.216   msaitoh 
   6163  1.216   msaitoh 	bge_stop_block(sc, BGE_TX_MODE, BGE_TXMODE_ENABLE);
   6164  1.216   msaitoh 
   6165    1.1      fvdl 	/*
   6166    1.1      fvdl 	 * Shut down all of the memory managers and related
   6167    1.1      fvdl 	 * state machines.
   6168    1.1      fvdl 	 */
   6169  1.236   msaitoh 	/* 5718 step 5a,5b */
   6170   1.11   thorpej 	bge_stop_block(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE);
   6171   1.11   thorpej 	bge_stop_block(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE);
   6172  1.172   msaitoh 	if (BGE_IS_5700_FAMILY(sc))
   6173   1.44   hannken 		bge_stop_block(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE);
   6174   1.11   thorpej 
   6175  1.236   msaitoh 	/* 5718 step 5c,5d */
   6176    1.1      fvdl 	CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF);
   6177    1.1      fvdl 	CSR_WRITE_4(sc, BGE_FTQ_RESET, 0);
   6178   1.11   thorpej 
   6179  1.172   msaitoh 	if (BGE_IS_5700_FAMILY(sc)) {
   6180   1.44   hannken 		bge_stop_block(sc, BGE_BMAN_MODE, BGE_BMANMODE_ENABLE);
   6181   1.44   hannken 		bge_stop_block(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE);
   6182   1.44   hannken 	}
   6183    1.1      fvdl 
   6184  1.177   msaitoh 	bge_reset(sc);
   6185  1.216   msaitoh 	bge_sig_legacy(sc, BGE_RESET_SHUTDOWN);
   6186  1.216   msaitoh 	bge_sig_post_reset(sc, BGE_RESET_SHUTDOWN);
   6187    1.1      fvdl 
   6188    1.1      fvdl 	/*
   6189  1.177   msaitoh 	 * Keep the ASF firmware running if up.
   6190    1.1      fvdl 	 */
   6191  1.177   msaitoh 	if (sc->bge_asf_mode & ASF_STACKUP)
   6192  1.177   msaitoh 		BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
   6193  1.177   msaitoh 	else
   6194  1.177   msaitoh 		BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
   6195    1.1      fvdl 
   6196    1.1      fvdl 	/* Free the RX lists. */
   6197  1.376     skrll 	bge_free_rx_ring_std(sc);
   6198    1.1      fvdl 
   6199    1.1      fvdl 	/* Free jumbo RX list. */
   6200  1.172   msaitoh 	if (BGE_IS_JUMBO_CAPABLE(sc))
   6201  1.172   msaitoh 		bge_free_rx_ring_jumbo(sc);
   6202    1.1      fvdl 
   6203    1.1      fvdl 	/* Free TX buffers. */
   6204  1.320    bouyer 	bge_free_tx_ring(sc, disable);
   6205    1.1      fvdl 
   6206    1.1      fvdl 	/*
   6207    1.1      fvdl 	 * Isolate/power down the PHY.
   6208    1.1      fvdl 	 */
   6209  1.261   msaitoh 	if (!(sc->bge_flags & BGEF_FIBER_TBI))
   6210    1.1      fvdl 		mii_down(&sc->bge_mii);
   6211    1.1      fvdl 
   6212  1.161   msaitoh 	sc->bge_tx_saved_considx = BGE_TXCONS_UNSET;
   6213    1.1      fvdl 
   6214  1.161   msaitoh 	/* Clear MAC's link state (PHY may still have link UP). */
   6215  1.161   msaitoh 	BGE_STS_CLRBIT(sc, BGE_STS_LINK);
   6216    1.1      fvdl 
   6217  1.375     skrll 	ifp->if_flags &= ~IFF_RUNNING;
   6218    1.1      fvdl }
   6219    1.1      fvdl 
   6220  1.161   msaitoh static void
   6221  1.161   msaitoh bge_link_upd(struct bge_softc *sc)
   6222  1.161   msaitoh {
   6223  1.354     skrll 	struct ifnet * const ifp = &sc->ethercom.ec_if;
   6224  1.354     skrll 	struct mii_data * const mii = &sc->bge_mii;
   6225  1.170   msaitoh 	uint32_t status;
   6226  1.322   msaitoh 	uint16_t phyval;
   6227  1.161   msaitoh 	int link;
   6228  1.161   msaitoh 
   6229  1.161   msaitoh 	/* Clear 'pending link event' flag */
   6230  1.161   msaitoh 	BGE_STS_CLRBIT(sc, BGE_STS_LINK_EVT);
   6231  1.161   msaitoh 
   6232  1.161   msaitoh 	/*
   6233  1.161   msaitoh 	 * Process link state changes.
   6234  1.161   msaitoh 	 * Grrr. The link status word in the status block does
   6235  1.161   msaitoh 	 * not work correctly on the BCM5700 rev AX and BX chips,
   6236  1.161   msaitoh 	 * according to all available information. Hence, we have
   6237  1.161   msaitoh 	 * to enable MII interrupts in order to properly obtain
   6238  1.161   msaitoh 	 * async link changes. Unfortunately, this also means that
   6239  1.161   msaitoh 	 * we have to read the MAC status register to detect link
   6240  1.161   msaitoh 	 * changes, thereby adding an additional register access to
   6241  1.161   msaitoh 	 * the interrupt handler.
   6242  1.161   msaitoh 	 */
   6243  1.161   msaitoh 
   6244  1.161   msaitoh 	if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700) {
   6245  1.161   msaitoh 		status = CSR_READ_4(sc, BGE_MAC_STS);
   6246  1.161   msaitoh 		if (status & BGE_MACSTAT_MI_INTERRUPT) {
   6247  1.161   msaitoh 			mii_pollstat(mii);
   6248  1.161   msaitoh 
   6249  1.161   msaitoh 			if (!BGE_STS_BIT(sc, BGE_STS_LINK) &&
   6250  1.161   msaitoh 			    mii->mii_media_status & IFM_ACTIVE &&
   6251  1.161   msaitoh 			    IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE)
   6252  1.161   msaitoh 				BGE_STS_SETBIT(sc, BGE_STS_LINK);
   6253  1.161   msaitoh 			else if (BGE_STS_BIT(sc, BGE_STS_LINK) &&
   6254  1.161   msaitoh 			    (!(mii->mii_media_status & IFM_ACTIVE) ||
   6255  1.161   msaitoh 			    IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE))
   6256  1.161   msaitoh 				BGE_STS_CLRBIT(sc, BGE_STS_LINK);
   6257  1.161   msaitoh 
   6258  1.161   msaitoh 			/* Clear the interrupt */
   6259  1.161   msaitoh 			CSR_WRITE_4(sc, BGE_MAC_EVT_ENB,
   6260  1.161   msaitoh 			    BGE_EVTENB_MI_INTERRUPT);
   6261  1.216   msaitoh 			bge_miibus_readreg(sc->bge_dev, sc->bge_phy_addr,
   6262  1.322   msaitoh 			    BRGPHY_MII_ISR, &phyval);
   6263  1.216   msaitoh 			bge_miibus_writereg(sc->bge_dev, sc->bge_phy_addr,
   6264  1.216   msaitoh 			    BRGPHY_MII_IMR, BRGPHY_INTRS);
   6265  1.161   msaitoh 		}
   6266  1.161   msaitoh 		return;
   6267  1.161   msaitoh 	}
   6268  1.161   msaitoh 
   6269  1.261   msaitoh 	if (sc->bge_flags & BGEF_FIBER_TBI) {
   6270  1.161   msaitoh 		status = CSR_READ_4(sc, BGE_MAC_STS);
   6271  1.161   msaitoh 		if (status & BGE_MACSTAT_TBI_PCS_SYNCHED) {
   6272  1.161   msaitoh 			if (!BGE_STS_BIT(sc, BGE_STS_LINK)) {
   6273  1.161   msaitoh 				BGE_STS_SETBIT(sc, BGE_STS_LINK);
   6274  1.219   msaitoh 				if (BGE_ASICREV(sc->bge_chipid)
   6275  1.219   msaitoh 				    == BGE_ASICREV_BCM5704) {
   6276  1.341   msaitoh 					BGE_CLRBIT_FLUSH(sc, BGE_MAC_MODE,
   6277  1.161   msaitoh 					    BGE_MACMODE_TBI_SEND_CFGS);
   6278  1.219   msaitoh 					DELAY(40);
   6279  1.219   msaitoh 				}
   6280  1.161   msaitoh 				CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF);
   6281  1.161   msaitoh 				if_link_state_change(ifp, LINK_STATE_UP);
   6282  1.161   msaitoh 			}
   6283  1.161   msaitoh 		} else if (BGE_STS_BIT(sc, BGE_STS_LINK)) {
   6284  1.161   msaitoh 			BGE_STS_CLRBIT(sc, BGE_STS_LINK);
   6285  1.161   msaitoh 			if_link_state_change(ifp, LINK_STATE_DOWN);
   6286  1.161   msaitoh 		}
   6287  1.161   msaitoh 	} else if (BGE_STS_BIT(sc, BGE_STS_AUTOPOLL)) {
   6288  1.178   msaitoh 		/*
   6289  1.161   msaitoh 		 * Some broken BCM chips have BGE_STATFLAG_LINKSTATE_CHANGED
   6290  1.161   msaitoh 		 * bit in status word always set. Workaround this bug by
   6291  1.161   msaitoh 		 * reading PHY link status directly.
   6292  1.161   msaitoh 		 */
   6293  1.161   msaitoh 		link = (CSR_READ_4(sc, BGE_MI_STS) & BGE_MISTS_LINK)?
   6294  1.161   msaitoh 		    BGE_STS_LINK : 0;
   6295  1.161   msaitoh 
   6296  1.161   msaitoh 		if (BGE_STS_BIT(sc, BGE_STS_LINK) != link) {
   6297  1.161   msaitoh 			mii_pollstat(mii);
   6298  1.161   msaitoh 
   6299  1.161   msaitoh 			if (!BGE_STS_BIT(sc, BGE_STS_LINK) &&
   6300  1.161   msaitoh 			    mii->mii_media_status & IFM_ACTIVE &&
   6301  1.161   msaitoh 			    IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE)
   6302  1.161   msaitoh 				BGE_STS_SETBIT(sc, BGE_STS_LINK);
   6303  1.161   msaitoh 			else if (BGE_STS_BIT(sc, BGE_STS_LINK) &&
   6304  1.161   msaitoh 			    (!(mii->mii_media_status & IFM_ACTIVE) ||
   6305  1.161   msaitoh 			    IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE))
   6306  1.161   msaitoh 				BGE_STS_CLRBIT(sc, BGE_STS_LINK);
   6307  1.161   msaitoh 		}
   6308  1.256   msaitoh 	} else {
   6309  1.256   msaitoh 		/*
   6310  1.256   msaitoh 		 * For controllers that call mii_tick, we have to poll
   6311  1.256   msaitoh 		 * link status.
   6312  1.256   msaitoh 		 */
   6313  1.256   msaitoh 		mii_pollstat(mii);
   6314  1.161   msaitoh 	}
   6315  1.161   msaitoh 
   6316  1.287   msaitoh 	if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5784_AX) {
   6317  1.287   msaitoh 		uint32_t reg, scale;
   6318  1.287   msaitoh 
   6319  1.287   msaitoh 		reg = CSR_READ_4(sc, BGE_CPMU_CLCK_STAT) &
   6320  1.287   msaitoh 		    BGE_CPMU_CLCK_STAT_MAC_CLCK_MASK;
   6321  1.287   msaitoh 		if (reg == BGE_CPMU_CLCK_STAT_MAC_CLCK_62_5)
   6322  1.287   msaitoh 			scale = 65;
   6323  1.287   msaitoh 		else if (reg == BGE_CPMU_CLCK_STAT_MAC_CLCK_6_25)
   6324  1.287   msaitoh 			scale = 6;
   6325  1.287   msaitoh 		else
   6326  1.287   msaitoh 			scale = 12;
   6327  1.287   msaitoh 
   6328  1.287   msaitoh 		reg = CSR_READ_4(sc, BGE_MISC_CFG) &
   6329  1.287   msaitoh 		    ~BGE_MISCCFG_TIMER_PRESCALER;
   6330  1.287   msaitoh 		reg |= scale << 1;
   6331  1.287   msaitoh 		CSR_WRITE_4(sc, BGE_MISC_CFG, reg);
   6332  1.287   msaitoh 	}
   6333  1.161   msaitoh 	/* Clear the attention */
   6334  1.331   msaitoh 	CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
   6335  1.331   msaitoh 	    BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE |
   6336  1.161   msaitoh 	    BGE_MACSTAT_LINK_CHANGED);
   6337  1.161   msaitoh }
   6338  1.161   msaitoh 
   6339   1.64  jonathan static int
   6340  1.207   msaitoh bge_sysctl_verify(SYSCTLFN_ARGS)
   6341   1.64  jonathan {
   6342   1.64  jonathan 	int error, t;
   6343   1.64  jonathan 	struct sysctlnode node;
   6344   1.64  jonathan 
   6345   1.64  jonathan 	node = *rnode;
   6346   1.64  jonathan 	t = *(int*)rnode->sysctl_data;
   6347   1.64  jonathan 	node.sysctl_data = &t;
   6348   1.64  jonathan 	error = sysctl_lookup(SYSCTLFN_CALL(&node));
   6349   1.64  jonathan 	if (error || newp == NULL)
   6350  1.170   msaitoh 		return error;
   6351   1.64  jonathan 
   6352   1.64  jonathan #if 0
   6353   1.64  jonathan 	DPRINTF2(("%s: t = %d, nodenum = %d, rnodenum = %d\n", __func__, t,
   6354   1.64  jonathan 	    node.sysctl_num, rnode->sysctl_num));
   6355   1.64  jonathan #endif
   6356   1.64  jonathan 
   6357   1.64  jonathan 	if (node.sysctl_num == bge_rxthresh_nodenum) {
   6358   1.64  jonathan 		if (t < 0 || t >= NBGE_RX_THRESH)
   6359  1.170   msaitoh 			return EINVAL;
   6360   1.64  jonathan 		bge_update_all_threshes(t);
   6361   1.64  jonathan 	} else
   6362  1.170   msaitoh 		return EINVAL;
   6363   1.64  jonathan 
   6364   1.64  jonathan 	*(int*)rnode->sysctl_data = t;
   6365   1.64  jonathan 
   6366  1.170   msaitoh 	return 0;
   6367   1.64  jonathan }
   6368   1.64  jonathan 
   6369   1.64  jonathan /*
   6370   1.65    atatat  * Set up sysctl(3) MIB, hw.bge.*.
   6371   1.64  jonathan  */
   6372  1.190    jruoho static void
   6373  1.207   msaitoh bge_sysctl_init(struct bge_softc *sc)
   6374   1.64  jonathan {
   6375   1.66    atatat 	int rc, bge_root_num;
   6376   1.90    atatat 	const struct sysctlnode *node;
   6377   1.64  jonathan 
   6378  1.190    jruoho 	if ((rc = sysctl_createv(&sc->bge_log, 0, NULL, &node,
   6379  1.190    jruoho 	    0, CTLTYPE_NODE, "bge",
   6380   1.73    atatat 	    SYSCTL_DESCR("BGE interface controls"),
   6381   1.64  jonathan 	    NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL)) != 0) {
   6382  1.203   msaitoh 		goto out;
   6383   1.64  jonathan 	}
   6384   1.64  jonathan 
   6385   1.66    atatat 	bge_root_num = node->sysctl_num;
   6386   1.66    atatat 
   6387   1.64  jonathan 	/* BGE Rx interrupt mitigation level */
   6388  1.190    jruoho 	if ((rc = sysctl_createv(&sc->bge_log, 0, NULL, &node,
   6389  1.190    jruoho 	    CTLFLAG_READWRITE,
   6390   1.73    atatat 	    CTLTYPE_INT, "rx_lvl",
   6391   1.73    atatat 	    SYSCTL_DESCR("BGE receive interrupt mitigation level"),
   6392  1.207   msaitoh 	    bge_sysctl_verify, 0,
   6393   1.64  jonathan 	    &bge_rx_thresh_lvl,
   6394   1.66    atatat 	    0, CTL_HW, bge_root_num, CTL_CREATE,
   6395   1.64  jonathan 	    CTL_EOL)) != 0) {
   6396  1.203   msaitoh 		goto out;
   6397   1.64  jonathan 	}
   6398   1.64  jonathan 
   6399   1.64  jonathan 	bge_rxthresh_nodenum = node->sysctl_num;
   6400   1.64  jonathan 
   6401  1.375     skrll #ifdef BGE_DEBUG
   6402  1.375     skrll 	if ((rc = sysctl_createv(&sc->bge_log, 0, NULL, &node,
   6403  1.375     skrll 	    CTLFLAG_READWRITE,
   6404  1.375     skrll 	    CTLTYPE_BOOL, "trigger_reset",
   6405  1.375     skrll 	    SYSCTL_DESCR("Trigger an interface reset"),
   6406  1.379     skrll 	    NULL, 0, &sc->sc_trigger_reset, 0, CTL_CREATE,
   6407  1.375     skrll 	    CTL_EOL)) != 0) {
   6408  1.375     skrll 		goto out;
   6409  1.375     skrll 	}
   6410  1.375     skrll #endif
   6411   1.64  jonathan 	return;
   6412   1.64  jonathan 
   6413  1.203   msaitoh out:
   6414  1.138     joerg 	aprint_error("%s: sysctl_createv failed (rc = %d)\n", __func__, rc);
   6415   1.64  jonathan }
   6416  1.151    cegger 
   6417  1.172   msaitoh #ifdef BGE_DEBUG
   6418  1.172   msaitoh void
   6419  1.172   msaitoh bge_debug_info(struct bge_softc *sc)
   6420  1.172   msaitoh {
   6421  1.172   msaitoh 
   6422  1.172   msaitoh 	printf("Hardware Flags:\n");
   6423  1.214   msaitoh 	if (BGE_IS_57765_PLUS(sc))
   6424  1.214   msaitoh 		printf(" - 57765 Plus\n");
   6425  1.214   msaitoh 	if (BGE_IS_5717_PLUS(sc))
   6426  1.214   msaitoh 		printf(" - 5717 Plus\n");
   6427  1.172   msaitoh 	if (BGE_IS_5755_PLUS(sc))
   6428  1.172   msaitoh 		printf(" - 5755 Plus\n");
   6429  1.207   msaitoh 	if (BGE_IS_575X_PLUS(sc))
   6430  1.207   msaitoh 		printf(" - 575X Plus\n");
   6431  1.172   msaitoh 	if (BGE_IS_5705_PLUS(sc))
   6432  1.172   msaitoh 		printf(" - 5705 Plus\n");
   6433  1.172   msaitoh 	if (BGE_IS_5714_FAMILY(sc))
   6434  1.172   msaitoh 		printf(" - 5714 Family\n");
   6435  1.172   msaitoh 	if (BGE_IS_5700_FAMILY(sc))
   6436  1.172   msaitoh 		printf(" - 5700 Family\n");
   6437  1.261   msaitoh 	if (sc->bge_flags & BGEF_IS_5788)
   6438  1.172   msaitoh 		printf(" - 5788\n");
   6439  1.261   msaitoh 	if (sc->bge_flags & BGEF_JUMBO_CAPABLE)
   6440  1.172   msaitoh 		printf(" - Supports Jumbo Frames\n");
   6441  1.261   msaitoh 	if (sc->bge_flags & BGEF_NO_EEPROM)
   6442  1.173   msaitoh 		printf(" - No EEPROM\n");
   6443  1.261   msaitoh 	if (sc->bge_flags & BGEF_PCIX)
   6444  1.172   msaitoh 		printf(" - PCI-X Bus\n");
   6445  1.261   msaitoh 	if (sc->bge_flags & BGEF_PCIE)
   6446  1.172   msaitoh 		printf(" - PCI Express Bus\n");
   6447  1.261   msaitoh 	if (sc->bge_flags & BGEF_RX_ALIGNBUG)
   6448  1.172   msaitoh 		printf(" - RX Alignment Bug\n");
   6449  1.261   msaitoh 	if (sc->bge_flags & BGEF_APE)
   6450  1.216   msaitoh 		printf(" - APE\n");
   6451  1.261   msaitoh 	if (sc->bge_flags & BGEF_CPMU_PRESENT)
   6452  1.214   msaitoh 		printf(" - CPMU\n");
   6453  1.261   msaitoh 	if (sc->bge_flags & BGEF_TSO)
   6454  1.172   msaitoh 		printf(" - TSO\n");
   6455  1.288   msaitoh 	if (sc->bge_flags & BGEF_TAGGED_STATUS)
   6456  1.288   msaitoh 		printf(" - TAGGED_STATUS\n");
   6457  1.220   msaitoh 
   6458  1.279   msaitoh 	/* PHY related */
   6459  1.261   msaitoh 	if (sc->bge_phy_flags & BGEPHYF_NO_3LED)
   6460  1.220   msaitoh 		printf(" - No 3 LEDs\n");
   6461  1.261   msaitoh 	if (sc->bge_phy_flags & BGEPHYF_CRC_BUG)
   6462  1.220   msaitoh 		printf(" - CRC bug\n");
   6463  1.261   msaitoh 	if (sc->bge_phy_flags & BGEPHYF_ADC_BUG)
   6464  1.220   msaitoh 		printf(" - ADC bug\n");
   6465  1.261   msaitoh 	if (sc->bge_phy_flags & BGEPHYF_5704_A0_BUG)
   6466  1.220   msaitoh 		printf(" - 5704 A0 bug\n");
   6467  1.261   msaitoh 	if (sc->bge_phy_flags & BGEPHYF_JITTER_BUG)
   6468  1.220   msaitoh 		printf(" - jitter bug\n");
   6469  1.261   msaitoh 	if (sc->bge_phy_flags & BGEPHYF_BER_BUG)
   6470  1.220   msaitoh 		printf(" - BER bug\n");
   6471  1.261   msaitoh 	if (sc->bge_phy_flags & BGEPHYF_ADJUST_TRIM)
   6472  1.220   msaitoh 		printf(" - adjust trim\n");
   6473  1.261   msaitoh 	if (sc->bge_phy_flags & BGEPHYF_NO_WIRESPEED)
   6474  1.220   msaitoh 		printf(" - no wirespeed\n");
   6475  1.279   msaitoh 
   6476  1.279   msaitoh 	/* ASF related */
   6477  1.279   msaitoh 	if (sc->bge_asf_mode & ASF_ENABLE)
   6478  1.279   msaitoh 		printf(" - ASF enable\n");
   6479  1.280     enami 	if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE)
   6480  1.279   msaitoh 		printf(" - ASF new handshake\n");
   6481  1.279   msaitoh 	if (sc->bge_asf_mode & ASF_STACKUP)
   6482  1.279   msaitoh 		printf(" - ASF stackup\n");
   6483  1.172   msaitoh }
   6484  1.172   msaitoh #endif /* BGE_DEBUG */
   6485  1.172   msaitoh 
   6486  1.172   msaitoh static int
   6487  1.172   msaitoh bge_get_eaddr_fw(struct bge_softc *sc, uint8_t ether_addr[])
   6488  1.172   msaitoh {
   6489  1.172   msaitoh 	prop_dictionary_t dict;
   6490  1.172   msaitoh 	prop_data_t ea;
   6491  1.172   msaitoh 
   6492  1.261   msaitoh 	if ((sc->bge_flags & BGEF_NO_EEPROM) == 0)
   6493  1.172   msaitoh 		return 1;
   6494  1.172   msaitoh 
   6495  1.172   msaitoh 	dict = device_properties(sc->bge_dev);
   6496  1.172   msaitoh 	ea = prop_dictionary_get(dict, "mac-address");
   6497  1.172   msaitoh 	if (ea != NULL) {
   6498  1.172   msaitoh 		KASSERT(prop_object_type(ea) == PROP_TYPE_DATA);
   6499  1.172   msaitoh 		KASSERT(prop_data_size(ea) == ETHER_ADDR_LEN);
   6500  1.346   msaitoh 		memcpy(ether_addr, prop_data_value(ea), ETHER_ADDR_LEN);
   6501  1.172   msaitoh 		return 0;
   6502  1.172   msaitoh 	}
   6503  1.172   msaitoh 
   6504  1.172   msaitoh 	return 1;
   6505  1.172   msaitoh }
   6506  1.172   msaitoh 
   6507  1.178   msaitoh static int
   6508  1.170   msaitoh bge_get_eaddr_mem(struct bge_softc *sc, uint8_t ether_addr[])
   6509  1.151    cegger {
   6510  1.170   msaitoh 	uint32_t mac_addr;
   6511  1.151    cegger 
   6512  1.205   msaitoh 	mac_addr = bge_readmem_ind(sc, BGE_SRAM_MAC_ADDR_HIGH_MB);
   6513  1.151    cegger 	if ((mac_addr >> 16) == 0x484b) {
   6514  1.151    cegger 		ether_addr[0] = (uint8_t)(mac_addr >> 8);
   6515  1.151    cegger 		ether_addr[1] = (uint8_t)mac_addr;
   6516  1.205   msaitoh 		mac_addr = bge_readmem_ind(sc, BGE_SRAM_MAC_ADDR_LOW_MB);
   6517  1.151    cegger 		ether_addr[2] = (uint8_t)(mac_addr >> 24);
   6518  1.151    cegger 		ether_addr[3] = (uint8_t)(mac_addr >> 16);
   6519  1.151    cegger 		ether_addr[4] = (uint8_t)(mac_addr >> 8);
   6520  1.151    cegger 		ether_addr[5] = (uint8_t)mac_addr;
   6521  1.170   msaitoh 		return 0;
   6522  1.151    cegger 	}
   6523  1.170   msaitoh 	return 1;
   6524  1.151    cegger }
   6525  1.151    cegger 
   6526  1.151    cegger static int
   6527  1.170   msaitoh bge_get_eaddr_nvram(struct bge_softc *sc, uint8_t ether_addr[])
   6528  1.151    cegger {
   6529  1.151    cegger 	int mac_offset = BGE_EE_MAC_OFFSET;
   6530  1.151    cegger 
   6531  1.177   msaitoh 	if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906)
   6532  1.151    cegger 		mac_offset = BGE_EE_MAC_OFFSET_5906;
   6533  1.151    cegger 
   6534  1.151    cegger 	return (bge_read_nvram(sc, ether_addr, mac_offset + 2,
   6535  1.151    cegger 	    ETHER_ADDR_LEN));
   6536  1.151    cegger }
   6537  1.151    cegger 
   6538  1.151    cegger static int
   6539  1.170   msaitoh bge_get_eaddr_eeprom(struct bge_softc *sc, uint8_t ether_addr[])
   6540  1.151    cegger {
   6541  1.151    cegger 
   6542  1.170   msaitoh 	if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906)
   6543  1.170   msaitoh 		return 1;
   6544  1.151    cegger 
   6545  1.151    cegger 	return (bge_read_eeprom(sc, ether_addr, BGE_EE_MAC_OFFSET + 2,
   6546  1.151    cegger 	   ETHER_ADDR_LEN));
   6547  1.151    cegger }
   6548  1.151    cegger 
   6549  1.151    cegger static int
   6550  1.170   msaitoh bge_get_eaddr(struct bge_softc *sc, uint8_t eaddr[])
   6551  1.151    cegger {
   6552  1.151    cegger 	static const bge_eaddr_fcn_t bge_eaddr_funcs[] = {
   6553  1.151    cegger 		/* NOTE: Order is critical */
   6554  1.172   msaitoh 		bge_get_eaddr_fw,
   6555  1.151    cegger 		bge_get_eaddr_mem,
   6556  1.151    cegger 		bge_get_eaddr_nvram,
   6557  1.151    cegger 		bge_get_eaddr_eeprom,
   6558  1.151    cegger 		NULL
   6559  1.151    cegger 	};
   6560  1.151    cegger 	const bge_eaddr_fcn_t *func;
   6561  1.151    cegger 
   6562  1.151    cegger 	for (func = bge_eaddr_funcs; *func != NULL; ++func) {
   6563  1.151    cegger 		if ((*func)(sc, eaddr) == 0)
   6564  1.151    cegger 			break;
   6565  1.151    cegger 	}
   6566  1.362     skrll 	return *func == NULL ? ENXIO : 0;
   6567  1.151    cegger }
   6568