if_bge.c revision 1.48 1 1.48 hannken /* $NetBSD: if_bge.c,v 1.48 2003/08/26 10:17:02 hannken Exp $ */
2 1.8 thorpej
3 1.1 fvdl /*
4 1.1 fvdl * Copyright (c) 2001 Wind River Systems
5 1.1 fvdl * Copyright (c) 1997, 1998, 1999, 2001
6 1.1 fvdl * Bill Paul <wpaul (at) windriver.com>. All rights reserved.
7 1.1 fvdl *
8 1.1 fvdl * Redistribution and use in source and binary forms, with or without
9 1.1 fvdl * modification, are permitted provided that the following conditions
10 1.1 fvdl * are met:
11 1.1 fvdl * 1. Redistributions of source code must retain the above copyright
12 1.1 fvdl * notice, this list of conditions and the following disclaimer.
13 1.1 fvdl * 2. Redistributions in binary form must reproduce the above copyright
14 1.1 fvdl * notice, this list of conditions and the following disclaimer in the
15 1.1 fvdl * documentation and/or other materials provided with the distribution.
16 1.1 fvdl * 3. All advertising materials mentioning features or use of this software
17 1.1 fvdl * must display the following acknowledgement:
18 1.1 fvdl * This product includes software developed by Bill Paul.
19 1.1 fvdl * 4. Neither the name of the author nor the names of any co-contributors
20 1.1 fvdl * may be used to endorse or promote products derived from this software
21 1.1 fvdl * without specific prior written permission.
22 1.1 fvdl *
23 1.1 fvdl * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
24 1.1 fvdl * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
25 1.1 fvdl * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
26 1.1 fvdl * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
27 1.1 fvdl * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
28 1.1 fvdl * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
29 1.1 fvdl * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
30 1.1 fvdl * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
31 1.1 fvdl * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
32 1.1 fvdl * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
33 1.1 fvdl * THE POSSIBILITY OF SUCH DAMAGE.
34 1.1 fvdl *
35 1.1 fvdl * $FreeBSD: if_bge.c,v 1.13 2002/04/04 06:01:31 wpaul Exp $
36 1.1 fvdl */
37 1.1 fvdl
38 1.1 fvdl /*
39 1.12 thorpej * Broadcom BCM570x family gigabit ethernet driver for NetBSD.
40 1.1 fvdl *
41 1.12 thorpej * NetBSD version by:
42 1.12 thorpej *
43 1.12 thorpej * Frank van der Linden <fvdl (at) wasabisystems.com>
44 1.12 thorpej * Jason Thorpe <thorpej (at) wasabisystems.com>
45 1.32 tron * Jonathan Stone <jonathan (at) dsg.stanford.edu>
46 1.12 thorpej *
47 1.12 thorpej * Originally written for FreeBSD by Bill Paul <wpaul (at) windriver.com>
48 1.1 fvdl * Senior Engineer, Wind River Systems
49 1.1 fvdl */
50 1.1 fvdl
51 1.1 fvdl /*
52 1.1 fvdl * The Broadcom BCM5700 is based on technology originally developed by
53 1.1 fvdl * Alteon Networks as part of the Tigon I and Tigon II gigabit ethernet
54 1.1 fvdl * MAC chips. The BCM5700, sometimes refered to as the Tigon III, has
55 1.1 fvdl * two on-board MIPS R4000 CPUs and can have as much as 16MB of external
56 1.1 fvdl * SSRAM. The BCM5700 supports TCP, UDP and IP checksum offload, jumbo
57 1.1 fvdl * frames, highly configurable RX filtering, and 16 RX and TX queues
58 1.1 fvdl * (which, along with RX filter rules, can be used for QOS applications).
59 1.1 fvdl * Other features, such as TCP segmentation, may be available as part
60 1.1 fvdl * of value-added firmware updates. Unlike the Tigon I and Tigon II,
61 1.1 fvdl * firmware images can be stored in hardware and need not be compiled
62 1.1 fvdl * into the driver.
63 1.1 fvdl *
64 1.1 fvdl * The BCM5700 supports the PCI v2.2 and PCI-X v1.0 standards, and will
65 1.33 tsutsui * function in a 32-bit/64-bit 33/66MHz bus, or a 64-bit/133MHz bus.
66 1.1 fvdl *
67 1.1 fvdl * The BCM5701 is a single-chip solution incorporating both the BCM5700
68 1.25 jonathan * MAC and a BCM5401 10/100/1000 PHY. Unlike the BCM5700, the BCM5701
69 1.1 fvdl * does not support external SSRAM.
70 1.1 fvdl *
71 1.1 fvdl * Broadcom also produces a variation of the BCM5700 under the "Altima"
72 1.1 fvdl * brand name, which is functionally similar but lacks PCI-X support.
73 1.1 fvdl *
74 1.1 fvdl * Without external SSRAM, you can only have at most 4 TX rings,
75 1.1 fvdl * and the use of the mini RX ring is disabled. This seems to imply
76 1.1 fvdl * that these features are simply not available on the BCM5701. As a
77 1.1 fvdl * result, this driver does not implement any support for the mini RX
78 1.1 fvdl * ring.
79 1.1 fvdl */
80 1.43 lukem
81 1.43 lukem #include <sys/cdefs.h>
82 1.48 hannken __KERNEL_RCSID(0, "$NetBSD: if_bge.c,v 1.48 2003/08/26 10:17:02 hannken Exp $");
83 1.1 fvdl
84 1.1 fvdl #include "bpfilter.h"
85 1.1 fvdl #include "vlan.h"
86 1.1 fvdl
87 1.1 fvdl #include <sys/param.h>
88 1.1 fvdl #include <sys/systm.h>
89 1.1 fvdl #include <sys/callout.h>
90 1.1 fvdl #include <sys/sockio.h>
91 1.1 fvdl #include <sys/mbuf.h>
92 1.1 fvdl #include <sys/malloc.h>
93 1.1 fvdl #include <sys/kernel.h>
94 1.1 fvdl #include <sys/device.h>
95 1.1 fvdl #include <sys/socket.h>
96 1.1 fvdl
97 1.1 fvdl #include <net/if.h>
98 1.1 fvdl #include <net/if_dl.h>
99 1.1 fvdl #include <net/if_media.h>
100 1.1 fvdl #include <net/if_ether.h>
101 1.1 fvdl
102 1.1 fvdl #ifdef INET
103 1.1 fvdl #include <netinet/in.h>
104 1.1 fvdl #include <netinet/in_systm.h>
105 1.1 fvdl #include <netinet/in_var.h>
106 1.1 fvdl #include <netinet/ip.h>
107 1.1 fvdl #endif
108 1.1 fvdl
109 1.1 fvdl #if NBPFILTER > 0
110 1.1 fvdl #include <net/bpf.h>
111 1.1 fvdl #endif
112 1.1 fvdl
113 1.1 fvdl #include <dev/pci/pcireg.h>
114 1.1 fvdl #include <dev/pci/pcivar.h>
115 1.1 fvdl #include <dev/pci/pcidevs.h>
116 1.1 fvdl
117 1.1 fvdl #include <dev/mii/mii.h>
118 1.1 fvdl #include <dev/mii/miivar.h>
119 1.1 fvdl #include <dev/mii/miidevs.h>
120 1.1 fvdl #include <dev/mii/brgphyreg.h>
121 1.1 fvdl
122 1.1 fvdl #include <dev/pci/if_bgereg.h>
123 1.1 fvdl
124 1.1 fvdl #include <uvm/uvm_extern.h>
125 1.1 fvdl
126 1.46 jonathan #define ETHER_MIN_NOPAD (ETHER_MIN_LEN - ETHER_CRC_LEN) /* i.e., 60 */
127 1.46 jonathan
128 1.1 fvdl int bge_probe(struct device *, struct cfdata *, void *);
129 1.1 fvdl void bge_attach(struct device *, struct device *, void *);
130 1.1 fvdl void bge_release_resources(struct bge_softc *);
131 1.1 fvdl void bge_txeof(struct bge_softc *);
132 1.1 fvdl void bge_rxeof(struct bge_softc *);
133 1.1 fvdl
134 1.1 fvdl void bge_tick(void *);
135 1.1 fvdl void bge_stats_update(struct bge_softc *);
136 1.1 fvdl int bge_encap(struct bge_softc *, struct mbuf *, u_int32_t *);
137 1.46 jonathan static __inline int bge_cksum_pad(struct mbuf *pkt);
138 1.45 jonathan static __inline int bge_compact_dma_runt(struct mbuf *pkt);
139 1.1 fvdl
140 1.1 fvdl int bge_intr(void *);
141 1.1 fvdl void bge_start(struct ifnet *);
142 1.1 fvdl int bge_ioctl(struct ifnet *, u_long, caddr_t);
143 1.1 fvdl int bge_init(struct ifnet *);
144 1.1 fvdl void bge_stop(struct bge_softc *);
145 1.1 fvdl void bge_watchdog(struct ifnet *);
146 1.1 fvdl void bge_shutdown(void *);
147 1.1 fvdl int bge_ifmedia_upd(struct ifnet *);
148 1.1 fvdl void bge_ifmedia_sts(struct ifnet *, struct ifmediareq *);
149 1.1 fvdl
150 1.1 fvdl u_int8_t bge_eeprom_getbyte(struct bge_softc *, int, u_int8_t *);
151 1.1 fvdl int bge_read_eeprom(struct bge_softc *, caddr_t, int, int);
152 1.1 fvdl
153 1.1 fvdl void bge_setmulti(struct bge_softc *);
154 1.1 fvdl
155 1.1 fvdl void bge_handle_events(struct bge_softc *);
156 1.1 fvdl int bge_alloc_jumbo_mem(struct bge_softc *);
157 1.1 fvdl void bge_free_jumbo_mem(struct bge_softc *);
158 1.1 fvdl void *bge_jalloc(struct bge_softc *);
159 1.31 thorpej void bge_jfree(struct mbuf *, caddr_t, size_t, void *);
160 1.1 fvdl int bge_newbuf_std(struct bge_softc *, int, struct mbuf *, bus_dmamap_t);
161 1.1 fvdl int bge_newbuf_jumbo(struct bge_softc *, int, struct mbuf *);
162 1.1 fvdl int bge_init_rx_ring_std(struct bge_softc *);
163 1.1 fvdl void bge_free_rx_ring_std(struct bge_softc *);
164 1.1 fvdl int bge_init_rx_ring_jumbo(struct bge_softc *);
165 1.1 fvdl void bge_free_rx_ring_jumbo(struct bge_softc *);
166 1.1 fvdl void bge_free_tx_ring(struct bge_softc *);
167 1.1 fvdl int bge_init_tx_ring(struct bge_softc *);
168 1.1 fvdl
169 1.1 fvdl int bge_chipinit(struct bge_softc *);
170 1.1 fvdl int bge_blockinit(struct bge_softc *);
171 1.25 jonathan int bge_setpowerstate(struct bge_softc *, int);
172 1.1 fvdl
173 1.1 fvdl #ifdef notdef
174 1.1 fvdl u_int8_t bge_vpd_readbyte(struct bge_softc *, int);
175 1.1 fvdl void bge_vpd_read_res(struct bge_softc *, struct vpd_res *, int);
176 1.1 fvdl void bge_vpd_read(struct bge_softc *);
177 1.1 fvdl #endif
178 1.1 fvdl
179 1.1 fvdl u_int32_t bge_readmem_ind(struct bge_softc *, int);
180 1.1 fvdl void bge_writemem_ind(struct bge_softc *, int, int);
181 1.1 fvdl #ifdef notdef
182 1.1 fvdl u_int32_t bge_readreg_ind(struct bge_softc *, int);
183 1.1 fvdl #endif
184 1.1 fvdl void bge_writereg_ind(struct bge_softc *, int, int);
185 1.1 fvdl
186 1.1 fvdl int bge_miibus_readreg(struct device *, int, int);
187 1.1 fvdl void bge_miibus_writereg(struct device *, int, int, int);
188 1.1 fvdl void bge_miibus_statchg(struct device *);
189 1.1 fvdl
190 1.1 fvdl void bge_reset(struct bge_softc *);
191 1.1 fvdl
192 1.1 fvdl void bge_dump_status(struct bge_softc *);
193 1.1 fvdl void bge_dump_rxbd(struct bge_rx_bd *);
194 1.1 fvdl
195 1.1 fvdl #define BGE_DEBUG
196 1.1 fvdl #ifdef BGE_DEBUG
197 1.1 fvdl #define DPRINTF(x) if (bgedebug) printf x
198 1.1 fvdl #define DPRINTFN(n,x) if (bgedebug >= (n)) printf x
199 1.1 fvdl int bgedebug = 0;
200 1.1 fvdl #else
201 1.1 fvdl #define DPRINTF(x)
202 1.1 fvdl #define DPRINTFN(n,x)
203 1.1 fvdl #endif
204 1.1 fvdl
205 1.17 thorpej /* Various chip quirks. */
206 1.17 thorpej #define BGE_QUIRK_LINK_STATE_BROKEN 0x00000001
207 1.18 thorpej #define BGE_QUIRK_CSUM_BROKEN 0x00000002
208 1.24 matt #define BGE_QUIRK_ONLY_PHY_1 0x00000004
209 1.25 jonathan #define BGE_QUIRK_5700_SMALLDMA 0x00000008
210 1.25 jonathan #define BGE_QUIRK_5700_PCIX_REG_BUG 0x00000010
211 1.36 jonathan #define BGE_QUIRK_PRODUCER_BUG 0x00000020
212 1.37 jonathan #define BGE_QUIRK_PCIX_DMA_ALIGN_BUG 0x00000040
213 1.44 hannken #define BGE_QUIRK_5705_CORE 0x00000080
214 1.25 jonathan
215 1.25 jonathan /* following bugs are common to bcm5700 rev B, all flavours */
216 1.25 jonathan #define BGE_QUIRK_5700_COMMON \
217 1.25 jonathan (BGE_QUIRK_5700_SMALLDMA|BGE_QUIRK_PRODUCER_BUG)
218 1.17 thorpej
219 1.21 thorpej CFATTACH_DECL(bge, sizeof(struct bge_softc),
220 1.22 thorpej bge_probe, bge_attach, NULL, NULL);
221 1.1 fvdl
222 1.1 fvdl u_int32_t
223 1.1 fvdl bge_readmem_ind(sc, off)
224 1.1 fvdl struct bge_softc *sc;
225 1.1 fvdl int off;
226 1.1 fvdl {
227 1.1 fvdl struct pci_attach_args *pa = &(sc->bge_pa);
228 1.1 fvdl pcireg_t val;
229 1.1 fvdl
230 1.1 fvdl pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_MEMWIN_BASEADDR, off);
231 1.1 fvdl val = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_MEMWIN_DATA);
232 1.1 fvdl return val;
233 1.1 fvdl }
234 1.1 fvdl
235 1.1 fvdl void
236 1.1 fvdl bge_writemem_ind(sc, off, val)
237 1.1 fvdl struct bge_softc *sc;
238 1.1 fvdl int off, val;
239 1.1 fvdl {
240 1.1 fvdl struct pci_attach_args *pa = &(sc->bge_pa);
241 1.1 fvdl
242 1.1 fvdl pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_MEMWIN_BASEADDR, off);
243 1.1 fvdl pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_MEMWIN_DATA, val);
244 1.1 fvdl }
245 1.1 fvdl
246 1.1 fvdl #ifdef notdef
247 1.1 fvdl u_int32_t
248 1.1 fvdl bge_readreg_ind(sc, off)
249 1.1 fvdl struct bge_softc *sc;
250 1.1 fvdl int off;
251 1.1 fvdl {
252 1.1 fvdl struct pci_attach_args *pa = &(sc->bge_pa);
253 1.1 fvdl
254 1.1 fvdl pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_REG_BASEADDR, off);
255 1.1 fvdl return(pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_REG_DATA));
256 1.1 fvdl }
257 1.1 fvdl #endif
258 1.1 fvdl
259 1.1 fvdl void
260 1.1 fvdl bge_writereg_ind(sc, off, val)
261 1.1 fvdl struct bge_softc *sc;
262 1.1 fvdl int off, val;
263 1.1 fvdl {
264 1.1 fvdl struct pci_attach_args *pa = &(sc->bge_pa);
265 1.1 fvdl
266 1.1 fvdl pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_REG_BASEADDR, off);
267 1.1 fvdl pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_REG_DATA, val);
268 1.1 fvdl }
269 1.1 fvdl
270 1.1 fvdl #ifdef notdef
271 1.1 fvdl u_int8_t
272 1.1 fvdl bge_vpd_readbyte(sc, addr)
273 1.1 fvdl struct bge_softc *sc;
274 1.1 fvdl int addr;
275 1.1 fvdl {
276 1.1 fvdl int i;
277 1.1 fvdl u_int32_t val;
278 1.1 fvdl struct pci_attach_args *pa = &(sc->bge_pa);
279 1.1 fvdl
280 1.1 fvdl pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_VPD_ADDR, addr);
281 1.1 fvdl for (i = 0; i < BGE_TIMEOUT * 10; i++) {
282 1.1 fvdl DELAY(10);
283 1.1 fvdl if (pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_VPD_ADDR) &
284 1.1 fvdl BGE_VPD_FLAG)
285 1.1 fvdl break;
286 1.1 fvdl }
287 1.1 fvdl
288 1.1 fvdl if (i == BGE_TIMEOUT) {
289 1.1 fvdl printf("%s: VPD read timed out\n", sc->bge_dev.dv_xname);
290 1.1 fvdl return(0);
291 1.1 fvdl }
292 1.1 fvdl
293 1.1 fvdl val = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_VPD_DATA);
294 1.1 fvdl
295 1.1 fvdl return((val >> ((addr % 4) * 8)) & 0xFF);
296 1.1 fvdl }
297 1.1 fvdl
298 1.1 fvdl void
299 1.1 fvdl bge_vpd_read_res(sc, res, addr)
300 1.1 fvdl struct bge_softc *sc;
301 1.1 fvdl struct vpd_res *res;
302 1.1 fvdl int addr;
303 1.1 fvdl {
304 1.1 fvdl int i;
305 1.1 fvdl u_int8_t *ptr;
306 1.1 fvdl
307 1.1 fvdl ptr = (u_int8_t *)res;
308 1.1 fvdl for (i = 0; i < sizeof(struct vpd_res); i++)
309 1.1 fvdl ptr[i] = bge_vpd_readbyte(sc, i + addr);
310 1.1 fvdl }
311 1.1 fvdl
312 1.1 fvdl void
313 1.1 fvdl bge_vpd_read(sc)
314 1.1 fvdl struct bge_softc *sc;
315 1.1 fvdl {
316 1.1 fvdl int pos = 0, i;
317 1.1 fvdl struct vpd_res res;
318 1.1 fvdl
319 1.1 fvdl if (sc->bge_vpd_prodname != NULL)
320 1.1 fvdl free(sc->bge_vpd_prodname, M_DEVBUF);
321 1.1 fvdl if (sc->bge_vpd_readonly != NULL)
322 1.1 fvdl free(sc->bge_vpd_readonly, M_DEVBUF);
323 1.1 fvdl sc->bge_vpd_prodname = NULL;
324 1.1 fvdl sc->bge_vpd_readonly = NULL;
325 1.1 fvdl
326 1.1 fvdl bge_vpd_read_res(sc, &res, pos);
327 1.1 fvdl
328 1.1 fvdl if (res.vr_id != VPD_RES_ID) {
329 1.1 fvdl printf("%s: bad VPD resource id: expected %x got %x\n",
330 1.1 fvdl sc->bge_dev.dv_xname, VPD_RES_ID, res.vr_id);
331 1.1 fvdl return;
332 1.1 fvdl }
333 1.1 fvdl
334 1.1 fvdl pos += sizeof(res);
335 1.1 fvdl sc->bge_vpd_prodname = malloc(res.vr_len + 1, M_DEVBUF, M_NOWAIT);
336 1.1 fvdl if (sc->bge_vpd_prodname == NULL)
337 1.1 fvdl panic("bge_vpd_read");
338 1.1 fvdl for (i = 0; i < res.vr_len; i++)
339 1.1 fvdl sc->bge_vpd_prodname[i] = bge_vpd_readbyte(sc, i + pos);
340 1.1 fvdl sc->bge_vpd_prodname[i] = '\0';
341 1.1 fvdl pos += i;
342 1.1 fvdl
343 1.1 fvdl bge_vpd_read_res(sc, &res, pos);
344 1.1 fvdl
345 1.1 fvdl if (res.vr_id != VPD_RES_READ) {
346 1.1 fvdl printf("%s: bad VPD resource id: expected %x got %x\n",
347 1.1 fvdl sc->bge_dev.dv_xname, VPD_RES_READ, res.vr_id);
348 1.1 fvdl return;
349 1.1 fvdl }
350 1.1 fvdl
351 1.1 fvdl pos += sizeof(res);
352 1.1 fvdl sc->bge_vpd_readonly = malloc(res.vr_len, M_DEVBUF, M_NOWAIT);
353 1.1 fvdl if (sc->bge_vpd_readonly == NULL)
354 1.1 fvdl panic("bge_vpd_read");
355 1.1 fvdl for (i = 0; i < res.vr_len + 1; i++)
356 1.1 fvdl sc->bge_vpd_readonly[i] = bge_vpd_readbyte(sc, i + pos);
357 1.1 fvdl }
358 1.1 fvdl #endif
359 1.1 fvdl
360 1.1 fvdl /*
361 1.1 fvdl * Read a byte of data stored in the EEPROM at address 'addr.' The
362 1.1 fvdl * BCM570x supports both the traditional bitbang interface and an
363 1.1 fvdl * auto access interface for reading the EEPROM. We use the auto
364 1.1 fvdl * access method.
365 1.1 fvdl */
366 1.1 fvdl u_int8_t
367 1.1 fvdl bge_eeprom_getbyte(sc, addr, dest)
368 1.1 fvdl struct bge_softc *sc;
369 1.1 fvdl int addr;
370 1.1 fvdl u_int8_t *dest;
371 1.1 fvdl {
372 1.1 fvdl int i;
373 1.1 fvdl u_int32_t byte = 0;
374 1.1 fvdl
375 1.1 fvdl /*
376 1.1 fvdl * Enable use of auto EEPROM access so we can avoid
377 1.1 fvdl * having to use the bitbang method.
378 1.1 fvdl */
379 1.1 fvdl BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM);
380 1.1 fvdl
381 1.1 fvdl /* Reset the EEPROM, load the clock period. */
382 1.1 fvdl CSR_WRITE_4(sc, BGE_EE_ADDR,
383 1.1 fvdl BGE_EEADDR_RESET|BGE_EEHALFCLK(BGE_HALFCLK_384SCL));
384 1.1 fvdl DELAY(20);
385 1.1 fvdl
386 1.1 fvdl /* Issue the read EEPROM command. */
387 1.1 fvdl CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr);
388 1.1 fvdl
389 1.1 fvdl /* Wait for completion */
390 1.1 fvdl for(i = 0; i < BGE_TIMEOUT * 10; i++) {
391 1.1 fvdl DELAY(10);
392 1.1 fvdl if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE)
393 1.1 fvdl break;
394 1.1 fvdl }
395 1.1 fvdl
396 1.1 fvdl if (i == BGE_TIMEOUT) {
397 1.1 fvdl printf("%s: eeprom read timed out\n", sc->bge_dev.dv_xname);
398 1.1 fvdl return(0);
399 1.1 fvdl }
400 1.1 fvdl
401 1.1 fvdl /* Get result. */
402 1.1 fvdl byte = CSR_READ_4(sc, BGE_EE_DATA);
403 1.1 fvdl
404 1.1 fvdl *dest = (byte >> ((addr % 4) * 8)) & 0xFF;
405 1.1 fvdl
406 1.1 fvdl return(0);
407 1.1 fvdl }
408 1.1 fvdl
409 1.1 fvdl /*
410 1.1 fvdl * Read a sequence of bytes from the EEPROM.
411 1.1 fvdl */
412 1.1 fvdl int
413 1.1 fvdl bge_read_eeprom(sc, dest, off, cnt)
414 1.1 fvdl struct bge_softc *sc;
415 1.1 fvdl caddr_t dest;
416 1.1 fvdl int off;
417 1.1 fvdl int cnt;
418 1.1 fvdl {
419 1.1 fvdl int err = 0, i;
420 1.1 fvdl u_int8_t byte = 0;
421 1.1 fvdl
422 1.1 fvdl for (i = 0; i < cnt; i++) {
423 1.1 fvdl err = bge_eeprom_getbyte(sc, off + i, &byte);
424 1.1 fvdl if (err)
425 1.1 fvdl break;
426 1.1 fvdl *(dest + i) = byte;
427 1.1 fvdl }
428 1.1 fvdl
429 1.1 fvdl return(err ? 1 : 0);
430 1.1 fvdl }
431 1.1 fvdl
432 1.1 fvdl int
433 1.1 fvdl bge_miibus_readreg(dev, phy, reg)
434 1.1 fvdl struct device *dev;
435 1.1 fvdl int phy, reg;
436 1.1 fvdl {
437 1.1 fvdl struct bge_softc *sc = (struct bge_softc *)dev;
438 1.1 fvdl struct ifnet *ifp;
439 1.1 fvdl u_int32_t val;
440 1.25 jonathan u_int32_t saved_autopoll;
441 1.1 fvdl int i;
442 1.1 fvdl
443 1.1 fvdl ifp = &sc->ethercom.ec_if;
444 1.1 fvdl
445 1.25 jonathan /*
446 1.25 jonathan * Several chips with builtin PHYs will incorrectly answer to
447 1.25 jonathan * other PHY instances than the builtin PHY at id 1.
448 1.25 jonathan */
449 1.24 matt if (phy != 1 && (sc->bge_quirks & BGE_QUIRK_ONLY_PHY_1))
450 1.1 fvdl return(0);
451 1.1 fvdl
452 1.25 jonathan /* Reading with autopolling on may trigger PCI errors */
453 1.25 jonathan saved_autopoll = CSR_READ_4(sc, BGE_MI_MODE);
454 1.25 jonathan if (saved_autopoll & BGE_MIMODE_AUTOPOLL) {
455 1.25 jonathan CSR_WRITE_4(sc, BGE_MI_MODE,
456 1.29 itojun saved_autopoll &~ BGE_MIMODE_AUTOPOLL);
457 1.25 jonathan DELAY(40);
458 1.25 jonathan }
459 1.25 jonathan
460 1.1 fvdl CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_READ|BGE_MICOMM_BUSY|
461 1.1 fvdl BGE_MIPHY(phy)|BGE_MIREG(reg));
462 1.1 fvdl
463 1.1 fvdl for (i = 0; i < BGE_TIMEOUT; i++) {
464 1.1 fvdl val = CSR_READ_4(sc, BGE_MI_COMM);
465 1.1 fvdl if (!(val & BGE_MICOMM_BUSY))
466 1.1 fvdl break;
467 1.9 thorpej delay(10);
468 1.1 fvdl }
469 1.1 fvdl
470 1.1 fvdl if (i == BGE_TIMEOUT) {
471 1.1 fvdl printf("%s: PHY read timed out\n", sc->bge_dev.dv_xname);
472 1.29 itojun val = 0;
473 1.25 jonathan goto done;
474 1.1 fvdl }
475 1.1 fvdl
476 1.1 fvdl val = CSR_READ_4(sc, BGE_MI_COMM);
477 1.1 fvdl
478 1.25 jonathan done:
479 1.25 jonathan if (saved_autopoll & BGE_MIMODE_AUTOPOLL) {
480 1.25 jonathan CSR_WRITE_4(sc, BGE_MI_MODE, saved_autopoll);
481 1.25 jonathan DELAY(40);
482 1.25 jonathan }
483 1.29 itojun
484 1.1 fvdl if (val & BGE_MICOMM_READFAIL)
485 1.1 fvdl return(0);
486 1.1 fvdl
487 1.1 fvdl return(val & 0xFFFF);
488 1.1 fvdl }
489 1.1 fvdl
490 1.1 fvdl void
491 1.1 fvdl bge_miibus_writereg(dev, phy, reg, val)
492 1.1 fvdl struct device *dev;
493 1.1 fvdl int phy, reg, val;
494 1.1 fvdl {
495 1.1 fvdl struct bge_softc *sc = (struct bge_softc *)dev;
496 1.29 itojun u_int32_t saved_autopoll;
497 1.29 itojun int i;
498 1.1 fvdl
499 1.29 itojun /* Touching the PHY while autopolling is on may trigger PCI errors */
500 1.25 jonathan saved_autopoll = CSR_READ_4(sc, BGE_MI_MODE);
501 1.25 jonathan if (saved_autopoll & BGE_MIMODE_AUTOPOLL) {
502 1.25 jonathan delay(40);
503 1.25 jonathan CSR_WRITE_4(sc, BGE_MI_MODE,
504 1.25 jonathan saved_autopoll & (~BGE_MIMODE_AUTOPOLL));
505 1.25 jonathan delay(10); /* 40 usec is supposed to be adequate */
506 1.25 jonathan }
507 1.29 itojun
508 1.1 fvdl CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_WRITE|BGE_MICOMM_BUSY|
509 1.1 fvdl BGE_MIPHY(phy)|BGE_MIREG(reg)|val);
510 1.1 fvdl
511 1.1 fvdl for (i = 0; i < BGE_TIMEOUT; i++) {
512 1.1 fvdl if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY))
513 1.1 fvdl break;
514 1.9 thorpej delay(10);
515 1.1 fvdl }
516 1.1 fvdl
517 1.25 jonathan if (saved_autopoll & BGE_MIMODE_AUTOPOLL) {
518 1.25 jonathan CSR_WRITE_4(sc, BGE_MI_MODE, saved_autopoll);
519 1.25 jonathan delay(40);
520 1.25 jonathan }
521 1.29 itojun
522 1.1 fvdl if (i == BGE_TIMEOUT) {
523 1.1 fvdl printf("%s: PHY read timed out\n", sc->bge_dev.dv_xname);
524 1.1 fvdl }
525 1.1 fvdl }
526 1.1 fvdl
527 1.1 fvdl void
528 1.1 fvdl bge_miibus_statchg(dev)
529 1.1 fvdl struct device *dev;
530 1.1 fvdl {
531 1.1 fvdl struct bge_softc *sc = (struct bge_softc *)dev;
532 1.1 fvdl struct mii_data *mii = &sc->bge_mii;
533 1.1 fvdl
534 1.1 fvdl BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_PORTMODE);
535 1.1 fvdl if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) {
536 1.1 fvdl BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_GMII);
537 1.1 fvdl } else {
538 1.1 fvdl BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_MII);
539 1.1 fvdl }
540 1.1 fvdl
541 1.1 fvdl if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
542 1.1 fvdl BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX);
543 1.1 fvdl } else {
544 1.1 fvdl BGE_SETBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX);
545 1.1 fvdl }
546 1.1 fvdl }
547 1.1 fvdl
548 1.1 fvdl /*
549 1.1 fvdl * Handle events that have triggered interrupts.
550 1.1 fvdl */
551 1.1 fvdl void
552 1.1 fvdl bge_handle_events(sc)
553 1.1 fvdl struct bge_softc *sc;
554 1.1 fvdl {
555 1.1 fvdl
556 1.1 fvdl return;
557 1.1 fvdl }
558 1.1 fvdl
559 1.1 fvdl /*
560 1.1 fvdl * Memory management for jumbo frames.
561 1.1 fvdl */
562 1.1 fvdl
563 1.1 fvdl int
564 1.1 fvdl bge_alloc_jumbo_mem(sc)
565 1.1 fvdl struct bge_softc *sc;
566 1.1 fvdl {
567 1.1 fvdl caddr_t ptr, kva;
568 1.1 fvdl bus_dma_segment_t seg;
569 1.1 fvdl int i, rseg, state, error;
570 1.1 fvdl struct bge_jpool_entry *entry;
571 1.1 fvdl
572 1.1 fvdl state = error = 0;
573 1.1 fvdl
574 1.1 fvdl /* Grab a big chunk o' storage. */
575 1.1 fvdl if (bus_dmamem_alloc(sc->bge_dmatag, BGE_JMEM, PAGE_SIZE, 0,
576 1.1 fvdl &seg, 1, &rseg, BUS_DMA_NOWAIT)) {
577 1.1 fvdl printf("%s: can't alloc rx buffers\n", sc->bge_dev.dv_xname);
578 1.1 fvdl return ENOBUFS;
579 1.1 fvdl }
580 1.1 fvdl
581 1.1 fvdl state = 1;
582 1.1 fvdl if (bus_dmamem_map(sc->bge_dmatag, &seg, rseg, BGE_JMEM, &kva,
583 1.1 fvdl BUS_DMA_NOWAIT)) {
584 1.39 wiz printf("%s: can't map DMA buffers (%d bytes)\n",
585 1.1 fvdl sc->bge_dev.dv_xname, (int)BGE_JMEM);
586 1.1 fvdl error = ENOBUFS;
587 1.1 fvdl goto out;
588 1.1 fvdl }
589 1.1 fvdl
590 1.1 fvdl state = 2;
591 1.1 fvdl if (bus_dmamap_create(sc->bge_dmatag, BGE_JMEM, 1, BGE_JMEM, 0,
592 1.1 fvdl BUS_DMA_NOWAIT, &sc->bge_cdata.bge_rx_jumbo_map)) {
593 1.39 wiz printf("%s: can't create DMA map\n", sc->bge_dev.dv_xname);
594 1.1 fvdl error = ENOBUFS;
595 1.1 fvdl goto out;
596 1.1 fvdl }
597 1.1 fvdl
598 1.1 fvdl state = 3;
599 1.1 fvdl if (bus_dmamap_load(sc->bge_dmatag, sc->bge_cdata.bge_rx_jumbo_map,
600 1.1 fvdl kva, BGE_JMEM, NULL, BUS_DMA_NOWAIT)) {
601 1.39 wiz printf("%s: can't load DMA map\n", sc->bge_dev.dv_xname);
602 1.1 fvdl error = ENOBUFS;
603 1.1 fvdl goto out;
604 1.1 fvdl }
605 1.1 fvdl
606 1.1 fvdl state = 4;
607 1.1 fvdl sc->bge_cdata.bge_jumbo_buf = (caddr_t)kva;
608 1.1 fvdl DPRINTFN(1,("bge_jumbo_buf = 0x%p\n", sc->bge_cdata.bge_jumbo_buf));
609 1.1 fvdl
610 1.1 fvdl SLIST_INIT(&sc->bge_jfree_listhead);
611 1.1 fvdl SLIST_INIT(&sc->bge_jinuse_listhead);
612 1.1 fvdl
613 1.1 fvdl /*
614 1.1 fvdl * Now divide it up into 9K pieces and save the addresses
615 1.1 fvdl * in an array.
616 1.1 fvdl */
617 1.1 fvdl ptr = sc->bge_cdata.bge_jumbo_buf;
618 1.1 fvdl for (i = 0; i < BGE_JSLOTS; i++) {
619 1.1 fvdl sc->bge_cdata.bge_jslots[i] = ptr;
620 1.1 fvdl ptr += BGE_JLEN;
621 1.1 fvdl entry = malloc(sizeof(struct bge_jpool_entry),
622 1.1 fvdl M_DEVBUF, M_NOWAIT);
623 1.1 fvdl if (entry == NULL) {
624 1.1 fvdl printf("%s: no memory for jumbo buffer queue!\n",
625 1.1 fvdl sc->bge_dev.dv_xname);
626 1.1 fvdl error = ENOBUFS;
627 1.1 fvdl goto out;
628 1.1 fvdl }
629 1.1 fvdl entry->slot = i;
630 1.1 fvdl SLIST_INSERT_HEAD(&sc->bge_jfree_listhead,
631 1.1 fvdl entry, jpool_entries);
632 1.1 fvdl }
633 1.1 fvdl out:
634 1.1 fvdl if (error != 0) {
635 1.1 fvdl switch (state) {
636 1.1 fvdl case 4:
637 1.1 fvdl bus_dmamap_unload(sc->bge_dmatag,
638 1.1 fvdl sc->bge_cdata.bge_rx_jumbo_map);
639 1.1 fvdl case 3:
640 1.1 fvdl bus_dmamap_destroy(sc->bge_dmatag,
641 1.1 fvdl sc->bge_cdata.bge_rx_jumbo_map);
642 1.1 fvdl case 2:
643 1.1 fvdl bus_dmamem_unmap(sc->bge_dmatag, kva, BGE_JMEM);
644 1.1 fvdl case 1:
645 1.1 fvdl bus_dmamem_free(sc->bge_dmatag, &seg, rseg);
646 1.1 fvdl break;
647 1.1 fvdl default:
648 1.1 fvdl break;
649 1.1 fvdl }
650 1.1 fvdl }
651 1.1 fvdl
652 1.1 fvdl return error;
653 1.1 fvdl }
654 1.1 fvdl
655 1.1 fvdl /*
656 1.1 fvdl * Allocate a jumbo buffer.
657 1.1 fvdl */
658 1.1 fvdl void *
659 1.1 fvdl bge_jalloc(sc)
660 1.1 fvdl struct bge_softc *sc;
661 1.1 fvdl {
662 1.1 fvdl struct bge_jpool_entry *entry;
663 1.1 fvdl
664 1.1 fvdl entry = SLIST_FIRST(&sc->bge_jfree_listhead);
665 1.1 fvdl
666 1.1 fvdl if (entry == NULL) {
667 1.1 fvdl printf("%s: no free jumbo buffers\n", sc->bge_dev.dv_xname);
668 1.1 fvdl return(NULL);
669 1.1 fvdl }
670 1.1 fvdl
671 1.1 fvdl SLIST_REMOVE_HEAD(&sc->bge_jfree_listhead, jpool_entries);
672 1.1 fvdl SLIST_INSERT_HEAD(&sc->bge_jinuse_listhead, entry, jpool_entries);
673 1.1 fvdl return(sc->bge_cdata.bge_jslots[entry->slot]);
674 1.1 fvdl }
675 1.1 fvdl
676 1.1 fvdl /*
677 1.1 fvdl * Release a jumbo buffer.
678 1.1 fvdl */
679 1.1 fvdl void
680 1.1 fvdl bge_jfree(m, buf, size, arg)
681 1.1 fvdl struct mbuf *m;
682 1.1 fvdl caddr_t buf;
683 1.31 thorpej size_t size;
684 1.1 fvdl void *arg;
685 1.1 fvdl {
686 1.1 fvdl struct bge_jpool_entry *entry;
687 1.1 fvdl struct bge_softc *sc;
688 1.1 fvdl int i, s;
689 1.1 fvdl
690 1.1 fvdl /* Extract the softc struct pointer. */
691 1.1 fvdl sc = (struct bge_softc *)arg;
692 1.1 fvdl
693 1.1 fvdl if (sc == NULL)
694 1.1 fvdl panic("bge_jfree: can't find softc pointer!");
695 1.1 fvdl
696 1.1 fvdl /* calculate the slot this buffer belongs to */
697 1.1 fvdl
698 1.1 fvdl i = ((caddr_t)buf
699 1.1 fvdl - (caddr_t)sc->bge_cdata.bge_jumbo_buf) / BGE_JLEN;
700 1.1 fvdl
701 1.1 fvdl if ((i < 0) || (i >= BGE_JSLOTS))
702 1.1 fvdl panic("bge_jfree: asked to free buffer that we don't manage!");
703 1.1 fvdl
704 1.1 fvdl s = splvm();
705 1.1 fvdl entry = SLIST_FIRST(&sc->bge_jinuse_listhead);
706 1.1 fvdl if (entry == NULL)
707 1.1 fvdl panic("bge_jfree: buffer not in use!");
708 1.1 fvdl entry->slot = i;
709 1.1 fvdl SLIST_REMOVE_HEAD(&sc->bge_jinuse_listhead, jpool_entries);
710 1.1 fvdl SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, entry, jpool_entries);
711 1.1 fvdl
712 1.1 fvdl if (__predict_true(m != NULL))
713 1.1 fvdl pool_cache_put(&mbpool_cache, m);
714 1.1 fvdl splx(s);
715 1.1 fvdl }
716 1.1 fvdl
717 1.1 fvdl
718 1.1 fvdl /*
719 1.1 fvdl * Intialize a standard receive ring descriptor.
720 1.1 fvdl */
721 1.1 fvdl int
722 1.1 fvdl bge_newbuf_std(sc, i, m, dmamap)
723 1.1 fvdl struct bge_softc *sc;
724 1.1 fvdl int i;
725 1.1 fvdl struct mbuf *m;
726 1.1 fvdl bus_dmamap_t dmamap;
727 1.1 fvdl {
728 1.1 fvdl struct mbuf *m_new = NULL;
729 1.1 fvdl struct bge_rx_bd *r;
730 1.1 fvdl int error;
731 1.1 fvdl
732 1.1 fvdl if (dmamap == NULL) {
733 1.1 fvdl error = bus_dmamap_create(sc->bge_dmatag, MCLBYTES, 1,
734 1.1 fvdl MCLBYTES, 0, BUS_DMA_NOWAIT, &dmamap);
735 1.1 fvdl if (error != 0)
736 1.1 fvdl return error;
737 1.1 fvdl }
738 1.1 fvdl
739 1.1 fvdl sc->bge_cdata.bge_rx_std_map[i] = dmamap;
740 1.1 fvdl
741 1.1 fvdl if (m == NULL) {
742 1.1 fvdl MGETHDR(m_new, M_DONTWAIT, MT_DATA);
743 1.1 fvdl if (m_new == NULL) {
744 1.1 fvdl return(ENOBUFS);
745 1.1 fvdl }
746 1.1 fvdl
747 1.1 fvdl MCLGET(m_new, M_DONTWAIT);
748 1.1 fvdl if (!(m_new->m_flags & M_EXT)) {
749 1.1 fvdl m_freem(m_new);
750 1.1 fvdl return(ENOBUFS);
751 1.1 fvdl }
752 1.1 fvdl m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
753 1.37 jonathan if (!sc->bge_rx_alignment_bug)
754 1.37 jonathan m_adj(m_new, ETHER_ALIGN);
755 1.1 fvdl
756 1.1 fvdl if (bus_dmamap_load_mbuf(sc->bge_dmatag, dmamap, m_new,
757 1.1 fvdl BUS_DMA_READ|BUS_DMA_NOWAIT))
758 1.1 fvdl return(ENOBUFS);
759 1.1 fvdl } else {
760 1.1 fvdl m_new = m;
761 1.1 fvdl m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
762 1.1 fvdl m_new->m_data = m_new->m_ext.ext_buf;
763 1.37 jonathan if (!sc->bge_rx_alignment_bug)
764 1.37 jonathan m_adj(m_new, ETHER_ALIGN);
765 1.1 fvdl }
766 1.1 fvdl
767 1.1 fvdl sc->bge_cdata.bge_rx_std_chain[i] = m_new;
768 1.1 fvdl r = &sc->bge_rdata->bge_rx_std_ring[i];
769 1.1 fvdl bge_set_hostaddr(&r->bge_addr,
770 1.10 fvdl dmamap->dm_segs[0].ds_addr);
771 1.1 fvdl r->bge_flags = BGE_RXBDFLAG_END;
772 1.1 fvdl r->bge_len = m_new->m_len;
773 1.1 fvdl r->bge_idx = i;
774 1.1 fvdl
775 1.1 fvdl bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map,
776 1.1 fvdl offsetof(struct bge_ring_data, bge_rx_std_ring) +
777 1.1 fvdl i * sizeof (struct bge_rx_bd),
778 1.1 fvdl sizeof (struct bge_rx_bd),
779 1.1 fvdl BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD);
780 1.1 fvdl
781 1.1 fvdl return(0);
782 1.1 fvdl }
783 1.1 fvdl
784 1.1 fvdl /*
785 1.1 fvdl * Initialize a jumbo receive ring descriptor. This allocates
786 1.1 fvdl * a jumbo buffer from the pool managed internally by the driver.
787 1.1 fvdl */
788 1.1 fvdl int
789 1.1 fvdl bge_newbuf_jumbo(sc, i, m)
790 1.1 fvdl struct bge_softc *sc;
791 1.1 fvdl int i;
792 1.1 fvdl struct mbuf *m;
793 1.1 fvdl {
794 1.1 fvdl struct mbuf *m_new = NULL;
795 1.1 fvdl struct bge_rx_bd *r;
796 1.1 fvdl
797 1.1 fvdl if (m == NULL) {
798 1.1 fvdl caddr_t *buf = NULL;
799 1.1 fvdl
800 1.1 fvdl /* Allocate the mbuf. */
801 1.1 fvdl MGETHDR(m_new, M_DONTWAIT, MT_DATA);
802 1.1 fvdl if (m_new == NULL) {
803 1.1 fvdl return(ENOBUFS);
804 1.1 fvdl }
805 1.1 fvdl
806 1.1 fvdl /* Allocate the jumbo buffer */
807 1.1 fvdl buf = bge_jalloc(sc);
808 1.1 fvdl if (buf == NULL) {
809 1.1 fvdl m_freem(m_new);
810 1.1 fvdl printf("%s: jumbo allocation failed "
811 1.1 fvdl "-- packet dropped!\n", sc->bge_dev.dv_xname);
812 1.1 fvdl return(ENOBUFS);
813 1.1 fvdl }
814 1.1 fvdl
815 1.1 fvdl /* Attach the buffer to the mbuf. */
816 1.1 fvdl m_new->m_len = m_new->m_pkthdr.len = BGE_JUMBO_FRAMELEN;
817 1.1 fvdl MEXTADD(m_new, buf, BGE_JUMBO_FRAMELEN, M_DEVBUF,
818 1.1 fvdl bge_jfree, sc);
819 1.1 fvdl } else {
820 1.1 fvdl m_new = m;
821 1.1 fvdl m_new->m_data = m_new->m_ext.ext_buf;
822 1.1 fvdl m_new->m_ext.ext_size = BGE_JUMBO_FRAMELEN;
823 1.1 fvdl }
824 1.1 fvdl
825 1.37 jonathan if (!sc->bge_rx_alignment_bug)
826 1.37 jonathan m_adj(m_new, ETHER_ALIGN);
827 1.1 fvdl /* Set up the descriptor. */
828 1.1 fvdl r = &sc->bge_rdata->bge_rx_jumbo_ring[i];
829 1.1 fvdl sc->bge_cdata.bge_rx_jumbo_chain[i] = m_new;
830 1.1 fvdl bge_set_hostaddr(&r->bge_addr, BGE_JUMBO_DMA_ADDR(sc, m_new));
831 1.1 fvdl r->bge_flags = BGE_RXBDFLAG_END|BGE_RXBDFLAG_JUMBO_RING;
832 1.1 fvdl r->bge_len = m_new->m_len;
833 1.1 fvdl r->bge_idx = i;
834 1.1 fvdl
835 1.1 fvdl bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map,
836 1.1 fvdl offsetof(struct bge_ring_data, bge_rx_jumbo_ring) +
837 1.1 fvdl i * sizeof (struct bge_rx_bd),
838 1.1 fvdl sizeof (struct bge_rx_bd),
839 1.1 fvdl BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD);
840 1.1 fvdl
841 1.1 fvdl return(0);
842 1.1 fvdl }
843 1.1 fvdl
844 1.1 fvdl /*
845 1.1 fvdl * The standard receive ring has 512 entries in it. At 2K per mbuf cluster,
846 1.1 fvdl * that's 1MB or memory, which is a lot. For now, we fill only the first
847 1.1 fvdl * 256 ring entries and hope that our CPU is fast enough to keep up with
848 1.1 fvdl * the NIC.
849 1.1 fvdl */
850 1.1 fvdl int
851 1.1 fvdl bge_init_rx_ring_std(sc)
852 1.1 fvdl struct bge_softc *sc;
853 1.1 fvdl {
854 1.1 fvdl int i;
855 1.1 fvdl
856 1.1 fvdl if (sc->bge_flags & BGE_RXRING_VALID)
857 1.1 fvdl return 0;
858 1.1 fvdl
859 1.1 fvdl for (i = 0; i < BGE_SSLOTS; i++) {
860 1.1 fvdl if (bge_newbuf_std(sc, i, NULL, 0) == ENOBUFS)
861 1.1 fvdl return(ENOBUFS);
862 1.1 fvdl }
863 1.1 fvdl
864 1.1 fvdl sc->bge_std = i - 1;
865 1.1 fvdl CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std);
866 1.1 fvdl
867 1.1 fvdl sc->bge_flags |= BGE_RXRING_VALID;
868 1.1 fvdl
869 1.1 fvdl return(0);
870 1.1 fvdl }
871 1.1 fvdl
872 1.1 fvdl void
873 1.1 fvdl bge_free_rx_ring_std(sc)
874 1.1 fvdl struct bge_softc *sc;
875 1.1 fvdl {
876 1.1 fvdl int i;
877 1.1 fvdl
878 1.1 fvdl if (!(sc->bge_flags & BGE_RXRING_VALID))
879 1.1 fvdl return;
880 1.1 fvdl
881 1.1 fvdl for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
882 1.1 fvdl if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) {
883 1.1 fvdl m_freem(sc->bge_cdata.bge_rx_std_chain[i]);
884 1.1 fvdl sc->bge_cdata.bge_rx_std_chain[i] = NULL;
885 1.1 fvdl bus_dmamap_destroy(sc->bge_dmatag,
886 1.1 fvdl sc->bge_cdata.bge_rx_std_map[i]);
887 1.1 fvdl }
888 1.1 fvdl memset((char *)&sc->bge_rdata->bge_rx_std_ring[i], 0,
889 1.1 fvdl sizeof(struct bge_rx_bd));
890 1.1 fvdl }
891 1.1 fvdl
892 1.1 fvdl sc->bge_flags &= ~BGE_RXRING_VALID;
893 1.1 fvdl }
894 1.1 fvdl
895 1.1 fvdl int
896 1.1 fvdl bge_init_rx_ring_jumbo(sc)
897 1.1 fvdl struct bge_softc *sc;
898 1.1 fvdl {
899 1.1 fvdl int i;
900 1.34 jonathan volatile struct bge_rcb *rcb;
901 1.1 fvdl
902 1.1 fvdl for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
903 1.1 fvdl if (bge_newbuf_jumbo(sc, i, NULL) == ENOBUFS)
904 1.1 fvdl return(ENOBUFS);
905 1.1 fvdl };
906 1.1 fvdl
907 1.1 fvdl sc->bge_jumbo = i - 1;
908 1.1 fvdl
909 1.1 fvdl rcb = &sc->bge_rdata->bge_info.bge_jumbo_rx_rcb;
910 1.34 jonathan rcb->bge_maxlen_flags = 0;
911 1.34 jonathan CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags);
912 1.1 fvdl
913 1.1 fvdl CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo);
914 1.1 fvdl
915 1.1 fvdl return(0);
916 1.1 fvdl }
917 1.1 fvdl
918 1.1 fvdl void
919 1.1 fvdl bge_free_rx_ring_jumbo(sc)
920 1.1 fvdl struct bge_softc *sc;
921 1.1 fvdl {
922 1.1 fvdl int i;
923 1.1 fvdl
924 1.1 fvdl if (!(sc->bge_flags & BGE_JUMBO_RXRING_VALID))
925 1.1 fvdl return;
926 1.1 fvdl
927 1.1 fvdl for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
928 1.1 fvdl if (sc->bge_cdata.bge_rx_jumbo_chain[i] != NULL) {
929 1.1 fvdl m_freem(sc->bge_cdata.bge_rx_jumbo_chain[i]);
930 1.1 fvdl sc->bge_cdata.bge_rx_jumbo_chain[i] = NULL;
931 1.1 fvdl }
932 1.1 fvdl memset((char *)&sc->bge_rdata->bge_rx_jumbo_ring[i], 0,
933 1.1 fvdl sizeof(struct bge_rx_bd));
934 1.1 fvdl }
935 1.1 fvdl
936 1.1 fvdl sc->bge_flags &= ~BGE_JUMBO_RXRING_VALID;
937 1.1 fvdl }
938 1.1 fvdl
939 1.1 fvdl void
940 1.1 fvdl bge_free_tx_ring(sc)
941 1.1 fvdl struct bge_softc *sc;
942 1.1 fvdl {
943 1.1 fvdl int i, freed;
944 1.1 fvdl struct txdmamap_pool_entry *dma;
945 1.1 fvdl
946 1.1 fvdl if (!(sc->bge_flags & BGE_TXRING_VALID))
947 1.1 fvdl return;
948 1.1 fvdl
949 1.1 fvdl freed = 0;
950 1.1 fvdl
951 1.1 fvdl for (i = 0; i < BGE_TX_RING_CNT; i++) {
952 1.1 fvdl if (sc->bge_cdata.bge_tx_chain[i] != NULL) {
953 1.1 fvdl freed++;
954 1.1 fvdl m_freem(sc->bge_cdata.bge_tx_chain[i]);
955 1.1 fvdl sc->bge_cdata.bge_tx_chain[i] = NULL;
956 1.1 fvdl SLIST_INSERT_HEAD(&sc->txdma_list, sc->txdma[i],
957 1.1 fvdl link);
958 1.1 fvdl sc->txdma[i] = 0;
959 1.1 fvdl }
960 1.1 fvdl memset((char *)&sc->bge_rdata->bge_tx_ring[i], 0,
961 1.1 fvdl sizeof(struct bge_tx_bd));
962 1.1 fvdl }
963 1.1 fvdl
964 1.1 fvdl while ((dma = SLIST_FIRST(&sc->txdma_list))) {
965 1.1 fvdl SLIST_REMOVE_HEAD(&sc->txdma_list, link);
966 1.1 fvdl bus_dmamap_destroy(sc->bge_dmatag, dma->dmamap);
967 1.1 fvdl free(dma, M_DEVBUF);
968 1.1 fvdl }
969 1.1 fvdl
970 1.1 fvdl sc->bge_flags &= ~BGE_TXRING_VALID;
971 1.1 fvdl }
972 1.1 fvdl
973 1.1 fvdl int
974 1.1 fvdl bge_init_tx_ring(sc)
975 1.1 fvdl struct bge_softc *sc;
976 1.1 fvdl {
977 1.1 fvdl int i;
978 1.1 fvdl bus_dmamap_t dmamap;
979 1.1 fvdl struct txdmamap_pool_entry *dma;
980 1.1 fvdl
981 1.1 fvdl if (sc->bge_flags & BGE_TXRING_VALID)
982 1.1 fvdl return 0;
983 1.1 fvdl
984 1.1 fvdl sc->bge_txcnt = 0;
985 1.1 fvdl sc->bge_tx_saved_considx = 0;
986 1.1 fvdl CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, 0);
987 1.25 jonathan if (sc->bge_quirks & BGE_QUIRK_PRODUCER_BUG) /* 5700 b2 errata */
988 1.25 jonathan CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, 0);
989 1.25 jonathan
990 1.1 fvdl CSR_WRITE_4(sc, BGE_MBX_TX_NIC_PROD0_LO, 0);
991 1.25 jonathan if (sc->bge_quirks & BGE_QUIRK_PRODUCER_BUG) /* 5700 b2 errata */
992 1.25 jonathan CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, 0);
993 1.1 fvdl
994 1.1 fvdl SLIST_INIT(&sc->txdma_list);
995 1.1 fvdl for (i = 0; i < BGE_RSLOTS; i++) {
996 1.1 fvdl if (bus_dmamap_create(sc->bge_dmatag, ETHER_MAX_LEN_JUMBO,
997 1.1 fvdl BGE_NTXSEG, ETHER_MAX_LEN_JUMBO, 0, BUS_DMA_NOWAIT,
998 1.1 fvdl &dmamap))
999 1.1 fvdl return(ENOBUFS);
1000 1.1 fvdl if (dmamap == NULL)
1001 1.1 fvdl panic("dmamap NULL in bge_init_tx_ring");
1002 1.1 fvdl dma = malloc(sizeof(*dma), M_DEVBUF, M_NOWAIT);
1003 1.1 fvdl if (dma == NULL) {
1004 1.1 fvdl printf("%s: can't alloc txdmamap_pool_entry\n",
1005 1.1 fvdl sc->bge_dev.dv_xname);
1006 1.1 fvdl bus_dmamap_destroy(sc->bge_dmatag, dmamap);
1007 1.1 fvdl return (ENOMEM);
1008 1.1 fvdl }
1009 1.1 fvdl dma->dmamap = dmamap;
1010 1.1 fvdl SLIST_INSERT_HEAD(&sc->txdma_list, dma, link);
1011 1.1 fvdl }
1012 1.1 fvdl
1013 1.1 fvdl sc->bge_flags |= BGE_TXRING_VALID;
1014 1.1 fvdl
1015 1.1 fvdl return(0);
1016 1.1 fvdl }
1017 1.1 fvdl
1018 1.1 fvdl void
1019 1.1 fvdl bge_setmulti(sc)
1020 1.1 fvdl struct bge_softc *sc;
1021 1.1 fvdl {
1022 1.1 fvdl struct ethercom *ac = &sc->ethercom;
1023 1.1 fvdl struct ifnet *ifp = &ac->ec_if;
1024 1.1 fvdl struct ether_multi *enm;
1025 1.1 fvdl struct ether_multistep step;
1026 1.1 fvdl u_int32_t hashes[4] = { 0, 0, 0, 0 };
1027 1.1 fvdl u_int32_t h;
1028 1.1 fvdl int i;
1029 1.1 fvdl
1030 1.13 thorpej if (ifp->if_flags & IFF_PROMISC)
1031 1.13 thorpej goto allmulti;
1032 1.1 fvdl
1033 1.1 fvdl /* Now program new ones. */
1034 1.1 fvdl ETHER_FIRST_MULTI(step, ac, enm);
1035 1.1 fvdl while (enm != NULL) {
1036 1.13 thorpej if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) {
1037 1.13 thorpej /*
1038 1.13 thorpej * We must listen to a range of multicast addresses.
1039 1.13 thorpej * For now, just accept all multicasts, rather than
1040 1.13 thorpej * trying to set only those filter bits needed to match
1041 1.13 thorpej * the range. (At this time, the only use of address
1042 1.13 thorpej * ranges is for IP multicast routing, for which the
1043 1.13 thorpej * range is big enough to require all bits set.)
1044 1.13 thorpej */
1045 1.13 thorpej goto allmulti;
1046 1.13 thorpej }
1047 1.13 thorpej
1048 1.13 thorpej h = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN);
1049 1.13 thorpej
1050 1.13 thorpej /* Just want the 7 least-significant bits. */
1051 1.13 thorpej h &= 0x7f;
1052 1.13 thorpej
1053 1.1 fvdl hashes[(h & 0x60) >> 5] |= 1 << (h & 0x1F);
1054 1.1 fvdl ETHER_NEXT_MULTI(step, enm);
1055 1.1 fvdl }
1056 1.1 fvdl
1057 1.13 thorpej ifp->if_flags &= ~IFF_ALLMULTI;
1058 1.13 thorpej goto setit;
1059 1.13 thorpej
1060 1.13 thorpej allmulti:
1061 1.13 thorpej ifp->if_flags |= IFF_ALLMULTI;
1062 1.13 thorpej hashes[0] = hashes[1] = hashes[2] = hashes[3] = 0xffffffff;
1063 1.13 thorpej
1064 1.13 thorpej setit:
1065 1.1 fvdl for (i = 0; i < 4; i++)
1066 1.1 fvdl CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]);
1067 1.1 fvdl }
1068 1.1 fvdl
1069 1.24 matt const int bge_swapbits[] = {
1070 1.1 fvdl 0,
1071 1.1 fvdl BGE_MODECTL_BYTESWAP_DATA,
1072 1.1 fvdl BGE_MODECTL_WORDSWAP_DATA,
1073 1.1 fvdl BGE_MODECTL_BYTESWAP_NONFRAME,
1074 1.1 fvdl BGE_MODECTL_WORDSWAP_NONFRAME,
1075 1.1 fvdl
1076 1.1 fvdl BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA,
1077 1.1 fvdl BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_BYTESWAP_NONFRAME,
1078 1.1 fvdl BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_NONFRAME,
1079 1.1 fvdl
1080 1.1 fvdl BGE_MODECTL_WORDSWAP_DATA|BGE_MODECTL_BYTESWAP_NONFRAME,
1081 1.1 fvdl BGE_MODECTL_WORDSWAP_DATA|BGE_MODECTL_WORDSWAP_NONFRAME,
1082 1.1 fvdl
1083 1.1 fvdl BGE_MODECTL_BYTESWAP_NONFRAME|BGE_MODECTL_WORDSWAP_NONFRAME,
1084 1.1 fvdl
1085 1.1 fvdl BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA|
1086 1.1 fvdl BGE_MODECTL_BYTESWAP_NONFRAME,
1087 1.1 fvdl BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA|
1088 1.1 fvdl BGE_MODECTL_WORDSWAP_NONFRAME,
1089 1.1 fvdl BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_BYTESWAP_NONFRAME|
1090 1.1 fvdl BGE_MODECTL_WORDSWAP_NONFRAME,
1091 1.1 fvdl BGE_MODECTL_WORDSWAP_DATA|BGE_MODECTL_BYTESWAP_NONFRAME|
1092 1.1 fvdl BGE_MODECTL_WORDSWAP_NONFRAME,
1093 1.1 fvdl
1094 1.1 fvdl BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA|
1095 1.1 fvdl BGE_MODECTL_BYTESWAP_NONFRAME|BGE_MODECTL_WORDSWAP_NONFRAME,
1096 1.1 fvdl };
1097 1.1 fvdl
1098 1.1 fvdl int bge_swapindex = 0;
1099 1.1 fvdl
1100 1.1 fvdl /*
1101 1.1 fvdl * Do endian, PCI and DMA initialization. Also check the on-board ROM
1102 1.1 fvdl * self-test results.
1103 1.1 fvdl */
1104 1.1 fvdl int
1105 1.1 fvdl bge_chipinit(sc)
1106 1.1 fvdl struct bge_softc *sc;
1107 1.1 fvdl {
1108 1.1 fvdl u_int32_t cachesize;
1109 1.1 fvdl int i;
1110 1.25 jonathan u_int32_t dma_rw_ctl;
1111 1.1 fvdl struct pci_attach_args *pa = &(sc->bge_pa);
1112 1.1 fvdl
1113 1.1 fvdl
1114 1.1 fvdl /* Set endianness before we access any non-PCI registers. */
1115 1.1 fvdl pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_MISC_CTL,
1116 1.1 fvdl BGE_INIT);
1117 1.1 fvdl
1118 1.25 jonathan /* Set power state to D0. */
1119 1.25 jonathan bge_setpowerstate(sc, 0);
1120 1.25 jonathan
1121 1.1 fvdl /*
1122 1.1 fvdl * Check the 'ROM failed' bit on the RX CPU to see if
1123 1.1 fvdl * self-tests passed.
1124 1.1 fvdl */
1125 1.1 fvdl if (CSR_READ_4(sc, BGE_RXCPU_MODE) & BGE_RXCPUMODE_ROMFAIL) {
1126 1.1 fvdl printf("%s: RX CPU self-diagnostics failed!\n",
1127 1.1 fvdl sc->bge_dev.dv_xname);
1128 1.1 fvdl return(ENODEV);
1129 1.1 fvdl }
1130 1.1 fvdl
1131 1.1 fvdl /* Clear the MAC control register */
1132 1.1 fvdl CSR_WRITE_4(sc, BGE_MAC_MODE, 0);
1133 1.1 fvdl
1134 1.1 fvdl /*
1135 1.1 fvdl * Clear the MAC statistics block in the NIC's
1136 1.1 fvdl * internal memory.
1137 1.1 fvdl */
1138 1.1 fvdl for (i = BGE_STATS_BLOCK;
1139 1.1 fvdl i < BGE_STATS_BLOCK_END + 1; i += sizeof(u_int32_t))
1140 1.1 fvdl BGE_MEMWIN_WRITE(pa->pa_pc, pa->pa_tag, i, 0);
1141 1.1 fvdl
1142 1.1 fvdl for (i = BGE_STATUS_BLOCK;
1143 1.1 fvdl i < BGE_STATUS_BLOCK_END + 1; i += sizeof(u_int32_t))
1144 1.1 fvdl BGE_MEMWIN_WRITE(pa->pa_pc, pa->pa_tag, i, 0);
1145 1.1 fvdl
1146 1.1 fvdl /* Set up the PCI DMA control register. */
1147 1.25 jonathan if (pci_conf_read(pa->pa_pc, pa->pa_tag,BGE_PCI_PCISTATE) &
1148 1.25 jonathan BGE_PCISTATE_PCI_BUSMODE) {
1149 1.25 jonathan /* Conventional PCI bus */
1150 1.39 wiz DPRINTFN(4, ("(%s: PCI 2.2 DMA setting)\n", sc->bge_dev.dv_xname));
1151 1.25 jonathan dma_rw_ctl = (BGE_PCI_READ_CMD | BGE_PCI_WRITE_CMD |
1152 1.25 jonathan (0x7 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
1153 1.44 hannken (0x7 << BGE_PCIDMARWCTL_WR_WAT_SHIFT));
1154 1.44 hannken if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) {
1155 1.44 hannken dma_rw_ctl |= 0x0F;
1156 1.44 hannken }
1157 1.25 jonathan } else {
1158 1.39 wiz DPRINTFN(4, ("(:%s: PCI-X DMA setting)\n", sc->bge_dev.dv_xname));
1159 1.25 jonathan /* PCI-X bus */
1160 1.25 jonathan dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
1161 1.25 jonathan (0x3 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
1162 1.25 jonathan (0x3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT) |
1163 1.25 jonathan (0x0F);
1164 1.25 jonathan /*
1165 1.25 jonathan * 5703 and 5704 need ONEDMA_AT_ONCE as a workaround
1166 1.25 jonathan * for hardware bugs, which means we should also clear
1167 1.25 jonathan * the low-order MINDMA bits. In addition, the 5704
1168 1.25 jonathan * uses a different encoding of read/write watermarks.
1169 1.25 jonathan */
1170 1.40 fvdl if (sc->bge_asicrev == BGE_ASICREV_BCM5704_A0 ||
1171 1.40 fvdl sc->bge_asicrev == BGE_ASICREV_BCM5704_A1 ||
1172 1.40 fvdl sc->bge_asicrev == BGE_ASICREV_BCM5704_A2) {
1173 1.25 jonathan dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
1174 1.25 jonathan /* should be 0x1f0000 */
1175 1.25 jonathan (0x7 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
1176 1.25 jonathan (0x3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT);
1177 1.25 jonathan dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE;
1178 1.25 jonathan }
1179 1.25 jonathan else if ((sc->bge_asicrev >> 28) ==
1180 1.25 jonathan (BGE_ASICREV_BCM5703_A0 >> 28)) {
1181 1.25 jonathan dma_rw_ctl &= 0xfffffff0;
1182 1.25 jonathan dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE;
1183 1.25 jonathan }
1184 1.25 jonathan }
1185 1.25 jonathan
1186 1.25 jonathan pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_DMA_RW_CTL, dma_rw_ctl);
1187 1.1 fvdl
1188 1.1 fvdl /*
1189 1.1 fvdl * Set up general mode register.
1190 1.1 fvdl */
1191 1.1 fvdl CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS|
1192 1.1 fvdl BGE_MODECTL_MAC_ATTN_INTR|BGE_MODECTL_HOST_SEND_BDS|
1193 1.1 fvdl BGE_MODECTL_NO_RX_CRC|BGE_MODECTL_TX_NO_PHDR_CSUM|
1194 1.1 fvdl BGE_MODECTL_RX_NO_PHDR_CSUM);
1195 1.1 fvdl
1196 1.1 fvdl /* Get cache line size. */
1197 1.1 fvdl cachesize = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_CACHESZ);
1198 1.1 fvdl
1199 1.1 fvdl /*
1200 1.1 fvdl * Avoid violating PCI spec on certain chip revs.
1201 1.1 fvdl */
1202 1.1 fvdl if (pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_CMD) &
1203 1.1 fvdl PCIM_CMD_MWIEN) {
1204 1.1 fvdl switch(cachesize) {
1205 1.1 fvdl case 1:
1206 1.1 fvdl PCI_SETBIT(pa->pa_pc, pa->pa_tag, BGE_PCI_DMA_RW_CTL,
1207 1.1 fvdl BGE_PCI_WRITE_BNDRY_16BYTES);
1208 1.1 fvdl break;
1209 1.1 fvdl case 2:
1210 1.1 fvdl PCI_SETBIT(pa->pa_pc, pa->pa_tag, BGE_PCI_DMA_RW_CTL,
1211 1.1 fvdl BGE_PCI_WRITE_BNDRY_32BYTES);
1212 1.1 fvdl break;
1213 1.1 fvdl case 4:
1214 1.1 fvdl PCI_SETBIT(pa->pa_pc, pa->pa_tag, BGE_PCI_DMA_RW_CTL,
1215 1.1 fvdl BGE_PCI_WRITE_BNDRY_64BYTES);
1216 1.1 fvdl break;
1217 1.1 fvdl case 8:
1218 1.1 fvdl PCI_SETBIT(pa->pa_pc, pa->pa_tag, BGE_PCI_DMA_RW_CTL,
1219 1.1 fvdl BGE_PCI_WRITE_BNDRY_128BYTES);
1220 1.1 fvdl break;
1221 1.1 fvdl case 16:
1222 1.1 fvdl PCI_SETBIT(pa->pa_pc, pa->pa_tag, BGE_PCI_DMA_RW_CTL,
1223 1.1 fvdl BGE_PCI_WRITE_BNDRY_256BYTES);
1224 1.1 fvdl break;
1225 1.1 fvdl case 32:
1226 1.1 fvdl PCI_SETBIT(pa->pa_pc, pa->pa_tag, BGE_PCI_DMA_RW_CTL,
1227 1.1 fvdl BGE_PCI_WRITE_BNDRY_512BYTES);
1228 1.1 fvdl break;
1229 1.1 fvdl case 64:
1230 1.1 fvdl PCI_SETBIT(pa->pa_pc, pa->pa_tag, BGE_PCI_DMA_RW_CTL,
1231 1.1 fvdl BGE_PCI_WRITE_BNDRY_1024BYTES);
1232 1.1 fvdl break;
1233 1.1 fvdl default:
1234 1.1 fvdl /* Disable PCI memory write and invalidate. */
1235 1.1 fvdl #if 0
1236 1.1 fvdl if (bootverbose)
1237 1.1 fvdl printf("%s: cache line size %d not "
1238 1.1 fvdl "supported; disabling PCI MWI\n",
1239 1.1 fvdl sc->bge_dev.dv_xname, cachesize);
1240 1.1 fvdl #endif
1241 1.1 fvdl PCI_CLRBIT(pa->pa_pc, pa->pa_tag, BGE_PCI_CMD,
1242 1.1 fvdl PCIM_CMD_MWIEN);
1243 1.1 fvdl break;
1244 1.1 fvdl }
1245 1.1 fvdl }
1246 1.1 fvdl
1247 1.25 jonathan /*
1248 1.25 jonathan * Disable memory write invalidate. Apparently it is not supported
1249 1.25 jonathan * properly by these devices.
1250 1.25 jonathan */
1251 1.25 jonathan PCI_CLRBIT(pa->pa_pc, pa->pa_tag, BGE_PCI_CMD, PCIM_CMD_MWIEN);
1252 1.25 jonathan
1253 1.25 jonathan
1254 1.1 fvdl #ifdef __brokenalpha__
1255 1.1 fvdl /*
1256 1.1 fvdl * Must insure that we do not cross an 8K (bytes) boundary
1257 1.1 fvdl * for DMA reads. Our highest limit is 1K bytes. This is a
1258 1.1 fvdl * restriction on some ALPHA platforms with early revision
1259 1.1 fvdl * 21174 PCI chipsets, such as the AlphaPC 164lx
1260 1.1 fvdl */
1261 1.1 fvdl PCI_SETBIT(sc, BGE_PCI_DMA_RW_CTL, BGE_PCI_READ_BNDRY_1024, 4);
1262 1.1 fvdl #endif
1263 1.1 fvdl
1264 1.33 tsutsui /* Set the timer prescaler (always 66MHz) */
1265 1.1 fvdl CSR_WRITE_4(sc, BGE_MISC_CFG, 65 << 1/*BGE_32BITTIME_66MHZ*/);
1266 1.1 fvdl
1267 1.1 fvdl return(0);
1268 1.1 fvdl }
1269 1.1 fvdl
1270 1.1 fvdl int
1271 1.1 fvdl bge_blockinit(sc)
1272 1.1 fvdl struct bge_softc *sc;
1273 1.1 fvdl {
1274 1.34 jonathan volatile struct bge_rcb *rcb;
1275 1.1 fvdl bus_size_t rcb_addr;
1276 1.1 fvdl int i;
1277 1.1 fvdl struct ifnet *ifp = &sc->ethercom.ec_if;
1278 1.1 fvdl bge_hostaddr taddr;
1279 1.1 fvdl
1280 1.1 fvdl /*
1281 1.1 fvdl * Initialize the memory window pointer register so that
1282 1.1 fvdl * we can access the first 32K of internal NIC RAM. This will
1283 1.1 fvdl * allow us to set up the TX send ring RCBs and the RX return
1284 1.1 fvdl * ring RCBs, plus other things which live in NIC memory.
1285 1.1 fvdl */
1286 1.1 fvdl
1287 1.1 fvdl pci_conf_write(sc->bge_pa.pa_pc, sc->bge_pa.pa_tag,
1288 1.1 fvdl BGE_PCI_MEMWIN_BASEADDR, 0);
1289 1.1 fvdl
1290 1.1 fvdl /* Configure mbuf memory pool */
1291 1.44 hannken if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) {
1292 1.44 hannken if (sc->bge_extram) {
1293 1.44 hannken CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR,
1294 1.44 hannken BGE_EXT_SSRAM);
1295 1.44 hannken CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000);
1296 1.44 hannken } else {
1297 1.44 hannken CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR,
1298 1.44 hannken BGE_BUFFPOOL_1);
1299 1.44 hannken CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000);
1300 1.44 hannken }
1301 1.44 hannken
1302 1.44 hannken /* Configure DMA resource pool */
1303 1.44 hannken CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_BASEADDR,
1304 1.44 hannken BGE_DMA_DESCRIPTORS);
1305 1.44 hannken CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LEN, 0x2000);
1306 1.1 fvdl }
1307 1.1 fvdl
1308 1.1 fvdl /* Configure mbuf pool watermarks */
1309 1.25 jonathan #ifdef ORIG_WPAUL_VALUES
1310 1.1 fvdl CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 24);
1311 1.1 fvdl CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 24);
1312 1.1 fvdl CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 48);
1313 1.25 jonathan #else
1314 1.25 jonathan /* new broadcom docs strongly recommend these: */
1315 1.44 hannken if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) {
1316 1.44 hannken CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x50);
1317 1.44 hannken CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x20);
1318 1.44 hannken } else {
1319 1.44 hannken CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0);
1320 1.44 hannken CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x10);
1321 1.44 hannken }
1322 1.25 jonathan CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60);
1323 1.25 jonathan #endif
1324 1.1 fvdl
1325 1.1 fvdl /* Configure DMA resource watermarks */
1326 1.1 fvdl CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5);
1327 1.1 fvdl CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10);
1328 1.1 fvdl
1329 1.1 fvdl /* Enable buffer manager */
1330 1.44 hannken if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) {
1331 1.44 hannken CSR_WRITE_4(sc, BGE_BMAN_MODE,
1332 1.44 hannken BGE_BMANMODE_ENABLE|BGE_BMANMODE_LOMBUF_ATTN);
1333 1.44 hannken
1334 1.44 hannken /* Poll for buffer manager start indication */
1335 1.44 hannken for (i = 0; i < BGE_TIMEOUT; i++) {
1336 1.44 hannken if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE)
1337 1.44 hannken break;
1338 1.44 hannken DELAY(10);
1339 1.44 hannken }
1340 1.1 fvdl
1341 1.44 hannken if (i == BGE_TIMEOUT) {
1342 1.44 hannken printf("%s: buffer manager failed to start\n",
1343 1.44 hannken sc->bge_dev.dv_xname);
1344 1.44 hannken return(ENXIO);
1345 1.44 hannken }
1346 1.1 fvdl }
1347 1.1 fvdl
1348 1.1 fvdl /* Enable flow-through queues */
1349 1.1 fvdl CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF);
1350 1.1 fvdl CSR_WRITE_4(sc, BGE_FTQ_RESET, 0);
1351 1.1 fvdl
1352 1.1 fvdl /* Wait until queue initialization is complete */
1353 1.1 fvdl for (i = 0; i < BGE_TIMEOUT; i++) {
1354 1.1 fvdl if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0)
1355 1.1 fvdl break;
1356 1.1 fvdl DELAY(10);
1357 1.1 fvdl }
1358 1.1 fvdl
1359 1.1 fvdl if (i == BGE_TIMEOUT) {
1360 1.1 fvdl printf("%s: flow-through queue init failed\n",
1361 1.1 fvdl sc->bge_dev.dv_xname);
1362 1.1 fvdl return(ENXIO);
1363 1.1 fvdl }
1364 1.1 fvdl
1365 1.1 fvdl /* Initialize the standard RX ring control block */
1366 1.1 fvdl rcb = &sc->bge_rdata->bge_info.bge_std_rx_rcb;
1367 1.1 fvdl bge_set_hostaddr(&rcb->bge_hostaddr,
1368 1.1 fvdl BGE_RING_DMA_ADDR(sc, bge_rx_std_ring));
1369 1.44 hannken if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) {
1370 1.44 hannken rcb->bge_maxlen_flags =
1371 1.44 hannken BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 0);
1372 1.44 hannken } else {
1373 1.44 hannken rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(512, 0);
1374 1.44 hannken }
1375 1.1 fvdl if (sc->bge_extram)
1376 1.1 fvdl rcb->bge_nicaddr = BGE_EXT_STD_RX_RINGS;
1377 1.1 fvdl else
1378 1.1 fvdl rcb->bge_nicaddr = BGE_STD_RX_RINGS;
1379 1.34 jonathan CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcb->bge_hostaddr.bge_addr_hi);
1380 1.34 jonathan CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcb->bge_hostaddr.bge_addr_lo);
1381 1.34 jonathan CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags);
1382 1.34 jonathan CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcb->bge_nicaddr);
1383 1.1 fvdl
1384 1.44 hannken if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) {
1385 1.44 hannken sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT;
1386 1.44 hannken } else {
1387 1.44 hannken sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT_5705;
1388 1.44 hannken }
1389 1.44 hannken
1390 1.1 fvdl /*
1391 1.1 fvdl * Initialize the jumbo RX ring control block
1392 1.1 fvdl * We set the 'ring disabled' bit in the flags
1393 1.1 fvdl * field until we're actually ready to start
1394 1.1 fvdl * using this ring (i.e. once we set the MTU
1395 1.1 fvdl * high enough to require it).
1396 1.1 fvdl */
1397 1.44 hannken if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) {
1398 1.44 hannken rcb = &sc->bge_rdata->bge_info.bge_jumbo_rx_rcb;
1399 1.44 hannken bge_set_hostaddr(&rcb->bge_hostaddr,
1400 1.44 hannken BGE_RING_DMA_ADDR(sc, bge_rx_jumbo_ring));
1401 1.44 hannken rcb->bge_maxlen_flags =
1402 1.44 hannken BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN,
1403 1.44 hannken BGE_RCB_FLAG_RING_DISABLED);
1404 1.44 hannken if (sc->bge_extram)
1405 1.44 hannken rcb->bge_nicaddr = BGE_EXT_JUMBO_RX_RINGS;
1406 1.44 hannken else
1407 1.44 hannken rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS;
1408 1.44 hannken
1409 1.44 hannken CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI,
1410 1.44 hannken rcb->bge_hostaddr.bge_addr_hi);
1411 1.44 hannken CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO,
1412 1.44 hannken rcb->bge_hostaddr.bge_addr_lo);
1413 1.44 hannken CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS,
1414 1.44 hannken rcb->bge_maxlen_flags);
1415 1.44 hannken CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcb->bge_nicaddr);
1416 1.44 hannken
1417 1.44 hannken /* Set up dummy disabled mini ring RCB */
1418 1.44 hannken rcb = &sc->bge_rdata->bge_info.bge_mini_rx_rcb;
1419 1.44 hannken rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0,
1420 1.44 hannken BGE_RCB_FLAG_RING_DISABLED);
1421 1.44 hannken CSR_WRITE_4(sc, BGE_RX_MINI_RCB_MAXLEN_FLAGS,
1422 1.44 hannken rcb->bge_maxlen_flags);
1423 1.1 fvdl
1424 1.44 hannken bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map,
1425 1.44 hannken offsetof(struct bge_ring_data, bge_info),
1426 1.44 hannken sizeof (struct bge_gib),
1427 1.44 hannken BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
1428 1.44 hannken }
1429 1.1 fvdl
1430 1.1 fvdl /*
1431 1.1 fvdl * Set the BD ring replentish thresholds. The recommended
1432 1.1 fvdl * values are 1/8th the number of descriptors allocated to
1433 1.1 fvdl * each ring.
1434 1.1 fvdl */
1435 1.1 fvdl CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, BGE_STD_RX_RING_CNT/8);
1436 1.1 fvdl CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH, BGE_JUMBO_RX_RING_CNT/8);
1437 1.1 fvdl
1438 1.1 fvdl /*
1439 1.1 fvdl * Disable all unused send rings by setting the 'ring disabled'
1440 1.1 fvdl * bit in the flags field of all the TX send ring control blocks.
1441 1.1 fvdl * These are located in NIC memory.
1442 1.1 fvdl */
1443 1.1 fvdl rcb_addr = BGE_MEMWIN_START + BGE_SEND_RING_RCB;
1444 1.1 fvdl for (i = 0; i < BGE_TX_RINGS_EXTSSRAM_MAX; i++) {
1445 1.34 jonathan RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags,
1446 1.34 jonathan BGE_RCB_MAXLEN_FLAGS(0,BGE_RCB_FLAG_RING_DISABLED));
1447 1.1 fvdl RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 0);
1448 1.1 fvdl rcb_addr += sizeof(struct bge_rcb);
1449 1.1 fvdl }
1450 1.1 fvdl
1451 1.1 fvdl /* Configure TX RCB 0 (we use only the first ring) */
1452 1.1 fvdl rcb_addr = BGE_MEMWIN_START + BGE_SEND_RING_RCB;
1453 1.1 fvdl bge_set_hostaddr(&taddr, BGE_RING_DMA_ADDR(sc, bge_tx_ring));
1454 1.1 fvdl RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi);
1455 1.1 fvdl RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo);
1456 1.1 fvdl RCB_WRITE_4(sc, rcb_addr, bge_nicaddr,
1457 1.1 fvdl BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT));
1458 1.44 hannken if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) {
1459 1.44 hannken RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags,
1460 1.44 hannken BGE_RCB_MAXLEN_FLAGS(BGE_TX_RING_CNT, 0));
1461 1.44 hannken }
1462 1.1 fvdl
1463 1.1 fvdl /* Disable all unused RX return rings */
1464 1.1 fvdl rcb_addr = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB;
1465 1.1 fvdl for (i = 0; i < BGE_RX_RINGS_MAX; i++) {
1466 1.1 fvdl RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_hi, 0);
1467 1.1 fvdl RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_lo, 0);
1468 1.34 jonathan RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags,
1469 1.44 hannken BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt,
1470 1.34 jonathan BGE_RCB_FLAG_RING_DISABLED));
1471 1.1 fvdl RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 0);
1472 1.1 fvdl CSR_WRITE_4(sc, BGE_MBX_RX_CONS0_LO +
1473 1.1 fvdl (i * (sizeof(u_int64_t))), 0);
1474 1.1 fvdl rcb_addr += sizeof(struct bge_rcb);
1475 1.1 fvdl }
1476 1.1 fvdl
1477 1.1 fvdl /* Initialize RX ring indexes */
1478 1.1 fvdl CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, 0);
1479 1.1 fvdl CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0);
1480 1.1 fvdl CSR_WRITE_4(sc, BGE_MBX_RX_MINI_PROD_LO, 0);
1481 1.1 fvdl
1482 1.1 fvdl /*
1483 1.1 fvdl * Set up RX return ring 0
1484 1.1 fvdl * Note that the NIC address for RX return rings is 0x00000000.
1485 1.1 fvdl * The return rings live entirely within the host, so the
1486 1.1 fvdl * nicaddr field in the RCB isn't used.
1487 1.1 fvdl */
1488 1.1 fvdl rcb_addr = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB;
1489 1.1 fvdl bge_set_hostaddr(&taddr, BGE_RING_DMA_ADDR(sc, bge_rx_return_ring));
1490 1.1 fvdl RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi);
1491 1.1 fvdl RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo);
1492 1.1 fvdl RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 0x00000000);
1493 1.34 jonathan RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags,
1494 1.44 hannken BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 0));
1495 1.1 fvdl
1496 1.1 fvdl /* Set random backoff seed for TX */
1497 1.1 fvdl CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF,
1498 1.1 fvdl LLADDR(ifp->if_sadl)[0] + LLADDR(ifp->if_sadl)[1] +
1499 1.1 fvdl LLADDR(ifp->if_sadl)[2] + LLADDR(ifp->if_sadl)[3] +
1500 1.1 fvdl LLADDR(ifp->if_sadl)[4] + LLADDR(ifp->if_sadl)[5] +
1501 1.1 fvdl BGE_TX_BACKOFF_SEED_MASK);
1502 1.1 fvdl
1503 1.1 fvdl /* Set inter-packet gap */
1504 1.1 fvdl CSR_WRITE_4(sc, BGE_TX_LENGTHS, 0x2620);
1505 1.1 fvdl
1506 1.1 fvdl /*
1507 1.1 fvdl * Specify which ring to use for packets that don't match
1508 1.1 fvdl * any RX rules.
1509 1.1 fvdl */
1510 1.1 fvdl CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08);
1511 1.1 fvdl
1512 1.1 fvdl /*
1513 1.1 fvdl * Configure number of RX lists. One interrupt distribution
1514 1.1 fvdl * list, sixteen active lists, one bad frames class.
1515 1.1 fvdl */
1516 1.1 fvdl CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181);
1517 1.1 fvdl
1518 1.1 fvdl /* Inialize RX list placement stats mask. */
1519 1.1 fvdl CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF);
1520 1.1 fvdl CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1);
1521 1.1 fvdl
1522 1.1 fvdl /* Disable host coalescing until we get it set up */
1523 1.1 fvdl CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000);
1524 1.1 fvdl
1525 1.1 fvdl /* Poll to make sure it's shut down. */
1526 1.1 fvdl for (i = 0; i < BGE_TIMEOUT; i++) {
1527 1.1 fvdl if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE))
1528 1.1 fvdl break;
1529 1.1 fvdl DELAY(10);
1530 1.1 fvdl }
1531 1.1 fvdl
1532 1.1 fvdl if (i == BGE_TIMEOUT) {
1533 1.1 fvdl printf("%s: host coalescing engine failed to idle\n",
1534 1.1 fvdl sc->bge_dev.dv_xname);
1535 1.1 fvdl return(ENXIO);
1536 1.1 fvdl }
1537 1.1 fvdl
1538 1.1 fvdl /* Set up host coalescing defaults */
1539 1.1 fvdl CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bge_rx_coal_ticks);
1540 1.1 fvdl CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bge_tx_coal_ticks);
1541 1.1 fvdl CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bge_rx_max_coal_bds);
1542 1.1 fvdl CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bge_tx_max_coal_bds);
1543 1.44 hannken if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) {
1544 1.44 hannken CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT, 0);
1545 1.44 hannken CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT, 0);
1546 1.44 hannken }
1547 1.1 fvdl CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 0);
1548 1.1 fvdl CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 0);
1549 1.1 fvdl
1550 1.1 fvdl /* Set up address of statistics block */
1551 1.44 hannken if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) {
1552 1.44 hannken bge_set_hostaddr(&taddr,
1553 1.44 hannken BGE_RING_DMA_ADDR(sc, bge_info.bge_stats));
1554 1.44 hannken CSR_WRITE_4(sc, BGE_HCC_STATS_TICKS, sc->bge_stat_ticks);
1555 1.44 hannken CSR_WRITE_4(sc, BGE_HCC_STATS_BASEADDR, BGE_STATS_BLOCK);
1556 1.44 hannken CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_HI, taddr.bge_addr_hi);
1557 1.44 hannken CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_LO, taddr.bge_addr_lo);
1558 1.44 hannken }
1559 1.1 fvdl
1560 1.1 fvdl /* Set up address of status block */
1561 1.1 fvdl bge_set_hostaddr(&taddr, BGE_RING_DMA_ADDR(sc, bge_status_block));
1562 1.1 fvdl CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_BASEADDR, BGE_STATUS_BLOCK);
1563 1.1 fvdl CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI, taddr.bge_addr_hi);
1564 1.1 fvdl CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO, taddr.bge_addr_lo);
1565 1.1 fvdl sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx = 0;
1566 1.1 fvdl sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx = 0;
1567 1.1 fvdl
1568 1.1 fvdl /* Turn on host coalescing state machine */
1569 1.1 fvdl CSR_WRITE_4(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE);
1570 1.1 fvdl
1571 1.1 fvdl /* Turn on RX BD completion state machine and enable attentions */
1572 1.1 fvdl CSR_WRITE_4(sc, BGE_RBDC_MODE,
1573 1.1 fvdl BGE_RBDCMODE_ENABLE|BGE_RBDCMODE_ATTN);
1574 1.1 fvdl
1575 1.1 fvdl /* Turn on RX list placement state machine */
1576 1.1 fvdl CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);
1577 1.1 fvdl
1578 1.1 fvdl /* Turn on RX list selector state machine. */
1579 1.44 hannken if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) {
1580 1.44 hannken CSR_WRITE_4(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE);
1581 1.44 hannken }
1582 1.1 fvdl
1583 1.1 fvdl /* Turn on DMA, clear stats */
1584 1.1 fvdl CSR_WRITE_4(sc, BGE_MAC_MODE, BGE_MACMODE_TXDMA_ENB|
1585 1.1 fvdl BGE_MACMODE_RXDMA_ENB|BGE_MACMODE_RX_STATS_CLEAR|
1586 1.1 fvdl BGE_MACMODE_TX_STATS_CLEAR|BGE_MACMODE_RX_STATS_ENB|
1587 1.1 fvdl BGE_MACMODE_TX_STATS_ENB|BGE_MACMODE_FRMHDR_DMA_ENB|
1588 1.1 fvdl (sc->bge_tbi ? BGE_PORTMODE_TBI : BGE_PORTMODE_MII));
1589 1.1 fvdl
1590 1.1 fvdl /* Set misc. local control, enable interrupts on attentions */
1591 1.25 jonathan sc->bge_local_ctrl_reg = BGE_MLC_INTR_ONATTN | BGE_MLC_AUTO_EEPROM;
1592 1.1 fvdl
1593 1.1 fvdl #ifdef notdef
1594 1.1 fvdl /* Assert GPIO pins for PHY reset */
1595 1.1 fvdl BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUT0|
1596 1.1 fvdl BGE_MLC_MISCIO_OUT1|BGE_MLC_MISCIO_OUT2);
1597 1.1 fvdl BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUTEN0|
1598 1.1 fvdl BGE_MLC_MISCIO_OUTEN1|BGE_MLC_MISCIO_OUTEN2);
1599 1.1 fvdl #endif
1600 1.1 fvdl
1601 1.25 jonathan #if defined(not_quite_yet)
1602 1.25 jonathan /* Linux driver enables enable gpio pin #1 on 5700s */
1603 1.25 jonathan if (sc->bge_asicrev == BGE_ASICREV_BCM5700) {
1604 1.25 jonathan sc->bge_local_ctrl_reg |=
1605 1.25 jonathan (BGE_MLC_MISCIO_OUT1|BGE_MLC_MISCIO_OUTEN1);
1606 1.25 jonathan }
1607 1.25 jonathan #endif
1608 1.25 jonathan CSR_WRITE_4(sc, BGE_MISC_LOCAL_CTL, sc->bge_local_ctrl_reg);
1609 1.25 jonathan
1610 1.1 fvdl /* Turn on DMA completion state machine */
1611 1.44 hannken if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) {
1612 1.44 hannken CSR_WRITE_4(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE);
1613 1.44 hannken }
1614 1.1 fvdl
1615 1.1 fvdl /* Turn on write DMA state machine */
1616 1.1 fvdl CSR_WRITE_4(sc, BGE_WDMA_MODE,
1617 1.1 fvdl BGE_WDMAMODE_ENABLE|BGE_WDMAMODE_ALL_ATTNS);
1618 1.1 fvdl
1619 1.1 fvdl /* Turn on read DMA state machine */
1620 1.1 fvdl CSR_WRITE_4(sc, BGE_RDMA_MODE,
1621 1.1 fvdl BGE_RDMAMODE_ENABLE|BGE_RDMAMODE_ALL_ATTNS);
1622 1.1 fvdl
1623 1.1 fvdl /* Turn on RX data completion state machine */
1624 1.1 fvdl CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);
1625 1.1 fvdl
1626 1.1 fvdl /* Turn on RX BD initiator state machine */
1627 1.1 fvdl CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE);
1628 1.1 fvdl
1629 1.1 fvdl /* Turn on RX data and RX BD initiator state machine */
1630 1.1 fvdl CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE);
1631 1.1 fvdl
1632 1.1 fvdl /* Turn on Mbuf cluster free state machine */
1633 1.44 hannken if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) {
1634 1.44 hannken CSR_WRITE_4(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE);
1635 1.44 hannken }
1636 1.1 fvdl
1637 1.1 fvdl /* Turn on send BD completion state machine */
1638 1.1 fvdl CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);
1639 1.1 fvdl
1640 1.1 fvdl /* Turn on send data completion state machine */
1641 1.1 fvdl CSR_WRITE_4(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE);
1642 1.1 fvdl
1643 1.1 fvdl /* Turn on send data initiator state machine */
1644 1.1 fvdl CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE);
1645 1.1 fvdl
1646 1.1 fvdl /* Turn on send BD initiator state machine */
1647 1.1 fvdl CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE);
1648 1.1 fvdl
1649 1.1 fvdl /* Turn on send BD selector state machine */
1650 1.1 fvdl CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE);
1651 1.1 fvdl
1652 1.1 fvdl CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF);
1653 1.1 fvdl CSR_WRITE_4(sc, BGE_SDI_STATS_CTL,
1654 1.1 fvdl BGE_SDISTATSCTL_ENABLE|BGE_SDISTATSCTL_FASTER);
1655 1.1 fvdl
1656 1.1 fvdl /* init LED register */
1657 1.1 fvdl CSR_WRITE_4(sc, BGE_MAC_LED_CTL, 0x00000000);
1658 1.1 fvdl
1659 1.1 fvdl /* ack/clear link change events */
1660 1.1 fvdl CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED|
1661 1.1 fvdl BGE_MACSTAT_CFG_CHANGED);
1662 1.1 fvdl CSR_WRITE_4(sc, BGE_MI_STS, 0);
1663 1.1 fvdl
1664 1.1 fvdl /* Enable PHY auto polling (for MII/GMII only) */
1665 1.1 fvdl if (sc->bge_tbi) {
1666 1.1 fvdl CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK);
1667 1.1 fvdl } else {
1668 1.1 fvdl BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL|10<<16);
1669 1.17 thorpej if (sc->bge_quirks & BGE_QUIRK_LINK_STATE_BROKEN)
1670 1.1 fvdl CSR_WRITE_4(sc, BGE_MAC_EVT_ENB,
1671 1.1 fvdl BGE_EVTENB_MI_INTERRUPT);
1672 1.1 fvdl }
1673 1.1 fvdl
1674 1.1 fvdl /* Enable link state change attentions. */
1675 1.1 fvdl BGE_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED);
1676 1.1 fvdl
1677 1.1 fvdl return(0);
1678 1.1 fvdl }
1679 1.1 fvdl
1680 1.16 thorpej static const struct bge_revision {
1681 1.16 thorpej uint32_t br_asicrev;
1682 1.16 thorpej uint32_t br_quirks;
1683 1.16 thorpej const char *br_name;
1684 1.16 thorpej } bge_revisions[] = {
1685 1.16 thorpej { BGE_ASICREV_BCM5700_A0,
1686 1.17 thorpej BGE_QUIRK_LINK_STATE_BROKEN,
1687 1.16 thorpej "BCM5700 A0" },
1688 1.16 thorpej
1689 1.16 thorpej { BGE_ASICREV_BCM5700_A1,
1690 1.17 thorpej BGE_QUIRK_LINK_STATE_BROKEN,
1691 1.16 thorpej "BCM5700 A1" },
1692 1.16 thorpej
1693 1.16 thorpej { BGE_ASICREV_BCM5700_B0,
1694 1.26 jonathan BGE_QUIRK_LINK_STATE_BROKEN|BGE_QUIRK_CSUM_BROKEN|BGE_QUIRK_5700_COMMON,
1695 1.16 thorpej "BCM5700 B0" },
1696 1.16 thorpej
1697 1.16 thorpej { BGE_ASICREV_BCM5700_B1,
1698 1.26 jonathan BGE_QUIRK_LINK_STATE_BROKEN|BGE_QUIRK_5700_COMMON,
1699 1.16 thorpej "BCM5700 B1" },
1700 1.16 thorpej
1701 1.16 thorpej { BGE_ASICREV_BCM5700_B2,
1702 1.26 jonathan BGE_QUIRK_LINK_STATE_BROKEN|BGE_QUIRK_5700_COMMON,
1703 1.16 thorpej "BCM5700 B2" },
1704 1.16 thorpej
1705 1.17 thorpej /* This is treated like a BCM5700 Bx */
1706 1.16 thorpej { BGE_ASICREV_BCM5700_ALTIMA,
1707 1.26 jonathan BGE_QUIRK_LINK_STATE_BROKEN|BGE_QUIRK_5700_COMMON,
1708 1.16 thorpej "BCM5700 Altima" },
1709 1.16 thorpej
1710 1.16 thorpej { BGE_ASICREV_BCM5700_C0,
1711 1.16 thorpej 0,
1712 1.16 thorpej "BCM5700 C0" },
1713 1.16 thorpej
1714 1.16 thorpej { BGE_ASICREV_BCM5701_A0,
1715 1.37 jonathan 0, /*XXX really, just not known */
1716 1.16 thorpej "BCM5701 A0" },
1717 1.16 thorpej
1718 1.16 thorpej { BGE_ASICREV_BCM5701_B0,
1719 1.37 jonathan BGE_QUIRK_PCIX_DMA_ALIGN_BUG,
1720 1.16 thorpej "BCM5701 B0" },
1721 1.16 thorpej
1722 1.16 thorpej { BGE_ASICREV_BCM5701_B2,
1723 1.37 jonathan BGE_QUIRK_PCIX_DMA_ALIGN_BUG,
1724 1.16 thorpej "BCM5701 B2" },
1725 1.16 thorpej
1726 1.16 thorpej { BGE_ASICREV_BCM5701_B5,
1727 1.37 jonathan BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_PCIX_DMA_ALIGN_BUG,
1728 1.16 thorpej "BCM5701 B5" },
1729 1.16 thorpej
1730 1.16 thorpej { BGE_ASICREV_BCM5703_A0,
1731 1.16 thorpej 0,
1732 1.16 thorpej "BCM5703 A0" },
1733 1.16 thorpej
1734 1.16 thorpej { BGE_ASICREV_BCM5703_A1,
1735 1.16 thorpej 0,
1736 1.16 thorpej "BCM5703 A1" },
1737 1.16 thorpej
1738 1.16 thorpej { BGE_ASICREV_BCM5703_A2,
1739 1.24 matt BGE_QUIRK_ONLY_PHY_1,
1740 1.16 thorpej "BCM5703 A2" },
1741 1.16 thorpej
1742 1.25 jonathan { BGE_ASICREV_BCM5704_A0,
1743 1.25 jonathan BGE_QUIRK_ONLY_PHY_1,
1744 1.25 jonathan "BCM5704 A0" },
1745 1.40 fvdl
1746 1.40 fvdl { BGE_ASICREV_BCM5704_A1,
1747 1.40 fvdl BGE_QUIRK_ONLY_PHY_1,
1748 1.40 fvdl "BCM5704 A1" },
1749 1.40 fvdl
1750 1.40 fvdl { BGE_ASICREV_BCM5704_A2,
1751 1.40 fvdl BGE_QUIRK_ONLY_PHY_1,
1752 1.40 fvdl "BCM5704 A2" },
1753 1.25 jonathan
1754 1.44 hannken { BGE_ASICREV_BCM5705_A1,
1755 1.44 hannken BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_5705_CORE,
1756 1.44 hannken "BCM5705 A1" },
1757 1.44 hannken
1758 1.16 thorpej { 0, 0, NULL }
1759 1.16 thorpej };
1760 1.16 thorpej
1761 1.16 thorpej static const struct bge_revision *
1762 1.16 thorpej bge_lookup_rev(uint32_t asicrev)
1763 1.16 thorpej {
1764 1.16 thorpej const struct bge_revision *br;
1765 1.16 thorpej
1766 1.16 thorpej for (br = bge_revisions; br->br_name != NULL; br++) {
1767 1.16 thorpej if (br->br_asicrev == asicrev)
1768 1.16 thorpej return (br);
1769 1.16 thorpej }
1770 1.16 thorpej
1771 1.16 thorpej return (NULL);
1772 1.16 thorpej }
1773 1.16 thorpej
1774 1.7 thorpej static const struct bge_product {
1775 1.7 thorpej pci_vendor_id_t bp_vendor;
1776 1.7 thorpej pci_product_id_t bp_product;
1777 1.7 thorpej const char *bp_name;
1778 1.7 thorpej } bge_products[] = {
1779 1.7 thorpej /*
1780 1.7 thorpej * The BCM5700 documentation seems to indicate that the hardware
1781 1.7 thorpej * still has the Alteon vendor ID burned into it, though it
1782 1.7 thorpej * should always be overridden by the value in the EEPROM. We'll
1783 1.7 thorpej * check for it anyway.
1784 1.7 thorpej */
1785 1.7 thorpej { PCI_VENDOR_ALTEON,
1786 1.7 thorpej PCI_PRODUCT_ALTEON_BCM5700,
1787 1.7 thorpej "Broadcom BCM5700 Gigabit Ethernet" },
1788 1.7 thorpej { PCI_VENDOR_ALTEON,
1789 1.7 thorpej PCI_PRODUCT_ALTEON_BCM5701,
1790 1.7 thorpej "Broadcom BCM5701 Gigabit Ethernet" },
1791 1.7 thorpej
1792 1.7 thorpej { PCI_VENDOR_ALTIMA,
1793 1.7 thorpej PCI_PRODUCT_ALTIMA_AC1000,
1794 1.7 thorpej "Altima AC1000 Gigabit Ethernet" },
1795 1.14 enami { PCI_VENDOR_ALTIMA,
1796 1.14 enami PCI_PRODUCT_ALTIMA_AC1001,
1797 1.14 enami "Altima AC1001 Gigabit Ethernet" },
1798 1.7 thorpej { PCI_VENDOR_ALTIMA,
1799 1.7 thorpej PCI_PRODUCT_ALTIMA_AC9100,
1800 1.7 thorpej "Altima AC9100 Gigabit Ethernet" },
1801 1.7 thorpej
1802 1.7 thorpej { PCI_VENDOR_BROADCOM,
1803 1.7 thorpej PCI_PRODUCT_BROADCOM_BCM5700,
1804 1.7 thorpej "Broadcom BCM5700 Gigabit Ethernet" },
1805 1.7 thorpej { PCI_VENDOR_BROADCOM,
1806 1.7 thorpej PCI_PRODUCT_BROADCOM_BCM5701,
1807 1.24 matt "Broadcom BCM5701 Gigabit Ethernet" },
1808 1.24 matt { PCI_VENDOR_BROADCOM,
1809 1.24 matt PCI_PRODUCT_BROADCOM_BCM5702,
1810 1.24 matt "Broadcom BCM5702 Gigabit Ethernet" },
1811 1.24 matt { PCI_VENDOR_BROADCOM,
1812 1.24 matt PCI_PRODUCT_BROADCOM_BCM5702X,
1813 1.24 matt "Broadcom BCM5702X Gigabit Ethernet" },
1814 1.24 matt { PCI_VENDOR_BROADCOM,
1815 1.24 matt PCI_PRODUCT_BROADCOM_BCM5703,
1816 1.24 matt "Broadcom BCM5703 Gigabit Ethernet" },
1817 1.24 matt { PCI_VENDOR_BROADCOM,
1818 1.24 matt PCI_PRODUCT_BROADCOM_BCM5703X,
1819 1.24 matt "Broadcom BCM5703X Gigabit Ethernet" },
1820 1.25 jonathan { PCI_VENDOR_BROADCOM,
1821 1.25 jonathan PCI_PRODUCT_BROADCOM_BCM5704C,
1822 1.25 jonathan "Broadcom BCM5704C Dual Gigabit Ethernet" },
1823 1.25 jonathan { PCI_VENDOR_BROADCOM,
1824 1.25 jonathan PCI_PRODUCT_BROADCOM_BCM5704S,
1825 1.25 jonathan "Broadcom BCM5704S Dual Gigabit Ethernet" },
1826 1.44 hannken { PCI_VENDOR_BROADCOM,
1827 1.44 hannken PCI_PRODUCT_BROADCOM_BCM5705M,
1828 1.44 hannken "Broadcom BCM5705M Gigabit Ethernet" },
1829 1.7 thorpej
1830 1.7 thorpej { PCI_VENDOR_SCHNEIDERKOCH,
1831 1.7 thorpej PCI_PRODUCT_SCHNEIDERKOCH_SK_9DX1,
1832 1.8 thorpej "SysKonnect SK-9Dx1 Gigabit Ethernet" },
1833 1.7 thorpej
1834 1.7 thorpej { PCI_VENDOR_3COM,
1835 1.7 thorpej PCI_PRODUCT_3COM_3C996,
1836 1.7 thorpej "3Com 3c996 Gigabit Ethernet" },
1837 1.7 thorpej
1838 1.7 thorpej { 0,
1839 1.7 thorpej 0,
1840 1.7 thorpej NULL },
1841 1.7 thorpej };
1842 1.7 thorpej
1843 1.7 thorpej static const struct bge_product *
1844 1.7 thorpej bge_lookup(const struct pci_attach_args *pa)
1845 1.7 thorpej {
1846 1.7 thorpej const struct bge_product *bp;
1847 1.7 thorpej
1848 1.7 thorpej for (bp = bge_products; bp->bp_name != NULL; bp++) {
1849 1.7 thorpej if (PCI_VENDOR(pa->pa_id) == bp->bp_vendor &&
1850 1.7 thorpej PCI_PRODUCT(pa->pa_id) == bp->bp_product)
1851 1.7 thorpej return (bp);
1852 1.7 thorpej }
1853 1.7 thorpej
1854 1.7 thorpej return (NULL);
1855 1.7 thorpej }
1856 1.7 thorpej
1857 1.25 jonathan int
1858 1.25 jonathan bge_setpowerstate(sc, powerlevel)
1859 1.25 jonathan struct bge_softc *sc;
1860 1.25 jonathan int powerlevel;
1861 1.25 jonathan {
1862 1.25 jonathan #ifdef NOTYET
1863 1.25 jonathan u_int32_t pm_ctl = 0;
1864 1.25 jonathan
1865 1.25 jonathan /* XXX FIXME: make sure indirect accesses enabled? */
1866 1.25 jonathan pm_ctl = pci_conf_read(sc->bge_dev, BGE_PCI_MISC_CTL, 4);
1867 1.25 jonathan pm_ctl |= BGE_PCIMISCCTL_INDIRECT_ACCESS;
1868 1.25 jonathan pci_write_config(sc->bge_dev, BGE_PCI_MISC_CTL, pm_ctl, 4);
1869 1.25 jonathan
1870 1.25 jonathan /* clear the PME_assert bit and power state bits, enable PME */
1871 1.25 jonathan pm_ctl = pci_conf_read(sc->bge_dev, BGE_PCI_PWRMGMT_CMD, 2);
1872 1.25 jonathan pm_ctl &= ~PCIM_PSTAT_DMASK;
1873 1.25 jonathan pm_ctl |= (1 << 8);
1874 1.25 jonathan
1875 1.25 jonathan if (powerlevel == 0) {
1876 1.25 jonathan pm_ctl |= PCIM_PSTAT_D0;
1877 1.25 jonathan pci_write_config(sc->bge_dev, BGE_PCI_PWRMGMT_CMD,
1878 1.25 jonathan pm_ctl, 2);
1879 1.25 jonathan DELAY(10000);
1880 1.27 jonathan CSR_WRITE_4(sc, BGE_MISC_LOCAL_CTL, sc->bge_local_ctrl_reg);
1881 1.25 jonathan DELAY(10000);
1882 1.25 jonathan
1883 1.25 jonathan #ifdef NOTYET
1884 1.25 jonathan /* XXX FIXME: write 0x02 to phy aux_Ctrl reg */
1885 1.25 jonathan bge_miibus_writereg(sc->bge_dev, 1, 0x18, 0x02);
1886 1.25 jonathan #endif
1887 1.25 jonathan DELAY(40); DELAY(40); DELAY(40);
1888 1.25 jonathan DELAY(10000); /* above not quite adequate on 5700 */
1889 1.25 jonathan return 0;
1890 1.25 jonathan }
1891 1.25 jonathan
1892 1.25 jonathan
1893 1.25 jonathan /*
1894 1.25 jonathan * Entering ACPI power states D1-D3 is achieved by wiggling
1895 1.25 jonathan * GMII gpio pins. Example code assumes all hardware vendors
1896 1.25 jonathan * followed Broadom's sample pcb layout. Until we verify that
1897 1.25 jonathan * for all supported OEM cards, states D1-D3 are unsupported.
1898 1.25 jonathan */
1899 1.25 jonathan printf("%s: power state %d unimplemented; check GPIO pins\n",
1900 1.25 jonathan sc->bge_dev.dv_xname, powerlevel);
1901 1.25 jonathan #endif
1902 1.25 jonathan return EOPNOTSUPP;
1903 1.25 jonathan }
1904 1.25 jonathan
1905 1.25 jonathan
1906 1.1 fvdl /*
1907 1.1 fvdl * Probe for a Broadcom chip. Check the PCI vendor and device IDs
1908 1.1 fvdl * against our list and return its name if we find a match. Note
1909 1.1 fvdl * that since the Broadcom controller contains VPD support, we
1910 1.1 fvdl * can get the device name string from the controller itself instead
1911 1.1 fvdl * of the compiled-in string. This is a little slow, but it guarantees
1912 1.1 fvdl * we'll always announce the right product name.
1913 1.1 fvdl */
1914 1.1 fvdl int
1915 1.1 fvdl bge_probe(parent, match, aux)
1916 1.1 fvdl struct device *parent;
1917 1.1 fvdl struct cfdata *match;
1918 1.1 fvdl void *aux;
1919 1.1 fvdl {
1920 1.1 fvdl struct pci_attach_args *pa = (struct pci_attach_args *)aux;
1921 1.1 fvdl
1922 1.7 thorpej if (bge_lookup(pa) != NULL)
1923 1.1 fvdl return (1);
1924 1.1 fvdl
1925 1.1 fvdl return (0);
1926 1.1 fvdl }
1927 1.1 fvdl
1928 1.1 fvdl void
1929 1.1 fvdl bge_attach(parent, self, aux)
1930 1.1 fvdl struct device *parent, *self;
1931 1.1 fvdl void *aux;
1932 1.1 fvdl {
1933 1.1 fvdl struct bge_softc *sc = (struct bge_softc *)self;
1934 1.1 fvdl struct pci_attach_args *pa = aux;
1935 1.7 thorpej const struct bge_product *bp;
1936 1.16 thorpej const struct bge_revision *br;
1937 1.1 fvdl pci_chipset_tag_t pc = pa->pa_pc;
1938 1.1 fvdl pci_intr_handle_t ih;
1939 1.1 fvdl const char *intrstr = NULL;
1940 1.1 fvdl bus_dma_segment_t seg;
1941 1.1 fvdl int rseg;
1942 1.1 fvdl u_int32_t hwcfg = 0;
1943 1.24 matt u_int32_t mac_addr = 0;
1944 1.1 fvdl u_int32_t command;
1945 1.1 fvdl struct ifnet *ifp;
1946 1.1 fvdl caddr_t kva;
1947 1.1 fvdl u_char eaddr[ETHER_ADDR_LEN];
1948 1.1 fvdl pcireg_t memtype;
1949 1.1 fvdl bus_addr_t memaddr;
1950 1.1 fvdl bus_size_t memsize;
1951 1.25 jonathan u_int32_t pm_ctl;
1952 1.25 jonathan
1953 1.7 thorpej bp = bge_lookup(pa);
1954 1.7 thorpej KASSERT(bp != NULL);
1955 1.7 thorpej
1956 1.1 fvdl sc->bge_pa = *pa;
1957 1.1 fvdl
1958 1.30 thorpej aprint_naive(": Ethernet controller\n");
1959 1.30 thorpej aprint_normal(": %s\n", bp->bp_name);
1960 1.1 fvdl
1961 1.1 fvdl /*
1962 1.1 fvdl * Map control/status registers.
1963 1.1 fvdl */
1964 1.1 fvdl DPRINTFN(5, ("Map control/status regs\n"));
1965 1.1 fvdl command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG);
1966 1.1 fvdl command |= PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_MASTER_ENABLE;
1967 1.1 fvdl pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, command);
1968 1.1 fvdl command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG);
1969 1.1 fvdl
1970 1.1 fvdl if (!(command & PCI_COMMAND_MEM_ENABLE)) {
1971 1.30 thorpej aprint_error("%s: failed to enable memory mapping!\n",
1972 1.1 fvdl sc->bge_dev.dv_xname);
1973 1.1 fvdl return;
1974 1.1 fvdl }
1975 1.1 fvdl
1976 1.1 fvdl DPRINTFN(5, ("pci_mem_find\n"));
1977 1.1 fvdl memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, BGE_PCI_BAR0);
1978 1.1 fvdl switch (memtype) {
1979 1.29 itojun case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT:
1980 1.29 itojun case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT:
1981 1.1 fvdl if (pci_mapreg_map(pa, BGE_PCI_BAR0,
1982 1.29 itojun memtype, 0, &sc->bge_btag, &sc->bge_bhandle,
1983 1.1 fvdl &memaddr, &memsize) == 0)
1984 1.1 fvdl break;
1985 1.1 fvdl default:
1986 1.30 thorpej aprint_error("%s: can't find mem space\n",
1987 1.1 fvdl sc->bge_dev.dv_xname);
1988 1.1 fvdl return;
1989 1.1 fvdl }
1990 1.1 fvdl
1991 1.1 fvdl DPRINTFN(5, ("pci_intr_map\n"));
1992 1.1 fvdl if (pci_intr_map(pa, &ih)) {
1993 1.30 thorpej aprint_error("%s: couldn't map interrupt\n",
1994 1.1 fvdl sc->bge_dev.dv_xname);
1995 1.1 fvdl return;
1996 1.1 fvdl }
1997 1.1 fvdl
1998 1.1 fvdl DPRINTFN(5, ("pci_intr_string\n"));
1999 1.1 fvdl intrstr = pci_intr_string(pc, ih);
2000 1.1 fvdl
2001 1.1 fvdl DPRINTFN(5, ("pci_intr_establish\n"));
2002 1.1 fvdl sc->bge_intrhand = pci_intr_establish(pc, ih, IPL_NET, bge_intr, sc);
2003 1.1 fvdl
2004 1.1 fvdl if (sc->bge_intrhand == NULL) {
2005 1.30 thorpej aprint_error("%s: couldn't establish interrupt",
2006 1.1 fvdl sc->bge_dev.dv_xname);
2007 1.1 fvdl if (intrstr != NULL)
2008 1.30 thorpej aprint_normal(" at %s", intrstr);
2009 1.30 thorpej aprint_normal("\n");
2010 1.1 fvdl return;
2011 1.1 fvdl }
2012 1.30 thorpej aprint_normal("%s: interrupting at %s\n",
2013 1.30 thorpej sc->bge_dev.dv_xname, intrstr);
2014 1.1 fvdl
2015 1.25 jonathan /*
2016 1.25 jonathan * Kludge for 5700 Bx bug: a hardware bug (PCIX byte enable?)
2017 1.25 jonathan * can clobber the chip's PCI config-space power control registers,
2018 1.25 jonathan * leaving the card in D3 powersave state.
2019 1.25 jonathan * We do not have memory-mapped registers in this state,
2020 1.25 jonathan * so force device into D0 state before starting initialization.
2021 1.25 jonathan */
2022 1.25 jonathan pm_ctl = pci_conf_read(pc, pa->pa_tag, BGE_PCI_PWRMGMT_CMD);
2023 1.25 jonathan pm_ctl &= ~(PCI_PWR_D0|PCI_PWR_D1|PCI_PWR_D2|PCI_PWR_D3);
2024 1.25 jonathan pm_ctl |= (1 << 8) | PCI_PWR_D0 ; /* D0 state */
2025 1.25 jonathan pci_conf_write(pc, pa->pa_tag, BGE_PCI_PWRMGMT_CMD, pm_ctl);
2026 1.25 jonathan DELAY(1000); /* 27 usec is allegedly sufficent */
2027 1.25 jonathan
2028 1.1 fvdl /* Try to reset the chip. */
2029 1.1 fvdl DPRINTFN(5, ("bge_reset\n"));
2030 1.1 fvdl bge_reset(sc);
2031 1.1 fvdl
2032 1.1 fvdl if (bge_chipinit(sc)) {
2033 1.30 thorpej aprint_error("%s: chip initialization failed\n",
2034 1.1 fvdl sc->bge_dev.dv_xname);
2035 1.1 fvdl bge_release_resources(sc);
2036 1.1 fvdl return;
2037 1.1 fvdl }
2038 1.1 fvdl
2039 1.1 fvdl /*
2040 1.1 fvdl * Get station address from the EEPROM.
2041 1.1 fvdl */
2042 1.24 matt mac_addr = bge_readmem_ind(sc, 0x0c14);
2043 1.24 matt if ((mac_addr >> 16) == 0x484b) {
2044 1.24 matt eaddr[0] = (u_char)(mac_addr >> 8);
2045 1.24 matt eaddr[1] = (u_char)(mac_addr >> 0);
2046 1.24 matt mac_addr = bge_readmem_ind(sc, 0x0c18);
2047 1.24 matt eaddr[2] = (u_char)(mac_addr >> 24);
2048 1.24 matt eaddr[3] = (u_char)(mac_addr >> 16);
2049 1.24 matt eaddr[4] = (u_char)(mac_addr >> 8);
2050 1.24 matt eaddr[5] = (u_char)(mac_addr >> 0);
2051 1.24 matt } else if (bge_read_eeprom(sc, (caddr_t)eaddr,
2052 1.1 fvdl BGE_EE_MAC_OFFSET + 2, ETHER_ADDR_LEN)) {
2053 1.30 thorpej aprint_error("%s: failed to read station address\n",
2054 1.23 kristerw sc->bge_dev.dv_xname);
2055 1.1 fvdl bge_release_resources(sc);
2056 1.1 fvdl return;
2057 1.1 fvdl }
2058 1.1 fvdl
2059 1.1 fvdl /*
2060 1.16 thorpej * Save ASIC rev. Look up any quirks associated with this
2061 1.16 thorpej * ASIC.
2062 1.1 fvdl */
2063 1.16 thorpej sc->bge_asicrev =
2064 1.16 thorpej pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_MISC_CTL) &
2065 1.16 thorpej BGE_PCIMISCCTL_ASICREV;
2066 1.16 thorpej br = bge_lookup_rev(sc->bge_asicrev);
2067 1.16 thorpej
2068 1.30 thorpej aprint_normal("%s: ", sc->bge_dev.dv_xname);
2069 1.16 thorpej if (br == NULL) {
2070 1.30 thorpej aprint_normal("unknown ASIC 0x%08x", sc->bge_asicrev);
2071 1.16 thorpej sc->bge_quirks = 0;
2072 1.16 thorpej } else {
2073 1.30 thorpej aprint_normal("ASIC %s", br->br_name);
2074 1.16 thorpej sc->bge_quirks = br->br_quirks;
2075 1.16 thorpej }
2076 1.30 thorpej aprint_normal(", Ethernet address %s\n", ether_sprintf(eaddr));
2077 1.1 fvdl
2078 1.1 fvdl /* Allocate the general information block and ring buffers. */
2079 1.41 fvdl if (pci_dma64_available(pa))
2080 1.41 fvdl sc->bge_dmatag = pa->pa_dmat64;
2081 1.41 fvdl else
2082 1.41 fvdl sc->bge_dmatag = pa->pa_dmat;
2083 1.1 fvdl DPRINTFN(5, ("bus_dmamem_alloc\n"));
2084 1.1 fvdl if (bus_dmamem_alloc(sc->bge_dmatag, sizeof(struct bge_ring_data),
2085 1.1 fvdl PAGE_SIZE, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) {
2086 1.30 thorpej aprint_error("%s: can't alloc rx buffers\n",
2087 1.30 thorpej sc->bge_dev.dv_xname);
2088 1.1 fvdl return;
2089 1.1 fvdl }
2090 1.1 fvdl DPRINTFN(5, ("bus_dmamem_map\n"));
2091 1.1 fvdl if (bus_dmamem_map(sc->bge_dmatag, &seg, rseg,
2092 1.1 fvdl sizeof(struct bge_ring_data), &kva,
2093 1.1 fvdl BUS_DMA_NOWAIT)) {
2094 1.39 wiz aprint_error("%s: can't map DMA buffers (%d bytes)\n",
2095 1.1 fvdl sc->bge_dev.dv_xname, (int)sizeof(struct bge_ring_data));
2096 1.1 fvdl bus_dmamem_free(sc->bge_dmatag, &seg, rseg);
2097 1.1 fvdl return;
2098 1.1 fvdl }
2099 1.1 fvdl DPRINTFN(5, ("bus_dmamem_create\n"));
2100 1.1 fvdl if (bus_dmamap_create(sc->bge_dmatag, sizeof(struct bge_ring_data), 1,
2101 1.1 fvdl sizeof(struct bge_ring_data), 0,
2102 1.1 fvdl BUS_DMA_NOWAIT, &sc->bge_ring_map)) {
2103 1.39 wiz aprint_error("%s: can't create DMA map\n",
2104 1.30 thorpej sc->bge_dev.dv_xname);
2105 1.1 fvdl bus_dmamem_unmap(sc->bge_dmatag, kva,
2106 1.1 fvdl sizeof(struct bge_ring_data));
2107 1.1 fvdl bus_dmamem_free(sc->bge_dmatag, &seg, rseg);
2108 1.1 fvdl return;
2109 1.1 fvdl }
2110 1.1 fvdl DPRINTFN(5, ("bus_dmamem_load\n"));
2111 1.1 fvdl if (bus_dmamap_load(sc->bge_dmatag, sc->bge_ring_map, kva,
2112 1.1 fvdl sizeof(struct bge_ring_data), NULL,
2113 1.1 fvdl BUS_DMA_NOWAIT)) {
2114 1.1 fvdl bus_dmamap_destroy(sc->bge_dmatag, sc->bge_ring_map);
2115 1.1 fvdl bus_dmamem_unmap(sc->bge_dmatag, kva,
2116 1.1 fvdl sizeof(struct bge_ring_data));
2117 1.1 fvdl bus_dmamem_free(sc->bge_dmatag, &seg, rseg);
2118 1.1 fvdl return;
2119 1.1 fvdl }
2120 1.1 fvdl
2121 1.1 fvdl DPRINTFN(5, ("bzero\n"));
2122 1.1 fvdl sc->bge_rdata = (struct bge_ring_data *)kva;
2123 1.1 fvdl
2124 1.19 mjl memset(sc->bge_rdata, 0, sizeof(struct bge_ring_data));
2125 1.1 fvdl
2126 1.1 fvdl /* Try to allocate memory for jumbo buffers. */
2127 1.44 hannken if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) {
2128 1.44 hannken if (bge_alloc_jumbo_mem(sc)) {
2129 1.44 hannken aprint_error("%s: jumbo buffer allocation failed\n",
2130 1.44 hannken sc->bge_dev.dv_xname);
2131 1.44 hannken } else
2132 1.44 hannken sc->ethercom.ec_capabilities |= ETHERCAP_JUMBO_MTU;
2133 1.44 hannken }
2134 1.1 fvdl
2135 1.1 fvdl /* Set default tuneable values. */
2136 1.1 fvdl sc->bge_stat_ticks = BGE_TICKS_PER_SEC;
2137 1.1 fvdl sc->bge_rx_coal_ticks = 150;
2138 1.25 jonathan sc->bge_rx_max_coal_bds = 64;
2139 1.25 jonathan #ifdef ORIG_WPAUL_VALUES
2140 1.1 fvdl sc->bge_tx_coal_ticks = 150;
2141 1.1 fvdl sc->bge_tx_max_coal_bds = 128;
2142 1.25 jonathan #else
2143 1.25 jonathan sc->bge_tx_coal_ticks = 300;
2144 1.25 jonathan sc->bge_tx_max_coal_bds = 400;
2145 1.25 jonathan #endif
2146 1.1 fvdl
2147 1.1 fvdl /* Set up ifnet structure */
2148 1.1 fvdl ifp = &sc->ethercom.ec_if;
2149 1.1 fvdl ifp->if_softc = sc;
2150 1.1 fvdl ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
2151 1.1 fvdl ifp->if_ioctl = bge_ioctl;
2152 1.1 fvdl ifp->if_start = bge_start;
2153 1.1 fvdl ifp->if_init = bge_init;
2154 1.1 fvdl ifp->if_watchdog = bge_watchdog;
2155 1.42 ragge IFQ_SET_MAXLEN(&ifp->if_snd, max(BGE_TX_RING_CNT - 1, IFQ_MAXLEN));
2156 1.1 fvdl IFQ_SET_READY(&ifp->if_snd);
2157 1.1 fvdl DPRINTFN(5, ("bcopy\n"));
2158 1.1 fvdl strcpy(ifp->if_xname, sc->bge_dev.dv_xname);
2159 1.1 fvdl
2160 1.18 thorpej if ((sc->bge_quirks & BGE_QUIRK_CSUM_BROKEN) == 0)
2161 1.18 thorpej sc->ethercom.ec_if.if_capabilities |=
2162 1.18 thorpej IFCAP_CSUM_IPv4 | IFCAP_CSUM_TCPv4 | IFCAP_CSUM_UDPv4;
2163 1.1 fvdl sc->ethercom.ec_capabilities |=
2164 1.1 fvdl ETHERCAP_VLAN_HWTAGGING | ETHERCAP_VLAN_MTU;
2165 1.1 fvdl
2166 1.1 fvdl /*
2167 1.1 fvdl * Do MII setup.
2168 1.1 fvdl */
2169 1.1 fvdl DPRINTFN(5, ("mii setup\n"));
2170 1.1 fvdl sc->bge_mii.mii_ifp = ifp;
2171 1.1 fvdl sc->bge_mii.mii_readreg = bge_miibus_readreg;
2172 1.1 fvdl sc->bge_mii.mii_writereg = bge_miibus_writereg;
2173 1.1 fvdl sc->bge_mii.mii_statchg = bge_miibus_statchg;
2174 1.1 fvdl
2175 1.1 fvdl /*
2176 1.1 fvdl * Figure out what sort of media we have by checking the
2177 1.35 jonathan * hardware config word in the first 32k of NIC internal memory,
2178 1.35 jonathan * or fall back to the config word in the EEPROM. Note: on some BCM5700
2179 1.1 fvdl * cards, this value appears to be unset. If that's the
2180 1.1 fvdl * case, we have to rely on identifying the NIC by its PCI
2181 1.1 fvdl * subsystem ID, as we do below for the SysKonnect SK-9D41.
2182 1.1 fvdl */
2183 1.35 jonathan if (bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_SIG) == BGE_MAGIC_NUMBER) {
2184 1.35 jonathan hwcfg = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_NICCFG);
2185 1.35 jonathan } else {
2186 1.35 jonathan bge_read_eeprom(sc, (caddr_t)&hwcfg,
2187 1.1 fvdl BGE_EE_HWCFG_OFFSET, sizeof(hwcfg));
2188 1.35 jonathan hwcfg = be32toh(hwcfg);
2189 1.35 jonathan }
2190 1.35 jonathan if ((hwcfg & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER)
2191 1.1 fvdl sc->bge_tbi = 1;
2192 1.1 fvdl
2193 1.1 fvdl /* The SysKonnect SK-9D41 is a 1000baseSX card. */
2194 1.1 fvdl if ((pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_SUBSYS) >> 16) ==
2195 1.1 fvdl SK_SUBSYSID_9D41)
2196 1.1 fvdl sc->bge_tbi = 1;
2197 1.1 fvdl
2198 1.1 fvdl if (sc->bge_tbi) {
2199 1.1 fvdl ifmedia_init(&sc->bge_ifmedia, IFM_IMASK, bge_ifmedia_upd,
2200 1.1 fvdl bge_ifmedia_sts);
2201 1.1 fvdl ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL);
2202 1.1 fvdl ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_1000_SX|IFM_FDX,
2203 1.1 fvdl 0, NULL);
2204 1.1 fvdl ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL);
2205 1.1 fvdl ifmedia_set(&sc->bge_ifmedia, IFM_ETHER|IFM_AUTO);
2206 1.1 fvdl } else {
2207 1.1 fvdl /*
2208 1.1 fvdl * Do transceiver setup.
2209 1.1 fvdl */
2210 1.1 fvdl ifmedia_init(&sc->bge_mii.mii_media, 0, bge_ifmedia_upd,
2211 1.1 fvdl bge_ifmedia_sts);
2212 1.1 fvdl mii_attach(&sc->bge_dev, &sc->bge_mii, 0xffffffff,
2213 1.1 fvdl MII_PHY_ANY, MII_OFFSET_ANY, 0);
2214 1.1 fvdl
2215 1.1 fvdl if (LIST_FIRST(&sc->bge_mii.mii_phys) == NULL) {
2216 1.1 fvdl printf("%s: no PHY found!\n", sc->bge_dev.dv_xname);
2217 1.1 fvdl ifmedia_add(&sc->bge_mii.mii_media,
2218 1.1 fvdl IFM_ETHER|IFM_MANUAL, 0, NULL);
2219 1.1 fvdl ifmedia_set(&sc->bge_mii.mii_media,
2220 1.1 fvdl IFM_ETHER|IFM_MANUAL);
2221 1.1 fvdl } else
2222 1.1 fvdl ifmedia_set(&sc->bge_mii.mii_media,
2223 1.1 fvdl IFM_ETHER|IFM_AUTO);
2224 1.1 fvdl }
2225 1.1 fvdl
2226 1.1 fvdl /*
2227 1.37 jonathan * When using the BCM5701 in PCI-X mode, data corruption has
2228 1.37 jonathan * been observed in the first few bytes of some received packets.
2229 1.37 jonathan * Aligning the packet buffer in memory eliminates the corruption.
2230 1.37 jonathan * Unfortunately, this misaligns the packet payloads. On platforms
2231 1.37 jonathan * which do not support unaligned accesses, we will realign the
2232 1.37 jonathan * payloads by copying the received packets.
2233 1.37 jonathan */
2234 1.37 jonathan if (sc->bge_quirks & BGE_QUIRK_PCIX_DMA_ALIGN_BUG) {
2235 1.37 jonathan /* If in PCI-X mode, work around the alignment bug. */
2236 1.37 jonathan if ((pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_PCISTATE) &
2237 1.37 jonathan (BGE_PCISTATE_PCI_BUSMODE | BGE_PCISTATE_PCI_BUSSPEED)) ==
2238 1.37 jonathan BGE_PCISTATE_PCI_BUSSPEED)
2239 1.37 jonathan sc->bge_rx_alignment_bug = 1;
2240 1.37 jonathan }
2241 1.37 jonathan
2242 1.37 jonathan /*
2243 1.1 fvdl * Call MI attach routine.
2244 1.1 fvdl */
2245 1.1 fvdl DPRINTFN(5, ("if_attach\n"));
2246 1.1 fvdl if_attach(ifp);
2247 1.1 fvdl DPRINTFN(5, ("ether_ifattach\n"));
2248 1.1 fvdl ether_ifattach(ifp, eaddr);
2249 1.1 fvdl DPRINTFN(5, ("callout_init\n"));
2250 1.1 fvdl callout_init(&sc->bge_timeout);
2251 1.1 fvdl }
2252 1.1 fvdl
2253 1.1 fvdl void
2254 1.1 fvdl bge_release_resources(sc)
2255 1.1 fvdl struct bge_softc *sc;
2256 1.1 fvdl {
2257 1.1 fvdl if (sc->bge_vpd_prodname != NULL)
2258 1.1 fvdl free(sc->bge_vpd_prodname, M_DEVBUF);
2259 1.1 fvdl
2260 1.1 fvdl if (sc->bge_vpd_readonly != NULL)
2261 1.1 fvdl free(sc->bge_vpd_readonly, M_DEVBUF);
2262 1.1 fvdl }
2263 1.1 fvdl
2264 1.1 fvdl void
2265 1.1 fvdl bge_reset(sc)
2266 1.1 fvdl struct bge_softc *sc;
2267 1.1 fvdl {
2268 1.1 fvdl struct pci_attach_args *pa = &sc->bge_pa;
2269 1.1 fvdl u_int32_t cachesize, command, pcistate;
2270 1.1 fvdl int i, val = 0;
2271 1.1 fvdl
2272 1.1 fvdl /* Save some important PCI state. */
2273 1.1 fvdl cachesize = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_CACHESZ);
2274 1.1 fvdl command = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_CMD);
2275 1.1 fvdl pcistate = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_PCISTATE);
2276 1.1 fvdl
2277 1.1 fvdl pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_MISC_CTL,
2278 1.1 fvdl BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR|
2279 1.1 fvdl BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_PCISTATE_RW);
2280 1.1 fvdl
2281 1.1 fvdl /* Issue global reset */
2282 1.1 fvdl bge_writereg_ind(sc, BGE_MISC_CFG,
2283 1.1 fvdl BGE_MISCCFG_RESET_CORE_CLOCKS|(65<<1));
2284 1.1 fvdl
2285 1.1 fvdl DELAY(1000);
2286 1.1 fvdl
2287 1.1 fvdl /* Reset some of the PCI state that got zapped by reset */
2288 1.1 fvdl pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_MISC_CTL,
2289 1.1 fvdl BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR|
2290 1.1 fvdl BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_PCISTATE_RW);
2291 1.1 fvdl pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_CMD, command);
2292 1.1 fvdl pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_CACHESZ, cachesize);
2293 1.1 fvdl bge_writereg_ind(sc, BGE_MISC_CFG, (65 << 1));
2294 1.1 fvdl
2295 1.1 fvdl /* Enable memory arbiter. */
2296 1.44 hannken if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) {
2297 1.44 hannken CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE);
2298 1.44 hannken }
2299 1.1 fvdl
2300 1.1 fvdl /*
2301 1.1 fvdl * Prevent PXE restart: write a magic number to the
2302 1.1 fvdl * general communications memory at 0xB50.
2303 1.1 fvdl */
2304 1.1 fvdl bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM, BGE_MAGIC_NUMBER);
2305 1.1 fvdl
2306 1.1 fvdl /*
2307 1.1 fvdl * Poll the value location we just wrote until
2308 1.1 fvdl * we see the 1's complement of the magic number.
2309 1.1 fvdl * This indicates that the firmware initialization
2310 1.1 fvdl * is complete.
2311 1.1 fvdl */
2312 1.1 fvdl for (i = 0; i < 750; i++) {
2313 1.1 fvdl val = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM);
2314 1.1 fvdl if (val == ~BGE_MAGIC_NUMBER)
2315 1.1 fvdl break;
2316 1.1 fvdl DELAY(1000);
2317 1.1 fvdl }
2318 1.1 fvdl
2319 1.8 thorpej if (i == 750) {
2320 1.1 fvdl printf("%s: firmware handshake timed out, val = %x\n",
2321 1.1 fvdl sc->bge_dev.dv_xname, val);
2322 1.1 fvdl return;
2323 1.1 fvdl }
2324 1.1 fvdl
2325 1.1 fvdl /*
2326 1.1 fvdl * XXX Wait for the value of the PCISTATE register to
2327 1.1 fvdl * return to its original pre-reset state. This is a
2328 1.1 fvdl * fairly good indicator of reset completion. If we don't
2329 1.1 fvdl * wait for the reset to fully complete, trying to read
2330 1.1 fvdl * from the device's non-PCI registers may yield garbage
2331 1.1 fvdl * results.
2332 1.1 fvdl */
2333 1.1 fvdl for (i = 0; i < BGE_TIMEOUT; i++) {
2334 1.1 fvdl if (pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_PCISTATE) ==
2335 1.1 fvdl pcistate)
2336 1.1 fvdl break;
2337 1.1 fvdl DELAY(10);
2338 1.1 fvdl }
2339 1.1 fvdl
2340 1.1 fvdl /* Enable memory arbiter. */
2341 1.44 hannken if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) {
2342 1.44 hannken CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE);
2343 1.44 hannken }
2344 1.1 fvdl
2345 1.1 fvdl /* Fix up byte swapping */
2346 1.1 fvdl CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS);
2347 1.1 fvdl
2348 1.1 fvdl CSR_WRITE_4(sc, BGE_MAC_MODE, 0);
2349 1.1 fvdl
2350 1.1 fvdl DELAY(10000);
2351 1.1 fvdl }
2352 1.1 fvdl
2353 1.1 fvdl /*
2354 1.1 fvdl * Frame reception handling. This is called if there's a frame
2355 1.1 fvdl * on the receive return list.
2356 1.1 fvdl *
2357 1.1 fvdl * Note: we have to be able to handle two possibilities here:
2358 1.1 fvdl * 1) the frame is from the jumbo recieve ring
2359 1.1 fvdl * 2) the frame is from the standard receive ring
2360 1.1 fvdl */
2361 1.1 fvdl
2362 1.1 fvdl void
2363 1.1 fvdl bge_rxeof(sc)
2364 1.1 fvdl struct bge_softc *sc;
2365 1.1 fvdl {
2366 1.1 fvdl struct ifnet *ifp;
2367 1.1 fvdl int stdcnt = 0, jumbocnt = 0;
2368 1.1 fvdl int have_tag = 0;
2369 1.1 fvdl u_int16_t vlan_tag = 0;
2370 1.1 fvdl bus_dmamap_t dmamap;
2371 1.1 fvdl bus_addr_t offset, toff;
2372 1.1 fvdl bus_size_t tlen;
2373 1.1 fvdl int tosync;
2374 1.1 fvdl
2375 1.1 fvdl ifp = &sc->ethercom.ec_if;
2376 1.1 fvdl
2377 1.1 fvdl bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map,
2378 1.1 fvdl offsetof(struct bge_ring_data, bge_status_block),
2379 1.1 fvdl sizeof (struct bge_status_block),
2380 1.1 fvdl BUS_DMASYNC_POSTREAD);
2381 1.1 fvdl
2382 1.1 fvdl offset = offsetof(struct bge_ring_data, bge_rx_return_ring);
2383 1.1 fvdl tosync = sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx -
2384 1.1 fvdl sc->bge_rx_saved_considx;
2385 1.1 fvdl
2386 1.1 fvdl toff = offset + (sc->bge_rx_saved_considx * sizeof (struct bge_rx_bd));
2387 1.1 fvdl
2388 1.1 fvdl if (tosync < 0) {
2389 1.44 hannken tlen = (sc->bge_return_ring_cnt - sc->bge_rx_saved_considx) *
2390 1.1 fvdl sizeof (struct bge_rx_bd);
2391 1.1 fvdl bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map,
2392 1.1 fvdl toff, tlen, BUS_DMASYNC_POSTREAD);
2393 1.1 fvdl tosync = -tosync;
2394 1.1 fvdl }
2395 1.1 fvdl
2396 1.1 fvdl bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map,
2397 1.1 fvdl offset, tosync * sizeof (struct bge_rx_bd),
2398 1.1 fvdl BUS_DMASYNC_POSTREAD);
2399 1.1 fvdl
2400 1.1 fvdl while(sc->bge_rx_saved_considx !=
2401 1.1 fvdl sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx) {
2402 1.1 fvdl struct bge_rx_bd *cur_rx;
2403 1.1 fvdl u_int32_t rxidx;
2404 1.1 fvdl struct mbuf *m = NULL;
2405 1.1 fvdl
2406 1.1 fvdl cur_rx = &sc->bge_rdata->
2407 1.1 fvdl bge_rx_return_ring[sc->bge_rx_saved_considx];
2408 1.1 fvdl
2409 1.1 fvdl rxidx = cur_rx->bge_idx;
2410 1.44 hannken BGE_INC(sc->bge_rx_saved_considx, sc->bge_return_ring_cnt);
2411 1.1 fvdl
2412 1.1 fvdl if (cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) {
2413 1.1 fvdl have_tag = 1;
2414 1.1 fvdl vlan_tag = cur_rx->bge_vlan_tag;
2415 1.1 fvdl }
2416 1.1 fvdl
2417 1.1 fvdl if (cur_rx->bge_flags & BGE_RXBDFLAG_JUMBO_RING) {
2418 1.1 fvdl BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT);
2419 1.1 fvdl m = sc->bge_cdata.bge_rx_jumbo_chain[rxidx];
2420 1.1 fvdl sc->bge_cdata.bge_rx_jumbo_chain[rxidx] = NULL;
2421 1.1 fvdl jumbocnt++;
2422 1.1 fvdl if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) {
2423 1.1 fvdl ifp->if_ierrors++;
2424 1.1 fvdl bge_newbuf_jumbo(sc, sc->bge_jumbo, m);
2425 1.1 fvdl continue;
2426 1.1 fvdl }
2427 1.1 fvdl if (bge_newbuf_jumbo(sc, sc->bge_jumbo,
2428 1.1 fvdl NULL)== ENOBUFS) {
2429 1.1 fvdl ifp->if_ierrors++;
2430 1.1 fvdl bge_newbuf_jumbo(sc, sc->bge_jumbo, m);
2431 1.1 fvdl continue;
2432 1.1 fvdl }
2433 1.1 fvdl } else {
2434 1.1 fvdl BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT);
2435 1.1 fvdl m = sc->bge_cdata.bge_rx_std_chain[rxidx];
2436 1.1 fvdl sc->bge_cdata.bge_rx_std_chain[rxidx] = NULL;
2437 1.1 fvdl stdcnt++;
2438 1.1 fvdl dmamap = sc->bge_cdata.bge_rx_std_map[rxidx];
2439 1.1 fvdl sc->bge_cdata.bge_rx_std_map[rxidx] = 0;
2440 1.1 fvdl if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) {
2441 1.1 fvdl ifp->if_ierrors++;
2442 1.1 fvdl bge_newbuf_std(sc, sc->bge_std, m, dmamap);
2443 1.1 fvdl continue;
2444 1.1 fvdl }
2445 1.1 fvdl if (bge_newbuf_std(sc, sc->bge_std,
2446 1.1 fvdl NULL, dmamap) == ENOBUFS) {
2447 1.1 fvdl ifp->if_ierrors++;
2448 1.1 fvdl bge_newbuf_std(sc, sc->bge_std, m, dmamap);
2449 1.1 fvdl continue;
2450 1.1 fvdl }
2451 1.1 fvdl }
2452 1.1 fvdl
2453 1.1 fvdl ifp->if_ipackets++;
2454 1.37 jonathan #ifndef __NO_STRICT_ALIGNMENT
2455 1.37 jonathan /*
2456 1.37 jonathan * XXX: if the 5701 PCIX-Rx-DMA workaround is in effect,
2457 1.37 jonathan * the Rx buffer has the layer-2 header unaligned.
2458 1.37 jonathan * If our CPU requires alignment, re-align by copying.
2459 1.37 jonathan */
2460 1.37 jonathan if (sc->bge_rx_alignment_bug) {
2461 1.37 jonathan memmove(mtod(m, caddr_t) + ETHER_ALIGN, m->m_data,
2462 1.37 jonathan cur_rx->bge_len);
2463 1.37 jonathan m->m_data += ETHER_ALIGN;
2464 1.37 jonathan }
2465 1.37 jonathan #endif
2466 1.37 jonathan
2467 1.1 fvdl m->m_pkthdr.len = m->m_len = cur_rx->bge_len;
2468 1.1 fvdl m->m_pkthdr.rcvif = ifp;
2469 1.1 fvdl
2470 1.1 fvdl #if NBPFILTER > 0
2471 1.1 fvdl /*
2472 1.1 fvdl * Handle BPF listeners. Let the BPF user see the packet.
2473 1.1 fvdl */
2474 1.1 fvdl if (ifp->if_bpf)
2475 1.1 fvdl bpf_mtap(ifp->if_bpf, m);
2476 1.1 fvdl #endif
2477 1.1 fvdl
2478 1.46 jonathan m->m_pkthdr.csum_flags |= M_CSUM_IPv4;
2479 1.46 jonathan
2480 1.46 jonathan if ((cur_rx->bge_ip_csum ^ 0xffff) != 0)
2481 1.46 jonathan m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD;
2482 1.46 jonathan /*
2483 1.46 jonathan * Rx transport checksum-offload may also
2484 1.46 jonathan * have bugs with packets which, when transmitted,
2485 1.46 jonathan * were `runts' requiring padding.
2486 1.46 jonathan */
2487 1.46 jonathan if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM &&
2488 1.46 jonathan (/* (sc->_bge_quirks & BGE_QUIRK_SHORT_CKSUM_BUG) == 0 ||*/
2489 1.46 jonathan m->m_pkthdr.len >= ETHER_MIN_NOPAD)) {
2490 1.46 jonathan m->m_pkthdr.csum_data =
2491 1.46 jonathan cur_rx->bge_tcp_udp_csum;
2492 1.46 jonathan m->m_pkthdr.csum_flags |=
2493 1.46 jonathan (M_CSUM_TCPv4|M_CSUM_UDPv4|
2494 1.46 jonathan M_CSUM_DATA|M_CSUM_NO_PSEUDOHDR);
2495 1.1 fvdl }
2496 1.1 fvdl
2497 1.1 fvdl /*
2498 1.1 fvdl * If we received a packet with a vlan tag, pass it
2499 1.1 fvdl * to vlan_input() instead of ether_input().
2500 1.1 fvdl */
2501 1.1 fvdl if (have_tag) {
2502 1.28 itojun struct m_tag *mtag;
2503 1.1 fvdl
2504 1.28 itojun mtag = m_tag_get(PACKET_TAG_VLAN, sizeof(u_int),
2505 1.28 itojun M_NOWAIT);
2506 1.28 itojun if (mtag != NULL) {
2507 1.28 itojun *(u_int *)(mtag + 1) = vlan_tag;
2508 1.28 itojun m_tag_prepend(m, mtag);
2509 1.1 fvdl have_tag = vlan_tag = 0;
2510 1.1 fvdl } else {
2511 1.1 fvdl printf("%s: no mbuf for tag\n", ifp->if_xname);
2512 1.1 fvdl m_freem(m);
2513 1.1 fvdl have_tag = vlan_tag = 0;
2514 1.1 fvdl continue;
2515 1.1 fvdl }
2516 1.1 fvdl }
2517 1.1 fvdl (*ifp->if_input)(ifp, m);
2518 1.1 fvdl }
2519 1.1 fvdl
2520 1.1 fvdl CSR_WRITE_4(sc, BGE_MBX_RX_CONS0_LO, sc->bge_rx_saved_considx);
2521 1.1 fvdl if (stdcnt)
2522 1.1 fvdl CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std);
2523 1.1 fvdl if (jumbocnt)
2524 1.1 fvdl CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo);
2525 1.1 fvdl }
2526 1.1 fvdl
2527 1.1 fvdl void
2528 1.1 fvdl bge_txeof(sc)
2529 1.1 fvdl struct bge_softc *sc;
2530 1.1 fvdl {
2531 1.1 fvdl struct bge_tx_bd *cur_tx = NULL;
2532 1.1 fvdl struct ifnet *ifp;
2533 1.1 fvdl struct txdmamap_pool_entry *dma;
2534 1.1 fvdl bus_addr_t offset, toff;
2535 1.1 fvdl bus_size_t tlen;
2536 1.1 fvdl int tosync;
2537 1.1 fvdl struct mbuf *m;
2538 1.1 fvdl
2539 1.1 fvdl ifp = &sc->ethercom.ec_if;
2540 1.1 fvdl
2541 1.1 fvdl bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map,
2542 1.1 fvdl offsetof(struct bge_ring_data, bge_status_block),
2543 1.1 fvdl sizeof (struct bge_status_block),
2544 1.1 fvdl BUS_DMASYNC_POSTREAD);
2545 1.1 fvdl
2546 1.1 fvdl offset = offsetof(struct bge_ring_data, bge_tx_ring);
2547 1.1 fvdl tosync = sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx -
2548 1.1 fvdl sc->bge_tx_saved_considx;
2549 1.1 fvdl
2550 1.1 fvdl toff = offset + (sc->bge_tx_saved_considx * sizeof (struct bge_tx_bd));
2551 1.1 fvdl
2552 1.1 fvdl if (tosync < 0) {
2553 1.1 fvdl tlen = (BGE_TX_RING_CNT - sc->bge_tx_saved_considx) *
2554 1.1 fvdl sizeof (struct bge_tx_bd);
2555 1.1 fvdl bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map,
2556 1.1 fvdl toff, tlen, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
2557 1.1 fvdl tosync = -tosync;
2558 1.1 fvdl }
2559 1.1 fvdl
2560 1.1 fvdl bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map,
2561 1.1 fvdl offset, tosync * sizeof (struct bge_tx_bd),
2562 1.1 fvdl BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
2563 1.1 fvdl
2564 1.1 fvdl /*
2565 1.1 fvdl * Go through our tx ring and free mbufs for those
2566 1.1 fvdl * frames that have been sent.
2567 1.1 fvdl */
2568 1.1 fvdl while (sc->bge_tx_saved_considx !=
2569 1.1 fvdl sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx) {
2570 1.1 fvdl u_int32_t idx = 0;
2571 1.1 fvdl
2572 1.1 fvdl idx = sc->bge_tx_saved_considx;
2573 1.1 fvdl cur_tx = &sc->bge_rdata->bge_tx_ring[idx];
2574 1.1 fvdl if (cur_tx->bge_flags & BGE_TXBDFLAG_END)
2575 1.1 fvdl ifp->if_opackets++;
2576 1.1 fvdl m = sc->bge_cdata.bge_tx_chain[idx];
2577 1.1 fvdl if (m != NULL) {
2578 1.1 fvdl sc->bge_cdata.bge_tx_chain[idx] = NULL;
2579 1.1 fvdl dma = sc->txdma[idx];
2580 1.1 fvdl bus_dmamap_sync(sc->bge_dmatag, dma->dmamap, 0,
2581 1.1 fvdl dma->dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE);
2582 1.1 fvdl bus_dmamap_unload(sc->bge_dmatag, dma->dmamap);
2583 1.1 fvdl SLIST_INSERT_HEAD(&sc->txdma_list, dma, link);
2584 1.1 fvdl sc->txdma[idx] = NULL;
2585 1.1 fvdl
2586 1.1 fvdl m_freem(m);
2587 1.1 fvdl }
2588 1.1 fvdl sc->bge_txcnt--;
2589 1.1 fvdl BGE_INC(sc->bge_tx_saved_considx, BGE_TX_RING_CNT);
2590 1.1 fvdl ifp->if_timer = 0;
2591 1.1 fvdl }
2592 1.1 fvdl
2593 1.1 fvdl if (cur_tx != NULL)
2594 1.1 fvdl ifp->if_flags &= ~IFF_OACTIVE;
2595 1.1 fvdl }
2596 1.1 fvdl
2597 1.1 fvdl int
2598 1.1 fvdl bge_intr(xsc)
2599 1.1 fvdl void *xsc;
2600 1.1 fvdl {
2601 1.1 fvdl struct bge_softc *sc;
2602 1.1 fvdl struct ifnet *ifp;
2603 1.1 fvdl
2604 1.1 fvdl sc = xsc;
2605 1.1 fvdl ifp = &sc->ethercom.ec_if;
2606 1.1 fvdl
2607 1.1 fvdl #ifdef notdef
2608 1.1 fvdl /* Avoid this for now -- checking this register is expensive. */
2609 1.1 fvdl /* Make sure this is really our interrupt. */
2610 1.1 fvdl if (!(CSR_READ_4(sc, BGE_MISC_LOCAL_CTL) & BGE_MLC_INTR_STATE))
2611 1.1 fvdl return (0);
2612 1.1 fvdl #endif
2613 1.1 fvdl /* Ack interrupt and stop others from occuring. */
2614 1.1 fvdl CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 1);
2615 1.1 fvdl
2616 1.1 fvdl /*
2617 1.1 fvdl * Process link state changes.
2618 1.1 fvdl * Grrr. The link status word in the status block does
2619 1.1 fvdl * not work correctly on the BCM5700 rev AX and BX chips,
2620 1.1 fvdl * according to all avaibable information. Hence, we have
2621 1.1 fvdl * to enable MII interrupts in order to properly obtain
2622 1.1 fvdl * async link changes. Unfortunately, this also means that
2623 1.1 fvdl * we have to read the MAC status register to detect link
2624 1.1 fvdl * changes, thereby adding an additional register access to
2625 1.1 fvdl * the interrupt handler.
2626 1.1 fvdl */
2627 1.1 fvdl
2628 1.17 thorpej if (sc->bge_quirks & BGE_QUIRK_LINK_STATE_BROKEN) {
2629 1.1 fvdl u_int32_t status;
2630 1.1 fvdl
2631 1.1 fvdl status = CSR_READ_4(sc, BGE_MAC_STS);
2632 1.1 fvdl if (status & BGE_MACSTAT_MI_INTERRUPT) {
2633 1.1 fvdl sc->bge_link = 0;
2634 1.1 fvdl callout_stop(&sc->bge_timeout);
2635 1.1 fvdl bge_tick(sc);
2636 1.1 fvdl /* Clear the interrupt */
2637 1.1 fvdl CSR_WRITE_4(sc, BGE_MAC_EVT_ENB,
2638 1.1 fvdl BGE_EVTENB_MI_INTERRUPT);
2639 1.1 fvdl bge_miibus_readreg(&sc->bge_dev, 1, BRGPHY_MII_ISR);
2640 1.1 fvdl bge_miibus_writereg(&sc->bge_dev, 1, BRGPHY_MII_IMR,
2641 1.1 fvdl BRGPHY_INTRS);
2642 1.1 fvdl }
2643 1.1 fvdl } else {
2644 1.1 fvdl if (sc->bge_rdata->bge_status_block.bge_status &
2645 1.1 fvdl BGE_STATFLAG_LINKSTATE_CHANGED) {
2646 1.1 fvdl sc->bge_link = 0;
2647 1.1 fvdl callout_stop(&sc->bge_timeout);
2648 1.1 fvdl bge_tick(sc);
2649 1.1 fvdl /* Clear the interrupt */
2650 1.1 fvdl CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED|
2651 1.44 hannken BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE|
2652 1.44 hannken BGE_MACSTAT_LINK_CHANGED);
2653 1.1 fvdl }
2654 1.1 fvdl }
2655 1.1 fvdl
2656 1.1 fvdl if (ifp->if_flags & IFF_RUNNING) {
2657 1.1 fvdl /* Check RX return ring producer/consumer */
2658 1.1 fvdl bge_rxeof(sc);
2659 1.1 fvdl
2660 1.1 fvdl /* Check TX ring producer/consumer */
2661 1.1 fvdl bge_txeof(sc);
2662 1.1 fvdl }
2663 1.1 fvdl
2664 1.1 fvdl bge_handle_events(sc);
2665 1.1 fvdl
2666 1.1 fvdl /* Re-enable interrupts. */
2667 1.1 fvdl CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 0);
2668 1.1 fvdl
2669 1.1 fvdl if (ifp->if_flags & IFF_RUNNING && !IFQ_IS_EMPTY(&ifp->if_snd))
2670 1.1 fvdl bge_start(ifp);
2671 1.1 fvdl
2672 1.1 fvdl return (1);
2673 1.1 fvdl }
2674 1.1 fvdl
2675 1.1 fvdl void
2676 1.1 fvdl bge_tick(xsc)
2677 1.1 fvdl void *xsc;
2678 1.1 fvdl {
2679 1.1 fvdl struct bge_softc *sc = xsc;
2680 1.1 fvdl struct mii_data *mii = &sc->bge_mii;
2681 1.1 fvdl struct ifmedia *ifm = NULL;
2682 1.1 fvdl struct ifnet *ifp = &sc->ethercom.ec_if;
2683 1.1 fvdl int s;
2684 1.1 fvdl
2685 1.1 fvdl s = splnet();
2686 1.1 fvdl
2687 1.1 fvdl bge_stats_update(sc);
2688 1.1 fvdl callout_reset(&sc->bge_timeout, hz, bge_tick, sc);
2689 1.1 fvdl if (sc->bge_link) {
2690 1.1 fvdl splx(s);
2691 1.1 fvdl return;
2692 1.1 fvdl }
2693 1.1 fvdl
2694 1.1 fvdl if (sc->bge_tbi) {
2695 1.1 fvdl ifm = &sc->bge_ifmedia;
2696 1.1 fvdl if (CSR_READ_4(sc, BGE_MAC_STS) &
2697 1.1 fvdl BGE_MACSTAT_TBI_PCS_SYNCHED) {
2698 1.1 fvdl sc->bge_link++;
2699 1.1 fvdl CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF);
2700 1.1 fvdl if (!IFQ_IS_EMPTY(&ifp->if_snd))
2701 1.1 fvdl bge_start(ifp);
2702 1.1 fvdl }
2703 1.1 fvdl splx(s);
2704 1.1 fvdl return;
2705 1.1 fvdl }
2706 1.1 fvdl
2707 1.1 fvdl mii_tick(mii);
2708 1.1 fvdl
2709 1.1 fvdl if (!sc->bge_link && mii->mii_media_status & IFM_ACTIVE &&
2710 1.1 fvdl IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
2711 1.1 fvdl sc->bge_link++;
2712 1.1 fvdl if (!IFQ_IS_EMPTY(&ifp->if_snd))
2713 1.1 fvdl bge_start(ifp);
2714 1.1 fvdl }
2715 1.1 fvdl
2716 1.1 fvdl splx(s);
2717 1.1 fvdl }
2718 1.1 fvdl
2719 1.1 fvdl void
2720 1.1 fvdl bge_stats_update(sc)
2721 1.1 fvdl struct bge_softc *sc;
2722 1.1 fvdl {
2723 1.1 fvdl struct ifnet *ifp = &sc->ethercom.ec_if;
2724 1.1 fvdl bus_size_t stats = BGE_MEMWIN_START + BGE_STATS_BLOCK;
2725 1.44 hannken bus_size_t rstats = BGE_RX_STATS;
2726 1.44 hannken
2727 1.44 hannken #define READ_RSTAT(sc, stats, stat) \
2728 1.44 hannken CSR_READ_4(sc, stats + offsetof(struct bge_mac_stats_regs, stat))
2729 1.1 fvdl
2730 1.44 hannken if (sc->bge_quirks & BGE_QUIRK_5705_CORE) {
2731 1.44 hannken ifp->if_collisions +=
2732 1.44 hannken READ_RSTAT(sc, rstats, dot3StatsSingleCollisionFrames) +
2733 1.44 hannken READ_RSTAT(sc, rstats, dot3StatsMultipleCollisionFrames) +
2734 1.44 hannken READ_RSTAT(sc, rstats, dot3StatsExcessiveCollisions) +
2735 1.44 hannken READ_RSTAT(sc, rstats, dot3StatsLateCollisions);
2736 1.44 hannken return;
2737 1.44 hannken }
2738 1.44 hannken
2739 1.44 hannken #undef READ_RSTAT
2740 1.1 fvdl #define READ_STAT(sc, stats, stat) \
2741 1.1 fvdl CSR_READ_4(sc, stats + offsetof(struct bge_stats, stat))
2742 1.1 fvdl
2743 1.1 fvdl ifp->if_collisions +=
2744 1.1 fvdl (READ_STAT(sc, stats, dot3StatsSingleCollisionFrames.bge_addr_lo) +
2745 1.1 fvdl READ_STAT(sc, stats, dot3StatsMultipleCollisionFrames.bge_addr_lo) +
2746 1.1 fvdl READ_STAT(sc, stats, dot3StatsExcessiveCollisions.bge_addr_lo) +
2747 1.1 fvdl READ_STAT(sc, stats, dot3StatsLateCollisions.bge_addr_lo)) -
2748 1.1 fvdl ifp->if_collisions;
2749 1.1 fvdl
2750 1.1 fvdl #undef READ_STAT
2751 1.1 fvdl
2752 1.1 fvdl #ifdef notdef
2753 1.1 fvdl ifp->if_collisions +=
2754 1.1 fvdl (sc->bge_rdata->bge_info.bge_stats.dot3StatsSingleCollisionFrames +
2755 1.1 fvdl sc->bge_rdata->bge_info.bge_stats.dot3StatsMultipleCollisionFrames +
2756 1.1 fvdl sc->bge_rdata->bge_info.bge_stats.dot3StatsExcessiveCollisions +
2757 1.1 fvdl sc->bge_rdata->bge_info.bge_stats.dot3StatsLateCollisions) -
2758 1.1 fvdl ifp->if_collisions;
2759 1.1 fvdl #endif
2760 1.1 fvdl }
2761 1.1 fvdl
2762 1.46 jonathan /*
2763 1.46 jonathan * Pad outbound frame to ETHER_MIN_NOPAD for an unusual reason.
2764 1.46 jonathan * The bge hardware will pad out Tx runts to ETHER_MIN_NOPAD,
2765 1.46 jonathan * but when such padded frames employ the bge IP/TCP checksum offload,
2766 1.46 jonathan * the hardware checksum assist gives incorrect results (possibly
2767 1.46 jonathan * from incorporating its own padding into the UDP/TCP checksum; who knows).
2768 1.46 jonathan * If we pad such runts with zeros, the onboard checksum comes out correct.
2769 1.46 jonathan */
2770 1.46 jonathan static __inline int
2771 1.46 jonathan bge_cksum_pad(struct mbuf *pkt)
2772 1.46 jonathan {
2773 1.46 jonathan struct mbuf *last = NULL;
2774 1.46 jonathan int padlen;
2775 1.46 jonathan
2776 1.46 jonathan padlen = ETHER_MIN_NOPAD - pkt->m_pkthdr.len;
2777 1.46 jonathan
2778 1.46 jonathan /* if there's only the packet-header and we can pad there, use it. */
2779 1.46 jonathan if (pkt->m_pkthdr.len == pkt->m_len &&
2780 1.46 jonathan !M_READONLY(pkt) && M_TRAILINGSPACE(pkt) >= padlen) {
2781 1.46 jonathan last = pkt;
2782 1.46 jonathan } else {
2783 1.46 jonathan /*
2784 1.46 jonathan * Walk packet chain to find last mbuf. We will either
2785 1.46 jonathan * pad there, or append a new mbuf and pad it
2786 1.46 jonathan * (thus perhaps avoiding the bcm5700 dma-min bug).
2787 1.46 jonathan */
2788 1.46 jonathan for (last = pkt; last->m_next != NULL; last = last->m_next) {
2789 1.46 jonathan (void) 0; /* do nothing*/
2790 1.46 jonathan }
2791 1.46 jonathan
2792 1.46 jonathan /* `last' now points to last in chain. */
2793 1.46 jonathan if (!M_READONLY(last) && M_TRAILINGSPACE(last) >= padlen) {
2794 1.46 jonathan (void) 0; /* we can pad here, in-place. */
2795 1.46 jonathan } else {
2796 1.46 jonathan /* Allocate new empty mbuf, pad it. Compact later. */
2797 1.46 jonathan struct mbuf *n;
2798 1.46 jonathan MGET(n, M_DONTWAIT, MT_DATA);
2799 1.46 jonathan n->m_len = 0;
2800 1.46 jonathan last->m_next = n;
2801 1.46 jonathan last = n;
2802 1.46 jonathan }
2803 1.46 jonathan }
2804 1.46 jonathan
2805 1.46 jonathan #ifdef DEBUG
2806 1.48 hannken /*KASSERT(M_WRITABLE(last), ("to-pad mbuf not writeable\n"));*/
2807 1.47 cjep KASSERT(M_TRAILINGSPACE(last) >= padlen /*, ("insufficient space to pad\n")*/ );
2808 1.46 jonathan #endif
2809 1.46 jonathan /* Now zero the pad area, to avoid the bge cksum-assist bug */
2810 1.46 jonathan memset(mtod(last, caddr_t) + last->m_len, 0, padlen);
2811 1.46 jonathan last->m_len += padlen;
2812 1.46 jonathan pkt->m_pkthdr.len += padlen;
2813 1.46 jonathan return 0;
2814 1.46 jonathan }
2815 1.45 jonathan
2816 1.45 jonathan /*
2817 1.45 jonathan * Compact outbound packets to avoid bug with DMA segments less than 8 bytes.
2818 1.45 jonathan */
2819 1.45 jonathan static __inline int
2820 1.45 jonathan bge_compact_dma_runt(struct mbuf *pkt)
2821 1.45 jonathan {
2822 1.45 jonathan struct mbuf *m, *prev;
2823 1.45 jonathan int totlen, prevlen;
2824 1.45 jonathan
2825 1.45 jonathan prev = NULL;
2826 1.45 jonathan totlen = 0;
2827 1.45 jonathan prevlen = -1;
2828 1.45 jonathan
2829 1.45 jonathan for (m = pkt; m != NULL; prev = m,m = m->m_next) {
2830 1.45 jonathan int mlen = m->m_len;
2831 1.45 jonathan int shortfall = 8 - mlen ;
2832 1.45 jonathan
2833 1.45 jonathan totlen += mlen;
2834 1.45 jonathan if (mlen == 0) {
2835 1.45 jonathan continue;
2836 1.45 jonathan }
2837 1.45 jonathan if (mlen >= 8)
2838 1.45 jonathan continue;
2839 1.45 jonathan
2840 1.45 jonathan /* If we get here, mbuf data is too small for DMA engine.
2841 1.45 jonathan * Try to fix by shuffling data to prev or next in chain.
2842 1.45 jonathan * If that fails, do a compacting deep-copy of the whole chain.
2843 1.45 jonathan */
2844 1.45 jonathan
2845 1.45 jonathan /* Internal frag. If fits in prev, copy it there. */
2846 1.45 jonathan if (prev && !M_READONLY(prev) &&
2847 1.45 jonathan M_TRAILINGSPACE(prev) >= m->m_len) {
2848 1.45 jonathan bcopy(m->m_data,
2849 1.45 jonathan prev->m_data+prev->m_len,
2850 1.45 jonathan mlen);
2851 1.45 jonathan prev->m_len += mlen;
2852 1.45 jonathan m->m_len = 0;
2853 1.45 jonathan /* XXX stitch chain */
2854 1.45 jonathan prev->m_next = m_free(m);
2855 1.45 jonathan m = prev;
2856 1.45 jonathan continue;
2857 1.45 jonathan }
2858 1.45 jonathan else if (m->m_next != NULL && !M_READONLY(m) &&
2859 1.45 jonathan M_TRAILINGSPACE(m) >= shortfall &&
2860 1.45 jonathan m->m_next->m_len >= (8 + shortfall)) {
2861 1.45 jonathan /* m is writable and have enough data in next, pull up. */
2862 1.45 jonathan
2863 1.45 jonathan bcopy(m->m_next->m_data,
2864 1.45 jonathan m->m_data+m->m_len,
2865 1.45 jonathan shortfall);
2866 1.45 jonathan m->m_len += shortfall;
2867 1.45 jonathan m->m_next->m_len -= shortfall;
2868 1.45 jonathan m->m_next->m_data += shortfall;
2869 1.45 jonathan }
2870 1.45 jonathan else if (m->m_next == NULL || 1) {
2871 1.45 jonathan /* Got a runt at the very end of the packet.
2872 1.45 jonathan * borrow data from the tail of the preceding mbuf and
2873 1.45 jonathan * update its length in-place. (The original data is still
2874 1.45 jonathan * valid, so we can do this even if prev is not writable.)
2875 1.45 jonathan */
2876 1.45 jonathan
2877 1.45 jonathan /* if we'd make prev a runt, just move all of its data. */
2878 1.45 jonathan #ifdef DEBUG
2879 1.45 jonathan KASSERT(prev != NULL /*, ("runt but null PREV")*/);
2880 1.45 jonathan KASSERT(prev->m_len >= 8 /*, ("runt prev")*/);
2881 1.45 jonathan #endif
2882 1.45 jonathan if ((prev->m_len - shortfall) < 8)
2883 1.45 jonathan shortfall = prev->m_len;
2884 1.45 jonathan
2885 1.45 jonathan #ifdef notyet /* just do the safe slow thing for now */
2886 1.45 jonathan if (!M_READONLY(m)) {
2887 1.45 jonathan if (M_LEADINGSPACE(m) < shorfall) {
2888 1.45 jonathan void *m_dat;
2889 1.45 jonathan m_dat = (m->m_flags & M_PKTHDR) ?
2890 1.45 jonathan m->m_pktdat : m->dat;
2891 1.45 jonathan memmove(m_dat, mtod(m, void*), m->m_len);
2892 1.45 jonathan m->m_data = m_dat;
2893 1.45 jonathan }
2894 1.45 jonathan } else
2895 1.45 jonathan #endif /* just do the safe slow thing */
2896 1.45 jonathan {
2897 1.45 jonathan struct mbuf * n = NULL;
2898 1.45 jonathan int newprevlen = prev->m_len - shortfall;
2899 1.45 jonathan
2900 1.45 jonathan MGET(n, M_NOWAIT, MT_DATA);
2901 1.45 jonathan if (n == NULL)
2902 1.45 jonathan return ENOBUFS;
2903 1.45 jonathan KASSERT(m->m_len + shortfall < MLEN
2904 1.45 jonathan /*,
2905 1.45 jonathan ("runt %d +prev %d too big\n", m->m_len, shortfall)*/);
2906 1.45 jonathan
2907 1.45 jonathan /* first copy the data we're stealing from prev */
2908 1.45 jonathan bcopy(prev->m_data + newprevlen, n->m_data, shortfall);
2909 1.45 jonathan
2910 1.45 jonathan /* update prev->m_len accordingly */
2911 1.45 jonathan prev->m_len -= shortfall;
2912 1.45 jonathan
2913 1.45 jonathan /* copy data from runt m */
2914 1.45 jonathan bcopy(m->m_data, n->m_data + shortfall, m->m_len);
2915 1.45 jonathan
2916 1.45 jonathan /* n holds what we stole from prev, plus m */
2917 1.45 jonathan n->m_len = shortfall + m->m_len;
2918 1.45 jonathan
2919 1.45 jonathan /* stitch n into chain and free m */
2920 1.45 jonathan n->m_next = m->m_next;
2921 1.45 jonathan prev->m_next = n;
2922 1.45 jonathan /* KASSERT(m->m_next == NULL); */
2923 1.45 jonathan m->m_next = NULL;
2924 1.45 jonathan m_free(m);
2925 1.45 jonathan m = n; /* for continuing loop */
2926 1.45 jonathan }
2927 1.45 jonathan }
2928 1.45 jonathan prevlen = m->m_len;
2929 1.45 jonathan }
2930 1.45 jonathan return 0;
2931 1.45 jonathan }
2932 1.45 jonathan
2933 1.1 fvdl /*
2934 1.1 fvdl * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data
2935 1.1 fvdl * pointers to descriptors.
2936 1.1 fvdl */
2937 1.1 fvdl int
2938 1.1 fvdl bge_encap(sc, m_head, txidx)
2939 1.1 fvdl struct bge_softc *sc;
2940 1.1 fvdl struct mbuf *m_head;
2941 1.1 fvdl u_int32_t *txidx;
2942 1.1 fvdl {
2943 1.1 fvdl struct bge_tx_bd *f = NULL;
2944 1.1 fvdl u_int32_t frag, cur, cnt = 0;
2945 1.1 fvdl u_int16_t csum_flags = 0;
2946 1.1 fvdl struct txdmamap_pool_entry *dma;
2947 1.1 fvdl bus_dmamap_t dmamap;
2948 1.1 fvdl int i = 0;
2949 1.29 itojun struct m_tag *mtag;
2950 1.1 fvdl
2951 1.1 fvdl cur = frag = *txidx;
2952 1.1 fvdl
2953 1.1 fvdl if (m_head->m_pkthdr.csum_flags) {
2954 1.1 fvdl if (m_head->m_pkthdr.csum_flags & M_CSUM_IPv4)
2955 1.1 fvdl csum_flags |= BGE_TXBDFLAG_IP_CSUM;
2956 1.8 thorpej if (m_head->m_pkthdr.csum_flags & (M_CSUM_TCPv4|M_CSUM_UDPv4))
2957 1.1 fvdl csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM;
2958 1.1 fvdl }
2959 1.1 fvdl
2960 1.46 jonathan /*
2961 1.46 jonathan * If we were asked to do an outboard checksum, and the NIC
2962 1.46 jonathan * has the bug where it sometimes adds in the Ethernet padding,
2963 1.46 jonathan * explicitly pad with zeros so the cksum will be correct either way.
2964 1.46 jonathan * (For now, do this for all chip versions, until newer
2965 1.46 jonathan * are confirmed to not require the workaround.)
2966 1.46 jonathan */
2967 1.46 jonathan if ((csum_flags & BGE_TXBDFLAG_TCP_UDP_CSUM) == 0 ||
2968 1.46 jonathan #ifdef notyet
2969 1.46 jonathan (sc->bge_quirks & BGE_QUIRK_SHORT_CKSUM_BUG) == 0 ||
2970 1.46 jonathan #endif
2971 1.46 jonathan m_head->m_pkthdr.len >= ETHER_MIN_NOPAD)
2972 1.46 jonathan goto check_dma_bug;
2973 1.46 jonathan
2974 1.46 jonathan if (bge_cksum_pad(m_head) != 0)
2975 1.46 jonathan return ENOBUFS;
2976 1.46 jonathan
2977 1.46 jonathan check_dma_bug:
2978 1.25 jonathan if (!(sc->bge_quirks & BGE_QUIRK_5700_SMALLDMA))
2979 1.29 itojun goto doit;
2980 1.25 jonathan /*
2981 1.25 jonathan * bcm5700 Revision B silicon cannot handle DMA descriptors with
2982 1.25 jonathan * less than eight bytes. If we encounter a teeny mbuf
2983 1.25 jonathan * at the end of a chain, we can pad. Otherwise, copy.
2984 1.25 jonathan */
2985 1.45 jonathan if (bge_compact_dma_runt(m_head) != 0)
2986 1.45 jonathan return ENOBUFS;
2987 1.25 jonathan
2988 1.25 jonathan doit:
2989 1.1 fvdl dma = SLIST_FIRST(&sc->txdma_list);
2990 1.1 fvdl if (dma == NULL)
2991 1.1 fvdl return ENOBUFS;
2992 1.1 fvdl dmamap = dma->dmamap;
2993 1.1 fvdl
2994 1.1 fvdl /*
2995 1.1 fvdl * Start packing the mbufs in this chain into
2996 1.1 fvdl * the fragment pointers. Stop when we run out
2997 1.1 fvdl * of fragments or hit the end of the mbuf chain.
2998 1.1 fvdl */
2999 1.1 fvdl if (bus_dmamap_load_mbuf(sc->bge_dmatag, dmamap, m_head,
3000 1.1 fvdl BUS_DMA_NOWAIT))
3001 1.1 fvdl return(ENOBUFS);
3002 1.1 fvdl
3003 1.28 itojun mtag = sc->ethercom.ec_nvlans ?
3004 1.28 itojun m_tag_find(m_head, PACKET_TAG_VLAN, NULL) : NULL;
3005 1.6 thorpej
3006 1.1 fvdl for (i = 0; i < dmamap->dm_nsegs; i++) {
3007 1.1 fvdl f = &sc->bge_rdata->bge_tx_ring[frag];
3008 1.1 fvdl if (sc->bge_cdata.bge_tx_chain[frag] != NULL)
3009 1.1 fvdl break;
3010 1.1 fvdl bge_set_hostaddr(&f->bge_addr, dmamap->dm_segs[i].ds_addr);
3011 1.1 fvdl f->bge_len = dmamap->dm_segs[i].ds_len;
3012 1.1 fvdl f->bge_flags = csum_flags;
3013 1.1 fvdl
3014 1.28 itojun if (mtag != NULL) {
3015 1.1 fvdl f->bge_flags |= BGE_TXBDFLAG_VLAN_TAG;
3016 1.28 itojun f->bge_vlan_tag = *(u_int *)(mtag + 1);
3017 1.1 fvdl } else {
3018 1.1 fvdl f->bge_vlan_tag = 0;
3019 1.1 fvdl }
3020 1.1 fvdl /*
3021 1.1 fvdl * Sanity check: avoid coming within 16 descriptors
3022 1.1 fvdl * of the end of the ring.
3023 1.1 fvdl */
3024 1.1 fvdl if ((BGE_TX_RING_CNT - (sc->bge_txcnt + cnt)) < 16)
3025 1.1 fvdl return(ENOBUFS);
3026 1.1 fvdl cur = frag;
3027 1.1 fvdl BGE_INC(frag, BGE_TX_RING_CNT);
3028 1.1 fvdl cnt++;
3029 1.1 fvdl }
3030 1.1 fvdl
3031 1.1 fvdl if (i < dmamap->dm_nsegs)
3032 1.1 fvdl return ENOBUFS;
3033 1.1 fvdl
3034 1.1 fvdl bus_dmamap_sync(sc->bge_dmatag, dmamap, 0, dmamap->dm_mapsize,
3035 1.1 fvdl BUS_DMASYNC_PREWRITE);
3036 1.1 fvdl
3037 1.1 fvdl if (frag == sc->bge_tx_saved_considx)
3038 1.1 fvdl return(ENOBUFS);
3039 1.1 fvdl
3040 1.1 fvdl sc->bge_rdata->bge_tx_ring[cur].bge_flags |= BGE_TXBDFLAG_END;
3041 1.1 fvdl sc->bge_cdata.bge_tx_chain[cur] = m_head;
3042 1.1 fvdl SLIST_REMOVE_HEAD(&sc->txdma_list, link);
3043 1.1 fvdl sc->txdma[cur] = dma;
3044 1.1 fvdl sc->bge_txcnt += cnt;
3045 1.1 fvdl
3046 1.1 fvdl *txidx = frag;
3047 1.1 fvdl
3048 1.1 fvdl return(0);
3049 1.1 fvdl }
3050 1.1 fvdl
3051 1.1 fvdl /*
3052 1.1 fvdl * Main transmit routine. To avoid having to do mbuf copies, we put pointers
3053 1.1 fvdl * to the mbuf data regions directly in the transmit descriptors.
3054 1.1 fvdl */
3055 1.1 fvdl void
3056 1.1 fvdl bge_start(ifp)
3057 1.1 fvdl struct ifnet *ifp;
3058 1.1 fvdl {
3059 1.1 fvdl struct bge_softc *sc;
3060 1.1 fvdl struct mbuf *m_head = NULL;
3061 1.1 fvdl u_int32_t prodidx = 0;
3062 1.1 fvdl int pkts = 0;
3063 1.1 fvdl
3064 1.1 fvdl sc = ifp->if_softc;
3065 1.1 fvdl
3066 1.1 fvdl if (!sc->bge_link && ifp->if_snd.ifq_len < 10)
3067 1.1 fvdl return;
3068 1.1 fvdl
3069 1.1 fvdl prodidx = CSR_READ_4(sc, BGE_MBX_TX_HOST_PROD0_LO);
3070 1.1 fvdl
3071 1.1 fvdl while(sc->bge_cdata.bge_tx_chain[prodidx] == NULL) {
3072 1.1 fvdl IFQ_POLL(&ifp->if_snd, m_head);
3073 1.1 fvdl if (m_head == NULL)
3074 1.1 fvdl break;
3075 1.1 fvdl
3076 1.1 fvdl #if 0
3077 1.1 fvdl /*
3078 1.1 fvdl * XXX
3079 1.1 fvdl * safety overkill. If this is a fragmented packet chain
3080 1.1 fvdl * with delayed TCP/UDP checksums, then only encapsulate
3081 1.1 fvdl * it if we have enough descriptors to handle the entire
3082 1.1 fvdl * chain at once.
3083 1.1 fvdl * (paranoia -- may not actually be needed)
3084 1.1 fvdl */
3085 1.1 fvdl if (m_head->m_flags & M_FIRSTFRAG &&
3086 1.1 fvdl m_head->m_pkthdr.csum_flags & (CSUM_DELAY_DATA)) {
3087 1.1 fvdl if ((BGE_TX_RING_CNT - sc->bge_txcnt) <
3088 1.1 fvdl m_head->m_pkthdr.csum_data + 16) {
3089 1.1 fvdl ifp->if_flags |= IFF_OACTIVE;
3090 1.1 fvdl break;
3091 1.1 fvdl }
3092 1.1 fvdl }
3093 1.1 fvdl #endif
3094 1.1 fvdl
3095 1.1 fvdl /*
3096 1.1 fvdl * Pack the data into the transmit ring. If we
3097 1.1 fvdl * don't have room, set the OACTIVE flag and wait
3098 1.1 fvdl * for the NIC to drain the ring.
3099 1.1 fvdl */
3100 1.1 fvdl if (bge_encap(sc, m_head, &prodidx)) {
3101 1.1 fvdl ifp->if_flags |= IFF_OACTIVE;
3102 1.1 fvdl break;
3103 1.1 fvdl }
3104 1.1 fvdl
3105 1.1 fvdl /* now we are committed to transmit the packet */
3106 1.1 fvdl IFQ_DEQUEUE(&ifp->if_snd, m_head);
3107 1.1 fvdl pkts++;
3108 1.1 fvdl
3109 1.1 fvdl #if NBPFILTER > 0
3110 1.1 fvdl /*
3111 1.1 fvdl * If there's a BPF listener, bounce a copy of this frame
3112 1.1 fvdl * to him.
3113 1.1 fvdl */
3114 1.1 fvdl if (ifp->if_bpf)
3115 1.1 fvdl bpf_mtap(ifp->if_bpf, m_head);
3116 1.1 fvdl #endif
3117 1.1 fvdl }
3118 1.1 fvdl if (pkts == 0)
3119 1.1 fvdl return;
3120 1.1 fvdl
3121 1.1 fvdl /* Transmit */
3122 1.1 fvdl CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx);
3123 1.29 itojun if (sc->bge_quirks & BGE_QUIRK_PRODUCER_BUG) /* 5700 b2 errata */
3124 1.29 itojun CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx);
3125 1.1 fvdl
3126 1.1 fvdl /*
3127 1.1 fvdl * Set a timeout in case the chip goes out to lunch.
3128 1.1 fvdl */
3129 1.1 fvdl ifp->if_timer = 5;
3130 1.1 fvdl }
3131 1.1 fvdl
3132 1.1 fvdl int
3133 1.1 fvdl bge_init(ifp)
3134 1.1 fvdl struct ifnet *ifp;
3135 1.1 fvdl {
3136 1.1 fvdl struct bge_softc *sc = ifp->if_softc;
3137 1.1 fvdl u_int16_t *m;
3138 1.1 fvdl int s, error;
3139 1.1 fvdl
3140 1.1 fvdl s = splnet();
3141 1.1 fvdl
3142 1.1 fvdl ifp = &sc->ethercom.ec_if;
3143 1.1 fvdl
3144 1.1 fvdl /* Cancel pending I/O and flush buffers. */
3145 1.1 fvdl bge_stop(sc);
3146 1.1 fvdl bge_reset(sc);
3147 1.1 fvdl bge_chipinit(sc);
3148 1.1 fvdl
3149 1.1 fvdl /*
3150 1.1 fvdl * Init the various state machines, ring
3151 1.1 fvdl * control blocks and firmware.
3152 1.1 fvdl */
3153 1.1 fvdl error = bge_blockinit(sc);
3154 1.1 fvdl if (error != 0) {
3155 1.1 fvdl printf("%s: initialization error %d\n", sc->bge_dev.dv_xname,
3156 1.1 fvdl error);
3157 1.1 fvdl splx(s);
3158 1.1 fvdl return error;
3159 1.1 fvdl }
3160 1.1 fvdl
3161 1.1 fvdl ifp = &sc->ethercom.ec_if;
3162 1.1 fvdl
3163 1.1 fvdl /* Specify MTU. */
3164 1.1 fvdl CSR_WRITE_4(sc, BGE_RX_MTU, ifp->if_mtu +
3165 1.1 fvdl ETHER_HDR_LEN + ETHER_CRC_LEN);
3166 1.1 fvdl
3167 1.1 fvdl /* Load our MAC address. */
3168 1.1 fvdl m = (u_int16_t *)&(LLADDR(ifp->if_sadl)[0]);
3169 1.1 fvdl CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0]));
3170 1.1 fvdl CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, (htons(m[1]) << 16) | htons(m[2]));
3171 1.1 fvdl
3172 1.1 fvdl /* Enable or disable promiscuous mode as needed. */
3173 1.1 fvdl if (ifp->if_flags & IFF_PROMISC) {
3174 1.1 fvdl BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC);
3175 1.1 fvdl } else {
3176 1.1 fvdl BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC);
3177 1.1 fvdl }
3178 1.1 fvdl
3179 1.1 fvdl /* Program multicast filter. */
3180 1.1 fvdl bge_setmulti(sc);
3181 1.1 fvdl
3182 1.1 fvdl /* Init RX ring. */
3183 1.1 fvdl bge_init_rx_ring_std(sc);
3184 1.1 fvdl
3185 1.1 fvdl /* Init jumbo RX ring. */
3186 1.1 fvdl if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN))
3187 1.1 fvdl bge_init_rx_ring_jumbo(sc);
3188 1.1 fvdl
3189 1.1 fvdl /* Init our RX return ring index */
3190 1.1 fvdl sc->bge_rx_saved_considx = 0;
3191 1.1 fvdl
3192 1.1 fvdl /* Init TX ring. */
3193 1.1 fvdl bge_init_tx_ring(sc);
3194 1.1 fvdl
3195 1.1 fvdl /* Turn on transmitter */
3196 1.1 fvdl BGE_SETBIT(sc, BGE_TX_MODE, BGE_TXMODE_ENABLE);
3197 1.1 fvdl
3198 1.1 fvdl /* Turn on receiver */
3199 1.1 fvdl BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE);
3200 1.1 fvdl
3201 1.1 fvdl /* Tell firmware we're alive. */
3202 1.1 fvdl BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
3203 1.1 fvdl
3204 1.1 fvdl /* Enable host interrupts. */
3205 1.1 fvdl BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA);
3206 1.1 fvdl BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR);
3207 1.1 fvdl CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 0);
3208 1.1 fvdl
3209 1.1 fvdl bge_ifmedia_upd(ifp);
3210 1.1 fvdl
3211 1.1 fvdl ifp->if_flags |= IFF_RUNNING;
3212 1.1 fvdl ifp->if_flags &= ~IFF_OACTIVE;
3213 1.1 fvdl
3214 1.1 fvdl splx(s);
3215 1.1 fvdl
3216 1.1 fvdl callout_reset(&sc->bge_timeout, hz, bge_tick, sc);
3217 1.1 fvdl
3218 1.1 fvdl return 0;
3219 1.1 fvdl }
3220 1.1 fvdl
3221 1.1 fvdl /*
3222 1.1 fvdl * Set media options.
3223 1.1 fvdl */
3224 1.1 fvdl int
3225 1.1 fvdl bge_ifmedia_upd(ifp)
3226 1.1 fvdl struct ifnet *ifp;
3227 1.1 fvdl {
3228 1.1 fvdl struct bge_softc *sc = ifp->if_softc;
3229 1.1 fvdl struct mii_data *mii = &sc->bge_mii;
3230 1.1 fvdl struct ifmedia *ifm = &sc->bge_ifmedia;
3231 1.1 fvdl
3232 1.1 fvdl /* If this is a 1000baseX NIC, enable the TBI port. */
3233 1.1 fvdl if (sc->bge_tbi) {
3234 1.1 fvdl if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
3235 1.1 fvdl return(EINVAL);
3236 1.1 fvdl switch(IFM_SUBTYPE(ifm->ifm_media)) {
3237 1.1 fvdl case IFM_AUTO:
3238 1.1 fvdl break;
3239 1.1 fvdl case IFM_1000_SX:
3240 1.1 fvdl if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) {
3241 1.1 fvdl BGE_CLRBIT(sc, BGE_MAC_MODE,
3242 1.1 fvdl BGE_MACMODE_HALF_DUPLEX);
3243 1.1 fvdl } else {
3244 1.1 fvdl BGE_SETBIT(sc, BGE_MAC_MODE,
3245 1.1 fvdl BGE_MACMODE_HALF_DUPLEX);
3246 1.1 fvdl }
3247 1.1 fvdl break;
3248 1.1 fvdl default:
3249 1.1 fvdl return(EINVAL);
3250 1.1 fvdl }
3251 1.1 fvdl return(0);
3252 1.1 fvdl }
3253 1.1 fvdl
3254 1.1 fvdl sc->bge_link = 0;
3255 1.1 fvdl mii_mediachg(mii);
3256 1.1 fvdl
3257 1.1 fvdl return(0);
3258 1.1 fvdl }
3259 1.1 fvdl
3260 1.1 fvdl /*
3261 1.1 fvdl * Report current media status.
3262 1.1 fvdl */
3263 1.1 fvdl void
3264 1.1 fvdl bge_ifmedia_sts(ifp, ifmr)
3265 1.1 fvdl struct ifnet *ifp;
3266 1.1 fvdl struct ifmediareq *ifmr;
3267 1.1 fvdl {
3268 1.1 fvdl struct bge_softc *sc = ifp->if_softc;
3269 1.1 fvdl struct mii_data *mii = &sc->bge_mii;
3270 1.1 fvdl
3271 1.1 fvdl if (sc->bge_tbi) {
3272 1.1 fvdl ifmr->ifm_status = IFM_AVALID;
3273 1.1 fvdl ifmr->ifm_active = IFM_ETHER;
3274 1.1 fvdl if (CSR_READ_4(sc, BGE_MAC_STS) &
3275 1.1 fvdl BGE_MACSTAT_TBI_PCS_SYNCHED)
3276 1.1 fvdl ifmr->ifm_status |= IFM_ACTIVE;
3277 1.1 fvdl ifmr->ifm_active |= IFM_1000_SX;
3278 1.1 fvdl if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX)
3279 1.1 fvdl ifmr->ifm_active |= IFM_HDX;
3280 1.1 fvdl else
3281 1.1 fvdl ifmr->ifm_active |= IFM_FDX;
3282 1.1 fvdl return;
3283 1.1 fvdl }
3284 1.1 fvdl
3285 1.1 fvdl mii_pollstat(mii);
3286 1.1 fvdl ifmr->ifm_active = mii->mii_media_active;
3287 1.1 fvdl ifmr->ifm_status = mii->mii_media_status;
3288 1.1 fvdl }
3289 1.1 fvdl
3290 1.1 fvdl int
3291 1.1 fvdl bge_ioctl(ifp, command, data)
3292 1.1 fvdl struct ifnet *ifp;
3293 1.1 fvdl u_long command;
3294 1.1 fvdl caddr_t data;
3295 1.1 fvdl {
3296 1.1 fvdl struct bge_softc *sc = ifp->if_softc;
3297 1.1 fvdl struct ifreq *ifr = (struct ifreq *) data;
3298 1.1 fvdl int s, error = 0;
3299 1.1 fvdl struct mii_data *mii;
3300 1.1 fvdl
3301 1.1 fvdl s = splnet();
3302 1.1 fvdl
3303 1.1 fvdl switch(command) {
3304 1.1 fvdl case SIOCSIFFLAGS:
3305 1.1 fvdl if (ifp->if_flags & IFF_UP) {
3306 1.1 fvdl /*
3307 1.1 fvdl * If only the state of the PROMISC flag changed,
3308 1.1 fvdl * then just use the 'set promisc mode' command
3309 1.1 fvdl * instead of reinitializing the entire NIC. Doing
3310 1.1 fvdl * a full re-init means reloading the firmware and
3311 1.1 fvdl * waiting for it to start up, which may take a
3312 1.1 fvdl * second or two.
3313 1.1 fvdl */
3314 1.1 fvdl if (ifp->if_flags & IFF_RUNNING &&
3315 1.1 fvdl ifp->if_flags & IFF_PROMISC &&
3316 1.1 fvdl !(sc->bge_if_flags & IFF_PROMISC)) {
3317 1.1 fvdl BGE_SETBIT(sc, BGE_RX_MODE,
3318 1.1 fvdl BGE_RXMODE_RX_PROMISC);
3319 1.1 fvdl } else if (ifp->if_flags & IFF_RUNNING &&
3320 1.1 fvdl !(ifp->if_flags & IFF_PROMISC) &&
3321 1.1 fvdl sc->bge_if_flags & IFF_PROMISC) {
3322 1.1 fvdl BGE_CLRBIT(sc, BGE_RX_MODE,
3323 1.1 fvdl BGE_RXMODE_RX_PROMISC);
3324 1.1 fvdl } else
3325 1.1 fvdl bge_init(ifp);
3326 1.1 fvdl } else {
3327 1.1 fvdl if (ifp->if_flags & IFF_RUNNING) {
3328 1.1 fvdl bge_stop(sc);
3329 1.1 fvdl }
3330 1.1 fvdl }
3331 1.1 fvdl sc->bge_if_flags = ifp->if_flags;
3332 1.1 fvdl error = 0;
3333 1.1 fvdl break;
3334 1.1 fvdl case SIOCSIFMEDIA:
3335 1.1 fvdl case SIOCGIFMEDIA:
3336 1.1 fvdl if (sc->bge_tbi) {
3337 1.1 fvdl error = ifmedia_ioctl(ifp, ifr, &sc->bge_ifmedia,
3338 1.1 fvdl command);
3339 1.1 fvdl } else {
3340 1.1 fvdl mii = &sc->bge_mii;
3341 1.1 fvdl error = ifmedia_ioctl(ifp, ifr, &mii->mii_media,
3342 1.1 fvdl command);
3343 1.1 fvdl }
3344 1.1 fvdl error = 0;
3345 1.1 fvdl break;
3346 1.1 fvdl default:
3347 1.1 fvdl error = ether_ioctl(ifp, command, data);
3348 1.1 fvdl if (error == ENETRESET) {
3349 1.1 fvdl bge_setmulti(sc);
3350 1.1 fvdl error = 0;
3351 1.1 fvdl }
3352 1.1 fvdl break;
3353 1.1 fvdl }
3354 1.1 fvdl
3355 1.1 fvdl splx(s);
3356 1.1 fvdl
3357 1.1 fvdl return(error);
3358 1.1 fvdl }
3359 1.1 fvdl
3360 1.1 fvdl void
3361 1.1 fvdl bge_watchdog(ifp)
3362 1.1 fvdl struct ifnet *ifp;
3363 1.1 fvdl {
3364 1.1 fvdl struct bge_softc *sc;
3365 1.1 fvdl
3366 1.1 fvdl sc = ifp->if_softc;
3367 1.1 fvdl
3368 1.1 fvdl printf("%s: watchdog timeout -- resetting\n", sc->bge_dev.dv_xname);
3369 1.1 fvdl
3370 1.1 fvdl ifp->if_flags &= ~IFF_RUNNING;
3371 1.1 fvdl bge_init(ifp);
3372 1.1 fvdl
3373 1.1 fvdl ifp->if_oerrors++;
3374 1.1 fvdl }
3375 1.1 fvdl
3376 1.11 thorpej static void
3377 1.11 thorpej bge_stop_block(struct bge_softc *sc, bus_addr_t reg, uint32_t bit)
3378 1.11 thorpej {
3379 1.11 thorpej int i;
3380 1.11 thorpej
3381 1.11 thorpej BGE_CLRBIT(sc, reg, bit);
3382 1.11 thorpej
3383 1.11 thorpej for (i = 0; i < BGE_TIMEOUT; i++) {
3384 1.11 thorpej if ((CSR_READ_4(sc, reg) & bit) == 0)
3385 1.11 thorpej return;
3386 1.11 thorpej delay(100);
3387 1.11 thorpej }
3388 1.11 thorpej
3389 1.11 thorpej printf("%s: block failed to stop: reg 0x%lx, bit 0x%08x\n",
3390 1.11 thorpej sc->bge_dev.dv_xname, (u_long) reg, bit);
3391 1.11 thorpej }
3392 1.11 thorpej
3393 1.1 fvdl /*
3394 1.1 fvdl * Stop the adapter and free any mbufs allocated to the
3395 1.1 fvdl * RX and TX lists.
3396 1.1 fvdl */
3397 1.1 fvdl void
3398 1.1 fvdl bge_stop(sc)
3399 1.1 fvdl struct bge_softc *sc;
3400 1.1 fvdl {
3401 1.1 fvdl struct ifnet *ifp = &sc->ethercom.ec_if;
3402 1.1 fvdl
3403 1.1 fvdl callout_stop(&sc->bge_timeout);
3404 1.1 fvdl
3405 1.1 fvdl /*
3406 1.1 fvdl * Disable all of the receiver blocks
3407 1.1 fvdl */
3408 1.11 thorpej bge_stop_block(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE);
3409 1.11 thorpej bge_stop_block(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE);
3410 1.11 thorpej bge_stop_block(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);
3411 1.44 hannken if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) {
3412 1.44 hannken bge_stop_block(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE);
3413 1.44 hannken }
3414 1.11 thorpej bge_stop_block(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE);
3415 1.11 thorpej bge_stop_block(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);
3416 1.11 thorpej bge_stop_block(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE);
3417 1.1 fvdl
3418 1.1 fvdl /*
3419 1.1 fvdl * Disable all of the transmit blocks
3420 1.1 fvdl */
3421 1.11 thorpej bge_stop_block(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE);
3422 1.11 thorpej bge_stop_block(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE);
3423 1.11 thorpej bge_stop_block(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE);
3424 1.11 thorpej bge_stop_block(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE);
3425 1.11 thorpej bge_stop_block(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE);
3426 1.44 hannken if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) {
3427 1.44 hannken bge_stop_block(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE);
3428 1.44 hannken }
3429 1.11 thorpej bge_stop_block(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);
3430 1.1 fvdl
3431 1.1 fvdl /*
3432 1.1 fvdl * Shut down all of the memory managers and related
3433 1.1 fvdl * state machines.
3434 1.1 fvdl */
3435 1.11 thorpej bge_stop_block(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE);
3436 1.11 thorpej bge_stop_block(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE);
3437 1.44 hannken if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) {
3438 1.44 hannken bge_stop_block(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE);
3439 1.44 hannken }
3440 1.11 thorpej
3441 1.1 fvdl CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF);
3442 1.1 fvdl CSR_WRITE_4(sc, BGE_FTQ_RESET, 0);
3443 1.11 thorpej
3444 1.44 hannken if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) {
3445 1.44 hannken bge_stop_block(sc, BGE_BMAN_MODE, BGE_BMANMODE_ENABLE);
3446 1.44 hannken bge_stop_block(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE);
3447 1.44 hannken }
3448 1.1 fvdl
3449 1.1 fvdl /* Disable host interrupts. */
3450 1.1 fvdl BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR);
3451 1.1 fvdl CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 1);
3452 1.1 fvdl
3453 1.1 fvdl /*
3454 1.1 fvdl * Tell firmware we're shutting down.
3455 1.1 fvdl */
3456 1.1 fvdl BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
3457 1.1 fvdl
3458 1.1 fvdl /* Free the RX lists. */
3459 1.1 fvdl bge_free_rx_ring_std(sc);
3460 1.1 fvdl
3461 1.1 fvdl /* Free jumbo RX list. */
3462 1.1 fvdl bge_free_rx_ring_jumbo(sc);
3463 1.1 fvdl
3464 1.1 fvdl /* Free TX buffers. */
3465 1.1 fvdl bge_free_tx_ring(sc);
3466 1.1 fvdl
3467 1.1 fvdl /*
3468 1.1 fvdl * Isolate/power down the PHY.
3469 1.1 fvdl */
3470 1.1 fvdl if (!sc->bge_tbi)
3471 1.1 fvdl mii_down(&sc->bge_mii);
3472 1.1 fvdl
3473 1.1 fvdl sc->bge_link = 0;
3474 1.1 fvdl
3475 1.1 fvdl sc->bge_tx_saved_considx = BGE_TXCONS_UNSET;
3476 1.1 fvdl
3477 1.1 fvdl ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
3478 1.1 fvdl }
3479 1.1 fvdl
3480 1.1 fvdl /*
3481 1.1 fvdl * Stop all chip I/O so that the kernel's probe routines don't
3482 1.1 fvdl * get confused by errant DMAs when rebooting.
3483 1.1 fvdl */
3484 1.1 fvdl void
3485 1.1 fvdl bge_shutdown(xsc)
3486 1.1 fvdl void *xsc;
3487 1.1 fvdl {
3488 1.1 fvdl struct bge_softc *sc = (struct bge_softc *)xsc;
3489 1.1 fvdl
3490 1.1 fvdl bge_stop(sc);
3491 1.1 fvdl bge_reset(sc);
3492 1.1 fvdl }
3493