if_bge.c revision 1.106
1 /* $NetBSD: if_bge.c,v 1.106 2006/04/27 18:09:54 jonathan Exp $ */ 2 3 /* 4 * Copyright (c) 2001 Wind River Systems 5 * Copyright (c) 1997, 1998, 1999, 2001 6 * Bill Paul <wpaul (at) windriver.com>. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Bill Paul. 19 * 4. Neither the name of the author nor the names of any co-contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 33 * THE POSSIBILITY OF SUCH DAMAGE. 34 * 35 * $FreeBSD: if_bge.c,v 1.13 2002/04/04 06:01:31 wpaul Exp $ 36 */ 37 38 /* 39 * Broadcom BCM570x family gigabit ethernet driver for NetBSD. 40 * 41 * NetBSD version by: 42 * 43 * Frank van der Linden <fvdl (at) wasabisystems.com> 44 * Jason Thorpe <thorpej (at) wasabisystems.com> 45 * Jonathan Stone <jonathan (at) dsg.stanford.edu> 46 * 47 * Originally written for FreeBSD by Bill Paul <wpaul (at) windriver.com> 48 * Senior Engineer, Wind River Systems 49 */ 50 51 /* 52 * The Broadcom BCM5700 is based on technology originally developed by 53 * Alteon Networks as part of the Tigon I and Tigon II gigabit ethernet 54 * MAC chips. The BCM5700, sometimes refered to as the Tigon III, has 55 * two on-board MIPS R4000 CPUs and can have as much as 16MB of external 56 * SSRAM. The BCM5700 supports TCP, UDP and IP checksum offload, jumbo 57 * frames, highly configurable RX filtering, and 16 RX and TX queues 58 * (which, along with RX filter rules, can be used for QOS applications). 59 * Other features, such as TCP segmentation, may be available as part 60 * of value-added firmware updates. Unlike the Tigon I and Tigon II, 61 * firmware images can be stored in hardware and need not be compiled 62 * into the driver. 63 * 64 * The BCM5700 supports the PCI v2.2 and PCI-X v1.0 standards, and will 65 * function in a 32-bit/64-bit 33/66MHz bus, or a 64-bit/133MHz bus. 66 * 67 * The BCM5701 is a single-chip solution incorporating both the BCM5700 68 * MAC and a BCM5401 10/100/1000 PHY. Unlike the BCM5700, the BCM5701 69 * does not support external SSRAM. 70 * 71 * Broadcom also produces a variation of the BCM5700 under the "Altima" 72 * brand name, which is functionally similar but lacks PCI-X support. 73 * 74 * Without external SSRAM, you can only have at most 4 TX rings, 75 * and the use of the mini RX ring is disabled. This seems to imply 76 * that these features are simply not available on the BCM5701. As a 77 * result, this driver does not implement any support for the mini RX 78 * ring. 79 */ 80 81 #include <sys/cdefs.h> 82 __KERNEL_RCSID(0, "$NetBSD: if_bge.c,v 1.106 2006/04/27 18:09:54 jonathan Exp $"); 83 84 #include "bpfilter.h" 85 #include "vlan.h" 86 87 #include <sys/param.h> 88 #include <sys/systm.h> 89 #include <sys/callout.h> 90 #include <sys/sockio.h> 91 #include <sys/mbuf.h> 92 #include <sys/malloc.h> 93 #include <sys/kernel.h> 94 #include <sys/device.h> 95 #include <sys/socket.h> 96 #include <sys/sysctl.h> 97 98 #include <net/if.h> 99 #include <net/if_dl.h> 100 #include <net/if_media.h> 101 #include <net/if_ether.h> 102 103 #ifdef INET 104 #include <netinet/in.h> 105 #include <netinet/in_systm.h> 106 #include <netinet/in_var.h> 107 #include <netinet/ip.h> 108 #endif 109 110 /* Headers for TCP Segmentation Offload (TSO) */ 111 #include <netinet/in_systm.h> /* n_time for <netinet/ip.h>... */ 112 #include <netinet/in.h> /* ip_{src,dst}, for <netinet/ip.h> */ 113 #include <netinet/ip.h> /* for struct ip */ 114 #include <netinet/tcp.h> /* for struct tcphdr */ 115 116 117 #if NBPFILTER > 0 118 #include <net/bpf.h> 119 #endif 120 121 #include <dev/pci/pcireg.h> 122 #include <dev/pci/pcivar.h> 123 #include <dev/pci/pcidevs.h> 124 125 #include <dev/mii/mii.h> 126 #include <dev/mii/miivar.h> 127 #include <dev/mii/miidevs.h> 128 #include <dev/mii/brgphyreg.h> 129 130 #include <dev/pci/if_bgereg.h> 131 132 #include <uvm/uvm_extern.h> 133 134 #define ETHER_MIN_NOPAD (ETHER_MIN_LEN - ETHER_CRC_LEN) /* i.e., 60 */ 135 136 137 /* 138 * Tunable thresholds for rx-side bge interrupt mitigation. 139 */ 140 141 /* 142 * The pairs of values below were obtained from empirical measurement 143 * on bcm5700 rev B2; they ar designed to give roughly 1 receive 144 * interrupt for every N packets received, where N is, approximately, 145 * the second value (rx_max_bds) in each pair. The values are chosen 146 * such that moving from one pair to the succeeding pair was observed 147 * to roughly halve interrupt rate under sustained input packet load. 148 * The values were empirically chosen to avoid overflowing internal 149 * limits on the bcm5700: inreasing rx_ticks much beyond 600 150 * results in internal wrapping and higher interrupt rates. 151 * The limit of 46 frames was chosen to match NFS workloads. 152 * 153 * These values also work well on bcm5701, bcm5704C, and (less 154 * tested) bcm5703. On other chipsets, (including the Altima chip 155 * family), the larger values may overflow internal chip limits, 156 * leading to increasing interrupt rates rather than lower interrupt 157 * rates. 158 * 159 * Applications using heavy interrupt mitigation (interrupting every 160 * 32 or 46 frames) in both directions may need to increase the TCP 161 * windowsize to above 131072 bytes (e.g., to 199608 bytes) to sustain 162 * full link bandwidth, due to ACKs and window updates lingering 163 * in the RX queue during the 30-to-40-frame interrupt-mitigation window. 164 */ 165 static const struct bge_load_rx_thresh { 166 int rx_ticks; 167 int rx_max_bds; } 168 bge_rx_threshes[] = { 169 { 32, 2 }, 170 { 50, 4 }, 171 { 100, 8 }, 172 { 192, 16 }, 173 { 416, 32 }, 174 { 598, 46 } 175 }; 176 #define NBGE_RX_THRESH (sizeof(bge_rx_threshes) / sizeof(bge_rx_threshes[0])) 177 178 /* XXX patchable; should be sysctl'able */ 179 static int bge_auto_thresh = 1; 180 static int bge_rx_thresh_lvl; 181 182 static int bge_rxthresh_nodenum; 183 184 static int bge_probe(device_t, cfdata_t, void *); 185 static void bge_attach(device_t, device_t, void *); 186 static void bge_powerhook(int, void *); 187 static void bge_release_resources(struct bge_softc *); 188 static void bge_txeof(struct bge_softc *); 189 static void bge_rxeof(struct bge_softc *); 190 191 static void bge_tick(void *); 192 static void bge_stats_update(struct bge_softc *); 193 static int bge_encap(struct bge_softc *, struct mbuf *, u_int32_t *); 194 195 static int bge_intr(void *); 196 static void bge_start(struct ifnet *); 197 static int bge_ioctl(struct ifnet *, u_long, caddr_t); 198 static int bge_init(struct ifnet *); 199 static void bge_stop(struct bge_softc *); 200 static void bge_watchdog(struct ifnet *); 201 static void bge_shutdown(void *); 202 static int bge_ifmedia_upd(struct ifnet *); 203 static void bge_ifmedia_sts(struct ifnet *, struct ifmediareq *); 204 205 static void bge_setmulti(struct bge_softc *); 206 207 static void bge_handle_events(struct bge_softc *); 208 static int bge_alloc_jumbo_mem(struct bge_softc *); 209 #if 0 /* XXX */ 210 static void bge_free_jumbo_mem(struct bge_softc *); 211 #endif 212 static void *bge_jalloc(struct bge_softc *); 213 static void bge_jfree(struct mbuf *, caddr_t, size_t, void *); 214 static int bge_newbuf_std(struct bge_softc *, int, struct mbuf *, 215 bus_dmamap_t); 216 static int bge_newbuf_jumbo(struct bge_softc *, int, struct mbuf *); 217 static int bge_init_rx_ring_std(struct bge_softc *); 218 static void bge_free_rx_ring_std(struct bge_softc *); 219 static int bge_init_rx_ring_jumbo(struct bge_softc *); 220 static void bge_free_rx_ring_jumbo(struct bge_softc *); 221 static void bge_free_tx_ring(struct bge_softc *); 222 static int bge_init_tx_ring(struct bge_softc *); 223 224 static int bge_chipinit(struct bge_softc *); 225 static int bge_blockinit(struct bge_softc *); 226 static int bge_setpowerstate(struct bge_softc *, int); 227 228 static void bge_reset(struct bge_softc *); 229 230 #define BGE_DEBUG 231 #ifdef BGE_DEBUG 232 #define DPRINTF(x) if (bgedebug) printf x 233 #define DPRINTFN(n,x) if (bgedebug >= (n)) printf x 234 #define BGE_TSO_PRINTF(x) do { if (bge_tso_debug) printf x ;} while (0) 235 int bgedebug = 0; 236 int bge_tso_debug = 0; 237 #else 238 #define DPRINTF(x) 239 #define DPRINTFN(n,x) 240 #define BGE_TSO_PRINTF(x) 241 #endif 242 243 #ifdef BGE_EVENT_COUNTERS 244 #define BGE_EVCNT_INCR(ev) (ev).ev_count++ 245 #define BGE_EVCNT_ADD(ev, val) (ev).ev_count += (val) 246 #define BGE_EVCNT_UPD(ev, val) (ev).ev_count = (val) 247 #else 248 #define BGE_EVCNT_INCR(ev) /* nothing */ 249 #define BGE_EVCNT_ADD(ev, val) /* nothing */ 250 #define BGE_EVCNT_UPD(ev, val) /* nothing */ 251 #endif 252 253 /* Various chip quirks. */ 254 #define BGE_QUIRK_LINK_STATE_BROKEN 0x00000001 255 #define BGE_QUIRK_CSUM_BROKEN 0x00000002 256 #define BGE_QUIRK_ONLY_PHY_1 0x00000004 257 #define BGE_QUIRK_5700_SMALLDMA 0x00000008 258 #define BGE_QUIRK_5700_PCIX_REG_BUG 0x00000010 259 #define BGE_QUIRK_PRODUCER_BUG 0x00000020 260 #define BGE_QUIRK_PCIX_DMA_ALIGN_BUG 0x00000040 261 #define BGE_QUIRK_5705_CORE 0x00000080 262 #define BGE_QUIRK_FEWER_MBUFS 0x00000100 263 264 /* 265 * XXX: how to handle variants based on 5750 and derivatives: 266 * 5750 5751, 5721, possibly 5714, 5752, and 5708?, which 267 * in general behave like a 5705, except with additional quirks. 268 * This driver's current handling of the 5721 is wrong; 269 * how we map ASIC revision to "quirks" needs more thought. 270 * (defined here until the thought is done). 271 */ 272 #define BGE_IS_5714_FAMILY(sc) \ 273 (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5714 || \ 274 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5780 || \ 275 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5715 ) 276 277 #define BGE_IS_5750_OR_BEYOND(sc) \ 278 (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5750 || \ 279 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5752 || \ 280 BGE_IS_5714_FAMILY(sc) ) 281 282 #define BGE_IS_5705_OR_BEYOND(sc) \ 283 ( ((sc)->bge_quirks & BGE_QUIRK_5705_CORE) || \ 284 BGE_IS_5750_OR_BEYOND(sc) ) 285 286 287 /* following bugs are common to bcm5700 rev B, all flavours */ 288 #define BGE_QUIRK_5700_COMMON \ 289 (BGE_QUIRK_5700_SMALLDMA|BGE_QUIRK_PRODUCER_BUG) 290 291 CFATTACH_DECL(bge, sizeof(struct bge_softc), 292 bge_probe, bge_attach, NULL, NULL); 293 294 static u_int32_t 295 bge_readmem_ind(struct bge_softc *sc, int off) 296 { 297 struct pci_attach_args *pa = &(sc->bge_pa); 298 pcireg_t val; 299 300 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_MEMWIN_BASEADDR, off); 301 val = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_MEMWIN_DATA); 302 return val; 303 } 304 305 static void 306 bge_writemem_ind(struct bge_softc *sc, int off, int val) 307 { 308 struct pci_attach_args *pa = &(sc->bge_pa); 309 310 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_MEMWIN_BASEADDR, off); 311 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_MEMWIN_DATA, val); 312 } 313 314 #ifdef notdef 315 static u_int32_t 316 bge_readreg_ind(struct bge_softc *sc, int off) 317 { 318 struct pci_attach_args *pa = &(sc->bge_pa); 319 320 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_REG_BASEADDR, off); 321 return(pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_REG_DATA)); 322 } 323 #endif 324 325 static void 326 bge_writereg_ind(struct bge_softc *sc, int off, int val) 327 { 328 struct pci_attach_args *pa = &(sc->bge_pa); 329 330 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_REG_BASEADDR, off); 331 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_REG_DATA, val); 332 } 333 334 #ifdef notdef 335 static u_int8_t 336 bge_vpd_readbyte(struct bge_softc *sc, int addr) 337 { 338 int i; 339 u_int32_t val; 340 struct pci_attach_args *pa = &(sc->bge_pa); 341 342 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_VPD_ADDR, addr); 343 for (i = 0; i < BGE_TIMEOUT * 10; i++) { 344 DELAY(10); 345 if (pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_VPD_ADDR) & 346 BGE_VPD_FLAG) 347 break; 348 } 349 350 if (i == BGE_TIMEOUT) { 351 printf("%s: VPD read timed out\n", sc->bge_dev.dv_xname); 352 return(0); 353 } 354 355 val = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_VPD_DATA); 356 357 return((val >> ((addr % 4) * 8)) & 0xFF); 358 } 359 360 static void 361 bge_vpd_read_res(struct bge_softc *sc, struct vpd_res *res, int addr) 362 { 363 int i; 364 u_int8_t *ptr; 365 366 ptr = (u_int8_t *)res; 367 for (i = 0; i < sizeof(struct vpd_res); i++) 368 ptr[i] = bge_vpd_readbyte(sc, i + addr); 369 } 370 371 static void 372 bge_vpd_read(struct bge_softc *sc) 373 { 374 int pos = 0, i; 375 struct vpd_res res; 376 377 if (sc->bge_vpd_prodname != NULL) 378 free(sc->bge_vpd_prodname, M_DEVBUF); 379 if (sc->bge_vpd_readonly != NULL) 380 free(sc->bge_vpd_readonly, M_DEVBUF); 381 sc->bge_vpd_prodname = NULL; 382 sc->bge_vpd_readonly = NULL; 383 384 bge_vpd_read_res(sc, &res, pos); 385 386 if (res.vr_id != VPD_RES_ID) { 387 printf("%s: bad VPD resource id: expected %x got %x\n", 388 sc->bge_dev.dv_xname, VPD_RES_ID, res.vr_id); 389 return; 390 } 391 392 pos += sizeof(res); 393 sc->bge_vpd_prodname = malloc(res.vr_len + 1, M_DEVBUF, M_NOWAIT); 394 if (sc->bge_vpd_prodname == NULL) 395 panic("bge_vpd_read"); 396 for (i = 0; i < res.vr_len; i++) 397 sc->bge_vpd_prodname[i] = bge_vpd_readbyte(sc, i + pos); 398 sc->bge_vpd_prodname[i] = '\0'; 399 pos += i; 400 401 bge_vpd_read_res(sc, &res, pos); 402 403 if (res.vr_id != VPD_RES_READ) { 404 printf("%s: bad VPD resource id: expected %x got %x\n", 405 sc->bge_dev.dv_xname, VPD_RES_READ, res.vr_id); 406 return; 407 } 408 409 pos += sizeof(res); 410 sc->bge_vpd_readonly = malloc(res.vr_len, M_DEVBUF, M_NOWAIT); 411 if (sc->bge_vpd_readonly == NULL) 412 panic("bge_vpd_read"); 413 for (i = 0; i < res.vr_len + 1; i++) 414 sc->bge_vpd_readonly[i] = bge_vpd_readbyte(sc, i + pos); 415 } 416 #endif 417 418 /* 419 * Read a byte of data stored in the EEPROM at address 'addr.' The 420 * BCM570x supports both the traditional bitbang interface and an 421 * auto access interface for reading the EEPROM. We use the auto 422 * access method. 423 */ 424 static u_int8_t 425 bge_eeprom_getbyte(struct bge_softc *sc, int addr, u_int8_t *dest) 426 { 427 int i; 428 u_int32_t byte = 0; 429 430 /* 431 * Enable use of auto EEPROM access so we can avoid 432 * having to use the bitbang method. 433 */ 434 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM); 435 436 /* Reset the EEPROM, load the clock period. */ 437 CSR_WRITE_4(sc, BGE_EE_ADDR, 438 BGE_EEADDR_RESET|BGE_EEHALFCLK(BGE_HALFCLK_384SCL)); 439 DELAY(20); 440 441 /* Issue the read EEPROM command. */ 442 CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr); 443 444 /* Wait for completion */ 445 for(i = 0; i < BGE_TIMEOUT * 10; i++) { 446 DELAY(10); 447 if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE) 448 break; 449 } 450 451 if (i == BGE_TIMEOUT) { 452 printf("%s: eeprom read timed out\n", sc->bge_dev.dv_xname); 453 return(0); 454 } 455 456 /* Get result. */ 457 byte = CSR_READ_4(sc, BGE_EE_DATA); 458 459 *dest = (byte >> ((addr % 4) * 8)) & 0xFF; 460 461 return(0); 462 } 463 464 /* 465 * Read a sequence of bytes from the EEPROM. 466 */ 467 static int 468 bge_read_eeprom(struct bge_softc *sc, caddr_t dest, int off, int cnt) 469 { 470 int err = 0, i; 471 u_int8_t byte = 0; 472 473 for (i = 0; i < cnt; i++) { 474 err = bge_eeprom_getbyte(sc, off + i, &byte); 475 if (err) 476 break; 477 *(dest + i) = byte; 478 } 479 480 return(err ? 1 : 0); 481 } 482 483 static int 484 bge_miibus_readreg(device_t dev, int phy, int reg) 485 { 486 struct bge_softc *sc = (struct bge_softc *)dev; 487 u_int32_t val; 488 u_int32_t saved_autopoll; 489 int i; 490 491 /* 492 * Several chips with builtin PHYs will incorrectly answer to 493 * other PHY instances than the builtin PHY at id 1. 494 */ 495 if (phy != 1 && (sc->bge_quirks & BGE_QUIRK_ONLY_PHY_1)) 496 return(0); 497 498 /* Reading with autopolling on may trigger PCI errors */ 499 saved_autopoll = CSR_READ_4(sc, BGE_MI_MODE); 500 if (saved_autopoll & BGE_MIMODE_AUTOPOLL) { 501 CSR_WRITE_4(sc, BGE_MI_MODE, 502 saved_autopoll &~ BGE_MIMODE_AUTOPOLL); 503 DELAY(40); 504 } 505 506 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_READ|BGE_MICOMM_BUSY| 507 BGE_MIPHY(phy)|BGE_MIREG(reg)); 508 509 for (i = 0; i < BGE_TIMEOUT; i++) { 510 val = CSR_READ_4(sc, BGE_MI_COMM); 511 if (!(val & BGE_MICOMM_BUSY)) 512 break; 513 delay(10); 514 } 515 516 if (i == BGE_TIMEOUT) { 517 printf("%s: PHY read timed out\n", sc->bge_dev.dv_xname); 518 val = 0; 519 goto done; 520 } 521 522 val = CSR_READ_4(sc, BGE_MI_COMM); 523 524 done: 525 if (saved_autopoll & BGE_MIMODE_AUTOPOLL) { 526 CSR_WRITE_4(sc, BGE_MI_MODE, saved_autopoll); 527 DELAY(40); 528 } 529 530 if (val & BGE_MICOMM_READFAIL) 531 return(0); 532 533 return(val & 0xFFFF); 534 } 535 536 static void 537 bge_miibus_writereg(device_t dev, int phy, int reg, int val) 538 { 539 struct bge_softc *sc = (struct bge_softc *)dev; 540 u_int32_t saved_autopoll; 541 int i; 542 543 /* Touching the PHY while autopolling is on may trigger PCI errors */ 544 saved_autopoll = CSR_READ_4(sc, BGE_MI_MODE); 545 if (saved_autopoll & BGE_MIMODE_AUTOPOLL) { 546 delay(40); 547 CSR_WRITE_4(sc, BGE_MI_MODE, 548 saved_autopoll & (~BGE_MIMODE_AUTOPOLL)); 549 delay(10); /* 40 usec is supposed to be adequate */ 550 } 551 552 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_WRITE|BGE_MICOMM_BUSY| 553 BGE_MIPHY(phy)|BGE_MIREG(reg)|val); 554 555 for (i = 0; i < BGE_TIMEOUT; i++) { 556 if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY)) 557 break; 558 delay(10); 559 } 560 561 if (saved_autopoll & BGE_MIMODE_AUTOPOLL) { 562 CSR_WRITE_4(sc, BGE_MI_MODE, saved_autopoll); 563 delay(40); 564 } 565 566 if (i == BGE_TIMEOUT) { 567 printf("%s: PHY read timed out\n", sc->bge_dev.dv_xname); 568 } 569 } 570 571 static void 572 bge_miibus_statchg(device_t dev) 573 { 574 struct bge_softc *sc = (struct bge_softc *)dev; 575 struct mii_data *mii = &sc->bge_mii; 576 577 /* 578 * Get flow control negotiation result. 579 */ 580 if (IFM_SUBTYPE(mii->mii_media.ifm_cur->ifm_media) == IFM_AUTO && 581 (mii->mii_media_active & IFM_ETH_FMASK) != sc->bge_flowflags) { 582 sc->bge_flowflags = mii->mii_media_active & IFM_ETH_FMASK; 583 mii->mii_media_active &= ~IFM_ETH_FMASK; 584 } 585 586 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_PORTMODE); 587 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) { 588 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_GMII); 589 } else { 590 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_MII); 591 } 592 593 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 594 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX); 595 } else { 596 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX); 597 } 598 599 /* 600 * 802.3x flow control 601 */ 602 if (sc->bge_flowflags & IFM_ETH_RXPAUSE) { 603 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_FLOWCTL_ENABLE); 604 } else { 605 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_FLOWCTL_ENABLE); 606 } 607 if (sc->bge_flowflags & IFM_ETH_TXPAUSE) { 608 BGE_SETBIT(sc, BGE_TX_MODE, BGE_TXMODE_FLOWCTL_ENABLE); 609 } else { 610 BGE_CLRBIT(sc, BGE_TX_MODE, BGE_TXMODE_FLOWCTL_ENABLE); 611 } 612 } 613 614 /* 615 * Update rx threshold levels to values in a particular slot 616 * of the interrupt-mitigation table bge_rx_threshes. 617 */ 618 static void 619 bge_set_thresh(struct ifnet *ifp, int lvl) 620 { 621 struct bge_softc *sc = ifp->if_softc; 622 int s; 623 624 /* For now, just save the new Rx-intr thresholds and record 625 * that a threshold update is pending. Updating the hardware 626 * registers here (even at splhigh()) is observed to 627 * occasionaly cause glitches where Rx-interrupts are not 628 * honoured for up to 10 seconds. jonathan (at) NetBSD.org, 2003-04-05 629 */ 630 s = splnet(); 631 sc->bge_rx_coal_ticks = bge_rx_threshes[lvl].rx_ticks; 632 sc->bge_rx_max_coal_bds = bge_rx_threshes[lvl].rx_max_bds; 633 sc->bge_pending_rxintr_change = 1; 634 splx(s); 635 636 return; 637 } 638 639 640 /* 641 * Update Rx thresholds of all bge devices 642 */ 643 static void 644 bge_update_all_threshes(int lvl) 645 { 646 struct ifnet *ifp; 647 const char * const namebuf = "bge"; 648 int namelen; 649 650 if (lvl < 0) 651 lvl = 0; 652 else if( lvl >= NBGE_RX_THRESH) 653 lvl = NBGE_RX_THRESH - 1; 654 655 namelen = strlen(namebuf); 656 /* 657 * Now search all the interfaces for this name/number 658 */ 659 IFNET_FOREACH(ifp) { 660 if (strncmp(ifp->if_xname, namebuf, namelen) != 0) 661 continue; 662 /* We got a match: update if doing auto-threshold-tuning */ 663 if (bge_auto_thresh) 664 bge_set_thresh(ifp, lvl); 665 } 666 } 667 668 /* 669 * Handle events that have triggered interrupts. 670 */ 671 static void 672 bge_handle_events(struct bge_softc *sc) 673 { 674 675 return; 676 } 677 678 /* 679 * Memory management for jumbo frames. 680 */ 681 682 static int 683 bge_alloc_jumbo_mem(struct bge_softc *sc) 684 { 685 caddr_t ptr, kva; 686 bus_dma_segment_t seg; 687 int i, rseg, state, error; 688 struct bge_jpool_entry *entry; 689 690 state = error = 0; 691 692 /* Grab a big chunk o' storage. */ 693 if (bus_dmamem_alloc(sc->bge_dmatag, BGE_JMEM, PAGE_SIZE, 0, 694 &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 695 printf("%s: can't alloc rx buffers\n", sc->bge_dev.dv_xname); 696 return ENOBUFS; 697 } 698 699 state = 1; 700 if (bus_dmamem_map(sc->bge_dmatag, &seg, rseg, BGE_JMEM, &kva, 701 BUS_DMA_NOWAIT)) { 702 printf("%s: can't map DMA buffers (%d bytes)\n", 703 sc->bge_dev.dv_xname, (int)BGE_JMEM); 704 error = ENOBUFS; 705 goto out; 706 } 707 708 state = 2; 709 if (bus_dmamap_create(sc->bge_dmatag, BGE_JMEM, 1, BGE_JMEM, 0, 710 BUS_DMA_NOWAIT, &sc->bge_cdata.bge_rx_jumbo_map)) { 711 printf("%s: can't create DMA map\n", sc->bge_dev.dv_xname); 712 error = ENOBUFS; 713 goto out; 714 } 715 716 state = 3; 717 if (bus_dmamap_load(sc->bge_dmatag, sc->bge_cdata.bge_rx_jumbo_map, 718 kva, BGE_JMEM, NULL, BUS_DMA_NOWAIT)) { 719 printf("%s: can't load DMA map\n", sc->bge_dev.dv_xname); 720 error = ENOBUFS; 721 goto out; 722 } 723 724 state = 4; 725 sc->bge_cdata.bge_jumbo_buf = (caddr_t)kva; 726 DPRINTFN(1,("bge_jumbo_buf = %p\n", sc->bge_cdata.bge_jumbo_buf)); 727 728 SLIST_INIT(&sc->bge_jfree_listhead); 729 SLIST_INIT(&sc->bge_jinuse_listhead); 730 731 /* 732 * Now divide it up into 9K pieces and save the addresses 733 * in an array. 734 */ 735 ptr = sc->bge_cdata.bge_jumbo_buf; 736 for (i = 0; i < BGE_JSLOTS; i++) { 737 sc->bge_cdata.bge_jslots[i] = ptr; 738 ptr += BGE_JLEN; 739 entry = malloc(sizeof(struct bge_jpool_entry), 740 M_DEVBUF, M_NOWAIT); 741 if (entry == NULL) { 742 printf("%s: no memory for jumbo buffer queue!\n", 743 sc->bge_dev.dv_xname); 744 error = ENOBUFS; 745 goto out; 746 } 747 entry->slot = i; 748 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, 749 entry, jpool_entries); 750 } 751 out: 752 if (error != 0) { 753 switch (state) { 754 case 4: 755 bus_dmamap_unload(sc->bge_dmatag, 756 sc->bge_cdata.bge_rx_jumbo_map); 757 case 3: 758 bus_dmamap_destroy(sc->bge_dmatag, 759 sc->bge_cdata.bge_rx_jumbo_map); 760 case 2: 761 bus_dmamem_unmap(sc->bge_dmatag, kva, BGE_JMEM); 762 case 1: 763 bus_dmamem_free(sc->bge_dmatag, &seg, rseg); 764 break; 765 default: 766 break; 767 } 768 } 769 770 return error; 771 } 772 773 /* 774 * Allocate a jumbo buffer. 775 */ 776 static void * 777 bge_jalloc(struct bge_softc *sc) 778 { 779 struct bge_jpool_entry *entry; 780 781 entry = SLIST_FIRST(&sc->bge_jfree_listhead); 782 783 if (entry == NULL) { 784 printf("%s: no free jumbo buffers\n", sc->bge_dev.dv_xname); 785 return(NULL); 786 } 787 788 SLIST_REMOVE_HEAD(&sc->bge_jfree_listhead, jpool_entries); 789 SLIST_INSERT_HEAD(&sc->bge_jinuse_listhead, entry, jpool_entries); 790 return(sc->bge_cdata.bge_jslots[entry->slot]); 791 } 792 793 /* 794 * Release a jumbo buffer. 795 */ 796 static void 797 bge_jfree(struct mbuf *m, caddr_t buf, size_t size, void *arg) 798 { 799 struct bge_jpool_entry *entry; 800 struct bge_softc *sc; 801 int i, s; 802 803 /* Extract the softc struct pointer. */ 804 sc = (struct bge_softc *)arg; 805 806 if (sc == NULL) 807 panic("bge_jfree: can't find softc pointer!"); 808 809 /* calculate the slot this buffer belongs to */ 810 811 i = ((caddr_t)buf 812 - (caddr_t)sc->bge_cdata.bge_jumbo_buf) / BGE_JLEN; 813 814 if ((i < 0) || (i >= BGE_JSLOTS)) 815 panic("bge_jfree: asked to free buffer that we don't manage!"); 816 817 s = splvm(); 818 entry = SLIST_FIRST(&sc->bge_jinuse_listhead); 819 if (entry == NULL) 820 panic("bge_jfree: buffer not in use!"); 821 entry->slot = i; 822 SLIST_REMOVE_HEAD(&sc->bge_jinuse_listhead, jpool_entries); 823 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, entry, jpool_entries); 824 825 if (__predict_true(m != NULL)) 826 pool_cache_put(&mbpool_cache, m); 827 splx(s); 828 } 829 830 831 /* 832 * Intialize a standard receive ring descriptor. 833 */ 834 static int 835 bge_newbuf_std(struct bge_softc *sc, int i, struct mbuf *m, bus_dmamap_t dmamap) 836 { 837 struct mbuf *m_new = NULL; 838 struct bge_rx_bd *r; 839 int error; 840 841 if (dmamap == NULL) { 842 error = bus_dmamap_create(sc->bge_dmatag, MCLBYTES, 1, 843 MCLBYTES, 0, BUS_DMA_NOWAIT, &dmamap); 844 if (error != 0) 845 return error; 846 } 847 848 sc->bge_cdata.bge_rx_std_map[i] = dmamap; 849 850 if (m == NULL) { 851 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 852 if (m_new == NULL) { 853 return(ENOBUFS); 854 } 855 856 MCLGET(m_new, M_DONTWAIT); 857 if (!(m_new->m_flags & M_EXT)) { 858 m_freem(m_new); 859 return(ENOBUFS); 860 } 861 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 862 if (!sc->bge_rx_alignment_bug) 863 m_adj(m_new, ETHER_ALIGN); 864 865 if (bus_dmamap_load_mbuf(sc->bge_dmatag, dmamap, m_new, 866 BUS_DMA_READ|BUS_DMA_NOWAIT)) 867 return(ENOBUFS); 868 } else { 869 m_new = m; 870 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 871 m_new->m_data = m_new->m_ext.ext_buf; 872 if (!sc->bge_rx_alignment_bug) 873 m_adj(m_new, ETHER_ALIGN); 874 } 875 876 sc->bge_cdata.bge_rx_std_chain[i] = m_new; 877 r = &sc->bge_rdata->bge_rx_std_ring[i]; 878 bge_set_hostaddr(&r->bge_addr, 879 dmamap->dm_segs[0].ds_addr); 880 r->bge_flags = BGE_RXBDFLAG_END; 881 r->bge_len = m_new->m_len; 882 r->bge_idx = i; 883 884 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 885 offsetof(struct bge_ring_data, bge_rx_std_ring) + 886 i * sizeof (struct bge_rx_bd), 887 sizeof (struct bge_rx_bd), 888 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 889 890 return(0); 891 } 892 893 /* 894 * Initialize a jumbo receive ring descriptor. This allocates 895 * a jumbo buffer from the pool managed internally by the driver. 896 */ 897 static int 898 bge_newbuf_jumbo(struct bge_softc *sc, int i, struct mbuf *m) 899 { 900 struct mbuf *m_new = NULL; 901 struct bge_rx_bd *r; 902 903 if (m == NULL) { 904 caddr_t buf = NULL; 905 906 /* Allocate the mbuf. */ 907 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 908 if (m_new == NULL) { 909 return(ENOBUFS); 910 } 911 912 /* Allocate the jumbo buffer */ 913 buf = bge_jalloc(sc); 914 if (buf == NULL) { 915 m_freem(m_new); 916 printf("%s: jumbo allocation failed " 917 "-- packet dropped!\n", sc->bge_dev.dv_xname); 918 return(ENOBUFS); 919 } 920 921 /* Attach the buffer to the mbuf. */ 922 m_new->m_len = m_new->m_pkthdr.len = BGE_JUMBO_FRAMELEN; 923 MEXTADD(m_new, buf, BGE_JUMBO_FRAMELEN, M_DEVBUF, 924 bge_jfree, sc); 925 m_new->m_flags |= M_EXT_RW; 926 } else { 927 m_new = m; 928 m_new->m_data = m_new->m_ext.ext_buf; 929 m_new->m_ext.ext_size = BGE_JUMBO_FRAMELEN; 930 } 931 932 if (!sc->bge_rx_alignment_bug) 933 m_adj(m_new, ETHER_ALIGN); 934 /* Set up the descriptor. */ 935 r = &sc->bge_rdata->bge_rx_jumbo_ring[i]; 936 sc->bge_cdata.bge_rx_jumbo_chain[i] = m_new; 937 bge_set_hostaddr(&r->bge_addr, BGE_JUMBO_DMA_ADDR(sc, m_new)); 938 r->bge_flags = BGE_RXBDFLAG_END|BGE_RXBDFLAG_JUMBO_RING; 939 r->bge_len = m_new->m_len; 940 r->bge_idx = i; 941 942 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 943 offsetof(struct bge_ring_data, bge_rx_jumbo_ring) + 944 i * sizeof (struct bge_rx_bd), 945 sizeof (struct bge_rx_bd), 946 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 947 948 return(0); 949 } 950 951 /* 952 * The standard receive ring has 512 entries in it. At 2K per mbuf cluster, 953 * that's 1MB or memory, which is a lot. For now, we fill only the first 954 * 256 ring entries and hope that our CPU is fast enough to keep up with 955 * the NIC. 956 */ 957 static int 958 bge_init_rx_ring_std(struct bge_softc *sc) 959 { 960 int i; 961 962 if (sc->bge_flags & BGE_RXRING_VALID) 963 return 0; 964 965 for (i = 0; i < BGE_SSLOTS; i++) { 966 if (bge_newbuf_std(sc, i, NULL, 0) == ENOBUFS) 967 return(ENOBUFS); 968 } 969 970 sc->bge_std = i - 1; 971 CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std); 972 973 sc->bge_flags |= BGE_RXRING_VALID; 974 975 return(0); 976 } 977 978 static void 979 bge_free_rx_ring_std(struct bge_softc *sc) 980 { 981 int i; 982 983 if (!(sc->bge_flags & BGE_RXRING_VALID)) 984 return; 985 986 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { 987 if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) { 988 m_freem(sc->bge_cdata.bge_rx_std_chain[i]); 989 sc->bge_cdata.bge_rx_std_chain[i] = NULL; 990 bus_dmamap_destroy(sc->bge_dmatag, 991 sc->bge_cdata.bge_rx_std_map[i]); 992 } 993 memset((char *)&sc->bge_rdata->bge_rx_std_ring[i], 0, 994 sizeof(struct bge_rx_bd)); 995 } 996 997 sc->bge_flags &= ~BGE_RXRING_VALID; 998 } 999 1000 static int 1001 bge_init_rx_ring_jumbo(struct bge_softc *sc) 1002 { 1003 int i; 1004 volatile struct bge_rcb *rcb; 1005 1006 if (sc->bge_flags & BGE_JUMBO_RXRING_VALID) 1007 return 0; 1008 1009 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 1010 if (bge_newbuf_jumbo(sc, i, NULL) == ENOBUFS) 1011 return(ENOBUFS); 1012 }; 1013 1014 sc->bge_jumbo = i - 1; 1015 sc->bge_flags |= BGE_JUMBO_RXRING_VALID; 1016 1017 rcb = &sc->bge_rdata->bge_info.bge_jumbo_rx_rcb; 1018 rcb->bge_maxlen_flags = 0; 1019 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 1020 1021 CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo); 1022 1023 return(0); 1024 } 1025 1026 static void 1027 bge_free_rx_ring_jumbo(struct bge_softc *sc) 1028 { 1029 int i; 1030 1031 if (!(sc->bge_flags & BGE_JUMBO_RXRING_VALID)) 1032 return; 1033 1034 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 1035 if (sc->bge_cdata.bge_rx_jumbo_chain[i] != NULL) { 1036 m_freem(sc->bge_cdata.bge_rx_jumbo_chain[i]); 1037 sc->bge_cdata.bge_rx_jumbo_chain[i] = NULL; 1038 } 1039 memset((char *)&sc->bge_rdata->bge_rx_jumbo_ring[i], 0, 1040 sizeof(struct bge_rx_bd)); 1041 } 1042 1043 sc->bge_flags &= ~BGE_JUMBO_RXRING_VALID; 1044 } 1045 1046 static void 1047 bge_free_tx_ring(struct bge_softc *sc) 1048 { 1049 int i, freed; 1050 struct txdmamap_pool_entry *dma; 1051 1052 if (!(sc->bge_flags & BGE_TXRING_VALID)) 1053 return; 1054 1055 freed = 0; 1056 1057 for (i = 0; i < BGE_TX_RING_CNT; i++) { 1058 if (sc->bge_cdata.bge_tx_chain[i] != NULL) { 1059 freed++; 1060 m_freem(sc->bge_cdata.bge_tx_chain[i]); 1061 sc->bge_cdata.bge_tx_chain[i] = NULL; 1062 SLIST_INSERT_HEAD(&sc->txdma_list, sc->txdma[i], 1063 link); 1064 sc->txdma[i] = 0; 1065 } 1066 memset((char *)&sc->bge_rdata->bge_tx_ring[i], 0, 1067 sizeof(struct bge_tx_bd)); 1068 } 1069 1070 while ((dma = SLIST_FIRST(&sc->txdma_list))) { 1071 SLIST_REMOVE_HEAD(&sc->txdma_list, link); 1072 bus_dmamap_destroy(sc->bge_dmatag, dma->dmamap); 1073 free(dma, M_DEVBUF); 1074 } 1075 1076 sc->bge_flags &= ~BGE_TXRING_VALID; 1077 } 1078 1079 static int 1080 bge_init_tx_ring(struct bge_softc *sc) 1081 { 1082 int i; 1083 bus_dmamap_t dmamap; 1084 struct txdmamap_pool_entry *dma; 1085 1086 if (sc->bge_flags & BGE_TXRING_VALID) 1087 return 0; 1088 1089 sc->bge_txcnt = 0; 1090 sc->bge_tx_saved_considx = 0; 1091 1092 /* Initialize transmit producer index for host-memory send ring. */ 1093 sc->bge_tx_prodidx = 0; 1094 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx); 1095 if (sc->bge_quirks & BGE_QUIRK_PRODUCER_BUG) /* 5700 b2 errata */ 1096 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx); 1097 1098 /* NIC-memory send ring not used; initialize to zero. */ 1099 CSR_WRITE_4(sc, BGE_MBX_TX_NIC_PROD0_LO, 0); 1100 if (sc->bge_quirks & BGE_QUIRK_PRODUCER_BUG) /* 5700 b2 errata */ 1101 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, 0); 1102 1103 SLIST_INIT(&sc->txdma_list); 1104 for (i = 0; i < BGE_RSLOTS; i++) { 1105 if (bus_dmamap_create(sc->bge_dmatag, BGE_TXDMA_MAX, 1106 BGE_NTXSEG, ETHER_MAX_LEN_JUMBO, 0, BUS_DMA_NOWAIT, 1107 &dmamap)) 1108 return(ENOBUFS); 1109 if (dmamap == NULL) 1110 panic("dmamap NULL in bge_init_tx_ring"); 1111 dma = malloc(sizeof(*dma), M_DEVBUF, M_NOWAIT); 1112 if (dma == NULL) { 1113 printf("%s: can't alloc txdmamap_pool_entry\n", 1114 sc->bge_dev.dv_xname); 1115 bus_dmamap_destroy(sc->bge_dmatag, dmamap); 1116 return (ENOMEM); 1117 } 1118 dma->dmamap = dmamap; 1119 SLIST_INSERT_HEAD(&sc->txdma_list, dma, link); 1120 } 1121 1122 sc->bge_flags |= BGE_TXRING_VALID; 1123 1124 return(0); 1125 } 1126 1127 static void 1128 bge_setmulti(struct bge_softc *sc) 1129 { 1130 struct ethercom *ac = &sc->ethercom; 1131 struct ifnet *ifp = &ac->ec_if; 1132 struct ether_multi *enm; 1133 struct ether_multistep step; 1134 u_int32_t hashes[4] = { 0, 0, 0, 0 }; 1135 u_int32_t h; 1136 int i; 1137 1138 if (ifp->if_flags & IFF_PROMISC) 1139 goto allmulti; 1140 1141 /* Now program new ones. */ 1142 ETHER_FIRST_MULTI(step, ac, enm); 1143 while (enm != NULL) { 1144 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1145 /* 1146 * We must listen to a range of multicast addresses. 1147 * For now, just accept all multicasts, rather than 1148 * trying to set only those filter bits needed to match 1149 * the range. (At this time, the only use of address 1150 * ranges is for IP multicast routing, for which the 1151 * range is big enough to require all bits set.) 1152 */ 1153 goto allmulti; 1154 } 1155 1156 h = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN); 1157 1158 /* Just want the 7 least-significant bits. */ 1159 h &= 0x7f; 1160 1161 hashes[(h & 0x60) >> 5] |= 1 << (h & 0x1F); 1162 ETHER_NEXT_MULTI(step, enm); 1163 } 1164 1165 ifp->if_flags &= ~IFF_ALLMULTI; 1166 goto setit; 1167 1168 allmulti: 1169 ifp->if_flags |= IFF_ALLMULTI; 1170 hashes[0] = hashes[1] = hashes[2] = hashes[3] = 0xffffffff; 1171 1172 setit: 1173 for (i = 0; i < 4; i++) 1174 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]); 1175 } 1176 1177 const int bge_swapbits[] = { 1178 0, 1179 BGE_MODECTL_BYTESWAP_DATA, 1180 BGE_MODECTL_WORDSWAP_DATA, 1181 BGE_MODECTL_BYTESWAP_NONFRAME, 1182 BGE_MODECTL_WORDSWAP_NONFRAME, 1183 1184 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA, 1185 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_BYTESWAP_NONFRAME, 1186 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_NONFRAME, 1187 1188 BGE_MODECTL_WORDSWAP_DATA|BGE_MODECTL_BYTESWAP_NONFRAME, 1189 BGE_MODECTL_WORDSWAP_DATA|BGE_MODECTL_WORDSWAP_NONFRAME, 1190 1191 BGE_MODECTL_BYTESWAP_NONFRAME|BGE_MODECTL_WORDSWAP_NONFRAME, 1192 1193 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA| 1194 BGE_MODECTL_BYTESWAP_NONFRAME, 1195 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA| 1196 BGE_MODECTL_WORDSWAP_NONFRAME, 1197 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_BYTESWAP_NONFRAME| 1198 BGE_MODECTL_WORDSWAP_NONFRAME, 1199 BGE_MODECTL_WORDSWAP_DATA|BGE_MODECTL_BYTESWAP_NONFRAME| 1200 BGE_MODECTL_WORDSWAP_NONFRAME, 1201 1202 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA| 1203 BGE_MODECTL_BYTESWAP_NONFRAME|BGE_MODECTL_WORDSWAP_NONFRAME, 1204 }; 1205 1206 int bge_swapindex = 0; 1207 1208 /* 1209 * Do endian, PCI and DMA initialization. Also check the on-board ROM 1210 * self-test results. 1211 */ 1212 static int 1213 bge_chipinit(struct bge_softc *sc) 1214 { 1215 u_int32_t cachesize; 1216 int i; 1217 u_int32_t dma_rw_ctl; 1218 struct pci_attach_args *pa = &(sc->bge_pa); 1219 1220 1221 /* Set endianness before we access any non-PCI registers. */ 1222 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_MISC_CTL, 1223 BGE_INIT); 1224 1225 /* Set power state to D0. */ 1226 bge_setpowerstate(sc, 0); 1227 1228 /* 1229 * Check the 'ROM failed' bit on the RX CPU to see if 1230 * self-tests passed. 1231 */ 1232 if (CSR_READ_4(sc, BGE_RXCPU_MODE) & BGE_RXCPUMODE_ROMFAIL) { 1233 printf("%s: RX CPU self-diagnostics failed!\n", 1234 sc->bge_dev.dv_xname); 1235 return(ENODEV); 1236 } 1237 1238 /* Clear the MAC control register */ 1239 CSR_WRITE_4(sc, BGE_MAC_MODE, 0); 1240 1241 /* 1242 * Clear the MAC statistics block in the NIC's 1243 * internal memory. 1244 */ 1245 for (i = BGE_STATS_BLOCK; 1246 i < BGE_STATS_BLOCK_END + 1; i += sizeof(u_int32_t)) 1247 BGE_MEMWIN_WRITE(pa->pa_pc, pa->pa_tag, i, 0); 1248 1249 for (i = BGE_STATUS_BLOCK; 1250 i < BGE_STATUS_BLOCK_END + 1; i += sizeof(u_int32_t)) 1251 BGE_MEMWIN_WRITE(pa->pa_pc, pa->pa_tag, i, 0); 1252 1253 /* Set up the PCI DMA control register. */ 1254 if (sc->bge_pcie) { 1255 u_int32_t device_ctl; 1256 1257 /* From FreeBSD */ 1258 DPRINTFN(4, ("(%s: PCI-Express DMA setting)\n", 1259 sc->bge_dev.dv_xname)); 1260 dma_rw_ctl = (BGE_PCI_READ_CMD | BGE_PCI_WRITE_CMD | 1261 (0xf << BGE_PCIDMARWCTL_RD_WAT_SHIFT) | 1262 (0x2 << BGE_PCIDMARWCTL_WR_WAT_SHIFT)); 1263 1264 /* jonathan: alternative from Linux driver */ 1265 #define DMA_CTRL_WRITE_PCIE_H20MARK_128 0x00180000 1266 #define DMA_CTRL_WRITE_PCIE_H20MARK_256 0x00380000 1267 1268 dma_rw_ctl = 0x76000000; /* XXX XXX XXX */; 1269 device_ctl = pci_conf_read(pa->pa_pc, pa->pa_tag, 1270 BGE_PCI_CONF_DEV_CTRL); 1271 printf("%s: pcie mode=0x%x\n", sc->bge_dev.dv_xname, device_ctl); 1272 1273 if ((device_ctl & 0x00e0) && 0) { 1274 /* 1275 * XXX jonathan (at) NetBSD.org: 1276 * This clause is exactly what the Broadcom-supplied 1277 * Linux does; but given overall register programming 1278 * by if_bge(4), this larger DMA-write watermark 1279 * value causes bcm5721 chips to totally wedge. 1280 */ 1281 dma_rw_ctl |= BGE_PCIDMA_RWCTL_PCIE_WRITE_WATRMARK_256; 1282 } else { 1283 dma_rw_ctl |= BGE_PCIDMA_RWCTL_PCIE_WRITE_WATRMARK_128; 1284 } 1285 } else if (pci_conf_read(pa->pa_pc, pa->pa_tag,BGE_PCI_PCISTATE) & 1286 BGE_PCISTATE_PCI_BUSMODE) { 1287 /* Conventional PCI bus */ 1288 DPRINTFN(4, ("(%s: PCI 2.2 DMA setting)\n", sc->bge_dev.dv_xname)); 1289 dma_rw_ctl = (BGE_PCI_READ_CMD | BGE_PCI_WRITE_CMD | 1290 (0x7 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) | 1291 (0x7 << BGE_PCIDMARWCTL_WR_WAT_SHIFT)); 1292 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 1293 dma_rw_ctl |= 0x0F; 1294 } 1295 } else { 1296 DPRINTFN(4, ("(:%s: PCI-X DMA setting)\n", sc->bge_dev.dv_xname)); 1297 /* PCI-X bus */ 1298 dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD | 1299 (0x3 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) | 1300 (0x3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT) | 1301 (0x0F); 1302 /* 1303 * 5703 and 5704 need ONEDMA_AT_ONCE as a workaround 1304 * for hardware bugs, which means we should also clear 1305 * the low-order MINDMA bits. In addition, the 5704 1306 * uses a different encoding of read/write watermarks. 1307 */ 1308 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) { 1309 dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD | 1310 /* should be 0x1f0000 */ 1311 (0x7 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) | 1312 (0x3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT); 1313 dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE; 1314 } 1315 else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5703) { 1316 dma_rw_ctl &= 0xfffffff0; 1317 dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE; 1318 } 1319 else if (BGE_IS_5714_FAMILY(sc)) { 1320 dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD; 1321 dma_rw_ctl &= ~BGE_PCIDMARWCTL_ONEDMA_ATONCE; /* XXX */ 1322 /* XXX magic values, Broadcom-supplied Linux driver */ 1323 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5780) 1324 dma_rw_ctl |= (1 << 20) | (1 << 18) | 1325 BGE_PCIDMARWCTL_ONEDMA_ATONCE; 1326 else 1327 dma_rw_ctl |= (1<<20) | (1<<18) | (1 << 15); 1328 } 1329 } 1330 1331 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_DMA_RW_CTL, dma_rw_ctl); 1332 1333 /* 1334 * Set up general mode register. 1335 */ 1336 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS| 1337 BGE_MODECTL_MAC_ATTN_INTR|BGE_MODECTL_HOST_SEND_BDS| 1338 BGE_MODECTL_TX_NO_PHDR_CSUM|BGE_MODECTL_RX_NO_PHDR_CSUM); 1339 1340 /* Get cache line size. */ 1341 cachesize = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_CACHESZ); 1342 1343 /* 1344 * Avoid violating PCI spec on certain chip revs. 1345 */ 1346 if (pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_CMD) & 1347 PCIM_CMD_MWIEN) { 1348 switch(cachesize) { 1349 case 1: 1350 PCI_SETBIT(pa->pa_pc, pa->pa_tag, BGE_PCI_DMA_RW_CTL, 1351 BGE_PCI_WRITE_BNDRY_16BYTES); 1352 break; 1353 case 2: 1354 PCI_SETBIT(pa->pa_pc, pa->pa_tag, BGE_PCI_DMA_RW_CTL, 1355 BGE_PCI_WRITE_BNDRY_32BYTES); 1356 break; 1357 case 4: 1358 PCI_SETBIT(pa->pa_pc, pa->pa_tag, BGE_PCI_DMA_RW_CTL, 1359 BGE_PCI_WRITE_BNDRY_64BYTES); 1360 break; 1361 case 8: 1362 PCI_SETBIT(pa->pa_pc, pa->pa_tag, BGE_PCI_DMA_RW_CTL, 1363 BGE_PCI_WRITE_BNDRY_128BYTES); 1364 break; 1365 case 16: 1366 PCI_SETBIT(pa->pa_pc, pa->pa_tag, BGE_PCI_DMA_RW_CTL, 1367 BGE_PCI_WRITE_BNDRY_256BYTES); 1368 break; 1369 case 32: 1370 PCI_SETBIT(pa->pa_pc, pa->pa_tag, BGE_PCI_DMA_RW_CTL, 1371 BGE_PCI_WRITE_BNDRY_512BYTES); 1372 break; 1373 case 64: 1374 PCI_SETBIT(pa->pa_pc, pa->pa_tag, BGE_PCI_DMA_RW_CTL, 1375 BGE_PCI_WRITE_BNDRY_1024BYTES); 1376 break; 1377 default: 1378 /* Disable PCI memory write and invalidate. */ 1379 #if 0 1380 if (bootverbose) 1381 printf("%s: cache line size %d not " 1382 "supported; disabling PCI MWI\n", 1383 sc->bge_dev.dv_xname, cachesize); 1384 #endif 1385 PCI_CLRBIT(pa->pa_pc, pa->pa_tag, BGE_PCI_CMD, 1386 PCIM_CMD_MWIEN); 1387 break; 1388 } 1389 } 1390 1391 /* 1392 * Disable memory write invalidate. Apparently it is not supported 1393 * properly by these devices. 1394 */ 1395 PCI_CLRBIT(pa->pa_pc, pa->pa_tag, BGE_PCI_CMD, PCIM_CMD_MWIEN); 1396 1397 1398 #ifdef __brokenalpha__ 1399 /* 1400 * Must insure that we do not cross an 8K (bytes) boundary 1401 * for DMA reads. Our highest limit is 1K bytes. This is a 1402 * restriction on some ALPHA platforms with early revision 1403 * 21174 PCI chipsets, such as the AlphaPC 164lx 1404 */ 1405 PCI_SETBIT(sc, BGE_PCI_DMA_RW_CTL, BGE_PCI_READ_BNDRY_1024, 4); 1406 #endif 1407 1408 /* Set the timer prescaler (always 66MHz) */ 1409 CSR_WRITE_4(sc, BGE_MISC_CFG, 65 << 1/*BGE_32BITTIME_66MHZ*/); 1410 1411 return(0); 1412 } 1413 1414 static int 1415 bge_blockinit(struct bge_softc *sc) 1416 { 1417 volatile struct bge_rcb *rcb; 1418 bus_size_t rcb_addr; 1419 int i; 1420 struct ifnet *ifp = &sc->ethercom.ec_if; 1421 bge_hostaddr taddr; 1422 1423 /* 1424 * Initialize the memory window pointer register so that 1425 * we can access the first 32K of internal NIC RAM. This will 1426 * allow us to set up the TX send ring RCBs and the RX return 1427 * ring RCBs, plus other things which live in NIC memory. 1428 */ 1429 1430 pci_conf_write(sc->bge_pa.pa_pc, sc->bge_pa.pa_tag, 1431 BGE_PCI_MEMWIN_BASEADDR, 0); 1432 1433 /* Configure mbuf memory pool */ 1434 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 1435 if (sc->bge_extram) { 1436 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, 1437 BGE_EXT_SSRAM); 1438 if ((sc->bge_quirks & BGE_QUIRK_FEWER_MBUFS) != 0) 1439 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000); 1440 else 1441 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000); 1442 } else { 1443 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, 1444 BGE_BUFFPOOL_1); 1445 if ((sc->bge_quirks & BGE_QUIRK_FEWER_MBUFS) != 0) 1446 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000); 1447 else 1448 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000); 1449 } 1450 1451 /* Configure DMA resource pool */ 1452 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_BASEADDR, 1453 BGE_DMA_DESCRIPTORS); 1454 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LEN, 0x2000); 1455 } 1456 1457 /* Configure mbuf pool watermarks */ 1458 #ifdef ORIG_WPAUL_VALUES 1459 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 24); 1460 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 24); 1461 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 48); 1462 #else 1463 /* new broadcom docs strongly recommend these: */ 1464 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 1465 if (ifp->if_mtu > ETHER_MAX_LEN) { 1466 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x50); 1467 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x20); 1468 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60); 1469 } else { 1470 /* Values from Linux driver... */ 1471 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 304); 1472 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 152); 1473 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 380); 1474 } 1475 } else { 1476 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0); 1477 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x10); 1478 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60); 1479 } 1480 #endif 1481 1482 /* Configure DMA resource watermarks */ 1483 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5); 1484 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10); 1485 1486 /* Enable buffer manager */ 1487 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 1488 CSR_WRITE_4(sc, BGE_BMAN_MODE, 1489 BGE_BMANMODE_ENABLE|BGE_BMANMODE_LOMBUF_ATTN); 1490 1491 /* Poll for buffer manager start indication */ 1492 for (i = 0; i < BGE_TIMEOUT; i++) { 1493 if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE) 1494 break; 1495 DELAY(10); 1496 } 1497 1498 if (i == BGE_TIMEOUT) { 1499 printf("%s: buffer manager failed to start\n", 1500 sc->bge_dev.dv_xname); 1501 return(ENXIO); 1502 } 1503 } 1504 1505 /* Enable flow-through queues */ 1506 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 1507 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 1508 1509 /* Wait until queue initialization is complete */ 1510 for (i = 0; i < BGE_TIMEOUT; i++) { 1511 if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0) 1512 break; 1513 DELAY(10); 1514 } 1515 1516 if (i == BGE_TIMEOUT) { 1517 printf("%s: flow-through queue init failed\n", 1518 sc->bge_dev.dv_xname); 1519 return(ENXIO); 1520 } 1521 1522 /* Initialize the standard RX ring control block */ 1523 rcb = &sc->bge_rdata->bge_info.bge_std_rx_rcb; 1524 bge_set_hostaddr(&rcb->bge_hostaddr, 1525 BGE_RING_DMA_ADDR(sc, bge_rx_std_ring)); 1526 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 1527 rcb->bge_maxlen_flags = 1528 BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 0); 1529 } else { 1530 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(512, 0); 1531 } 1532 if (sc->bge_extram) 1533 rcb->bge_nicaddr = BGE_EXT_STD_RX_RINGS; 1534 else 1535 rcb->bge_nicaddr = BGE_STD_RX_RINGS; 1536 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcb->bge_hostaddr.bge_addr_hi); 1537 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcb->bge_hostaddr.bge_addr_lo); 1538 CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 1539 CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcb->bge_nicaddr); 1540 1541 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 1542 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT; 1543 } else { 1544 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT_5705; 1545 } 1546 1547 /* 1548 * Initialize the jumbo RX ring control block 1549 * We set the 'ring disabled' bit in the flags 1550 * field until we're actually ready to start 1551 * using this ring (i.e. once we set the MTU 1552 * high enough to require it). 1553 */ 1554 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 1555 rcb = &sc->bge_rdata->bge_info.bge_jumbo_rx_rcb; 1556 bge_set_hostaddr(&rcb->bge_hostaddr, 1557 BGE_RING_DMA_ADDR(sc, bge_rx_jumbo_ring)); 1558 rcb->bge_maxlen_flags = 1559 BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 1560 BGE_RCB_FLAG_RING_DISABLED); 1561 if (sc->bge_extram) 1562 rcb->bge_nicaddr = BGE_EXT_JUMBO_RX_RINGS; 1563 else 1564 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS; 1565 1566 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI, 1567 rcb->bge_hostaddr.bge_addr_hi); 1568 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO, 1569 rcb->bge_hostaddr.bge_addr_lo); 1570 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, 1571 rcb->bge_maxlen_flags); 1572 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcb->bge_nicaddr); 1573 1574 /* Set up dummy disabled mini ring RCB */ 1575 rcb = &sc->bge_rdata->bge_info.bge_mini_rx_rcb; 1576 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0, 1577 BGE_RCB_FLAG_RING_DISABLED); 1578 CSR_WRITE_4(sc, BGE_RX_MINI_RCB_MAXLEN_FLAGS, 1579 rcb->bge_maxlen_flags); 1580 1581 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 1582 offsetof(struct bge_ring_data, bge_info), 1583 sizeof (struct bge_gib), 1584 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1585 } 1586 1587 /* 1588 * Set the BD ring replentish thresholds. The recommended 1589 * values are 1/8th the number of descriptors allocated to 1590 * each ring. 1591 */ 1592 CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, BGE_STD_RX_RING_CNT/8); 1593 CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH, BGE_JUMBO_RX_RING_CNT/8); 1594 1595 /* 1596 * Disable all unused send rings by setting the 'ring disabled' 1597 * bit in the flags field of all the TX send ring control blocks. 1598 * These are located in NIC memory. 1599 */ 1600 rcb_addr = BGE_MEMWIN_START + BGE_SEND_RING_RCB; 1601 for (i = 0; i < BGE_TX_RINGS_EXTSSRAM_MAX; i++) { 1602 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 1603 BGE_RCB_MAXLEN_FLAGS(0,BGE_RCB_FLAG_RING_DISABLED)); 1604 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 0); 1605 rcb_addr += sizeof(struct bge_rcb); 1606 } 1607 1608 /* Configure TX RCB 0 (we use only the first ring) */ 1609 rcb_addr = BGE_MEMWIN_START + BGE_SEND_RING_RCB; 1610 bge_set_hostaddr(&taddr, BGE_RING_DMA_ADDR(sc, bge_tx_ring)); 1611 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi); 1612 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo); 1613 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 1614 BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT)); 1615 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 1616 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 1617 BGE_RCB_MAXLEN_FLAGS(BGE_TX_RING_CNT, 0)); 1618 } 1619 1620 /* Disable all unused RX return rings */ 1621 rcb_addr = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB; 1622 for (i = 0; i < BGE_RX_RINGS_MAX; i++) { 1623 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_hi, 0); 1624 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_lo, 0); 1625 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 1626 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 1627 BGE_RCB_FLAG_RING_DISABLED)); 1628 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 0); 1629 CSR_WRITE_4(sc, BGE_MBX_RX_CONS0_LO + 1630 (i * (sizeof(u_int64_t))), 0); 1631 rcb_addr += sizeof(struct bge_rcb); 1632 } 1633 1634 /* Initialize RX ring indexes */ 1635 CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, 0); 1636 CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0); 1637 CSR_WRITE_4(sc, BGE_MBX_RX_MINI_PROD_LO, 0); 1638 1639 /* 1640 * Set up RX return ring 0 1641 * Note that the NIC address for RX return rings is 0x00000000. 1642 * The return rings live entirely within the host, so the 1643 * nicaddr field in the RCB isn't used. 1644 */ 1645 rcb_addr = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB; 1646 bge_set_hostaddr(&taddr, BGE_RING_DMA_ADDR(sc, bge_rx_return_ring)); 1647 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi); 1648 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo); 1649 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 0x00000000); 1650 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 1651 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 0)); 1652 1653 /* Set random backoff seed for TX */ 1654 CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF, 1655 LLADDR(ifp->if_sadl)[0] + LLADDR(ifp->if_sadl)[1] + 1656 LLADDR(ifp->if_sadl)[2] + LLADDR(ifp->if_sadl)[3] + 1657 LLADDR(ifp->if_sadl)[4] + LLADDR(ifp->if_sadl)[5] + 1658 BGE_TX_BACKOFF_SEED_MASK); 1659 1660 /* Set inter-packet gap */ 1661 CSR_WRITE_4(sc, BGE_TX_LENGTHS, 0x2620); 1662 1663 /* 1664 * Specify which ring to use for packets that don't match 1665 * any RX rules. 1666 */ 1667 CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08); 1668 1669 /* 1670 * Configure number of RX lists. One interrupt distribution 1671 * list, sixteen active lists, one bad frames class. 1672 */ 1673 CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181); 1674 1675 /* Inialize RX list placement stats mask. */ 1676 CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF); 1677 CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1); 1678 1679 /* Disable host coalescing until we get it set up */ 1680 CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000); 1681 1682 /* Poll to make sure it's shut down. */ 1683 for (i = 0; i < BGE_TIMEOUT; i++) { 1684 if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE)) 1685 break; 1686 DELAY(10); 1687 } 1688 1689 if (i == BGE_TIMEOUT) { 1690 printf("%s: host coalescing engine failed to idle\n", 1691 sc->bge_dev.dv_xname); 1692 return(ENXIO); 1693 } 1694 1695 /* Set up host coalescing defaults */ 1696 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bge_rx_coal_ticks); 1697 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bge_tx_coal_ticks); 1698 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bge_rx_max_coal_bds); 1699 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bge_tx_max_coal_bds); 1700 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 1701 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT, 0); 1702 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT, 0); 1703 } 1704 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 0); 1705 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 0); 1706 1707 /* Set up address of statistics block */ 1708 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 1709 bge_set_hostaddr(&taddr, 1710 BGE_RING_DMA_ADDR(sc, bge_info.bge_stats)); 1711 CSR_WRITE_4(sc, BGE_HCC_STATS_TICKS, sc->bge_stat_ticks); 1712 CSR_WRITE_4(sc, BGE_HCC_STATS_BASEADDR, BGE_STATS_BLOCK); 1713 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_HI, taddr.bge_addr_hi); 1714 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_LO, taddr.bge_addr_lo); 1715 } 1716 1717 /* Set up address of status block */ 1718 bge_set_hostaddr(&taddr, BGE_RING_DMA_ADDR(sc, bge_status_block)); 1719 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_BASEADDR, BGE_STATUS_BLOCK); 1720 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI, taddr.bge_addr_hi); 1721 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO, taddr.bge_addr_lo); 1722 sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx = 0; 1723 sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx = 0; 1724 1725 /* Turn on host coalescing state machine */ 1726 CSR_WRITE_4(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE); 1727 1728 /* Turn on RX BD completion state machine and enable attentions */ 1729 CSR_WRITE_4(sc, BGE_RBDC_MODE, 1730 BGE_RBDCMODE_ENABLE|BGE_RBDCMODE_ATTN); 1731 1732 /* Turn on RX list placement state machine */ 1733 CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 1734 1735 /* Turn on RX list selector state machine. */ 1736 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 1737 CSR_WRITE_4(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 1738 } 1739 1740 /* Turn on DMA, clear stats */ 1741 CSR_WRITE_4(sc, BGE_MAC_MODE, BGE_MACMODE_TXDMA_ENB| 1742 BGE_MACMODE_RXDMA_ENB|BGE_MACMODE_RX_STATS_CLEAR| 1743 BGE_MACMODE_TX_STATS_CLEAR|BGE_MACMODE_RX_STATS_ENB| 1744 BGE_MACMODE_TX_STATS_ENB|BGE_MACMODE_FRMHDR_DMA_ENB| 1745 (sc->bge_tbi ? BGE_PORTMODE_TBI : BGE_PORTMODE_MII)); 1746 1747 /* Set misc. local control, enable interrupts on attentions */ 1748 sc->bge_local_ctrl_reg = BGE_MLC_INTR_ONATTN | BGE_MLC_AUTO_EEPROM; 1749 1750 #ifdef notdef 1751 /* Assert GPIO pins for PHY reset */ 1752 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUT0| 1753 BGE_MLC_MISCIO_OUT1|BGE_MLC_MISCIO_OUT2); 1754 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUTEN0| 1755 BGE_MLC_MISCIO_OUTEN1|BGE_MLC_MISCIO_OUTEN2); 1756 #endif 1757 1758 #if defined(not_quite_yet) 1759 /* Linux driver enables enable gpio pin #1 on 5700s */ 1760 if (sc->bge_chipid == BGE_CHIPID_BCM5700) { 1761 sc->bge_local_ctrl_reg |= 1762 (BGE_MLC_MISCIO_OUT1|BGE_MLC_MISCIO_OUTEN1); 1763 } 1764 #endif 1765 CSR_WRITE_4(sc, BGE_MISC_LOCAL_CTL, sc->bge_local_ctrl_reg); 1766 1767 /* Turn on DMA completion state machine */ 1768 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 1769 CSR_WRITE_4(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 1770 } 1771 1772 /* Turn on write DMA state machine */ 1773 CSR_WRITE_4(sc, BGE_WDMA_MODE, 1774 BGE_WDMAMODE_ENABLE|BGE_WDMAMODE_ALL_ATTNS); 1775 1776 /* Turn on read DMA state machine */ 1777 { 1778 uint32_t dma_read_modebits; 1779 1780 dma_read_modebits = 1781 BGE_RDMAMODE_ENABLE | BGE_RDMAMODE_ALL_ATTNS; 1782 1783 if (sc->bge_pcie && 0) { 1784 dma_read_modebits |= BGE_RDMA_MODE_FIFO_LONG_BURST; 1785 } else if ((sc->bge_quirks & BGE_QUIRK_5705_CORE)) { 1786 dma_read_modebits |= BGE_RDMA_MODE_FIFO_SIZE_128; 1787 } 1788 1789 /* XXX broadcom-supplied linux driver; undocumented */ 1790 if (BGE_IS_5750_OR_BEYOND(sc)) { 1791 /* 1792 * XXX: magic values. 1793 * From Broadcom-supplied Linux driver; apparently 1794 * required to workaround a DMA bug affecting TSO 1795 * on bcm575x/bcm5721? 1796 */ 1797 dma_read_modebits |= (1 << 27); 1798 } 1799 CSR_WRITE_4(sc, BGE_RDMA_MODE, dma_read_modebits); 1800 } 1801 1802 /* Turn on RX data completion state machine */ 1803 CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 1804 1805 /* Turn on RX BD initiator state machine */ 1806 CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 1807 1808 /* Turn on RX data and RX BD initiator state machine */ 1809 CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE); 1810 1811 /* Turn on Mbuf cluster free state machine */ 1812 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 1813 CSR_WRITE_4(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 1814 } 1815 1816 /* Turn on send BD completion state machine */ 1817 CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 1818 1819 /* Turn on send data completion state machine */ 1820 CSR_WRITE_4(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE); 1821 1822 /* Turn on send data initiator state machine */ 1823 if (BGE_IS_5750_OR_BEYOND(sc)) { 1824 /* XXX: magic value from Linux driver */ 1825 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE | 0x08); 1826 } else { 1827 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 1828 } 1829 1830 /* Turn on send BD initiator state machine */ 1831 CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 1832 1833 /* Turn on send BD selector state machine */ 1834 CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 1835 1836 CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF); 1837 CSR_WRITE_4(sc, BGE_SDI_STATS_CTL, 1838 BGE_SDISTATSCTL_ENABLE|BGE_SDISTATSCTL_FASTER); 1839 1840 /* ack/clear link change events */ 1841 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED| 1842 BGE_MACSTAT_CFG_CHANGED); 1843 CSR_WRITE_4(sc, BGE_MI_STS, 0); 1844 1845 /* Enable PHY auto polling (for MII/GMII only) */ 1846 if (sc->bge_tbi) { 1847 CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK); 1848 } else { 1849 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL|10<<16); 1850 if (sc->bge_quirks & BGE_QUIRK_LINK_STATE_BROKEN) 1851 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, 1852 BGE_EVTENB_MI_INTERRUPT); 1853 } 1854 1855 /* Enable link state change attentions. */ 1856 BGE_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED); 1857 1858 return(0); 1859 } 1860 1861 static const struct bge_revision { 1862 uint32_t br_chipid; 1863 uint32_t br_quirks; 1864 const char *br_name; 1865 } bge_revisions[] = { 1866 { BGE_CHIPID_BCM5700_A0, 1867 BGE_QUIRK_LINK_STATE_BROKEN, 1868 "BCM5700 A0" }, 1869 1870 { BGE_CHIPID_BCM5700_A1, 1871 BGE_QUIRK_LINK_STATE_BROKEN, 1872 "BCM5700 A1" }, 1873 1874 { BGE_CHIPID_BCM5700_B0, 1875 BGE_QUIRK_LINK_STATE_BROKEN|BGE_QUIRK_CSUM_BROKEN|BGE_QUIRK_5700_COMMON, 1876 "BCM5700 B0" }, 1877 1878 { BGE_CHIPID_BCM5700_B1, 1879 BGE_QUIRK_LINK_STATE_BROKEN|BGE_QUIRK_5700_COMMON, 1880 "BCM5700 B1" }, 1881 1882 { BGE_CHIPID_BCM5700_B2, 1883 BGE_QUIRK_LINK_STATE_BROKEN|BGE_QUIRK_5700_COMMON, 1884 "BCM5700 B2" }, 1885 1886 /* This is treated like a BCM5700 Bx */ 1887 { BGE_CHIPID_BCM5700_ALTIMA, 1888 BGE_QUIRK_LINK_STATE_BROKEN|BGE_QUIRK_5700_COMMON, 1889 "BCM5700 Altima" }, 1890 1891 { BGE_CHIPID_BCM5700_C0, 1892 0, 1893 "BCM5700 C0" }, 1894 1895 { BGE_CHIPID_BCM5701_A0, 1896 0, /*XXX really, just not known */ 1897 "BCM5701 A0" }, 1898 1899 { BGE_CHIPID_BCM5701_B0, 1900 BGE_QUIRK_PCIX_DMA_ALIGN_BUG, 1901 "BCM5701 B0" }, 1902 1903 { BGE_CHIPID_BCM5701_B2, 1904 BGE_QUIRK_PCIX_DMA_ALIGN_BUG, 1905 "BCM5701 B2" }, 1906 1907 { BGE_CHIPID_BCM5701_B5, 1908 BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_PCIX_DMA_ALIGN_BUG, 1909 "BCM5701 B5" }, 1910 1911 { BGE_CHIPID_BCM5703_A0, 1912 0, 1913 "BCM5703 A0" }, 1914 1915 { BGE_CHIPID_BCM5703_A1, 1916 0, 1917 "BCM5703 A1" }, 1918 1919 { BGE_CHIPID_BCM5703_A2, 1920 BGE_QUIRK_ONLY_PHY_1, 1921 "BCM5703 A2" }, 1922 1923 { BGE_CHIPID_BCM5703_A3, 1924 BGE_QUIRK_ONLY_PHY_1, 1925 "BCM5703 A3" }, 1926 1927 { BGE_CHIPID_BCM5704_A0, 1928 BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_FEWER_MBUFS, 1929 "BCM5704 A0" }, 1930 1931 { BGE_CHIPID_BCM5704_A1, 1932 BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_FEWER_MBUFS, 1933 "BCM5704 A1" }, 1934 1935 { BGE_CHIPID_BCM5704_A2, 1936 BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_FEWER_MBUFS, 1937 "BCM5704 A2" }, 1938 1939 { BGE_CHIPID_BCM5704_A3, 1940 BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_FEWER_MBUFS, 1941 "BCM5704 A3" }, 1942 1943 { BGE_CHIPID_BCM5705_A0, 1944 BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_5705_CORE, 1945 "BCM5705 A0" }, 1946 1947 { BGE_CHIPID_BCM5705_A1, 1948 BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_5705_CORE, 1949 "BCM5705 A1" }, 1950 1951 { BGE_CHIPID_BCM5705_A2, 1952 BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_5705_CORE, 1953 "BCM5705 A2" }, 1954 1955 { BGE_CHIPID_BCM5705_A3, 1956 BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_5705_CORE, 1957 "BCM5705 A3" }, 1958 1959 { BGE_CHIPID_BCM5750_A0, 1960 BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_5705_CORE, 1961 "BCM5750 A1" }, 1962 1963 { BGE_CHIPID_BCM5750_A1, 1964 BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_5705_CORE, 1965 "BCM5750 A1" }, 1966 1967 { BGE_CHIPID_BCM5751_A1, 1968 BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_5705_CORE, 1969 "BCM5751 A1" }, 1970 1971 { 0, 0, NULL } 1972 }; 1973 1974 /* 1975 * Some defaults for major revisions, so that newer steppings 1976 * that we don't know about have a shot at working. 1977 */ 1978 static const struct bge_revision bge_majorrevs[] = { 1979 { BGE_ASICREV_BCM5700, 1980 BGE_QUIRK_LINK_STATE_BROKEN, 1981 "unknown BCM5700" }, 1982 1983 { BGE_ASICREV_BCM5701, 1984 BGE_QUIRK_PCIX_DMA_ALIGN_BUG, 1985 "unknown BCM5701" }, 1986 1987 { BGE_ASICREV_BCM5703, 1988 0, 1989 "unknown BCM5703" }, 1990 1991 { BGE_ASICREV_BCM5704, 1992 BGE_QUIRK_ONLY_PHY_1, 1993 "unknown BCM5704" }, 1994 1995 { BGE_ASICREV_BCM5705, 1996 BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_5705_CORE, 1997 "unknown BCM5705" }, 1998 1999 { BGE_ASICREV_BCM5750, 2000 BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_5705_CORE, 2001 "unknown BCM575x family" }, 2002 2003 { BGE_ASICREV_BCM5714, 2004 BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_5705_CORE, 2005 "unknown BCM5714" }, 2006 2007 { BGE_ASICREV_BCM5752, 2008 BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_5705_CORE, 2009 "unknown BCM5752 family" }, 2010 2011 2012 { BGE_ASICREV_BCM5780, 2013 BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_5705_CORE, 2014 "unknown BCM5780" }, 2015 2016 { BGE_ASICREV_BCM5715, 2017 BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_5705_CORE, 2018 "unknown BCM5715" }, 2019 2020 { 0, 2021 0, 2022 NULL } 2023 }; 2024 2025 2026 static const struct bge_revision * 2027 bge_lookup_rev(uint32_t chipid) 2028 { 2029 const struct bge_revision *br; 2030 2031 for (br = bge_revisions; br->br_name != NULL; br++) { 2032 if (br->br_chipid == chipid) 2033 return (br); 2034 } 2035 2036 for (br = bge_majorrevs; br->br_name != NULL; br++) { 2037 if (br->br_chipid == BGE_ASICREV(chipid)) 2038 return (br); 2039 } 2040 2041 return (NULL); 2042 } 2043 2044 static const struct bge_product { 2045 pci_vendor_id_t bp_vendor; 2046 pci_product_id_t bp_product; 2047 const char *bp_name; 2048 } bge_products[] = { 2049 /* 2050 * The BCM5700 documentation seems to indicate that the hardware 2051 * still has the Alteon vendor ID burned into it, though it 2052 * should always be overridden by the value in the EEPROM. We'll 2053 * check for it anyway. 2054 */ 2055 { PCI_VENDOR_ALTEON, 2056 PCI_PRODUCT_ALTEON_BCM5700, 2057 "Broadcom BCM5700 Gigabit Ethernet", 2058 }, 2059 { PCI_VENDOR_ALTEON, 2060 PCI_PRODUCT_ALTEON_BCM5701, 2061 "Broadcom BCM5701 Gigabit Ethernet", 2062 }, 2063 2064 { PCI_VENDOR_ALTIMA, 2065 PCI_PRODUCT_ALTIMA_AC1000, 2066 "Altima AC1000 Gigabit Ethernet", 2067 }, 2068 { PCI_VENDOR_ALTIMA, 2069 PCI_PRODUCT_ALTIMA_AC1001, 2070 "Altima AC1001 Gigabit Ethernet", 2071 }, 2072 { PCI_VENDOR_ALTIMA, 2073 PCI_PRODUCT_ALTIMA_AC9100, 2074 "Altima AC9100 Gigabit Ethernet", 2075 }, 2076 2077 { PCI_VENDOR_BROADCOM, 2078 PCI_PRODUCT_BROADCOM_BCM5700, 2079 "Broadcom BCM5700 Gigabit Ethernet", 2080 }, 2081 { PCI_VENDOR_BROADCOM, 2082 PCI_PRODUCT_BROADCOM_BCM5701, 2083 "Broadcom BCM5701 Gigabit Ethernet", 2084 }, 2085 { PCI_VENDOR_BROADCOM, 2086 PCI_PRODUCT_BROADCOM_BCM5702, 2087 "Broadcom BCM5702 Gigabit Ethernet", 2088 }, 2089 { PCI_VENDOR_BROADCOM, 2090 PCI_PRODUCT_BROADCOM_BCM5702X, 2091 "Broadcom BCM5702X Gigabit Ethernet" }, 2092 2093 { PCI_VENDOR_BROADCOM, 2094 PCI_PRODUCT_BROADCOM_BCM5703, 2095 "Broadcom BCM5703 Gigabit Ethernet", 2096 }, 2097 { PCI_VENDOR_BROADCOM, 2098 PCI_PRODUCT_BROADCOM_BCM5703X, 2099 "Broadcom BCM5703X Gigabit Ethernet", 2100 }, 2101 { PCI_VENDOR_BROADCOM, 2102 PCI_PRODUCT_BROADCOM_BCM5703A3, 2103 "Broadcom BCM5703A3 Gigabit Ethernet", 2104 }, 2105 2106 { PCI_VENDOR_BROADCOM, 2107 PCI_PRODUCT_BROADCOM_BCM5704C, 2108 "Broadcom BCM5704C Dual Gigabit Ethernet", 2109 }, 2110 { PCI_VENDOR_BROADCOM, 2111 PCI_PRODUCT_BROADCOM_BCM5704S, 2112 "Broadcom BCM5704S Dual Gigabit Ethernet", 2113 }, 2114 2115 { PCI_VENDOR_BROADCOM, 2116 PCI_PRODUCT_BROADCOM_BCM5705, 2117 "Broadcom BCM5705 Gigabit Ethernet", 2118 }, 2119 { PCI_VENDOR_BROADCOM, 2120 PCI_PRODUCT_BROADCOM_BCM5705K, 2121 "Broadcom BCM5705K Gigabit Ethernet", 2122 }, 2123 { PCI_VENDOR_BROADCOM, 2124 PCI_PRODUCT_BROADCOM_BCM5705_ALT, 2125 "Broadcom BCM5705 Gigabit Ethernet", 2126 }, 2127 { PCI_VENDOR_BROADCOM, 2128 PCI_PRODUCT_BROADCOM_BCM5705M, 2129 "Broadcom BCM5705M Gigabit Ethernet", 2130 }, 2131 2132 { PCI_VENDOR_BROADCOM, 2133 PCI_PRODUCT_BROADCOM_BCM5714, 2134 "Broadcom BCM5714/5715 Gigabit Ethernet", 2135 }, 2136 { PCI_VENDOR_BROADCOM, 2137 PCI_PRODUCT_BROADCOM_BCM5789, 2138 "Broadcom BCM5789 Gigabit Ethernet", 2139 }, 2140 2141 { PCI_VENDOR_BROADCOM, 2142 PCI_PRODUCT_BROADCOM_BCM5721, 2143 "Broadcom BCM5721 Gigabit Ethernet", 2144 }, 2145 2146 { PCI_VENDOR_BROADCOM, 2147 PCI_PRODUCT_BROADCOM_BCM5750, 2148 "Broadcom BCM5750 Gigabit Ethernet", 2149 }, 2150 2151 { PCI_VENDOR_BROADCOM, 2152 PCI_PRODUCT_BROADCOM_BCM5750M, 2153 "Broadcom BCM5750M Gigabit Ethernet", 2154 }, 2155 2156 { PCI_VENDOR_BROADCOM, 2157 PCI_PRODUCT_BROADCOM_BCM5751, 2158 "Broadcom BCM5751 Gigabit Ethernet", 2159 }, 2160 2161 { PCI_VENDOR_BROADCOM, 2162 PCI_PRODUCT_BROADCOM_BCM5751M, 2163 "Broadcom BCM5751M Gigabit Ethernet", 2164 }, 2165 2166 { PCI_VENDOR_BROADCOM, 2167 PCI_PRODUCT_BROADCOM_BCM5752, 2168 "Broadcom BCM5752 Gigabit Ethernet", 2169 }, 2170 2171 { PCI_VENDOR_BROADCOM, 2172 PCI_PRODUCT_BROADCOM_BCM5780, 2173 "Broadcom BCM5780 Gigabit Ethernet", 2174 }, 2175 2176 { PCI_VENDOR_BROADCOM, 2177 PCI_PRODUCT_BROADCOM_BCM5780S, 2178 "Broadcom BCM5780S Gigabit Ethernet", 2179 }, 2180 2181 { PCI_VENDOR_BROADCOM, 2182 PCI_PRODUCT_BROADCOM_BCM5782, 2183 "Broadcom BCM5782 Gigabit Ethernet", 2184 }, 2185 2186 { PCI_VENDOR_BROADCOM, 2187 PCI_PRODUCT_BROADCOM_BCM5788, 2188 "Broadcom BCM5788 Gigabit Ethernet", 2189 }, 2190 { PCI_VENDOR_BROADCOM, 2191 PCI_PRODUCT_BROADCOM_BCM5789, 2192 "Broadcom BCM5789 Gigabit Ethernet", 2193 }, 2194 2195 { PCI_VENDOR_BROADCOM, 2196 PCI_PRODUCT_BROADCOM_BCM5901, 2197 "Broadcom BCM5901 Fast Ethernet", 2198 }, 2199 { PCI_VENDOR_BROADCOM, 2200 PCI_PRODUCT_BROADCOM_BCM5901A2, 2201 "Broadcom BCM5901A2 Fast Ethernet", 2202 }, 2203 2204 { PCI_VENDOR_SCHNEIDERKOCH, 2205 PCI_PRODUCT_SCHNEIDERKOCH_SK_9DX1, 2206 "SysKonnect SK-9Dx1 Gigabit Ethernet", 2207 }, 2208 2209 { PCI_VENDOR_3COM, 2210 PCI_PRODUCT_3COM_3C996, 2211 "3Com 3c996 Gigabit Ethernet", 2212 }, 2213 2214 { 0, 2215 0, 2216 NULL }, 2217 }; 2218 2219 static const struct bge_product * 2220 bge_lookup(const struct pci_attach_args *pa) 2221 { 2222 const struct bge_product *bp; 2223 2224 for (bp = bge_products; bp->bp_name != NULL; bp++) { 2225 if (PCI_VENDOR(pa->pa_id) == bp->bp_vendor && 2226 PCI_PRODUCT(pa->pa_id) == bp->bp_product) 2227 return (bp); 2228 } 2229 2230 return (NULL); 2231 } 2232 2233 static int 2234 bge_setpowerstate(struct bge_softc *sc, int powerlevel) 2235 { 2236 #ifdef NOTYET 2237 u_int32_t pm_ctl = 0; 2238 2239 /* XXX FIXME: make sure indirect accesses enabled? */ 2240 pm_ctl = pci_conf_read(sc->bge_dev, BGE_PCI_MISC_CTL, 4); 2241 pm_ctl |= BGE_PCIMISCCTL_INDIRECT_ACCESS; 2242 pci_write_config(sc->bge_dev, BGE_PCI_MISC_CTL, pm_ctl, 4); 2243 2244 /* clear the PME_assert bit and power state bits, enable PME */ 2245 pm_ctl = pci_conf_read(sc->bge_dev, BGE_PCI_PWRMGMT_CMD, 2); 2246 pm_ctl &= ~PCIM_PSTAT_DMASK; 2247 pm_ctl |= (1 << 8); 2248 2249 if (powerlevel == 0) { 2250 pm_ctl |= PCIM_PSTAT_D0; 2251 pci_write_config(sc->bge_dev, BGE_PCI_PWRMGMT_CMD, 2252 pm_ctl, 2); 2253 DELAY(10000); 2254 CSR_WRITE_4(sc, BGE_MISC_LOCAL_CTL, sc->bge_local_ctrl_reg); 2255 DELAY(10000); 2256 2257 #ifdef NOTYET 2258 /* XXX FIXME: write 0x02 to phy aux_Ctrl reg */ 2259 bge_miibus_writereg(sc->bge_dev, 1, 0x18, 0x02); 2260 #endif 2261 DELAY(40); DELAY(40); DELAY(40); 2262 DELAY(10000); /* above not quite adequate on 5700 */ 2263 return 0; 2264 } 2265 2266 2267 /* 2268 * Entering ACPI power states D1-D3 is achieved by wiggling 2269 * GMII gpio pins. Example code assumes all hardware vendors 2270 * followed Broadom's sample pcb layout. Until we verify that 2271 * for all supported OEM cards, states D1-D3 are unsupported. 2272 */ 2273 printf("%s: power state %d unimplemented; check GPIO pins\n", 2274 sc->bge_dev.dv_xname, powerlevel); 2275 #endif 2276 return EOPNOTSUPP; 2277 } 2278 2279 2280 /* 2281 * Probe for a Broadcom chip. Check the PCI vendor and device IDs 2282 * against our list and return its name if we find a match. Note 2283 * that since the Broadcom controller contains VPD support, we 2284 * can get the device name string from the controller itself instead 2285 * of the compiled-in string. This is a little slow, but it guarantees 2286 * we'll always announce the right product name. 2287 */ 2288 static int 2289 bge_probe(device_t parent, cfdata_t match, void *aux) 2290 { 2291 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 2292 2293 if (bge_lookup(pa) != NULL) 2294 return (1); 2295 2296 return (0); 2297 } 2298 2299 static void 2300 bge_attach(device_t parent, device_t self, void *aux) 2301 { 2302 struct bge_softc *sc = (struct bge_softc *)self; 2303 struct pci_attach_args *pa = aux; 2304 const struct bge_product *bp; 2305 const struct bge_revision *br; 2306 pci_chipset_tag_t pc = pa->pa_pc; 2307 pci_intr_handle_t ih; 2308 const char *intrstr = NULL; 2309 bus_dma_segment_t seg; 2310 int rseg; 2311 u_int32_t hwcfg = 0; 2312 u_int32_t mac_addr = 0; 2313 u_int32_t command; 2314 struct ifnet *ifp; 2315 caddr_t kva; 2316 u_char eaddr[ETHER_ADDR_LEN]; 2317 pcireg_t memtype; 2318 bus_addr_t memaddr; 2319 bus_size_t memsize; 2320 u_int32_t pm_ctl; 2321 2322 bp = bge_lookup(pa); 2323 KASSERT(bp != NULL); 2324 2325 sc->bge_pa = *pa; 2326 2327 aprint_naive(": Ethernet controller\n"); 2328 aprint_normal(": %s\n", bp->bp_name); 2329 2330 /* 2331 * Map control/status registers. 2332 */ 2333 DPRINTFN(5, ("Map control/status regs\n")); 2334 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 2335 command |= PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_MASTER_ENABLE; 2336 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, command); 2337 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 2338 2339 if (!(command & PCI_COMMAND_MEM_ENABLE)) { 2340 aprint_error("%s: failed to enable memory mapping!\n", 2341 sc->bge_dev.dv_xname); 2342 return; 2343 } 2344 2345 DPRINTFN(5, ("pci_mem_find\n")); 2346 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, BGE_PCI_BAR0); 2347 switch (memtype) { 2348 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 2349 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 2350 if (pci_mapreg_map(pa, BGE_PCI_BAR0, 2351 memtype, 0, &sc->bge_btag, &sc->bge_bhandle, 2352 &memaddr, &memsize) == 0) 2353 break; 2354 default: 2355 aprint_error("%s: can't find mem space\n", 2356 sc->bge_dev.dv_xname); 2357 return; 2358 } 2359 2360 DPRINTFN(5, ("pci_intr_map\n")); 2361 if (pci_intr_map(pa, &ih)) { 2362 aprint_error("%s: couldn't map interrupt\n", 2363 sc->bge_dev.dv_xname); 2364 return; 2365 } 2366 2367 DPRINTFN(5, ("pci_intr_string\n")); 2368 intrstr = pci_intr_string(pc, ih); 2369 2370 DPRINTFN(5, ("pci_intr_establish\n")); 2371 sc->bge_intrhand = pci_intr_establish(pc, ih, IPL_NET, bge_intr, sc); 2372 2373 if (sc->bge_intrhand == NULL) { 2374 aprint_error("%s: couldn't establish interrupt", 2375 sc->bge_dev.dv_xname); 2376 if (intrstr != NULL) 2377 aprint_normal(" at %s", intrstr); 2378 aprint_normal("\n"); 2379 return; 2380 } 2381 aprint_normal("%s: interrupting at %s\n", 2382 sc->bge_dev.dv_xname, intrstr); 2383 2384 /* 2385 * Kludge for 5700 Bx bug: a hardware bug (PCIX byte enable?) 2386 * can clobber the chip's PCI config-space power control registers, 2387 * leaving the card in D3 powersave state. 2388 * We do not have memory-mapped registers in this state, 2389 * so force device into D0 state before starting initialization. 2390 */ 2391 pm_ctl = pci_conf_read(pc, pa->pa_tag, BGE_PCI_PWRMGMT_CMD); 2392 pm_ctl &= ~(PCI_PWR_D0|PCI_PWR_D1|PCI_PWR_D2|PCI_PWR_D3); 2393 pm_ctl |= (1 << 8) | PCI_PWR_D0 ; /* D0 state */ 2394 pci_conf_write(pc, pa->pa_tag, BGE_PCI_PWRMGMT_CMD, pm_ctl); 2395 DELAY(1000); /* 27 usec is allegedly sufficent */ 2396 2397 /* 2398 * Save ASIC rev. Look up any quirks associated with this 2399 * ASIC. 2400 */ 2401 sc->bge_chipid = 2402 pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_MISC_CTL) & 2403 BGE_PCIMISCCTL_ASICREV; 2404 2405 /* 2406 * Detect PCI-Express devices 2407 * XXX: guessed from Linux/FreeBSD; no documentation 2408 */ 2409 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5750 && 2410 pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_PCIEXPRESS, 2411 NULL, NULL) != 0) 2412 sc->bge_pcie = 1; 2413 else 2414 sc->bge_pcie = 0; 2415 2416 /* Try to reset the chip. */ 2417 DPRINTFN(5, ("bge_reset\n")); 2418 bge_reset(sc); 2419 2420 if (bge_chipinit(sc)) { 2421 aprint_error("%s: chip initialization failed\n", 2422 sc->bge_dev.dv_xname); 2423 bge_release_resources(sc); 2424 return; 2425 } 2426 2427 /* 2428 * Get station address from the EEPROM. 2429 */ 2430 mac_addr = bge_readmem_ind(sc, 0x0c14); 2431 if ((mac_addr >> 16) == 0x484b) { 2432 eaddr[0] = (u_char)(mac_addr >> 8); 2433 eaddr[1] = (u_char)(mac_addr >> 0); 2434 mac_addr = bge_readmem_ind(sc, 0x0c18); 2435 eaddr[2] = (u_char)(mac_addr >> 24); 2436 eaddr[3] = (u_char)(mac_addr >> 16); 2437 eaddr[4] = (u_char)(mac_addr >> 8); 2438 eaddr[5] = (u_char)(mac_addr >> 0); 2439 } else if (bge_read_eeprom(sc, (caddr_t)eaddr, 2440 BGE_EE_MAC_OFFSET + 2, ETHER_ADDR_LEN)) { 2441 aprint_error("%s: failed to read station address\n", 2442 sc->bge_dev.dv_xname); 2443 bge_release_resources(sc); 2444 return; 2445 } 2446 2447 br = bge_lookup_rev(sc->bge_chipid); 2448 aprint_normal("%s: ", sc->bge_dev.dv_xname); 2449 2450 if (br == NULL) { 2451 aprint_normal("unknown ASIC (0x%04x)", sc->bge_chipid >> 16); 2452 sc->bge_quirks = 0; 2453 } else { 2454 aprint_normal("ASIC %s (0x%04x)", 2455 br->br_name, sc->bge_chipid >> 16); 2456 sc->bge_quirks |= br->br_quirks; 2457 } 2458 aprint_normal(", Ethernet address %s\n", ether_sprintf(eaddr)); 2459 2460 /* Allocate the general information block and ring buffers. */ 2461 if (pci_dma64_available(pa)) 2462 sc->bge_dmatag = pa->pa_dmat64; 2463 else 2464 sc->bge_dmatag = pa->pa_dmat; 2465 DPRINTFN(5, ("bus_dmamem_alloc\n")); 2466 if (bus_dmamem_alloc(sc->bge_dmatag, sizeof(struct bge_ring_data), 2467 PAGE_SIZE, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 2468 aprint_error("%s: can't alloc rx buffers\n", 2469 sc->bge_dev.dv_xname); 2470 return; 2471 } 2472 DPRINTFN(5, ("bus_dmamem_map\n")); 2473 if (bus_dmamem_map(sc->bge_dmatag, &seg, rseg, 2474 sizeof(struct bge_ring_data), &kva, 2475 BUS_DMA_NOWAIT)) { 2476 aprint_error("%s: can't map DMA buffers (%d bytes)\n", 2477 sc->bge_dev.dv_xname, (int)sizeof(struct bge_ring_data)); 2478 bus_dmamem_free(sc->bge_dmatag, &seg, rseg); 2479 return; 2480 } 2481 DPRINTFN(5, ("bus_dmamem_create\n")); 2482 if (bus_dmamap_create(sc->bge_dmatag, sizeof(struct bge_ring_data), 1, 2483 sizeof(struct bge_ring_data), 0, 2484 BUS_DMA_NOWAIT, &sc->bge_ring_map)) { 2485 aprint_error("%s: can't create DMA map\n", 2486 sc->bge_dev.dv_xname); 2487 bus_dmamem_unmap(sc->bge_dmatag, kva, 2488 sizeof(struct bge_ring_data)); 2489 bus_dmamem_free(sc->bge_dmatag, &seg, rseg); 2490 return; 2491 } 2492 DPRINTFN(5, ("bus_dmamem_load\n")); 2493 if (bus_dmamap_load(sc->bge_dmatag, sc->bge_ring_map, kva, 2494 sizeof(struct bge_ring_data), NULL, 2495 BUS_DMA_NOWAIT)) { 2496 bus_dmamap_destroy(sc->bge_dmatag, sc->bge_ring_map); 2497 bus_dmamem_unmap(sc->bge_dmatag, kva, 2498 sizeof(struct bge_ring_data)); 2499 bus_dmamem_free(sc->bge_dmatag, &seg, rseg); 2500 return; 2501 } 2502 2503 DPRINTFN(5, ("bzero\n")); 2504 sc->bge_rdata = (struct bge_ring_data *)kva; 2505 2506 memset(sc->bge_rdata, 0, sizeof(struct bge_ring_data)); 2507 2508 /* Try to allocate memory for jumbo buffers. */ 2509 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 2510 if (bge_alloc_jumbo_mem(sc)) { 2511 aprint_error("%s: jumbo buffer allocation failed\n", 2512 sc->bge_dev.dv_xname); 2513 } else 2514 sc->ethercom.ec_capabilities |= ETHERCAP_JUMBO_MTU; 2515 } 2516 2517 /* Set default tuneable values. */ 2518 sc->bge_stat_ticks = BGE_TICKS_PER_SEC; 2519 sc->bge_rx_coal_ticks = 150; 2520 sc->bge_rx_max_coal_bds = 64; 2521 #ifdef ORIG_WPAUL_VALUES 2522 sc->bge_tx_coal_ticks = 150; 2523 sc->bge_tx_max_coal_bds = 128; 2524 #else 2525 sc->bge_tx_coal_ticks = 300; 2526 sc->bge_tx_max_coal_bds = 400; 2527 #endif 2528 if (sc->bge_quirks & BGE_QUIRK_5705_CORE) { 2529 sc->bge_tx_coal_ticks = (12 * 5); 2530 sc->bge_rx_max_coal_bds = (12 * 5); 2531 aprint_error("%s: setting short Tx thresholds\n", 2532 sc->bge_dev.dv_xname); 2533 } 2534 2535 /* Set up ifnet structure */ 2536 ifp = &sc->ethercom.ec_if; 2537 ifp->if_softc = sc; 2538 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 2539 ifp->if_ioctl = bge_ioctl; 2540 ifp->if_start = bge_start; 2541 ifp->if_init = bge_init; 2542 ifp->if_watchdog = bge_watchdog; 2543 IFQ_SET_MAXLEN(&ifp->if_snd, max(BGE_TX_RING_CNT - 1, IFQ_MAXLEN)); 2544 IFQ_SET_READY(&ifp->if_snd); 2545 DPRINTFN(5, ("bcopy\n")); 2546 strcpy(ifp->if_xname, sc->bge_dev.dv_xname); 2547 2548 if ((sc->bge_quirks & BGE_QUIRK_CSUM_BROKEN) == 0) 2549 sc->ethercom.ec_if.if_capabilities |= 2550 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 2551 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 2552 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 2553 sc->ethercom.ec_capabilities |= 2554 ETHERCAP_VLAN_HWTAGGING | ETHERCAP_VLAN_MTU; 2555 2556 if (sc->bge_pcie) 2557 sc->ethercom.ec_if.if_capabilities |= IFCAP_TSOv4; 2558 2559 /* 2560 * Do MII setup. 2561 */ 2562 DPRINTFN(5, ("mii setup\n")); 2563 sc->bge_mii.mii_ifp = ifp; 2564 sc->bge_mii.mii_readreg = bge_miibus_readreg; 2565 sc->bge_mii.mii_writereg = bge_miibus_writereg; 2566 sc->bge_mii.mii_statchg = bge_miibus_statchg; 2567 2568 /* 2569 * Figure out what sort of media we have by checking the 2570 * hardware config word in the first 32k of NIC internal memory, 2571 * or fall back to the config word in the EEPROM. Note: on some BCM5700 2572 * cards, this value appears to be unset. If that's the 2573 * case, we have to rely on identifying the NIC by its PCI 2574 * subsystem ID, as we do below for the SysKonnect SK-9D41. 2575 */ 2576 if (bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_SIG) == BGE_MAGIC_NUMBER) { 2577 hwcfg = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_NICCFG); 2578 } else { 2579 bge_read_eeprom(sc, (caddr_t)&hwcfg, 2580 BGE_EE_HWCFG_OFFSET, sizeof(hwcfg)); 2581 hwcfg = be32toh(hwcfg); 2582 } 2583 if ((hwcfg & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER) 2584 sc->bge_tbi = 1; 2585 2586 /* The SysKonnect SK-9D41 is a 1000baseSX card. */ 2587 if ((pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_SUBSYS) >> 16) == 2588 SK_SUBSYSID_9D41) 2589 sc->bge_tbi = 1; 2590 2591 if (sc->bge_tbi) { 2592 ifmedia_init(&sc->bge_ifmedia, IFM_IMASK, bge_ifmedia_upd, 2593 bge_ifmedia_sts); 2594 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL); 2595 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_1000_SX|IFM_FDX, 2596 0, NULL); 2597 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL); 2598 ifmedia_set(&sc->bge_ifmedia, IFM_ETHER|IFM_AUTO); 2599 } else { 2600 /* 2601 * Do transceiver setup. 2602 */ 2603 ifmedia_init(&sc->bge_mii.mii_media, 0, bge_ifmedia_upd, 2604 bge_ifmedia_sts); 2605 mii_attach(&sc->bge_dev, &sc->bge_mii, 0xffffffff, 2606 MII_PHY_ANY, MII_OFFSET_ANY, 2607 MIIF_FORCEANEG|MIIF_DOPAUSE); 2608 2609 if (LIST_FIRST(&sc->bge_mii.mii_phys) == NULL) { 2610 printf("%s: no PHY found!\n", sc->bge_dev.dv_xname); 2611 ifmedia_add(&sc->bge_mii.mii_media, 2612 IFM_ETHER|IFM_MANUAL, 0, NULL); 2613 ifmedia_set(&sc->bge_mii.mii_media, 2614 IFM_ETHER|IFM_MANUAL); 2615 } else 2616 ifmedia_set(&sc->bge_mii.mii_media, 2617 IFM_ETHER|IFM_AUTO); 2618 } 2619 2620 /* 2621 * When using the BCM5701 in PCI-X mode, data corruption has 2622 * been observed in the first few bytes of some received packets. 2623 * Aligning the packet buffer in memory eliminates the corruption. 2624 * Unfortunately, this misaligns the packet payloads. On platforms 2625 * which do not support unaligned accesses, we will realign the 2626 * payloads by copying the received packets. 2627 */ 2628 if (sc->bge_quirks & BGE_QUIRK_PCIX_DMA_ALIGN_BUG) { 2629 /* If in PCI-X mode, work around the alignment bug. */ 2630 if ((pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_PCISTATE) & 2631 (BGE_PCISTATE_PCI_BUSMODE | BGE_PCISTATE_PCI_BUSSPEED)) == 2632 BGE_PCISTATE_PCI_BUSSPEED) 2633 sc->bge_rx_alignment_bug = 1; 2634 } 2635 2636 /* 2637 * Call MI attach routine. 2638 */ 2639 DPRINTFN(5, ("if_attach\n")); 2640 if_attach(ifp); 2641 DPRINTFN(5, ("ether_ifattach\n")); 2642 ether_ifattach(ifp, eaddr); 2643 #ifdef BGE_EVENT_COUNTERS 2644 /* 2645 * Attach event counters. 2646 */ 2647 evcnt_attach_dynamic(&sc->bge_ev_intr, EVCNT_TYPE_INTR, 2648 NULL, sc->bge_dev.dv_xname, "intr"); 2649 evcnt_attach_dynamic(&sc->bge_ev_tx_xoff, EVCNT_TYPE_MISC, 2650 NULL, sc->bge_dev.dv_xname, "tx_xoff"); 2651 evcnt_attach_dynamic(&sc->bge_ev_tx_xon, EVCNT_TYPE_MISC, 2652 NULL, sc->bge_dev.dv_xname, "tx_xon"); 2653 evcnt_attach_dynamic(&sc->bge_ev_rx_xoff, EVCNT_TYPE_MISC, 2654 NULL, sc->bge_dev.dv_xname, "rx_xoff"); 2655 evcnt_attach_dynamic(&sc->bge_ev_rx_xon, EVCNT_TYPE_MISC, 2656 NULL, sc->bge_dev.dv_xname, "rx_xon"); 2657 evcnt_attach_dynamic(&sc->bge_ev_rx_macctl, EVCNT_TYPE_MISC, 2658 NULL, sc->bge_dev.dv_xname, "rx_macctl"); 2659 evcnt_attach_dynamic(&sc->bge_ev_xoffentered, EVCNT_TYPE_MISC, 2660 NULL, sc->bge_dev.dv_xname, "xoffentered"); 2661 #endif /* BGE_EVENT_COUNTERS */ 2662 DPRINTFN(5, ("callout_init\n")); 2663 callout_init(&sc->bge_timeout); 2664 2665 sc->bge_powerhook = powerhook_establish(bge_powerhook, sc); 2666 if (sc->bge_powerhook == NULL) 2667 printf("%s: WARNING: unable to establish PCI power hook\n", 2668 sc->bge_dev.dv_xname); 2669 } 2670 2671 static void 2672 bge_release_resources(struct bge_softc *sc) 2673 { 2674 if (sc->bge_vpd_prodname != NULL) 2675 free(sc->bge_vpd_prodname, M_DEVBUF); 2676 2677 if (sc->bge_vpd_readonly != NULL) 2678 free(sc->bge_vpd_readonly, M_DEVBUF); 2679 } 2680 2681 static void 2682 bge_reset(struct bge_softc *sc) 2683 { 2684 struct pci_attach_args *pa = &sc->bge_pa; 2685 u_int32_t cachesize, command, pcistate, new_pcistate; 2686 int i, val; 2687 2688 /* Save some important PCI state. */ 2689 cachesize = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_CACHESZ); 2690 command = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_CMD); 2691 pcistate = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_PCISTATE); 2692 2693 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_MISC_CTL, 2694 BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR| 2695 BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_PCISTATE_RW); 2696 2697 val = BGE_MISCCFG_RESET_CORE_CLOCKS | (65<<1); 2698 /* 2699 * XXX: from FreeBSD/Linux; no documentation 2700 */ 2701 if (sc->bge_pcie) { 2702 if (CSR_READ_4(sc, BGE_PCIE_CTL1) == 0x60) 2703 CSR_WRITE_4(sc, BGE_PCIE_CTL1, 0x20); 2704 if (sc->bge_chipid != BGE_CHIPID_BCM5750_A0) { 2705 /* No idea what that actually means */ 2706 CSR_WRITE_4(sc, BGE_MISC_CFG, 1 << 29); 2707 val |= (1<<29); 2708 } 2709 } 2710 2711 /* Issue global reset */ 2712 bge_writereg_ind(sc, BGE_MISC_CFG, val); 2713 2714 DELAY(1000); 2715 2716 /* 2717 * XXX: from FreeBSD/Linux; no documentation 2718 */ 2719 if (sc->bge_pcie) { 2720 if (sc->bge_chipid == BGE_CHIPID_BCM5750_A0) { 2721 pcireg_t reg; 2722 2723 DELAY(500000); 2724 /* XXX: Magic Numbers */ 2725 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_UNKNOWN0); 2726 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_UNKNOWN0, 2727 reg | (1 << 15)); 2728 } 2729 /* 2730 * XXX: Magic Numbers. 2731 * Sets maximal PCI-e payload and clears any PCI-e errors. 2732 * Should be replaced with references to PCI config-space 2733 * capability block for PCI-Express. 2734 */ 2735 pci_conf_write(pa->pa_pc, pa->pa_tag, 2736 BGE_PCI_CONF_DEV_CTRL, 0xf5000); 2737 2738 } 2739 2740 /* Reset some of the PCI state that got zapped by reset */ 2741 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_MISC_CTL, 2742 BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR| 2743 BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_PCISTATE_RW); 2744 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_CMD, command); 2745 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_CACHESZ, cachesize); 2746 bge_writereg_ind(sc, BGE_MISC_CFG, (65 << 1)); 2747 2748 /* Enable memory arbiter. */ 2749 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 2750 uint32_t marbmode = 0; 2751 if (BGE_IS_5714_FAMILY(sc)) { 2752 marbmode = CSR_READ_4(sc, BGE_MARB_MODE); 2753 } 2754 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE | marbmode); 2755 } 2756 2757 /* 2758 * Prevent PXE restart: write a magic number to the 2759 * general communications memory at 0xB50. 2760 */ 2761 bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM, BGE_MAGIC_NUMBER); 2762 2763 /* 2764 * Poll the value location we just wrote until 2765 * we see the 1's complement of the magic number. 2766 * This indicates that the firmware initialization 2767 * is complete. 2768 */ 2769 for (i = 0; i < BGE_TIMEOUT; i++) { 2770 val = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM); 2771 if (val == ~BGE_MAGIC_NUMBER) 2772 break; 2773 DELAY(1000); 2774 } 2775 2776 if (i >= BGE_TIMEOUT) { 2777 printf("%s: firmware handshake timed out, val = %x\n", 2778 sc->bge_dev.dv_xname, val); 2779 /* 2780 * XXX: occasionally fired on bcm5721, but without 2781 * apparent harm. For now, keep going if we timeout 2782 * against PCI-E devices. 2783 */ 2784 if (!sc->bge_pcie) 2785 return; 2786 } 2787 2788 /* 2789 * XXX Wait for the value of the PCISTATE register to 2790 * return to its original pre-reset state. This is a 2791 * fairly good indicator of reset completion. If we don't 2792 * wait for the reset to fully complete, trying to read 2793 * from the device's non-PCI registers may yield garbage 2794 * results. 2795 */ 2796 for (i = 0; i < BGE_TIMEOUT; i++) { 2797 new_pcistate = pci_conf_read(pa->pa_pc, pa->pa_tag, 2798 BGE_PCI_PCISTATE); 2799 if ((new_pcistate & ~BGE_PCISTATE_RESERVED) == 2800 (pcistate & ~BGE_PCISTATE_RESERVED)) 2801 break; 2802 DELAY(10); 2803 } 2804 if ((new_pcistate & ~BGE_PCISTATE_RESERVED) != 2805 (pcistate & ~BGE_PCISTATE_RESERVED)) { 2806 printf("%s: pcistate failed to revert\n", 2807 sc->bge_dev.dv_xname); 2808 } 2809 2810 /* XXX: from FreeBSD/Linux; no documentation */ 2811 if (sc->bge_pcie && sc->bge_chipid != BGE_CHIPID_BCM5750_A0) 2812 CSR_WRITE_4(sc, BGE_PCIE_CTL0, CSR_READ_4(sc, BGE_PCIE_CTL0) | (1<<25)); 2813 2814 /* Enable memory arbiter. */ 2815 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 2816 uint32_t marbmode = 0; 2817 if (BGE_IS_5714_FAMILY(sc)) { 2818 marbmode = CSR_READ_4(sc, BGE_MARB_MODE); 2819 } 2820 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE | marbmode); 2821 } 2822 2823 /* Fix up byte swapping */ 2824 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS); 2825 2826 CSR_WRITE_4(sc, BGE_MAC_MODE, 0); 2827 2828 DELAY(10000); 2829 } 2830 2831 /* 2832 * Frame reception handling. This is called if there's a frame 2833 * on the receive return list. 2834 * 2835 * Note: we have to be able to handle two possibilities here: 2836 * 1) the frame is from the jumbo recieve ring 2837 * 2) the frame is from the standard receive ring 2838 */ 2839 2840 static void 2841 bge_rxeof(struct bge_softc *sc) 2842 { 2843 struct ifnet *ifp; 2844 int stdcnt = 0, jumbocnt = 0; 2845 bus_dmamap_t dmamap; 2846 bus_addr_t offset, toff; 2847 bus_size_t tlen; 2848 int tosync; 2849 2850 ifp = &sc->ethercom.ec_if; 2851 2852 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 2853 offsetof(struct bge_ring_data, bge_status_block), 2854 sizeof (struct bge_status_block), 2855 BUS_DMASYNC_POSTREAD); 2856 2857 offset = offsetof(struct bge_ring_data, bge_rx_return_ring); 2858 tosync = sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx - 2859 sc->bge_rx_saved_considx; 2860 2861 toff = offset + (sc->bge_rx_saved_considx * sizeof (struct bge_rx_bd)); 2862 2863 if (tosync < 0) { 2864 tlen = (sc->bge_return_ring_cnt - sc->bge_rx_saved_considx) * 2865 sizeof (struct bge_rx_bd); 2866 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 2867 toff, tlen, BUS_DMASYNC_POSTREAD); 2868 tosync = -tosync; 2869 } 2870 2871 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 2872 offset, tosync * sizeof (struct bge_rx_bd), 2873 BUS_DMASYNC_POSTREAD); 2874 2875 while(sc->bge_rx_saved_considx != 2876 sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx) { 2877 struct bge_rx_bd *cur_rx; 2878 u_int32_t rxidx; 2879 struct mbuf *m = NULL; 2880 2881 cur_rx = &sc->bge_rdata-> 2882 bge_rx_return_ring[sc->bge_rx_saved_considx]; 2883 2884 rxidx = cur_rx->bge_idx; 2885 BGE_INC(sc->bge_rx_saved_considx, sc->bge_return_ring_cnt); 2886 2887 if (cur_rx->bge_flags & BGE_RXBDFLAG_JUMBO_RING) { 2888 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT); 2889 m = sc->bge_cdata.bge_rx_jumbo_chain[rxidx]; 2890 sc->bge_cdata.bge_rx_jumbo_chain[rxidx] = NULL; 2891 jumbocnt++; 2892 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 2893 ifp->if_ierrors++; 2894 bge_newbuf_jumbo(sc, sc->bge_jumbo, m); 2895 continue; 2896 } 2897 if (bge_newbuf_jumbo(sc, sc->bge_jumbo, 2898 NULL)== ENOBUFS) { 2899 ifp->if_ierrors++; 2900 bge_newbuf_jumbo(sc, sc->bge_jumbo, m); 2901 continue; 2902 } 2903 } else { 2904 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT); 2905 m = sc->bge_cdata.bge_rx_std_chain[rxidx]; 2906 sc->bge_cdata.bge_rx_std_chain[rxidx] = NULL; 2907 stdcnt++; 2908 dmamap = sc->bge_cdata.bge_rx_std_map[rxidx]; 2909 sc->bge_cdata.bge_rx_std_map[rxidx] = 0; 2910 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 2911 ifp->if_ierrors++; 2912 bge_newbuf_std(sc, sc->bge_std, m, dmamap); 2913 continue; 2914 } 2915 if (bge_newbuf_std(sc, sc->bge_std, 2916 NULL, dmamap) == ENOBUFS) { 2917 ifp->if_ierrors++; 2918 bge_newbuf_std(sc, sc->bge_std, m, dmamap); 2919 continue; 2920 } 2921 } 2922 2923 ifp->if_ipackets++; 2924 #ifndef __NO_STRICT_ALIGNMENT 2925 /* 2926 * XXX: if the 5701 PCIX-Rx-DMA workaround is in effect, 2927 * the Rx buffer has the layer-2 header unaligned. 2928 * If our CPU requires alignment, re-align by copying. 2929 */ 2930 if (sc->bge_rx_alignment_bug) { 2931 memmove(mtod(m, caddr_t) + ETHER_ALIGN, m->m_data, 2932 cur_rx->bge_len); 2933 m->m_data += ETHER_ALIGN; 2934 } 2935 #endif 2936 2937 m->m_pkthdr.len = m->m_len = cur_rx->bge_len - ETHER_CRC_LEN; 2938 m->m_pkthdr.rcvif = ifp; 2939 2940 #if NBPFILTER > 0 2941 /* 2942 * Handle BPF listeners. Let the BPF user see the packet. 2943 */ 2944 if (ifp->if_bpf) 2945 bpf_mtap(ifp->if_bpf, m); 2946 #endif 2947 2948 m->m_pkthdr.csum_flags = M_CSUM_IPv4; 2949 2950 if ((cur_rx->bge_ip_csum ^ 0xffff) != 0) 2951 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 2952 /* 2953 * Rx transport checksum-offload may also 2954 * have bugs with packets which, when transmitted, 2955 * were `runts' requiring padding. 2956 */ 2957 if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM && 2958 (/* (sc->_bge_quirks & BGE_QUIRK_SHORT_CKSUM_BUG) == 0 ||*/ 2959 m->m_pkthdr.len >= ETHER_MIN_NOPAD)) { 2960 m->m_pkthdr.csum_data = 2961 cur_rx->bge_tcp_udp_csum; 2962 m->m_pkthdr.csum_flags |= 2963 (M_CSUM_TCPv4|M_CSUM_UDPv4| 2964 M_CSUM_DATA|M_CSUM_NO_PSEUDOHDR); 2965 } 2966 2967 /* 2968 * If we received a packet with a vlan tag, pass it 2969 * to vlan_input() instead of ether_input(). 2970 */ 2971 if (cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) 2972 VLAN_INPUT_TAG(ifp, m, cur_rx->bge_vlan_tag, continue); 2973 2974 (*ifp->if_input)(ifp, m); 2975 } 2976 2977 CSR_WRITE_4(sc, BGE_MBX_RX_CONS0_LO, sc->bge_rx_saved_considx); 2978 if (stdcnt) 2979 CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std); 2980 if (jumbocnt) 2981 CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo); 2982 } 2983 2984 static void 2985 bge_txeof(struct bge_softc *sc) 2986 { 2987 struct bge_tx_bd *cur_tx = NULL; 2988 struct ifnet *ifp; 2989 struct txdmamap_pool_entry *dma; 2990 bus_addr_t offset, toff; 2991 bus_size_t tlen; 2992 int tosync; 2993 struct mbuf *m; 2994 2995 ifp = &sc->ethercom.ec_if; 2996 2997 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 2998 offsetof(struct bge_ring_data, bge_status_block), 2999 sizeof (struct bge_status_block), 3000 BUS_DMASYNC_POSTREAD); 3001 3002 offset = offsetof(struct bge_ring_data, bge_tx_ring); 3003 tosync = sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx - 3004 sc->bge_tx_saved_considx; 3005 3006 toff = offset + (sc->bge_tx_saved_considx * sizeof (struct bge_tx_bd)); 3007 3008 if (tosync < 0) { 3009 tlen = (BGE_TX_RING_CNT - sc->bge_tx_saved_considx) * 3010 sizeof (struct bge_tx_bd); 3011 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 3012 toff, tlen, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 3013 tosync = -tosync; 3014 } 3015 3016 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 3017 offset, tosync * sizeof (struct bge_tx_bd), 3018 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 3019 3020 /* 3021 * Go through our tx ring and free mbufs for those 3022 * frames that have been sent. 3023 */ 3024 while (sc->bge_tx_saved_considx != 3025 sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx) { 3026 u_int32_t idx = 0; 3027 3028 idx = sc->bge_tx_saved_considx; 3029 cur_tx = &sc->bge_rdata->bge_tx_ring[idx]; 3030 if (cur_tx->bge_flags & BGE_TXBDFLAG_END) 3031 ifp->if_opackets++; 3032 m = sc->bge_cdata.bge_tx_chain[idx]; 3033 if (m != NULL) { 3034 sc->bge_cdata.bge_tx_chain[idx] = NULL; 3035 dma = sc->txdma[idx]; 3036 bus_dmamap_sync(sc->bge_dmatag, dma->dmamap, 0, 3037 dma->dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 3038 bus_dmamap_unload(sc->bge_dmatag, dma->dmamap); 3039 SLIST_INSERT_HEAD(&sc->txdma_list, dma, link); 3040 sc->txdma[idx] = NULL; 3041 3042 m_freem(m); 3043 } 3044 sc->bge_txcnt--; 3045 BGE_INC(sc->bge_tx_saved_considx, BGE_TX_RING_CNT); 3046 ifp->if_timer = 0; 3047 } 3048 3049 if (cur_tx != NULL) 3050 ifp->if_flags &= ~IFF_OACTIVE; 3051 } 3052 3053 static int 3054 bge_intr(void *xsc) 3055 { 3056 struct bge_softc *sc; 3057 struct ifnet *ifp; 3058 3059 sc = xsc; 3060 ifp = &sc->ethercom.ec_if; 3061 3062 #ifdef notdef 3063 /* Avoid this for now -- checking this register is expensive. */ 3064 /* Make sure this is really our interrupt. */ 3065 if (!(CSR_READ_4(sc, BGE_MISC_LOCAL_CTL) & BGE_MLC_INTR_STATE)) 3066 return (0); 3067 #endif 3068 /* Ack interrupt and stop others from occuring. */ 3069 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 1); 3070 3071 BGE_EVCNT_INCR(sc->bge_ev_intr); 3072 3073 /* 3074 * Process link state changes. 3075 * Grrr. The link status word in the status block does 3076 * not work correctly on the BCM5700 rev AX and BX chips, 3077 * according to all available information. Hence, we have 3078 * to enable MII interrupts in order to properly obtain 3079 * async link changes. Unfortunately, this also means that 3080 * we have to read the MAC status register to detect link 3081 * changes, thereby adding an additional register access to 3082 * the interrupt handler. 3083 */ 3084 3085 if (sc->bge_quirks & BGE_QUIRK_LINK_STATE_BROKEN) { 3086 u_int32_t status; 3087 3088 status = CSR_READ_4(sc, BGE_MAC_STS); 3089 if (status & BGE_MACSTAT_MI_INTERRUPT) { 3090 sc->bge_link = 0; 3091 callout_stop(&sc->bge_timeout); 3092 bge_tick(sc); 3093 /* Clear the interrupt */ 3094 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, 3095 BGE_EVTENB_MI_INTERRUPT); 3096 bge_miibus_readreg(&sc->bge_dev, 1, BRGPHY_MII_ISR); 3097 bge_miibus_writereg(&sc->bge_dev, 1, BRGPHY_MII_IMR, 3098 BRGPHY_INTRS); 3099 } 3100 } else { 3101 if (sc->bge_rdata->bge_status_block.bge_status & 3102 BGE_STATFLAG_LINKSTATE_CHANGED) { 3103 sc->bge_link = 0; 3104 callout_stop(&sc->bge_timeout); 3105 bge_tick(sc); 3106 /* Clear the interrupt */ 3107 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED| 3108 BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE| 3109 BGE_MACSTAT_LINK_CHANGED); 3110 } 3111 } 3112 3113 if (ifp->if_flags & IFF_RUNNING) { 3114 /* Check RX return ring producer/consumer */ 3115 bge_rxeof(sc); 3116 3117 /* Check TX ring producer/consumer */ 3118 bge_txeof(sc); 3119 } 3120 3121 if (sc->bge_pending_rxintr_change) { 3122 uint32_t rx_ticks = sc->bge_rx_coal_ticks; 3123 uint32_t rx_bds = sc->bge_rx_max_coal_bds; 3124 uint32_t junk; 3125 3126 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, rx_ticks); 3127 DELAY(10); 3128 junk = CSR_READ_4(sc, BGE_HCC_RX_COAL_TICKS); 3129 3130 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, rx_bds); 3131 DELAY(10); 3132 junk = CSR_READ_4(sc, BGE_HCC_RX_MAX_COAL_BDS); 3133 3134 sc->bge_pending_rxintr_change = 0; 3135 } 3136 bge_handle_events(sc); 3137 3138 /* Re-enable interrupts. */ 3139 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 0); 3140 3141 if (ifp->if_flags & IFF_RUNNING && !IFQ_IS_EMPTY(&ifp->if_snd)) 3142 bge_start(ifp); 3143 3144 return (1); 3145 } 3146 3147 static void 3148 bge_tick(void *xsc) 3149 { 3150 struct bge_softc *sc = xsc; 3151 struct mii_data *mii = &sc->bge_mii; 3152 struct ifmedia *ifm = NULL; 3153 struct ifnet *ifp = &sc->ethercom.ec_if; 3154 int s; 3155 3156 s = splnet(); 3157 3158 bge_stats_update(sc); 3159 callout_reset(&sc->bge_timeout, hz, bge_tick, sc); 3160 if (sc->bge_link) { 3161 splx(s); 3162 return; 3163 } 3164 3165 if (sc->bge_tbi) { 3166 ifm = &sc->bge_ifmedia; 3167 if (CSR_READ_4(sc, BGE_MAC_STS) & 3168 BGE_MACSTAT_TBI_PCS_SYNCHED) { 3169 sc->bge_link++; 3170 CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF); 3171 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 3172 bge_start(ifp); 3173 } 3174 splx(s); 3175 return; 3176 } 3177 3178 mii_tick(mii); 3179 3180 if (!sc->bge_link && mii->mii_media_status & IFM_ACTIVE && 3181 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 3182 sc->bge_link++; 3183 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 3184 bge_start(ifp); 3185 } 3186 3187 splx(s); 3188 } 3189 3190 static void 3191 bge_stats_update(struct bge_softc *sc) 3192 { 3193 struct ifnet *ifp = &sc->ethercom.ec_if; 3194 bus_size_t stats = BGE_MEMWIN_START + BGE_STATS_BLOCK; 3195 bus_size_t rstats = BGE_RX_STATS; 3196 3197 #define READ_RSTAT(sc, stats, stat) \ 3198 CSR_READ_4(sc, stats + offsetof(struct bge_mac_stats_regs, stat)) 3199 3200 if (sc->bge_quirks & BGE_QUIRK_5705_CORE) { 3201 ifp->if_collisions += 3202 READ_RSTAT(sc, rstats, dot3StatsSingleCollisionFrames) + 3203 READ_RSTAT(sc, rstats, dot3StatsMultipleCollisionFrames) + 3204 READ_RSTAT(sc, rstats, dot3StatsExcessiveCollisions) + 3205 READ_RSTAT(sc, rstats, dot3StatsLateCollisions); 3206 3207 BGE_EVCNT_ADD(sc->bge_ev_tx_xoff, 3208 READ_RSTAT(sc, rstats, outXoffSent)); 3209 BGE_EVCNT_ADD(sc->bge_ev_tx_xon, 3210 READ_RSTAT(sc, rstats, outXonSent)); 3211 BGE_EVCNT_ADD(sc->bge_ev_rx_xoff, 3212 READ_RSTAT(sc, rstats, xoffPauseFramesReceived)); 3213 BGE_EVCNT_ADD(sc->bge_ev_rx_xon, 3214 READ_RSTAT(sc, rstats, xonPauseFramesReceived)); 3215 BGE_EVCNT_ADD(sc->bge_ev_rx_macctl, 3216 READ_RSTAT(sc, rstats, macControlFramesReceived)); 3217 BGE_EVCNT_ADD(sc->bge_ev_xoffentered, 3218 READ_RSTAT(sc, rstats, xoffStateEntered)); 3219 return; 3220 } 3221 3222 #undef READ_RSTAT 3223 #define READ_STAT(sc, stats, stat) \ 3224 CSR_READ_4(sc, stats + offsetof(struct bge_stats, stat)) 3225 3226 ifp->if_collisions += 3227 (READ_STAT(sc, stats, dot3StatsSingleCollisionFrames.bge_addr_lo) + 3228 READ_STAT(sc, stats, dot3StatsMultipleCollisionFrames.bge_addr_lo) + 3229 READ_STAT(sc, stats, dot3StatsExcessiveCollisions.bge_addr_lo) + 3230 READ_STAT(sc, stats, dot3StatsLateCollisions.bge_addr_lo)) - 3231 ifp->if_collisions; 3232 3233 BGE_EVCNT_UPD(sc->bge_ev_tx_xoff, 3234 READ_STAT(sc, stats, outXoffSent.bge_addr_lo)); 3235 BGE_EVCNT_UPD(sc->bge_ev_tx_xon, 3236 READ_STAT(sc, stats, outXonSent.bge_addr_lo)); 3237 BGE_EVCNT_UPD(sc->bge_ev_rx_xoff, 3238 READ_STAT(sc, stats, 3239 xoffPauseFramesReceived.bge_addr_lo)); 3240 BGE_EVCNT_UPD(sc->bge_ev_rx_xon, 3241 READ_STAT(sc, stats, xonPauseFramesReceived.bge_addr_lo)); 3242 BGE_EVCNT_UPD(sc->bge_ev_rx_macctl, 3243 READ_STAT(sc, stats, 3244 macControlFramesReceived.bge_addr_lo)); 3245 BGE_EVCNT_UPD(sc->bge_ev_xoffentered, 3246 READ_STAT(sc, stats, xoffStateEntered.bge_addr_lo)); 3247 3248 #undef READ_STAT 3249 3250 #ifdef notdef 3251 ifp->if_collisions += 3252 (sc->bge_rdata->bge_info.bge_stats.dot3StatsSingleCollisionFrames + 3253 sc->bge_rdata->bge_info.bge_stats.dot3StatsMultipleCollisionFrames + 3254 sc->bge_rdata->bge_info.bge_stats.dot3StatsExcessiveCollisions + 3255 sc->bge_rdata->bge_info.bge_stats.dot3StatsLateCollisions) - 3256 ifp->if_collisions; 3257 #endif 3258 } 3259 3260 /* 3261 * Pad outbound frame to ETHER_MIN_NOPAD for an unusual reason. 3262 * The bge hardware will pad out Tx runts to ETHER_MIN_NOPAD, 3263 * but when such padded frames employ the bge IP/TCP checksum offload, 3264 * the hardware checksum assist gives incorrect results (possibly 3265 * from incorporating its own padding into the UDP/TCP checksum; who knows). 3266 * If we pad such runts with zeros, the onboard checksum comes out correct. 3267 */ 3268 static inline int 3269 bge_cksum_pad(struct mbuf *pkt) 3270 { 3271 struct mbuf *last = NULL; 3272 int padlen; 3273 3274 padlen = ETHER_MIN_NOPAD - pkt->m_pkthdr.len; 3275 3276 /* if there's only the packet-header and we can pad there, use it. */ 3277 if (pkt->m_pkthdr.len == pkt->m_len && 3278 !M_READONLY(pkt) && M_TRAILINGSPACE(pkt) >= padlen) { 3279 last = pkt; 3280 } else { 3281 /* 3282 * Walk packet chain to find last mbuf. We will either 3283 * pad there, or append a new mbuf and pad it 3284 * (thus perhaps avoiding the bcm5700 dma-min bug). 3285 */ 3286 for (last = pkt; last->m_next != NULL; last = last->m_next) { 3287 (void) 0; /* do nothing*/ 3288 } 3289 3290 /* `last' now points to last in chain. */ 3291 if (!M_READONLY(last) && M_TRAILINGSPACE(last) >= padlen) { 3292 (void) 0; /* we can pad here, in-place. */ 3293 } else { 3294 /* Allocate new empty mbuf, pad it. Compact later. */ 3295 struct mbuf *n; 3296 MGET(n, M_DONTWAIT, MT_DATA); 3297 n->m_len = 0; 3298 last->m_next = n; 3299 last = n; 3300 } 3301 } 3302 3303 #ifdef DEBUG 3304 /*KASSERT(M_WRITABLE(last), ("to-pad mbuf not writeable\n"));*/ 3305 KASSERT(M_TRAILINGSPACE(last) >= padlen /*, ("insufficient space to pad\n")*/ ); 3306 #endif 3307 /* Now zero the pad area, to avoid the bge cksum-assist bug */ 3308 memset(mtod(last, caddr_t) + last->m_len, 0, padlen); 3309 last->m_len += padlen; 3310 pkt->m_pkthdr.len += padlen; 3311 return 0; 3312 } 3313 3314 /* 3315 * Compact outbound packets to avoid bug with DMA segments less than 8 bytes. 3316 */ 3317 static inline int 3318 bge_compact_dma_runt(struct mbuf *pkt) 3319 { 3320 struct mbuf *m, *prev; 3321 int totlen, prevlen; 3322 3323 prev = NULL; 3324 totlen = 0; 3325 prevlen = -1; 3326 3327 for (m = pkt; m != NULL; prev = m,m = m->m_next) { 3328 int mlen = m->m_len; 3329 int shortfall = 8 - mlen ; 3330 3331 totlen += mlen; 3332 if (mlen == 0) { 3333 continue; 3334 } 3335 if (mlen >= 8) 3336 continue; 3337 3338 /* If we get here, mbuf data is too small for DMA engine. 3339 * Try to fix by shuffling data to prev or next in chain. 3340 * If that fails, do a compacting deep-copy of the whole chain. 3341 */ 3342 3343 /* Internal frag. If fits in prev, copy it there. */ 3344 if (prev && !M_READONLY(prev) && 3345 M_TRAILINGSPACE(prev) >= m->m_len) { 3346 bcopy(m->m_data, 3347 prev->m_data+prev->m_len, 3348 mlen); 3349 prev->m_len += mlen; 3350 m->m_len = 0; 3351 /* XXX stitch chain */ 3352 prev->m_next = m_free(m); 3353 m = prev; 3354 continue; 3355 } 3356 else if (m->m_next != NULL && !M_READONLY(m) && 3357 M_TRAILINGSPACE(m) >= shortfall && 3358 m->m_next->m_len >= (8 + shortfall)) { 3359 /* m is writable and have enough data in next, pull up. */ 3360 3361 bcopy(m->m_next->m_data, 3362 m->m_data+m->m_len, 3363 shortfall); 3364 m->m_len += shortfall; 3365 m->m_next->m_len -= shortfall; 3366 m->m_next->m_data += shortfall; 3367 } 3368 else if (m->m_next == NULL || 1) { 3369 /* Got a runt at the very end of the packet. 3370 * borrow data from the tail of the preceding mbuf and 3371 * update its length in-place. (The original data is still 3372 * valid, so we can do this even if prev is not writable.) 3373 */ 3374 3375 /* if we'd make prev a runt, just move all of its data. */ 3376 #ifdef DEBUG 3377 KASSERT(prev != NULL /*, ("runt but null PREV")*/); 3378 KASSERT(prev->m_len >= 8 /*, ("runt prev")*/); 3379 #endif 3380 if ((prev->m_len - shortfall) < 8) 3381 shortfall = prev->m_len; 3382 3383 #ifdef notyet /* just do the safe slow thing for now */ 3384 if (!M_READONLY(m)) { 3385 if (M_LEADINGSPACE(m) < shorfall) { 3386 void *m_dat; 3387 m_dat = (m->m_flags & M_PKTHDR) ? 3388 m->m_pktdat : m->dat; 3389 memmove(m_dat, mtod(m, void*), m->m_len); 3390 m->m_data = m_dat; 3391 } 3392 } else 3393 #endif /* just do the safe slow thing */ 3394 { 3395 struct mbuf * n = NULL; 3396 int newprevlen = prev->m_len - shortfall; 3397 3398 MGET(n, M_NOWAIT, MT_DATA); 3399 if (n == NULL) 3400 return ENOBUFS; 3401 KASSERT(m->m_len + shortfall < MLEN 3402 /*, 3403 ("runt %d +prev %d too big\n", m->m_len, shortfall)*/); 3404 3405 /* first copy the data we're stealing from prev */ 3406 bcopy(prev->m_data + newprevlen, n->m_data, shortfall); 3407 3408 /* update prev->m_len accordingly */ 3409 prev->m_len -= shortfall; 3410 3411 /* copy data from runt m */ 3412 bcopy(m->m_data, n->m_data + shortfall, m->m_len); 3413 3414 /* n holds what we stole from prev, plus m */ 3415 n->m_len = shortfall + m->m_len; 3416 3417 /* stitch n into chain and free m */ 3418 n->m_next = m->m_next; 3419 prev->m_next = n; 3420 /* KASSERT(m->m_next == NULL); */ 3421 m->m_next = NULL; 3422 m_free(m); 3423 m = n; /* for continuing loop */ 3424 } 3425 } 3426 prevlen = m->m_len; 3427 } 3428 return 0; 3429 } 3430 3431 /* 3432 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data 3433 * pointers to descriptors. 3434 */ 3435 static int 3436 bge_encap(struct bge_softc *sc, struct mbuf *m_head, u_int32_t *txidx) 3437 { 3438 struct bge_tx_bd *f = NULL; 3439 u_int32_t frag, cur, cnt = 0; 3440 u_int16_t csum_flags = 0; 3441 u_int16_t txbd_tso_flags = 0; 3442 struct txdmamap_pool_entry *dma; 3443 bus_dmamap_t dmamap; 3444 int i = 0; 3445 struct m_tag *mtag; 3446 int use_tso, maxsegsize, error; 3447 3448 cur = frag = *txidx; 3449 3450 if (m_head->m_pkthdr.csum_flags) { 3451 if (m_head->m_pkthdr.csum_flags & M_CSUM_IPv4) 3452 csum_flags |= BGE_TXBDFLAG_IP_CSUM; 3453 if (m_head->m_pkthdr.csum_flags & (M_CSUM_TCPv4|M_CSUM_UDPv4)) 3454 csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM; 3455 } 3456 3457 /* 3458 * If we were asked to do an outboard checksum, and the NIC 3459 * has the bug where it sometimes adds in the Ethernet padding, 3460 * explicitly pad with zeros so the cksum will be correct either way. 3461 * (For now, do this for all chip versions, until newer 3462 * are confirmed to not require the workaround.) 3463 */ 3464 if ((csum_flags & BGE_TXBDFLAG_TCP_UDP_CSUM) == 0 || 3465 #ifdef notyet 3466 (sc->bge_quirks & BGE_QUIRK_SHORT_CKSUM_BUG) == 0 || 3467 #endif 3468 m_head->m_pkthdr.len >= ETHER_MIN_NOPAD) 3469 goto check_dma_bug; 3470 3471 if (bge_cksum_pad(m_head) != 0) { 3472 return ENOBUFS; 3473 } 3474 3475 check_dma_bug: 3476 if (!(sc->bge_quirks & BGE_QUIRK_5700_SMALLDMA)) 3477 goto doit; 3478 /* 3479 * bcm5700 Revision B silicon cannot handle DMA descriptors with 3480 * less than eight bytes. If we encounter a teeny mbuf 3481 * at the end of a chain, we can pad. Otherwise, copy. 3482 */ 3483 if (bge_compact_dma_runt(m_head) != 0) 3484 return ENOBUFS; 3485 3486 doit: 3487 dma = SLIST_FIRST(&sc->txdma_list); 3488 if (dma == NULL) 3489 return ENOBUFS; 3490 dmamap = dma->dmamap; 3491 3492 /* 3493 * Set up any necessary TSO state before we start packing... 3494 */ 3495 use_tso = (m_head->m_pkthdr.csum_flags & M_CSUM_TSOv4) != 0; 3496 if (!use_tso) { 3497 maxsegsize = 0; 3498 } else { /* TSO setup */ 3499 unsigned mss; 3500 struct ether_header *eh; 3501 unsigned ip_tcp_hlen, iptcp_opt_words, tcp_seg_flags, offset; 3502 struct mbuf * m0 = m_head; 3503 struct ip *ip; 3504 struct tcphdr *th; 3505 int iphl, hlen; 3506 3507 /* 3508 * XXX It would be nice if the mbuf pkthdr had offset 3509 * fields for the protocol headers. 3510 */ 3511 3512 eh = mtod(m0, struct ether_header *); 3513 switch (htons(eh->ether_type)) { 3514 case ETHERTYPE_IP: 3515 offset = ETHER_HDR_LEN; 3516 break; 3517 3518 case ETHERTYPE_VLAN: 3519 offset = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 3520 break; 3521 3522 default: 3523 /* 3524 * Don't support this protocol or encapsulation. 3525 */ 3526 return (ENOBUFS); 3527 } 3528 3529 /* 3530 * TCP/IP headers are in the first mbuf; we can do 3531 * this the easy way. 3532 */ 3533 iphl = M_CSUM_DATA_IPv4_IPHL(m0->m_pkthdr.csum_data); 3534 hlen = iphl + offset; 3535 if (__predict_false(m0->m_len < 3536 (hlen + sizeof(struct tcphdr)))) { 3537 3538 printf("TSO: hard case m0->m_len == %d <" 3539 " ip/tcp hlen %zd, not handled yet\n", 3540 m0->m_len, hlen+ sizeof(struct tcphdr)); 3541 #ifdef NOTYET 3542 /* 3543 * XXX jonathan (at) NetBSD.org: untested. 3544 * how to force this branch to be taken? 3545 */ 3546 BGE_EVCNT_INCR(&sc->sc_ev_txtsopain); 3547 3548 m_copydata(m0, offset, sizeof(ip), &ip); 3549 m_copydata(m0, hlen, sizeof(th), &th); 3550 3551 ip.ip_len = 0; 3552 3553 m_copyback(m0, hlen + offsetof(struct ip, ip_len), 3554 sizeof(ip.ip_len), &ip.ip_len); 3555 3556 th.th_sum = in_cksum_phdr(ip.ip_src.s_addr, 3557 ip.ip_dst.s_addr, htons(IPPROTO_TCP)); 3558 3559 m_copyback(m0, hlen + offsetof(struct tcphdr, th_sum), 3560 sizeof(th.th_sum), &th.th_sum); 3561 3562 hlen += th.th_off << 2; 3563 iptcp_opt_words = hlen; 3564 #else 3565 /* 3566 * if_wm "hard" case not yet supported, can we not 3567 * mandate it out of existence? 3568 */ 3569 (void) ip; (void)th; (void) ip_tcp_hlen; 3570 3571 return ENOBUFS; 3572 #endif 3573 } else { 3574 ip = (struct ip *) (mtod(m0, caddr_t) + offset); 3575 th = (struct tcphdr *) (mtod(m0, caddr_t) + hlen); 3576 ip_tcp_hlen = iphl + (th->th_off << 2); 3577 3578 /* Total IP/TCP options, in 32-bit words */ 3579 iptcp_opt_words = (ip_tcp_hlen 3580 - sizeof(struct tcphdr) 3581 - sizeof(struct ip)) >> 2; 3582 } 3583 if (BGE_IS_5750_OR_BEYOND(sc)) { 3584 th->th_sum = 0; 3585 csum_flags &= ~(BGE_TXBDFLAG_TCP_UDP_CSUM); 3586 } else { 3587 /* 3588 * XXX jonathan (at) NetBSD.org: 5705 untested. 3589 * Requires TSO firmware patch for 5701/5703/5704. 3590 */ 3591 th->th_sum = in_cksum_phdr(ip->ip_src.s_addr, 3592 ip->ip_dst.s_addr, htons(IPPROTO_TCP)); 3593 } 3594 3595 mss = m_head->m_pkthdr.segsz; 3596 txbd_tso_flags |= 3597 BGE_TXBDFLAG_CPU_PRE_DMA | 3598 BGE_TXBDFLAG_CPU_POST_DMA; 3599 3600 /* 3601 * Our NIC TSO-assist assumes TSO has standard, optionless 3602 * IPv4 and TCP headers, which total 40 bytes. By default, 3603 * the NIC copies 40 bytes of IP/TCP header from the 3604 * supplied header into the IP/TCP header portion of 3605 * each post-TSO-segment. If the supplied packet has IP or 3606 * TCP options, we need to tell the NIC to copy those extra 3607 * bytes into each post-TSO header, in addition to the normal 3608 * 40-byte IP/TCP header (and to leave space accordingly). 3609 * Unfortunately, the driver encoding of option length 3610 * varies across different ASIC families. 3611 */ 3612 tcp_seg_flags = 0; 3613 if (iptcp_opt_words) { 3614 if ( BGE_IS_5705_OR_BEYOND(sc)) { 3615 tcp_seg_flags = 3616 iptcp_opt_words << 11; 3617 } else { 3618 txbd_tso_flags |= 3619 iptcp_opt_words << 12; 3620 } 3621 } 3622 maxsegsize = mss | tcp_seg_flags; 3623 ip->ip_len = htons(mss + ip_tcp_hlen); 3624 3625 } /* TSO setup */ 3626 3627 /* 3628 * Start packing the mbufs in this chain into 3629 * the fragment pointers. Stop when we run out 3630 * of fragments or hit the end of the mbuf chain. 3631 */ 3632 error = bus_dmamap_load_mbuf(sc->bge_dmatag, dmamap, m_head, 3633 BUS_DMA_NOWAIT); 3634 if (error) { 3635 return(ENOBUFS); 3636 } 3637 3638 mtag = sc->ethercom.ec_nvlans ? 3639 m_tag_find(m_head, PACKET_TAG_VLAN, NULL) : NULL; 3640 3641 3642 /* Iterate over dmap-map fragments. */ 3643 for (i = 0; i < dmamap->dm_nsegs; i++) { 3644 f = &sc->bge_rdata->bge_tx_ring[frag]; 3645 if (sc->bge_cdata.bge_tx_chain[frag] != NULL) 3646 break; 3647 3648 bge_set_hostaddr(&f->bge_addr, dmamap->dm_segs[i].ds_addr); 3649 f->bge_len = dmamap->dm_segs[i].ds_len; 3650 3651 /* 3652 * For 5751 and follow-ons, for TSO we must turn 3653 * off checksum-assist flag in the tx-descr, and 3654 * supply the ASIC-revision-specific encoding 3655 * of TSO flags and segsize. 3656 */ 3657 if (use_tso) { 3658 if (BGE_IS_5750_OR_BEYOND(sc) || i == 0) { 3659 f->bge_rsvd = maxsegsize; 3660 f->bge_flags = csum_flags | txbd_tso_flags; 3661 } else { 3662 f->bge_rsvd = 0; 3663 f->bge_flags = 3664 (csum_flags | txbd_tso_flags) & 0x0fff; 3665 } 3666 } else { 3667 f->bge_rsvd = 0; 3668 f->bge_flags = csum_flags; 3669 } 3670 3671 if (mtag != NULL) { 3672 f->bge_flags |= BGE_TXBDFLAG_VLAN_TAG; 3673 f->bge_vlan_tag = VLAN_TAG_VALUE(mtag); 3674 } else { 3675 f->bge_vlan_tag = 0; 3676 } 3677 /* 3678 * Sanity check: avoid coming within 16 descriptors 3679 * of the end of the ring. 3680 */ 3681 if ((BGE_TX_RING_CNT - (sc->bge_txcnt + cnt)) < 16) { 3682 BGE_TSO_PRINTF(("%s: " 3683 " dmamap_load_mbuf too close to ring wrap\n", 3684 sc->bge_dev.dv_xname)); 3685 return(ENOBUFS); 3686 } 3687 cur = frag; 3688 BGE_INC(frag, BGE_TX_RING_CNT); 3689 cnt++; 3690 } 3691 3692 if (i < dmamap->dm_nsegs) { 3693 BGE_TSO_PRINTF(("%s: reached %d < dm_nsegs %d\n", 3694 sc->bge_dev.dv_xname, i, dmamap->dm_nsegs)); 3695 return ENOBUFS; 3696 } 3697 3698 bus_dmamap_sync(sc->bge_dmatag, dmamap, 0, dmamap->dm_mapsize, 3699 BUS_DMASYNC_PREWRITE); 3700 3701 if (frag == sc->bge_tx_saved_considx) { 3702 BGE_TSO_PRINTF(("%s: frag %d = wrapped id %d?\n", 3703 sc->bge_dev.dv_xname, frag, sc->bge_tx_saved_considx)); 3704 3705 return(ENOBUFS); 3706 } 3707 3708 sc->bge_rdata->bge_tx_ring[cur].bge_flags |= BGE_TXBDFLAG_END; 3709 sc->bge_cdata.bge_tx_chain[cur] = m_head; 3710 SLIST_REMOVE_HEAD(&sc->txdma_list, link); 3711 sc->txdma[cur] = dma; 3712 sc->bge_txcnt += cnt; 3713 3714 *txidx = frag; 3715 3716 return(0); 3717 } 3718 3719 /* 3720 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 3721 * to the mbuf data regions directly in the transmit descriptors. 3722 */ 3723 static void 3724 bge_start(struct ifnet *ifp) 3725 { 3726 struct bge_softc *sc; 3727 struct mbuf *m_head = NULL; 3728 u_int32_t prodidx; 3729 int pkts = 0; 3730 3731 sc = ifp->if_softc; 3732 3733 if (!sc->bge_link && ifp->if_snd.ifq_len < 10) 3734 return; 3735 3736 prodidx = sc->bge_tx_prodidx; 3737 3738 while(sc->bge_cdata.bge_tx_chain[prodidx] == NULL) { 3739 IFQ_POLL(&ifp->if_snd, m_head); 3740 if (m_head == NULL) 3741 break; 3742 3743 #if 0 3744 /* 3745 * XXX 3746 * safety overkill. If this is a fragmented packet chain 3747 * with delayed TCP/UDP checksums, then only encapsulate 3748 * it if we have enough descriptors to handle the entire 3749 * chain at once. 3750 * (paranoia -- may not actually be needed) 3751 */ 3752 if (m_head->m_flags & M_FIRSTFRAG && 3753 m_head->m_pkthdr.csum_flags & (CSUM_DELAY_DATA)) { 3754 if ((BGE_TX_RING_CNT - sc->bge_txcnt) < 3755 M_CSUM_DATA_IPv4_OFFSET(m_head->m_pkthdr.csum_data) + 16) { 3756 ifp->if_flags |= IFF_OACTIVE; 3757 break; 3758 } 3759 } 3760 #endif 3761 3762 /* 3763 * Pack the data into the transmit ring. If we 3764 * don't have room, set the OACTIVE flag and wait 3765 * for the NIC to drain the ring. 3766 */ 3767 if (bge_encap(sc, m_head, &prodidx)) { 3768 printf("bge: failed on len %d?\n", m_head->m_pkthdr.len); 3769 ifp->if_flags |= IFF_OACTIVE; 3770 break; 3771 } 3772 3773 /* now we are committed to transmit the packet */ 3774 IFQ_DEQUEUE(&ifp->if_snd, m_head); 3775 pkts++; 3776 3777 #if NBPFILTER > 0 3778 /* 3779 * If there's a BPF listener, bounce a copy of this frame 3780 * to him. 3781 */ 3782 if (ifp->if_bpf) 3783 bpf_mtap(ifp->if_bpf, m_head); 3784 #endif 3785 } 3786 if (pkts == 0) 3787 return; 3788 3789 /* Transmit */ 3790 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); 3791 if (sc->bge_quirks & BGE_QUIRK_PRODUCER_BUG) /* 5700 b2 errata */ 3792 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); 3793 3794 sc->bge_tx_prodidx = prodidx; 3795 3796 /* 3797 * Set a timeout in case the chip goes out to lunch. 3798 */ 3799 ifp->if_timer = 5; 3800 } 3801 3802 static int 3803 bge_init(struct ifnet *ifp) 3804 { 3805 struct bge_softc *sc = ifp->if_softc; 3806 u_int16_t *m; 3807 int s, error; 3808 3809 s = splnet(); 3810 3811 ifp = &sc->ethercom.ec_if; 3812 3813 /* Cancel pending I/O and flush buffers. */ 3814 bge_stop(sc); 3815 bge_reset(sc); 3816 bge_chipinit(sc); 3817 3818 /* 3819 * Init the various state machines, ring 3820 * control blocks and firmware. 3821 */ 3822 error = bge_blockinit(sc); 3823 if (error != 0) { 3824 printf("%s: initialization error %d\n", sc->bge_dev.dv_xname, 3825 error); 3826 splx(s); 3827 return error; 3828 } 3829 3830 ifp = &sc->ethercom.ec_if; 3831 3832 /* Specify MTU. */ 3833 CSR_WRITE_4(sc, BGE_RX_MTU, ifp->if_mtu + 3834 ETHER_HDR_LEN + ETHER_CRC_LEN + ETHER_VLAN_ENCAP_LEN); 3835 3836 /* Load our MAC address. */ 3837 m = (u_int16_t *)&(LLADDR(ifp->if_sadl)[0]); 3838 CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0])); 3839 CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, (htons(m[1]) << 16) | htons(m[2])); 3840 3841 /* Enable or disable promiscuous mode as needed. */ 3842 if (ifp->if_flags & IFF_PROMISC) { 3843 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 3844 } else { 3845 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 3846 } 3847 3848 /* Program multicast filter. */ 3849 bge_setmulti(sc); 3850 3851 /* Init RX ring. */ 3852 bge_init_rx_ring_std(sc); 3853 3854 /* Init jumbo RX ring. */ 3855 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 3856 bge_init_rx_ring_jumbo(sc); 3857 3858 /* Init our RX return ring index */ 3859 sc->bge_rx_saved_considx = 0; 3860 3861 /* Init TX ring. */ 3862 bge_init_tx_ring(sc); 3863 3864 /* Turn on transmitter */ 3865 BGE_SETBIT(sc, BGE_TX_MODE, BGE_TXMODE_ENABLE); 3866 3867 /* Turn on receiver */ 3868 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE); 3869 3870 CSR_WRITE_4(sc, BGE_MAX_RX_FRAME_LOWAT, 2); 3871 3872 /* Tell firmware we're alive. */ 3873 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 3874 3875 /* Enable host interrupts. */ 3876 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA); 3877 BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); 3878 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 0); 3879 3880 bge_ifmedia_upd(ifp); 3881 3882 ifp->if_flags |= IFF_RUNNING; 3883 ifp->if_flags &= ~IFF_OACTIVE; 3884 3885 splx(s); 3886 3887 callout_reset(&sc->bge_timeout, hz, bge_tick, sc); 3888 3889 return 0; 3890 } 3891 3892 /* 3893 * Set media options. 3894 */ 3895 static int 3896 bge_ifmedia_upd(struct ifnet *ifp) 3897 { 3898 struct bge_softc *sc = ifp->if_softc; 3899 struct mii_data *mii = &sc->bge_mii; 3900 struct ifmedia *ifm = &sc->bge_ifmedia; 3901 3902 /* If this is a 1000baseX NIC, enable the TBI port. */ 3903 if (sc->bge_tbi) { 3904 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 3905 return(EINVAL); 3906 switch(IFM_SUBTYPE(ifm->ifm_media)) { 3907 case IFM_AUTO: 3908 break; 3909 case IFM_1000_SX: 3910 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 3911 BGE_CLRBIT(sc, BGE_MAC_MODE, 3912 BGE_MACMODE_HALF_DUPLEX); 3913 } else { 3914 BGE_SETBIT(sc, BGE_MAC_MODE, 3915 BGE_MACMODE_HALF_DUPLEX); 3916 } 3917 break; 3918 default: 3919 return(EINVAL); 3920 } 3921 /* XXX 802.3x flow control for 1000BASE-SX */ 3922 return(0); 3923 } 3924 3925 sc->bge_link = 0; 3926 mii_mediachg(mii); 3927 3928 return(0); 3929 } 3930 3931 /* 3932 * Report current media status. 3933 */ 3934 static void 3935 bge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 3936 { 3937 struct bge_softc *sc = ifp->if_softc; 3938 struct mii_data *mii = &sc->bge_mii; 3939 3940 if (sc->bge_tbi) { 3941 ifmr->ifm_status = IFM_AVALID; 3942 ifmr->ifm_active = IFM_ETHER; 3943 if (CSR_READ_4(sc, BGE_MAC_STS) & 3944 BGE_MACSTAT_TBI_PCS_SYNCHED) 3945 ifmr->ifm_status |= IFM_ACTIVE; 3946 ifmr->ifm_active |= IFM_1000_SX; 3947 if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX) 3948 ifmr->ifm_active |= IFM_HDX; 3949 else 3950 ifmr->ifm_active |= IFM_FDX; 3951 return; 3952 } 3953 3954 mii_pollstat(mii); 3955 ifmr->ifm_status = mii->mii_media_status; 3956 ifmr->ifm_active = (mii->mii_media_active & ~IFM_ETH_FMASK) | 3957 sc->bge_flowflags; 3958 } 3959 3960 static int 3961 bge_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 3962 { 3963 struct bge_softc *sc = ifp->if_softc; 3964 struct ifreq *ifr = (struct ifreq *) data; 3965 int s, error = 0; 3966 struct mii_data *mii; 3967 3968 s = splnet(); 3969 3970 switch(command) { 3971 case SIOCSIFFLAGS: 3972 if (ifp->if_flags & IFF_UP) { 3973 /* 3974 * If only the state of the PROMISC flag changed, 3975 * then just use the 'set promisc mode' command 3976 * instead of reinitializing the entire NIC. Doing 3977 * a full re-init means reloading the firmware and 3978 * waiting for it to start up, which may take a 3979 * second or two. 3980 */ 3981 if (ifp->if_flags & IFF_RUNNING && 3982 ifp->if_flags & IFF_PROMISC && 3983 !(sc->bge_if_flags & IFF_PROMISC)) { 3984 BGE_SETBIT(sc, BGE_RX_MODE, 3985 BGE_RXMODE_RX_PROMISC); 3986 } else if (ifp->if_flags & IFF_RUNNING && 3987 !(ifp->if_flags & IFF_PROMISC) && 3988 sc->bge_if_flags & IFF_PROMISC) { 3989 BGE_CLRBIT(sc, BGE_RX_MODE, 3990 BGE_RXMODE_RX_PROMISC); 3991 } else if (!(sc->bge_if_flags & IFF_UP)) 3992 bge_init(ifp); 3993 } else { 3994 if (ifp->if_flags & IFF_RUNNING) { 3995 bge_stop(sc); 3996 } 3997 } 3998 sc->bge_if_flags = ifp->if_flags; 3999 error = 0; 4000 break; 4001 case SIOCSIFMEDIA: 4002 /* XXX Flow control is not supported for 1000BASE-SX */ 4003 if (sc->bge_tbi) { 4004 ifr->ifr_media &= ~IFM_ETH_FMASK; 4005 sc->bge_flowflags = 0; 4006 } 4007 4008 /* Flow control requires full-duplex mode. */ 4009 if (IFM_SUBTYPE(ifr->ifr_media) == IFM_AUTO || 4010 (ifr->ifr_media & IFM_FDX) == 0) { 4011 ifr->ifr_media &= ~IFM_ETH_FMASK; 4012 } 4013 if (IFM_SUBTYPE(ifr->ifr_media) != IFM_AUTO) { 4014 if ((ifr->ifr_media & IFM_ETH_FMASK) == IFM_FLOW) { 4015 /* We an do both TXPAUSE and RXPAUSE. */ 4016 ifr->ifr_media |= 4017 IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE; 4018 } 4019 sc->bge_flowflags = ifr->ifr_media & IFM_ETH_FMASK; 4020 } 4021 /* FALLTHROUGH */ 4022 case SIOCGIFMEDIA: 4023 if (sc->bge_tbi) { 4024 error = ifmedia_ioctl(ifp, ifr, &sc->bge_ifmedia, 4025 command); 4026 } else { 4027 mii = &sc->bge_mii; 4028 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, 4029 command); 4030 } 4031 break; 4032 default: 4033 error = ether_ioctl(ifp, command, data); 4034 if (error == ENETRESET) { 4035 if (ifp->if_flags & IFF_RUNNING) 4036 bge_setmulti(sc); 4037 error = 0; 4038 } 4039 break; 4040 } 4041 4042 splx(s); 4043 4044 return(error); 4045 } 4046 4047 static void 4048 bge_watchdog(struct ifnet *ifp) 4049 { 4050 struct bge_softc *sc; 4051 4052 sc = ifp->if_softc; 4053 4054 printf("%s: watchdog timeout -- resetting\n", sc->bge_dev.dv_xname); 4055 4056 ifp->if_flags &= ~IFF_RUNNING; 4057 bge_init(ifp); 4058 4059 ifp->if_oerrors++; 4060 } 4061 4062 static void 4063 bge_stop_block(struct bge_softc *sc, bus_addr_t reg, uint32_t bit) 4064 { 4065 int i; 4066 4067 BGE_CLRBIT(sc, reg, bit); 4068 4069 for (i = 0; i < BGE_TIMEOUT; i++) { 4070 if ((CSR_READ_4(sc, reg) & bit) == 0) 4071 return; 4072 delay(100); 4073 if (sc->bge_pcie) 4074 DELAY(1000); 4075 } 4076 4077 printf("%s: block failed to stop: reg 0x%lx, bit 0x%08x\n", 4078 sc->bge_dev.dv_xname, (u_long) reg, bit); 4079 } 4080 4081 /* 4082 * Stop the adapter and free any mbufs allocated to the 4083 * RX and TX lists. 4084 */ 4085 static void 4086 bge_stop(struct bge_softc *sc) 4087 { 4088 struct ifnet *ifp = &sc->ethercom.ec_if; 4089 4090 callout_stop(&sc->bge_timeout); 4091 4092 /* 4093 * Disable all of the receiver blocks 4094 */ 4095 bge_stop_block(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE); 4096 bge_stop_block(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 4097 bge_stop_block(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 4098 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 4099 bge_stop_block(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 4100 } 4101 bge_stop_block(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE); 4102 bge_stop_block(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 4103 bge_stop_block(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE); 4104 4105 /* 4106 * Disable all of the transmit blocks 4107 */ 4108 bge_stop_block(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 4109 bge_stop_block(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 4110 bge_stop_block(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 4111 bge_stop_block(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE); 4112 bge_stop_block(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE); 4113 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 4114 bge_stop_block(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 4115 } 4116 bge_stop_block(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 4117 4118 /* 4119 * Shut down all of the memory managers and related 4120 * state machines. 4121 */ 4122 bge_stop_block(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE); 4123 bge_stop_block(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE); 4124 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 4125 bge_stop_block(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 4126 } 4127 4128 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 4129 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 4130 4131 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 4132 bge_stop_block(sc, BGE_BMAN_MODE, BGE_BMANMODE_ENABLE); 4133 bge_stop_block(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 4134 } 4135 4136 /* Disable host interrupts. */ 4137 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); 4138 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 1); 4139 4140 /* 4141 * Tell firmware we're shutting down. 4142 */ 4143 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 4144 4145 /* Free the RX lists. */ 4146 bge_free_rx_ring_std(sc); 4147 4148 /* Free jumbo RX list. */ 4149 bge_free_rx_ring_jumbo(sc); 4150 4151 /* Free TX buffers. */ 4152 bge_free_tx_ring(sc); 4153 4154 /* 4155 * Isolate/power down the PHY. 4156 */ 4157 if (!sc->bge_tbi) 4158 mii_down(&sc->bge_mii); 4159 4160 sc->bge_link = 0; 4161 4162 sc->bge_tx_saved_considx = BGE_TXCONS_UNSET; 4163 4164 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 4165 } 4166 4167 /* 4168 * Stop all chip I/O so that the kernel's probe routines don't 4169 * get confused by errant DMAs when rebooting. 4170 */ 4171 static void 4172 bge_shutdown(void *xsc) 4173 { 4174 struct bge_softc *sc = (struct bge_softc *)xsc; 4175 4176 bge_stop(sc); 4177 bge_reset(sc); 4178 } 4179 4180 4181 static int 4182 sysctl_bge_verify(SYSCTLFN_ARGS) 4183 { 4184 int error, t; 4185 struct sysctlnode node; 4186 4187 node = *rnode; 4188 t = *(int*)rnode->sysctl_data; 4189 node.sysctl_data = &t; 4190 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 4191 if (error || newp == NULL) 4192 return (error); 4193 4194 #if 0 4195 DPRINTF2(("%s: t = %d, nodenum = %d, rnodenum = %d\n", __func__, t, 4196 node.sysctl_num, rnode->sysctl_num)); 4197 #endif 4198 4199 if (node.sysctl_num == bge_rxthresh_nodenum) { 4200 if (t < 0 || t >= NBGE_RX_THRESH) 4201 return (EINVAL); 4202 bge_update_all_threshes(t); 4203 } else 4204 return (EINVAL); 4205 4206 *(int*)rnode->sysctl_data = t; 4207 4208 return (0); 4209 } 4210 4211 /* 4212 * Set up sysctl(3) MIB, hw.bge.*. 4213 * 4214 * TBD condition SYSCTL_PERMANENT on being an LKM or not 4215 */ 4216 SYSCTL_SETUP(sysctl_bge, "sysctl bge subtree setup") 4217 { 4218 int rc, bge_root_num; 4219 const struct sysctlnode *node; 4220 4221 if ((rc = sysctl_createv(clog, 0, NULL, NULL, 4222 CTLFLAG_PERMANENT, CTLTYPE_NODE, "hw", NULL, 4223 NULL, 0, NULL, 0, CTL_HW, CTL_EOL)) != 0) { 4224 goto err; 4225 } 4226 4227 if ((rc = sysctl_createv(clog, 0, NULL, &node, 4228 CTLFLAG_PERMANENT, CTLTYPE_NODE, "bge", 4229 SYSCTL_DESCR("BGE interface controls"), 4230 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL)) != 0) { 4231 goto err; 4232 } 4233 4234 bge_root_num = node->sysctl_num; 4235 4236 /* BGE Rx interrupt mitigation level */ 4237 if ((rc = sysctl_createv(clog, 0, NULL, &node, 4238 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, 4239 CTLTYPE_INT, "rx_lvl", 4240 SYSCTL_DESCR("BGE receive interrupt mitigation level"), 4241 sysctl_bge_verify, 0, 4242 &bge_rx_thresh_lvl, 4243 0, CTL_HW, bge_root_num, CTL_CREATE, 4244 CTL_EOL)) != 0) { 4245 goto err; 4246 } 4247 4248 bge_rxthresh_nodenum = node->sysctl_num; 4249 4250 return; 4251 4252 err: 4253 printf("%s: sysctl_createv failed (rc = %d)\n", __func__, rc); 4254 } 4255 4256 static void 4257 bge_powerhook(int why, void *hdl) 4258 { 4259 struct bge_softc *sc = (struct bge_softc *)hdl; 4260 struct ifnet *ifp = &sc->ethercom.ec_if; 4261 struct pci_attach_args *pa = &(sc->bge_pa); 4262 pci_chipset_tag_t pc = pa->pa_pc; 4263 pcitag_t tag = pa->pa_tag; 4264 4265 switch (why) { 4266 case PWR_SOFTSUSPEND: 4267 case PWR_SOFTSTANDBY: 4268 bge_shutdown(sc); 4269 break; 4270 case PWR_SOFTRESUME: 4271 if (ifp->if_flags & IFF_UP) { 4272 ifp->if_flags &= ~IFF_RUNNING; 4273 bge_init(ifp); 4274 } 4275 break; 4276 case PWR_SUSPEND: 4277 case PWR_STANDBY: 4278 pci_conf_capture(pc, tag, &sc->bge_pciconf); 4279 break; 4280 case PWR_RESUME: 4281 pci_conf_restore(pc, tag, &sc->bge_pciconf); 4282 break; 4283 } 4284 4285 return; 4286 } 4287
Indexes created Tue Sep 23 07:09:52 GMT 2025