if_bge.c revision 1.12
1 /* $NetBSD: if_bge.c,v 1.12 2002/06/28 18:46:46 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 2001 Wind River Systems 5 * Copyright (c) 1997, 1998, 1999, 2001 6 * Bill Paul <wpaul (at) windriver.com>. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Bill Paul. 19 * 4. Neither the name of the author nor the names of any co-contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 33 * THE POSSIBILITY OF SUCH DAMAGE. 34 * 35 * $FreeBSD: if_bge.c,v 1.13 2002/04/04 06:01:31 wpaul Exp $ 36 */ 37 38 /* 39 * Broadcom BCM570x family gigabit ethernet driver for NetBSD. 40 * 41 * NetBSD version by: 42 * 43 * Frank van der Linden <fvdl (at) wasabisystems.com> 44 * Jason Thorpe <thorpej (at) wasabisystems.com> 45 * 46 * Originally written for FreeBSD by Bill Paul <wpaul (at) windriver.com> 47 * Senior Engineer, Wind River Systems 48 */ 49 50 /* 51 * The Broadcom BCM5700 is based on technology originally developed by 52 * Alteon Networks as part of the Tigon I and Tigon II gigabit ethernet 53 * MAC chips. The BCM5700, sometimes refered to as the Tigon III, has 54 * two on-board MIPS R4000 CPUs and can have as much as 16MB of external 55 * SSRAM. The BCM5700 supports TCP, UDP and IP checksum offload, jumbo 56 * frames, highly configurable RX filtering, and 16 RX and TX queues 57 * (which, along with RX filter rules, can be used for QOS applications). 58 * Other features, such as TCP segmentation, may be available as part 59 * of value-added firmware updates. Unlike the Tigon I and Tigon II, 60 * firmware images can be stored in hardware and need not be compiled 61 * into the driver. 62 * 63 * The BCM5700 supports the PCI v2.2 and PCI-X v1.0 standards, and will 64 * function in a 32-bit/64-bit 33/66Mhz bus, or a 64-bit/133Mhz bus. 65 * 66 * The BCM5701 is a single-chip solution incorporating both the BCM5700 67 * MAC and a BCM5401 10/100/1000 PHY. Unlike the BCM5700, the BCM5700 68 * does not support external SSRAM. 69 * 70 * Broadcom also produces a variation of the BCM5700 under the "Altima" 71 * brand name, which is functionally similar but lacks PCI-X support. 72 * 73 * Without external SSRAM, you can only have at most 4 TX rings, 74 * and the use of the mini RX ring is disabled. This seems to imply 75 * that these features are simply not available on the BCM5701. As a 76 * result, this driver does not implement any support for the mini RX 77 * ring. 78 */ 79 80 #include "bpfilter.h" 81 #include "vlan.h" 82 83 #include <sys/param.h> 84 #include <sys/systm.h> 85 #include <sys/callout.h> 86 #include <sys/sockio.h> 87 #include <sys/mbuf.h> 88 #include <sys/malloc.h> 89 #include <sys/kernel.h> 90 #include <sys/device.h> 91 #include <sys/socket.h> 92 93 #include <net/if.h> 94 #include <net/if_dl.h> 95 #include <net/if_media.h> 96 #include <net/if_ether.h> 97 98 #ifdef INET 99 #include <netinet/in.h> 100 #include <netinet/in_systm.h> 101 #include <netinet/in_var.h> 102 #include <netinet/ip.h> 103 #endif 104 105 #if NBPFILTER > 0 106 #include <net/bpf.h> 107 #endif 108 109 #include <dev/pci/pcireg.h> 110 #include <dev/pci/pcivar.h> 111 #include <dev/pci/pcidevs.h> 112 113 #include <dev/mii/mii.h> 114 #include <dev/mii/miivar.h> 115 #include <dev/mii/miidevs.h> 116 #include <dev/mii/brgphyreg.h> 117 118 #include <dev/pci/if_bgereg.h> 119 120 #include <uvm/uvm_extern.h> 121 122 /* #define BGE_CHECKSUM */ 123 124 int bge_probe(struct device *, struct cfdata *, void *); 125 void bge_attach(struct device *, struct device *, void *); 126 void bge_release_resources(struct bge_softc *); 127 void bge_txeof(struct bge_softc *); 128 void bge_rxeof(struct bge_softc *); 129 130 void bge_tick(void *); 131 void bge_stats_update(struct bge_softc *); 132 int bge_encap(struct bge_softc *, struct mbuf *, u_int32_t *); 133 134 int bge_intr(void *); 135 void bge_start(struct ifnet *); 136 int bge_ioctl(struct ifnet *, u_long, caddr_t); 137 int bge_init(struct ifnet *); 138 void bge_stop(struct bge_softc *); 139 void bge_watchdog(struct ifnet *); 140 void bge_shutdown(void *); 141 int bge_ifmedia_upd(struct ifnet *); 142 void bge_ifmedia_sts(struct ifnet *, struct ifmediareq *); 143 144 u_int8_t bge_eeprom_getbyte(struct bge_softc *, int, u_int8_t *); 145 int bge_read_eeprom(struct bge_softc *, caddr_t, int, int); 146 147 u_int32_t bge_crc(struct bge_softc *, caddr_t); 148 void bge_setmulti(struct bge_softc *); 149 150 void bge_handle_events(struct bge_softc *); 151 int bge_alloc_jumbo_mem(struct bge_softc *); 152 void bge_free_jumbo_mem(struct bge_softc *); 153 void *bge_jalloc(struct bge_softc *); 154 void bge_jfree(struct mbuf *, caddr_t, u_int, void *); 155 int bge_newbuf_std(struct bge_softc *, int, struct mbuf *, bus_dmamap_t); 156 int bge_newbuf_jumbo(struct bge_softc *, int, struct mbuf *); 157 int bge_init_rx_ring_std(struct bge_softc *); 158 void bge_free_rx_ring_std(struct bge_softc *); 159 int bge_init_rx_ring_jumbo(struct bge_softc *); 160 void bge_free_rx_ring_jumbo(struct bge_softc *); 161 void bge_free_tx_ring(struct bge_softc *); 162 int bge_init_tx_ring(struct bge_softc *); 163 164 int bge_chipinit(struct bge_softc *); 165 int bge_blockinit(struct bge_softc *); 166 167 #ifdef notdef 168 u_int8_t bge_vpd_readbyte(struct bge_softc *, int); 169 void bge_vpd_read_res(struct bge_softc *, struct vpd_res *, int); 170 void bge_vpd_read(struct bge_softc *); 171 #endif 172 173 u_int32_t bge_readmem_ind(struct bge_softc *, int); 174 void bge_writemem_ind(struct bge_softc *, int, int); 175 #ifdef notdef 176 u_int32_t bge_readreg_ind(struct bge_softc *, int); 177 #endif 178 void bge_writereg_ind(struct bge_softc *, int, int); 179 180 int bge_miibus_readreg(struct device *, int, int); 181 void bge_miibus_writereg(struct device *, int, int, int); 182 void bge_miibus_statchg(struct device *); 183 184 void bge_reset(struct bge_softc *); 185 void bge_phy_hack(struct bge_softc *); 186 187 void bge_dump_status(struct bge_softc *); 188 void bge_dump_rxbd(struct bge_rx_bd *); 189 190 #define BGE_DEBUG 191 #ifdef BGE_DEBUG 192 #define DPRINTF(x) if (bgedebug) printf x 193 #define DPRINTFN(n,x) if (bgedebug >= (n)) printf x 194 int bgedebug = 0; 195 #else 196 #define DPRINTF(x) 197 #define DPRINTFN(n,x) 198 #endif 199 200 struct cfattach bge_ca = { 201 sizeof(struct bge_softc), bge_probe, bge_attach 202 }; 203 204 u_int32_t 205 bge_readmem_ind(sc, off) 206 struct bge_softc *sc; 207 int off; 208 { 209 struct pci_attach_args *pa = &(sc->bge_pa); 210 pcireg_t val; 211 212 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_MEMWIN_BASEADDR, off); 213 val = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_MEMWIN_DATA); 214 return val; 215 } 216 217 void 218 bge_writemem_ind(sc, off, val) 219 struct bge_softc *sc; 220 int off, val; 221 { 222 struct pci_attach_args *pa = &(sc->bge_pa); 223 224 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_MEMWIN_BASEADDR, off); 225 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_MEMWIN_DATA, val); 226 } 227 228 #ifdef notdef 229 u_int32_t 230 bge_readreg_ind(sc, off) 231 struct bge_softc *sc; 232 int off; 233 { 234 struct pci_attach_args *pa = &(sc->bge_pa); 235 236 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_REG_BASEADDR, off); 237 return(pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_REG_DATA)); 238 } 239 #endif 240 241 void 242 bge_writereg_ind(sc, off, val) 243 struct bge_softc *sc; 244 int off, val; 245 { 246 struct pci_attach_args *pa = &(sc->bge_pa); 247 248 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_REG_BASEADDR, off); 249 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_REG_DATA, val); 250 } 251 252 #ifdef notdef 253 u_int8_t 254 bge_vpd_readbyte(sc, addr) 255 struct bge_softc *sc; 256 int addr; 257 { 258 int i; 259 u_int32_t val; 260 struct pci_attach_args *pa = &(sc->bge_pa); 261 262 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_VPD_ADDR, addr); 263 for (i = 0; i < BGE_TIMEOUT * 10; i++) { 264 DELAY(10); 265 if (pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_VPD_ADDR) & 266 BGE_VPD_FLAG) 267 break; 268 } 269 270 if (i == BGE_TIMEOUT) { 271 printf("%s: VPD read timed out\n", sc->bge_dev.dv_xname); 272 return(0); 273 } 274 275 val = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_VPD_DATA); 276 277 return((val >> ((addr % 4) * 8)) & 0xFF); 278 } 279 280 void 281 bge_vpd_read_res(sc, res, addr) 282 struct bge_softc *sc; 283 struct vpd_res *res; 284 int addr; 285 { 286 int i; 287 u_int8_t *ptr; 288 289 ptr = (u_int8_t *)res; 290 for (i = 0; i < sizeof(struct vpd_res); i++) 291 ptr[i] = bge_vpd_readbyte(sc, i + addr); 292 } 293 294 void 295 bge_vpd_read(sc) 296 struct bge_softc *sc; 297 { 298 int pos = 0, i; 299 struct vpd_res res; 300 301 if (sc->bge_vpd_prodname != NULL) 302 free(sc->bge_vpd_prodname, M_DEVBUF); 303 if (sc->bge_vpd_readonly != NULL) 304 free(sc->bge_vpd_readonly, M_DEVBUF); 305 sc->bge_vpd_prodname = NULL; 306 sc->bge_vpd_readonly = NULL; 307 308 bge_vpd_read_res(sc, &res, pos); 309 310 if (res.vr_id != VPD_RES_ID) { 311 printf("%s: bad VPD resource id: expected %x got %x\n", 312 sc->bge_dev.dv_xname, VPD_RES_ID, res.vr_id); 313 return; 314 } 315 316 pos += sizeof(res); 317 sc->bge_vpd_prodname = malloc(res.vr_len + 1, M_DEVBUF, M_NOWAIT); 318 if (sc->bge_vpd_prodname == NULL) 319 panic("bge_vpd_read"); 320 for (i = 0; i < res.vr_len; i++) 321 sc->bge_vpd_prodname[i] = bge_vpd_readbyte(sc, i + pos); 322 sc->bge_vpd_prodname[i] = '\0'; 323 pos += i; 324 325 bge_vpd_read_res(sc, &res, pos); 326 327 if (res.vr_id != VPD_RES_READ) { 328 printf("%s: bad VPD resource id: expected %x got %x\n", 329 sc->bge_dev.dv_xname, VPD_RES_READ, res.vr_id); 330 return; 331 } 332 333 pos += sizeof(res); 334 sc->bge_vpd_readonly = malloc(res.vr_len, M_DEVBUF, M_NOWAIT); 335 if (sc->bge_vpd_readonly == NULL) 336 panic("bge_vpd_read"); 337 for (i = 0; i < res.vr_len + 1; i++) 338 sc->bge_vpd_readonly[i] = bge_vpd_readbyte(sc, i + pos); 339 } 340 #endif 341 342 /* 343 * Read a byte of data stored in the EEPROM at address 'addr.' The 344 * BCM570x supports both the traditional bitbang interface and an 345 * auto access interface for reading the EEPROM. We use the auto 346 * access method. 347 */ 348 u_int8_t 349 bge_eeprom_getbyte(sc, addr, dest) 350 struct bge_softc *sc; 351 int addr; 352 u_int8_t *dest; 353 { 354 int i; 355 u_int32_t byte = 0; 356 357 /* 358 * Enable use of auto EEPROM access so we can avoid 359 * having to use the bitbang method. 360 */ 361 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM); 362 363 /* Reset the EEPROM, load the clock period. */ 364 CSR_WRITE_4(sc, BGE_EE_ADDR, 365 BGE_EEADDR_RESET|BGE_EEHALFCLK(BGE_HALFCLK_384SCL)); 366 DELAY(20); 367 368 /* Issue the read EEPROM command. */ 369 CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr); 370 371 /* Wait for completion */ 372 for(i = 0; i < BGE_TIMEOUT * 10; i++) { 373 DELAY(10); 374 if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE) 375 break; 376 } 377 378 if (i == BGE_TIMEOUT) { 379 printf("%s: eeprom read timed out\n", sc->bge_dev.dv_xname); 380 return(0); 381 } 382 383 /* Get result. */ 384 byte = CSR_READ_4(sc, BGE_EE_DATA); 385 386 *dest = (byte >> ((addr % 4) * 8)) & 0xFF; 387 388 return(0); 389 } 390 391 /* 392 * Read a sequence of bytes from the EEPROM. 393 */ 394 int 395 bge_read_eeprom(sc, dest, off, cnt) 396 struct bge_softc *sc; 397 caddr_t dest; 398 int off; 399 int cnt; 400 { 401 int err = 0, i; 402 u_int8_t byte = 0; 403 404 for (i = 0; i < cnt; i++) { 405 err = bge_eeprom_getbyte(sc, off + i, &byte); 406 if (err) 407 break; 408 *(dest + i) = byte; 409 } 410 411 return(err ? 1 : 0); 412 } 413 414 int 415 bge_miibus_readreg(dev, phy, reg) 416 struct device *dev; 417 int phy, reg; 418 { 419 struct bge_softc *sc = (struct bge_softc *)dev; 420 struct ifnet *ifp; 421 u_int32_t val; 422 int i; 423 424 ifp = &sc->ethercom.ec_if; 425 426 if (sc->bge_asicrev == BGE_ASICREV_BCM5701_B5 && phy != 1) 427 return(0); 428 429 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_READ|BGE_MICOMM_BUSY| 430 BGE_MIPHY(phy)|BGE_MIREG(reg)); 431 432 for (i = 0; i < BGE_TIMEOUT; i++) { 433 val = CSR_READ_4(sc, BGE_MI_COMM); 434 if (!(val & BGE_MICOMM_BUSY)) 435 break; 436 delay(10); 437 } 438 439 if (i == BGE_TIMEOUT) { 440 printf("%s: PHY read timed out\n", sc->bge_dev.dv_xname); 441 return(0); 442 } 443 444 val = CSR_READ_4(sc, BGE_MI_COMM); 445 446 if (val & BGE_MICOMM_READFAIL) 447 return(0); 448 449 return(val & 0xFFFF); 450 } 451 452 void 453 bge_miibus_writereg(dev, phy, reg, val) 454 struct device *dev; 455 int phy, reg, val; 456 { 457 struct bge_softc *sc = (struct bge_softc *)dev; 458 int i; 459 460 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_WRITE|BGE_MICOMM_BUSY| 461 BGE_MIPHY(phy)|BGE_MIREG(reg)|val); 462 463 for (i = 0; i < BGE_TIMEOUT; i++) { 464 if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY)) 465 break; 466 delay(10); 467 } 468 469 if (i == BGE_TIMEOUT) { 470 printf("%s: PHY read timed out\n", sc->bge_dev.dv_xname); 471 } 472 } 473 474 void 475 bge_miibus_statchg(dev) 476 struct device *dev; 477 { 478 struct bge_softc *sc = (struct bge_softc *)dev; 479 struct mii_data *mii = &sc->bge_mii; 480 481 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_PORTMODE); 482 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) { 483 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_GMII); 484 } else { 485 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_MII); 486 } 487 488 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 489 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX); 490 } else { 491 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX); 492 } 493 494 bge_phy_hack(sc); 495 } 496 497 /* 498 * Handle events that have triggered interrupts. 499 */ 500 void 501 bge_handle_events(sc) 502 struct bge_softc *sc; 503 { 504 505 return; 506 } 507 508 /* 509 * Memory management for jumbo frames. 510 */ 511 512 int 513 bge_alloc_jumbo_mem(sc) 514 struct bge_softc *sc; 515 { 516 caddr_t ptr, kva; 517 bus_dma_segment_t seg; 518 int i, rseg, state, error; 519 struct bge_jpool_entry *entry; 520 521 state = error = 0; 522 523 /* Grab a big chunk o' storage. */ 524 if (bus_dmamem_alloc(sc->bge_dmatag, BGE_JMEM, PAGE_SIZE, 0, 525 &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 526 printf("%s: can't alloc rx buffers\n", sc->bge_dev.dv_xname); 527 return ENOBUFS; 528 } 529 530 state = 1; 531 if (bus_dmamem_map(sc->bge_dmatag, &seg, rseg, BGE_JMEM, &kva, 532 BUS_DMA_NOWAIT)) { 533 printf("%s: can't map dma buffers (%d bytes)\n", 534 sc->bge_dev.dv_xname, (int)BGE_JMEM); 535 error = ENOBUFS; 536 goto out; 537 } 538 539 state = 2; 540 if (bus_dmamap_create(sc->bge_dmatag, BGE_JMEM, 1, BGE_JMEM, 0, 541 BUS_DMA_NOWAIT, &sc->bge_cdata.bge_rx_jumbo_map)) { 542 printf("%s: can't create dma map\n", sc->bge_dev.dv_xname); 543 error = ENOBUFS; 544 goto out; 545 } 546 547 state = 3; 548 if (bus_dmamap_load(sc->bge_dmatag, sc->bge_cdata.bge_rx_jumbo_map, 549 kva, BGE_JMEM, NULL, BUS_DMA_NOWAIT)) { 550 printf("%s: can't load dma map\n", sc->bge_dev.dv_xname); 551 error = ENOBUFS; 552 goto out; 553 } 554 555 state = 4; 556 sc->bge_cdata.bge_jumbo_buf = (caddr_t)kva; 557 DPRINTFN(1,("bge_jumbo_buf = 0x%p\n", sc->bge_cdata.bge_jumbo_buf)); 558 559 SLIST_INIT(&sc->bge_jfree_listhead); 560 SLIST_INIT(&sc->bge_jinuse_listhead); 561 562 /* 563 * Now divide it up into 9K pieces and save the addresses 564 * in an array. 565 */ 566 ptr = sc->bge_cdata.bge_jumbo_buf; 567 for (i = 0; i < BGE_JSLOTS; i++) { 568 sc->bge_cdata.bge_jslots[i] = ptr; 569 ptr += BGE_JLEN; 570 entry = malloc(sizeof(struct bge_jpool_entry), 571 M_DEVBUF, M_NOWAIT); 572 if (entry == NULL) { 573 printf("%s: no memory for jumbo buffer queue!\n", 574 sc->bge_dev.dv_xname); 575 error = ENOBUFS; 576 goto out; 577 } 578 entry->slot = i; 579 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, 580 entry, jpool_entries); 581 } 582 out: 583 if (error != 0) { 584 switch (state) { 585 case 4: 586 bus_dmamap_unload(sc->bge_dmatag, 587 sc->bge_cdata.bge_rx_jumbo_map); 588 case 3: 589 bus_dmamap_destroy(sc->bge_dmatag, 590 sc->bge_cdata.bge_rx_jumbo_map); 591 case 2: 592 bus_dmamem_unmap(sc->bge_dmatag, kva, BGE_JMEM); 593 case 1: 594 bus_dmamem_free(sc->bge_dmatag, &seg, rseg); 595 break; 596 default: 597 break; 598 } 599 } 600 601 return error; 602 } 603 604 /* 605 * Allocate a jumbo buffer. 606 */ 607 void * 608 bge_jalloc(sc) 609 struct bge_softc *sc; 610 { 611 struct bge_jpool_entry *entry; 612 613 entry = SLIST_FIRST(&sc->bge_jfree_listhead); 614 615 if (entry == NULL) { 616 printf("%s: no free jumbo buffers\n", sc->bge_dev.dv_xname); 617 return(NULL); 618 } 619 620 SLIST_REMOVE_HEAD(&sc->bge_jfree_listhead, jpool_entries); 621 SLIST_INSERT_HEAD(&sc->bge_jinuse_listhead, entry, jpool_entries); 622 return(sc->bge_cdata.bge_jslots[entry->slot]); 623 } 624 625 /* 626 * Release a jumbo buffer. 627 */ 628 void 629 bge_jfree(m, buf, size, arg) 630 struct mbuf *m; 631 caddr_t buf; 632 u_int size; 633 void *arg; 634 { 635 struct bge_jpool_entry *entry; 636 struct bge_softc *sc; 637 int i, s; 638 639 /* Extract the softc struct pointer. */ 640 sc = (struct bge_softc *)arg; 641 642 if (sc == NULL) 643 panic("bge_jfree: can't find softc pointer!"); 644 645 /* calculate the slot this buffer belongs to */ 646 647 i = ((caddr_t)buf 648 - (caddr_t)sc->bge_cdata.bge_jumbo_buf) / BGE_JLEN; 649 650 if ((i < 0) || (i >= BGE_JSLOTS)) 651 panic("bge_jfree: asked to free buffer that we don't manage!"); 652 653 s = splvm(); 654 entry = SLIST_FIRST(&sc->bge_jinuse_listhead); 655 if (entry == NULL) 656 panic("bge_jfree: buffer not in use!"); 657 entry->slot = i; 658 SLIST_REMOVE_HEAD(&sc->bge_jinuse_listhead, jpool_entries); 659 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, entry, jpool_entries); 660 661 if (__predict_true(m != NULL)) 662 pool_cache_put(&mbpool_cache, m); 663 splx(s); 664 } 665 666 667 /* 668 * Intialize a standard receive ring descriptor. 669 */ 670 int 671 bge_newbuf_std(sc, i, m, dmamap) 672 struct bge_softc *sc; 673 int i; 674 struct mbuf *m; 675 bus_dmamap_t dmamap; 676 { 677 struct mbuf *m_new = NULL; 678 struct bge_rx_bd *r; 679 int error; 680 681 if (dmamap == NULL) { 682 error = bus_dmamap_create(sc->bge_dmatag, MCLBYTES, 1, 683 MCLBYTES, 0, BUS_DMA_NOWAIT, &dmamap); 684 if (error != 0) 685 return error; 686 } 687 688 sc->bge_cdata.bge_rx_std_map[i] = dmamap; 689 690 if (m == NULL) { 691 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 692 if (m_new == NULL) { 693 return(ENOBUFS); 694 } 695 696 MCLGET(m_new, M_DONTWAIT); 697 if (!(m_new->m_flags & M_EXT)) { 698 m_freem(m_new); 699 return(ENOBUFS); 700 } 701 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 702 m_adj(m_new, ETHER_ALIGN); 703 704 if (bus_dmamap_load_mbuf(sc->bge_dmatag, dmamap, m_new, 705 BUS_DMA_READ|BUS_DMA_NOWAIT)) 706 return(ENOBUFS); 707 } else { 708 m_new = m; 709 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 710 m_new->m_data = m_new->m_ext.ext_buf; 711 m_adj(m_new, ETHER_ALIGN); 712 } 713 714 sc->bge_cdata.bge_rx_std_chain[i] = m_new; 715 r = &sc->bge_rdata->bge_rx_std_ring[i]; 716 bge_set_hostaddr(&r->bge_addr, 717 dmamap->dm_segs[0].ds_addr); 718 r->bge_flags = BGE_RXBDFLAG_END; 719 r->bge_len = m_new->m_len; 720 r->bge_idx = i; 721 722 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 723 offsetof(struct bge_ring_data, bge_rx_std_ring) + 724 i * sizeof (struct bge_rx_bd), 725 sizeof (struct bge_rx_bd), 726 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 727 728 return(0); 729 } 730 731 /* 732 * Initialize a jumbo receive ring descriptor. This allocates 733 * a jumbo buffer from the pool managed internally by the driver. 734 */ 735 int 736 bge_newbuf_jumbo(sc, i, m) 737 struct bge_softc *sc; 738 int i; 739 struct mbuf *m; 740 { 741 struct mbuf *m_new = NULL; 742 struct bge_rx_bd *r; 743 744 if (m == NULL) { 745 caddr_t *buf = NULL; 746 747 /* Allocate the mbuf. */ 748 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 749 if (m_new == NULL) { 750 return(ENOBUFS); 751 } 752 753 /* Allocate the jumbo buffer */ 754 buf = bge_jalloc(sc); 755 if (buf == NULL) { 756 m_freem(m_new); 757 printf("%s: jumbo allocation failed " 758 "-- packet dropped!\n", sc->bge_dev.dv_xname); 759 return(ENOBUFS); 760 } 761 762 /* Attach the buffer to the mbuf. */ 763 m_new->m_len = m_new->m_pkthdr.len = BGE_JUMBO_FRAMELEN; 764 MEXTADD(m_new, buf, BGE_JUMBO_FRAMELEN, M_DEVBUF, 765 bge_jfree, sc); 766 } else { 767 m_new = m; 768 m_new->m_data = m_new->m_ext.ext_buf; 769 m_new->m_ext.ext_size = BGE_JUMBO_FRAMELEN; 770 } 771 772 m_adj(m_new, ETHER_ALIGN); 773 /* Set up the descriptor. */ 774 r = &sc->bge_rdata->bge_rx_jumbo_ring[i]; 775 sc->bge_cdata.bge_rx_jumbo_chain[i] = m_new; 776 bge_set_hostaddr(&r->bge_addr, BGE_JUMBO_DMA_ADDR(sc, m_new)); 777 r->bge_flags = BGE_RXBDFLAG_END|BGE_RXBDFLAG_JUMBO_RING; 778 r->bge_len = m_new->m_len; 779 r->bge_idx = i; 780 781 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 782 offsetof(struct bge_ring_data, bge_rx_jumbo_ring) + 783 i * sizeof (struct bge_rx_bd), 784 sizeof (struct bge_rx_bd), 785 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 786 787 return(0); 788 } 789 790 /* 791 * The standard receive ring has 512 entries in it. At 2K per mbuf cluster, 792 * that's 1MB or memory, which is a lot. For now, we fill only the first 793 * 256 ring entries and hope that our CPU is fast enough to keep up with 794 * the NIC. 795 */ 796 int 797 bge_init_rx_ring_std(sc) 798 struct bge_softc *sc; 799 { 800 int i; 801 802 if (sc->bge_flags & BGE_RXRING_VALID) 803 return 0; 804 805 for (i = 0; i < BGE_SSLOTS; i++) { 806 if (bge_newbuf_std(sc, i, NULL, 0) == ENOBUFS) 807 return(ENOBUFS); 808 } 809 810 sc->bge_std = i - 1; 811 CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std); 812 813 sc->bge_flags |= BGE_RXRING_VALID; 814 815 return(0); 816 } 817 818 void 819 bge_free_rx_ring_std(sc) 820 struct bge_softc *sc; 821 { 822 int i; 823 824 if (!(sc->bge_flags & BGE_RXRING_VALID)) 825 return; 826 827 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { 828 if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) { 829 m_freem(sc->bge_cdata.bge_rx_std_chain[i]); 830 sc->bge_cdata.bge_rx_std_chain[i] = NULL; 831 bus_dmamap_destroy(sc->bge_dmatag, 832 sc->bge_cdata.bge_rx_std_map[i]); 833 } 834 memset((char *)&sc->bge_rdata->bge_rx_std_ring[i], 0, 835 sizeof(struct bge_rx_bd)); 836 } 837 838 sc->bge_flags &= ~BGE_RXRING_VALID; 839 } 840 841 int 842 bge_init_rx_ring_jumbo(sc) 843 struct bge_softc *sc; 844 { 845 int i; 846 struct bge_rcb *rcb; 847 struct bge_rcb_opaque *rcbo; 848 849 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 850 if (bge_newbuf_jumbo(sc, i, NULL) == ENOBUFS) 851 return(ENOBUFS); 852 }; 853 854 sc->bge_jumbo = i - 1; 855 856 rcb = &sc->bge_rdata->bge_info.bge_jumbo_rx_rcb; 857 rcbo = (struct bge_rcb_opaque *)rcb; 858 rcb->bge_flags = 0; 859 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcbo->bge_reg2); 860 861 CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo); 862 863 return(0); 864 } 865 866 void 867 bge_free_rx_ring_jumbo(sc) 868 struct bge_softc *sc; 869 { 870 int i; 871 872 if (!(sc->bge_flags & BGE_JUMBO_RXRING_VALID)) 873 return; 874 875 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 876 if (sc->bge_cdata.bge_rx_jumbo_chain[i] != NULL) { 877 m_freem(sc->bge_cdata.bge_rx_jumbo_chain[i]); 878 sc->bge_cdata.bge_rx_jumbo_chain[i] = NULL; 879 } 880 memset((char *)&sc->bge_rdata->bge_rx_jumbo_ring[i], 0, 881 sizeof(struct bge_rx_bd)); 882 } 883 884 sc->bge_flags &= ~BGE_JUMBO_RXRING_VALID; 885 } 886 887 void 888 bge_free_tx_ring(sc) 889 struct bge_softc *sc; 890 { 891 int i, freed; 892 struct txdmamap_pool_entry *dma; 893 894 if (!(sc->bge_flags & BGE_TXRING_VALID)) 895 return; 896 897 freed = 0; 898 899 for (i = 0; i < BGE_TX_RING_CNT; i++) { 900 if (sc->bge_cdata.bge_tx_chain[i] != NULL) { 901 freed++; 902 m_freem(sc->bge_cdata.bge_tx_chain[i]); 903 sc->bge_cdata.bge_tx_chain[i] = NULL; 904 SLIST_INSERT_HEAD(&sc->txdma_list, sc->txdma[i], 905 link); 906 sc->txdma[i] = 0; 907 } 908 memset((char *)&sc->bge_rdata->bge_tx_ring[i], 0, 909 sizeof(struct bge_tx_bd)); 910 } 911 912 while ((dma = SLIST_FIRST(&sc->txdma_list))) { 913 SLIST_REMOVE_HEAD(&sc->txdma_list, link); 914 bus_dmamap_destroy(sc->bge_dmatag, dma->dmamap); 915 free(dma, M_DEVBUF); 916 } 917 918 sc->bge_flags &= ~BGE_TXRING_VALID; 919 } 920 921 int 922 bge_init_tx_ring(sc) 923 struct bge_softc *sc; 924 { 925 int i; 926 bus_dmamap_t dmamap; 927 struct txdmamap_pool_entry *dma; 928 929 if (sc->bge_flags & BGE_TXRING_VALID) 930 return 0; 931 932 sc->bge_txcnt = 0; 933 sc->bge_tx_saved_considx = 0; 934 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, 0); 935 CSR_WRITE_4(sc, BGE_MBX_TX_NIC_PROD0_LO, 0); 936 937 SLIST_INIT(&sc->txdma_list); 938 for (i = 0; i < BGE_RSLOTS; i++) { 939 if (bus_dmamap_create(sc->bge_dmatag, ETHER_MAX_LEN_JUMBO, 940 BGE_NTXSEG, ETHER_MAX_LEN_JUMBO, 0, BUS_DMA_NOWAIT, 941 &dmamap)) 942 return(ENOBUFS); 943 if (dmamap == NULL) 944 panic("dmamap NULL in bge_init_tx_ring"); 945 dma = malloc(sizeof(*dma), M_DEVBUF, M_NOWAIT); 946 if (dma == NULL) { 947 printf("%s: can't alloc txdmamap_pool_entry\n", 948 sc->bge_dev.dv_xname); 949 bus_dmamap_destroy(sc->bge_dmatag, dmamap); 950 return (ENOMEM); 951 } 952 dma->dmamap = dmamap; 953 SLIST_INSERT_HEAD(&sc->txdma_list, dma, link); 954 } 955 956 sc->bge_flags |= BGE_TXRING_VALID; 957 958 return(0); 959 } 960 961 #define BGE_POLY 0xEDB88320 962 963 u_int32_t 964 bge_crc(sc, addr) 965 struct bge_softc *sc; 966 caddr_t addr; 967 { 968 u_int32_t idx, bit, data, crc; 969 970 /* Compute CRC for the address value. */ 971 crc = 0xFFFFFFFF; /* initial value */ 972 973 for (idx = 0; idx < 6; idx++) { 974 for (data = *addr++, bit = 0; bit < 8; bit++, data >>= 1) 975 crc = (crc >> 1) ^ (((crc ^ data) & 1) ? BGE_POLY : 0); 976 } 977 978 return(crc & 0x7F); 979 } 980 981 void 982 bge_setmulti(sc) 983 struct bge_softc *sc; 984 { 985 struct ethercom *ac = &sc->ethercom; 986 struct ifnet *ifp = &ac->ec_if; 987 struct ether_multi *enm; 988 struct ether_multistep step; 989 u_int32_t hashes[4] = { 0, 0, 0, 0 }; 990 u_int32_t h; 991 int i; 992 993 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 994 for (i = 0; i < 4; i++) 995 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0xFFFFFFFF); 996 return; 997 } 998 999 /* First, zot all the existing filters. */ 1000 for (i = 0; i < 4; i++) 1001 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0); 1002 1003 /* Now program new ones. */ 1004 ETHER_FIRST_MULTI(step, ac, enm); 1005 while (enm != NULL) { 1006 h = bge_crc(sc, LLADDR((struct sockaddr_dl *)enm->enm_addrlo)); 1007 hashes[(h & 0x60) >> 5] |= 1 << (h & 0x1F); 1008 ETHER_NEXT_MULTI(step, enm); 1009 } 1010 1011 for (i = 0; i < 4; i++) 1012 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]); 1013 } 1014 1015 int bge_swapbits[] = { 1016 0, 1017 BGE_MODECTL_BYTESWAP_DATA, 1018 BGE_MODECTL_WORDSWAP_DATA, 1019 BGE_MODECTL_BYTESWAP_NONFRAME, 1020 BGE_MODECTL_WORDSWAP_NONFRAME, 1021 1022 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA, 1023 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_BYTESWAP_NONFRAME, 1024 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_NONFRAME, 1025 1026 BGE_MODECTL_WORDSWAP_DATA|BGE_MODECTL_BYTESWAP_NONFRAME, 1027 BGE_MODECTL_WORDSWAP_DATA|BGE_MODECTL_WORDSWAP_NONFRAME, 1028 1029 BGE_MODECTL_BYTESWAP_NONFRAME|BGE_MODECTL_WORDSWAP_NONFRAME, 1030 1031 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA| 1032 BGE_MODECTL_BYTESWAP_NONFRAME, 1033 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA| 1034 BGE_MODECTL_WORDSWAP_NONFRAME, 1035 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_BYTESWAP_NONFRAME| 1036 BGE_MODECTL_WORDSWAP_NONFRAME, 1037 BGE_MODECTL_WORDSWAP_DATA|BGE_MODECTL_BYTESWAP_NONFRAME| 1038 BGE_MODECTL_WORDSWAP_NONFRAME, 1039 1040 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA| 1041 BGE_MODECTL_BYTESWAP_NONFRAME|BGE_MODECTL_WORDSWAP_NONFRAME, 1042 }; 1043 1044 int bge_swapindex = 0; 1045 1046 /* 1047 * Do endian, PCI and DMA initialization. Also check the on-board ROM 1048 * self-test results. 1049 */ 1050 int 1051 bge_chipinit(sc) 1052 struct bge_softc *sc; 1053 { 1054 u_int32_t cachesize; 1055 int i; 1056 struct pci_attach_args *pa = &(sc->bge_pa); 1057 1058 1059 /* Set endianness before we access any non-PCI registers. */ 1060 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_MISC_CTL, 1061 BGE_INIT); 1062 1063 /* 1064 * Check the 'ROM failed' bit on the RX CPU to see if 1065 * self-tests passed. 1066 */ 1067 if (CSR_READ_4(sc, BGE_RXCPU_MODE) & BGE_RXCPUMODE_ROMFAIL) { 1068 printf("%s: RX CPU self-diagnostics failed!\n", 1069 sc->bge_dev.dv_xname); 1070 return(ENODEV); 1071 } 1072 1073 /* Clear the MAC control register */ 1074 CSR_WRITE_4(sc, BGE_MAC_MODE, 0); 1075 1076 /* 1077 * Clear the MAC statistics block in the NIC's 1078 * internal memory. 1079 */ 1080 for (i = BGE_STATS_BLOCK; 1081 i < BGE_STATS_BLOCK_END + 1; i += sizeof(u_int32_t)) 1082 BGE_MEMWIN_WRITE(pa->pa_pc, pa->pa_tag, i, 0); 1083 1084 for (i = BGE_STATUS_BLOCK; 1085 i < BGE_STATUS_BLOCK_END + 1; i += sizeof(u_int32_t)) 1086 BGE_MEMWIN_WRITE(pa->pa_pc, pa->pa_tag, i, 0); 1087 1088 /* Set up the PCI DMA control register. */ 1089 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_DMA_RW_CTL, 1090 BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD|0x0F); 1091 1092 /* 1093 * Set up general mode register. 1094 */ 1095 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS| 1096 BGE_MODECTL_MAC_ATTN_INTR|BGE_MODECTL_HOST_SEND_BDS| 1097 BGE_MODECTL_NO_RX_CRC|BGE_MODECTL_TX_NO_PHDR_CSUM| 1098 BGE_MODECTL_RX_NO_PHDR_CSUM); 1099 1100 /* Get cache line size. */ 1101 cachesize = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_CACHESZ); 1102 1103 /* 1104 * Avoid violating PCI spec on certain chip revs. 1105 */ 1106 if (pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_CMD) & 1107 PCIM_CMD_MWIEN) { 1108 switch(cachesize) { 1109 case 1: 1110 PCI_SETBIT(pa->pa_pc, pa->pa_tag, BGE_PCI_DMA_RW_CTL, 1111 BGE_PCI_WRITE_BNDRY_16BYTES); 1112 break; 1113 case 2: 1114 PCI_SETBIT(pa->pa_pc, pa->pa_tag, BGE_PCI_DMA_RW_CTL, 1115 BGE_PCI_WRITE_BNDRY_32BYTES); 1116 break; 1117 case 4: 1118 PCI_SETBIT(pa->pa_pc, pa->pa_tag, BGE_PCI_DMA_RW_CTL, 1119 BGE_PCI_WRITE_BNDRY_64BYTES); 1120 break; 1121 case 8: 1122 PCI_SETBIT(pa->pa_pc, pa->pa_tag, BGE_PCI_DMA_RW_CTL, 1123 BGE_PCI_WRITE_BNDRY_128BYTES); 1124 break; 1125 case 16: 1126 PCI_SETBIT(pa->pa_pc, pa->pa_tag, BGE_PCI_DMA_RW_CTL, 1127 BGE_PCI_WRITE_BNDRY_256BYTES); 1128 break; 1129 case 32: 1130 PCI_SETBIT(pa->pa_pc, pa->pa_tag, BGE_PCI_DMA_RW_CTL, 1131 BGE_PCI_WRITE_BNDRY_512BYTES); 1132 break; 1133 case 64: 1134 PCI_SETBIT(pa->pa_pc, pa->pa_tag, BGE_PCI_DMA_RW_CTL, 1135 BGE_PCI_WRITE_BNDRY_1024BYTES); 1136 break; 1137 default: 1138 /* Disable PCI memory write and invalidate. */ 1139 #if 0 1140 if (bootverbose) 1141 printf("%s: cache line size %d not " 1142 "supported; disabling PCI MWI\n", 1143 sc->bge_dev.dv_xname, cachesize); 1144 #endif 1145 PCI_CLRBIT(pa->pa_pc, pa->pa_tag, BGE_PCI_CMD, 1146 PCIM_CMD_MWIEN); 1147 break; 1148 } 1149 } 1150 1151 #ifdef __brokenalpha__ 1152 /* 1153 * Must insure that we do not cross an 8K (bytes) boundary 1154 * for DMA reads. Our highest limit is 1K bytes. This is a 1155 * restriction on some ALPHA platforms with early revision 1156 * 21174 PCI chipsets, such as the AlphaPC 164lx 1157 */ 1158 PCI_SETBIT(sc, BGE_PCI_DMA_RW_CTL, BGE_PCI_READ_BNDRY_1024, 4); 1159 #endif 1160 1161 /* Set the timer prescaler (always 66Mhz) */ 1162 CSR_WRITE_4(sc, BGE_MISC_CFG, 65 << 1/*BGE_32BITTIME_66MHZ*/); 1163 1164 return(0); 1165 } 1166 1167 int 1168 bge_blockinit(sc) 1169 struct bge_softc *sc; 1170 { 1171 struct bge_rcb *rcb; 1172 struct bge_rcb_opaque *rcbo; 1173 bus_size_t rcb_addr; 1174 int i; 1175 struct ifnet *ifp = &sc->ethercom.ec_if; 1176 bge_hostaddr taddr; 1177 1178 /* 1179 * Initialize the memory window pointer register so that 1180 * we can access the first 32K of internal NIC RAM. This will 1181 * allow us to set up the TX send ring RCBs and the RX return 1182 * ring RCBs, plus other things which live in NIC memory. 1183 */ 1184 1185 pci_conf_write(sc->bge_pa.pa_pc, sc->bge_pa.pa_tag, 1186 BGE_PCI_MEMWIN_BASEADDR, 0); 1187 1188 /* Configure mbuf memory pool */ 1189 if (sc->bge_extram) { 1190 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, BGE_EXT_SSRAM); 1191 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000); 1192 } else { 1193 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, BGE_BUFFPOOL_1); 1194 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000); 1195 } 1196 1197 /* Configure DMA resource pool */ 1198 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_BASEADDR, BGE_DMA_DESCRIPTORS); 1199 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LEN, 0x2000); 1200 1201 /* Configure mbuf pool watermarks */ 1202 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 24); 1203 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 24); 1204 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 48); 1205 1206 /* Configure DMA resource watermarks */ 1207 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5); 1208 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10); 1209 1210 /* Enable buffer manager */ 1211 CSR_WRITE_4(sc, BGE_BMAN_MODE, 1212 BGE_BMANMODE_ENABLE|BGE_BMANMODE_LOMBUF_ATTN); 1213 1214 /* Poll for buffer manager start indication */ 1215 for (i = 0; i < BGE_TIMEOUT; i++) { 1216 if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE) 1217 break; 1218 DELAY(10); 1219 } 1220 1221 if (i == BGE_TIMEOUT) { 1222 printf("%s: buffer manager failed to start\n", 1223 sc->bge_dev.dv_xname); 1224 return(ENXIO); 1225 } 1226 1227 /* Enable flow-through queues */ 1228 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 1229 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 1230 1231 /* Wait until queue initialization is complete */ 1232 for (i = 0; i < BGE_TIMEOUT; i++) { 1233 if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0) 1234 break; 1235 DELAY(10); 1236 } 1237 1238 if (i == BGE_TIMEOUT) { 1239 printf("%s: flow-through queue init failed\n", 1240 sc->bge_dev.dv_xname); 1241 return(ENXIO); 1242 } 1243 1244 /* Initialize the standard RX ring control block */ 1245 rcb = &sc->bge_rdata->bge_info.bge_std_rx_rcb; 1246 bge_set_hostaddr(&rcb->bge_hostaddr, 1247 BGE_RING_DMA_ADDR(sc, bge_rx_std_ring)); 1248 rcb->bge_max_len = BGE_MAX_FRAMELEN; 1249 if (sc->bge_extram) 1250 rcb->bge_nicaddr = BGE_EXT_STD_RX_RINGS; 1251 else 1252 rcb->bge_nicaddr = BGE_STD_RX_RINGS; 1253 rcb->bge_flags = 0; 1254 rcbo = (struct bge_rcb_opaque *)rcb; 1255 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcbo->bge_reg0); 1256 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcbo->bge_reg1); 1257 CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcbo->bge_reg2); 1258 CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcbo->bge_reg3); 1259 1260 /* 1261 * Initialize the jumbo RX ring control block 1262 * We set the 'ring disabled' bit in the flags 1263 * field until we're actually ready to start 1264 * using this ring (i.e. once we set the MTU 1265 * high enough to require it). 1266 */ 1267 rcb = &sc->bge_rdata->bge_info.bge_jumbo_rx_rcb; 1268 bge_set_hostaddr(&rcb->bge_hostaddr, 1269 BGE_RING_DMA_ADDR(sc, bge_rx_jumbo_ring)); 1270 rcb->bge_max_len = BGE_MAX_FRAMELEN; 1271 if (sc->bge_extram) 1272 rcb->bge_nicaddr = BGE_EXT_JUMBO_RX_RINGS; 1273 else 1274 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS; 1275 rcb->bge_flags = BGE_RCB_FLAG_RING_DISABLED; 1276 1277 rcbo = (struct bge_rcb_opaque *)rcb; 1278 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI, rcbo->bge_reg0); 1279 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO, rcbo->bge_reg1); 1280 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcbo->bge_reg2); 1281 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcbo->bge_reg3); 1282 1283 /* Set up dummy disabled mini ring RCB */ 1284 rcb = &sc->bge_rdata->bge_info.bge_mini_rx_rcb; 1285 rcb->bge_flags = BGE_RCB_FLAG_RING_DISABLED; 1286 rcbo = (struct bge_rcb_opaque *)rcb; 1287 CSR_WRITE_4(sc, BGE_RX_MINI_RCB_MAXLEN_FLAGS, rcbo->bge_reg2); 1288 1289 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 1290 offsetof(struct bge_ring_data, bge_info), sizeof (struct bge_gib), 1291 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1292 1293 /* 1294 * Set the BD ring replentish thresholds. The recommended 1295 * values are 1/8th the number of descriptors allocated to 1296 * each ring. 1297 */ 1298 CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, BGE_STD_RX_RING_CNT/8); 1299 CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH, BGE_JUMBO_RX_RING_CNT/8); 1300 1301 /* 1302 * Disable all unused send rings by setting the 'ring disabled' 1303 * bit in the flags field of all the TX send ring control blocks. 1304 * These are located in NIC memory. 1305 */ 1306 rcb_addr = BGE_MEMWIN_START + BGE_SEND_RING_RCB; 1307 for (i = 0; i < BGE_TX_RINGS_EXTSSRAM_MAX; i++) { 1308 RCB_WRITE_2(sc, rcb_addr, bge_flags, 1309 BGE_RCB_FLAG_RING_DISABLED); 1310 RCB_WRITE_2(sc, rcb_addr, bge_max_len, 0); 1311 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 0); 1312 rcb_addr += sizeof(struct bge_rcb); 1313 } 1314 1315 /* Configure TX RCB 0 (we use only the first ring) */ 1316 rcb_addr = BGE_MEMWIN_START + BGE_SEND_RING_RCB; 1317 bge_set_hostaddr(&taddr, BGE_RING_DMA_ADDR(sc, bge_tx_ring)); 1318 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi); 1319 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo); 1320 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 1321 BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT)); 1322 RCB_WRITE_2(sc, rcb_addr, bge_max_len, BGE_TX_RING_CNT); 1323 RCB_WRITE_2(sc, rcb_addr, bge_flags, 0); 1324 1325 /* Disable all unused RX return rings */ 1326 rcb_addr = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB; 1327 for (i = 0; i < BGE_RX_RINGS_MAX; i++) { 1328 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_hi, 0); 1329 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_lo, 0); 1330 RCB_WRITE_2(sc, rcb_addr, bge_flags, 1331 BGE_RCB_FLAG_RING_DISABLED); 1332 RCB_WRITE_2(sc, rcb_addr, bge_max_len, BGE_RETURN_RING_CNT); 1333 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 0); 1334 CSR_WRITE_4(sc, BGE_MBX_RX_CONS0_LO + 1335 (i * (sizeof(u_int64_t))), 0); 1336 rcb_addr += sizeof(struct bge_rcb); 1337 } 1338 1339 /* Initialize RX ring indexes */ 1340 CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, 0); 1341 CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0); 1342 CSR_WRITE_4(sc, BGE_MBX_RX_MINI_PROD_LO, 0); 1343 1344 /* 1345 * Set up RX return ring 0 1346 * Note that the NIC address for RX return rings is 0x00000000. 1347 * The return rings live entirely within the host, so the 1348 * nicaddr field in the RCB isn't used. 1349 */ 1350 rcb_addr = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB; 1351 bge_set_hostaddr(&taddr, BGE_RING_DMA_ADDR(sc, bge_rx_return_ring)); 1352 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi); 1353 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo); 1354 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 0x00000000); 1355 RCB_WRITE_2(sc, rcb_addr, bge_max_len, BGE_RETURN_RING_CNT); 1356 RCB_WRITE_2(sc, rcb_addr, bge_flags, 0); 1357 1358 /* Set random backoff seed for TX */ 1359 CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF, 1360 LLADDR(ifp->if_sadl)[0] + LLADDR(ifp->if_sadl)[1] + 1361 LLADDR(ifp->if_sadl)[2] + LLADDR(ifp->if_sadl)[3] + 1362 LLADDR(ifp->if_sadl)[4] + LLADDR(ifp->if_sadl)[5] + 1363 BGE_TX_BACKOFF_SEED_MASK); 1364 1365 /* Set inter-packet gap */ 1366 CSR_WRITE_4(sc, BGE_TX_LENGTHS, 0x2620); 1367 1368 /* 1369 * Specify which ring to use for packets that don't match 1370 * any RX rules. 1371 */ 1372 CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08); 1373 1374 /* 1375 * Configure number of RX lists. One interrupt distribution 1376 * list, sixteen active lists, one bad frames class. 1377 */ 1378 CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181); 1379 1380 /* Inialize RX list placement stats mask. */ 1381 CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF); 1382 CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1); 1383 1384 /* Disable host coalescing until we get it set up */ 1385 CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000); 1386 1387 /* Poll to make sure it's shut down. */ 1388 for (i = 0; i < BGE_TIMEOUT; i++) { 1389 if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE)) 1390 break; 1391 DELAY(10); 1392 } 1393 1394 if (i == BGE_TIMEOUT) { 1395 printf("%s: host coalescing engine failed to idle\n", 1396 sc->bge_dev.dv_xname); 1397 return(ENXIO); 1398 } 1399 1400 /* Set up host coalescing defaults */ 1401 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bge_rx_coal_ticks); 1402 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bge_tx_coal_ticks); 1403 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bge_rx_max_coal_bds); 1404 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bge_tx_max_coal_bds); 1405 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT, 0); 1406 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT, 0); 1407 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 0); 1408 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 0); 1409 CSR_WRITE_4(sc, BGE_HCC_STATS_TICKS, sc->bge_stat_ticks); 1410 1411 /* Set up address of statistics block */ 1412 bge_set_hostaddr(&taddr, BGE_RING_DMA_ADDR(sc, bge_info.bge_stats)); 1413 CSR_WRITE_4(sc, BGE_HCC_STATS_BASEADDR, BGE_STATS_BLOCK); 1414 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_HI, taddr.bge_addr_hi); 1415 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_LO, taddr.bge_addr_lo); 1416 1417 /* Set up address of status block */ 1418 bge_set_hostaddr(&taddr, BGE_RING_DMA_ADDR(sc, bge_status_block)); 1419 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_BASEADDR, BGE_STATUS_BLOCK); 1420 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI, taddr.bge_addr_hi); 1421 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO, taddr.bge_addr_lo); 1422 sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx = 0; 1423 sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx = 0; 1424 1425 /* Turn on host coalescing state machine */ 1426 CSR_WRITE_4(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE); 1427 1428 /* Turn on RX BD completion state machine and enable attentions */ 1429 CSR_WRITE_4(sc, BGE_RBDC_MODE, 1430 BGE_RBDCMODE_ENABLE|BGE_RBDCMODE_ATTN); 1431 1432 /* Turn on RX list placement state machine */ 1433 CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 1434 1435 /* Turn on RX list selector state machine. */ 1436 CSR_WRITE_4(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 1437 1438 /* Turn on DMA, clear stats */ 1439 CSR_WRITE_4(sc, BGE_MAC_MODE, BGE_MACMODE_TXDMA_ENB| 1440 BGE_MACMODE_RXDMA_ENB|BGE_MACMODE_RX_STATS_CLEAR| 1441 BGE_MACMODE_TX_STATS_CLEAR|BGE_MACMODE_RX_STATS_ENB| 1442 BGE_MACMODE_TX_STATS_ENB|BGE_MACMODE_FRMHDR_DMA_ENB| 1443 (sc->bge_tbi ? BGE_PORTMODE_TBI : BGE_PORTMODE_MII)); 1444 1445 /* Set misc. local control, enable interrupts on attentions */ 1446 CSR_WRITE_4(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_ONATTN); 1447 1448 #ifdef notdef 1449 /* Assert GPIO pins for PHY reset */ 1450 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUT0| 1451 BGE_MLC_MISCIO_OUT1|BGE_MLC_MISCIO_OUT2); 1452 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUTEN0| 1453 BGE_MLC_MISCIO_OUTEN1|BGE_MLC_MISCIO_OUTEN2); 1454 #endif 1455 1456 /* Turn on DMA completion state machine */ 1457 CSR_WRITE_4(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 1458 1459 /* Turn on write DMA state machine */ 1460 CSR_WRITE_4(sc, BGE_WDMA_MODE, 1461 BGE_WDMAMODE_ENABLE|BGE_WDMAMODE_ALL_ATTNS); 1462 1463 /* Turn on read DMA state machine */ 1464 CSR_WRITE_4(sc, BGE_RDMA_MODE, 1465 BGE_RDMAMODE_ENABLE|BGE_RDMAMODE_ALL_ATTNS); 1466 1467 /* Turn on RX data completion state machine */ 1468 CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 1469 1470 /* Turn on RX BD initiator state machine */ 1471 CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 1472 1473 /* Turn on RX data and RX BD initiator state machine */ 1474 CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE); 1475 1476 /* Turn on Mbuf cluster free state machine */ 1477 CSR_WRITE_4(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 1478 1479 /* Turn on send BD completion state machine */ 1480 CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 1481 1482 /* Turn on send data completion state machine */ 1483 CSR_WRITE_4(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE); 1484 1485 /* Turn on send data initiator state machine */ 1486 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 1487 1488 /* Turn on send BD initiator state machine */ 1489 CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 1490 1491 /* Turn on send BD selector state machine */ 1492 CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 1493 1494 CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF); 1495 CSR_WRITE_4(sc, BGE_SDI_STATS_CTL, 1496 BGE_SDISTATSCTL_ENABLE|BGE_SDISTATSCTL_FASTER); 1497 1498 /* init LED register */ 1499 CSR_WRITE_4(sc, BGE_MAC_LED_CTL, 0x00000000); 1500 1501 /* ack/clear link change events */ 1502 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED| 1503 BGE_MACSTAT_CFG_CHANGED); 1504 CSR_WRITE_4(sc, BGE_MI_STS, 0); 1505 1506 /* Enable PHY auto polling (for MII/GMII only) */ 1507 if (sc->bge_tbi) { 1508 CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK); 1509 } else { 1510 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL|10<<16); 1511 if (BGE_IS_5700_Ax_Bx(sc->bge_asicrev)) 1512 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, 1513 BGE_EVTENB_MI_INTERRUPT); 1514 } 1515 1516 /* Enable link state change attentions. */ 1517 BGE_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED); 1518 1519 return(0); 1520 } 1521 1522 static const struct bge_product { 1523 pci_vendor_id_t bp_vendor; 1524 pci_product_id_t bp_product; 1525 const char *bp_name; 1526 } bge_products[] = { 1527 /* 1528 * The BCM5700 documentation seems to indicate that the hardware 1529 * still has the Alteon vendor ID burned into it, though it 1530 * should always be overridden by the value in the EEPROM. We'll 1531 * check for it anyway. 1532 */ 1533 { PCI_VENDOR_ALTEON, 1534 PCI_PRODUCT_ALTEON_BCM5700, 1535 "Broadcom BCM5700 Gigabit Ethernet" }, 1536 { PCI_VENDOR_ALTEON, 1537 PCI_PRODUCT_ALTEON_BCM5701, 1538 "Broadcom BCM5701 Gigabit Ethernet" }, 1539 1540 { PCI_VENDOR_ALTIMA, 1541 PCI_PRODUCT_ALTIMA_AC1000, 1542 "Altima AC1000 Gigabit Ethernet" }, 1543 { PCI_VENDOR_ALTIMA, 1544 PCI_PRODUCT_ALTIMA_AC9100, 1545 "Altima AC9100 Gigabit Ethernet" }, 1546 1547 { PCI_VENDOR_BROADCOM, 1548 PCI_PRODUCT_BROADCOM_BCM5700, 1549 "Broadcom BCM5700 Gigabit Ethernet" }, 1550 { PCI_VENDOR_BROADCOM, 1551 PCI_PRODUCT_BROADCOM_BCM5701, 1552 "Broadcom BCM5700 Gigabit Ethernet" }, 1553 1554 { PCI_VENDOR_SCHNEIDERKOCH, 1555 PCI_PRODUCT_SCHNEIDERKOCH_SK_9DX1, 1556 "SysKonnect SK-9Dx1 Gigabit Ethernet" }, 1557 1558 { PCI_VENDOR_3COM, 1559 PCI_PRODUCT_3COM_3C996, 1560 "3Com 3c996 Gigabit Ethernet" }, 1561 1562 { 0, 1563 0, 1564 NULL }, 1565 }; 1566 1567 static const struct bge_product * 1568 bge_lookup(const struct pci_attach_args *pa) 1569 { 1570 const struct bge_product *bp; 1571 1572 for (bp = bge_products; bp->bp_name != NULL; bp++) { 1573 if (PCI_VENDOR(pa->pa_id) == bp->bp_vendor && 1574 PCI_PRODUCT(pa->pa_id) == bp->bp_product) 1575 return (bp); 1576 } 1577 1578 return (NULL); 1579 } 1580 1581 /* 1582 * Probe for a Broadcom chip. Check the PCI vendor and device IDs 1583 * against our list and return its name if we find a match. Note 1584 * that since the Broadcom controller contains VPD support, we 1585 * can get the device name string from the controller itself instead 1586 * of the compiled-in string. This is a little slow, but it guarantees 1587 * we'll always announce the right product name. 1588 */ 1589 int 1590 bge_probe(parent, match, aux) 1591 struct device *parent; 1592 struct cfdata *match; 1593 void *aux; 1594 { 1595 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 1596 1597 if (bge_lookup(pa) != NULL) 1598 return (1); 1599 1600 return (0); 1601 } 1602 1603 void 1604 bge_attach(parent, self, aux) 1605 struct device *parent, *self; 1606 void *aux; 1607 { 1608 struct bge_softc *sc = (struct bge_softc *)self; 1609 struct pci_attach_args *pa = aux; 1610 const struct bge_product *bp; 1611 pci_chipset_tag_t pc = pa->pa_pc; 1612 pci_intr_handle_t ih; 1613 const char *intrstr = NULL; 1614 bus_dma_segment_t seg; 1615 int rseg; 1616 u_int32_t hwcfg = 0; 1617 u_int32_t command; 1618 struct ifnet *ifp; 1619 int unit; 1620 caddr_t kva; 1621 u_char eaddr[ETHER_ADDR_LEN]; 1622 pcireg_t memtype; 1623 bus_addr_t memaddr; 1624 bus_size_t memsize; 1625 1626 bp = bge_lookup(pa); 1627 KASSERT(bp != NULL); 1628 1629 sc->bge_pa = *pa; 1630 1631 printf(": %s, rev. 0x%02x\n", bp->bp_name, PCI_REVISION(pa->pa_class)); 1632 1633 /* 1634 * Map control/status registers. 1635 */ 1636 DPRINTFN(5, ("Map control/status regs\n")); 1637 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 1638 command |= PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_MASTER_ENABLE; 1639 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, command); 1640 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 1641 1642 if (!(command & PCI_COMMAND_MEM_ENABLE)) { 1643 printf("%s: failed to enable memory mapping!\n", 1644 sc->bge_dev.dv_xname); 1645 return; 1646 } 1647 1648 DPRINTFN(5, ("pci_mem_find\n")); 1649 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, BGE_PCI_BAR0); 1650 switch (memtype) { 1651 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 1652 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 1653 if (pci_mapreg_map(pa, BGE_PCI_BAR0, 1654 memtype, 0, &sc->bge_btag, &sc->bge_bhandle, 1655 &memaddr, &memsize) == 0) 1656 break; 1657 default: 1658 printf("%s: can't find mem space\n", 1659 sc->bge_dev.dv_xname); 1660 return; 1661 } 1662 1663 DPRINTFN(5, ("pci_intr_map\n")); 1664 if (pci_intr_map(pa, &ih)) { 1665 printf("%s: couldn't map interrupt\n", 1666 sc->bge_dev.dv_xname); 1667 return; 1668 } 1669 1670 DPRINTFN(5, ("pci_intr_string\n")); 1671 intrstr = pci_intr_string(pc, ih); 1672 1673 DPRINTFN(5, ("pci_intr_establish\n")); 1674 sc->bge_intrhand = pci_intr_establish(pc, ih, IPL_NET, bge_intr, sc); 1675 1676 if (sc->bge_intrhand == NULL) { 1677 printf("%s: couldn't establish interrupt", 1678 sc->bge_dev.dv_xname); 1679 if (intrstr != NULL) 1680 printf(" at %s", intrstr); 1681 printf("\n"); 1682 return; 1683 } 1684 printf("%s: interrupting at %s\n", sc->bge_dev.dv_xname, intrstr); 1685 1686 /* Try to reset the chip. */ 1687 DPRINTFN(5, ("bge_reset\n")); 1688 bge_reset(sc); 1689 1690 if (bge_chipinit(sc)) { 1691 printf("%s: chip initializatino failed\n", 1692 sc->bge_dev.dv_xname); 1693 bge_release_resources(sc); 1694 return; 1695 } 1696 1697 /* 1698 * Get station address from the EEPROM. 1699 */ 1700 if (bge_read_eeprom(sc, (caddr_t)eaddr, 1701 BGE_EE_MAC_OFFSET + 2, ETHER_ADDR_LEN)) { 1702 printf("bge%d: failed to read station address\n", unit); 1703 bge_release_resources(sc); 1704 return; 1705 } 1706 1707 /* 1708 * A Broadcom chip was detected. Inform the world. 1709 */ 1710 printf("%s: Ethernet address %s\n", sc->bge_dev.dv_xname, 1711 ether_sprintf(eaddr)); 1712 1713 /* Allocate the general information block and ring buffers. */ 1714 sc->bge_dmatag = pa->pa_dmat; 1715 DPRINTFN(5, ("bus_dmamem_alloc\n")); 1716 if (bus_dmamem_alloc(sc->bge_dmatag, sizeof(struct bge_ring_data), 1717 PAGE_SIZE, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 1718 printf("%s: can't alloc rx buffers\n", sc->bge_dev.dv_xname); 1719 return; 1720 } 1721 DPRINTFN(5, ("bus_dmamem_map\n")); 1722 if (bus_dmamem_map(sc->bge_dmatag, &seg, rseg, 1723 sizeof(struct bge_ring_data), &kva, 1724 BUS_DMA_NOWAIT)) { 1725 printf("%s: can't map dma buffers (%d bytes)\n", 1726 sc->bge_dev.dv_xname, (int)sizeof(struct bge_ring_data)); 1727 bus_dmamem_free(sc->bge_dmatag, &seg, rseg); 1728 return; 1729 } 1730 DPRINTFN(5, ("bus_dmamem_create\n")); 1731 if (bus_dmamap_create(sc->bge_dmatag, sizeof(struct bge_ring_data), 1, 1732 sizeof(struct bge_ring_data), 0, 1733 BUS_DMA_NOWAIT, &sc->bge_ring_map)) { 1734 printf("%s: can't create dma map\n", sc->bge_dev.dv_xname); 1735 bus_dmamem_unmap(sc->bge_dmatag, kva, 1736 sizeof(struct bge_ring_data)); 1737 bus_dmamem_free(sc->bge_dmatag, &seg, rseg); 1738 return; 1739 } 1740 DPRINTFN(5, ("bus_dmamem_load\n")); 1741 if (bus_dmamap_load(sc->bge_dmatag, sc->bge_ring_map, kva, 1742 sizeof(struct bge_ring_data), NULL, 1743 BUS_DMA_NOWAIT)) { 1744 bus_dmamap_destroy(sc->bge_dmatag, sc->bge_ring_map); 1745 bus_dmamem_unmap(sc->bge_dmatag, kva, 1746 sizeof(struct bge_ring_data)); 1747 bus_dmamem_free(sc->bge_dmatag, &seg, rseg); 1748 return; 1749 } 1750 1751 DPRINTFN(5, ("bzero\n")); 1752 sc->bge_rdata = (struct bge_ring_data *)kva; 1753 1754 memset(sc->bge_rdata, sizeof(struct bge_ring_data), 0); 1755 1756 /* Try to allocate memory for jumbo buffers. */ 1757 if (bge_alloc_jumbo_mem(sc)) { 1758 printf("%s: jumbo buffer allocation failed\n", 1759 sc->bge_dev.dv_xname); 1760 } else 1761 sc->ethercom.ec_capabilities |= ETHERCAP_JUMBO_MTU; 1762 1763 /* Set default tuneable values. */ 1764 sc->bge_stat_ticks = BGE_TICKS_PER_SEC; 1765 sc->bge_rx_coal_ticks = 150; 1766 sc->bge_tx_coal_ticks = 150; 1767 sc->bge_rx_max_coal_bds = 64; 1768 sc->bge_tx_max_coal_bds = 128; 1769 1770 /* Set up ifnet structure */ 1771 ifp = &sc->ethercom.ec_if; 1772 ifp->if_softc = sc; 1773 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1774 ifp->if_ioctl = bge_ioctl; 1775 ifp->if_start = bge_start; 1776 ifp->if_init = bge_init; 1777 ifp->if_watchdog = bge_watchdog; 1778 IFQ_SET_MAXLEN(&ifp->if_snd, BGE_TX_RING_CNT - 1); 1779 IFQ_SET_READY(&ifp->if_snd); 1780 DPRINTFN(5, ("bcopy\n")); 1781 strcpy(ifp->if_xname, sc->bge_dev.dv_xname); 1782 1783 sc->ethercom.ec_if.if_capabilities |= 1784 IFCAP_CSUM_IPv4 | IFCAP_CSUM_TCPv4 | IFCAP_CSUM_UDPv4; 1785 sc->ethercom.ec_capabilities |= 1786 ETHERCAP_VLAN_HWTAGGING | ETHERCAP_VLAN_MTU; 1787 1788 /* 1789 * Do MII setup. 1790 */ 1791 DPRINTFN(5, ("mii setup\n")); 1792 sc->bge_mii.mii_ifp = ifp; 1793 sc->bge_mii.mii_readreg = bge_miibus_readreg; 1794 sc->bge_mii.mii_writereg = bge_miibus_writereg; 1795 sc->bge_mii.mii_statchg = bge_miibus_statchg; 1796 1797 /* Save ASIC rev. */ 1798 1799 sc->bge_asicrev = 1800 pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_MISC_CTL) & 1801 BGE_PCIMISCCTL_ASICREV; 1802 1803 /* 1804 * Figure out what sort of media we have by checking the 1805 * hardware config word in the EEPROM. Note: on some BCM5700 1806 * cards, this value appears to be unset. If that's the 1807 * case, we have to rely on identifying the NIC by its PCI 1808 * subsystem ID, as we do below for the SysKonnect SK-9D41. 1809 */ 1810 bge_read_eeprom(sc, (caddr_t)&hwcfg, 1811 BGE_EE_HWCFG_OFFSET, sizeof(hwcfg)); 1812 if ((be32toh(hwcfg) & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER) 1813 sc->bge_tbi = 1; 1814 1815 /* The SysKonnect SK-9D41 is a 1000baseSX card. */ 1816 if ((pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_SUBSYS) >> 16) == 1817 SK_SUBSYSID_9D41) 1818 sc->bge_tbi = 1; 1819 1820 if (sc->bge_tbi) { 1821 ifmedia_init(&sc->bge_ifmedia, IFM_IMASK, bge_ifmedia_upd, 1822 bge_ifmedia_sts); 1823 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL); 1824 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_1000_SX|IFM_FDX, 1825 0, NULL); 1826 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL); 1827 ifmedia_set(&sc->bge_ifmedia, IFM_ETHER|IFM_AUTO); 1828 } else { 1829 /* 1830 * Do transceiver setup. 1831 */ 1832 ifmedia_init(&sc->bge_mii.mii_media, 0, bge_ifmedia_upd, 1833 bge_ifmedia_sts); 1834 mii_attach(&sc->bge_dev, &sc->bge_mii, 0xffffffff, 1835 MII_PHY_ANY, MII_OFFSET_ANY, 0); 1836 1837 if (LIST_FIRST(&sc->bge_mii.mii_phys) == NULL) { 1838 printf("%s: no PHY found!\n", sc->bge_dev.dv_xname); 1839 ifmedia_add(&sc->bge_mii.mii_media, 1840 IFM_ETHER|IFM_MANUAL, 0, NULL); 1841 ifmedia_set(&sc->bge_mii.mii_media, 1842 IFM_ETHER|IFM_MANUAL); 1843 } else 1844 ifmedia_set(&sc->bge_mii.mii_media, 1845 IFM_ETHER|IFM_AUTO); 1846 } 1847 1848 /* 1849 * Call MI attach routine. 1850 */ 1851 DPRINTFN(5, ("if_attach\n")); 1852 if_attach(ifp); 1853 DPRINTFN(5, ("ether_ifattach\n")); 1854 ether_ifattach(ifp, eaddr); 1855 DPRINTFN(5, ("callout_init\n")); 1856 callout_init(&sc->bge_timeout); 1857 } 1858 1859 void 1860 bge_release_resources(sc) 1861 struct bge_softc *sc; 1862 { 1863 if (sc->bge_vpd_prodname != NULL) 1864 free(sc->bge_vpd_prodname, M_DEVBUF); 1865 1866 if (sc->bge_vpd_readonly != NULL) 1867 free(sc->bge_vpd_readonly, M_DEVBUF); 1868 } 1869 1870 void 1871 bge_reset(sc) 1872 struct bge_softc *sc; 1873 { 1874 struct pci_attach_args *pa = &sc->bge_pa; 1875 u_int32_t cachesize, command, pcistate; 1876 int i, val = 0; 1877 1878 /* Save some important PCI state. */ 1879 cachesize = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_CACHESZ); 1880 command = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_CMD); 1881 pcistate = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_PCISTATE); 1882 1883 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_MISC_CTL, 1884 BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR| 1885 BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_PCISTATE_RW); 1886 1887 /* Issue global reset */ 1888 bge_writereg_ind(sc, BGE_MISC_CFG, 1889 BGE_MISCCFG_RESET_CORE_CLOCKS|(65<<1)); 1890 1891 DELAY(1000); 1892 1893 /* Reset some of the PCI state that got zapped by reset */ 1894 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_MISC_CTL, 1895 BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR| 1896 BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_PCISTATE_RW); 1897 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_CMD, command); 1898 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_CACHESZ, cachesize); 1899 bge_writereg_ind(sc, BGE_MISC_CFG, (65 << 1)); 1900 1901 /* Enable memory arbiter. */ 1902 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 1903 1904 /* 1905 * Prevent PXE restart: write a magic number to the 1906 * general communications memory at 0xB50. 1907 */ 1908 bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM, BGE_MAGIC_NUMBER); 1909 1910 /* 1911 * Poll the value location we just wrote until 1912 * we see the 1's complement of the magic number. 1913 * This indicates that the firmware initialization 1914 * is complete. 1915 */ 1916 for (i = 0; i < 750; i++) { 1917 val = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM); 1918 if (val == ~BGE_MAGIC_NUMBER) 1919 break; 1920 DELAY(1000); 1921 } 1922 1923 if (i == 750) { 1924 printf("%s: firmware handshake timed out, val = %x\n", 1925 sc->bge_dev.dv_xname, val); 1926 return; 1927 } 1928 1929 /* 1930 * XXX Wait for the value of the PCISTATE register to 1931 * return to its original pre-reset state. This is a 1932 * fairly good indicator of reset completion. If we don't 1933 * wait for the reset to fully complete, trying to read 1934 * from the device's non-PCI registers may yield garbage 1935 * results. 1936 */ 1937 for (i = 0; i < BGE_TIMEOUT; i++) { 1938 if (pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_PCISTATE) == 1939 pcistate) 1940 break; 1941 DELAY(10); 1942 } 1943 1944 /* Enable memory arbiter. */ 1945 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 1946 1947 /* Fix up byte swapping */ 1948 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS); 1949 1950 CSR_WRITE_4(sc, BGE_MAC_MODE, 0); 1951 1952 DELAY(10000); 1953 } 1954 1955 /* 1956 * Frame reception handling. This is called if there's a frame 1957 * on the receive return list. 1958 * 1959 * Note: we have to be able to handle two possibilities here: 1960 * 1) the frame is from the jumbo recieve ring 1961 * 2) the frame is from the standard receive ring 1962 */ 1963 1964 void 1965 bge_rxeof(sc) 1966 struct bge_softc *sc; 1967 { 1968 struct ifnet *ifp; 1969 int stdcnt = 0, jumbocnt = 0; 1970 int have_tag = 0; 1971 u_int16_t vlan_tag = 0; 1972 bus_dmamap_t dmamap; 1973 bus_addr_t offset, toff; 1974 bus_size_t tlen; 1975 int tosync; 1976 1977 ifp = &sc->ethercom.ec_if; 1978 1979 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 1980 offsetof(struct bge_ring_data, bge_status_block), 1981 sizeof (struct bge_status_block), 1982 BUS_DMASYNC_POSTREAD); 1983 1984 offset = offsetof(struct bge_ring_data, bge_rx_return_ring); 1985 tosync = sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx - 1986 sc->bge_rx_saved_considx; 1987 1988 toff = offset + (sc->bge_rx_saved_considx * sizeof (struct bge_rx_bd)); 1989 1990 if (tosync < 0) { 1991 tlen = (BGE_RETURN_RING_CNT - sc->bge_rx_saved_considx) * 1992 sizeof (struct bge_rx_bd); 1993 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 1994 toff, tlen, BUS_DMASYNC_POSTREAD); 1995 tosync = -tosync; 1996 } 1997 1998 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 1999 offset, tosync * sizeof (struct bge_rx_bd), 2000 BUS_DMASYNC_POSTREAD); 2001 2002 while(sc->bge_rx_saved_considx != 2003 sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx) { 2004 struct bge_rx_bd *cur_rx; 2005 u_int32_t rxidx; 2006 struct mbuf *m = NULL; 2007 2008 cur_rx = &sc->bge_rdata-> 2009 bge_rx_return_ring[sc->bge_rx_saved_considx]; 2010 2011 rxidx = cur_rx->bge_idx; 2012 BGE_INC(sc->bge_rx_saved_considx, BGE_RETURN_RING_CNT); 2013 2014 if (cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) { 2015 have_tag = 1; 2016 vlan_tag = cur_rx->bge_vlan_tag; 2017 } 2018 2019 if (cur_rx->bge_flags & BGE_RXBDFLAG_JUMBO_RING) { 2020 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT); 2021 m = sc->bge_cdata.bge_rx_jumbo_chain[rxidx]; 2022 sc->bge_cdata.bge_rx_jumbo_chain[rxidx] = NULL; 2023 jumbocnt++; 2024 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 2025 ifp->if_ierrors++; 2026 bge_newbuf_jumbo(sc, sc->bge_jumbo, m); 2027 continue; 2028 } 2029 if (bge_newbuf_jumbo(sc, sc->bge_jumbo, 2030 NULL)== ENOBUFS) { 2031 ifp->if_ierrors++; 2032 bge_newbuf_jumbo(sc, sc->bge_jumbo, m); 2033 continue; 2034 } 2035 } else { 2036 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT); 2037 m = sc->bge_cdata.bge_rx_std_chain[rxidx]; 2038 sc->bge_cdata.bge_rx_std_chain[rxidx] = NULL; 2039 stdcnt++; 2040 dmamap = sc->bge_cdata.bge_rx_std_map[rxidx]; 2041 sc->bge_cdata.bge_rx_std_map[rxidx] = 0; 2042 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 2043 ifp->if_ierrors++; 2044 bge_newbuf_std(sc, sc->bge_std, m, dmamap); 2045 continue; 2046 } 2047 if (bge_newbuf_std(sc, sc->bge_std, 2048 NULL, dmamap) == ENOBUFS) { 2049 ifp->if_ierrors++; 2050 bge_newbuf_std(sc, sc->bge_std, m, dmamap); 2051 continue; 2052 } 2053 } 2054 2055 ifp->if_ipackets++; 2056 m->m_pkthdr.len = m->m_len = cur_rx->bge_len; 2057 m->m_pkthdr.rcvif = ifp; 2058 2059 #if NBPFILTER > 0 2060 /* 2061 * Handle BPF listeners. Let the BPF user see the packet. 2062 */ 2063 if (ifp->if_bpf) 2064 bpf_mtap(ifp->if_bpf, m); 2065 #endif 2066 2067 if (sc->bge_asicrev != BGE_ASICREV_BCM5700_B0) { 2068 m->m_pkthdr.csum_flags |= M_CSUM_IPv4; 2069 if ((cur_rx->bge_ip_csum ^ 0xffff) != 0) 2070 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 2071 #if 0 /* XXX appears to be broken */ 2072 if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM) { 2073 m->m_pkthdr.csum_data = 2074 cur_rx->bge_tcp_udp_csum; 2075 m->m_pkthdr.csum_flags |= 2076 (M_CSUM_TCPv4|M_CSUM_UDPv4|M_CSUM_DATA); 2077 } 2078 #endif 2079 } 2080 2081 /* 2082 * If we received a packet with a vlan tag, pass it 2083 * to vlan_input() instead of ether_input(). 2084 */ 2085 if (have_tag) { 2086 struct mbuf *n; 2087 2088 n = m_aux_add(m, AF_LINK, ETHERTYPE_VLAN); 2089 if (n != NULL) { 2090 *mtod(n, int *) = vlan_tag; 2091 n->m_len = sizeof(int); 2092 have_tag = vlan_tag = 0; 2093 } else { 2094 printf("%s: no mbuf for tag\n", ifp->if_xname); 2095 m_freem(m); 2096 have_tag = vlan_tag = 0; 2097 continue; 2098 } 2099 } 2100 (*ifp->if_input)(ifp, m); 2101 } 2102 2103 CSR_WRITE_4(sc, BGE_MBX_RX_CONS0_LO, sc->bge_rx_saved_considx); 2104 if (stdcnt) 2105 CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std); 2106 if (jumbocnt) 2107 CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo); 2108 } 2109 2110 void 2111 bge_txeof(sc) 2112 struct bge_softc *sc; 2113 { 2114 struct bge_tx_bd *cur_tx = NULL; 2115 struct ifnet *ifp; 2116 struct txdmamap_pool_entry *dma; 2117 bus_addr_t offset, toff; 2118 bus_size_t tlen; 2119 int tosync; 2120 struct mbuf *m; 2121 2122 ifp = &sc->ethercom.ec_if; 2123 2124 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 2125 offsetof(struct bge_ring_data, bge_status_block), 2126 sizeof (struct bge_status_block), 2127 BUS_DMASYNC_POSTREAD); 2128 2129 offset = offsetof(struct bge_ring_data, bge_tx_ring); 2130 tosync = sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx - 2131 sc->bge_tx_saved_considx; 2132 2133 toff = offset + (sc->bge_tx_saved_considx * sizeof (struct bge_tx_bd)); 2134 2135 if (tosync < 0) { 2136 tlen = (BGE_TX_RING_CNT - sc->bge_tx_saved_considx) * 2137 sizeof (struct bge_tx_bd); 2138 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 2139 toff, tlen, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2140 tosync = -tosync; 2141 } 2142 2143 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 2144 offset, tosync * sizeof (struct bge_tx_bd), 2145 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2146 2147 /* 2148 * Go through our tx ring and free mbufs for those 2149 * frames that have been sent. 2150 */ 2151 while (sc->bge_tx_saved_considx != 2152 sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx) { 2153 u_int32_t idx = 0; 2154 2155 idx = sc->bge_tx_saved_considx; 2156 cur_tx = &sc->bge_rdata->bge_tx_ring[idx]; 2157 if (cur_tx->bge_flags & BGE_TXBDFLAG_END) 2158 ifp->if_opackets++; 2159 m = sc->bge_cdata.bge_tx_chain[idx]; 2160 if (m != NULL) { 2161 sc->bge_cdata.bge_tx_chain[idx] = NULL; 2162 dma = sc->txdma[idx]; 2163 bus_dmamap_sync(sc->bge_dmatag, dma->dmamap, 0, 2164 dma->dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 2165 bus_dmamap_unload(sc->bge_dmatag, dma->dmamap); 2166 SLIST_INSERT_HEAD(&sc->txdma_list, dma, link); 2167 sc->txdma[idx] = NULL; 2168 2169 m_freem(m); 2170 } 2171 sc->bge_txcnt--; 2172 BGE_INC(sc->bge_tx_saved_considx, BGE_TX_RING_CNT); 2173 ifp->if_timer = 0; 2174 } 2175 2176 if (cur_tx != NULL) 2177 ifp->if_flags &= ~IFF_OACTIVE; 2178 } 2179 2180 int 2181 bge_intr(xsc) 2182 void *xsc; 2183 { 2184 struct bge_softc *sc; 2185 struct ifnet *ifp; 2186 2187 sc = xsc; 2188 ifp = &sc->ethercom.ec_if; 2189 2190 #ifdef notdef 2191 /* Avoid this for now -- checking this register is expensive. */ 2192 /* Make sure this is really our interrupt. */ 2193 if (!(CSR_READ_4(sc, BGE_MISC_LOCAL_CTL) & BGE_MLC_INTR_STATE)) 2194 return (0); 2195 #endif 2196 /* Ack interrupt and stop others from occuring. */ 2197 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 1); 2198 2199 /* 2200 * Process link state changes. 2201 * Grrr. The link status word in the status block does 2202 * not work correctly on the BCM5700 rev AX and BX chips, 2203 * according to all avaibable information. Hence, we have 2204 * to enable MII interrupts in order to properly obtain 2205 * async link changes. Unfortunately, this also means that 2206 * we have to read the MAC status register to detect link 2207 * changes, thereby adding an additional register access to 2208 * the interrupt handler. 2209 */ 2210 2211 if (BGE_IS_5700_Ax_Bx(sc->bge_asicrev)) { 2212 u_int32_t status; 2213 2214 status = CSR_READ_4(sc, BGE_MAC_STS); 2215 if (status & BGE_MACSTAT_MI_INTERRUPT) { 2216 sc->bge_link = 0; 2217 callout_stop(&sc->bge_timeout); 2218 bge_tick(sc); 2219 /* Clear the interrupt */ 2220 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, 2221 BGE_EVTENB_MI_INTERRUPT); 2222 bge_miibus_readreg(&sc->bge_dev, 1, BRGPHY_MII_ISR); 2223 bge_miibus_writereg(&sc->bge_dev, 1, BRGPHY_MII_IMR, 2224 BRGPHY_INTRS); 2225 } 2226 } else { 2227 if (sc->bge_rdata->bge_status_block.bge_status & 2228 BGE_STATFLAG_LINKSTATE_CHANGED) { 2229 sc->bge_link = 0; 2230 callout_stop(&sc->bge_timeout); 2231 bge_tick(sc); 2232 /* Clear the interrupt */ 2233 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED| 2234 BGE_MACSTAT_CFG_CHANGED); 2235 } 2236 } 2237 2238 if (ifp->if_flags & IFF_RUNNING) { 2239 /* Check RX return ring producer/consumer */ 2240 bge_rxeof(sc); 2241 2242 /* Check TX ring producer/consumer */ 2243 bge_txeof(sc); 2244 } 2245 2246 bge_handle_events(sc); 2247 2248 /* Re-enable interrupts. */ 2249 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 0); 2250 2251 if (ifp->if_flags & IFF_RUNNING && !IFQ_IS_EMPTY(&ifp->if_snd)) 2252 bge_start(ifp); 2253 2254 return (1); 2255 } 2256 2257 void 2258 bge_tick(xsc) 2259 void *xsc; 2260 { 2261 struct bge_softc *sc = xsc; 2262 struct mii_data *mii = &sc->bge_mii; 2263 struct ifmedia *ifm = NULL; 2264 struct ifnet *ifp = &sc->ethercom.ec_if; 2265 int s; 2266 2267 s = splnet(); 2268 2269 bge_stats_update(sc); 2270 callout_reset(&sc->bge_timeout, hz, bge_tick, sc); 2271 if (sc->bge_link) { 2272 splx(s); 2273 return; 2274 } 2275 2276 if (sc->bge_tbi) { 2277 ifm = &sc->bge_ifmedia; 2278 if (CSR_READ_4(sc, BGE_MAC_STS) & 2279 BGE_MACSTAT_TBI_PCS_SYNCHED) { 2280 sc->bge_link++; 2281 CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF); 2282 printf("%s: gigabit link up\n", sc->bge_dev.dv_xname); 2283 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 2284 bge_start(ifp); 2285 } 2286 splx(s); 2287 return; 2288 } 2289 2290 mii_tick(mii); 2291 2292 if (!sc->bge_link && mii->mii_media_status & IFM_ACTIVE && 2293 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 2294 sc->bge_link++; 2295 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T || 2296 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX) 2297 printf("%s: gigabit link up\n", sc->bge_dev.dv_xname); 2298 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 2299 bge_start(ifp); 2300 } 2301 2302 splx(s); 2303 } 2304 2305 void 2306 bge_stats_update(sc) 2307 struct bge_softc *sc; 2308 { 2309 struct ifnet *ifp = &sc->ethercom.ec_if; 2310 bus_size_t stats = BGE_MEMWIN_START + BGE_STATS_BLOCK; 2311 2312 #define READ_STAT(sc, stats, stat) \ 2313 CSR_READ_4(sc, stats + offsetof(struct bge_stats, stat)) 2314 2315 ifp->if_collisions += 2316 (READ_STAT(sc, stats, dot3StatsSingleCollisionFrames.bge_addr_lo) + 2317 READ_STAT(sc, stats, dot3StatsMultipleCollisionFrames.bge_addr_lo) + 2318 READ_STAT(sc, stats, dot3StatsExcessiveCollisions.bge_addr_lo) + 2319 READ_STAT(sc, stats, dot3StatsLateCollisions.bge_addr_lo)) - 2320 ifp->if_collisions; 2321 2322 #undef READ_STAT 2323 2324 #ifdef notdef 2325 ifp->if_collisions += 2326 (sc->bge_rdata->bge_info.bge_stats.dot3StatsSingleCollisionFrames + 2327 sc->bge_rdata->bge_info.bge_stats.dot3StatsMultipleCollisionFrames + 2328 sc->bge_rdata->bge_info.bge_stats.dot3StatsExcessiveCollisions + 2329 sc->bge_rdata->bge_info.bge_stats.dot3StatsLateCollisions) - 2330 ifp->if_collisions; 2331 #endif 2332 } 2333 2334 /* 2335 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data 2336 * pointers to descriptors. 2337 */ 2338 int 2339 bge_encap(sc, m_head, txidx) 2340 struct bge_softc *sc; 2341 struct mbuf *m_head; 2342 u_int32_t *txidx; 2343 { 2344 struct bge_tx_bd *f = NULL; 2345 u_int32_t frag, cur, cnt = 0; 2346 u_int16_t csum_flags = 0; 2347 struct txdmamap_pool_entry *dma; 2348 bus_dmamap_t dmamap; 2349 int i = 0; 2350 struct mbuf *n; 2351 2352 cur = frag = *txidx; 2353 2354 if (m_head->m_pkthdr.csum_flags) { 2355 if (m_head->m_pkthdr.csum_flags & M_CSUM_IPv4) 2356 csum_flags |= BGE_TXBDFLAG_IP_CSUM; 2357 if (m_head->m_pkthdr.csum_flags & (M_CSUM_TCPv4|M_CSUM_UDPv4)) 2358 csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM; 2359 } 2360 2361 dma = SLIST_FIRST(&sc->txdma_list); 2362 if (dma == NULL) 2363 return ENOBUFS; 2364 dmamap = dma->dmamap; 2365 2366 /* 2367 * Start packing the mbufs in this chain into 2368 * the fragment pointers. Stop when we run out 2369 * of fragments or hit the end of the mbuf chain. 2370 */ 2371 if (bus_dmamap_load_mbuf(sc->bge_dmatag, dmamap, m_head, 2372 BUS_DMA_NOWAIT)) 2373 return(ENOBUFS); 2374 2375 n = sc->ethercom.ec_nvlans ? 2376 m_aux_find(m_head, AF_LINK, ETHERTYPE_VLAN) : NULL; 2377 2378 for (i = 0; i < dmamap->dm_nsegs; i++) { 2379 f = &sc->bge_rdata->bge_tx_ring[frag]; 2380 if (sc->bge_cdata.bge_tx_chain[frag] != NULL) 2381 break; 2382 bge_set_hostaddr(&f->bge_addr, dmamap->dm_segs[i].ds_addr); 2383 f->bge_len = dmamap->dm_segs[i].ds_len; 2384 f->bge_flags = csum_flags; 2385 2386 if (n != NULL) { 2387 f->bge_flags |= BGE_TXBDFLAG_VLAN_TAG; 2388 f->bge_vlan_tag = *mtod(n, int *); 2389 } else { 2390 f->bge_vlan_tag = 0; 2391 } 2392 /* 2393 * Sanity check: avoid coming within 16 descriptors 2394 * of the end of the ring. 2395 */ 2396 if ((BGE_TX_RING_CNT - (sc->bge_txcnt + cnt)) < 16) 2397 return(ENOBUFS); 2398 cur = frag; 2399 BGE_INC(frag, BGE_TX_RING_CNT); 2400 cnt++; 2401 } 2402 2403 if (i < dmamap->dm_nsegs) 2404 return ENOBUFS; 2405 2406 bus_dmamap_sync(sc->bge_dmatag, dmamap, 0, dmamap->dm_mapsize, 2407 BUS_DMASYNC_PREWRITE); 2408 2409 if (frag == sc->bge_tx_saved_considx) 2410 return(ENOBUFS); 2411 2412 sc->bge_rdata->bge_tx_ring[cur].bge_flags |= BGE_TXBDFLAG_END; 2413 sc->bge_cdata.bge_tx_chain[cur] = m_head; 2414 SLIST_REMOVE_HEAD(&sc->txdma_list, link); 2415 sc->txdma[cur] = dma; 2416 sc->bge_txcnt += cnt; 2417 2418 *txidx = frag; 2419 2420 return(0); 2421 } 2422 2423 /* 2424 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 2425 * to the mbuf data regions directly in the transmit descriptors. 2426 */ 2427 void 2428 bge_start(ifp) 2429 struct ifnet *ifp; 2430 { 2431 struct bge_softc *sc; 2432 struct mbuf *m_head = NULL; 2433 u_int32_t prodidx = 0; 2434 int pkts = 0; 2435 2436 sc = ifp->if_softc; 2437 2438 if (!sc->bge_link && ifp->if_snd.ifq_len < 10) 2439 return; 2440 2441 prodidx = CSR_READ_4(sc, BGE_MBX_TX_HOST_PROD0_LO); 2442 2443 while(sc->bge_cdata.bge_tx_chain[prodidx] == NULL) { 2444 IFQ_POLL(&ifp->if_snd, m_head); 2445 if (m_head == NULL) 2446 break; 2447 2448 #if 0 2449 /* 2450 * XXX 2451 * safety overkill. If this is a fragmented packet chain 2452 * with delayed TCP/UDP checksums, then only encapsulate 2453 * it if we have enough descriptors to handle the entire 2454 * chain at once. 2455 * (paranoia -- may not actually be needed) 2456 */ 2457 if (m_head->m_flags & M_FIRSTFRAG && 2458 m_head->m_pkthdr.csum_flags & (CSUM_DELAY_DATA)) { 2459 if ((BGE_TX_RING_CNT - sc->bge_txcnt) < 2460 m_head->m_pkthdr.csum_data + 16) { 2461 ifp->if_flags |= IFF_OACTIVE; 2462 break; 2463 } 2464 } 2465 #endif 2466 2467 /* 2468 * Pack the data into the transmit ring. If we 2469 * don't have room, set the OACTIVE flag and wait 2470 * for the NIC to drain the ring. 2471 */ 2472 if (bge_encap(sc, m_head, &prodidx)) { 2473 ifp->if_flags |= IFF_OACTIVE; 2474 break; 2475 } 2476 2477 /* now we are committed to transmit the packet */ 2478 IFQ_DEQUEUE(&ifp->if_snd, m_head); 2479 pkts++; 2480 2481 #if NBPFILTER > 0 2482 /* 2483 * If there's a BPF listener, bounce a copy of this frame 2484 * to him. 2485 */ 2486 if (ifp->if_bpf) 2487 bpf_mtap(ifp->if_bpf, m_head); 2488 #endif 2489 } 2490 if (pkts == 0) 2491 return; 2492 2493 /* Transmit */ 2494 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); 2495 2496 /* 2497 * Set a timeout in case the chip goes out to lunch. 2498 */ 2499 ifp->if_timer = 5; 2500 } 2501 2502 /* 2503 * If we have a BCM5400 or BCM5401 PHY, we need to properly 2504 * program its internal DSP. Failing to do this can result in 2505 * massive packet loss at 1Gb speeds. 2506 */ 2507 void 2508 bge_phy_hack(sc) 2509 struct bge_softc *sc; 2510 { 2511 struct bge_bcom_hack bhack[] = { 2512 { BRGPHY_MII_AUXCTL, 0x4C20 }, 2513 { BRGPHY_MII_DSP_ADDR_REG, 0x0012 }, 2514 { BRGPHY_MII_DSP_RW_PORT, 0x1804 }, 2515 { BRGPHY_MII_DSP_ADDR_REG, 0x0013 }, 2516 { BRGPHY_MII_DSP_RW_PORT, 0x1204 }, 2517 { BRGPHY_MII_DSP_ADDR_REG, 0x8006 }, 2518 { BRGPHY_MII_DSP_RW_PORT, 0x0132 }, 2519 { BRGPHY_MII_DSP_ADDR_REG, 0x8006 }, 2520 { BRGPHY_MII_DSP_RW_PORT, 0x0232 }, 2521 { BRGPHY_MII_DSP_ADDR_REG, 0x201F }, 2522 { BRGPHY_MII_DSP_RW_PORT, 0x0A20 }, 2523 { 0, 0 } }; 2524 u_int16_t vid, did; 2525 int i; 2526 2527 vid = bge_miibus_readreg(&sc->bge_dev, 1, MII_PHYIDR1); 2528 did = bge_miibus_readreg(&sc->bge_dev, 1, MII_PHYIDR2); 2529 2530 if (MII_OUI(vid, did) == MII_OUI_BROADCOM && 2531 (MII_MODEL(did) == MII_MODEL_BROADCOM_BCM5400 || 2532 MII_MODEL(did) == MII_MODEL_BROADCOM_BCM5401)) { 2533 i = 0; 2534 while (bhack[i].reg) { 2535 bge_miibus_writereg(&sc->bge_dev, 1, bhack[i].reg, 2536 bhack[i].val); 2537 i++; 2538 } 2539 } 2540 } 2541 2542 int 2543 bge_init(ifp) 2544 struct ifnet *ifp; 2545 { 2546 struct bge_softc *sc = ifp->if_softc; 2547 u_int16_t *m; 2548 int s, error; 2549 2550 s = splnet(); 2551 2552 ifp = &sc->ethercom.ec_if; 2553 2554 /* Cancel pending I/O and flush buffers. */ 2555 bge_stop(sc); 2556 bge_reset(sc); 2557 bge_chipinit(sc); 2558 2559 /* 2560 * Init the various state machines, ring 2561 * control blocks and firmware. 2562 */ 2563 error = bge_blockinit(sc); 2564 if (error != 0) { 2565 printf("%s: initialization error %d\n", sc->bge_dev.dv_xname, 2566 error); 2567 splx(s); 2568 return error; 2569 } 2570 2571 ifp = &sc->ethercom.ec_if; 2572 2573 /* Specify MTU. */ 2574 CSR_WRITE_4(sc, BGE_RX_MTU, ifp->if_mtu + 2575 ETHER_HDR_LEN + ETHER_CRC_LEN); 2576 2577 /* Load our MAC address. */ 2578 m = (u_int16_t *)&(LLADDR(ifp->if_sadl)[0]); 2579 CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0])); 2580 CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, (htons(m[1]) << 16) | htons(m[2])); 2581 2582 /* Enable or disable promiscuous mode as needed. */ 2583 if (ifp->if_flags & IFF_PROMISC) { 2584 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 2585 } else { 2586 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 2587 } 2588 2589 /* Program multicast filter. */ 2590 bge_setmulti(sc); 2591 2592 /* Init RX ring. */ 2593 bge_init_rx_ring_std(sc); 2594 2595 /* Init jumbo RX ring. */ 2596 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 2597 bge_init_rx_ring_jumbo(sc); 2598 2599 /* Init our RX return ring index */ 2600 sc->bge_rx_saved_considx = 0; 2601 2602 /* Init TX ring. */ 2603 bge_init_tx_ring(sc); 2604 2605 /* Turn on transmitter */ 2606 BGE_SETBIT(sc, BGE_TX_MODE, BGE_TXMODE_ENABLE); 2607 2608 /* Turn on receiver */ 2609 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE); 2610 2611 /* Tell firmware we're alive. */ 2612 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 2613 2614 /* Enable host interrupts. */ 2615 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA); 2616 BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); 2617 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 0); 2618 2619 bge_ifmedia_upd(ifp); 2620 2621 ifp->if_flags |= IFF_RUNNING; 2622 ifp->if_flags &= ~IFF_OACTIVE; 2623 2624 splx(s); 2625 2626 callout_reset(&sc->bge_timeout, hz, bge_tick, sc); 2627 2628 return 0; 2629 } 2630 2631 /* 2632 * Set media options. 2633 */ 2634 int 2635 bge_ifmedia_upd(ifp) 2636 struct ifnet *ifp; 2637 { 2638 struct bge_softc *sc = ifp->if_softc; 2639 struct mii_data *mii = &sc->bge_mii; 2640 struct ifmedia *ifm = &sc->bge_ifmedia; 2641 2642 /* If this is a 1000baseX NIC, enable the TBI port. */ 2643 if (sc->bge_tbi) { 2644 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 2645 return(EINVAL); 2646 switch(IFM_SUBTYPE(ifm->ifm_media)) { 2647 case IFM_AUTO: 2648 break; 2649 case IFM_1000_SX: 2650 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 2651 BGE_CLRBIT(sc, BGE_MAC_MODE, 2652 BGE_MACMODE_HALF_DUPLEX); 2653 } else { 2654 BGE_SETBIT(sc, BGE_MAC_MODE, 2655 BGE_MACMODE_HALF_DUPLEX); 2656 } 2657 break; 2658 default: 2659 return(EINVAL); 2660 } 2661 return(0); 2662 } 2663 2664 sc->bge_link = 0; 2665 if (mii->mii_instance) { 2666 struct mii_softc *miisc; 2667 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL; 2668 miisc = LIST_NEXT(miisc, mii_list)) 2669 mii_phy_reset(miisc); 2670 } 2671 bge_phy_hack(sc); 2672 mii_mediachg(mii); 2673 2674 return(0); 2675 } 2676 2677 /* 2678 * Report current media status. 2679 */ 2680 void 2681 bge_ifmedia_sts(ifp, ifmr) 2682 struct ifnet *ifp; 2683 struct ifmediareq *ifmr; 2684 { 2685 struct bge_softc *sc = ifp->if_softc; 2686 struct mii_data *mii = &sc->bge_mii; 2687 2688 if (sc->bge_tbi) { 2689 ifmr->ifm_status = IFM_AVALID; 2690 ifmr->ifm_active = IFM_ETHER; 2691 if (CSR_READ_4(sc, BGE_MAC_STS) & 2692 BGE_MACSTAT_TBI_PCS_SYNCHED) 2693 ifmr->ifm_status |= IFM_ACTIVE; 2694 ifmr->ifm_active |= IFM_1000_SX; 2695 if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX) 2696 ifmr->ifm_active |= IFM_HDX; 2697 else 2698 ifmr->ifm_active |= IFM_FDX; 2699 return; 2700 } 2701 2702 mii_pollstat(mii); 2703 ifmr->ifm_active = mii->mii_media_active; 2704 ifmr->ifm_status = mii->mii_media_status; 2705 } 2706 2707 int 2708 bge_ioctl(ifp, command, data) 2709 struct ifnet *ifp; 2710 u_long command; 2711 caddr_t data; 2712 { 2713 struct bge_softc *sc = ifp->if_softc; 2714 struct ifreq *ifr = (struct ifreq *) data; 2715 int s, error = 0; 2716 struct mii_data *mii; 2717 2718 s = splnet(); 2719 2720 switch(command) { 2721 case SIOCSIFFLAGS: 2722 if (ifp->if_flags & IFF_UP) { 2723 /* 2724 * If only the state of the PROMISC flag changed, 2725 * then just use the 'set promisc mode' command 2726 * instead of reinitializing the entire NIC. Doing 2727 * a full re-init means reloading the firmware and 2728 * waiting for it to start up, which may take a 2729 * second or two. 2730 */ 2731 if (ifp->if_flags & IFF_RUNNING && 2732 ifp->if_flags & IFF_PROMISC && 2733 !(sc->bge_if_flags & IFF_PROMISC)) { 2734 BGE_SETBIT(sc, BGE_RX_MODE, 2735 BGE_RXMODE_RX_PROMISC); 2736 } else if (ifp->if_flags & IFF_RUNNING && 2737 !(ifp->if_flags & IFF_PROMISC) && 2738 sc->bge_if_flags & IFF_PROMISC) { 2739 BGE_CLRBIT(sc, BGE_RX_MODE, 2740 BGE_RXMODE_RX_PROMISC); 2741 } else 2742 bge_init(ifp); 2743 } else { 2744 if (ifp->if_flags & IFF_RUNNING) { 2745 bge_stop(sc); 2746 } 2747 } 2748 sc->bge_if_flags = ifp->if_flags; 2749 error = 0; 2750 break; 2751 case SIOCSIFMEDIA: 2752 case SIOCGIFMEDIA: 2753 if (sc->bge_tbi) { 2754 error = ifmedia_ioctl(ifp, ifr, &sc->bge_ifmedia, 2755 command); 2756 } else { 2757 mii = &sc->bge_mii; 2758 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, 2759 command); 2760 } 2761 error = 0; 2762 break; 2763 default: 2764 error = ether_ioctl(ifp, command, data); 2765 if (error == ENETRESET) { 2766 bge_setmulti(sc); 2767 error = 0; 2768 } 2769 break; 2770 } 2771 2772 splx(s); 2773 2774 return(error); 2775 } 2776 2777 void 2778 bge_watchdog(ifp) 2779 struct ifnet *ifp; 2780 { 2781 struct bge_softc *sc; 2782 2783 sc = ifp->if_softc; 2784 2785 printf("%s: watchdog timeout -- resetting\n", sc->bge_dev.dv_xname); 2786 2787 ifp->if_flags &= ~IFF_RUNNING; 2788 bge_init(ifp); 2789 2790 ifp->if_oerrors++; 2791 } 2792 2793 static void 2794 bge_stop_block(struct bge_softc *sc, bus_addr_t reg, uint32_t bit) 2795 { 2796 int i; 2797 2798 BGE_CLRBIT(sc, reg, bit); 2799 2800 for (i = 0; i < BGE_TIMEOUT; i++) { 2801 if ((CSR_READ_4(sc, reg) & bit) == 0) 2802 return; 2803 delay(100); 2804 } 2805 2806 printf("%s: block failed to stop: reg 0x%lx, bit 0x%08x\n", 2807 sc->bge_dev.dv_xname, (u_long) reg, bit); 2808 } 2809 2810 /* 2811 * Stop the adapter and free any mbufs allocated to the 2812 * RX and TX lists. 2813 */ 2814 void 2815 bge_stop(sc) 2816 struct bge_softc *sc; 2817 { 2818 struct ifnet *ifp = &sc->ethercom.ec_if; 2819 2820 callout_stop(&sc->bge_timeout); 2821 2822 /* 2823 * Disable all of the receiver blocks 2824 */ 2825 bge_stop_block(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE); 2826 bge_stop_block(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 2827 bge_stop_block(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 2828 bge_stop_block(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 2829 bge_stop_block(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE); 2830 bge_stop_block(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 2831 bge_stop_block(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE); 2832 2833 /* 2834 * Disable all of the transmit blocks 2835 */ 2836 bge_stop_block(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 2837 bge_stop_block(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 2838 bge_stop_block(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 2839 bge_stop_block(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE); 2840 bge_stop_block(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE); 2841 bge_stop_block(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 2842 bge_stop_block(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 2843 2844 /* 2845 * Shut down all of the memory managers and related 2846 * state machines. 2847 */ 2848 bge_stop_block(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE); 2849 bge_stop_block(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE); 2850 bge_stop_block(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 2851 2852 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 2853 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 2854 2855 bge_stop_block(sc, BGE_BMAN_MODE, BGE_BMANMODE_ENABLE); 2856 bge_stop_block(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 2857 2858 /* Disable host interrupts. */ 2859 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); 2860 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 1); 2861 2862 /* 2863 * Tell firmware we're shutting down. 2864 */ 2865 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 2866 2867 /* Free the RX lists. */ 2868 bge_free_rx_ring_std(sc); 2869 2870 /* Free jumbo RX list. */ 2871 bge_free_rx_ring_jumbo(sc); 2872 2873 /* Free TX buffers. */ 2874 bge_free_tx_ring(sc); 2875 2876 /* 2877 * Isolate/power down the PHY. 2878 */ 2879 if (!sc->bge_tbi) 2880 mii_down(&sc->bge_mii); 2881 2882 sc->bge_link = 0; 2883 2884 sc->bge_tx_saved_considx = BGE_TXCONS_UNSET; 2885 2886 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2887 } 2888 2889 /* 2890 * Stop all chip I/O so that the kernel's probe routines don't 2891 * get confused by errant DMAs when rebooting. 2892 */ 2893 void 2894 bge_shutdown(xsc) 2895 void *xsc; 2896 { 2897 struct bge_softc *sc = (struct bge_softc *)xsc; 2898 2899 bge_stop(sc); 2900 bge_reset(sc); 2901 } 2902
Indexes created Thu Sep 25 02:09:54 GMT 2025