if_bge.c revision 1.123
1 /* $NetBSD: if_bge.c,v 1.123 2007/02/09 21:55:27 ad Exp $ */ 2 3 /* 4 * Copyright (c) 2001 Wind River Systems 5 * Copyright (c) 1997, 1998, 1999, 2001 6 * Bill Paul <wpaul (at) windriver.com>. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Bill Paul. 19 * 4. Neither the name of the author nor the names of any co-contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 33 * THE POSSIBILITY OF SUCH DAMAGE. 34 * 35 * $FreeBSD: if_bge.c,v 1.13 2002/04/04 06:01:31 wpaul Exp $ 36 */ 37 38 /* 39 * Broadcom BCM570x family gigabit ethernet driver for NetBSD. 40 * 41 * NetBSD version by: 42 * 43 * Frank van der Linden <fvdl (at) wasabisystems.com> 44 * Jason Thorpe <thorpej (at) wasabisystems.com> 45 * Jonathan Stone <jonathan (at) dsg.stanford.edu> 46 * 47 * Originally written for FreeBSD by Bill Paul <wpaul (at) windriver.com> 48 * Senior Engineer, Wind River Systems 49 */ 50 51 /* 52 * The Broadcom BCM5700 is based on technology originally developed by 53 * Alteon Networks as part of the Tigon I and Tigon II gigabit ethernet 54 * MAC chips. The BCM5700, sometimes refered to as the Tigon III, has 55 * two on-board MIPS R4000 CPUs and can have as much as 16MB of external 56 * SSRAM. The BCM5700 supports TCP, UDP and IP checksum offload, jumbo 57 * frames, highly configurable RX filtering, and 16 RX and TX queues 58 * (which, along with RX filter rules, can be used for QOS applications). 59 * Other features, such as TCP segmentation, may be available as part 60 * of value-added firmware updates. Unlike the Tigon I and Tigon II, 61 * firmware images can be stored in hardware and need not be compiled 62 * into the driver. 63 * 64 * The BCM5700 supports the PCI v2.2 and PCI-X v1.0 standards, and will 65 * function in a 32-bit/64-bit 33/66MHz bus, or a 64-bit/133MHz bus. 66 * 67 * The BCM5701 is a single-chip solution incorporating both the BCM5700 68 * MAC and a BCM5401 10/100/1000 PHY. Unlike the BCM5700, the BCM5701 69 * does not support external SSRAM. 70 * 71 * Broadcom also produces a variation of the BCM5700 under the "Altima" 72 * brand name, which is functionally similar but lacks PCI-X support. 73 * 74 * Without external SSRAM, you can only have at most 4 TX rings, 75 * and the use of the mini RX ring is disabled. This seems to imply 76 * that these features are simply not available on the BCM5701. As a 77 * result, this driver does not implement any support for the mini RX 78 * ring. 79 */ 80 81 #include <sys/cdefs.h> 82 __KERNEL_RCSID(0, "$NetBSD: if_bge.c,v 1.123 2007/02/09 21:55:27 ad Exp $"); 83 84 #include "bpfilter.h" 85 #include "vlan.h" 86 87 #include <sys/param.h> 88 #include <sys/systm.h> 89 #include <sys/callout.h> 90 #include <sys/sockio.h> 91 #include <sys/mbuf.h> 92 #include <sys/malloc.h> 93 #include <sys/kernel.h> 94 #include <sys/device.h> 95 #include <sys/socket.h> 96 #include <sys/sysctl.h> 97 98 #include <net/if.h> 99 #include <net/if_dl.h> 100 #include <net/if_media.h> 101 #include <net/if_ether.h> 102 103 #ifdef INET 104 #include <netinet/in.h> 105 #include <netinet/in_systm.h> 106 #include <netinet/in_var.h> 107 #include <netinet/ip.h> 108 #endif 109 110 /* Headers for TCP Segmentation Offload (TSO) */ 111 #include <netinet/in_systm.h> /* n_time for <netinet/ip.h>... */ 112 #include <netinet/in.h> /* ip_{src,dst}, for <netinet/ip.h> */ 113 #include <netinet/ip.h> /* for struct ip */ 114 #include <netinet/tcp.h> /* for struct tcphdr */ 115 116 117 #if NBPFILTER > 0 118 #include <net/bpf.h> 119 #endif 120 121 #include <dev/pci/pcireg.h> 122 #include <dev/pci/pcivar.h> 123 #include <dev/pci/pcidevs.h> 124 125 #include <dev/mii/mii.h> 126 #include <dev/mii/miivar.h> 127 #include <dev/mii/miidevs.h> 128 #include <dev/mii/brgphyreg.h> 129 130 #include <dev/pci/if_bgereg.h> 131 132 #include <uvm/uvm_extern.h> 133 134 #define ETHER_MIN_NOPAD (ETHER_MIN_LEN - ETHER_CRC_LEN) /* i.e., 60 */ 135 136 137 /* 138 * Tunable thresholds for rx-side bge interrupt mitigation. 139 */ 140 141 /* 142 * The pairs of values below were obtained from empirical measurement 143 * on bcm5700 rev B2; they ar designed to give roughly 1 receive 144 * interrupt for every N packets received, where N is, approximately, 145 * the second value (rx_max_bds) in each pair. The values are chosen 146 * such that moving from one pair to the succeeding pair was observed 147 * to roughly halve interrupt rate under sustained input packet load. 148 * The values were empirically chosen to avoid overflowing internal 149 * limits on the bcm5700: inreasing rx_ticks much beyond 600 150 * results in internal wrapping and higher interrupt rates. 151 * The limit of 46 frames was chosen to match NFS workloads. 152 * 153 * These values also work well on bcm5701, bcm5704C, and (less 154 * tested) bcm5703. On other chipsets, (including the Altima chip 155 * family), the larger values may overflow internal chip limits, 156 * leading to increasing interrupt rates rather than lower interrupt 157 * rates. 158 * 159 * Applications using heavy interrupt mitigation (interrupting every 160 * 32 or 46 frames) in both directions may need to increase the TCP 161 * windowsize to above 131072 bytes (e.g., to 199608 bytes) to sustain 162 * full link bandwidth, due to ACKs and window updates lingering 163 * in the RX queue during the 30-to-40-frame interrupt-mitigation window. 164 */ 165 static const struct bge_load_rx_thresh { 166 int rx_ticks; 167 int rx_max_bds; } 168 bge_rx_threshes[] = { 169 { 32, 2 }, 170 { 50, 4 }, 171 { 100, 8 }, 172 { 192, 16 }, 173 { 416, 32 }, 174 { 598, 46 } 175 }; 176 #define NBGE_RX_THRESH (sizeof(bge_rx_threshes) / sizeof(bge_rx_threshes[0])) 177 178 /* XXX patchable; should be sysctl'able */ 179 static int bge_auto_thresh = 1; 180 static int bge_rx_thresh_lvl; 181 182 static int bge_rxthresh_nodenum; 183 184 static int bge_probe(device_t, cfdata_t, void *); 185 static void bge_attach(device_t, device_t, void *); 186 static void bge_powerhook(int, void *); 187 static void bge_release_resources(struct bge_softc *); 188 static void bge_txeof(struct bge_softc *); 189 static void bge_rxeof(struct bge_softc *); 190 191 static void bge_tick(void *); 192 static void bge_stats_update(struct bge_softc *); 193 static int bge_encap(struct bge_softc *, struct mbuf *, u_int32_t *); 194 195 static int bge_intr(void *); 196 static void bge_start(struct ifnet *); 197 static int bge_ioctl(struct ifnet *, u_long, caddr_t); 198 static int bge_init(struct ifnet *); 199 static void bge_stop(struct bge_softc *); 200 static void bge_watchdog(struct ifnet *); 201 static void bge_shutdown(void *); 202 static int bge_ifmedia_upd(struct ifnet *); 203 static void bge_ifmedia_sts(struct ifnet *, struct ifmediareq *); 204 205 static void bge_setmulti(struct bge_softc *); 206 207 static void bge_handle_events(struct bge_softc *); 208 static int bge_alloc_jumbo_mem(struct bge_softc *); 209 #if 0 /* XXX */ 210 static void bge_free_jumbo_mem(struct bge_softc *); 211 #endif 212 static void *bge_jalloc(struct bge_softc *); 213 static void bge_jfree(struct mbuf *, caddr_t, size_t, void *); 214 static int bge_newbuf_std(struct bge_softc *, int, struct mbuf *, 215 bus_dmamap_t); 216 static int bge_newbuf_jumbo(struct bge_softc *, int, struct mbuf *); 217 static int bge_init_rx_ring_std(struct bge_softc *); 218 static void bge_free_rx_ring_std(struct bge_softc *); 219 static int bge_init_rx_ring_jumbo(struct bge_softc *); 220 static void bge_free_rx_ring_jumbo(struct bge_softc *); 221 static void bge_free_tx_ring(struct bge_softc *); 222 static int bge_init_tx_ring(struct bge_softc *); 223 224 static int bge_chipinit(struct bge_softc *); 225 static int bge_blockinit(struct bge_softc *); 226 static int bge_setpowerstate(struct bge_softc *, int); 227 228 static void bge_reset(struct bge_softc *); 229 230 #define BGE_DEBUG 231 #ifdef BGE_DEBUG 232 #define DPRINTF(x) if (bgedebug) printf x 233 #define DPRINTFN(n,x) if (bgedebug >= (n)) printf x 234 #define BGE_TSO_PRINTF(x) do { if (bge_tso_debug) printf x ;} while (0) 235 int bgedebug = 0; 236 int bge_tso_debug = 0; 237 #else 238 #define DPRINTF(x) 239 #define DPRINTFN(n,x) 240 #define BGE_TSO_PRINTF(x) 241 #endif 242 243 #ifdef BGE_EVENT_COUNTERS 244 #define BGE_EVCNT_INCR(ev) (ev).ev_count++ 245 #define BGE_EVCNT_ADD(ev, val) (ev).ev_count += (val) 246 #define BGE_EVCNT_UPD(ev, val) (ev).ev_count = (val) 247 #else 248 #define BGE_EVCNT_INCR(ev) /* nothing */ 249 #define BGE_EVCNT_ADD(ev, val) /* nothing */ 250 #define BGE_EVCNT_UPD(ev, val) /* nothing */ 251 #endif 252 253 /* Various chip quirks. */ 254 #define BGE_QUIRK_LINK_STATE_BROKEN 0x00000001 255 #define BGE_QUIRK_CSUM_BROKEN 0x00000002 256 #define BGE_QUIRK_ONLY_PHY_1 0x00000004 257 #define BGE_QUIRK_5700_SMALLDMA 0x00000008 258 #define BGE_QUIRK_5700_PCIX_REG_BUG 0x00000010 259 #define BGE_QUIRK_PRODUCER_BUG 0x00000020 260 #define BGE_QUIRK_PCIX_DMA_ALIGN_BUG 0x00000040 261 #define BGE_QUIRK_5705_CORE 0x00000080 262 #define BGE_QUIRK_FEWER_MBUFS 0x00000100 263 264 /* 265 * XXX: how to handle variants based on 5750 and derivatives: 266 * 5750 5751, 5721, possibly 5714, 5752, and 5708?, which 267 * in general behave like a 5705, except with additional quirks. 268 * This driver's current handling of the 5721 is wrong; 269 * how we map ASIC revision to "quirks" needs more thought. 270 * (defined here until the thought is done). 271 */ 272 #define BGE_IS_5714_FAMILY(sc) \ 273 (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5714_A0 || \ 274 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5780 || \ 275 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5714 ) 276 277 #define BGE_IS_5750_OR_BEYOND(sc) \ 278 (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5750 || \ 279 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5752 || \ 280 BGE_IS_5714_FAMILY(sc) ) 281 282 #define BGE_IS_5705_OR_BEYOND(sc) \ 283 ( ((sc)->bge_quirks & BGE_QUIRK_5705_CORE) || \ 284 BGE_IS_5750_OR_BEYOND(sc) ) 285 286 287 /* following bugs are common to bcm5700 rev B, all flavours */ 288 #define BGE_QUIRK_5700_COMMON \ 289 (BGE_QUIRK_5700_SMALLDMA|BGE_QUIRK_PRODUCER_BUG) 290 291 CFATTACH_DECL(bge, sizeof(struct bge_softc), 292 bge_probe, bge_attach, NULL, NULL); 293 294 static u_int32_t 295 bge_readmem_ind(struct bge_softc *sc, int off) 296 { 297 struct pci_attach_args *pa = &(sc->bge_pa); 298 pcireg_t val; 299 300 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_MEMWIN_BASEADDR, off); 301 val = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_MEMWIN_DATA); 302 return val; 303 } 304 305 static void 306 bge_writemem_ind(struct bge_softc *sc, int off, int val) 307 { 308 struct pci_attach_args *pa = &(sc->bge_pa); 309 310 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_MEMWIN_BASEADDR, off); 311 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_MEMWIN_DATA, val); 312 } 313 314 #ifdef notdef 315 static u_int32_t 316 bge_readreg_ind(struct bge_softc *sc, int off) 317 { 318 struct pci_attach_args *pa = &(sc->bge_pa); 319 320 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_REG_BASEADDR, off); 321 return(pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_REG_DATA)); 322 } 323 #endif 324 325 static void 326 bge_writereg_ind(struct bge_softc *sc, int off, int val) 327 { 328 struct pci_attach_args *pa = &(sc->bge_pa); 329 330 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_REG_BASEADDR, off); 331 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_REG_DATA, val); 332 } 333 334 #ifdef notdef 335 static u_int8_t 336 bge_vpd_readbyte(struct bge_softc *sc, int addr) 337 { 338 int i; 339 u_int32_t val; 340 struct pci_attach_args *pa = &(sc->bge_pa); 341 342 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_VPD_ADDR, addr); 343 for (i = 0; i < BGE_TIMEOUT * 10; i++) { 344 DELAY(10); 345 if (pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_VPD_ADDR) & 346 BGE_VPD_FLAG) 347 break; 348 } 349 350 if (i == BGE_TIMEOUT) { 351 printf("%s: VPD read timed out\n", sc->bge_dev.dv_xname); 352 return(0); 353 } 354 355 val = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_VPD_DATA); 356 357 return((val >> ((addr % 4) * 8)) & 0xFF); 358 } 359 360 static void 361 bge_vpd_read_res(struct bge_softc *sc, struct vpd_res *res, int addr) 362 { 363 int i; 364 u_int8_t *ptr; 365 366 ptr = (u_int8_t *)res; 367 for (i = 0; i < sizeof(struct vpd_res); i++) 368 ptr[i] = bge_vpd_readbyte(sc, i + addr); 369 } 370 371 static void 372 bge_vpd_read(struct bge_softc *sc) 373 { 374 int pos = 0, i; 375 struct vpd_res res; 376 377 if (sc->bge_vpd_prodname != NULL) 378 free(sc->bge_vpd_prodname, M_DEVBUF); 379 if (sc->bge_vpd_readonly != NULL) 380 free(sc->bge_vpd_readonly, M_DEVBUF); 381 sc->bge_vpd_prodname = NULL; 382 sc->bge_vpd_readonly = NULL; 383 384 bge_vpd_read_res(sc, &res, pos); 385 386 if (res.vr_id != VPD_RES_ID) { 387 printf("%s: bad VPD resource id: expected %x got %x\n", 388 sc->bge_dev.dv_xname, VPD_RES_ID, res.vr_id); 389 return; 390 } 391 392 pos += sizeof(res); 393 sc->bge_vpd_prodname = malloc(res.vr_len + 1, M_DEVBUF, M_NOWAIT); 394 if (sc->bge_vpd_prodname == NULL) 395 panic("bge_vpd_read"); 396 for (i = 0; i < res.vr_len; i++) 397 sc->bge_vpd_prodname[i] = bge_vpd_readbyte(sc, i + pos); 398 sc->bge_vpd_prodname[i] = '\0'; 399 pos += i; 400 401 bge_vpd_read_res(sc, &res, pos); 402 403 if (res.vr_id != VPD_RES_READ) { 404 printf("%s: bad VPD resource id: expected %x got %x\n", 405 sc->bge_dev.dv_xname, VPD_RES_READ, res.vr_id); 406 return; 407 } 408 409 pos += sizeof(res); 410 sc->bge_vpd_readonly = malloc(res.vr_len, M_DEVBUF, M_NOWAIT); 411 if (sc->bge_vpd_readonly == NULL) 412 panic("bge_vpd_read"); 413 for (i = 0; i < res.vr_len + 1; i++) 414 sc->bge_vpd_readonly[i] = bge_vpd_readbyte(sc, i + pos); 415 } 416 #endif 417 418 /* 419 * Read a byte of data stored in the EEPROM at address 'addr.' The 420 * BCM570x supports both the traditional bitbang interface and an 421 * auto access interface for reading the EEPROM. We use the auto 422 * access method. 423 */ 424 static u_int8_t 425 bge_eeprom_getbyte(struct bge_softc *sc, int addr, u_int8_t *dest) 426 { 427 int i; 428 u_int32_t byte = 0; 429 430 /* 431 * Enable use of auto EEPROM access so we can avoid 432 * having to use the bitbang method. 433 */ 434 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM); 435 436 /* Reset the EEPROM, load the clock period. */ 437 CSR_WRITE_4(sc, BGE_EE_ADDR, 438 BGE_EEADDR_RESET|BGE_EEHALFCLK(BGE_HALFCLK_384SCL)); 439 DELAY(20); 440 441 /* Issue the read EEPROM command. */ 442 CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr); 443 444 /* Wait for completion */ 445 for(i = 0; i < BGE_TIMEOUT * 10; i++) { 446 DELAY(10); 447 if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE) 448 break; 449 } 450 451 if (i == BGE_TIMEOUT) { 452 printf("%s: eeprom read timed out\n", sc->bge_dev.dv_xname); 453 return(0); 454 } 455 456 /* Get result. */ 457 byte = CSR_READ_4(sc, BGE_EE_DATA); 458 459 *dest = (byte >> ((addr % 4) * 8)) & 0xFF; 460 461 return(0); 462 } 463 464 /* 465 * Read a sequence of bytes from the EEPROM. 466 */ 467 static int 468 bge_read_eeprom(struct bge_softc *sc, caddr_t dest, int off, int cnt) 469 { 470 int err = 0, i; 471 u_int8_t byte = 0; 472 473 for (i = 0; i < cnt; i++) { 474 err = bge_eeprom_getbyte(sc, off + i, &byte); 475 if (err) 476 break; 477 *(dest + i) = byte; 478 } 479 480 return(err ? 1 : 0); 481 } 482 483 static int 484 bge_miibus_readreg(device_t dev, int phy, int reg) 485 { 486 struct bge_softc *sc = (struct bge_softc *)dev; 487 u_int32_t val; 488 u_int32_t saved_autopoll; 489 int i; 490 491 /* 492 * Several chips with builtin PHYs will incorrectly answer to 493 * other PHY instances than the builtin PHY at id 1. 494 */ 495 if (phy != 1 && (sc->bge_quirks & BGE_QUIRK_ONLY_PHY_1)) 496 return(0); 497 498 /* Reading with autopolling on may trigger PCI errors */ 499 saved_autopoll = CSR_READ_4(sc, BGE_MI_MODE); 500 if (saved_autopoll & BGE_MIMODE_AUTOPOLL) { 501 CSR_WRITE_4(sc, BGE_MI_MODE, 502 saved_autopoll &~ BGE_MIMODE_AUTOPOLL); 503 DELAY(40); 504 } 505 506 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_READ|BGE_MICOMM_BUSY| 507 BGE_MIPHY(phy)|BGE_MIREG(reg)); 508 509 for (i = 0; i < BGE_TIMEOUT; i++) { 510 val = CSR_READ_4(sc, BGE_MI_COMM); 511 if (!(val & BGE_MICOMM_BUSY)) 512 break; 513 delay(10); 514 } 515 516 if (i == BGE_TIMEOUT) { 517 printf("%s: PHY read timed out\n", sc->bge_dev.dv_xname); 518 val = 0; 519 goto done; 520 } 521 522 val = CSR_READ_4(sc, BGE_MI_COMM); 523 524 done: 525 if (saved_autopoll & BGE_MIMODE_AUTOPOLL) { 526 CSR_WRITE_4(sc, BGE_MI_MODE, saved_autopoll); 527 DELAY(40); 528 } 529 530 if (val & BGE_MICOMM_READFAIL) 531 return(0); 532 533 return(val & 0xFFFF); 534 } 535 536 static void 537 bge_miibus_writereg(device_t dev, int phy, int reg, int val) 538 { 539 struct bge_softc *sc = (struct bge_softc *)dev; 540 u_int32_t saved_autopoll; 541 int i; 542 543 /* Touching the PHY while autopolling is on may trigger PCI errors */ 544 saved_autopoll = CSR_READ_4(sc, BGE_MI_MODE); 545 if (saved_autopoll & BGE_MIMODE_AUTOPOLL) { 546 delay(40); 547 CSR_WRITE_4(sc, BGE_MI_MODE, 548 saved_autopoll & (~BGE_MIMODE_AUTOPOLL)); 549 delay(10); /* 40 usec is supposed to be adequate */ 550 } 551 552 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_WRITE|BGE_MICOMM_BUSY| 553 BGE_MIPHY(phy)|BGE_MIREG(reg)|val); 554 555 for (i = 0; i < BGE_TIMEOUT; i++) { 556 if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY)) 557 break; 558 delay(10); 559 } 560 561 if (saved_autopoll & BGE_MIMODE_AUTOPOLL) { 562 CSR_WRITE_4(sc, BGE_MI_MODE, saved_autopoll); 563 delay(40); 564 } 565 566 if (i == BGE_TIMEOUT) { 567 printf("%s: PHY read timed out\n", sc->bge_dev.dv_xname); 568 } 569 } 570 571 static void 572 bge_miibus_statchg(device_t dev) 573 { 574 struct bge_softc *sc = (struct bge_softc *)dev; 575 struct mii_data *mii = &sc->bge_mii; 576 577 /* 578 * Get flow control negotiation result. 579 */ 580 if (IFM_SUBTYPE(mii->mii_media.ifm_cur->ifm_media) == IFM_AUTO && 581 (mii->mii_media_active & IFM_ETH_FMASK) != sc->bge_flowflags) { 582 sc->bge_flowflags = mii->mii_media_active & IFM_ETH_FMASK; 583 mii->mii_media_active &= ~IFM_ETH_FMASK; 584 } 585 586 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_PORTMODE); 587 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) { 588 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_GMII); 589 } else { 590 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_MII); 591 } 592 593 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 594 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX); 595 } else { 596 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX); 597 } 598 599 /* 600 * 802.3x flow control 601 */ 602 if (sc->bge_flowflags & IFM_ETH_RXPAUSE) { 603 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_FLOWCTL_ENABLE); 604 } else { 605 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_FLOWCTL_ENABLE); 606 } 607 if (sc->bge_flowflags & IFM_ETH_TXPAUSE) { 608 BGE_SETBIT(sc, BGE_TX_MODE, BGE_TXMODE_FLOWCTL_ENABLE); 609 } else { 610 BGE_CLRBIT(sc, BGE_TX_MODE, BGE_TXMODE_FLOWCTL_ENABLE); 611 } 612 } 613 614 /* 615 * Update rx threshold levels to values in a particular slot 616 * of the interrupt-mitigation table bge_rx_threshes. 617 */ 618 static void 619 bge_set_thresh(struct ifnet *ifp, int lvl) 620 { 621 struct bge_softc *sc = ifp->if_softc; 622 int s; 623 624 /* For now, just save the new Rx-intr thresholds and record 625 * that a threshold update is pending. Updating the hardware 626 * registers here (even at splhigh()) is observed to 627 * occasionaly cause glitches where Rx-interrupts are not 628 * honoured for up to 10 seconds. jonathan (at) NetBSD.org, 2003-04-05 629 */ 630 s = splnet(); 631 sc->bge_rx_coal_ticks = bge_rx_threshes[lvl].rx_ticks; 632 sc->bge_rx_max_coal_bds = bge_rx_threshes[lvl].rx_max_bds; 633 sc->bge_pending_rxintr_change = 1; 634 splx(s); 635 636 return; 637 } 638 639 640 /* 641 * Update Rx thresholds of all bge devices 642 */ 643 static void 644 bge_update_all_threshes(int lvl) 645 { 646 struct ifnet *ifp; 647 const char * const namebuf = "bge"; 648 int namelen; 649 650 if (lvl < 0) 651 lvl = 0; 652 else if( lvl >= NBGE_RX_THRESH) 653 lvl = NBGE_RX_THRESH - 1; 654 655 namelen = strlen(namebuf); 656 /* 657 * Now search all the interfaces for this name/number 658 */ 659 IFNET_FOREACH(ifp) { 660 if (strncmp(ifp->if_xname, namebuf, namelen) != 0) 661 continue; 662 /* We got a match: update if doing auto-threshold-tuning */ 663 if (bge_auto_thresh) 664 bge_set_thresh(ifp, lvl); 665 } 666 } 667 668 /* 669 * Handle events that have triggered interrupts. 670 */ 671 static void 672 bge_handle_events(struct bge_softc *sc) 673 { 674 675 return; 676 } 677 678 /* 679 * Memory management for jumbo frames. 680 */ 681 682 static int 683 bge_alloc_jumbo_mem(struct bge_softc *sc) 684 { 685 caddr_t ptr, kva; 686 bus_dma_segment_t seg; 687 int i, rseg, state, error; 688 struct bge_jpool_entry *entry; 689 690 state = error = 0; 691 692 /* Grab a big chunk o' storage. */ 693 if (bus_dmamem_alloc(sc->bge_dmatag, BGE_JMEM, PAGE_SIZE, 0, 694 &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 695 printf("%s: can't alloc rx buffers\n", sc->bge_dev.dv_xname); 696 return ENOBUFS; 697 } 698 699 state = 1; 700 if (bus_dmamem_map(sc->bge_dmatag, &seg, rseg, BGE_JMEM, &kva, 701 BUS_DMA_NOWAIT)) { 702 printf("%s: can't map DMA buffers (%d bytes)\n", 703 sc->bge_dev.dv_xname, (int)BGE_JMEM); 704 error = ENOBUFS; 705 goto out; 706 } 707 708 state = 2; 709 if (bus_dmamap_create(sc->bge_dmatag, BGE_JMEM, 1, BGE_JMEM, 0, 710 BUS_DMA_NOWAIT, &sc->bge_cdata.bge_rx_jumbo_map)) { 711 printf("%s: can't create DMA map\n", sc->bge_dev.dv_xname); 712 error = ENOBUFS; 713 goto out; 714 } 715 716 state = 3; 717 if (bus_dmamap_load(sc->bge_dmatag, sc->bge_cdata.bge_rx_jumbo_map, 718 kva, BGE_JMEM, NULL, BUS_DMA_NOWAIT)) { 719 printf("%s: can't load DMA map\n", sc->bge_dev.dv_xname); 720 error = ENOBUFS; 721 goto out; 722 } 723 724 state = 4; 725 sc->bge_cdata.bge_jumbo_buf = (caddr_t)kva; 726 DPRINTFN(1,("bge_jumbo_buf = %p\n", sc->bge_cdata.bge_jumbo_buf)); 727 728 SLIST_INIT(&sc->bge_jfree_listhead); 729 SLIST_INIT(&sc->bge_jinuse_listhead); 730 731 /* 732 * Now divide it up into 9K pieces and save the addresses 733 * in an array. 734 */ 735 ptr = sc->bge_cdata.bge_jumbo_buf; 736 for (i = 0; i < BGE_JSLOTS; i++) { 737 sc->bge_cdata.bge_jslots[i] = ptr; 738 ptr += BGE_JLEN; 739 entry = malloc(sizeof(struct bge_jpool_entry), 740 M_DEVBUF, M_NOWAIT); 741 if (entry == NULL) { 742 printf("%s: no memory for jumbo buffer queue!\n", 743 sc->bge_dev.dv_xname); 744 error = ENOBUFS; 745 goto out; 746 } 747 entry->slot = i; 748 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, 749 entry, jpool_entries); 750 } 751 out: 752 if (error != 0) { 753 switch (state) { 754 case 4: 755 bus_dmamap_unload(sc->bge_dmatag, 756 sc->bge_cdata.bge_rx_jumbo_map); 757 case 3: 758 bus_dmamap_destroy(sc->bge_dmatag, 759 sc->bge_cdata.bge_rx_jumbo_map); 760 case 2: 761 bus_dmamem_unmap(sc->bge_dmatag, kva, BGE_JMEM); 762 case 1: 763 bus_dmamem_free(sc->bge_dmatag, &seg, rseg); 764 break; 765 default: 766 break; 767 } 768 } 769 770 return error; 771 } 772 773 /* 774 * Allocate a jumbo buffer. 775 */ 776 static void * 777 bge_jalloc(struct bge_softc *sc) 778 { 779 struct bge_jpool_entry *entry; 780 781 entry = SLIST_FIRST(&sc->bge_jfree_listhead); 782 783 if (entry == NULL) { 784 printf("%s: no free jumbo buffers\n", sc->bge_dev.dv_xname); 785 return(NULL); 786 } 787 788 SLIST_REMOVE_HEAD(&sc->bge_jfree_listhead, jpool_entries); 789 SLIST_INSERT_HEAD(&sc->bge_jinuse_listhead, entry, jpool_entries); 790 return(sc->bge_cdata.bge_jslots[entry->slot]); 791 } 792 793 /* 794 * Release a jumbo buffer. 795 */ 796 static void 797 bge_jfree(struct mbuf *m, caddr_t buf, size_t size, void *arg) 798 { 799 struct bge_jpool_entry *entry; 800 struct bge_softc *sc; 801 int i, s; 802 803 /* Extract the softc struct pointer. */ 804 sc = (struct bge_softc *)arg; 805 806 if (sc == NULL) 807 panic("bge_jfree: can't find softc pointer!"); 808 809 /* calculate the slot this buffer belongs to */ 810 811 i = ((caddr_t)buf 812 - (caddr_t)sc->bge_cdata.bge_jumbo_buf) / BGE_JLEN; 813 814 if ((i < 0) || (i >= BGE_JSLOTS)) 815 panic("bge_jfree: asked to free buffer that we don't manage!"); 816 817 s = splvm(); 818 entry = SLIST_FIRST(&sc->bge_jinuse_listhead); 819 if (entry == NULL) 820 panic("bge_jfree: buffer not in use!"); 821 entry->slot = i; 822 SLIST_REMOVE_HEAD(&sc->bge_jinuse_listhead, jpool_entries); 823 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, entry, jpool_entries); 824 825 if (__predict_true(m != NULL)) 826 pool_cache_put(&mbpool_cache, m); 827 splx(s); 828 } 829 830 831 /* 832 * Intialize a standard receive ring descriptor. 833 */ 834 static int 835 bge_newbuf_std(struct bge_softc *sc, int i, struct mbuf *m, bus_dmamap_t dmamap) 836 { 837 struct mbuf *m_new = NULL; 838 struct bge_rx_bd *r; 839 int error; 840 841 if (dmamap == NULL) { 842 error = bus_dmamap_create(sc->bge_dmatag, MCLBYTES, 1, 843 MCLBYTES, 0, BUS_DMA_NOWAIT, &dmamap); 844 if (error != 0) 845 return error; 846 } 847 848 sc->bge_cdata.bge_rx_std_map[i] = dmamap; 849 850 if (m == NULL) { 851 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 852 if (m_new == NULL) { 853 return(ENOBUFS); 854 } 855 856 MCLGET(m_new, M_DONTWAIT); 857 if (!(m_new->m_flags & M_EXT)) { 858 m_freem(m_new); 859 return(ENOBUFS); 860 } 861 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 862 if (!sc->bge_rx_alignment_bug) 863 m_adj(m_new, ETHER_ALIGN); 864 865 if (bus_dmamap_load_mbuf(sc->bge_dmatag, dmamap, m_new, 866 BUS_DMA_READ|BUS_DMA_NOWAIT)) 867 return(ENOBUFS); 868 } else { 869 m_new = m; 870 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 871 m_new->m_data = m_new->m_ext.ext_buf; 872 if (!sc->bge_rx_alignment_bug) 873 m_adj(m_new, ETHER_ALIGN); 874 } 875 876 sc->bge_cdata.bge_rx_std_chain[i] = m_new; 877 r = &sc->bge_rdata->bge_rx_std_ring[i]; 878 bge_set_hostaddr(&r->bge_addr, 879 dmamap->dm_segs[0].ds_addr); 880 r->bge_flags = BGE_RXBDFLAG_END; 881 r->bge_len = m_new->m_len; 882 r->bge_idx = i; 883 884 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 885 offsetof(struct bge_ring_data, bge_rx_std_ring) + 886 i * sizeof (struct bge_rx_bd), 887 sizeof (struct bge_rx_bd), 888 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 889 890 return(0); 891 } 892 893 /* 894 * Initialize a jumbo receive ring descriptor. This allocates 895 * a jumbo buffer from the pool managed internally by the driver. 896 */ 897 static int 898 bge_newbuf_jumbo(struct bge_softc *sc, int i, struct mbuf *m) 899 { 900 struct mbuf *m_new = NULL; 901 struct bge_rx_bd *r; 902 903 if (m == NULL) { 904 caddr_t buf = NULL; 905 906 /* Allocate the mbuf. */ 907 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 908 if (m_new == NULL) { 909 return(ENOBUFS); 910 } 911 912 /* Allocate the jumbo buffer */ 913 buf = bge_jalloc(sc); 914 if (buf == NULL) { 915 m_freem(m_new); 916 printf("%s: jumbo allocation failed " 917 "-- packet dropped!\n", sc->bge_dev.dv_xname); 918 return(ENOBUFS); 919 } 920 921 /* Attach the buffer to the mbuf. */ 922 m_new->m_len = m_new->m_pkthdr.len = BGE_JUMBO_FRAMELEN; 923 MEXTADD(m_new, buf, BGE_JUMBO_FRAMELEN, M_DEVBUF, 924 bge_jfree, sc); 925 m_new->m_flags |= M_EXT_RW; 926 } else { 927 m_new = m; 928 m_new->m_data = m_new->m_ext.ext_buf; 929 m_new->m_ext.ext_size = BGE_JUMBO_FRAMELEN; 930 } 931 932 if (!sc->bge_rx_alignment_bug) 933 m_adj(m_new, ETHER_ALIGN); 934 /* Set up the descriptor. */ 935 r = &sc->bge_rdata->bge_rx_jumbo_ring[i]; 936 sc->bge_cdata.bge_rx_jumbo_chain[i] = m_new; 937 bge_set_hostaddr(&r->bge_addr, BGE_JUMBO_DMA_ADDR(sc, m_new)); 938 r->bge_flags = BGE_RXBDFLAG_END|BGE_RXBDFLAG_JUMBO_RING; 939 r->bge_len = m_new->m_len; 940 r->bge_idx = i; 941 942 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 943 offsetof(struct bge_ring_data, bge_rx_jumbo_ring) + 944 i * sizeof (struct bge_rx_bd), 945 sizeof (struct bge_rx_bd), 946 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 947 948 return(0); 949 } 950 951 /* 952 * The standard receive ring has 512 entries in it. At 2K per mbuf cluster, 953 * that's 1MB or memory, which is a lot. For now, we fill only the first 954 * 256 ring entries and hope that our CPU is fast enough to keep up with 955 * the NIC. 956 */ 957 static int 958 bge_init_rx_ring_std(struct bge_softc *sc) 959 { 960 int i; 961 962 if (sc->bge_flags & BGE_RXRING_VALID) 963 return 0; 964 965 for (i = 0; i < BGE_SSLOTS; i++) { 966 if (bge_newbuf_std(sc, i, NULL, 0) == ENOBUFS) 967 return(ENOBUFS); 968 } 969 970 sc->bge_std = i - 1; 971 CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std); 972 973 sc->bge_flags |= BGE_RXRING_VALID; 974 975 return(0); 976 } 977 978 static void 979 bge_free_rx_ring_std(struct bge_softc *sc) 980 { 981 int i; 982 983 if (!(sc->bge_flags & BGE_RXRING_VALID)) 984 return; 985 986 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { 987 if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) { 988 m_freem(sc->bge_cdata.bge_rx_std_chain[i]); 989 sc->bge_cdata.bge_rx_std_chain[i] = NULL; 990 bus_dmamap_destroy(sc->bge_dmatag, 991 sc->bge_cdata.bge_rx_std_map[i]); 992 } 993 memset((char *)&sc->bge_rdata->bge_rx_std_ring[i], 0, 994 sizeof(struct bge_rx_bd)); 995 } 996 997 sc->bge_flags &= ~BGE_RXRING_VALID; 998 } 999 1000 static int 1001 bge_init_rx_ring_jumbo(struct bge_softc *sc) 1002 { 1003 int i; 1004 volatile struct bge_rcb *rcb; 1005 1006 if (sc->bge_flags & BGE_JUMBO_RXRING_VALID) 1007 return 0; 1008 1009 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 1010 if (bge_newbuf_jumbo(sc, i, NULL) == ENOBUFS) 1011 return(ENOBUFS); 1012 }; 1013 1014 sc->bge_jumbo = i - 1; 1015 sc->bge_flags |= BGE_JUMBO_RXRING_VALID; 1016 1017 rcb = &sc->bge_rdata->bge_info.bge_jumbo_rx_rcb; 1018 rcb->bge_maxlen_flags = 0; 1019 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 1020 1021 CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo); 1022 1023 return(0); 1024 } 1025 1026 static void 1027 bge_free_rx_ring_jumbo(struct bge_softc *sc) 1028 { 1029 int i; 1030 1031 if (!(sc->bge_flags & BGE_JUMBO_RXRING_VALID)) 1032 return; 1033 1034 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 1035 if (sc->bge_cdata.bge_rx_jumbo_chain[i] != NULL) { 1036 m_freem(sc->bge_cdata.bge_rx_jumbo_chain[i]); 1037 sc->bge_cdata.bge_rx_jumbo_chain[i] = NULL; 1038 } 1039 memset((char *)&sc->bge_rdata->bge_rx_jumbo_ring[i], 0, 1040 sizeof(struct bge_rx_bd)); 1041 } 1042 1043 sc->bge_flags &= ~BGE_JUMBO_RXRING_VALID; 1044 } 1045 1046 static void 1047 bge_free_tx_ring(struct bge_softc *sc) 1048 { 1049 int i, freed; 1050 struct txdmamap_pool_entry *dma; 1051 1052 if (!(sc->bge_flags & BGE_TXRING_VALID)) 1053 return; 1054 1055 freed = 0; 1056 1057 for (i = 0; i < BGE_TX_RING_CNT; i++) { 1058 if (sc->bge_cdata.bge_tx_chain[i] != NULL) { 1059 freed++; 1060 m_freem(sc->bge_cdata.bge_tx_chain[i]); 1061 sc->bge_cdata.bge_tx_chain[i] = NULL; 1062 SLIST_INSERT_HEAD(&sc->txdma_list, sc->txdma[i], 1063 link); 1064 sc->txdma[i] = 0; 1065 } 1066 memset((char *)&sc->bge_rdata->bge_tx_ring[i], 0, 1067 sizeof(struct bge_tx_bd)); 1068 } 1069 1070 while ((dma = SLIST_FIRST(&sc->txdma_list))) { 1071 SLIST_REMOVE_HEAD(&sc->txdma_list, link); 1072 bus_dmamap_destroy(sc->bge_dmatag, dma->dmamap); 1073 free(dma, M_DEVBUF); 1074 } 1075 1076 sc->bge_flags &= ~BGE_TXRING_VALID; 1077 } 1078 1079 static int 1080 bge_init_tx_ring(struct bge_softc *sc) 1081 { 1082 int i; 1083 bus_dmamap_t dmamap; 1084 struct txdmamap_pool_entry *dma; 1085 1086 if (sc->bge_flags & BGE_TXRING_VALID) 1087 return 0; 1088 1089 sc->bge_txcnt = 0; 1090 sc->bge_tx_saved_considx = 0; 1091 1092 /* Initialize transmit producer index for host-memory send ring. */ 1093 sc->bge_tx_prodidx = 0; 1094 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx); 1095 if (sc->bge_quirks & BGE_QUIRK_PRODUCER_BUG) /* 5700 b2 errata */ 1096 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx); 1097 1098 /* NIC-memory send ring not used; initialize to zero. */ 1099 CSR_WRITE_4(sc, BGE_MBX_TX_NIC_PROD0_LO, 0); 1100 if (sc->bge_quirks & BGE_QUIRK_PRODUCER_BUG) /* 5700 b2 errata */ 1101 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, 0); 1102 1103 SLIST_INIT(&sc->txdma_list); 1104 for (i = 0; i < BGE_RSLOTS; i++) { 1105 if (bus_dmamap_create(sc->bge_dmatag, BGE_TXDMA_MAX, 1106 BGE_NTXSEG, ETHER_MAX_LEN_JUMBO, 0, BUS_DMA_NOWAIT, 1107 &dmamap)) 1108 return(ENOBUFS); 1109 if (dmamap == NULL) 1110 panic("dmamap NULL in bge_init_tx_ring"); 1111 dma = malloc(sizeof(*dma), M_DEVBUF, M_NOWAIT); 1112 if (dma == NULL) { 1113 printf("%s: can't alloc txdmamap_pool_entry\n", 1114 sc->bge_dev.dv_xname); 1115 bus_dmamap_destroy(sc->bge_dmatag, dmamap); 1116 return (ENOMEM); 1117 } 1118 dma->dmamap = dmamap; 1119 SLIST_INSERT_HEAD(&sc->txdma_list, dma, link); 1120 } 1121 1122 sc->bge_flags |= BGE_TXRING_VALID; 1123 1124 return(0); 1125 } 1126 1127 static void 1128 bge_setmulti(struct bge_softc *sc) 1129 { 1130 struct ethercom *ac = &sc->ethercom; 1131 struct ifnet *ifp = &ac->ec_if; 1132 struct ether_multi *enm; 1133 struct ether_multistep step; 1134 u_int32_t hashes[4] = { 0, 0, 0, 0 }; 1135 u_int32_t h; 1136 int i; 1137 1138 if (ifp->if_flags & IFF_PROMISC) 1139 goto allmulti; 1140 1141 /* Now program new ones. */ 1142 ETHER_FIRST_MULTI(step, ac, enm); 1143 while (enm != NULL) { 1144 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1145 /* 1146 * We must listen to a range of multicast addresses. 1147 * For now, just accept all multicasts, rather than 1148 * trying to set only those filter bits needed to match 1149 * the range. (At this time, the only use of address 1150 * ranges is for IP multicast routing, for which the 1151 * range is big enough to require all bits set.) 1152 */ 1153 goto allmulti; 1154 } 1155 1156 h = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN); 1157 1158 /* Just want the 7 least-significant bits. */ 1159 h &= 0x7f; 1160 1161 hashes[(h & 0x60) >> 5] |= 1 << (h & 0x1F); 1162 ETHER_NEXT_MULTI(step, enm); 1163 } 1164 1165 ifp->if_flags &= ~IFF_ALLMULTI; 1166 goto setit; 1167 1168 allmulti: 1169 ifp->if_flags |= IFF_ALLMULTI; 1170 hashes[0] = hashes[1] = hashes[2] = hashes[3] = 0xffffffff; 1171 1172 setit: 1173 for (i = 0; i < 4; i++) 1174 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]); 1175 } 1176 1177 const int bge_swapbits[] = { 1178 0, 1179 BGE_MODECTL_BYTESWAP_DATA, 1180 BGE_MODECTL_WORDSWAP_DATA, 1181 BGE_MODECTL_BYTESWAP_NONFRAME, 1182 BGE_MODECTL_WORDSWAP_NONFRAME, 1183 1184 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA, 1185 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_BYTESWAP_NONFRAME, 1186 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_NONFRAME, 1187 1188 BGE_MODECTL_WORDSWAP_DATA|BGE_MODECTL_BYTESWAP_NONFRAME, 1189 BGE_MODECTL_WORDSWAP_DATA|BGE_MODECTL_WORDSWAP_NONFRAME, 1190 1191 BGE_MODECTL_BYTESWAP_NONFRAME|BGE_MODECTL_WORDSWAP_NONFRAME, 1192 1193 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA| 1194 BGE_MODECTL_BYTESWAP_NONFRAME, 1195 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA| 1196 BGE_MODECTL_WORDSWAP_NONFRAME, 1197 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_BYTESWAP_NONFRAME| 1198 BGE_MODECTL_WORDSWAP_NONFRAME, 1199 BGE_MODECTL_WORDSWAP_DATA|BGE_MODECTL_BYTESWAP_NONFRAME| 1200 BGE_MODECTL_WORDSWAP_NONFRAME, 1201 1202 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA| 1203 BGE_MODECTL_BYTESWAP_NONFRAME|BGE_MODECTL_WORDSWAP_NONFRAME, 1204 }; 1205 1206 int bge_swapindex = 0; 1207 1208 /* 1209 * Do endian, PCI and DMA initialization. Also check the on-board ROM 1210 * self-test results. 1211 */ 1212 static int 1213 bge_chipinit(struct bge_softc *sc) 1214 { 1215 u_int32_t cachesize; 1216 int i; 1217 u_int32_t dma_rw_ctl; 1218 struct pci_attach_args *pa = &(sc->bge_pa); 1219 1220 1221 /* Set endianness before we access any non-PCI registers. */ 1222 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_MISC_CTL, 1223 BGE_INIT); 1224 1225 /* Set power state to D0. */ 1226 bge_setpowerstate(sc, 0); 1227 1228 /* 1229 * Check the 'ROM failed' bit on the RX CPU to see if 1230 * self-tests passed. 1231 */ 1232 if (CSR_READ_4(sc, BGE_RXCPU_MODE) & BGE_RXCPUMODE_ROMFAIL) { 1233 printf("%s: RX CPU self-diagnostics failed!\n", 1234 sc->bge_dev.dv_xname); 1235 return(ENODEV); 1236 } 1237 1238 /* Clear the MAC control register */ 1239 CSR_WRITE_4(sc, BGE_MAC_MODE, 0); 1240 1241 /* 1242 * Clear the MAC statistics block in the NIC's 1243 * internal memory. 1244 */ 1245 for (i = BGE_STATS_BLOCK; 1246 i < BGE_STATS_BLOCK_END + 1; i += sizeof(u_int32_t)) 1247 BGE_MEMWIN_WRITE(pa->pa_pc, pa->pa_tag, i, 0); 1248 1249 for (i = BGE_STATUS_BLOCK; 1250 i < BGE_STATUS_BLOCK_END + 1; i += sizeof(u_int32_t)) 1251 BGE_MEMWIN_WRITE(pa->pa_pc, pa->pa_tag, i, 0); 1252 1253 /* Set up the PCI DMA control register. */ 1254 if (sc->bge_pcie) { 1255 u_int32_t device_ctl; 1256 1257 /* From FreeBSD */ 1258 DPRINTFN(4, ("(%s: PCI-Express DMA setting)\n", 1259 sc->bge_dev.dv_xname)); 1260 dma_rw_ctl = (BGE_PCI_READ_CMD | BGE_PCI_WRITE_CMD | 1261 (0xf << BGE_PCIDMARWCTL_RD_WAT_SHIFT) | 1262 (0x2 << BGE_PCIDMARWCTL_WR_WAT_SHIFT)); 1263 1264 /* jonathan: alternative from Linux driver */ 1265 #define DMA_CTRL_WRITE_PCIE_H20MARK_128 0x00180000 1266 #define DMA_CTRL_WRITE_PCIE_H20MARK_256 0x00380000 1267 1268 dma_rw_ctl = 0x76000000; /* XXX XXX XXX */; 1269 device_ctl = pci_conf_read(pa->pa_pc, pa->pa_tag, 1270 BGE_PCI_CONF_DEV_CTRL); 1271 aprint_debug("%s: pcie mode=0x%x\n", sc->bge_dev.dv_xname, 1272 device_ctl); 1273 1274 if ((device_ctl & 0x00e0) && 0) { 1275 /* 1276 * XXX jonathan (at) NetBSD.org: 1277 * This clause is exactly what the Broadcom-supplied 1278 * Linux does; but given overall register programming 1279 * by if_bge(4), this larger DMA-write watermark 1280 * value causes bcm5721 chips to totally wedge. 1281 */ 1282 dma_rw_ctl |= BGE_PCIDMA_RWCTL_PCIE_WRITE_WATRMARK_256; 1283 } else { 1284 dma_rw_ctl |= BGE_PCIDMA_RWCTL_PCIE_WRITE_WATRMARK_128; 1285 } 1286 } else if (pci_conf_read(pa->pa_pc, pa->pa_tag,BGE_PCI_PCISTATE) & 1287 BGE_PCISTATE_PCI_BUSMODE) { 1288 /* Conventional PCI bus */ 1289 DPRINTFN(4, ("(%s: PCI 2.2 DMA setting)\n", sc->bge_dev.dv_xname)); 1290 dma_rw_ctl = (BGE_PCI_READ_CMD | BGE_PCI_WRITE_CMD | 1291 (0x7 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) | 1292 (0x7 << BGE_PCIDMARWCTL_WR_WAT_SHIFT)); 1293 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 1294 dma_rw_ctl |= 0x0F; 1295 } 1296 } else { 1297 DPRINTFN(4, ("(:%s: PCI-X DMA setting)\n", sc->bge_dev.dv_xname)); 1298 /* PCI-X bus */ 1299 dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD | 1300 (0x3 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) | 1301 (0x3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT) | 1302 (0x0F); 1303 /* 1304 * 5703 and 5704 need ONEDMA_AT_ONCE as a workaround 1305 * for hardware bugs, which means we should also clear 1306 * the low-order MINDMA bits. In addition, the 5704 1307 * uses a different encoding of read/write watermarks. 1308 */ 1309 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) { 1310 dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD | 1311 /* should be 0x1f0000 */ 1312 (0x7 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) | 1313 (0x3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT); 1314 dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE; 1315 } 1316 else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5703) { 1317 dma_rw_ctl &= 0xfffffff0; 1318 dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE; 1319 } 1320 else if (BGE_IS_5714_FAMILY(sc)) { 1321 dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD; 1322 dma_rw_ctl &= ~BGE_PCIDMARWCTL_ONEDMA_ATONCE; /* XXX */ 1323 /* XXX magic values, Broadcom-supplied Linux driver */ 1324 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5780) 1325 dma_rw_ctl |= (1 << 20) | (1 << 18) | 1326 BGE_PCIDMARWCTL_ONEDMA_ATONCE; 1327 else 1328 dma_rw_ctl |= (1<<20) | (1<<18) | (1 << 15); 1329 } 1330 } 1331 1332 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_DMA_RW_CTL, dma_rw_ctl); 1333 1334 /* 1335 * Set up general mode register. 1336 */ 1337 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS| 1338 BGE_MODECTL_MAC_ATTN_INTR|BGE_MODECTL_HOST_SEND_BDS| 1339 BGE_MODECTL_TX_NO_PHDR_CSUM|BGE_MODECTL_RX_NO_PHDR_CSUM); 1340 1341 /* Get cache line size. */ 1342 cachesize = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_CACHESZ); 1343 1344 /* 1345 * Avoid violating PCI spec on certain chip revs. 1346 */ 1347 if (pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_CMD) & 1348 PCIM_CMD_MWIEN) { 1349 switch(cachesize) { 1350 case 1: 1351 PCI_SETBIT(pa->pa_pc, pa->pa_tag, BGE_PCI_DMA_RW_CTL, 1352 BGE_PCI_WRITE_BNDRY_16BYTES); 1353 break; 1354 case 2: 1355 PCI_SETBIT(pa->pa_pc, pa->pa_tag, BGE_PCI_DMA_RW_CTL, 1356 BGE_PCI_WRITE_BNDRY_32BYTES); 1357 break; 1358 case 4: 1359 PCI_SETBIT(pa->pa_pc, pa->pa_tag, BGE_PCI_DMA_RW_CTL, 1360 BGE_PCI_WRITE_BNDRY_64BYTES); 1361 break; 1362 case 8: 1363 PCI_SETBIT(pa->pa_pc, pa->pa_tag, BGE_PCI_DMA_RW_CTL, 1364 BGE_PCI_WRITE_BNDRY_128BYTES); 1365 break; 1366 case 16: 1367 PCI_SETBIT(pa->pa_pc, pa->pa_tag, BGE_PCI_DMA_RW_CTL, 1368 BGE_PCI_WRITE_BNDRY_256BYTES); 1369 break; 1370 case 32: 1371 PCI_SETBIT(pa->pa_pc, pa->pa_tag, BGE_PCI_DMA_RW_CTL, 1372 BGE_PCI_WRITE_BNDRY_512BYTES); 1373 break; 1374 case 64: 1375 PCI_SETBIT(pa->pa_pc, pa->pa_tag, BGE_PCI_DMA_RW_CTL, 1376 BGE_PCI_WRITE_BNDRY_1024BYTES); 1377 break; 1378 default: 1379 /* Disable PCI memory write and invalidate. */ 1380 #if 0 1381 if (bootverbose) 1382 printf("%s: cache line size %d not " 1383 "supported; disabling PCI MWI\n", 1384 sc->bge_dev.dv_xname, cachesize); 1385 #endif 1386 PCI_CLRBIT(pa->pa_pc, pa->pa_tag, BGE_PCI_CMD, 1387 PCIM_CMD_MWIEN); 1388 break; 1389 } 1390 } 1391 1392 /* 1393 * Disable memory write invalidate. Apparently it is not supported 1394 * properly by these devices. 1395 */ 1396 PCI_CLRBIT(pa->pa_pc, pa->pa_tag, BGE_PCI_CMD, PCIM_CMD_MWIEN); 1397 1398 1399 #ifdef __brokenalpha__ 1400 /* 1401 * Must insure that we do not cross an 8K (bytes) boundary 1402 * for DMA reads. Our highest limit is 1K bytes. This is a 1403 * restriction on some ALPHA platforms with early revision 1404 * 21174 PCI chipsets, such as the AlphaPC 164lx 1405 */ 1406 PCI_SETBIT(sc, BGE_PCI_DMA_RW_CTL, BGE_PCI_READ_BNDRY_1024, 4); 1407 #endif 1408 1409 /* Set the timer prescaler (always 66MHz) */ 1410 CSR_WRITE_4(sc, BGE_MISC_CFG, 65 << 1/*BGE_32BITTIME_66MHZ*/); 1411 1412 return(0); 1413 } 1414 1415 static int 1416 bge_blockinit(struct bge_softc *sc) 1417 { 1418 volatile struct bge_rcb *rcb; 1419 bus_size_t rcb_addr; 1420 int i; 1421 struct ifnet *ifp = &sc->ethercom.ec_if; 1422 bge_hostaddr taddr; 1423 1424 /* 1425 * Initialize the memory window pointer register so that 1426 * we can access the first 32K of internal NIC RAM. This will 1427 * allow us to set up the TX send ring RCBs and the RX return 1428 * ring RCBs, plus other things which live in NIC memory. 1429 */ 1430 1431 pci_conf_write(sc->bge_pa.pa_pc, sc->bge_pa.pa_tag, 1432 BGE_PCI_MEMWIN_BASEADDR, 0); 1433 1434 /* Configure mbuf memory pool */ 1435 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 1436 if (sc->bge_extram) { 1437 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, 1438 BGE_EXT_SSRAM); 1439 if ((sc->bge_quirks & BGE_QUIRK_FEWER_MBUFS) != 0) 1440 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000); 1441 else 1442 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000); 1443 } else { 1444 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, 1445 BGE_BUFFPOOL_1); 1446 if ((sc->bge_quirks & BGE_QUIRK_FEWER_MBUFS) != 0) 1447 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000); 1448 else 1449 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000); 1450 } 1451 1452 /* Configure DMA resource pool */ 1453 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_BASEADDR, 1454 BGE_DMA_DESCRIPTORS); 1455 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LEN, 0x2000); 1456 } 1457 1458 /* Configure mbuf pool watermarks */ 1459 #ifdef ORIG_WPAUL_VALUES 1460 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 24); 1461 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 24); 1462 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 48); 1463 #else 1464 /* new broadcom docs strongly recommend these: */ 1465 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 1466 if (ifp->if_mtu > ETHER_MAX_LEN) { 1467 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x50); 1468 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x20); 1469 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60); 1470 } else { 1471 /* Values from Linux driver... */ 1472 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 304); 1473 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 152); 1474 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 380); 1475 } 1476 } else { 1477 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0); 1478 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x10); 1479 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60); 1480 } 1481 #endif 1482 1483 /* Configure DMA resource watermarks */ 1484 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5); 1485 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10); 1486 1487 /* Enable buffer manager */ 1488 CSR_WRITE_4(sc, BGE_BMAN_MODE, 1489 BGE_BMANMODE_ENABLE|BGE_BMANMODE_LOMBUF_ATTN); 1490 1491 /* Poll for buffer manager start indication */ 1492 for (i = 0; i < BGE_TIMEOUT; i++) { 1493 if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE) 1494 break; 1495 DELAY(10); 1496 } 1497 1498 if (i == BGE_TIMEOUT) { 1499 printf("%s: buffer manager failed to start\n", 1500 sc->bge_dev.dv_xname); 1501 return(ENXIO); 1502 } 1503 1504 /* Enable flow-through queues */ 1505 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 1506 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 1507 1508 /* Wait until queue initialization is complete */ 1509 for (i = 0; i < BGE_TIMEOUT; i++) { 1510 if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0) 1511 break; 1512 DELAY(10); 1513 } 1514 1515 if (i == BGE_TIMEOUT) { 1516 printf("%s: flow-through queue init failed\n", 1517 sc->bge_dev.dv_xname); 1518 return(ENXIO); 1519 } 1520 1521 /* Initialize the standard RX ring control block */ 1522 rcb = &sc->bge_rdata->bge_info.bge_std_rx_rcb; 1523 bge_set_hostaddr(&rcb->bge_hostaddr, 1524 BGE_RING_DMA_ADDR(sc, bge_rx_std_ring)); 1525 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 1526 rcb->bge_maxlen_flags = 1527 BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 0); 1528 } else { 1529 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(512, 0); 1530 } 1531 if (sc->bge_extram) 1532 rcb->bge_nicaddr = BGE_EXT_STD_RX_RINGS; 1533 else 1534 rcb->bge_nicaddr = BGE_STD_RX_RINGS; 1535 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcb->bge_hostaddr.bge_addr_hi); 1536 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcb->bge_hostaddr.bge_addr_lo); 1537 CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 1538 CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcb->bge_nicaddr); 1539 1540 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 1541 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT; 1542 } else { 1543 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT_5705; 1544 } 1545 1546 /* 1547 * Initialize the jumbo RX ring control block 1548 * We set the 'ring disabled' bit in the flags 1549 * field until we're actually ready to start 1550 * using this ring (i.e. once we set the MTU 1551 * high enough to require it). 1552 */ 1553 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 1554 rcb = &sc->bge_rdata->bge_info.bge_jumbo_rx_rcb; 1555 bge_set_hostaddr(&rcb->bge_hostaddr, 1556 BGE_RING_DMA_ADDR(sc, bge_rx_jumbo_ring)); 1557 rcb->bge_maxlen_flags = 1558 BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 1559 BGE_RCB_FLAG_RING_DISABLED); 1560 if (sc->bge_extram) 1561 rcb->bge_nicaddr = BGE_EXT_JUMBO_RX_RINGS; 1562 else 1563 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS; 1564 1565 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI, 1566 rcb->bge_hostaddr.bge_addr_hi); 1567 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO, 1568 rcb->bge_hostaddr.bge_addr_lo); 1569 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, 1570 rcb->bge_maxlen_flags); 1571 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcb->bge_nicaddr); 1572 1573 /* Set up dummy disabled mini ring RCB */ 1574 rcb = &sc->bge_rdata->bge_info.bge_mini_rx_rcb; 1575 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0, 1576 BGE_RCB_FLAG_RING_DISABLED); 1577 CSR_WRITE_4(sc, BGE_RX_MINI_RCB_MAXLEN_FLAGS, 1578 rcb->bge_maxlen_flags); 1579 1580 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 1581 offsetof(struct bge_ring_data, bge_info), 1582 sizeof (struct bge_gib), 1583 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1584 } 1585 1586 /* 1587 * Set the BD ring replentish thresholds. The recommended 1588 * values are 1/8th the number of descriptors allocated to 1589 * each ring. 1590 */ 1591 CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, BGE_STD_RX_RING_CNT/8); 1592 CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH, BGE_JUMBO_RX_RING_CNT/8); 1593 1594 /* 1595 * Disable all unused send rings by setting the 'ring disabled' 1596 * bit in the flags field of all the TX send ring control blocks. 1597 * These are located in NIC memory. 1598 */ 1599 rcb_addr = BGE_MEMWIN_START + BGE_SEND_RING_RCB; 1600 for (i = 0; i < BGE_TX_RINGS_EXTSSRAM_MAX; i++) { 1601 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 1602 BGE_RCB_MAXLEN_FLAGS(0,BGE_RCB_FLAG_RING_DISABLED)); 1603 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 0); 1604 rcb_addr += sizeof(struct bge_rcb); 1605 } 1606 1607 /* Configure TX RCB 0 (we use only the first ring) */ 1608 rcb_addr = BGE_MEMWIN_START + BGE_SEND_RING_RCB; 1609 bge_set_hostaddr(&taddr, BGE_RING_DMA_ADDR(sc, bge_tx_ring)); 1610 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi); 1611 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo); 1612 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 1613 BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT)); 1614 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 1615 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 1616 BGE_RCB_MAXLEN_FLAGS(BGE_TX_RING_CNT, 0)); 1617 } 1618 1619 /* Disable all unused RX return rings */ 1620 rcb_addr = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB; 1621 for (i = 0; i < BGE_RX_RINGS_MAX; i++) { 1622 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_hi, 0); 1623 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_lo, 0); 1624 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 1625 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 1626 BGE_RCB_FLAG_RING_DISABLED)); 1627 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 0); 1628 CSR_WRITE_4(sc, BGE_MBX_RX_CONS0_LO + 1629 (i * (sizeof(u_int64_t))), 0); 1630 rcb_addr += sizeof(struct bge_rcb); 1631 } 1632 1633 /* Initialize RX ring indexes */ 1634 CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, 0); 1635 CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0); 1636 CSR_WRITE_4(sc, BGE_MBX_RX_MINI_PROD_LO, 0); 1637 1638 /* 1639 * Set up RX return ring 0 1640 * Note that the NIC address for RX return rings is 0x00000000. 1641 * The return rings live entirely within the host, so the 1642 * nicaddr field in the RCB isn't used. 1643 */ 1644 rcb_addr = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB; 1645 bge_set_hostaddr(&taddr, BGE_RING_DMA_ADDR(sc, bge_rx_return_ring)); 1646 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi); 1647 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo); 1648 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 0x00000000); 1649 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 1650 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 0)); 1651 1652 /* Set random backoff seed for TX */ 1653 CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF, 1654 LLADDR(ifp->if_sadl)[0] + LLADDR(ifp->if_sadl)[1] + 1655 LLADDR(ifp->if_sadl)[2] + LLADDR(ifp->if_sadl)[3] + 1656 LLADDR(ifp->if_sadl)[4] + LLADDR(ifp->if_sadl)[5] + 1657 BGE_TX_BACKOFF_SEED_MASK); 1658 1659 /* Set inter-packet gap */ 1660 CSR_WRITE_4(sc, BGE_TX_LENGTHS, 0x2620); 1661 1662 /* 1663 * Specify which ring to use for packets that don't match 1664 * any RX rules. 1665 */ 1666 CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08); 1667 1668 /* 1669 * Configure number of RX lists. One interrupt distribution 1670 * list, sixteen active lists, one bad frames class. 1671 */ 1672 CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181); 1673 1674 /* Inialize RX list placement stats mask. */ 1675 CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF); 1676 CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1); 1677 1678 /* Disable host coalescing until we get it set up */ 1679 CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000); 1680 1681 /* Poll to make sure it's shut down. */ 1682 for (i = 0; i < BGE_TIMEOUT; i++) { 1683 if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE)) 1684 break; 1685 DELAY(10); 1686 } 1687 1688 if (i == BGE_TIMEOUT) { 1689 printf("%s: host coalescing engine failed to idle\n", 1690 sc->bge_dev.dv_xname); 1691 return(ENXIO); 1692 } 1693 1694 /* Set up host coalescing defaults */ 1695 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bge_rx_coal_ticks); 1696 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bge_tx_coal_ticks); 1697 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bge_rx_max_coal_bds); 1698 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bge_tx_max_coal_bds); 1699 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 1700 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT, 0); 1701 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT, 0); 1702 } 1703 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 0); 1704 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 0); 1705 1706 /* Set up address of statistics block */ 1707 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 1708 bge_set_hostaddr(&taddr, 1709 BGE_RING_DMA_ADDR(sc, bge_info.bge_stats)); 1710 CSR_WRITE_4(sc, BGE_HCC_STATS_TICKS, sc->bge_stat_ticks); 1711 CSR_WRITE_4(sc, BGE_HCC_STATS_BASEADDR, BGE_STATS_BLOCK); 1712 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_HI, taddr.bge_addr_hi); 1713 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_LO, taddr.bge_addr_lo); 1714 } 1715 1716 /* Set up address of status block */ 1717 bge_set_hostaddr(&taddr, BGE_RING_DMA_ADDR(sc, bge_status_block)); 1718 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_BASEADDR, BGE_STATUS_BLOCK); 1719 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI, taddr.bge_addr_hi); 1720 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO, taddr.bge_addr_lo); 1721 sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx = 0; 1722 sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx = 0; 1723 1724 /* Turn on host coalescing state machine */ 1725 CSR_WRITE_4(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE); 1726 1727 /* Turn on RX BD completion state machine and enable attentions */ 1728 CSR_WRITE_4(sc, BGE_RBDC_MODE, 1729 BGE_RBDCMODE_ENABLE|BGE_RBDCMODE_ATTN); 1730 1731 /* Turn on RX list placement state machine */ 1732 CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 1733 1734 /* Turn on RX list selector state machine. */ 1735 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 1736 CSR_WRITE_4(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 1737 } 1738 1739 /* Turn on DMA, clear stats */ 1740 CSR_WRITE_4(sc, BGE_MAC_MODE, BGE_MACMODE_TXDMA_ENB| 1741 BGE_MACMODE_RXDMA_ENB|BGE_MACMODE_RX_STATS_CLEAR| 1742 BGE_MACMODE_TX_STATS_CLEAR|BGE_MACMODE_RX_STATS_ENB| 1743 BGE_MACMODE_TX_STATS_ENB|BGE_MACMODE_FRMHDR_DMA_ENB| 1744 (sc->bge_tbi ? BGE_PORTMODE_TBI : BGE_PORTMODE_MII)); 1745 1746 /* Set misc. local control, enable interrupts on attentions */ 1747 sc->bge_local_ctrl_reg = BGE_MLC_INTR_ONATTN | BGE_MLC_AUTO_EEPROM; 1748 1749 #ifdef notdef 1750 /* Assert GPIO pins for PHY reset */ 1751 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUT0| 1752 BGE_MLC_MISCIO_OUT1|BGE_MLC_MISCIO_OUT2); 1753 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUTEN0| 1754 BGE_MLC_MISCIO_OUTEN1|BGE_MLC_MISCIO_OUTEN2); 1755 #endif 1756 1757 #if defined(not_quite_yet) 1758 /* Linux driver enables enable gpio pin #1 on 5700s */ 1759 if (sc->bge_chipid == BGE_CHIPID_BCM5700) { 1760 sc->bge_local_ctrl_reg |= 1761 (BGE_MLC_MISCIO_OUT1|BGE_MLC_MISCIO_OUTEN1); 1762 } 1763 #endif 1764 CSR_WRITE_4(sc, BGE_MISC_LOCAL_CTL, sc->bge_local_ctrl_reg); 1765 1766 /* Turn on DMA completion state machine */ 1767 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 1768 CSR_WRITE_4(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 1769 } 1770 1771 /* Turn on write DMA state machine */ 1772 CSR_WRITE_4(sc, BGE_WDMA_MODE, 1773 BGE_WDMAMODE_ENABLE|BGE_WDMAMODE_ALL_ATTNS); 1774 1775 /* Turn on read DMA state machine */ 1776 { 1777 uint32_t dma_read_modebits; 1778 1779 dma_read_modebits = 1780 BGE_RDMAMODE_ENABLE | BGE_RDMAMODE_ALL_ATTNS; 1781 1782 if (sc->bge_pcie && 0) { 1783 dma_read_modebits |= BGE_RDMA_MODE_FIFO_LONG_BURST; 1784 } else if ((sc->bge_quirks & BGE_QUIRK_5705_CORE)) { 1785 dma_read_modebits |= BGE_RDMA_MODE_FIFO_SIZE_128; 1786 } 1787 1788 /* XXX broadcom-supplied linux driver; undocumented */ 1789 if (BGE_IS_5750_OR_BEYOND(sc)) { 1790 /* 1791 * XXX: magic values. 1792 * From Broadcom-supplied Linux driver; apparently 1793 * required to workaround a DMA bug affecting TSO 1794 * on bcm575x/bcm5721? 1795 */ 1796 dma_read_modebits |= (1 << 27); 1797 } 1798 CSR_WRITE_4(sc, BGE_RDMA_MODE, dma_read_modebits); 1799 } 1800 1801 /* Turn on RX data completion state machine */ 1802 CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 1803 1804 /* Turn on RX BD initiator state machine */ 1805 CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 1806 1807 /* Turn on RX data and RX BD initiator state machine */ 1808 CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE); 1809 1810 /* Turn on Mbuf cluster free state machine */ 1811 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 1812 CSR_WRITE_4(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 1813 } 1814 1815 /* Turn on send BD completion state machine */ 1816 CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 1817 1818 /* Turn on send data completion state machine */ 1819 CSR_WRITE_4(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE); 1820 1821 /* Turn on send data initiator state machine */ 1822 if (BGE_IS_5750_OR_BEYOND(sc)) { 1823 /* XXX: magic value from Linux driver */ 1824 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE | 0x08); 1825 } else { 1826 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 1827 } 1828 1829 /* Turn on send BD initiator state machine */ 1830 CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 1831 1832 /* Turn on send BD selector state machine */ 1833 CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 1834 1835 CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF); 1836 CSR_WRITE_4(sc, BGE_SDI_STATS_CTL, 1837 BGE_SDISTATSCTL_ENABLE|BGE_SDISTATSCTL_FASTER); 1838 1839 /* ack/clear link change events */ 1840 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED| 1841 BGE_MACSTAT_CFG_CHANGED); 1842 CSR_WRITE_4(sc, BGE_MI_STS, 0); 1843 1844 /* Enable PHY auto polling (for MII/GMII only) */ 1845 if (sc->bge_tbi) { 1846 CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK); 1847 } else { 1848 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL|10<<16); 1849 if (sc->bge_quirks & BGE_QUIRK_LINK_STATE_BROKEN) 1850 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, 1851 BGE_EVTENB_MI_INTERRUPT); 1852 } 1853 1854 /* Enable link state change attentions. */ 1855 BGE_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED); 1856 1857 return(0); 1858 } 1859 1860 static const struct bge_revision { 1861 uint32_t br_chipid; 1862 uint32_t br_quirks; 1863 const char *br_name; 1864 } bge_revisions[] = { 1865 { BGE_CHIPID_BCM5700_A0, 1866 BGE_QUIRK_LINK_STATE_BROKEN, 1867 "BCM5700 A0" }, 1868 1869 { BGE_CHIPID_BCM5700_A1, 1870 BGE_QUIRK_LINK_STATE_BROKEN, 1871 "BCM5700 A1" }, 1872 1873 { BGE_CHIPID_BCM5700_B0, 1874 BGE_QUIRK_LINK_STATE_BROKEN|BGE_QUIRK_CSUM_BROKEN|BGE_QUIRK_5700_COMMON, 1875 "BCM5700 B0" }, 1876 1877 { BGE_CHIPID_BCM5700_B1, 1878 BGE_QUIRK_LINK_STATE_BROKEN|BGE_QUIRK_5700_COMMON, 1879 "BCM5700 B1" }, 1880 1881 { BGE_CHIPID_BCM5700_B2, 1882 BGE_QUIRK_LINK_STATE_BROKEN|BGE_QUIRK_5700_COMMON, 1883 "BCM5700 B2" }, 1884 1885 { BGE_CHIPID_BCM5700_B3, 1886 BGE_QUIRK_LINK_STATE_BROKEN|BGE_QUIRK_5700_COMMON, 1887 "BCM5700 B3" }, 1888 1889 /* This is treated like a BCM5700 Bx */ 1890 { BGE_CHIPID_BCM5700_ALTIMA, 1891 BGE_QUIRK_LINK_STATE_BROKEN|BGE_QUIRK_5700_COMMON, 1892 "BCM5700 Altima" }, 1893 1894 { BGE_CHIPID_BCM5700_C0, 1895 0, 1896 "BCM5700 C0" }, 1897 1898 { BGE_CHIPID_BCM5701_A0, 1899 0, /*XXX really, just not known */ 1900 "BCM5701 A0" }, 1901 1902 { BGE_CHIPID_BCM5701_B0, 1903 BGE_QUIRK_PCIX_DMA_ALIGN_BUG, 1904 "BCM5701 B0" }, 1905 1906 { BGE_CHIPID_BCM5701_B2, 1907 BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_PCIX_DMA_ALIGN_BUG, 1908 "BCM5701 B2" }, 1909 1910 { BGE_CHIPID_BCM5701_B5, 1911 BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_PCIX_DMA_ALIGN_BUG, 1912 "BCM5701 B5" }, 1913 1914 { BGE_CHIPID_BCM5703_A0, 1915 0, 1916 "BCM5703 A0" }, 1917 1918 { BGE_CHIPID_BCM5703_A1, 1919 0, 1920 "BCM5703 A1" }, 1921 1922 { BGE_CHIPID_BCM5703_A2, 1923 BGE_QUIRK_ONLY_PHY_1, 1924 "BCM5703 A2" }, 1925 1926 { BGE_CHIPID_BCM5703_A3, 1927 BGE_QUIRK_ONLY_PHY_1, 1928 "BCM5703 A3" }, 1929 1930 { BGE_CHIPID_BCM5703_B0, 1931 BGE_QUIRK_ONLY_PHY_1, 1932 "BCM5703 B0" }, 1933 1934 { BGE_CHIPID_BCM5704_A0, 1935 BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_FEWER_MBUFS, 1936 "BCM5704 A0" }, 1937 1938 { BGE_CHIPID_BCM5704_A1, 1939 BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_FEWER_MBUFS, 1940 "BCM5704 A1" }, 1941 1942 { BGE_CHIPID_BCM5704_A2, 1943 BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_FEWER_MBUFS, 1944 "BCM5704 A2" }, 1945 1946 { BGE_CHIPID_BCM5704_A3, 1947 BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_FEWER_MBUFS, 1948 "BCM5704 A3" }, 1949 1950 { BGE_CHIPID_BCM5705_A0, 1951 BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_5705_CORE, 1952 "BCM5705 A0" }, 1953 1954 { BGE_CHIPID_BCM5705_A1, 1955 BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_5705_CORE, 1956 "BCM5705 A1" }, 1957 1958 { BGE_CHIPID_BCM5705_A2, 1959 BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_5705_CORE, 1960 "BCM5705 A2" }, 1961 1962 { BGE_CHIPID_BCM5705_A3, 1963 BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_5705_CORE, 1964 "BCM5705 A3" }, 1965 1966 { BGE_CHIPID_BCM5750_A0, 1967 BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_5705_CORE, 1968 "BCM5750 A0" }, 1969 1970 { BGE_CHIPID_BCM5750_A1, 1971 BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_5705_CORE, 1972 "BCM5750 A1" }, 1973 1974 { BGE_CHIPID_BCM5751_A1, 1975 BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_5705_CORE, 1976 "BCM5751 A1" }, 1977 1978 { BGE_CHIPID_BCM5752_A0, 1979 BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_5705_CORE, 1980 "BCM5752 A0" }, 1981 1982 { BGE_CHIPID_BCM5752_A1, 1983 BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_5705_CORE, 1984 "BCM5752 A1" }, 1985 1986 { BGE_CHIPID_BCM5752_A2, 1987 BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_5705_CORE, 1988 "BCM5752 A2" }, 1989 1990 { 0, 0, NULL } 1991 }; 1992 1993 /* 1994 * Some defaults for major revisions, so that newer steppings 1995 * that we don't know about have a shot at working. 1996 */ 1997 static const struct bge_revision bge_majorrevs[] = { 1998 { BGE_ASICREV_BCM5700, 1999 BGE_QUIRK_LINK_STATE_BROKEN, 2000 "unknown BCM5700" }, 2001 2002 { BGE_ASICREV_BCM5701, 2003 BGE_QUIRK_PCIX_DMA_ALIGN_BUG, 2004 "unknown BCM5701" }, 2005 2006 { BGE_ASICREV_BCM5703, 2007 0, 2008 "unknown BCM5703" }, 2009 2010 { BGE_ASICREV_BCM5704, 2011 BGE_QUIRK_ONLY_PHY_1, 2012 "unknown BCM5704" }, 2013 2014 { BGE_ASICREV_BCM5705, 2015 BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_5705_CORE, 2016 "unknown BCM5705" }, 2017 2018 { BGE_ASICREV_BCM5750, 2019 BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_5705_CORE, 2020 "unknown BCM575x family" }, 2021 2022 { BGE_ASICREV_BCM5714_A0, 2023 BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_5705_CORE, 2024 "unknown BCM5714" }, 2025 2026 { BGE_ASICREV_BCM5714, 2027 BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_5705_CORE, 2028 "unknown BCM5714" }, 2029 2030 { BGE_ASICREV_BCM5752, 2031 BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_5705_CORE, 2032 "unknown BCM5752 family" }, 2033 2034 2035 { BGE_ASICREV_BCM5780, 2036 BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_5705_CORE, 2037 "unknown BCM5780" }, 2038 2039 { 0, 2040 0, 2041 NULL } 2042 }; 2043 2044 2045 static const struct bge_revision * 2046 bge_lookup_rev(uint32_t chipid) 2047 { 2048 const struct bge_revision *br; 2049 2050 for (br = bge_revisions; br->br_name != NULL; br++) { 2051 if (br->br_chipid == chipid) 2052 return (br); 2053 } 2054 2055 for (br = bge_majorrevs; br->br_name != NULL; br++) { 2056 if (br->br_chipid == BGE_ASICREV(chipid)) 2057 return (br); 2058 } 2059 2060 return (NULL); 2061 } 2062 2063 static const struct bge_product { 2064 pci_vendor_id_t bp_vendor; 2065 pci_product_id_t bp_product; 2066 const char *bp_name; 2067 } bge_products[] = { 2068 /* 2069 * The BCM5700 documentation seems to indicate that the hardware 2070 * still has the Alteon vendor ID burned into it, though it 2071 * should always be overridden by the value in the EEPROM. We'll 2072 * check for it anyway. 2073 */ 2074 { PCI_VENDOR_ALTEON, 2075 PCI_PRODUCT_ALTEON_BCM5700, 2076 "Broadcom BCM5700 Gigabit Ethernet", 2077 }, 2078 { PCI_VENDOR_ALTEON, 2079 PCI_PRODUCT_ALTEON_BCM5701, 2080 "Broadcom BCM5701 Gigabit Ethernet", 2081 }, 2082 2083 { PCI_VENDOR_ALTIMA, 2084 PCI_PRODUCT_ALTIMA_AC1000, 2085 "Altima AC1000 Gigabit Ethernet", 2086 }, 2087 { PCI_VENDOR_ALTIMA, 2088 PCI_PRODUCT_ALTIMA_AC1001, 2089 "Altima AC1001 Gigabit Ethernet", 2090 }, 2091 { PCI_VENDOR_ALTIMA, 2092 PCI_PRODUCT_ALTIMA_AC9100, 2093 "Altima AC9100 Gigabit Ethernet", 2094 }, 2095 2096 { PCI_VENDOR_BROADCOM, 2097 PCI_PRODUCT_BROADCOM_BCM5700, 2098 "Broadcom BCM5700 Gigabit Ethernet", 2099 }, 2100 { PCI_VENDOR_BROADCOM, 2101 PCI_PRODUCT_BROADCOM_BCM5701, 2102 "Broadcom BCM5701 Gigabit Ethernet", 2103 }, 2104 { PCI_VENDOR_BROADCOM, 2105 PCI_PRODUCT_BROADCOM_BCM5702, 2106 "Broadcom BCM5702 Gigabit Ethernet", 2107 }, 2108 { PCI_VENDOR_BROADCOM, 2109 PCI_PRODUCT_BROADCOM_BCM5702X, 2110 "Broadcom BCM5702X Gigabit Ethernet" }, 2111 2112 { PCI_VENDOR_BROADCOM, 2113 PCI_PRODUCT_BROADCOM_BCM5703, 2114 "Broadcom BCM5703 Gigabit Ethernet", 2115 }, 2116 { PCI_VENDOR_BROADCOM, 2117 PCI_PRODUCT_BROADCOM_BCM5703X, 2118 "Broadcom BCM5703X Gigabit Ethernet", 2119 }, 2120 { PCI_VENDOR_BROADCOM, 2121 PCI_PRODUCT_BROADCOM_BCM5703_ALT, 2122 "Broadcom BCM5703 Gigabit Ethernet", 2123 }, 2124 2125 { PCI_VENDOR_BROADCOM, 2126 PCI_PRODUCT_BROADCOM_BCM5704C, 2127 "Broadcom BCM5704C Dual Gigabit Ethernet", 2128 }, 2129 { PCI_VENDOR_BROADCOM, 2130 PCI_PRODUCT_BROADCOM_BCM5704S, 2131 "Broadcom BCM5704S Dual Gigabit Ethernet", 2132 }, 2133 2134 { PCI_VENDOR_BROADCOM, 2135 PCI_PRODUCT_BROADCOM_BCM5705, 2136 "Broadcom BCM5705 Gigabit Ethernet", 2137 }, 2138 { PCI_VENDOR_BROADCOM, 2139 PCI_PRODUCT_BROADCOM_BCM5705K, 2140 "Broadcom BCM5705K Gigabit Ethernet", 2141 }, 2142 { PCI_VENDOR_BROADCOM, 2143 PCI_PRODUCT_BROADCOM_BCM5705M, 2144 "Broadcom BCM5705M Gigabit Ethernet", 2145 }, 2146 { PCI_VENDOR_BROADCOM, 2147 PCI_PRODUCT_BROADCOM_BCM5705M_ALT, 2148 "Broadcom BCM5705M Gigabit Ethernet", 2149 }, 2150 2151 { PCI_VENDOR_BROADCOM, 2152 PCI_PRODUCT_BROADCOM_BCM5714, 2153 "Broadcom BCM5714/5715 Gigabit Ethernet", 2154 }, 2155 { PCI_VENDOR_BROADCOM, 2156 PCI_PRODUCT_BROADCOM_BCM5789, 2157 "Broadcom BCM5789 Gigabit Ethernet", 2158 }, 2159 2160 { PCI_VENDOR_BROADCOM, 2161 PCI_PRODUCT_BROADCOM_BCM5721, 2162 "Broadcom BCM5721 Gigabit Ethernet", 2163 }, 2164 2165 { PCI_VENDOR_BROADCOM, 2166 PCI_PRODUCT_BROADCOM_BCM5750, 2167 "Broadcom BCM5750 Gigabit Ethernet", 2168 }, 2169 2170 { PCI_VENDOR_BROADCOM, 2171 PCI_PRODUCT_BROADCOM_BCM5750M, 2172 "Broadcom BCM5750M Gigabit Ethernet", 2173 }, 2174 2175 { PCI_VENDOR_BROADCOM, 2176 PCI_PRODUCT_BROADCOM_BCM5751, 2177 "Broadcom BCM5751 Gigabit Ethernet", 2178 }, 2179 2180 { PCI_VENDOR_BROADCOM, 2181 PCI_PRODUCT_BROADCOM_BCM5751M, 2182 "Broadcom BCM5751M Gigabit Ethernet", 2183 }, 2184 2185 { PCI_VENDOR_BROADCOM, 2186 PCI_PRODUCT_BROADCOM_BCM5752, 2187 "Broadcom BCM5752 Gigabit Ethernet", 2188 }, 2189 2190 { PCI_VENDOR_BROADCOM, 2191 PCI_PRODUCT_BROADCOM_BCM5752M, 2192 "Broadcom BCM5752M Gigabit Ethernet", 2193 }, 2194 2195 { PCI_VENDOR_BROADCOM, 2196 PCI_PRODUCT_BROADCOM_BCM5780, 2197 "Broadcom BCM5780 Gigabit Ethernet", 2198 }, 2199 2200 { PCI_VENDOR_BROADCOM, 2201 PCI_PRODUCT_BROADCOM_BCM5780S, 2202 "Broadcom BCM5780S Gigabit Ethernet", 2203 }, 2204 2205 { PCI_VENDOR_BROADCOM, 2206 PCI_PRODUCT_BROADCOM_BCM5782, 2207 "Broadcom BCM5782 Gigabit Ethernet", 2208 }, 2209 2210 { PCI_VENDOR_BROADCOM, 2211 PCI_PRODUCT_BROADCOM_BCM5788, 2212 "Broadcom BCM5788 Gigabit Ethernet", 2213 }, 2214 { PCI_VENDOR_BROADCOM, 2215 PCI_PRODUCT_BROADCOM_BCM5789, 2216 "Broadcom BCM5789 Gigabit Ethernet", 2217 }, 2218 2219 { PCI_VENDOR_BROADCOM, 2220 PCI_PRODUCT_BROADCOM_BCM5901, 2221 "Broadcom BCM5901 Fast Ethernet", 2222 }, 2223 { PCI_VENDOR_BROADCOM, 2224 PCI_PRODUCT_BROADCOM_BCM5901A2, 2225 "Broadcom BCM5901A2 Fast Ethernet", 2226 }, 2227 2228 { PCI_VENDOR_SCHNEIDERKOCH, 2229 PCI_PRODUCT_SCHNEIDERKOCH_SK_9DX1, 2230 "SysKonnect SK-9Dx1 Gigabit Ethernet", 2231 }, 2232 2233 { PCI_VENDOR_3COM, 2234 PCI_PRODUCT_3COM_3C996, 2235 "3Com 3c996 Gigabit Ethernet", 2236 }, 2237 2238 { 0, 2239 0, 2240 NULL }, 2241 }; 2242 2243 static const struct bge_product * 2244 bge_lookup(const struct pci_attach_args *pa) 2245 { 2246 const struct bge_product *bp; 2247 2248 for (bp = bge_products; bp->bp_name != NULL; bp++) { 2249 if (PCI_VENDOR(pa->pa_id) == bp->bp_vendor && 2250 PCI_PRODUCT(pa->pa_id) == bp->bp_product) 2251 return (bp); 2252 } 2253 2254 return (NULL); 2255 } 2256 2257 static int 2258 bge_setpowerstate(struct bge_softc *sc, int powerlevel) 2259 { 2260 #ifdef NOTYET 2261 u_int32_t pm_ctl = 0; 2262 2263 /* XXX FIXME: make sure indirect accesses enabled? */ 2264 pm_ctl = pci_conf_read(sc->bge_dev, BGE_PCI_MISC_CTL, 4); 2265 pm_ctl |= BGE_PCIMISCCTL_INDIRECT_ACCESS; 2266 pci_write_config(sc->bge_dev, BGE_PCI_MISC_CTL, pm_ctl, 4); 2267 2268 /* clear the PME_assert bit and power state bits, enable PME */ 2269 pm_ctl = pci_conf_read(sc->bge_dev, BGE_PCI_PWRMGMT_CMD, 2); 2270 pm_ctl &= ~PCIM_PSTAT_DMASK; 2271 pm_ctl |= (1 << 8); 2272 2273 if (powerlevel == 0) { 2274 pm_ctl |= PCIM_PSTAT_D0; 2275 pci_write_config(sc->bge_dev, BGE_PCI_PWRMGMT_CMD, 2276 pm_ctl, 2); 2277 DELAY(10000); 2278 CSR_WRITE_4(sc, BGE_MISC_LOCAL_CTL, sc->bge_local_ctrl_reg); 2279 DELAY(10000); 2280 2281 #ifdef NOTYET 2282 /* XXX FIXME: write 0x02 to phy aux_Ctrl reg */ 2283 bge_miibus_writereg(sc->bge_dev, 1, 0x18, 0x02); 2284 #endif 2285 DELAY(40); DELAY(40); DELAY(40); 2286 DELAY(10000); /* above not quite adequate on 5700 */ 2287 return 0; 2288 } 2289 2290 2291 /* 2292 * Entering ACPI power states D1-D3 is achieved by wiggling 2293 * GMII gpio pins. Example code assumes all hardware vendors 2294 * followed Broadom's sample pcb layout. Until we verify that 2295 * for all supported OEM cards, states D1-D3 are unsupported. 2296 */ 2297 printf("%s: power state %d unimplemented; check GPIO pins\n", 2298 sc->bge_dev.dv_xname, powerlevel); 2299 #endif 2300 return EOPNOTSUPP; 2301 } 2302 2303 2304 /* 2305 * Probe for a Broadcom chip. Check the PCI vendor and device IDs 2306 * against our list and return its name if we find a match. Note 2307 * that since the Broadcom controller contains VPD support, we 2308 * can get the device name string from the controller itself instead 2309 * of the compiled-in string. This is a little slow, but it guarantees 2310 * we'll always announce the right product name. 2311 */ 2312 static int 2313 bge_probe(device_t parent, cfdata_t match, void *aux) 2314 { 2315 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 2316 2317 if (bge_lookup(pa) != NULL) 2318 return (1); 2319 2320 return (0); 2321 } 2322 2323 static void 2324 bge_attach(device_t parent, device_t self, void *aux) 2325 { 2326 struct bge_softc *sc = (struct bge_softc *)self; 2327 struct pci_attach_args *pa = aux; 2328 const struct bge_product *bp; 2329 const struct bge_revision *br; 2330 pci_chipset_tag_t pc = pa->pa_pc; 2331 pci_intr_handle_t ih; 2332 const char *intrstr = NULL; 2333 bus_dma_segment_t seg; 2334 int rseg; 2335 u_int32_t hwcfg = 0; 2336 u_int32_t mac_addr = 0; 2337 u_int32_t command; 2338 struct ifnet *ifp; 2339 caddr_t kva; 2340 u_char eaddr[ETHER_ADDR_LEN]; 2341 pcireg_t memtype; 2342 bus_addr_t memaddr; 2343 bus_size_t memsize; 2344 u_int32_t pm_ctl; 2345 2346 bp = bge_lookup(pa); 2347 KASSERT(bp != NULL); 2348 2349 sc->bge_pa = *pa; 2350 2351 aprint_naive(": Ethernet controller\n"); 2352 aprint_normal(": %s\n", bp->bp_name); 2353 2354 /* 2355 * Map control/status registers. 2356 */ 2357 DPRINTFN(5, ("Map control/status regs\n")); 2358 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 2359 command |= PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_MASTER_ENABLE; 2360 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, command); 2361 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 2362 2363 if (!(command & PCI_COMMAND_MEM_ENABLE)) { 2364 aprint_error("%s: failed to enable memory mapping!\n", 2365 sc->bge_dev.dv_xname); 2366 return; 2367 } 2368 2369 DPRINTFN(5, ("pci_mem_find\n")); 2370 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, BGE_PCI_BAR0); 2371 switch (memtype) { 2372 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 2373 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 2374 if (pci_mapreg_map(pa, BGE_PCI_BAR0, 2375 memtype, 0, &sc->bge_btag, &sc->bge_bhandle, 2376 &memaddr, &memsize) == 0) 2377 break; 2378 default: 2379 aprint_error("%s: can't find mem space\n", 2380 sc->bge_dev.dv_xname); 2381 return; 2382 } 2383 2384 DPRINTFN(5, ("pci_intr_map\n")); 2385 if (pci_intr_map(pa, &ih)) { 2386 aprint_error("%s: couldn't map interrupt\n", 2387 sc->bge_dev.dv_xname); 2388 return; 2389 } 2390 2391 DPRINTFN(5, ("pci_intr_string\n")); 2392 intrstr = pci_intr_string(pc, ih); 2393 2394 DPRINTFN(5, ("pci_intr_establish\n")); 2395 sc->bge_intrhand = pci_intr_establish(pc, ih, IPL_NET, bge_intr, sc); 2396 2397 if (sc->bge_intrhand == NULL) { 2398 aprint_error("%s: couldn't establish interrupt", 2399 sc->bge_dev.dv_xname); 2400 if (intrstr != NULL) 2401 aprint_normal(" at %s", intrstr); 2402 aprint_normal("\n"); 2403 return; 2404 } 2405 aprint_normal("%s: interrupting at %s\n", 2406 sc->bge_dev.dv_xname, intrstr); 2407 2408 /* 2409 * Kludge for 5700 Bx bug: a hardware bug (PCIX byte enable?) 2410 * can clobber the chip's PCI config-space power control registers, 2411 * leaving the card in D3 powersave state. 2412 * We do not have memory-mapped registers in this state, 2413 * so force device into D0 state before starting initialization. 2414 */ 2415 pm_ctl = pci_conf_read(pc, pa->pa_tag, BGE_PCI_PWRMGMT_CMD); 2416 pm_ctl &= ~(PCI_PWR_D0|PCI_PWR_D1|PCI_PWR_D2|PCI_PWR_D3); 2417 pm_ctl |= (1 << 8) | PCI_PWR_D0 ; /* D0 state */ 2418 pci_conf_write(pc, pa->pa_tag, BGE_PCI_PWRMGMT_CMD, pm_ctl); 2419 DELAY(1000); /* 27 usec is allegedly sufficent */ 2420 2421 /* 2422 * Save ASIC rev. Look up any quirks associated with this 2423 * ASIC. 2424 */ 2425 sc->bge_chipid = 2426 pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_MISC_CTL) & 2427 BGE_PCIMISCCTL_ASICREV; 2428 2429 /* 2430 * Detect PCI-Express devices 2431 * XXX: guessed from Linux/FreeBSD; no documentation 2432 */ 2433 if (pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_PCIEXPRESS, 2434 NULL, NULL) != 0) 2435 sc->bge_pcie = 1; 2436 else 2437 sc->bge_pcie = 0; 2438 2439 /* Try to reset the chip. */ 2440 DPRINTFN(5, ("bge_reset\n")); 2441 bge_reset(sc); 2442 2443 if (bge_chipinit(sc)) { 2444 aprint_error("%s: chip initialization failed\n", 2445 sc->bge_dev.dv_xname); 2446 bge_release_resources(sc); 2447 return; 2448 } 2449 2450 /* 2451 * Get station address from the EEPROM. 2452 */ 2453 mac_addr = bge_readmem_ind(sc, 0x0c14); 2454 if ((mac_addr >> 16) == 0x484b) { 2455 eaddr[0] = (u_char)(mac_addr >> 8); 2456 eaddr[1] = (u_char)(mac_addr >> 0); 2457 mac_addr = bge_readmem_ind(sc, 0x0c18); 2458 eaddr[2] = (u_char)(mac_addr >> 24); 2459 eaddr[3] = (u_char)(mac_addr >> 16); 2460 eaddr[4] = (u_char)(mac_addr >> 8); 2461 eaddr[5] = (u_char)(mac_addr >> 0); 2462 } else if (bge_read_eeprom(sc, (caddr_t)eaddr, 2463 BGE_EE_MAC_OFFSET + 2, ETHER_ADDR_LEN)) { 2464 aprint_error("%s: failed to read station address\n", 2465 sc->bge_dev.dv_xname); 2466 bge_release_resources(sc); 2467 return; 2468 } 2469 2470 br = bge_lookup_rev(sc->bge_chipid); 2471 aprint_normal("%s: ", sc->bge_dev.dv_xname); 2472 2473 if (br == NULL) { 2474 aprint_normal("unknown ASIC (0x%04x)", sc->bge_chipid >> 16); 2475 sc->bge_quirks = 0; 2476 } else { 2477 aprint_normal("ASIC %s (0x%04x)", 2478 br->br_name, sc->bge_chipid >> 16); 2479 sc->bge_quirks |= br->br_quirks; 2480 } 2481 aprint_normal(", Ethernet address %s\n", ether_sprintf(eaddr)); 2482 2483 /* Allocate the general information block and ring buffers. */ 2484 if (pci_dma64_available(pa)) 2485 sc->bge_dmatag = pa->pa_dmat64; 2486 else 2487 sc->bge_dmatag = pa->pa_dmat; 2488 DPRINTFN(5, ("bus_dmamem_alloc\n")); 2489 if (bus_dmamem_alloc(sc->bge_dmatag, sizeof(struct bge_ring_data), 2490 PAGE_SIZE, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 2491 aprint_error("%s: can't alloc rx buffers\n", 2492 sc->bge_dev.dv_xname); 2493 return; 2494 } 2495 DPRINTFN(5, ("bus_dmamem_map\n")); 2496 if (bus_dmamem_map(sc->bge_dmatag, &seg, rseg, 2497 sizeof(struct bge_ring_data), &kva, 2498 BUS_DMA_NOWAIT)) { 2499 aprint_error("%s: can't map DMA buffers (%d bytes)\n", 2500 sc->bge_dev.dv_xname, (int)sizeof(struct bge_ring_data)); 2501 bus_dmamem_free(sc->bge_dmatag, &seg, rseg); 2502 return; 2503 } 2504 DPRINTFN(5, ("bus_dmamem_create\n")); 2505 if (bus_dmamap_create(sc->bge_dmatag, sizeof(struct bge_ring_data), 1, 2506 sizeof(struct bge_ring_data), 0, 2507 BUS_DMA_NOWAIT, &sc->bge_ring_map)) { 2508 aprint_error("%s: can't create DMA map\n", 2509 sc->bge_dev.dv_xname); 2510 bus_dmamem_unmap(sc->bge_dmatag, kva, 2511 sizeof(struct bge_ring_data)); 2512 bus_dmamem_free(sc->bge_dmatag, &seg, rseg); 2513 return; 2514 } 2515 DPRINTFN(5, ("bus_dmamem_load\n")); 2516 if (bus_dmamap_load(sc->bge_dmatag, sc->bge_ring_map, kva, 2517 sizeof(struct bge_ring_data), NULL, 2518 BUS_DMA_NOWAIT)) { 2519 bus_dmamap_destroy(sc->bge_dmatag, sc->bge_ring_map); 2520 bus_dmamem_unmap(sc->bge_dmatag, kva, 2521 sizeof(struct bge_ring_data)); 2522 bus_dmamem_free(sc->bge_dmatag, &seg, rseg); 2523 return; 2524 } 2525 2526 DPRINTFN(5, ("bzero\n")); 2527 sc->bge_rdata = (struct bge_ring_data *)kva; 2528 2529 memset(sc->bge_rdata, 0, sizeof(struct bge_ring_data)); 2530 2531 /* Try to allocate memory for jumbo buffers. */ 2532 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 2533 if (bge_alloc_jumbo_mem(sc)) { 2534 aprint_error("%s: jumbo buffer allocation failed\n", 2535 sc->bge_dev.dv_xname); 2536 } else 2537 sc->ethercom.ec_capabilities |= ETHERCAP_JUMBO_MTU; 2538 } 2539 2540 /* Set default tuneable values. */ 2541 sc->bge_stat_ticks = BGE_TICKS_PER_SEC; 2542 sc->bge_rx_coal_ticks = 150; 2543 sc->bge_rx_max_coal_bds = 64; 2544 #ifdef ORIG_WPAUL_VALUES 2545 sc->bge_tx_coal_ticks = 150; 2546 sc->bge_tx_max_coal_bds = 128; 2547 #else 2548 sc->bge_tx_coal_ticks = 300; 2549 sc->bge_tx_max_coal_bds = 400; 2550 #endif 2551 if (sc->bge_quirks & BGE_QUIRK_5705_CORE) { 2552 sc->bge_tx_coal_ticks = (12 * 5); 2553 sc->bge_rx_max_coal_bds = (12 * 5); 2554 aprint_verbose("%s: setting short Tx thresholds\n", 2555 sc->bge_dev.dv_xname); 2556 } 2557 2558 /* Set up ifnet structure */ 2559 ifp = &sc->ethercom.ec_if; 2560 ifp->if_softc = sc; 2561 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 2562 ifp->if_ioctl = bge_ioctl; 2563 ifp->if_start = bge_start; 2564 ifp->if_init = bge_init; 2565 ifp->if_watchdog = bge_watchdog; 2566 IFQ_SET_MAXLEN(&ifp->if_snd, max(BGE_TX_RING_CNT - 1, IFQ_MAXLEN)); 2567 IFQ_SET_READY(&ifp->if_snd); 2568 DPRINTFN(5, ("strcpy if_xname\n")); 2569 strcpy(ifp->if_xname, sc->bge_dev.dv_xname); 2570 2571 if ((sc->bge_quirks & BGE_QUIRK_CSUM_BROKEN) == 0) 2572 sc->ethercom.ec_if.if_capabilities |= 2573 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 2574 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 2575 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 2576 sc->ethercom.ec_capabilities |= 2577 ETHERCAP_VLAN_HWTAGGING | ETHERCAP_VLAN_MTU; 2578 2579 if (sc->bge_pcie) 2580 sc->ethercom.ec_if.if_capabilities |= IFCAP_TSOv4; 2581 2582 /* 2583 * Do MII setup. 2584 */ 2585 DPRINTFN(5, ("mii setup\n")); 2586 sc->bge_mii.mii_ifp = ifp; 2587 sc->bge_mii.mii_readreg = bge_miibus_readreg; 2588 sc->bge_mii.mii_writereg = bge_miibus_writereg; 2589 sc->bge_mii.mii_statchg = bge_miibus_statchg; 2590 2591 /* 2592 * Figure out what sort of media we have by checking the 2593 * hardware config word in the first 32k of NIC internal memory, 2594 * or fall back to the config word in the EEPROM. Note: on some BCM5700 2595 * cards, this value appears to be unset. If that's the 2596 * case, we have to rely on identifying the NIC by its PCI 2597 * subsystem ID, as we do below for the SysKonnect SK-9D41. 2598 */ 2599 if (bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_SIG) == BGE_MAGIC_NUMBER) { 2600 hwcfg = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_NICCFG); 2601 } else { 2602 bge_read_eeprom(sc, (caddr_t)&hwcfg, 2603 BGE_EE_HWCFG_OFFSET, sizeof(hwcfg)); 2604 hwcfg = be32toh(hwcfg); 2605 } 2606 if ((hwcfg & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER) 2607 sc->bge_tbi = 1; 2608 2609 /* The SysKonnect SK-9D41 is a 1000baseSX card. */ 2610 if ((pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_SUBSYS) >> 16) == 2611 SK_SUBSYSID_9D41) 2612 sc->bge_tbi = 1; 2613 2614 if (sc->bge_tbi) { 2615 ifmedia_init(&sc->bge_ifmedia, IFM_IMASK, bge_ifmedia_upd, 2616 bge_ifmedia_sts); 2617 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL); 2618 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_1000_SX|IFM_FDX, 2619 0, NULL); 2620 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL); 2621 ifmedia_set(&sc->bge_ifmedia, IFM_ETHER|IFM_AUTO); 2622 } else { 2623 /* 2624 * Do transceiver setup. 2625 */ 2626 ifmedia_init(&sc->bge_mii.mii_media, 0, bge_ifmedia_upd, 2627 bge_ifmedia_sts); 2628 mii_attach(&sc->bge_dev, &sc->bge_mii, 0xffffffff, 2629 MII_PHY_ANY, MII_OFFSET_ANY, 2630 MIIF_FORCEANEG|MIIF_DOPAUSE); 2631 2632 if (LIST_FIRST(&sc->bge_mii.mii_phys) == NULL) { 2633 printf("%s: no PHY found!\n", sc->bge_dev.dv_xname); 2634 ifmedia_add(&sc->bge_mii.mii_media, 2635 IFM_ETHER|IFM_MANUAL, 0, NULL); 2636 ifmedia_set(&sc->bge_mii.mii_media, 2637 IFM_ETHER|IFM_MANUAL); 2638 } else 2639 ifmedia_set(&sc->bge_mii.mii_media, 2640 IFM_ETHER|IFM_AUTO); 2641 } 2642 2643 /* 2644 * When using the BCM5701 in PCI-X mode, data corruption has 2645 * been observed in the first few bytes of some received packets. 2646 * Aligning the packet buffer in memory eliminates the corruption. 2647 * Unfortunately, this misaligns the packet payloads. On platforms 2648 * which do not support unaligned accesses, we will realign the 2649 * payloads by copying the received packets. 2650 */ 2651 if (sc->bge_quirks & BGE_QUIRK_PCIX_DMA_ALIGN_BUG) { 2652 /* If in PCI-X mode, work around the alignment bug. */ 2653 if ((pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_PCISTATE) & 2654 (BGE_PCISTATE_PCI_BUSMODE | BGE_PCISTATE_PCI_BUSSPEED)) == 2655 BGE_PCISTATE_PCI_BUSSPEED) 2656 sc->bge_rx_alignment_bug = 1; 2657 } 2658 2659 /* 2660 * Call MI attach routine. 2661 */ 2662 DPRINTFN(5, ("if_attach\n")); 2663 if_attach(ifp); 2664 DPRINTFN(5, ("ether_ifattach\n")); 2665 ether_ifattach(ifp, eaddr); 2666 #ifdef BGE_EVENT_COUNTERS 2667 /* 2668 * Attach event counters. 2669 */ 2670 evcnt_attach_dynamic(&sc->bge_ev_intr, EVCNT_TYPE_INTR, 2671 NULL, sc->bge_dev.dv_xname, "intr"); 2672 evcnt_attach_dynamic(&sc->bge_ev_tx_xoff, EVCNT_TYPE_MISC, 2673 NULL, sc->bge_dev.dv_xname, "tx_xoff"); 2674 evcnt_attach_dynamic(&sc->bge_ev_tx_xon, EVCNT_TYPE_MISC, 2675 NULL, sc->bge_dev.dv_xname, "tx_xon"); 2676 evcnt_attach_dynamic(&sc->bge_ev_rx_xoff, EVCNT_TYPE_MISC, 2677 NULL, sc->bge_dev.dv_xname, "rx_xoff"); 2678 evcnt_attach_dynamic(&sc->bge_ev_rx_xon, EVCNT_TYPE_MISC, 2679 NULL, sc->bge_dev.dv_xname, "rx_xon"); 2680 evcnt_attach_dynamic(&sc->bge_ev_rx_macctl, EVCNT_TYPE_MISC, 2681 NULL, sc->bge_dev.dv_xname, "rx_macctl"); 2682 evcnt_attach_dynamic(&sc->bge_ev_xoffentered, EVCNT_TYPE_MISC, 2683 NULL, sc->bge_dev.dv_xname, "xoffentered"); 2684 #endif /* BGE_EVENT_COUNTERS */ 2685 DPRINTFN(5, ("callout_init\n")); 2686 callout_init(&sc->bge_timeout); 2687 2688 sc->bge_powerhook = powerhook_establish(sc->bge_dev.dv_xname, 2689 bge_powerhook, sc); 2690 if (sc->bge_powerhook == NULL) 2691 printf("%s: WARNING: unable to establish PCI power hook\n", 2692 sc->bge_dev.dv_xname); 2693 } 2694 2695 static void 2696 bge_release_resources(struct bge_softc *sc) 2697 { 2698 if (sc->bge_vpd_prodname != NULL) 2699 free(sc->bge_vpd_prodname, M_DEVBUF); 2700 2701 if (sc->bge_vpd_readonly != NULL) 2702 free(sc->bge_vpd_readonly, M_DEVBUF); 2703 } 2704 2705 static void 2706 bge_reset(struct bge_softc *sc) 2707 { 2708 struct pci_attach_args *pa = &sc->bge_pa; 2709 u_int32_t cachesize, command, pcistate, new_pcistate; 2710 int i, val; 2711 2712 /* Save some important PCI state. */ 2713 cachesize = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_CACHESZ); 2714 command = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_CMD); 2715 pcistate = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_PCISTATE); 2716 2717 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_MISC_CTL, 2718 BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR| 2719 BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_PCISTATE_RW); 2720 2721 /* 2722 * Disable the firmware fastboot feature on 5752 ASIC 2723 * to avoid firmware timeout. 2724 */ 2725 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5752) 2726 CSR_WRITE_4(sc, BGE_FASTBOOT_PC, 0); 2727 2728 val = BGE_MISCCFG_RESET_CORE_CLOCKS | (65<<1); 2729 /* 2730 * XXX: from FreeBSD/Linux; no documentation 2731 */ 2732 if (sc->bge_pcie) { 2733 if (CSR_READ_4(sc, BGE_PCIE_CTL1) == 0x60) 2734 CSR_WRITE_4(sc, BGE_PCIE_CTL1, 0x20); 2735 if (sc->bge_chipid != BGE_CHIPID_BCM5750_A0) { 2736 /* No idea what that actually means */ 2737 CSR_WRITE_4(sc, BGE_MISC_CFG, 1 << 29); 2738 val |= (1<<29); 2739 } 2740 } 2741 2742 /* Issue global reset */ 2743 bge_writereg_ind(sc, BGE_MISC_CFG, val); 2744 2745 DELAY(1000); 2746 2747 /* 2748 * XXX: from FreeBSD/Linux; no documentation 2749 */ 2750 if (sc->bge_pcie) { 2751 if (sc->bge_chipid == BGE_CHIPID_BCM5750_A0) { 2752 pcireg_t reg; 2753 2754 DELAY(500000); 2755 /* XXX: Magic Numbers */ 2756 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_UNKNOWN0); 2757 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_UNKNOWN0, 2758 reg | (1 << 15)); 2759 } 2760 /* 2761 * XXX: Magic Numbers. 2762 * Sets maximal PCI-e payload and clears any PCI-e errors. 2763 * Should be replaced with references to PCI config-space 2764 * capability block for PCI-Express. 2765 */ 2766 pci_conf_write(pa->pa_pc, pa->pa_tag, 2767 BGE_PCI_CONF_DEV_CTRL, 0xf5000); 2768 2769 } 2770 2771 /* Reset some of the PCI state that got zapped by reset */ 2772 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_MISC_CTL, 2773 BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR| 2774 BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_PCISTATE_RW); 2775 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_CMD, command); 2776 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_CACHESZ, cachesize); 2777 bge_writereg_ind(sc, BGE_MISC_CFG, (65 << 1)); 2778 2779 /* Enable memory arbiter. */ 2780 { 2781 uint32_t marbmode = 0; 2782 if (BGE_IS_5714_FAMILY(sc)) { 2783 marbmode = CSR_READ_4(sc, BGE_MARB_MODE); 2784 } 2785 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE | marbmode); 2786 } 2787 2788 /* 2789 * Prevent PXE restart: write a magic number to the 2790 * general communications memory at 0xB50. 2791 */ 2792 bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM, BGE_MAGIC_NUMBER); 2793 2794 /* 2795 * Poll the value location we just wrote until 2796 * we see the 1's complement of the magic number. 2797 * This indicates that the firmware initialization 2798 * is complete. 2799 */ 2800 for (i = 0; i < BGE_TIMEOUT; i++) { 2801 val = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM); 2802 if (val == ~BGE_MAGIC_NUMBER) 2803 break; 2804 DELAY(1000); 2805 } 2806 2807 if (i >= BGE_TIMEOUT) { 2808 printf("%s: firmware handshake timed out, val = %x\n", 2809 sc->bge_dev.dv_xname, val); 2810 /* 2811 * XXX: occasionally fired on bcm5721, but without 2812 * apparent harm. For now, keep going if we timeout 2813 * against PCI-E devices. 2814 */ 2815 if (!sc->bge_pcie) 2816 return; 2817 } 2818 2819 /* 2820 * XXX Wait for the value of the PCISTATE register to 2821 * return to its original pre-reset state. This is a 2822 * fairly good indicator of reset completion. If we don't 2823 * wait for the reset to fully complete, trying to read 2824 * from the device's non-PCI registers may yield garbage 2825 * results. 2826 */ 2827 for (i = 0; i < BGE_TIMEOUT; i++) { 2828 new_pcistate = pci_conf_read(pa->pa_pc, pa->pa_tag, 2829 BGE_PCI_PCISTATE); 2830 if ((new_pcistate & ~BGE_PCISTATE_RESERVED) == 2831 (pcistate & ~BGE_PCISTATE_RESERVED)) 2832 break; 2833 DELAY(10); 2834 } 2835 if ((new_pcistate & ~BGE_PCISTATE_RESERVED) != 2836 (pcistate & ~BGE_PCISTATE_RESERVED)) { 2837 printf("%s: pcistate failed to revert\n", 2838 sc->bge_dev.dv_xname); 2839 } 2840 2841 /* XXX: from FreeBSD/Linux; no documentation */ 2842 if (sc->bge_pcie && sc->bge_chipid != BGE_CHIPID_BCM5750_A0) 2843 CSR_WRITE_4(sc, BGE_PCIE_CTL0, CSR_READ_4(sc, BGE_PCIE_CTL0) | (1<<25)); 2844 2845 /* Enable memory arbiter. */ 2846 /* XXX why do this twice? */ 2847 { 2848 uint32_t marbmode = 0; 2849 if (BGE_IS_5714_FAMILY(sc)) { 2850 marbmode = CSR_READ_4(sc, BGE_MARB_MODE); 2851 } 2852 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE | marbmode); 2853 } 2854 2855 /* Fix up byte swapping */ 2856 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS); 2857 2858 CSR_WRITE_4(sc, BGE_MAC_MODE, 0); 2859 2860 DELAY(10000); 2861 } 2862 2863 /* 2864 * Frame reception handling. This is called if there's a frame 2865 * on the receive return list. 2866 * 2867 * Note: we have to be able to handle two possibilities here: 2868 * 1) the frame is from the jumbo recieve ring 2869 * 2) the frame is from the standard receive ring 2870 */ 2871 2872 static void 2873 bge_rxeof(struct bge_softc *sc) 2874 { 2875 struct ifnet *ifp; 2876 int stdcnt = 0, jumbocnt = 0; 2877 bus_dmamap_t dmamap; 2878 bus_addr_t offset, toff; 2879 bus_size_t tlen; 2880 int tosync; 2881 2882 ifp = &sc->ethercom.ec_if; 2883 2884 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 2885 offsetof(struct bge_ring_data, bge_status_block), 2886 sizeof (struct bge_status_block), 2887 BUS_DMASYNC_POSTREAD); 2888 2889 offset = offsetof(struct bge_ring_data, bge_rx_return_ring); 2890 tosync = sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx - 2891 sc->bge_rx_saved_considx; 2892 2893 toff = offset + (sc->bge_rx_saved_considx * sizeof (struct bge_rx_bd)); 2894 2895 if (tosync < 0) { 2896 tlen = (sc->bge_return_ring_cnt - sc->bge_rx_saved_considx) * 2897 sizeof (struct bge_rx_bd); 2898 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 2899 toff, tlen, BUS_DMASYNC_POSTREAD); 2900 tosync = -tosync; 2901 } 2902 2903 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 2904 offset, tosync * sizeof (struct bge_rx_bd), 2905 BUS_DMASYNC_POSTREAD); 2906 2907 while(sc->bge_rx_saved_considx != 2908 sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx) { 2909 struct bge_rx_bd *cur_rx; 2910 u_int32_t rxidx; 2911 struct mbuf *m = NULL; 2912 2913 cur_rx = &sc->bge_rdata-> 2914 bge_rx_return_ring[sc->bge_rx_saved_considx]; 2915 2916 rxidx = cur_rx->bge_idx; 2917 BGE_INC(sc->bge_rx_saved_considx, sc->bge_return_ring_cnt); 2918 2919 if (cur_rx->bge_flags & BGE_RXBDFLAG_JUMBO_RING) { 2920 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT); 2921 m = sc->bge_cdata.bge_rx_jumbo_chain[rxidx]; 2922 sc->bge_cdata.bge_rx_jumbo_chain[rxidx] = NULL; 2923 jumbocnt++; 2924 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 2925 ifp->if_ierrors++; 2926 bge_newbuf_jumbo(sc, sc->bge_jumbo, m); 2927 continue; 2928 } 2929 if (bge_newbuf_jumbo(sc, sc->bge_jumbo, 2930 NULL)== ENOBUFS) { 2931 ifp->if_ierrors++; 2932 bge_newbuf_jumbo(sc, sc->bge_jumbo, m); 2933 continue; 2934 } 2935 } else { 2936 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT); 2937 m = sc->bge_cdata.bge_rx_std_chain[rxidx]; 2938 sc->bge_cdata.bge_rx_std_chain[rxidx] = NULL; 2939 stdcnt++; 2940 dmamap = sc->bge_cdata.bge_rx_std_map[rxidx]; 2941 sc->bge_cdata.bge_rx_std_map[rxidx] = 0; 2942 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 2943 ifp->if_ierrors++; 2944 bge_newbuf_std(sc, sc->bge_std, m, dmamap); 2945 continue; 2946 } 2947 if (bge_newbuf_std(sc, sc->bge_std, 2948 NULL, dmamap) == ENOBUFS) { 2949 ifp->if_ierrors++; 2950 bge_newbuf_std(sc, sc->bge_std, m, dmamap); 2951 continue; 2952 } 2953 } 2954 2955 ifp->if_ipackets++; 2956 #ifndef __NO_STRICT_ALIGNMENT 2957 /* 2958 * XXX: if the 5701 PCIX-Rx-DMA workaround is in effect, 2959 * the Rx buffer has the layer-2 header unaligned. 2960 * If our CPU requires alignment, re-align by copying. 2961 */ 2962 if (sc->bge_rx_alignment_bug) { 2963 memmove(mtod(m, caddr_t) + ETHER_ALIGN, m->m_data, 2964 cur_rx->bge_len); 2965 m->m_data += ETHER_ALIGN; 2966 } 2967 #endif 2968 2969 m->m_pkthdr.len = m->m_len = cur_rx->bge_len - ETHER_CRC_LEN; 2970 m->m_pkthdr.rcvif = ifp; 2971 2972 #if NBPFILTER > 0 2973 /* 2974 * Handle BPF listeners. Let the BPF user see the packet. 2975 */ 2976 if (ifp->if_bpf) 2977 bpf_mtap(ifp->if_bpf, m); 2978 #endif 2979 2980 m->m_pkthdr.csum_flags = M_CSUM_IPv4; 2981 2982 if ((cur_rx->bge_ip_csum ^ 0xffff) != 0) 2983 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 2984 /* 2985 * Rx transport checksum-offload may also 2986 * have bugs with packets which, when transmitted, 2987 * were `runts' requiring padding. 2988 */ 2989 if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM && 2990 (/* (sc->_bge_quirks & BGE_QUIRK_SHORT_CKSUM_BUG) == 0 ||*/ 2991 m->m_pkthdr.len >= ETHER_MIN_NOPAD)) { 2992 m->m_pkthdr.csum_data = 2993 cur_rx->bge_tcp_udp_csum; 2994 m->m_pkthdr.csum_flags |= 2995 (M_CSUM_TCPv4|M_CSUM_UDPv4| 2996 M_CSUM_DATA|M_CSUM_NO_PSEUDOHDR); 2997 } 2998 2999 /* 3000 * If we received a packet with a vlan tag, pass it 3001 * to vlan_input() instead of ether_input(). 3002 */ 3003 if (cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) 3004 VLAN_INPUT_TAG(ifp, m, cur_rx->bge_vlan_tag, continue); 3005 3006 (*ifp->if_input)(ifp, m); 3007 } 3008 3009 CSR_WRITE_4(sc, BGE_MBX_RX_CONS0_LO, sc->bge_rx_saved_considx); 3010 if (stdcnt) 3011 CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std); 3012 if (jumbocnt) 3013 CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo); 3014 } 3015 3016 static void 3017 bge_txeof(struct bge_softc *sc) 3018 { 3019 struct bge_tx_bd *cur_tx = NULL; 3020 struct ifnet *ifp; 3021 struct txdmamap_pool_entry *dma; 3022 bus_addr_t offset, toff; 3023 bus_size_t tlen; 3024 int tosync; 3025 struct mbuf *m; 3026 3027 ifp = &sc->ethercom.ec_if; 3028 3029 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 3030 offsetof(struct bge_ring_data, bge_status_block), 3031 sizeof (struct bge_status_block), 3032 BUS_DMASYNC_POSTREAD); 3033 3034 offset = offsetof(struct bge_ring_data, bge_tx_ring); 3035 tosync = sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx - 3036 sc->bge_tx_saved_considx; 3037 3038 toff = offset + (sc->bge_tx_saved_considx * sizeof (struct bge_tx_bd)); 3039 3040 if (tosync < 0) { 3041 tlen = (BGE_TX_RING_CNT - sc->bge_tx_saved_considx) * 3042 sizeof (struct bge_tx_bd); 3043 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 3044 toff, tlen, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 3045 tosync = -tosync; 3046 } 3047 3048 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 3049 offset, tosync * sizeof (struct bge_tx_bd), 3050 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 3051 3052 /* 3053 * Go through our tx ring and free mbufs for those 3054 * frames that have been sent. 3055 */ 3056 while (sc->bge_tx_saved_considx != 3057 sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx) { 3058 u_int32_t idx = 0; 3059 3060 idx = sc->bge_tx_saved_considx; 3061 cur_tx = &sc->bge_rdata->bge_tx_ring[idx]; 3062 if (cur_tx->bge_flags & BGE_TXBDFLAG_END) 3063 ifp->if_opackets++; 3064 m = sc->bge_cdata.bge_tx_chain[idx]; 3065 if (m != NULL) { 3066 sc->bge_cdata.bge_tx_chain[idx] = NULL; 3067 dma = sc->txdma[idx]; 3068 bus_dmamap_sync(sc->bge_dmatag, dma->dmamap, 0, 3069 dma->dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 3070 bus_dmamap_unload(sc->bge_dmatag, dma->dmamap); 3071 SLIST_INSERT_HEAD(&sc->txdma_list, dma, link); 3072 sc->txdma[idx] = NULL; 3073 3074 m_freem(m); 3075 } 3076 sc->bge_txcnt--; 3077 BGE_INC(sc->bge_tx_saved_considx, BGE_TX_RING_CNT); 3078 ifp->if_timer = 0; 3079 } 3080 3081 if (cur_tx != NULL) 3082 ifp->if_flags &= ~IFF_OACTIVE; 3083 } 3084 3085 static int 3086 bge_intr(void *xsc) 3087 { 3088 struct bge_softc *sc; 3089 struct ifnet *ifp; 3090 3091 sc = xsc; 3092 ifp = &sc->ethercom.ec_if; 3093 3094 #ifdef notdef 3095 /* Avoid this for now -- checking this register is expensive. */ 3096 /* Make sure this is really our interrupt. */ 3097 if (!(CSR_READ_4(sc, BGE_MISC_LOCAL_CTL) & BGE_MLC_INTR_STATE)) 3098 return (0); 3099 #endif 3100 /* Ack interrupt and stop others from occuring. */ 3101 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 1); 3102 3103 BGE_EVCNT_INCR(sc->bge_ev_intr); 3104 3105 /* 3106 * Process link state changes. 3107 * Grrr. The link status word in the status block does 3108 * not work correctly on the BCM5700 rev AX and BX chips, 3109 * according to all available information. Hence, we have 3110 * to enable MII interrupts in order to properly obtain 3111 * async link changes. Unfortunately, this also means that 3112 * we have to read the MAC status register to detect link 3113 * changes, thereby adding an additional register access to 3114 * the interrupt handler. 3115 */ 3116 3117 if (sc->bge_quirks & BGE_QUIRK_LINK_STATE_BROKEN) { 3118 u_int32_t status; 3119 3120 status = CSR_READ_4(sc, BGE_MAC_STS); 3121 if (status & BGE_MACSTAT_MI_INTERRUPT) { 3122 sc->bge_link = 0; 3123 callout_stop(&sc->bge_timeout); 3124 bge_tick(sc); 3125 /* Clear the interrupt */ 3126 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, 3127 BGE_EVTENB_MI_INTERRUPT); 3128 bge_miibus_readreg(&sc->bge_dev, 1, BRGPHY_MII_ISR); 3129 bge_miibus_writereg(&sc->bge_dev, 1, BRGPHY_MII_IMR, 3130 BRGPHY_INTRS); 3131 } 3132 } else { 3133 if (sc->bge_rdata->bge_status_block.bge_status & 3134 BGE_STATFLAG_LINKSTATE_CHANGED) { 3135 sc->bge_link = 0; 3136 callout_stop(&sc->bge_timeout); 3137 bge_tick(sc); 3138 /* Clear the interrupt */ 3139 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED| 3140 BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE| 3141 BGE_MACSTAT_LINK_CHANGED); 3142 } 3143 } 3144 3145 if (ifp->if_flags & IFF_RUNNING) { 3146 /* Check RX return ring producer/consumer */ 3147 bge_rxeof(sc); 3148 3149 /* Check TX ring producer/consumer */ 3150 bge_txeof(sc); 3151 } 3152 3153 if (sc->bge_pending_rxintr_change) { 3154 uint32_t rx_ticks = sc->bge_rx_coal_ticks; 3155 uint32_t rx_bds = sc->bge_rx_max_coal_bds; 3156 uint32_t junk; 3157 3158 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, rx_ticks); 3159 DELAY(10); 3160 junk = CSR_READ_4(sc, BGE_HCC_RX_COAL_TICKS); 3161 3162 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, rx_bds); 3163 DELAY(10); 3164 junk = CSR_READ_4(sc, BGE_HCC_RX_MAX_COAL_BDS); 3165 3166 sc->bge_pending_rxintr_change = 0; 3167 } 3168 bge_handle_events(sc); 3169 3170 /* Re-enable interrupts. */ 3171 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 0); 3172 3173 if (ifp->if_flags & IFF_RUNNING && !IFQ_IS_EMPTY(&ifp->if_snd)) 3174 bge_start(ifp); 3175 3176 return (1); 3177 } 3178 3179 static void 3180 bge_tick(void *xsc) 3181 { 3182 struct bge_softc *sc = xsc; 3183 struct mii_data *mii = &sc->bge_mii; 3184 struct ifmedia *ifm = NULL; 3185 struct ifnet *ifp = &sc->ethercom.ec_if; 3186 int s; 3187 3188 s = splnet(); 3189 3190 bge_stats_update(sc); 3191 callout_reset(&sc->bge_timeout, hz, bge_tick, sc); 3192 if (sc->bge_link) { 3193 splx(s); 3194 return; 3195 } 3196 3197 if (sc->bge_tbi) { 3198 ifm = &sc->bge_ifmedia; 3199 if (CSR_READ_4(sc, BGE_MAC_STS) & 3200 BGE_MACSTAT_TBI_PCS_SYNCHED) { 3201 sc->bge_link++; 3202 CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF); 3203 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 3204 bge_start(ifp); 3205 } 3206 splx(s); 3207 return; 3208 } 3209 3210 mii_tick(mii); 3211 3212 if (!sc->bge_link && mii->mii_media_status & IFM_ACTIVE && 3213 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 3214 sc->bge_link++; 3215 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 3216 bge_start(ifp); 3217 } 3218 3219 splx(s); 3220 } 3221 3222 static void 3223 bge_stats_update(struct bge_softc *sc) 3224 { 3225 struct ifnet *ifp = &sc->ethercom.ec_if; 3226 bus_size_t stats = BGE_MEMWIN_START + BGE_STATS_BLOCK; 3227 bus_size_t rstats = BGE_RX_STATS; 3228 3229 #define READ_RSTAT(sc, stats, stat) \ 3230 CSR_READ_4(sc, stats + offsetof(struct bge_mac_stats_regs, stat)) 3231 3232 if (sc->bge_quirks & BGE_QUIRK_5705_CORE) { 3233 ifp->if_collisions += 3234 READ_RSTAT(sc, rstats, dot3StatsSingleCollisionFrames) + 3235 READ_RSTAT(sc, rstats, dot3StatsMultipleCollisionFrames) + 3236 READ_RSTAT(sc, rstats, dot3StatsExcessiveCollisions) + 3237 READ_RSTAT(sc, rstats, dot3StatsLateCollisions); 3238 3239 BGE_EVCNT_ADD(sc->bge_ev_tx_xoff, 3240 READ_RSTAT(sc, rstats, outXoffSent)); 3241 BGE_EVCNT_ADD(sc->bge_ev_tx_xon, 3242 READ_RSTAT(sc, rstats, outXonSent)); 3243 BGE_EVCNT_ADD(sc->bge_ev_rx_xoff, 3244 READ_RSTAT(sc, rstats, xoffPauseFramesReceived)); 3245 BGE_EVCNT_ADD(sc->bge_ev_rx_xon, 3246 READ_RSTAT(sc, rstats, xonPauseFramesReceived)); 3247 BGE_EVCNT_ADD(sc->bge_ev_rx_macctl, 3248 READ_RSTAT(sc, rstats, macControlFramesReceived)); 3249 BGE_EVCNT_ADD(sc->bge_ev_xoffentered, 3250 READ_RSTAT(sc, rstats, xoffStateEntered)); 3251 return; 3252 } 3253 3254 #undef READ_RSTAT 3255 #define READ_STAT(sc, stats, stat) \ 3256 CSR_READ_4(sc, stats + offsetof(struct bge_stats, stat)) 3257 3258 ifp->if_collisions += 3259 (READ_STAT(sc, stats, dot3StatsSingleCollisionFrames.bge_addr_lo) + 3260 READ_STAT(sc, stats, dot3StatsMultipleCollisionFrames.bge_addr_lo) + 3261 READ_STAT(sc, stats, dot3StatsExcessiveCollisions.bge_addr_lo) + 3262 READ_STAT(sc, stats, dot3StatsLateCollisions.bge_addr_lo)) - 3263 ifp->if_collisions; 3264 3265 BGE_EVCNT_UPD(sc->bge_ev_tx_xoff, 3266 READ_STAT(sc, stats, outXoffSent.bge_addr_lo)); 3267 BGE_EVCNT_UPD(sc->bge_ev_tx_xon, 3268 READ_STAT(sc, stats, outXonSent.bge_addr_lo)); 3269 BGE_EVCNT_UPD(sc->bge_ev_rx_xoff, 3270 READ_STAT(sc, stats, 3271 xoffPauseFramesReceived.bge_addr_lo)); 3272 BGE_EVCNT_UPD(sc->bge_ev_rx_xon, 3273 READ_STAT(sc, stats, xonPauseFramesReceived.bge_addr_lo)); 3274 BGE_EVCNT_UPD(sc->bge_ev_rx_macctl, 3275 READ_STAT(sc, stats, 3276 macControlFramesReceived.bge_addr_lo)); 3277 BGE_EVCNT_UPD(sc->bge_ev_xoffentered, 3278 READ_STAT(sc, stats, xoffStateEntered.bge_addr_lo)); 3279 3280 #undef READ_STAT 3281 3282 #ifdef notdef 3283 ifp->if_collisions += 3284 (sc->bge_rdata->bge_info.bge_stats.dot3StatsSingleCollisionFrames + 3285 sc->bge_rdata->bge_info.bge_stats.dot3StatsMultipleCollisionFrames + 3286 sc->bge_rdata->bge_info.bge_stats.dot3StatsExcessiveCollisions + 3287 sc->bge_rdata->bge_info.bge_stats.dot3StatsLateCollisions) - 3288 ifp->if_collisions; 3289 #endif 3290 } 3291 3292 /* 3293 * Pad outbound frame to ETHER_MIN_NOPAD for an unusual reason. 3294 * The bge hardware will pad out Tx runts to ETHER_MIN_NOPAD, 3295 * but when such padded frames employ the bge IP/TCP checksum offload, 3296 * the hardware checksum assist gives incorrect results (possibly 3297 * from incorporating its own padding into the UDP/TCP checksum; who knows). 3298 * If we pad such runts with zeros, the onboard checksum comes out correct. 3299 */ 3300 static inline int 3301 bge_cksum_pad(struct mbuf *pkt) 3302 { 3303 struct mbuf *last = NULL; 3304 int padlen; 3305 3306 padlen = ETHER_MIN_NOPAD - pkt->m_pkthdr.len; 3307 3308 /* if there's only the packet-header and we can pad there, use it. */ 3309 if (pkt->m_pkthdr.len == pkt->m_len && 3310 M_TRAILINGSPACE(pkt) >= padlen) { 3311 last = pkt; 3312 } else { 3313 /* 3314 * Walk packet chain to find last mbuf. We will either 3315 * pad there, or append a new mbuf and pad it 3316 * (thus perhaps avoiding the bcm5700 dma-min bug). 3317 */ 3318 for (last = pkt; last->m_next != NULL; last = last->m_next) { 3319 continue; /* do nothing */ 3320 } 3321 3322 /* `last' now points to last in chain. */ 3323 if (M_TRAILINGSPACE(last) < padlen) { 3324 /* Allocate new empty mbuf, pad it. Compact later. */ 3325 struct mbuf *n; 3326 MGET(n, M_DONTWAIT, MT_DATA); 3327 n->m_len = 0; 3328 last->m_next = n; 3329 last = n; 3330 } 3331 } 3332 3333 KDASSERT(!M_READONLY(last)); 3334 KDASSERT(M_TRAILINGSPACE(last) >= padlen); 3335 3336 /* Now zero the pad area, to avoid the bge cksum-assist bug */ 3337 memset(mtod(last, caddr_t) + last->m_len, 0, padlen); 3338 last->m_len += padlen; 3339 pkt->m_pkthdr.len += padlen; 3340 return 0; 3341 } 3342 3343 /* 3344 * Compact outbound packets to avoid bug with DMA segments less than 8 bytes. 3345 */ 3346 static inline int 3347 bge_compact_dma_runt(struct mbuf *pkt) 3348 { 3349 struct mbuf *m, *prev; 3350 int totlen, prevlen; 3351 3352 prev = NULL; 3353 totlen = 0; 3354 prevlen = -1; 3355 3356 for (m = pkt; m != NULL; prev = m,m = m->m_next) { 3357 int mlen = m->m_len; 3358 int shortfall = 8 - mlen ; 3359 3360 totlen += mlen; 3361 if (mlen == 0) { 3362 continue; 3363 } 3364 if (mlen >= 8) 3365 continue; 3366 3367 /* If we get here, mbuf data is too small for DMA engine. 3368 * Try to fix by shuffling data to prev or next in chain. 3369 * If that fails, do a compacting deep-copy of the whole chain. 3370 */ 3371 3372 /* Internal frag. If fits in prev, copy it there. */ 3373 if (prev && M_TRAILINGSPACE(prev) >= m->m_len) { 3374 memcpy(prev->m_data + prev->m_len, m->m_data, mlen); 3375 prev->m_len += mlen; 3376 m->m_len = 0; 3377 /* XXX stitch chain */ 3378 prev->m_next = m_free(m); 3379 m = prev; 3380 continue; 3381 } 3382 else if (m->m_next != NULL && 3383 M_TRAILINGSPACE(m) >= shortfall && 3384 m->m_next->m_len >= (8 + shortfall)) { 3385 /* m is writable and have enough data in next, pull up. */ 3386 3387 memcpy(m->m_data + m->m_len, m->m_next->m_data, 3388 shortfall); 3389 m->m_len += shortfall; 3390 m->m_next->m_len -= shortfall; 3391 m->m_next->m_data += shortfall; 3392 } 3393 else if (m->m_next == NULL || 1) { 3394 /* Got a runt at the very end of the packet. 3395 * borrow data from the tail of the preceding mbuf and 3396 * update its length in-place. (The original data is still 3397 * valid, so we can do this even if prev is not writable.) 3398 */ 3399 3400 /* if we'd make prev a runt, just move all of its data. */ 3401 KASSERT(prev != NULL /*, ("runt but null PREV")*/); 3402 KASSERT(prev->m_len >= 8 /*, ("runt prev")*/); 3403 3404 if ((prev->m_len - shortfall) < 8) 3405 shortfall = prev->m_len; 3406 3407 #ifdef notyet /* just do the safe slow thing for now */ 3408 if (!M_READONLY(m)) { 3409 if (M_LEADINGSPACE(m) < shorfall) { 3410 void *m_dat; 3411 m_dat = (m->m_flags & M_PKTHDR) ? 3412 m->m_pktdat : m->dat; 3413 memmove(m_dat, mtod(m, void*), m->m_len); 3414 m->m_data = m_dat; 3415 } 3416 } else 3417 #endif /* just do the safe slow thing */ 3418 { 3419 struct mbuf * n = NULL; 3420 int newprevlen = prev->m_len - shortfall; 3421 3422 MGET(n, M_NOWAIT, MT_DATA); 3423 if (n == NULL) 3424 return ENOBUFS; 3425 KASSERT(m->m_len + shortfall < MLEN 3426 /*, 3427 ("runt %d +prev %d too big\n", m->m_len, shortfall)*/); 3428 3429 /* first copy the data we're stealing from prev */ 3430 memcpy(n->m_data, prev->m_data + newprevlen, 3431 shortfall); 3432 3433 /* update prev->m_len accordingly */ 3434 prev->m_len -= shortfall; 3435 3436 /* copy data from runt m */ 3437 memcpy(n->m_data + shortfall, m->m_data, 3438 m->m_len); 3439 3440 /* n holds what we stole from prev, plus m */ 3441 n->m_len = shortfall + m->m_len; 3442 3443 /* stitch n into chain and free m */ 3444 n->m_next = m->m_next; 3445 prev->m_next = n; 3446 /* KASSERT(m->m_next == NULL); */ 3447 m->m_next = NULL; 3448 m_free(m); 3449 m = n; /* for continuing loop */ 3450 } 3451 } 3452 prevlen = m->m_len; 3453 } 3454 return 0; 3455 } 3456 3457 /* 3458 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data 3459 * pointers to descriptors. 3460 */ 3461 static int 3462 bge_encap(struct bge_softc *sc, struct mbuf *m_head, u_int32_t *txidx) 3463 { 3464 struct bge_tx_bd *f = NULL; 3465 u_int32_t frag, cur; 3466 u_int16_t csum_flags = 0; 3467 u_int16_t txbd_tso_flags = 0; 3468 struct txdmamap_pool_entry *dma; 3469 bus_dmamap_t dmamap; 3470 int i = 0; 3471 struct m_tag *mtag; 3472 int use_tso, maxsegsize, error; 3473 3474 cur = frag = *txidx; 3475 3476 if (m_head->m_pkthdr.csum_flags) { 3477 if (m_head->m_pkthdr.csum_flags & M_CSUM_IPv4) 3478 csum_flags |= BGE_TXBDFLAG_IP_CSUM; 3479 if (m_head->m_pkthdr.csum_flags & (M_CSUM_TCPv4|M_CSUM_UDPv4)) 3480 csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM; 3481 } 3482 3483 /* 3484 * If we were asked to do an outboard checksum, and the NIC 3485 * has the bug where it sometimes adds in the Ethernet padding, 3486 * explicitly pad with zeros so the cksum will be correct either way. 3487 * (For now, do this for all chip versions, until newer 3488 * are confirmed to not require the workaround.) 3489 */ 3490 if ((csum_flags & BGE_TXBDFLAG_TCP_UDP_CSUM) == 0 || 3491 #ifdef notyet 3492 (sc->bge_quirks & BGE_QUIRK_SHORT_CKSUM_BUG) == 0 || 3493 #endif 3494 m_head->m_pkthdr.len >= ETHER_MIN_NOPAD) 3495 goto check_dma_bug; 3496 3497 if (bge_cksum_pad(m_head) != 0) { 3498 return ENOBUFS; 3499 } 3500 3501 check_dma_bug: 3502 if (!(sc->bge_quirks & BGE_QUIRK_5700_SMALLDMA)) 3503 goto doit; 3504 /* 3505 * bcm5700 Revision B silicon cannot handle DMA descriptors with 3506 * less than eight bytes. If we encounter a teeny mbuf 3507 * at the end of a chain, we can pad. Otherwise, copy. 3508 */ 3509 if (bge_compact_dma_runt(m_head) != 0) 3510 return ENOBUFS; 3511 3512 doit: 3513 dma = SLIST_FIRST(&sc->txdma_list); 3514 if (dma == NULL) 3515 return ENOBUFS; 3516 dmamap = dma->dmamap; 3517 3518 /* 3519 * Set up any necessary TSO state before we start packing... 3520 */ 3521 use_tso = (m_head->m_pkthdr.csum_flags & M_CSUM_TSOv4) != 0; 3522 if (!use_tso) { 3523 maxsegsize = 0; 3524 } else { /* TSO setup */ 3525 unsigned mss; 3526 struct ether_header *eh; 3527 unsigned ip_tcp_hlen, iptcp_opt_words, tcp_seg_flags, offset; 3528 struct mbuf * m0 = m_head; 3529 struct ip *ip; 3530 struct tcphdr *th; 3531 int iphl, hlen; 3532 3533 /* 3534 * XXX It would be nice if the mbuf pkthdr had offset 3535 * fields for the protocol headers. 3536 */ 3537 3538 eh = mtod(m0, struct ether_header *); 3539 switch (htons(eh->ether_type)) { 3540 case ETHERTYPE_IP: 3541 offset = ETHER_HDR_LEN; 3542 break; 3543 3544 case ETHERTYPE_VLAN: 3545 offset = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 3546 break; 3547 3548 default: 3549 /* 3550 * Don't support this protocol or encapsulation. 3551 */ 3552 return (ENOBUFS); 3553 } 3554 3555 /* 3556 * TCP/IP headers are in the first mbuf; we can do 3557 * this the easy way. 3558 */ 3559 iphl = M_CSUM_DATA_IPv4_IPHL(m0->m_pkthdr.csum_data); 3560 hlen = iphl + offset; 3561 if (__predict_false(m0->m_len < 3562 (hlen + sizeof(struct tcphdr)))) { 3563 3564 printf("TSO: hard case m0->m_len == %d <" 3565 " ip/tcp hlen %zd, not handled yet\n", 3566 m0->m_len, hlen+ sizeof(struct tcphdr)); 3567 #ifdef NOTYET 3568 /* 3569 * XXX jonathan (at) NetBSD.org: untested. 3570 * how to force this branch to be taken? 3571 */ 3572 BGE_EVCNT_INCR(&sc->sc_ev_txtsopain); 3573 3574 m_copydata(m0, offset, sizeof(ip), &ip); 3575 m_copydata(m0, hlen, sizeof(th), &th); 3576 3577 ip.ip_len = 0; 3578 3579 m_copyback(m0, hlen + offsetof(struct ip, ip_len), 3580 sizeof(ip.ip_len), &ip.ip_len); 3581 3582 th.th_sum = in_cksum_phdr(ip.ip_src.s_addr, 3583 ip.ip_dst.s_addr, htons(IPPROTO_TCP)); 3584 3585 m_copyback(m0, hlen + offsetof(struct tcphdr, th_sum), 3586 sizeof(th.th_sum), &th.th_sum); 3587 3588 hlen += th.th_off << 2; 3589 iptcp_opt_words = hlen; 3590 #else 3591 /* 3592 * if_wm "hard" case not yet supported, can we not 3593 * mandate it out of existence? 3594 */ 3595 (void) ip; (void)th; (void) ip_tcp_hlen; 3596 3597 return ENOBUFS; 3598 #endif 3599 } else { 3600 ip = (struct ip *) (mtod(m0, caddr_t) + offset); 3601 th = (struct tcphdr *) (mtod(m0, caddr_t) + hlen); 3602 ip_tcp_hlen = iphl + (th->th_off << 2); 3603 3604 /* Total IP/TCP options, in 32-bit words */ 3605 iptcp_opt_words = (ip_tcp_hlen 3606 - sizeof(struct tcphdr) 3607 - sizeof(struct ip)) >> 2; 3608 } 3609 if (BGE_IS_5750_OR_BEYOND(sc)) { 3610 th->th_sum = 0; 3611 csum_flags &= ~(BGE_TXBDFLAG_TCP_UDP_CSUM); 3612 } else { 3613 /* 3614 * XXX jonathan (at) NetBSD.org: 5705 untested. 3615 * Requires TSO firmware patch for 5701/5703/5704. 3616 */ 3617 th->th_sum = in_cksum_phdr(ip->ip_src.s_addr, 3618 ip->ip_dst.s_addr, htons(IPPROTO_TCP)); 3619 } 3620 3621 mss = m_head->m_pkthdr.segsz; 3622 txbd_tso_flags |= 3623 BGE_TXBDFLAG_CPU_PRE_DMA | 3624 BGE_TXBDFLAG_CPU_POST_DMA; 3625 3626 /* 3627 * Our NIC TSO-assist assumes TSO has standard, optionless 3628 * IPv4 and TCP headers, which total 40 bytes. By default, 3629 * the NIC copies 40 bytes of IP/TCP header from the 3630 * supplied header into the IP/TCP header portion of 3631 * each post-TSO-segment. If the supplied packet has IP or 3632 * TCP options, we need to tell the NIC to copy those extra 3633 * bytes into each post-TSO header, in addition to the normal 3634 * 40-byte IP/TCP header (and to leave space accordingly). 3635 * Unfortunately, the driver encoding of option length 3636 * varies across different ASIC families. 3637 */ 3638 tcp_seg_flags = 0; 3639 if (iptcp_opt_words) { 3640 if ( BGE_IS_5705_OR_BEYOND(sc)) { 3641 tcp_seg_flags = 3642 iptcp_opt_words << 11; 3643 } else { 3644 txbd_tso_flags |= 3645 iptcp_opt_words << 12; 3646 } 3647 } 3648 maxsegsize = mss | tcp_seg_flags; 3649 ip->ip_len = htons(mss + ip_tcp_hlen); 3650 3651 } /* TSO setup */ 3652 3653 /* 3654 * Start packing the mbufs in this chain into 3655 * the fragment pointers. Stop when we run out 3656 * of fragments or hit the end of the mbuf chain. 3657 */ 3658 error = bus_dmamap_load_mbuf(sc->bge_dmatag, dmamap, m_head, 3659 BUS_DMA_NOWAIT); 3660 if (error) { 3661 return(ENOBUFS); 3662 } 3663 /* 3664 * Sanity check: avoid coming within 16 descriptors 3665 * of the end of the ring. 3666 */ 3667 if (dmamap->dm_nsegs > (BGE_TX_RING_CNT - sc->bge_txcnt - 16)) { 3668 BGE_TSO_PRINTF(("%s: " 3669 " dmamap_load_mbuf too close to ring wrap\n", 3670 sc->bge_dev.dv_xname)); 3671 goto fail_unload; 3672 } 3673 3674 mtag = sc->ethercom.ec_nvlans ? 3675 m_tag_find(m_head, PACKET_TAG_VLAN, NULL) : NULL; 3676 3677 3678 /* Iterate over dmap-map fragments. */ 3679 for (i = 0; i < dmamap->dm_nsegs; i++) { 3680 f = &sc->bge_rdata->bge_tx_ring[frag]; 3681 if (sc->bge_cdata.bge_tx_chain[frag] != NULL) 3682 break; 3683 3684 bge_set_hostaddr(&f->bge_addr, dmamap->dm_segs[i].ds_addr); 3685 f->bge_len = dmamap->dm_segs[i].ds_len; 3686 3687 /* 3688 * For 5751 and follow-ons, for TSO we must turn 3689 * off checksum-assist flag in the tx-descr, and 3690 * supply the ASIC-revision-specific encoding 3691 * of TSO flags and segsize. 3692 */ 3693 if (use_tso) { 3694 if (BGE_IS_5750_OR_BEYOND(sc) || i == 0) { 3695 f->bge_rsvd = maxsegsize; 3696 f->bge_flags = csum_flags | txbd_tso_flags; 3697 } else { 3698 f->bge_rsvd = 0; 3699 f->bge_flags = 3700 (csum_flags | txbd_tso_flags) & 0x0fff; 3701 } 3702 } else { 3703 f->bge_rsvd = 0; 3704 f->bge_flags = csum_flags; 3705 } 3706 3707 if (mtag != NULL) { 3708 f->bge_flags |= BGE_TXBDFLAG_VLAN_TAG; 3709 f->bge_vlan_tag = VLAN_TAG_VALUE(mtag); 3710 } else { 3711 f->bge_vlan_tag = 0; 3712 } 3713 cur = frag; 3714 BGE_INC(frag, BGE_TX_RING_CNT); 3715 } 3716 3717 if (i < dmamap->dm_nsegs) { 3718 BGE_TSO_PRINTF(("%s: reached %d < dm_nsegs %d\n", 3719 sc->bge_dev.dv_xname, i, dmamap->dm_nsegs)); 3720 goto fail_unload; 3721 } 3722 3723 bus_dmamap_sync(sc->bge_dmatag, dmamap, 0, dmamap->dm_mapsize, 3724 BUS_DMASYNC_PREWRITE); 3725 3726 if (frag == sc->bge_tx_saved_considx) { 3727 BGE_TSO_PRINTF(("%s: frag %d = wrapped id %d?\n", 3728 sc->bge_dev.dv_xname, frag, sc->bge_tx_saved_considx)); 3729 3730 goto fail_unload; 3731 } 3732 3733 sc->bge_rdata->bge_tx_ring[cur].bge_flags |= BGE_TXBDFLAG_END; 3734 sc->bge_cdata.bge_tx_chain[cur] = m_head; 3735 SLIST_REMOVE_HEAD(&sc->txdma_list, link); 3736 sc->txdma[cur] = dma; 3737 sc->bge_txcnt += dmamap->dm_nsegs; 3738 3739 *txidx = frag; 3740 3741 return(0); 3742 3743 fail_unload: 3744 bus_dmamap_unload(sc->bge_dmatag, dmamap); 3745 3746 return ENOBUFS; 3747 } 3748 3749 /* 3750 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 3751 * to the mbuf data regions directly in the transmit descriptors. 3752 */ 3753 static void 3754 bge_start(struct ifnet *ifp) 3755 { 3756 struct bge_softc *sc; 3757 struct mbuf *m_head = NULL; 3758 u_int32_t prodidx; 3759 int pkts = 0; 3760 3761 sc = ifp->if_softc; 3762 3763 if (!sc->bge_link && ifp->if_snd.ifq_len < 10) 3764 return; 3765 3766 prodidx = sc->bge_tx_prodidx; 3767 3768 while(sc->bge_cdata.bge_tx_chain[prodidx] == NULL) { 3769 IFQ_POLL(&ifp->if_snd, m_head); 3770 if (m_head == NULL) 3771 break; 3772 3773 #if 0 3774 /* 3775 * XXX 3776 * safety overkill. If this is a fragmented packet chain 3777 * with delayed TCP/UDP checksums, then only encapsulate 3778 * it if we have enough descriptors to handle the entire 3779 * chain at once. 3780 * (paranoia -- may not actually be needed) 3781 */ 3782 if (m_head->m_flags & M_FIRSTFRAG && 3783 m_head->m_pkthdr.csum_flags & (CSUM_DELAY_DATA)) { 3784 if ((BGE_TX_RING_CNT - sc->bge_txcnt) < 3785 M_CSUM_DATA_IPv4_OFFSET(m_head->m_pkthdr.csum_data) + 16) { 3786 ifp->if_flags |= IFF_OACTIVE; 3787 break; 3788 } 3789 } 3790 #endif 3791 3792 /* 3793 * Pack the data into the transmit ring. If we 3794 * don't have room, set the OACTIVE flag and wait 3795 * for the NIC to drain the ring. 3796 */ 3797 if (bge_encap(sc, m_head, &prodidx)) { 3798 printf("bge: failed on len %d?\n", m_head->m_pkthdr.len); 3799 ifp->if_flags |= IFF_OACTIVE; 3800 break; 3801 } 3802 3803 /* now we are committed to transmit the packet */ 3804 IFQ_DEQUEUE(&ifp->if_snd, m_head); 3805 pkts++; 3806 3807 #if NBPFILTER > 0 3808 /* 3809 * If there's a BPF listener, bounce a copy of this frame 3810 * to him. 3811 */ 3812 if (ifp->if_bpf) 3813 bpf_mtap(ifp->if_bpf, m_head); 3814 #endif 3815 } 3816 if (pkts == 0) 3817 return; 3818 3819 /* Transmit */ 3820 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); 3821 if (sc->bge_quirks & BGE_QUIRK_PRODUCER_BUG) /* 5700 b2 errata */ 3822 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); 3823 3824 sc->bge_tx_prodidx = prodidx; 3825 3826 /* 3827 * Set a timeout in case the chip goes out to lunch. 3828 */ 3829 ifp->if_timer = 5; 3830 } 3831 3832 static int 3833 bge_init(struct ifnet *ifp) 3834 { 3835 struct bge_softc *sc = ifp->if_softc; 3836 u_int16_t *m; 3837 int s, error; 3838 3839 s = splnet(); 3840 3841 ifp = &sc->ethercom.ec_if; 3842 3843 /* Cancel pending I/O and flush buffers. */ 3844 bge_stop(sc); 3845 bge_reset(sc); 3846 bge_chipinit(sc); 3847 3848 /* 3849 * Init the various state machines, ring 3850 * control blocks and firmware. 3851 */ 3852 error = bge_blockinit(sc); 3853 if (error != 0) { 3854 printf("%s: initialization error %d\n", sc->bge_dev.dv_xname, 3855 error); 3856 splx(s); 3857 return error; 3858 } 3859 3860 ifp = &sc->ethercom.ec_if; 3861 3862 /* Specify MTU. */ 3863 CSR_WRITE_4(sc, BGE_RX_MTU, ifp->if_mtu + 3864 ETHER_HDR_LEN + ETHER_CRC_LEN + ETHER_VLAN_ENCAP_LEN); 3865 3866 /* Load our MAC address. */ 3867 m = (u_int16_t *)&(LLADDR(ifp->if_sadl)[0]); 3868 CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0])); 3869 CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, (htons(m[1]) << 16) | htons(m[2])); 3870 3871 /* Enable or disable promiscuous mode as needed. */ 3872 if (ifp->if_flags & IFF_PROMISC) { 3873 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 3874 } else { 3875 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 3876 } 3877 3878 /* Program multicast filter. */ 3879 bge_setmulti(sc); 3880 3881 /* Init RX ring. */ 3882 bge_init_rx_ring_std(sc); 3883 3884 /* Init jumbo RX ring. */ 3885 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 3886 bge_init_rx_ring_jumbo(sc); 3887 3888 /* Init our RX return ring index */ 3889 sc->bge_rx_saved_considx = 0; 3890 3891 /* Init TX ring. */ 3892 bge_init_tx_ring(sc); 3893 3894 /* Turn on transmitter */ 3895 BGE_SETBIT(sc, BGE_TX_MODE, BGE_TXMODE_ENABLE); 3896 3897 /* Turn on receiver */ 3898 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE); 3899 3900 CSR_WRITE_4(sc, BGE_MAX_RX_FRAME_LOWAT, 2); 3901 3902 /* Tell firmware we're alive. */ 3903 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 3904 3905 /* Enable host interrupts. */ 3906 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA); 3907 BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); 3908 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 0); 3909 3910 bge_ifmedia_upd(ifp); 3911 3912 ifp->if_flags |= IFF_RUNNING; 3913 ifp->if_flags &= ~IFF_OACTIVE; 3914 3915 splx(s); 3916 3917 callout_reset(&sc->bge_timeout, hz, bge_tick, sc); 3918 3919 return 0; 3920 } 3921 3922 /* 3923 * Set media options. 3924 */ 3925 static int 3926 bge_ifmedia_upd(struct ifnet *ifp) 3927 { 3928 struct bge_softc *sc = ifp->if_softc; 3929 struct mii_data *mii = &sc->bge_mii; 3930 struct ifmedia *ifm = &sc->bge_ifmedia; 3931 3932 /* If this is a 1000baseX NIC, enable the TBI port. */ 3933 if (sc->bge_tbi) { 3934 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 3935 return(EINVAL); 3936 switch(IFM_SUBTYPE(ifm->ifm_media)) { 3937 case IFM_AUTO: 3938 break; 3939 case IFM_1000_SX: 3940 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 3941 BGE_CLRBIT(sc, BGE_MAC_MODE, 3942 BGE_MACMODE_HALF_DUPLEX); 3943 } else { 3944 BGE_SETBIT(sc, BGE_MAC_MODE, 3945 BGE_MACMODE_HALF_DUPLEX); 3946 } 3947 break; 3948 default: 3949 return(EINVAL); 3950 } 3951 /* XXX 802.3x flow control for 1000BASE-SX */ 3952 return(0); 3953 } 3954 3955 sc->bge_link = 0; 3956 mii_mediachg(mii); 3957 3958 return(0); 3959 } 3960 3961 /* 3962 * Report current media status. 3963 */ 3964 static void 3965 bge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 3966 { 3967 struct bge_softc *sc = ifp->if_softc; 3968 struct mii_data *mii = &sc->bge_mii; 3969 3970 if (sc->bge_tbi) { 3971 ifmr->ifm_status = IFM_AVALID; 3972 ifmr->ifm_active = IFM_ETHER; 3973 if (CSR_READ_4(sc, BGE_MAC_STS) & 3974 BGE_MACSTAT_TBI_PCS_SYNCHED) 3975 ifmr->ifm_status |= IFM_ACTIVE; 3976 ifmr->ifm_active |= IFM_1000_SX; 3977 if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX) 3978 ifmr->ifm_active |= IFM_HDX; 3979 else 3980 ifmr->ifm_active |= IFM_FDX; 3981 return; 3982 } 3983 3984 mii_pollstat(mii); 3985 ifmr->ifm_status = mii->mii_media_status; 3986 ifmr->ifm_active = (mii->mii_media_active & ~IFM_ETH_FMASK) | 3987 sc->bge_flowflags; 3988 } 3989 3990 static int 3991 bge_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 3992 { 3993 struct bge_softc *sc = ifp->if_softc; 3994 struct ifreq *ifr = (struct ifreq *) data; 3995 int s, error = 0; 3996 struct mii_data *mii; 3997 3998 s = splnet(); 3999 4000 switch(command) { 4001 case SIOCSIFFLAGS: 4002 if (ifp->if_flags & IFF_UP) { 4003 /* 4004 * If only the state of the PROMISC flag changed, 4005 * then just use the 'set promisc mode' command 4006 * instead of reinitializing the entire NIC. Doing 4007 * a full re-init means reloading the firmware and 4008 * waiting for it to start up, which may take a 4009 * second or two. 4010 */ 4011 if (ifp->if_flags & IFF_RUNNING && 4012 ifp->if_flags & IFF_PROMISC && 4013 !(sc->bge_if_flags & IFF_PROMISC)) { 4014 BGE_SETBIT(sc, BGE_RX_MODE, 4015 BGE_RXMODE_RX_PROMISC); 4016 } else if (ifp->if_flags & IFF_RUNNING && 4017 !(ifp->if_flags & IFF_PROMISC) && 4018 sc->bge_if_flags & IFF_PROMISC) { 4019 BGE_CLRBIT(sc, BGE_RX_MODE, 4020 BGE_RXMODE_RX_PROMISC); 4021 } else if (!(sc->bge_if_flags & IFF_UP)) 4022 bge_init(ifp); 4023 } else { 4024 if (ifp->if_flags & IFF_RUNNING) { 4025 bge_stop(sc); 4026 } 4027 } 4028 sc->bge_if_flags = ifp->if_flags; 4029 error = 0; 4030 break; 4031 case SIOCSIFMEDIA: 4032 /* XXX Flow control is not supported for 1000BASE-SX */ 4033 if (sc->bge_tbi) { 4034 ifr->ifr_media &= ~IFM_ETH_FMASK; 4035 sc->bge_flowflags = 0; 4036 } 4037 4038 /* Flow control requires full-duplex mode. */ 4039 if (IFM_SUBTYPE(ifr->ifr_media) == IFM_AUTO || 4040 (ifr->ifr_media & IFM_FDX) == 0) { 4041 ifr->ifr_media &= ~IFM_ETH_FMASK; 4042 } 4043 if (IFM_SUBTYPE(ifr->ifr_media) != IFM_AUTO) { 4044 if ((ifr->ifr_media & IFM_ETH_FMASK) == IFM_FLOW) { 4045 /* We an do both TXPAUSE and RXPAUSE. */ 4046 ifr->ifr_media |= 4047 IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE; 4048 } 4049 sc->bge_flowflags = ifr->ifr_media & IFM_ETH_FMASK; 4050 } 4051 /* FALLTHROUGH */ 4052 case SIOCGIFMEDIA: 4053 if (sc->bge_tbi) { 4054 error = ifmedia_ioctl(ifp, ifr, &sc->bge_ifmedia, 4055 command); 4056 } else { 4057 mii = &sc->bge_mii; 4058 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, 4059 command); 4060 } 4061 break; 4062 default: 4063 error = ether_ioctl(ifp, command, data); 4064 if (error == ENETRESET) { 4065 if (ifp->if_flags & IFF_RUNNING) 4066 bge_setmulti(sc); 4067 error = 0; 4068 } 4069 break; 4070 } 4071 4072 splx(s); 4073 4074 return(error); 4075 } 4076 4077 static void 4078 bge_watchdog(struct ifnet *ifp) 4079 { 4080 struct bge_softc *sc; 4081 4082 sc = ifp->if_softc; 4083 4084 printf("%s: watchdog timeout -- resetting\n", sc->bge_dev.dv_xname); 4085 4086 ifp->if_flags &= ~IFF_RUNNING; 4087 bge_init(ifp); 4088 4089 ifp->if_oerrors++; 4090 } 4091 4092 static void 4093 bge_stop_block(struct bge_softc *sc, bus_addr_t reg, uint32_t bit) 4094 { 4095 int i; 4096 4097 BGE_CLRBIT(sc, reg, bit); 4098 4099 for (i = 0; i < BGE_TIMEOUT; i++) { 4100 if ((CSR_READ_4(sc, reg) & bit) == 0) 4101 return; 4102 delay(100); 4103 if (sc->bge_pcie) 4104 DELAY(1000); 4105 } 4106 4107 printf("%s: block failed to stop: reg 0x%lx, bit 0x%08x\n", 4108 sc->bge_dev.dv_xname, (u_long) reg, bit); 4109 } 4110 4111 /* 4112 * Stop the adapter and free any mbufs allocated to the 4113 * RX and TX lists. 4114 */ 4115 static void 4116 bge_stop(struct bge_softc *sc) 4117 { 4118 struct ifnet *ifp = &sc->ethercom.ec_if; 4119 4120 callout_stop(&sc->bge_timeout); 4121 4122 /* 4123 * Disable all of the receiver blocks 4124 */ 4125 bge_stop_block(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE); 4126 bge_stop_block(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 4127 bge_stop_block(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 4128 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 4129 bge_stop_block(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 4130 } 4131 bge_stop_block(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE); 4132 bge_stop_block(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 4133 bge_stop_block(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE); 4134 4135 /* 4136 * Disable all of the transmit blocks 4137 */ 4138 bge_stop_block(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 4139 bge_stop_block(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 4140 bge_stop_block(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 4141 bge_stop_block(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE); 4142 bge_stop_block(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE); 4143 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 4144 bge_stop_block(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 4145 } 4146 bge_stop_block(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 4147 4148 /* 4149 * Shut down all of the memory managers and related 4150 * state machines. 4151 */ 4152 bge_stop_block(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE); 4153 bge_stop_block(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE); 4154 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 4155 bge_stop_block(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 4156 } 4157 4158 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 4159 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 4160 4161 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 4162 bge_stop_block(sc, BGE_BMAN_MODE, BGE_BMANMODE_ENABLE); 4163 bge_stop_block(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 4164 } 4165 4166 /* Disable host interrupts. */ 4167 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); 4168 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 1); 4169 4170 /* 4171 * Tell firmware we're shutting down. 4172 */ 4173 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 4174 4175 /* Free the RX lists. */ 4176 bge_free_rx_ring_std(sc); 4177 4178 /* Free jumbo RX list. */ 4179 bge_free_rx_ring_jumbo(sc); 4180 4181 /* Free TX buffers. */ 4182 bge_free_tx_ring(sc); 4183 4184 /* 4185 * Isolate/power down the PHY. 4186 */ 4187 if (!sc->bge_tbi) 4188 mii_down(&sc->bge_mii); 4189 4190 sc->bge_link = 0; 4191 4192 sc->bge_tx_saved_considx = BGE_TXCONS_UNSET; 4193 4194 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 4195 } 4196 4197 /* 4198 * Stop all chip I/O so that the kernel's probe routines don't 4199 * get confused by errant DMAs when rebooting. 4200 */ 4201 static void 4202 bge_shutdown(void *xsc) 4203 { 4204 struct bge_softc *sc = (struct bge_softc *)xsc; 4205 4206 bge_stop(sc); 4207 bge_reset(sc); 4208 } 4209 4210 4211 static int 4212 sysctl_bge_verify(SYSCTLFN_ARGS) 4213 { 4214 int error, t; 4215 struct sysctlnode node; 4216 4217 node = *rnode; 4218 t = *(int*)rnode->sysctl_data; 4219 node.sysctl_data = &t; 4220 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 4221 if (error || newp == NULL) 4222 return (error); 4223 4224 #if 0 4225 DPRINTF2(("%s: t = %d, nodenum = %d, rnodenum = %d\n", __func__, t, 4226 node.sysctl_num, rnode->sysctl_num)); 4227 #endif 4228 4229 if (node.sysctl_num == bge_rxthresh_nodenum) { 4230 if (t < 0 || t >= NBGE_RX_THRESH) 4231 return (EINVAL); 4232 bge_update_all_threshes(t); 4233 } else 4234 return (EINVAL); 4235 4236 *(int*)rnode->sysctl_data = t; 4237 4238 return (0); 4239 } 4240 4241 /* 4242 * Set up sysctl(3) MIB, hw.bge.*. 4243 * 4244 * TBD condition SYSCTL_PERMANENT on being an LKM or not 4245 */ 4246 SYSCTL_SETUP(sysctl_bge, "sysctl bge subtree setup") 4247 { 4248 int rc, bge_root_num; 4249 const struct sysctlnode *node; 4250 4251 if ((rc = sysctl_createv(clog, 0, NULL, NULL, 4252 CTLFLAG_PERMANENT, CTLTYPE_NODE, "hw", NULL, 4253 NULL, 0, NULL, 0, CTL_HW, CTL_EOL)) != 0) { 4254 goto err; 4255 } 4256 4257 if ((rc = sysctl_createv(clog, 0, NULL, &node, 4258 CTLFLAG_PERMANENT, CTLTYPE_NODE, "bge", 4259 SYSCTL_DESCR("BGE interface controls"), 4260 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL)) != 0) { 4261 goto err; 4262 } 4263 4264 bge_root_num = node->sysctl_num; 4265 4266 /* BGE Rx interrupt mitigation level */ 4267 if ((rc = sysctl_createv(clog, 0, NULL, &node, 4268 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, 4269 CTLTYPE_INT, "rx_lvl", 4270 SYSCTL_DESCR("BGE receive interrupt mitigation level"), 4271 sysctl_bge_verify, 0, 4272 &bge_rx_thresh_lvl, 4273 0, CTL_HW, bge_root_num, CTL_CREATE, 4274 CTL_EOL)) != 0) { 4275 goto err; 4276 } 4277 4278 bge_rxthresh_nodenum = node->sysctl_num; 4279 4280 return; 4281 4282 err: 4283 printf("%s: sysctl_createv failed (rc = %d)\n", __func__, rc); 4284 } 4285 4286 static void 4287 bge_powerhook(int why, void *hdl) 4288 { 4289 struct bge_softc *sc = (struct bge_softc *)hdl; 4290 struct ifnet *ifp = &sc->ethercom.ec_if; 4291 struct pci_attach_args *pa = &(sc->bge_pa); 4292 pci_chipset_tag_t pc = pa->pa_pc; 4293 pcitag_t tag = pa->pa_tag; 4294 4295 switch (why) { 4296 case PWR_SOFTSUSPEND: 4297 case PWR_SOFTSTANDBY: 4298 bge_shutdown(sc); 4299 break; 4300 case PWR_SOFTRESUME: 4301 if (ifp->if_flags & IFF_UP) { 4302 ifp->if_flags &= ~IFF_RUNNING; 4303 bge_init(ifp); 4304 } 4305 break; 4306 case PWR_SUSPEND: 4307 case PWR_STANDBY: 4308 pci_conf_capture(pc, tag, &sc->bge_pciconf); 4309 break; 4310 case PWR_RESUME: 4311 pci_conf_restore(pc, tag, &sc->bge_pciconf); 4312 break; 4313 } 4314 4315 return; 4316 } 4317
Indexes created Thu Sep 25 08:09:54 GMT 2025