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if_bge.c revision 1.126
      1 /*	$NetBSD: if_bge.c,v 1.126 2007/03/04 06:02:19 christos Exp $	*/
      2 
      3 /*
      4  * Copyright (c) 2001 Wind River Systems
      5  * Copyright (c) 1997, 1998, 1999, 2001
      6  *	Bill Paul <wpaul (at) windriver.com>.  All rights reserved.
      7  *
      8  * Redistribution and use in source and binary forms, with or without
      9  * modification, are permitted provided that the following conditions
     10  * are met:
     11  * 1. Redistributions of source code must retain the above copyright
     12  *    notice, this list of conditions and the following disclaimer.
     13  * 2. Redistributions in binary form must reproduce the above copyright
     14  *    notice, this list of conditions and the following disclaimer in the
     15  *    documentation and/or other materials provided with the distribution.
     16  * 3. All advertising materials mentioning features or use of this software
     17  *    must display the following acknowledgement:
     18  *	This product includes software developed by Bill Paul.
     19  * 4. Neither the name of the author nor the names of any co-contributors
     20  *    may be used to endorse or promote products derived from this software
     21  *    without specific prior written permission.
     22  *
     23  * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
     24  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
     25  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
     26  * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
     27  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
     28  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
     29  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
     30  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
     31  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
     32  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
     33  * THE POSSIBILITY OF SUCH DAMAGE.
     34  *
     35  * $FreeBSD: if_bge.c,v 1.13 2002/04/04 06:01:31 wpaul Exp $
     36  */
     37 
     38 /*
     39  * Broadcom BCM570x family gigabit ethernet driver for NetBSD.
     40  *
     41  * NetBSD version by:
     42  *
     43  *	Frank van der Linden <fvdl (at) wasabisystems.com>
     44  *	Jason Thorpe <thorpej (at) wasabisystems.com>
     45  *	Jonathan Stone <jonathan (at) dsg.stanford.edu>
     46  *
     47  * Originally written for FreeBSD by Bill Paul <wpaul (at) windriver.com>
     48  * Senior Engineer, Wind River Systems
     49  */
     50 
     51 /*
     52  * The Broadcom BCM5700 is based on technology originally developed by
     53  * Alteon Networks as part of the Tigon I and Tigon II gigabit ethernet
     54  * MAC chips. The BCM5700, sometimes refered to as the Tigon III, has
     55  * two on-board MIPS R4000 CPUs and can have as much as 16MB of external
     56  * SSRAM. The BCM5700 supports TCP, UDP and IP checksum offload, jumbo
     57  * frames, highly configurable RX filtering, and 16 RX and TX queues
     58  * (which, along with RX filter rules, can be used for QOS applications).
     59  * Other features, such as TCP segmentation, may be available as part
     60  * of value-added firmware updates. Unlike the Tigon I and Tigon II,
     61  * firmware images can be stored in hardware and need not be compiled
     62  * into the driver.
     63  *
     64  * The BCM5700 supports the PCI v2.2 and PCI-X v1.0 standards, and will
     65  * function in a 32-bit/64-bit 33/66MHz bus, or a 64-bit/133MHz bus.
     66  *
     67  * The BCM5701 is a single-chip solution incorporating both the BCM5700
     68  * MAC and a BCM5401 10/100/1000 PHY. Unlike the BCM5700, the BCM5701
     69  * does not support external SSRAM.
     70  *
     71  * Broadcom also produces a variation of the BCM5700 under the "Altima"
     72  * brand name, which is functionally similar but lacks PCI-X support.
     73  *
     74  * Without external SSRAM, you can only have at most 4 TX rings,
     75  * and the use of the mini RX ring is disabled. This seems to imply
     76  * that these features are simply not available on the BCM5701. As a
     77  * result, this driver does not implement any support for the mini RX
     78  * ring.
     79  */
     80 
     81 #include <sys/cdefs.h>
     82 __KERNEL_RCSID(0, "$NetBSD: if_bge.c,v 1.126 2007/03/04 06:02:19 christos Exp $");
     83 
     84 #include "bpfilter.h"
     85 #include "vlan.h"
     86 
     87 #include <sys/param.h>
     88 #include <sys/systm.h>
     89 #include <sys/callout.h>
     90 #include <sys/sockio.h>
     91 #include <sys/mbuf.h>
     92 #include <sys/malloc.h>
     93 #include <sys/kernel.h>
     94 #include <sys/device.h>
     95 #include <sys/socket.h>
     96 #include <sys/sysctl.h>
     97 
     98 #include <net/if.h>
     99 #include <net/if_dl.h>
    100 #include <net/if_media.h>
    101 #include <net/if_ether.h>
    102 
    103 #ifdef INET
    104 #include <netinet/in.h>
    105 #include <netinet/in_systm.h>
    106 #include <netinet/in_var.h>
    107 #include <netinet/ip.h>
    108 #endif
    109 
    110 /* Headers for TCP  Segmentation Offload (TSO) */
    111 #include <netinet/in_systm.h>		/* n_time for <netinet/ip.h>... */
    112 #include <netinet/in.h>			/* ip_{src,dst}, for <netinet/ip.h> */
    113 #include <netinet/ip.h>			/* for struct ip */
    114 #include <netinet/tcp.h>		/* for struct tcphdr */
    115 
    116 
    117 #if NBPFILTER > 0
    118 #include <net/bpf.h>
    119 #endif
    120 
    121 #include <dev/pci/pcireg.h>
    122 #include <dev/pci/pcivar.h>
    123 #include <dev/pci/pcidevs.h>
    124 
    125 #include <dev/mii/mii.h>
    126 #include <dev/mii/miivar.h>
    127 #include <dev/mii/miidevs.h>
    128 #include <dev/mii/brgphyreg.h>
    129 
    130 #include <dev/pci/if_bgereg.h>
    131 
    132 #include <uvm/uvm_extern.h>
    133 
    134 #define ETHER_MIN_NOPAD (ETHER_MIN_LEN - ETHER_CRC_LEN) /* i.e., 60 */
    135 
    136 
    137 /*
    138  * Tunable thresholds for rx-side bge interrupt mitigation.
    139  */
    140 
    141 /*
    142  * The pairs of values below were obtained from empirical measurement
    143  * on bcm5700 rev B2; they ar designed to give roughly 1 receive
    144  * interrupt for every N packets received, where N is, approximately,
    145  * the second value (rx_max_bds) in each pair.  The values are chosen
    146  * such that moving from one pair to the succeeding pair was observed
    147  * to roughly halve interrupt rate under sustained input packet load.
    148  * The values were empirically chosen to avoid overflowing internal
    149  * limits on the  bcm5700: inreasing rx_ticks much beyond 600
    150  * results in internal wrapping and higher interrupt rates.
    151  * The limit of 46 frames was chosen to match NFS workloads.
    152  *
    153  * These values also work well on bcm5701, bcm5704C, and (less
    154  * tested) bcm5703.  On other chipsets, (including the Altima chip
    155  * family), the larger values may overflow internal chip limits,
    156  * leading to increasing interrupt rates rather than lower interrupt
    157  * rates.
    158  *
    159  * Applications using heavy interrupt mitigation (interrupting every
    160  * 32 or 46 frames) in both directions may need to increase the TCP
    161  * windowsize to above 131072 bytes (e.g., to 199608 bytes) to sustain
    162  * full link bandwidth, due to ACKs and window updates lingering
    163  * in the RX queue during the 30-to-40-frame interrupt-mitigation window.
    164  */
    165 static const struct bge_load_rx_thresh {
    166 	int rx_ticks;
    167 	int rx_max_bds; }
    168 bge_rx_threshes[] = {
    169 	{ 32,   2 },
    170 	{ 50,   4 },
    171 	{ 100,  8 },
    172 	{ 192, 16 },
    173 	{ 416, 32 },
    174 	{ 598, 46 }
    175 };
    176 #define NBGE_RX_THRESH (sizeof(bge_rx_threshes) / sizeof(bge_rx_threshes[0]))
    177 
    178 /* XXX patchable; should be sysctl'able */
    179 static int	bge_auto_thresh = 1;
    180 static int	bge_rx_thresh_lvl;
    181 
    182 static int	bge_rxthresh_nodenum;
    183 
    184 static int	bge_probe(device_t, cfdata_t, void *);
    185 static void	bge_attach(device_t, device_t, void *);
    186 static void	bge_powerhook(int, void *);
    187 static void	bge_release_resources(struct bge_softc *);
    188 static void	bge_txeof(struct bge_softc *);
    189 static void	bge_rxeof(struct bge_softc *);
    190 
    191 static void	bge_tick(void *);
    192 static void	bge_stats_update(struct bge_softc *);
    193 static int	bge_encap(struct bge_softc *, struct mbuf *, u_int32_t *);
    194 
    195 static int	bge_intr(void *);
    196 static void	bge_start(struct ifnet *);
    197 static int	bge_ioctl(struct ifnet *, u_long, void *);
    198 static int	bge_init(struct ifnet *);
    199 static void	bge_stop(struct bge_softc *);
    200 static void	bge_watchdog(struct ifnet *);
    201 static void	bge_shutdown(void *);
    202 static int	bge_ifmedia_upd(struct ifnet *);
    203 static void	bge_ifmedia_sts(struct ifnet *, struct ifmediareq *);
    204 
    205 static void	bge_setmulti(struct bge_softc *);
    206 
    207 static void	bge_handle_events(struct bge_softc *);
    208 static int	bge_alloc_jumbo_mem(struct bge_softc *);
    209 #if 0 /* XXX */
    210 static void	bge_free_jumbo_mem(struct bge_softc *);
    211 #endif
    212 static void	*bge_jalloc(struct bge_softc *);
    213 static void	bge_jfree(struct mbuf *, void *, size_t, void *);
    214 static int	bge_newbuf_std(struct bge_softc *, int, struct mbuf *,
    215 			       bus_dmamap_t);
    216 static int	bge_newbuf_jumbo(struct bge_softc *, int, struct mbuf *);
    217 static int	bge_init_rx_ring_std(struct bge_softc *);
    218 static void	bge_free_rx_ring_std(struct bge_softc *);
    219 static int	bge_init_rx_ring_jumbo(struct bge_softc *);
    220 static void	bge_free_rx_ring_jumbo(struct bge_softc *);
    221 static void	bge_free_tx_ring(struct bge_softc *);
    222 static int	bge_init_tx_ring(struct bge_softc *);
    223 
    224 static int	bge_chipinit(struct bge_softc *);
    225 static int	bge_blockinit(struct bge_softc *);
    226 static int	bge_setpowerstate(struct bge_softc *, int);
    227 
    228 static void	bge_reset(struct bge_softc *);
    229 
    230 #define BGE_DEBUG
    231 #ifdef BGE_DEBUG
    232 #define DPRINTF(x)	if (bgedebug) printf x
    233 #define DPRINTFN(n,x)	if (bgedebug >= (n)) printf x
    234 #define BGE_TSO_PRINTF(x)  do { if (bge_tso_debug) printf x ;} while (0)
    235 int	bgedebug = 0;
    236 int	bge_tso_debug = 0;
    237 #else
    238 #define DPRINTF(x)
    239 #define DPRINTFN(n,x)
    240 #define BGE_TSO_PRINTF(x)
    241 #endif
    242 
    243 #ifdef BGE_EVENT_COUNTERS
    244 #define	BGE_EVCNT_INCR(ev)	(ev).ev_count++
    245 #define	BGE_EVCNT_ADD(ev, val)	(ev).ev_count += (val)
    246 #define	BGE_EVCNT_UPD(ev, val)	(ev).ev_count = (val)
    247 #else
    248 #define	BGE_EVCNT_INCR(ev)	/* nothing */
    249 #define	BGE_EVCNT_ADD(ev, val)	/* nothing */
    250 #define	BGE_EVCNT_UPD(ev, val)	/* nothing */
    251 #endif
    252 
    253 /* Various chip quirks. */
    254 #define	BGE_QUIRK_LINK_STATE_BROKEN	0x00000001
    255 #define	BGE_QUIRK_CSUM_BROKEN		0x00000002
    256 #define	BGE_QUIRK_ONLY_PHY_1		0x00000004
    257 #define	BGE_QUIRK_5700_SMALLDMA		0x00000008
    258 #define	BGE_QUIRK_5700_PCIX_REG_BUG	0x00000010
    259 #define	BGE_QUIRK_PRODUCER_BUG		0x00000020
    260 #define	BGE_QUIRK_PCIX_DMA_ALIGN_BUG	0x00000040
    261 #define	BGE_QUIRK_5705_CORE		0x00000080
    262 #define	BGE_QUIRK_FEWER_MBUFS		0x00000100
    263 
    264 /*
    265  * XXX: how to handle variants based on 5750 and derivatives:
    266  * 5750 5751, 5721, possibly 5714, 5752, and 5708?, which
    267  * in general behave like a 5705, except with additional quirks.
    268  * This driver's current handling of the 5721 is wrong;
    269  * how we map ASIC revision to "quirks" needs more thought.
    270  * (defined here until the thought is done).
    271  */
    272 #define BGE_IS_5714_FAMILY(sc) \
    273 	(BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5714_A0 || \
    274 	 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5780 ||	\
    275 	 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5714 )
    276 
    277 #define BGE_IS_5750_OR_BEYOND(sc)  \
    278 	(BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5750 || \
    279 	 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5752 || \
    280 	 BGE_IS_5714_FAMILY(sc) )
    281 
    282 #define BGE_IS_5705_OR_BEYOND(sc)  \
    283 	( ((sc)->bge_quirks & BGE_QUIRK_5705_CORE) || \
    284 	  BGE_IS_5750_OR_BEYOND(sc) )
    285 
    286 
    287 /* following bugs are common to bcm5700 rev B, all flavours */
    288 #define BGE_QUIRK_5700_COMMON \
    289 	(BGE_QUIRK_5700_SMALLDMA|BGE_QUIRK_PRODUCER_BUG)
    290 
    291 CFATTACH_DECL(bge, sizeof(struct bge_softc),
    292     bge_probe, bge_attach, NULL, NULL);
    293 
    294 static u_int32_t
    295 bge_readmem_ind(struct bge_softc *sc, int off)
    296 {
    297 	struct pci_attach_args	*pa = &(sc->bge_pa);
    298 	pcireg_t val;
    299 
    300 	pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_MEMWIN_BASEADDR, off);
    301 	val = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_MEMWIN_DATA);
    302 	return val;
    303 }
    304 
    305 static void
    306 bge_writemem_ind(struct bge_softc *sc, int off, int val)
    307 {
    308 	struct pci_attach_args	*pa = &(sc->bge_pa);
    309 
    310 	pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_MEMWIN_BASEADDR, off);
    311 	pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_MEMWIN_DATA, val);
    312 }
    313 
    314 #ifdef notdef
    315 static u_int32_t
    316 bge_readreg_ind(struct bge_softc *sc, int off)
    317 {
    318 	struct pci_attach_args	*pa = &(sc->bge_pa);
    319 
    320 	pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_REG_BASEADDR, off);
    321 	return(pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_REG_DATA));
    322 }
    323 #endif
    324 
    325 static void
    326 bge_writereg_ind(struct bge_softc *sc, int off, int val)
    327 {
    328 	struct pci_attach_args	*pa = &(sc->bge_pa);
    329 
    330 	pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_REG_BASEADDR, off);
    331 	pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_REG_DATA, val);
    332 }
    333 
    334 #ifdef notdef
    335 static u_int8_t
    336 bge_vpd_readbyte(struct bge_softc *sc, int addr)
    337 {
    338 	int i;
    339 	u_int32_t val;
    340 	struct pci_attach_args	*pa = &(sc->bge_pa);
    341 
    342 	pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_VPD_ADDR, addr);
    343 	for (i = 0; i < BGE_TIMEOUT * 10; i++) {
    344 		DELAY(10);
    345 		if (pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_VPD_ADDR) &
    346 		    BGE_VPD_FLAG)
    347 			break;
    348 	}
    349 
    350 	if (i == BGE_TIMEOUT) {
    351 		printf("%s: VPD read timed out\n", sc->bge_dev.dv_xname);
    352 		return(0);
    353 	}
    354 
    355 	val = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_VPD_DATA);
    356 
    357 	return((val >> ((addr % 4) * 8)) & 0xFF);
    358 }
    359 
    360 static void
    361 bge_vpd_read_res(struct bge_softc *sc, struct vpd_res *res, int addr)
    362 {
    363 	int i;
    364 	u_int8_t *ptr;
    365 
    366 	ptr = (u_int8_t *)res;
    367 	for (i = 0; i < sizeof(struct vpd_res); i++)
    368 		ptr[i] = bge_vpd_readbyte(sc, i + addr);
    369 }
    370 
    371 static void
    372 bge_vpd_read(struct bge_softc *sc)
    373 {
    374 	int pos = 0, i;
    375 	struct vpd_res res;
    376 
    377 	if (sc->bge_vpd_prodname != NULL)
    378 		free(sc->bge_vpd_prodname, M_DEVBUF);
    379 	if (sc->bge_vpd_readonly != NULL)
    380 		free(sc->bge_vpd_readonly, M_DEVBUF);
    381 	sc->bge_vpd_prodname = NULL;
    382 	sc->bge_vpd_readonly = NULL;
    383 
    384 	bge_vpd_read_res(sc, &res, pos);
    385 
    386 	if (res.vr_id != VPD_RES_ID) {
    387 		printf("%s: bad VPD resource id: expected %x got %x\n",
    388 			sc->bge_dev.dv_xname, VPD_RES_ID, res.vr_id);
    389 		return;
    390 	}
    391 
    392 	pos += sizeof(res);
    393 	sc->bge_vpd_prodname = malloc(res.vr_len + 1, M_DEVBUF, M_NOWAIT);
    394 	if (sc->bge_vpd_prodname == NULL)
    395 		panic("bge_vpd_read");
    396 	for (i = 0; i < res.vr_len; i++)
    397 		sc->bge_vpd_prodname[i] = bge_vpd_readbyte(sc, i + pos);
    398 	sc->bge_vpd_prodname[i] = '\0';
    399 	pos += i;
    400 
    401 	bge_vpd_read_res(sc, &res, pos);
    402 
    403 	if (res.vr_id != VPD_RES_READ) {
    404 		printf("%s: bad VPD resource id: expected %x got %x\n",
    405 		    sc->bge_dev.dv_xname, VPD_RES_READ, res.vr_id);
    406 		return;
    407 	}
    408 
    409 	pos += sizeof(res);
    410 	sc->bge_vpd_readonly = malloc(res.vr_len, M_DEVBUF, M_NOWAIT);
    411 	if (sc->bge_vpd_readonly == NULL)
    412 		panic("bge_vpd_read");
    413 	for (i = 0; i < res.vr_len + 1; i++)
    414 		sc->bge_vpd_readonly[i] = bge_vpd_readbyte(sc, i + pos);
    415 }
    416 #endif
    417 
    418 /*
    419  * Read a byte of data stored in the EEPROM at address 'addr.' The
    420  * BCM570x supports both the traditional bitbang interface and an
    421  * auto access interface for reading the EEPROM. We use the auto
    422  * access method.
    423  */
    424 static u_int8_t
    425 bge_eeprom_getbyte(struct bge_softc *sc, int addr, u_int8_t *dest)
    426 {
    427 	int i;
    428 	u_int32_t byte = 0;
    429 
    430 	/*
    431 	 * Enable use of auto EEPROM access so we can avoid
    432 	 * having to use the bitbang method.
    433 	 */
    434 	BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM);
    435 
    436 	/* Reset the EEPROM, load the clock period. */
    437 	CSR_WRITE_4(sc, BGE_EE_ADDR,
    438 	    BGE_EEADDR_RESET|BGE_EEHALFCLK(BGE_HALFCLK_384SCL));
    439 	DELAY(20);
    440 
    441 	/* Issue the read EEPROM command. */
    442 	CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr);
    443 
    444 	/* Wait for completion */
    445 	for(i = 0; i < BGE_TIMEOUT * 10; i++) {
    446 		DELAY(10);
    447 		if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE)
    448 			break;
    449 	}
    450 
    451 	if (i == BGE_TIMEOUT) {
    452 		printf("%s: eeprom read timed out\n", sc->bge_dev.dv_xname);
    453 		return(0);
    454 	}
    455 
    456 	/* Get result. */
    457 	byte = CSR_READ_4(sc, BGE_EE_DATA);
    458 
    459 	*dest = (byte >> ((addr % 4) * 8)) & 0xFF;
    460 
    461 	return(0);
    462 }
    463 
    464 /*
    465  * Read a sequence of bytes from the EEPROM.
    466  */
    467 static int
    468 bge_read_eeprom(struct bge_softc *sc, void *destv, int off, int cnt)
    469 {
    470 	int err = 0, i;
    471 	u_int8_t byte = 0;
    472 	char *dest = destv;
    473 
    474 	for (i = 0; i < cnt; i++) {
    475 		err = bge_eeprom_getbyte(sc, off + i, &byte);
    476 		if (err)
    477 			break;
    478 		*(dest + i) = byte;
    479 	}
    480 
    481 	return(err ? 1 : 0);
    482 }
    483 
    484 static int
    485 bge_miibus_readreg(device_t dev, int phy, int reg)
    486 {
    487 	struct bge_softc *sc = (struct bge_softc *)dev;
    488 	u_int32_t val;
    489 	u_int32_t saved_autopoll;
    490 	int i;
    491 
    492 	/*
    493 	 * Several chips with builtin PHYs will incorrectly answer to
    494 	 * other PHY instances than the builtin PHY at id 1.
    495 	 */
    496 	if (phy != 1 && (sc->bge_quirks & BGE_QUIRK_ONLY_PHY_1))
    497 		return(0);
    498 
    499 	/* Reading with autopolling on may trigger PCI errors */
    500 	saved_autopoll = CSR_READ_4(sc, BGE_MI_MODE);
    501 	if (saved_autopoll & BGE_MIMODE_AUTOPOLL) {
    502 		CSR_WRITE_4(sc, BGE_MI_MODE,
    503 		    saved_autopoll &~ BGE_MIMODE_AUTOPOLL);
    504 		DELAY(40);
    505 	}
    506 
    507 	CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_READ|BGE_MICOMM_BUSY|
    508 	    BGE_MIPHY(phy)|BGE_MIREG(reg));
    509 
    510 	for (i = 0; i < BGE_TIMEOUT; i++) {
    511 		val = CSR_READ_4(sc, BGE_MI_COMM);
    512 		if (!(val & BGE_MICOMM_BUSY))
    513 			break;
    514 		delay(10);
    515 	}
    516 
    517 	if (i == BGE_TIMEOUT) {
    518 		printf("%s: PHY read timed out\n", sc->bge_dev.dv_xname);
    519 		val = 0;
    520 		goto done;
    521 	}
    522 
    523 	val = CSR_READ_4(sc, BGE_MI_COMM);
    524 
    525 done:
    526 	if (saved_autopoll & BGE_MIMODE_AUTOPOLL) {
    527 		CSR_WRITE_4(sc, BGE_MI_MODE, saved_autopoll);
    528 		DELAY(40);
    529 	}
    530 
    531 	if (val & BGE_MICOMM_READFAIL)
    532 		return(0);
    533 
    534 	return(val & 0xFFFF);
    535 }
    536 
    537 static void
    538 bge_miibus_writereg(device_t dev, int phy, int reg, int val)
    539 {
    540 	struct bge_softc *sc = (struct bge_softc *)dev;
    541 	u_int32_t saved_autopoll;
    542 	int i;
    543 
    544 	/* Touching the PHY while autopolling is on may trigger PCI errors */
    545 	saved_autopoll = CSR_READ_4(sc, BGE_MI_MODE);
    546 	if (saved_autopoll & BGE_MIMODE_AUTOPOLL) {
    547 		delay(40);
    548 		CSR_WRITE_4(sc, BGE_MI_MODE,
    549 		    saved_autopoll & (~BGE_MIMODE_AUTOPOLL));
    550 		delay(10); /* 40 usec is supposed to be adequate */
    551 	}
    552 
    553 	CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_WRITE|BGE_MICOMM_BUSY|
    554 	    BGE_MIPHY(phy)|BGE_MIREG(reg)|val);
    555 
    556 	for (i = 0; i < BGE_TIMEOUT; i++) {
    557 		if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY))
    558 			break;
    559 		delay(10);
    560 	}
    561 
    562 	if (saved_autopoll & BGE_MIMODE_AUTOPOLL) {
    563 		CSR_WRITE_4(sc, BGE_MI_MODE, saved_autopoll);
    564 		delay(40);
    565 	}
    566 
    567 	if (i == BGE_TIMEOUT) {
    568 		printf("%s: PHY read timed out\n", sc->bge_dev.dv_xname);
    569 	}
    570 }
    571 
    572 static void
    573 bge_miibus_statchg(device_t dev)
    574 {
    575 	struct bge_softc *sc = (struct bge_softc *)dev;
    576 	struct mii_data *mii = &sc->bge_mii;
    577 
    578 	/*
    579 	 * Get flow control negotiation result.
    580 	 */
    581 	if (IFM_SUBTYPE(mii->mii_media.ifm_cur->ifm_media) == IFM_AUTO &&
    582 	    (mii->mii_media_active & IFM_ETH_FMASK) != sc->bge_flowflags) {
    583 		sc->bge_flowflags = mii->mii_media_active & IFM_ETH_FMASK;
    584 		mii->mii_media_active &= ~IFM_ETH_FMASK;
    585 	}
    586 
    587 	BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_PORTMODE);
    588 	if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) {
    589 		BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_GMII);
    590 	} else {
    591 		BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_MII);
    592 	}
    593 
    594 	if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
    595 		BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX);
    596 	} else {
    597 		BGE_SETBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX);
    598 	}
    599 
    600 	/*
    601 	 * 802.3x flow control
    602 	 */
    603 	if (sc->bge_flowflags & IFM_ETH_RXPAUSE) {
    604 		BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_FLOWCTL_ENABLE);
    605 	} else {
    606 		BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_FLOWCTL_ENABLE);
    607 	}
    608 	if (sc->bge_flowflags & IFM_ETH_TXPAUSE) {
    609 		BGE_SETBIT(sc, BGE_TX_MODE, BGE_TXMODE_FLOWCTL_ENABLE);
    610 	} else {
    611 		BGE_CLRBIT(sc, BGE_TX_MODE, BGE_TXMODE_FLOWCTL_ENABLE);
    612 	}
    613 }
    614 
    615 /*
    616  * Update rx threshold levels to values in a particular slot
    617  * of the interrupt-mitigation table bge_rx_threshes.
    618  */
    619 static void
    620 bge_set_thresh(struct ifnet *ifp, int lvl)
    621 {
    622 	struct bge_softc *sc = ifp->if_softc;
    623 	int s;
    624 
    625 	/* For now, just save the new Rx-intr thresholds and record
    626 	 * that a threshold update is pending.  Updating the hardware
    627 	 * registers here (even at splhigh()) is observed to
    628 	 * occasionaly cause glitches where Rx-interrupts are not
    629 	 * honoured for up to 10 seconds. jonathan (at) NetBSD.org, 2003-04-05
    630 	 */
    631 	s = splnet();
    632 	sc->bge_rx_coal_ticks = bge_rx_threshes[lvl].rx_ticks;
    633 	sc->bge_rx_max_coal_bds = bge_rx_threshes[lvl].rx_max_bds;
    634 	sc->bge_pending_rxintr_change = 1;
    635 	splx(s);
    636 
    637 	 return;
    638 }
    639 
    640 
    641 /*
    642  * Update Rx thresholds of all bge devices
    643  */
    644 static void
    645 bge_update_all_threshes(int lvl)
    646 {
    647 	struct ifnet *ifp;
    648 	const char * const namebuf = "bge";
    649 	int namelen;
    650 
    651 	if (lvl < 0)
    652 		lvl = 0;
    653 	else if( lvl >= NBGE_RX_THRESH)
    654 		lvl = NBGE_RX_THRESH - 1;
    655 
    656 	namelen = strlen(namebuf);
    657 	/*
    658 	 * Now search all the interfaces for this name/number
    659 	 */
    660 	IFNET_FOREACH(ifp) {
    661 		if (strncmp(ifp->if_xname, namebuf, namelen) != 0)
    662 		      continue;
    663 		/* We got a match: update if doing auto-threshold-tuning */
    664 		if (bge_auto_thresh)
    665 			bge_set_thresh(ifp, lvl);
    666 	}
    667 }
    668 
    669 /*
    670  * Handle events that have triggered interrupts.
    671  */
    672 static void
    673 bge_handle_events(struct bge_softc *sc)
    674 {
    675 
    676 	return;
    677 }
    678 
    679 /*
    680  * Memory management for jumbo frames.
    681  */
    682 
    683 static int
    684 bge_alloc_jumbo_mem(struct bge_softc *sc)
    685 {
    686 	char *ptr, *kva;
    687 	bus_dma_segment_t	seg;
    688 	int		i, rseg, state, error;
    689 	struct bge_jpool_entry   *entry;
    690 
    691 	state = error = 0;
    692 
    693 	/* Grab a big chunk o' storage. */
    694 	if (bus_dmamem_alloc(sc->bge_dmatag, BGE_JMEM, PAGE_SIZE, 0,
    695 	     &seg, 1, &rseg, BUS_DMA_NOWAIT)) {
    696 		printf("%s: can't alloc rx buffers\n", sc->bge_dev.dv_xname);
    697 		return ENOBUFS;
    698 	}
    699 
    700 	state = 1;
    701 	if (bus_dmamem_map(sc->bge_dmatag, &seg, rseg, BGE_JMEM, (void **)&kva,
    702 	    BUS_DMA_NOWAIT)) {
    703 		printf("%s: can't map DMA buffers (%d bytes)\n",
    704 		    sc->bge_dev.dv_xname, (int)BGE_JMEM);
    705 		error = ENOBUFS;
    706 		goto out;
    707 	}
    708 
    709 	state = 2;
    710 	if (bus_dmamap_create(sc->bge_dmatag, BGE_JMEM, 1, BGE_JMEM, 0,
    711 	    BUS_DMA_NOWAIT, &sc->bge_cdata.bge_rx_jumbo_map)) {
    712 		printf("%s: can't create DMA map\n", sc->bge_dev.dv_xname);
    713 		error = ENOBUFS;
    714 		goto out;
    715 	}
    716 
    717 	state = 3;
    718 	if (bus_dmamap_load(sc->bge_dmatag, sc->bge_cdata.bge_rx_jumbo_map,
    719 	    kva, BGE_JMEM, NULL, BUS_DMA_NOWAIT)) {
    720 		printf("%s: can't load DMA map\n", sc->bge_dev.dv_xname);
    721 		error = ENOBUFS;
    722 		goto out;
    723 	}
    724 
    725 	state = 4;
    726 	sc->bge_cdata.bge_jumbo_buf = (void *)kva;
    727 	DPRINTFN(1,("bge_jumbo_buf = %p\n", sc->bge_cdata.bge_jumbo_buf));
    728 
    729 	SLIST_INIT(&sc->bge_jfree_listhead);
    730 	SLIST_INIT(&sc->bge_jinuse_listhead);
    731 
    732 	/*
    733 	 * Now divide it up into 9K pieces and save the addresses
    734 	 * in an array.
    735 	 */
    736 	ptr = sc->bge_cdata.bge_jumbo_buf;
    737 	for (i = 0; i < BGE_JSLOTS; i++) {
    738 		sc->bge_cdata.bge_jslots[i] = ptr;
    739 		ptr += BGE_JLEN;
    740 		entry = malloc(sizeof(struct bge_jpool_entry),
    741 		    M_DEVBUF, M_NOWAIT);
    742 		if (entry == NULL) {
    743 			printf("%s: no memory for jumbo buffer queue!\n",
    744 			    sc->bge_dev.dv_xname);
    745 			error = ENOBUFS;
    746 			goto out;
    747 		}
    748 		entry->slot = i;
    749 		SLIST_INSERT_HEAD(&sc->bge_jfree_listhead,
    750 				 entry, jpool_entries);
    751 	}
    752 out:
    753 	if (error != 0) {
    754 		switch (state) {
    755 		case 4:
    756 			bus_dmamap_unload(sc->bge_dmatag,
    757 			    sc->bge_cdata.bge_rx_jumbo_map);
    758 		case 3:
    759 			bus_dmamap_destroy(sc->bge_dmatag,
    760 			    sc->bge_cdata.bge_rx_jumbo_map);
    761 		case 2:
    762 			bus_dmamem_unmap(sc->bge_dmatag, kva, BGE_JMEM);
    763 		case 1:
    764 			bus_dmamem_free(sc->bge_dmatag, &seg, rseg);
    765 			break;
    766 		default:
    767 			break;
    768 		}
    769 	}
    770 
    771 	return error;
    772 }
    773 
    774 /*
    775  * Allocate a jumbo buffer.
    776  */
    777 static void *
    778 bge_jalloc(struct bge_softc *sc)
    779 {
    780 	struct bge_jpool_entry   *entry;
    781 
    782 	entry = SLIST_FIRST(&sc->bge_jfree_listhead);
    783 
    784 	if (entry == NULL) {
    785 		printf("%s: no free jumbo buffers\n", sc->bge_dev.dv_xname);
    786 		return(NULL);
    787 	}
    788 
    789 	SLIST_REMOVE_HEAD(&sc->bge_jfree_listhead, jpool_entries);
    790 	SLIST_INSERT_HEAD(&sc->bge_jinuse_listhead, entry, jpool_entries);
    791 	return(sc->bge_cdata.bge_jslots[entry->slot]);
    792 }
    793 
    794 /*
    795  * Release a jumbo buffer.
    796  */
    797 static void
    798 bge_jfree(struct mbuf *m, void *buf, size_t size, void *arg)
    799 {
    800 	struct bge_jpool_entry *entry;
    801 	struct bge_softc *sc;
    802 	int i, s;
    803 
    804 	/* Extract the softc struct pointer. */
    805 	sc = (struct bge_softc *)arg;
    806 
    807 	if (sc == NULL)
    808 		panic("bge_jfree: can't find softc pointer!");
    809 
    810 	/* calculate the slot this buffer belongs to */
    811 
    812 	i = ((char *)buf
    813 	     - (char *)sc->bge_cdata.bge_jumbo_buf) / BGE_JLEN;
    814 
    815 	if ((i < 0) || (i >= BGE_JSLOTS))
    816 		panic("bge_jfree: asked to free buffer that we don't manage!");
    817 
    818 	s = splvm();
    819 	entry = SLIST_FIRST(&sc->bge_jinuse_listhead);
    820 	if (entry == NULL)
    821 		panic("bge_jfree: buffer not in use!");
    822 	entry->slot = i;
    823 	SLIST_REMOVE_HEAD(&sc->bge_jinuse_listhead, jpool_entries);
    824 	SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, entry, jpool_entries);
    825 
    826 	if (__predict_true(m != NULL))
    827   		pool_cache_put(&mbpool_cache, m);
    828 	splx(s);
    829 }
    830 
    831 
    832 /*
    833  * Intialize a standard receive ring descriptor.
    834  */
    835 static int
    836 bge_newbuf_std(struct bge_softc *sc, int i, struct mbuf *m, bus_dmamap_t dmamap)
    837 {
    838 	struct mbuf		*m_new = NULL;
    839 	struct bge_rx_bd	*r;
    840 	int			error;
    841 
    842 	if (dmamap == NULL) {
    843 		error = bus_dmamap_create(sc->bge_dmatag, MCLBYTES, 1,
    844 		    MCLBYTES, 0, BUS_DMA_NOWAIT, &dmamap);
    845 		if (error != 0)
    846 			return error;
    847 	}
    848 
    849 	sc->bge_cdata.bge_rx_std_map[i] = dmamap;
    850 
    851 	if (m == NULL) {
    852 		MGETHDR(m_new, M_DONTWAIT, MT_DATA);
    853 		if (m_new == NULL) {
    854 			return(ENOBUFS);
    855 		}
    856 
    857 		MCLGET(m_new, M_DONTWAIT);
    858 		if (!(m_new->m_flags & M_EXT)) {
    859 			m_freem(m_new);
    860 			return(ENOBUFS);
    861 		}
    862 		m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
    863 
    864 	} else {
    865 		m_new = m;
    866 		m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
    867 		m_new->m_data = m_new->m_ext.ext_buf;
    868 	}
    869 	if (!sc->bge_rx_alignment_bug)
    870 	    m_adj(m_new, ETHER_ALIGN);
    871 	if (bus_dmamap_load_mbuf(sc->bge_dmatag, dmamap, m_new,
    872 	    BUS_DMA_READ|BUS_DMA_NOWAIT))
    873 		return(ENOBUFS);
    874 	bus_dmamap_sync(sc->bge_dmatag, dmamap, 0, dmamap->dm_mapsize,
    875 	    BUS_DMASYNC_PREREAD);
    876 
    877 	sc->bge_cdata.bge_rx_std_chain[i] = m_new;
    878 	r = &sc->bge_rdata->bge_rx_std_ring[i];
    879 	bge_set_hostaddr(&r->bge_addr,
    880 	    dmamap->dm_segs[0].ds_addr);
    881 	r->bge_flags = BGE_RXBDFLAG_END;
    882 	r->bge_len = m_new->m_len;
    883 	r->bge_idx = i;
    884 
    885 	bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map,
    886 	    offsetof(struct bge_ring_data, bge_rx_std_ring) +
    887 		i * sizeof (struct bge_rx_bd),
    888 	    sizeof (struct bge_rx_bd),
    889 	    BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD);
    890 
    891 	return(0);
    892 }
    893 
    894 /*
    895  * Initialize a jumbo receive ring descriptor. This allocates
    896  * a jumbo buffer from the pool managed internally by the driver.
    897  */
    898 static int
    899 bge_newbuf_jumbo(struct bge_softc *sc, int i, struct mbuf *m)
    900 {
    901 	struct mbuf *m_new = NULL;
    902 	struct bge_rx_bd *r;
    903 	void *buf = NULL;
    904 
    905 	if (m == NULL) {
    906 
    907 		/* Allocate the mbuf. */
    908 		MGETHDR(m_new, M_DONTWAIT, MT_DATA);
    909 		if (m_new == NULL) {
    910 			return(ENOBUFS);
    911 		}
    912 
    913 		/* Allocate the jumbo buffer */
    914 		buf = bge_jalloc(sc);
    915 		if (buf == NULL) {
    916 			m_freem(m_new);
    917 			printf("%s: jumbo allocation failed "
    918 			    "-- packet dropped!\n", sc->bge_dev.dv_xname);
    919 			return(ENOBUFS);
    920 		}
    921 
    922 		/* Attach the buffer to the mbuf. */
    923 		m_new->m_len = m_new->m_pkthdr.len = BGE_JUMBO_FRAMELEN;
    924 		MEXTADD(m_new, buf, BGE_JUMBO_FRAMELEN, M_DEVBUF,
    925 		    bge_jfree, sc);
    926 		m_new->m_flags |= M_EXT_RW;
    927 	} else {
    928 		m_new = m;
    929 		buf = m_new->m_data = m_new->m_ext.ext_buf;
    930 		m_new->m_ext.ext_size = BGE_JUMBO_FRAMELEN;
    931 	}
    932 	if (!sc->bge_rx_alignment_bug)
    933 	    m_adj(m_new, ETHER_ALIGN);
    934 	bus_dmamap_sync(sc->bge_dmatag, sc->bge_cdata.bge_rx_jumbo_map,
    935 	    mtod(m_new, char *) - (char *)sc->bge_cdata.bge_jumbo_buf, BGE_JLEN,
    936 	    BUS_DMASYNC_PREREAD);
    937 	/* Set up the descriptor. */
    938 	r = &sc->bge_rdata->bge_rx_jumbo_ring[i];
    939 	sc->bge_cdata.bge_rx_jumbo_chain[i] = m_new;
    940 	bge_set_hostaddr(&r->bge_addr, BGE_JUMBO_DMA_ADDR(sc, m_new));
    941 	r->bge_flags = BGE_RXBDFLAG_END|BGE_RXBDFLAG_JUMBO_RING;
    942 	r->bge_len = m_new->m_len;
    943 	r->bge_idx = i;
    944 
    945 	bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map,
    946 	    offsetof(struct bge_ring_data, bge_rx_jumbo_ring) +
    947 		i * sizeof (struct bge_rx_bd),
    948 	    sizeof (struct bge_rx_bd),
    949 	    BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD);
    950 
    951 	return(0);
    952 }
    953 
    954 /*
    955  * The standard receive ring has 512 entries in it. At 2K per mbuf cluster,
    956  * that's 1MB or memory, which is a lot. For now, we fill only the first
    957  * 256 ring entries and hope that our CPU is fast enough to keep up with
    958  * the NIC.
    959  */
    960 static int
    961 bge_init_rx_ring_std(struct bge_softc *sc)
    962 {
    963 	int i;
    964 
    965 	if (sc->bge_flags & BGE_RXRING_VALID)
    966 		return 0;
    967 
    968 	for (i = 0; i < BGE_SSLOTS; i++) {
    969 		if (bge_newbuf_std(sc, i, NULL, 0) == ENOBUFS)
    970 			return(ENOBUFS);
    971 	}
    972 
    973 	sc->bge_std = i - 1;
    974 	CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std);
    975 
    976 	sc->bge_flags |= BGE_RXRING_VALID;
    977 
    978 	return(0);
    979 }
    980 
    981 static void
    982 bge_free_rx_ring_std(struct bge_softc *sc)
    983 {
    984 	int i;
    985 
    986 	if (!(sc->bge_flags & BGE_RXRING_VALID))
    987 		return;
    988 
    989 	for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
    990 		if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) {
    991 			m_freem(sc->bge_cdata.bge_rx_std_chain[i]);
    992 			sc->bge_cdata.bge_rx_std_chain[i] = NULL;
    993 			bus_dmamap_destroy(sc->bge_dmatag,
    994 			    sc->bge_cdata.bge_rx_std_map[i]);
    995 		}
    996 		memset((char *)&sc->bge_rdata->bge_rx_std_ring[i], 0,
    997 		    sizeof(struct bge_rx_bd));
    998 	}
    999 
   1000 	sc->bge_flags &= ~BGE_RXRING_VALID;
   1001 }
   1002 
   1003 static int
   1004 bge_init_rx_ring_jumbo(struct bge_softc *sc)
   1005 {
   1006 	int i;
   1007 	volatile struct bge_rcb *rcb;
   1008 
   1009 	if (sc->bge_flags & BGE_JUMBO_RXRING_VALID)
   1010 		return 0;
   1011 
   1012 	for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
   1013 		if (bge_newbuf_jumbo(sc, i, NULL) == ENOBUFS)
   1014 			return(ENOBUFS);
   1015 	};
   1016 
   1017 	sc->bge_jumbo = i - 1;
   1018 	sc->bge_flags |= BGE_JUMBO_RXRING_VALID;
   1019 
   1020 	rcb = &sc->bge_rdata->bge_info.bge_jumbo_rx_rcb;
   1021 	rcb->bge_maxlen_flags = 0;
   1022 	CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags);
   1023 
   1024 	CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo);
   1025 
   1026 	return(0);
   1027 }
   1028 
   1029 static void
   1030 bge_free_rx_ring_jumbo(struct bge_softc *sc)
   1031 {
   1032 	int i;
   1033 
   1034 	if (!(sc->bge_flags & BGE_JUMBO_RXRING_VALID))
   1035 		return;
   1036 
   1037 	for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
   1038 		if (sc->bge_cdata.bge_rx_jumbo_chain[i] != NULL) {
   1039 			m_freem(sc->bge_cdata.bge_rx_jumbo_chain[i]);
   1040 			sc->bge_cdata.bge_rx_jumbo_chain[i] = NULL;
   1041 		}
   1042 		memset((char *)&sc->bge_rdata->bge_rx_jumbo_ring[i], 0,
   1043 		    sizeof(struct bge_rx_bd));
   1044 	}
   1045 
   1046 	sc->bge_flags &= ~BGE_JUMBO_RXRING_VALID;
   1047 }
   1048 
   1049 static void
   1050 bge_free_tx_ring(struct bge_softc *sc)
   1051 {
   1052 	int i, freed;
   1053 	struct txdmamap_pool_entry *dma;
   1054 
   1055 	if (!(sc->bge_flags & BGE_TXRING_VALID))
   1056 		return;
   1057 
   1058 	freed = 0;
   1059 
   1060 	for (i = 0; i < BGE_TX_RING_CNT; i++) {
   1061 		if (sc->bge_cdata.bge_tx_chain[i] != NULL) {
   1062 			freed++;
   1063 			m_freem(sc->bge_cdata.bge_tx_chain[i]);
   1064 			sc->bge_cdata.bge_tx_chain[i] = NULL;
   1065 			SLIST_INSERT_HEAD(&sc->txdma_list, sc->txdma[i],
   1066 					    link);
   1067 			sc->txdma[i] = 0;
   1068 		}
   1069 		memset((char *)&sc->bge_rdata->bge_tx_ring[i], 0,
   1070 		    sizeof(struct bge_tx_bd));
   1071 	}
   1072 
   1073 	while ((dma = SLIST_FIRST(&sc->txdma_list))) {
   1074 		SLIST_REMOVE_HEAD(&sc->txdma_list, link);
   1075 		bus_dmamap_destroy(sc->bge_dmatag, dma->dmamap);
   1076 		free(dma, M_DEVBUF);
   1077 	}
   1078 
   1079 	sc->bge_flags &= ~BGE_TXRING_VALID;
   1080 }
   1081 
   1082 static int
   1083 bge_init_tx_ring(struct bge_softc *sc)
   1084 {
   1085 	int i;
   1086 	bus_dmamap_t dmamap;
   1087 	struct txdmamap_pool_entry *dma;
   1088 
   1089 	if (sc->bge_flags & BGE_TXRING_VALID)
   1090 		return 0;
   1091 
   1092 	sc->bge_txcnt = 0;
   1093 	sc->bge_tx_saved_considx = 0;
   1094 
   1095 	/* Initialize transmit producer index for host-memory send ring. */
   1096 	sc->bge_tx_prodidx = 0;
   1097 	CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx);
   1098 	if (sc->bge_quirks & BGE_QUIRK_PRODUCER_BUG)	/* 5700 b2 errata */
   1099 		CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx);
   1100 
   1101 	/* NIC-memory send ring  not used; initialize to zero. */
   1102 	CSR_WRITE_4(sc, BGE_MBX_TX_NIC_PROD0_LO, 0);
   1103 	if (sc->bge_quirks & BGE_QUIRK_PRODUCER_BUG)	/* 5700 b2 errata */
   1104 		CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, 0);
   1105 
   1106 	SLIST_INIT(&sc->txdma_list);
   1107 	for (i = 0; i < BGE_RSLOTS; i++) {
   1108 		if (bus_dmamap_create(sc->bge_dmatag, BGE_TXDMA_MAX,
   1109 		    BGE_NTXSEG, ETHER_MAX_LEN_JUMBO, 0, BUS_DMA_NOWAIT,
   1110 		    &dmamap))
   1111 			return(ENOBUFS);
   1112 		if (dmamap == NULL)
   1113 			panic("dmamap NULL in bge_init_tx_ring");
   1114 		dma = malloc(sizeof(*dma), M_DEVBUF, M_NOWAIT);
   1115 		if (dma == NULL) {
   1116 			printf("%s: can't alloc txdmamap_pool_entry\n",
   1117 			    sc->bge_dev.dv_xname);
   1118 			bus_dmamap_destroy(sc->bge_dmatag, dmamap);
   1119 			return (ENOMEM);
   1120 		}
   1121 		dma->dmamap = dmamap;
   1122 		SLIST_INSERT_HEAD(&sc->txdma_list, dma, link);
   1123 	}
   1124 
   1125 	sc->bge_flags |= BGE_TXRING_VALID;
   1126 
   1127 	return(0);
   1128 }
   1129 
   1130 static void
   1131 bge_setmulti(struct bge_softc *sc)
   1132 {
   1133 	struct ethercom		*ac = &sc->ethercom;
   1134 	struct ifnet		*ifp = &ac->ec_if;
   1135 	struct ether_multi	*enm;
   1136 	struct ether_multistep  step;
   1137 	u_int32_t		hashes[4] = { 0, 0, 0, 0 };
   1138 	u_int32_t		h;
   1139 	int			i;
   1140 
   1141 	if (ifp->if_flags & IFF_PROMISC)
   1142 		goto allmulti;
   1143 
   1144 	/* Now program new ones. */
   1145 	ETHER_FIRST_MULTI(step, ac, enm);
   1146 	while (enm != NULL) {
   1147 		if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) {
   1148 			/*
   1149 			 * We must listen to a range of multicast addresses.
   1150 			 * For now, just accept all multicasts, rather than
   1151 			 * trying to set only those filter bits needed to match
   1152 			 * the range.  (At this time, the only use of address
   1153 			 * ranges is for IP multicast routing, for which the
   1154 			 * range is big enough to require all bits set.)
   1155 			 */
   1156 			goto allmulti;
   1157 		}
   1158 
   1159 		h = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN);
   1160 
   1161 		/* Just want the 7 least-significant bits. */
   1162 		h &= 0x7f;
   1163 
   1164 		hashes[(h & 0x60) >> 5] |= 1 << (h & 0x1F);
   1165 		ETHER_NEXT_MULTI(step, enm);
   1166 	}
   1167 
   1168 	ifp->if_flags &= ~IFF_ALLMULTI;
   1169 	goto setit;
   1170 
   1171  allmulti:
   1172 	ifp->if_flags |= IFF_ALLMULTI;
   1173 	hashes[0] = hashes[1] = hashes[2] = hashes[3] = 0xffffffff;
   1174 
   1175  setit:
   1176 	for (i = 0; i < 4; i++)
   1177 		CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]);
   1178 }
   1179 
   1180 const int bge_swapbits[] = {
   1181 	0,
   1182 	BGE_MODECTL_BYTESWAP_DATA,
   1183 	BGE_MODECTL_WORDSWAP_DATA,
   1184 	BGE_MODECTL_BYTESWAP_NONFRAME,
   1185 	BGE_MODECTL_WORDSWAP_NONFRAME,
   1186 
   1187 	BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA,
   1188 	BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_BYTESWAP_NONFRAME,
   1189 	BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_NONFRAME,
   1190 
   1191 	BGE_MODECTL_WORDSWAP_DATA|BGE_MODECTL_BYTESWAP_NONFRAME,
   1192 	BGE_MODECTL_WORDSWAP_DATA|BGE_MODECTL_WORDSWAP_NONFRAME,
   1193 
   1194 	BGE_MODECTL_BYTESWAP_NONFRAME|BGE_MODECTL_WORDSWAP_NONFRAME,
   1195 
   1196 	BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA|
   1197 	    BGE_MODECTL_BYTESWAP_NONFRAME,
   1198 	BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA|
   1199 	    BGE_MODECTL_WORDSWAP_NONFRAME,
   1200 	BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_BYTESWAP_NONFRAME|
   1201 	    BGE_MODECTL_WORDSWAP_NONFRAME,
   1202 	BGE_MODECTL_WORDSWAP_DATA|BGE_MODECTL_BYTESWAP_NONFRAME|
   1203 	    BGE_MODECTL_WORDSWAP_NONFRAME,
   1204 
   1205 	BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA|
   1206 	    BGE_MODECTL_BYTESWAP_NONFRAME|BGE_MODECTL_WORDSWAP_NONFRAME,
   1207 };
   1208 
   1209 int bge_swapindex = 0;
   1210 
   1211 /*
   1212  * Do endian, PCI and DMA initialization. Also check the on-board ROM
   1213  * self-test results.
   1214  */
   1215 static int
   1216 bge_chipinit(struct bge_softc *sc)
   1217 {
   1218 	u_int32_t		cachesize;
   1219 	int			i;
   1220 	u_int32_t		dma_rw_ctl;
   1221 	struct pci_attach_args	*pa = &(sc->bge_pa);
   1222 
   1223 
   1224 	/* Set endianness before we access any non-PCI registers. */
   1225 	pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_MISC_CTL,
   1226 	    BGE_INIT);
   1227 
   1228 	/* Set power state to D0. */
   1229 	bge_setpowerstate(sc, 0);
   1230 
   1231 	/*
   1232 	 * Check the 'ROM failed' bit on the RX CPU to see if
   1233 	 * self-tests passed.
   1234 	 */
   1235 	if (CSR_READ_4(sc, BGE_RXCPU_MODE) & BGE_RXCPUMODE_ROMFAIL) {
   1236 		printf("%s: RX CPU self-diagnostics failed!\n",
   1237 		    sc->bge_dev.dv_xname);
   1238 		return(ENODEV);
   1239 	}
   1240 
   1241 	/* Clear the MAC control register */
   1242 	CSR_WRITE_4(sc, BGE_MAC_MODE, 0);
   1243 
   1244 	/*
   1245 	 * Clear the MAC statistics block in the NIC's
   1246 	 * internal memory.
   1247 	 */
   1248 	for (i = BGE_STATS_BLOCK;
   1249 	    i < BGE_STATS_BLOCK_END + 1; i += sizeof(u_int32_t))
   1250 		BGE_MEMWIN_WRITE(pa->pa_pc, pa->pa_tag, i, 0);
   1251 
   1252 	for (i = BGE_STATUS_BLOCK;
   1253 	    i < BGE_STATUS_BLOCK_END + 1; i += sizeof(u_int32_t))
   1254 		BGE_MEMWIN_WRITE(pa->pa_pc, pa->pa_tag, i, 0);
   1255 
   1256 	/* Set up the PCI DMA control register. */
   1257 	if (sc->bge_pcie) {
   1258 	  u_int32_t device_ctl;
   1259 
   1260 		/* From FreeBSD */
   1261 		DPRINTFN(4, ("(%s: PCI-Express DMA setting)\n",
   1262 		    sc->bge_dev.dv_xname));
   1263 		dma_rw_ctl = (BGE_PCI_READ_CMD | BGE_PCI_WRITE_CMD |
   1264 		    (0xf << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
   1265 		    (0x2 << BGE_PCIDMARWCTL_WR_WAT_SHIFT));
   1266 
   1267 		/* jonathan: alternative from Linux driver */
   1268 #define DMA_CTRL_WRITE_PCIE_H20MARK_128         0x00180000
   1269 #define DMA_CTRL_WRITE_PCIE_H20MARK_256         0x00380000
   1270 
   1271 		dma_rw_ctl =   0x76000000; /* XXX XXX XXX */;
   1272 		device_ctl = pci_conf_read(pa->pa_pc, pa->pa_tag,
   1273 					   BGE_PCI_CONF_DEV_CTRL);
   1274 		aprint_debug("%s: pcie mode=0x%x\n", sc->bge_dev.dv_xname,
   1275 		    device_ctl);
   1276 
   1277 		if ((device_ctl & 0x00e0) && 0) {
   1278 			/*
   1279 			 * XXX jonathan (at) NetBSD.org:
   1280 			 * This clause is exactly what the Broadcom-supplied
   1281 			 * Linux does; but given overall register programming
   1282 			 * by if_bge(4), this larger DMA-write watermark
   1283 			 * value causes bcm5721 chips to totally wedge.
   1284 			 */
   1285 			dma_rw_ctl |= BGE_PCIDMA_RWCTL_PCIE_WRITE_WATRMARK_256;
   1286 		} else {
   1287 			dma_rw_ctl |= BGE_PCIDMA_RWCTL_PCIE_WRITE_WATRMARK_128;
   1288 		}
   1289 	} else if (pci_conf_read(pa->pa_pc, pa->pa_tag,BGE_PCI_PCISTATE) &
   1290 	    BGE_PCISTATE_PCI_BUSMODE) {
   1291 		/* Conventional PCI bus */
   1292 	  	DPRINTFN(4, ("(%s: PCI 2.2 DMA setting)\n", sc->bge_dev.dv_xname));
   1293 		dma_rw_ctl = (BGE_PCI_READ_CMD | BGE_PCI_WRITE_CMD |
   1294 		   (0x7 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
   1295 		   (0x7 << BGE_PCIDMARWCTL_WR_WAT_SHIFT));
   1296 		if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) {
   1297 			dma_rw_ctl |= 0x0F;
   1298 		}
   1299 	} else {
   1300 	  	DPRINTFN(4, ("(:%s: PCI-X DMA setting)\n", sc->bge_dev.dv_xname));
   1301 		/* PCI-X bus */
   1302 		dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
   1303 		    (0x3 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
   1304 		    (0x3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT) |
   1305 		    (0x0F);
   1306 		/*
   1307 		 * 5703 and 5704 need ONEDMA_AT_ONCE as a workaround
   1308 		 * for hardware bugs, which means we should also clear
   1309 		 * the low-order MINDMA bits.  In addition, the 5704
   1310 		 * uses a different encoding of read/write watermarks.
   1311 		 */
   1312 		if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) {
   1313 			dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
   1314 			  /* should be 0x1f0000 */
   1315 			  (0x7 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
   1316 			  (0x3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT);
   1317 			dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE;
   1318 		}
   1319 		else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5703) {
   1320 			dma_rw_ctl &=  0xfffffff0;
   1321 			dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE;
   1322 		}
   1323 		else if (BGE_IS_5714_FAMILY(sc)) {
   1324 			dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD;
   1325 			dma_rw_ctl &= ~BGE_PCIDMARWCTL_ONEDMA_ATONCE; /* XXX */
   1326 			/* XXX magic values, Broadcom-supplied Linux driver */
   1327 			if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5780)
   1328 				dma_rw_ctl |= (1 << 20) | (1 << 18) |
   1329 				  BGE_PCIDMARWCTL_ONEDMA_ATONCE;
   1330 			else
   1331 				dma_rw_ctl |= (1<<20) | (1<<18) | (1 << 15);
   1332 		}
   1333 	}
   1334 
   1335 	pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_DMA_RW_CTL, dma_rw_ctl);
   1336 
   1337 	/*
   1338 	 * Set up general mode register.
   1339 	 */
   1340 	CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS|
   1341 		    BGE_MODECTL_MAC_ATTN_INTR|BGE_MODECTL_HOST_SEND_BDS|
   1342 		    BGE_MODECTL_TX_NO_PHDR_CSUM|BGE_MODECTL_RX_NO_PHDR_CSUM);
   1343 
   1344 	/* Get cache line size. */
   1345 	cachesize = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_CACHESZ);
   1346 
   1347 	/*
   1348 	 * Avoid violating PCI spec on certain chip revs.
   1349 	 */
   1350 	if (pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_CMD) &
   1351 	    PCIM_CMD_MWIEN) {
   1352 		switch(cachesize) {
   1353 		case 1:
   1354 			PCI_SETBIT(pa->pa_pc, pa->pa_tag, BGE_PCI_DMA_RW_CTL,
   1355 				   BGE_PCI_WRITE_BNDRY_16BYTES);
   1356 			break;
   1357 		case 2:
   1358 			PCI_SETBIT(pa->pa_pc, pa->pa_tag, BGE_PCI_DMA_RW_CTL,
   1359 				   BGE_PCI_WRITE_BNDRY_32BYTES);
   1360 			break;
   1361 		case 4:
   1362 			PCI_SETBIT(pa->pa_pc, pa->pa_tag, BGE_PCI_DMA_RW_CTL,
   1363 				   BGE_PCI_WRITE_BNDRY_64BYTES);
   1364 			break;
   1365 		case 8:
   1366 			PCI_SETBIT(pa->pa_pc, pa->pa_tag, BGE_PCI_DMA_RW_CTL,
   1367 				   BGE_PCI_WRITE_BNDRY_128BYTES);
   1368 			break;
   1369 		case 16:
   1370 			PCI_SETBIT(pa->pa_pc, pa->pa_tag, BGE_PCI_DMA_RW_CTL,
   1371 				   BGE_PCI_WRITE_BNDRY_256BYTES);
   1372 			break;
   1373 		case 32:
   1374 			PCI_SETBIT(pa->pa_pc, pa->pa_tag, BGE_PCI_DMA_RW_CTL,
   1375 				   BGE_PCI_WRITE_BNDRY_512BYTES);
   1376 			break;
   1377 		case 64:
   1378 			PCI_SETBIT(pa->pa_pc, pa->pa_tag, BGE_PCI_DMA_RW_CTL,
   1379 				   BGE_PCI_WRITE_BNDRY_1024BYTES);
   1380 			break;
   1381 		default:
   1382 		/* Disable PCI memory write and invalidate. */
   1383 #if 0
   1384 			if (bootverbose)
   1385 				printf("%s: cache line size %d not "
   1386 				    "supported; disabling PCI MWI\n",
   1387 				    sc->bge_dev.dv_xname, cachesize);
   1388 #endif
   1389 			PCI_CLRBIT(pa->pa_pc, pa->pa_tag, BGE_PCI_CMD,
   1390 			    PCIM_CMD_MWIEN);
   1391 			break;
   1392 		}
   1393 	}
   1394 
   1395 	/*
   1396 	 * Disable memory write invalidate.  Apparently it is not supported
   1397 	 * properly by these devices.
   1398 	 */
   1399 	PCI_CLRBIT(pa->pa_pc, pa->pa_tag, BGE_PCI_CMD, PCIM_CMD_MWIEN);
   1400 
   1401 
   1402 #ifdef __brokenalpha__
   1403 	/*
   1404 	 * Must insure that we do not cross an 8K (bytes) boundary
   1405 	 * for DMA reads.  Our highest limit is 1K bytes.  This is a
   1406 	 * restriction on some ALPHA platforms with early revision
   1407 	 * 21174 PCI chipsets, such as the AlphaPC 164lx
   1408 	 */
   1409 	PCI_SETBIT(sc, BGE_PCI_DMA_RW_CTL, BGE_PCI_READ_BNDRY_1024, 4);
   1410 #endif
   1411 
   1412 	/* Set the timer prescaler (always 66MHz) */
   1413 	CSR_WRITE_4(sc, BGE_MISC_CFG, 65 << 1/*BGE_32BITTIME_66MHZ*/);
   1414 
   1415 	return(0);
   1416 }
   1417 
   1418 static int
   1419 bge_blockinit(struct bge_softc *sc)
   1420 {
   1421 	volatile struct bge_rcb		*rcb;
   1422 	bus_size_t		rcb_addr;
   1423 	int			i;
   1424 	struct ifnet		*ifp = &sc->ethercom.ec_if;
   1425 	bge_hostaddr		taddr;
   1426 
   1427 	/*
   1428 	 * Initialize the memory window pointer register so that
   1429 	 * we can access the first 32K of internal NIC RAM. This will
   1430 	 * allow us to set up the TX send ring RCBs and the RX return
   1431 	 * ring RCBs, plus other things which live in NIC memory.
   1432 	 */
   1433 
   1434 	pci_conf_write(sc->bge_pa.pa_pc, sc->bge_pa.pa_tag,
   1435 	    BGE_PCI_MEMWIN_BASEADDR, 0);
   1436 
   1437 	/* Configure mbuf memory pool */
   1438 	if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) {
   1439 		if (sc->bge_extram) {
   1440 			CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR,
   1441 			    BGE_EXT_SSRAM);
   1442 			if ((sc->bge_quirks & BGE_QUIRK_FEWER_MBUFS) != 0)
   1443 				CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000);
   1444 			else
   1445 				CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000);
   1446 		} else {
   1447 			CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR,
   1448 			    BGE_BUFFPOOL_1);
   1449 			if ((sc->bge_quirks & BGE_QUIRK_FEWER_MBUFS) != 0)
   1450 				CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000);
   1451 			else
   1452 				CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000);
   1453 		}
   1454 
   1455 		/* Configure DMA resource pool */
   1456 		CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_BASEADDR,
   1457 		    BGE_DMA_DESCRIPTORS);
   1458 		CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LEN, 0x2000);
   1459 	}
   1460 
   1461 	/* Configure mbuf pool watermarks */
   1462 #ifdef ORIG_WPAUL_VALUES
   1463 	CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 24);
   1464 	CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 24);
   1465 	CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 48);
   1466 #else
   1467 	/* new broadcom docs strongly recommend these: */
   1468 	if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) {
   1469 		if (ifp->if_mtu > ETHER_MAX_LEN) {
   1470 			CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x50);
   1471 			CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x20);
   1472 			CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60);
   1473 		} else {
   1474 			/* Values from Linux driver... */
   1475 			CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 304);
   1476 			CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 152);
   1477 			CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 380);
   1478 		}
   1479 	} else {
   1480 		CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0);
   1481 		CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x10);
   1482 		CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60);
   1483 	}
   1484 #endif
   1485 
   1486 	/* Configure DMA resource watermarks */
   1487 	CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5);
   1488 	CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10);
   1489 
   1490 	/* Enable buffer manager */
   1491 	CSR_WRITE_4(sc, BGE_BMAN_MODE,
   1492 	    BGE_BMANMODE_ENABLE|BGE_BMANMODE_LOMBUF_ATTN);
   1493 
   1494 	/* Poll for buffer manager start indication */
   1495 	for (i = 0; i < BGE_TIMEOUT; i++) {
   1496 		if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE)
   1497 			break;
   1498 		DELAY(10);
   1499 	}
   1500 
   1501 	if (i == BGE_TIMEOUT) {
   1502 		printf("%s: buffer manager failed to start\n",
   1503 		    sc->bge_dev.dv_xname);
   1504 		return(ENXIO);
   1505 	}
   1506 
   1507 	/* Enable flow-through queues */
   1508 	CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF);
   1509 	CSR_WRITE_4(sc, BGE_FTQ_RESET, 0);
   1510 
   1511 	/* Wait until queue initialization is complete */
   1512 	for (i = 0; i < BGE_TIMEOUT; i++) {
   1513 		if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0)
   1514 			break;
   1515 		DELAY(10);
   1516 	}
   1517 
   1518 	if (i == BGE_TIMEOUT) {
   1519 		printf("%s: flow-through queue init failed\n",
   1520 		    sc->bge_dev.dv_xname);
   1521 		return(ENXIO);
   1522 	}
   1523 
   1524 	/* Initialize the standard RX ring control block */
   1525 	rcb = &sc->bge_rdata->bge_info.bge_std_rx_rcb;
   1526 	bge_set_hostaddr(&rcb->bge_hostaddr,
   1527 	    BGE_RING_DMA_ADDR(sc, bge_rx_std_ring));
   1528 	if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) {
   1529 		rcb->bge_maxlen_flags =
   1530 		    BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 0);
   1531 	} else {
   1532 		rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(512, 0);
   1533 	}
   1534 	if (sc->bge_extram)
   1535 		rcb->bge_nicaddr = BGE_EXT_STD_RX_RINGS;
   1536 	else
   1537 		rcb->bge_nicaddr = BGE_STD_RX_RINGS;
   1538 	CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcb->bge_hostaddr.bge_addr_hi);
   1539 	CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcb->bge_hostaddr.bge_addr_lo);
   1540 	CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags);
   1541 	CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcb->bge_nicaddr);
   1542 
   1543 	if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) {
   1544 		sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT;
   1545 	} else {
   1546 		sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT_5705;
   1547 	}
   1548 
   1549 	/*
   1550 	 * Initialize the jumbo RX ring control block
   1551 	 * We set the 'ring disabled' bit in the flags
   1552 	 * field until we're actually ready to start
   1553 	 * using this ring (i.e. once we set the MTU
   1554 	 * high enough to require it).
   1555 	 */
   1556 	if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) {
   1557 		rcb = &sc->bge_rdata->bge_info.bge_jumbo_rx_rcb;
   1558 		bge_set_hostaddr(&rcb->bge_hostaddr,
   1559 		    BGE_RING_DMA_ADDR(sc, bge_rx_jumbo_ring));
   1560 		rcb->bge_maxlen_flags =
   1561 		    BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN,
   1562 			BGE_RCB_FLAG_RING_DISABLED);
   1563 		if (sc->bge_extram)
   1564 			rcb->bge_nicaddr = BGE_EXT_JUMBO_RX_RINGS;
   1565 		else
   1566 			rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS;
   1567 
   1568 		CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI,
   1569 		    rcb->bge_hostaddr.bge_addr_hi);
   1570 		CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO,
   1571 		    rcb->bge_hostaddr.bge_addr_lo);
   1572 		CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS,
   1573 		    rcb->bge_maxlen_flags);
   1574 		CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcb->bge_nicaddr);
   1575 
   1576 		/* Set up dummy disabled mini ring RCB */
   1577 		rcb = &sc->bge_rdata->bge_info.bge_mini_rx_rcb;
   1578 		rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0,
   1579 		    BGE_RCB_FLAG_RING_DISABLED);
   1580 		CSR_WRITE_4(sc, BGE_RX_MINI_RCB_MAXLEN_FLAGS,
   1581 		    rcb->bge_maxlen_flags);
   1582 
   1583 		bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map,
   1584 		    offsetof(struct bge_ring_data, bge_info),
   1585 		    sizeof (struct bge_gib),
   1586 		    BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
   1587 	}
   1588 
   1589 	/*
   1590 	 * Set the BD ring replentish thresholds. The recommended
   1591 	 * values are 1/8th the number of descriptors allocated to
   1592 	 * each ring.
   1593 	 */
   1594 	CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, BGE_STD_RX_RING_CNT/8);
   1595 	CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH, BGE_JUMBO_RX_RING_CNT/8);
   1596 
   1597 	/*
   1598 	 * Disable all unused send rings by setting the 'ring disabled'
   1599 	 * bit in the flags field of all the TX send ring control blocks.
   1600 	 * These are located in NIC memory.
   1601 	 */
   1602 	rcb_addr = BGE_MEMWIN_START + BGE_SEND_RING_RCB;
   1603 	for (i = 0; i < BGE_TX_RINGS_EXTSSRAM_MAX; i++) {
   1604 		RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags,
   1605 		    BGE_RCB_MAXLEN_FLAGS(0,BGE_RCB_FLAG_RING_DISABLED));
   1606 		RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 0);
   1607 		rcb_addr += sizeof(struct bge_rcb);
   1608 	}
   1609 
   1610 	/* Configure TX RCB 0 (we use only the first ring) */
   1611 	rcb_addr = BGE_MEMWIN_START + BGE_SEND_RING_RCB;
   1612 	bge_set_hostaddr(&taddr, BGE_RING_DMA_ADDR(sc, bge_tx_ring));
   1613 	RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi);
   1614 	RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo);
   1615 	RCB_WRITE_4(sc, rcb_addr, bge_nicaddr,
   1616 		    BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT));
   1617 	if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) {
   1618 		RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags,
   1619 		    BGE_RCB_MAXLEN_FLAGS(BGE_TX_RING_CNT, 0));
   1620 	}
   1621 
   1622 	/* Disable all unused RX return rings */
   1623 	rcb_addr = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB;
   1624 	for (i = 0; i < BGE_RX_RINGS_MAX; i++) {
   1625 		RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_hi, 0);
   1626 		RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_lo, 0);
   1627 		RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags,
   1628 			    BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt,
   1629                                      BGE_RCB_FLAG_RING_DISABLED));
   1630 		RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 0);
   1631 		CSR_WRITE_4(sc, BGE_MBX_RX_CONS0_LO +
   1632 		    (i * (sizeof(u_int64_t))), 0);
   1633 		rcb_addr += sizeof(struct bge_rcb);
   1634 	}
   1635 
   1636 	/* Initialize RX ring indexes */
   1637 	CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, 0);
   1638 	CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0);
   1639 	CSR_WRITE_4(sc, BGE_MBX_RX_MINI_PROD_LO, 0);
   1640 
   1641 	/*
   1642 	 * Set up RX return ring 0
   1643 	 * Note that the NIC address for RX return rings is 0x00000000.
   1644 	 * The return rings live entirely within the host, so the
   1645 	 * nicaddr field in the RCB isn't used.
   1646 	 */
   1647 	rcb_addr = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB;
   1648 	bge_set_hostaddr(&taddr, BGE_RING_DMA_ADDR(sc, bge_rx_return_ring));
   1649 	RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi);
   1650 	RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo);
   1651 	RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 0x00000000);
   1652 	RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags,
   1653 	    BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 0));
   1654 
   1655 	/* Set random backoff seed for TX */
   1656 	CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF,
   1657 	    LLADDR(ifp->if_sadl)[0] + LLADDR(ifp->if_sadl)[1] +
   1658 	    LLADDR(ifp->if_sadl)[2] + LLADDR(ifp->if_sadl)[3] +
   1659 	    LLADDR(ifp->if_sadl)[4] + LLADDR(ifp->if_sadl)[5] +
   1660 	    BGE_TX_BACKOFF_SEED_MASK);
   1661 
   1662 	/* Set inter-packet gap */
   1663 	CSR_WRITE_4(sc, BGE_TX_LENGTHS, 0x2620);
   1664 
   1665 	/*
   1666 	 * Specify which ring to use for packets that don't match
   1667 	 * any RX rules.
   1668 	 */
   1669 	CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08);
   1670 
   1671 	/*
   1672 	 * Configure number of RX lists. One interrupt distribution
   1673 	 * list, sixteen active lists, one bad frames class.
   1674 	 */
   1675 	CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181);
   1676 
   1677 	/* Inialize RX list placement stats mask. */
   1678 	CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF);
   1679 	CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1);
   1680 
   1681 	/* Disable host coalescing until we get it set up */
   1682 	CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000);
   1683 
   1684 	/* Poll to make sure it's shut down. */
   1685 	for (i = 0; i < BGE_TIMEOUT; i++) {
   1686 		if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE))
   1687 			break;
   1688 		DELAY(10);
   1689 	}
   1690 
   1691 	if (i == BGE_TIMEOUT) {
   1692 		printf("%s: host coalescing engine failed to idle\n",
   1693 		    sc->bge_dev.dv_xname);
   1694 		return(ENXIO);
   1695 	}
   1696 
   1697 	/* Set up host coalescing defaults */
   1698 	CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bge_rx_coal_ticks);
   1699 	CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bge_tx_coal_ticks);
   1700 	CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bge_rx_max_coal_bds);
   1701 	CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bge_tx_max_coal_bds);
   1702 	if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) {
   1703 		CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT, 0);
   1704 		CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT, 0);
   1705 	}
   1706 	CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 0);
   1707 	CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 0);
   1708 
   1709 	/* Set up address of statistics block */
   1710 	if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) {
   1711 		bge_set_hostaddr(&taddr,
   1712 		    BGE_RING_DMA_ADDR(sc, bge_info.bge_stats));
   1713 		CSR_WRITE_4(sc, BGE_HCC_STATS_TICKS, sc->bge_stat_ticks);
   1714 		CSR_WRITE_4(sc, BGE_HCC_STATS_BASEADDR, BGE_STATS_BLOCK);
   1715 		CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_HI, taddr.bge_addr_hi);
   1716 		CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_LO, taddr.bge_addr_lo);
   1717 	}
   1718 
   1719 	/* Set up address of status block */
   1720 	bge_set_hostaddr(&taddr, BGE_RING_DMA_ADDR(sc, bge_status_block));
   1721 	CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_BASEADDR, BGE_STATUS_BLOCK);
   1722 	CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI, taddr.bge_addr_hi);
   1723 	CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO, taddr.bge_addr_lo);
   1724 	sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx = 0;
   1725 	sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx = 0;
   1726 
   1727 	/* Turn on host coalescing state machine */
   1728 	CSR_WRITE_4(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE);
   1729 
   1730 	/* Turn on RX BD completion state machine and enable attentions */
   1731 	CSR_WRITE_4(sc, BGE_RBDC_MODE,
   1732 	    BGE_RBDCMODE_ENABLE|BGE_RBDCMODE_ATTN);
   1733 
   1734 	/* Turn on RX list placement state machine */
   1735 	CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);
   1736 
   1737 	/* Turn on RX list selector state machine. */
   1738 	if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) {
   1739 		CSR_WRITE_4(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE);
   1740 	}
   1741 
   1742 	/* Turn on DMA, clear stats */
   1743 	CSR_WRITE_4(sc, BGE_MAC_MODE, BGE_MACMODE_TXDMA_ENB|
   1744 	    BGE_MACMODE_RXDMA_ENB|BGE_MACMODE_RX_STATS_CLEAR|
   1745 	    BGE_MACMODE_TX_STATS_CLEAR|BGE_MACMODE_RX_STATS_ENB|
   1746 	    BGE_MACMODE_TX_STATS_ENB|BGE_MACMODE_FRMHDR_DMA_ENB|
   1747 	    (sc->bge_tbi ? BGE_PORTMODE_TBI : BGE_PORTMODE_MII));
   1748 
   1749 	/* Set misc. local control, enable interrupts on attentions */
   1750 	sc->bge_local_ctrl_reg = BGE_MLC_INTR_ONATTN | BGE_MLC_AUTO_EEPROM;
   1751 
   1752 #ifdef notdef
   1753 	/* Assert GPIO pins for PHY reset */
   1754 	BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUT0|
   1755 	    BGE_MLC_MISCIO_OUT1|BGE_MLC_MISCIO_OUT2);
   1756 	BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUTEN0|
   1757 	    BGE_MLC_MISCIO_OUTEN1|BGE_MLC_MISCIO_OUTEN2);
   1758 #endif
   1759 
   1760 #if defined(not_quite_yet)
   1761 	/* Linux driver enables enable gpio pin #1 on 5700s */
   1762 	if (sc->bge_chipid == BGE_CHIPID_BCM5700) {
   1763 		sc->bge_local_ctrl_reg |=
   1764 		  (BGE_MLC_MISCIO_OUT1|BGE_MLC_MISCIO_OUTEN1);
   1765 	}
   1766 #endif
   1767 	CSR_WRITE_4(sc, BGE_MISC_LOCAL_CTL, sc->bge_local_ctrl_reg);
   1768 
   1769 	/* Turn on DMA completion state machine */
   1770 	if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) {
   1771 		CSR_WRITE_4(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE);
   1772 	}
   1773 
   1774 	/* Turn on write DMA state machine */
   1775 	CSR_WRITE_4(sc, BGE_WDMA_MODE,
   1776 	    BGE_WDMAMODE_ENABLE|BGE_WDMAMODE_ALL_ATTNS);
   1777 
   1778 	/* Turn on read DMA state machine */
   1779 	{
   1780 		uint32_t dma_read_modebits;
   1781 
   1782 		dma_read_modebits =
   1783 		  BGE_RDMAMODE_ENABLE | BGE_RDMAMODE_ALL_ATTNS;
   1784 
   1785 		if (sc->bge_pcie && 0) {
   1786 			dma_read_modebits |= BGE_RDMA_MODE_FIFO_LONG_BURST;
   1787 		} else if ((sc->bge_quirks & BGE_QUIRK_5705_CORE)) {
   1788 			dma_read_modebits |= BGE_RDMA_MODE_FIFO_SIZE_128;
   1789 		}
   1790 
   1791 		/* XXX broadcom-supplied linux driver; undocumented */
   1792 		if (BGE_IS_5750_OR_BEYOND(sc)) {
   1793  			/*
   1794 			 * XXX: magic values.
   1795 			 * From Broadcom-supplied Linux driver;  apparently
   1796 			 * required to workaround a DMA bug affecting TSO
   1797 			 * on bcm575x/bcm5721?
   1798 			 */
   1799 			dma_read_modebits |= (1 << 27);
   1800 		}
   1801 		CSR_WRITE_4(sc, BGE_RDMA_MODE, dma_read_modebits);
   1802 	}
   1803 
   1804 	/* Turn on RX data completion state machine */
   1805 	CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);
   1806 
   1807 	/* Turn on RX BD initiator state machine */
   1808 	CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE);
   1809 
   1810 	/* Turn on RX data and RX BD initiator state machine */
   1811 	CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE);
   1812 
   1813 	/* Turn on Mbuf cluster free state machine */
   1814 	if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) {
   1815 		CSR_WRITE_4(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE);
   1816 	}
   1817 
   1818 	/* Turn on send BD completion state machine */
   1819 	CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);
   1820 
   1821 	/* Turn on send data completion state machine */
   1822 	CSR_WRITE_4(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE);
   1823 
   1824 	/* Turn on send data initiator state machine */
   1825 	if (BGE_IS_5750_OR_BEYOND(sc)) {
   1826 		/* XXX: magic value from Linux driver */
   1827 		CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE | 0x08);
   1828 	} else {
   1829 		CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE);
   1830 	}
   1831 
   1832 	/* Turn on send BD initiator state machine */
   1833 	CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE);
   1834 
   1835 	/* Turn on send BD selector state machine */
   1836 	CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE);
   1837 
   1838 	CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF);
   1839 	CSR_WRITE_4(sc, BGE_SDI_STATS_CTL,
   1840 	    BGE_SDISTATSCTL_ENABLE|BGE_SDISTATSCTL_FASTER);
   1841 
   1842 	/* ack/clear link change events */
   1843 	CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED|
   1844 	    BGE_MACSTAT_CFG_CHANGED);
   1845 	CSR_WRITE_4(sc, BGE_MI_STS, 0);
   1846 
   1847 	/* Enable PHY auto polling (for MII/GMII only) */
   1848 	if (sc->bge_tbi) {
   1849 		CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK);
   1850  	} else {
   1851 		BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL|10<<16);
   1852 		if (sc->bge_quirks & BGE_QUIRK_LINK_STATE_BROKEN)
   1853 			CSR_WRITE_4(sc, BGE_MAC_EVT_ENB,
   1854 			    BGE_EVTENB_MI_INTERRUPT);
   1855 	}
   1856 
   1857 	/* Enable link state change attentions. */
   1858 	BGE_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED);
   1859 
   1860 	return(0);
   1861 }
   1862 
   1863 static const struct bge_revision {
   1864 	uint32_t		br_chipid;
   1865 	uint32_t		br_quirks;
   1866 	const char		*br_name;
   1867 } bge_revisions[] = {
   1868 	{ BGE_CHIPID_BCM5700_A0,
   1869 	  BGE_QUIRK_LINK_STATE_BROKEN,
   1870 	  "BCM5700 A0" },
   1871 
   1872 	{ BGE_CHIPID_BCM5700_A1,
   1873 	  BGE_QUIRK_LINK_STATE_BROKEN,
   1874 	  "BCM5700 A1" },
   1875 
   1876 	{ BGE_CHIPID_BCM5700_B0,
   1877 	  BGE_QUIRK_LINK_STATE_BROKEN|BGE_QUIRK_CSUM_BROKEN|BGE_QUIRK_5700_COMMON,
   1878 	  "BCM5700 B0" },
   1879 
   1880 	{ BGE_CHIPID_BCM5700_B1,
   1881 	  BGE_QUIRK_LINK_STATE_BROKEN|BGE_QUIRK_5700_COMMON,
   1882 	  "BCM5700 B1" },
   1883 
   1884 	{ BGE_CHIPID_BCM5700_B2,
   1885 	  BGE_QUIRK_LINK_STATE_BROKEN|BGE_QUIRK_5700_COMMON,
   1886 	  "BCM5700 B2" },
   1887 
   1888 	{ BGE_CHIPID_BCM5700_B3,
   1889 	  BGE_QUIRK_LINK_STATE_BROKEN|BGE_QUIRK_5700_COMMON,
   1890 	  "BCM5700 B3" },
   1891 
   1892 	/* This is treated like a BCM5700 Bx */
   1893 	{ BGE_CHIPID_BCM5700_ALTIMA,
   1894 	  BGE_QUIRK_LINK_STATE_BROKEN|BGE_QUIRK_5700_COMMON,
   1895 	  "BCM5700 Altima" },
   1896 
   1897 	{ BGE_CHIPID_BCM5700_C0,
   1898 	  0,
   1899 	  "BCM5700 C0" },
   1900 
   1901 	{ BGE_CHIPID_BCM5701_A0,
   1902 	  0, /*XXX really, just not known */
   1903 	  "BCM5701 A0" },
   1904 
   1905 	{ BGE_CHIPID_BCM5701_B0,
   1906 	  BGE_QUIRK_PCIX_DMA_ALIGN_BUG,
   1907 	  "BCM5701 B0" },
   1908 
   1909 	{ BGE_CHIPID_BCM5701_B2,
   1910 	  BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_PCIX_DMA_ALIGN_BUG,
   1911 	  "BCM5701 B2" },
   1912 
   1913 	{ BGE_CHIPID_BCM5701_B5,
   1914 	  BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_PCIX_DMA_ALIGN_BUG,
   1915 	  "BCM5701 B5" },
   1916 
   1917 	{ BGE_CHIPID_BCM5703_A0,
   1918 	  0,
   1919 	  "BCM5703 A0" },
   1920 
   1921 	{ BGE_CHIPID_BCM5703_A1,
   1922 	  0,
   1923 	  "BCM5703 A1" },
   1924 
   1925 	{ BGE_CHIPID_BCM5703_A2,
   1926 	  BGE_QUIRK_ONLY_PHY_1,
   1927 	  "BCM5703 A2" },
   1928 
   1929 	{ BGE_CHIPID_BCM5703_A3,
   1930 	  BGE_QUIRK_ONLY_PHY_1,
   1931 	  "BCM5703 A3" },
   1932 
   1933 	{ BGE_CHIPID_BCM5703_B0,
   1934 	  BGE_QUIRK_ONLY_PHY_1,
   1935 	  "BCM5703 B0" },
   1936 
   1937 	{ BGE_CHIPID_BCM5704_A0,
   1938   	  BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_FEWER_MBUFS,
   1939 	  "BCM5704 A0" },
   1940 
   1941 	{ BGE_CHIPID_BCM5704_A1,
   1942   	  BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_FEWER_MBUFS,
   1943 	  "BCM5704 A1" },
   1944 
   1945 	{ BGE_CHIPID_BCM5704_A2,
   1946   	  BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_FEWER_MBUFS,
   1947 	  "BCM5704 A2" },
   1948 
   1949 	{ BGE_CHIPID_BCM5704_A3,
   1950   	  BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_FEWER_MBUFS,
   1951 	  "BCM5704 A3" },
   1952 
   1953 	{ BGE_CHIPID_BCM5705_A0,
   1954 	  BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_5705_CORE,
   1955 	  "BCM5705 A0" },
   1956 
   1957 	{ BGE_CHIPID_BCM5705_A1,
   1958 	  BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_5705_CORE,
   1959 	  "BCM5705 A1" },
   1960 
   1961 	{ BGE_CHIPID_BCM5705_A2,
   1962 	  BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_5705_CORE,
   1963 	  "BCM5705 A2" },
   1964 
   1965 	{ BGE_CHIPID_BCM5705_A3,
   1966 	  BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_5705_CORE,
   1967 	  "BCM5705 A3" },
   1968 
   1969 	{ BGE_CHIPID_BCM5750_A0,
   1970 	  BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_5705_CORE,
   1971 	  "BCM5750 A0" },
   1972 
   1973 	{ BGE_CHIPID_BCM5750_A1,
   1974 	  BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_5705_CORE,
   1975 	  "BCM5750 A1" },
   1976 
   1977 	{ BGE_CHIPID_BCM5751_A1,
   1978 	  BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_5705_CORE,
   1979 	  "BCM5751 A1" },
   1980 
   1981 	{ BGE_CHIPID_BCM5752_A0,
   1982 	  BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_5705_CORE,
   1983 	  "BCM5752 A0" },
   1984 
   1985 	{ BGE_CHIPID_BCM5752_A1,
   1986 	  BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_5705_CORE,
   1987 	  "BCM5752 A1" },
   1988 
   1989 	{ BGE_CHIPID_BCM5752_A2,
   1990 	  BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_5705_CORE,
   1991 	  "BCM5752 A2" },
   1992 
   1993 	{ 0, 0, NULL }
   1994 };
   1995 
   1996 /*
   1997  * Some defaults for major revisions, so that newer steppings
   1998  * that we don't know about have a shot at working.
   1999  */
   2000 static const struct bge_revision bge_majorrevs[] = {
   2001 	{ BGE_ASICREV_BCM5700,
   2002 	  BGE_QUIRK_LINK_STATE_BROKEN,
   2003 	  "unknown BCM5700" },
   2004 
   2005 	{ BGE_ASICREV_BCM5701,
   2006 	  BGE_QUIRK_PCIX_DMA_ALIGN_BUG,
   2007 	  "unknown BCM5701" },
   2008 
   2009 	{ BGE_ASICREV_BCM5703,
   2010 	  0,
   2011 	  "unknown BCM5703" },
   2012 
   2013 	{ BGE_ASICREV_BCM5704,
   2014 	  BGE_QUIRK_ONLY_PHY_1,
   2015 	  "unknown BCM5704" },
   2016 
   2017 	{ BGE_ASICREV_BCM5705,
   2018 	  BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_5705_CORE,
   2019 	  "unknown BCM5705" },
   2020 
   2021 	{ BGE_ASICREV_BCM5750,
   2022 	  BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_5705_CORE,
   2023 	  "unknown BCM575x family" },
   2024 
   2025 	{ BGE_ASICREV_BCM5714_A0,
   2026 	  BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_5705_CORE,
   2027 	  "unknown BCM5714" },
   2028 
   2029 	{ BGE_ASICREV_BCM5714,
   2030 	  BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_5705_CORE,
   2031 	  "unknown BCM5714" },
   2032 
   2033 	{ BGE_ASICREV_BCM5752,
   2034 	  BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_5705_CORE,
   2035 	  "unknown BCM5752 family" },
   2036 
   2037 
   2038 	{ BGE_ASICREV_BCM5780,
   2039 	  BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_5705_CORE,
   2040 	  "unknown BCM5780" },
   2041 
   2042 	{ 0,
   2043 	  0,
   2044 	  NULL }
   2045 };
   2046 
   2047 
   2048 static const struct bge_revision *
   2049 bge_lookup_rev(uint32_t chipid)
   2050 {
   2051 	const struct bge_revision *br;
   2052 
   2053 	for (br = bge_revisions; br->br_name != NULL; br++) {
   2054 		if (br->br_chipid == chipid)
   2055 			return (br);
   2056 	}
   2057 
   2058 	for (br = bge_majorrevs; br->br_name != NULL; br++) {
   2059 		if (br->br_chipid == BGE_ASICREV(chipid))
   2060 			return (br);
   2061 	}
   2062 
   2063 	return (NULL);
   2064 }
   2065 
   2066 static const struct bge_product {
   2067 	pci_vendor_id_t		bp_vendor;
   2068 	pci_product_id_t	bp_product;
   2069 	const char		*bp_name;
   2070 } bge_products[] = {
   2071 	/*
   2072 	 * The BCM5700 documentation seems to indicate that the hardware
   2073 	 * still has the Alteon vendor ID burned into it, though it
   2074 	 * should always be overridden by the value in the EEPROM.  We'll
   2075 	 * check for it anyway.
   2076 	 */
   2077 	{ PCI_VENDOR_ALTEON,
   2078 	  PCI_PRODUCT_ALTEON_BCM5700,
   2079 	  "Broadcom BCM5700 Gigabit Ethernet",
   2080 	  },
   2081 	{ PCI_VENDOR_ALTEON,
   2082 	  PCI_PRODUCT_ALTEON_BCM5701,
   2083 	  "Broadcom BCM5701 Gigabit Ethernet",
   2084 	  },
   2085 
   2086 	{ PCI_VENDOR_ALTIMA,
   2087 	  PCI_PRODUCT_ALTIMA_AC1000,
   2088 	  "Altima AC1000 Gigabit Ethernet",
   2089 	  },
   2090 	{ PCI_VENDOR_ALTIMA,
   2091 	  PCI_PRODUCT_ALTIMA_AC1001,
   2092 	  "Altima AC1001 Gigabit Ethernet",
   2093 	   },
   2094 	{ PCI_VENDOR_ALTIMA,
   2095 	  PCI_PRODUCT_ALTIMA_AC9100,
   2096 	  "Altima AC9100 Gigabit Ethernet",
   2097 	  },
   2098 
   2099 	{ PCI_VENDOR_BROADCOM,
   2100 	  PCI_PRODUCT_BROADCOM_BCM5700,
   2101 	  "Broadcom BCM5700 Gigabit Ethernet",
   2102 	  },
   2103 	{ PCI_VENDOR_BROADCOM,
   2104 	  PCI_PRODUCT_BROADCOM_BCM5701,
   2105 	  "Broadcom BCM5701 Gigabit Ethernet",
   2106 	  },
   2107 	{ PCI_VENDOR_BROADCOM,
   2108 	  PCI_PRODUCT_BROADCOM_BCM5702,
   2109 	  "Broadcom BCM5702 Gigabit Ethernet",
   2110 	  },
   2111 	{ PCI_VENDOR_BROADCOM,
   2112 	  PCI_PRODUCT_BROADCOM_BCM5702X,
   2113 	  "Broadcom BCM5702X Gigabit Ethernet" },
   2114 
   2115 	{ PCI_VENDOR_BROADCOM,
   2116 	  PCI_PRODUCT_BROADCOM_BCM5703,
   2117 	  "Broadcom BCM5703 Gigabit Ethernet",
   2118 	  },
   2119 	{ PCI_VENDOR_BROADCOM,
   2120 	  PCI_PRODUCT_BROADCOM_BCM5703X,
   2121 	  "Broadcom BCM5703X Gigabit Ethernet",
   2122 	  },
   2123 	{ PCI_VENDOR_BROADCOM,
   2124 	  PCI_PRODUCT_BROADCOM_BCM5703_ALT,
   2125 	  "Broadcom BCM5703 Gigabit Ethernet",
   2126 	  },
   2127 
   2128    	{ PCI_VENDOR_BROADCOM,
   2129 	  PCI_PRODUCT_BROADCOM_BCM5704C,
   2130 	  "Broadcom BCM5704C Dual Gigabit Ethernet",
   2131 	  },
   2132    	{ PCI_VENDOR_BROADCOM,
   2133 	  PCI_PRODUCT_BROADCOM_BCM5704S,
   2134 	  "Broadcom BCM5704S Dual Gigabit Ethernet",
   2135 	  },
   2136 
   2137    	{ PCI_VENDOR_BROADCOM,
   2138 	  PCI_PRODUCT_BROADCOM_BCM5705,
   2139 	  "Broadcom BCM5705 Gigabit Ethernet",
   2140 	  },
   2141    	{ PCI_VENDOR_BROADCOM,
   2142 	  PCI_PRODUCT_BROADCOM_BCM5705K,
   2143 	  "Broadcom BCM5705K Gigabit Ethernet",
   2144 	  },
   2145    	{ PCI_VENDOR_BROADCOM,
   2146 	  PCI_PRODUCT_BROADCOM_BCM5705M,
   2147 	  "Broadcom BCM5705M Gigabit Ethernet",
   2148 	  },
   2149    	{ PCI_VENDOR_BROADCOM,
   2150 	  PCI_PRODUCT_BROADCOM_BCM5705M_ALT,
   2151 	  "Broadcom BCM5705M Gigabit Ethernet",
   2152 	  },
   2153 
   2154 	{ PCI_VENDOR_BROADCOM,
   2155 	  PCI_PRODUCT_BROADCOM_BCM5714,
   2156 	  "Broadcom BCM5714/5715 Gigabit Ethernet",
   2157 	  },
   2158 	{ PCI_VENDOR_BROADCOM,
   2159 	  PCI_PRODUCT_BROADCOM_BCM5789,
   2160 	  "Broadcom BCM5789 Gigabit Ethernet",
   2161 	  },
   2162 
   2163 	{ PCI_VENDOR_BROADCOM,
   2164 	  PCI_PRODUCT_BROADCOM_BCM5721,
   2165 	  "Broadcom BCM5721 Gigabit Ethernet",
   2166 	  },
   2167 
   2168 	{ PCI_VENDOR_BROADCOM,
   2169 	  PCI_PRODUCT_BROADCOM_BCM5750,
   2170 	  "Broadcom BCM5750 Gigabit Ethernet",
   2171 	  },
   2172 
   2173 	{ PCI_VENDOR_BROADCOM,
   2174 	  PCI_PRODUCT_BROADCOM_BCM5750M,
   2175 	  "Broadcom BCM5750M Gigabit Ethernet",
   2176 	  },
   2177 
   2178 	{ PCI_VENDOR_BROADCOM,
   2179 	  PCI_PRODUCT_BROADCOM_BCM5751,
   2180 	  "Broadcom BCM5751 Gigabit Ethernet",
   2181 	  },
   2182 
   2183 	{ PCI_VENDOR_BROADCOM,
   2184 	  PCI_PRODUCT_BROADCOM_BCM5751M,
   2185 	  "Broadcom BCM5751M Gigabit Ethernet",
   2186 	  },
   2187 
   2188 	{ PCI_VENDOR_BROADCOM,
   2189 	  PCI_PRODUCT_BROADCOM_BCM5752,
   2190 	  "Broadcom BCM5752 Gigabit Ethernet",
   2191 	  },
   2192 
   2193 	{ PCI_VENDOR_BROADCOM,
   2194 	  PCI_PRODUCT_BROADCOM_BCM5752M,
   2195 	  "Broadcom BCM5752M Gigabit Ethernet",
   2196 	  },
   2197 
   2198    	{ PCI_VENDOR_BROADCOM,
   2199 	  PCI_PRODUCT_BROADCOM_BCM5780,
   2200 	  "Broadcom BCM5780 Gigabit Ethernet",
   2201 	  },
   2202 
   2203    	{ PCI_VENDOR_BROADCOM,
   2204 	  PCI_PRODUCT_BROADCOM_BCM5780S,
   2205 	  "Broadcom BCM5780S Gigabit Ethernet",
   2206 	  },
   2207 
   2208    	{ PCI_VENDOR_BROADCOM,
   2209 	  PCI_PRODUCT_BROADCOM_BCM5782,
   2210 	  "Broadcom BCM5782 Gigabit Ethernet",
   2211 	  },
   2212 
   2213    	{ PCI_VENDOR_BROADCOM,
   2214 	  PCI_PRODUCT_BROADCOM_BCM5788,
   2215 	  "Broadcom BCM5788 Gigabit Ethernet",
   2216 	  },
   2217    	{ PCI_VENDOR_BROADCOM,
   2218 	  PCI_PRODUCT_BROADCOM_BCM5789,
   2219 	  "Broadcom BCM5789 Gigabit Ethernet",
   2220 	  },
   2221 
   2222    	{ PCI_VENDOR_BROADCOM,
   2223 	  PCI_PRODUCT_BROADCOM_BCM5901,
   2224 	  "Broadcom BCM5901 Fast Ethernet",
   2225 	  },
   2226    	{ PCI_VENDOR_BROADCOM,
   2227 	  PCI_PRODUCT_BROADCOM_BCM5901A2,
   2228 	  "Broadcom BCM5901A2 Fast Ethernet",
   2229 	  },
   2230 
   2231 	{ PCI_VENDOR_SCHNEIDERKOCH,
   2232 	  PCI_PRODUCT_SCHNEIDERKOCH_SK_9DX1,
   2233 	  "SysKonnect SK-9Dx1 Gigabit Ethernet",
   2234 	  },
   2235 
   2236 	{ PCI_VENDOR_3COM,
   2237 	  PCI_PRODUCT_3COM_3C996,
   2238 	  "3Com 3c996 Gigabit Ethernet",
   2239 	  },
   2240 
   2241 	{ 0,
   2242 	  0,
   2243 	  NULL },
   2244 };
   2245 
   2246 static const struct bge_product *
   2247 bge_lookup(const struct pci_attach_args *pa)
   2248 {
   2249 	const struct bge_product *bp;
   2250 
   2251 	for (bp = bge_products; bp->bp_name != NULL; bp++) {
   2252 		if (PCI_VENDOR(pa->pa_id) == bp->bp_vendor &&
   2253 		    PCI_PRODUCT(pa->pa_id) == bp->bp_product)
   2254 			return (bp);
   2255 	}
   2256 
   2257 	return (NULL);
   2258 }
   2259 
   2260 static int
   2261 bge_setpowerstate(struct bge_softc *sc, int powerlevel)
   2262 {
   2263 #ifdef NOTYET
   2264 	u_int32_t pm_ctl = 0;
   2265 
   2266 	/* XXX FIXME: make sure indirect accesses enabled? */
   2267 	pm_ctl = pci_conf_read(sc->bge_dev, BGE_PCI_MISC_CTL, 4);
   2268 	pm_ctl |= BGE_PCIMISCCTL_INDIRECT_ACCESS;
   2269 	pci_write_config(sc->bge_dev, BGE_PCI_MISC_CTL, pm_ctl, 4);
   2270 
   2271 	/* clear the PME_assert bit and power state bits, enable PME */
   2272 	pm_ctl = pci_conf_read(sc->bge_dev, BGE_PCI_PWRMGMT_CMD, 2);
   2273 	pm_ctl &= ~PCIM_PSTAT_DMASK;
   2274 	pm_ctl |= (1 << 8);
   2275 
   2276 	if (powerlevel == 0) {
   2277 		pm_ctl |= PCIM_PSTAT_D0;
   2278 		pci_write_config(sc->bge_dev, BGE_PCI_PWRMGMT_CMD,
   2279 		    pm_ctl, 2);
   2280 		DELAY(10000);
   2281 		CSR_WRITE_4(sc, BGE_MISC_LOCAL_CTL, sc->bge_local_ctrl_reg);
   2282 		DELAY(10000);
   2283 
   2284 #ifdef NOTYET
   2285 		/* XXX FIXME: write 0x02 to phy aux_Ctrl reg */
   2286 		bge_miibus_writereg(sc->bge_dev, 1, 0x18, 0x02);
   2287 #endif
   2288 		DELAY(40); DELAY(40); DELAY(40);
   2289 		DELAY(10000);	/* above not quite adequate on 5700 */
   2290 		return 0;
   2291 	}
   2292 
   2293 
   2294 	/*
   2295 	 * Entering ACPI power states D1-D3 is achieved by wiggling
   2296 	 * GMII gpio pins. Example code assumes all hardware vendors
   2297 	 * followed Broadom's sample pcb layout. Until we verify that
   2298 	 * for all supported OEM cards, states D1-D3 are  unsupported.
   2299 	 */
   2300 	printf("%s: power state %d unimplemented; check GPIO pins\n",
   2301 	       sc->bge_dev.dv_xname, powerlevel);
   2302 #endif
   2303 	return EOPNOTSUPP;
   2304 }
   2305 
   2306 
   2307 /*
   2308  * Probe for a Broadcom chip. Check the PCI vendor and device IDs
   2309  * against our list and return its name if we find a match. Note
   2310  * that since the Broadcom controller contains VPD support, we
   2311  * can get the device name string from the controller itself instead
   2312  * of the compiled-in string. This is a little slow, but it guarantees
   2313  * we'll always announce the right product name.
   2314  */
   2315 static int
   2316 bge_probe(device_t parent, cfdata_t match, void *aux)
   2317 {
   2318 	struct pci_attach_args *pa = (struct pci_attach_args *)aux;
   2319 
   2320 	if (bge_lookup(pa) != NULL)
   2321 		return (1);
   2322 
   2323 	return (0);
   2324 }
   2325 
   2326 static void
   2327 bge_attach(device_t parent, device_t self, void *aux)
   2328 {
   2329 	struct bge_softc	*sc = (struct bge_softc *)self;
   2330 	struct pci_attach_args	*pa = aux;
   2331 	const struct bge_product *bp;
   2332 	const struct bge_revision *br;
   2333 	pci_chipset_tag_t	pc = pa->pa_pc;
   2334 	pci_intr_handle_t	ih;
   2335 	const char		*intrstr = NULL;
   2336 	bus_dma_segment_t	seg;
   2337 	int			rseg;
   2338 	u_int32_t		hwcfg = 0;
   2339 	u_int32_t		mac_addr = 0;
   2340 	u_int32_t		command;
   2341 	struct ifnet		*ifp;
   2342 	void *			kva;
   2343 	u_char			eaddr[ETHER_ADDR_LEN];
   2344 	pcireg_t		memtype;
   2345 	bus_addr_t		memaddr;
   2346 	bus_size_t		memsize;
   2347 	u_int32_t		pm_ctl;
   2348 
   2349 	bp = bge_lookup(pa);
   2350 	KASSERT(bp != NULL);
   2351 
   2352 	sc->bge_pa = *pa;
   2353 
   2354 	aprint_naive(": Ethernet controller\n");
   2355 	aprint_normal(": %s\n", bp->bp_name);
   2356 
   2357 	/*
   2358 	 * Map control/status registers.
   2359 	 */
   2360 	DPRINTFN(5, ("Map control/status regs\n"));
   2361 	command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG);
   2362 	command |= PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_MASTER_ENABLE;
   2363 	pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, command);
   2364 	command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG);
   2365 
   2366 	if (!(command & PCI_COMMAND_MEM_ENABLE)) {
   2367 		aprint_error("%s: failed to enable memory mapping!\n",
   2368 		    sc->bge_dev.dv_xname);
   2369 		return;
   2370 	}
   2371 
   2372 	DPRINTFN(5, ("pci_mem_find\n"));
   2373 	memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, BGE_PCI_BAR0);
   2374  	switch (memtype) {
   2375 	case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT:
   2376 	case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT:
   2377 		if (pci_mapreg_map(pa, BGE_PCI_BAR0,
   2378 		    memtype, 0, &sc->bge_btag, &sc->bge_bhandle,
   2379 		    &memaddr, &memsize) == 0)
   2380 			break;
   2381 	default:
   2382 		aprint_error("%s: can't find mem space\n",
   2383 		    sc->bge_dev.dv_xname);
   2384 		return;
   2385 	}
   2386 
   2387 	DPRINTFN(5, ("pci_intr_map\n"));
   2388 	if (pci_intr_map(pa, &ih)) {
   2389 		aprint_error("%s: couldn't map interrupt\n",
   2390 		    sc->bge_dev.dv_xname);
   2391 		return;
   2392 	}
   2393 
   2394 	DPRINTFN(5, ("pci_intr_string\n"));
   2395 	intrstr = pci_intr_string(pc, ih);
   2396 
   2397 	DPRINTFN(5, ("pci_intr_establish\n"));
   2398 	sc->bge_intrhand = pci_intr_establish(pc, ih, IPL_NET, bge_intr, sc);
   2399 
   2400 	if (sc->bge_intrhand == NULL) {
   2401 		aprint_error("%s: couldn't establish interrupt",
   2402 		    sc->bge_dev.dv_xname);
   2403 		if (intrstr != NULL)
   2404 			aprint_normal(" at %s", intrstr);
   2405 		aprint_normal("\n");
   2406 		return;
   2407 	}
   2408 	aprint_normal("%s: interrupting at %s\n",
   2409 	    sc->bge_dev.dv_xname, intrstr);
   2410 
   2411 	/*
   2412 	 * Kludge for 5700 Bx bug: a hardware bug (PCIX byte enable?)
   2413 	 * can clobber the chip's PCI config-space power control registers,
   2414 	 * leaving the card in D3 powersave state.
   2415 	 * We do not have memory-mapped registers in this state,
   2416 	 * so force device into D0 state before starting initialization.
   2417 	 */
   2418 	pm_ctl = pci_conf_read(pc, pa->pa_tag, BGE_PCI_PWRMGMT_CMD);
   2419 	pm_ctl &= ~(PCI_PWR_D0|PCI_PWR_D1|PCI_PWR_D2|PCI_PWR_D3);
   2420 	pm_ctl |= (1 << 8) | PCI_PWR_D0 ; /* D0 state */
   2421 	pci_conf_write(pc, pa->pa_tag, BGE_PCI_PWRMGMT_CMD, pm_ctl);
   2422 	DELAY(1000);	/* 27 usec is allegedly sufficent */
   2423 
   2424 	/*
   2425 	 * Save ASIC rev.  Look up any quirks associated with this
   2426 	 * ASIC.
   2427 	 */
   2428 	sc->bge_chipid =
   2429 	    pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_MISC_CTL) &
   2430 	    BGE_PCIMISCCTL_ASICREV;
   2431 
   2432 	/*
   2433 	 * Detect PCI-Express devices
   2434 	 * XXX: guessed from Linux/FreeBSD; no documentation
   2435 	 */
   2436 	if (pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_PCIEXPRESS,
   2437 	        NULL, NULL) != 0)
   2438 		sc->bge_pcie = 1;
   2439 	else
   2440 		sc->bge_pcie = 0;
   2441 
   2442 	/* Try to reset the chip. */
   2443 	DPRINTFN(5, ("bge_reset\n"));
   2444 	bge_reset(sc);
   2445 
   2446 	if (bge_chipinit(sc)) {
   2447 		aprint_error("%s: chip initialization failed\n",
   2448 		    sc->bge_dev.dv_xname);
   2449 		bge_release_resources(sc);
   2450 		return;
   2451 	}
   2452 
   2453 	/*
   2454 	 * Get station address from the EEPROM.
   2455 	 */
   2456 	mac_addr = bge_readmem_ind(sc, 0x0c14);
   2457 	if ((mac_addr >> 16) == 0x484b) {
   2458 		eaddr[0] = (u_char)(mac_addr >> 8);
   2459 		eaddr[1] = (u_char)(mac_addr >> 0);
   2460 		mac_addr = bge_readmem_ind(sc, 0x0c18);
   2461 		eaddr[2] = (u_char)(mac_addr >> 24);
   2462 		eaddr[3] = (u_char)(mac_addr >> 16);
   2463 		eaddr[4] = (u_char)(mac_addr >> 8);
   2464 		eaddr[5] = (u_char)(mac_addr >> 0);
   2465 	} else if (bge_read_eeprom(sc, (void *)eaddr,
   2466 	    BGE_EE_MAC_OFFSET + 2, ETHER_ADDR_LEN)) {
   2467 		aprint_error("%s: failed to read station address\n",
   2468 		    sc->bge_dev.dv_xname);
   2469 		bge_release_resources(sc);
   2470 		return;
   2471 	}
   2472 
   2473 	br = bge_lookup_rev(sc->bge_chipid);
   2474 	aprint_normal("%s: ", sc->bge_dev.dv_xname);
   2475 
   2476 	if (br == NULL) {
   2477 		aprint_normal("unknown ASIC (0x%04x)", sc->bge_chipid >> 16);
   2478 		sc->bge_quirks = 0;
   2479 	} else {
   2480 		aprint_normal("ASIC %s (0x%04x)",
   2481 		    br->br_name, sc->bge_chipid >> 16);
   2482 		sc->bge_quirks |= br->br_quirks;
   2483 	}
   2484 	aprint_normal(", Ethernet address %s\n", ether_sprintf(eaddr));
   2485 
   2486 	/* Allocate the general information block and ring buffers. */
   2487 	if (pci_dma64_available(pa))
   2488 		sc->bge_dmatag = pa->pa_dmat64;
   2489 	else
   2490 		sc->bge_dmatag = pa->pa_dmat;
   2491 	DPRINTFN(5, ("bus_dmamem_alloc\n"));
   2492 	if (bus_dmamem_alloc(sc->bge_dmatag, sizeof(struct bge_ring_data),
   2493 			     PAGE_SIZE, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) {
   2494 		aprint_error("%s: can't alloc rx buffers\n",
   2495 		    sc->bge_dev.dv_xname);
   2496 		return;
   2497 	}
   2498 	DPRINTFN(5, ("bus_dmamem_map\n"));
   2499 	if (bus_dmamem_map(sc->bge_dmatag, &seg, rseg,
   2500 			   sizeof(struct bge_ring_data), &kva,
   2501 			   BUS_DMA_NOWAIT)) {
   2502 		aprint_error("%s: can't map DMA buffers (%d bytes)\n",
   2503 		    sc->bge_dev.dv_xname, (int)sizeof(struct bge_ring_data));
   2504 		bus_dmamem_free(sc->bge_dmatag, &seg, rseg);
   2505 		return;
   2506 	}
   2507 	DPRINTFN(5, ("bus_dmamem_create\n"));
   2508 	if (bus_dmamap_create(sc->bge_dmatag, sizeof(struct bge_ring_data), 1,
   2509 	    sizeof(struct bge_ring_data), 0,
   2510 	    BUS_DMA_NOWAIT, &sc->bge_ring_map)) {
   2511 		aprint_error("%s: can't create DMA map\n",
   2512 		    sc->bge_dev.dv_xname);
   2513 		bus_dmamem_unmap(sc->bge_dmatag, kva,
   2514 				 sizeof(struct bge_ring_data));
   2515 		bus_dmamem_free(sc->bge_dmatag, &seg, rseg);
   2516 		return;
   2517 	}
   2518 	DPRINTFN(5, ("bus_dmamem_load\n"));
   2519 	if (bus_dmamap_load(sc->bge_dmatag, sc->bge_ring_map, kva,
   2520 			    sizeof(struct bge_ring_data), NULL,
   2521 			    BUS_DMA_NOWAIT)) {
   2522 		bus_dmamap_destroy(sc->bge_dmatag, sc->bge_ring_map);
   2523 		bus_dmamem_unmap(sc->bge_dmatag, kva,
   2524 				 sizeof(struct bge_ring_data));
   2525 		bus_dmamem_free(sc->bge_dmatag, &seg, rseg);
   2526 		return;
   2527 	}
   2528 
   2529 	DPRINTFN(5, ("bzero\n"));
   2530 	sc->bge_rdata = (struct bge_ring_data *)kva;
   2531 
   2532 	memset(sc->bge_rdata, 0, sizeof(struct bge_ring_data));
   2533 
   2534 	/* Try to allocate memory for jumbo buffers. */
   2535 	if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) {
   2536 		if (bge_alloc_jumbo_mem(sc)) {
   2537 			aprint_error("%s: jumbo buffer allocation failed\n",
   2538 			    sc->bge_dev.dv_xname);
   2539 		} else
   2540 			sc->ethercom.ec_capabilities |= ETHERCAP_JUMBO_MTU;
   2541 	}
   2542 
   2543 	/* Set default tuneable values. */
   2544 	sc->bge_stat_ticks = BGE_TICKS_PER_SEC;
   2545 	sc->bge_rx_coal_ticks = 150;
   2546 	sc->bge_rx_max_coal_bds = 64;
   2547 #ifdef ORIG_WPAUL_VALUES
   2548 	sc->bge_tx_coal_ticks = 150;
   2549 	sc->bge_tx_max_coal_bds = 128;
   2550 #else
   2551 	sc->bge_tx_coal_ticks = 300;
   2552 	sc->bge_tx_max_coal_bds = 400;
   2553 #endif
   2554 	if (sc->bge_quirks & BGE_QUIRK_5705_CORE) {
   2555 		sc->bge_tx_coal_ticks = (12 * 5);
   2556 		sc->bge_rx_max_coal_bds = (12 * 5);
   2557 			aprint_verbose("%s: setting short Tx thresholds\n",
   2558 			    sc->bge_dev.dv_xname);
   2559 	}
   2560 
   2561 	/* Set up ifnet structure */
   2562 	ifp = &sc->ethercom.ec_if;
   2563 	ifp->if_softc = sc;
   2564 	ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
   2565 	ifp->if_ioctl = bge_ioctl;
   2566 	ifp->if_start = bge_start;
   2567 	ifp->if_init = bge_init;
   2568 	ifp->if_watchdog = bge_watchdog;
   2569 	IFQ_SET_MAXLEN(&ifp->if_snd, max(BGE_TX_RING_CNT - 1, IFQ_MAXLEN));
   2570 	IFQ_SET_READY(&ifp->if_snd);
   2571 	DPRINTFN(5, ("strcpy if_xname\n"));
   2572 	strcpy(ifp->if_xname, sc->bge_dev.dv_xname);
   2573 
   2574 	if ((sc->bge_quirks & BGE_QUIRK_CSUM_BROKEN) == 0)
   2575 		sc->ethercom.ec_if.if_capabilities |=
   2576 		    IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx |
   2577 		    IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx |
   2578 		    IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx;
   2579 	sc->ethercom.ec_capabilities |=
   2580 	    ETHERCAP_VLAN_HWTAGGING | ETHERCAP_VLAN_MTU;
   2581 
   2582 	if (sc->bge_pcie)
   2583 		sc->ethercom.ec_if.if_capabilities |= IFCAP_TSOv4;
   2584 
   2585 	/*
   2586 	 * Do MII setup.
   2587 	 */
   2588 	DPRINTFN(5, ("mii setup\n"));
   2589 	sc->bge_mii.mii_ifp = ifp;
   2590 	sc->bge_mii.mii_readreg = bge_miibus_readreg;
   2591 	sc->bge_mii.mii_writereg = bge_miibus_writereg;
   2592 	sc->bge_mii.mii_statchg = bge_miibus_statchg;
   2593 
   2594 	/*
   2595 	 * Figure out what sort of media we have by checking the
   2596 	 * hardware config word in the first 32k of NIC internal memory,
   2597 	 * or fall back to the config word in the EEPROM. Note: on some BCM5700
   2598 	 * cards, this value appears to be unset. If that's the
   2599 	 * case, we have to rely on identifying the NIC by its PCI
   2600 	 * subsystem ID, as we do below for the SysKonnect SK-9D41.
   2601 	 */
   2602 	if (bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_SIG) == BGE_MAGIC_NUMBER) {
   2603 		hwcfg = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_NICCFG);
   2604 	} else {
   2605 		bge_read_eeprom(sc, (void *)&hwcfg,
   2606 		    BGE_EE_HWCFG_OFFSET, sizeof(hwcfg));
   2607 		hwcfg = be32toh(hwcfg);
   2608 	}
   2609 	if ((hwcfg & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER)
   2610 		sc->bge_tbi = 1;
   2611 
   2612 	/* The SysKonnect SK-9D41 is a 1000baseSX card. */
   2613 	if ((pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_SUBSYS) >> 16) ==
   2614 	    SK_SUBSYSID_9D41)
   2615 		sc->bge_tbi = 1;
   2616 
   2617 	if (sc->bge_tbi) {
   2618 		ifmedia_init(&sc->bge_ifmedia, IFM_IMASK, bge_ifmedia_upd,
   2619 		    bge_ifmedia_sts);
   2620 		ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL);
   2621 		ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_1000_SX|IFM_FDX,
   2622 			    0, NULL);
   2623 		ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL);
   2624 		ifmedia_set(&sc->bge_ifmedia, IFM_ETHER|IFM_AUTO);
   2625 	} else {
   2626 		/*
   2627 		 * Do transceiver setup.
   2628 		 */
   2629 		ifmedia_init(&sc->bge_mii.mii_media, 0, bge_ifmedia_upd,
   2630 			     bge_ifmedia_sts);
   2631 		mii_attach(&sc->bge_dev, &sc->bge_mii, 0xffffffff,
   2632 			   MII_PHY_ANY, MII_OFFSET_ANY,
   2633 			   MIIF_FORCEANEG|MIIF_DOPAUSE);
   2634 
   2635 		if (LIST_FIRST(&sc->bge_mii.mii_phys) == NULL) {
   2636 			printf("%s: no PHY found!\n", sc->bge_dev.dv_xname);
   2637 			ifmedia_add(&sc->bge_mii.mii_media,
   2638 				    IFM_ETHER|IFM_MANUAL, 0, NULL);
   2639 			ifmedia_set(&sc->bge_mii.mii_media,
   2640 				    IFM_ETHER|IFM_MANUAL);
   2641 		} else
   2642 			ifmedia_set(&sc->bge_mii.mii_media,
   2643 				    IFM_ETHER|IFM_AUTO);
   2644 	}
   2645 
   2646 	/*
   2647 	 * When using the BCM5701 in PCI-X mode, data corruption has
   2648 	 * been observed in the first few bytes of some received packets.
   2649 	 * Aligning the packet buffer in memory eliminates the corruption.
   2650 	 * Unfortunately, this misaligns the packet payloads.  On platforms
   2651 	 * which do not support unaligned accesses, we will realign the
   2652 	 * payloads by copying the received packets.
   2653 	 */
   2654 	if (sc->bge_quirks & BGE_QUIRK_PCIX_DMA_ALIGN_BUG) {
   2655 		/* If in PCI-X mode, work around the alignment bug. */
   2656 		if ((pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_PCISTATE) &
   2657                     (BGE_PCISTATE_PCI_BUSMODE | BGE_PCISTATE_PCI_BUSSPEED)) ==
   2658                          BGE_PCISTATE_PCI_BUSSPEED)
   2659 		sc->bge_rx_alignment_bug = 1;
   2660         }
   2661 
   2662 	/*
   2663 	 * Call MI attach routine.
   2664 	 */
   2665 	DPRINTFN(5, ("if_attach\n"));
   2666 	if_attach(ifp);
   2667 	DPRINTFN(5, ("ether_ifattach\n"));
   2668 	ether_ifattach(ifp, eaddr);
   2669 #ifdef BGE_EVENT_COUNTERS
   2670 	/*
   2671 	 * Attach event counters.
   2672 	 */
   2673 	evcnt_attach_dynamic(&sc->bge_ev_intr, EVCNT_TYPE_INTR,
   2674 	    NULL, sc->bge_dev.dv_xname, "intr");
   2675 	evcnt_attach_dynamic(&sc->bge_ev_tx_xoff, EVCNT_TYPE_MISC,
   2676 	    NULL, sc->bge_dev.dv_xname, "tx_xoff");
   2677 	evcnt_attach_dynamic(&sc->bge_ev_tx_xon, EVCNT_TYPE_MISC,
   2678 	    NULL, sc->bge_dev.dv_xname, "tx_xon");
   2679 	evcnt_attach_dynamic(&sc->bge_ev_rx_xoff, EVCNT_TYPE_MISC,
   2680 	    NULL, sc->bge_dev.dv_xname, "rx_xoff");
   2681 	evcnt_attach_dynamic(&sc->bge_ev_rx_xon, EVCNT_TYPE_MISC,
   2682 	    NULL, sc->bge_dev.dv_xname, "rx_xon");
   2683 	evcnt_attach_dynamic(&sc->bge_ev_rx_macctl, EVCNT_TYPE_MISC,
   2684 	    NULL, sc->bge_dev.dv_xname, "rx_macctl");
   2685 	evcnt_attach_dynamic(&sc->bge_ev_xoffentered, EVCNT_TYPE_MISC,
   2686 	    NULL, sc->bge_dev.dv_xname, "xoffentered");
   2687 #endif /* BGE_EVENT_COUNTERS */
   2688 	DPRINTFN(5, ("callout_init\n"));
   2689 	callout_init(&sc->bge_timeout);
   2690 
   2691 	sc->bge_powerhook = powerhook_establish(sc->bge_dev.dv_xname,
   2692 	    bge_powerhook, sc);
   2693 	if (sc->bge_powerhook == NULL)
   2694 		printf("%s: WARNING: unable to establish PCI power hook\n",
   2695 		    sc->bge_dev.dv_xname);
   2696 }
   2697 
   2698 static void
   2699 bge_release_resources(struct bge_softc *sc)
   2700 {
   2701 	if (sc->bge_vpd_prodname != NULL)
   2702 		free(sc->bge_vpd_prodname, M_DEVBUF);
   2703 
   2704 	if (sc->bge_vpd_readonly != NULL)
   2705 		free(sc->bge_vpd_readonly, M_DEVBUF);
   2706 }
   2707 
   2708 static void
   2709 bge_reset(struct bge_softc *sc)
   2710 {
   2711 	struct pci_attach_args *pa = &sc->bge_pa;
   2712 	u_int32_t cachesize, command, pcistate, new_pcistate;
   2713 	int i, val;
   2714 
   2715 	/* Save some important PCI state. */
   2716 	cachesize = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_CACHESZ);
   2717 	command = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_CMD);
   2718 	pcistate = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_PCISTATE);
   2719 
   2720 	pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_MISC_CTL,
   2721 	    BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR|
   2722 	    BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_PCISTATE_RW);
   2723 
   2724 	/*
   2725 	 * Disable the firmware fastboot feature on 5752 ASIC
   2726 	 * to avoid firmware timeout.
   2727 	 */
   2728 	if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5752)
   2729 		CSR_WRITE_4(sc, BGE_FASTBOOT_PC, 0);
   2730 
   2731 	val = BGE_MISCCFG_RESET_CORE_CLOCKS | (65<<1);
   2732 	/*
   2733 	 * XXX: from FreeBSD/Linux; no documentation
   2734 	 */
   2735 	if (sc->bge_pcie) {
   2736 		if (CSR_READ_4(sc, BGE_PCIE_CTL1) == 0x60)
   2737 			CSR_WRITE_4(sc, BGE_PCIE_CTL1, 0x20);
   2738 		if (sc->bge_chipid != BGE_CHIPID_BCM5750_A0) {
   2739 			/* No idea what that actually means */
   2740 			CSR_WRITE_4(sc, BGE_MISC_CFG, 1 << 29);
   2741 			val |= (1<<29);
   2742 		}
   2743 	}
   2744 
   2745 	/* Issue global reset */
   2746 	bge_writereg_ind(sc, BGE_MISC_CFG, val);
   2747 
   2748 	DELAY(1000);
   2749 
   2750 	/*
   2751 	 * XXX: from FreeBSD/Linux; no documentation
   2752 	 */
   2753 	if (sc->bge_pcie) {
   2754 		if (sc->bge_chipid == BGE_CHIPID_BCM5750_A0) {
   2755 			pcireg_t reg;
   2756 
   2757 			DELAY(500000);
   2758 			/* XXX: Magic Numbers */
   2759 			reg = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_UNKNOWN0);
   2760 			pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_UNKNOWN0,
   2761 			    reg | (1 << 15));
   2762 		}
   2763 		/*
   2764 		 * XXX: Magic Numbers.
   2765 		 * Sets maximal PCI-e payload and clears any PCI-e errors.
   2766 		 * Should be replaced with references to PCI config-space
   2767 		 * capability block for PCI-Express.
   2768 		 */
   2769 		pci_conf_write(pa->pa_pc, pa->pa_tag,
   2770 		    BGE_PCI_CONF_DEV_CTRL, 0xf5000);
   2771 
   2772 	}
   2773 
   2774 	/* Reset some of the PCI state that got zapped by reset */
   2775 	pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_MISC_CTL,
   2776 	    BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR|
   2777 	    BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_PCISTATE_RW);
   2778 	pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_CMD, command);
   2779 	pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_CACHESZ, cachesize);
   2780 	bge_writereg_ind(sc, BGE_MISC_CFG, (65 << 1));
   2781 
   2782 	/* Enable memory arbiter. */
   2783 	{
   2784 		uint32_t marbmode = 0;
   2785 		if (BGE_IS_5714_FAMILY(sc)) {
   2786 			marbmode = CSR_READ_4(sc, BGE_MARB_MODE);
   2787 		}
   2788  		CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE | marbmode);
   2789 	}
   2790 
   2791 	/*
   2792 	 * Prevent PXE restart: write a magic number to the
   2793 	 * general communications memory at 0xB50.
   2794 	 */
   2795 	bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM, BGE_MAGIC_NUMBER);
   2796 
   2797 	/*
   2798 	 * Poll the value location we just wrote until
   2799 	 * we see the 1's complement of the magic number.
   2800 	 * This indicates that the firmware initialization
   2801 	 * is complete.
   2802 	 */
   2803 	for (i = 0; i < BGE_TIMEOUT; i++) {
   2804 		val = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM);
   2805 		if (val == ~BGE_MAGIC_NUMBER)
   2806 			break;
   2807 		DELAY(1000);
   2808 	}
   2809 
   2810 	if (i >= BGE_TIMEOUT) {
   2811 		printf("%s: firmware handshake timed out, val = %x\n",
   2812 		    sc->bge_dev.dv_xname, val);
   2813 		/*
   2814 		 * XXX: occasionally fired on bcm5721, but without
   2815 		 * apparent harm.  For now, keep going if we timeout
   2816 		 * against PCI-E devices.
   2817 		 */
   2818 		 if (!sc->bge_pcie)
   2819 		  return;
   2820 	}
   2821 
   2822 	/*
   2823 	 * XXX Wait for the value of the PCISTATE register to
   2824 	 * return to its original pre-reset state. This is a
   2825 	 * fairly good indicator of reset completion. If we don't
   2826 	 * wait for the reset to fully complete, trying to read
   2827 	 * from the device's non-PCI registers may yield garbage
   2828 	 * results.
   2829 	 */
   2830 	for (i = 0; i < BGE_TIMEOUT; i++) {
   2831 		new_pcistate = pci_conf_read(pa->pa_pc, pa->pa_tag,
   2832 		    BGE_PCI_PCISTATE);
   2833 		if ((new_pcistate & ~BGE_PCISTATE_RESERVED) ==
   2834 		    (pcistate & ~BGE_PCISTATE_RESERVED))
   2835 			break;
   2836 		DELAY(10);
   2837 	}
   2838 	if ((new_pcistate & ~BGE_PCISTATE_RESERVED) !=
   2839 	    (pcistate & ~BGE_PCISTATE_RESERVED)) {
   2840 		printf("%s: pcistate failed to revert\n",
   2841 		    sc->bge_dev.dv_xname);
   2842 	}
   2843 
   2844 	/* XXX: from FreeBSD/Linux; no documentation */
   2845 	if (sc->bge_pcie && sc->bge_chipid != BGE_CHIPID_BCM5750_A0)
   2846 		CSR_WRITE_4(sc, BGE_PCIE_CTL0, CSR_READ_4(sc, BGE_PCIE_CTL0) | (1<<25));
   2847 
   2848 	/* Enable memory arbiter. */
   2849 	/* XXX why do this twice? */
   2850 	{
   2851 		uint32_t marbmode = 0;
   2852 		if (BGE_IS_5714_FAMILY(sc)) {
   2853 			marbmode = CSR_READ_4(sc, BGE_MARB_MODE);
   2854 		}
   2855  		CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE | marbmode);
   2856 	}
   2857 
   2858 	/* Fix up byte swapping */
   2859 	CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS);
   2860 
   2861 	CSR_WRITE_4(sc, BGE_MAC_MODE, 0);
   2862 
   2863 	DELAY(10000);
   2864 }
   2865 
   2866 /*
   2867  * Frame reception handling. This is called if there's a frame
   2868  * on the receive return list.
   2869  *
   2870  * Note: we have to be able to handle two possibilities here:
   2871  * 1) the frame is from the jumbo recieve ring
   2872  * 2) the frame is from the standard receive ring
   2873  */
   2874 
   2875 static void
   2876 bge_rxeof(struct bge_softc *sc)
   2877 {
   2878 	struct ifnet *ifp;
   2879 	int stdcnt = 0, jumbocnt = 0;
   2880 	bus_dmamap_t dmamap;
   2881 	bus_addr_t offset, toff;
   2882 	bus_size_t tlen;
   2883 	int tosync;
   2884 
   2885 	ifp = &sc->ethercom.ec_if;
   2886 
   2887 	bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map,
   2888 	    offsetof(struct bge_ring_data, bge_status_block),
   2889 	    sizeof (struct bge_status_block),
   2890 	    BUS_DMASYNC_POSTREAD);
   2891 
   2892 	offset = offsetof(struct bge_ring_data, bge_rx_return_ring);
   2893 	tosync = sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx -
   2894 	    sc->bge_rx_saved_considx;
   2895 
   2896 	toff = offset + (sc->bge_rx_saved_considx * sizeof (struct bge_rx_bd));
   2897 
   2898 	if (tosync < 0) {
   2899 		tlen = (sc->bge_return_ring_cnt - sc->bge_rx_saved_considx) *
   2900 		    sizeof (struct bge_rx_bd);
   2901 		bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map,
   2902 		    toff, tlen, BUS_DMASYNC_POSTREAD);
   2903 		tosync = -tosync;
   2904 	}
   2905 
   2906 	bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map,
   2907 	    offset, tosync * sizeof (struct bge_rx_bd),
   2908 	    BUS_DMASYNC_POSTREAD);
   2909 
   2910 	while(sc->bge_rx_saved_considx !=
   2911 	    sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx) {
   2912 		struct bge_rx_bd	*cur_rx;
   2913 		u_int32_t		rxidx;
   2914 		struct mbuf		*m = NULL;
   2915 
   2916 		cur_rx = &sc->bge_rdata->
   2917 			bge_rx_return_ring[sc->bge_rx_saved_considx];
   2918 
   2919 		rxidx = cur_rx->bge_idx;
   2920 		BGE_INC(sc->bge_rx_saved_considx, sc->bge_return_ring_cnt);
   2921 
   2922 		if (cur_rx->bge_flags & BGE_RXBDFLAG_JUMBO_RING) {
   2923 			BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT);
   2924 			m = sc->bge_cdata.bge_rx_jumbo_chain[rxidx];
   2925 			sc->bge_cdata.bge_rx_jumbo_chain[rxidx] = NULL;
   2926 			jumbocnt++;
   2927 			bus_dmamap_sync(sc->bge_dmatag,
   2928 			    sc->bge_cdata.bge_rx_jumbo_map,
   2929 			    mtod(m, char *) - (char *)sc->bge_cdata.bge_jumbo_buf,
   2930 			    BGE_JLEN, BUS_DMASYNC_POSTREAD);
   2931 			if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) {
   2932 				ifp->if_ierrors++;
   2933 				bge_newbuf_jumbo(sc, sc->bge_jumbo, m);
   2934 				continue;
   2935 			}
   2936 			if (bge_newbuf_jumbo(sc, sc->bge_jumbo,
   2937 					     NULL)== ENOBUFS) {
   2938 				ifp->if_ierrors++;
   2939 				bge_newbuf_jumbo(sc, sc->bge_jumbo, m);
   2940 				continue;
   2941 			}
   2942 		} else {
   2943 			BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT);
   2944 			m = sc->bge_cdata.bge_rx_std_chain[rxidx];
   2945 
   2946 			sc->bge_cdata.bge_rx_std_chain[rxidx] = NULL;
   2947 			stdcnt++;
   2948 			dmamap = sc->bge_cdata.bge_rx_std_map[rxidx];
   2949 			sc->bge_cdata.bge_rx_std_map[rxidx] = 0;
   2950 			bus_dmamap_sync(sc->bge_dmatag, dmamap, 0,
   2951 			    dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD);
   2952 			bus_dmamap_unload(sc->bge_dmatag, dmamap);
   2953 			if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) {
   2954 				ifp->if_ierrors++;
   2955 				bge_newbuf_std(sc, sc->bge_std, m, dmamap);
   2956 				continue;
   2957 			}
   2958 			if (bge_newbuf_std(sc, sc->bge_std,
   2959 			    NULL, dmamap) == ENOBUFS) {
   2960 				ifp->if_ierrors++;
   2961 				bge_newbuf_std(sc, sc->bge_std, m, dmamap);
   2962 				continue;
   2963 			}
   2964 		}
   2965 
   2966 		ifp->if_ipackets++;
   2967 #ifndef __NO_STRICT_ALIGNMENT
   2968                 /*
   2969                  * XXX: if the 5701 PCIX-Rx-DMA workaround is in effect,
   2970                  * the Rx buffer has the layer-2 header unaligned.
   2971                  * If our CPU requires alignment, re-align by copying.
   2972                  */
   2973 		if (sc->bge_rx_alignment_bug) {
   2974 			memmove(mtod(m, void *) + ETHER_ALIGN, m->m_data,
   2975                                 cur_rx->bge_len);
   2976 			m->m_data += ETHER_ALIGN;
   2977 		}
   2978 #endif
   2979 
   2980 		m->m_pkthdr.len = m->m_len = cur_rx->bge_len - ETHER_CRC_LEN;
   2981 		m->m_pkthdr.rcvif = ifp;
   2982 
   2983 #if NBPFILTER > 0
   2984 		/*
   2985 		 * Handle BPF listeners. Let the BPF user see the packet.
   2986 		 */
   2987 		if (ifp->if_bpf)
   2988 			bpf_mtap(ifp->if_bpf, m);
   2989 #endif
   2990 
   2991 		m->m_pkthdr.csum_flags = M_CSUM_IPv4;
   2992 
   2993 		if ((cur_rx->bge_ip_csum ^ 0xffff) != 0)
   2994 			m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD;
   2995 		/*
   2996 		 * Rx transport checksum-offload may also
   2997 		 * have bugs with packets which, when transmitted,
   2998 		 * were `runts' requiring padding.
   2999 		 */
   3000 		if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM &&
   3001 		    (/* (sc->_bge_quirks & BGE_QUIRK_SHORT_CKSUM_BUG) == 0 ||*/
   3002 		     m->m_pkthdr.len >= ETHER_MIN_NOPAD)) {
   3003 			m->m_pkthdr.csum_data =
   3004 			    cur_rx->bge_tcp_udp_csum;
   3005 			m->m_pkthdr.csum_flags |=
   3006 			    (M_CSUM_TCPv4|M_CSUM_UDPv4|
   3007 			     M_CSUM_DATA|M_CSUM_NO_PSEUDOHDR);
   3008 		}
   3009 
   3010 		/*
   3011 		 * If we received a packet with a vlan tag, pass it
   3012 		 * to vlan_input() instead of ether_input().
   3013 		 */
   3014 		if (cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG)
   3015 			VLAN_INPUT_TAG(ifp, m, cur_rx->bge_vlan_tag, continue);
   3016 
   3017 		(*ifp->if_input)(ifp, m);
   3018 	}
   3019 
   3020 	CSR_WRITE_4(sc, BGE_MBX_RX_CONS0_LO, sc->bge_rx_saved_considx);
   3021 	if (stdcnt)
   3022 		CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std);
   3023 	if (jumbocnt)
   3024 		CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo);
   3025 }
   3026 
   3027 static void
   3028 bge_txeof(struct bge_softc *sc)
   3029 {
   3030 	struct bge_tx_bd *cur_tx = NULL;
   3031 	struct ifnet *ifp;
   3032 	struct txdmamap_pool_entry *dma;
   3033 	bus_addr_t offset, toff;
   3034 	bus_size_t tlen;
   3035 	int tosync;
   3036 	struct mbuf *m;
   3037 
   3038 	ifp = &sc->ethercom.ec_if;
   3039 
   3040 	bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map,
   3041 	    offsetof(struct bge_ring_data, bge_status_block),
   3042 	    sizeof (struct bge_status_block),
   3043 	    BUS_DMASYNC_POSTREAD);
   3044 
   3045 	offset = offsetof(struct bge_ring_data, bge_tx_ring);
   3046 	tosync = sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx -
   3047 	    sc->bge_tx_saved_considx;
   3048 
   3049 	toff = offset + (sc->bge_tx_saved_considx * sizeof (struct bge_tx_bd));
   3050 
   3051 	if (tosync < 0) {
   3052 		tlen = (BGE_TX_RING_CNT - sc->bge_tx_saved_considx) *
   3053 		    sizeof (struct bge_tx_bd);
   3054 		bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map,
   3055 		    toff, tlen, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
   3056 		tosync = -tosync;
   3057 	}
   3058 
   3059 	bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map,
   3060 	    offset, tosync * sizeof (struct bge_tx_bd),
   3061 	    BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
   3062 
   3063 	/*
   3064 	 * Go through our tx ring and free mbufs for those
   3065 	 * frames that have been sent.
   3066 	 */
   3067 	while (sc->bge_tx_saved_considx !=
   3068 	    sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx) {
   3069 		u_int32_t		idx = 0;
   3070 
   3071 		idx = sc->bge_tx_saved_considx;
   3072 		cur_tx = &sc->bge_rdata->bge_tx_ring[idx];
   3073 		if (cur_tx->bge_flags & BGE_TXBDFLAG_END)
   3074 			ifp->if_opackets++;
   3075 		m = sc->bge_cdata.bge_tx_chain[idx];
   3076 		if (m != NULL) {
   3077 			sc->bge_cdata.bge_tx_chain[idx] = NULL;
   3078 			dma = sc->txdma[idx];
   3079 			bus_dmamap_sync(sc->bge_dmatag, dma->dmamap, 0,
   3080 			    dma->dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE);
   3081 			bus_dmamap_unload(sc->bge_dmatag, dma->dmamap);
   3082 			SLIST_INSERT_HEAD(&sc->txdma_list, dma, link);
   3083 			sc->txdma[idx] = NULL;
   3084 
   3085 			m_freem(m);
   3086 		}
   3087 		sc->bge_txcnt--;
   3088 		BGE_INC(sc->bge_tx_saved_considx, BGE_TX_RING_CNT);
   3089 		ifp->if_timer = 0;
   3090 	}
   3091 
   3092 	if (cur_tx != NULL)
   3093 		ifp->if_flags &= ~IFF_OACTIVE;
   3094 }
   3095 
   3096 static int
   3097 bge_intr(void *xsc)
   3098 {
   3099 	struct bge_softc *sc;
   3100 	struct ifnet *ifp;
   3101 
   3102 	sc = xsc;
   3103 	ifp = &sc->ethercom.ec_if;
   3104 
   3105 #ifdef notdef
   3106 	/* Avoid this for now -- checking this register is expensive. */
   3107 	/* Make sure this is really our interrupt. */
   3108 	if (!(CSR_READ_4(sc, BGE_MISC_LOCAL_CTL) & BGE_MLC_INTR_STATE))
   3109 		return (0);
   3110 #endif
   3111 	/* Ack interrupt and stop others from occuring. */
   3112 	CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 1);
   3113 
   3114 	BGE_EVCNT_INCR(sc->bge_ev_intr);
   3115 
   3116 	/*
   3117 	 * Process link state changes.
   3118 	 * Grrr. The link status word in the status block does
   3119 	 * not work correctly on the BCM5700 rev AX and BX chips,
   3120 	 * according to all available information. Hence, we have
   3121 	 * to enable MII interrupts in order to properly obtain
   3122 	 * async link changes. Unfortunately, this also means that
   3123 	 * we have to read the MAC status register to detect link
   3124 	 * changes, thereby adding an additional register access to
   3125 	 * the interrupt handler.
   3126 	 */
   3127 
   3128 	if (sc->bge_quirks & BGE_QUIRK_LINK_STATE_BROKEN) {
   3129 		u_int32_t		status;
   3130 
   3131 		status = CSR_READ_4(sc, BGE_MAC_STS);
   3132 		if (status & BGE_MACSTAT_MI_INTERRUPT) {
   3133 			sc->bge_link = 0;
   3134 			callout_stop(&sc->bge_timeout);
   3135 			bge_tick(sc);
   3136 			/* Clear the interrupt */
   3137 			CSR_WRITE_4(sc, BGE_MAC_EVT_ENB,
   3138 			    BGE_EVTENB_MI_INTERRUPT);
   3139 			bge_miibus_readreg(&sc->bge_dev, 1, BRGPHY_MII_ISR);
   3140 			bge_miibus_writereg(&sc->bge_dev, 1, BRGPHY_MII_IMR,
   3141 			    BRGPHY_INTRS);
   3142 		}
   3143 	} else {
   3144 		if (sc->bge_rdata->bge_status_block.bge_status &
   3145 		    BGE_STATFLAG_LINKSTATE_CHANGED) {
   3146 			sc->bge_link = 0;
   3147 			callout_stop(&sc->bge_timeout);
   3148 			bge_tick(sc);
   3149 			/* Clear the interrupt */
   3150 			CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED|
   3151 			    BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE|
   3152 			    BGE_MACSTAT_LINK_CHANGED);
   3153 		}
   3154 	}
   3155 
   3156 	if (ifp->if_flags & IFF_RUNNING) {
   3157 		/* Check RX return ring producer/consumer */
   3158 		bge_rxeof(sc);
   3159 
   3160 		/* Check TX ring producer/consumer */
   3161 		bge_txeof(sc);
   3162 	}
   3163 
   3164 	if (sc->bge_pending_rxintr_change) {
   3165 		uint32_t rx_ticks = sc->bge_rx_coal_ticks;
   3166 		uint32_t rx_bds = sc->bge_rx_max_coal_bds;
   3167 		uint32_t junk;
   3168 
   3169 		CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, rx_ticks);
   3170 		DELAY(10);
   3171 		junk = CSR_READ_4(sc, BGE_HCC_RX_COAL_TICKS);
   3172 
   3173 		CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, rx_bds);
   3174 		DELAY(10);
   3175 		junk = CSR_READ_4(sc, BGE_HCC_RX_MAX_COAL_BDS);
   3176 
   3177 		sc->bge_pending_rxintr_change = 0;
   3178 	}
   3179 	bge_handle_events(sc);
   3180 
   3181 	/* Re-enable interrupts. */
   3182 	CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 0);
   3183 
   3184 	if (ifp->if_flags & IFF_RUNNING && !IFQ_IS_EMPTY(&ifp->if_snd))
   3185 		bge_start(ifp);
   3186 
   3187 	return (1);
   3188 }
   3189 
   3190 static void
   3191 bge_tick(void *xsc)
   3192 {
   3193 	struct bge_softc *sc = xsc;
   3194 	struct mii_data *mii = &sc->bge_mii;
   3195 	struct ifmedia *ifm = NULL;
   3196 	struct ifnet *ifp = &sc->ethercom.ec_if;
   3197 	int s;
   3198 
   3199 	s = splnet();
   3200 
   3201 	bge_stats_update(sc);
   3202 	callout_reset(&sc->bge_timeout, hz, bge_tick, sc);
   3203 	if (sc->bge_link) {
   3204 		splx(s);
   3205 		return;
   3206 	}
   3207 
   3208 	if (sc->bge_tbi) {
   3209 		ifm = &sc->bge_ifmedia;
   3210 		if (CSR_READ_4(sc, BGE_MAC_STS) &
   3211 		    BGE_MACSTAT_TBI_PCS_SYNCHED) {
   3212 			sc->bge_link++;
   3213 			CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF);
   3214 			if (!IFQ_IS_EMPTY(&ifp->if_snd))
   3215 				bge_start(ifp);
   3216 		}
   3217 		splx(s);
   3218 		return;
   3219 	}
   3220 
   3221 	mii_tick(mii);
   3222 
   3223 	if (!sc->bge_link && mii->mii_media_status & IFM_ACTIVE &&
   3224 	    IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
   3225 		sc->bge_link++;
   3226 		if (!IFQ_IS_EMPTY(&ifp->if_snd))
   3227 			bge_start(ifp);
   3228 	}
   3229 
   3230 	splx(s);
   3231 }
   3232 
   3233 static void
   3234 bge_stats_update(struct bge_softc *sc)
   3235 {
   3236 	struct ifnet *ifp = &sc->ethercom.ec_if;
   3237 	bus_size_t stats = BGE_MEMWIN_START + BGE_STATS_BLOCK;
   3238 	bus_size_t rstats = BGE_RX_STATS;
   3239 
   3240 #define READ_RSTAT(sc, stats, stat) \
   3241 	  CSR_READ_4(sc, stats + offsetof(struct bge_mac_stats_regs, stat))
   3242 
   3243 	if (sc->bge_quirks & BGE_QUIRK_5705_CORE) {
   3244 		ifp->if_collisions +=
   3245 		    READ_RSTAT(sc, rstats, dot3StatsSingleCollisionFrames) +
   3246 		    READ_RSTAT(sc, rstats, dot3StatsMultipleCollisionFrames) +
   3247 		    READ_RSTAT(sc, rstats, dot3StatsExcessiveCollisions) +
   3248 		    READ_RSTAT(sc, rstats, dot3StatsLateCollisions);
   3249 
   3250 		BGE_EVCNT_ADD(sc->bge_ev_tx_xoff,
   3251 			      READ_RSTAT(sc, rstats, outXoffSent));
   3252 		BGE_EVCNT_ADD(sc->bge_ev_tx_xon,
   3253 			      READ_RSTAT(sc, rstats, outXonSent));
   3254 		BGE_EVCNT_ADD(sc->bge_ev_rx_xoff,
   3255 			      READ_RSTAT(sc, rstats, xoffPauseFramesReceived));
   3256 		BGE_EVCNT_ADD(sc->bge_ev_rx_xon,
   3257 			      READ_RSTAT(sc, rstats, xonPauseFramesReceived));
   3258 		BGE_EVCNT_ADD(sc->bge_ev_rx_macctl,
   3259 			      READ_RSTAT(sc, rstats, macControlFramesReceived));
   3260 		BGE_EVCNT_ADD(sc->bge_ev_xoffentered,
   3261 			      READ_RSTAT(sc, rstats, xoffStateEntered));
   3262 		return;
   3263 	}
   3264 
   3265 #undef READ_RSTAT
   3266 #define READ_STAT(sc, stats, stat) \
   3267 	  CSR_READ_4(sc, stats + offsetof(struct bge_stats, stat))
   3268 
   3269 	ifp->if_collisions +=
   3270 	  (READ_STAT(sc, stats, dot3StatsSingleCollisionFrames.bge_addr_lo) +
   3271 	   READ_STAT(sc, stats, dot3StatsMultipleCollisionFrames.bge_addr_lo) +
   3272 	   READ_STAT(sc, stats, dot3StatsExcessiveCollisions.bge_addr_lo) +
   3273 	   READ_STAT(sc, stats, dot3StatsLateCollisions.bge_addr_lo)) -
   3274 	  ifp->if_collisions;
   3275 
   3276 	BGE_EVCNT_UPD(sc->bge_ev_tx_xoff,
   3277 		      READ_STAT(sc, stats, outXoffSent.bge_addr_lo));
   3278 	BGE_EVCNT_UPD(sc->bge_ev_tx_xon,
   3279 		      READ_STAT(sc, stats, outXonSent.bge_addr_lo));
   3280 	BGE_EVCNT_UPD(sc->bge_ev_rx_xoff,
   3281 		      READ_STAT(sc, stats,
   3282 		      		xoffPauseFramesReceived.bge_addr_lo));
   3283 	BGE_EVCNT_UPD(sc->bge_ev_rx_xon,
   3284 		      READ_STAT(sc, stats, xonPauseFramesReceived.bge_addr_lo));
   3285 	BGE_EVCNT_UPD(sc->bge_ev_rx_macctl,
   3286 		      READ_STAT(sc, stats,
   3287 		      		macControlFramesReceived.bge_addr_lo));
   3288 	BGE_EVCNT_UPD(sc->bge_ev_xoffentered,
   3289 		      READ_STAT(sc, stats, xoffStateEntered.bge_addr_lo));
   3290 
   3291 #undef READ_STAT
   3292 
   3293 #ifdef notdef
   3294 	ifp->if_collisions +=
   3295 	   (sc->bge_rdata->bge_info.bge_stats.dot3StatsSingleCollisionFrames +
   3296 	   sc->bge_rdata->bge_info.bge_stats.dot3StatsMultipleCollisionFrames +
   3297 	   sc->bge_rdata->bge_info.bge_stats.dot3StatsExcessiveCollisions +
   3298 	   sc->bge_rdata->bge_info.bge_stats.dot3StatsLateCollisions) -
   3299 	   ifp->if_collisions;
   3300 #endif
   3301 }
   3302 
   3303 /*
   3304  * Pad outbound frame to ETHER_MIN_NOPAD for an unusual reason.
   3305  * The bge hardware will pad out Tx runts to ETHER_MIN_NOPAD,
   3306  * but when such padded frames employ the  bge IP/TCP checksum offload,
   3307  * the hardware checksum assist gives incorrect results (possibly
   3308  * from incorporating its own padding into the UDP/TCP checksum; who knows).
   3309  * If we pad such runts with zeros, the onboard checksum comes out correct.
   3310  */
   3311 static inline int
   3312 bge_cksum_pad(struct mbuf *pkt)
   3313 {
   3314 	struct mbuf *last = NULL;
   3315 	int padlen;
   3316 
   3317 	padlen = ETHER_MIN_NOPAD - pkt->m_pkthdr.len;
   3318 
   3319 	/* if there's only the packet-header and we can pad there, use it. */
   3320 	if (pkt->m_pkthdr.len == pkt->m_len &&
   3321 	    M_TRAILINGSPACE(pkt) >= padlen) {
   3322 		last = pkt;
   3323 	} else {
   3324 		/*
   3325 		 * Walk packet chain to find last mbuf. We will either
   3326 		 * pad there, or append a new mbuf and pad it
   3327 		 * (thus perhaps avoiding the bcm5700 dma-min bug).
   3328 		 */
   3329 		for (last = pkt; last->m_next != NULL; last = last->m_next) {
   3330 	      	       continue; /* do nothing */
   3331 		}
   3332 
   3333 		/* `last' now points to last in chain. */
   3334 		if (M_TRAILINGSPACE(last) < padlen) {
   3335 			/* Allocate new empty mbuf, pad it. Compact later. */
   3336 			struct mbuf *n;
   3337 			MGET(n, M_DONTWAIT, MT_DATA);
   3338 			n->m_len = 0;
   3339 			last->m_next = n;
   3340 			last = n;
   3341 		}
   3342 	}
   3343 
   3344 	KDASSERT(!M_READONLY(last));
   3345 	KDASSERT(M_TRAILINGSPACE(last) >= padlen);
   3346 
   3347 	/* Now zero the pad area, to avoid the bge cksum-assist bug */
   3348 	memset(mtod(last, char *) + last->m_len, 0, padlen);
   3349 	last->m_len += padlen;
   3350 	pkt->m_pkthdr.len += padlen;
   3351 	return 0;
   3352 }
   3353 
   3354 /*
   3355  * Compact outbound packets to avoid bug with DMA segments less than 8 bytes.
   3356  */
   3357 static inline int
   3358 bge_compact_dma_runt(struct mbuf *pkt)
   3359 {
   3360 	struct mbuf	*m, *prev;
   3361 	int 		totlen, prevlen;
   3362 
   3363 	prev = NULL;
   3364 	totlen = 0;
   3365 	prevlen = -1;
   3366 
   3367 	for (m = pkt; m != NULL; prev = m,m = m->m_next) {
   3368 		int mlen = m->m_len;
   3369 		int shortfall = 8 - mlen ;
   3370 
   3371 		totlen += mlen;
   3372 		if (mlen == 0) {
   3373 			continue;
   3374 		}
   3375 		if (mlen >= 8)
   3376 			continue;
   3377 
   3378 		/* If we get here, mbuf data is too small for DMA engine.
   3379 		 * Try to fix by shuffling data to prev or next in chain.
   3380 		 * If that fails, do a compacting deep-copy of the whole chain.
   3381 		 */
   3382 
   3383 		/* Internal frag. If fits in prev, copy it there. */
   3384 		if (prev && M_TRAILINGSPACE(prev) >= m->m_len) {
   3385 		  	memcpy(prev->m_data + prev->m_len, m->m_data, mlen);
   3386 			prev->m_len += mlen;
   3387 			m->m_len = 0;
   3388 			/* XXX stitch chain */
   3389 			prev->m_next = m_free(m);
   3390 			m = prev;
   3391 			continue;
   3392 		}
   3393 		else if (m->m_next != NULL &&
   3394 			     M_TRAILINGSPACE(m) >= shortfall &&
   3395 			     m->m_next->m_len >= (8 + shortfall)) {
   3396 		    /* m is writable and have enough data in next, pull up. */
   3397 
   3398 		  	memcpy(m->m_data + m->m_len, m->m_next->m_data,
   3399 			    shortfall);
   3400 			m->m_len += shortfall;
   3401 			m->m_next->m_len -= shortfall;
   3402 			m->m_next->m_data += shortfall;
   3403 		}
   3404 		else if (m->m_next == NULL || 1) {
   3405 		  	/* Got a runt at the very end of the packet.
   3406 			 * borrow data from the tail of the preceding mbuf and
   3407 			 * update its length in-place. (The original data is still
   3408 			 * valid, so we can do this even if prev is not writable.)
   3409 			 */
   3410 
   3411 			/* if we'd make prev a runt, just move all of its data. */
   3412 			KASSERT(prev != NULL /*, ("runt but null PREV")*/);
   3413 			KASSERT(prev->m_len >= 8 /*, ("runt prev")*/);
   3414 
   3415 			if ((prev->m_len - shortfall) < 8)
   3416 				shortfall = prev->m_len;
   3417 
   3418 #ifdef notyet	/* just do the safe slow thing for now */
   3419 			if (!M_READONLY(m)) {
   3420 				if (M_LEADINGSPACE(m) < shorfall) {
   3421 					void *m_dat;
   3422 					m_dat = (m->m_flags & M_PKTHDR) ?
   3423 					  m->m_pktdat : m->dat;
   3424 					memmove(m_dat, mtod(m, void*), m->m_len);
   3425 					m->m_data = m_dat;
   3426 				    }
   3427 			} else
   3428 #endif	/* just do the safe slow thing */
   3429 			{
   3430 				struct mbuf * n = NULL;
   3431 				int newprevlen = prev->m_len - shortfall;
   3432 
   3433 				MGET(n, M_NOWAIT, MT_DATA);
   3434 				if (n == NULL)
   3435 				   return ENOBUFS;
   3436 				KASSERT(m->m_len + shortfall < MLEN
   3437 					/*,
   3438 					  ("runt %d +prev %d too big\n", m->m_len, shortfall)*/);
   3439 
   3440 				/* first copy the data we're stealing from prev */
   3441 				memcpy(n->m_data, prev->m_data + newprevlen,
   3442 				    shortfall);
   3443 
   3444 				/* update prev->m_len accordingly */
   3445 				prev->m_len -= shortfall;
   3446 
   3447 				/* copy data from runt m */
   3448 				memcpy(n->m_data + shortfall, m->m_data,
   3449 				    m->m_len);
   3450 
   3451 				/* n holds what we stole from prev, plus m */
   3452 				n->m_len = shortfall + m->m_len;
   3453 
   3454 				/* stitch n into chain and free m */
   3455 				n->m_next = m->m_next;
   3456 				prev->m_next = n;
   3457 				/* KASSERT(m->m_next == NULL); */
   3458 				m->m_next = NULL;
   3459 				m_free(m);
   3460 				m = n;	/* for continuing loop */
   3461 			}
   3462 		}
   3463 		prevlen = m->m_len;
   3464 	}
   3465 	return 0;
   3466 }
   3467 
   3468 /*
   3469  * Encapsulate an mbuf chain in the tx ring  by coupling the mbuf data
   3470  * pointers to descriptors.
   3471  */
   3472 static int
   3473 bge_encap(struct bge_softc *sc, struct mbuf *m_head, u_int32_t *txidx)
   3474 {
   3475 	struct bge_tx_bd	*f = NULL;
   3476 	u_int32_t		frag, cur;
   3477 	u_int16_t		csum_flags = 0;
   3478 	u_int16_t		txbd_tso_flags = 0;
   3479 	struct txdmamap_pool_entry *dma;
   3480 	bus_dmamap_t dmamap;
   3481 	int			i = 0;
   3482 	struct m_tag		*mtag;
   3483 	int			use_tso, maxsegsize, error;
   3484 
   3485 	cur = frag = *txidx;
   3486 
   3487 	if (m_head->m_pkthdr.csum_flags) {
   3488 		if (m_head->m_pkthdr.csum_flags & M_CSUM_IPv4)
   3489 			csum_flags |= BGE_TXBDFLAG_IP_CSUM;
   3490 		if (m_head->m_pkthdr.csum_flags & (M_CSUM_TCPv4|M_CSUM_UDPv4))
   3491 			csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM;
   3492 	}
   3493 
   3494 	/*
   3495 	 * If we were asked to do an outboard checksum, and the NIC
   3496 	 * has the bug where it sometimes adds in the Ethernet padding,
   3497 	 * explicitly pad with zeros so the cksum will be correct either way.
   3498 	 * (For now, do this for all chip versions, until newer
   3499 	 * are confirmed to not require the workaround.)
   3500 	 */
   3501 	if ((csum_flags & BGE_TXBDFLAG_TCP_UDP_CSUM) == 0 ||
   3502 #ifdef notyet
   3503 	    (sc->bge_quirks & BGE_QUIRK_SHORT_CKSUM_BUG) == 0 ||
   3504 #endif
   3505 	    m_head->m_pkthdr.len >= ETHER_MIN_NOPAD)
   3506 		goto check_dma_bug;
   3507 
   3508 	if (bge_cksum_pad(m_head) != 0) {
   3509 	    return ENOBUFS;
   3510 	}
   3511 
   3512 check_dma_bug:
   3513 	if (!(sc->bge_quirks & BGE_QUIRK_5700_SMALLDMA))
   3514 		goto doit;
   3515 	/*
   3516 	 * bcm5700 Revision B silicon cannot handle DMA descriptors with
   3517 	 * less than eight bytes.  If we encounter a teeny mbuf
   3518 	 * at the end of a chain, we can pad.  Otherwise, copy.
   3519 	 */
   3520 	if (bge_compact_dma_runt(m_head) != 0)
   3521 		return ENOBUFS;
   3522 
   3523 doit:
   3524 	dma = SLIST_FIRST(&sc->txdma_list);
   3525 	if (dma == NULL)
   3526 		return ENOBUFS;
   3527 	dmamap = dma->dmamap;
   3528 
   3529 	/*
   3530 	 * Set up any necessary TSO state before we start packing...
   3531 	 */
   3532 	use_tso = (m_head->m_pkthdr.csum_flags & M_CSUM_TSOv4) != 0;
   3533 	if (!use_tso) {
   3534 		maxsegsize = 0;
   3535 	} else {	/* TSO setup */
   3536 		unsigned  mss;
   3537 		struct ether_header *eh;
   3538 		unsigned ip_tcp_hlen, iptcp_opt_words, tcp_seg_flags, offset;
   3539 		struct mbuf * m0 = m_head;
   3540 		struct ip *ip;
   3541 		struct tcphdr *th;
   3542 		int iphl, hlen;
   3543 
   3544 		/*
   3545 		 * XXX It would be nice if the mbuf pkthdr had offset
   3546 		 * fields for the protocol headers.
   3547 		 */
   3548 
   3549 		eh = mtod(m0, struct ether_header *);
   3550 		switch (htons(eh->ether_type)) {
   3551 		case ETHERTYPE_IP:
   3552 			offset = ETHER_HDR_LEN;
   3553 			break;
   3554 
   3555 		case ETHERTYPE_VLAN:
   3556 			offset = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN;
   3557 			break;
   3558 
   3559 		default:
   3560 			/*
   3561 			 * Don't support this protocol or encapsulation.
   3562 			 */
   3563 			return (ENOBUFS);
   3564 		}
   3565 
   3566 		/*
   3567 		 * TCP/IP headers are in the first mbuf; we can do
   3568 		 * this the easy way.
   3569 		 */
   3570 		iphl = M_CSUM_DATA_IPv4_IPHL(m0->m_pkthdr.csum_data);
   3571 		hlen = iphl + offset;
   3572 		if (__predict_false(m0->m_len <
   3573 				    (hlen + sizeof(struct tcphdr)))) {
   3574 
   3575 			  printf("TSO: hard case m0->m_len == %d <"
   3576 				 " ip/tcp hlen %zd, not handled yet\n",
   3577 				 m0->m_len, hlen+ sizeof(struct tcphdr));
   3578 #ifdef NOTYET
   3579 			/*
   3580 			 * XXX jonathan (at) NetBSD.org: untested.
   3581 			 * how to force  this branch to be taken?
   3582 			 */
   3583 			BGE_EVCNT_INCR(&sc->sc_ev_txtsopain);
   3584 
   3585 			m_copydata(m0, offset, sizeof(ip), &ip);
   3586 			m_copydata(m0, hlen, sizeof(th), &th);
   3587 
   3588 			ip.ip_len = 0;
   3589 
   3590 			m_copyback(m0, hlen + offsetof(struct ip, ip_len),
   3591 			    sizeof(ip.ip_len), &ip.ip_len);
   3592 
   3593 			th.th_sum = in_cksum_phdr(ip.ip_src.s_addr,
   3594 			    ip.ip_dst.s_addr, htons(IPPROTO_TCP));
   3595 
   3596 			m_copyback(m0, hlen + offsetof(struct tcphdr, th_sum),
   3597 			    sizeof(th.th_sum), &th.th_sum);
   3598 
   3599 			hlen += th.th_off << 2;
   3600 			iptcp_opt_words	= hlen;
   3601 #else
   3602 			/*
   3603 			 * if_wm "hard" case not yet supported, can we not
   3604 			 * mandate it out of existence?
   3605 			 */
   3606 			(void) ip; (void)th; (void) ip_tcp_hlen;
   3607 
   3608 			return ENOBUFS;
   3609 #endif
   3610 		} else {
   3611 			ip = (struct ip *) (mtod(m0, char *) + offset);
   3612 			th = (struct tcphdr *) (mtod(m0, char *) + hlen);
   3613 			ip_tcp_hlen = iphl +  (th->th_off << 2);
   3614 
   3615 			/* Total IP/TCP options, in 32-bit words */
   3616 			iptcp_opt_words = (ip_tcp_hlen
   3617 					   - sizeof(struct tcphdr)
   3618 					   - sizeof(struct ip)) >> 2;
   3619 		}
   3620 		if (BGE_IS_5750_OR_BEYOND(sc)) {
   3621 			th->th_sum = 0;
   3622 			csum_flags &= ~(BGE_TXBDFLAG_TCP_UDP_CSUM);
   3623 		} else {
   3624 			/*
   3625 			 * XXX jonathan (at) NetBSD.org: 5705 untested.
   3626 			 * Requires TSO firmware patch for 5701/5703/5704.
   3627 			 */
   3628 			th->th_sum = in_cksum_phdr(ip->ip_src.s_addr,
   3629 			    ip->ip_dst.s_addr, htons(IPPROTO_TCP));
   3630 		}
   3631 
   3632 		mss = m_head->m_pkthdr.segsz;
   3633 		txbd_tso_flags |=
   3634 		    BGE_TXBDFLAG_CPU_PRE_DMA |
   3635 		    BGE_TXBDFLAG_CPU_POST_DMA;
   3636 
   3637 		/*
   3638 		 * Our NIC TSO-assist assumes TSO has standard, optionless
   3639 		 * IPv4 and TCP headers, which total 40 bytes. By default,
   3640 		 * the NIC copies 40 bytes of IP/TCP header from the
   3641 		 * supplied header into the IP/TCP header portion of
   3642 		 * each post-TSO-segment. If the supplied packet has IP or
   3643 		 * TCP options, we need to tell the NIC to copy those extra
   3644 		 * bytes into each  post-TSO header, in addition to the normal
   3645 		 * 40-byte IP/TCP header (and to leave space accordingly).
   3646 		 * Unfortunately, the driver encoding of option length
   3647 		 * varies across different ASIC families.
   3648 		 */
   3649 		tcp_seg_flags = 0;
   3650 		if (iptcp_opt_words) {
   3651 			if ( BGE_IS_5705_OR_BEYOND(sc)) {
   3652 				tcp_seg_flags =
   3653 					iptcp_opt_words << 11;
   3654 			} else {
   3655 				txbd_tso_flags |=
   3656 					iptcp_opt_words << 12;
   3657 			}
   3658 		}
   3659 		maxsegsize = mss | tcp_seg_flags;
   3660 		ip->ip_len = htons(mss + ip_tcp_hlen);
   3661 
   3662 	}	/* TSO setup */
   3663 
   3664 	/*
   3665 	 * Start packing the mbufs in this chain into
   3666 	 * the fragment pointers. Stop when we run out
   3667 	 * of fragments or hit the end of the mbuf chain.
   3668 	 */
   3669 	error = bus_dmamap_load_mbuf(sc->bge_dmatag, dmamap, m_head,
   3670 	    BUS_DMA_NOWAIT);
   3671 	if (error) {
   3672 		return(ENOBUFS);
   3673 	}
   3674 	/*
   3675 	 * Sanity check: avoid coming within 16 descriptors
   3676 	 * of the end of the ring.
   3677 	 */
   3678 	if (dmamap->dm_nsegs > (BGE_TX_RING_CNT - sc->bge_txcnt - 16)) {
   3679 		BGE_TSO_PRINTF(("%s: "
   3680 		    " dmamap_load_mbuf too close to ring wrap\n",
   3681 		    sc->bge_dev.dv_xname));
   3682 		goto fail_unload;
   3683 	}
   3684 
   3685 	mtag = sc->ethercom.ec_nvlans ?
   3686 	    m_tag_find(m_head, PACKET_TAG_VLAN, NULL) : NULL;
   3687 
   3688 
   3689 	/* Iterate over dmap-map fragments. */
   3690 	for (i = 0; i < dmamap->dm_nsegs; i++) {
   3691 		f = &sc->bge_rdata->bge_tx_ring[frag];
   3692 		if (sc->bge_cdata.bge_tx_chain[frag] != NULL)
   3693 			break;
   3694 
   3695 		bge_set_hostaddr(&f->bge_addr, dmamap->dm_segs[i].ds_addr);
   3696 		f->bge_len = dmamap->dm_segs[i].ds_len;
   3697 
   3698 		/*
   3699 		 * For 5751 and follow-ons, for TSO we must turn
   3700 		 * off checksum-assist flag in the tx-descr, and
   3701 		 * supply the ASIC-revision-specific encoding
   3702 		 * of TSO flags and segsize.
   3703 		 */
   3704 		if (use_tso) {
   3705 			if (BGE_IS_5750_OR_BEYOND(sc) || i == 0) {
   3706 				f->bge_rsvd = maxsegsize;
   3707 				f->bge_flags = csum_flags | txbd_tso_flags;
   3708 			} else {
   3709 				f->bge_rsvd = 0;
   3710 				f->bge_flags =
   3711 				  (csum_flags | txbd_tso_flags) & 0x0fff;
   3712 			}
   3713 		} else {
   3714 			f->bge_rsvd = 0;
   3715 			f->bge_flags = csum_flags;
   3716 		}
   3717 
   3718 		if (mtag != NULL) {
   3719 			f->bge_flags |= BGE_TXBDFLAG_VLAN_TAG;
   3720 			f->bge_vlan_tag = VLAN_TAG_VALUE(mtag);
   3721 		} else {
   3722 			f->bge_vlan_tag = 0;
   3723 		}
   3724 		cur = frag;
   3725 		BGE_INC(frag, BGE_TX_RING_CNT);
   3726 	}
   3727 
   3728 	if (i < dmamap->dm_nsegs) {
   3729 		BGE_TSO_PRINTF(("%s: reached %d < dm_nsegs %d\n",
   3730 		    sc->bge_dev.dv_xname, i, dmamap->dm_nsegs));
   3731 		goto fail_unload;
   3732 	}
   3733 
   3734 	bus_dmamap_sync(sc->bge_dmatag, dmamap, 0, dmamap->dm_mapsize,
   3735 	    BUS_DMASYNC_PREWRITE);
   3736 
   3737 	if (frag == sc->bge_tx_saved_considx) {
   3738 		BGE_TSO_PRINTF(("%s: frag %d = wrapped id %d?\n",
   3739 		    sc->bge_dev.dv_xname, frag, sc->bge_tx_saved_considx));
   3740 
   3741 		goto fail_unload;
   3742 	}
   3743 
   3744 	sc->bge_rdata->bge_tx_ring[cur].bge_flags |= BGE_TXBDFLAG_END;
   3745 	sc->bge_cdata.bge_tx_chain[cur] = m_head;
   3746 	SLIST_REMOVE_HEAD(&sc->txdma_list, link);
   3747 	sc->txdma[cur] = dma;
   3748 	sc->bge_txcnt += dmamap->dm_nsegs;
   3749 
   3750 	*txidx = frag;
   3751 
   3752 	return(0);
   3753 
   3754  fail_unload:
   3755 	bus_dmamap_unload(sc->bge_dmatag, dmamap);
   3756 
   3757 	return ENOBUFS;
   3758 }
   3759 
   3760 /*
   3761  * Main transmit routine. To avoid having to do mbuf copies, we put pointers
   3762  * to the mbuf data regions directly in the transmit descriptors.
   3763  */
   3764 static void
   3765 bge_start(struct ifnet *ifp)
   3766 {
   3767 	struct bge_softc *sc;
   3768 	struct mbuf *m_head = NULL;
   3769 	u_int32_t prodidx;
   3770 	int pkts = 0;
   3771 
   3772 	sc = ifp->if_softc;
   3773 
   3774 	if (!sc->bge_link && ifp->if_snd.ifq_len < 10)
   3775 		return;
   3776 
   3777 	prodidx = sc->bge_tx_prodidx;
   3778 
   3779 	while(sc->bge_cdata.bge_tx_chain[prodidx] == NULL) {
   3780 		IFQ_POLL(&ifp->if_snd, m_head);
   3781 		if (m_head == NULL)
   3782 			break;
   3783 
   3784 #if 0
   3785 		/*
   3786 		 * XXX
   3787 		 * safety overkill.  If this is a fragmented packet chain
   3788 		 * with delayed TCP/UDP checksums, then only encapsulate
   3789 		 * it if we have enough descriptors to handle the entire
   3790 		 * chain at once.
   3791 		 * (paranoia -- may not actually be needed)
   3792 		 */
   3793 		if (m_head->m_flags & M_FIRSTFRAG &&
   3794 		    m_head->m_pkthdr.csum_flags & (CSUM_DELAY_DATA)) {
   3795 			if ((BGE_TX_RING_CNT - sc->bge_txcnt) <
   3796 			    M_CSUM_DATA_IPv4_OFFSET(m_head->m_pkthdr.csum_data) + 16) {
   3797 				ifp->if_flags |= IFF_OACTIVE;
   3798 				break;
   3799 			}
   3800 		}
   3801 #endif
   3802 
   3803 		/*
   3804 		 * Pack the data into the transmit ring. If we
   3805 		 * don't have room, set the OACTIVE flag and wait
   3806 		 * for the NIC to drain the ring.
   3807 		 */
   3808 		if (bge_encap(sc, m_head, &prodidx)) {
   3809 			printf("bge: failed on len %d?\n", m_head->m_pkthdr.len);
   3810 			ifp->if_flags |= IFF_OACTIVE;
   3811 			break;
   3812 		}
   3813 
   3814 		/* now we are committed to transmit the packet */
   3815 		IFQ_DEQUEUE(&ifp->if_snd, m_head);
   3816 		pkts++;
   3817 
   3818 #if NBPFILTER > 0
   3819 		/*
   3820 		 * If there's a BPF listener, bounce a copy of this frame
   3821 		 * to him.
   3822 		 */
   3823 		if (ifp->if_bpf)
   3824 			bpf_mtap(ifp->if_bpf, m_head);
   3825 #endif
   3826 	}
   3827 	if (pkts == 0)
   3828 		return;
   3829 
   3830 	/* Transmit */
   3831 	CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx);
   3832 	if (sc->bge_quirks & BGE_QUIRK_PRODUCER_BUG)	/* 5700 b2 errata */
   3833 		CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx);
   3834 
   3835 	sc->bge_tx_prodidx = prodidx;
   3836 
   3837 	/*
   3838 	 * Set a timeout in case the chip goes out to lunch.
   3839 	 */
   3840 	ifp->if_timer = 5;
   3841 }
   3842 
   3843 static int
   3844 bge_init(struct ifnet *ifp)
   3845 {
   3846 	struct bge_softc *sc = ifp->if_softc;
   3847 	u_int16_t *m;
   3848 	int s, error;
   3849 
   3850 	s = splnet();
   3851 
   3852 	ifp = &sc->ethercom.ec_if;
   3853 
   3854 	/* Cancel pending I/O and flush buffers. */
   3855 	bge_stop(sc);
   3856 	bge_reset(sc);
   3857 	bge_chipinit(sc);
   3858 
   3859 	/*
   3860 	 * Init the various state machines, ring
   3861 	 * control blocks and firmware.
   3862 	 */
   3863 	error = bge_blockinit(sc);
   3864 	if (error != 0) {
   3865 		printf("%s: initialization error %d\n", sc->bge_dev.dv_xname,
   3866 		    error);
   3867 		splx(s);
   3868 		return error;
   3869 	}
   3870 
   3871 	ifp = &sc->ethercom.ec_if;
   3872 
   3873 	/* Specify MTU. */
   3874 	CSR_WRITE_4(sc, BGE_RX_MTU, ifp->if_mtu +
   3875 	    ETHER_HDR_LEN + ETHER_CRC_LEN + ETHER_VLAN_ENCAP_LEN);
   3876 
   3877 	/* Load our MAC address. */
   3878 	m = (u_int16_t *)&(LLADDR(ifp->if_sadl)[0]);
   3879 	CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0]));
   3880 	CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, (htons(m[1]) << 16) | htons(m[2]));
   3881 
   3882 	/* Enable or disable promiscuous mode as needed. */
   3883 	if (ifp->if_flags & IFF_PROMISC) {
   3884 		BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC);
   3885 	} else {
   3886 		BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC);
   3887 	}
   3888 
   3889 	/* Program multicast filter. */
   3890 	bge_setmulti(sc);
   3891 
   3892 	/* Init RX ring. */
   3893 	bge_init_rx_ring_std(sc);
   3894 
   3895 	/* Init jumbo RX ring. */
   3896 	if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN))
   3897 		bge_init_rx_ring_jumbo(sc);
   3898 
   3899 	/* Init our RX return ring index */
   3900 	sc->bge_rx_saved_considx = 0;
   3901 
   3902 	/* Init TX ring. */
   3903 	bge_init_tx_ring(sc);
   3904 
   3905 	/* Turn on transmitter */
   3906 	BGE_SETBIT(sc, BGE_TX_MODE, BGE_TXMODE_ENABLE);
   3907 
   3908 	/* Turn on receiver */
   3909 	BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE);
   3910 
   3911 	CSR_WRITE_4(sc, BGE_MAX_RX_FRAME_LOWAT, 2);
   3912 
   3913 	/* Tell firmware we're alive. */
   3914 	BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
   3915 
   3916 	/* Enable host interrupts. */
   3917 	BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA);
   3918 	BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR);
   3919 	CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 0);
   3920 
   3921 	bge_ifmedia_upd(ifp);
   3922 
   3923 	ifp->if_flags |= IFF_RUNNING;
   3924 	ifp->if_flags &= ~IFF_OACTIVE;
   3925 
   3926 	splx(s);
   3927 
   3928 	callout_reset(&sc->bge_timeout, hz, bge_tick, sc);
   3929 
   3930 	return 0;
   3931 }
   3932 
   3933 /*
   3934  * Set media options.
   3935  */
   3936 static int
   3937 bge_ifmedia_upd(struct ifnet *ifp)
   3938 {
   3939 	struct bge_softc *sc = ifp->if_softc;
   3940 	struct mii_data *mii = &sc->bge_mii;
   3941 	struct ifmedia *ifm = &sc->bge_ifmedia;
   3942 
   3943 	/* If this is a 1000baseX NIC, enable the TBI port. */
   3944 	if (sc->bge_tbi) {
   3945 		if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
   3946 			return(EINVAL);
   3947 		switch(IFM_SUBTYPE(ifm->ifm_media)) {
   3948 		case IFM_AUTO:
   3949 			break;
   3950 		case IFM_1000_SX:
   3951 			if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) {
   3952 				BGE_CLRBIT(sc, BGE_MAC_MODE,
   3953 				    BGE_MACMODE_HALF_DUPLEX);
   3954 			} else {
   3955 				BGE_SETBIT(sc, BGE_MAC_MODE,
   3956 				    BGE_MACMODE_HALF_DUPLEX);
   3957 			}
   3958 			break;
   3959 		default:
   3960 			return(EINVAL);
   3961 		}
   3962 		/* XXX 802.3x flow control for 1000BASE-SX */
   3963 		return(0);
   3964 	}
   3965 
   3966 	sc->bge_link = 0;
   3967 	mii_mediachg(mii);
   3968 
   3969 	return(0);
   3970 }
   3971 
   3972 /*
   3973  * Report current media status.
   3974  */
   3975 static void
   3976 bge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
   3977 {
   3978 	struct bge_softc *sc = ifp->if_softc;
   3979 	struct mii_data *mii = &sc->bge_mii;
   3980 
   3981 	if (sc->bge_tbi) {
   3982 		ifmr->ifm_status = IFM_AVALID;
   3983 		ifmr->ifm_active = IFM_ETHER;
   3984 		if (CSR_READ_4(sc, BGE_MAC_STS) &
   3985 		    BGE_MACSTAT_TBI_PCS_SYNCHED)
   3986 			ifmr->ifm_status |= IFM_ACTIVE;
   3987 		ifmr->ifm_active |= IFM_1000_SX;
   3988 		if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX)
   3989 			ifmr->ifm_active |= IFM_HDX;
   3990 		else
   3991 			ifmr->ifm_active |= IFM_FDX;
   3992 		return;
   3993 	}
   3994 
   3995 	mii_pollstat(mii);
   3996 	ifmr->ifm_status = mii->mii_media_status;
   3997 	ifmr->ifm_active = (mii->mii_media_active & ~IFM_ETH_FMASK) |
   3998 	    sc->bge_flowflags;
   3999 }
   4000 
   4001 static int
   4002 bge_ioctl(struct ifnet *ifp, u_long command, void *data)
   4003 {
   4004 	struct bge_softc *sc = ifp->if_softc;
   4005 	struct ifreq *ifr = (struct ifreq *) data;
   4006 	int s, error = 0;
   4007 	struct mii_data *mii;
   4008 
   4009 	s = splnet();
   4010 
   4011 	switch(command) {
   4012 	case SIOCSIFFLAGS:
   4013 		if (ifp->if_flags & IFF_UP) {
   4014 			/*
   4015 			 * If only the state of the PROMISC flag changed,
   4016 			 * then just use the 'set promisc mode' command
   4017 			 * instead of reinitializing the entire NIC. Doing
   4018 			 * a full re-init means reloading the firmware and
   4019 			 * waiting for it to start up, which may take a
   4020 			 * second or two.
   4021 			 */
   4022 			if (ifp->if_flags & IFF_RUNNING &&
   4023 			    ifp->if_flags & IFF_PROMISC &&
   4024 			    !(sc->bge_if_flags & IFF_PROMISC)) {
   4025 				BGE_SETBIT(sc, BGE_RX_MODE,
   4026 				    BGE_RXMODE_RX_PROMISC);
   4027 			} else if (ifp->if_flags & IFF_RUNNING &&
   4028 			    !(ifp->if_flags & IFF_PROMISC) &&
   4029 			    sc->bge_if_flags & IFF_PROMISC) {
   4030 				BGE_CLRBIT(sc, BGE_RX_MODE,
   4031 				    BGE_RXMODE_RX_PROMISC);
   4032 			} else if (!(sc->bge_if_flags & IFF_UP))
   4033 				bge_init(ifp);
   4034 		} else {
   4035 			if (ifp->if_flags & IFF_RUNNING) {
   4036 				bge_stop(sc);
   4037 			}
   4038 		}
   4039 		sc->bge_if_flags = ifp->if_flags;
   4040 		error = 0;
   4041 		break;
   4042 	case SIOCSIFMEDIA:
   4043 		/* XXX Flow control is not supported for 1000BASE-SX */
   4044 		if (sc->bge_tbi) {
   4045 			ifr->ifr_media &= ~IFM_ETH_FMASK;
   4046 			sc->bge_flowflags = 0;
   4047 		}
   4048 
   4049 		/* Flow control requires full-duplex mode. */
   4050 		if (IFM_SUBTYPE(ifr->ifr_media) == IFM_AUTO ||
   4051 		    (ifr->ifr_media & IFM_FDX) == 0) {
   4052 		    	ifr->ifr_media &= ~IFM_ETH_FMASK;
   4053 		}
   4054 		if (IFM_SUBTYPE(ifr->ifr_media) != IFM_AUTO) {
   4055 			if ((ifr->ifr_media & IFM_ETH_FMASK) == IFM_FLOW) {
   4056 				/* We an do both TXPAUSE and RXPAUSE. */
   4057 				ifr->ifr_media |=
   4058 				    IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE;
   4059 			}
   4060 			sc->bge_flowflags = ifr->ifr_media & IFM_ETH_FMASK;
   4061 		}
   4062 		/* FALLTHROUGH */
   4063 	case SIOCGIFMEDIA:
   4064 		if (sc->bge_tbi) {
   4065 			error = ifmedia_ioctl(ifp, ifr, &sc->bge_ifmedia,
   4066 			    command);
   4067 		} else {
   4068 			mii = &sc->bge_mii;
   4069 			error = ifmedia_ioctl(ifp, ifr, &mii->mii_media,
   4070 			    command);
   4071 		}
   4072 		break;
   4073 	default:
   4074 		error = ether_ioctl(ifp, command, data);
   4075 		if (error == ENETRESET) {
   4076 			if (ifp->if_flags & IFF_RUNNING)
   4077 				bge_setmulti(sc);
   4078 			error = 0;
   4079 		}
   4080 		break;
   4081 	}
   4082 
   4083 	splx(s);
   4084 
   4085 	return(error);
   4086 }
   4087 
   4088 static void
   4089 bge_watchdog(struct ifnet *ifp)
   4090 {
   4091 	struct bge_softc *sc;
   4092 
   4093 	sc = ifp->if_softc;
   4094 
   4095 	printf("%s: watchdog timeout -- resetting\n", sc->bge_dev.dv_xname);
   4096 
   4097 	ifp->if_flags &= ~IFF_RUNNING;
   4098 	bge_init(ifp);
   4099 
   4100 	ifp->if_oerrors++;
   4101 }
   4102 
   4103 static void
   4104 bge_stop_block(struct bge_softc *sc, bus_addr_t reg, uint32_t bit)
   4105 {
   4106 	int i;
   4107 
   4108 	BGE_CLRBIT(sc, reg, bit);
   4109 
   4110 	for (i = 0; i < BGE_TIMEOUT; i++) {
   4111 		if ((CSR_READ_4(sc, reg) & bit) == 0)
   4112 			return;
   4113 		delay(100);
   4114 		if (sc->bge_pcie)
   4115 		  DELAY(1000);
   4116 	}
   4117 
   4118 	printf("%s: block failed to stop: reg 0x%lx, bit 0x%08x\n",
   4119 	    sc->bge_dev.dv_xname, (u_long) reg, bit);
   4120 }
   4121 
   4122 /*
   4123  * Stop the adapter and free any mbufs allocated to the
   4124  * RX and TX lists.
   4125  */
   4126 static void
   4127 bge_stop(struct bge_softc *sc)
   4128 {
   4129 	struct ifnet *ifp = &sc->ethercom.ec_if;
   4130 
   4131 	callout_stop(&sc->bge_timeout);
   4132 
   4133 	/*
   4134 	 * Disable all of the receiver blocks
   4135 	 */
   4136 	bge_stop_block(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE);
   4137 	bge_stop_block(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE);
   4138 	bge_stop_block(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);
   4139 	if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) {
   4140 		bge_stop_block(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE);
   4141 	}
   4142 	bge_stop_block(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE);
   4143 	bge_stop_block(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);
   4144 	bge_stop_block(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE);
   4145 
   4146 	/*
   4147 	 * Disable all of the transmit blocks
   4148 	 */
   4149 	bge_stop_block(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE);
   4150 	bge_stop_block(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE);
   4151 	bge_stop_block(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE);
   4152 	bge_stop_block(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE);
   4153 	bge_stop_block(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE);
   4154 	if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) {
   4155 		bge_stop_block(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE);
   4156 	}
   4157 	bge_stop_block(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);
   4158 
   4159 	/*
   4160 	 * Shut down all of the memory managers and related
   4161 	 * state machines.
   4162 	 */
   4163 	bge_stop_block(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE);
   4164 	bge_stop_block(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE);
   4165 	if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) {
   4166 		bge_stop_block(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE);
   4167 	}
   4168 
   4169 	CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF);
   4170 	CSR_WRITE_4(sc, BGE_FTQ_RESET, 0);
   4171 
   4172 	if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) {
   4173 		bge_stop_block(sc, BGE_BMAN_MODE, BGE_BMANMODE_ENABLE);
   4174 		bge_stop_block(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE);
   4175 	}
   4176 
   4177 	/* Disable host interrupts. */
   4178 	BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR);
   4179 	CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 1);
   4180 
   4181 	/*
   4182 	 * Tell firmware we're shutting down.
   4183 	 */
   4184 	BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
   4185 
   4186 	/* Free the RX lists. */
   4187 	bge_free_rx_ring_std(sc);
   4188 
   4189 	/* Free jumbo RX list. */
   4190 	bge_free_rx_ring_jumbo(sc);
   4191 
   4192 	/* Free TX buffers. */
   4193 	bge_free_tx_ring(sc);
   4194 
   4195 	/*
   4196 	 * Isolate/power down the PHY.
   4197 	 */
   4198 	if (!sc->bge_tbi)
   4199 		mii_down(&sc->bge_mii);
   4200 
   4201 	sc->bge_link = 0;
   4202 
   4203 	sc->bge_tx_saved_considx = BGE_TXCONS_UNSET;
   4204 
   4205 	ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
   4206 }
   4207 
   4208 /*
   4209  * Stop all chip I/O so that the kernel's probe routines don't
   4210  * get confused by errant DMAs when rebooting.
   4211  */
   4212 static void
   4213 bge_shutdown(void *xsc)
   4214 {
   4215 	struct bge_softc *sc = (struct bge_softc *)xsc;
   4216 
   4217 	bge_stop(sc);
   4218 	bge_reset(sc);
   4219 }
   4220 
   4221 
   4222 static int
   4223 sysctl_bge_verify(SYSCTLFN_ARGS)
   4224 {
   4225 	int error, t;
   4226 	struct sysctlnode node;
   4227 
   4228 	node = *rnode;
   4229 	t = *(int*)rnode->sysctl_data;
   4230 	node.sysctl_data = &t;
   4231 	error = sysctl_lookup(SYSCTLFN_CALL(&node));
   4232 	if (error || newp == NULL)
   4233 		return (error);
   4234 
   4235 #if 0
   4236 	DPRINTF2(("%s: t = %d, nodenum = %d, rnodenum = %d\n", __func__, t,
   4237 	    node.sysctl_num, rnode->sysctl_num));
   4238 #endif
   4239 
   4240 	if (node.sysctl_num == bge_rxthresh_nodenum) {
   4241 		if (t < 0 || t >= NBGE_RX_THRESH)
   4242 			return (EINVAL);
   4243 		bge_update_all_threshes(t);
   4244 	} else
   4245 		return (EINVAL);
   4246 
   4247 	*(int*)rnode->sysctl_data = t;
   4248 
   4249 	return (0);
   4250 }
   4251 
   4252 /*
   4253  * Set up sysctl(3) MIB, hw.bge.*.
   4254  *
   4255  * TBD condition SYSCTL_PERMANENT on being an LKM or not
   4256  */
   4257 SYSCTL_SETUP(sysctl_bge, "sysctl bge subtree setup")
   4258 {
   4259 	int rc, bge_root_num;
   4260 	const struct sysctlnode *node;
   4261 
   4262 	if ((rc = sysctl_createv(clog, 0, NULL, NULL,
   4263 	    CTLFLAG_PERMANENT, CTLTYPE_NODE, "hw", NULL,
   4264 	    NULL, 0, NULL, 0, CTL_HW, CTL_EOL)) != 0) {
   4265 		goto err;
   4266 	}
   4267 
   4268 	if ((rc = sysctl_createv(clog, 0, NULL, &node,
   4269 	    CTLFLAG_PERMANENT, CTLTYPE_NODE, "bge",
   4270 	    SYSCTL_DESCR("BGE interface controls"),
   4271 	    NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL)) != 0) {
   4272 		goto err;
   4273 	}
   4274 
   4275 	bge_root_num = node->sysctl_num;
   4276 
   4277 	/* BGE Rx interrupt mitigation level */
   4278 	if ((rc = sysctl_createv(clog, 0, NULL, &node,
   4279 	    CTLFLAG_PERMANENT|CTLFLAG_READWRITE,
   4280 	    CTLTYPE_INT, "rx_lvl",
   4281 	    SYSCTL_DESCR("BGE receive interrupt mitigation level"),
   4282 	    sysctl_bge_verify, 0,
   4283 	    &bge_rx_thresh_lvl,
   4284 	    0, CTL_HW, bge_root_num, CTL_CREATE,
   4285 	    CTL_EOL)) != 0) {
   4286 		goto err;
   4287 	}
   4288 
   4289 	bge_rxthresh_nodenum = node->sysctl_num;
   4290 
   4291 	return;
   4292 
   4293 err:
   4294 	printf("%s: sysctl_createv failed (rc = %d)\n", __func__, rc);
   4295 }
   4296 
   4297 static void
   4298 bge_powerhook(int why, void *hdl)
   4299 {
   4300 	struct bge_softc *sc = (struct bge_softc *)hdl;
   4301 	struct ifnet *ifp = &sc->ethercom.ec_if;
   4302 	struct pci_attach_args *pa = &(sc->bge_pa);
   4303 	pci_chipset_tag_t pc = pa->pa_pc;
   4304 	pcitag_t tag = pa->pa_tag;
   4305 
   4306 	switch (why) {
   4307 	case PWR_SOFTSUSPEND:
   4308 	case PWR_SOFTSTANDBY:
   4309 		bge_shutdown(sc);
   4310 		break;
   4311 	case PWR_SOFTRESUME:
   4312 		if (ifp->if_flags & IFF_UP) {
   4313 			ifp->if_flags &= ~IFF_RUNNING;
   4314 			bge_init(ifp);
   4315 		}
   4316 		break;
   4317 	case PWR_SUSPEND:
   4318 	case PWR_STANDBY:
   4319 		pci_conf_capture(pc, tag, &sc->bge_pciconf);
   4320 		break;
   4321 	case PWR_RESUME:
   4322 		pci_conf_restore(pc, tag, &sc->bge_pciconf);
   4323 		break;
   4324 	}
   4325 
   4326 	return;
   4327 }
   4328