if_bge.c revision 1.133
1 /* $NetBSD: if_bge.c,v 1.133 2007/08/06 12:29:36 markd Exp $ */ 2 3 /* 4 * Copyright (c) 2001 Wind River Systems 5 * Copyright (c) 1997, 1998, 1999, 2001 6 * Bill Paul <wpaul (at) windriver.com>. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Bill Paul. 19 * 4. Neither the name of the author nor the names of any co-contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 33 * THE POSSIBILITY OF SUCH DAMAGE. 34 * 35 * $FreeBSD: if_bge.c,v 1.13 2002/04/04 06:01:31 wpaul Exp $ 36 */ 37 38 /* 39 * Broadcom BCM570x family gigabit ethernet driver for NetBSD. 40 * 41 * NetBSD version by: 42 * 43 * Frank van der Linden <fvdl (at) wasabisystems.com> 44 * Jason Thorpe <thorpej (at) wasabisystems.com> 45 * Jonathan Stone <jonathan (at) dsg.stanford.edu> 46 * 47 * Originally written for FreeBSD by Bill Paul <wpaul (at) windriver.com> 48 * Senior Engineer, Wind River Systems 49 */ 50 51 /* 52 * The Broadcom BCM5700 is based on technology originally developed by 53 * Alteon Networks as part of the Tigon I and Tigon II gigabit ethernet 54 * MAC chips. The BCM5700, sometimes refered to as the Tigon III, has 55 * two on-board MIPS R4000 CPUs and can have as much as 16MB of external 56 * SSRAM. The BCM5700 supports TCP, UDP and IP checksum offload, jumbo 57 * frames, highly configurable RX filtering, and 16 RX and TX queues 58 * (which, along with RX filter rules, can be used for QOS applications). 59 * Other features, such as TCP segmentation, may be available as part 60 * of value-added firmware updates. Unlike the Tigon I and Tigon II, 61 * firmware images can be stored in hardware and need not be compiled 62 * into the driver. 63 * 64 * The BCM5700 supports the PCI v2.2 and PCI-X v1.0 standards, and will 65 * function in a 32-bit/64-bit 33/66MHz bus, or a 64-bit/133MHz bus. 66 * 67 * The BCM5701 is a single-chip solution incorporating both the BCM5700 68 * MAC and a BCM5401 10/100/1000 PHY. Unlike the BCM5700, the BCM5701 69 * does not support external SSRAM. 70 * 71 * Broadcom also produces a variation of the BCM5700 under the "Altima" 72 * brand name, which is functionally similar but lacks PCI-X support. 73 * 74 * Without external SSRAM, you can only have at most 4 TX rings, 75 * and the use of the mini RX ring is disabled. This seems to imply 76 * that these features are simply not available on the BCM5701. As a 77 * result, this driver does not implement any support for the mini RX 78 * ring. 79 */ 80 81 #include <sys/cdefs.h> 82 __KERNEL_RCSID(0, "$NetBSD: if_bge.c,v 1.133 2007/08/06 12:29:36 markd Exp $"); 83 84 #include "bpfilter.h" 85 #include "vlan.h" 86 87 #include <sys/param.h> 88 #include <sys/systm.h> 89 #include <sys/callout.h> 90 #include <sys/sockio.h> 91 #include <sys/mbuf.h> 92 #include <sys/malloc.h> 93 #include <sys/kernel.h> 94 #include <sys/device.h> 95 #include <sys/socket.h> 96 #include <sys/sysctl.h> 97 98 #include <net/if.h> 99 #include <net/if_dl.h> 100 #include <net/if_media.h> 101 #include <net/if_ether.h> 102 103 #ifdef INET 104 #include <netinet/in.h> 105 #include <netinet/in_systm.h> 106 #include <netinet/in_var.h> 107 #include <netinet/ip.h> 108 #endif 109 110 /* Headers for TCP Segmentation Offload (TSO) */ 111 #include <netinet/in_systm.h> /* n_time for <netinet/ip.h>... */ 112 #include <netinet/in.h> /* ip_{src,dst}, for <netinet/ip.h> */ 113 #include <netinet/ip.h> /* for struct ip */ 114 #include <netinet/tcp.h> /* for struct tcphdr */ 115 116 117 #if NBPFILTER > 0 118 #include <net/bpf.h> 119 #endif 120 121 #include <dev/pci/pcireg.h> 122 #include <dev/pci/pcivar.h> 123 #include <dev/pci/pcidevs.h> 124 125 #include <dev/mii/mii.h> 126 #include <dev/mii/miivar.h> 127 #include <dev/mii/miidevs.h> 128 #include <dev/mii/brgphyreg.h> 129 130 #include <dev/pci/if_bgereg.h> 131 132 #include <uvm/uvm_extern.h> 133 134 #define ETHER_MIN_NOPAD (ETHER_MIN_LEN - ETHER_CRC_LEN) /* i.e., 60 */ 135 136 137 /* 138 * Tunable thresholds for rx-side bge interrupt mitigation. 139 */ 140 141 /* 142 * The pairs of values below were obtained from empirical measurement 143 * on bcm5700 rev B2; they ar designed to give roughly 1 receive 144 * interrupt for every N packets received, where N is, approximately, 145 * the second value (rx_max_bds) in each pair. The values are chosen 146 * such that moving from one pair to the succeeding pair was observed 147 * to roughly halve interrupt rate under sustained input packet load. 148 * The values were empirically chosen to avoid overflowing internal 149 * limits on the bcm5700: inreasing rx_ticks much beyond 600 150 * results in internal wrapping and higher interrupt rates. 151 * The limit of 46 frames was chosen to match NFS workloads. 152 * 153 * These values also work well on bcm5701, bcm5704C, and (less 154 * tested) bcm5703. On other chipsets, (including the Altima chip 155 * family), the larger values may overflow internal chip limits, 156 * leading to increasing interrupt rates rather than lower interrupt 157 * rates. 158 * 159 * Applications using heavy interrupt mitigation (interrupting every 160 * 32 or 46 frames) in both directions may need to increase the TCP 161 * windowsize to above 131072 bytes (e.g., to 199608 bytes) to sustain 162 * full link bandwidth, due to ACKs and window updates lingering 163 * in the RX queue during the 30-to-40-frame interrupt-mitigation window. 164 */ 165 static const struct bge_load_rx_thresh { 166 int rx_ticks; 167 int rx_max_bds; } 168 bge_rx_threshes[] = { 169 { 32, 2 }, 170 { 50, 4 }, 171 { 100, 8 }, 172 { 192, 16 }, 173 { 416, 32 }, 174 { 598, 46 } 175 }; 176 #define NBGE_RX_THRESH (sizeof(bge_rx_threshes) / sizeof(bge_rx_threshes[0])) 177 178 /* XXX patchable; should be sysctl'able */ 179 static int bge_auto_thresh = 1; 180 static int bge_rx_thresh_lvl; 181 182 static int bge_rxthresh_nodenum; 183 184 static int bge_probe(device_t, cfdata_t, void *); 185 static void bge_attach(device_t, device_t, void *); 186 static void bge_powerhook(int, void *); 187 static void bge_release_resources(struct bge_softc *); 188 static void bge_txeof(struct bge_softc *); 189 static void bge_rxeof(struct bge_softc *); 190 191 static void bge_tick(void *); 192 static void bge_stats_update(struct bge_softc *); 193 static int bge_encap(struct bge_softc *, struct mbuf *, u_int32_t *); 194 195 static int bge_intr(void *); 196 static void bge_start(struct ifnet *); 197 static int bge_ioctl(struct ifnet *, u_long, void *); 198 static int bge_init(struct ifnet *); 199 static void bge_stop(struct bge_softc *); 200 static void bge_watchdog(struct ifnet *); 201 static void bge_shutdown(void *); 202 static int bge_ifmedia_upd(struct ifnet *); 203 static void bge_ifmedia_sts(struct ifnet *, struct ifmediareq *); 204 205 static void bge_setmulti(struct bge_softc *); 206 207 static void bge_handle_events(struct bge_softc *); 208 static int bge_alloc_jumbo_mem(struct bge_softc *); 209 #if 0 /* XXX */ 210 static void bge_free_jumbo_mem(struct bge_softc *); 211 #endif 212 static void *bge_jalloc(struct bge_softc *); 213 static void bge_jfree(struct mbuf *, void *, size_t, void *); 214 static int bge_newbuf_std(struct bge_softc *, int, struct mbuf *, 215 bus_dmamap_t); 216 static int bge_newbuf_jumbo(struct bge_softc *, int, struct mbuf *); 217 static int bge_init_rx_ring_std(struct bge_softc *); 218 static void bge_free_rx_ring_std(struct bge_softc *); 219 static int bge_init_rx_ring_jumbo(struct bge_softc *); 220 static void bge_free_rx_ring_jumbo(struct bge_softc *); 221 static void bge_free_tx_ring(struct bge_softc *); 222 static int bge_init_tx_ring(struct bge_softc *); 223 224 static int bge_chipinit(struct bge_softc *); 225 static int bge_blockinit(struct bge_softc *); 226 static int bge_setpowerstate(struct bge_softc *, int); 227 228 static void bge_reset(struct bge_softc *); 229 230 #define BGE_DEBUG 231 #ifdef BGE_DEBUG 232 #define DPRINTF(x) if (bgedebug) printf x 233 #define DPRINTFN(n,x) if (bgedebug >= (n)) printf x 234 #define BGE_TSO_PRINTF(x) do { if (bge_tso_debug) printf x ;} while (0) 235 int bgedebug = 0; 236 int bge_tso_debug = 0; 237 #else 238 #define DPRINTF(x) 239 #define DPRINTFN(n,x) 240 #define BGE_TSO_PRINTF(x) 241 #endif 242 243 #ifdef BGE_EVENT_COUNTERS 244 #define BGE_EVCNT_INCR(ev) (ev).ev_count++ 245 #define BGE_EVCNT_ADD(ev, val) (ev).ev_count += (val) 246 #define BGE_EVCNT_UPD(ev, val) (ev).ev_count = (val) 247 #else 248 #define BGE_EVCNT_INCR(ev) /* nothing */ 249 #define BGE_EVCNT_ADD(ev, val) /* nothing */ 250 #define BGE_EVCNT_UPD(ev, val) /* nothing */ 251 #endif 252 253 /* Various chip quirks. */ 254 #define BGE_QUIRK_LINK_STATE_BROKEN 0x00000001 255 #define BGE_QUIRK_CSUM_BROKEN 0x00000002 256 #define BGE_QUIRK_ONLY_PHY_1 0x00000004 257 #define BGE_QUIRK_5700_SMALLDMA 0x00000008 258 #define BGE_QUIRK_5700_PCIX_REG_BUG 0x00000010 259 #define BGE_QUIRK_PRODUCER_BUG 0x00000020 260 #define BGE_QUIRK_PCIX_DMA_ALIGN_BUG 0x00000040 261 #define BGE_QUIRK_5705_CORE 0x00000080 262 #define BGE_QUIRK_FEWER_MBUFS 0x00000100 263 264 /* 265 * XXX: how to handle variants based on 5750 and derivatives: 266 * 5750 5751, 5721, possibly 5714, 5752, and 5708?, which 267 * in general behave like a 5705, except with additional quirks. 268 * This driver's current handling of the 5721 is wrong; 269 * how we map ASIC revision to "quirks" needs more thought. 270 * (defined here until the thought is done). 271 */ 272 #define BGE_IS_5714_FAMILY(sc) \ 273 (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5714_A0 || \ 274 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5780 || \ 275 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5714 ) 276 277 #define BGE_IS_5750_OR_BEYOND(sc) \ 278 (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5750 || \ 279 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5752 || \ 280 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5755 || \ 281 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5787 || \ 282 BGE_IS_5714_FAMILY(sc) ) 283 284 #define BGE_IS_5705_OR_BEYOND(sc) \ 285 ( ((sc)->bge_quirks & BGE_QUIRK_5705_CORE) || \ 286 BGE_IS_5750_OR_BEYOND(sc) ) 287 288 289 /* following bugs are common to bcm5700 rev B, all flavours */ 290 #define BGE_QUIRK_5700_COMMON \ 291 (BGE_QUIRK_5700_SMALLDMA|BGE_QUIRK_PRODUCER_BUG) 292 293 CFATTACH_DECL(bge, sizeof(struct bge_softc), 294 bge_probe, bge_attach, NULL, NULL); 295 296 static u_int32_t 297 bge_readmem_ind(struct bge_softc *sc, int off) 298 { 299 struct pci_attach_args *pa = &(sc->bge_pa); 300 pcireg_t val; 301 302 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_MEMWIN_BASEADDR, off); 303 val = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_MEMWIN_DATA); 304 return val; 305 } 306 307 static void 308 bge_writemem_ind(struct bge_softc *sc, int off, int val) 309 { 310 struct pci_attach_args *pa = &(sc->bge_pa); 311 312 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_MEMWIN_BASEADDR, off); 313 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_MEMWIN_DATA, val); 314 } 315 316 #ifdef notdef 317 static u_int32_t 318 bge_readreg_ind(struct bge_softc *sc, int off) 319 { 320 struct pci_attach_args *pa = &(sc->bge_pa); 321 322 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_REG_BASEADDR, off); 323 return(pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_REG_DATA)); 324 } 325 #endif 326 327 static void 328 bge_writereg_ind(struct bge_softc *sc, int off, int val) 329 { 330 struct pci_attach_args *pa = &(sc->bge_pa); 331 332 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_REG_BASEADDR, off); 333 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_REG_DATA, val); 334 } 335 336 #ifdef notdef 337 static u_int8_t 338 bge_vpd_readbyte(struct bge_softc *sc, int addr) 339 { 340 int i; 341 u_int32_t val; 342 struct pci_attach_args *pa = &(sc->bge_pa); 343 344 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_VPD_ADDR, addr); 345 for (i = 0; i < BGE_TIMEOUT * 10; i++) { 346 DELAY(10); 347 if (pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_VPD_ADDR) & 348 BGE_VPD_FLAG) 349 break; 350 } 351 352 if (i == BGE_TIMEOUT) { 353 printf("%s: VPD read timed out\n", sc->bge_dev.dv_xname); 354 return(0); 355 } 356 357 val = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_VPD_DATA); 358 359 return((val >> ((addr % 4) * 8)) & 0xFF); 360 } 361 362 static void 363 bge_vpd_read_res(struct bge_softc *sc, struct vpd_res *res, int addr) 364 { 365 int i; 366 u_int8_t *ptr; 367 368 ptr = (u_int8_t *)res; 369 for (i = 0; i < sizeof(struct vpd_res); i++) 370 ptr[i] = bge_vpd_readbyte(sc, i + addr); 371 } 372 373 static void 374 bge_vpd_read(struct bge_softc *sc) 375 { 376 int pos = 0, i; 377 struct vpd_res res; 378 379 if (sc->bge_vpd_prodname != NULL) 380 free(sc->bge_vpd_prodname, M_DEVBUF); 381 if (sc->bge_vpd_readonly != NULL) 382 free(sc->bge_vpd_readonly, M_DEVBUF); 383 sc->bge_vpd_prodname = NULL; 384 sc->bge_vpd_readonly = NULL; 385 386 bge_vpd_read_res(sc, &res, pos); 387 388 if (res.vr_id != VPD_RES_ID) { 389 printf("%s: bad VPD resource id: expected %x got %x\n", 390 sc->bge_dev.dv_xname, VPD_RES_ID, res.vr_id); 391 return; 392 } 393 394 pos += sizeof(res); 395 sc->bge_vpd_prodname = malloc(res.vr_len + 1, M_DEVBUF, M_NOWAIT); 396 if (sc->bge_vpd_prodname == NULL) 397 panic("bge_vpd_read"); 398 for (i = 0; i < res.vr_len; i++) 399 sc->bge_vpd_prodname[i] = bge_vpd_readbyte(sc, i + pos); 400 sc->bge_vpd_prodname[i] = '\0'; 401 pos += i; 402 403 bge_vpd_read_res(sc, &res, pos); 404 405 if (res.vr_id != VPD_RES_READ) { 406 printf("%s: bad VPD resource id: expected %x got %x\n", 407 sc->bge_dev.dv_xname, VPD_RES_READ, res.vr_id); 408 return; 409 } 410 411 pos += sizeof(res); 412 sc->bge_vpd_readonly = malloc(res.vr_len, M_DEVBUF, M_NOWAIT); 413 if (sc->bge_vpd_readonly == NULL) 414 panic("bge_vpd_read"); 415 for (i = 0; i < res.vr_len + 1; i++) 416 sc->bge_vpd_readonly[i] = bge_vpd_readbyte(sc, i + pos); 417 } 418 #endif 419 420 /* 421 * Read a byte of data stored in the EEPROM at address 'addr.' The 422 * BCM570x supports both the traditional bitbang interface and an 423 * auto access interface for reading the EEPROM. We use the auto 424 * access method. 425 */ 426 static u_int8_t 427 bge_eeprom_getbyte(struct bge_softc *sc, int addr, u_int8_t *dest) 428 { 429 int i; 430 u_int32_t byte = 0; 431 432 /* 433 * Enable use of auto EEPROM access so we can avoid 434 * having to use the bitbang method. 435 */ 436 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM); 437 438 /* Reset the EEPROM, load the clock period. */ 439 CSR_WRITE_4(sc, BGE_EE_ADDR, 440 BGE_EEADDR_RESET|BGE_EEHALFCLK(BGE_HALFCLK_384SCL)); 441 DELAY(20); 442 443 /* Issue the read EEPROM command. */ 444 CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr); 445 446 /* Wait for completion */ 447 for(i = 0; i < BGE_TIMEOUT * 10; i++) { 448 DELAY(10); 449 if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE) 450 break; 451 } 452 453 if (i == BGE_TIMEOUT) { 454 printf("%s: eeprom read timed out\n", sc->bge_dev.dv_xname); 455 return(0); 456 } 457 458 /* Get result. */ 459 byte = CSR_READ_4(sc, BGE_EE_DATA); 460 461 *dest = (byte >> ((addr % 4) * 8)) & 0xFF; 462 463 return(0); 464 } 465 466 /* 467 * Read a sequence of bytes from the EEPROM. 468 */ 469 static int 470 bge_read_eeprom(struct bge_softc *sc, void *destv, int off, int cnt) 471 { 472 int err = 0, i; 473 u_int8_t byte = 0; 474 char *dest = destv; 475 476 for (i = 0; i < cnt; i++) { 477 err = bge_eeprom_getbyte(sc, off + i, &byte); 478 if (err) 479 break; 480 *(dest + i) = byte; 481 } 482 483 return(err ? 1 : 0); 484 } 485 486 static int 487 bge_miibus_readreg(device_t dev, int phy, int reg) 488 { 489 struct bge_softc *sc = (struct bge_softc *)dev; 490 u_int32_t val; 491 u_int32_t saved_autopoll; 492 int i; 493 494 /* 495 * Several chips with builtin PHYs will incorrectly answer to 496 * other PHY instances than the builtin PHY at id 1. 497 */ 498 if (phy != 1 && (sc->bge_quirks & BGE_QUIRK_ONLY_PHY_1)) 499 return(0); 500 501 /* Reading with autopolling on may trigger PCI errors */ 502 saved_autopoll = CSR_READ_4(sc, BGE_MI_MODE); 503 if (saved_autopoll & BGE_MIMODE_AUTOPOLL) { 504 CSR_WRITE_4(sc, BGE_MI_MODE, 505 saved_autopoll &~ BGE_MIMODE_AUTOPOLL); 506 DELAY(40); 507 } 508 509 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_READ|BGE_MICOMM_BUSY| 510 BGE_MIPHY(phy)|BGE_MIREG(reg)); 511 512 for (i = 0; i < BGE_TIMEOUT; i++) { 513 val = CSR_READ_4(sc, BGE_MI_COMM); 514 if (!(val & BGE_MICOMM_BUSY)) 515 break; 516 delay(10); 517 } 518 519 if (i == BGE_TIMEOUT) { 520 printf("%s: PHY read timed out\n", sc->bge_dev.dv_xname); 521 val = 0; 522 goto done; 523 } 524 525 val = CSR_READ_4(sc, BGE_MI_COMM); 526 527 done: 528 if (saved_autopoll & BGE_MIMODE_AUTOPOLL) { 529 CSR_WRITE_4(sc, BGE_MI_MODE, saved_autopoll); 530 DELAY(40); 531 } 532 533 if (val & BGE_MICOMM_READFAIL) 534 return(0); 535 536 return(val & 0xFFFF); 537 } 538 539 static void 540 bge_miibus_writereg(device_t dev, int phy, int reg, int val) 541 { 542 struct bge_softc *sc = (struct bge_softc *)dev; 543 u_int32_t saved_autopoll; 544 int i; 545 546 /* Touching the PHY while autopolling is on may trigger PCI errors */ 547 saved_autopoll = CSR_READ_4(sc, BGE_MI_MODE); 548 if (saved_autopoll & BGE_MIMODE_AUTOPOLL) { 549 delay(40); 550 CSR_WRITE_4(sc, BGE_MI_MODE, 551 saved_autopoll & (~BGE_MIMODE_AUTOPOLL)); 552 delay(10); /* 40 usec is supposed to be adequate */ 553 } 554 555 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_WRITE|BGE_MICOMM_BUSY| 556 BGE_MIPHY(phy)|BGE_MIREG(reg)|val); 557 558 for (i = 0; i < BGE_TIMEOUT; i++) { 559 if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY)) 560 break; 561 delay(10); 562 } 563 564 if (saved_autopoll & BGE_MIMODE_AUTOPOLL) { 565 CSR_WRITE_4(sc, BGE_MI_MODE, saved_autopoll); 566 delay(40); 567 } 568 569 if (i == BGE_TIMEOUT) { 570 printf("%s: PHY read timed out\n", sc->bge_dev.dv_xname); 571 } 572 } 573 574 static void 575 bge_miibus_statchg(device_t dev) 576 { 577 struct bge_softc *sc = (struct bge_softc *)dev; 578 struct mii_data *mii = &sc->bge_mii; 579 580 /* 581 * Get flow control negotiation result. 582 */ 583 if (IFM_SUBTYPE(mii->mii_media.ifm_cur->ifm_media) == IFM_AUTO && 584 (mii->mii_media_active & IFM_ETH_FMASK) != sc->bge_flowflags) { 585 sc->bge_flowflags = mii->mii_media_active & IFM_ETH_FMASK; 586 mii->mii_media_active &= ~IFM_ETH_FMASK; 587 } 588 589 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_PORTMODE); 590 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) { 591 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_GMII); 592 } else { 593 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_MII); 594 } 595 596 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 597 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX); 598 } else { 599 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX); 600 } 601 602 /* 603 * 802.3x flow control 604 */ 605 if (sc->bge_flowflags & IFM_ETH_RXPAUSE) { 606 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_FLOWCTL_ENABLE); 607 } else { 608 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_FLOWCTL_ENABLE); 609 } 610 if (sc->bge_flowflags & IFM_ETH_TXPAUSE) { 611 BGE_SETBIT(sc, BGE_TX_MODE, BGE_TXMODE_FLOWCTL_ENABLE); 612 } else { 613 BGE_CLRBIT(sc, BGE_TX_MODE, BGE_TXMODE_FLOWCTL_ENABLE); 614 } 615 } 616 617 /* 618 * Update rx threshold levels to values in a particular slot 619 * of the interrupt-mitigation table bge_rx_threshes. 620 */ 621 static void 622 bge_set_thresh(struct ifnet *ifp, int lvl) 623 { 624 struct bge_softc *sc = ifp->if_softc; 625 int s; 626 627 /* For now, just save the new Rx-intr thresholds and record 628 * that a threshold update is pending. Updating the hardware 629 * registers here (even at splhigh()) is observed to 630 * occasionaly cause glitches where Rx-interrupts are not 631 * honoured for up to 10 seconds. jonathan (at) NetBSD.org, 2003-04-05 632 */ 633 s = splnet(); 634 sc->bge_rx_coal_ticks = bge_rx_threshes[lvl].rx_ticks; 635 sc->bge_rx_max_coal_bds = bge_rx_threshes[lvl].rx_max_bds; 636 sc->bge_pending_rxintr_change = 1; 637 splx(s); 638 639 return; 640 } 641 642 643 /* 644 * Update Rx thresholds of all bge devices 645 */ 646 static void 647 bge_update_all_threshes(int lvl) 648 { 649 struct ifnet *ifp; 650 const char * const namebuf = "bge"; 651 int namelen; 652 653 if (lvl < 0) 654 lvl = 0; 655 else if( lvl >= NBGE_RX_THRESH) 656 lvl = NBGE_RX_THRESH - 1; 657 658 namelen = strlen(namebuf); 659 /* 660 * Now search all the interfaces for this name/number 661 */ 662 IFNET_FOREACH(ifp) { 663 if (strncmp(ifp->if_xname, namebuf, namelen) != 0) 664 continue; 665 /* We got a match: update if doing auto-threshold-tuning */ 666 if (bge_auto_thresh) 667 bge_set_thresh(ifp, lvl); 668 } 669 } 670 671 /* 672 * Handle events that have triggered interrupts. 673 */ 674 static void 675 bge_handle_events(struct bge_softc *sc) 676 { 677 678 return; 679 } 680 681 /* 682 * Memory management for jumbo frames. 683 */ 684 685 static int 686 bge_alloc_jumbo_mem(struct bge_softc *sc) 687 { 688 char *ptr, *kva; 689 bus_dma_segment_t seg; 690 int i, rseg, state, error; 691 struct bge_jpool_entry *entry; 692 693 state = error = 0; 694 695 /* Grab a big chunk o' storage. */ 696 if (bus_dmamem_alloc(sc->bge_dmatag, BGE_JMEM, PAGE_SIZE, 0, 697 &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 698 printf("%s: can't alloc rx buffers\n", sc->bge_dev.dv_xname); 699 return ENOBUFS; 700 } 701 702 state = 1; 703 if (bus_dmamem_map(sc->bge_dmatag, &seg, rseg, BGE_JMEM, (void **)&kva, 704 BUS_DMA_NOWAIT)) { 705 printf("%s: can't map DMA buffers (%d bytes)\n", 706 sc->bge_dev.dv_xname, (int)BGE_JMEM); 707 error = ENOBUFS; 708 goto out; 709 } 710 711 state = 2; 712 if (bus_dmamap_create(sc->bge_dmatag, BGE_JMEM, 1, BGE_JMEM, 0, 713 BUS_DMA_NOWAIT, &sc->bge_cdata.bge_rx_jumbo_map)) { 714 printf("%s: can't create DMA map\n", sc->bge_dev.dv_xname); 715 error = ENOBUFS; 716 goto out; 717 } 718 719 state = 3; 720 if (bus_dmamap_load(sc->bge_dmatag, sc->bge_cdata.bge_rx_jumbo_map, 721 kva, BGE_JMEM, NULL, BUS_DMA_NOWAIT)) { 722 printf("%s: can't load DMA map\n", sc->bge_dev.dv_xname); 723 error = ENOBUFS; 724 goto out; 725 } 726 727 state = 4; 728 sc->bge_cdata.bge_jumbo_buf = (void *)kva; 729 DPRINTFN(1,("bge_jumbo_buf = %p\n", sc->bge_cdata.bge_jumbo_buf)); 730 731 SLIST_INIT(&sc->bge_jfree_listhead); 732 SLIST_INIT(&sc->bge_jinuse_listhead); 733 734 /* 735 * Now divide it up into 9K pieces and save the addresses 736 * in an array. 737 */ 738 ptr = sc->bge_cdata.bge_jumbo_buf; 739 for (i = 0; i < BGE_JSLOTS; i++) { 740 sc->bge_cdata.bge_jslots[i] = ptr; 741 ptr += BGE_JLEN; 742 entry = malloc(sizeof(struct bge_jpool_entry), 743 M_DEVBUF, M_NOWAIT); 744 if (entry == NULL) { 745 printf("%s: no memory for jumbo buffer queue!\n", 746 sc->bge_dev.dv_xname); 747 error = ENOBUFS; 748 goto out; 749 } 750 entry->slot = i; 751 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, 752 entry, jpool_entries); 753 } 754 out: 755 if (error != 0) { 756 switch (state) { 757 case 4: 758 bus_dmamap_unload(sc->bge_dmatag, 759 sc->bge_cdata.bge_rx_jumbo_map); 760 case 3: 761 bus_dmamap_destroy(sc->bge_dmatag, 762 sc->bge_cdata.bge_rx_jumbo_map); 763 case 2: 764 bus_dmamem_unmap(sc->bge_dmatag, kva, BGE_JMEM); 765 case 1: 766 bus_dmamem_free(sc->bge_dmatag, &seg, rseg); 767 break; 768 default: 769 break; 770 } 771 } 772 773 return error; 774 } 775 776 /* 777 * Allocate a jumbo buffer. 778 */ 779 static void * 780 bge_jalloc(struct bge_softc *sc) 781 { 782 struct bge_jpool_entry *entry; 783 784 entry = SLIST_FIRST(&sc->bge_jfree_listhead); 785 786 if (entry == NULL) { 787 printf("%s: no free jumbo buffers\n", sc->bge_dev.dv_xname); 788 return(NULL); 789 } 790 791 SLIST_REMOVE_HEAD(&sc->bge_jfree_listhead, jpool_entries); 792 SLIST_INSERT_HEAD(&sc->bge_jinuse_listhead, entry, jpool_entries); 793 return(sc->bge_cdata.bge_jslots[entry->slot]); 794 } 795 796 /* 797 * Release a jumbo buffer. 798 */ 799 static void 800 bge_jfree(struct mbuf *m, void *buf, size_t size, void *arg) 801 { 802 struct bge_jpool_entry *entry; 803 struct bge_softc *sc; 804 int i, s; 805 806 /* Extract the softc struct pointer. */ 807 sc = (struct bge_softc *)arg; 808 809 if (sc == NULL) 810 panic("bge_jfree: can't find softc pointer!"); 811 812 /* calculate the slot this buffer belongs to */ 813 814 i = ((char *)buf 815 - (char *)sc->bge_cdata.bge_jumbo_buf) / BGE_JLEN; 816 817 if ((i < 0) || (i >= BGE_JSLOTS)) 818 panic("bge_jfree: asked to free buffer that we don't manage!"); 819 820 s = splvm(); 821 entry = SLIST_FIRST(&sc->bge_jinuse_listhead); 822 if (entry == NULL) 823 panic("bge_jfree: buffer not in use!"); 824 entry->slot = i; 825 SLIST_REMOVE_HEAD(&sc->bge_jinuse_listhead, jpool_entries); 826 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, entry, jpool_entries); 827 828 if (__predict_true(m != NULL)) 829 pool_cache_put(&mbpool_cache, m); 830 splx(s); 831 } 832 833 834 /* 835 * Intialize a standard receive ring descriptor. 836 */ 837 static int 838 bge_newbuf_std(struct bge_softc *sc, int i, struct mbuf *m, bus_dmamap_t dmamap) 839 { 840 struct mbuf *m_new = NULL; 841 struct bge_rx_bd *r; 842 int error; 843 844 if (dmamap == NULL) { 845 error = bus_dmamap_create(sc->bge_dmatag, MCLBYTES, 1, 846 MCLBYTES, 0, BUS_DMA_NOWAIT, &dmamap); 847 if (error != 0) 848 return error; 849 } 850 851 sc->bge_cdata.bge_rx_std_map[i] = dmamap; 852 853 if (m == NULL) { 854 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 855 if (m_new == NULL) { 856 return(ENOBUFS); 857 } 858 859 MCLGET(m_new, M_DONTWAIT); 860 if (!(m_new->m_flags & M_EXT)) { 861 m_freem(m_new); 862 return(ENOBUFS); 863 } 864 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 865 866 } else { 867 m_new = m; 868 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 869 m_new->m_data = m_new->m_ext.ext_buf; 870 } 871 if (!sc->bge_rx_alignment_bug) 872 m_adj(m_new, ETHER_ALIGN); 873 if (bus_dmamap_load_mbuf(sc->bge_dmatag, dmamap, m_new, 874 BUS_DMA_READ|BUS_DMA_NOWAIT)) 875 return(ENOBUFS); 876 bus_dmamap_sync(sc->bge_dmatag, dmamap, 0, dmamap->dm_mapsize, 877 BUS_DMASYNC_PREREAD); 878 879 sc->bge_cdata.bge_rx_std_chain[i] = m_new; 880 r = &sc->bge_rdata->bge_rx_std_ring[i]; 881 bge_set_hostaddr(&r->bge_addr, 882 dmamap->dm_segs[0].ds_addr); 883 r->bge_flags = BGE_RXBDFLAG_END; 884 r->bge_len = m_new->m_len; 885 r->bge_idx = i; 886 887 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 888 offsetof(struct bge_ring_data, bge_rx_std_ring) + 889 i * sizeof (struct bge_rx_bd), 890 sizeof (struct bge_rx_bd), 891 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 892 893 return(0); 894 } 895 896 /* 897 * Initialize a jumbo receive ring descriptor. This allocates 898 * a jumbo buffer from the pool managed internally by the driver. 899 */ 900 static int 901 bge_newbuf_jumbo(struct bge_softc *sc, int i, struct mbuf *m) 902 { 903 struct mbuf *m_new = NULL; 904 struct bge_rx_bd *r; 905 void *buf = NULL; 906 907 if (m == NULL) { 908 909 /* Allocate the mbuf. */ 910 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 911 if (m_new == NULL) { 912 return(ENOBUFS); 913 } 914 915 /* Allocate the jumbo buffer */ 916 buf = bge_jalloc(sc); 917 if (buf == NULL) { 918 m_freem(m_new); 919 printf("%s: jumbo allocation failed " 920 "-- packet dropped!\n", sc->bge_dev.dv_xname); 921 return(ENOBUFS); 922 } 923 924 /* Attach the buffer to the mbuf. */ 925 m_new->m_len = m_new->m_pkthdr.len = BGE_JUMBO_FRAMELEN; 926 MEXTADD(m_new, buf, BGE_JUMBO_FRAMELEN, M_DEVBUF, 927 bge_jfree, sc); 928 m_new->m_flags |= M_EXT_RW; 929 } else { 930 m_new = m; 931 buf = m_new->m_data = m_new->m_ext.ext_buf; 932 m_new->m_ext.ext_size = BGE_JUMBO_FRAMELEN; 933 } 934 if (!sc->bge_rx_alignment_bug) 935 m_adj(m_new, ETHER_ALIGN); 936 bus_dmamap_sync(sc->bge_dmatag, sc->bge_cdata.bge_rx_jumbo_map, 937 mtod(m_new, char *) - (char *)sc->bge_cdata.bge_jumbo_buf, BGE_JLEN, 938 BUS_DMASYNC_PREREAD); 939 /* Set up the descriptor. */ 940 r = &sc->bge_rdata->bge_rx_jumbo_ring[i]; 941 sc->bge_cdata.bge_rx_jumbo_chain[i] = m_new; 942 bge_set_hostaddr(&r->bge_addr, BGE_JUMBO_DMA_ADDR(sc, m_new)); 943 r->bge_flags = BGE_RXBDFLAG_END|BGE_RXBDFLAG_JUMBO_RING; 944 r->bge_len = m_new->m_len; 945 r->bge_idx = i; 946 947 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 948 offsetof(struct bge_ring_data, bge_rx_jumbo_ring) + 949 i * sizeof (struct bge_rx_bd), 950 sizeof (struct bge_rx_bd), 951 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 952 953 return(0); 954 } 955 956 /* 957 * The standard receive ring has 512 entries in it. At 2K per mbuf cluster, 958 * that's 1MB or memory, which is a lot. For now, we fill only the first 959 * 256 ring entries and hope that our CPU is fast enough to keep up with 960 * the NIC. 961 */ 962 static int 963 bge_init_rx_ring_std(struct bge_softc *sc) 964 { 965 int i; 966 967 if (sc->bge_flags & BGE_RXRING_VALID) 968 return 0; 969 970 for (i = 0; i < BGE_SSLOTS; i++) { 971 if (bge_newbuf_std(sc, i, NULL, 0) == ENOBUFS) 972 return(ENOBUFS); 973 } 974 975 sc->bge_std = i - 1; 976 CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std); 977 978 sc->bge_flags |= BGE_RXRING_VALID; 979 980 return(0); 981 } 982 983 static void 984 bge_free_rx_ring_std(struct bge_softc *sc) 985 { 986 int i; 987 988 if (!(sc->bge_flags & BGE_RXRING_VALID)) 989 return; 990 991 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { 992 if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) { 993 m_freem(sc->bge_cdata.bge_rx_std_chain[i]); 994 sc->bge_cdata.bge_rx_std_chain[i] = NULL; 995 bus_dmamap_destroy(sc->bge_dmatag, 996 sc->bge_cdata.bge_rx_std_map[i]); 997 } 998 memset((char *)&sc->bge_rdata->bge_rx_std_ring[i], 0, 999 sizeof(struct bge_rx_bd)); 1000 } 1001 1002 sc->bge_flags &= ~BGE_RXRING_VALID; 1003 } 1004 1005 static int 1006 bge_init_rx_ring_jumbo(struct bge_softc *sc) 1007 { 1008 int i; 1009 volatile struct bge_rcb *rcb; 1010 1011 if (sc->bge_flags & BGE_JUMBO_RXRING_VALID) 1012 return 0; 1013 1014 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 1015 if (bge_newbuf_jumbo(sc, i, NULL) == ENOBUFS) 1016 return(ENOBUFS); 1017 }; 1018 1019 sc->bge_jumbo = i - 1; 1020 sc->bge_flags |= BGE_JUMBO_RXRING_VALID; 1021 1022 rcb = &sc->bge_rdata->bge_info.bge_jumbo_rx_rcb; 1023 rcb->bge_maxlen_flags = 0; 1024 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 1025 1026 CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo); 1027 1028 return(0); 1029 } 1030 1031 static void 1032 bge_free_rx_ring_jumbo(struct bge_softc *sc) 1033 { 1034 int i; 1035 1036 if (!(sc->bge_flags & BGE_JUMBO_RXRING_VALID)) 1037 return; 1038 1039 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 1040 if (sc->bge_cdata.bge_rx_jumbo_chain[i] != NULL) { 1041 m_freem(sc->bge_cdata.bge_rx_jumbo_chain[i]); 1042 sc->bge_cdata.bge_rx_jumbo_chain[i] = NULL; 1043 } 1044 memset((char *)&sc->bge_rdata->bge_rx_jumbo_ring[i], 0, 1045 sizeof(struct bge_rx_bd)); 1046 } 1047 1048 sc->bge_flags &= ~BGE_JUMBO_RXRING_VALID; 1049 } 1050 1051 static void 1052 bge_free_tx_ring(struct bge_softc *sc) 1053 { 1054 int i, freed; 1055 struct txdmamap_pool_entry *dma; 1056 1057 if (!(sc->bge_flags & BGE_TXRING_VALID)) 1058 return; 1059 1060 freed = 0; 1061 1062 for (i = 0; i < BGE_TX_RING_CNT; i++) { 1063 if (sc->bge_cdata.bge_tx_chain[i] != NULL) { 1064 freed++; 1065 m_freem(sc->bge_cdata.bge_tx_chain[i]); 1066 sc->bge_cdata.bge_tx_chain[i] = NULL; 1067 SLIST_INSERT_HEAD(&sc->txdma_list, sc->txdma[i], 1068 link); 1069 sc->txdma[i] = 0; 1070 } 1071 memset((char *)&sc->bge_rdata->bge_tx_ring[i], 0, 1072 sizeof(struct bge_tx_bd)); 1073 } 1074 1075 while ((dma = SLIST_FIRST(&sc->txdma_list))) { 1076 SLIST_REMOVE_HEAD(&sc->txdma_list, link); 1077 bus_dmamap_destroy(sc->bge_dmatag, dma->dmamap); 1078 free(dma, M_DEVBUF); 1079 } 1080 1081 sc->bge_flags &= ~BGE_TXRING_VALID; 1082 } 1083 1084 static int 1085 bge_init_tx_ring(struct bge_softc *sc) 1086 { 1087 int i; 1088 bus_dmamap_t dmamap; 1089 struct txdmamap_pool_entry *dma; 1090 1091 if (sc->bge_flags & BGE_TXRING_VALID) 1092 return 0; 1093 1094 sc->bge_txcnt = 0; 1095 sc->bge_tx_saved_considx = 0; 1096 1097 /* Initialize transmit producer index for host-memory send ring. */ 1098 sc->bge_tx_prodidx = 0; 1099 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx); 1100 if (sc->bge_quirks & BGE_QUIRK_PRODUCER_BUG) /* 5700 b2 errata */ 1101 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx); 1102 1103 /* NIC-memory send ring not used; initialize to zero. */ 1104 CSR_WRITE_4(sc, BGE_MBX_TX_NIC_PROD0_LO, 0); 1105 if (sc->bge_quirks & BGE_QUIRK_PRODUCER_BUG) /* 5700 b2 errata */ 1106 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, 0); 1107 1108 SLIST_INIT(&sc->txdma_list); 1109 for (i = 0; i < BGE_RSLOTS; i++) { 1110 if (bus_dmamap_create(sc->bge_dmatag, BGE_TXDMA_MAX, 1111 BGE_NTXSEG, ETHER_MAX_LEN_JUMBO, 0, BUS_DMA_NOWAIT, 1112 &dmamap)) 1113 return(ENOBUFS); 1114 if (dmamap == NULL) 1115 panic("dmamap NULL in bge_init_tx_ring"); 1116 dma = malloc(sizeof(*dma), M_DEVBUF, M_NOWAIT); 1117 if (dma == NULL) { 1118 printf("%s: can't alloc txdmamap_pool_entry\n", 1119 sc->bge_dev.dv_xname); 1120 bus_dmamap_destroy(sc->bge_dmatag, dmamap); 1121 return (ENOMEM); 1122 } 1123 dma->dmamap = dmamap; 1124 SLIST_INSERT_HEAD(&sc->txdma_list, dma, link); 1125 } 1126 1127 sc->bge_flags |= BGE_TXRING_VALID; 1128 1129 return(0); 1130 } 1131 1132 static void 1133 bge_setmulti(struct bge_softc *sc) 1134 { 1135 struct ethercom *ac = &sc->ethercom; 1136 struct ifnet *ifp = &ac->ec_if; 1137 struct ether_multi *enm; 1138 struct ether_multistep step; 1139 u_int32_t hashes[4] = { 0, 0, 0, 0 }; 1140 u_int32_t h; 1141 int i; 1142 1143 if (ifp->if_flags & IFF_PROMISC) 1144 goto allmulti; 1145 1146 /* Now program new ones. */ 1147 ETHER_FIRST_MULTI(step, ac, enm); 1148 while (enm != NULL) { 1149 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1150 /* 1151 * We must listen to a range of multicast addresses. 1152 * For now, just accept all multicasts, rather than 1153 * trying to set only those filter bits needed to match 1154 * the range. (At this time, the only use of address 1155 * ranges is for IP multicast routing, for which the 1156 * range is big enough to require all bits set.) 1157 */ 1158 goto allmulti; 1159 } 1160 1161 h = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN); 1162 1163 /* Just want the 7 least-significant bits. */ 1164 h &= 0x7f; 1165 1166 hashes[(h & 0x60) >> 5] |= 1 << (h & 0x1F); 1167 ETHER_NEXT_MULTI(step, enm); 1168 } 1169 1170 ifp->if_flags &= ~IFF_ALLMULTI; 1171 goto setit; 1172 1173 allmulti: 1174 ifp->if_flags |= IFF_ALLMULTI; 1175 hashes[0] = hashes[1] = hashes[2] = hashes[3] = 0xffffffff; 1176 1177 setit: 1178 for (i = 0; i < 4; i++) 1179 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]); 1180 } 1181 1182 const int bge_swapbits[] = { 1183 0, 1184 BGE_MODECTL_BYTESWAP_DATA, 1185 BGE_MODECTL_WORDSWAP_DATA, 1186 BGE_MODECTL_BYTESWAP_NONFRAME, 1187 BGE_MODECTL_WORDSWAP_NONFRAME, 1188 1189 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA, 1190 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_BYTESWAP_NONFRAME, 1191 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_NONFRAME, 1192 1193 BGE_MODECTL_WORDSWAP_DATA|BGE_MODECTL_BYTESWAP_NONFRAME, 1194 BGE_MODECTL_WORDSWAP_DATA|BGE_MODECTL_WORDSWAP_NONFRAME, 1195 1196 BGE_MODECTL_BYTESWAP_NONFRAME|BGE_MODECTL_WORDSWAP_NONFRAME, 1197 1198 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA| 1199 BGE_MODECTL_BYTESWAP_NONFRAME, 1200 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA| 1201 BGE_MODECTL_WORDSWAP_NONFRAME, 1202 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_BYTESWAP_NONFRAME| 1203 BGE_MODECTL_WORDSWAP_NONFRAME, 1204 BGE_MODECTL_WORDSWAP_DATA|BGE_MODECTL_BYTESWAP_NONFRAME| 1205 BGE_MODECTL_WORDSWAP_NONFRAME, 1206 1207 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA| 1208 BGE_MODECTL_BYTESWAP_NONFRAME|BGE_MODECTL_WORDSWAP_NONFRAME, 1209 }; 1210 1211 int bge_swapindex = 0; 1212 1213 /* 1214 * Do endian, PCI and DMA initialization. Also check the on-board ROM 1215 * self-test results. 1216 */ 1217 static int 1218 bge_chipinit(struct bge_softc *sc) 1219 { 1220 u_int32_t cachesize; 1221 int i; 1222 u_int32_t dma_rw_ctl; 1223 struct pci_attach_args *pa = &(sc->bge_pa); 1224 1225 1226 /* Set endianness before we access any non-PCI registers. */ 1227 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_MISC_CTL, 1228 BGE_INIT); 1229 1230 /* Set power state to D0. */ 1231 bge_setpowerstate(sc, 0); 1232 1233 /* 1234 * Check the 'ROM failed' bit on the RX CPU to see if 1235 * self-tests passed. 1236 */ 1237 if (CSR_READ_4(sc, BGE_RXCPU_MODE) & BGE_RXCPUMODE_ROMFAIL) { 1238 printf("%s: RX CPU self-diagnostics failed!\n", 1239 sc->bge_dev.dv_xname); 1240 return(ENODEV); 1241 } 1242 1243 /* Clear the MAC control register */ 1244 CSR_WRITE_4(sc, BGE_MAC_MODE, 0); 1245 1246 /* 1247 * Clear the MAC statistics block in the NIC's 1248 * internal memory. 1249 */ 1250 for (i = BGE_STATS_BLOCK; 1251 i < BGE_STATS_BLOCK_END + 1; i += sizeof(u_int32_t)) 1252 BGE_MEMWIN_WRITE(pa->pa_pc, pa->pa_tag, i, 0); 1253 1254 for (i = BGE_STATUS_BLOCK; 1255 i < BGE_STATUS_BLOCK_END + 1; i += sizeof(u_int32_t)) 1256 BGE_MEMWIN_WRITE(pa->pa_pc, pa->pa_tag, i, 0); 1257 1258 /* Set up the PCI DMA control register. */ 1259 if (sc->bge_pcie) { 1260 u_int32_t device_ctl; 1261 1262 /* From FreeBSD */ 1263 DPRINTFN(4, ("(%s: PCI-Express DMA setting)\n", 1264 sc->bge_dev.dv_xname)); 1265 dma_rw_ctl = (BGE_PCI_READ_CMD | BGE_PCI_WRITE_CMD | 1266 (0xf << BGE_PCIDMARWCTL_RD_WAT_SHIFT) | 1267 (0x2 << BGE_PCIDMARWCTL_WR_WAT_SHIFT)); 1268 1269 /* jonathan: alternative from Linux driver */ 1270 #define DMA_CTRL_WRITE_PCIE_H20MARK_128 0x00180000 1271 #define DMA_CTRL_WRITE_PCIE_H20MARK_256 0x00380000 1272 1273 dma_rw_ctl = 0x76000000; /* XXX XXX XXX */; 1274 device_ctl = pci_conf_read(pa->pa_pc, pa->pa_tag, 1275 BGE_PCI_CONF_DEV_CTRL); 1276 aprint_debug("%s: pcie mode=0x%x\n", sc->bge_dev.dv_xname, 1277 device_ctl); 1278 1279 if ((device_ctl & 0x00e0) && 0) { 1280 /* 1281 * XXX jonathan (at) NetBSD.org: 1282 * This clause is exactly what the Broadcom-supplied 1283 * Linux does; but given overall register programming 1284 * by if_bge(4), this larger DMA-write watermark 1285 * value causes bcm5721 chips to totally wedge. 1286 */ 1287 dma_rw_ctl |= BGE_PCIDMA_RWCTL_PCIE_WRITE_WATRMARK_256; 1288 } else { 1289 dma_rw_ctl |= BGE_PCIDMA_RWCTL_PCIE_WRITE_WATRMARK_128; 1290 } 1291 } else if (pci_conf_read(pa->pa_pc, pa->pa_tag,BGE_PCI_PCISTATE) & 1292 BGE_PCISTATE_PCI_BUSMODE) { 1293 /* Conventional PCI bus */ 1294 DPRINTFN(4, ("(%s: PCI 2.2 DMA setting)\n", sc->bge_dev.dv_xname)); 1295 dma_rw_ctl = (BGE_PCI_READ_CMD | BGE_PCI_WRITE_CMD | 1296 (0x7 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) | 1297 (0x7 << BGE_PCIDMARWCTL_WR_WAT_SHIFT)); 1298 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 1299 dma_rw_ctl |= 0x0F; 1300 } 1301 } else { 1302 DPRINTFN(4, ("(:%s: PCI-X DMA setting)\n", sc->bge_dev.dv_xname)); 1303 /* PCI-X bus */ 1304 dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD | 1305 (0x3 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) | 1306 (0x3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT) | 1307 (0x0F); 1308 /* 1309 * 5703 and 5704 need ONEDMA_AT_ONCE as a workaround 1310 * for hardware bugs, which means we should also clear 1311 * the low-order MINDMA bits. In addition, the 5704 1312 * uses a different encoding of read/write watermarks. 1313 */ 1314 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) { 1315 dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD | 1316 /* should be 0x1f0000 */ 1317 (0x7 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) | 1318 (0x3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT); 1319 dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE; 1320 } 1321 else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5703) { 1322 dma_rw_ctl &= 0xfffffff0; 1323 dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE; 1324 } 1325 else if (BGE_IS_5714_FAMILY(sc)) { 1326 dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD; 1327 dma_rw_ctl &= ~BGE_PCIDMARWCTL_ONEDMA_ATONCE; /* XXX */ 1328 /* XXX magic values, Broadcom-supplied Linux driver */ 1329 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5780) 1330 dma_rw_ctl |= (1 << 20) | (1 << 18) | 1331 BGE_PCIDMARWCTL_ONEDMA_ATONCE; 1332 else 1333 dma_rw_ctl |= (1<<20) | (1<<18) | (1 << 15); 1334 } 1335 } 1336 1337 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_DMA_RW_CTL, dma_rw_ctl); 1338 1339 /* 1340 * Set up general mode register. 1341 */ 1342 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS| 1343 BGE_MODECTL_MAC_ATTN_INTR|BGE_MODECTL_HOST_SEND_BDS| 1344 BGE_MODECTL_TX_NO_PHDR_CSUM|BGE_MODECTL_RX_NO_PHDR_CSUM); 1345 1346 /* Get cache line size. */ 1347 cachesize = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_CACHESZ); 1348 1349 /* 1350 * Avoid violating PCI spec on certain chip revs. 1351 */ 1352 if (pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_CMD) & 1353 PCIM_CMD_MWIEN) { 1354 switch(cachesize) { 1355 case 1: 1356 PCI_SETBIT(pa->pa_pc, pa->pa_tag, BGE_PCI_DMA_RW_CTL, 1357 BGE_PCI_WRITE_BNDRY_16BYTES); 1358 break; 1359 case 2: 1360 PCI_SETBIT(pa->pa_pc, pa->pa_tag, BGE_PCI_DMA_RW_CTL, 1361 BGE_PCI_WRITE_BNDRY_32BYTES); 1362 break; 1363 case 4: 1364 PCI_SETBIT(pa->pa_pc, pa->pa_tag, BGE_PCI_DMA_RW_CTL, 1365 BGE_PCI_WRITE_BNDRY_64BYTES); 1366 break; 1367 case 8: 1368 PCI_SETBIT(pa->pa_pc, pa->pa_tag, BGE_PCI_DMA_RW_CTL, 1369 BGE_PCI_WRITE_BNDRY_128BYTES); 1370 break; 1371 case 16: 1372 PCI_SETBIT(pa->pa_pc, pa->pa_tag, BGE_PCI_DMA_RW_CTL, 1373 BGE_PCI_WRITE_BNDRY_256BYTES); 1374 break; 1375 case 32: 1376 PCI_SETBIT(pa->pa_pc, pa->pa_tag, BGE_PCI_DMA_RW_CTL, 1377 BGE_PCI_WRITE_BNDRY_512BYTES); 1378 break; 1379 case 64: 1380 PCI_SETBIT(pa->pa_pc, pa->pa_tag, BGE_PCI_DMA_RW_CTL, 1381 BGE_PCI_WRITE_BNDRY_1024BYTES); 1382 break; 1383 default: 1384 /* Disable PCI memory write and invalidate. */ 1385 #if 0 1386 if (bootverbose) 1387 printf("%s: cache line size %d not " 1388 "supported; disabling PCI MWI\n", 1389 sc->bge_dev.dv_xname, cachesize); 1390 #endif 1391 PCI_CLRBIT(pa->pa_pc, pa->pa_tag, BGE_PCI_CMD, 1392 PCIM_CMD_MWIEN); 1393 break; 1394 } 1395 } 1396 1397 /* 1398 * Disable memory write invalidate. Apparently it is not supported 1399 * properly by these devices. 1400 */ 1401 PCI_CLRBIT(pa->pa_pc, pa->pa_tag, BGE_PCI_CMD, PCIM_CMD_MWIEN); 1402 1403 1404 #ifdef __brokenalpha__ 1405 /* 1406 * Must insure that we do not cross an 8K (bytes) boundary 1407 * for DMA reads. Our highest limit is 1K bytes. This is a 1408 * restriction on some ALPHA platforms with early revision 1409 * 21174 PCI chipsets, such as the AlphaPC 164lx 1410 */ 1411 PCI_SETBIT(sc, BGE_PCI_DMA_RW_CTL, BGE_PCI_READ_BNDRY_1024, 4); 1412 #endif 1413 1414 /* Set the timer prescaler (always 66MHz) */ 1415 CSR_WRITE_4(sc, BGE_MISC_CFG, 65 << 1/*BGE_32BITTIME_66MHZ*/); 1416 1417 return(0); 1418 } 1419 1420 static int 1421 bge_blockinit(struct bge_softc *sc) 1422 { 1423 volatile struct bge_rcb *rcb; 1424 bus_size_t rcb_addr; 1425 int i; 1426 struct ifnet *ifp = &sc->ethercom.ec_if; 1427 bge_hostaddr taddr; 1428 1429 /* 1430 * Initialize the memory window pointer register so that 1431 * we can access the first 32K of internal NIC RAM. This will 1432 * allow us to set up the TX send ring RCBs and the RX return 1433 * ring RCBs, plus other things which live in NIC memory. 1434 */ 1435 1436 pci_conf_write(sc->bge_pa.pa_pc, sc->bge_pa.pa_tag, 1437 BGE_PCI_MEMWIN_BASEADDR, 0); 1438 1439 /* Configure mbuf memory pool */ 1440 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 1441 if (sc->bge_extram) { 1442 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, 1443 BGE_EXT_SSRAM); 1444 if ((sc->bge_quirks & BGE_QUIRK_FEWER_MBUFS) != 0) 1445 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000); 1446 else 1447 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000); 1448 } else { 1449 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, 1450 BGE_BUFFPOOL_1); 1451 if ((sc->bge_quirks & BGE_QUIRK_FEWER_MBUFS) != 0) 1452 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000); 1453 else 1454 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000); 1455 } 1456 1457 /* Configure DMA resource pool */ 1458 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_BASEADDR, 1459 BGE_DMA_DESCRIPTORS); 1460 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LEN, 0x2000); 1461 } 1462 1463 /* Configure mbuf pool watermarks */ 1464 #ifdef ORIG_WPAUL_VALUES 1465 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 24); 1466 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 24); 1467 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 48); 1468 #else 1469 /* new broadcom docs strongly recommend these: */ 1470 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 1471 if (ifp->if_mtu > ETHER_MAX_LEN) { 1472 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x50); 1473 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x20); 1474 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60); 1475 } else { 1476 /* Values from Linux driver... */ 1477 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 304); 1478 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 152); 1479 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 380); 1480 } 1481 } else { 1482 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0); 1483 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x10); 1484 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60); 1485 } 1486 #endif 1487 1488 /* Configure DMA resource watermarks */ 1489 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5); 1490 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10); 1491 1492 /* Enable buffer manager */ 1493 CSR_WRITE_4(sc, BGE_BMAN_MODE, 1494 BGE_BMANMODE_ENABLE|BGE_BMANMODE_LOMBUF_ATTN); 1495 1496 /* Poll for buffer manager start indication */ 1497 for (i = 0; i < BGE_TIMEOUT; i++) { 1498 if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE) 1499 break; 1500 DELAY(10); 1501 } 1502 1503 if (i == BGE_TIMEOUT) { 1504 printf("%s: buffer manager failed to start\n", 1505 sc->bge_dev.dv_xname); 1506 return(ENXIO); 1507 } 1508 1509 /* Enable flow-through queues */ 1510 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 1511 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 1512 1513 /* Wait until queue initialization is complete */ 1514 for (i = 0; i < BGE_TIMEOUT; i++) { 1515 if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0) 1516 break; 1517 DELAY(10); 1518 } 1519 1520 if (i == BGE_TIMEOUT) { 1521 printf("%s: flow-through queue init failed\n", 1522 sc->bge_dev.dv_xname); 1523 return(ENXIO); 1524 } 1525 1526 /* Initialize the standard RX ring control block */ 1527 rcb = &sc->bge_rdata->bge_info.bge_std_rx_rcb; 1528 bge_set_hostaddr(&rcb->bge_hostaddr, 1529 BGE_RING_DMA_ADDR(sc, bge_rx_std_ring)); 1530 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 1531 rcb->bge_maxlen_flags = 1532 BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 0); 1533 } else { 1534 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(512, 0); 1535 } 1536 if (sc->bge_extram) 1537 rcb->bge_nicaddr = BGE_EXT_STD_RX_RINGS; 1538 else 1539 rcb->bge_nicaddr = BGE_STD_RX_RINGS; 1540 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcb->bge_hostaddr.bge_addr_hi); 1541 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcb->bge_hostaddr.bge_addr_lo); 1542 CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 1543 CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcb->bge_nicaddr); 1544 1545 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 1546 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT; 1547 } else { 1548 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT_5705; 1549 } 1550 1551 /* 1552 * Initialize the jumbo RX ring control block 1553 * We set the 'ring disabled' bit in the flags 1554 * field until we're actually ready to start 1555 * using this ring (i.e. once we set the MTU 1556 * high enough to require it). 1557 */ 1558 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 1559 rcb = &sc->bge_rdata->bge_info.bge_jumbo_rx_rcb; 1560 bge_set_hostaddr(&rcb->bge_hostaddr, 1561 BGE_RING_DMA_ADDR(sc, bge_rx_jumbo_ring)); 1562 rcb->bge_maxlen_flags = 1563 BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 1564 BGE_RCB_FLAG_RING_DISABLED); 1565 if (sc->bge_extram) 1566 rcb->bge_nicaddr = BGE_EXT_JUMBO_RX_RINGS; 1567 else 1568 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS; 1569 1570 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI, 1571 rcb->bge_hostaddr.bge_addr_hi); 1572 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO, 1573 rcb->bge_hostaddr.bge_addr_lo); 1574 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, 1575 rcb->bge_maxlen_flags); 1576 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcb->bge_nicaddr); 1577 1578 /* Set up dummy disabled mini ring RCB */ 1579 rcb = &sc->bge_rdata->bge_info.bge_mini_rx_rcb; 1580 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0, 1581 BGE_RCB_FLAG_RING_DISABLED); 1582 CSR_WRITE_4(sc, BGE_RX_MINI_RCB_MAXLEN_FLAGS, 1583 rcb->bge_maxlen_flags); 1584 1585 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 1586 offsetof(struct bge_ring_data, bge_info), 1587 sizeof (struct bge_gib), 1588 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1589 } 1590 1591 /* 1592 * Set the BD ring replenish thresholds. The recommended 1593 * values are 1/8th the number of descriptors allocated to 1594 * each ring. 1595 */ 1596 i = BGE_STD_RX_RING_CNT / 8; 1597 1598 /* 1599 * Use a value of 8 for the following chips to workaround HW errata. 1600 * Some of these chips have been added based on empirical 1601 * evidence (they don't work unless this is done). 1602 */ 1603 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5750 || 1604 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5752 || 1605 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5755 || 1606 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5787) 1607 i = 8; 1608 1609 CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, i); 1610 CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH, BGE_JUMBO_RX_RING_CNT/8); 1611 1612 /* 1613 * Disable all unused send rings by setting the 'ring disabled' 1614 * bit in the flags field of all the TX send ring control blocks. 1615 * These are located in NIC memory. 1616 */ 1617 rcb_addr = BGE_MEMWIN_START + BGE_SEND_RING_RCB; 1618 for (i = 0; i < BGE_TX_RINGS_EXTSSRAM_MAX; i++) { 1619 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 1620 BGE_RCB_MAXLEN_FLAGS(0,BGE_RCB_FLAG_RING_DISABLED)); 1621 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 0); 1622 rcb_addr += sizeof(struct bge_rcb); 1623 } 1624 1625 /* Configure TX RCB 0 (we use only the first ring) */ 1626 rcb_addr = BGE_MEMWIN_START + BGE_SEND_RING_RCB; 1627 bge_set_hostaddr(&taddr, BGE_RING_DMA_ADDR(sc, bge_tx_ring)); 1628 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi); 1629 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo); 1630 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 1631 BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT)); 1632 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 1633 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 1634 BGE_RCB_MAXLEN_FLAGS(BGE_TX_RING_CNT, 0)); 1635 } 1636 1637 /* Disable all unused RX return rings */ 1638 rcb_addr = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB; 1639 for (i = 0; i < BGE_RX_RINGS_MAX; i++) { 1640 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_hi, 0); 1641 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_lo, 0); 1642 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 1643 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 1644 BGE_RCB_FLAG_RING_DISABLED)); 1645 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 0); 1646 CSR_WRITE_4(sc, BGE_MBX_RX_CONS0_LO + 1647 (i * (sizeof(u_int64_t))), 0); 1648 rcb_addr += sizeof(struct bge_rcb); 1649 } 1650 1651 /* Initialize RX ring indexes */ 1652 CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, 0); 1653 CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0); 1654 CSR_WRITE_4(sc, BGE_MBX_RX_MINI_PROD_LO, 0); 1655 1656 /* 1657 * Set up RX return ring 0 1658 * Note that the NIC address for RX return rings is 0x00000000. 1659 * The return rings live entirely within the host, so the 1660 * nicaddr field in the RCB isn't used. 1661 */ 1662 rcb_addr = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB; 1663 bge_set_hostaddr(&taddr, BGE_RING_DMA_ADDR(sc, bge_rx_return_ring)); 1664 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi); 1665 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo); 1666 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 0x00000000); 1667 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 1668 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 0)); 1669 1670 /* Set random backoff seed for TX */ 1671 CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF, 1672 LLADDR(ifp->if_sadl)[0] + LLADDR(ifp->if_sadl)[1] + 1673 LLADDR(ifp->if_sadl)[2] + LLADDR(ifp->if_sadl)[3] + 1674 LLADDR(ifp->if_sadl)[4] + LLADDR(ifp->if_sadl)[5] + 1675 BGE_TX_BACKOFF_SEED_MASK); 1676 1677 /* Set inter-packet gap */ 1678 CSR_WRITE_4(sc, BGE_TX_LENGTHS, 0x2620); 1679 1680 /* 1681 * Specify which ring to use for packets that don't match 1682 * any RX rules. 1683 */ 1684 CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08); 1685 1686 /* 1687 * Configure number of RX lists. One interrupt distribution 1688 * list, sixteen active lists, one bad frames class. 1689 */ 1690 CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181); 1691 1692 /* Inialize RX list placement stats mask. */ 1693 CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF); 1694 CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1); 1695 1696 /* Disable host coalescing until we get it set up */ 1697 CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000); 1698 1699 /* Poll to make sure it's shut down. */ 1700 for (i = 0; i < BGE_TIMEOUT; i++) { 1701 if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE)) 1702 break; 1703 DELAY(10); 1704 } 1705 1706 if (i == BGE_TIMEOUT) { 1707 printf("%s: host coalescing engine failed to idle\n", 1708 sc->bge_dev.dv_xname); 1709 return(ENXIO); 1710 } 1711 1712 /* Set up host coalescing defaults */ 1713 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bge_rx_coal_ticks); 1714 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bge_tx_coal_ticks); 1715 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bge_rx_max_coal_bds); 1716 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bge_tx_max_coal_bds); 1717 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 1718 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT, 0); 1719 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT, 0); 1720 } 1721 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 0); 1722 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 0); 1723 1724 /* Set up address of statistics block */ 1725 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 1726 bge_set_hostaddr(&taddr, 1727 BGE_RING_DMA_ADDR(sc, bge_info.bge_stats)); 1728 CSR_WRITE_4(sc, BGE_HCC_STATS_TICKS, sc->bge_stat_ticks); 1729 CSR_WRITE_4(sc, BGE_HCC_STATS_BASEADDR, BGE_STATS_BLOCK); 1730 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_HI, taddr.bge_addr_hi); 1731 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_LO, taddr.bge_addr_lo); 1732 } 1733 1734 /* Set up address of status block */ 1735 bge_set_hostaddr(&taddr, BGE_RING_DMA_ADDR(sc, bge_status_block)); 1736 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_BASEADDR, BGE_STATUS_BLOCK); 1737 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI, taddr.bge_addr_hi); 1738 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO, taddr.bge_addr_lo); 1739 sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx = 0; 1740 sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx = 0; 1741 1742 /* Turn on host coalescing state machine */ 1743 CSR_WRITE_4(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE); 1744 1745 /* Turn on RX BD completion state machine and enable attentions */ 1746 CSR_WRITE_4(sc, BGE_RBDC_MODE, 1747 BGE_RBDCMODE_ENABLE|BGE_RBDCMODE_ATTN); 1748 1749 /* Turn on RX list placement state machine */ 1750 CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 1751 1752 /* Turn on RX list selector state machine. */ 1753 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 1754 CSR_WRITE_4(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 1755 } 1756 1757 /* Turn on DMA, clear stats */ 1758 CSR_WRITE_4(sc, BGE_MAC_MODE, BGE_MACMODE_TXDMA_ENB| 1759 BGE_MACMODE_RXDMA_ENB|BGE_MACMODE_RX_STATS_CLEAR| 1760 BGE_MACMODE_TX_STATS_CLEAR|BGE_MACMODE_RX_STATS_ENB| 1761 BGE_MACMODE_TX_STATS_ENB|BGE_MACMODE_FRMHDR_DMA_ENB| 1762 (sc->bge_tbi ? BGE_PORTMODE_TBI : BGE_PORTMODE_MII)); 1763 1764 /* Set misc. local control, enable interrupts on attentions */ 1765 sc->bge_local_ctrl_reg = BGE_MLC_INTR_ONATTN | BGE_MLC_AUTO_EEPROM; 1766 1767 #ifdef notdef 1768 /* Assert GPIO pins for PHY reset */ 1769 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUT0| 1770 BGE_MLC_MISCIO_OUT1|BGE_MLC_MISCIO_OUT2); 1771 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUTEN0| 1772 BGE_MLC_MISCIO_OUTEN1|BGE_MLC_MISCIO_OUTEN2); 1773 #endif 1774 1775 #if defined(not_quite_yet) 1776 /* Linux driver enables enable gpio pin #1 on 5700s */ 1777 if (sc->bge_chipid == BGE_CHIPID_BCM5700) { 1778 sc->bge_local_ctrl_reg |= 1779 (BGE_MLC_MISCIO_OUT1|BGE_MLC_MISCIO_OUTEN1); 1780 } 1781 #endif 1782 CSR_WRITE_4(sc, BGE_MISC_LOCAL_CTL, sc->bge_local_ctrl_reg); 1783 1784 /* Turn on DMA completion state machine */ 1785 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 1786 CSR_WRITE_4(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 1787 } 1788 1789 /* Turn on write DMA state machine */ 1790 { 1791 uint32_t bge_wdma_mode = 1792 BGE_WDMAMODE_ENABLE|BGE_WDMAMODE_ALL_ATTNS; 1793 1794 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5755 || 1795 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5787) 1796 /* Enable host coalescing bug fix; see Linux tg3.c */ 1797 bge_wdma_mode |= (1 << 29); 1798 1799 CSR_WRITE_4(sc, BGE_WDMA_MODE, bge_wdma_mode); 1800 } 1801 1802 /* Turn on read DMA state machine */ 1803 { 1804 uint32_t dma_read_modebits; 1805 1806 dma_read_modebits = 1807 BGE_RDMAMODE_ENABLE | BGE_RDMAMODE_ALL_ATTNS; 1808 1809 if (sc->bge_pcie && 0) { 1810 dma_read_modebits |= BGE_RDMA_MODE_FIFO_LONG_BURST; 1811 } else if ((sc->bge_quirks & BGE_QUIRK_5705_CORE)) { 1812 dma_read_modebits |= BGE_RDMA_MODE_FIFO_SIZE_128; 1813 } 1814 1815 /* XXX broadcom-supplied linux driver; undocumented */ 1816 if (BGE_IS_5750_OR_BEYOND(sc)) { 1817 /* 1818 * XXX: magic values. 1819 * From Broadcom-supplied Linux driver; apparently 1820 * required to workaround a DMA bug affecting TSO 1821 * on bcm575x/bcm5721? 1822 */ 1823 dma_read_modebits |= (1 << 27); 1824 } 1825 CSR_WRITE_4(sc, BGE_RDMA_MODE, dma_read_modebits); 1826 } 1827 1828 /* Turn on RX data completion state machine */ 1829 CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 1830 1831 /* Turn on RX BD initiator state machine */ 1832 CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 1833 1834 /* Turn on RX data and RX BD initiator state machine */ 1835 CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE); 1836 1837 /* Turn on Mbuf cluster free state machine */ 1838 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 1839 CSR_WRITE_4(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 1840 } 1841 1842 /* Turn on send BD completion state machine */ 1843 CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 1844 1845 /* Turn on send data completion state machine */ 1846 CSR_WRITE_4(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE); 1847 1848 /* Turn on send data initiator state machine */ 1849 if (BGE_IS_5750_OR_BEYOND(sc)) { 1850 /* XXX: magic value from Linux driver */ 1851 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE | 0x08); 1852 } else { 1853 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 1854 } 1855 1856 /* Turn on send BD initiator state machine */ 1857 CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 1858 1859 /* Turn on send BD selector state machine */ 1860 CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 1861 1862 CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF); 1863 CSR_WRITE_4(sc, BGE_SDI_STATS_CTL, 1864 BGE_SDISTATSCTL_ENABLE|BGE_SDISTATSCTL_FASTER); 1865 1866 /* ack/clear link change events */ 1867 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED| 1868 BGE_MACSTAT_CFG_CHANGED); 1869 CSR_WRITE_4(sc, BGE_MI_STS, 0); 1870 1871 /* Enable PHY auto polling (for MII/GMII only) */ 1872 if (sc->bge_tbi) { 1873 CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK); 1874 } else { 1875 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL|10<<16); 1876 if (sc->bge_quirks & BGE_QUIRK_LINK_STATE_BROKEN) 1877 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, 1878 BGE_EVTENB_MI_INTERRUPT); 1879 } 1880 1881 /* Enable link state change attentions. */ 1882 BGE_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED); 1883 1884 return(0); 1885 } 1886 1887 static const struct bge_revision { 1888 uint32_t br_chipid; 1889 uint32_t br_quirks; 1890 const char *br_name; 1891 } bge_revisions[] = { 1892 { BGE_CHIPID_BCM5700_A0, 1893 BGE_QUIRK_LINK_STATE_BROKEN, 1894 "BCM5700 A0" }, 1895 1896 { BGE_CHIPID_BCM5700_A1, 1897 BGE_QUIRK_LINK_STATE_BROKEN, 1898 "BCM5700 A1" }, 1899 1900 { BGE_CHIPID_BCM5700_B0, 1901 BGE_QUIRK_LINK_STATE_BROKEN|BGE_QUIRK_CSUM_BROKEN|BGE_QUIRK_5700_COMMON, 1902 "BCM5700 B0" }, 1903 1904 { BGE_CHIPID_BCM5700_B1, 1905 BGE_QUIRK_LINK_STATE_BROKEN|BGE_QUIRK_5700_COMMON, 1906 "BCM5700 B1" }, 1907 1908 { BGE_CHIPID_BCM5700_B2, 1909 BGE_QUIRK_LINK_STATE_BROKEN|BGE_QUIRK_5700_COMMON, 1910 "BCM5700 B2" }, 1911 1912 { BGE_CHIPID_BCM5700_B3, 1913 BGE_QUIRK_LINK_STATE_BROKEN|BGE_QUIRK_5700_COMMON, 1914 "BCM5700 B3" }, 1915 1916 /* This is treated like a BCM5700 Bx */ 1917 { BGE_CHIPID_BCM5700_ALTIMA, 1918 BGE_QUIRK_LINK_STATE_BROKEN|BGE_QUIRK_5700_COMMON, 1919 "BCM5700 Altima" }, 1920 1921 { BGE_CHIPID_BCM5700_C0, 1922 0, 1923 "BCM5700 C0" }, 1924 1925 { BGE_CHIPID_BCM5701_A0, 1926 0, /*XXX really, just not known */ 1927 "BCM5701 A0" }, 1928 1929 { BGE_CHIPID_BCM5701_B0, 1930 BGE_QUIRK_PCIX_DMA_ALIGN_BUG, 1931 "BCM5701 B0" }, 1932 1933 { BGE_CHIPID_BCM5701_B2, 1934 BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_PCIX_DMA_ALIGN_BUG, 1935 "BCM5701 B2" }, 1936 1937 { BGE_CHIPID_BCM5701_B5, 1938 BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_PCIX_DMA_ALIGN_BUG, 1939 "BCM5701 B5" }, 1940 1941 { BGE_CHIPID_BCM5703_A0, 1942 0, 1943 "BCM5703 A0" }, 1944 1945 { BGE_CHIPID_BCM5703_A1, 1946 0, 1947 "BCM5703 A1" }, 1948 1949 { BGE_CHIPID_BCM5703_A2, 1950 BGE_QUIRK_ONLY_PHY_1, 1951 "BCM5703 A2" }, 1952 1953 { BGE_CHIPID_BCM5703_A3, 1954 BGE_QUIRK_ONLY_PHY_1, 1955 "BCM5703 A3" }, 1956 1957 { BGE_CHIPID_BCM5703_B0, 1958 BGE_QUIRK_ONLY_PHY_1, 1959 "BCM5703 B0" }, 1960 1961 { BGE_CHIPID_BCM5704_A0, 1962 BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_FEWER_MBUFS, 1963 "BCM5704 A0" }, 1964 1965 { BGE_CHIPID_BCM5704_A1, 1966 BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_FEWER_MBUFS, 1967 "BCM5704 A1" }, 1968 1969 { BGE_CHIPID_BCM5704_A2, 1970 BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_FEWER_MBUFS, 1971 "BCM5704 A2" }, 1972 1973 { BGE_CHIPID_BCM5704_A3, 1974 BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_FEWER_MBUFS, 1975 "BCM5704 A3" }, 1976 1977 { BGE_CHIPID_BCM5705_A0, 1978 BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_5705_CORE, 1979 "BCM5705 A0" }, 1980 1981 { BGE_CHIPID_BCM5705_A1, 1982 BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_5705_CORE, 1983 "BCM5705 A1" }, 1984 1985 { BGE_CHIPID_BCM5705_A2, 1986 BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_5705_CORE, 1987 "BCM5705 A2" }, 1988 1989 { BGE_CHIPID_BCM5705_A3, 1990 BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_5705_CORE, 1991 "BCM5705 A3" }, 1992 1993 { BGE_CHIPID_BCM5750_A0, 1994 BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_5705_CORE, 1995 "BCM5750 A0" }, 1996 1997 { BGE_CHIPID_BCM5750_A1, 1998 BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_5705_CORE, 1999 "BCM5750 A1" }, 2000 2001 { BGE_CHIPID_BCM5751_A1, 2002 BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_5705_CORE, 2003 "BCM5751 A1" }, 2004 2005 { BGE_CHIPID_BCM5752_A0, 2006 BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_5705_CORE, 2007 "BCM5752 A0" }, 2008 2009 { BGE_CHIPID_BCM5752_A1, 2010 BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_5705_CORE, 2011 "BCM5752 A1" }, 2012 2013 { BGE_CHIPID_BCM5752_A2, 2014 BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_5705_CORE, 2015 "BCM5752 A2" }, 2016 2017 { BGE_CHIPID_BCM5787_A0, 2018 BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_5705_CORE, 2019 "BCM5754/5787 A0" }, 2020 2021 { BGE_CHIPID_BCM5787_A1, 2022 BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_5705_CORE, 2023 "BCM5754/5787 A1" }, 2024 2025 { BGE_CHIPID_BCM5787_A2, 2026 BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_5705_CORE, 2027 "BCM5754/5787 A2" }, 2028 2029 { 0, 0, NULL } 2030 }; 2031 2032 /* 2033 * Some defaults for major revisions, so that newer steppings 2034 * that we don't know about have a shot at working. 2035 */ 2036 static const struct bge_revision bge_majorrevs[] = { 2037 { BGE_ASICREV_BCM5700, 2038 BGE_QUIRK_LINK_STATE_BROKEN, 2039 "unknown BCM5700" }, 2040 2041 { BGE_ASICREV_BCM5701, 2042 BGE_QUIRK_PCIX_DMA_ALIGN_BUG, 2043 "unknown BCM5701" }, 2044 2045 { BGE_ASICREV_BCM5703, 2046 0, 2047 "unknown BCM5703" }, 2048 2049 { BGE_ASICREV_BCM5704, 2050 BGE_QUIRK_ONLY_PHY_1, 2051 "unknown BCM5704" }, 2052 2053 { BGE_ASICREV_BCM5705, 2054 BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_5705_CORE, 2055 "unknown BCM5705" }, 2056 2057 { BGE_ASICREV_BCM5750, 2058 BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_5705_CORE, 2059 "unknown BCM575x family" }, 2060 2061 { BGE_ASICREV_BCM5714_A0, 2062 BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_5705_CORE, 2063 "unknown BCM5714" }, 2064 2065 { BGE_ASICREV_BCM5714, 2066 BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_5705_CORE, 2067 "unknown BCM5714" }, 2068 2069 { BGE_ASICREV_BCM5752, 2070 BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_5705_CORE, 2071 "unknown BCM5752 family" }, 2072 2073 { BGE_ASICREV_BCM5755, 2074 BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_5705_CORE, 2075 "unknown BCM5755" }, 2076 2077 { BGE_ASICREV_BCM5780, 2078 BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_5705_CORE, 2079 "unknown BCM5780" }, 2080 2081 { BGE_ASICREV_BCM5787, 2082 BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_5705_CORE, 2083 "unknown BCM5787" }, 2084 2085 { 0, 2086 0, 2087 NULL } 2088 }; 2089 2090 2091 static const struct bge_revision * 2092 bge_lookup_rev(uint32_t chipid) 2093 { 2094 const struct bge_revision *br; 2095 2096 for (br = bge_revisions; br->br_name != NULL; br++) { 2097 if (br->br_chipid == chipid) 2098 return (br); 2099 } 2100 2101 for (br = bge_majorrevs; br->br_name != NULL; br++) { 2102 if (br->br_chipid == BGE_ASICREV(chipid)) 2103 return (br); 2104 } 2105 2106 return (NULL); 2107 } 2108 2109 static const struct bge_product { 2110 pci_vendor_id_t bp_vendor; 2111 pci_product_id_t bp_product; 2112 const char *bp_name; 2113 } bge_products[] = { 2114 /* 2115 * The BCM5700 documentation seems to indicate that the hardware 2116 * still has the Alteon vendor ID burned into it, though it 2117 * should always be overridden by the value in the EEPROM. We'll 2118 * check for it anyway. 2119 */ 2120 { PCI_VENDOR_ALTEON, 2121 PCI_PRODUCT_ALTEON_BCM5700, 2122 "Broadcom BCM5700 Gigabit Ethernet", 2123 }, 2124 { PCI_VENDOR_ALTEON, 2125 PCI_PRODUCT_ALTEON_BCM5701, 2126 "Broadcom BCM5701 Gigabit Ethernet", 2127 }, 2128 2129 { PCI_VENDOR_ALTIMA, 2130 PCI_PRODUCT_ALTIMA_AC1000, 2131 "Altima AC1000 Gigabit Ethernet", 2132 }, 2133 { PCI_VENDOR_ALTIMA, 2134 PCI_PRODUCT_ALTIMA_AC1001, 2135 "Altima AC1001 Gigabit Ethernet", 2136 }, 2137 { PCI_VENDOR_ALTIMA, 2138 PCI_PRODUCT_ALTIMA_AC9100, 2139 "Altima AC9100 Gigabit Ethernet", 2140 }, 2141 2142 { PCI_VENDOR_BROADCOM, 2143 PCI_PRODUCT_BROADCOM_BCM5700, 2144 "Broadcom BCM5700 Gigabit Ethernet", 2145 }, 2146 { PCI_VENDOR_BROADCOM, 2147 PCI_PRODUCT_BROADCOM_BCM5701, 2148 "Broadcom BCM5701 Gigabit Ethernet", 2149 }, 2150 { PCI_VENDOR_BROADCOM, 2151 PCI_PRODUCT_BROADCOM_BCM5702, 2152 "Broadcom BCM5702 Gigabit Ethernet", 2153 }, 2154 { PCI_VENDOR_BROADCOM, 2155 PCI_PRODUCT_BROADCOM_BCM5702X, 2156 "Broadcom BCM5702X Gigabit Ethernet" }, 2157 2158 { PCI_VENDOR_BROADCOM, 2159 PCI_PRODUCT_BROADCOM_BCM5703, 2160 "Broadcom BCM5703 Gigabit Ethernet", 2161 }, 2162 { PCI_VENDOR_BROADCOM, 2163 PCI_PRODUCT_BROADCOM_BCM5703X, 2164 "Broadcom BCM5703X Gigabit Ethernet", 2165 }, 2166 { PCI_VENDOR_BROADCOM, 2167 PCI_PRODUCT_BROADCOM_BCM5703_ALT, 2168 "Broadcom BCM5703 Gigabit Ethernet", 2169 }, 2170 2171 { PCI_VENDOR_BROADCOM, 2172 PCI_PRODUCT_BROADCOM_BCM5704C, 2173 "Broadcom BCM5704C Dual Gigabit Ethernet", 2174 }, 2175 { PCI_VENDOR_BROADCOM, 2176 PCI_PRODUCT_BROADCOM_BCM5704S, 2177 "Broadcom BCM5704S Dual Gigabit Ethernet", 2178 }, 2179 2180 { PCI_VENDOR_BROADCOM, 2181 PCI_PRODUCT_BROADCOM_BCM5705, 2182 "Broadcom BCM5705 Gigabit Ethernet", 2183 }, 2184 { PCI_VENDOR_BROADCOM, 2185 PCI_PRODUCT_BROADCOM_BCM5705K, 2186 "Broadcom BCM5705K Gigabit Ethernet", 2187 }, 2188 { PCI_VENDOR_BROADCOM, 2189 PCI_PRODUCT_BROADCOM_BCM5705M, 2190 "Broadcom BCM5705M Gigabit Ethernet", 2191 }, 2192 { PCI_VENDOR_BROADCOM, 2193 PCI_PRODUCT_BROADCOM_BCM5705M_ALT, 2194 "Broadcom BCM5705M Gigabit Ethernet", 2195 }, 2196 2197 { PCI_VENDOR_BROADCOM, 2198 PCI_PRODUCT_BROADCOM_BCM5714, 2199 "Broadcom BCM5714/5715 Gigabit Ethernet", 2200 }, 2201 { PCI_VENDOR_BROADCOM, 2202 PCI_PRODUCT_BROADCOM_BCM5715, 2203 "Broadcom BCM5714/5715 Gigabit Ethernet", 2204 }, 2205 { PCI_VENDOR_BROADCOM, 2206 PCI_PRODUCT_BROADCOM_BCM5789, 2207 "Broadcom BCM5789 Gigabit Ethernet", 2208 }, 2209 2210 { PCI_VENDOR_BROADCOM, 2211 PCI_PRODUCT_BROADCOM_BCM5721, 2212 "Broadcom BCM5721 Gigabit Ethernet", 2213 }, 2214 2215 { PCI_VENDOR_BROADCOM, 2216 PCI_PRODUCT_BROADCOM_BCM5750, 2217 "Broadcom BCM5750 Gigabit Ethernet", 2218 }, 2219 2220 { PCI_VENDOR_BROADCOM, 2221 PCI_PRODUCT_BROADCOM_BCM5750M, 2222 "Broadcom BCM5750M Gigabit Ethernet", 2223 }, 2224 2225 { PCI_VENDOR_BROADCOM, 2226 PCI_PRODUCT_BROADCOM_BCM5751, 2227 "Broadcom BCM5751 Gigabit Ethernet", 2228 }, 2229 2230 { PCI_VENDOR_BROADCOM, 2231 PCI_PRODUCT_BROADCOM_BCM5751M, 2232 "Broadcom BCM5751M Gigabit Ethernet", 2233 }, 2234 2235 { PCI_VENDOR_BROADCOM, 2236 PCI_PRODUCT_BROADCOM_BCM5752, 2237 "Broadcom BCM5752 Gigabit Ethernet", 2238 }, 2239 2240 { PCI_VENDOR_BROADCOM, 2241 PCI_PRODUCT_BROADCOM_BCM5752M, 2242 "Broadcom BCM5752M Gigabit Ethernet", 2243 }, 2244 2245 { PCI_VENDOR_BROADCOM, 2246 PCI_PRODUCT_BROADCOM_BCM5753, 2247 "Broadcom BCM5753 Gigabit Ethernet", 2248 }, 2249 2250 { PCI_VENDOR_BROADCOM, 2251 PCI_PRODUCT_BROADCOM_BCM5753M, 2252 "Broadcom BCM5753M Gigabit Ethernet", 2253 }, 2254 2255 { PCI_VENDOR_BROADCOM, 2256 PCI_PRODUCT_BROADCOM_BCM5754, 2257 "Broadcom BCM5754 Gigabit Ethernet", 2258 }, 2259 2260 { PCI_VENDOR_BROADCOM, 2261 PCI_PRODUCT_BROADCOM_BCM5754M, 2262 "Broadcom BCM5754M Gigabit Ethernet", 2263 }, 2264 2265 { PCI_VENDOR_BROADCOM, 2266 PCI_PRODUCT_BROADCOM_BCM5755, 2267 "Broadcom BCM5755 Gigabit Ethernet", 2268 }, 2269 2270 { PCI_VENDOR_BROADCOM, 2271 PCI_PRODUCT_BROADCOM_BCM5755M, 2272 "Broadcom BCM5755M Gigabit Ethernet", 2273 }, 2274 2275 { PCI_VENDOR_BROADCOM, 2276 PCI_PRODUCT_BROADCOM_BCM5780, 2277 "Broadcom BCM5780 Gigabit Ethernet", 2278 }, 2279 2280 { PCI_VENDOR_BROADCOM, 2281 PCI_PRODUCT_BROADCOM_BCM5780S, 2282 "Broadcom BCM5780S Gigabit Ethernet", 2283 }, 2284 2285 { PCI_VENDOR_BROADCOM, 2286 PCI_PRODUCT_BROADCOM_BCM5782, 2287 "Broadcom BCM5782 Gigabit Ethernet", 2288 }, 2289 2290 { PCI_VENDOR_BROADCOM, 2291 PCI_PRODUCT_BROADCOM_BCM5787, 2292 "Broadcom BCM5787 Gigabit Ethernet", 2293 }, 2294 2295 { PCI_VENDOR_BROADCOM, 2296 PCI_PRODUCT_BROADCOM_BCM5787M, 2297 "Broadcom BCM5787M Gigabit Ethernet", 2298 }, 2299 2300 { PCI_VENDOR_BROADCOM, 2301 PCI_PRODUCT_BROADCOM_BCM5788, 2302 "Broadcom BCM5788 Gigabit Ethernet", 2303 }, 2304 { PCI_VENDOR_BROADCOM, 2305 PCI_PRODUCT_BROADCOM_BCM5789, 2306 "Broadcom BCM5789 Gigabit Ethernet", 2307 }, 2308 2309 { PCI_VENDOR_BROADCOM, 2310 PCI_PRODUCT_BROADCOM_BCM5901, 2311 "Broadcom BCM5901 Fast Ethernet", 2312 }, 2313 { PCI_VENDOR_BROADCOM, 2314 PCI_PRODUCT_BROADCOM_BCM5901A2, 2315 "Broadcom BCM5901A2 Fast Ethernet", 2316 }, 2317 2318 { PCI_VENDOR_SCHNEIDERKOCH, 2319 PCI_PRODUCT_SCHNEIDERKOCH_SK_9DX1, 2320 "SysKonnect SK-9Dx1 Gigabit Ethernet", 2321 }, 2322 2323 { PCI_VENDOR_3COM, 2324 PCI_PRODUCT_3COM_3C996, 2325 "3Com 3c996 Gigabit Ethernet", 2326 }, 2327 2328 { 0, 2329 0, 2330 NULL }, 2331 }; 2332 2333 static const struct bge_product * 2334 bge_lookup(const struct pci_attach_args *pa) 2335 { 2336 const struct bge_product *bp; 2337 2338 for (bp = bge_products; bp->bp_name != NULL; bp++) { 2339 if (PCI_VENDOR(pa->pa_id) == bp->bp_vendor && 2340 PCI_PRODUCT(pa->pa_id) == bp->bp_product) 2341 return (bp); 2342 } 2343 2344 return (NULL); 2345 } 2346 2347 static int 2348 bge_setpowerstate(struct bge_softc *sc, int powerlevel) 2349 { 2350 #ifdef NOTYET 2351 u_int32_t pm_ctl = 0; 2352 2353 /* XXX FIXME: make sure indirect accesses enabled? */ 2354 pm_ctl = pci_conf_read(sc->bge_dev, BGE_PCI_MISC_CTL, 4); 2355 pm_ctl |= BGE_PCIMISCCTL_INDIRECT_ACCESS; 2356 pci_write_config(sc->bge_dev, BGE_PCI_MISC_CTL, pm_ctl, 4); 2357 2358 /* clear the PME_assert bit and power state bits, enable PME */ 2359 pm_ctl = pci_conf_read(sc->bge_dev, BGE_PCI_PWRMGMT_CMD, 2); 2360 pm_ctl &= ~PCIM_PSTAT_DMASK; 2361 pm_ctl |= (1 << 8); 2362 2363 if (powerlevel == 0) { 2364 pm_ctl |= PCIM_PSTAT_D0; 2365 pci_write_config(sc->bge_dev, BGE_PCI_PWRMGMT_CMD, 2366 pm_ctl, 2); 2367 DELAY(10000); 2368 CSR_WRITE_4(sc, BGE_MISC_LOCAL_CTL, sc->bge_local_ctrl_reg); 2369 DELAY(10000); 2370 2371 #ifdef NOTYET 2372 /* XXX FIXME: write 0x02 to phy aux_Ctrl reg */ 2373 bge_miibus_writereg(sc->bge_dev, 1, 0x18, 0x02); 2374 #endif 2375 DELAY(40); DELAY(40); DELAY(40); 2376 DELAY(10000); /* above not quite adequate on 5700 */ 2377 return 0; 2378 } 2379 2380 2381 /* 2382 * Entering ACPI power states D1-D3 is achieved by wiggling 2383 * GMII gpio pins. Example code assumes all hardware vendors 2384 * followed Broadom's sample pcb layout. Until we verify that 2385 * for all supported OEM cards, states D1-D3 are unsupported. 2386 */ 2387 printf("%s: power state %d unimplemented; check GPIO pins\n", 2388 sc->bge_dev.dv_xname, powerlevel); 2389 #endif 2390 return EOPNOTSUPP; 2391 } 2392 2393 2394 /* 2395 * Probe for a Broadcom chip. Check the PCI vendor and device IDs 2396 * against our list and return its name if we find a match. Note 2397 * that since the Broadcom controller contains VPD support, we 2398 * can get the device name string from the controller itself instead 2399 * of the compiled-in string. This is a little slow, but it guarantees 2400 * we'll always announce the right product name. 2401 */ 2402 static int 2403 bge_probe(device_t parent, cfdata_t match, void *aux) 2404 { 2405 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 2406 2407 if (bge_lookup(pa) != NULL) 2408 return (1); 2409 2410 return (0); 2411 } 2412 2413 static void 2414 bge_attach(device_t parent, device_t self, void *aux) 2415 { 2416 struct bge_softc *sc = (struct bge_softc *)self; 2417 struct pci_attach_args *pa = aux; 2418 const struct bge_product *bp; 2419 const struct bge_revision *br; 2420 pci_chipset_tag_t pc = pa->pa_pc; 2421 pci_intr_handle_t ih; 2422 const char *intrstr = NULL; 2423 bus_dma_segment_t seg; 2424 int rseg; 2425 u_int32_t hwcfg = 0; 2426 u_int32_t mac_addr = 0; 2427 u_int32_t command; 2428 struct ifnet *ifp; 2429 void * kva; 2430 u_char eaddr[ETHER_ADDR_LEN]; 2431 pcireg_t memtype; 2432 bus_addr_t memaddr; 2433 bus_size_t memsize; 2434 u_int32_t pm_ctl; 2435 2436 bp = bge_lookup(pa); 2437 KASSERT(bp != NULL); 2438 2439 sc->bge_pa = *pa; 2440 2441 aprint_naive(": Ethernet controller\n"); 2442 aprint_normal(": %s\n", bp->bp_name); 2443 2444 /* 2445 * Map control/status registers. 2446 */ 2447 DPRINTFN(5, ("Map control/status regs\n")); 2448 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 2449 command |= PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_MASTER_ENABLE; 2450 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, command); 2451 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 2452 2453 if (!(command & PCI_COMMAND_MEM_ENABLE)) { 2454 aprint_error("%s: failed to enable memory mapping!\n", 2455 sc->bge_dev.dv_xname); 2456 return; 2457 } 2458 2459 DPRINTFN(5, ("pci_mem_find\n")); 2460 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, BGE_PCI_BAR0); 2461 switch (memtype) { 2462 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 2463 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 2464 if (pci_mapreg_map(pa, BGE_PCI_BAR0, 2465 memtype, 0, &sc->bge_btag, &sc->bge_bhandle, 2466 &memaddr, &memsize) == 0) 2467 break; 2468 default: 2469 aprint_error("%s: can't find mem space\n", 2470 sc->bge_dev.dv_xname); 2471 return; 2472 } 2473 2474 DPRINTFN(5, ("pci_intr_map\n")); 2475 if (pci_intr_map(pa, &ih)) { 2476 aprint_error("%s: couldn't map interrupt\n", 2477 sc->bge_dev.dv_xname); 2478 return; 2479 } 2480 2481 DPRINTFN(5, ("pci_intr_string\n")); 2482 intrstr = pci_intr_string(pc, ih); 2483 2484 DPRINTFN(5, ("pci_intr_establish\n")); 2485 sc->bge_intrhand = pci_intr_establish(pc, ih, IPL_NET, bge_intr, sc); 2486 2487 if (sc->bge_intrhand == NULL) { 2488 aprint_error("%s: couldn't establish interrupt", 2489 sc->bge_dev.dv_xname); 2490 if (intrstr != NULL) 2491 aprint_normal(" at %s", intrstr); 2492 aprint_normal("\n"); 2493 return; 2494 } 2495 aprint_normal("%s: interrupting at %s\n", 2496 sc->bge_dev.dv_xname, intrstr); 2497 2498 /* 2499 * Kludge for 5700 Bx bug: a hardware bug (PCIX byte enable?) 2500 * can clobber the chip's PCI config-space power control registers, 2501 * leaving the card in D3 powersave state. 2502 * We do not have memory-mapped registers in this state, 2503 * so force device into D0 state before starting initialization. 2504 */ 2505 pm_ctl = pci_conf_read(pc, pa->pa_tag, BGE_PCI_PWRMGMT_CMD); 2506 pm_ctl &= ~(PCI_PWR_D0|PCI_PWR_D1|PCI_PWR_D2|PCI_PWR_D3); 2507 pm_ctl |= (1 << 8) | PCI_PWR_D0 ; /* D0 state */ 2508 pci_conf_write(pc, pa->pa_tag, BGE_PCI_PWRMGMT_CMD, pm_ctl); 2509 DELAY(1000); /* 27 usec is allegedly sufficent */ 2510 2511 /* 2512 * Save ASIC rev. Look up any quirks associated with this 2513 * ASIC. 2514 */ 2515 sc->bge_chipid = 2516 pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_MISC_CTL) & 2517 BGE_PCIMISCCTL_ASICREV; 2518 2519 /* 2520 * Detect PCI-Express devices 2521 * XXX: guessed from Linux/FreeBSD; no documentation 2522 */ 2523 if (pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_PCIEXPRESS, 2524 NULL, NULL) != 0) 2525 sc->bge_pcie = 1; 2526 else 2527 sc->bge_pcie = 0; 2528 2529 /* Try to reset the chip. */ 2530 DPRINTFN(5, ("bge_reset\n")); 2531 bge_reset(sc); 2532 2533 if (bge_chipinit(sc)) { 2534 aprint_error("%s: chip initialization failed\n", 2535 sc->bge_dev.dv_xname); 2536 bge_release_resources(sc); 2537 return; 2538 } 2539 2540 /* 2541 * Get station address from the EEPROM. 2542 */ 2543 mac_addr = bge_readmem_ind(sc, 0x0c14); 2544 if ((mac_addr >> 16) == 0x484b) { 2545 eaddr[0] = (u_char)(mac_addr >> 8); 2546 eaddr[1] = (u_char)(mac_addr >> 0); 2547 mac_addr = bge_readmem_ind(sc, 0x0c18); 2548 eaddr[2] = (u_char)(mac_addr >> 24); 2549 eaddr[3] = (u_char)(mac_addr >> 16); 2550 eaddr[4] = (u_char)(mac_addr >> 8); 2551 eaddr[5] = (u_char)(mac_addr >> 0); 2552 } else if (bge_read_eeprom(sc, (void *)eaddr, 2553 BGE_EE_MAC_OFFSET + 2, ETHER_ADDR_LEN)) { 2554 aprint_error("%s: failed to read station address\n", 2555 sc->bge_dev.dv_xname); 2556 bge_release_resources(sc); 2557 return; 2558 } 2559 2560 br = bge_lookup_rev(sc->bge_chipid); 2561 aprint_normal("%s: ", sc->bge_dev.dv_xname); 2562 2563 if (br == NULL) { 2564 aprint_normal("unknown ASIC (0x%04x)", sc->bge_chipid >> 16); 2565 sc->bge_quirks = 0; 2566 } else { 2567 aprint_normal("ASIC %s (0x%04x)", 2568 br->br_name, sc->bge_chipid >> 16); 2569 sc->bge_quirks |= br->br_quirks; 2570 } 2571 aprint_normal(", Ethernet address %s\n", ether_sprintf(eaddr)); 2572 2573 /* Allocate the general information block and ring buffers. */ 2574 if (pci_dma64_available(pa)) 2575 sc->bge_dmatag = pa->pa_dmat64; 2576 else 2577 sc->bge_dmatag = pa->pa_dmat; 2578 DPRINTFN(5, ("bus_dmamem_alloc\n")); 2579 if (bus_dmamem_alloc(sc->bge_dmatag, sizeof(struct bge_ring_data), 2580 PAGE_SIZE, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 2581 aprint_error("%s: can't alloc rx buffers\n", 2582 sc->bge_dev.dv_xname); 2583 return; 2584 } 2585 DPRINTFN(5, ("bus_dmamem_map\n")); 2586 if (bus_dmamem_map(sc->bge_dmatag, &seg, rseg, 2587 sizeof(struct bge_ring_data), &kva, 2588 BUS_DMA_NOWAIT)) { 2589 aprint_error("%s: can't map DMA buffers (%d bytes)\n", 2590 sc->bge_dev.dv_xname, (int)sizeof(struct bge_ring_data)); 2591 bus_dmamem_free(sc->bge_dmatag, &seg, rseg); 2592 return; 2593 } 2594 DPRINTFN(5, ("bus_dmamem_create\n")); 2595 if (bus_dmamap_create(sc->bge_dmatag, sizeof(struct bge_ring_data), 1, 2596 sizeof(struct bge_ring_data), 0, 2597 BUS_DMA_NOWAIT, &sc->bge_ring_map)) { 2598 aprint_error("%s: can't create DMA map\n", 2599 sc->bge_dev.dv_xname); 2600 bus_dmamem_unmap(sc->bge_dmatag, kva, 2601 sizeof(struct bge_ring_data)); 2602 bus_dmamem_free(sc->bge_dmatag, &seg, rseg); 2603 return; 2604 } 2605 DPRINTFN(5, ("bus_dmamem_load\n")); 2606 if (bus_dmamap_load(sc->bge_dmatag, sc->bge_ring_map, kva, 2607 sizeof(struct bge_ring_data), NULL, 2608 BUS_DMA_NOWAIT)) { 2609 bus_dmamap_destroy(sc->bge_dmatag, sc->bge_ring_map); 2610 bus_dmamem_unmap(sc->bge_dmatag, kva, 2611 sizeof(struct bge_ring_data)); 2612 bus_dmamem_free(sc->bge_dmatag, &seg, rseg); 2613 return; 2614 } 2615 2616 DPRINTFN(5, ("bzero\n")); 2617 sc->bge_rdata = (struct bge_ring_data *)kva; 2618 2619 memset(sc->bge_rdata, 0, sizeof(struct bge_ring_data)); 2620 2621 /* Try to allocate memory for jumbo buffers. */ 2622 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 2623 if (bge_alloc_jumbo_mem(sc)) { 2624 aprint_error("%s: jumbo buffer allocation failed\n", 2625 sc->bge_dev.dv_xname); 2626 } else 2627 sc->ethercom.ec_capabilities |= ETHERCAP_JUMBO_MTU; 2628 } 2629 2630 /* Set default tuneable values. */ 2631 sc->bge_stat_ticks = BGE_TICKS_PER_SEC; 2632 sc->bge_rx_coal_ticks = 150; 2633 sc->bge_rx_max_coal_bds = 64; 2634 #ifdef ORIG_WPAUL_VALUES 2635 sc->bge_tx_coal_ticks = 150; 2636 sc->bge_tx_max_coal_bds = 128; 2637 #else 2638 sc->bge_tx_coal_ticks = 300; 2639 sc->bge_tx_max_coal_bds = 400; 2640 #endif 2641 if (sc->bge_quirks & BGE_QUIRK_5705_CORE) { 2642 sc->bge_tx_coal_ticks = (12 * 5); 2643 sc->bge_rx_max_coal_bds = (12 * 5); 2644 aprint_verbose("%s: setting short Tx thresholds\n", 2645 sc->bge_dev.dv_xname); 2646 } 2647 2648 /* Set up ifnet structure */ 2649 ifp = &sc->ethercom.ec_if; 2650 ifp->if_softc = sc; 2651 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 2652 ifp->if_ioctl = bge_ioctl; 2653 ifp->if_start = bge_start; 2654 ifp->if_init = bge_init; 2655 ifp->if_watchdog = bge_watchdog; 2656 IFQ_SET_MAXLEN(&ifp->if_snd, max(BGE_TX_RING_CNT - 1, IFQ_MAXLEN)); 2657 IFQ_SET_READY(&ifp->if_snd); 2658 DPRINTFN(5, ("strcpy if_xname\n")); 2659 strcpy(ifp->if_xname, sc->bge_dev.dv_xname); 2660 2661 if ((sc->bge_quirks & BGE_QUIRK_CSUM_BROKEN) == 0) 2662 sc->ethercom.ec_if.if_capabilities |= 2663 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 2664 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 2665 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 2666 sc->ethercom.ec_capabilities |= 2667 ETHERCAP_VLAN_HWTAGGING | ETHERCAP_VLAN_MTU; 2668 2669 if (sc->bge_pcie) 2670 sc->ethercom.ec_if.if_capabilities |= IFCAP_TSOv4; 2671 2672 /* 2673 * Do MII setup. 2674 */ 2675 DPRINTFN(5, ("mii setup\n")); 2676 sc->bge_mii.mii_ifp = ifp; 2677 sc->bge_mii.mii_readreg = bge_miibus_readreg; 2678 sc->bge_mii.mii_writereg = bge_miibus_writereg; 2679 sc->bge_mii.mii_statchg = bge_miibus_statchg; 2680 2681 /* 2682 * Figure out what sort of media we have by checking the 2683 * hardware config word in the first 32k of NIC internal memory, 2684 * or fall back to the config word in the EEPROM. Note: on some BCM5700 2685 * cards, this value appears to be unset. If that's the 2686 * case, we have to rely on identifying the NIC by its PCI 2687 * subsystem ID, as we do below for the SysKonnect SK-9D41. 2688 */ 2689 if (bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_SIG) == BGE_MAGIC_NUMBER) { 2690 hwcfg = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_NICCFG); 2691 } else { 2692 bge_read_eeprom(sc, (void *)&hwcfg, 2693 BGE_EE_HWCFG_OFFSET, sizeof(hwcfg)); 2694 hwcfg = be32toh(hwcfg); 2695 } 2696 if ((hwcfg & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER) 2697 sc->bge_tbi = 1; 2698 2699 /* The SysKonnect SK-9D41 is a 1000baseSX card. */ 2700 if ((pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_SUBSYS) >> 16) == 2701 SK_SUBSYSID_9D41) 2702 sc->bge_tbi = 1; 2703 2704 if (sc->bge_tbi) { 2705 ifmedia_init(&sc->bge_ifmedia, IFM_IMASK, bge_ifmedia_upd, 2706 bge_ifmedia_sts); 2707 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL); 2708 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_1000_SX|IFM_FDX, 2709 0, NULL); 2710 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL); 2711 ifmedia_set(&sc->bge_ifmedia, IFM_ETHER|IFM_AUTO); 2712 } else { 2713 /* 2714 * Do transceiver setup. 2715 */ 2716 ifmedia_init(&sc->bge_mii.mii_media, 0, bge_ifmedia_upd, 2717 bge_ifmedia_sts); 2718 mii_attach(&sc->bge_dev, &sc->bge_mii, 0xffffffff, 2719 MII_PHY_ANY, MII_OFFSET_ANY, 2720 MIIF_FORCEANEG|MIIF_DOPAUSE); 2721 2722 if (LIST_FIRST(&sc->bge_mii.mii_phys) == NULL) { 2723 printf("%s: no PHY found!\n", sc->bge_dev.dv_xname); 2724 ifmedia_add(&sc->bge_mii.mii_media, 2725 IFM_ETHER|IFM_MANUAL, 0, NULL); 2726 ifmedia_set(&sc->bge_mii.mii_media, 2727 IFM_ETHER|IFM_MANUAL); 2728 } else 2729 ifmedia_set(&sc->bge_mii.mii_media, 2730 IFM_ETHER|IFM_AUTO); 2731 } 2732 2733 /* 2734 * When using the BCM5701 in PCI-X mode, data corruption has 2735 * been observed in the first few bytes of some received packets. 2736 * Aligning the packet buffer in memory eliminates the corruption. 2737 * Unfortunately, this misaligns the packet payloads. On platforms 2738 * which do not support unaligned accesses, we will realign the 2739 * payloads by copying the received packets. 2740 */ 2741 if (sc->bge_quirks & BGE_QUIRK_PCIX_DMA_ALIGN_BUG) { 2742 /* If in PCI-X mode, work around the alignment bug. */ 2743 if ((pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_PCISTATE) & 2744 (BGE_PCISTATE_PCI_BUSMODE | BGE_PCISTATE_PCI_BUSSPEED)) == 2745 BGE_PCISTATE_PCI_BUSSPEED) 2746 sc->bge_rx_alignment_bug = 1; 2747 } 2748 2749 /* 2750 * Call MI attach routine. 2751 */ 2752 DPRINTFN(5, ("if_attach\n")); 2753 if_attach(ifp); 2754 DPRINTFN(5, ("ether_ifattach\n")); 2755 ether_ifattach(ifp, eaddr); 2756 #ifdef BGE_EVENT_COUNTERS 2757 /* 2758 * Attach event counters. 2759 */ 2760 evcnt_attach_dynamic(&sc->bge_ev_intr, EVCNT_TYPE_INTR, 2761 NULL, sc->bge_dev.dv_xname, "intr"); 2762 evcnt_attach_dynamic(&sc->bge_ev_tx_xoff, EVCNT_TYPE_MISC, 2763 NULL, sc->bge_dev.dv_xname, "tx_xoff"); 2764 evcnt_attach_dynamic(&sc->bge_ev_tx_xon, EVCNT_TYPE_MISC, 2765 NULL, sc->bge_dev.dv_xname, "tx_xon"); 2766 evcnt_attach_dynamic(&sc->bge_ev_rx_xoff, EVCNT_TYPE_MISC, 2767 NULL, sc->bge_dev.dv_xname, "rx_xoff"); 2768 evcnt_attach_dynamic(&sc->bge_ev_rx_xon, EVCNT_TYPE_MISC, 2769 NULL, sc->bge_dev.dv_xname, "rx_xon"); 2770 evcnt_attach_dynamic(&sc->bge_ev_rx_macctl, EVCNT_TYPE_MISC, 2771 NULL, sc->bge_dev.dv_xname, "rx_macctl"); 2772 evcnt_attach_dynamic(&sc->bge_ev_xoffentered, EVCNT_TYPE_MISC, 2773 NULL, sc->bge_dev.dv_xname, "xoffentered"); 2774 #endif /* BGE_EVENT_COUNTERS */ 2775 DPRINTFN(5, ("callout_init\n")); 2776 callout_init(&sc->bge_timeout, 0); 2777 2778 sc->bge_powerhook = powerhook_establish(sc->bge_dev.dv_xname, 2779 bge_powerhook, sc); 2780 if (sc->bge_powerhook == NULL) 2781 printf("%s: WARNING: unable to establish PCI power hook\n", 2782 sc->bge_dev.dv_xname); 2783 } 2784 2785 static void 2786 bge_release_resources(struct bge_softc *sc) 2787 { 2788 if (sc->bge_vpd_prodname != NULL) 2789 free(sc->bge_vpd_prodname, M_DEVBUF); 2790 2791 if (sc->bge_vpd_readonly != NULL) 2792 free(sc->bge_vpd_readonly, M_DEVBUF); 2793 } 2794 2795 static void 2796 bge_reset(struct bge_softc *sc) 2797 { 2798 struct pci_attach_args *pa = &sc->bge_pa; 2799 u_int32_t cachesize, command, pcistate, new_pcistate; 2800 int i, val; 2801 2802 /* Save some important PCI state. */ 2803 cachesize = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_CACHESZ); 2804 command = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_CMD); 2805 pcistate = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_PCISTATE); 2806 2807 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_MISC_CTL, 2808 BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR| 2809 BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_PCISTATE_RW); 2810 2811 /* 2812 * Disable the firmware fastboot feature on 5752 ASIC 2813 * to avoid firmware timeout. 2814 */ 2815 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5752) 2816 CSR_WRITE_4(sc, BGE_FASTBOOT_PC, 0); 2817 2818 val = BGE_MISCCFG_RESET_CORE_CLOCKS | (65<<1); 2819 /* 2820 * XXX: from FreeBSD/Linux; no documentation 2821 */ 2822 if (sc->bge_pcie) { 2823 if (CSR_READ_4(sc, BGE_PCIE_CTL1) == 0x60) 2824 CSR_WRITE_4(sc, BGE_PCIE_CTL1, 0x20); 2825 if (sc->bge_chipid != BGE_CHIPID_BCM5750_A0) { 2826 /* No idea what that actually means */ 2827 CSR_WRITE_4(sc, BGE_MISC_CFG, 1 << 29); 2828 val |= (1<<29); 2829 } 2830 } 2831 /* 2832 * Write the magic number to the firmware mailbox at 0xb50 2833 * so that the driver can synchronize with the firmware. 2834 */ 2835 bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM, BGE_MAGIC_NUMBER); 2836 2837 /* Issue global reset */ 2838 bge_writereg_ind(sc, BGE_MISC_CFG, val); 2839 2840 DELAY(1000); 2841 2842 /* 2843 * XXX: from FreeBSD/Linux; no documentation 2844 */ 2845 if (sc->bge_pcie) { 2846 if (sc->bge_chipid == BGE_CHIPID_BCM5750_A0) { 2847 pcireg_t reg; 2848 2849 DELAY(500000); 2850 /* XXX: Magic Numbers */ 2851 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_UNKNOWN0); 2852 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_UNKNOWN0, 2853 reg | (1 << 15)); 2854 } 2855 /* 2856 * XXX: Magic Numbers. 2857 * Sets maximal PCI-e payload and clears any PCI-e errors. 2858 * Should be replaced with references to PCI config-space 2859 * capability block for PCI-Express. 2860 */ 2861 pci_conf_write(pa->pa_pc, pa->pa_tag, 2862 BGE_PCI_CONF_DEV_CTRL, 0xf5000); 2863 2864 } 2865 2866 /* Reset some of the PCI state that got zapped by reset */ 2867 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_MISC_CTL, 2868 BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR| 2869 BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_PCISTATE_RW); 2870 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_CMD, command); 2871 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_CACHESZ, cachesize); 2872 bge_writereg_ind(sc, BGE_MISC_CFG, (65 << 1)); 2873 2874 /* Enable memory arbiter. */ 2875 { 2876 uint32_t marbmode = 0; 2877 if (BGE_IS_5714_FAMILY(sc)) { 2878 marbmode = CSR_READ_4(sc, BGE_MARB_MODE); 2879 } 2880 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE | marbmode); 2881 } 2882 2883 /* 2884 * Poll the value location we just wrote until 2885 * we see the 1's complement of the magic number. 2886 * This indicates that the firmware initialization 2887 * is complete. 2888 */ 2889 for (i = 0; i < BGE_TIMEOUT; i++) { 2890 val = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM); 2891 if (val == ~BGE_MAGIC_NUMBER) 2892 break; 2893 DELAY(1000); 2894 } 2895 2896 if (i >= BGE_TIMEOUT) { 2897 printf("%s: firmware handshake timed out, val = %x\n", 2898 sc->bge_dev.dv_xname, val); 2899 /* 2900 * XXX: occasionally fired on bcm5721, but without 2901 * apparent harm. For now, keep going if we timeout 2902 * against PCI-E devices. 2903 */ 2904 if (!sc->bge_pcie) 2905 return; 2906 } 2907 2908 /* 2909 * XXX Wait for the value of the PCISTATE register to 2910 * return to its original pre-reset state. This is a 2911 * fairly good indicator of reset completion. If we don't 2912 * wait for the reset to fully complete, trying to read 2913 * from the device's non-PCI registers may yield garbage 2914 * results. 2915 */ 2916 for (i = 0; i < BGE_TIMEOUT; i++) { 2917 new_pcistate = pci_conf_read(pa->pa_pc, pa->pa_tag, 2918 BGE_PCI_PCISTATE); 2919 if ((new_pcistate & ~BGE_PCISTATE_RESERVED) == 2920 (pcistate & ~BGE_PCISTATE_RESERVED)) 2921 break; 2922 DELAY(10); 2923 } 2924 if ((new_pcistate & ~BGE_PCISTATE_RESERVED) != 2925 (pcistate & ~BGE_PCISTATE_RESERVED)) { 2926 printf("%s: pcistate failed to revert\n", 2927 sc->bge_dev.dv_xname); 2928 } 2929 2930 /* XXX: from FreeBSD/Linux; no documentation */ 2931 if (sc->bge_pcie && sc->bge_chipid != BGE_CHIPID_BCM5750_A0) 2932 CSR_WRITE_4(sc, BGE_PCIE_CTL0, CSR_READ_4(sc, BGE_PCIE_CTL0) | (1<<25)); 2933 2934 /* Enable memory arbiter. */ 2935 /* XXX why do this twice? */ 2936 { 2937 uint32_t marbmode = 0; 2938 if (BGE_IS_5714_FAMILY(sc)) { 2939 marbmode = CSR_READ_4(sc, BGE_MARB_MODE); 2940 } 2941 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE | marbmode); 2942 } 2943 2944 /* Fix up byte swapping */ 2945 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS); 2946 2947 CSR_WRITE_4(sc, BGE_MAC_MODE, 0); 2948 2949 DELAY(10000); 2950 } 2951 2952 /* 2953 * Frame reception handling. This is called if there's a frame 2954 * on the receive return list. 2955 * 2956 * Note: we have to be able to handle two possibilities here: 2957 * 1) the frame is from the jumbo recieve ring 2958 * 2) the frame is from the standard receive ring 2959 */ 2960 2961 static void 2962 bge_rxeof(struct bge_softc *sc) 2963 { 2964 struct ifnet *ifp; 2965 int stdcnt = 0, jumbocnt = 0; 2966 bus_dmamap_t dmamap; 2967 bus_addr_t offset, toff; 2968 bus_size_t tlen; 2969 int tosync; 2970 2971 ifp = &sc->ethercom.ec_if; 2972 2973 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 2974 offsetof(struct bge_ring_data, bge_status_block), 2975 sizeof (struct bge_status_block), 2976 BUS_DMASYNC_POSTREAD); 2977 2978 offset = offsetof(struct bge_ring_data, bge_rx_return_ring); 2979 tosync = sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx - 2980 sc->bge_rx_saved_considx; 2981 2982 toff = offset + (sc->bge_rx_saved_considx * sizeof (struct bge_rx_bd)); 2983 2984 if (tosync < 0) { 2985 tlen = (sc->bge_return_ring_cnt - sc->bge_rx_saved_considx) * 2986 sizeof (struct bge_rx_bd); 2987 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 2988 toff, tlen, BUS_DMASYNC_POSTREAD); 2989 tosync = -tosync; 2990 } 2991 2992 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 2993 offset, tosync * sizeof (struct bge_rx_bd), 2994 BUS_DMASYNC_POSTREAD); 2995 2996 while(sc->bge_rx_saved_considx != 2997 sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx) { 2998 struct bge_rx_bd *cur_rx; 2999 u_int32_t rxidx; 3000 struct mbuf *m = NULL; 3001 3002 cur_rx = &sc->bge_rdata-> 3003 bge_rx_return_ring[sc->bge_rx_saved_considx]; 3004 3005 rxidx = cur_rx->bge_idx; 3006 BGE_INC(sc->bge_rx_saved_considx, sc->bge_return_ring_cnt); 3007 3008 if (cur_rx->bge_flags & BGE_RXBDFLAG_JUMBO_RING) { 3009 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT); 3010 m = sc->bge_cdata.bge_rx_jumbo_chain[rxidx]; 3011 sc->bge_cdata.bge_rx_jumbo_chain[rxidx] = NULL; 3012 jumbocnt++; 3013 bus_dmamap_sync(sc->bge_dmatag, 3014 sc->bge_cdata.bge_rx_jumbo_map, 3015 mtod(m, char *) - (char *)sc->bge_cdata.bge_jumbo_buf, 3016 BGE_JLEN, BUS_DMASYNC_POSTREAD); 3017 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 3018 ifp->if_ierrors++; 3019 bge_newbuf_jumbo(sc, sc->bge_jumbo, m); 3020 continue; 3021 } 3022 if (bge_newbuf_jumbo(sc, sc->bge_jumbo, 3023 NULL)== ENOBUFS) { 3024 ifp->if_ierrors++; 3025 bge_newbuf_jumbo(sc, sc->bge_jumbo, m); 3026 continue; 3027 } 3028 } else { 3029 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT); 3030 m = sc->bge_cdata.bge_rx_std_chain[rxidx]; 3031 3032 sc->bge_cdata.bge_rx_std_chain[rxidx] = NULL; 3033 stdcnt++; 3034 dmamap = sc->bge_cdata.bge_rx_std_map[rxidx]; 3035 sc->bge_cdata.bge_rx_std_map[rxidx] = 0; 3036 bus_dmamap_sync(sc->bge_dmatag, dmamap, 0, 3037 dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 3038 bus_dmamap_unload(sc->bge_dmatag, dmamap); 3039 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 3040 ifp->if_ierrors++; 3041 bge_newbuf_std(sc, sc->bge_std, m, dmamap); 3042 continue; 3043 } 3044 if (bge_newbuf_std(sc, sc->bge_std, 3045 NULL, dmamap) == ENOBUFS) { 3046 ifp->if_ierrors++; 3047 bge_newbuf_std(sc, sc->bge_std, m, dmamap); 3048 continue; 3049 } 3050 } 3051 3052 ifp->if_ipackets++; 3053 #ifndef __NO_STRICT_ALIGNMENT 3054 /* 3055 * XXX: if the 5701 PCIX-Rx-DMA workaround is in effect, 3056 * the Rx buffer has the layer-2 header unaligned. 3057 * If our CPU requires alignment, re-align by copying. 3058 */ 3059 if (sc->bge_rx_alignment_bug) { 3060 memmove(mtod(m, char *) + ETHER_ALIGN, m->m_data, 3061 cur_rx->bge_len); 3062 m->m_data += ETHER_ALIGN; 3063 } 3064 #endif 3065 3066 m->m_pkthdr.len = m->m_len = cur_rx->bge_len - ETHER_CRC_LEN; 3067 m->m_pkthdr.rcvif = ifp; 3068 3069 #if NBPFILTER > 0 3070 /* 3071 * Handle BPF listeners. Let the BPF user see the packet. 3072 */ 3073 if (ifp->if_bpf) 3074 bpf_mtap(ifp->if_bpf, m); 3075 #endif 3076 3077 m->m_pkthdr.csum_flags = M_CSUM_IPv4; 3078 3079 if ((cur_rx->bge_ip_csum ^ 0xffff) != 0) 3080 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 3081 /* 3082 * Rx transport checksum-offload may also 3083 * have bugs with packets which, when transmitted, 3084 * were `runts' requiring padding. 3085 */ 3086 if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM && 3087 (/* (sc->_bge_quirks & BGE_QUIRK_SHORT_CKSUM_BUG) == 0 ||*/ 3088 m->m_pkthdr.len >= ETHER_MIN_NOPAD)) { 3089 m->m_pkthdr.csum_data = 3090 cur_rx->bge_tcp_udp_csum; 3091 m->m_pkthdr.csum_flags |= 3092 (M_CSUM_TCPv4|M_CSUM_UDPv4| 3093 M_CSUM_DATA|M_CSUM_NO_PSEUDOHDR); 3094 } 3095 3096 /* 3097 * If we received a packet with a vlan tag, pass it 3098 * to vlan_input() instead of ether_input(). 3099 */ 3100 if (cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) 3101 VLAN_INPUT_TAG(ifp, m, cur_rx->bge_vlan_tag, continue); 3102 3103 (*ifp->if_input)(ifp, m); 3104 } 3105 3106 CSR_WRITE_4(sc, BGE_MBX_RX_CONS0_LO, sc->bge_rx_saved_considx); 3107 if (stdcnt) 3108 CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std); 3109 if (jumbocnt) 3110 CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo); 3111 } 3112 3113 static void 3114 bge_txeof(struct bge_softc *sc) 3115 { 3116 struct bge_tx_bd *cur_tx = NULL; 3117 struct ifnet *ifp; 3118 struct txdmamap_pool_entry *dma; 3119 bus_addr_t offset, toff; 3120 bus_size_t tlen; 3121 int tosync; 3122 struct mbuf *m; 3123 3124 ifp = &sc->ethercom.ec_if; 3125 3126 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 3127 offsetof(struct bge_ring_data, bge_status_block), 3128 sizeof (struct bge_status_block), 3129 BUS_DMASYNC_POSTREAD); 3130 3131 offset = offsetof(struct bge_ring_data, bge_tx_ring); 3132 tosync = sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx - 3133 sc->bge_tx_saved_considx; 3134 3135 toff = offset + (sc->bge_tx_saved_considx * sizeof (struct bge_tx_bd)); 3136 3137 if (tosync < 0) { 3138 tlen = (BGE_TX_RING_CNT - sc->bge_tx_saved_considx) * 3139 sizeof (struct bge_tx_bd); 3140 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 3141 toff, tlen, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 3142 tosync = -tosync; 3143 } 3144 3145 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 3146 offset, tosync * sizeof (struct bge_tx_bd), 3147 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 3148 3149 /* 3150 * Go through our tx ring and free mbufs for those 3151 * frames that have been sent. 3152 */ 3153 while (sc->bge_tx_saved_considx != 3154 sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx) { 3155 u_int32_t idx = 0; 3156 3157 idx = sc->bge_tx_saved_considx; 3158 cur_tx = &sc->bge_rdata->bge_tx_ring[idx]; 3159 if (cur_tx->bge_flags & BGE_TXBDFLAG_END) 3160 ifp->if_opackets++; 3161 m = sc->bge_cdata.bge_tx_chain[idx]; 3162 if (m != NULL) { 3163 sc->bge_cdata.bge_tx_chain[idx] = NULL; 3164 dma = sc->txdma[idx]; 3165 bus_dmamap_sync(sc->bge_dmatag, dma->dmamap, 0, 3166 dma->dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 3167 bus_dmamap_unload(sc->bge_dmatag, dma->dmamap); 3168 SLIST_INSERT_HEAD(&sc->txdma_list, dma, link); 3169 sc->txdma[idx] = NULL; 3170 3171 m_freem(m); 3172 } 3173 sc->bge_txcnt--; 3174 BGE_INC(sc->bge_tx_saved_considx, BGE_TX_RING_CNT); 3175 ifp->if_timer = 0; 3176 } 3177 3178 if (cur_tx != NULL) 3179 ifp->if_flags &= ~IFF_OACTIVE; 3180 } 3181 3182 static int 3183 bge_intr(void *xsc) 3184 { 3185 struct bge_softc *sc; 3186 struct ifnet *ifp; 3187 3188 sc = xsc; 3189 ifp = &sc->ethercom.ec_if; 3190 3191 #ifdef notdef 3192 /* Avoid this for now -- checking this register is expensive. */ 3193 /* Make sure this is really our interrupt. */ 3194 if (!(CSR_READ_4(sc, BGE_MISC_LOCAL_CTL) & BGE_MLC_INTR_STATE)) 3195 return (0); 3196 #endif 3197 /* Ack interrupt and stop others from occuring. */ 3198 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 1); 3199 3200 BGE_EVCNT_INCR(sc->bge_ev_intr); 3201 3202 /* 3203 * Process link state changes. 3204 * Grrr. The link status word in the status block does 3205 * not work correctly on the BCM5700 rev AX and BX chips, 3206 * according to all available information. Hence, we have 3207 * to enable MII interrupts in order to properly obtain 3208 * async link changes. Unfortunately, this also means that 3209 * we have to read the MAC status register to detect link 3210 * changes, thereby adding an additional register access to 3211 * the interrupt handler. 3212 */ 3213 3214 if (sc->bge_quirks & BGE_QUIRK_LINK_STATE_BROKEN) { 3215 u_int32_t status; 3216 3217 status = CSR_READ_4(sc, BGE_MAC_STS); 3218 if (status & BGE_MACSTAT_MI_INTERRUPT) { 3219 sc->bge_link = 0; 3220 callout_stop(&sc->bge_timeout); 3221 bge_tick(sc); 3222 /* Clear the interrupt */ 3223 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, 3224 BGE_EVTENB_MI_INTERRUPT); 3225 bge_miibus_readreg(&sc->bge_dev, 1, BRGPHY_MII_ISR); 3226 bge_miibus_writereg(&sc->bge_dev, 1, BRGPHY_MII_IMR, 3227 BRGPHY_INTRS); 3228 } 3229 } else { 3230 if (sc->bge_rdata->bge_status_block.bge_status & 3231 BGE_STATFLAG_LINKSTATE_CHANGED) { 3232 sc->bge_link = 0; 3233 callout_stop(&sc->bge_timeout); 3234 bge_tick(sc); 3235 /* Clear the interrupt */ 3236 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED| 3237 BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE| 3238 BGE_MACSTAT_LINK_CHANGED); 3239 } 3240 } 3241 3242 if (ifp->if_flags & IFF_RUNNING) { 3243 /* Check RX return ring producer/consumer */ 3244 bge_rxeof(sc); 3245 3246 /* Check TX ring producer/consumer */ 3247 bge_txeof(sc); 3248 } 3249 3250 if (sc->bge_pending_rxintr_change) { 3251 uint32_t rx_ticks = sc->bge_rx_coal_ticks; 3252 uint32_t rx_bds = sc->bge_rx_max_coal_bds; 3253 uint32_t junk; 3254 3255 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, rx_ticks); 3256 DELAY(10); 3257 junk = CSR_READ_4(sc, BGE_HCC_RX_COAL_TICKS); 3258 3259 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, rx_bds); 3260 DELAY(10); 3261 junk = CSR_READ_4(sc, BGE_HCC_RX_MAX_COAL_BDS); 3262 3263 sc->bge_pending_rxintr_change = 0; 3264 } 3265 bge_handle_events(sc); 3266 3267 /* Re-enable interrupts. */ 3268 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 0); 3269 3270 if (ifp->if_flags & IFF_RUNNING && !IFQ_IS_EMPTY(&ifp->if_snd)) 3271 bge_start(ifp); 3272 3273 return (1); 3274 } 3275 3276 static void 3277 bge_tick(void *xsc) 3278 { 3279 struct bge_softc *sc = xsc; 3280 struct mii_data *mii = &sc->bge_mii; 3281 struct ifmedia *ifm = NULL; 3282 struct ifnet *ifp = &sc->ethercom.ec_if; 3283 int s; 3284 3285 s = splnet(); 3286 3287 bge_stats_update(sc); 3288 callout_reset(&sc->bge_timeout, hz, bge_tick, sc); 3289 if (sc->bge_link) { 3290 splx(s); 3291 return; 3292 } 3293 3294 if (sc->bge_tbi) { 3295 ifm = &sc->bge_ifmedia; 3296 if (CSR_READ_4(sc, BGE_MAC_STS) & 3297 BGE_MACSTAT_TBI_PCS_SYNCHED) { 3298 sc->bge_link++; 3299 CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF); 3300 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 3301 bge_start(ifp); 3302 } 3303 splx(s); 3304 return; 3305 } 3306 3307 mii_tick(mii); 3308 3309 if (!sc->bge_link && mii->mii_media_status & IFM_ACTIVE && 3310 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 3311 sc->bge_link++; 3312 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 3313 bge_start(ifp); 3314 } 3315 3316 splx(s); 3317 } 3318 3319 static void 3320 bge_stats_update(struct bge_softc *sc) 3321 { 3322 struct ifnet *ifp = &sc->ethercom.ec_if; 3323 bus_size_t stats = BGE_MEMWIN_START + BGE_STATS_BLOCK; 3324 bus_size_t rstats = BGE_RX_STATS; 3325 3326 #define READ_RSTAT(sc, stats, stat) \ 3327 CSR_READ_4(sc, stats + offsetof(struct bge_mac_stats_regs, stat)) 3328 3329 if (sc->bge_quirks & BGE_QUIRK_5705_CORE) { 3330 ifp->if_collisions += 3331 READ_RSTAT(sc, rstats, dot3StatsSingleCollisionFrames) + 3332 READ_RSTAT(sc, rstats, dot3StatsMultipleCollisionFrames) + 3333 READ_RSTAT(sc, rstats, dot3StatsExcessiveCollisions) + 3334 READ_RSTAT(sc, rstats, dot3StatsLateCollisions); 3335 3336 BGE_EVCNT_ADD(sc->bge_ev_tx_xoff, 3337 READ_RSTAT(sc, rstats, outXoffSent)); 3338 BGE_EVCNT_ADD(sc->bge_ev_tx_xon, 3339 READ_RSTAT(sc, rstats, outXonSent)); 3340 BGE_EVCNT_ADD(sc->bge_ev_rx_xoff, 3341 READ_RSTAT(sc, rstats, xoffPauseFramesReceived)); 3342 BGE_EVCNT_ADD(sc->bge_ev_rx_xon, 3343 READ_RSTAT(sc, rstats, xonPauseFramesReceived)); 3344 BGE_EVCNT_ADD(sc->bge_ev_rx_macctl, 3345 READ_RSTAT(sc, rstats, macControlFramesReceived)); 3346 BGE_EVCNT_ADD(sc->bge_ev_xoffentered, 3347 READ_RSTAT(sc, rstats, xoffStateEntered)); 3348 return; 3349 } 3350 3351 #undef READ_RSTAT 3352 #define READ_STAT(sc, stats, stat) \ 3353 CSR_READ_4(sc, stats + offsetof(struct bge_stats, stat)) 3354 3355 ifp->if_collisions += 3356 (READ_STAT(sc, stats, dot3StatsSingleCollisionFrames.bge_addr_lo) + 3357 READ_STAT(sc, stats, dot3StatsMultipleCollisionFrames.bge_addr_lo) + 3358 READ_STAT(sc, stats, dot3StatsExcessiveCollisions.bge_addr_lo) + 3359 READ_STAT(sc, stats, dot3StatsLateCollisions.bge_addr_lo)) - 3360 ifp->if_collisions; 3361 3362 BGE_EVCNT_UPD(sc->bge_ev_tx_xoff, 3363 READ_STAT(sc, stats, outXoffSent.bge_addr_lo)); 3364 BGE_EVCNT_UPD(sc->bge_ev_tx_xon, 3365 READ_STAT(sc, stats, outXonSent.bge_addr_lo)); 3366 BGE_EVCNT_UPD(sc->bge_ev_rx_xoff, 3367 READ_STAT(sc, stats, 3368 xoffPauseFramesReceived.bge_addr_lo)); 3369 BGE_EVCNT_UPD(sc->bge_ev_rx_xon, 3370 READ_STAT(sc, stats, xonPauseFramesReceived.bge_addr_lo)); 3371 BGE_EVCNT_UPD(sc->bge_ev_rx_macctl, 3372 READ_STAT(sc, stats, 3373 macControlFramesReceived.bge_addr_lo)); 3374 BGE_EVCNT_UPD(sc->bge_ev_xoffentered, 3375 READ_STAT(sc, stats, xoffStateEntered.bge_addr_lo)); 3376 3377 #undef READ_STAT 3378 3379 #ifdef notdef 3380 ifp->if_collisions += 3381 (sc->bge_rdata->bge_info.bge_stats.dot3StatsSingleCollisionFrames + 3382 sc->bge_rdata->bge_info.bge_stats.dot3StatsMultipleCollisionFrames + 3383 sc->bge_rdata->bge_info.bge_stats.dot3StatsExcessiveCollisions + 3384 sc->bge_rdata->bge_info.bge_stats.dot3StatsLateCollisions) - 3385 ifp->if_collisions; 3386 #endif 3387 } 3388 3389 /* 3390 * Pad outbound frame to ETHER_MIN_NOPAD for an unusual reason. 3391 * The bge hardware will pad out Tx runts to ETHER_MIN_NOPAD, 3392 * but when such padded frames employ the bge IP/TCP checksum offload, 3393 * the hardware checksum assist gives incorrect results (possibly 3394 * from incorporating its own padding into the UDP/TCP checksum; who knows). 3395 * If we pad such runts with zeros, the onboard checksum comes out correct. 3396 */ 3397 static inline int 3398 bge_cksum_pad(struct mbuf *pkt) 3399 { 3400 struct mbuf *last = NULL; 3401 int padlen; 3402 3403 padlen = ETHER_MIN_NOPAD - pkt->m_pkthdr.len; 3404 3405 /* if there's only the packet-header and we can pad there, use it. */ 3406 if (pkt->m_pkthdr.len == pkt->m_len && 3407 M_TRAILINGSPACE(pkt) >= padlen) { 3408 last = pkt; 3409 } else { 3410 /* 3411 * Walk packet chain to find last mbuf. We will either 3412 * pad there, or append a new mbuf and pad it 3413 * (thus perhaps avoiding the bcm5700 dma-min bug). 3414 */ 3415 for (last = pkt; last->m_next != NULL; last = last->m_next) { 3416 continue; /* do nothing */ 3417 } 3418 3419 /* `last' now points to last in chain. */ 3420 if (M_TRAILINGSPACE(last) < padlen) { 3421 /* Allocate new empty mbuf, pad it. Compact later. */ 3422 struct mbuf *n; 3423 MGET(n, M_DONTWAIT, MT_DATA); 3424 if (n == NULL) 3425 return ENOBUFS; 3426 n->m_len = 0; 3427 last->m_next = n; 3428 last = n; 3429 } 3430 } 3431 3432 KDASSERT(!M_READONLY(last)); 3433 KDASSERT(M_TRAILINGSPACE(last) >= padlen); 3434 3435 /* Now zero the pad area, to avoid the bge cksum-assist bug */ 3436 memset(mtod(last, char *) + last->m_len, 0, padlen); 3437 last->m_len += padlen; 3438 pkt->m_pkthdr.len += padlen; 3439 return 0; 3440 } 3441 3442 /* 3443 * Compact outbound packets to avoid bug with DMA segments less than 8 bytes. 3444 */ 3445 static inline int 3446 bge_compact_dma_runt(struct mbuf *pkt) 3447 { 3448 struct mbuf *m, *prev; 3449 int totlen, prevlen; 3450 3451 prev = NULL; 3452 totlen = 0; 3453 prevlen = -1; 3454 3455 for (m = pkt; m != NULL; prev = m,m = m->m_next) { 3456 int mlen = m->m_len; 3457 int shortfall = 8 - mlen ; 3458 3459 totlen += mlen; 3460 if (mlen == 0) { 3461 continue; 3462 } 3463 if (mlen >= 8) 3464 continue; 3465 3466 /* If we get here, mbuf data is too small for DMA engine. 3467 * Try to fix by shuffling data to prev or next in chain. 3468 * If that fails, do a compacting deep-copy of the whole chain. 3469 */ 3470 3471 /* Internal frag. If fits in prev, copy it there. */ 3472 if (prev && M_TRAILINGSPACE(prev) >= m->m_len) { 3473 memcpy(prev->m_data + prev->m_len, m->m_data, mlen); 3474 prev->m_len += mlen; 3475 m->m_len = 0; 3476 /* XXX stitch chain */ 3477 prev->m_next = m_free(m); 3478 m = prev; 3479 continue; 3480 } 3481 else if (m->m_next != NULL && 3482 M_TRAILINGSPACE(m) >= shortfall && 3483 m->m_next->m_len >= (8 + shortfall)) { 3484 /* m is writable and have enough data in next, pull up. */ 3485 3486 memcpy(m->m_data + m->m_len, m->m_next->m_data, 3487 shortfall); 3488 m->m_len += shortfall; 3489 m->m_next->m_len -= shortfall; 3490 m->m_next->m_data += shortfall; 3491 } 3492 else if (m->m_next == NULL || 1) { 3493 /* Got a runt at the very end of the packet. 3494 * borrow data from the tail of the preceding mbuf and 3495 * update its length in-place. (The original data is still 3496 * valid, so we can do this even if prev is not writable.) 3497 */ 3498 3499 /* if we'd make prev a runt, just move all of its data. */ 3500 KASSERT(prev != NULL /*, ("runt but null PREV")*/); 3501 KASSERT(prev->m_len >= 8 /*, ("runt prev")*/); 3502 3503 if ((prev->m_len - shortfall) < 8) 3504 shortfall = prev->m_len; 3505 3506 #ifdef notyet /* just do the safe slow thing for now */ 3507 if (!M_READONLY(m)) { 3508 if (M_LEADINGSPACE(m) < shorfall) { 3509 void *m_dat; 3510 m_dat = (m->m_flags & M_PKTHDR) ? 3511 m->m_pktdat : m->dat; 3512 memmove(m_dat, mtod(m, void*), m->m_len); 3513 m->m_data = m_dat; 3514 } 3515 } else 3516 #endif /* just do the safe slow thing */ 3517 { 3518 struct mbuf * n = NULL; 3519 int newprevlen = prev->m_len - shortfall; 3520 3521 MGET(n, M_NOWAIT, MT_DATA); 3522 if (n == NULL) 3523 return ENOBUFS; 3524 KASSERT(m->m_len + shortfall < MLEN 3525 /*, 3526 ("runt %d +prev %d too big\n", m->m_len, shortfall)*/); 3527 3528 /* first copy the data we're stealing from prev */ 3529 memcpy(n->m_data, prev->m_data + newprevlen, 3530 shortfall); 3531 3532 /* update prev->m_len accordingly */ 3533 prev->m_len -= shortfall; 3534 3535 /* copy data from runt m */ 3536 memcpy(n->m_data + shortfall, m->m_data, 3537 m->m_len); 3538 3539 /* n holds what we stole from prev, plus m */ 3540 n->m_len = shortfall + m->m_len; 3541 3542 /* stitch n into chain and free m */ 3543 n->m_next = m->m_next; 3544 prev->m_next = n; 3545 /* KASSERT(m->m_next == NULL); */ 3546 m->m_next = NULL; 3547 m_free(m); 3548 m = n; /* for continuing loop */ 3549 } 3550 } 3551 prevlen = m->m_len; 3552 } 3553 return 0; 3554 } 3555 3556 /* 3557 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data 3558 * pointers to descriptors. 3559 */ 3560 static int 3561 bge_encap(struct bge_softc *sc, struct mbuf *m_head, u_int32_t *txidx) 3562 { 3563 struct bge_tx_bd *f = NULL; 3564 u_int32_t frag, cur; 3565 u_int16_t csum_flags = 0; 3566 u_int16_t txbd_tso_flags = 0; 3567 struct txdmamap_pool_entry *dma; 3568 bus_dmamap_t dmamap; 3569 int i = 0; 3570 struct m_tag *mtag; 3571 int use_tso, maxsegsize, error; 3572 3573 cur = frag = *txidx; 3574 3575 if (m_head->m_pkthdr.csum_flags) { 3576 if (m_head->m_pkthdr.csum_flags & M_CSUM_IPv4) 3577 csum_flags |= BGE_TXBDFLAG_IP_CSUM; 3578 if (m_head->m_pkthdr.csum_flags & (M_CSUM_TCPv4|M_CSUM_UDPv4)) 3579 csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM; 3580 } 3581 3582 /* 3583 * If we were asked to do an outboard checksum, and the NIC 3584 * has the bug where it sometimes adds in the Ethernet padding, 3585 * explicitly pad with zeros so the cksum will be correct either way. 3586 * (For now, do this for all chip versions, until newer 3587 * are confirmed to not require the workaround.) 3588 */ 3589 if ((csum_flags & BGE_TXBDFLAG_TCP_UDP_CSUM) == 0 || 3590 #ifdef notyet 3591 (sc->bge_quirks & BGE_QUIRK_SHORT_CKSUM_BUG) == 0 || 3592 #endif 3593 m_head->m_pkthdr.len >= ETHER_MIN_NOPAD) 3594 goto check_dma_bug; 3595 3596 if (bge_cksum_pad(m_head) != 0) { 3597 return ENOBUFS; 3598 } 3599 3600 check_dma_bug: 3601 if (!(sc->bge_quirks & BGE_QUIRK_5700_SMALLDMA)) 3602 goto doit; 3603 /* 3604 * bcm5700 Revision B silicon cannot handle DMA descriptors with 3605 * less than eight bytes. If we encounter a teeny mbuf 3606 * at the end of a chain, we can pad. Otherwise, copy. 3607 */ 3608 if (bge_compact_dma_runt(m_head) != 0) 3609 return ENOBUFS; 3610 3611 doit: 3612 dma = SLIST_FIRST(&sc->txdma_list); 3613 if (dma == NULL) 3614 return ENOBUFS; 3615 dmamap = dma->dmamap; 3616 3617 /* 3618 * Set up any necessary TSO state before we start packing... 3619 */ 3620 use_tso = (m_head->m_pkthdr.csum_flags & M_CSUM_TSOv4) != 0; 3621 if (!use_tso) { 3622 maxsegsize = 0; 3623 } else { /* TSO setup */ 3624 unsigned mss; 3625 struct ether_header *eh; 3626 unsigned ip_tcp_hlen, iptcp_opt_words, tcp_seg_flags, offset; 3627 struct mbuf * m0 = m_head; 3628 struct ip *ip; 3629 struct tcphdr *th; 3630 int iphl, hlen; 3631 3632 /* 3633 * XXX It would be nice if the mbuf pkthdr had offset 3634 * fields for the protocol headers. 3635 */ 3636 3637 eh = mtod(m0, struct ether_header *); 3638 switch (htons(eh->ether_type)) { 3639 case ETHERTYPE_IP: 3640 offset = ETHER_HDR_LEN; 3641 break; 3642 3643 case ETHERTYPE_VLAN: 3644 offset = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 3645 break; 3646 3647 default: 3648 /* 3649 * Don't support this protocol or encapsulation. 3650 */ 3651 return (ENOBUFS); 3652 } 3653 3654 /* 3655 * TCP/IP headers are in the first mbuf; we can do 3656 * this the easy way. 3657 */ 3658 iphl = M_CSUM_DATA_IPv4_IPHL(m0->m_pkthdr.csum_data); 3659 hlen = iphl + offset; 3660 if (__predict_false(m0->m_len < 3661 (hlen + sizeof(struct tcphdr)))) { 3662 3663 printf("TSO: hard case m0->m_len == %d <" 3664 " ip/tcp hlen %zd, not handled yet\n", 3665 m0->m_len, hlen+ sizeof(struct tcphdr)); 3666 #ifdef NOTYET 3667 /* 3668 * XXX jonathan (at) NetBSD.org: untested. 3669 * how to force this branch to be taken? 3670 */ 3671 BGE_EVCNT_INCR(&sc->sc_ev_txtsopain); 3672 3673 m_copydata(m0, offset, sizeof(ip), &ip); 3674 m_copydata(m0, hlen, sizeof(th), &th); 3675 3676 ip.ip_len = 0; 3677 3678 m_copyback(m0, hlen + offsetof(struct ip, ip_len), 3679 sizeof(ip.ip_len), &ip.ip_len); 3680 3681 th.th_sum = in_cksum_phdr(ip.ip_src.s_addr, 3682 ip.ip_dst.s_addr, htons(IPPROTO_TCP)); 3683 3684 m_copyback(m0, hlen + offsetof(struct tcphdr, th_sum), 3685 sizeof(th.th_sum), &th.th_sum); 3686 3687 hlen += th.th_off << 2; 3688 iptcp_opt_words = hlen; 3689 #else 3690 /* 3691 * if_wm "hard" case not yet supported, can we not 3692 * mandate it out of existence? 3693 */ 3694 (void) ip; (void)th; (void) ip_tcp_hlen; 3695 3696 return ENOBUFS; 3697 #endif 3698 } else { 3699 ip = (struct ip *) (mtod(m0, char *) + offset); 3700 th = (struct tcphdr *) (mtod(m0, char *) + hlen); 3701 ip_tcp_hlen = iphl + (th->th_off << 2); 3702 3703 /* Total IP/TCP options, in 32-bit words */ 3704 iptcp_opt_words = (ip_tcp_hlen 3705 - sizeof(struct tcphdr) 3706 - sizeof(struct ip)) >> 2; 3707 } 3708 if (BGE_IS_5750_OR_BEYOND(sc)) { 3709 th->th_sum = 0; 3710 csum_flags &= ~(BGE_TXBDFLAG_TCP_UDP_CSUM); 3711 } else { 3712 /* 3713 * XXX jonathan (at) NetBSD.org: 5705 untested. 3714 * Requires TSO firmware patch for 5701/5703/5704. 3715 */ 3716 th->th_sum = in_cksum_phdr(ip->ip_src.s_addr, 3717 ip->ip_dst.s_addr, htons(IPPROTO_TCP)); 3718 } 3719 3720 mss = m_head->m_pkthdr.segsz; 3721 txbd_tso_flags |= 3722 BGE_TXBDFLAG_CPU_PRE_DMA | 3723 BGE_TXBDFLAG_CPU_POST_DMA; 3724 3725 /* 3726 * Our NIC TSO-assist assumes TSO has standard, optionless 3727 * IPv4 and TCP headers, which total 40 bytes. By default, 3728 * the NIC copies 40 bytes of IP/TCP header from the 3729 * supplied header into the IP/TCP header portion of 3730 * each post-TSO-segment. If the supplied packet has IP or 3731 * TCP options, we need to tell the NIC to copy those extra 3732 * bytes into each post-TSO header, in addition to the normal 3733 * 40-byte IP/TCP header (and to leave space accordingly). 3734 * Unfortunately, the driver encoding of option length 3735 * varies across different ASIC families. 3736 */ 3737 tcp_seg_flags = 0; 3738 if (iptcp_opt_words) { 3739 if ( BGE_IS_5705_OR_BEYOND(sc)) { 3740 tcp_seg_flags = 3741 iptcp_opt_words << 11; 3742 } else { 3743 txbd_tso_flags |= 3744 iptcp_opt_words << 12; 3745 } 3746 } 3747 maxsegsize = mss | tcp_seg_flags; 3748 ip->ip_len = htons(mss + ip_tcp_hlen); 3749 3750 } /* TSO setup */ 3751 3752 /* 3753 * Start packing the mbufs in this chain into 3754 * the fragment pointers. Stop when we run out 3755 * of fragments or hit the end of the mbuf chain. 3756 */ 3757 error = bus_dmamap_load_mbuf(sc->bge_dmatag, dmamap, m_head, 3758 BUS_DMA_NOWAIT); 3759 if (error) { 3760 return(ENOBUFS); 3761 } 3762 /* 3763 * Sanity check: avoid coming within 16 descriptors 3764 * of the end of the ring. 3765 */ 3766 if (dmamap->dm_nsegs > (BGE_TX_RING_CNT - sc->bge_txcnt - 16)) { 3767 BGE_TSO_PRINTF(("%s: " 3768 " dmamap_load_mbuf too close to ring wrap\n", 3769 sc->bge_dev.dv_xname)); 3770 goto fail_unload; 3771 } 3772 3773 mtag = sc->ethercom.ec_nvlans ? 3774 m_tag_find(m_head, PACKET_TAG_VLAN, NULL) : NULL; 3775 3776 3777 /* Iterate over dmap-map fragments. */ 3778 for (i = 0; i < dmamap->dm_nsegs; i++) { 3779 f = &sc->bge_rdata->bge_tx_ring[frag]; 3780 if (sc->bge_cdata.bge_tx_chain[frag] != NULL) 3781 break; 3782 3783 bge_set_hostaddr(&f->bge_addr, dmamap->dm_segs[i].ds_addr); 3784 f->bge_len = dmamap->dm_segs[i].ds_len; 3785 3786 /* 3787 * For 5751 and follow-ons, for TSO we must turn 3788 * off checksum-assist flag in the tx-descr, and 3789 * supply the ASIC-revision-specific encoding 3790 * of TSO flags and segsize. 3791 */ 3792 if (use_tso) { 3793 if (BGE_IS_5750_OR_BEYOND(sc) || i == 0) { 3794 f->bge_rsvd = maxsegsize; 3795 f->bge_flags = csum_flags | txbd_tso_flags; 3796 } else { 3797 f->bge_rsvd = 0; 3798 f->bge_flags = 3799 (csum_flags | txbd_tso_flags) & 0x0fff; 3800 } 3801 } else { 3802 f->bge_rsvd = 0; 3803 f->bge_flags = csum_flags; 3804 } 3805 3806 if (mtag != NULL) { 3807 f->bge_flags |= BGE_TXBDFLAG_VLAN_TAG; 3808 f->bge_vlan_tag = VLAN_TAG_VALUE(mtag); 3809 } else { 3810 f->bge_vlan_tag = 0; 3811 } 3812 cur = frag; 3813 BGE_INC(frag, BGE_TX_RING_CNT); 3814 } 3815 3816 if (i < dmamap->dm_nsegs) { 3817 BGE_TSO_PRINTF(("%s: reached %d < dm_nsegs %d\n", 3818 sc->bge_dev.dv_xname, i, dmamap->dm_nsegs)); 3819 goto fail_unload; 3820 } 3821 3822 bus_dmamap_sync(sc->bge_dmatag, dmamap, 0, dmamap->dm_mapsize, 3823 BUS_DMASYNC_PREWRITE); 3824 3825 if (frag == sc->bge_tx_saved_considx) { 3826 BGE_TSO_PRINTF(("%s: frag %d = wrapped id %d?\n", 3827 sc->bge_dev.dv_xname, frag, sc->bge_tx_saved_considx)); 3828 3829 goto fail_unload; 3830 } 3831 3832 sc->bge_rdata->bge_tx_ring[cur].bge_flags |= BGE_TXBDFLAG_END; 3833 sc->bge_cdata.bge_tx_chain[cur] = m_head; 3834 SLIST_REMOVE_HEAD(&sc->txdma_list, link); 3835 sc->txdma[cur] = dma; 3836 sc->bge_txcnt += dmamap->dm_nsegs; 3837 3838 *txidx = frag; 3839 3840 return(0); 3841 3842 fail_unload: 3843 bus_dmamap_unload(sc->bge_dmatag, dmamap); 3844 3845 return ENOBUFS; 3846 } 3847 3848 /* 3849 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 3850 * to the mbuf data regions directly in the transmit descriptors. 3851 */ 3852 static void 3853 bge_start(struct ifnet *ifp) 3854 { 3855 struct bge_softc *sc; 3856 struct mbuf *m_head = NULL; 3857 u_int32_t prodidx; 3858 int pkts = 0; 3859 3860 sc = ifp->if_softc; 3861 3862 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 3863 return; 3864 3865 prodidx = sc->bge_tx_prodidx; 3866 3867 while(sc->bge_cdata.bge_tx_chain[prodidx] == NULL) { 3868 IFQ_POLL(&ifp->if_snd, m_head); 3869 if (m_head == NULL) 3870 break; 3871 3872 #if 0 3873 /* 3874 * XXX 3875 * safety overkill. If this is a fragmented packet chain 3876 * with delayed TCP/UDP checksums, then only encapsulate 3877 * it if we have enough descriptors to handle the entire 3878 * chain at once. 3879 * (paranoia -- may not actually be needed) 3880 */ 3881 if (m_head->m_flags & M_FIRSTFRAG && 3882 m_head->m_pkthdr.csum_flags & (CSUM_DELAY_DATA)) { 3883 if ((BGE_TX_RING_CNT - sc->bge_txcnt) < 3884 M_CSUM_DATA_IPv4_OFFSET(m_head->m_pkthdr.csum_data) + 16) { 3885 ifp->if_flags |= IFF_OACTIVE; 3886 break; 3887 } 3888 } 3889 #endif 3890 3891 /* 3892 * Pack the data into the transmit ring. If we 3893 * don't have room, set the OACTIVE flag and wait 3894 * for the NIC to drain the ring. 3895 */ 3896 if (bge_encap(sc, m_head, &prodidx)) { 3897 ifp->if_flags |= IFF_OACTIVE; 3898 break; 3899 } 3900 3901 /* now we are committed to transmit the packet */ 3902 IFQ_DEQUEUE(&ifp->if_snd, m_head); 3903 pkts++; 3904 3905 #if NBPFILTER > 0 3906 /* 3907 * If there's a BPF listener, bounce a copy of this frame 3908 * to him. 3909 */ 3910 if (ifp->if_bpf) 3911 bpf_mtap(ifp->if_bpf, m_head); 3912 #endif 3913 } 3914 if (pkts == 0) 3915 return; 3916 3917 /* Transmit */ 3918 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); 3919 if (sc->bge_quirks & BGE_QUIRK_PRODUCER_BUG) /* 5700 b2 errata */ 3920 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); 3921 3922 sc->bge_tx_prodidx = prodidx; 3923 3924 /* 3925 * Set a timeout in case the chip goes out to lunch. 3926 */ 3927 ifp->if_timer = 5; 3928 } 3929 3930 static int 3931 bge_init(struct ifnet *ifp) 3932 { 3933 struct bge_softc *sc = ifp->if_softc; 3934 u_int16_t *m; 3935 int s, error; 3936 3937 s = splnet(); 3938 3939 ifp = &sc->ethercom.ec_if; 3940 3941 /* Cancel pending I/O and flush buffers. */ 3942 bge_stop(sc); 3943 bge_reset(sc); 3944 bge_chipinit(sc); 3945 3946 /* 3947 * Init the various state machines, ring 3948 * control blocks and firmware. 3949 */ 3950 error = bge_blockinit(sc); 3951 if (error != 0) { 3952 printf("%s: initialization error %d\n", sc->bge_dev.dv_xname, 3953 error); 3954 splx(s); 3955 return error; 3956 } 3957 3958 ifp = &sc->ethercom.ec_if; 3959 3960 /* Specify MTU. */ 3961 CSR_WRITE_4(sc, BGE_RX_MTU, ifp->if_mtu + 3962 ETHER_HDR_LEN + ETHER_CRC_LEN + ETHER_VLAN_ENCAP_LEN); 3963 3964 /* Load our MAC address. */ 3965 m = (u_int16_t *)&(LLADDR(ifp->if_sadl)[0]); 3966 CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0])); 3967 CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, (htons(m[1]) << 16) | htons(m[2])); 3968 3969 /* Enable or disable promiscuous mode as needed. */ 3970 if (ifp->if_flags & IFF_PROMISC) { 3971 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 3972 } else { 3973 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 3974 } 3975 3976 /* Program multicast filter. */ 3977 bge_setmulti(sc); 3978 3979 /* Init RX ring. */ 3980 bge_init_rx_ring_std(sc); 3981 3982 /* Init jumbo RX ring. */ 3983 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 3984 bge_init_rx_ring_jumbo(sc); 3985 3986 /* Init our RX return ring index */ 3987 sc->bge_rx_saved_considx = 0; 3988 3989 /* Init TX ring. */ 3990 bge_init_tx_ring(sc); 3991 3992 /* Turn on transmitter */ 3993 BGE_SETBIT(sc, BGE_TX_MODE, BGE_TXMODE_ENABLE); 3994 3995 /* Turn on receiver */ 3996 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE); 3997 3998 CSR_WRITE_4(sc, BGE_MAX_RX_FRAME_LOWAT, 2); 3999 4000 /* Tell firmware we're alive. */ 4001 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 4002 4003 /* Enable host interrupts. */ 4004 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA); 4005 BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); 4006 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 0); 4007 4008 bge_ifmedia_upd(ifp); 4009 4010 ifp->if_flags |= IFF_RUNNING; 4011 ifp->if_flags &= ~IFF_OACTIVE; 4012 4013 splx(s); 4014 4015 callout_reset(&sc->bge_timeout, hz, bge_tick, sc); 4016 4017 return 0; 4018 } 4019 4020 /* 4021 * Set media options. 4022 */ 4023 static int 4024 bge_ifmedia_upd(struct ifnet *ifp) 4025 { 4026 struct bge_softc *sc = ifp->if_softc; 4027 struct mii_data *mii = &sc->bge_mii; 4028 struct ifmedia *ifm = &sc->bge_ifmedia; 4029 4030 /* If this is a 1000baseX NIC, enable the TBI port. */ 4031 if (sc->bge_tbi) { 4032 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 4033 return(EINVAL); 4034 switch(IFM_SUBTYPE(ifm->ifm_media)) { 4035 case IFM_AUTO: 4036 break; 4037 case IFM_1000_SX: 4038 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 4039 BGE_CLRBIT(sc, BGE_MAC_MODE, 4040 BGE_MACMODE_HALF_DUPLEX); 4041 } else { 4042 BGE_SETBIT(sc, BGE_MAC_MODE, 4043 BGE_MACMODE_HALF_DUPLEX); 4044 } 4045 break; 4046 default: 4047 return(EINVAL); 4048 } 4049 /* XXX 802.3x flow control for 1000BASE-SX */ 4050 return(0); 4051 } 4052 4053 sc->bge_link = 0; 4054 mii_mediachg(mii); 4055 4056 return(0); 4057 } 4058 4059 /* 4060 * Report current media status. 4061 */ 4062 static void 4063 bge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 4064 { 4065 struct bge_softc *sc = ifp->if_softc; 4066 struct mii_data *mii = &sc->bge_mii; 4067 4068 if (sc->bge_tbi) { 4069 ifmr->ifm_status = IFM_AVALID; 4070 ifmr->ifm_active = IFM_ETHER; 4071 if (CSR_READ_4(sc, BGE_MAC_STS) & 4072 BGE_MACSTAT_TBI_PCS_SYNCHED) 4073 ifmr->ifm_status |= IFM_ACTIVE; 4074 ifmr->ifm_active |= IFM_1000_SX; 4075 if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX) 4076 ifmr->ifm_active |= IFM_HDX; 4077 else 4078 ifmr->ifm_active |= IFM_FDX; 4079 return; 4080 } 4081 4082 mii_pollstat(mii); 4083 ifmr->ifm_status = mii->mii_media_status; 4084 ifmr->ifm_active = (mii->mii_media_active & ~IFM_ETH_FMASK) | 4085 sc->bge_flowflags; 4086 } 4087 4088 static int 4089 bge_ioctl(struct ifnet *ifp, u_long command, void *data) 4090 { 4091 struct bge_softc *sc = ifp->if_softc; 4092 struct ifreq *ifr = (struct ifreq *) data; 4093 int s, error = 0; 4094 struct mii_data *mii; 4095 4096 s = splnet(); 4097 4098 switch(command) { 4099 case SIOCSIFFLAGS: 4100 if (ifp->if_flags & IFF_UP) { 4101 /* 4102 * If only the state of the PROMISC flag changed, 4103 * then just use the 'set promisc mode' command 4104 * instead of reinitializing the entire NIC. Doing 4105 * a full re-init means reloading the firmware and 4106 * waiting for it to start up, which may take a 4107 * second or two. 4108 */ 4109 if (ifp->if_flags & IFF_RUNNING && 4110 ifp->if_flags & IFF_PROMISC && 4111 !(sc->bge_if_flags & IFF_PROMISC)) { 4112 BGE_SETBIT(sc, BGE_RX_MODE, 4113 BGE_RXMODE_RX_PROMISC); 4114 } else if (ifp->if_flags & IFF_RUNNING && 4115 !(ifp->if_flags & IFF_PROMISC) && 4116 sc->bge_if_flags & IFF_PROMISC) { 4117 BGE_CLRBIT(sc, BGE_RX_MODE, 4118 BGE_RXMODE_RX_PROMISC); 4119 } else if (!(sc->bge_if_flags & IFF_UP)) 4120 bge_init(ifp); 4121 } else { 4122 if (ifp->if_flags & IFF_RUNNING) { 4123 bge_stop(sc); 4124 } 4125 } 4126 sc->bge_if_flags = ifp->if_flags; 4127 error = 0; 4128 break; 4129 case SIOCSIFMEDIA: 4130 /* XXX Flow control is not supported for 1000BASE-SX */ 4131 if (sc->bge_tbi) { 4132 ifr->ifr_media &= ~IFM_ETH_FMASK; 4133 sc->bge_flowflags = 0; 4134 } 4135 4136 /* Flow control requires full-duplex mode. */ 4137 if (IFM_SUBTYPE(ifr->ifr_media) == IFM_AUTO || 4138 (ifr->ifr_media & IFM_FDX) == 0) { 4139 ifr->ifr_media &= ~IFM_ETH_FMASK; 4140 } 4141 if (IFM_SUBTYPE(ifr->ifr_media) != IFM_AUTO) { 4142 if ((ifr->ifr_media & IFM_ETH_FMASK) == IFM_FLOW) { 4143 /* We an do both TXPAUSE and RXPAUSE. */ 4144 ifr->ifr_media |= 4145 IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE; 4146 } 4147 sc->bge_flowflags = ifr->ifr_media & IFM_ETH_FMASK; 4148 } 4149 /* FALLTHROUGH */ 4150 case SIOCGIFMEDIA: 4151 if (sc->bge_tbi) { 4152 error = ifmedia_ioctl(ifp, ifr, &sc->bge_ifmedia, 4153 command); 4154 } else { 4155 mii = &sc->bge_mii; 4156 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, 4157 command); 4158 } 4159 break; 4160 default: 4161 error = ether_ioctl(ifp, command, data); 4162 if (error == ENETRESET) { 4163 if (ifp->if_flags & IFF_RUNNING) 4164 bge_setmulti(sc); 4165 error = 0; 4166 } 4167 break; 4168 } 4169 4170 splx(s); 4171 4172 return(error); 4173 } 4174 4175 static void 4176 bge_watchdog(struct ifnet *ifp) 4177 { 4178 struct bge_softc *sc; 4179 4180 sc = ifp->if_softc; 4181 4182 printf("%s: watchdog timeout -- resetting\n", sc->bge_dev.dv_xname); 4183 4184 ifp->if_flags &= ~IFF_RUNNING; 4185 bge_init(ifp); 4186 4187 ifp->if_oerrors++; 4188 } 4189 4190 static void 4191 bge_stop_block(struct bge_softc *sc, bus_addr_t reg, uint32_t bit) 4192 { 4193 int i; 4194 4195 BGE_CLRBIT(sc, reg, bit); 4196 4197 for (i = 0; i < BGE_TIMEOUT; i++) { 4198 if ((CSR_READ_4(sc, reg) & bit) == 0) 4199 return; 4200 delay(100); 4201 if (sc->bge_pcie) 4202 DELAY(1000); 4203 } 4204 4205 printf("%s: block failed to stop: reg 0x%lx, bit 0x%08x\n", 4206 sc->bge_dev.dv_xname, (u_long) reg, bit); 4207 } 4208 4209 /* 4210 * Stop the adapter and free any mbufs allocated to the 4211 * RX and TX lists. 4212 */ 4213 static void 4214 bge_stop(struct bge_softc *sc) 4215 { 4216 struct ifnet *ifp = &sc->ethercom.ec_if; 4217 4218 callout_stop(&sc->bge_timeout); 4219 4220 /* 4221 * Disable all of the receiver blocks 4222 */ 4223 bge_stop_block(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE); 4224 bge_stop_block(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 4225 bge_stop_block(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 4226 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 4227 bge_stop_block(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 4228 } 4229 bge_stop_block(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE); 4230 bge_stop_block(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 4231 bge_stop_block(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE); 4232 4233 /* 4234 * Disable all of the transmit blocks 4235 */ 4236 bge_stop_block(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 4237 bge_stop_block(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 4238 bge_stop_block(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 4239 bge_stop_block(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE); 4240 bge_stop_block(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE); 4241 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 4242 bge_stop_block(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 4243 } 4244 bge_stop_block(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 4245 4246 /* 4247 * Shut down all of the memory managers and related 4248 * state machines. 4249 */ 4250 bge_stop_block(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE); 4251 bge_stop_block(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE); 4252 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 4253 bge_stop_block(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 4254 } 4255 4256 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 4257 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 4258 4259 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 4260 bge_stop_block(sc, BGE_BMAN_MODE, BGE_BMANMODE_ENABLE); 4261 bge_stop_block(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 4262 } 4263 4264 /* Disable host interrupts. */ 4265 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); 4266 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 1); 4267 4268 /* 4269 * Tell firmware we're shutting down. 4270 */ 4271 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 4272 4273 /* Free the RX lists. */ 4274 bge_free_rx_ring_std(sc); 4275 4276 /* Free jumbo RX list. */ 4277 bge_free_rx_ring_jumbo(sc); 4278 4279 /* Free TX buffers. */ 4280 bge_free_tx_ring(sc); 4281 4282 /* 4283 * Isolate/power down the PHY. 4284 */ 4285 if (!sc->bge_tbi) 4286 mii_down(&sc->bge_mii); 4287 4288 sc->bge_link = 0; 4289 4290 sc->bge_tx_saved_considx = BGE_TXCONS_UNSET; 4291 4292 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 4293 } 4294 4295 /* 4296 * Stop all chip I/O so that the kernel's probe routines don't 4297 * get confused by errant DMAs when rebooting. 4298 */ 4299 static void 4300 bge_shutdown(void *xsc) 4301 { 4302 struct bge_softc *sc = (struct bge_softc *)xsc; 4303 4304 bge_stop(sc); 4305 bge_reset(sc); 4306 } 4307 4308 4309 static int 4310 sysctl_bge_verify(SYSCTLFN_ARGS) 4311 { 4312 int error, t; 4313 struct sysctlnode node; 4314 4315 node = *rnode; 4316 t = *(int*)rnode->sysctl_data; 4317 node.sysctl_data = &t; 4318 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 4319 if (error || newp == NULL) 4320 return (error); 4321 4322 #if 0 4323 DPRINTF2(("%s: t = %d, nodenum = %d, rnodenum = %d\n", __func__, t, 4324 node.sysctl_num, rnode->sysctl_num)); 4325 #endif 4326 4327 if (node.sysctl_num == bge_rxthresh_nodenum) { 4328 if (t < 0 || t >= NBGE_RX_THRESH) 4329 return (EINVAL); 4330 bge_update_all_threshes(t); 4331 } else 4332 return (EINVAL); 4333 4334 *(int*)rnode->sysctl_data = t; 4335 4336 return (0); 4337 } 4338 4339 /* 4340 * Set up sysctl(3) MIB, hw.bge.*. 4341 * 4342 * TBD condition SYSCTL_PERMANENT on being an LKM or not 4343 */ 4344 SYSCTL_SETUP(sysctl_bge, "sysctl bge subtree setup") 4345 { 4346 int rc, bge_root_num; 4347 const struct sysctlnode *node; 4348 4349 if ((rc = sysctl_createv(clog, 0, NULL, NULL, 4350 CTLFLAG_PERMANENT, CTLTYPE_NODE, "hw", NULL, 4351 NULL, 0, NULL, 0, CTL_HW, CTL_EOL)) != 0) { 4352 goto err; 4353 } 4354 4355 if ((rc = sysctl_createv(clog, 0, NULL, &node, 4356 CTLFLAG_PERMANENT, CTLTYPE_NODE, "bge", 4357 SYSCTL_DESCR("BGE interface controls"), 4358 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL)) != 0) { 4359 goto err; 4360 } 4361 4362 bge_root_num = node->sysctl_num; 4363 4364 /* BGE Rx interrupt mitigation level */ 4365 if ((rc = sysctl_createv(clog, 0, NULL, &node, 4366 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, 4367 CTLTYPE_INT, "rx_lvl", 4368 SYSCTL_DESCR("BGE receive interrupt mitigation level"), 4369 sysctl_bge_verify, 0, 4370 &bge_rx_thresh_lvl, 4371 0, CTL_HW, bge_root_num, CTL_CREATE, 4372 CTL_EOL)) != 0) { 4373 goto err; 4374 } 4375 4376 bge_rxthresh_nodenum = node->sysctl_num; 4377 4378 return; 4379 4380 err: 4381 printf("%s: sysctl_createv failed (rc = %d)\n", __func__, rc); 4382 } 4383 4384 static void 4385 bge_powerhook(int why, void *hdl) 4386 { 4387 struct bge_softc *sc = (struct bge_softc *)hdl; 4388 struct ifnet *ifp = &sc->ethercom.ec_if; 4389 struct pci_attach_args *pa = &(sc->bge_pa); 4390 pci_chipset_tag_t pc = pa->pa_pc; 4391 pcitag_t tag = pa->pa_tag; 4392 4393 switch (why) { 4394 case PWR_SOFTSUSPEND: 4395 case PWR_SOFTSTANDBY: 4396 bge_shutdown(sc); 4397 break; 4398 case PWR_SOFTRESUME: 4399 if (ifp->if_flags & IFF_UP) { 4400 ifp->if_flags &= ~IFF_RUNNING; 4401 bge_init(ifp); 4402 } 4403 break; 4404 case PWR_SUSPEND: 4405 case PWR_STANDBY: 4406 pci_conf_capture(pc, tag, &sc->bge_pciconf); 4407 break; 4408 case PWR_RESUME: 4409 pci_conf_restore(pc, tag, &sc->bge_pciconf); 4410 break; 4411 } 4412 4413 return; 4414 } 4415
Indexes created Tue Sep 23 02:09:52 GMT 2025