if_bge.c revision 1.14
1 /* $NetBSD: if_bge.c,v 1.14 2002/07/12 22:29:14 enami Exp $ */ 2 3 /* 4 * Copyright (c) 2001 Wind River Systems 5 * Copyright (c) 1997, 1998, 1999, 2001 6 * Bill Paul <wpaul (at) windriver.com>. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Bill Paul. 19 * 4. Neither the name of the author nor the names of any co-contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 33 * THE POSSIBILITY OF SUCH DAMAGE. 34 * 35 * $FreeBSD: if_bge.c,v 1.13 2002/04/04 06:01:31 wpaul Exp $ 36 */ 37 38 /* 39 * Broadcom BCM570x family gigabit ethernet driver for NetBSD. 40 * 41 * NetBSD version by: 42 * 43 * Frank van der Linden <fvdl (at) wasabisystems.com> 44 * Jason Thorpe <thorpej (at) wasabisystems.com> 45 * 46 * Originally written for FreeBSD by Bill Paul <wpaul (at) windriver.com> 47 * Senior Engineer, Wind River Systems 48 */ 49 50 /* 51 * The Broadcom BCM5700 is based on technology originally developed by 52 * Alteon Networks as part of the Tigon I and Tigon II gigabit ethernet 53 * MAC chips. The BCM5700, sometimes refered to as the Tigon III, has 54 * two on-board MIPS R4000 CPUs and can have as much as 16MB of external 55 * SSRAM. The BCM5700 supports TCP, UDP and IP checksum offload, jumbo 56 * frames, highly configurable RX filtering, and 16 RX and TX queues 57 * (which, along with RX filter rules, can be used for QOS applications). 58 * Other features, such as TCP segmentation, may be available as part 59 * of value-added firmware updates. Unlike the Tigon I and Tigon II, 60 * firmware images can be stored in hardware and need not be compiled 61 * into the driver. 62 * 63 * The BCM5700 supports the PCI v2.2 and PCI-X v1.0 standards, and will 64 * function in a 32-bit/64-bit 33/66Mhz bus, or a 64-bit/133Mhz bus. 65 * 66 * The BCM5701 is a single-chip solution incorporating both the BCM5700 67 * MAC and a BCM5401 10/100/1000 PHY. Unlike the BCM5700, the BCM5700 68 * does not support external SSRAM. 69 * 70 * Broadcom also produces a variation of the BCM5700 under the "Altima" 71 * brand name, which is functionally similar but lacks PCI-X support. 72 * 73 * Without external SSRAM, you can only have at most 4 TX rings, 74 * and the use of the mini RX ring is disabled. This seems to imply 75 * that these features are simply not available on the BCM5701. As a 76 * result, this driver does not implement any support for the mini RX 77 * ring. 78 */ 79 80 #include "bpfilter.h" 81 #include "vlan.h" 82 83 #include <sys/param.h> 84 #include <sys/systm.h> 85 #include <sys/callout.h> 86 #include <sys/sockio.h> 87 #include <sys/mbuf.h> 88 #include <sys/malloc.h> 89 #include <sys/kernel.h> 90 #include <sys/device.h> 91 #include <sys/socket.h> 92 93 #include <net/if.h> 94 #include <net/if_dl.h> 95 #include <net/if_media.h> 96 #include <net/if_ether.h> 97 98 #ifdef INET 99 #include <netinet/in.h> 100 #include <netinet/in_systm.h> 101 #include <netinet/in_var.h> 102 #include <netinet/ip.h> 103 #endif 104 105 #if NBPFILTER > 0 106 #include <net/bpf.h> 107 #endif 108 109 #include <dev/pci/pcireg.h> 110 #include <dev/pci/pcivar.h> 111 #include <dev/pci/pcidevs.h> 112 113 #include <dev/mii/mii.h> 114 #include <dev/mii/miivar.h> 115 #include <dev/mii/miidevs.h> 116 #include <dev/mii/brgphyreg.h> 117 118 #include <dev/pci/if_bgereg.h> 119 120 #include <uvm/uvm_extern.h> 121 122 /* #define BGE_CHECKSUM */ 123 124 int bge_probe(struct device *, struct cfdata *, void *); 125 void bge_attach(struct device *, struct device *, void *); 126 void bge_release_resources(struct bge_softc *); 127 void bge_txeof(struct bge_softc *); 128 void bge_rxeof(struct bge_softc *); 129 130 void bge_tick(void *); 131 void bge_stats_update(struct bge_softc *); 132 int bge_encap(struct bge_softc *, struct mbuf *, u_int32_t *); 133 134 int bge_intr(void *); 135 void bge_start(struct ifnet *); 136 int bge_ioctl(struct ifnet *, u_long, caddr_t); 137 int bge_init(struct ifnet *); 138 void bge_stop(struct bge_softc *); 139 void bge_watchdog(struct ifnet *); 140 void bge_shutdown(void *); 141 int bge_ifmedia_upd(struct ifnet *); 142 void bge_ifmedia_sts(struct ifnet *, struct ifmediareq *); 143 144 u_int8_t bge_eeprom_getbyte(struct bge_softc *, int, u_int8_t *); 145 int bge_read_eeprom(struct bge_softc *, caddr_t, int, int); 146 147 void bge_setmulti(struct bge_softc *); 148 149 void bge_handle_events(struct bge_softc *); 150 int bge_alloc_jumbo_mem(struct bge_softc *); 151 void bge_free_jumbo_mem(struct bge_softc *); 152 void *bge_jalloc(struct bge_softc *); 153 void bge_jfree(struct mbuf *, caddr_t, u_int, void *); 154 int bge_newbuf_std(struct bge_softc *, int, struct mbuf *, bus_dmamap_t); 155 int bge_newbuf_jumbo(struct bge_softc *, int, struct mbuf *); 156 int bge_init_rx_ring_std(struct bge_softc *); 157 void bge_free_rx_ring_std(struct bge_softc *); 158 int bge_init_rx_ring_jumbo(struct bge_softc *); 159 void bge_free_rx_ring_jumbo(struct bge_softc *); 160 void bge_free_tx_ring(struct bge_softc *); 161 int bge_init_tx_ring(struct bge_softc *); 162 163 int bge_chipinit(struct bge_softc *); 164 int bge_blockinit(struct bge_softc *); 165 166 #ifdef notdef 167 u_int8_t bge_vpd_readbyte(struct bge_softc *, int); 168 void bge_vpd_read_res(struct bge_softc *, struct vpd_res *, int); 169 void bge_vpd_read(struct bge_softc *); 170 #endif 171 172 u_int32_t bge_readmem_ind(struct bge_softc *, int); 173 void bge_writemem_ind(struct bge_softc *, int, int); 174 #ifdef notdef 175 u_int32_t bge_readreg_ind(struct bge_softc *, int); 176 #endif 177 void bge_writereg_ind(struct bge_softc *, int, int); 178 179 int bge_miibus_readreg(struct device *, int, int); 180 void bge_miibus_writereg(struct device *, int, int, int); 181 void bge_miibus_statchg(struct device *); 182 183 void bge_reset(struct bge_softc *); 184 void bge_phy_hack(struct bge_softc *); 185 186 void bge_dump_status(struct bge_softc *); 187 void bge_dump_rxbd(struct bge_rx_bd *); 188 189 #define BGE_DEBUG 190 #ifdef BGE_DEBUG 191 #define DPRINTF(x) if (bgedebug) printf x 192 #define DPRINTFN(n,x) if (bgedebug >= (n)) printf x 193 int bgedebug = 0; 194 #else 195 #define DPRINTF(x) 196 #define DPRINTFN(n,x) 197 #endif 198 199 struct cfattach bge_ca = { 200 sizeof(struct bge_softc), bge_probe, bge_attach 201 }; 202 203 u_int32_t 204 bge_readmem_ind(sc, off) 205 struct bge_softc *sc; 206 int off; 207 { 208 struct pci_attach_args *pa = &(sc->bge_pa); 209 pcireg_t val; 210 211 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_MEMWIN_BASEADDR, off); 212 val = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_MEMWIN_DATA); 213 return val; 214 } 215 216 void 217 bge_writemem_ind(sc, off, val) 218 struct bge_softc *sc; 219 int off, val; 220 { 221 struct pci_attach_args *pa = &(sc->bge_pa); 222 223 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_MEMWIN_BASEADDR, off); 224 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_MEMWIN_DATA, val); 225 } 226 227 #ifdef notdef 228 u_int32_t 229 bge_readreg_ind(sc, off) 230 struct bge_softc *sc; 231 int off; 232 { 233 struct pci_attach_args *pa = &(sc->bge_pa); 234 235 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_REG_BASEADDR, off); 236 return(pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_REG_DATA)); 237 } 238 #endif 239 240 void 241 bge_writereg_ind(sc, off, val) 242 struct bge_softc *sc; 243 int off, val; 244 { 245 struct pci_attach_args *pa = &(sc->bge_pa); 246 247 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_REG_BASEADDR, off); 248 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_REG_DATA, val); 249 } 250 251 #ifdef notdef 252 u_int8_t 253 bge_vpd_readbyte(sc, addr) 254 struct bge_softc *sc; 255 int addr; 256 { 257 int i; 258 u_int32_t val; 259 struct pci_attach_args *pa = &(sc->bge_pa); 260 261 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_VPD_ADDR, addr); 262 for (i = 0; i < BGE_TIMEOUT * 10; i++) { 263 DELAY(10); 264 if (pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_VPD_ADDR) & 265 BGE_VPD_FLAG) 266 break; 267 } 268 269 if (i == BGE_TIMEOUT) { 270 printf("%s: VPD read timed out\n", sc->bge_dev.dv_xname); 271 return(0); 272 } 273 274 val = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_VPD_DATA); 275 276 return((val >> ((addr % 4) * 8)) & 0xFF); 277 } 278 279 void 280 bge_vpd_read_res(sc, res, addr) 281 struct bge_softc *sc; 282 struct vpd_res *res; 283 int addr; 284 { 285 int i; 286 u_int8_t *ptr; 287 288 ptr = (u_int8_t *)res; 289 for (i = 0; i < sizeof(struct vpd_res); i++) 290 ptr[i] = bge_vpd_readbyte(sc, i + addr); 291 } 292 293 void 294 bge_vpd_read(sc) 295 struct bge_softc *sc; 296 { 297 int pos = 0, i; 298 struct vpd_res res; 299 300 if (sc->bge_vpd_prodname != NULL) 301 free(sc->bge_vpd_prodname, M_DEVBUF); 302 if (sc->bge_vpd_readonly != NULL) 303 free(sc->bge_vpd_readonly, M_DEVBUF); 304 sc->bge_vpd_prodname = NULL; 305 sc->bge_vpd_readonly = NULL; 306 307 bge_vpd_read_res(sc, &res, pos); 308 309 if (res.vr_id != VPD_RES_ID) { 310 printf("%s: bad VPD resource id: expected %x got %x\n", 311 sc->bge_dev.dv_xname, VPD_RES_ID, res.vr_id); 312 return; 313 } 314 315 pos += sizeof(res); 316 sc->bge_vpd_prodname = malloc(res.vr_len + 1, M_DEVBUF, M_NOWAIT); 317 if (sc->bge_vpd_prodname == NULL) 318 panic("bge_vpd_read"); 319 for (i = 0; i < res.vr_len; i++) 320 sc->bge_vpd_prodname[i] = bge_vpd_readbyte(sc, i + pos); 321 sc->bge_vpd_prodname[i] = '\0'; 322 pos += i; 323 324 bge_vpd_read_res(sc, &res, pos); 325 326 if (res.vr_id != VPD_RES_READ) { 327 printf("%s: bad VPD resource id: expected %x got %x\n", 328 sc->bge_dev.dv_xname, VPD_RES_READ, res.vr_id); 329 return; 330 } 331 332 pos += sizeof(res); 333 sc->bge_vpd_readonly = malloc(res.vr_len, M_DEVBUF, M_NOWAIT); 334 if (sc->bge_vpd_readonly == NULL) 335 panic("bge_vpd_read"); 336 for (i = 0; i < res.vr_len + 1; i++) 337 sc->bge_vpd_readonly[i] = bge_vpd_readbyte(sc, i + pos); 338 } 339 #endif 340 341 /* 342 * Read a byte of data stored in the EEPROM at address 'addr.' The 343 * BCM570x supports both the traditional bitbang interface and an 344 * auto access interface for reading the EEPROM. We use the auto 345 * access method. 346 */ 347 u_int8_t 348 bge_eeprom_getbyte(sc, addr, dest) 349 struct bge_softc *sc; 350 int addr; 351 u_int8_t *dest; 352 { 353 int i; 354 u_int32_t byte = 0; 355 356 /* 357 * Enable use of auto EEPROM access so we can avoid 358 * having to use the bitbang method. 359 */ 360 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM); 361 362 /* Reset the EEPROM, load the clock period. */ 363 CSR_WRITE_4(sc, BGE_EE_ADDR, 364 BGE_EEADDR_RESET|BGE_EEHALFCLK(BGE_HALFCLK_384SCL)); 365 DELAY(20); 366 367 /* Issue the read EEPROM command. */ 368 CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr); 369 370 /* Wait for completion */ 371 for(i = 0; i < BGE_TIMEOUT * 10; i++) { 372 DELAY(10); 373 if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE) 374 break; 375 } 376 377 if (i == BGE_TIMEOUT) { 378 printf("%s: eeprom read timed out\n", sc->bge_dev.dv_xname); 379 return(0); 380 } 381 382 /* Get result. */ 383 byte = CSR_READ_4(sc, BGE_EE_DATA); 384 385 *dest = (byte >> ((addr % 4) * 8)) & 0xFF; 386 387 return(0); 388 } 389 390 /* 391 * Read a sequence of bytes from the EEPROM. 392 */ 393 int 394 bge_read_eeprom(sc, dest, off, cnt) 395 struct bge_softc *sc; 396 caddr_t dest; 397 int off; 398 int cnt; 399 { 400 int err = 0, i; 401 u_int8_t byte = 0; 402 403 for (i = 0; i < cnt; i++) { 404 err = bge_eeprom_getbyte(sc, off + i, &byte); 405 if (err) 406 break; 407 *(dest + i) = byte; 408 } 409 410 return(err ? 1 : 0); 411 } 412 413 int 414 bge_miibus_readreg(dev, phy, reg) 415 struct device *dev; 416 int phy, reg; 417 { 418 struct bge_softc *sc = (struct bge_softc *)dev; 419 struct ifnet *ifp; 420 u_int32_t val; 421 int i; 422 423 ifp = &sc->ethercom.ec_if; 424 425 if (sc->bge_asicrev == BGE_ASICREV_BCM5701_B5 && phy != 1) 426 return(0); 427 428 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_READ|BGE_MICOMM_BUSY| 429 BGE_MIPHY(phy)|BGE_MIREG(reg)); 430 431 for (i = 0; i < BGE_TIMEOUT; i++) { 432 val = CSR_READ_4(sc, BGE_MI_COMM); 433 if (!(val & BGE_MICOMM_BUSY)) 434 break; 435 delay(10); 436 } 437 438 if (i == BGE_TIMEOUT) { 439 printf("%s: PHY read timed out\n", sc->bge_dev.dv_xname); 440 return(0); 441 } 442 443 val = CSR_READ_4(sc, BGE_MI_COMM); 444 445 if (val & BGE_MICOMM_READFAIL) 446 return(0); 447 448 return(val & 0xFFFF); 449 } 450 451 void 452 bge_miibus_writereg(dev, phy, reg, val) 453 struct device *dev; 454 int phy, reg, val; 455 { 456 struct bge_softc *sc = (struct bge_softc *)dev; 457 int i; 458 459 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_WRITE|BGE_MICOMM_BUSY| 460 BGE_MIPHY(phy)|BGE_MIREG(reg)|val); 461 462 for (i = 0; i < BGE_TIMEOUT; i++) { 463 if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY)) 464 break; 465 delay(10); 466 } 467 468 if (i == BGE_TIMEOUT) { 469 printf("%s: PHY read timed out\n", sc->bge_dev.dv_xname); 470 } 471 } 472 473 void 474 bge_miibus_statchg(dev) 475 struct device *dev; 476 { 477 struct bge_softc *sc = (struct bge_softc *)dev; 478 struct mii_data *mii = &sc->bge_mii; 479 480 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_PORTMODE); 481 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) { 482 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_GMII); 483 } else { 484 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_MII); 485 } 486 487 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 488 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX); 489 } else { 490 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX); 491 } 492 493 bge_phy_hack(sc); 494 } 495 496 /* 497 * Handle events that have triggered interrupts. 498 */ 499 void 500 bge_handle_events(sc) 501 struct bge_softc *sc; 502 { 503 504 return; 505 } 506 507 /* 508 * Memory management for jumbo frames. 509 */ 510 511 int 512 bge_alloc_jumbo_mem(sc) 513 struct bge_softc *sc; 514 { 515 caddr_t ptr, kva; 516 bus_dma_segment_t seg; 517 int i, rseg, state, error; 518 struct bge_jpool_entry *entry; 519 520 state = error = 0; 521 522 /* Grab a big chunk o' storage. */ 523 if (bus_dmamem_alloc(sc->bge_dmatag, BGE_JMEM, PAGE_SIZE, 0, 524 &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 525 printf("%s: can't alloc rx buffers\n", sc->bge_dev.dv_xname); 526 return ENOBUFS; 527 } 528 529 state = 1; 530 if (bus_dmamem_map(sc->bge_dmatag, &seg, rseg, BGE_JMEM, &kva, 531 BUS_DMA_NOWAIT)) { 532 printf("%s: can't map dma buffers (%d bytes)\n", 533 sc->bge_dev.dv_xname, (int)BGE_JMEM); 534 error = ENOBUFS; 535 goto out; 536 } 537 538 state = 2; 539 if (bus_dmamap_create(sc->bge_dmatag, BGE_JMEM, 1, BGE_JMEM, 0, 540 BUS_DMA_NOWAIT, &sc->bge_cdata.bge_rx_jumbo_map)) { 541 printf("%s: can't create dma map\n", sc->bge_dev.dv_xname); 542 error = ENOBUFS; 543 goto out; 544 } 545 546 state = 3; 547 if (bus_dmamap_load(sc->bge_dmatag, sc->bge_cdata.bge_rx_jumbo_map, 548 kva, BGE_JMEM, NULL, BUS_DMA_NOWAIT)) { 549 printf("%s: can't load dma map\n", sc->bge_dev.dv_xname); 550 error = ENOBUFS; 551 goto out; 552 } 553 554 state = 4; 555 sc->bge_cdata.bge_jumbo_buf = (caddr_t)kva; 556 DPRINTFN(1,("bge_jumbo_buf = 0x%p\n", sc->bge_cdata.bge_jumbo_buf)); 557 558 SLIST_INIT(&sc->bge_jfree_listhead); 559 SLIST_INIT(&sc->bge_jinuse_listhead); 560 561 /* 562 * Now divide it up into 9K pieces and save the addresses 563 * in an array. 564 */ 565 ptr = sc->bge_cdata.bge_jumbo_buf; 566 for (i = 0; i < BGE_JSLOTS; i++) { 567 sc->bge_cdata.bge_jslots[i] = ptr; 568 ptr += BGE_JLEN; 569 entry = malloc(sizeof(struct bge_jpool_entry), 570 M_DEVBUF, M_NOWAIT); 571 if (entry == NULL) { 572 printf("%s: no memory for jumbo buffer queue!\n", 573 sc->bge_dev.dv_xname); 574 error = ENOBUFS; 575 goto out; 576 } 577 entry->slot = i; 578 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, 579 entry, jpool_entries); 580 } 581 out: 582 if (error != 0) { 583 switch (state) { 584 case 4: 585 bus_dmamap_unload(sc->bge_dmatag, 586 sc->bge_cdata.bge_rx_jumbo_map); 587 case 3: 588 bus_dmamap_destroy(sc->bge_dmatag, 589 sc->bge_cdata.bge_rx_jumbo_map); 590 case 2: 591 bus_dmamem_unmap(sc->bge_dmatag, kva, BGE_JMEM); 592 case 1: 593 bus_dmamem_free(sc->bge_dmatag, &seg, rseg); 594 break; 595 default: 596 break; 597 } 598 } 599 600 return error; 601 } 602 603 /* 604 * Allocate a jumbo buffer. 605 */ 606 void * 607 bge_jalloc(sc) 608 struct bge_softc *sc; 609 { 610 struct bge_jpool_entry *entry; 611 612 entry = SLIST_FIRST(&sc->bge_jfree_listhead); 613 614 if (entry == NULL) { 615 printf("%s: no free jumbo buffers\n", sc->bge_dev.dv_xname); 616 return(NULL); 617 } 618 619 SLIST_REMOVE_HEAD(&sc->bge_jfree_listhead, jpool_entries); 620 SLIST_INSERT_HEAD(&sc->bge_jinuse_listhead, entry, jpool_entries); 621 return(sc->bge_cdata.bge_jslots[entry->slot]); 622 } 623 624 /* 625 * Release a jumbo buffer. 626 */ 627 void 628 bge_jfree(m, buf, size, arg) 629 struct mbuf *m; 630 caddr_t buf; 631 u_int size; 632 void *arg; 633 { 634 struct bge_jpool_entry *entry; 635 struct bge_softc *sc; 636 int i, s; 637 638 /* Extract the softc struct pointer. */ 639 sc = (struct bge_softc *)arg; 640 641 if (sc == NULL) 642 panic("bge_jfree: can't find softc pointer!"); 643 644 /* calculate the slot this buffer belongs to */ 645 646 i = ((caddr_t)buf 647 - (caddr_t)sc->bge_cdata.bge_jumbo_buf) / BGE_JLEN; 648 649 if ((i < 0) || (i >= BGE_JSLOTS)) 650 panic("bge_jfree: asked to free buffer that we don't manage!"); 651 652 s = splvm(); 653 entry = SLIST_FIRST(&sc->bge_jinuse_listhead); 654 if (entry == NULL) 655 panic("bge_jfree: buffer not in use!"); 656 entry->slot = i; 657 SLIST_REMOVE_HEAD(&sc->bge_jinuse_listhead, jpool_entries); 658 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, entry, jpool_entries); 659 660 if (__predict_true(m != NULL)) 661 pool_cache_put(&mbpool_cache, m); 662 splx(s); 663 } 664 665 666 /* 667 * Intialize a standard receive ring descriptor. 668 */ 669 int 670 bge_newbuf_std(sc, i, m, dmamap) 671 struct bge_softc *sc; 672 int i; 673 struct mbuf *m; 674 bus_dmamap_t dmamap; 675 { 676 struct mbuf *m_new = NULL; 677 struct bge_rx_bd *r; 678 int error; 679 680 if (dmamap == NULL) { 681 error = bus_dmamap_create(sc->bge_dmatag, MCLBYTES, 1, 682 MCLBYTES, 0, BUS_DMA_NOWAIT, &dmamap); 683 if (error != 0) 684 return error; 685 } 686 687 sc->bge_cdata.bge_rx_std_map[i] = dmamap; 688 689 if (m == NULL) { 690 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 691 if (m_new == NULL) { 692 return(ENOBUFS); 693 } 694 695 MCLGET(m_new, M_DONTWAIT); 696 if (!(m_new->m_flags & M_EXT)) { 697 m_freem(m_new); 698 return(ENOBUFS); 699 } 700 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 701 m_adj(m_new, ETHER_ALIGN); 702 703 if (bus_dmamap_load_mbuf(sc->bge_dmatag, dmamap, m_new, 704 BUS_DMA_READ|BUS_DMA_NOWAIT)) 705 return(ENOBUFS); 706 } else { 707 m_new = m; 708 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 709 m_new->m_data = m_new->m_ext.ext_buf; 710 m_adj(m_new, ETHER_ALIGN); 711 } 712 713 sc->bge_cdata.bge_rx_std_chain[i] = m_new; 714 r = &sc->bge_rdata->bge_rx_std_ring[i]; 715 bge_set_hostaddr(&r->bge_addr, 716 dmamap->dm_segs[0].ds_addr); 717 r->bge_flags = BGE_RXBDFLAG_END; 718 r->bge_len = m_new->m_len; 719 r->bge_idx = i; 720 721 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 722 offsetof(struct bge_ring_data, bge_rx_std_ring) + 723 i * sizeof (struct bge_rx_bd), 724 sizeof (struct bge_rx_bd), 725 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 726 727 return(0); 728 } 729 730 /* 731 * Initialize a jumbo receive ring descriptor. This allocates 732 * a jumbo buffer from the pool managed internally by the driver. 733 */ 734 int 735 bge_newbuf_jumbo(sc, i, m) 736 struct bge_softc *sc; 737 int i; 738 struct mbuf *m; 739 { 740 struct mbuf *m_new = NULL; 741 struct bge_rx_bd *r; 742 743 if (m == NULL) { 744 caddr_t *buf = NULL; 745 746 /* Allocate the mbuf. */ 747 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 748 if (m_new == NULL) { 749 return(ENOBUFS); 750 } 751 752 /* Allocate the jumbo buffer */ 753 buf = bge_jalloc(sc); 754 if (buf == NULL) { 755 m_freem(m_new); 756 printf("%s: jumbo allocation failed " 757 "-- packet dropped!\n", sc->bge_dev.dv_xname); 758 return(ENOBUFS); 759 } 760 761 /* Attach the buffer to the mbuf. */ 762 m_new->m_len = m_new->m_pkthdr.len = BGE_JUMBO_FRAMELEN; 763 MEXTADD(m_new, buf, BGE_JUMBO_FRAMELEN, M_DEVBUF, 764 bge_jfree, sc); 765 } else { 766 m_new = m; 767 m_new->m_data = m_new->m_ext.ext_buf; 768 m_new->m_ext.ext_size = BGE_JUMBO_FRAMELEN; 769 } 770 771 m_adj(m_new, ETHER_ALIGN); 772 /* Set up the descriptor. */ 773 r = &sc->bge_rdata->bge_rx_jumbo_ring[i]; 774 sc->bge_cdata.bge_rx_jumbo_chain[i] = m_new; 775 bge_set_hostaddr(&r->bge_addr, BGE_JUMBO_DMA_ADDR(sc, m_new)); 776 r->bge_flags = BGE_RXBDFLAG_END|BGE_RXBDFLAG_JUMBO_RING; 777 r->bge_len = m_new->m_len; 778 r->bge_idx = i; 779 780 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 781 offsetof(struct bge_ring_data, bge_rx_jumbo_ring) + 782 i * sizeof (struct bge_rx_bd), 783 sizeof (struct bge_rx_bd), 784 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 785 786 return(0); 787 } 788 789 /* 790 * The standard receive ring has 512 entries in it. At 2K per mbuf cluster, 791 * that's 1MB or memory, which is a lot. For now, we fill only the first 792 * 256 ring entries and hope that our CPU is fast enough to keep up with 793 * the NIC. 794 */ 795 int 796 bge_init_rx_ring_std(sc) 797 struct bge_softc *sc; 798 { 799 int i; 800 801 if (sc->bge_flags & BGE_RXRING_VALID) 802 return 0; 803 804 for (i = 0; i < BGE_SSLOTS; i++) { 805 if (bge_newbuf_std(sc, i, NULL, 0) == ENOBUFS) 806 return(ENOBUFS); 807 } 808 809 sc->bge_std = i - 1; 810 CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std); 811 812 sc->bge_flags |= BGE_RXRING_VALID; 813 814 return(0); 815 } 816 817 void 818 bge_free_rx_ring_std(sc) 819 struct bge_softc *sc; 820 { 821 int i; 822 823 if (!(sc->bge_flags & BGE_RXRING_VALID)) 824 return; 825 826 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { 827 if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) { 828 m_freem(sc->bge_cdata.bge_rx_std_chain[i]); 829 sc->bge_cdata.bge_rx_std_chain[i] = NULL; 830 bus_dmamap_destroy(sc->bge_dmatag, 831 sc->bge_cdata.bge_rx_std_map[i]); 832 } 833 memset((char *)&sc->bge_rdata->bge_rx_std_ring[i], 0, 834 sizeof(struct bge_rx_bd)); 835 } 836 837 sc->bge_flags &= ~BGE_RXRING_VALID; 838 } 839 840 int 841 bge_init_rx_ring_jumbo(sc) 842 struct bge_softc *sc; 843 { 844 int i; 845 struct bge_rcb *rcb; 846 struct bge_rcb_opaque *rcbo; 847 848 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 849 if (bge_newbuf_jumbo(sc, i, NULL) == ENOBUFS) 850 return(ENOBUFS); 851 }; 852 853 sc->bge_jumbo = i - 1; 854 855 rcb = &sc->bge_rdata->bge_info.bge_jumbo_rx_rcb; 856 rcbo = (struct bge_rcb_opaque *)rcb; 857 rcb->bge_flags = 0; 858 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcbo->bge_reg2); 859 860 CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo); 861 862 return(0); 863 } 864 865 void 866 bge_free_rx_ring_jumbo(sc) 867 struct bge_softc *sc; 868 { 869 int i; 870 871 if (!(sc->bge_flags & BGE_JUMBO_RXRING_VALID)) 872 return; 873 874 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 875 if (sc->bge_cdata.bge_rx_jumbo_chain[i] != NULL) { 876 m_freem(sc->bge_cdata.bge_rx_jumbo_chain[i]); 877 sc->bge_cdata.bge_rx_jumbo_chain[i] = NULL; 878 } 879 memset((char *)&sc->bge_rdata->bge_rx_jumbo_ring[i], 0, 880 sizeof(struct bge_rx_bd)); 881 } 882 883 sc->bge_flags &= ~BGE_JUMBO_RXRING_VALID; 884 } 885 886 void 887 bge_free_tx_ring(sc) 888 struct bge_softc *sc; 889 { 890 int i, freed; 891 struct txdmamap_pool_entry *dma; 892 893 if (!(sc->bge_flags & BGE_TXRING_VALID)) 894 return; 895 896 freed = 0; 897 898 for (i = 0; i < BGE_TX_RING_CNT; i++) { 899 if (sc->bge_cdata.bge_tx_chain[i] != NULL) { 900 freed++; 901 m_freem(sc->bge_cdata.bge_tx_chain[i]); 902 sc->bge_cdata.bge_tx_chain[i] = NULL; 903 SLIST_INSERT_HEAD(&sc->txdma_list, sc->txdma[i], 904 link); 905 sc->txdma[i] = 0; 906 } 907 memset((char *)&sc->bge_rdata->bge_tx_ring[i], 0, 908 sizeof(struct bge_tx_bd)); 909 } 910 911 while ((dma = SLIST_FIRST(&sc->txdma_list))) { 912 SLIST_REMOVE_HEAD(&sc->txdma_list, link); 913 bus_dmamap_destroy(sc->bge_dmatag, dma->dmamap); 914 free(dma, M_DEVBUF); 915 } 916 917 sc->bge_flags &= ~BGE_TXRING_VALID; 918 } 919 920 int 921 bge_init_tx_ring(sc) 922 struct bge_softc *sc; 923 { 924 int i; 925 bus_dmamap_t dmamap; 926 struct txdmamap_pool_entry *dma; 927 928 if (sc->bge_flags & BGE_TXRING_VALID) 929 return 0; 930 931 sc->bge_txcnt = 0; 932 sc->bge_tx_saved_considx = 0; 933 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, 0); 934 CSR_WRITE_4(sc, BGE_MBX_TX_NIC_PROD0_LO, 0); 935 936 SLIST_INIT(&sc->txdma_list); 937 for (i = 0; i < BGE_RSLOTS; i++) { 938 if (bus_dmamap_create(sc->bge_dmatag, ETHER_MAX_LEN_JUMBO, 939 BGE_NTXSEG, ETHER_MAX_LEN_JUMBO, 0, BUS_DMA_NOWAIT, 940 &dmamap)) 941 return(ENOBUFS); 942 if (dmamap == NULL) 943 panic("dmamap NULL in bge_init_tx_ring"); 944 dma = malloc(sizeof(*dma), M_DEVBUF, M_NOWAIT); 945 if (dma == NULL) { 946 printf("%s: can't alloc txdmamap_pool_entry\n", 947 sc->bge_dev.dv_xname); 948 bus_dmamap_destroy(sc->bge_dmatag, dmamap); 949 return (ENOMEM); 950 } 951 dma->dmamap = dmamap; 952 SLIST_INSERT_HEAD(&sc->txdma_list, dma, link); 953 } 954 955 sc->bge_flags |= BGE_TXRING_VALID; 956 957 return(0); 958 } 959 960 void 961 bge_setmulti(sc) 962 struct bge_softc *sc; 963 { 964 struct ethercom *ac = &sc->ethercom; 965 struct ifnet *ifp = &ac->ec_if; 966 struct ether_multi *enm; 967 struct ether_multistep step; 968 u_int32_t hashes[4] = { 0, 0, 0, 0 }; 969 u_int32_t h; 970 int i; 971 972 if (ifp->if_flags & IFF_PROMISC) 973 goto allmulti; 974 975 /* Now program new ones. */ 976 ETHER_FIRST_MULTI(step, ac, enm); 977 while (enm != NULL) { 978 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 979 /* 980 * We must listen to a range of multicast addresses. 981 * For now, just accept all multicasts, rather than 982 * trying to set only those filter bits needed to match 983 * the range. (At this time, the only use of address 984 * ranges is for IP multicast routing, for which the 985 * range is big enough to require all bits set.) 986 */ 987 goto allmulti; 988 } 989 990 h = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN); 991 992 /* Just want the 7 least-significant bits. */ 993 h &= 0x7f; 994 995 hashes[(h & 0x60) >> 5] |= 1 << (h & 0x1F); 996 ETHER_NEXT_MULTI(step, enm); 997 } 998 999 ifp->if_flags &= ~IFF_ALLMULTI; 1000 goto setit; 1001 1002 allmulti: 1003 ifp->if_flags |= IFF_ALLMULTI; 1004 hashes[0] = hashes[1] = hashes[2] = hashes[3] = 0xffffffff; 1005 1006 setit: 1007 for (i = 0; i < 4; i++) 1008 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]); 1009 } 1010 1011 int bge_swapbits[] = { 1012 0, 1013 BGE_MODECTL_BYTESWAP_DATA, 1014 BGE_MODECTL_WORDSWAP_DATA, 1015 BGE_MODECTL_BYTESWAP_NONFRAME, 1016 BGE_MODECTL_WORDSWAP_NONFRAME, 1017 1018 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA, 1019 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_BYTESWAP_NONFRAME, 1020 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_NONFRAME, 1021 1022 BGE_MODECTL_WORDSWAP_DATA|BGE_MODECTL_BYTESWAP_NONFRAME, 1023 BGE_MODECTL_WORDSWAP_DATA|BGE_MODECTL_WORDSWAP_NONFRAME, 1024 1025 BGE_MODECTL_BYTESWAP_NONFRAME|BGE_MODECTL_WORDSWAP_NONFRAME, 1026 1027 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA| 1028 BGE_MODECTL_BYTESWAP_NONFRAME, 1029 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA| 1030 BGE_MODECTL_WORDSWAP_NONFRAME, 1031 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_BYTESWAP_NONFRAME| 1032 BGE_MODECTL_WORDSWAP_NONFRAME, 1033 BGE_MODECTL_WORDSWAP_DATA|BGE_MODECTL_BYTESWAP_NONFRAME| 1034 BGE_MODECTL_WORDSWAP_NONFRAME, 1035 1036 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA| 1037 BGE_MODECTL_BYTESWAP_NONFRAME|BGE_MODECTL_WORDSWAP_NONFRAME, 1038 }; 1039 1040 int bge_swapindex = 0; 1041 1042 /* 1043 * Do endian, PCI and DMA initialization. Also check the on-board ROM 1044 * self-test results. 1045 */ 1046 int 1047 bge_chipinit(sc) 1048 struct bge_softc *sc; 1049 { 1050 u_int32_t cachesize; 1051 int i; 1052 struct pci_attach_args *pa = &(sc->bge_pa); 1053 1054 1055 /* Set endianness before we access any non-PCI registers. */ 1056 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_MISC_CTL, 1057 BGE_INIT); 1058 1059 /* 1060 * Check the 'ROM failed' bit on the RX CPU to see if 1061 * self-tests passed. 1062 */ 1063 if (CSR_READ_4(sc, BGE_RXCPU_MODE) & BGE_RXCPUMODE_ROMFAIL) { 1064 printf("%s: RX CPU self-diagnostics failed!\n", 1065 sc->bge_dev.dv_xname); 1066 return(ENODEV); 1067 } 1068 1069 /* Clear the MAC control register */ 1070 CSR_WRITE_4(sc, BGE_MAC_MODE, 0); 1071 1072 /* 1073 * Clear the MAC statistics block in the NIC's 1074 * internal memory. 1075 */ 1076 for (i = BGE_STATS_BLOCK; 1077 i < BGE_STATS_BLOCK_END + 1; i += sizeof(u_int32_t)) 1078 BGE_MEMWIN_WRITE(pa->pa_pc, pa->pa_tag, i, 0); 1079 1080 for (i = BGE_STATUS_BLOCK; 1081 i < BGE_STATUS_BLOCK_END + 1; i += sizeof(u_int32_t)) 1082 BGE_MEMWIN_WRITE(pa->pa_pc, pa->pa_tag, i, 0); 1083 1084 /* Set up the PCI DMA control register. */ 1085 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_DMA_RW_CTL, 1086 BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD|0x0F); 1087 1088 /* 1089 * Set up general mode register. 1090 */ 1091 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS| 1092 BGE_MODECTL_MAC_ATTN_INTR|BGE_MODECTL_HOST_SEND_BDS| 1093 BGE_MODECTL_NO_RX_CRC|BGE_MODECTL_TX_NO_PHDR_CSUM| 1094 BGE_MODECTL_RX_NO_PHDR_CSUM); 1095 1096 /* Get cache line size. */ 1097 cachesize = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_CACHESZ); 1098 1099 /* 1100 * Avoid violating PCI spec on certain chip revs. 1101 */ 1102 if (pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_CMD) & 1103 PCIM_CMD_MWIEN) { 1104 switch(cachesize) { 1105 case 1: 1106 PCI_SETBIT(pa->pa_pc, pa->pa_tag, BGE_PCI_DMA_RW_CTL, 1107 BGE_PCI_WRITE_BNDRY_16BYTES); 1108 break; 1109 case 2: 1110 PCI_SETBIT(pa->pa_pc, pa->pa_tag, BGE_PCI_DMA_RW_CTL, 1111 BGE_PCI_WRITE_BNDRY_32BYTES); 1112 break; 1113 case 4: 1114 PCI_SETBIT(pa->pa_pc, pa->pa_tag, BGE_PCI_DMA_RW_CTL, 1115 BGE_PCI_WRITE_BNDRY_64BYTES); 1116 break; 1117 case 8: 1118 PCI_SETBIT(pa->pa_pc, pa->pa_tag, BGE_PCI_DMA_RW_CTL, 1119 BGE_PCI_WRITE_BNDRY_128BYTES); 1120 break; 1121 case 16: 1122 PCI_SETBIT(pa->pa_pc, pa->pa_tag, BGE_PCI_DMA_RW_CTL, 1123 BGE_PCI_WRITE_BNDRY_256BYTES); 1124 break; 1125 case 32: 1126 PCI_SETBIT(pa->pa_pc, pa->pa_tag, BGE_PCI_DMA_RW_CTL, 1127 BGE_PCI_WRITE_BNDRY_512BYTES); 1128 break; 1129 case 64: 1130 PCI_SETBIT(pa->pa_pc, pa->pa_tag, BGE_PCI_DMA_RW_CTL, 1131 BGE_PCI_WRITE_BNDRY_1024BYTES); 1132 break; 1133 default: 1134 /* Disable PCI memory write and invalidate. */ 1135 #if 0 1136 if (bootverbose) 1137 printf("%s: cache line size %d not " 1138 "supported; disabling PCI MWI\n", 1139 sc->bge_dev.dv_xname, cachesize); 1140 #endif 1141 PCI_CLRBIT(pa->pa_pc, pa->pa_tag, BGE_PCI_CMD, 1142 PCIM_CMD_MWIEN); 1143 break; 1144 } 1145 } 1146 1147 #ifdef __brokenalpha__ 1148 /* 1149 * Must insure that we do not cross an 8K (bytes) boundary 1150 * for DMA reads. Our highest limit is 1K bytes. This is a 1151 * restriction on some ALPHA platforms with early revision 1152 * 21174 PCI chipsets, such as the AlphaPC 164lx 1153 */ 1154 PCI_SETBIT(sc, BGE_PCI_DMA_RW_CTL, BGE_PCI_READ_BNDRY_1024, 4); 1155 #endif 1156 1157 /* Set the timer prescaler (always 66Mhz) */ 1158 CSR_WRITE_4(sc, BGE_MISC_CFG, 65 << 1/*BGE_32BITTIME_66MHZ*/); 1159 1160 return(0); 1161 } 1162 1163 int 1164 bge_blockinit(sc) 1165 struct bge_softc *sc; 1166 { 1167 struct bge_rcb *rcb; 1168 struct bge_rcb_opaque *rcbo; 1169 bus_size_t rcb_addr; 1170 int i; 1171 struct ifnet *ifp = &sc->ethercom.ec_if; 1172 bge_hostaddr taddr; 1173 1174 /* 1175 * Initialize the memory window pointer register so that 1176 * we can access the first 32K of internal NIC RAM. This will 1177 * allow us to set up the TX send ring RCBs and the RX return 1178 * ring RCBs, plus other things which live in NIC memory. 1179 */ 1180 1181 pci_conf_write(sc->bge_pa.pa_pc, sc->bge_pa.pa_tag, 1182 BGE_PCI_MEMWIN_BASEADDR, 0); 1183 1184 /* Configure mbuf memory pool */ 1185 if (sc->bge_extram) { 1186 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, BGE_EXT_SSRAM); 1187 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000); 1188 } else { 1189 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, BGE_BUFFPOOL_1); 1190 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000); 1191 } 1192 1193 /* Configure DMA resource pool */ 1194 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_BASEADDR, BGE_DMA_DESCRIPTORS); 1195 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LEN, 0x2000); 1196 1197 /* Configure mbuf pool watermarks */ 1198 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 24); 1199 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 24); 1200 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 48); 1201 1202 /* Configure DMA resource watermarks */ 1203 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5); 1204 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10); 1205 1206 /* Enable buffer manager */ 1207 CSR_WRITE_4(sc, BGE_BMAN_MODE, 1208 BGE_BMANMODE_ENABLE|BGE_BMANMODE_LOMBUF_ATTN); 1209 1210 /* Poll for buffer manager start indication */ 1211 for (i = 0; i < BGE_TIMEOUT; i++) { 1212 if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE) 1213 break; 1214 DELAY(10); 1215 } 1216 1217 if (i == BGE_TIMEOUT) { 1218 printf("%s: buffer manager failed to start\n", 1219 sc->bge_dev.dv_xname); 1220 return(ENXIO); 1221 } 1222 1223 /* Enable flow-through queues */ 1224 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 1225 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 1226 1227 /* Wait until queue initialization is complete */ 1228 for (i = 0; i < BGE_TIMEOUT; i++) { 1229 if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0) 1230 break; 1231 DELAY(10); 1232 } 1233 1234 if (i == BGE_TIMEOUT) { 1235 printf("%s: flow-through queue init failed\n", 1236 sc->bge_dev.dv_xname); 1237 return(ENXIO); 1238 } 1239 1240 /* Initialize the standard RX ring control block */ 1241 rcb = &sc->bge_rdata->bge_info.bge_std_rx_rcb; 1242 bge_set_hostaddr(&rcb->bge_hostaddr, 1243 BGE_RING_DMA_ADDR(sc, bge_rx_std_ring)); 1244 rcb->bge_max_len = BGE_MAX_FRAMELEN; 1245 if (sc->bge_extram) 1246 rcb->bge_nicaddr = BGE_EXT_STD_RX_RINGS; 1247 else 1248 rcb->bge_nicaddr = BGE_STD_RX_RINGS; 1249 rcb->bge_flags = 0; 1250 rcbo = (struct bge_rcb_opaque *)rcb; 1251 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcbo->bge_reg0); 1252 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcbo->bge_reg1); 1253 CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcbo->bge_reg2); 1254 CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcbo->bge_reg3); 1255 1256 /* 1257 * Initialize the jumbo RX ring control block 1258 * We set the 'ring disabled' bit in the flags 1259 * field until we're actually ready to start 1260 * using this ring (i.e. once we set the MTU 1261 * high enough to require it). 1262 */ 1263 rcb = &sc->bge_rdata->bge_info.bge_jumbo_rx_rcb; 1264 bge_set_hostaddr(&rcb->bge_hostaddr, 1265 BGE_RING_DMA_ADDR(sc, bge_rx_jumbo_ring)); 1266 rcb->bge_max_len = BGE_MAX_FRAMELEN; 1267 if (sc->bge_extram) 1268 rcb->bge_nicaddr = BGE_EXT_JUMBO_RX_RINGS; 1269 else 1270 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS; 1271 rcb->bge_flags = BGE_RCB_FLAG_RING_DISABLED; 1272 1273 rcbo = (struct bge_rcb_opaque *)rcb; 1274 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI, rcbo->bge_reg0); 1275 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO, rcbo->bge_reg1); 1276 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcbo->bge_reg2); 1277 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcbo->bge_reg3); 1278 1279 /* Set up dummy disabled mini ring RCB */ 1280 rcb = &sc->bge_rdata->bge_info.bge_mini_rx_rcb; 1281 rcb->bge_flags = BGE_RCB_FLAG_RING_DISABLED; 1282 rcbo = (struct bge_rcb_opaque *)rcb; 1283 CSR_WRITE_4(sc, BGE_RX_MINI_RCB_MAXLEN_FLAGS, rcbo->bge_reg2); 1284 1285 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 1286 offsetof(struct bge_ring_data, bge_info), sizeof (struct bge_gib), 1287 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1288 1289 /* 1290 * Set the BD ring replentish thresholds. The recommended 1291 * values are 1/8th the number of descriptors allocated to 1292 * each ring. 1293 */ 1294 CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, BGE_STD_RX_RING_CNT/8); 1295 CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH, BGE_JUMBO_RX_RING_CNT/8); 1296 1297 /* 1298 * Disable all unused send rings by setting the 'ring disabled' 1299 * bit in the flags field of all the TX send ring control blocks. 1300 * These are located in NIC memory. 1301 */ 1302 rcb_addr = BGE_MEMWIN_START + BGE_SEND_RING_RCB; 1303 for (i = 0; i < BGE_TX_RINGS_EXTSSRAM_MAX; i++) { 1304 RCB_WRITE_2(sc, rcb_addr, bge_flags, 1305 BGE_RCB_FLAG_RING_DISABLED); 1306 RCB_WRITE_2(sc, rcb_addr, bge_max_len, 0); 1307 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 0); 1308 rcb_addr += sizeof(struct bge_rcb); 1309 } 1310 1311 /* Configure TX RCB 0 (we use only the first ring) */ 1312 rcb_addr = BGE_MEMWIN_START + BGE_SEND_RING_RCB; 1313 bge_set_hostaddr(&taddr, BGE_RING_DMA_ADDR(sc, bge_tx_ring)); 1314 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi); 1315 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo); 1316 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 1317 BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT)); 1318 RCB_WRITE_2(sc, rcb_addr, bge_max_len, BGE_TX_RING_CNT); 1319 RCB_WRITE_2(sc, rcb_addr, bge_flags, 0); 1320 1321 /* Disable all unused RX return rings */ 1322 rcb_addr = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB; 1323 for (i = 0; i < BGE_RX_RINGS_MAX; i++) { 1324 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_hi, 0); 1325 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_lo, 0); 1326 RCB_WRITE_2(sc, rcb_addr, bge_flags, 1327 BGE_RCB_FLAG_RING_DISABLED); 1328 RCB_WRITE_2(sc, rcb_addr, bge_max_len, BGE_RETURN_RING_CNT); 1329 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 0); 1330 CSR_WRITE_4(sc, BGE_MBX_RX_CONS0_LO + 1331 (i * (sizeof(u_int64_t))), 0); 1332 rcb_addr += sizeof(struct bge_rcb); 1333 } 1334 1335 /* Initialize RX ring indexes */ 1336 CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, 0); 1337 CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0); 1338 CSR_WRITE_4(sc, BGE_MBX_RX_MINI_PROD_LO, 0); 1339 1340 /* 1341 * Set up RX return ring 0 1342 * Note that the NIC address for RX return rings is 0x00000000. 1343 * The return rings live entirely within the host, so the 1344 * nicaddr field in the RCB isn't used. 1345 */ 1346 rcb_addr = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB; 1347 bge_set_hostaddr(&taddr, BGE_RING_DMA_ADDR(sc, bge_rx_return_ring)); 1348 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi); 1349 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo); 1350 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 0x00000000); 1351 RCB_WRITE_2(sc, rcb_addr, bge_max_len, BGE_RETURN_RING_CNT); 1352 RCB_WRITE_2(sc, rcb_addr, bge_flags, 0); 1353 1354 /* Set random backoff seed for TX */ 1355 CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF, 1356 LLADDR(ifp->if_sadl)[0] + LLADDR(ifp->if_sadl)[1] + 1357 LLADDR(ifp->if_sadl)[2] + LLADDR(ifp->if_sadl)[3] + 1358 LLADDR(ifp->if_sadl)[4] + LLADDR(ifp->if_sadl)[5] + 1359 BGE_TX_BACKOFF_SEED_MASK); 1360 1361 /* Set inter-packet gap */ 1362 CSR_WRITE_4(sc, BGE_TX_LENGTHS, 0x2620); 1363 1364 /* 1365 * Specify which ring to use for packets that don't match 1366 * any RX rules. 1367 */ 1368 CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08); 1369 1370 /* 1371 * Configure number of RX lists. One interrupt distribution 1372 * list, sixteen active lists, one bad frames class. 1373 */ 1374 CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181); 1375 1376 /* Inialize RX list placement stats mask. */ 1377 CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF); 1378 CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1); 1379 1380 /* Disable host coalescing until we get it set up */ 1381 CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000); 1382 1383 /* Poll to make sure it's shut down. */ 1384 for (i = 0; i < BGE_TIMEOUT; i++) { 1385 if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE)) 1386 break; 1387 DELAY(10); 1388 } 1389 1390 if (i == BGE_TIMEOUT) { 1391 printf("%s: host coalescing engine failed to idle\n", 1392 sc->bge_dev.dv_xname); 1393 return(ENXIO); 1394 } 1395 1396 /* Set up host coalescing defaults */ 1397 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bge_rx_coal_ticks); 1398 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bge_tx_coal_ticks); 1399 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bge_rx_max_coal_bds); 1400 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bge_tx_max_coal_bds); 1401 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT, 0); 1402 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT, 0); 1403 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 0); 1404 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 0); 1405 CSR_WRITE_4(sc, BGE_HCC_STATS_TICKS, sc->bge_stat_ticks); 1406 1407 /* Set up address of statistics block */ 1408 bge_set_hostaddr(&taddr, BGE_RING_DMA_ADDR(sc, bge_info.bge_stats)); 1409 CSR_WRITE_4(sc, BGE_HCC_STATS_BASEADDR, BGE_STATS_BLOCK); 1410 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_HI, taddr.bge_addr_hi); 1411 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_LO, taddr.bge_addr_lo); 1412 1413 /* Set up address of status block */ 1414 bge_set_hostaddr(&taddr, BGE_RING_DMA_ADDR(sc, bge_status_block)); 1415 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_BASEADDR, BGE_STATUS_BLOCK); 1416 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI, taddr.bge_addr_hi); 1417 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO, taddr.bge_addr_lo); 1418 sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx = 0; 1419 sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx = 0; 1420 1421 /* Turn on host coalescing state machine */ 1422 CSR_WRITE_4(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE); 1423 1424 /* Turn on RX BD completion state machine and enable attentions */ 1425 CSR_WRITE_4(sc, BGE_RBDC_MODE, 1426 BGE_RBDCMODE_ENABLE|BGE_RBDCMODE_ATTN); 1427 1428 /* Turn on RX list placement state machine */ 1429 CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 1430 1431 /* Turn on RX list selector state machine. */ 1432 CSR_WRITE_4(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 1433 1434 /* Turn on DMA, clear stats */ 1435 CSR_WRITE_4(sc, BGE_MAC_MODE, BGE_MACMODE_TXDMA_ENB| 1436 BGE_MACMODE_RXDMA_ENB|BGE_MACMODE_RX_STATS_CLEAR| 1437 BGE_MACMODE_TX_STATS_CLEAR|BGE_MACMODE_RX_STATS_ENB| 1438 BGE_MACMODE_TX_STATS_ENB|BGE_MACMODE_FRMHDR_DMA_ENB| 1439 (sc->bge_tbi ? BGE_PORTMODE_TBI : BGE_PORTMODE_MII)); 1440 1441 /* Set misc. local control, enable interrupts on attentions */ 1442 CSR_WRITE_4(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_ONATTN); 1443 1444 #ifdef notdef 1445 /* Assert GPIO pins for PHY reset */ 1446 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUT0| 1447 BGE_MLC_MISCIO_OUT1|BGE_MLC_MISCIO_OUT2); 1448 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUTEN0| 1449 BGE_MLC_MISCIO_OUTEN1|BGE_MLC_MISCIO_OUTEN2); 1450 #endif 1451 1452 /* Turn on DMA completion state machine */ 1453 CSR_WRITE_4(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 1454 1455 /* Turn on write DMA state machine */ 1456 CSR_WRITE_4(sc, BGE_WDMA_MODE, 1457 BGE_WDMAMODE_ENABLE|BGE_WDMAMODE_ALL_ATTNS); 1458 1459 /* Turn on read DMA state machine */ 1460 CSR_WRITE_4(sc, BGE_RDMA_MODE, 1461 BGE_RDMAMODE_ENABLE|BGE_RDMAMODE_ALL_ATTNS); 1462 1463 /* Turn on RX data completion state machine */ 1464 CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 1465 1466 /* Turn on RX BD initiator state machine */ 1467 CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 1468 1469 /* Turn on RX data and RX BD initiator state machine */ 1470 CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE); 1471 1472 /* Turn on Mbuf cluster free state machine */ 1473 CSR_WRITE_4(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 1474 1475 /* Turn on send BD completion state machine */ 1476 CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 1477 1478 /* Turn on send data completion state machine */ 1479 CSR_WRITE_4(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE); 1480 1481 /* Turn on send data initiator state machine */ 1482 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 1483 1484 /* Turn on send BD initiator state machine */ 1485 CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 1486 1487 /* Turn on send BD selector state machine */ 1488 CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 1489 1490 CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF); 1491 CSR_WRITE_4(sc, BGE_SDI_STATS_CTL, 1492 BGE_SDISTATSCTL_ENABLE|BGE_SDISTATSCTL_FASTER); 1493 1494 /* init LED register */ 1495 CSR_WRITE_4(sc, BGE_MAC_LED_CTL, 0x00000000); 1496 1497 /* ack/clear link change events */ 1498 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED| 1499 BGE_MACSTAT_CFG_CHANGED); 1500 CSR_WRITE_4(sc, BGE_MI_STS, 0); 1501 1502 /* Enable PHY auto polling (for MII/GMII only) */ 1503 if (sc->bge_tbi) { 1504 CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK); 1505 } else { 1506 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL|10<<16); 1507 if (BGE_IS_5700_Ax_Bx(sc->bge_asicrev)) 1508 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, 1509 BGE_EVTENB_MI_INTERRUPT); 1510 } 1511 1512 /* Enable link state change attentions. */ 1513 BGE_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED); 1514 1515 return(0); 1516 } 1517 1518 static const struct bge_product { 1519 pci_vendor_id_t bp_vendor; 1520 pci_product_id_t bp_product; 1521 const char *bp_name; 1522 } bge_products[] = { 1523 /* 1524 * The BCM5700 documentation seems to indicate that the hardware 1525 * still has the Alteon vendor ID burned into it, though it 1526 * should always be overridden by the value in the EEPROM. We'll 1527 * check for it anyway. 1528 */ 1529 { PCI_VENDOR_ALTEON, 1530 PCI_PRODUCT_ALTEON_BCM5700, 1531 "Broadcom BCM5700 Gigabit Ethernet" }, 1532 { PCI_VENDOR_ALTEON, 1533 PCI_PRODUCT_ALTEON_BCM5701, 1534 "Broadcom BCM5701 Gigabit Ethernet" }, 1535 1536 { PCI_VENDOR_ALTIMA, 1537 PCI_PRODUCT_ALTIMA_AC1000, 1538 "Altima AC1000 Gigabit Ethernet" }, 1539 { PCI_VENDOR_ALTIMA, 1540 PCI_PRODUCT_ALTIMA_AC1001, 1541 "Altima AC1001 Gigabit Ethernet" }, 1542 { PCI_VENDOR_ALTIMA, 1543 PCI_PRODUCT_ALTIMA_AC9100, 1544 "Altima AC9100 Gigabit Ethernet" }, 1545 1546 { PCI_VENDOR_BROADCOM, 1547 PCI_PRODUCT_BROADCOM_BCM5700, 1548 "Broadcom BCM5700 Gigabit Ethernet" }, 1549 { PCI_VENDOR_BROADCOM, 1550 PCI_PRODUCT_BROADCOM_BCM5701, 1551 "Broadcom BCM5700 Gigabit Ethernet" }, 1552 1553 { PCI_VENDOR_SCHNEIDERKOCH, 1554 PCI_PRODUCT_SCHNEIDERKOCH_SK_9DX1, 1555 "SysKonnect SK-9Dx1 Gigabit Ethernet" }, 1556 1557 { PCI_VENDOR_3COM, 1558 PCI_PRODUCT_3COM_3C996, 1559 "3Com 3c996 Gigabit Ethernet" }, 1560 1561 { 0, 1562 0, 1563 NULL }, 1564 }; 1565 1566 static const struct bge_product * 1567 bge_lookup(const struct pci_attach_args *pa) 1568 { 1569 const struct bge_product *bp; 1570 1571 for (bp = bge_products; bp->bp_name != NULL; bp++) { 1572 if (PCI_VENDOR(pa->pa_id) == bp->bp_vendor && 1573 PCI_PRODUCT(pa->pa_id) == bp->bp_product) 1574 return (bp); 1575 } 1576 1577 return (NULL); 1578 } 1579 1580 /* 1581 * Probe for a Broadcom chip. Check the PCI vendor and device IDs 1582 * against our list and return its name if we find a match. Note 1583 * that since the Broadcom controller contains VPD support, we 1584 * can get the device name string from the controller itself instead 1585 * of the compiled-in string. This is a little slow, but it guarantees 1586 * we'll always announce the right product name. 1587 */ 1588 int 1589 bge_probe(parent, match, aux) 1590 struct device *parent; 1591 struct cfdata *match; 1592 void *aux; 1593 { 1594 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 1595 1596 if (bge_lookup(pa) != NULL) 1597 return (1); 1598 1599 return (0); 1600 } 1601 1602 void 1603 bge_attach(parent, self, aux) 1604 struct device *parent, *self; 1605 void *aux; 1606 { 1607 struct bge_softc *sc = (struct bge_softc *)self; 1608 struct pci_attach_args *pa = aux; 1609 const struct bge_product *bp; 1610 pci_chipset_tag_t pc = pa->pa_pc; 1611 pci_intr_handle_t ih; 1612 const char *intrstr = NULL; 1613 bus_dma_segment_t seg; 1614 int rseg; 1615 u_int32_t hwcfg = 0; 1616 u_int32_t command; 1617 struct ifnet *ifp; 1618 int unit; 1619 caddr_t kva; 1620 u_char eaddr[ETHER_ADDR_LEN]; 1621 pcireg_t memtype; 1622 bus_addr_t memaddr; 1623 bus_size_t memsize; 1624 1625 bp = bge_lookup(pa); 1626 KASSERT(bp != NULL); 1627 1628 sc->bge_pa = *pa; 1629 1630 printf(": %s, rev. 0x%02x\n", bp->bp_name, PCI_REVISION(pa->pa_class)); 1631 1632 /* 1633 * Map control/status registers. 1634 */ 1635 DPRINTFN(5, ("Map control/status regs\n")); 1636 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 1637 command |= PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_MASTER_ENABLE; 1638 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, command); 1639 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 1640 1641 if (!(command & PCI_COMMAND_MEM_ENABLE)) { 1642 printf("%s: failed to enable memory mapping!\n", 1643 sc->bge_dev.dv_xname); 1644 return; 1645 } 1646 1647 DPRINTFN(5, ("pci_mem_find\n")); 1648 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, BGE_PCI_BAR0); 1649 switch (memtype) { 1650 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 1651 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 1652 if (pci_mapreg_map(pa, BGE_PCI_BAR0, 1653 memtype, 0, &sc->bge_btag, &sc->bge_bhandle, 1654 &memaddr, &memsize) == 0) 1655 break; 1656 default: 1657 printf("%s: can't find mem space\n", 1658 sc->bge_dev.dv_xname); 1659 return; 1660 } 1661 1662 DPRINTFN(5, ("pci_intr_map\n")); 1663 if (pci_intr_map(pa, &ih)) { 1664 printf("%s: couldn't map interrupt\n", 1665 sc->bge_dev.dv_xname); 1666 return; 1667 } 1668 1669 DPRINTFN(5, ("pci_intr_string\n")); 1670 intrstr = pci_intr_string(pc, ih); 1671 1672 DPRINTFN(5, ("pci_intr_establish\n")); 1673 sc->bge_intrhand = pci_intr_establish(pc, ih, IPL_NET, bge_intr, sc); 1674 1675 if (sc->bge_intrhand == NULL) { 1676 printf("%s: couldn't establish interrupt", 1677 sc->bge_dev.dv_xname); 1678 if (intrstr != NULL) 1679 printf(" at %s", intrstr); 1680 printf("\n"); 1681 return; 1682 } 1683 printf("%s: interrupting at %s\n", sc->bge_dev.dv_xname, intrstr); 1684 1685 /* Try to reset the chip. */ 1686 DPRINTFN(5, ("bge_reset\n")); 1687 bge_reset(sc); 1688 1689 if (bge_chipinit(sc)) { 1690 printf("%s: chip initializatino failed\n", 1691 sc->bge_dev.dv_xname); 1692 bge_release_resources(sc); 1693 return; 1694 } 1695 1696 /* 1697 * Get station address from the EEPROM. 1698 */ 1699 if (bge_read_eeprom(sc, (caddr_t)eaddr, 1700 BGE_EE_MAC_OFFSET + 2, ETHER_ADDR_LEN)) { 1701 printf("bge%d: failed to read station address\n", unit); 1702 bge_release_resources(sc); 1703 return; 1704 } 1705 1706 /* 1707 * A Broadcom chip was detected. Inform the world. 1708 */ 1709 printf("%s: Ethernet address %s\n", sc->bge_dev.dv_xname, 1710 ether_sprintf(eaddr)); 1711 1712 /* Allocate the general information block and ring buffers. */ 1713 sc->bge_dmatag = pa->pa_dmat; 1714 DPRINTFN(5, ("bus_dmamem_alloc\n")); 1715 if (bus_dmamem_alloc(sc->bge_dmatag, sizeof(struct bge_ring_data), 1716 PAGE_SIZE, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 1717 printf("%s: can't alloc rx buffers\n", sc->bge_dev.dv_xname); 1718 return; 1719 } 1720 DPRINTFN(5, ("bus_dmamem_map\n")); 1721 if (bus_dmamem_map(sc->bge_dmatag, &seg, rseg, 1722 sizeof(struct bge_ring_data), &kva, 1723 BUS_DMA_NOWAIT)) { 1724 printf("%s: can't map dma buffers (%d bytes)\n", 1725 sc->bge_dev.dv_xname, (int)sizeof(struct bge_ring_data)); 1726 bus_dmamem_free(sc->bge_dmatag, &seg, rseg); 1727 return; 1728 } 1729 DPRINTFN(5, ("bus_dmamem_create\n")); 1730 if (bus_dmamap_create(sc->bge_dmatag, sizeof(struct bge_ring_data), 1, 1731 sizeof(struct bge_ring_data), 0, 1732 BUS_DMA_NOWAIT, &sc->bge_ring_map)) { 1733 printf("%s: can't create dma map\n", sc->bge_dev.dv_xname); 1734 bus_dmamem_unmap(sc->bge_dmatag, kva, 1735 sizeof(struct bge_ring_data)); 1736 bus_dmamem_free(sc->bge_dmatag, &seg, rseg); 1737 return; 1738 } 1739 DPRINTFN(5, ("bus_dmamem_load\n")); 1740 if (bus_dmamap_load(sc->bge_dmatag, sc->bge_ring_map, kva, 1741 sizeof(struct bge_ring_data), NULL, 1742 BUS_DMA_NOWAIT)) { 1743 bus_dmamap_destroy(sc->bge_dmatag, sc->bge_ring_map); 1744 bus_dmamem_unmap(sc->bge_dmatag, kva, 1745 sizeof(struct bge_ring_data)); 1746 bus_dmamem_free(sc->bge_dmatag, &seg, rseg); 1747 return; 1748 } 1749 1750 DPRINTFN(5, ("bzero\n")); 1751 sc->bge_rdata = (struct bge_ring_data *)kva; 1752 1753 memset(sc->bge_rdata, sizeof(struct bge_ring_data), 0); 1754 1755 /* Try to allocate memory for jumbo buffers. */ 1756 if (bge_alloc_jumbo_mem(sc)) { 1757 printf("%s: jumbo buffer allocation failed\n", 1758 sc->bge_dev.dv_xname); 1759 } else 1760 sc->ethercom.ec_capabilities |= ETHERCAP_JUMBO_MTU; 1761 1762 /* Set default tuneable values. */ 1763 sc->bge_stat_ticks = BGE_TICKS_PER_SEC; 1764 sc->bge_rx_coal_ticks = 150; 1765 sc->bge_tx_coal_ticks = 150; 1766 sc->bge_rx_max_coal_bds = 64; 1767 sc->bge_tx_max_coal_bds = 128; 1768 1769 /* Set up ifnet structure */ 1770 ifp = &sc->ethercom.ec_if; 1771 ifp->if_softc = sc; 1772 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1773 ifp->if_ioctl = bge_ioctl; 1774 ifp->if_start = bge_start; 1775 ifp->if_init = bge_init; 1776 ifp->if_watchdog = bge_watchdog; 1777 IFQ_SET_MAXLEN(&ifp->if_snd, BGE_TX_RING_CNT - 1); 1778 IFQ_SET_READY(&ifp->if_snd); 1779 DPRINTFN(5, ("bcopy\n")); 1780 strcpy(ifp->if_xname, sc->bge_dev.dv_xname); 1781 1782 sc->ethercom.ec_if.if_capabilities |= 1783 IFCAP_CSUM_IPv4 | IFCAP_CSUM_TCPv4 | IFCAP_CSUM_UDPv4; 1784 sc->ethercom.ec_capabilities |= 1785 ETHERCAP_VLAN_HWTAGGING | ETHERCAP_VLAN_MTU; 1786 1787 /* 1788 * Do MII setup. 1789 */ 1790 DPRINTFN(5, ("mii setup\n")); 1791 sc->bge_mii.mii_ifp = ifp; 1792 sc->bge_mii.mii_readreg = bge_miibus_readreg; 1793 sc->bge_mii.mii_writereg = bge_miibus_writereg; 1794 sc->bge_mii.mii_statchg = bge_miibus_statchg; 1795 1796 /* Save ASIC rev. */ 1797 1798 sc->bge_asicrev = 1799 pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_MISC_CTL) & 1800 BGE_PCIMISCCTL_ASICREV; 1801 1802 /* 1803 * Figure out what sort of media we have by checking the 1804 * hardware config word in the EEPROM. Note: on some BCM5700 1805 * cards, this value appears to be unset. If that's the 1806 * case, we have to rely on identifying the NIC by its PCI 1807 * subsystem ID, as we do below for the SysKonnect SK-9D41. 1808 */ 1809 bge_read_eeprom(sc, (caddr_t)&hwcfg, 1810 BGE_EE_HWCFG_OFFSET, sizeof(hwcfg)); 1811 if ((be32toh(hwcfg) & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER) 1812 sc->bge_tbi = 1; 1813 1814 /* The SysKonnect SK-9D41 is a 1000baseSX card. */ 1815 if ((pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_SUBSYS) >> 16) == 1816 SK_SUBSYSID_9D41) 1817 sc->bge_tbi = 1; 1818 1819 if (sc->bge_tbi) { 1820 ifmedia_init(&sc->bge_ifmedia, IFM_IMASK, bge_ifmedia_upd, 1821 bge_ifmedia_sts); 1822 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL); 1823 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_1000_SX|IFM_FDX, 1824 0, NULL); 1825 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL); 1826 ifmedia_set(&sc->bge_ifmedia, IFM_ETHER|IFM_AUTO); 1827 } else { 1828 /* 1829 * Do transceiver setup. 1830 */ 1831 ifmedia_init(&sc->bge_mii.mii_media, 0, bge_ifmedia_upd, 1832 bge_ifmedia_sts); 1833 mii_attach(&sc->bge_dev, &sc->bge_mii, 0xffffffff, 1834 MII_PHY_ANY, MII_OFFSET_ANY, 0); 1835 1836 if (LIST_FIRST(&sc->bge_mii.mii_phys) == NULL) { 1837 printf("%s: no PHY found!\n", sc->bge_dev.dv_xname); 1838 ifmedia_add(&sc->bge_mii.mii_media, 1839 IFM_ETHER|IFM_MANUAL, 0, NULL); 1840 ifmedia_set(&sc->bge_mii.mii_media, 1841 IFM_ETHER|IFM_MANUAL); 1842 } else 1843 ifmedia_set(&sc->bge_mii.mii_media, 1844 IFM_ETHER|IFM_AUTO); 1845 } 1846 1847 /* 1848 * Call MI attach routine. 1849 */ 1850 DPRINTFN(5, ("if_attach\n")); 1851 if_attach(ifp); 1852 DPRINTFN(5, ("ether_ifattach\n")); 1853 ether_ifattach(ifp, eaddr); 1854 DPRINTFN(5, ("callout_init\n")); 1855 callout_init(&sc->bge_timeout); 1856 } 1857 1858 void 1859 bge_release_resources(sc) 1860 struct bge_softc *sc; 1861 { 1862 if (sc->bge_vpd_prodname != NULL) 1863 free(sc->bge_vpd_prodname, M_DEVBUF); 1864 1865 if (sc->bge_vpd_readonly != NULL) 1866 free(sc->bge_vpd_readonly, M_DEVBUF); 1867 } 1868 1869 void 1870 bge_reset(sc) 1871 struct bge_softc *sc; 1872 { 1873 struct pci_attach_args *pa = &sc->bge_pa; 1874 u_int32_t cachesize, command, pcistate; 1875 int i, val = 0; 1876 1877 /* Save some important PCI state. */ 1878 cachesize = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_CACHESZ); 1879 command = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_CMD); 1880 pcistate = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_PCISTATE); 1881 1882 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_MISC_CTL, 1883 BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR| 1884 BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_PCISTATE_RW); 1885 1886 /* Issue global reset */ 1887 bge_writereg_ind(sc, BGE_MISC_CFG, 1888 BGE_MISCCFG_RESET_CORE_CLOCKS|(65<<1)); 1889 1890 DELAY(1000); 1891 1892 /* Reset some of the PCI state that got zapped by reset */ 1893 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_MISC_CTL, 1894 BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR| 1895 BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_PCISTATE_RW); 1896 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_CMD, command); 1897 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_CACHESZ, cachesize); 1898 bge_writereg_ind(sc, BGE_MISC_CFG, (65 << 1)); 1899 1900 /* Enable memory arbiter. */ 1901 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 1902 1903 /* 1904 * Prevent PXE restart: write a magic number to the 1905 * general communications memory at 0xB50. 1906 */ 1907 bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM, BGE_MAGIC_NUMBER); 1908 1909 /* 1910 * Poll the value location we just wrote until 1911 * we see the 1's complement of the magic number. 1912 * This indicates that the firmware initialization 1913 * is complete. 1914 */ 1915 for (i = 0; i < 750; i++) { 1916 val = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM); 1917 if (val == ~BGE_MAGIC_NUMBER) 1918 break; 1919 DELAY(1000); 1920 } 1921 1922 if (i == 750) { 1923 printf("%s: firmware handshake timed out, val = %x\n", 1924 sc->bge_dev.dv_xname, val); 1925 return; 1926 } 1927 1928 /* 1929 * XXX Wait for the value of the PCISTATE register to 1930 * return to its original pre-reset state. This is a 1931 * fairly good indicator of reset completion. If we don't 1932 * wait for the reset to fully complete, trying to read 1933 * from the device's non-PCI registers may yield garbage 1934 * results. 1935 */ 1936 for (i = 0; i < BGE_TIMEOUT; i++) { 1937 if (pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_PCISTATE) == 1938 pcistate) 1939 break; 1940 DELAY(10); 1941 } 1942 1943 /* Enable memory arbiter. */ 1944 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 1945 1946 /* Fix up byte swapping */ 1947 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS); 1948 1949 CSR_WRITE_4(sc, BGE_MAC_MODE, 0); 1950 1951 DELAY(10000); 1952 } 1953 1954 /* 1955 * Frame reception handling. This is called if there's a frame 1956 * on the receive return list. 1957 * 1958 * Note: we have to be able to handle two possibilities here: 1959 * 1) the frame is from the jumbo recieve ring 1960 * 2) the frame is from the standard receive ring 1961 */ 1962 1963 void 1964 bge_rxeof(sc) 1965 struct bge_softc *sc; 1966 { 1967 struct ifnet *ifp; 1968 int stdcnt = 0, jumbocnt = 0; 1969 int have_tag = 0; 1970 u_int16_t vlan_tag = 0; 1971 bus_dmamap_t dmamap; 1972 bus_addr_t offset, toff; 1973 bus_size_t tlen; 1974 int tosync; 1975 1976 ifp = &sc->ethercom.ec_if; 1977 1978 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 1979 offsetof(struct bge_ring_data, bge_status_block), 1980 sizeof (struct bge_status_block), 1981 BUS_DMASYNC_POSTREAD); 1982 1983 offset = offsetof(struct bge_ring_data, bge_rx_return_ring); 1984 tosync = sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx - 1985 sc->bge_rx_saved_considx; 1986 1987 toff = offset + (sc->bge_rx_saved_considx * sizeof (struct bge_rx_bd)); 1988 1989 if (tosync < 0) { 1990 tlen = (BGE_RETURN_RING_CNT - sc->bge_rx_saved_considx) * 1991 sizeof (struct bge_rx_bd); 1992 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 1993 toff, tlen, BUS_DMASYNC_POSTREAD); 1994 tosync = -tosync; 1995 } 1996 1997 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 1998 offset, tosync * sizeof (struct bge_rx_bd), 1999 BUS_DMASYNC_POSTREAD); 2000 2001 while(sc->bge_rx_saved_considx != 2002 sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx) { 2003 struct bge_rx_bd *cur_rx; 2004 u_int32_t rxidx; 2005 struct mbuf *m = NULL; 2006 2007 cur_rx = &sc->bge_rdata-> 2008 bge_rx_return_ring[sc->bge_rx_saved_considx]; 2009 2010 rxidx = cur_rx->bge_idx; 2011 BGE_INC(sc->bge_rx_saved_considx, BGE_RETURN_RING_CNT); 2012 2013 if (cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) { 2014 have_tag = 1; 2015 vlan_tag = cur_rx->bge_vlan_tag; 2016 } 2017 2018 if (cur_rx->bge_flags & BGE_RXBDFLAG_JUMBO_RING) { 2019 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT); 2020 m = sc->bge_cdata.bge_rx_jumbo_chain[rxidx]; 2021 sc->bge_cdata.bge_rx_jumbo_chain[rxidx] = NULL; 2022 jumbocnt++; 2023 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 2024 ifp->if_ierrors++; 2025 bge_newbuf_jumbo(sc, sc->bge_jumbo, m); 2026 continue; 2027 } 2028 if (bge_newbuf_jumbo(sc, sc->bge_jumbo, 2029 NULL)== ENOBUFS) { 2030 ifp->if_ierrors++; 2031 bge_newbuf_jumbo(sc, sc->bge_jumbo, m); 2032 continue; 2033 } 2034 } else { 2035 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT); 2036 m = sc->bge_cdata.bge_rx_std_chain[rxidx]; 2037 sc->bge_cdata.bge_rx_std_chain[rxidx] = NULL; 2038 stdcnt++; 2039 dmamap = sc->bge_cdata.bge_rx_std_map[rxidx]; 2040 sc->bge_cdata.bge_rx_std_map[rxidx] = 0; 2041 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 2042 ifp->if_ierrors++; 2043 bge_newbuf_std(sc, sc->bge_std, m, dmamap); 2044 continue; 2045 } 2046 if (bge_newbuf_std(sc, sc->bge_std, 2047 NULL, dmamap) == ENOBUFS) { 2048 ifp->if_ierrors++; 2049 bge_newbuf_std(sc, sc->bge_std, m, dmamap); 2050 continue; 2051 } 2052 } 2053 2054 ifp->if_ipackets++; 2055 m->m_pkthdr.len = m->m_len = cur_rx->bge_len; 2056 m->m_pkthdr.rcvif = ifp; 2057 2058 #if NBPFILTER > 0 2059 /* 2060 * Handle BPF listeners. Let the BPF user see the packet. 2061 */ 2062 if (ifp->if_bpf) 2063 bpf_mtap(ifp->if_bpf, m); 2064 #endif 2065 2066 if (sc->bge_asicrev != BGE_ASICREV_BCM5700_B0) { 2067 m->m_pkthdr.csum_flags |= M_CSUM_IPv4; 2068 if ((cur_rx->bge_ip_csum ^ 0xffff) != 0) 2069 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 2070 #if 0 /* XXX appears to be broken */ 2071 if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM) { 2072 m->m_pkthdr.csum_data = 2073 cur_rx->bge_tcp_udp_csum; 2074 m->m_pkthdr.csum_flags |= 2075 (M_CSUM_TCPv4|M_CSUM_UDPv4|M_CSUM_DATA); 2076 } 2077 #endif 2078 } 2079 2080 /* 2081 * If we received a packet with a vlan tag, pass it 2082 * to vlan_input() instead of ether_input(). 2083 */ 2084 if (have_tag) { 2085 struct mbuf *n; 2086 2087 n = m_aux_add(m, AF_LINK, ETHERTYPE_VLAN); 2088 if (n != NULL) { 2089 *mtod(n, int *) = vlan_tag; 2090 n->m_len = sizeof(int); 2091 have_tag = vlan_tag = 0; 2092 } else { 2093 printf("%s: no mbuf for tag\n", ifp->if_xname); 2094 m_freem(m); 2095 have_tag = vlan_tag = 0; 2096 continue; 2097 } 2098 } 2099 (*ifp->if_input)(ifp, m); 2100 } 2101 2102 CSR_WRITE_4(sc, BGE_MBX_RX_CONS0_LO, sc->bge_rx_saved_considx); 2103 if (stdcnt) 2104 CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std); 2105 if (jumbocnt) 2106 CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo); 2107 } 2108 2109 void 2110 bge_txeof(sc) 2111 struct bge_softc *sc; 2112 { 2113 struct bge_tx_bd *cur_tx = NULL; 2114 struct ifnet *ifp; 2115 struct txdmamap_pool_entry *dma; 2116 bus_addr_t offset, toff; 2117 bus_size_t tlen; 2118 int tosync; 2119 struct mbuf *m; 2120 2121 ifp = &sc->ethercom.ec_if; 2122 2123 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 2124 offsetof(struct bge_ring_data, bge_status_block), 2125 sizeof (struct bge_status_block), 2126 BUS_DMASYNC_POSTREAD); 2127 2128 offset = offsetof(struct bge_ring_data, bge_tx_ring); 2129 tosync = sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx - 2130 sc->bge_tx_saved_considx; 2131 2132 toff = offset + (sc->bge_tx_saved_considx * sizeof (struct bge_tx_bd)); 2133 2134 if (tosync < 0) { 2135 tlen = (BGE_TX_RING_CNT - sc->bge_tx_saved_considx) * 2136 sizeof (struct bge_tx_bd); 2137 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 2138 toff, tlen, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2139 tosync = -tosync; 2140 } 2141 2142 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 2143 offset, tosync * sizeof (struct bge_tx_bd), 2144 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2145 2146 /* 2147 * Go through our tx ring and free mbufs for those 2148 * frames that have been sent. 2149 */ 2150 while (sc->bge_tx_saved_considx != 2151 sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx) { 2152 u_int32_t idx = 0; 2153 2154 idx = sc->bge_tx_saved_considx; 2155 cur_tx = &sc->bge_rdata->bge_tx_ring[idx]; 2156 if (cur_tx->bge_flags & BGE_TXBDFLAG_END) 2157 ifp->if_opackets++; 2158 m = sc->bge_cdata.bge_tx_chain[idx]; 2159 if (m != NULL) { 2160 sc->bge_cdata.bge_tx_chain[idx] = NULL; 2161 dma = sc->txdma[idx]; 2162 bus_dmamap_sync(sc->bge_dmatag, dma->dmamap, 0, 2163 dma->dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 2164 bus_dmamap_unload(sc->bge_dmatag, dma->dmamap); 2165 SLIST_INSERT_HEAD(&sc->txdma_list, dma, link); 2166 sc->txdma[idx] = NULL; 2167 2168 m_freem(m); 2169 } 2170 sc->bge_txcnt--; 2171 BGE_INC(sc->bge_tx_saved_considx, BGE_TX_RING_CNT); 2172 ifp->if_timer = 0; 2173 } 2174 2175 if (cur_tx != NULL) 2176 ifp->if_flags &= ~IFF_OACTIVE; 2177 } 2178 2179 int 2180 bge_intr(xsc) 2181 void *xsc; 2182 { 2183 struct bge_softc *sc; 2184 struct ifnet *ifp; 2185 2186 sc = xsc; 2187 ifp = &sc->ethercom.ec_if; 2188 2189 #ifdef notdef 2190 /* Avoid this for now -- checking this register is expensive. */ 2191 /* Make sure this is really our interrupt. */ 2192 if (!(CSR_READ_4(sc, BGE_MISC_LOCAL_CTL) & BGE_MLC_INTR_STATE)) 2193 return (0); 2194 #endif 2195 /* Ack interrupt and stop others from occuring. */ 2196 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 1); 2197 2198 /* 2199 * Process link state changes. 2200 * Grrr. The link status word in the status block does 2201 * not work correctly on the BCM5700 rev AX and BX chips, 2202 * according to all avaibable information. Hence, we have 2203 * to enable MII interrupts in order to properly obtain 2204 * async link changes. Unfortunately, this also means that 2205 * we have to read the MAC status register to detect link 2206 * changes, thereby adding an additional register access to 2207 * the interrupt handler. 2208 */ 2209 2210 if (BGE_IS_5700_Ax_Bx(sc->bge_asicrev)) { 2211 u_int32_t status; 2212 2213 status = CSR_READ_4(sc, BGE_MAC_STS); 2214 if (status & BGE_MACSTAT_MI_INTERRUPT) { 2215 sc->bge_link = 0; 2216 callout_stop(&sc->bge_timeout); 2217 bge_tick(sc); 2218 /* Clear the interrupt */ 2219 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, 2220 BGE_EVTENB_MI_INTERRUPT); 2221 bge_miibus_readreg(&sc->bge_dev, 1, BRGPHY_MII_ISR); 2222 bge_miibus_writereg(&sc->bge_dev, 1, BRGPHY_MII_IMR, 2223 BRGPHY_INTRS); 2224 } 2225 } else { 2226 if (sc->bge_rdata->bge_status_block.bge_status & 2227 BGE_STATFLAG_LINKSTATE_CHANGED) { 2228 sc->bge_link = 0; 2229 callout_stop(&sc->bge_timeout); 2230 bge_tick(sc); 2231 /* Clear the interrupt */ 2232 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED| 2233 BGE_MACSTAT_CFG_CHANGED); 2234 } 2235 } 2236 2237 if (ifp->if_flags & IFF_RUNNING) { 2238 /* Check RX return ring producer/consumer */ 2239 bge_rxeof(sc); 2240 2241 /* Check TX ring producer/consumer */ 2242 bge_txeof(sc); 2243 } 2244 2245 bge_handle_events(sc); 2246 2247 /* Re-enable interrupts. */ 2248 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 0); 2249 2250 if (ifp->if_flags & IFF_RUNNING && !IFQ_IS_EMPTY(&ifp->if_snd)) 2251 bge_start(ifp); 2252 2253 return (1); 2254 } 2255 2256 void 2257 bge_tick(xsc) 2258 void *xsc; 2259 { 2260 struct bge_softc *sc = xsc; 2261 struct mii_data *mii = &sc->bge_mii; 2262 struct ifmedia *ifm = NULL; 2263 struct ifnet *ifp = &sc->ethercom.ec_if; 2264 int s; 2265 2266 s = splnet(); 2267 2268 bge_stats_update(sc); 2269 callout_reset(&sc->bge_timeout, hz, bge_tick, sc); 2270 if (sc->bge_link) { 2271 splx(s); 2272 return; 2273 } 2274 2275 if (sc->bge_tbi) { 2276 ifm = &sc->bge_ifmedia; 2277 if (CSR_READ_4(sc, BGE_MAC_STS) & 2278 BGE_MACSTAT_TBI_PCS_SYNCHED) { 2279 sc->bge_link++; 2280 CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF); 2281 printf("%s: gigabit link up\n", sc->bge_dev.dv_xname); 2282 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 2283 bge_start(ifp); 2284 } 2285 splx(s); 2286 return; 2287 } 2288 2289 mii_tick(mii); 2290 2291 if (!sc->bge_link && mii->mii_media_status & IFM_ACTIVE && 2292 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 2293 sc->bge_link++; 2294 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T || 2295 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX) 2296 printf("%s: gigabit link up\n", sc->bge_dev.dv_xname); 2297 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 2298 bge_start(ifp); 2299 } 2300 2301 splx(s); 2302 } 2303 2304 void 2305 bge_stats_update(sc) 2306 struct bge_softc *sc; 2307 { 2308 struct ifnet *ifp = &sc->ethercom.ec_if; 2309 bus_size_t stats = BGE_MEMWIN_START + BGE_STATS_BLOCK; 2310 2311 #define READ_STAT(sc, stats, stat) \ 2312 CSR_READ_4(sc, stats + offsetof(struct bge_stats, stat)) 2313 2314 ifp->if_collisions += 2315 (READ_STAT(sc, stats, dot3StatsSingleCollisionFrames.bge_addr_lo) + 2316 READ_STAT(sc, stats, dot3StatsMultipleCollisionFrames.bge_addr_lo) + 2317 READ_STAT(sc, stats, dot3StatsExcessiveCollisions.bge_addr_lo) + 2318 READ_STAT(sc, stats, dot3StatsLateCollisions.bge_addr_lo)) - 2319 ifp->if_collisions; 2320 2321 #undef READ_STAT 2322 2323 #ifdef notdef 2324 ifp->if_collisions += 2325 (sc->bge_rdata->bge_info.bge_stats.dot3StatsSingleCollisionFrames + 2326 sc->bge_rdata->bge_info.bge_stats.dot3StatsMultipleCollisionFrames + 2327 sc->bge_rdata->bge_info.bge_stats.dot3StatsExcessiveCollisions + 2328 sc->bge_rdata->bge_info.bge_stats.dot3StatsLateCollisions) - 2329 ifp->if_collisions; 2330 #endif 2331 } 2332 2333 /* 2334 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data 2335 * pointers to descriptors. 2336 */ 2337 int 2338 bge_encap(sc, m_head, txidx) 2339 struct bge_softc *sc; 2340 struct mbuf *m_head; 2341 u_int32_t *txidx; 2342 { 2343 struct bge_tx_bd *f = NULL; 2344 u_int32_t frag, cur, cnt = 0; 2345 u_int16_t csum_flags = 0; 2346 struct txdmamap_pool_entry *dma; 2347 bus_dmamap_t dmamap; 2348 int i = 0; 2349 struct mbuf *n; 2350 2351 cur = frag = *txidx; 2352 2353 if (m_head->m_pkthdr.csum_flags) { 2354 if (m_head->m_pkthdr.csum_flags & M_CSUM_IPv4) 2355 csum_flags |= BGE_TXBDFLAG_IP_CSUM; 2356 if (m_head->m_pkthdr.csum_flags & (M_CSUM_TCPv4|M_CSUM_UDPv4)) 2357 csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM; 2358 } 2359 2360 dma = SLIST_FIRST(&sc->txdma_list); 2361 if (dma == NULL) 2362 return ENOBUFS; 2363 dmamap = dma->dmamap; 2364 2365 /* 2366 * Start packing the mbufs in this chain into 2367 * the fragment pointers. Stop when we run out 2368 * of fragments or hit the end of the mbuf chain. 2369 */ 2370 if (bus_dmamap_load_mbuf(sc->bge_dmatag, dmamap, m_head, 2371 BUS_DMA_NOWAIT)) 2372 return(ENOBUFS); 2373 2374 n = sc->ethercom.ec_nvlans ? 2375 m_aux_find(m_head, AF_LINK, ETHERTYPE_VLAN) : NULL; 2376 2377 for (i = 0; i < dmamap->dm_nsegs; i++) { 2378 f = &sc->bge_rdata->bge_tx_ring[frag]; 2379 if (sc->bge_cdata.bge_tx_chain[frag] != NULL) 2380 break; 2381 bge_set_hostaddr(&f->bge_addr, dmamap->dm_segs[i].ds_addr); 2382 f->bge_len = dmamap->dm_segs[i].ds_len; 2383 f->bge_flags = csum_flags; 2384 2385 if (n != NULL) { 2386 f->bge_flags |= BGE_TXBDFLAG_VLAN_TAG; 2387 f->bge_vlan_tag = *mtod(n, int *); 2388 } else { 2389 f->bge_vlan_tag = 0; 2390 } 2391 /* 2392 * Sanity check: avoid coming within 16 descriptors 2393 * of the end of the ring. 2394 */ 2395 if ((BGE_TX_RING_CNT - (sc->bge_txcnt + cnt)) < 16) 2396 return(ENOBUFS); 2397 cur = frag; 2398 BGE_INC(frag, BGE_TX_RING_CNT); 2399 cnt++; 2400 } 2401 2402 if (i < dmamap->dm_nsegs) 2403 return ENOBUFS; 2404 2405 bus_dmamap_sync(sc->bge_dmatag, dmamap, 0, dmamap->dm_mapsize, 2406 BUS_DMASYNC_PREWRITE); 2407 2408 if (frag == sc->bge_tx_saved_considx) 2409 return(ENOBUFS); 2410 2411 sc->bge_rdata->bge_tx_ring[cur].bge_flags |= BGE_TXBDFLAG_END; 2412 sc->bge_cdata.bge_tx_chain[cur] = m_head; 2413 SLIST_REMOVE_HEAD(&sc->txdma_list, link); 2414 sc->txdma[cur] = dma; 2415 sc->bge_txcnt += cnt; 2416 2417 *txidx = frag; 2418 2419 return(0); 2420 } 2421 2422 /* 2423 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 2424 * to the mbuf data regions directly in the transmit descriptors. 2425 */ 2426 void 2427 bge_start(ifp) 2428 struct ifnet *ifp; 2429 { 2430 struct bge_softc *sc; 2431 struct mbuf *m_head = NULL; 2432 u_int32_t prodidx = 0; 2433 int pkts = 0; 2434 2435 sc = ifp->if_softc; 2436 2437 if (!sc->bge_link && ifp->if_snd.ifq_len < 10) 2438 return; 2439 2440 prodidx = CSR_READ_4(sc, BGE_MBX_TX_HOST_PROD0_LO); 2441 2442 while(sc->bge_cdata.bge_tx_chain[prodidx] == NULL) { 2443 IFQ_POLL(&ifp->if_snd, m_head); 2444 if (m_head == NULL) 2445 break; 2446 2447 #if 0 2448 /* 2449 * XXX 2450 * safety overkill. If this is a fragmented packet chain 2451 * with delayed TCP/UDP checksums, then only encapsulate 2452 * it if we have enough descriptors to handle the entire 2453 * chain at once. 2454 * (paranoia -- may not actually be needed) 2455 */ 2456 if (m_head->m_flags & M_FIRSTFRAG && 2457 m_head->m_pkthdr.csum_flags & (CSUM_DELAY_DATA)) { 2458 if ((BGE_TX_RING_CNT - sc->bge_txcnt) < 2459 m_head->m_pkthdr.csum_data + 16) { 2460 ifp->if_flags |= IFF_OACTIVE; 2461 break; 2462 } 2463 } 2464 #endif 2465 2466 /* 2467 * Pack the data into the transmit ring. If we 2468 * don't have room, set the OACTIVE flag and wait 2469 * for the NIC to drain the ring. 2470 */ 2471 if (bge_encap(sc, m_head, &prodidx)) { 2472 ifp->if_flags |= IFF_OACTIVE; 2473 break; 2474 } 2475 2476 /* now we are committed to transmit the packet */ 2477 IFQ_DEQUEUE(&ifp->if_snd, m_head); 2478 pkts++; 2479 2480 #if NBPFILTER > 0 2481 /* 2482 * If there's a BPF listener, bounce a copy of this frame 2483 * to him. 2484 */ 2485 if (ifp->if_bpf) 2486 bpf_mtap(ifp->if_bpf, m_head); 2487 #endif 2488 } 2489 if (pkts == 0) 2490 return; 2491 2492 /* Transmit */ 2493 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); 2494 2495 /* 2496 * Set a timeout in case the chip goes out to lunch. 2497 */ 2498 ifp->if_timer = 5; 2499 } 2500 2501 /* 2502 * If we have a BCM5400 or BCM5401 PHY, we need to properly 2503 * program its internal DSP. Failing to do this can result in 2504 * massive packet loss at 1Gb speeds. 2505 */ 2506 void 2507 bge_phy_hack(sc) 2508 struct bge_softc *sc; 2509 { 2510 struct bge_bcom_hack bhack[] = { 2511 { BRGPHY_MII_AUXCTL, 0x4C20 }, 2512 { BRGPHY_MII_DSP_ADDR_REG, 0x0012 }, 2513 { BRGPHY_MII_DSP_RW_PORT, 0x1804 }, 2514 { BRGPHY_MII_DSP_ADDR_REG, 0x0013 }, 2515 { BRGPHY_MII_DSP_RW_PORT, 0x1204 }, 2516 { BRGPHY_MII_DSP_ADDR_REG, 0x8006 }, 2517 { BRGPHY_MII_DSP_RW_PORT, 0x0132 }, 2518 { BRGPHY_MII_DSP_ADDR_REG, 0x8006 }, 2519 { BRGPHY_MII_DSP_RW_PORT, 0x0232 }, 2520 { BRGPHY_MII_DSP_ADDR_REG, 0x201F }, 2521 { BRGPHY_MII_DSP_RW_PORT, 0x0A20 }, 2522 { 0, 0 } }; 2523 u_int16_t vid, did; 2524 int i; 2525 2526 vid = bge_miibus_readreg(&sc->bge_dev, 1, MII_PHYIDR1); 2527 did = bge_miibus_readreg(&sc->bge_dev, 1, MII_PHYIDR2); 2528 2529 if (MII_OUI(vid, did) == MII_OUI_BROADCOM && 2530 (MII_MODEL(did) == MII_MODEL_BROADCOM_BCM5400 || 2531 MII_MODEL(did) == MII_MODEL_BROADCOM_BCM5401)) { 2532 i = 0; 2533 while (bhack[i].reg) { 2534 bge_miibus_writereg(&sc->bge_dev, 1, bhack[i].reg, 2535 bhack[i].val); 2536 i++; 2537 } 2538 } 2539 } 2540 2541 int 2542 bge_init(ifp) 2543 struct ifnet *ifp; 2544 { 2545 struct bge_softc *sc = ifp->if_softc; 2546 u_int16_t *m; 2547 int s, error; 2548 2549 s = splnet(); 2550 2551 ifp = &sc->ethercom.ec_if; 2552 2553 /* Cancel pending I/O and flush buffers. */ 2554 bge_stop(sc); 2555 bge_reset(sc); 2556 bge_chipinit(sc); 2557 2558 /* 2559 * Init the various state machines, ring 2560 * control blocks and firmware. 2561 */ 2562 error = bge_blockinit(sc); 2563 if (error != 0) { 2564 printf("%s: initialization error %d\n", sc->bge_dev.dv_xname, 2565 error); 2566 splx(s); 2567 return error; 2568 } 2569 2570 ifp = &sc->ethercom.ec_if; 2571 2572 /* Specify MTU. */ 2573 CSR_WRITE_4(sc, BGE_RX_MTU, ifp->if_mtu + 2574 ETHER_HDR_LEN + ETHER_CRC_LEN); 2575 2576 /* Load our MAC address. */ 2577 m = (u_int16_t *)&(LLADDR(ifp->if_sadl)[0]); 2578 CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0])); 2579 CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, (htons(m[1]) << 16) | htons(m[2])); 2580 2581 /* Enable or disable promiscuous mode as needed. */ 2582 if (ifp->if_flags & IFF_PROMISC) { 2583 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 2584 } else { 2585 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 2586 } 2587 2588 /* Program multicast filter. */ 2589 bge_setmulti(sc); 2590 2591 /* Init RX ring. */ 2592 bge_init_rx_ring_std(sc); 2593 2594 /* Init jumbo RX ring. */ 2595 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 2596 bge_init_rx_ring_jumbo(sc); 2597 2598 /* Init our RX return ring index */ 2599 sc->bge_rx_saved_considx = 0; 2600 2601 /* Init TX ring. */ 2602 bge_init_tx_ring(sc); 2603 2604 /* Turn on transmitter */ 2605 BGE_SETBIT(sc, BGE_TX_MODE, BGE_TXMODE_ENABLE); 2606 2607 /* Turn on receiver */ 2608 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE); 2609 2610 /* Tell firmware we're alive. */ 2611 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 2612 2613 /* Enable host interrupts. */ 2614 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA); 2615 BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); 2616 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 0); 2617 2618 bge_ifmedia_upd(ifp); 2619 2620 ifp->if_flags |= IFF_RUNNING; 2621 ifp->if_flags &= ~IFF_OACTIVE; 2622 2623 splx(s); 2624 2625 callout_reset(&sc->bge_timeout, hz, bge_tick, sc); 2626 2627 return 0; 2628 } 2629 2630 /* 2631 * Set media options. 2632 */ 2633 int 2634 bge_ifmedia_upd(ifp) 2635 struct ifnet *ifp; 2636 { 2637 struct bge_softc *sc = ifp->if_softc; 2638 struct mii_data *mii = &sc->bge_mii; 2639 struct ifmedia *ifm = &sc->bge_ifmedia; 2640 2641 /* If this is a 1000baseX NIC, enable the TBI port. */ 2642 if (sc->bge_tbi) { 2643 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 2644 return(EINVAL); 2645 switch(IFM_SUBTYPE(ifm->ifm_media)) { 2646 case IFM_AUTO: 2647 break; 2648 case IFM_1000_SX: 2649 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 2650 BGE_CLRBIT(sc, BGE_MAC_MODE, 2651 BGE_MACMODE_HALF_DUPLEX); 2652 } else { 2653 BGE_SETBIT(sc, BGE_MAC_MODE, 2654 BGE_MACMODE_HALF_DUPLEX); 2655 } 2656 break; 2657 default: 2658 return(EINVAL); 2659 } 2660 return(0); 2661 } 2662 2663 sc->bge_link = 0; 2664 if (mii->mii_instance) { 2665 struct mii_softc *miisc; 2666 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL; 2667 miisc = LIST_NEXT(miisc, mii_list)) 2668 mii_phy_reset(miisc); 2669 } 2670 bge_phy_hack(sc); 2671 mii_mediachg(mii); 2672 2673 return(0); 2674 } 2675 2676 /* 2677 * Report current media status. 2678 */ 2679 void 2680 bge_ifmedia_sts(ifp, ifmr) 2681 struct ifnet *ifp; 2682 struct ifmediareq *ifmr; 2683 { 2684 struct bge_softc *sc = ifp->if_softc; 2685 struct mii_data *mii = &sc->bge_mii; 2686 2687 if (sc->bge_tbi) { 2688 ifmr->ifm_status = IFM_AVALID; 2689 ifmr->ifm_active = IFM_ETHER; 2690 if (CSR_READ_4(sc, BGE_MAC_STS) & 2691 BGE_MACSTAT_TBI_PCS_SYNCHED) 2692 ifmr->ifm_status |= IFM_ACTIVE; 2693 ifmr->ifm_active |= IFM_1000_SX; 2694 if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX) 2695 ifmr->ifm_active |= IFM_HDX; 2696 else 2697 ifmr->ifm_active |= IFM_FDX; 2698 return; 2699 } 2700 2701 mii_pollstat(mii); 2702 ifmr->ifm_active = mii->mii_media_active; 2703 ifmr->ifm_status = mii->mii_media_status; 2704 } 2705 2706 int 2707 bge_ioctl(ifp, command, data) 2708 struct ifnet *ifp; 2709 u_long command; 2710 caddr_t data; 2711 { 2712 struct bge_softc *sc = ifp->if_softc; 2713 struct ifreq *ifr = (struct ifreq *) data; 2714 int s, error = 0; 2715 struct mii_data *mii; 2716 2717 s = splnet(); 2718 2719 switch(command) { 2720 case SIOCSIFFLAGS: 2721 if (ifp->if_flags & IFF_UP) { 2722 /* 2723 * If only the state of the PROMISC flag changed, 2724 * then just use the 'set promisc mode' command 2725 * instead of reinitializing the entire NIC. Doing 2726 * a full re-init means reloading the firmware and 2727 * waiting for it to start up, which may take a 2728 * second or two. 2729 */ 2730 if (ifp->if_flags & IFF_RUNNING && 2731 ifp->if_flags & IFF_PROMISC && 2732 !(sc->bge_if_flags & IFF_PROMISC)) { 2733 BGE_SETBIT(sc, BGE_RX_MODE, 2734 BGE_RXMODE_RX_PROMISC); 2735 } else if (ifp->if_flags & IFF_RUNNING && 2736 !(ifp->if_flags & IFF_PROMISC) && 2737 sc->bge_if_flags & IFF_PROMISC) { 2738 BGE_CLRBIT(sc, BGE_RX_MODE, 2739 BGE_RXMODE_RX_PROMISC); 2740 } else 2741 bge_init(ifp); 2742 } else { 2743 if (ifp->if_flags & IFF_RUNNING) { 2744 bge_stop(sc); 2745 } 2746 } 2747 sc->bge_if_flags = ifp->if_flags; 2748 error = 0; 2749 break; 2750 case SIOCSIFMEDIA: 2751 case SIOCGIFMEDIA: 2752 if (sc->bge_tbi) { 2753 error = ifmedia_ioctl(ifp, ifr, &sc->bge_ifmedia, 2754 command); 2755 } else { 2756 mii = &sc->bge_mii; 2757 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, 2758 command); 2759 } 2760 error = 0; 2761 break; 2762 default: 2763 error = ether_ioctl(ifp, command, data); 2764 if (error == ENETRESET) { 2765 bge_setmulti(sc); 2766 error = 0; 2767 } 2768 break; 2769 } 2770 2771 splx(s); 2772 2773 return(error); 2774 } 2775 2776 void 2777 bge_watchdog(ifp) 2778 struct ifnet *ifp; 2779 { 2780 struct bge_softc *sc; 2781 2782 sc = ifp->if_softc; 2783 2784 printf("%s: watchdog timeout -- resetting\n", sc->bge_dev.dv_xname); 2785 2786 ifp->if_flags &= ~IFF_RUNNING; 2787 bge_init(ifp); 2788 2789 ifp->if_oerrors++; 2790 } 2791 2792 static void 2793 bge_stop_block(struct bge_softc *sc, bus_addr_t reg, uint32_t bit) 2794 { 2795 int i; 2796 2797 BGE_CLRBIT(sc, reg, bit); 2798 2799 for (i = 0; i < BGE_TIMEOUT; i++) { 2800 if ((CSR_READ_4(sc, reg) & bit) == 0) 2801 return; 2802 delay(100); 2803 } 2804 2805 printf("%s: block failed to stop: reg 0x%lx, bit 0x%08x\n", 2806 sc->bge_dev.dv_xname, (u_long) reg, bit); 2807 } 2808 2809 /* 2810 * Stop the adapter and free any mbufs allocated to the 2811 * RX and TX lists. 2812 */ 2813 void 2814 bge_stop(sc) 2815 struct bge_softc *sc; 2816 { 2817 struct ifnet *ifp = &sc->ethercom.ec_if; 2818 2819 callout_stop(&sc->bge_timeout); 2820 2821 /* 2822 * Disable all of the receiver blocks 2823 */ 2824 bge_stop_block(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE); 2825 bge_stop_block(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 2826 bge_stop_block(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 2827 bge_stop_block(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 2828 bge_stop_block(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE); 2829 bge_stop_block(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 2830 bge_stop_block(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE); 2831 2832 /* 2833 * Disable all of the transmit blocks 2834 */ 2835 bge_stop_block(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 2836 bge_stop_block(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 2837 bge_stop_block(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 2838 bge_stop_block(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE); 2839 bge_stop_block(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE); 2840 bge_stop_block(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 2841 bge_stop_block(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 2842 2843 /* 2844 * Shut down all of the memory managers and related 2845 * state machines. 2846 */ 2847 bge_stop_block(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE); 2848 bge_stop_block(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE); 2849 bge_stop_block(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 2850 2851 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 2852 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 2853 2854 bge_stop_block(sc, BGE_BMAN_MODE, BGE_BMANMODE_ENABLE); 2855 bge_stop_block(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 2856 2857 /* Disable host interrupts. */ 2858 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); 2859 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 1); 2860 2861 /* 2862 * Tell firmware we're shutting down. 2863 */ 2864 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 2865 2866 /* Free the RX lists. */ 2867 bge_free_rx_ring_std(sc); 2868 2869 /* Free jumbo RX list. */ 2870 bge_free_rx_ring_jumbo(sc); 2871 2872 /* Free TX buffers. */ 2873 bge_free_tx_ring(sc); 2874 2875 /* 2876 * Isolate/power down the PHY. 2877 */ 2878 if (!sc->bge_tbi) 2879 mii_down(&sc->bge_mii); 2880 2881 sc->bge_link = 0; 2882 2883 sc->bge_tx_saved_considx = BGE_TXCONS_UNSET; 2884 2885 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2886 } 2887 2888 /* 2889 * Stop all chip I/O so that the kernel's probe routines don't 2890 * get confused by errant DMAs when rebooting. 2891 */ 2892 void 2893 bge_shutdown(xsc) 2894 void *xsc; 2895 { 2896 struct bge_softc *sc = (struct bge_softc *)xsc; 2897 2898 bge_stop(sc); 2899 bge_reset(sc); 2900 } 2901
Indexes created Tue Sep 23 14:10:03 GMT 2025