if_bge.c revision 1.149
1 /* $NetBSD: if_bge.c,v 1.149 2008/07/24 08:14:49 sborrill Exp $ */ 2 3 /* 4 * Copyright (c) 2001 Wind River Systems 5 * Copyright (c) 1997, 1998, 1999, 2001 6 * Bill Paul <wpaul (at) windriver.com>. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Bill Paul. 19 * 4. Neither the name of the author nor the names of any co-contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 33 * THE POSSIBILITY OF SUCH DAMAGE. 34 * 35 * $FreeBSD: if_bge.c,v 1.13 2002/04/04 06:01:31 wpaul Exp $ 36 */ 37 38 /* 39 * Broadcom BCM570x family gigabit ethernet driver for NetBSD. 40 * 41 * NetBSD version by: 42 * 43 * Frank van der Linden <fvdl (at) wasabisystems.com> 44 * Jason Thorpe <thorpej (at) wasabisystems.com> 45 * Jonathan Stone <jonathan (at) dsg.stanford.edu> 46 * 47 * Originally written for FreeBSD by Bill Paul <wpaul (at) windriver.com> 48 * Senior Engineer, Wind River Systems 49 */ 50 51 /* 52 * The Broadcom BCM5700 is based on technology originally developed by 53 * Alteon Networks as part of the Tigon I and Tigon II gigabit ethernet 54 * MAC chips. The BCM5700, sometimes refered to as the Tigon III, has 55 * two on-board MIPS R4000 CPUs and can have as much as 16MB of external 56 * SSRAM. The BCM5700 supports TCP, UDP and IP checksum offload, jumbo 57 * frames, highly configurable RX filtering, and 16 RX and TX queues 58 * (which, along with RX filter rules, can be used for QOS applications). 59 * Other features, such as TCP segmentation, may be available as part 60 * of value-added firmware updates. Unlike the Tigon I and Tigon II, 61 * firmware images can be stored in hardware and need not be compiled 62 * into the driver. 63 * 64 * The BCM5700 supports the PCI v2.2 and PCI-X v1.0 standards, and will 65 * function in a 32-bit/64-bit 33/66MHz bus, or a 64-bit/133MHz bus. 66 * 67 * The BCM5701 is a single-chip solution incorporating both the BCM5700 68 * MAC and a BCM5401 10/100/1000 PHY. Unlike the BCM5700, the BCM5701 69 * does not support external SSRAM. 70 * 71 * Broadcom also produces a variation of the BCM5700 under the "Altima" 72 * brand name, which is functionally similar but lacks PCI-X support. 73 * 74 * Without external SSRAM, you can only have at most 4 TX rings, 75 * and the use of the mini RX ring is disabled. This seems to imply 76 * that these features are simply not available on the BCM5701. As a 77 * result, this driver does not implement any support for the mini RX 78 * ring. 79 */ 80 81 #include <sys/cdefs.h> 82 __KERNEL_RCSID(0, "$NetBSD: if_bge.c,v 1.149 2008/07/24 08:14:49 sborrill Exp $"); 83 84 #include "bpfilter.h" 85 #include "vlan.h" 86 #include "rnd.h" 87 88 #include <sys/param.h> 89 #include <sys/systm.h> 90 #include <sys/callout.h> 91 #include <sys/sockio.h> 92 #include <sys/mbuf.h> 93 #include <sys/malloc.h> 94 #include <sys/kernel.h> 95 #include <sys/device.h> 96 #include <sys/socket.h> 97 #include <sys/sysctl.h> 98 99 #include <net/if.h> 100 #include <net/if_dl.h> 101 #include <net/if_media.h> 102 #include <net/if_ether.h> 103 104 #if NRND > 0 105 #include <sys/rnd.h> 106 #endif 107 108 #ifdef INET 109 #include <netinet/in.h> 110 #include <netinet/in_systm.h> 111 #include <netinet/in_var.h> 112 #include <netinet/ip.h> 113 #endif 114 115 /* Headers for TCP Segmentation Offload (TSO) */ 116 #include <netinet/in_systm.h> /* n_time for <netinet/ip.h>... */ 117 #include <netinet/in.h> /* ip_{src,dst}, for <netinet/ip.h> */ 118 #include <netinet/ip.h> /* for struct ip */ 119 #include <netinet/tcp.h> /* for struct tcphdr */ 120 121 122 #if NBPFILTER > 0 123 #include <net/bpf.h> 124 #endif 125 126 #include <dev/pci/pcireg.h> 127 #include <dev/pci/pcivar.h> 128 #include <dev/pci/pcidevs.h> 129 130 #include <dev/mii/mii.h> 131 #include <dev/mii/miivar.h> 132 #include <dev/mii/miidevs.h> 133 #include <dev/mii/brgphyreg.h> 134 135 #include <dev/pci/if_bgereg.h> 136 137 #include <uvm/uvm_extern.h> 138 139 #define ETHER_MIN_NOPAD (ETHER_MIN_LEN - ETHER_CRC_LEN) /* i.e., 60 */ 140 141 142 /* 143 * Tunable thresholds for rx-side bge interrupt mitigation. 144 */ 145 146 /* 147 * The pairs of values below were obtained from empirical measurement 148 * on bcm5700 rev B2; they ar designed to give roughly 1 receive 149 * interrupt for every N packets received, where N is, approximately, 150 * the second value (rx_max_bds) in each pair. The values are chosen 151 * such that moving from one pair to the succeeding pair was observed 152 * to roughly halve interrupt rate under sustained input packet load. 153 * The values were empirically chosen to avoid overflowing internal 154 * limits on the bcm5700: inreasing rx_ticks much beyond 600 155 * results in internal wrapping and higher interrupt rates. 156 * The limit of 46 frames was chosen to match NFS workloads. 157 * 158 * These values also work well on bcm5701, bcm5704C, and (less 159 * tested) bcm5703. On other chipsets, (including the Altima chip 160 * family), the larger values may overflow internal chip limits, 161 * leading to increasing interrupt rates rather than lower interrupt 162 * rates. 163 * 164 * Applications using heavy interrupt mitigation (interrupting every 165 * 32 or 46 frames) in both directions may need to increase the TCP 166 * windowsize to above 131072 bytes (e.g., to 199608 bytes) to sustain 167 * full link bandwidth, due to ACKs and window updates lingering 168 * in the RX queue during the 30-to-40-frame interrupt-mitigation window. 169 */ 170 static const struct bge_load_rx_thresh { 171 int rx_ticks; 172 int rx_max_bds; } 173 bge_rx_threshes[] = { 174 { 32, 2 }, 175 { 50, 4 }, 176 { 100, 8 }, 177 { 192, 16 }, 178 { 416, 32 }, 179 { 598, 46 } 180 }; 181 #define NBGE_RX_THRESH (sizeof(bge_rx_threshes) / sizeof(bge_rx_threshes[0])) 182 183 /* XXX patchable; should be sysctl'able */ 184 static int bge_auto_thresh = 1; 185 static int bge_rx_thresh_lvl; 186 187 static int bge_rxthresh_nodenum; 188 189 static int bge_probe(device_t, cfdata_t, void *); 190 static void bge_attach(device_t, device_t, void *); 191 static void bge_release_resources(struct bge_softc *); 192 static void bge_txeof(struct bge_softc *); 193 static void bge_rxeof(struct bge_softc *); 194 195 static void bge_tick(void *); 196 static void bge_stats_update(struct bge_softc *); 197 static int bge_encap(struct bge_softc *, struct mbuf *, u_int32_t *); 198 199 static int bge_intr(void *); 200 static void bge_start(struct ifnet *); 201 static int bge_ioctl(struct ifnet *, u_long, void *); 202 static int bge_init(struct ifnet *); 203 static void bge_stop(struct ifnet *, int); 204 static void bge_watchdog(struct ifnet *); 205 static int bge_ifmedia_upd(struct ifnet *); 206 static void bge_ifmedia_sts(struct ifnet *, struct ifmediareq *); 207 208 static void bge_setmulti(struct bge_softc *); 209 210 static void bge_handle_events(struct bge_softc *); 211 static int bge_alloc_jumbo_mem(struct bge_softc *); 212 #if 0 /* XXX */ 213 static void bge_free_jumbo_mem(struct bge_softc *); 214 #endif 215 static void *bge_jalloc(struct bge_softc *); 216 static void bge_jfree(struct mbuf *, void *, size_t, void *); 217 static int bge_newbuf_std(struct bge_softc *, int, struct mbuf *, 218 bus_dmamap_t); 219 static int bge_newbuf_jumbo(struct bge_softc *, int, struct mbuf *); 220 static int bge_init_rx_ring_std(struct bge_softc *); 221 static void bge_free_rx_ring_std(struct bge_softc *); 222 static int bge_init_rx_ring_jumbo(struct bge_softc *); 223 static void bge_free_rx_ring_jumbo(struct bge_softc *); 224 static void bge_free_tx_ring(struct bge_softc *); 225 static int bge_init_tx_ring(struct bge_softc *); 226 227 static int bge_chipinit(struct bge_softc *); 228 static int bge_blockinit(struct bge_softc *); 229 static int bge_setpowerstate(struct bge_softc *, int); 230 231 static void bge_reset(struct bge_softc *); 232 233 #define BGE_DEBUG 234 #ifdef BGE_DEBUG 235 #define DPRINTF(x) if (bgedebug) printf x 236 #define DPRINTFN(n,x) if (bgedebug >= (n)) printf x 237 #define BGE_TSO_PRINTF(x) do { if (bge_tso_debug) printf x ;} while (0) 238 int bgedebug = 0; 239 int bge_tso_debug = 0; 240 #else 241 #define DPRINTF(x) 242 #define DPRINTFN(n,x) 243 #define BGE_TSO_PRINTF(x) 244 #endif 245 246 #ifdef BGE_EVENT_COUNTERS 247 #define BGE_EVCNT_INCR(ev) (ev).ev_count++ 248 #define BGE_EVCNT_ADD(ev, val) (ev).ev_count += (val) 249 #define BGE_EVCNT_UPD(ev, val) (ev).ev_count = (val) 250 #else 251 #define BGE_EVCNT_INCR(ev) /* nothing */ 252 #define BGE_EVCNT_ADD(ev, val) /* nothing */ 253 #define BGE_EVCNT_UPD(ev, val) /* nothing */ 254 #endif 255 256 /* Various chip quirks. */ 257 #define BGE_QUIRK_LINK_STATE_BROKEN 0x00000001 258 #define BGE_QUIRK_CSUM_BROKEN 0x00000002 259 #define BGE_QUIRK_ONLY_PHY_1 0x00000004 260 #define BGE_QUIRK_5700_SMALLDMA 0x00000008 261 #define BGE_QUIRK_5700_PCIX_REG_BUG 0x00000010 262 #define BGE_QUIRK_PRODUCER_BUG 0x00000020 263 #define BGE_QUIRK_PCIX_DMA_ALIGN_BUG 0x00000040 264 #define BGE_QUIRK_5705_CORE 0x00000080 265 #define BGE_QUIRK_FEWER_MBUFS 0x00000100 266 267 /* 268 * XXX: how to handle variants based on 5750 and derivatives: 269 * 5750 5751, 5721, possibly 5714, 5752, and 5708?, which 270 * in general behave like a 5705, except with additional quirks. 271 * This driver's current handling of the 5721 is wrong; 272 * how we map ASIC revision to "quirks" needs more thought. 273 * (defined here until the thought is done). 274 */ 275 #define BGE_IS_5714_FAMILY(sc) \ 276 (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5714_A0 || \ 277 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5780 || \ 278 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5714 ) 279 280 #define BGE_IS_5750_OR_BEYOND(sc) \ 281 (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5750 || \ 282 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5752 || \ 283 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5755 || \ 284 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5787 || \ 285 BGE_IS_5714_FAMILY(sc) ) 286 287 #define BGE_IS_5705_OR_BEYOND(sc) \ 288 ( ((sc)->bge_quirks & BGE_QUIRK_5705_CORE) || \ 289 BGE_IS_5750_OR_BEYOND(sc) ) 290 291 292 /* following bugs are common to bcm5700 rev B, all flavours */ 293 #define BGE_QUIRK_5700_COMMON \ 294 (BGE_QUIRK_5700_SMALLDMA|BGE_QUIRK_PRODUCER_BUG) 295 296 CFATTACH_DECL_NEW(bge, sizeof(struct bge_softc), 297 bge_probe, bge_attach, NULL, NULL); 298 299 static u_int32_t 300 bge_readmem_ind(struct bge_softc *sc, int off) 301 { 302 pcireg_t val; 303 304 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_BASEADDR, off); 305 val = pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_DATA); 306 return val; 307 } 308 309 static void 310 bge_writemem_ind(struct bge_softc *sc, int off, int val) 311 { 312 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_BASEADDR, off); 313 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_DATA, val); 314 } 315 316 #ifdef notdef 317 static u_int32_t 318 bge_readreg_ind(struct bge_softc *sc, int off) 319 { 320 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_REG_BASEADDR, off); 321 return(pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_REG_DATA)); 322 } 323 #endif 324 325 static void 326 bge_writereg_ind(struct bge_softc *sc, int off, int val) 327 { 328 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_REG_BASEADDR, off); 329 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_REG_DATA, val); 330 } 331 332 #ifdef notdef 333 static u_int8_t 334 bge_vpd_readbyte(struct bge_softc *sc, int addr) 335 { 336 int i; 337 u_int32_t val; 338 339 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_VPD_ADDR, addr); 340 for (i = 0; i < BGE_TIMEOUT * 10; i++) { 341 DELAY(10); 342 if (pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_VPD_ADDR) & 343 BGE_VPD_FLAG) 344 break; 345 } 346 347 if (i == BGE_TIMEOUT) { 348 aprint_error_dev(sc->bge_dev, "VPD read timed out\n"); 349 return(0); 350 } 351 352 val = pci_conf_read(sc->sc_pc, sc->sca_pcitag, BGE_PCI_VPD_DATA); 353 354 return((val >> ((addr % 4) * 8)) & 0xFF); 355 } 356 357 static void 358 bge_vpd_read_res(struct bge_softc *sc, struct vpd_res *res, int addr) 359 { 360 int i; 361 u_int8_t *ptr; 362 363 ptr = (u_int8_t *)res; 364 for (i = 0; i < sizeof(struct vpd_res); i++) 365 ptr[i] = bge_vpd_readbyte(sc, i + addr); 366 } 367 368 static void 369 bge_vpd_read(struct bge_softc *sc) 370 { 371 int pos = 0, i; 372 struct vpd_res res; 373 374 if (sc->bge_vpd_prodname != NULL) 375 free(sc->bge_vpd_prodname, M_DEVBUF); 376 if (sc->bge_vpd_readonly != NULL) 377 free(sc->bge_vpd_readonly, M_DEVBUF); 378 sc->bge_vpd_prodname = NULL; 379 sc->bge_vpd_readonly = NULL; 380 381 bge_vpd_read_res(sc, &res, pos); 382 383 if (res.vr_id != VPD_RES_ID) { 384 aprint_error_dev("bad VPD resource id: expected %x got %x\n", 385 VPD_RES_ID, res.vr_id); 386 return; 387 } 388 389 pos += sizeof(res); 390 sc->bge_vpd_prodname = malloc(res.vr_len + 1, M_DEVBUF, M_NOWAIT); 391 if (sc->bge_vpd_prodname == NULL) 392 panic("bge_vpd_read"); 393 for (i = 0; i < res.vr_len; i++) 394 sc->bge_vpd_prodname[i] = bge_vpd_readbyte(sc, i + pos); 395 sc->bge_vpd_prodname[i] = '\0'; 396 pos += i; 397 398 bge_vpd_read_res(sc, &res, pos); 399 400 if (res.vr_id != VPD_RES_READ) { 401 aprint_error_dev(sc->bge_dev, 402 "bad VPD resource id: expected %x got %x\n", 403 VPD_RES_READ, res.vr_id); 404 return; 405 } 406 407 pos += sizeof(res); 408 sc->bge_vpd_readonly = malloc(res.vr_len, M_DEVBUF, M_NOWAIT); 409 if (sc->bge_vpd_readonly == NULL) 410 panic("bge_vpd_read"); 411 for (i = 0; i < res.vr_len + 1; i++) 412 sc->bge_vpd_readonly[i] = bge_vpd_readbyte(sc, i + pos); 413 } 414 #endif 415 416 /* 417 * Read a byte of data stored in the EEPROM at address 'addr.' The 418 * BCM570x supports both the traditional bitbang interface and an 419 * auto access interface for reading the EEPROM. We use the auto 420 * access method. 421 */ 422 static u_int8_t 423 bge_eeprom_getbyte(struct bge_softc *sc, int addr, u_int8_t *dest) 424 { 425 int i; 426 u_int32_t byte = 0; 427 428 /* 429 * Enable use of auto EEPROM access so we can avoid 430 * having to use the bitbang method. 431 */ 432 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM); 433 434 /* Reset the EEPROM, load the clock period. */ 435 CSR_WRITE_4(sc, BGE_EE_ADDR, 436 BGE_EEADDR_RESET|BGE_EEHALFCLK(BGE_HALFCLK_384SCL)); 437 DELAY(20); 438 439 /* Issue the read EEPROM command. */ 440 CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr); 441 442 /* Wait for completion */ 443 for(i = 0; i < BGE_TIMEOUT * 10; i++) { 444 DELAY(10); 445 if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE) 446 break; 447 } 448 449 if (i == BGE_TIMEOUT) { 450 aprint_error_dev(sc->bge_dev, "eeprom read timed out\n"); 451 return(0); 452 } 453 454 /* Get result. */ 455 byte = CSR_READ_4(sc, BGE_EE_DATA); 456 457 *dest = (byte >> ((addr % 4) * 8)) & 0xFF; 458 459 return(0); 460 } 461 462 /* 463 * Read a sequence of bytes from the EEPROM. 464 */ 465 static int 466 bge_read_eeprom(struct bge_softc *sc, void *destv, int off, int cnt) 467 { 468 int err = 0, i; 469 u_int8_t byte = 0; 470 char *dest = destv; 471 472 for (i = 0; i < cnt; i++) { 473 err = bge_eeprom_getbyte(sc, off + i, &byte); 474 if (err) 475 break; 476 *(dest + i) = byte; 477 } 478 479 return(err ? 1 : 0); 480 } 481 482 static int 483 bge_miibus_readreg(device_t dev, int phy, int reg) 484 { 485 struct bge_softc *sc = device_private(dev); 486 u_int32_t val; 487 u_int32_t saved_autopoll; 488 int i; 489 490 /* 491 * Several chips with builtin PHYs will incorrectly answer to 492 * other PHY instances than the builtin PHY at id 1. 493 */ 494 if (phy != 1 && (sc->bge_quirks & BGE_QUIRK_ONLY_PHY_1)) 495 return(0); 496 497 /* Reading with autopolling on may trigger PCI errors */ 498 saved_autopoll = CSR_READ_4(sc, BGE_MI_MODE); 499 if (saved_autopoll & BGE_MIMODE_AUTOPOLL) { 500 CSR_WRITE_4(sc, BGE_MI_MODE, 501 saved_autopoll &~ BGE_MIMODE_AUTOPOLL); 502 DELAY(40); 503 } 504 505 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_READ|BGE_MICOMM_BUSY| 506 BGE_MIPHY(phy)|BGE_MIREG(reg)); 507 508 for (i = 0; i < BGE_TIMEOUT; i++) { 509 val = CSR_READ_4(sc, BGE_MI_COMM); 510 if (!(val & BGE_MICOMM_BUSY)) 511 break; 512 delay(10); 513 } 514 515 if (i == BGE_TIMEOUT) { 516 aprint_error_dev(sc->bge_dev, "PHY read timed out\n"); 517 val = 0; 518 goto done; 519 } 520 521 val = CSR_READ_4(sc, BGE_MI_COMM); 522 523 done: 524 if (saved_autopoll & BGE_MIMODE_AUTOPOLL) { 525 CSR_WRITE_4(sc, BGE_MI_MODE, saved_autopoll); 526 DELAY(40); 527 } 528 529 if (val & BGE_MICOMM_READFAIL) 530 return(0); 531 532 return(val & 0xFFFF); 533 } 534 535 static void 536 bge_miibus_writereg(device_t dev, int phy, int reg, int val) 537 { 538 struct bge_softc *sc = device_private(dev); 539 u_int32_t saved_autopoll; 540 int i; 541 542 /* Touching the PHY while autopolling is on may trigger PCI errors */ 543 saved_autopoll = CSR_READ_4(sc, BGE_MI_MODE); 544 if (saved_autopoll & BGE_MIMODE_AUTOPOLL) { 545 delay(40); 546 CSR_WRITE_4(sc, BGE_MI_MODE, 547 saved_autopoll & (~BGE_MIMODE_AUTOPOLL)); 548 delay(10); /* 40 usec is supposed to be adequate */ 549 } 550 551 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_WRITE|BGE_MICOMM_BUSY| 552 BGE_MIPHY(phy)|BGE_MIREG(reg)|val); 553 554 for (i = 0; i < BGE_TIMEOUT; i++) { 555 if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY)) 556 break; 557 delay(10); 558 } 559 560 if (saved_autopoll & BGE_MIMODE_AUTOPOLL) { 561 CSR_WRITE_4(sc, BGE_MI_MODE, saved_autopoll); 562 delay(40); 563 } 564 565 if (i == BGE_TIMEOUT) 566 aprint_error_dev(sc->bge_dev, "PHY read timed out\n"); 567 } 568 569 static void 570 bge_miibus_statchg(device_t dev) 571 { 572 struct bge_softc *sc = device_private(dev); 573 struct mii_data *mii = &sc->bge_mii; 574 575 /* 576 * Get flow control negotiation result. 577 */ 578 if (IFM_SUBTYPE(mii->mii_media.ifm_cur->ifm_media) == IFM_AUTO && 579 (mii->mii_media_active & IFM_ETH_FMASK) != sc->bge_flowflags) { 580 sc->bge_flowflags = mii->mii_media_active & IFM_ETH_FMASK; 581 mii->mii_media_active &= ~IFM_ETH_FMASK; 582 } 583 584 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_PORTMODE); 585 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) { 586 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_GMII); 587 } else { 588 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_MII); 589 } 590 591 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 592 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX); 593 } else { 594 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX); 595 } 596 597 /* 598 * 802.3x flow control 599 */ 600 if (sc->bge_flowflags & IFM_ETH_RXPAUSE) { 601 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_FLOWCTL_ENABLE); 602 } else { 603 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_FLOWCTL_ENABLE); 604 } 605 if (sc->bge_flowflags & IFM_ETH_TXPAUSE) { 606 BGE_SETBIT(sc, BGE_TX_MODE, BGE_TXMODE_FLOWCTL_ENABLE); 607 } else { 608 BGE_CLRBIT(sc, BGE_TX_MODE, BGE_TXMODE_FLOWCTL_ENABLE); 609 } 610 } 611 612 /* 613 * Update rx threshold levels to values in a particular slot 614 * of the interrupt-mitigation table bge_rx_threshes. 615 */ 616 static void 617 bge_set_thresh(struct ifnet *ifp, int lvl) 618 { 619 struct bge_softc *sc = ifp->if_softc; 620 int s; 621 622 /* For now, just save the new Rx-intr thresholds and record 623 * that a threshold update is pending. Updating the hardware 624 * registers here (even at splhigh()) is observed to 625 * occasionaly cause glitches where Rx-interrupts are not 626 * honoured for up to 10 seconds. jonathan (at) NetBSD.org, 2003-04-05 627 */ 628 s = splnet(); 629 sc->bge_rx_coal_ticks = bge_rx_threshes[lvl].rx_ticks; 630 sc->bge_rx_max_coal_bds = bge_rx_threshes[lvl].rx_max_bds; 631 sc->bge_pending_rxintr_change = 1; 632 splx(s); 633 634 return; 635 } 636 637 638 /* 639 * Update Rx thresholds of all bge devices 640 */ 641 static void 642 bge_update_all_threshes(int lvl) 643 { 644 struct ifnet *ifp; 645 const char * const namebuf = "bge"; 646 int namelen; 647 648 if (lvl < 0) 649 lvl = 0; 650 else if( lvl >= NBGE_RX_THRESH) 651 lvl = NBGE_RX_THRESH - 1; 652 653 namelen = strlen(namebuf); 654 /* 655 * Now search all the interfaces for this name/number 656 */ 657 IFNET_FOREACH(ifp) { 658 if (strncmp(ifp->if_xname, namebuf, namelen) != 0) 659 continue; 660 /* We got a match: update if doing auto-threshold-tuning */ 661 if (bge_auto_thresh) 662 bge_set_thresh(ifp, lvl); 663 } 664 } 665 666 /* 667 * Handle events that have triggered interrupts. 668 */ 669 static void 670 bge_handle_events(struct bge_softc *sc) 671 { 672 673 return; 674 } 675 676 /* 677 * Memory management for jumbo frames. 678 */ 679 680 static int 681 bge_alloc_jumbo_mem(struct bge_softc *sc) 682 { 683 char *ptr, *kva; 684 bus_dma_segment_t seg; 685 int i, rseg, state, error; 686 struct bge_jpool_entry *entry; 687 688 state = error = 0; 689 690 /* Grab a big chunk o' storage. */ 691 if (bus_dmamem_alloc(sc->bge_dmatag, BGE_JMEM, PAGE_SIZE, 0, 692 &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 693 aprint_error_dev(sc->bge_dev, "can't alloc rx buffers\n"); 694 return ENOBUFS; 695 } 696 697 state = 1; 698 if (bus_dmamem_map(sc->bge_dmatag, &seg, rseg, BGE_JMEM, (void **)&kva, 699 BUS_DMA_NOWAIT)) { 700 aprint_error_dev(sc->bge_dev, 701 "can't map DMA buffers (%d bytes)\n", (int)BGE_JMEM); 702 error = ENOBUFS; 703 goto out; 704 } 705 706 state = 2; 707 if (bus_dmamap_create(sc->bge_dmatag, BGE_JMEM, 1, BGE_JMEM, 0, 708 BUS_DMA_NOWAIT, &sc->bge_cdata.bge_rx_jumbo_map)) { 709 aprint_error_dev(sc->bge_dev, "can't create DMA map\n"); 710 error = ENOBUFS; 711 goto out; 712 } 713 714 state = 3; 715 if (bus_dmamap_load(sc->bge_dmatag, sc->bge_cdata.bge_rx_jumbo_map, 716 kva, BGE_JMEM, NULL, BUS_DMA_NOWAIT)) { 717 aprint_error_dev(sc->bge_dev, "can't load DMA map\n"); 718 error = ENOBUFS; 719 goto out; 720 } 721 722 state = 4; 723 sc->bge_cdata.bge_jumbo_buf = (void *)kva; 724 DPRINTFN(1,("bge_jumbo_buf = %p\n", sc->bge_cdata.bge_jumbo_buf)); 725 726 SLIST_INIT(&sc->bge_jfree_listhead); 727 SLIST_INIT(&sc->bge_jinuse_listhead); 728 729 /* 730 * Now divide it up into 9K pieces and save the addresses 731 * in an array. 732 */ 733 ptr = sc->bge_cdata.bge_jumbo_buf; 734 for (i = 0; i < BGE_JSLOTS; i++) { 735 sc->bge_cdata.bge_jslots[i] = ptr; 736 ptr += BGE_JLEN; 737 entry = malloc(sizeof(struct bge_jpool_entry), 738 M_DEVBUF, M_NOWAIT); 739 if (entry == NULL) { 740 aprint_error_dev(sc->bge_dev, 741 "no memory for jumbo buffer queue!\n"); 742 error = ENOBUFS; 743 goto out; 744 } 745 entry->slot = i; 746 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, 747 entry, jpool_entries); 748 } 749 out: 750 if (error != 0) { 751 switch (state) { 752 case 4: 753 bus_dmamap_unload(sc->bge_dmatag, 754 sc->bge_cdata.bge_rx_jumbo_map); 755 case 3: 756 bus_dmamap_destroy(sc->bge_dmatag, 757 sc->bge_cdata.bge_rx_jumbo_map); 758 case 2: 759 bus_dmamem_unmap(sc->bge_dmatag, kva, BGE_JMEM); 760 case 1: 761 bus_dmamem_free(sc->bge_dmatag, &seg, rseg); 762 break; 763 default: 764 break; 765 } 766 } 767 768 return error; 769 } 770 771 /* 772 * Allocate a jumbo buffer. 773 */ 774 static void * 775 bge_jalloc(struct bge_softc *sc) 776 { 777 struct bge_jpool_entry *entry; 778 779 entry = SLIST_FIRST(&sc->bge_jfree_listhead); 780 781 if (entry == NULL) { 782 aprint_error_dev(sc->bge_dev, "no free jumbo buffers\n"); 783 return(NULL); 784 } 785 786 SLIST_REMOVE_HEAD(&sc->bge_jfree_listhead, jpool_entries); 787 SLIST_INSERT_HEAD(&sc->bge_jinuse_listhead, entry, jpool_entries); 788 return(sc->bge_cdata.bge_jslots[entry->slot]); 789 } 790 791 /* 792 * Release a jumbo buffer. 793 */ 794 static void 795 bge_jfree(struct mbuf *m, void *buf, size_t size, void *arg) 796 { 797 struct bge_jpool_entry *entry; 798 struct bge_softc *sc; 799 int i, s; 800 801 /* Extract the softc struct pointer. */ 802 sc = (struct bge_softc *)arg; 803 804 if (sc == NULL) 805 panic("bge_jfree: can't find softc pointer!"); 806 807 /* calculate the slot this buffer belongs to */ 808 809 i = ((char *)buf 810 - (char *)sc->bge_cdata.bge_jumbo_buf) / BGE_JLEN; 811 812 if ((i < 0) || (i >= BGE_JSLOTS)) 813 panic("bge_jfree: asked to free buffer that we don't manage!"); 814 815 s = splvm(); 816 entry = SLIST_FIRST(&sc->bge_jinuse_listhead); 817 if (entry == NULL) 818 panic("bge_jfree: buffer not in use!"); 819 entry->slot = i; 820 SLIST_REMOVE_HEAD(&sc->bge_jinuse_listhead, jpool_entries); 821 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, entry, jpool_entries); 822 823 if (__predict_true(m != NULL)) 824 pool_cache_put(mb_cache, m); 825 splx(s); 826 } 827 828 829 /* 830 * Intialize a standard receive ring descriptor. 831 */ 832 static int 833 bge_newbuf_std(struct bge_softc *sc, int i, struct mbuf *m, bus_dmamap_t dmamap) 834 { 835 struct mbuf *m_new = NULL; 836 struct bge_rx_bd *r; 837 int error; 838 839 if (dmamap == NULL) { 840 error = bus_dmamap_create(sc->bge_dmatag, MCLBYTES, 1, 841 MCLBYTES, 0, BUS_DMA_NOWAIT, &dmamap); 842 if (error != 0) 843 return error; 844 } 845 846 sc->bge_cdata.bge_rx_std_map[i] = dmamap; 847 848 if (m == NULL) { 849 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 850 if (m_new == NULL) { 851 return(ENOBUFS); 852 } 853 854 MCLGET(m_new, M_DONTWAIT); 855 if (!(m_new->m_flags & M_EXT)) { 856 m_freem(m_new); 857 return(ENOBUFS); 858 } 859 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 860 861 } else { 862 m_new = m; 863 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 864 m_new->m_data = m_new->m_ext.ext_buf; 865 } 866 if (!sc->bge_rx_alignment_bug) 867 m_adj(m_new, ETHER_ALIGN); 868 if (bus_dmamap_load_mbuf(sc->bge_dmatag, dmamap, m_new, 869 BUS_DMA_READ|BUS_DMA_NOWAIT)) 870 return(ENOBUFS); 871 bus_dmamap_sync(sc->bge_dmatag, dmamap, 0, dmamap->dm_mapsize, 872 BUS_DMASYNC_PREREAD); 873 874 sc->bge_cdata.bge_rx_std_chain[i] = m_new; 875 r = &sc->bge_rdata->bge_rx_std_ring[i]; 876 bge_set_hostaddr(&r->bge_addr, 877 dmamap->dm_segs[0].ds_addr); 878 r->bge_flags = BGE_RXBDFLAG_END; 879 r->bge_len = m_new->m_len; 880 r->bge_idx = i; 881 882 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 883 offsetof(struct bge_ring_data, bge_rx_std_ring) + 884 i * sizeof (struct bge_rx_bd), 885 sizeof (struct bge_rx_bd), 886 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 887 888 return(0); 889 } 890 891 /* 892 * Initialize a jumbo receive ring descriptor. This allocates 893 * a jumbo buffer from the pool managed internally by the driver. 894 */ 895 static int 896 bge_newbuf_jumbo(struct bge_softc *sc, int i, struct mbuf *m) 897 { 898 struct mbuf *m_new = NULL; 899 struct bge_rx_bd *r; 900 void *buf = NULL; 901 902 if (m == NULL) { 903 904 /* Allocate the mbuf. */ 905 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 906 if (m_new == NULL) { 907 return(ENOBUFS); 908 } 909 910 /* Allocate the jumbo buffer */ 911 buf = bge_jalloc(sc); 912 if (buf == NULL) { 913 m_freem(m_new); 914 aprint_error_dev(sc->bge_dev, 915 "jumbo allocation failed -- packet dropped!\n"); 916 return(ENOBUFS); 917 } 918 919 /* Attach the buffer to the mbuf. */ 920 m_new->m_len = m_new->m_pkthdr.len = BGE_JUMBO_FRAMELEN; 921 MEXTADD(m_new, buf, BGE_JUMBO_FRAMELEN, M_DEVBUF, 922 bge_jfree, sc); 923 m_new->m_flags |= M_EXT_RW; 924 } else { 925 m_new = m; 926 buf = m_new->m_data = m_new->m_ext.ext_buf; 927 m_new->m_ext.ext_size = BGE_JUMBO_FRAMELEN; 928 } 929 if (!sc->bge_rx_alignment_bug) 930 m_adj(m_new, ETHER_ALIGN); 931 bus_dmamap_sync(sc->bge_dmatag, sc->bge_cdata.bge_rx_jumbo_map, 932 mtod(m_new, char *) - (char *)sc->bge_cdata.bge_jumbo_buf, BGE_JLEN, 933 BUS_DMASYNC_PREREAD); 934 /* Set up the descriptor. */ 935 r = &sc->bge_rdata->bge_rx_jumbo_ring[i]; 936 sc->bge_cdata.bge_rx_jumbo_chain[i] = m_new; 937 bge_set_hostaddr(&r->bge_addr, BGE_JUMBO_DMA_ADDR(sc, m_new)); 938 r->bge_flags = BGE_RXBDFLAG_END|BGE_RXBDFLAG_JUMBO_RING; 939 r->bge_len = m_new->m_len; 940 r->bge_idx = i; 941 942 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 943 offsetof(struct bge_ring_data, bge_rx_jumbo_ring) + 944 i * sizeof (struct bge_rx_bd), 945 sizeof (struct bge_rx_bd), 946 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 947 948 return(0); 949 } 950 951 /* 952 * The standard receive ring has 512 entries in it. At 2K per mbuf cluster, 953 * that's 1MB or memory, which is a lot. For now, we fill only the first 954 * 256 ring entries and hope that our CPU is fast enough to keep up with 955 * the NIC. 956 */ 957 static int 958 bge_init_rx_ring_std(struct bge_softc *sc) 959 { 960 int i; 961 962 if (sc->bge_flags & BGE_RXRING_VALID) 963 return 0; 964 965 for (i = 0; i < BGE_SSLOTS; i++) { 966 if (bge_newbuf_std(sc, i, NULL, 0) == ENOBUFS) 967 return(ENOBUFS); 968 } 969 970 sc->bge_std = i - 1; 971 CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std); 972 973 sc->bge_flags |= BGE_RXRING_VALID; 974 975 return(0); 976 } 977 978 static void 979 bge_free_rx_ring_std(struct bge_softc *sc) 980 { 981 int i; 982 983 if (!(sc->bge_flags & BGE_RXRING_VALID)) 984 return; 985 986 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { 987 if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) { 988 m_freem(sc->bge_cdata.bge_rx_std_chain[i]); 989 sc->bge_cdata.bge_rx_std_chain[i] = NULL; 990 bus_dmamap_destroy(sc->bge_dmatag, 991 sc->bge_cdata.bge_rx_std_map[i]); 992 } 993 memset((char *)&sc->bge_rdata->bge_rx_std_ring[i], 0, 994 sizeof(struct bge_rx_bd)); 995 } 996 997 sc->bge_flags &= ~BGE_RXRING_VALID; 998 } 999 1000 static int 1001 bge_init_rx_ring_jumbo(struct bge_softc *sc) 1002 { 1003 int i; 1004 volatile struct bge_rcb *rcb; 1005 1006 if (sc->bge_flags & BGE_JUMBO_RXRING_VALID) 1007 return 0; 1008 1009 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 1010 if (bge_newbuf_jumbo(sc, i, NULL) == ENOBUFS) 1011 return(ENOBUFS); 1012 }; 1013 1014 sc->bge_jumbo = i - 1; 1015 sc->bge_flags |= BGE_JUMBO_RXRING_VALID; 1016 1017 rcb = &sc->bge_rdata->bge_info.bge_jumbo_rx_rcb; 1018 rcb->bge_maxlen_flags = 0; 1019 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 1020 1021 CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo); 1022 1023 return(0); 1024 } 1025 1026 static void 1027 bge_free_rx_ring_jumbo(struct bge_softc *sc) 1028 { 1029 int i; 1030 1031 if (!(sc->bge_flags & BGE_JUMBO_RXRING_VALID)) 1032 return; 1033 1034 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 1035 if (sc->bge_cdata.bge_rx_jumbo_chain[i] != NULL) { 1036 m_freem(sc->bge_cdata.bge_rx_jumbo_chain[i]); 1037 sc->bge_cdata.bge_rx_jumbo_chain[i] = NULL; 1038 } 1039 memset((char *)&sc->bge_rdata->bge_rx_jumbo_ring[i], 0, 1040 sizeof(struct bge_rx_bd)); 1041 } 1042 1043 sc->bge_flags &= ~BGE_JUMBO_RXRING_VALID; 1044 } 1045 1046 static void 1047 bge_free_tx_ring(struct bge_softc *sc) 1048 { 1049 int i, freed; 1050 struct txdmamap_pool_entry *dma; 1051 1052 if (!(sc->bge_flags & BGE_TXRING_VALID)) 1053 return; 1054 1055 freed = 0; 1056 1057 for (i = 0; i < BGE_TX_RING_CNT; i++) { 1058 if (sc->bge_cdata.bge_tx_chain[i] != NULL) { 1059 freed++; 1060 m_freem(sc->bge_cdata.bge_tx_chain[i]); 1061 sc->bge_cdata.bge_tx_chain[i] = NULL; 1062 SLIST_INSERT_HEAD(&sc->txdma_list, sc->txdma[i], 1063 link); 1064 sc->txdma[i] = 0; 1065 } 1066 memset((char *)&sc->bge_rdata->bge_tx_ring[i], 0, 1067 sizeof(struct bge_tx_bd)); 1068 } 1069 1070 while ((dma = SLIST_FIRST(&sc->txdma_list))) { 1071 SLIST_REMOVE_HEAD(&sc->txdma_list, link); 1072 bus_dmamap_destroy(sc->bge_dmatag, dma->dmamap); 1073 free(dma, M_DEVBUF); 1074 } 1075 1076 sc->bge_flags &= ~BGE_TXRING_VALID; 1077 } 1078 1079 static int 1080 bge_init_tx_ring(struct bge_softc *sc) 1081 { 1082 int i; 1083 bus_dmamap_t dmamap; 1084 struct txdmamap_pool_entry *dma; 1085 1086 if (sc->bge_flags & BGE_TXRING_VALID) 1087 return 0; 1088 1089 sc->bge_txcnt = 0; 1090 sc->bge_tx_saved_considx = 0; 1091 1092 /* Initialize transmit producer index for host-memory send ring. */ 1093 sc->bge_tx_prodidx = 0; 1094 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx); 1095 if (sc->bge_quirks & BGE_QUIRK_PRODUCER_BUG) /* 5700 b2 errata */ 1096 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx); 1097 1098 /* NIC-memory send ring not used; initialize to zero. */ 1099 CSR_WRITE_4(sc, BGE_MBX_TX_NIC_PROD0_LO, 0); 1100 if (sc->bge_quirks & BGE_QUIRK_PRODUCER_BUG) /* 5700 b2 errata */ 1101 CSR_WRITE_4(sc, BGE_MBX_TX_NIC_PROD0_LO, 0); 1102 1103 SLIST_INIT(&sc->txdma_list); 1104 for (i = 0; i < BGE_RSLOTS; i++) { 1105 if (bus_dmamap_create(sc->bge_dmatag, BGE_TXDMA_MAX, 1106 BGE_NTXSEG, ETHER_MAX_LEN_JUMBO, 0, BUS_DMA_NOWAIT, 1107 &dmamap)) 1108 return(ENOBUFS); 1109 if (dmamap == NULL) 1110 panic("dmamap NULL in bge_init_tx_ring"); 1111 dma = malloc(sizeof(*dma), M_DEVBUF, M_NOWAIT); 1112 if (dma == NULL) { 1113 aprint_error_dev(sc->bge_dev, 1114 "can't alloc txdmamap_pool_entry\n"); 1115 bus_dmamap_destroy(sc->bge_dmatag, dmamap); 1116 return (ENOMEM); 1117 } 1118 dma->dmamap = dmamap; 1119 SLIST_INSERT_HEAD(&sc->txdma_list, dma, link); 1120 } 1121 1122 sc->bge_flags |= BGE_TXRING_VALID; 1123 1124 return(0); 1125 } 1126 1127 static void 1128 bge_setmulti(struct bge_softc *sc) 1129 { 1130 struct ethercom *ac = &sc->ethercom; 1131 struct ifnet *ifp = &ac->ec_if; 1132 struct ether_multi *enm; 1133 struct ether_multistep step; 1134 u_int32_t hashes[4] = { 0, 0, 0, 0 }; 1135 u_int32_t h; 1136 int i; 1137 1138 if (ifp->if_flags & IFF_PROMISC) 1139 goto allmulti; 1140 1141 /* Now program new ones. */ 1142 ETHER_FIRST_MULTI(step, ac, enm); 1143 while (enm != NULL) { 1144 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1145 /* 1146 * We must listen to a range of multicast addresses. 1147 * For now, just accept all multicasts, rather than 1148 * trying to set only those filter bits needed to match 1149 * the range. (At this time, the only use of address 1150 * ranges is for IP multicast routing, for which the 1151 * range is big enough to require all bits set.) 1152 */ 1153 goto allmulti; 1154 } 1155 1156 h = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN); 1157 1158 /* Just want the 7 least-significant bits. */ 1159 h &= 0x7f; 1160 1161 hashes[(h & 0x60) >> 5] |= 1 << (h & 0x1F); 1162 ETHER_NEXT_MULTI(step, enm); 1163 } 1164 1165 ifp->if_flags &= ~IFF_ALLMULTI; 1166 goto setit; 1167 1168 allmulti: 1169 ifp->if_flags |= IFF_ALLMULTI; 1170 hashes[0] = hashes[1] = hashes[2] = hashes[3] = 0xffffffff; 1171 1172 setit: 1173 for (i = 0; i < 4; i++) 1174 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]); 1175 } 1176 1177 const int bge_swapbits[] = { 1178 0, 1179 BGE_MODECTL_BYTESWAP_DATA, 1180 BGE_MODECTL_WORDSWAP_DATA, 1181 BGE_MODECTL_BYTESWAP_NONFRAME, 1182 BGE_MODECTL_WORDSWAP_NONFRAME, 1183 1184 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA, 1185 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_BYTESWAP_NONFRAME, 1186 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_NONFRAME, 1187 1188 BGE_MODECTL_WORDSWAP_DATA|BGE_MODECTL_BYTESWAP_NONFRAME, 1189 BGE_MODECTL_WORDSWAP_DATA|BGE_MODECTL_WORDSWAP_NONFRAME, 1190 1191 BGE_MODECTL_BYTESWAP_NONFRAME|BGE_MODECTL_WORDSWAP_NONFRAME, 1192 1193 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA| 1194 BGE_MODECTL_BYTESWAP_NONFRAME, 1195 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA| 1196 BGE_MODECTL_WORDSWAP_NONFRAME, 1197 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_BYTESWAP_NONFRAME| 1198 BGE_MODECTL_WORDSWAP_NONFRAME, 1199 BGE_MODECTL_WORDSWAP_DATA|BGE_MODECTL_BYTESWAP_NONFRAME| 1200 BGE_MODECTL_WORDSWAP_NONFRAME, 1201 1202 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA| 1203 BGE_MODECTL_BYTESWAP_NONFRAME|BGE_MODECTL_WORDSWAP_NONFRAME, 1204 }; 1205 1206 int bge_swapindex = 0; 1207 1208 /* 1209 * Do endian, PCI and DMA initialization. Also check the on-board ROM 1210 * self-test results. 1211 */ 1212 static int 1213 bge_chipinit(struct bge_softc *sc) 1214 { 1215 u_int32_t cachesize; 1216 int i; 1217 u_int32_t dma_rw_ctl; 1218 1219 1220 /* Set endianness before we access any non-PCI registers. */ 1221 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MISC_CTL, 1222 BGE_INIT); 1223 1224 /* Set power state to D0. */ 1225 bge_setpowerstate(sc, 0); 1226 1227 /* 1228 * Check the 'ROM failed' bit on the RX CPU to see if 1229 * self-tests passed. 1230 */ 1231 if (CSR_READ_4(sc, BGE_RXCPU_MODE) & BGE_RXCPUMODE_ROMFAIL) { 1232 aprint_error_dev(sc->bge_dev, 1233 "RX CPU self-diagnostics failed!\n"); 1234 return(ENODEV); 1235 } 1236 1237 /* Clear the MAC control register */ 1238 CSR_WRITE_4(sc, BGE_MAC_MODE, 0); 1239 1240 /* 1241 * Clear the MAC statistics block in the NIC's 1242 * internal memory. 1243 */ 1244 for (i = BGE_STATS_BLOCK; 1245 i < BGE_STATS_BLOCK_END + 1; i += sizeof(u_int32_t)) 1246 BGE_MEMWIN_WRITE(sc->sc_pc, sc->sc_pcitag, i, 0); 1247 1248 for (i = BGE_STATUS_BLOCK; 1249 i < BGE_STATUS_BLOCK_END + 1; i += sizeof(u_int32_t)) 1250 BGE_MEMWIN_WRITE(sc->sc_pc, sc->sc_pcitag, i, 0); 1251 1252 /* Set up the PCI DMA control register. */ 1253 if (sc->bge_pcie) { 1254 u_int32_t device_ctl; 1255 1256 /* From FreeBSD */ 1257 DPRINTFN(4, ("(%s: PCI-Express DMA setting)\n", 1258 device_xname(sc->bge_dev))); 1259 dma_rw_ctl = (BGE_PCI_READ_CMD | BGE_PCI_WRITE_CMD | 1260 (0xf << BGE_PCIDMARWCTL_RD_WAT_SHIFT) | 1261 (0x2 << BGE_PCIDMARWCTL_WR_WAT_SHIFT)); 1262 1263 /* jonathan: alternative from Linux driver */ 1264 #define DMA_CTRL_WRITE_PCIE_H20MARK_128 0x00180000 1265 #define DMA_CTRL_WRITE_PCIE_H20MARK_256 0x00380000 1266 1267 dma_rw_ctl = 0x76000000; /* XXX XXX XXX */; 1268 device_ctl = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 1269 BGE_PCI_CONF_DEV_CTRL); 1270 aprint_debug_dev(sc->bge_dev, "pcie mode=0x%x\n", device_ctl); 1271 1272 if ((device_ctl & 0x00e0) && 0) { 1273 /* 1274 * XXX jonathan (at) NetBSD.org: 1275 * This clause is exactly what the Broadcom-supplied 1276 * Linux does; but given overall register programming 1277 * by if_bge(4), this larger DMA-write watermark 1278 * value causes bcm5721 chips to totally wedge. 1279 */ 1280 dma_rw_ctl |= BGE_PCIDMA_RWCTL_PCIE_WRITE_WATRMARK_256; 1281 } else { 1282 dma_rw_ctl |= BGE_PCIDMA_RWCTL_PCIE_WRITE_WATRMARK_128; 1283 } 1284 } else if (pci_conf_read(sc->sc_pc, sc->sc_pcitag,BGE_PCI_PCISTATE) & 1285 BGE_PCISTATE_PCI_BUSMODE) { 1286 /* Conventional PCI bus */ 1287 DPRINTFN(4, ("(%s: PCI 2.2 DMA setting)\n", 1288 device_xname(sc->bge_dev))); 1289 dma_rw_ctl = (BGE_PCI_READ_CMD | BGE_PCI_WRITE_CMD | 1290 (0x7 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) | 1291 (0x7 << BGE_PCIDMARWCTL_WR_WAT_SHIFT)); 1292 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 1293 dma_rw_ctl |= 0x0F; 1294 } 1295 } else { 1296 DPRINTFN(4, ("(:%s: PCI-X DMA setting)\n", 1297 device_xname(sc->bge_dev))); 1298 /* PCI-X bus */ 1299 dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD | 1300 (0x3 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) | 1301 (0x3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT) | 1302 (0x0F); 1303 /* 1304 * 5703 and 5704 need ONEDMA_AT_ONCE as a workaround 1305 * for hardware bugs, which means we should also clear 1306 * the low-order MINDMA bits. In addition, the 5704 1307 * uses a different encoding of read/write watermarks. 1308 */ 1309 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) { 1310 dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD | 1311 /* should be 0x1f0000 */ 1312 (0x7 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) | 1313 (0x3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT); 1314 dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE; 1315 } 1316 else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5703) { 1317 dma_rw_ctl &= 0xfffffff0; 1318 dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE; 1319 } 1320 else if (BGE_IS_5714_FAMILY(sc)) { 1321 dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD; 1322 dma_rw_ctl &= ~BGE_PCIDMARWCTL_ONEDMA_ATONCE; /* XXX */ 1323 /* XXX magic values, Broadcom-supplied Linux driver */ 1324 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5780) 1325 dma_rw_ctl |= (1 << 20) | (1 << 18) | 1326 BGE_PCIDMARWCTL_ONEDMA_ATONCE; 1327 else 1328 dma_rw_ctl |= (1<<20) | (1<<18) | (1 << 15); 1329 } 1330 } 1331 1332 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_DMA_RW_CTL, dma_rw_ctl); 1333 1334 /* 1335 * Set up general mode register. 1336 */ 1337 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS| 1338 BGE_MODECTL_MAC_ATTN_INTR|BGE_MODECTL_HOST_SEND_BDS| 1339 BGE_MODECTL_TX_NO_PHDR_CSUM|BGE_MODECTL_RX_NO_PHDR_CSUM); 1340 1341 /* Get cache line size. */ 1342 cachesize = pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CACHESZ); 1343 1344 /* 1345 * Avoid violating PCI spec on certain chip revs. 1346 */ 1347 if (pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CMD) & 1348 PCIM_CMD_MWIEN) { 1349 switch(cachesize) { 1350 case 1: 1351 PCI_SETBIT(sc->sc_pc, sc->sc_pcitag, BGE_PCI_DMA_RW_CTL, 1352 BGE_PCI_WRITE_BNDRY_16BYTES); 1353 break; 1354 case 2: 1355 PCI_SETBIT(sc->sc_pc, sc->sc_pcitag, BGE_PCI_DMA_RW_CTL, 1356 BGE_PCI_WRITE_BNDRY_32BYTES); 1357 break; 1358 case 4: 1359 PCI_SETBIT(sc->sc_pc, sc->sc_pcitag, BGE_PCI_DMA_RW_CTL, 1360 BGE_PCI_WRITE_BNDRY_64BYTES); 1361 break; 1362 case 8: 1363 PCI_SETBIT(sc->sc_pc, sc->sc_pcitag, BGE_PCI_DMA_RW_CTL, 1364 BGE_PCI_WRITE_BNDRY_128BYTES); 1365 break; 1366 case 16: 1367 PCI_SETBIT(sc->sc_pc, sc->sc_pcitag, BGE_PCI_DMA_RW_CTL, 1368 BGE_PCI_WRITE_BNDRY_256BYTES); 1369 break; 1370 case 32: 1371 PCI_SETBIT(sc->sc_pc, sc->sc_pcitag, BGE_PCI_DMA_RW_CTL, 1372 BGE_PCI_WRITE_BNDRY_512BYTES); 1373 break; 1374 case 64: 1375 PCI_SETBIT(sc->sc_pc, sc->sc_pcitag, BGE_PCI_DMA_RW_CTL, 1376 BGE_PCI_WRITE_BNDRY_1024BYTES); 1377 break; 1378 default: 1379 /* Disable PCI memory write and invalidate. */ 1380 #if 0 1381 if (bootverbose) 1382 aprint_error_dev(sc->bge_dev, 1383 "cache line size %d not supported " 1384 "disabling PCI MWI\n", 1385 #endif 1386 PCI_CLRBIT(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CMD, 1387 PCIM_CMD_MWIEN); 1388 break; 1389 } 1390 } 1391 1392 /* 1393 * Disable memory write invalidate. Apparently it is not supported 1394 * properly by these devices. 1395 */ 1396 PCI_CLRBIT(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CMD, PCIM_CMD_MWIEN); 1397 1398 1399 #ifdef __brokenalpha__ 1400 /* 1401 * Must insure that we do not cross an 8K (bytes) boundary 1402 * for DMA reads. Our highest limit is 1K bytes. This is a 1403 * restriction on some ALPHA platforms with early revision 1404 * 21174 PCI chipsets, such as the AlphaPC 164lx 1405 */ 1406 PCI_SETBIT(sc, BGE_PCI_DMA_RW_CTL, BGE_PCI_READ_BNDRY_1024, 4); 1407 #endif 1408 1409 /* Set the timer prescaler (always 66MHz) */ 1410 CSR_WRITE_4(sc, BGE_MISC_CFG, 65 << 1/*BGE_32BITTIME_66MHZ*/); 1411 1412 return(0); 1413 } 1414 1415 static int 1416 bge_blockinit(struct bge_softc *sc) 1417 { 1418 volatile struct bge_rcb *rcb; 1419 bus_size_t rcb_addr; 1420 int i; 1421 struct ifnet *ifp = &sc->ethercom.ec_if; 1422 bge_hostaddr taddr; 1423 1424 /* 1425 * Initialize the memory window pointer register so that 1426 * we can access the first 32K of internal NIC RAM. This will 1427 * allow us to set up the TX send ring RCBs and the RX return 1428 * ring RCBs, plus other things which live in NIC memory. 1429 */ 1430 1431 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_BASEADDR, 0); 1432 1433 /* Configure mbuf memory pool */ 1434 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 1435 if (sc->bge_extram) { 1436 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, 1437 BGE_EXT_SSRAM); 1438 if ((sc->bge_quirks & BGE_QUIRK_FEWER_MBUFS) != 0) 1439 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000); 1440 else 1441 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000); 1442 } else { 1443 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, 1444 BGE_BUFFPOOL_1); 1445 if ((sc->bge_quirks & BGE_QUIRK_FEWER_MBUFS) != 0) 1446 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000); 1447 else 1448 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000); 1449 } 1450 1451 /* Configure DMA resource pool */ 1452 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_BASEADDR, 1453 BGE_DMA_DESCRIPTORS); 1454 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LEN, 0x2000); 1455 } 1456 1457 /* Configure mbuf pool watermarks */ 1458 #ifdef ORIG_WPAUL_VALUES 1459 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 24); 1460 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 24); 1461 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 48); 1462 #else 1463 /* new broadcom docs strongly recommend these: */ 1464 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 1465 if (ifp->if_mtu > ETHER_MAX_LEN) { 1466 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x50); 1467 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x20); 1468 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60); 1469 } else { 1470 /* Values from Linux driver... */ 1471 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 304); 1472 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 152); 1473 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 380); 1474 } 1475 } else { 1476 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0); 1477 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x10); 1478 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60); 1479 } 1480 #endif 1481 1482 /* Configure DMA resource watermarks */ 1483 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5); 1484 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10); 1485 1486 /* Enable buffer manager */ 1487 CSR_WRITE_4(sc, BGE_BMAN_MODE, 1488 BGE_BMANMODE_ENABLE|BGE_BMANMODE_LOMBUF_ATTN); 1489 1490 /* Poll for buffer manager start indication */ 1491 for (i = 0; i < BGE_TIMEOUT; i++) { 1492 if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE) 1493 break; 1494 DELAY(10); 1495 } 1496 1497 if (i == BGE_TIMEOUT) { 1498 aprint_error_dev(sc->bge_dev, 1499 "buffer manager failed to start\n"); 1500 return(ENXIO); 1501 } 1502 1503 /* Enable flow-through queues */ 1504 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 1505 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 1506 1507 /* Wait until queue initialization is complete */ 1508 for (i = 0; i < BGE_TIMEOUT; i++) { 1509 if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0) 1510 break; 1511 DELAY(10); 1512 } 1513 1514 if (i == BGE_TIMEOUT) { 1515 aprint_error_dev(sc->bge_dev, 1516 "flow-through queue init failed\n"); 1517 return(ENXIO); 1518 } 1519 1520 /* Initialize the standard RX ring control block */ 1521 rcb = &sc->bge_rdata->bge_info.bge_std_rx_rcb; 1522 bge_set_hostaddr(&rcb->bge_hostaddr, 1523 BGE_RING_DMA_ADDR(sc, bge_rx_std_ring)); 1524 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 1525 rcb->bge_maxlen_flags = 1526 BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 0); 1527 } else { 1528 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(512, 0); 1529 } 1530 if (sc->bge_extram) 1531 rcb->bge_nicaddr = BGE_EXT_STD_RX_RINGS; 1532 else 1533 rcb->bge_nicaddr = BGE_STD_RX_RINGS; 1534 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcb->bge_hostaddr.bge_addr_hi); 1535 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcb->bge_hostaddr.bge_addr_lo); 1536 CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 1537 CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcb->bge_nicaddr); 1538 1539 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 1540 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT; 1541 } else { 1542 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT_5705; 1543 } 1544 1545 /* 1546 * Initialize the jumbo RX ring control block 1547 * We set the 'ring disabled' bit in the flags 1548 * field until we're actually ready to start 1549 * using this ring (i.e. once we set the MTU 1550 * high enough to require it). 1551 */ 1552 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 1553 rcb = &sc->bge_rdata->bge_info.bge_jumbo_rx_rcb; 1554 bge_set_hostaddr(&rcb->bge_hostaddr, 1555 BGE_RING_DMA_ADDR(sc, bge_rx_jumbo_ring)); 1556 rcb->bge_maxlen_flags = 1557 BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 1558 BGE_RCB_FLAG_RING_DISABLED); 1559 if (sc->bge_extram) 1560 rcb->bge_nicaddr = BGE_EXT_JUMBO_RX_RINGS; 1561 else 1562 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS; 1563 1564 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI, 1565 rcb->bge_hostaddr.bge_addr_hi); 1566 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO, 1567 rcb->bge_hostaddr.bge_addr_lo); 1568 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, 1569 rcb->bge_maxlen_flags); 1570 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcb->bge_nicaddr); 1571 1572 /* Set up dummy disabled mini ring RCB */ 1573 rcb = &sc->bge_rdata->bge_info.bge_mini_rx_rcb; 1574 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0, 1575 BGE_RCB_FLAG_RING_DISABLED); 1576 CSR_WRITE_4(sc, BGE_RX_MINI_RCB_MAXLEN_FLAGS, 1577 rcb->bge_maxlen_flags); 1578 1579 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 1580 offsetof(struct bge_ring_data, bge_info), 1581 sizeof (struct bge_gib), 1582 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1583 } 1584 1585 /* 1586 * Set the BD ring replenish thresholds. The recommended 1587 * values are 1/8th the number of descriptors allocated to 1588 * each ring. 1589 */ 1590 i = BGE_STD_RX_RING_CNT / 8; 1591 1592 /* 1593 * Use a value of 8 for the following chips to workaround HW errata. 1594 * Some of these chips have been added based on empirical 1595 * evidence (they don't work unless this is done). 1596 */ 1597 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5750 || 1598 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5752 || 1599 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5755 || 1600 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5787) 1601 i = 8; 1602 1603 CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, i); 1604 CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH, BGE_JUMBO_RX_RING_CNT/8); 1605 1606 /* 1607 * Disable all unused send rings by setting the 'ring disabled' 1608 * bit in the flags field of all the TX send ring control blocks. 1609 * These are located in NIC memory. 1610 */ 1611 rcb_addr = BGE_MEMWIN_START + BGE_SEND_RING_RCB; 1612 for (i = 0; i < BGE_TX_RINGS_EXTSSRAM_MAX; i++) { 1613 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 1614 BGE_RCB_MAXLEN_FLAGS(0,BGE_RCB_FLAG_RING_DISABLED)); 1615 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 0); 1616 rcb_addr += sizeof(struct bge_rcb); 1617 } 1618 1619 /* Configure TX RCB 0 (we use only the first ring) */ 1620 rcb_addr = BGE_MEMWIN_START + BGE_SEND_RING_RCB; 1621 bge_set_hostaddr(&taddr, BGE_RING_DMA_ADDR(sc, bge_tx_ring)); 1622 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi); 1623 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo); 1624 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 1625 BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT)); 1626 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 1627 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 1628 BGE_RCB_MAXLEN_FLAGS(BGE_TX_RING_CNT, 0)); 1629 } 1630 1631 /* Disable all unused RX return rings */ 1632 rcb_addr = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB; 1633 for (i = 0; i < BGE_RX_RINGS_MAX; i++) { 1634 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_hi, 0); 1635 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_lo, 0); 1636 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 1637 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 1638 BGE_RCB_FLAG_RING_DISABLED)); 1639 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 0); 1640 CSR_WRITE_4(sc, BGE_MBX_RX_CONS0_LO + 1641 (i * (sizeof(u_int64_t))), 0); 1642 rcb_addr += sizeof(struct bge_rcb); 1643 } 1644 1645 /* Initialize RX ring indexes */ 1646 CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, 0); 1647 CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0); 1648 CSR_WRITE_4(sc, BGE_MBX_RX_MINI_PROD_LO, 0); 1649 1650 /* 1651 * Set up RX return ring 0 1652 * Note that the NIC address for RX return rings is 0x00000000. 1653 * The return rings live entirely within the host, so the 1654 * nicaddr field in the RCB isn't used. 1655 */ 1656 rcb_addr = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB; 1657 bge_set_hostaddr(&taddr, BGE_RING_DMA_ADDR(sc, bge_rx_return_ring)); 1658 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi); 1659 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo); 1660 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 0x00000000); 1661 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 1662 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 0)); 1663 1664 /* Set random backoff seed for TX */ 1665 CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF, 1666 CLLADDR(ifp->if_sadl)[0] + CLLADDR(ifp->if_sadl)[1] + 1667 CLLADDR(ifp->if_sadl)[2] + CLLADDR(ifp->if_sadl)[3] + 1668 CLLADDR(ifp->if_sadl)[4] + CLLADDR(ifp->if_sadl)[5] + 1669 BGE_TX_BACKOFF_SEED_MASK); 1670 1671 /* Set inter-packet gap */ 1672 CSR_WRITE_4(sc, BGE_TX_LENGTHS, 0x2620); 1673 1674 /* 1675 * Specify which ring to use for packets that don't match 1676 * any RX rules. 1677 */ 1678 CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08); 1679 1680 /* 1681 * Configure number of RX lists. One interrupt distribution 1682 * list, sixteen active lists, one bad frames class. 1683 */ 1684 CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181); 1685 1686 /* Inialize RX list placement stats mask. */ 1687 CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF); 1688 CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1); 1689 1690 /* Disable host coalescing until we get it set up */ 1691 CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000); 1692 1693 /* Poll to make sure it's shut down. */ 1694 for (i = 0; i < BGE_TIMEOUT; i++) { 1695 if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE)) 1696 break; 1697 DELAY(10); 1698 } 1699 1700 if (i == BGE_TIMEOUT) { 1701 aprint_error_dev(sc->bge_dev, 1702 "host coalescing engine failed to idle\n"); 1703 return(ENXIO); 1704 } 1705 1706 /* Set up host coalescing defaults */ 1707 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bge_rx_coal_ticks); 1708 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bge_tx_coal_ticks); 1709 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bge_rx_max_coal_bds); 1710 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bge_tx_max_coal_bds); 1711 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 1712 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT, 0); 1713 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT, 0); 1714 } 1715 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 0); 1716 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 0); 1717 1718 /* Set up address of statistics block */ 1719 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 1720 bge_set_hostaddr(&taddr, 1721 BGE_RING_DMA_ADDR(sc, bge_info.bge_stats)); 1722 CSR_WRITE_4(sc, BGE_HCC_STATS_TICKS, sc->bge_stat_ticks); 1723 CSR_WRITE_4(sc, BGE_HCC_STATS_BASEADDR, BGE_STATS_BLOCK); 1724 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_HI, taddr.bge_addr_hi); 1725 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_LO, taddr.bge_addr_lo); 1726 } 1727 1728 /* Set up address of status block */ 1729 bge_set_hostaddr(&taddr, BGE_RING_DMA_ADDR(sc, bge_status_block)); 1730 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_BASEADDR, BGE_STATUS_BLOCK); 1731 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI, taddr.bge_addr_hi); 1732 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO, taddr.bge_addr_lo); 1733 sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx = 0; 1734 sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx = 0; 1735 1736 /* Turn on host coalescing state machine */ 1737 CSR_WRITE_4(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE); 1738 1739 /* Turn on RX BD completion state machine and enable attentions */ 1740 CSR_WRITE_4(sc, BGE_RBDC_MODE, 1741 BGE_RBDCMODE_ENABLE|BGE_RBDCMODE_ATTN); 1742 1743 /* Turn on RX list placement state machine */ 1744 CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 1745 1746 /* Turn on RX list selector state machine. */ 1747 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 1748 CSR_WRITE_4(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 1749 } 1750 1751 /* Turn on DMA, clear stats */ 1752 CSR_WRITE_4(sc, BGE_MAC_MODE, BGE_MACMODE_TXDMA_ENB| 1753 BGE_MACMODE_RXDMA_ENB|BGE_MACMODE_RX_STATS_CLEAR| 1754 BGE_MACMODE_TX_STATS_CLEAR|BGE_MACMODE_RX_STATS_ENB| 1755 BGE_MACMODE_TX_STATS_ENB|BGE_MACMODE_FRMHDR_DMA_ENB| 1756 (sc->bge_tbi ? BGE_PORTMODE_TBI : BGE_PORTMODE_MII)); 1757 1758 /* Set misc. local control, enable interrupts on attentions */ 1759 sc->bge_local_ctrl_reg = BGE_MLC_INTR_ONATTN | BGE_MLC_AUTO_EEPROM; 1760 1761 #ifdef notdef 1762 /* Assert GPIO pins for PHY reset */ 1763 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUT0| 1764 BGE_MLC_MISCIO_OUT1|BGE_MLC_MISCIO_OUT2); 1765 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUTEN0| 1766 BGE_MLC_MISCIO_OUTEN1|BGE_MLC_MISCIO_OUTEN2); 1767 #endif 1768 1769 #if defined(not_quite_yet) 1770 /* Linux driver enables enable gpio pin #1 on 5700s */ 1771 if (sc->bge_chipid == BGE_CHIPID_BCM5700) { 1772 sc->bge_local_ctrl_reg |= 1773 (BGE_MLC_MISCIO_OUT1|BGE_MLC_MISCIO_OUTEN1); 1774 } 1775 #endif 1776 CSR_WRITE_4(sc, BGE_MISC_LOCAL_CTL, sc->bge_local_ctrl_reg); 1777 1778 /* Turn on DMA completion state machine */ 1779 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 1780 CSR_WRITE_4(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 1781 } 1782 1783 /* Turn on write DMA state machine */ 1784 { 1785 uint32_t bge_wdma_mode = 1786 BGE_WDMAMODE_ENABLE|BGE_WDMAMODE_ALL_ATTNS; 1787 1788 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5755 || 1789 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5787) 1790 /* Enable host coalescing bug fix; see Linux tg3.c */ 1791 bge_wdma_mode |= (1 << 29); 1792 1793 CSR_WRITE_4(sc, BGE_WDMA_MODE, bge_wdma_mode); 1794 } 1795 1796 /* Turn on read DMA state machine */ 1797 { 1798 uint32_t dma_read_modebits; 1799 1800 dma_read_modebits = 1801 BGE_RDMAMODE_ENABLE | BGE_RDMAMODE_ALL_ATTNS; 1802 1803 if (sc->bge_pcie && 0) { 1804 dma_read_modebits |= BGE_RDMA_MODE_FIFO_LONG_BURST; 1805 } else if ((sc->bge_quirks & BGE_QUIRK_5705_CORE)) { 1806 dma_read_modebits |= BGE_RDMA_MODE_FIFO_SIZE_128; 1807 } 1808 1809 /* XXX broadcom-supplied linux driver; undocumented */ 1810 if (BGE_IS_5750_OR_BEYOND(sc)) { 1811 /* 1812 * XXX: magic values. 1813 * From Broadcom-supplied Linux driver; apparently 1814 * required to workaround a DMA bug affecting TSO 1815 * on bcm575x/bcm5721? 1816 */ 1817 dma_read_modebits |= (1 << 27); 1818 } 1819 CSR_WRITE_4(sc, BGE_RDMA_MODE, dma_read_modebits); 1820 } 1821 1822 /* Turn on RX data completion state machine */ 1823 CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 1824 1825 /* Turn on RX BD initiator state machine */ 1826 CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 1827 1828 /* Turn on RX data and RX BD initiator state machine */ 1829 CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE); 1830 1831 /* Turn on Mbuf cluster free state machine */ 1832 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 1833 CSR_WRITE_4(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 1834 } 1835 1836 /* Turn on send BD completion state machine */ 1837 CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 1838 1839 /* Turn on send data completion state machine */ 1840 CSR_WRITE_4(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE); 1841 1842 /* Turn on send data initiator state machine */ 1843 if (BGE_IS_5750_OR_BEYOND(sc)) { 1844 /* XXX: magic value from Linux driver */ 1845 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE | 0x08); 1846 } else { 1847 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 1848 } 1849 1850 /* Turn on send BD initiator state machine */ 1851 CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 1852 1853 /* Turn on send BD selector state machine */ 1854 CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 1855 1856 CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF); 1857 CSR_WRITE_4(sc, BGE_SDI_STATS_CTL, 1858 BGE_SDISTATSCTL_ENABLE|BGE_SDISTATSCTL_FASTER); 1859 1860 /* ack/clear link change events */ 1861 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED| 1862 BGE_MACSTAT_CFG_CHANGED); 1863 CSR_WRITE_4(sc, BGE_MI_STS, 0); 1864 1865 /* Enable PHY auto polling (for MII/GMII only) */ 1866 if (sc->bge_tbi) { 1867 CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK); 1868 } else { 1869 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL|10<<16); 1870 if (sc->bge_quirks & BGE_QUIRK_LINK_STATE_BROKEN) 1871 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, 1872 BGE_EVTENB_MI_INTERRUPT); 1873 } 1874 1875 /* Enable link state change attentions. */ 1876 BGE_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED); 1877 1878 return(0); 1879 } 1880 1881 static const struct bge_revision { 1882 uint32_t br_chipid; 1883 uint32_t br_quirks; 1884 const char *br_name; 1885 } bge_revisions[] = { 1886 { BGE_CHIPID_BCM5700_A0, 1887 BGE_QUIRK_LINK_STATE_BROKEN, 1888 "BCM5700 A0" }, 1889 1890 { BGE_CHIPID_BCM5700_A1, 1891 BGE_QUIRK_LINK_STATE_BROKEN, 1892 "BCM5700 A1" }, 1893 1894 { BGE_CHIPID_BCM5700_B0, 1895 BGE_QUIRK_LINK_STATE_BROKEN|BGE_QUIRK_CSUM_BROKEN|BGE_QUIRK_5700_COMMON, 1896 "BCM5700 B0" }, 1897 1898 { BGE_CHIPID_BCM5700_B1, 1899 BGE_QUIRK_LINK_STATE_BROKEN|BGE_QUIRK_5700_COMMON, 1900 "BCM5700 B1" }, 1901 1902 { BGE_CHIPID_BCM5700_B2, 1903 BGE_QUIRK_LINK_STATE_BROKEN|BGE_QUIRK_5700_COMMON, 1904 "BCM5700 B2" }, 1905 1906 { BGE_CHIPID_BCM5700_B3, 1907 BGE_QUIRK_LINK_STATE_BROKEN|BGE_QUIRK_5700_COMMON, 1908 "BCM5700 B3" }, 1909 1910 /* This is treated like a BCM5700 Bx */ 1911 { BGE_CHIPID_BCM5700_ALTIMA, 1912 BGE_QUIRK_LINK_STATE_BROKEN|BGE_QUIRK_5700_COMMON, 1913 "BCM5700 Altima" }, 1914 1915 { BGE_CHIPID_BCM5700_C0, 1916 0, 1917 "BCM5700 C0" }, 1918 1919 { BGE_CHIPID_BCM5701_A0, 1920 0, /*XXX really, just not known */ 1921 "BCM5701 A0" }, 1922 1923 { BGE_CHIPID_BCM5701_B0, 1924 BGE_QUIRK_PCIX_DMA_ALIGN_BUG, 1925 "BCM5701 B0" }, 1926 1927 { BGE_CHIPID_BCM5701_B2, 1928 BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_PCIX_DMA_ALIGN_BUG, 1929 "BCM5701 B2" }, 1930 1931 { BGE_CHIPID_BCM5701_B5, 1932 BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_PCIX_DMA_ALIGN_BUG, 1933 "BCM5701 B5" }, 1934 1935 { BGE_CHIPID_BCM5703_A0, 1936 0, 1937 "BCM5703 A0" }, 1938 1939 { BGE_CHIPID_BCM5703_A1, 1940 0, 1941 "BCM5703 A1" }, 1942 1943 { BGE_CHIPID_BCM5703_A2, 1944 BGE_QUIRK_ONLY_PHY_1, 1945 "BCM5703 A2" }, 1946 1947 { BGE_CHIPID_BCM5703_A3, 1948 BGE_QUIRK_ONLY_PHY_1, 1949 "BCM5703 A3" }, 1950 1951 { BGE_CHIPID_BCM5703_B0, 1952 BGE_QUIRK_ONLY_PHY_1, 1953 "BCM5703 B0" }, 1954 1955 { BGE_CHIPID_BCM5704_A0, 1956 BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_FEWER_MBUFS, 1957 "BCM5704 A0" }, 1958 1959 { BGE_CHIPID_BCM5704_A1, 1960 BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_FEWER_MBUFS, 1961 "BCM5704 A1" }, 1962 1963 { BGE_CHIPID_BCM5704_A2, 1964 BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_FEWER_MBUFS, 1965 "BCM5704 A2" }, 1966 1967 { BGE_CHIPID_BCM5704_A3, 1968 BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_FEWER_MBUFS, 1969 "BCM5704 A3" }, 1970 1971 { BGE_CHIPID_BCM5705_A0, 1972 BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_5705_CORE, 1973 "BCM5705 A0" }, 1974 1975 { BGE_CHIPID_BCM5705_A1, 1976 BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_5705_CORE, 1977 "BCM5705 A1" }, 1978 1979 { BGE_CHIPID_BCM5705_A2, 1980 BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_5705_CORE, 1981 "BCM5705 A2" }, 1982 1983 { BGE_CHIPID_BCM5705_A3, 1984 BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_5705_CORE, 1985 "BCM5705 A3" }, 1986 1987 { BGE_CHIPID_BCM5750_A0, 1988 BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_5705_CORE, 1989 "BCM5750 A0" }, 1990 1991 { BGE_CHIPID_BCM5750_A1, 1992 BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_5705_CORE, 1993 "BCM5750 A1" }, 1994 1995 { BGE_CHIPID_BCM5751_A1, 1996 BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_5705_CORE, 1997 "BCM5751 A1" }, 1998 1999 { BGE_CHIPID_BCM5752_A0, 2000 BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_5705_CORE, 2001 "BCM5752 A0" }, 2002 2003 { BGE_CHIPID_BCM5752_A1, 2004 BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_5705_CORE, 2005 "BCM5752 A1" }, 2006 2007 { BGE_CHIPID_BCM5752_A2, 2008 BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_5705_CORE, 2009 "BCM5752 A2" }, 2010 2011 { BGE_CHIPID_BCM5755_A0, 2012 BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_5705_CORE, 2013 "BCM5755 A0" }, 2014 2015 { BGE_CHIPID_BCM5755_A1, 2016 BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_5705_CORE, 2017 "BCM5755 A1" }, 2018 2019 { BGE_CHIPID_BCM5755_A2, 2020 BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_5705_CORE, 2021 "BCM5755 A2" }, 2022 2023 { BGE_CHIPID_BCM5755_C0, 2024 BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_5705_CORE, 2025 "BCM5755 C0" }, 2026 2027 { BGE_CHIPID_BCM5787_A0, 2028 BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_5705_CORE, 2029 "BCM5754/5787 A0" }, 2030 2031 { BGE_CHIPID_BCM5787_A1, 2032 BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_5705_CORE, 2033 "BCM5754/5787 A1" }, 2034 2035 { BGE_CHIPID_BCM5787_A2, 2036 BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_5705_CORE, 2037 "BCM5754/5787 A2" }, 2038 2039 { 0, 0, NULL } 2040 }; 2041 2042 /* 2043 * Some defaults for major revisions, so that newer steppings 2044 * that we don't know about have a shot at working. 2045 */ 2046 static const struct bge_revision bge_majorrevs[] = { 2047 { BGE_ASICREV_BCM5700, 2048 BGE_QUIRK_LINK_STATE_BROKEN, 2049 "unknown BCM5700" }, 2050 2051 { BGE_ASICREV_BCM5701, 2052 BGE_QUIRK_PCIX_DMA_ALIGN_BUG, 2053 "unknown BCM5701" }, 2054 2055 { BGE_ASICREV_BCM5703, 2056 0, 2057 "unknown BCM5703" }, 2058 2059 { BGE_ASICREV_BCM5704, 2060 BGE_QUIRK_ONLY_PHY_1, 2061 "unknown BCM5704" }, 2062 2063 { BGE_ASICREV_BCM5705, 2064 BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_5705_CORE, 2065 "unknown BCM5705" }, 2066 2067 { BGE_ASICREV_BCM5750, 2068 BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_5705_CORE, 2069 "unknown BCM575x family" }, 2070 2071 { BGE_ASICREV_BCM5714_A0, 2072 BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_5705_CORE, 2073 "unknown BCM5714" }, 2074 2075 { BGE_ASICREV_BCM5714, 2076 BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_5705_CORE, 2077 "unknown BCM5714" }, 2078 2079 { BGE_ASICREV_BCM5752, 2080 BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_5705_CORE, 2081 "unknown BCM5752 family" }, 2082 2083 { BGE_ASICREV_BCM5755, 2084 BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_5705_CORE, 2085 "unknown BCM5755" }, 2086 2087 { BGE_ASICREV_BCM5780, 2088 BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_5705_CORE, 2089 "unknown BCM5780" }, 2090 2091 { BGE_ASICREV_BCM5787, 2092 BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_5705_CORE, 2093 "unknown BCM5787" }, 2094 2095 { 0, 2096 0, 2097 NULL } 2098 }; 2099 2100 2101 static const struct bge_revision * 2102 bge_lookup_rev(uint32_t chipid) 2103 { 2104 const struct bge_revision *br; 2105 2106 for (br = bge_revisions; br->br_name != NULL; br++) { 2107 if (br->br_chipid == chipid) 2108 return (br); 2109 } 2110 2111 for (br = bge_majorrevs; br->br_name != NULL; br++) { 2112 if (br->br_chipid == BGE_ASICREV(chipid)) 2113 return (br); 2114 } 2115 2116 return (NULL); 2117 } 2118 2119 static const struct bge_product { 2120 pci_vendor_id_t bp_vendor; 2121 pci_product_id_t bp_product; 2122 const char *bp_name; 2123 } bge_products[] = { 2124 /* 2125 * The BCM5700 documentation seems to indicate that the hardware 2126 * still has the Alteon vendor ID burned into it, though it 2127 * should always be overridden by the value in the EEPROM. We'll 2128 * check for it anyway. 2129 */ 2130 { PCI_VENDOR_ALTEON, 2131 PCI_PRODUCT_ALTEON_BCM5700, 2132 "Broadcom BCM5700 Gigabit Ethernet", 2133 }, 2134 { PCI_VENDOR_ALTEON, 2135 PCI_PRODUCT_ALTEON_BCM5701, 2136 "Broadcom BCM5701 Gigabit Ethernet", 2137 }, 2138 2139 { PCI_VENDOR_ALTIMA, 2140 PCI_PRODUCT_ALTIMA_AC1000, 2141 "Altima AC1000 Gigabit Ethernet", 2142 }, 2143 { PCI_VENDOR_ALTIMA, 2144 PCI_PRODUCT_ALTIMA_AC1001, 2145 "Altima AC1001 Gigabit Ethernet", 2146 }, 2147 { PCI_VENDOR_ALTIMA, 2148 PCI_PRODUCT_ALTIMA_AC9100, 2149 "Altima AC9100 Gigabit Ethernet", 2150 }, 2151 2152 { PCI_VENDOR_BROADCOM, 2153 PCI_PRODUCT_BROADCOM_BCM5700, 2154 "Broadcom BCM5700 Gigabit Ethernet", 2155 }, 2156 { PCI_VENDOR_BROADCOM, 2157 PCI_PRODUCT_BROADCOM_BCM5701, 2158 "Broadcom BCM5701 Gigabit Ethernet", 2159 }, 2160 { PCI_VENDOR_BROADCOM, 2161 PCI_PRODUCT_BROADCOM_BCM5702, 2162 "Broadcom BCM5702 Gigabit Ethernet", 2163 }, 2164 { PCI_VENDOR_BROADCOM, 2165 PCI_PRODUCT_BROADCOM_BCM5702X, 2166 "Broadcom BCM5702X Gigabit Ethernet" }, 2167 2168 { PCI_VENDOR_BROADCOM, 2169 PCI_PRODUCT_BROADCOM_BCM5703, 2170 "Broadcom BCM5703 Gigabit Ethernet", 2171 }, 2172 { PCI_VENDOR_BROADCOM, 2173 PCI_PRODUCT_BROADCOM_BCM5703X, 2174 "Broadcom BCM5703X Gigabit Ethernet", 2175 }, 2176 { PCI_VENDOR_BROADCOM, 2177 PCI_PRODUCT_BROADCOM_BCM5703_ALT, 2178 "Broadcom BCM5703 Gigabit Ethernet", 2179 }, 2180 2181 { PCI_VENDOR_BROADCOM, 2182 PCI_PRODUCT_BROADCOM_BCM5704C, 2183 "Broadcom BCM5704C Dual Gigabit Ethernet", 2184 }, 2185 { PCI_VENDOR_BROADCOM, 2186 PCI_PRODUCT_BROADCOM_BCM5704S, 2187 "Broadcom BCM5704S Dual Gigabit Ethernet", 2188 }, 2189 2190 { PCI_VENDOR_BROADCOM, 2191 PCI_PRODUCT_BROADCOM_BCM5705, 2192 "Broadcom BCM5705 Gigabit Ethernet", 2193 }, 2194 { PCI_VENDOR_BROADCOM, 2195 PCI_PRODUCT_BROADCOM_BCM5705K, 2196 "Broadcom BCM5705K Gigabit Ethernet", 2197 }, 2198 { PCI_VENDOR_BROADCOM, 2199 PCI_PRODUCT_BROADCOM_BCM5705M, 2200 "Broadcom BCM5705M Gigabit Ethernet", 2201 }, 2202 { PCI_VENDOR_BROADCOM, 2203 PCI_PRODUCT_BROADCOM_BCM5705M_ALT, 2204 "Broadcom BCM5705M Gigabit Ethernet", 2205 }, 2206 2207 { PCI_VENDOR_BROADCOM, 2208 PCI_PRODUCT_BROADCOM_BCM5714, 2209 "Broadcom BCM5714/5715 Gigabit Ethernet", 2210 }, 2211 { PCI_VENDOR_BROADCOM, 2212 PCI_PRODUCT_BROADCOM_BCM5715, 2213 "Broadcom BCM5714/5715 Gigabit Ethernet", 2214 }, 2215 { PCI_VENDOR_BROADCOM, 2216 PCI_PRODUCT_BROADCOM_BCM5789, 2217 "Broadcom BCM5789 Gigabit Ethernet", 2218 }, 2219 2220 { PCI_VENDOR_BROADCOM, 2221 PCI_PRODUCT_BROADCOM_BCM5721, 2222 "Broadcom BCM5721 Gigabit Ethernet", 2223 }, 2224 2225 { PCI_VENDOR_BROADCOM, 2226 PCI_PRODUCT_BROADCOM_BCM5722, 2227 "Broadcom BCM5722 Gigabit Ethernet", 2228 }, 2229 2230 { PCI_VENDOR_BROADCOM, 2231 PCI_PRODUCT_BROADCOM_BCM5750, 2232 "Broadcom BCM5750 Gigabit Ethernet", 2233 }, 2234 2235 { PCI_VENDOR_BROADCOM, 2236 PCI_PRODUCT_BROADCOM_BCM5750M, 2237 "Broadcom BCM5750M Gigabit Ethernet", 2238 }, 2239 2240 { PCI_VENDOR_BROADCOM, 2241 PCI_PRODUCT_BROADCOM_BCM5751, 2242 "Broadcom BCM5751 Gigabit Ethernet", 2243 }, 2244 2245 { PCI_VENDOR_BROADCOM, 2246 PCI_PRODUCT_BROADCOM_BCM5751M, 2247 "Broadcom BCM5751M Gigabit Ethernet", 2248 }, 2249 2250 { PCI_VENDOR_BROADCOM, 2251 PCI_PRODUCT_BROADCOM_BCM5752, 2252 "Broadcom BCM5752 Gigabit Ethernet", 2253 }, 2254 2255 { PCI_VENDOR_BROADCOM, 2256 PCI_PRODUCT_BROADCOM_BCM5752M, 2257 "Broadcom BCM5752M Gigabit Ethernet", 2258 }, 2259 2260 { PCI_VENDOR_BROADCOM, 2261 PCI_PRODUCT_BROADCOM_BCM5753, 2262 "Broadcom BCM5753 Gigabit Ethernet", 2263 }, 2264 2265 { PCI_VENDOR_BROADCOM, 2266 PCI_PRODUCT_BROADCOM_BCM5753M, 2267 "Broadcom BCM5753M Gigabit Ethernet", 2268 }, 2269 2270 { PCI_VENDOR_BROADCOM, 2271 PCI_PRODUCT_BROADCOM_BCM5754, 2272 "Broadcom BCM5754 Gigabit Ethernet", 2273 }, 2274 2275 { PCI_VENDOR_BROADCOM, 2276 PCI_PRODUCT_BROADCOM_BCM5754M, 2277 "Broadcom BCM5754M Gigabit Ethernet", 2278 }, 2279 2280 { PCI_VENDOR_BROADCOM, 2281 PCI_PRODUCT_BROADCOM_BCM5755, 2282 "Broadcom BCM5755 Gigabit Ethernet", 2283 }, 2284 2285 { PCI_VENDOR_BROADCOM, 2286 PCI_PRODUCT_BROADCOM_BCM5755M, 2287 "Broadcom BCM5755M Gigabit Ethernet", 2288 }, 2289 2290 { PCI_VENDOR_BROADCOM, 2291 PCI_PRODUCT_BROADCOM_BCM5780, 2292 "Broadcom BCM5780 Gigabit Ethernet", 2293 }, 2294 2295 { PCI_VENDOR_BROADCOM, 2296 PCI_PRODUCT_BROADCOM_BCM5780S, 2297 "Broadcom BCM5780S Gigabit Ethernet", 2298 }, 2299 2300 { PCI_VENDOR_BROADCOM, 2301 PCI_PRODUCT_BROADCOM_BCM5782, 2302 "Broadcom BCM5782 Gigabit Ethernet", 2303 }, 2304 2305 { PCI_VENDOR_BROADCOM, 2306 PCI_PRODUCT_BROADCOM_BCM5786, 2307 "Broadcom BCM5786 Gigabit Ethernet", 2308 }, 2309 2310 { PCI_VENDOR_BROADCOM, 2311 PCI_PRODUCT_BROADCOM_BCM5787, 2312 "Broadcom BCM5787 Gigabit Ethernet", 2313 }, 2314 2315 { PCI_VENDOR_BROADCOM, 2316 PCI_PRODUCT_BROADCOM_BCM5787M, 2317 "Broadcom BCM5787M Gigabit Ethernet", 2318 }, 2319 2320 { PCI_VENDOR_BROADCOM, 2321 PCI_PRODUCT_BROADCOM_BCM5788, 2322 "Broadcom BCM5788 Gigabit Ethernet", 2323 }, 2324 { PCI_VENDOR_BROADCOM, 2325 PCI_PRODUCT_BROADCOM_BCM5789, 2326 "Broadcom BCM5789 Gigabit Ethernet", 2327 }, 2328 2329 { PCI_VENDOR_BROADCOM, 2330 PCI_PRODUCT_BROADCOM_BCM5901, 2331 "Broadcom BCM5901 Fast Ethernet", 2332 }, 2333 { PCI_VENDOR_BROADCOM, 2334 PCI_PRODUCT_BROADCOM_BCM5901A2, 2335 "Broadcom BCM5901A2 Fast Ethernet", 2336 }, 2337 2338 { PCI_VENDOR_SCHNEIDERKOCH, 2339 PCI_PRODUCT_SCHNEIDERKOCH_SK_9DX1, 2340 "SysKonnect SK-9Dx1 Gigabit Ethernet", 2341 }, 2342 2343 { PCI_VENDOR_3COM, 2344 PCI_PRODUCT_3COM_3C996, 2345 "3Com 3c996 Gigabit Ethernet", 2346 }, 2347 2348 { 0, 2349 0, 2350 NULL }, 2351 }; 2352 2353 static const struct bge_product * 2354 bge_lookup(const struct pci_attach_args *pa) 2355 { 2356 const struct bge_product *bp; 2357 2358 for (bp = bge_products; bp->bp_name != NULL; bp++) { 2359 if (PCI_VENDOR(pa->pa_id) == bp->bp_vendor && 2360 PCI_PRODUCT(pa->pa_id) == bp->bp_product) 2361 return (bp); 2362 } 2363 2364 return (NULL); 2365 } 2366 2367 static int 2368 bge_setpowerstate(struct bge_softc *sc, int powerlevel) 2369 { 2370 #ifdef NOTYET 2371 u_int32_t pm_ctl = 0; 2372 2373 /* XXX FIXME: make sure indirect accesses enabled? */ 2374 pm_ctl = pci_conf_read(sc->bge_dev, BGE_PCI_MISC_CTL, 4); 2375 pm_ctl |= BGE_PCIMISCCTL_INDIRECT_ACCESS; 2376 pci_write_config(sc->bge_dev, BGE_PCI_MISC_CTL, pm_ctl, 4); 2377 2378 /* clear the PME_assert bit and power state bits, enable PME */ 2379 pm_ctl = pci_conf_read(sc->bge_dev, BGE_PCI_PWRMGMT_CMD, 2); 2380 pm_ctl &= ~PCIM_PSTAT_DMASK; 2381 pm_ctl |= (1 << 8); 2382 2383 if (powerlevel == 0) { 2384 pm_ctl |= PCIM_PSTAT_D0; 2385 pci_write_config(sc->bge_dev, BGE_PCI_PWRMGMT_CMD, 2386 pm_ctl, 2); 2387 DELAY(10000); 2388 CSR_WRITE_4(sc, BGE_MISC_LOCAL_CTL, sc->bge_local_ctrl_reg); 2389 DELAY(10000); 2390 2391 #ifdef NOTYET 2392 /* XXX FIXME: write 0x02 to phy aux_Ctrl reg */ 2393 bge_miibus_writereg(sc->bge_dev, 1, 0x18, 0x02); 2394 #endif 2395 DELAY(40); DELAY(40); DELAY(40); 2396 DELAY(10000); /* above not quite adequate on 5700 */ 2397 return 0; 2398 } 2399 2400 2401 /* 2402 * Entering ACPI power states D1-D3 is achieved by wiggling 2403 * GMII gpio pins. Example code assumes all hardware vendors 2404 * followed Broadom's sample pcb layout. Until we verify that 2405 * for all supported OEM cards, states D1-D3 are unsupported. 2406 */ 2407 aprint_error_dev(sc->bge_dev, 2408 "power state %d unimplemented; check GPIO pins\n", 2409 powerlevel); 2410 #endif 2411 return EOPNOTSUPP; 2412 } 2413 2414 2415 /* 2416 * Probe for a Broadcom chip. Check the PCI vendor and device IDs 2417 * against our list and return its name if we find a match. Note 2418 * that since the Broadcom controller contains VPD support, we 2419 * can get the device name string from the controller itself instead 2420 * of the compiled-in string. This is a little slow, but it guarantees 2421 * we'll always announce the right product name. 2422 */ 2423 static int 2424 bge_probe(device_t parent, cfdata_t match, void *aux) 2425 { 2426 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 2427 2428 if (bge_lookup(pa) != NULL) 2429 return (1); 2430 2431 return (0); 2432 } 2433 2434 static void 2435 bge_attach(device_t parent, device_t self, void *aux) 2436 { 2437 struct bge_softc *sc = device_private(self); 2438 struct pci_attach_args *pa = aux; 2439 const struct bge_product *bp; 2440 const struct bge_revision *br; 2441 pci_chipset_tag_t pc; 2442 pci_intr_handle_t ih; 2443 const char *intrstr = NULL; 2444 bus_dma_segment_t seg; 2445 int rseg; 2446 u_int32_t hwcfg = 0; 2447 u_int32_t mac_addr = 0; 2448 u_int32_t command; 2449 struct ifnet *ifp; 2450 void * kva; 2451 u_char eaddr[ETHER_ADDR_LEN]; 2452 pcireg_t memtype; 2453 bus_addr_t memaddr; 2454 bus_size_t memsize; 2455 u_int32_t pm_ctl; 2456 2457 bp = bge_lookup(pa); 2458 KASSERT(bp != NULL); 2459 2460 sc->sc_pc = pa->pa_pc; 2461 sc->sc_pcitag = pa->pa_tag; 2462 sc->bge_dev = self; 2463 2464 aprint_naive(": Ethernet controller\n"); 2465 aprint_normal(": %s\n", bp->bp_name); 2466 2467 /* 2468 * Map control/status registers. 2469 */ 2470 DPRINTFN(5, ("Map control/status regs\n")); 2471 pc = sc->sc_pc; 2472 command = pci_conf_read(pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG); 2473 command |= PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_MASTER_ENABLE; 2474 pci_conf_write(pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG, command); 2475 command = pci_conf_read(pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG); 2476 2477 if (!(command & PCI_COMMAND_MEM_ENABLE)) { 2478 aprint_error_dev(sc->bge_dev, 2479 "failed to enable memory mapping!\n"); 2480 return; 2481 } 2482 2483 DPRINTFN(5, ("pci_mem_find\n")); 2484 memtype = pci_mapreg_type(sc->sc_pc, sc->sc_pcitag, BGE_PCI_BAR0); 2485 switch (memtype) { 2486 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 2487 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 2488 if (pci_mapreg_map(pa, BGE_PCI_BAR0, 2489 memtype, 0, &sc->bge_btag, &sc->bge_bhandle, 2490 &memaddr, &memsize) == 0) 2491 break; 2492 default: 2493 aprint_error_dev(sc->bge_dev, "can't find mem space\n"); 2494 return; 2495 } 2496 2497 DPRINTFN(5, ("pci_intr_map\n")); 2498 if (pci_intr_map(pa, &ih)) { 2499 aprint_error_dev(sc->bge_dev, "couldn't map interrupt\n"); 2500 return; 2501 } 2502 2503 DPRINTFN(5, ("pci_intr_string\n")); 2504 intrstr = pci_intr_string(pc, ih); 2505 2506 DPRINTFN(5, ("pci_intr_establish\n")); 2507 sc->bge_intrhand = pci_intr_establish(pc, ih, IPL_NET, bge_intr, sc); 2508 2509 if (sc->bge_intrhand == NULL) { 2510 aprint_error_dev(sc->bge_dev, 2511 "couldn't establish interrupt%s%s\n", 2512 intrstr ? " at " : "", intrstr ? intrstr : ""); 2513 return; 2514 } 2515 aprint_normal_dev(sc->bge_dev, "interrupting at %s\n", intrstr); 2516 2517 /* 2518 * Kludge for 5700 Bx bug: a hardware bug (PCIX byte enable?) 2519 * can clobber the chip's PCI config-space power control registers, 2520 * leaving the card in D3 powersave state. 2521 * We do not have memory-mapped registers in this state, 2522 * so force device into D0 state before starting initialization. 2523 */ 2524 pm_ctl = pci_conf_read(pc, sc->sc_pcitag, BGE_PCI_PWRMGMT_CMD); 2525 pm_ctl &= ~(PCI_PWR_D0|PCI_PWR_D1|PCI_PWR_D2|PCI_PWR_D3); 2526 pm_ctl |= (1 << 8) | PCI_PWR_D0 ; /* D0 state */ 2527 pci_conf_write(pc, sc->sc_pcitag, BGE_PCI_PWRMGMT_CMD, pm_ctl); 2528 DELAY(1000); /* 27 usec is allegedly sufficent */ 2529 2530 /* 2531 * Save ASIC rev. Look up any quirks associated with this 2532 * ASIC. 2533 */ 2534 sc->bge_chipid = 2535 pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MISC_CTL) & 2536 BGE_PCIMISCCTL_ASICREV; 2537 2538 /* 2539 * Detect PCI-Express devices 2540 * XXX: guessed from Linux/FreeBSD; no documentation 2541 */ 2542 if (pci_get_capability(sc->sc_pc, sc->sc_pcitag, PCI_CAP_PCIEXPRESS, 2543 NULL, NULL) != 0) 2544 sc->bge_pcie = 1; 2545 else 2546 sc->bge_pcie = 0; 2547 2548 /* Try to reset the chip. */ 2549 DPRINTFN(5, ("bge_reset\n")); 2550 bge_reset(sc); 2551 2552 if (bge_chipinit(sc)) { 2553 aprint_error_dev(sc->bge_dev, "chip initialization failed\n"); 2554 bge_release_resources(sc); 2555 return; 2556 } 2557 2558 /* 2559 * Get station address from the EEPROM. 2560 */ 2561 mac_addr = bge_readmem_ind(sc, 0x0c14); 2562 if ((mac_addr >> 16) == 0x484b) { 2563 eaddr[0] = (u_char)(mac_addr >> 8); 2564 eaddr[1] = (u_char)(mac_addr >> 0); 2565 mac_addr = bge_readmem_ind(sc, 0x0c18); 2566 eaddr[2] = (u_char)(mac_addr >> 24); 2567 eaddr[3] = (u_char)(mac_addr >> 16); 2568 eaddr[4] = (u_char)(mac_addr >> 8); 2569 eaddr[5] = (u_char)(mac_addr >> 0); 2570 } else if (bge_read_eeprom(sc, (void *)eaddr, 2571 BGE_EE_MAC_OFFSET + 2, ETHER_ADDR_LEN)) { 2572 aprint_error_dev(sc->bge_dev, 2573 "failed to read station address\n"); 2574 bge_release_resources(sc); 2575 return; 2576 } 2577 2578 br = bge_lookup_rev(sc->bge_chipid); 2579 2580 if (br == NULL) { 2581 aprint_normal_dev(sc->bge_dev, "unknown ASIC (0x%04x)", 2582 sc->bge_chipid >> 16); 2583 sc->bge_quirks = 0; 2584 } else { 2585 aprint_normal_dev(sc->bge_dev, "ASIC %s (0x%04x)", 2586 br->br_name, sc->bge_chipid >> 16); 2587 sc->bge_quirks |= br->br_quirks; 2588 } 2589 aprint_normal(", Ethernet address %s\n", ether_sprintf(eaddr)); 2590 2591 /* Allocate the general information block and ring buffers. */ 2592 if (pci_dma64_available(pa)) 2593 sc->bge_dmatag = pa->pa_dmat64; 2594 else 2595 sc->bge_dmatag = pa->pa_dmat; 2596 DPRINTFN(5, ("bus_dmamem_alloc\n")); 2597 if (bus_dmamem_alloc(sc->bge_dmatag, sizeof(struct bge_ring_data), 2598 PAGE_SIZE, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 2599 aprint_error_dev(sc->bge_dev, "can't alloc rx buffers\n"); 2600 return; 2601 } 2602 DPRINTFN(5, ("bus_dmamem_map\n")); 2603 if (bus_dmamem_map(sc->bge_dmatag, &seg, rseg, 2604 sizeof(struct bge_ring_data), &kva, 2605 BUS_DMA_NOWAIT)) { 2606 aprint_error_dev(sc->bge_dev, 2607 "can't map DMA buffers (%zu bytes)\n", 2608 sizeof(struct bge_ring_data)); 2609 bus_dmamem_free(sc->bge_dmatag, &seg, rseg); 2610 return; 2611 } 2612 DPRINTFN(5, ("bus_dmamem_create\n")); 2613 if (bus_dmamap_create(sc->bge_dmatag, sizeof(struct bge_ring_data), 1, 2614 sizeof(struct bge_ring_data), 0, 2615 BUS_DMA_NOWAIT, &sc->bge_ring_map)) { 2616 aprint_error_dev(sc->bge_dev, "can't create DMA map\n"); 2617 bus_dmamem_unmap(sc->bge_dmatag, kva, 2618 sizeof(struct bge_ring_data)); 2619 bus_dmamem_free(sc->bge_dmatag, &seg, rseg); 2620 return; 2621 } 2622 DPRINTFN(5, ("bus_dmamem_load\n")); 2623 if (bus_dmamap_load(sc->bge_dmatag, sc->bge_ring_map, kva, 2624 sizeof(struct bge_ring_data), NULL, 2625 BUS_DMA_NOWAIT)) { 2626 bus_dmamap_destroy(sc->bge_dmatag, sc->bge_ring_map); 2627 bus_dmamem_unmap(sc->bge_dmatag, kva, 2628 sizeof(struct bge_ring_data)); 2629 bus_dmamem_free(sc->bge_dmatag, &seg, rseg); 2630 return; 2631 } 2632 2633 DPRINTFN(5, ("bzero\n")); 2634 sc->bge_rdata = (struct bge_ring_data *)kva; 2635 2636 memset(sc->bge_rdata, 0, sizeof(struct bge_ring_data)); 2637 2638 /* Try to allocate memory for jumbo buffers. */ 2639 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 2640 if (bge_alloc_jumbo_mem(sc)) { 2641 aprint_error_dev(sc->bge_dev, 2642 "jumbo buffer allocation failed\n"); 2643 } else 2644 sc->ethercom.ec_capabilities |= ETHERCAP_JUMBO_MTU; 2645 } 2646 2647 /* Set default tuneable values. */ 2648 sc->bge_stat_ticks = BGE_TICKS_PER_SEC; 2649 sc->bge_rx_coal_ticks = 150; 2650 sc->bge_rx_max_coal_bds = 64; 2651 #ifdef ORIG_WPAUL_VALUES 2652 sc->bge_tx_coal_ticks = 150; 2653 sc->bge_tx_max_coal_bds = 128; 2654 #else 2655 sc->bge_tx_coal_ticks = 300; 2656 sc->bge_tx_max_coal_bds = 400; 2657 #endif 2658 if (sc->bge_quirks & BGE_QUIRK_5705_CORE) { 2659 sc->bge_tx_coal_ticks = (12 * 5); 2660 sc->bge_tx_max_coal_bds = (12 * 5); 2661 aprint_verbose_dev(sc->bge_dev, 2662 "setting short Tx thresholds\n"); 2663 } 2664 2665 /* Set up ifnet structure */ 2666 ifp = &sc->ethercom.ec_if; 2667 ifp->if_softc = sc; 2668 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 2669 ifp->if_ioctl = bge_ioctl; 2670 ifp->if_stop = bge_stop; 2671 ifp->if_start = bge_start; 2672 ifp->if_init = bge_init; 2673 ifp->if_watchdog = bge_watchdog; 2674 IFQ_SET_MAXLEN(&ifp->if_snd, max(BGE_TX_RING_CNT - 1, IFQ_MAXLEN)); 2675 IFQ_SET_READY(&ifp->if_snd); 2676 DPRINTFN(5, ("strcpy if_xname\n")); 2677 strcpy(ifp->if_xname, device_xname(sc->bge_dev)); 2678 2679 if ((sc->bge_quirks & BGE_QUIRK_CSUM_BROKEN) == 0) 2680 sc->ethercom.ec_if.if_capabilities |= 2681 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 2682 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 2683 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 2684 sc->ethercom.ec_capabilities |= 2685 ETHERCAP_VLAN_HWTAGGING | ETHERCAP_VLAN_MTU; 2686 2687 if (sc->bge_pcie) 2688 sc->ethercom.ec_if.if_capabilities |= IFCAP_TSOv4; 2689 2690 /* 2691 * Do MII setup. 2692 */ 2693 DPRINTFN(5, ("mii setup\n")); 2694 sc->bge_mii.mii_ifp = ifp; 2695 sc->bge_mii.mii_readreg = bge_miibus_readreg; 2696 sc->bge_mii.mii_writereg = bge_miibus_writereg; 2697 sc->bge_mii.mii_statchg = bge_miibus_statchg; 2698 2699 /* 2700 * Figure out what sort of media we have by checking the 2701 * hardware config word in the first 32k of NIC internal memory, 2702 * or fall back to the config word in the EEPROM. Note: on some BCM5700 2703 * cards, this value appears to be unset. If that's the 2704 * case, we have to rely on identifying the NIC by its PCI 2705 * subsystem ID, as we do below for the SysKonnect SK-9D41. 2706 */ 2707 if (bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_SIG) == BGE_MAGIC_NUMBER) { 2708 hwcfg = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_NICCFG); 2709 } else { 2710 bge_read_eeprom(sc, (void *)&hwcfg, 2711 BGE_EE_HWCFG_OFFSET, sizeof(hwcfg)); 2712 hwcfg = be32toh(hwcfg); 2713 } 2714 if ((hwcfg & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER) 2715 sc->bge_tbi = 1; 2716 2717 /* The SysKonnect SK-9D41 is a 1000baseSX card. */ 2718 if ((pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_SUBSYS) >> 16) == 2719 SK_SUBSYSID_9D41) 2720 sc->bge_tbi = 1; 2721 2722 if (sc->bge_tbi) { 2723 ifmedia_init(&sc->bge_ifmedia, IFM_IMASK, bge_ifmedia_upd, 2724 bge_ifmedia_sts); 2725 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL); 2726 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_1000_SX|IFM_FDX, 2727 0, NULL); 2728 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL); 2729 ifmedia_set(&sc->bge_ifmedia, IFM_ETHER|IFM_AUTO); 2730 } else { 2731 /* 2732 * Do transceiver setup. 2733 */ 2734 ifmedia_init(&sc->bge_mii.mii_media, 0, bge_ifmedia_upd, 2735 bge_ifmedia_sts); 2736 mii_attach(sc->bge_dev, &sc->bge_mii, 0xffffffff, 2737 MII_PHY_ANY, MII_OFFSET_ANY, 2738 MIIF_FORCEANEG|MIIF_DOPAUSE); 2739 2740 if (LIST_EMPTY(&sc->bge_mii.mii_phys)) { 2741 aprint_error_dev(sc->bge_dev, "no PHY found!\n"); 2742 ifmedia_add(&sc->bge_mii.mii_media, 2743 IFM_ETHER|IFM_MANUAL, 0, NULL); 2744 ifmedia_set(&sc->bge_mii.mii_media, 2745 IFM_ETHER|IFM_MANUAL); 2746 } else 2747 ifmedia_set(&sc->bge_mii.mii_media, 2748 IFM_ETHER|IFM_AUTO); 2749 } 2750 2751 /* 2752 * When using the BCM5701 in PCI-X mode, data corruption has 2753 * been observed in the first few bytes of some received packets. 2754 * Aligning the packet buffer in memory eliminates the corruption. 2755 * Unfortunately, this misaligns the packet payloads. On platforms 2756 * which do not support unaligned accesses, we will realign the 2757 * payloads by copying the received packets. 2758 */ 2759 if (sc->bge_quirks & BGE_QUIRK_PCIX_DMA_ALIGN_BUG) { 2760 /* If in PCI-X mode, work around the alignment bug. */ 2761 if ((pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_PCISTATE) & 2762 (BGE_PCISTATE_PCI_BUSMODE | BGE_PCISTATE_PCI_BUSSPEED)) == 2763 BGE_PCISTATE_PCI_BUSSPEED) 2764 sc->bge_rx_alignment_bug = 1; 2765 } 2766 2767 /* 2768 * Call MI attach routine. 2769 */ 2770 DPRINTFN(5, ("if_attach\n")); 2771 if_attach(ifp); 2772 DPRINTFN(5, ("ether_ifattach\n")); 2773 ether_ifattach(ifp, eaddr); 2774 #if NRND > 0 2775 rnd_attach_source(&sc->rnd_source, device_xname(sc->bge_dev), 2776 RND_TYPE_NET, 0); 2777 #endif 2778 #ifdef BGE_EVENT_COUNTERS 2779 /* 2780 * Attach event counters. 2781 */ 2782 evcnt_attach_dynamic(&sc->bge_ev_intr, EVCNT_TYPE_INTR, 2783 NULL, device_xname(sc->bge_dev), "intr"); 2784 evcnt_attach_dynamic(&sc->bge_ev_tx_xoff, EVCNT_TYPE_MISC, 2785 NULL, device_xname(sc->bge_dev), "tx_xoff"); 2786 evcnt_attach_dynamic(&sc->bge_ev_tx_xon, EVCNT_TYPE_MISC, 2787 NULL, device_xname(sc->bge_dev), "tx_xon"); 2788 evcnt_attach_dynamic(&sc->bge_ev_rx_xoff, EVCNT_TYPE_MISC, 2789 NULL, device_xname(sc->bge_dev), "rx_xoff"); 2790 evcnt_attach_dynamic(&sc->bge_ev_rx_xon, EVCNT_TYPE_MISC, 2791 NULL, device_xname(sc->bge_dev), "rx_xon"); 2792 evcnt_attach_dynamic(&sc->bge_ev_rx_macctl, EVCNT_TYPE_MISC, 2793 NULL, device_xname(sc->bge_dev), "rx_macctl"); 2794 evcnt_attach_dynamic(&sc->bge_ev_xoffentered, EVCNT_TYPE_MISC, 2795 NULL, device_xname(sc->bge_dev), "xoffentered"); 2796 #endif /* BGE_EVENT_COUNTERS */ 2797 DPRINTFN(5, ("callout_init\n")); 2798 callout_init(&sc->bge_timeout, 0); 2799 2800 if (!pmf_device_register(self, NULL, NULL)) 2801 aprint_error_dev(self, "couldn't establish power handler\n"); 2802 else 2803 pmf_class_network_register(self, ifp); 2804 } 2805 2806 static void 2807 bge_release_resources(struct bge_softc *sc) 2808 { 2809 if (sc->bge_vpd_prodname != NULL) 2810 free(sc->bge_vpd_prodname, M_DEVBUF); 2811 2812 if (sc->bge_vpd_readonly != NULL) 2813 free(sc->bge_vpd_readonly, M_DEVBUF); 2814 } 2815 2816 static void 2817 bge_reset(struct bge_softc *sc) 2818 { 2819 u_int32_t cachesize, command, pcistate, new_pcistate; 2820 int i, val; 2821 2822 /* Save some important PCI state. */ 2823 cachesize = pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CACHESZ); 2824 command = pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CMD); 2825 pcistate = pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_PCISTATE); 2826 2827 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MISC_CTL, 2828 BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR| 2829 BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_PCISTATE_RW); 2830 2831 /* 2832 * Disable the firmware fastboot feature on 5752 ASIC 2833 * to avoid firmware timeout. 2834 */ 2835 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5752 || 2836 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5755 || 2837 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5787) 2838 CSR_WRITE_4(sc, BGE_FASTBOOT_PC, 0); 2839 2840 val = BGE_MISCCFG_RESET_CORE_CLOCKS | (65<<1); 2841 /* 2842 * XXX: from FreeBSD/Linux; no documentation 2843 */ 2844 if (sc->bge_pcie) { 2845 if (CSR_READ_4(sc, BGE_PCIE_CTL1) == 0x60) 2846 CSR_WRITE_4(sc, BGE_PCIE_CTL1, 0x20); 2847 if (sc->bge_chipid != BGE_CHIPID_BCM5750_A0) { 2848 /* No idea what that actually means */ 2849 CSR_WRITE_4(sc, BGE_MISC_CFG, 1 << 29); 2850 val |= (1<<29); 2851 } 2852 } 2853 2854 /* Issue global reset */ 2855 bge_writereg_ind(sc, BGE_MISC_CFG, val); 2856 2857 DELAY(1000); 2858 2859 /* 2860 * XXX: from FreeBSD/Linux; no documentation 2861 */ 2862 if (sc->bge_pcie) { 2863 if (sc->bge_chipid == BGE_CHIPID_BCM5750_A0) { 2864 pcireg_t reg; 2865 2866 DELAY(500000); 2867 /* XXX: Magic Numbers */ 2868 reg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_UNKNOWN0); 2869 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_UNKNOWN0, 2870 reg | (1 << 15)); 2871 } 2872 /* 2873 * XXX: Magic Numbers. 2874 * Sets maximal PCI-e payload and clears any PCI-e errors. 2875 * Should be replaced with references to PCI config-space 2876 * capability block for PCI-Express. 2877 */ 2878 pci_conf_write(sc->sc_pc, sc->sc_pcitag, 2879 BGE_PCI_CONF_DEV_CTRL, 0xf5000); 2880 2881 } 2882 2883 /* Reset some of the PCI state that got zapped by reset */ 2884 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MISC_CTL, 2885 BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR| 2886 BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_PCISTATE_RW); 2887 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CMD, command); 2888 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CACHESZ, cachesize); 2889 bge_writereg_ind(sc, BGE_MISC_CFG, (65 << 1)); 2890 2891 /* Enable memory arbiter. */ 2892 { 2893 uint32_t marbmode = 0; 2894 if (BGE_IS_5714_FAMILY(sc)) { 2895 marbmode = CSR_READ_4(sc, BGE_MARB_MODE); 2896 } 2897 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE | marbmode); 2898 } 2899 2900 /* 2901 * Write the magic number to the firmware mailbox at 0xb50 2902 * so that the driver can synchronize with the firmware. 2903 */ 2904 bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM, BGE_MAGIC_NUMBER); 2905 2906 /* 2907 * Poll the value location we just wrote until 2908 * we see the 1's complement of the magic number. 2909 * This indicates that the firmware initialization 2910 * is complete. 2911 */ 2912 for (i = 0; i < BGE_TIMEOUT; i++) { 2913 val = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM); 2914 if (val == ~BGE_MAGIC_NUMBER) 2915 break; 2916 DELAY(1000); 2917 } 2918 2919 if (i >= BGE_TIMEOUT) { 2920 aprint_error_dev(sc->bge_dev, 2921 "firmware handshake timed out, val = %x\n", val); 2922 /* 2923 * XXX: occasionally fired on bcm5721, but without 2924 * apparent harm. For now, keep going if we timeout 2925 * against PCI-E devices. 2926 */ 2927 if (!sc->bge_pcie) 2928 return; 2929 } 2930 2931 /* 2932 * XXX Wait for the value of the PCISTATE register to 2933 * return to its original pre-reset state. This is a 2934 * fairly good indicator of reset completion. If we don't 2935 * wait for the reset to fully complete, trying to read 2936 * from the device's non-PCI registers may yield garbage 2937 * results. 2938 */ 2939 for (i = 0; i < 10000; i++) { 2940 new_pcistate = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 2941 BGE_PCI_PCISTATE); 2942 if ((new_pcistate & ~BGE_PCISTATE_RESERVED) == 2943 (pcistate & ~BGE_PCISTATE_RESERVED)) 2944 break; 2945 DELAY(10); 2946 } 2947 if ((new_pcistate & ~BGE_PCISTATE_RESERVED) != 2948 (pcistate & ~BGE_PCISTATE_RESERVED)) { 2949 aprint_error_dev(sc->bge_dev, "pcistate failed to revert\n"); 2950 } 2951 2952 /* XXX: from FreeBSD/Linux; no documentation */ 2953 if (sc->bge_pcie && sc->bge_chipid != BGE_CHIPID_BCM5750_A0) 2954 CSR_WRITE_4(sc, BGE_PCIE_CTL0, CSR_READ_4(sc, BGE_PCIE_CTL0) | (1<<25)); 2955 2956 /* Enable memory arbiter. */ 2957 /* XXX why do this twice? */ 2958 { 2959 uint32_t marbmode = 0; 2960 if (BGE_IS_5714_FAMILY(sc)) { 2961 marbmode = CSR_READ_4(sc, BGE_MARB_MODE); 2962 } 2963 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE | marbmode); 2964 } 2965 2966 /* Fix up byte swapping */ 2967 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS); 2968 2969 CSR_WRITE_4(sc, BGE_MAC_MODE, 0); 2970 2971 DELAY(10000); 2972 } 2973 2974 /* 2975 * Frame reception handling. This is called if there's a frame 2976 * on the receive return list. 2977 * 2978 * Note: we have to be able to handle two possibilities here: 2979 * 1) the frame is from the jumbo recieve ring 2980 * 2) the frame is from the standard receive ring 2981 */ 2982 2983 static void 2984 bge_rxeof(struct bge_softc *sc) 2985 { 2986 struct ifnet *ifp; 2987 int stdcnt = 0, jumbocnt = 0; 2988 bus_dmamap_t dmamap; 2989 bus_addr_t offset, toff; 2990 bus_size_t tlen; 2991 int tosync; 2992 2993 ifp = &sc->ethercom.ec_if; 2994 2995 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 2996 offsetof(struct bge_ring_data, bge_status_block), 2997 sizeof (struct bge_status_block), 2998 BUS_DMASYNC_POSTREAD); 2999 3000 offset = offsetof(struct bge_ring_data, bge_rx_return_ring); 3001 tosync = sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx - 3002 sc->bge_rx_saved_considx; 3003 3004 #if NRND > 0 3005 if (tosync != 0 && RND_ENABLED(&sc->rnd_source)) 3006 rnd_add_uint32(&sc->rnd_source, tosync); 3007 #endif 3008 3009 toff = offset + (sc->bge_rx_saved_considx * sizeof (struct bge_rx_bd)); 3010 3011 if (tosync < 0) { 3012 tlen = (sc->bge_return_ring_cnt - sc->bge_rx_saved_considx) * 3013 sizeof (struct bge_rx_bd); 3014 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 3015 toff, tlen, BUS_DMASYNC_POSTREAD); 3016 tosync = -tosync; 3017 } 3018 3019 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 3020 offset, tosync * sizeof (struct bge_rx_bd), 3021 BUS_DMASYNC_POSTREAD); 3022 3023 while(sc->bge_rx_saved_considx != 3024 sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx) { 3025 struct bge_rx_bd *cur_rx; 3026 u_int32_t rxidx; 3027 struct mbuf *m = NULL; 3028 3029 cur_rx = &sc->bge_rdata-> 3030 bge_rx_return_ring[sc->bge_rx_saved_considx]; 3031 3032 rxidx = cur_rx->bge_idx; 3033 BGE_INC(sc->bge_rx_saved_considx, sc->bge_return_ring_cnt); 3034 3035 if (cur_rx->bge_flags & BGE_RXBDFLAG_JUMBO_RING) { 3036 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT); 3037 m = sc->bge_cdata.bge_rx_jumbo_chain[rxidx]; 3038 sc->bge_cdata.bge_rx_jumbo_chain[rxidx] = NULL; 3039 jumbocnt++; 3040 bus_dmamap_sync(sc->bge_dmatag, 3041 sc->bge_cdata.bge_rx_jumbo_map, 3042 mtod(m, char *) - (char *)sc->bge_cdata.bge_jumbo_buf, 3043 BGE_JLEN, BUS_DMASYNC_POSTREAD); 3044 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 3045 ifp->if_ierrors++; 3046 bge_newbuf_jumbo(sc, sc->bge_jumbo, m); 3047 continue; 3048 } 3049 if (bge_newbuf_jumbo(sc, sc->bge_jumbo, 3050 NULL)== ENOBUFS) { 3051 ifp->if_ierrors++; 3052 bge_newbuf_jumbo(sc, sc->bge_jumbo, m); 3053 continue; 3054 } 3055 } else { 3056 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT); 3057 m = sc->bge_cdata.bge_rx_std_chain[rxidx]; 3058 3059 sc->bge_cdata.bge_rx_std_chain[rxidx] = NULL; 3060 stdcnt++; 3061 dmamap = sc->bge_cdata.bge_rx_std_map[rxidx]; 3062 sc->bge_cdata.bge_rx_std_map[rxidx] = 0; 3063 bus_dmamap_sync(sc->bge_dmatag, dmamap, 0, 3064 dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 3065 bus_dmamap_unload(sc->bge_dmatag, dmamap); 3066 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 3067 ifp->if_ierrors++; 3068 bge_newbuf_std(sc, sc->bge_std, m, dmamap); 3069 continue; 3070 } 3071 if (bge_newbuf_std(sc, sc->bge_std, 3072 NULL, dmamap) == ENOBUFS) { 3073 ifp->if_ierrors++; 3074 bge_newbuf_std(sc, sc->bge_std, m, dmamap); 3075 continue; 3076 } 3077 } 3078 3079 ifp->if_ipackets++; 3080 #ifndef __NO_STRICT_ALIGNMENT 3081 /* 3082 * XXX: if the 5701 PCIX-Rx-DMA workaround is in effect, 3083 * the Rx buffer has the layer-2 header unaligned. 3084 * If our CPU requires alignment, re-align by copying. 3085 */ 3086 if (sc->bge_rx_alignment_bug) { 3087 memmove(mtod(m, char *) + ETHER_ALIGN, m->m_data, 3088 cur_rx->bge_len); 3089 m->m_data += ETHER_ALIGN; 3090 } 3091 #endif 3092 3093 m->m_pkthdr.len = m->m_len = cur_rx->bge_len - ETHER_CRC_LEN; 3094 m->m_pkthdr.rcvif = ifp; 3095 3096 #if NBPFILTER > 0 3097 /* 3098 * Handle BPF listeners. Let the BPF user see the packet. 3099 */ 3100 if (ifp->if_bpf) 3101 bpf_mtap(ifp->if_bpf, m); 3102 #endif 3103 3104 m->m_pkthdr.csum_flags = M_CSUM_IPv4; 3105 3106 if ((cur_rx->bge_ip_csum ^ 0xffff) != 0) 3107 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 3108 /* 3109 * Rx transport checksum-offload may also 3110 * have bugs with packets which, when transmitted, 3111 * were `runts' requiring padding. 3112 */ 3113 if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM && 3114 (/* (sc->_bge_quirks & BGE_QUIRK_SHORT_CKSUM_BUG) == 0 ||*/ 3115 m->m_pkthdr.len >= ETHER_MIN_NOPAD)) { 3116 m->m_pkthdr.csum_data = 3117 cur_rx->bge_tcp_udp_csum; 3118 m->m_pkthdr.csum_flags |= 3119 (M_CSUM_TCPv4|M_CSUM_UDPv4| 3120 M_CSUM_DATA|M_CSUM_NO_PSEUDOHDR); 3121 } 3122 3123 /* 3124 * If we received a packet with a vlan tag, pass it 3125 * to vlan_input() instead of ether_input(). 3126 */ 3127 if (cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) 3128 VLAN_INPUT_TAG(ifp, m, cur_rx->bge_vlan_tag, continue); 3129 3130 (*ifp->if_input)(ifp, m); 3131 } 3132 3133 CSR_WRITE_4(sc, BGE_MBX_RX_CONS0_LO, sc->bge_rx_saved_considx); 3134 if (stdcnt) 3135 CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std); 3136 if (jumbocnt) 3137 CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo); 3138 } 3139 3140 static void 3141 bge_txeof(struct bge_softc *sc) 3142 { 3143 struct bge_tx_bd *cur_tx = NULL; 3144 struct ifnet *ifp; 3145 struct txdmamap_pool_entry *dma; 3146 bus_addr_t offset, toff; 3147 bus_size_t tlen; 3148 int tosync; 3149 struct mbuf *m; 3150 3151 ifp = &sc->ethercom.ec_if; 3152 3153 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 3154 offsetof(struct bge_ring_data, bge_status_block), 3155 sizeof (struct bge_status_block), 3156 BUS_DMASYNC_POSTREAD); 3157 3158 offset = offsetof(struct bge_ring_data, bge_tx_ring); 3159 tosync = sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx - 3160 sc->bge_tx_saved_considx; 3161 3162 #if NRND > 0 3163 if (tosync != 0 && RND_ENABLED(&sc->rnd_source)) 3164 rnd_add_uint32(&sc->rnd_source, tosync); 3165 #endif 3166 3167 toff = offset + (sc->bge_tx_saved_considx * sizeof (struct bge_tx_bd)); 3168 3169 if (tosync < 0) { 3170 tlen = (BGE_TX_RING_CNT - sc->bge_tx_saved_considx) * 3171 sizeof (struct bge_tx_bd); 3172 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 3173 toff, tlen, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 3174 tosync = -tosync; 3175 } 3176 3177 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 3178 offset, tosync * sizeof (struct bge_tx_bd), 3179 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 3180 3181 /* 3182 * Go through our tx ring and free mbufs for those 3183 * frames that have been sent. 3184 */ 3185 while (sc->bge_tx_saved_considx != 3186 sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx) { 3187 u_int32_t idx = 0; 3188 3189 idx = sc->bge_tx_saved_considx; 3190 cur_tx = &sc->bge_rdata->bge_tx_ring[idx]; 3191 if (cur_tx->bge_flags & BGE_TXBDFLAG_END) 3192 ifp->if_opackets++; 3193 m = sc->bge_cdata.bge_tx_chain[idx]; 3194 if (m != NULL) { 3195 sc->bge_cdata.bge_tx_chain[idx] = NULL; 3196 dma = sc->txdma[idx]; 3197 bus_dmamap_sync(sc->bge_dmatag, dma->dmamap, 0, 3198 dma->dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 3199 bus_dmamap_unload(sc->bge_dmatag, dma->dmamap); 3200 SLIST_INSERT_HEAD(&sc->txdma_list, dma, link); 3201 sc->txdma[idx] = NULL; 3202 3203 m_freem(m); 3204 } 3205 sc->bge_txcnt--; 3206 BGE_INC(sc->bge_tx_saved_considx, BGE_TX_RING_CNT); 3207 ifp->if_timer = 0; 3208 } 3209 3210 if (cur_tx != NULL) 3211 ifp->if_flags &= ~IFF_OACTIVE; 3212 } 3213 3214 static int 3215 bge_intr(void *xsc) 3216 { 3217 struct bge_softc *sc; 3218 struct ifnet *ifp; 3219 3220 sc = xsc; 3221 ifp = &sc->ethercom.ec_if; 3222 3223 /* 3224 * Ascertain whether the interrupt is from this bge device. 3225 * Do the cheap test first. 3226 */ 3227 if ((sc->bge_rdata->bge_status_block.bge_status & 3228 BGE_STATFLAG_UPDATED) == 0) { 3229 /* 3230 * Sometimes, the interrupt comes in before the 3231 * DMA update of the status block (performed prior 3232 * to the interrupt itself) has completed. 3233 * In that case, do the (extremely expensive!) 3234 * PCI-config-space register read. 3235 */ 3236 uint32_t pcistate = 3237 pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_PCISTATE); 3238 3239 if (pcistate & BGE_PCISTATE_INTR_STATE) 3240 return (0); 3241 3242 } 3243 /* 3244 * If we reach here, then the interrupt is for us. 3245 */ 3246 3247 /* Ack interrupt and stop others from occuring. */ 3248 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 1); 3249 3250 BGE_EVCNT_INCR(sc->bge_ev_intr); 3251 3252 /* 3253 * Process link state changes. 3254 * Grrr. The link status word in the status block does 3255 * not work correctly on the BCM5700 rev AX and BX chips, 3256 * according to all available information. Hence, we have 3257 * to enable MII interrupts in order to properly obtain 3258 * async link changes. Unfortunately, this also means that 3259 * we have to read the MAC status register to detect link 3260 * changes, thereby adding an additional register access to 3261 * the interrupt handler. 3262 */ 3263 3264 if (sc->bge_quirks & BGE_QUIRK_LINK_STATE_BROKEN) { 3265 u_int32_t status; 3266 3267 status = CSR_READ_4(sc, BGE_MAC_STS); 3268 if (status & BGE_MACSTAT_MI_INTERRUPT) { 3269 sc->bge_link = 0; 3270 callout_stop(&sc->bge_timeout); 3271 bge_tick(sc); 3272 /* Clear the interrupt */ 3273 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, 3274 BGE_EVTENB_MI_INTERRUPT); 3275 bge_miibus_readreg(sc->bge_dev, 1, BRGPHY_MII_ISR); 3276 bge_miibus_writereg(sc->bge_dev, 1, BRGPHY_MII_IMR, 3277 BRGPHY_INTRS); 3278 } 3279 } else { 3280 u_int32_t status; 3281 3282 status = CSR_READ_4(sc, BGE_MAC_STS); 3283 if (status & BGE_MACSTAT_LINK_CHANGED) { 3284 sc->bge_link = 0; 3285 callout_stop(&sc->bge_timeout); 3286 bge_tick(sc); 3287 /* Clear the interrupt */ 3288 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED| 3289 BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE| 3290 BGE_MACSTAT_LINK_CHANGED); 3291 } 3292 } 3293 3294 if (ifp->if_flags & IFF_RUNNING) { 3295 /* Check RX return ring producer/consumer */ 3296 bge_rxeof(sc); 3297 3298 /* Check TX ring producer/consumer */ 3299 bge_txeof(sc); 3300 } 3301 3302 if (sc->bge_pending_rxintr_change) { 3303 uint32_t rx_ticks = sc->bge_rx_coal_ticks; 3304 uint32_t rx_bds = sc->bge_rx_max_coal_bds; 3305 uint32_t junk; 3306 3307 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, rx_ticks); 3308 DELAY(10); 3309 junk = CSR_READ_4(sc, BGE_HCC_RX_COAL_TICKS); 3310 3311 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, rx_bds); 3312 DELAY(10); 3313 junk = CSR_READ_4(sc, BGE_HCC_RX_MAX_COAL_BDS); 3314 3315 sc->bge_pending_rxintr_change = 0; 3316 } 3317 bge_handle_events(sc); 3318 3319 /* Re-enable interrupts. */ 3320 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 0); 3321 3322 if (ifp->if_flags & IFF_RUNNING && !IFQ_IS_EMPTY(&ifp->if_snd)) 3323 bge_start(ifp); 3324 3325 return (1); 3326 } 3327 3328 static void 3329 bge_tick(void *xsc) 3330 { 3331 struct bge_softc *sc = xsc; 3332 struct mii_data *mii = &sc->bge_mii; 3333 int s; 3334 3335 s = splnet(); 3336 3337 bge_stats_update(sc); 3338 callout_reset(&sc->bge_timeout, hz, bge_tick, sc); 3339 3340 if (sc->bge_tbi) { 3341 if (CSR_READ_4(sc, BGE_MAC_STS) & 3342 BGE_MACSTAT_TBI_PCS_SYNCHED) { 3343 CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF); 3344 } 3345 } else 3346 mii_tick(mii); 3347 3348 splx(s); 3349 } 3350 3351 static void 3352 bge_stats_update(struct bge_softc *sc) 3353 { 3354 struct ifnet *ifp = &sc->ethercom.ec_if; 3355 bus_size_t stats = BGE_MEMWIN_START + BGE_STATS_BLOCK; 3356 bus_size_t rstats = BGE_RX_STATS; 3357 3358 #define READ_RSTAT(sc, stats, stat) \ 3359 CSR_READ_4(sc, stats + offsetof(struct bge_mac_stats_regs, stat)) 3360 3361 if (sc->bge_quirks & BGE_QUIRK_5705_CORE) { 3362 ifp->if_collisions += 3363 READ_RSTAT(sc, rstats, dot3StatsSingleCollisionFrames) + 3364 READ_RSTAT(sc, rstats, dot3StatsMultipleCollisionFrames) + 3365 READ_RSTAT(sc, rstats, dot3StatsExcessiveCollisions) + 3366 READ_RSTAT(sc, rstats, dot3StatsLateCollisions); 3367 3368 BGE_EVCNT_ADD(sc->bge_ev_tx_xoff, 3369 READ_RSTAT(sc, rstats, outXoffSent)); 3370 BGE_EVCNT_ADD(sc->bge_ev_tx_xon, 3371 READ_RSTAT(sc, rstats, outXonSent)); 3372 BGE_EVCNT_ADD(sc->bge_ev_rx_xoff, 3373 READ_RSTAT(sc, rstats, xoffPauseFramesReceived)); 3374 BGE_EVCNT_ADD(sc->bge_ev_rx_xon, 3375 READ_RSTAT(sc, rstats, xonPauseFramesReceived)); 3376 BGE_EVCNT_ADD(sc->bge_ev_rx_macctl, 3377 READ_RSTAT(sc, rstats, macControlFramesReceived)); 3378 BGE_EVCNT_ADD(sc->bge_ev_xoffentered, 3379 READ_RSTAT(sc, rstats, xoffStateEntered)); 3380 return; 3381 } 3382 3383 #undef READ_RSTAT 3384 #define READ_STAT(sc, stats, stat) \ 3385 CSR_READ_4(sc, stats + offsetof(struct bge_stats, stat)) 3386 3387 ifp->if_collisions += 3388 (READ_STAT(sc, stats, dot3StatsSingleCollisionFrames.bge_addr_lo) + 3389 READ_STAT(sc, stats, dot3StatsMultipleCollisionFrames.bge_addr_lo) + 3390 READ_STAT(sc, stats, dot3StatsExcessiveCollisions.bge_addr_lo) + 3391 READ_STAT(sc, stats, dot3StatsLateCollisions.bge_addr_lo)) - 3392 ifp->if_collisions; 3393 3394 BGE_EVCNT_UPD(sc->bge_ev_tx_xoff, 3395 READ_STAT(sc, stats, outXoffSent.bge_addr_lo)); 3396 BGE_EVCNT_UPD(sc->bge_ev_tx_xon, 3397 READ_STAT(sc, stats, outXonSent.bge_addr_lo)); 3398 BGE_EVCNT_UPD(sc->bge_ev_rx_xoff, 3399 READ_STAT(sc, stats, 3400 xoffPauseFramesReceived.bge_addr_lo)); 3401 BGE_EVCNT_UPD(sc->bge_ev_rx_xon, 3402 READ_STAT(sc, stats, xonPauseFramesReceived.bge_addr_lo)); 3403 BGE_EVCNT_UPD(sc->bge_ev_rx_macctl, 3404 READ_STAT(sc, stats, 3405 macControlFramesReceived.bge_addr_lo)); 3406 BGE_EVCNT_UPD(sc->bge_ev_xoffentered, 3407 READ_STAT(sc, stats, xoffStateEntered.bge_addr_lo)); 3408 3409 #undef READ_STAT 3410 3411 #ifdef notdef 3412 ifp->if_collisions += 3413 (sc->bge_rdata->bge_info.bge_stats.dot3StatsSingleCollisionFrames + 3414 sc->bge_rdata->bge_info.bge_stats.dot3StatsMultipleCollisionFrames + 3415 sc->bge_rdata->bge_info.bge_stats.dot3StatsExcessiveCollisions + 3416 sc->bge_rdata->bge_info.bge_stats.dot3StatsLateCollisions) - 3417 ifp->if_collisions; 3418 #endif 3419 } 3420 3421 /* 3422 * Pad outbound frame to ETHER_MIN_NOPAD for an unusual reason. 3423 * The bge hardware will pad out Tx runts to ETHER_MIN_NOPAD, 3424 * but when such padded frames employ the bge IP/TCP checksum offload, 3425 * the hardware checksum assist gives incorrect results (possibly 3426 * from incorporating its own padding into the UDP/TCP checksum; who knows). 3427 * If we pad such runts with zeros, the onboard checksum comes out correct. 3428 */ 3429 static inline int 3430 bge_cksum_pad(struct mbuf *pkt) 3431 { 3432 struct mbuf *last = NULL; 3433 int padlen; 3434 3435 padlen = ETHER_MIN_NOPAD - pkt->m_pkthdr.len; 3436 3437 /* if there's only the packet-header and we can pad there, use it. */ 3438 if (pkt->m_pkthdr.len == pkt->m_len && 3439 M_TRAILINGSPACE(pkt) >= padlen) { 3440 last = pkt; 3441 } else { 3442 /* 3443 * Walk packet chain to find last mbuf. We will either 3444 * pad there, or append a new mbuf and pad it 3445 * (thus perhaps avoiding the bcm5700 dma-min bug). 3446 */ 3447 for (last = pkt; last->m_next != NULL; last = last->m_next) { 3448 continue; /* do nothing */ 3449 } 3450 3451 /* `last' now points to last in chain. */ 3452 if (M_TRAILINGSPACE(last) < padlen) { 3453 /* Allocate new empty mbuf, pad it. Compact later. */ 3454 struct mbuf *n; 3455 MGET(n, M_DONTWAIT, MT_DATA); 3456 if (n == NULL) 3457 return ENOBUFS; 3458 n->m_len = 0; 3459 last->m_next = n; 3460 last = n; 3461 } 3462 } 3463 3464 KDASSERT(!M_READONLY(last)); 3465 KDASSERT(M_TRAILINGSPACE(last) >= padlen); 3466 3467 /* Now zero the pad area, to avoid the bge cksum-assist bug */ 3468 memset(mtod(last, char *) + last->m_len, 0, padlen); 3469 last->m_len += padlen; 3470 pkt->m_pkthdr.len += padlen; 3471 return 0; 3472 } 3473 3474 /* 3475 * Compact outbound packets to avoid bug with DMA segments less than 8 bytes. 3476 */ 3477 static inline int 3478 bge_compact_dma_runt(struct mbuf *pkt) 3479 { 3480 struct mbuf *m, *prev; 3481 int totlen, prevlen; 3482 3483 prev = NULL; 3484 totlen = 0; 3485 prevlen = -1; 3486 3487 for (m = pkt; m != NULL; prev = m,m = m->m_next) { 3488 int mlen = m->m_len; 3489 int shortfall = 8 - mlen ; 3490 3491 totlen += mlen; 3492 if (mlen == 0) { 3493 continue; 3494 } 3495 if (mlen >= 8) 3496 continue; 3497 3498 /* If we get here, mbuf data is too small for DMA engine. 3499 * Try to fix by shuffling data to prev or next in chain. 3500 * If that fails, do a compacting deep-copy of the whole chain. 3501 */ 3502 3503 /* Internal frag. If fits in prev, copy it there. */ 3504 if (prev && M_TRAILINGSPACE(prev) >= m->m_len) { 3505 memcpy(prev->m_data + prev->m_len, m->m_data, mlen); 3506 prev->m_len += mlen; 3507 m->m_len = 0; 3508 /* XXX stitch chain */ 3509 prev->m_next = m_free(m); 3510 m = prev; 3511 continue; 3512 } 3513 else if (m->m_next != NULL && 3514 M_TRAILINGSPACE(m) >= shortfall && 3515 m->m_next->m_len >= (8 + shortfall)) { 3516 /* m is writable and have enough data in next, pull up. */ 3517 3518 memcpy(m->m_data + m->m_len, m->m_next->m_data, 3519 shortfall); 3520 m->m_len += shortfall; 3521 m->m_next->m_len -= shortfall; 3522 m->m_next->m_data += shortfall; 3523 } 3524 else if (m->m_next == NULL || 1) { 3525 /* Got a runt at the very end of the packet. 3526 * borrow data from the tail of the preceding mbuf and 3527 * update its length in-place. (The original data is still 3528 * valid, so we can do this even if prev is not writable.) 3529 */ 3530 3531 /* if we'd make prev a runt, just move all of its data. */ 3532 KASSERT(prev != NULL /*, ("runt but null PREV")*/); 3533 KASSERT(prev->m_len >= 8 /*, ("runt prev")*/); 3534 3535 if ((prev->m_len - shortfall) < 8) 3536 shortfall = prev->m_len; 3537 3538 #ifdef notyet /* just do the safe slow thing for now */ 3539 if (!M_READONLY(m)) { 3540 if (M_LEADINGSPACE(m) < shorfall) { 3541 void *m_dat; 3542 m_dat = (m->m_flags & M_PKTHDR) ? 3543 m->m_pktdat : m->dat; 3544 memmove(m_dat, mtod(m, void*), m->m_len); 3545 m->m_data = m_dat; 3546 } 3547 } else 3548 #endif /* just do the safe slow thing */ 3549 { 3550 struct mbuf * n = NULL; 3551 int newprevlen = prev->m_len - shortfall; 3552 3553 MGET(n, M_NOWAIT, MT_DATA); 3554 if (n == NULL) 3555 return ENOBUFS; 3556 KASSERT(m->m_len + shortfall < MLEN 3557 /*, 3558 ("runt %d +prev %d too big\n", m->m_len, shortfall)*/); 3559 3560 /* first copy the data we're stealing from prev */ 3561 memcpy(n->m_data, prev->m_data + newprevlen, 3562 shortfall); 3563 3564 /* update prev->m_len accordingly */ 3565 prev->m_len -= shortfall; 3566 3567 /* copy data from runt m */ 3568 memcpy(n->m_data + shortfall, m->m_data, 3569 m->m_len); 3570 3571 /* n holds what we stole from prev, plus m */ 3572 n->m_len = shortfall + m->m_len; 3573 3574 /* stitch n into chain and free m */ 3575 n->m_next = m->m_next; 3576 prev->m_next = n; 3577 /* KASSERT(m->m_next == NULL); */ 3578 m->m_next = NULL; 3579 m_free(m); 3580 m = n; /* for continuing loop */ 3581 } 3582 } 3583 prevlen = m->m_len; 3584 } 3585 return 0; 3586 } 3587 3588 /* 3589 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data 3590 * pointers to descriptors. 3591 */ 3592 static int 3593 bge_encap(struct bge_softc *sc, struct mbuf *m_head, u_int32_t *txidx) 3594 { 3595 struct bge_tx_bd *f = NULL; 3596 u_int32_t frag, cur; 3597 u_int16_t csum_flags = 0; 3598 u_int16_t txbd_tso_flags = 0; 3599 struct txdmamap_pool_entry *dma; 3600 bus_dmamap_t dmamap; 3601 int i = 0; 3602 struct m_tag *mtag; 3603 int use_tso, maxsegsize, error; 3604 3605 cur = frag = *txidx; 3606 3607 if (m_head->m_pkthdr.csum_flags) { 3608 if (m_head->m_pkthdr.csum_flags & M_CSUM_IPv4) 3609 csum_flags |= BGE_TXBDFLAG_IP_CSUM; 3610 if (m_head->m_pkthdr.csum_flags & (M_CSUM_TCPv4|M_CSUM_UDPv4)) 3611 csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM; 3612 } 3613 3614 /* 3615 * If we were asked to do an outboard checksum, and the NIC 3616 * has the bug where it sometimes adds in the Ethernet padding, 3617 * explicitly pad with zeros so the cksum will be correct either way. 3618 * (For now, do this for all chip versions, until newer 3619 * are confirmed to not require the workaround.) 3620 */ 3621 if ((csum_flags & BGE_TXBDFLAG_TCP_UDP_CSUM) == 0 || 3622 #ifdef notyet 3623 (sc->bge_quirks & BGE_QUIRK_SHORT_CKSUM_BUG) == 0 || 3624 #endif 3625 m_head->m_pkthdr.len >= ETHER_MIN_NOPAD) 3626 goto check_dma_bug; 3627 3628 if (bge_cksum_pad(m_head) != 0) { 3629 return ENOBUFS; 3630 } 3631 3632 check_dma_bug: 3633 if (!(sc->bge_quirks & BGE_QUIRK_5700_SMALLDMA)) 3634 goto doit; 3635 /* 3636 * bcm5700 Revision B silicon cannot handle DMA descriptors with 3637 * less than eight bytes. If we encounter a teeny mbuf 3638 * at the end of a chain, we can pad. Otherwise, copy. 3639 */ 3640 if (bge_compact_dma_runt(m_head) != 0) 3641 return ENOBUFS; 3642 3643 doit: 3644 dma = SLIST_FIRST(&sc->txdma_list); 3645 if (dma == NULL) 3646 return ENOBUFS; 3647 dmamap = dma->dmamap; 3648 3649 /* 3650 * Set up any necessary TSO state before we start packing... 3651 */ 3652 use_tso = (m_head->m_pkthdr.csum_flags & M_CSUM_TSOv4) != 0; 3653 if (!use_tso) { 3654 maxsegsize = 0; 3655 } else { /* TSO setup */ 3656 unsigned mss; 3657 struct ether_header *eh; 3658 unsigned ip_tcp_hlen, iptcp_opt_words, tcp_seg_flags, offset; 3659 struct mbuf * m0 = m_head; 3660 struct ip *ip; 3661 struct tcphdr *th; 3662 int iphl, hlen; 3663 3664 /* 3665 * XXX It would be nice if the mbuf pkthdr had offset 3666 * fields for the protocol headers. 3667 */ 3668 3669 eh = mtod(m0, struct ether_header *); 3670 switch (htons(eh->ether_type)) { 3671 case ETHERTYPE_IP: 3672 offset = ETHER_HDR_LEN; 3673 break; 3674 3675 case ETHERTYPE_VLAN: 3676 offset = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 3677 break; 3678 3679 default: 3680 /* 3681 * Don't support this protocol or encapsulation. 3682 */ 3683 return (ENOBUFS); 3684 } 3685 3686 /* 3687 * TCP/IP headers are in the first mbuf; we can do 3688 * this the easy way. 3689 */ 3690 iphl = M_CSUM_DATA_IPv4_IPHL(m0->m_pkthdr.csum_data); 3691 hlen = iphl + offset; 3692 if (__predict_false(m0->m_len < 3693 (hlen + sizeof(struct tcphdr)))) { 3694 3695 aprint_debug_dev(sc->bge_dev, 3696 "TSO: hard case m0->m_len == %d < ip/tcp hlen %zd," 3697 "not handled yet\n", 3698 m0->m_len, hlen+ sizeof(struct tcphdr)); 3699 #ifdef NOTYET 3700 /* 3701 * XXX jonathan (at) NetBSD.org: untested. 3702 * how to force this branch to be taken? 3703 */ 3704 BGE_EVCNT_INCR(&sc->sc_ev_txtsopain); 3705 3706 m_copydata(m0, offset, sizeof(ip), &ip); 3707 m_copydata(m0, hlen, sizeof(th), &th); 3708 3709 ip.ip_len = 0; 3710 3711 m_copyback(m0, hlen + offsetof(struct ip, ip_len), 3712 sizeof(ip.ip_len), &ip.ip_len); 3713 3714 th.th_sum = in_cksum_phdr(ip.ip_src.s_addr, 3715 ip.ip_dst.s_addr, htons(IPPROTO_TCP)); 3716 3717 m_copyback(m0, hlen + offsetof(struct tcphdr, th_sum), 3718 sizeof(th.th_sum), &th.th_sum); 3719 3720 hlen += th.th_off << 2; 3721 iptcp_opt_words = hlen; 3722 #else 3723 /* 3724 * if_wm "hard" case not yet supported, can we not 3725 * mandate it out of existence? 3726 */ 3727 (void) ip; (void)th; (void) ip_tcp_hlen; 3728 3729 return ENOBUFS; 3730 #endif 3731 } else { 3732 ip = (struct ip *) (mtod(m0, char *) + offset); 3733 th = (struct tcphdr *) (mtod(m0, char *) + hlen); 3734 ip_tcp_hlen = iphl + (th->th_off << 2); 3735 3736 /* Total IP/TCP options, in 32-bit words */ 3737 iptcp_opt_words = (ip_tcp_hlen 3738 - sizeof(struct tcphdr) 3739 - sizeof(struct ip)) >> 2; 3740 } 3741 if (BGE_IS_5750_OR_BEYOND(sc)) { 3742 th->th_sum = 0; 3743 csum_flags &= ~(BGE_TXBDFLAG_TCP_UDP_CSUM); 3744 } else { 3745 /* 3746 * XXX jonathan (at) NetBSD.org: 5705 untested. 3747 * Requires TSO firmware patch for 5701/5703/5704. 3748 */ 3749 th->th_sum = in_cksum_phdr(ip->ip_src.s_addr, 3750 ip->ip_dst.s_addr, htons(IPPROTO_TCP)); 3751 } 3752 3753 mss = m_head->m_pkthdr.segsz; 3754 txbd_tso_flags |= 3755 BGE_TXBDFLAG_CPU_PRE_DMA | 3756 BGE_TXBDFLAG_CPU_POST_DMA; 3757 3758 /* 3759 * Our NIC TSO-assist assumes TSO has standard, optionless 3760 * IPv4 and TCP headers, which total 40 bytes. By default, 3761 * the NIC copies 40 bytes of IP/TCP header from the 3762 * supplied header into the IP/TCP header portion of 3763 * each post-TSO-segment. If the supplied packet has IP or 3764 * TCP options, we need to tell the NIC to copy those extra 3765 * bytes into each post-TSO header, in addition to the normal 3766 * 40-byte IP/TCP header (and to leave space accordingly). 3767 * Unfortunately, the driver encoding of option length 3768 * varies across different ASIC families. 3769 */ 3770 tcp_seg_flags = 0; 3771 if (iptcp_opt_words) { 3772 if ( BGE_IS_5705_OR_BEYOND(sc)) { 3773 tcp_seg_flags = 3774 iptcp_opt_words << 11; 3775 } else { 3776 txbd_tso_flags |= 3777 iptcp_opt_words << 12; 3778 } 3779 } 3780 maxsegsize = mss | tcp_seg_flags; 3781 ip->ip_len = htons(mss + ip_tcp_hlen); 3782 3783 } /* TSO setup */ 3784 3785 /* 3786 * Start packing the mbufs in this chain into 3787 * the fragment pointers. Stop when we run out 3788 * of fragments or hit the end of the mbuf chain. 3789 */ 3790 error = bus_dmamap_load_mbuf(sc->bge_dmatag, dmamap, m_head, 3791 BUS_DMA_NOWAIT); 3792 if (error) { 3793 return(ENOBUFS); 3794 } 3795 /* 3796 * Sanity check: avoid coming within 16 descriptors 3797 * of the end of the ring. 3798 */ 3799 if (dmamap->dm_nsegs > (BGE_TX_RING_CNT - sc->bge_txcnt - 16)) { 3800 BGE_TSO_PRINTF(("%s: " 3801 " dmamap_load_mbuf too close to ring wrap\n", 3802 device_xname(sc->bge_dev))); 3803 goto fail_unload; 3804 } 3805 3806 mtag = sc->ethercom.ec_nvlans ? 3807 m_tag_find(m_head, PACKET_TAG_VLAN, NULL) : NULL; 3808 3809 3810 /* Iterate over dmap-map fragments. */ 3811 for (i = 0; i < dmamap->dm_nsegs; i++) { 3812 f = &sc->bge_rdata->bge_tx_ring[frag]; 3813 if (sc->bge_cdata.bge_tx_chain[frag] != NULL) 3814 break; 3815 3816 bge_set_hostaddr(&f->bge_addr, dmamap->dm_segs[i].ds_addr); 3817 f->bge_len = dmamap->dm_segs[i].ds_len; 3818 3819 /* 3820 * For 5751 and follow-ons, for TSO we must turn 3821 * off checksum-assist flag in the tx-descr, and 3822 * supply the ASIC-revision-specific encoding 3823 * of TSO flags and segsize. 3824 */ 3825 if (use_tso) { 3826 if (BGE_IS_5750_OR_BEYOND(sc) || i == 0) { 3827 f->bge_rsvd = maxsegsize; 3828 f->bge_flags = csum_flags | txbd_tso_flags; 3829 } else { 3830 f->bge_rsvd = 0; 3831 f->bge_flags = 3832 (csum_flags | txbd_tso_flags) & 0x0fff; 3833 } 3834 } else { 3835 f->bge_rsvd = 0; 3836 f->bge_flags = csum_flags; 3837 } 3838 3839 if (mtag != NULL) { 3840 f->bge_flags |= BGE_TXBDFLAG_VLAN_TAG; 3841 f->bge_vlan_tag = VLAN_TAG_VALUE(mtag); 3842 } else { 3843 f->bge_vlan_tag = 0; 3844 } 3845 cur = frag; 3846 BGE_INC(frag, BGE_TX_RING_CNT); 3847 } 3848 3849 if (i < dmamap->dm_nsegs) { 3850 BGE_TSO_PRINTF(("%s: reached %d < dm_nsegs %d\n", 3851 device_xname(sc->bge_dev), i, dmamap->dm_nsegs)); 3852 goto fail_unload; 3853 } 3854 3855 bus_dmamap_sync(sc->bge_dmatag, dmamap, 0, dmamap->dm_mapsize, 3856 BUS_DMASYNC_PREWRITE); 3857 3858 if (frag == sc->bge_tx_saved_considx) { 3859 BGE_TSO_PRINTF(("%s: frag %d = wrapped id %d?\n", 3860 device_xname(sc->bge_dev), frag, sc->bge_tx_saved_considx)); 3861 3862 goto fail_unload; 3863 } 3864 3865 sc->bge_rdata->bge_tx_ring[cur].bge_flags |= BGE_TXBDFLAG_END; 3866 sc->bge_cdata.bge_tx_chain[cur] = m_head; 3867 SLIST_REMOVE_HEAD(&sc->txdma_list, link); 3868 sc->txdma[cur] = dma; 3869 sc->bge_txcnt += dmamap->dm_nsegs; 3870 3871 *txidx = frag; 3872 3873 return(0); 3874 3875 fail_unload: 3876 bus_dmamap_unload(sc->bge_dmatag, dmamap); 3877 3878 return ENOBUFS; 3879 } 3880 3881 /* 3882 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 3883 * to the mbuf data regions directly in the transmit descriptors. 3884 */ 3885 static void 3886 bge_start(struct ifnet *ifp) 3887 { 3888 struct bge_softc *sc; 3889 struct mbuf *m_head = NULL; 3890 u_int32_t prodidx; 3891 int pkts = 0; 3892 3893 sc = ifp->if_softc; 3894 3895 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 3896 return; 3897 3898 prodidx = sc->bge_tx_prodidx; 3899 3900 while(sc->bge_cdata.bge_tx_chain[prodidx] == NULL) { 3901 IFQ_POLL(&ifp->if_snd, m_head); 3902 if (m_head == NULL) 3903 break; 3904 3905 #if 0 3906 /* 3907 * XXX 3908 * safety overkill. If this is a fragmented packet chain 3909 * with delayed TCP/UDP checksums, then only encapsulate 3910 * it if we have enough descriptors to handle the entire 3911 * chain at once. 3912 * (paranoia -- may not actually be needed) 3913 */ 3914 if (m_head->m_flags & M_FIRSTFRAG && 3915 m_head->m_pkthdr.csum_flags & (CSUM_DELAY_DATA)) { 3916 if ((BGE_TX_RING_CNT - sc->bge_txcnt) < 3917 M_CSUM_DATA_IPv4_OFFSET(m_head->m_pkthdr.csum_data) + 16) { 3918 ifp->if_flags |= IFF_OACTIVE; 3919 break; 3920 } 3921 } 3922 #endif 3923 3924 /* 3925 * Pack the data into the transmit ring. If we 3926 * don't have room, set the OACTIVE flag and wait 3927 * for the NIC to drain the ring. 3928 */ 3929 if (bge_encap(sc, m_head, &prodidx)) { 3930 ifp->if_flags |= IFF_OACTIVE; 3931 break; 3932 } 3933 3934 /* now we are committed to transmit the packet */ 3935 IFQ_DEQUEUE(&ifp->if_snd, m_head); 3936 pkts++; 3937 3938 #if NBPFILTER > 0 3939 /* 3940 * If there's a BPF listener, bounce a copy of this frame 3941 * to him. 3942 */ 3943 if (ifp->if_bpf) 3944 bpf_mtap(ifp->if_bpf, m_head); 3945 #endif 3946 } 3947 if (pkts == 0) 3948 return; 3949 3950 /* Transmit */ 3951 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); 3952 if (sc->bge_quirks & BGE_QUIRK_PRODUCER_BUG) /* 5700 b2 errata */ 3953 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); 3954 3955 sc->bge_tx_prodidx = prodidx; 3956 3957 /* 3958 * Set a timeout in case the chip goes out to lunch. 3959 */ 3960 ifp->if_timer = 5; 3961 } 3962 3963 static int 3964 bge_init(struct ifnet *ifp) 3965 { 3966 struct bge_softc *sc = ifp->if_softc; 3967 const u_int16_t *m; 3968 int s, error = 0; 3969 3970 s = splnet(); 3971 3972 ifp = &sc->ethercom.ec_if; 3973 3974 /* Cancel pending I/O and flush buffers. */ 3975 bge_stop(ifp, 0); 3976 bge_reset(sc); 3977 bge_chipinit(sc); 3978 3979 /* 3980 * Init the various state machines, ring 3981 * control blocks and firmware. 3982 */ 3983 error = bge_blockinit(sc); 3984 if (error != 0) { 3985 aprint_error_dev(sc->bge_dev, "initialization error %d\n", 3986 error); 3987 splx(s); 3988 return error; 3989 } 3990 3991 ifp = &sc->ethercom.ec_if; 3992 3993 /* Specify MTU. */ 3994 CSR_WRITE_4(sc, BGE_RX_MTU, ifp->if_mtu + 3995 ETHER_HDR_LEN + ETHER_CRC_LEN + ETHER_VLAN_ENCAP_LEN); 3996 3997 /* Load our MAC address. */ 3998 m = (const u_int16_t *)&(CLLADDR(ifp->if_sadl)[0]); 3999 CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0])); 4000 CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, (htons(m[1]) << 16) | htons(m[2])); 4001 4002 /* Enable or disable promiscuous mode as needed. */ 4003 if (ifp->if_flags & IFF_PROMISC) { 4004 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 4005 } else { 4006 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 4007 } 4008 4009 /* Program multicast filter. */ 4010 bge_setmulti(sc); 4011 4012 /* Init RX ring. */ 4013 bge_init_rx_ring_std(sc); 4014 4015 /* Init jumbo RX ring. */ 4016 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 4017 bge_init_rx_ring_jumbo(sc); 4018 4019 /* Init our RX return ring index */ 4020 sc->bge_rx_saved_considx = 0; 4021 4022 /* Init TX ring. */ 4023 bge_init_tx_ring(sc); 4024 4025 /* Turn on transmitter */ 4026 BGE_SETBIT(sc, BGE_TX_MODE, BGE_TXMODE_ENABLE); 4027 4028 /* Turn on receiver */ 4029 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE); 4030 4031 CSR_WRITE_4(sc, BGE_MAX_RX_FRAME_LOWAT, 2); 4032 4033 /* Tell firmware we're alive. */ 4034 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 4035 4036 /* Enable host interrupts. */ 4037 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA); 4038 BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); 4039 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 0); 4040 4041 if ((error = bge_ifmedia_upd(ifp)) != 0) 4042 goto out; 4043 4044 ifp->if_flags |= IFF_RUNNING; 4045 ifp->if_flags &= ~IFF_OACTIVE; 4046 4047 callout_reset(&sc->bge_timeout, hz, bge_tick, sc); 4048 4049 out: 4050 splx(s); 4051 4052 return error; 4053 } 4054 4055 /* 4056 * Set media options. 4057 */ 4058 static int 4059 bge_ifmedia_upd(struct ifnet *ifp) 4060 { 4061 struct bge_softc *sc = ifp->if_softc; 4062 struct mii_data *mii = &sc->bge_mii; 4063 struct ifmedia *ifm = &sc->bge_ifmedia; 4064 int rc; 4065 4066 /* If this is a 1000baseX NIC, enable the TBI port. */ 4067 if (sc->bge_tbi) { 4068 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 4069 return(EINVAL); 4070 switch(IFM_SUBTYPE(ifm->ifm_media)) { 4071 case IFM_AUTO: 4072 break; 4073 case IFM_1000_SX: 4074 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 4075 BGE_CLRBIT(sc, BGE_MAC_MODE, 4076 BGE_MACMODE_HALF_DUPLEX); 4077 } else { 4078 BGE_SETBIT(sc, BGE_MAC_MODE, 4079 BGE_MACMODE_HALF_DUPLEX); 4080 } 4081 break; 4082 default: 4083 return(EINVAL); 4084 } 4085 /* XXX 802.3x flow control for 1000BASE-SX */ 4086 return(0); 4087 } 4088 4089 sc->bge_link = 0; 4090 if ((rc = mii_mediachg(mii)) == ENXIO) 4091 return 0; 4092 return rc; 4093 } 4094 4095 /* 4096 * Report current media status. 4097 */ 4098 static void 4099 bge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 4100 { 4101 struct bge_softc *sc = ifp->if_softc; 4102 struct mii_data *mii = &sc->bge_mii; 4103 4104 if (sc->bge_tbi) { 4105 ifmr->ifm_status = IFM_AVALID; 4106 ifmr->ifm_active = IFM_ETHER; 4107 if (CSR_READ_4(sc, BGE_MAC_STS) & 4108 BGE_MACSTAT_TBI_PCS_SYNCHED) 4109 ifmr->ifm_status |= IFM_ACTIVE; 4110 ifmr->ifm_active |= IFM_1000_SX; 4111 if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX) 4112 ifmr->ifm_active |= IFM_HDX; 4113 else 4114 ifmr->ifm_active |= IFM_FDX; 4115 return; 4116 } 4117 4118 mii_pollstat(mii); 4119 ifmr->ifm_status = mii->mii_media_status; 4120 ifmr->ifm_active = (mii->mii_media_active & ~IFM_ETH_FMASK) | 4121 sc->bge_flowflags; 4122 } 4123 4124 static int 4125 bge_ioctl(struct ifnet *ifp, u_long command, void *data) 4126 { 4127 struct bge_softc *sc = ifp->if_softc; 4128 struct ifreq *ifr = (struct ifreq *) data; 4129 int s, error = 0; 4130 struct mii_data *mii; 4131 4132 s = splnet(); 4133 4134 switch(command) { 4135 case SIOCSIFFLAGS: 4136 if (ifp->if_flags & IFF_UP) { 4137 /* 4138 * If only the state of the PROMISC flag changed, 4139 * then just use the 'set promisc mode' command 4140 * instead of reinitializing the entire NIC. Doing 4141 * a full re-init means reloading the firmware and 4142 * waiting for it to start up, which may take a 4143 * second or two. 4144 */ 4145 if (ifp->if_flags & IFF_RUNNING && 4146 ifp->if_flags & IFF_PROMISC && 4147 !(sc->bge_if_flags & IFF_PROMISC)) { 4148 BGE_SETBIT(sc, BGE_RX_MODE, 4149 BGE_RXMODE_RX_PROMISC); 4150 } else if (ifp->if_flags & IFF_RUNNING && 4151 !(ifp->if_flags & IFF_PROMISC) && 4152 sc->bge_if_flags & IFF_PROMISC) { 4153 BGE_CLRBIT(sc, BGE_RX_MODE, 4154 BGE_RXMODE_RX_PROMISC); 4155 } else if (!(sc->bge_if_flags & IFF_UP)) 4156 bge_init(ifp); 4157 } else { 4158 if (ifp->if_flags & IFF_RUNNING) 4159 bge_stop(ifp, 1); 4160 } 4161 sc->bge_if_flags = ifp->if_flags; 4162 error = 0; 4163 break; 4164 case SIOCSIFMEDIA: 4165 /* XXX Flow control is not supported for 1000BASE-SX */ 4166 if (sc->bge_tbi) { 4167 ifr->ifr_media &= ~IFM_ETH_FMASK; 4168 sc->bge_flowflags = 0; 4169 } 4170 4171 /* Flow control requires full-duplex mode. */ 4172 if (IFM_SUBTYPE(ifr->ifr_media) == IFM_AUTO || 4173 (ifr->ifr_media & IFM_FDX) == 0) { 4174 ifr->ifr_media &= ~IFM_ETH_FMASK; 4175 } 4176 if (IFM_SUBTYPE(ifr->ifr_media) != IFM_AUTO) { 4177 if ((ifr->ifr_media & IFM_ETH_FMASK) == IFM_FLOW) { 4178 /* We an do both TXPAUSE and RXPAUSE. */ 4179 ifr->ifr_media |= 4180 IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE; 4181 } 4182 sc->bge_flowflags = ifr->ifr_media & IFM_ETH_FMASK; 4183 } 4184 /* FALLTHROUGH */ 4185 case SIOCGIFMEDIA: 4186 if (sc->bge_tbi) { 4187 error = ifmedia_ioctl(ifp, ifr, &sc->bge_ifmedia, 4188 command); 4189 } else { 4190 mii = &sc->bge_mii; 4191 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, 4192 command); 4193 } 4194 break; 4195 default: 4196 if ((error = ether_ioctl(ifp, command, data)) != ENETRESET) 4197 break; 4198 4199 error = 0; 4200 4201 if (command != SIOCADDMULTI && command != SIOCDELMULTI) 4202 ; 4203 else if (ifp->if_flags & IFF_RUNNING) 4204 bge_setmulti(sc); 4205 break; 4206 } 4207 4208 splx(s); 4209 4210 return(error); 4211 } 4212 4213 static void 4214 bge_watchdog(struct ifnet *ifp) 4215 { 4216 struct bge_softc *sc; 4217 4218 sc = ifp->if_softc; 4219 4220 aprint_error_dev(sc->bge_dev, "watchdog timeout -- resetting\n"); 4221 4222 ifp->if_flags &= ~IFF_RUNNING; 4223 bge_init(ifp); 4224 4225 ifp->if_oerrors++; 4226 } 4227 4228 static void 4229 bge_stop_block(struct bge_softc *sc, bus_addr_t reg, uint32_t bit) 4230 { 4231 int i; 4232 4233 BGE_CLRBIT(sc, reg, bit); 4234 4235 for (i = 0; i < BGE_TIMEOUT; i++) { 4236 if ((CSR_READ_4(sc, reg) & bit) == 0) 4237 return; 4238 delay(100); 4239 if (sc->bge_pcie) 4240 DELAY(1000); 4241 } 4242 4243 aprint_error_dev(sc->bge_dev, 4244 "block failed to stop: reg 0x%lx, bit 0x%08x\n", (u_long)reg, bit); 4245 } 4246 4247 /* 4248 * Stop the adapter and free any mbufs allocated to the 4249 * RX and TX lists. 4250 */ 4251 static void 4252 bge_stop(struct ifnet *ifp, int disable) 4253 { 4254 struct bge_softc *sc = ifp->if_softc; 4255 4256 callout_stop(&sc->bge_timeout); 4257 4258 /* 4259 * Disable all of the receiver blocks 4260 */ 4261 bge_stop_block(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE); 4262 bge_stop_block(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 4263 bge_stop_block(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 4264 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 4265 bge_stop_block(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 4266 } 4267 bge_stop_block(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE); 4268 bge_stop_block(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 4269 bge_stop_block(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE); 4270 4271 /* 4272 * Disable all of the transmit blocks 4273 */ 4274 bge_stop_block(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 4275 bge_stop_block(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 4276 bge_stop_block(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 4277 bge_stop_block(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE); 4278 bge_stop_block(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE); 4279 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 4280 bge_stop_block(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 4281 } 4282 bge_stop_block(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 4283 4284 /* 4285 * Shut down all of the memory managers and related 4286 * state machines. 4287 */ 4288 bge_stop_block(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE); 4289 bge_stop_block(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE); 4290 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 4291 bge_stop_block(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 4292 } 4293 4294 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 4295 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 4296 4297 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 4298 bge_stop_block(sc, BGE_BMAN_MODE, BGE_BMANMODE_ENABLE); 4299 bge_stop_block(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 4300 } 4301 4302 /* Disable host interrupts. */ 4303 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); 4304 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 1); 4305 4306 /* 4307 * Tell firmware we're shutting down. 4308 */ 4309 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 4310 4311 /* Free the RX lists. */ 4312 bge_free_rx_ring_std(sc); 4313 4314 /* Free jumbo RX list. */ 4315 bge_free_rx_ring_jumbo(sc); 4316 4317 /* Free TX buffers. */ 4318 bge_free_tx_ring(sc); 4319 4320 /* 4321 * Isolate/power down the PHY. 4322 */ 4323 if (!sc->bge_tbi) 4324 mii_down(&sc->bge_mii); 4325 4326 sc->bge_link = 0; 4327 4328 sc->bge_tx_saved_considx = BGE_TXCONS_UNSET; 4329 4330 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 4331 } 4332 4333 static int 4334 sysctl_bge_verify(SYSCTLFN_ARGS) 4335 { 4336 int error, t; 4337 struct sysctlnode node; 4338 4339 node = *rnode; 4340 t = *(int*)rnode->sysctl_data; 4341 node.sysctl_data = &t; 4342 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 4343 if (error || newp == NULL) 4344 return (error); 4345 4346 #if 0 4347 DPRINTF2(("%s: t = %d, nodenum = %d, rnodenum = %d\n", __func__, t, 4348 node.sysctl_num, rnode->sysctl_num)); 4349 #endif 4350 4351 if (node.sysctl_num == bge_rxthresh_nodenum) { 4352 if (t < 0 || t >= NBGE_RX_THRESH) 4353 return (EINVAL); 4354 bge_update_all_threshes(t); 4355 } else 4356 return (EINVAL); 4357 4358 *(int*)rnode->sysctl_data = t; 4359 4360 return (0); 4361 } 4362 4363 /* 4364 * Set up sysctl(3) MIB, hw.bge.*. 4365 * 4366 * TBD condition SYSCTL_PERMANENT on being an LKM or not 4367 */ 4368 SYSCTL_SETUP(sysctl_bge, "sysctl bge subtree setup") 4369 { 4370 int rc, bge_root_num; 4371 const struct sysctlnode *node; 4372 4373 if ((rc = sysctl_createv(clog, 0, NULL, NULL, 4374 CTLFLAG_PERMANENT, CTLTYPE_NODE, "hw", NULL, 4375 NULL, 0, NULL, 0, CTL_HW, CTL_EOL)) != 0) { 4376 goto err; 4377 } 4378 4379 if ((rc = sysctl_createv(clog, 0, NULL, &node, 4380 CTLFLAG_PERMANENT, CTLTYPE_NODE, "bge", 4381 SYSCTL_DESCR("BGE interface controls"), 4382 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL)) != 0) { 4383 goto err; 4384 } 4385 4386 bge_root_num = node->sysctl_num; 4387 4388 /* BGE Rx interrupt mitigation level */ 4389 if ((rc = sysctl_createv(clog, 0, NULL, &node, 4390 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, 4391 CTLTYPE_INT, "rx_lvl", 4392 SYSCTL_DESCR("BGE receive interrupt mitigation level"), 4393 sysctl_bge_verify, 0, 4394 &bge_rx_thresh_lvl, 4395 0, CTL_HW, bge_root_num, CTL_CREATE, 4396 CTL_EOL)) != 0) { 4397 goto err; 4398 } 4399 4400 bge_rxthresh_nodenum = node->sysctl_num; 4401 4402 return; 4403 4404 err: 4405 aprint_error("%s: sysctl_createv failed (rc = %d)\n", __func__, rc); 4406 } 4407
Indexes created Tue Sep 23 02:09:52 GMT 2025