if_bge.c revision 1.156
1 /* $NetBSD: if_bge.c,v 1.156 2009/03/22 16:12:53 msaitoh Exp $ */ 2 3 /* 4 * Copyright (c) 2001 Wind River Systems 5 * Copyright (c) 1997, 1998, 1999, 2001 6 * Bill Paul <wpaul (at) windriver.com>. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Bill Paul. 19 * 4. Neither the name of the author nor the names of any co-contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 33 * THE POSSIBILITY OF SUCH DAMAGE. 34 * 35 * $FreeBSD: if_bge.c,v 1.13 2002/04/04 06:01:31 wpaul Exp $ 36 */ 37 38 /* 39 * Broadcom BCM570x family gigabit ethernet driver for NetBSD. 40 * 41 * NetBSD version by: 42 * 43 * Frank van der Linden <fvdl (at) wasabisystems.com> 44 * Jason Thorpe <thorpej (at) wasabisystems.com> 45 * Jonathan Stone <jonathan (at) dsg.stanford.edu> 46 * 47 * Originally written for FreeBSD by Bill Paul <wpaul (at) windriver.com> 48 * Senior Engineer, Wind River Systems 49 */ 50 51 /* 52 * The Broadcom BCM5700 is based on technology originally developed by 53 * Alteon Networks as part of the Tigon I and Tigon II gigabit ethernet 54 * MAC chips. The BCM5700, sometimes refered to as the Tigon III, has 55 * two on-board MIPS R4000 CPUs and can have as much as 16MB of external 56 * SSRAM. The BCM5700 supports TCP, UDP and IP checksum offload, jumbo 57 * frames, highly configurable RX filtering, and 16 RX and TX queues 58 * (which, along with RX filter rules, can be used for QOS applications). 59 * Other features, such as TCP segmentation, may be available as part 60 * of value-added firmware updates. Unlike the Tigon I and Tigon II, 61 * firmware images can be stored in hardware and need not be compiled 62 * into the driver. 63 * 64 * The BCM5700 supports the PCI v2.2 and PCI-X v1.0 standards, and will 65 * function in a 32-bit/64-bit 33/66MHz bus, or a 64-bit/133MHz bus. 66 * 67 * The BCM5701 is a single-chip solution incorporating both the BCM5700 68 * MAC and a BCM5401 10/100/1000 PHY. Unlike the BCM5700, the BCM5701 69 * does not support external SSRAM. 70 * 71 * Broadcom also produces a variation of the BCM5700 under the "Altima" 72 * brand name, which is functionally similar but lacks PCI-X support. 73 * 74 * Without external SSRAM, you can only have at most 4 TX rings, 75 * and the use of the mini RX ring is disabled. This seems to imply 76 * that these features are simply not available on the BCM5701. As a 77 * result, this driver does not implement any support for the mini RX 78 * ring. 79 */ 80 81 #include <sys/cdefs.h> 82 __KERNEL_RCSID(0, "$NetBSD: if_bge.c,v 1.156 2009/03/22 16:12:53 msaitoh Exp $"); 83 84 #include "bpfilter.h" 85 #include "vlan.h" 86 #include "rnd.h" 87 88 #include <sys/param.h> 89 #include <sys/systm.h> 90 #include <sys/callout.h> 91 #include <sys/sockio.h> 92 #include <sys/mbuf.h> 93 #include <sys/malloc.h> 94 #include <sys/kernel.h> 95 #include <sys/device.h> 96 #include <sys/socket.h> 97 #include <sys/sysctl.h> 98 99 #include <net/if.h> 100 #include <net/if_dl.h> 101 #include <net/if_media.h> 102 #include <net/if_ether.h> 103 104 #if NRND > 0 105 #include <sys/rnd.h> 106 #endif 107 108 #ifdef INET 109 #include <netinet/in.h> 110 #include <netinet/in_systm.h> 111 #include <netinet/in_var.h> 112 #include <netinet/ip.h> 113 #endif 114 115 /* Headers for TCP Segmentation Offload (TSO) */ 116 #include <netinet/in_systm.h> /* n_time for <netinet/ip.h>... */ 117 #include <netinet/in.h> /* ip_{src,dst}, for <netinet/ip.h> */ 118 #include <netinet/ip.h> /* for struct ip */ 119 #include <netinet/tcp.h> /* for struct tcphdr */ 120 121 122 #if NBPFILTER > 0 123 #include <net/bpf.h> 124 #endif 125 126 #include <dev/pci/pcireg.h> 127 #include <dev/pci/pcivar.h> 128 #include <dev/pci/pcidevs.h> 129 130 #include <dev/mii/mii.h> 131 #include <dev/mii/miivar.h> 132 #include <dev/mii/miidevs.h> 133 #include <dev/mii/brgphyreg.h> 134 135 #include <dev/pci/if_bgereg.h> 136 137 #include <uvm/uvm_extern.h> 138 139 #define ETHER_MIN_NOPAD (ETHER_MIN_LEN - ETHER_CRC_LEN) /* i.e., 60 */ 140 141 142 /* 143 * Tunable thresholds for rx-side bge interrupt mitigation. 144 */ 145 146 /* 147 * The pairs of values below were obtained from empirical measurement 148 * on bcm5700 rev B2; they ar designed to give roughly 1 receive 149 * interrupt for every N packets received, where N is, approximately, 150 * the second value (rx_max_bds) in each pair. The values are chosen 151 * such that moving from one pair to the succeeding pair was observed 152 * to roughly halve interrupt rate under sustained input packet load. 153 * The values were empirically chosen to avoid overflowing internal 154 * limits on the bcm5700: inreasing rx_ticks much beyond 600 155 * results in internal wrapping and higher interrupt rates. 156 * The limit of 46 frames was chosen to match NFS workloads. 157 * 158 * These values also work well on bcm5701, bcm5704C, and (less 159 * tested) bcm5703. On other chipsets, (including the Altima chip 160 * family), the larger values may overflow internal chip limits, 161 * leading to increasing interrupt rates rather than lower interrupt 162 * rates. 163 * 164 * Applications using heavy interrupt mitigation (interrupting every 165 * 32 or 46 frames) in both directions may need to increase the TCP 166 * windowsize to above 131072 bytes (e.g., to 199608 bytes) to sustain 167 * full link bandwidth, due to ACKs and window updates lingering 168 * in the RX queue during the 30-to-40-frame interrupt-mitigation window. 169 */ 170 static const struct bge_load_rx_thresh { 171 int rx_ticks; 172 int rx_max_bds; } 173 bge_rx_threshes[] = { 174 { 32, 2 }, 175 { 50, 4 }, 176 { 100, 8 }, 177 { 192, 16 }, 178 { 416, 32 }, 179 { 598, 46 } 180 }; 181 #define NBGE_RX_THRESH (sizeof(bge_rx_threshes) / sizeof(bge_rx_threshes[0])) 182 183 /* XXX patchable; should be sysctl'able */ 184 static int bge_auto_thresh = 1; 185 static int bge_rx_thresh_lvl; 186 187 static int bge_rxthresh_nodenum; 188 189 typedef int (*bge_eaddr_fcn_t)(struct bge_softc *, u_int8_t[]); 190 191 static int bge_probe(device_t, cfdata_t, void *); 192 static void bge_attach(device_t, device_t, void *); 193 static void bge_release_resources(struct bge_softc *); 194 static void bge_txeof(struct bge_softc *); 195 static void bge_rxeof(struct bge_softc *); 196 197 static int bge_get_eaddr_mem(struct bge_softc *, u_int8_t[]); 198 static int bge_get_eaddr_nvram(struct bge_softc *, u_int8_t[]); 199 static int bge_get_eaddr_eeprom(struct bge_softc *, u_int8_t[]); 200 static int bge_get_eaddr(struct bge_softc *, u_int8_t[]); 201 202 static void bge_tick(void *); 203 static void bge_stats_update(struct bge_softc *); 204 static int bge_encap(struct bge_softc *, struct mbuf *, u_int32_t *); 205 206 static int bge_intr(void *); 207 static void bge_start(struct ifnet *); 208 static int bge_ioctl(struct ifnet *, u_long, void *); 209 static int bge_init(struct ifnet *); 210 static void bge_stop(struct ifnet *, int); 211 static void bge_watchdog(struct ifnet *); 212 static int bge_ifmedia_upd(struct ifnet *); 213 static void bge_ifmedia_sts(struct ifnet *, struct ifmediareq *); 214 215 static void bge_setmulti(struct bge_softc *); 216 217 static void bge_handle_events(struct bge_softc *); 218 static int bge_alloc_jumbo_mem(struct bge_softc *); 219 #if 0 /* XXX */ 220 static void bge_free_jumbo_mem(struct bge_softc *); 221 #endif 222 static void *bge_jalloc(struct bge_softc *); 223 static void bge_jfree(struct mbuf *, void *, size_t, void *); 224 static int bge_newbuf_std(struct bge_softc *, int, struct mbuf *, 225 bus_dmamap_t); 226 static int bge_newbuf_jumbo(struct bge_softc *, int, struct mbuf *); 227 static int bge_init_rx_ring_std(struct bge_softc *); 228 static void bge_free_rx_ring_std(struct bge_softc *); 229 static int bge_init_rx_ring_jumbo(struct bge_softc *); 230 static void bge_free_rx_ring_jumbo(struct bge_softc *); 231 static void bge_free_tx_ring(struct bge_softc *); 232 static int bge_init_tx_ring(struct bge_softc *); 233 234 static int bge_chipinit(struct bge_softc *); 235 static int bge_blockinit(struct bge_softc *); 236 static int bge_setpowerstate(struct bge_softc *, int); 237 238 static void bge_reset(struct bge_softc *); 239 240 #define BGE_DEBUG 241 #ifdef BGE_DEBUG 242 #define DPRINTF(x) if (bgedebug) printf x 243 #define DPRINTFN(n,x) if (bgedebug >= (n)) printf x 244 #define BGE_TSO_PRINTF(x) do { if (bge_tso_debug) printf x ;} while (0) 245 int bgedebug = 0; 246 int bge_tso_debug = 0; 247 #else 248 #define DPRINTF(x) 249 #define DPRINTFN(n,x) 250 #define BGE_TSO_PRINTF(x) 251 #endif 252 253 #ifdef BGE_EVENT_COUNTERS 254 #define BGE_EVCNT_INCR(ev) (ev).ev_count++ 255 #define BGE_EVCNT_ADD(ev, val) (ev).ev_count += (val) 256 #define BGE_EVCNT_UPD(ev, val) (ev).ev_count = (val) 257 #else 258 #define BGE_EVCNT_INCR(ev) /* nothing */ 259 #define BGE_EVCNT_ADD(ev, val) /* nothing */ 260 #define BGE_EVCNT_UPD(ev, val) /* nothing */ 261 #endif 262 263 /* Various chip quirks. */ 264 #define BGE_QUIRK_LINK_STATE_BROKEN 0x00000001 265 #define BGE_QUIRK_CSUM_BROKEN 0x00000002 266 #define BGE_QUIRK_5700_SMALLDMA 0x00000008 267 #define BGE_QUIRK_5700_PCIX_REG_BUG 0x00000010 268 #define BGE_QUIRK_PRODUCER_BUG 0x00000020 269 #define BGE_QUIRK_PCIX_DMA_ALIGN_BUG 0x00000040 270 #define BGE_QUIRK_5705_CORE 0x00000080 271 #define BGE_QUIRK_FEWER_MBUFS 0x00000100 272 273 /* 274 * XXX: how to handle variants based on 5750 and derivatives: 275 * 5750 5751, 5721, possibly 5714, 5752, and 5708?, which 276 * in general behave like a 5705, except with additional quirks. 277 * This driver's current handling of the 5721 is wrong; 278 * how we map ASIC revision to "quirks" needs more thought. 279 * (defined here until the thought is done). 280 */ 281 #define BGE_IS_5714_FAMILY(sc) \ 282 (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5714_A0 || \ 283 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5780 || \ 284 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5714 ) 285 286 #define BGE_IS_5750_OR_BEYOND(sc) \ 287 (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5750 || \ 288 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5752 || \ 289 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5755 || \ 290 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5787 || \ 291 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906 || \ 292 BGE_IS_5714_FAMILY(sc) ) 293 294 #define BGE_IS_5705_OR_BEYOND(sc) \ 295 ( ((sc)->bge_quirks & BGE_QUIRK_5705_CORE) || \ 296 BGE_IS_5750_OR_BEYOND(sc) ) 297 298 299 /* following bugs are common to bcm5700 rev B, all flavours */ 300 #define BGE_QUIRK_5700_COMMON \ 301 (BGE_QUIRK_5700_SMALLDMA|BGE_QUIRK_PRODUCER_BUG) 302 303 CFATTACH_DECL_NEW(bge, sizeof(struct bge_softc), 304 bge_probe, bge_attach, NULL, NULL); 305 306 static u_int32_t 307 bge_readmem_ind(struct bge_softc *sc, int off) 308 { 309 pcireg_t val; 310 311 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_BASEADDR, off); 312 val = pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_DATA); 313 return val; 314 } 315 316 static void 317 bge_writemem_ind(struct bge_softc *sc, int off, int val) 318 { 319 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_BASEADDR, off); 320 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_DATA, val); 321 } 322 323 #ifdef notdef 324 static u_int32_t 325 bge_readreg_ind(struct bge_softc *sc, int off) 326 { 327 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_REG_BASEADDR, off); 328 return(pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_REG_DATA)); 329 } 330 #endif 331 332 static void 333 bge_writereg_ind(struct bge_softc *sc, int off, int val) 334 { 335 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_REG_BASEADDR, off); 336 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_REG_DATA, val); 337 } 338 339 static void 340 bge_writemem_direct(struct bge_softc *sc, int off, int val) 341 { 342 CSR_WRITE_4(sc, off, val); 343 } 344 345 static void 346 bge_writembx(struct bge_softc *sc, int off, int val) 347 { 348 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 349 off += BGE_LPMBX_IRQ0_HI - BGE_MBX_IRQ0_HI; 350 351 CSR_WRITE_4(sc, off, val); 352 } 353 354 #ifdef notdef 355 static u_int8_t 356 bge_vpd_readbyte(struct bge_softc *sc, int addr) 357 { 358 int i; 359 u_int32_t val; 360 361 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_VPD_ADDR, addr); 362 for (i = 0; i < BGE_TIMEOUT * 10; i++) { 363 DELAY(10); 364 if (pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_VPD_ADDR) & 365 BGE_VPD_FLAG) 366 break; 367 } 368 369 if (i == BGE_TIMEOUT) { 370 aprint_error_dev(sc->bge_dev, "VPD read timed out\n"); 371 return(0); 372 } 373 374 val = pci_conf_read(sc->sc_pc, sc->sca_pcitag, BGE_PCI_VPD_DATA); 375 376 return((val >> ((addr % 4) * 8)) & 0xFF); 377 } 378 379 static void 380 bge_vpd_read_res(struct bge_softc *sc, struct vpd_res *res, int addr) 381 { 382 int i; 383 u_int8_t *ptr; 384 385 ptr = (u_int8_t *)res; 386 for (i = 0; i < sizeof(struct vpd_res); i++) 387 ptr[i] = bge_vpd_readbyte(sc, i + addr); 388 } 389 390 static void 391 bge_vpd_read(struct bge_softc *sc) 392 { 393 int pos = 0, i; 394 struct vpd_res res; 395 396 if (sc->bge_vpd_prodname != NULL) 397 free(sc->bge_vpd_prodname, M_DEVBUF); 398 if (sc->bge_vpd_readonly != NULL) 399 free(sc->bge_vpd_readonly, M_DEVBUF); 400 sc->bge_vpd_prodname = NULL; 401 sc->bge_vpd_readonly = NULL; 402 403 bge_vpd_read_res(sc, &res, pos); 404 405 if (res.vr_id != VPD_RES_ID) { 406 aprint_error_dev("bad VPD resource id: expected %x got %x\n", 407 VPD_RES_ID, res.vr_id); 408 return; 409 } 410 411 pos += sizeof(res); 412 sc->bge_vpd_prodname = malloc(res.vr_len + 1, M_DEVBUF, M_NOWAIT); 413 if (sc->bge_vpd_prodname == NULL) 414 panic("bge_vpd_read"); 415 for (i = 0; i < res.vr_len; i++) 416 sc->bge_vpd_prodname[i] = bge_vpd_readbyte(sc, i + pos); 417 sc->bge_vpd_prodname[i] = '\0'; 418 pos += i; 419 420 bge_vpd_read_res(sc, &res, pos); 421 422 if (res.vr_id != VPD_RES_READ) { 423 aprint_error_dev(sc->bge_dev, 424 "bad VPD resource id: expected %x got %x\n", 425 VPD_RES_READ, res.vr_id); 426 return; 427 } 428 429 pos += sizeof(res); 430 sc->bge_vpd_readonly = malloc(res.vr_len, M_DEVBUF, M_NOWAIT); 431 if (sc->bge_vpd_readonly == NULL) 432 panic("bge_vpd_read"); 433 for (i = 0; i < res.vr_len + 1; i++) 434 sc->bge_vpd_readonly[i] = bge_vpd_readbyte(sc, i + pos); 435 } 436 #endif 437 438 static u_int8_t 439 bge_nvram_getbyte(struct bge_softc *sc, int addr, u_int8_t *dest) 440 { 441 u_int32_t access, byte = 0; 442 int i; 443 444 /* Lock. */ 445 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_SET1); 446 for (i = 0; i < 8000; i++) { 447 if (CSR_READ_4(sc, BGE_NVRAM_SWARB) & BGE_NVRAMSWARB_GNT1) 448 break; 449 DELAY(20); 450 } 451 if (i == 8000) 452 return (1); 453 454 /* Enable access. */ 455 access = CSR_READ_4(sc, BGE_NVRAM_ACCESS); 456 CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access | BGE_NVRAMACC_ENABLE); 457 458 CSR_WRITE_4(sc, BGE_NVRAM_ADDR, addr & 0xfffffffc); 459 CSR_WRITE_4(sc, BGE_NVRAM_CMD, BGE_NVRAM_READCMD); 460 for (i = 0; i < BGE_TIMEOUT * 10; i++) { 461 DELAY(10); 462 if (CSR_READ_4(sc, BGE_NVRAM_CMD) & BGE_NVRAMCMD_DONE) { 463 DELAY(10); 464 break; 465 } 466 } 467 468 if (i == BGE_TIMEOUT * 10) { 469 aprint_error_dev(sc->bge_dev, "nvram read timed out\n"); 470 return (1); 471 } 472 473 /* Get result. */ 474 byte = CSR_READ_4(sc, BGE_NVRAM_RDDATA); 475 476 *dest = (bswap32(byte) >> ((addr % 4) * 8)) & 0xFF; 477 478 /* Disable access. */ 479 CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access); 480 481 /* Unlock. */ 482 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_CLR1); 483 CSR_READ_4(sc, BGE_NVRAM_SWARB); 484 485 return (0); 486 } 487 488 /* 489 * Read a sequence of bytes from NVRAM. 490 */ 491 static int 492 bge_read_nvram(struct bge_softc *sc, u_int8_t *dest, int off, int cnt) 493 { 494 int err = 0, i; 495 u_int8_t byte = 0; 496 497 if (BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5906) 498 return (1); 499 500 for (i = 0; i < cnt; i++) { 501 err = bge_nvram_getbyte(sc, off + i, &byte); 502 if (err) 503 break; 504 *(dest + i) = byte; 505 } 506 507 return (err ? 1 : 0); 508 } 509 510 511 /* 512 * Read a byte of data stored in the EEPROM at address 'addr.' The 513 * BCM570x supports both the traditional bitbang interface and an 514 * auto access interface for reading the EEPROM. We use the auto 515 * access method. 516 */ 517 static u_int8_t 518 bge_eeprom_getbyte(struct bge_softc *sc, int addr, u_int8_t *dest) 519 { 520 int i; 521 u_int32_t byte = 0; 522 523 /* 524 * Enable use of auto EEPROM access so we can avoid 525 * having to use the bitbang method. 526 */ 527 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM); 528 529 /* Reset the EEPROM, load the clock period. */ 530 CSR_WRITE_4(sc, BGE_EE_ADDR, 531 BGE_EEADDR_RESET|BGE_EEHALFCLK(BGE_HALFCLK_384SCL)); 532 DELAY(20); 533 534 /* Issue the read EEPROM command. */ 535 CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr); 536 537 /* Wait for completion */ 538 for(i = 0; i < BGE_TIMEOUT * 10; i++) { 539 DELAY(10); 540 if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE) 541 break; 542 } 543 544 if (i == BGE_TIMEOUT) { 545 aprint_error_dev(sc->bge_dev, "eeprom read timed out\n"); 546 return(0); 547 } 548 549 /* Get result. */ 550 byte = CSR_READ_4(sc, BGE_EE_DATA); 551 552 *dest = (byte >> ((addr % 4) * 8)) & 0xFF; 553 554 return(0); 555 } 556 557 /* 558 * Read a sequence of bytes from the EEPROM. 559 */ 560 static int 561 bge_read_eeprom(struct bge_softc *sc, void *destv, int off, int cnt) 562 { 563 int err = 0, i; 564 u_int8_t byte = 0; 565 char *dest = destv; 566 567 for (i = 0; i < cnt; i++) { 568 err = bge_eeprom_getbyte(sc, off + i, &byte); 569 if (err) 570 break; 571 *(dest + i) = byte; 572 } 573 574 return(err ? 1 : 0); 575 } 576 577 static int 578 bge_miibus_readreg(device_t dev, int phy, int reg) 579 { 580 struct bge_softc *sc = device_private(dev); 581 u_int32_t val; 582 u_int32_t saved_autopoll; 583 int i; 584 585 /* 586 * Broadcom's own driver always assumes the internal 587 * PHY is at GMII address 1. On some chips, the PHY responds 588 * to accesses at all addresses, which could cause us to 589 * bogusly attach the PHY 32 times at probe type. Always 590 * restricting the lookup to address 1 is simpler than 591 * trying to figure out which chips revisions should be 592 * special-cased. 593 */ 594 if (phy != 1) 595 return (0); 596 597 /* Reading with autopolling on may trigger PCI errors */ 598 saved_autopoll = CSR_READ_4(sc, BGE_MI_MODE); 599 if (saved_autopoll & BGE_MIMODE_AUTOPOLL) { 600 CSR_WRITE_4(sc, BGE_MI_MODE, 601 saved_autopoll &~ BGE_MIMODE_AUTOPOLL); 602 DELAY(40); 603 } 604 605 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_READ|BGE_MICOMM_BUSY| 606 BGE_MIPHY(phy)|BGE_MIREG(reg)); 607 608 for (i = 0; i < BGE_TIMEOUT; i++) { 609 val = CSR_READ_4(sc, BGE_MI_COMM); 610 if (!(val & BGE_MICOMM_BUSY)) 611 break; 612 delay(10); 613 } 614 615 if (i == BGE_TIMEOUT) { 616 aprint_error_dev(sc->bge_dev, "PHY read timed out\n"); 617 val = 0; 618 goto done; 619 } 620 621 val = CSR_READ_4(sc, BGE_MI_COMM); 622 623 done: 624 if (saved_autopoll & BGE_MIMODE_AUTOPOLL) { 625 CSR_WRITE_4(sc, BGE_MI_MODE, saved_autopoll); 626 DELAY(40); 627 } 628 629 if (val & BGE_MICOMM_READFAIL) 630 return(0); 631 632 return(val & 0xFFFF); 633 } 634 635 static void 636 bge_miibus_writereg(device_t dev, int phy, int reg, int val) 637 { 638 struct bge_softc *sc = device_private(dev); 639 u_int32_t saved_autopoll; 640 int i; 641 642 if (phy!=1) { 643 return; 644 } 645 646 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906 && 647 (reg == BRGPHY_MII_1000CTL || reg == BRGPHY_MII_AUXCTL)) { 648 return; 649 } 650 651 /* Touching the PHY while autopolling is on may trigger PCI errors */ 652 saved_autopoll = CSR_READ_4(sc, BGE_MI_MODE); 653 if (saved_autopoll & BGE_MIMODE_AUTOPOLL) { 654 delay(40); 655 CSR_WRITE_4(sc, BGE_MI_MODE, 656 saved_autopoll & (~BGE_MIMODE_AUTOPOLL)); 657 delay(10); /* 40 usec is supposed to be adequate */ 658 } 659 660 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_WRITE|BGE_MICOMM_BUSY| 661 BGE_MIPHY(phy)|BGE_MIREG(reg)|val); 662 663 for (i = 0; i < BGE_TIMEOUT; i++) { 664 delay(10); 665 if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY)) { 666 delay(5); 667 CSR_READ_4(sc, BGE_MI_COMM); 668 break; 669 } 670 } 671 672 if (saved_autopoll & BGE_MIMODE_AUTOPOLL) { 673 CSR_WRITE_4(sc, BGE_MI_MODE, saved_autopoll); 674 delay(40); 675 } 676 677 if (i == BGE_TIMEOUT) 678 aprint_error_dev(sc->bge_dev, "PHY read timed out\n"); 679 } 680 681 static void 682 bge_miibus_statchg(device_t dev) 683 { 684 struct bge_softc *sc = device_private(dev); 685 struct mii_data *mii = &sc->bge_mii; 686 687 /* 688 * Get flow control negotiation result. 689 */ 690 if (IFM_SUBTYPE(mii->mii_media.ifm_cur->ifm_media) == IFM_AUTO && 691 (mii->mii_media_active & IFM_ETH_FMASK) != sc->bge_flowflags) { 692 sc->bge_flowflags = mii->mii_media_active & IFM_ETH_FMASK; 693 mii->mii_media_active &= ~IFM_ETH_FMASK; 694 } 695 696 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_PORTMODE); 697 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) { 698 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_GMII); 699 } else { 700 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_MII); 701 } 702 703 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 704 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX); 705 } else { 706 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX); 707 } 708 709 /* 710 * 802.3x flow control 711 */ 712 if (sc->bge_flowflags & IFM_ETH_RXPAUSE) { 713 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_FLOWCTL_ENABLE); 714 } else { 715 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_FLOWCTL_ENABLE); 716 } 717 if (sc->bge_flowflags & IFM_ETH_TXPAUSE) { 718 BGE_SETBIT(sc, BGE_TX_MODE, BGE_TXMODE_FLOWCTL_ENABLE); 719 } else { 720 BGE_CLRBIT(sc, BGE_TX_MODE, BGE_TXMODE_FLOWCTL_ENABLE); 721 } 722 } 723 724 /* 725 * Update rx threshold levels to values in a particular slot 726 * of the interrupt-mitigation table bge_rx_threshes. 727 */ 728 static void 729 bge_set_thresh(struct ifnet *ifp, int lvl) 730 { 731 struct bge_softc *sc = ifp->if_softc; 732 int s; 733 734 /* For now, just save the new Rx-intr thresholds and record 735 * that a threshold update is pending. Updating the hardware 736 * registers here (even at splhigh()) is observed to 737 * occasionaly cause glitches where Rx-interrupts are not 738 * honoured for up to 10 seconds. jonathan (at) NetBSD.org, 2003-04-05 739 */ 740 s = splnet(); 741 sc->bge_rx_coal_ticks = bge_rx_threshes[lvl].rx_ticks; 742 sc->bge_rx_max_coal_bds = bge_rx_threshes[lvl].rx_max_bds; 743 sc->bge_pending_rxintr_change = 1; 744 splx(s); 745 746 return; 747 } 748 749 750 /* 751 * Update Rx thresholds of all bge devices 752 */ 753 static void 754 bge_update_all_threshes(int lvl) 755 { 756 struct ifnet *ifp; 757 const char * const namebuf = "bge"; 758 int namelen; 759 760 if (lvl < 0) 761 lvl = 0; 762 else if( lvl >= NBGE_RX_THRESH) 763 lvl = NBGE_RX_THRESH - 1; 764 765 namelen = strlen(namebuf); 766 /* 767 * Now search all the interfaces for this name/number 768 */ 769 IFNET_FOREACH(ifp) { 770 if (strncmp(ifp->if_xname, namebuf, namelen) != 0) 771 continue; 772 /* We got a match: update if doing auto-threshold-tuning */ 773 if (bge_auto_thresh) 774 bge_set_thresh(ifp, lvl); 775 } 776 } 777 778 /* 779 * Handle events that have triggered interrupts. 780 */ 781 static void 782 bge_handle_events(struct bge_softc *sc) 783 { 784 785 return; 786 } 787 788 /* 789 * Memory management for jumbo frames. 790 */ 791 792 static int 793 bge_alloc_jumbo_mem(struct bge_softc *sc) 794 { 795 char *ptr, *kva; 796 bus_dma_segment_t seg; 797 int i, rseg, state, error; 798 struct bge_jpool_entry *entry; 799 800 state = error = 0; 801 802 /* Grab a big chunk o' storage. */ 803 if (bus_dmamem_alloc(sc->bge_dmatag, BGE_JMEM, PAGE_SIZE, 0, 804 &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 805 aprint_error_dev(sc->bge_dev, "can't alloc rx buffers\n"); 806 return ENOBUFS; 807 } 808 809 state = 1; 810 if (bus_dmamem_map(sc->bge_dmatag, &seg, rseg, BGE_JMEM, (void **)&kva, 811 BUS_DMA_NOWAIT)) { 812 aprint_error_dev(sc->bge_dev, 813 "can't map DMA buffers (%d bytes)\n", (int)BGE_JMEM); 814 error = ENOBUFS; 815 goto out; 816 } 817 818 state = 2; 819 if (bus_dmamap_create(sc->bge_dmatag, BGE_JMEM, 1, BGE_JMEM, 0, 820 BUS_DMA_NOWAIT, &sc->bge_cdata.bge_rx_jumbo_map)) { 821 aprint_error_dev(sc->bge_dev, "can't create DMA map\n"); 822 error = ENOBUFS; 823 goto out; 824 } 825 826 state = 3; 827 if (bus_dmamap_load(sc->bge_dmatag, sc->bge_cdata.bge_rx_jumbo_map, 828 kva, BGE_JMEM, NULL, BUS_DMA_NOWAIT)) { 829 aprint_error_dev(sc->bge_dev, "can't load DMA map\n"); 830 error = ENOBUFS; 831 goto out; 832 } 833 834 state = 4; 835 sc->bge_cdata.bge_jumbo_buf = (void *)kva; 836 DPRINTFN(1,("bge_jumbo_buf = %p\n", sc->bge_cdata.bge_jumbo_buf)); 837 838 SLIST_INIT(&sc->bge_jfree_listhead); 839 SLIST_INIT(&sc->bge_jinuse_listhead); 840 841 /* 842 * Now divide it up into 9K pieces and save the addresses 843 * in an array. 844 */ 845 ptr = sc->bge_cdata.bge_jumbo_buf; 846 for (i = 0; i < BGE_JSLOTS; i++) { 847 sc->bge_cdata.bge_jslots[i] = ptr; 848 ptr += BGE_JLEN; 849 entry = malloc(sizeof(struct bge_jpool_entry), 850 M_DEVBUF, M_NOWAIT); 851 if (entry == NULL) { 852 aprint_error_dev(sc->bge_dev, 853 "no memory for jumbo buffer queue!\n"); 854 error = ENOBUFS; 855 goto out; 856 } 857 entry->slot = i; 858 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, 859 entry, jpool_entries); 860 } 861 out: 862 if (error != 0) { 863 switch (state) { 864 case 4: 865 bus_dmamap_unload(sc->bge_dmatag, 866 sc->bge_cdata.bge_rx_jumbo_map); 867 case 3: 868 bus_dmamap_destroy(sc->bge_dmatag, 869 sc->bge_cdata.bge_rx_jumbo_map); 870 case 2: 871 bus_dmamem_unmap(sc->bge_dmatag, kva, BGE_JMEM); 872 case 1: 873 bus_dmamem_free(sc->bge_dmatag, &seg, rseg); 874 break; 875 default: 876 break; 877 } 878 } 879 880 return error; 881 } 882 883 /* 884 * Allocate a jumbo buffer. 885 */ 886 static void * 887 bge_jalloc(struct bge_softc *sc) 888 { 889 struct bge_jpool_entry *entry; 890 891 entry = SLIST_FIRST(&sc->bge_jfree_listhead); 892 893 if (entry == NULL) { 894 aprint_error_dev(sc->bge_dev, "no free jumbo buffers\n"); 895 return(NULL); 896 } 897 898 SLIST_REMOVE_HEAD(&sc->bge_jfree_listhead, jpool_entries); 899 SLIST_INSERT_HEAD(&sc->bge_jinuse_listhead, entry, jpool_entries); 900 return(sc->bge_cdata.bge_jslots[entry->slot]); 901 } 902 903 /* 904 * Release a jumbo buffer. 905 */ 906 static void 907 bge_jfree(struct mbuf *m, void *buf, size_t size, void *arg) 908 { 909 struct bge_jpool_entry *entry; 910 struct bge_softc *sc; 911 int i, s; 912 913 /* Extract the softc struct pointer. */ 914 sc = (struct bge_softc *)arg; 915 916 if (sc == NULL) 917 panic("bge_jfree: can't find softc pointer!"); 918 919 /* calculate the slot this buffer belongs to */ 920 921 i = ((char *)buf 922 - (char *)sc->bge_cdata.bge_jumbo_buf) / BGE_JLEN; 923 924 if ((i < 0) || (i >= BGE_JSLOTS)) 925 panic("bge_jfree: asked to free buffer that we don't manage!"); 926 927 s = splvm(); 928 entry = SLIST_FIRST(&sc->bge_jinuse_listhead); 929 if (entry == NULL) 930 panic("bge_jfree: buffer not in use!"); 931 entry->slot = i; 932 SLIST_REMOVE_HEAD(&sc->bge_jinuse_listhead, jpool_entries); 933 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, entry, jpool_entries); 934 935 if (__predict_true(m != NULL)) 936 pool_cache_put(mb_cache, m); 937 splx(s); 938 } 939 940 941 /* 942 * Intialize a standard receive ring descriptor. 943 */ 944 static int 945 bge_newbuf_std(struct bge_softc *sc, int i, struct mbuf *m, bus_dmamap_t dmamap) 946 { 947 struct mbuf *m_new = NULL; 948 struct bge_rx_bd *r; 949 int error; 950 951 if (dmamap == NULL) { 952 error = bus_dmamap_create(sc->bge_dmatag, MCLBYTES, 1, 953 MCLBYTES, 0, BUS_DMA_NOWAIT, &dmamap); 954 if (error != 0) 955 return error; 956 } 957 958 sc->bge_cdata.bge_rx_std_map[i] = dmamap; 959 960 if (m == NULL) { 961 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 962 if (m_new == NULL) { 963 return(ENOBUFS); 964 } 965 966 MCLGET(m_new, M_DONTWAIT); 967 if (!(m_new->m_flags & M_EXT)) { 968 m_freem(m_new); 969 return(ENOBUFS); 970 } 971 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 972 973 } else { 974 m_new = m; 975 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 976 m_new->m_data = m_new->m_ext.ext_buf; 977 } 978 if (!sc->bge_rx_alignment_bug) 979 m_adj(m_new, ETHER_ALIGN); 980 if (bus_dmamap_load_mbuf(sc->bge_dmatag, dmamap, m_new, 981 BUS_DMA_READ|BUS_DMA_NOWAIT)) 982 return(ENOBUFS); 983 bus_dmamap_sync(sc->bge_dmatag, dmamap, 0, dmamap->dm_mapsize, 984 BUS_DMASYNC_PREREAD); 985 986 sc->bge_cdata.bge_rx_std_chain[i] = m_new; 987 r = &sc->bge_rdata->bge_rx_std_ring[i]; 988 bge_set_hostaddr(&r->bge_addr, 989 dmamap->dm_segs[0].ds_addr); 990 r->bge_flags = BGE_RXBDFLAG_END; 991 r->bge_len = m_new->m_len; 992 r->bge_idx = i; 993 994 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 995 offsetof(struct bge_ring_data, bge_rx_std_ring) + 996 i * sizeof (struct bge_rx_bd), 997 sizeof (struct bge_rx_bd), 998 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 999 1000 return(0); 1001 } 1002 1003 /* 1004 * Initialize a jumbo receive ring descriptor. This allocates 1005 * a jumbo buffer from the pool managed internally by the driver. 1006 */ 1007 static int 1008 bge_newbuf_jumbo(struct bge_softc *sc, int i, struct mbuf *m) 1009 { 1010 struct mbuf *m_new = NULL; 1011 struct bge_rx_bd *r; 1012 void *buf = NULL; 1013 1014 if (m == NULL) { 1015 1016 /* Allocate the mbuf. */ 1017 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1018 if (m_new == NULL) { 1019 return(ENOBUFS); 1020 } 1021 1022 /* Allocate the jumbo buffer */ 1023 buf = bge_jalloc(sc); 1024 if (buf == NULL) { 1025 m_freem(m_new); 1026 aprint_error_dev(sc->bge_dev, 1027 "jumbo allocation failed -- packet dropped!\n"); 1028 return(ENOBUFS); 1029 } 1030 1031 /* Attach the buffer to the mbuf. */ 1032 m_new->m_len = m_new->m_pkthdr.len = BGE_JUMBO_FRAMELEN; 1033 MEXTADD(m_new, buf, BGE_JUMBO_FRAMELEN, M_DEVBUF, 1034 bge_jfree, sc); 1035 m_new->m_flags |= M_EXT_RW; 1036 } else { 1037 m_new = m; 1038 buf = m_new->m_data = m_new->m_ext.ext_buf; 1039 m_new->m_ext.ext_size = BGE_JUMBO_FRAMELEN; 1040 } 1041 if (!sc->bge_rx_alignment_bug) 1042 m_adj(m_new, ETHER_ALIGN); 1043 bus_dmamap_sync(sc->bge_dmatag, sc->bge_cdata.bge_rx_jumbo_map, 1044 mtod(m_new, char *) - (char *)sc->bge_cdata.bge_jumbo_buf, BGE_JLEN, 1045 BUS_DMASYNC_PREREAD); 1046 /* Set up the descriptor. */ 1047 r = &sc->bge_rdata->bge_rx_jumbo_ring[i]; 1048 sc->bge_cdata.bge_rx_jumbo_chain[i] = m_new; 1049 bge_set_hostaddr(&r->bge_addr, BGE_JUMBO_DMA_ADDR(sc, m_new)); 1050 r->bge_flags = BGE_RXBDFLAG_END|BGE_RXBDFLAG_JUMBO_RING; 1051 r->bge_len = m_new->m_len; 1052 r->bge_idx = i; 1053 1054 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 1055 offsetof(struct bge_ring_data, bge_rx_jumbo_ring) + 1056 i * sizeof (struct bge_rx_bd), 1057 sizeof (struct bge_rx_bd), 1058 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1059 1060 return(0); 1061 } 1062 1063 /* 1064 * The standard receive ring has 512 entries in it. At 2K per mbuf cluster, 1065 * that's 1MB or memory, which is a lot. For now, we fill only the first 1066 * 256 ring entries and hope that our CPU is fast enough to keep up with 1067 * the NIC. 1068 */ 1069 static int 1070 bge_init_rx_ring_std(struct bge_softc *sc) 1071 { 1072 int i; 1073 1074 if (sc->bge_flags & BGE_RXRING_VALID) 1075 return 0; 1076 1077 for (i = 0; i < BGE_SSLOTS; i++) { 1078 if (bge_newbuf_std(sc, i, NULL, 0) == ENOBUFS) 1079 return(ENOBUFS); 1080 } 1081 1082 sc->bge_std = i - 1; 1083 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std); 1084 1085 sc->bge_flags |= BGE_RXRING_VALID; 1086 1087 return(0); 1088 } 1089 1090 static void 1091 bge_free_rx_ring_std(struct bge_softc *sc) 1092 { 1093 int i; 1094 1095 if (!(sc->bge_flags & BGE_RXRING_VALID)) 1096 return; 1097 1098 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { 1099 if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) { 1100 m_freem(sc->bge_cdata.bge_rx_std_chain[i]); 1101 sc->bge_cdata.bge_rx_std_chain[i] = NULL; 1102 bus_dmamap_destroy(sc->bge_dmatag, 1103 sc->bge_cdata.bge_rx_std_map[i]); 1104 } 1105 memset((char *)&sc->bge_rdata->bge_rx_std_ring[i], 0, 1106 sizeof(struct bge_rx_bd)); 1107 } 1108 1109 sc->bge_flags &= ~BGE_RXRING_VALID; 1110 } 1111 1112 static int 1113 bge_init_rx_ring_jumbo(struct bge_softc *sc) 1114 { 1115 int i; 1116 volatile struct bge_rcb *rcb; 1117 1118 if (sc->bge_flags & BGE_JUMBO_RXRING_VALID) 1119 return 0; 1120 1121 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 1122 if (bge_newbuf_jumbo(sc, i, NULL) == ENOBUFS) 1123 return(ENOBUFS); 1124 }; 1125 1126 sc->bge_jumbo = i - 1; 1127 sc->bge_flags |= BGE_JUMBO_RXRING_VALID; 1128 1129 rcb = &sc->bge_rdata->bge_info.bge_jumbo_rx_rcb; 1130 rcb->bge_maxlen_flags = 0; 1131 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 1132 1133 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo); 1134 1135 return(0); 1136 } 1137 1138 static void 1139 bge_free_rx_ring_jumbo(struct bge_softc *sc) 1140 { 1141 int i; 1142 1143 if (!(sc->bge_flags & BGE_JUMBO_RXRING_VALID)) 1144 return; 1145 1146 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 1147 if (sc->bge_cdata.bge_rx_jumbo_chain[i] != NULL) { 1148 m_freem(sc->bge_cdata.bge_rx_jumbo_chain[i]); 1149 sc->bge_cdata.bge_rx_jumbo_chain[i] = NULL; 1150 } 1151 memset((char *)&sc->bge_rdata->bge_rx_jumbo_ring[i], 0, 1152 sizeof(struct bge_rx_bd)); 1153 } 1154 1155 sc->bge_flags &= ~BGE_JUMBO_RXRING_VALID; 1156 } 1157 1158 static void 1159 bge_free_tx_ring(struct bge_softc *sc) 1160 { 1161 int i, freed; 1162 struct txdmamap_pool_entry *dma; 1163 1164 if (!(sc->bge_flags & BGE_TXRING_VALID)) 1165 return; 1166 1167 freed = 0; 1168 1169 for (i = 0; i < BGE_TX_RING_CNT; i++) { 1170 if (sc->bge_cdata.bge_tx_chain[i] != NULL) { 1171 freed++; 1172 m_freem(sc->bge_cdata.bge_tx_chain[i]); 1173 sc->bge_cdata.bge_tx_chain[i] = NULL; 1174 SLIST_INSERT_HEAD(&sc->txdma_list, sc->txdma[i], 1175 link); 1176 sc->txdma[i] = 0; 1177 } 1178 memset((char *)&sc->bge_rdata->bge_tx_ring[i], 0, 1179 sizeof(struct bge_tx_bd)); 1180 } 1181 1182 while ((dma = SLIST_FIRST(&sc->txdma_list))) { 1183 SLIST_REMOVE_HEAD(&sc->txdma_list, link); 1184 bus_dmamap_destroy(sc->bge_dmatag, dma->dmamap); 1185 free(dma, M_DEVBUF); 1186 } 1187 1188 sc->bge_flags &= ~BGE_TXRING_VALID; 1189 } 1190 1191 static int 1192 bge_init_tx_ring(struct bge_softc *sc) 1193 { 1194 int i; 1195 bus_dmamap_t dmamap; 1196 struct txdmamap_pool_entry *dma; 1197 1198 if (sc->bge_flags & BGE_TXRING_VALID) 1199 return 0; 1200 1201 sc->bge_txcnt = 0; 1202 sc->bge_tx_saved_considx = 0; 1203 1204 /* Initialize transmit producer index for host-memory send ring. */ 1205 sc->bge_tx_prodidx = 0; 1206 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx); 1207 if (sc->bge_quirks & BGE_QUIRK_PRODUCER_BUG) /* 5700 b2 errata */ 1208 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx); 1209 1210 /* NIC-memory send ring not used; initialize to zero. */ 1211 bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0); 1212 if (sc->bge_quirks & BGE_QUIRK_PRODUCER_BUG) /* 5700 b2 errata */ 1213 bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0); 1214 1215 SLIST_INIT(&sc->txdma_list); 1216 for (i = 0; i < BGE_RSLOTS; i++) { 1217 if (bus_dmamap_create(sc->bge_dmatag, BGE_TXDMA_MAX, 1218 BGE_NTXSEG, ETHER_MAX_LEN_JUMBO, 0, BUS_DMA_NOWAIT, 1219 &dmamap)) 1220 return(ENOBUFS); 1221 if (dmamap == NULL) 1222 panic("dmamap NULL in bge_init_tx_ring"); 1223 dma = malloc(sizeof(*dma), M_DEVBUF, M_NOWAIT); 1224 if (dma == NULL) { 1225 aprint_error_dev(sc->bge_dev, 1226 "can't alloc txdmamap_pool_entry\n"); 1227 bus_dmamap_destroy(sc->bge_dmatag, dmamap); 1228 return (ENOMEM); 1229 } 1230 dma->dmamap = dmamap; 1231 SLIST_INSERT_HEAD(&sc->txdma_list, dma, link); 1232 } 1233 1234 sc->bge_flags |= BGE_TXRING_VALID; 1235 1236 return(0); 1237 } 1238 1239 static void 1240 bge_setmulti(struct bge_softc *sc) 1241 { 1242 struct ethercom *ac = &sc->ethercom; 1243 struct ifnet *ifp = &ac->ec_if; 1244 struct ether_multi *enm; 1245 struct ether_multistep step; 1246 u_int32_t hashes[4] = { 0, 0, 0, 0 }; 1247 u_int32_t h; 1248 int i; 1249 1250 if (ifp->if_flags & IFF_PROMISC) 1251 goto allmulti; 1252 1253 /* Now program new ones. */ 1254 ETHER_FIRST_MULTI(step, ac, enm); 1255 while (enm != NULL) { 1256 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1257 /* 1258 * We must listen to a range of multicast addresses. 1259 * For now, just accept all multicasts, rather than 1260 * trying to set only those filter bits needed to match 1261 * the range. (At this time, the only use of address 1262 * ranges is for IP multicast routing, for which the 1263 * range is big enough to require all bits set.) 1264 */ 1265 goto allmulti; 1266 } 1267 1268 h = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN); 1269 1270 /* Just want the 7 least-significant bits. */ 1271 h &= 0x7f; 1272 1273 hashes[(h & 0x60) >> 5] |= 1 << (h & 0x1F); 1274 ETHER_NEXT_MULTI(step, enm); 1275 } 1276 1277 ifp->if_flags &= ~IFF_ALLMULTI; 1278 goto setit; 1279 1280 allmulti: 1281 ifp->if_flags |= IFF_ALLMULTI; 1282 hashes[0] = hashes[1] = hashes[2] = hashes[3] = 0xffffffff; 1283 1284 setit: 1285 for (i = 0; i < 4; i++) 1286 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]); 1287 } 1288 1289 const int bge_swapbits[] = { 1290 0, 1291 BGE_MODECTL_BYTESWAP_DATA, 1292 BGE_MODECTL_WORDSWAP_DATA, 1293 BGE_MODECTL_BYTESWAP_NONFRAME, 1294 BGE_MODECTL_WORDSWAP_NONFRAME, 1295 1296 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA, 1297 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_BYTESWAP_NONFRAME, 1298 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_NONFRAME, 1299 1300 BGE_MODECTL_WORDSWAP_DATA|BGE_MODECTL_BYTESWAP_NONFRAME, 1301 BGE_MODECTL_WORDSWAP_DATA|BGE_MODECTL_WORDSWAP_NONFRAME, 1302 1303 BGE_MODECTL_BYTESWAP_NONFRAME|BGE_MODECTL_WORDSWAP_NONFRAME, 1304 1305 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA| 1306 BGE_MODECTL_BYTESWAP_NONFRAME, 1307 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA| 1308 BGE_MODECTL_WORDSWAP_NONFRAME, 1309 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_BYTESWAP_NONFRAME| 1310 BGE_MODECTL_WORDSWAP_NONFRAME, 1311 BGE_MODECTL_WORDSWAP_DATA|BGE_MODECTL_BYTESWAP_NONFRAME| 1312 BGE_MODECTL_WORDSWAP_NONFRAME, 1313 1314 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA| 1315 BGE_MODECTL_BYTESWAP_NONFRAME|BGE_MODECTL_WORDSWAP_NONFRAME, 1316 }; 1317 1318 int bge_swapindex = 0; 1319 1320 /* 1321 * Do endian, PCI and DMA initialization. Also check the on-board ROM 1322 * self-test results. 1323 */ 1324 static int 1325 bge_chipinit(struct bge_softc *sc) 1326 { 1327 u_int32_t cachesize; 1328 int i; 1329 u_int32_t dma_rw_ctl; 1330 1331 1332 /* Set endianness before we access any non-PCI registers. */ 1333 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MISC_CTL, 1334 BGE_INIT); 1335 1336 /* Set power state to D0. */ 1337 bge_setpowerstate(sc, 0); 1338 1339 /* 1340 * Check the 'ROM failed' bit on the RX CPU to see if 1341 * self-tests passed. 1342 */ 1343 if (CSR_READ_4(sc, BGE_RXCPU_MODE) & BGE_RXCPUMODE_ROMFAIL) { 1344 aprint_error_dev(sc->bge_dev, 1345 "RX CPU self-diagnostics failed!\n"); 1346 return(ENODEV); 1347 } 1348 1349 /* Clear the MAC control register */ 1350 CSR_WRITE_4(sc, BGE_MAC_MODE, 0); 1351 1352 /* 1353 * Clear the MAC statistics block in the NIC's 1354 * internal memory. 1355 */ 1356 for (i = BGE_STATS_BLOCK; 1357 i < BGE_STATS_BLOCK_END + 1; i += sizeof(u_int32_t)) 1358 BGE_MEMWIN_WRITE(sc->sc_pc, sc->sc_pcitag, i, 0); 1359 1360 for (i = BGE_STATUS_BLOCK; 1361 i < BGE_STATUS_BLOCK_END + 1; i += sizeof(u_int32_t)) 1362 BGE_MEMWIN_WRITE(sc->sc_pc, sc->sc_pcitag, i, 0); 1363 1364 /* Set up the PCI DMA control register. */ 1365 if (sc->bge_pcie) { 1366 u_int32_t device_ctl; 1367 1368 /* From FreeBSD */ 1369 DPRINTFN(4, ("(%s: PCI-Express DMA setting)\n", 1370 device_xname(sc->bge_dev))); 1371 dma_rw_ctl = (BGE_PCI_READ_CMD | BGE_PCI_WRITE_CMD | 1372 (0xf << BGE_PCIDMARWCTL_RD_WAT_SHIFT) | 1373 (0x2 << BGE_PCIDMARWCTL_WR_WAT_SHIFT)); 1374 1375 /* jonathan: alternative from Linux driver */ 1376 #define DMA_CTRL_WRITE_PCIE_H20MARK_128 0x00180000 1377 #define DMA_CTRL_WRITE_PCIE_H20MARK_256 0x00380000 1378 1379 dma_rw_ctl = 0x76000000; /* XXX XXX XXX */; 1380 device_ctl = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 1381 BGE_PCI_CONF_DEV_CTRL); 1382 aprint_debug_dev(sc->bge_dev, "pcie mode=0x%x\n", device_ctl); 1383 1384 if ((device_ctl & 0x00e0) && 0) { 1385 /* 1386 * XXX jonathan (at) NetBSD.org: 1387 * This clause is exactly what the Broadcom-supplied 1388 * Linux does; but given overall register programming 1389 * by if_bge(4), this larger DMA-write watermark 1390 * value causes bcm5721 chips to totally wedge. 1391 */ 1392 dma_rw_ctl |= BGE_PCIDMA_RWCTL_PCIE_WRITE_WATRMARK_256; 1393 } else { 1394 dma_rw_ctl |= BGE_PCIDMA_RWCTL_PCIE_WRITE_WATRMARK_128; 1395 } 1396 } else if (pci_conf_read(sc->sc_pc, sc->sc_pcitag,BGE_PCI_PCISTATE) & 1397 BGE_PCISTATE_PCI_BUSMODE) { 1398 /* Conventional PCI bus */ 1399 DPRINTFN(4, ("(%s: PCI 2.2 DMA setting)\n", 1400 device_xname(sc->bge_dev))); 1401 dma_rw_ctl = (BGE_PCI_READ_CMD | BGE_PCI_WRITE_CMD | 1402 (0x7 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) | 1403 (0x7 << BGE_PCIDMARWCTL_WR_WAT_SHIFT)); 1404 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 1405 dma_rw_ctl |= 0x0F; 1406 } 1407 } else { 1408 DPRINTFN(4, ("(:%s: PCI-X DMA setting)\n", 1409 device_xname(sc->bge_dev))); 1410 /* PCI-X bus */ 1411 dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD | 1412 (0x3 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) | 1413 (0x3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT) | 1414 (0x0F); 1415 /* 1416 * 5703 and 5704 need ONEDMA_AT_ONCE as a workaround 1417 * for hardware bugs, which means we should also clear 1418 * the low-order MINDMA bits. In addition, the 5704 1419 * uses a different encoding of read/write watermarks. 1420 */ 1421 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) { 1422 dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD | 1423 /* should be 0x1f0000 */ 1424 (0x7 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) | 1425 (0x3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT); 1426 dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE; 1427 } 1428 else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5703) { 1429 dma_rw_ctl &= 0xfffffff0; 1430 dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE; 1431 } 1432 else if (BGE_IS_5714_FAMILY(sc)) { 1433 dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD; 1434 dma_rw_ctl &= ~BGE_PCIDMARWCTL_ONEDMA_ATONCE; /* XXX */ 1435 /* XXX magic values, Broadcom-supplied Linux driver */ 1436 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5780) 1437 dma_rw_ctl |= (1 << 20) | (1 << 18) | 1438 BGE_PCIDMARWCTL_ONEDMA_ATONCE; 1439 else 1440 dma_rw_ctl |= (1<<20) | (1<<18) | (1 << 15); 1441 } 1442 } 1443 1444 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_DMA_RW_CTL, dma_rw_ctl); 1445 1446 /* 1447 * Set up general mode register. 1448 */ 1449 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS| 1450 BGE_MODECTL_MAC_ATTN_INTR|BGE_MODECTL_HOST_SEND_BDS| 1451 BGE_MODECTL_TX_NO_PHDR_CSUM|BGE_MODECTL_RX_NO_PHDR_CSUM); 1452 1453 /* Get cache line size. */ 1454 cachesize = pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CACHESZ); 1455 1456 /* 1457 * Avoid violating PCI spec on certain chip revs. 1458 */ 1459 if (pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CMD) & 1460 PCIM_CMD_MWIEN) { 1461 switch(cachesize) { 1462 case 1: 1463 PCI_SETBIT(sc->sc_pc, sc->sc_pcitag, BGE_PCI_DMA_RW_CTL, 1464 BGE_PCI_WRITE_BNDRY_16BYTES); 1465 break; 1466 case 2: 1467 PCI_SETBIT(sc->sc_pc, sc->sc_pcitag, BGE_PCI_DMA_RW_CTL, 1468 BGE_PCI_WRITE_BNDRY_32BYTES); 1469 break; 1470 case 4: 1471 PCI_SETBIT(sc->sc_pc, sc->sc_pcitag, BGE_PCI_DMA_RW_CTL, 1472 BGE_PCI_WRITE_BNDRY_64BYTES); 1473 break; 1474 case 8: 1475 PCI_SETBIT(sc->sc_pc, sc->sc_pcitag, BGE_PCI_DMA_RW_CTL, 1476 BGE_PCI_WRITE_BNDRY_128BYTES); 1477 break; 1478 case 16: 1479 PCI_SETBIT(sc->sc_pc, sc->sc_pcitag, BGE_PCI_DMA_RW_CTL, 1480 BGE_PCI_WRITE_BNDRY_256BYTES); 1481 break; 1482 case 32: 1483 PCI_SETBIT(sc->sc_pc, sc->sc_pcitag, BGE_PCI_DMA_RW_CTL, 1484 BGE_PCI_WRITE_BNDRY_512BYTES); 1485 break; 1486 case 64: 1487 PCI_SETBIT(sc->sc_pc, sc->sc_pcitag, BGE_PCI_DMA_RW_CTL, 1488 BGE_PCI_WRITE_BNDRY_1024BYTES); 1489 break; 1490 default: 1491 /* Disable PCI memory write and invalidate. */ 1492 #if 0 1493 if (bootverbose) 1494 aprint_error_dev(sc->bge_dev, 1495 "cache line size %d not supported " 1496 "disabling PCI MWI\n", 1497 #endif 1498 PCI_CLRBIT(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CMD, 1499 PCIM_CMD_MWIEN); 1500 break; 1501 } 1502 } 1503 1504 /* 1505 * Disable memory write invalidate. Apparently it is not supported 1506 * properly by these devices. 1507 */ 1508 PCI_CLRBIT(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CMD, PCIM_CMD_MWIEN); 1509 1510 1511 #ifdef __brokenalpha__ 1512 /* 1513 * Must insure that we do not cross an 8K (bytes) boundary 1514 * for DMA reads. Our highest limit is 1K bytes. This is a 1515 * restriction on some ALPHA platforms with early revision 1516 * 21174 PCI chipsets, such as the AlphaPC 164lx 1517 */ 1518 PCI_SETBIT(sc, BGE_PCI_DMA_RW_CTL, BGE_PCI_READ_BNDRY_1024, 4); 1519 #endif 1520 1521 /* Set the timer prescaler (always 66MHz) */ 1522 CSR_WRITE_4(sc, BGE_MISC_CFG, 65 << 1/*BGE_32BITTIME_66MHZ*/); 1523 1524 return(0); 1525 } 1526 1527 static int 1528 bge_blockinit(struct bge_softc *sc) 1529 { 1530 volatile struct bge_rcb *rcb; 1531 bus_size_t rcb_addr; 1532 int i; 1533 struct ifnet *ifp = &sc->ethercom.ec_if; 1534 bge_hostaddr taddr; 1535 1536 /* 1537 * Initialize the memory window pointer register so that 1538 * we can access the first 32K of internal NIC RAM. This will 1539 * allow us to set up the TX send ring RCBs and the RX return 1540 * ring RCBs, plus other things which live in NIC memory. 1541 */ 1542 1543 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_BASEADDR, 0); 1544 1545 /* Configure mbuf memory pool */ 1546 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 1547 if (sc->bge_extram) { 1548 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, 1549 BGE_EXT_SSRAM); 1550 if ((sc->bge_quirks & BGE_QUIRK_FEWER_MBUFS) != 0) 1551 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000); 1552 else 1553 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000); 1554 } else { 1555 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, 1556 BGE_BUFFPOOL_1); 1557 if ((sc->bge_quirks & BGE_QUIRK_FEWER_MBUFS) != 0) 1558 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000); 1559 else 1560 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000); 1561 } 1562 1563 /* Configure DMA resource pool */ 1564 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_BASEADDR, 1565 BGE_DMA_DESCRIPTORS); 1566 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LEN, 0x2000); 1567 } 1568 1569 /* Configure mbuf pool watermarks */ 1570 #ifdef ORIG_WPAUL_VALUES 1571 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 24); 1572 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 24); 1573 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 48); 1574 #else 1575 1576 /* new broadcom docs strongly recommend these: */ 1577 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 1578 if (ifp->if_mtu > ETHER_MAX_LEN) { 1579 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x50); 1580 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x20); 1581 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60); 1582 } else { 1583 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 304); 1584 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 152); 1585 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 380); 1586 } 1587 } else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 1588 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0); 1589 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x04); 1590 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x10); 1591 } else { 1592 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0); 1593 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x10); 1594 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60); 1595 } 1596 #endif 1597 1598 /* Configure DMA resource watermarks */ 1599 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5); 1600 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10); 1601 1602 /* Enable buffer manager */ 1603 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 1604 CSR_WRITE_4(sc, BGE_BMAN_MODE, 1605 BGE_BMANMODE_ENABLE|BGE_BMANMODE_LOMBUF_ATTN); 1606 1607 /* Poll for buffer manager start indication */ 1608 for (i = 0; i < BGE_TIMEOUT; i++) { 1609 if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE) 1610 break; 1611 DELAY(10); 1612 } 1613 1614 if (i == BGE_TIMEOUT) { 1615 aprint_error_dev(sc->bge_dev, 1616 "buffer manager failed to start\n"); 1617 return(ENXIO); 1618 } 1619 } 1620 1621 /* Enable flow-through queues */ 1622 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 1623 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 1624 1625 /* Wait until queue initialization is complete */ 1626 for (i = 0; i < BGE_TIMEOUT; i++) { 1627 if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0) 1628 break; 1629 DELAY(10); 1630 } 1631 1632 if (i == BGE_TIMEOUT) { 1633 aprint_error_dev(sc->bge_dev, 1634 "flow-through queue init failed\n"); 1635 return(ENXIO); 1636 } 1637 1638 /* Initialize the standard RX ring control block */ 1639 rcb = &sc->bge_rdata->bge_info.bge_std_rx_rcb; 1640 bge_set_hostaddr(&rcb->bge_hostaddr, 1641 BGE_RING_DMA_ADDR(sc, bge_rx_std_ring)); 1642 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 1643 rcb->bge_maxlen_flags = 1644 BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 0); 1645 } else { 1646 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(512, 0); 1647 } 1648 if (sc->bge_extram) 1649 rcb->bge_nicaddr = BGE_EXT_STD_RX_RINGS; 1650 else 1651 rcb->bge_nicaddr = BGE_STD_RX_RINGS; 1652 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcb->bge_hostaddr.bge_addr_hi); 1653 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcb->bge_hostaddr.bge_addr_lo); 1654 CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 1655 CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcb->bge_nicaddr); 1656 1657 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 1658 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT; 1659 } else { 1660 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT_5705; 1661 } 1662 1663 /* 1664 * Initialize the jumbo RX ring control block 1665 * We set the 'ring disabled' bit in the flags 1666 * field until we're actually ready to start 1667 * using this ring (i.e. once we set the MTU 1668 * high enough to require it). 1669 */ 1670 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 1671 rcb = &sc->bge_rdata->bge_info.bge_jumbo_rx_rcb; 1672 bge_set_hostaddr(&rcb->bge_hostaddr, 1673 BGE_RING_DMA_ADDR(sc, bge_rx_jumbo_ring)); 1674 rcb->bge_maxlen_flags = 1675 BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 1676 BGE_RCB_FLAG_RING_DISABLED); 1677 if (sc->bge_extram) 1678 rcb->bge_nicaddr = BGE_EXT_JUMBO_RX_RINGS; 1679 else 1680 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS; 1681 1682 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI, 1683 rcb->bge_hostaddr.bge_addr_hi); 1684 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO, 1685 rcb->bge_hostaddr.bge_addr_lo); 1686 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, 1687 rcb->bge_maxlen_flags); 1688 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcb->bge_nicaddr); 1689 1690 /* Set up dummy disabled mini ring RCB */ 1691 rcb = &sc->bge_rdata->bge_info.bge_mini_rx_rcb; 1692 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0, 1693 BGE_RCB_FLAG_RING_DISABLED); 1694 CSR_WRITE_4(sc, BGE_RX_MINI_RCB_MAXLEN_FLAGS, 1695 rcb->bge_maxlen_flags); 1696 1697 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 1698 offsetof(struct bge_ring_data, bge_info), 1699 sizeof (struct bge_gib), 1700 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1701 } 1702 1703 /* 1704 * Set the BD ring replenish thresholds. The recommended 1705 * values are 1/8th the number of descriptors allocated to 1706 * each ring. 1707 */ 1708 i = BGE_STD_RX_RING_CNT / 8; 1709 1710 /* 1711 * Use a value of 8 for the following chips to workaround HW errata. 1712 * Some of these chips have been added based on empirical 1713 * evidence (they don't work unless this is done). 1714 */ 1715 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5750 || 1716 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5752 || 1717 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5755 || 1718 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5787 || 1719 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 1720 i = 8; 1721 1722 CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, i); 1723 CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH, BGE_JUMBO_RX_RING_CNT/8); 1724 1725 /* 1726 * Disable all unused send rings by setting the 'ring disabled' 1727 * bit in the flags field of all the TX send ring control blocks. 1728 * These are located in NIC memory. 1729 */ 1730 rcb_addr = BGE_MEMWIN_START + BGE_SEND_RING_RCB; 1731 for (i = 0; i < BGE_TX_RINGS_EXTSSRAM_MAX; i++) { 1732 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 1733 BGE_RCB_MAXLEN_FLAGS(0,BGE_RCB_FLAG_RING_DISABLED)); 1734 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 0); 1735 rcb_addr += sizeof(struct bge_rcb); 1736 } 1737 1738 /* Configure TX RCB 0 (we use only the first ring) */ 1739 rcb_addr = BGE_MEMWIN_START + BGE_SEND_RING_RCB; 1740 bge_set_hostaddr(&taddr, BGE_RING_DMA_ADDR(sc, bge_tx_ring)); 1741 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi); 1742 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo); 1743 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 1744 BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT)); 1745 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 1746 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 1747 BGE_RCB_MAXLEN_FLAGS(BGE_TX_RING_CNT, 0)); 1748 } 1749 1750 /* Disable all unused RX return rings */ 1751 rcb_addr = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB; 1752 for (i = 0; i < BGE_RX_RINGS_MAX; i++) { 1753 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_hi, 0); 1754 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_lo, 0); 1755 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 1756 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 1757 BGE_RCB_FLAG_RING_DISABLED)); 1758 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 0); 1759 bge_writembx(sc, BGE_MBX_RX_CONS0_LO + 1760 (i * (sizeof(u_int64_t))), 0); 1761 rcb_addr += sizeof(struct bge_rcb); 1762 } 1763 1764 /* Initialize RX ring indexes */ 1765 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, 0); 1766 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0); 1767 bge_writembx(sc, BGE_MBX_RX_MINI_PROD_LO, 0); 1768 1769 /* 1770 * Set up RX return ring 0 1771 * Note that the NIC address for RX return rings is 0x00000000. 1772 * The return rings live entirely within the host, so the 1773 * nicaddr field in the RCB isn't used. 1774 */ 1775 rcb_addr = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB; 1776 bge_set_hostaddr(&taddr, BGE_RING_DMA_ADDR(sc, bge_rx_return_ring)); 1777 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi); 1778 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo); 1779 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 0x00000000); 1780 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 1781 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 0)); 1782 1783 /* Set random backoff seed for TX */ 1784 CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF, 1785 CLLADDR(ifp->if_sadl)[0] + CLLADDR(ifp->if_sadl)[1] + 1786 CLLADDR(ifp->if_sadl)[2] + CLLADDR(ifp->if_sadl)[3] + 1787 CLLADDR(ifp->if_sadl)[4] + CLLADDR(ifp->if_sadl)[5] + 1788 BGE_TX_BACKOFF_SEED_MASK); 1789 1790 /* Set inter-packet gap */ 1791 CSR_WRITE_4(sc, BGE_TX_LENGTHS, 0x2620); 1792 1793 /* 1794 * Specify which ring to use for packets that don't match 1795 * any RX rules. 1796 */ 1797 CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08); 1798 1799 /* 1800 * Configure number of RX lists. One interrupt distribution 1801 * list, sixteen active lists, one bad frames class. 1802 */ 1803 CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181); 1804 1805 /* Inialize RX list placement stats mask. */ 1806 CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF); 1807 CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1); 1808 1809 /* Disable host coalescing until we get it set up */ 1810 CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000); 1811 1812 /* Poll to make sure it's shut down. */ 1813 for (i = 0; i < BGE_TIMEOUT; i++) { 1814 if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE)) 1815 break; 1816 DELAY(10); 1817 } 1818 1819 if (i == BGE_TIMEOUT) { 1820 aprint_error_dev(sc->bge_dev, 1821 "host coalescing engine failed to idle\n"); 1822 return(ENXIO); 1823 } 1824 1825 /* Set up host coalescing defaults */ 1826 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bge_rx_coal_ticks); 1827 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bge_tx_coal_ticks); 1828 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bge_rx_max_coal_bds); 1829 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bge_tx_max_coal_bds); 1830 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 1831 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT, 0); 1832 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT, 0); 1833 } 1834 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 0); 1835 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 0); 1836 1837 /* Set up address of statistics block */ 1838 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 1839 bge_set_hostaddr(&taddr, 1840 BGE_RING_DMA_ADDR(sc, bge_info.bge_stats)); 1841 CSR_WRITE_4(sc, BGE_HCC_STATS_TICKS, sc->bge_stat_ticks); 1842 CSR_WRITE_4(sc, BGE_HCC_STATS_BASEADDR, BGE_STATS_BLOCK); 1843 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_HI, taddr.bge_addr_hi); 1844 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_LO, taddr.bge_addr_lo); 1845 } 1846 1847 /* Set up address of status block */ 1848 bge_set_hostaddr(&taddr, BGE_RING_DMA_ADDR(sc, bge_status_block)); 1849 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_BASEADDR, BGE_STATUS_BLOCK); 1850 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI, taddr.bge_addr_hi); 1851 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO, taddr.bge_addr_lo); 1852 sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx = 0; 1853 sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx = 0; 1854 1855 /* Turn on host coalescing state machine */ 1856 CSR_WRITE_4(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE); 1857 1858 /* Turn on RX BD completion state machine and enable attentions */ 1859 CSR_WRITE_4(sc, BGE_RBDC_MODE, 1860 BGE_RBDCMODE_ENABLE|BGE_RBDCMODE_ATTN); 1861 1862 /* Turn on RX list placement state machine */ 1863 CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 1864 1865 /* Turn on RX list selector state machine. */ 1866 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 1867 CSR_WRITE_4(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 1868 } 1869 1870 /* Turn on DMA, clear stats */ 1871 CSR_WRITE_4(sc, BGE_MAC_MODE, BGE_MACMODE_TXDMA_ENB| 1872 BGE_MACMODE_RXDMA_ENB|BGE_MACMODE_RX_STATS_CLEAR| 1873 BGE_MACMODE_TX_STATS_CLEAR|BGE_MACMODE_RX_STATS_ENB| 1874 BGE_MACMODE_TX_STATS_ENB|BGE_MACMODE_FRMHDR_DMA_ENB| 1875 (sc->bge_tbi ? BGE_PORTMODE_TBI : BGE_PORTMODE_MII)); 1876 1877 /* Set misc. local control, enable interrupts on attentions */ 1878 sc->bge_local_ctrl_reg = BGE_MLC_INTR_ONATTN | BGE_MLC_AUTO_EEPROM; 1879 1880 #ifdef notdef 1881 /* Assert GPIO pins for PHY reset */ 1882 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUT0| 1883 BGE_MLC_MISCIO_OUT1|BGE_MLC_MISCIO_OUT2); 1884 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUTEN0| 1885 BGE_MLC_MISCIO_OUTEN1|BGE_MLC_MISCIO_OUTEN2); 1886 #endif 1887 1888 #if defined(not_quite_yet) 1889 /* Linux driver enables enable gpio pin #1 on 5700s */ 1890 if (sc->bge_chipid == BGE_CHIPID_BCM5700) { 1891 sc->bge_local_ctrl_reg |= 1892 (BGE_MLC_MISCIO_OUT1|BGE_MLC_MISCIO_OUTEN1); 1893 } 1894 #endif 1895 CSR_WRITE_4(sc, BGE_MISC_LOCAL_CTL, sc->bge_local_ctrl_reg); 1896 1897 /* Turn on DMA completion state machine */ 1898 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 1899 CSR_WRITE_4(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 1900 } 1901 1902 /* Turn on write DMA state machine */ 1903 { 1904 uint32_t bge_wdma_mode = 1905 BGE_WDMAMODE_ENABLE|BGE_WDMAMODE_ALL_ATTNS; 1906 1907 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5755 || 1908 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5787) 1909 /* Enable host coalescing bug fix; see Linux tg3.c */ 1910 bge_wdma_mode |= (1 << 29); 1911 1912 CSR_WRITE_4(sc, BGE_WDMA_MODE, bge_wdma_mode); 1913 } 1914 1915 /* Turn on read DMA state machine */ 1916 { 1917 uint32_t dma_read_modebits; 1918 1919 dma_read_modebits = 1920 BGE_RDMAMODE_ENABLE | BGE_RDMAMODE_ALL_ATTNS; 1921 1922 if (sc->bge_pcie && 0) { 1923 dma_read_modebits |= BGE_RDMA_MODE_FIFO_LONG_BURST; 1924 } else if ((sc->bge_quirks & BGE_QUIRK_5705_CORE)) { 1925 dma_read_modebits |= BGE_RDMA_MODE_FIFO_SIZE_128; 1926 } 1927 1928 /* XXX broadcom-supplied linux driver; undocumented */ 1929 if (BGE_IS_5750_OR_BEYOND(sc)) { 1930 /* 1931 * XXX: magic values. 1932 * From Broadcom-supplied Linux driver; apparently 1933 * required to workaround a DMA bug affecting TSO 1934 * on bcm575x/bcm5721? 1935 */ 1936 dma_read_modebits |= (1 << 27); 1937 } 1938 CSR_WRITE_4(sc, BGE_RDMA_MODE, dma_read_modebits); 1939 } 1940 1941 /* Turn on RX data completion state machine */ 1942 CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 1943 1944 /* Turn on RX BD initiator state machine */ 1945 CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 1946 1947 /* Turn on RX data and RX BD initiator state machine */ 1948 CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE); 1949 1950 /* Turn on Mbuf cluster free state machine */ 1951 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 1952 CSR_WRITE_4(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 1953 } 1954 1955 /* Turn on send BD completion state machine */ 1956 CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 1957 1958 /* Turn on send data completion state machine */ 1959 CSR_WRITE_4(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE); 1960 1961 /* Turn on send data initiator state machine */ 1962 if (BGE_IS_5750_OR_BEYOND(sc)) { 1963 /* XXX: magic value from Linux driver */ 1964 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE | 0x08); 1965 } else { 1966 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 1967 } 1968 1969 /* Turn on send BD initiator state machine */ 1970 CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 1971 1972 /* Turn on send BD selector state machine */ 1973 CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 1974 1975 CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF); 1976 CSR_WRITE_4(sc, BGE_SDI_STATS_CTL, 1977 BGE_SDISTATSCTL_ENABLE|BGE_SDISTATSCTL_FASTER); 1978 1979 /* ack/clear link change events */ 1980 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED| 1981 BGE_MACSTAT_CFG_CHANGED); 1982 CSR_WRITE_4(sc, BGE_MI_STS, 0); 1983 1984 /* Enable PHY auto polling (for MII/GMII only) */ 1985 if (sc->bge_tbi) { 1986 CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK); 1987 } else { 1988 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL|10<<16); 1989 if (sc->bge_quirks & BGE_QUIRK_LINK_STATE_BROKEN) 1990 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, 1991 BGE_EVTENB_MI_INTERRUPT); 1992 } 1993 1994 /* Enable link state change attentions. */ 1995 BGE_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED); 1996 1997 return(0); 1998 } 1999 2000 static const struct bge_revision { 2001 uint32_t br_chipid; 2002 uint32_t br_quirks; 2003 const char *br_name; 2004 } bge_revisions[] = { 2005 { BGE_CHIPID_BCM5700_A0, 2006 BGE_QUIRK_LINK_STATE_BROKEN, 2007 "BCM5700 A0" }, 2008 2009 { BGE_CHIPID_BCM5700_A1, 2010 BGE_QUIRK_LINK_STATE_BROKEN, 2011 "BCM5700 A1" }, 2012 2013 { BGE_CHIPID_BCM5700_B0, 2014 BGE_QUIRK_LINK_STATE_BROKEN|BGE_QUIRK_CSUM_BROKEN|BGE_QUIRK_5700_COMMON, 2015 "BCM5700 B0" }, 2016 2017 { BGE_CHIPID_BCM5700_B1, 2018 BGE_QUIRK_LINK_STATE_BROKEN|BGE_QUIRK_5700_COMMON, 2019 "BCM5700 B1" }, 2020 2021 { BGE_CHIPID_BCM5700_B2, 2022 BGE_QUIRK_LINK_STATE_BROKEN|BGE_QUIRK_5700_COMMON, 2023 "BCM5700 B2" }, 2024 2025 { BGE_CHIPID_BCM5700_B3, 2026 BGE_QUIRK_LINK_STATE_BROKEN|BGE_QUIRK_5700_COMMON, 2027 "BCM5700 B3" }, 2028 2029 /* This is treated like a BCM5700 Bx */ 2030 { BGE_CHIPID_BCM5700_ALTIMA, 2031 BGE_QUIRK_LINK_STATE_BROKEN|BGE_QUIRK_5700_COMMON, 2032 "BCM5700 Altima" }, 2033 2034 { BGE_CHIPID_BCM5700_C0, 2035 0, 2036 "BCM5700 C0" }, 2037 2038 { BGE_CHIPID_BCM5701_A0, 2039 0, /*XXX really, just not known */ 2040 "BCM5701 A0" }, 2041 2042 { BGE_CHIPID_BCM5701_B0, 2043 BGE_QUIRK_PCIX_DMA_ALIGN_BUG, 2044 "BCM5701 B0" }, 2045 2046 { BGE_CHIPID_BCM5701_B2, 2047 BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_PCIX_DMA_ALIGN_BUG, 2048 "BCM5701 B2" }, 2049 2050 { BGE_CHIPID_BCM5701_B5, 2051 BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_PCIX_DMA_ALIGN_BUG, 2052 "BCM5701 B5" }, 2053 2054 { BGE_CHIPID_BCM5703_A0, 2055 0, 2056 "BCM5703 A0" }, 2057 2058 { BGE_CHIPID_BCM5703_A1, 2059 0, 2060 "BCM5703 A1" }, 2061 2062 { BGE_CHIPID_BCM5703_A2, 2063 BGE_QUIRK_ONLY_PHY_1, 2064 "BCM5703 A2" }, 2065 2066 { BGE_CHIPID_BCM5703_A3, 2067 BGE_QUIRK_ONLY_PHY_1, 2068 "BCM5703 A3" }, 2069 2070 { BGE_CHIPID_BCM5703_B0, 2071 BGE_QUIRK_ONLY_PHY_1, 2072 "BCM5703 B0" }, 2073 2074 { BGE_CHIPID_BCM5704_A0, 2075 BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_FEWER_MBUFS, 2076 "BCM5704 A0" }, 2077 2078 { BGE_CHIPID_BCM5704_A1, 2079 BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_FEWER_MBUFS, 2080 "BCM5704 A1" }, 2081 2082 { BGE_CHIPID_BCM5704_A2, 2083 BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_FEWER_MBUFS, 2084 "BCM5704 A2" }, 2085 2086 { BGE_CHIPID_BCM5704_A3, 2087 BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_FEWER_MBUFS, 2088 "BCM5704 A3" }, 2089 2090 { BGE_CHIPID_BCM5705_A0, 2091 BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_5705_CORE, 2092 "BCM5705 A0" }, 2093 2094 { BGE_CHIPID_BCM5705_A1, 2095 BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_5705_CORE, 2096 "BCM5705 A1" }, 2097 2098 { BGE_CHIPID_BCM5705_A2, 2099 BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_5705_CORE, 2100 "BCM5705 A2" }, 2101 2102 { BGE_CHIPID_BCM5705_A3, 2103 BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_5705_CORE, 2104 "BCM5705 A3" }, 2105 2106 { BGE_CHIPID_BCM5750_A0, 2107 BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_5705_CORE, 2108 "BCM5750 A0" }, 2109 2110 { BGE_CHIPID_BCM5750_A1, 2111 BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_5705_CORE, 2112 "BCM5750 A1" }, 2113 2114 { BGE_CHIPID_BCM5751_A1, 2115 BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_5705_CORE, 2116 "BCM5751 A1" }, 2117 2118 { BGE_CHIPID_BCM5752_A0, 2119 BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_5705_CORE, 2120 "BCM5752 A0" }, 2121 2122 { BGE_CHIPID_BCM5752_A1, 2123 BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_5705_CORE, 2124 "BCM5752 A1" }, 2125 2126 { BGE_CHIPID_BCM5752_A2, 2127 BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_5705_CORE, 2128 "BCM5752 A2" }, 2129 2130 { BGE_CHIPID_BCM5755_A0, 2131 BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_5705_CORE, 2132 "BCM5755 A0" }, 2133 2134 { BGE_CHIPID_BCM5755_A1, 2135 BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_5705_CORE, 2136 "BCM5755 A1" }, 2137 2138 { BGE_CHIPID_BCM5755_A2, 2139 BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_5705_CORE, 2140 "BCM5755 A2" }, 2141 2142 { BGE_CHIPID_BCM5755_C0, 2143 BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_5705_CORE, 2144 "BCM5755 C0" }, 2145 2146 { BGE_CHIPID_BCM5787_A0, 2147 BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_5705_CORE, 2148 "BCM5754/5787 A0" }, 2149 2150 { BGE_CHIPID_BCM5787_A1, 2151 BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_5705_CORE, 2152 "BCM5754/5787 A1" }, 2153 2154 { BGE_CHIPID_BCM5787_A2, 2155 BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_5705_CORE, 2156 "BCM5754/5787 A2" }, 2157 2158 { 0, 0, NULL } 2159 }; 2160 2161 /* 2162 * Some defaults for major revisions, so that newer steppings 2163 * that we don't know about have a shot at working. 2164 */ 2165 static const struct bge_revision bge_majorrevs[] = { 2166 { BGE_ASICREV_BCM5700, 2167 BGE_QUIRK_LINK_STATE_BROKEN, 2168 "unknown BCM5700" }, 2169 2170 { BGE_ASICREV_BCM5701, 2171 BGE_QUIRK_PCIX_DMA_ALIGN_BUG, 2172 "unknown BCM5701" }, 2173 2174 { BGE_ASICREV_BCM5703, 2175 0, 2176 "unknown BCM5703" }, 2177 2178 { BGE_ASICREV_BCM5704, 2179 BGE_QUIRK_ONLY_PHY_1, 2180 "unknown BCM5704" }, 2181 2182 { BGE_ASICREV_BCM5705, 2183 BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_5705_CORE, 2184 "unknown BCM5705" }, 2185 2186 { BGE_ASICREV_BCM5750, 2187 BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_5705_CORE, 2188 "unknown BCM575x family" }, 2189 2190 { BGE_ASICREV_BCM5714_A0, 2191 BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_5705_CORE, 2192 "unknown BCM5714" }, 2193 2194 { BGE_ASICREV_BCM5714, 2195 BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_5705_CORE, 2196 "unknown BCM5714" }, 2197 2198 { BGE_ASICREV_BCM5752, 2199 BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_5705_CORE, 2200 "unknown BCM5752 family" }, 2201 2202 { BGE_ASICREV_BCM5755, 2203 BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_5705_CORE, 2204 "unknown BCM5755" }, 2205 2206 { BGE_ASICREV_BCM5780, 2207 BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_5705_CORE, 2208 "unknown BCM5780" }, 2209 2210 { BGE_ASICREV_BCM5787, 2211 BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_5705_CORE, 2212 "unknown BCM5787" }, 2213 2214 { BGE_ASICREV_BCM5906, 2215 BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_5705_CORE, 2216 "unknown BCM5906" }, 2217 2218 { 0, 2219 0, 2220 NULL } 2221 }; 2222 2223 2224 static const struct bge_revision * 2225 bge_lookup_rev(uint32_t chipid) 2226 { 2227 const struct bge_revision *br; 2228 2229 for (br = bge_revisions; br->br_name != NULL; br++) { 2230 if (br->br_chipid == chipid) 2231 return (br); 2232 } 2233 2234 for (br = bge_majorrevs; br->br_name != NULL; br++) { 2235 if (br->br_chipid == BGE_ASICREV(chipid)) 2236 return (br); 2237 } 2238 2239 return (NULL); 2240 } 2241 2242 static const struct bge_product { 2243 pci_vendor_id_t bp_vendor; 2244 pci_product_id_t bp_product; 2245 const char *bp_name; 2246 } bge_products[] = { 2247 /* 2248 * The BCM5700 documentation seems to indicate that the hardware 2249 * still has the Alteon vendor ID burned into it, though it 2250 * should always be overridden by the value in the EEPROM. We'll 2251 * check for it anyway. 2252 */ 2253 { PCI_VENDOR_ALTEON, 2254 PCI_PRODUCT_ALTEON_BCM5700, 2255 "Broadcom BCM5700 Gigabit Ethernet", 2256 }, 2257 { PCI_VENDOR_ALTEON, 2258 PCI_PRODUCT_ALTEON_BCM5701, 2259 "Broadcom BCM5701 Gigabit Ethernet", 2260 }, 2261 2262 { PCI_VENDOR_ALTIMA, 2263 PCI_PRODUCT_ALTIMA_AC1000, 2264 "Altima AC1000 Gigabit Ethernet", 2265 }, 2266 { PCI_VENDOR_ALTIMA, 2267 PCI_PRODUCT_ALTIMA_AC1001, 2268 "Altima AC1001 Gigabit Ethernet", 2269 }, 2270 { PCI_VENDOR_ALTIMA, 2271 PCI_PRODUCT_ALTIMA_AC9100, 2272 "Altima AC9100 Gigabit Ethernet", 2273 }, 2274 2275 { PCI_VENDOR_BROADCOM, 2276 PCI_PRODUCT_BROADCOM_BCM5700, 2277 "Broadcom BCM5700 Gigabit Ethernet", 2278 }, 2279 { PCI_VENDOR_BROADCOM, 2280 PCI_PRODUCT_BROADCOM_BCM5701, 2281 "Broadcom BCM5701 Gigabit Ethernet", 2282 }, 2283 { PCI_VENDOR_BROADCOM, 2284 PCI_PRODUCT_BROADCOM_BCM5702, 2285 "Broadcom BCM5702 Gigabit Ethernet", 2286 }, 2287 { PCI_VENDOR_BROADCOM, 2288 PCI_PRODUCT_BROADCOM_BCM5702X, 2289 "Broadcom BCM5702X Gigabit Ethernet" }, 2290 2291 { PCI_VENDOR_BROADCOM, 2292 PCI_PRODUCT_BROADCOM_BCM5703, 2293 "Broadcom BCM5703 Gigabit Ethernet", 2294 }, 2295 { PCI_VENDOR_BROADCOM, 2296 PCI_PRODUCT_BROADCOM_BCM5703X, 2297 "Broadcom BCM5703X Gigabit Ethernet", 2298 }, 2299 { PCI_VENDOR_BROADCOM, 2300 PCI_PRODUCT_BROADCOM_BCM5703_ALT, 2301 "Broadcom BCM5703 Gigabit Ethernet", 2302 }, 2303 2304 { PCI_VENDOR_BROADCOM, 2305 PCI_PRODUCT_BROADCOM_BCM5704C, 2306 "Broadcom BCM5704C Dual Gigabit Ethernet", 2307 }, 2308 { PCI_VENDOR_BROADCOM, 2309 PCI_PRODUCT_BROADCOM_BCM5704S, 2310 "Broadcom BCM5704S Dual Gigabit Ethernet", 2311 }, 2312 2313 { PCI_VENDOR_BROADCOM, 2314 PCI_PRODUCT_BROADCOM_BCM5705, 2315 "Broadcom BCM5705 Gigabit Ethernet", 2316 }, 2317 { PCI_VENDOR_BROADCOM, 2318 PCI_PRODUCT_BROADCOM_BCM5705K, 2319 "Broadcom BCM5705K Gigabit Ethernet", 2320 }, 2321 { PCI_VENDOR_BROADCOM, 2322 PCI_PRODUCT_BROADCOM_BCM5705M, 2323 "Broadcom BCM5705M Gigabit Ethernet", 2324 }, 2325 { PCI_VENDOR_BROADCOM, 2326 PCI_PRODUCT_BROADCOM_BCM5705M_ALT, 2327 "Broadcom BCM5705M Gigabit Ethernet", 2328 }, 2329 2330 { PCI_VENDOR_BROADCOM, 2331 PCI_PRODUCT_BROADCOM_BCM5714, 2332 "Broadcom BCM5714/5715 Gigabit Ethernet", 2333 }, 2334 { PCI_VENDOR_BROADCOM, 2335 PCI_PRODUCT_BROADCOM_BCM5715, 2336 "Broadcom BCM5714/5715 Gigabit Ethernet", 2337 }, 2338 { PCI_VENDOR_BROADCOM, 2339 PCI_PRODUCT_BROADCOM_BCM5789, 2340 "Broadcom BCM5789 Gigabit Ethernet", 2341 }, 2342 2343 { PCI_VENDOR_BROADCOM, 2344 PCI_PRODUCT_BROADCOM_BCM5721, 2345 "Broadcom BCM5721 Gigabit Ethernet", 2346 }, 2347 2348 { PCI_VENDOR_BROADCOM, 2349 PCI_PRODUCT_BROADCOM_BCM5722, 2350 "Broadcom BCM5722 Gigabit Ethernet", 2351 }, 2352 2353 { PCI_VENDOR_BROADCOM, 2354 PCI_PRODUCT_BROADCOM_BCM5750, 2355 "Broadcom BCM5750 Gigabit Ethernet", 2356 }, 2357 2358 { PCI_VENDOR_BROADCOM, 2359 PCI_PRODUCT_BROADCOM_BCM5750M, 2360 "Broadcom BCM5750M Gigabit Ethernet", 2361 }, 2362 2363 { PCI_VENDOR_BROADCOM, 2364 PCI_PRODUCT_BROADCOM_BCM5751, 2365 "Broadcom BCM5751 Gigabit Ethernet", 2366 }, 2367 2368 { PCI_VENDOR_BROADCOM, 2369 PCI_PRODUCT_BROADCOM_BCM5751M, 2370 "Broadcom BCM5751M Gigabit Ethernet", 2371 }, 2372 2373 { PCI_VENDOR_BROADCOM, 2374 PCI_PRODUCT_BROADCOM_BCM5752, 2375 "Broadcom BCM5752 Gigabit Ethernet", 2376 }, 2377 2378 { PCI_VENDOR_BROADCOM, 2379 PCI_PRODUCT_BROADCOM_BCM5752M, 2380 "Broadcom BCM5752M Gigabit Ethernet", 2381 }, 2382 2383 { PCI_VENDOR_BROADCOM, 2384 PCI_PRODUCT_BROADCOM_BCM5753, 2385 "Broadcom BCM5753 Gigabit Ethernet", 2386 }, 2387 2388 { PCI_VENDOR_BROADCOM, 2389 PCI_PRODUCT_BROADCOM_BCM5753M, 2390 "Broadcom BCM5753M Gigabit Ethernet", 2391 }, 2392 2393 { PCI_VENDOR_BROADCOM, 2394 PCI_PRODUCT_BROADCOM_BCM5754, 2395 "Broadcom BCM5754 Gigabit Ethernet", 2396 }, 2397 2398 { PCI_VENDOR_BROADCOM, 2399 PCI_PRODUCT_BROADCOM_BCM5754M, 2400 "Broadcom BCM5754M Gigabit Ethernet", 2401 }, 2402 2403 { PCI_VENDOR_BROADCOM, 2404 PCI_PRODUCT_BROADCOM_BCM5755, 2405 "Broadcom BCM5755 Gigabit Ethernet", 2406 }, 2407 2408 { PCI_VENDOR_BROADCOM, 2409 PCI_PRODUCT_BROADCOM_BCM5755M, 2410 "Broadcom BCM5755M Gigabit Ethernet", 2411 }, 2412 2413 { PCI_VENDOR_BROADCOM, 2414 PCI_PRODUCT_BROADCOM_BCM5780, 2415 "Broadcom BCM5780 Gigabit Ethernet", 2416 }, 2417 2418 { PCI_VENDOR_BROADCOM, 2419 PCI_PRODUCT_BROADCOM_BCM5780S, 2420 "Broadcom BCM5780S Gigabit Ethernet", 2421 }, 2422 2423 { PCI_VENDOR_BROADCOM, 2424 PCI_PRODUCT_BROADCOM_BCM5782, 2425 "Broadcom BCM5782 Gigabit Ethernet", 2426 }, 2427 2428 { PCI_VENDOR_BROADCOM, 2429 PCI_PRODUCT_BROADCOM_BCM5786, 2430 "Broadcom BCM5786 Gigabit Ethernet", 2431 }, 2432 2433 { PCI_VENDOR_BROADCOM, 2434 PCI_PRODUCT_BROADCOM_BCM5787, 2435 "Broadcom BCM5787 Gigabit Ethernet", 2436 }, 2437 2438 { PCI_VENDOR_BROADCOM, 2439 PCI_PRODUCT_BROADCOM_BCM5787M, 2440 "Broadcom BCM5787M Gigabit Ethernet", 2441 }, 2442 2443 { PCI_VENDOR_BROADCOM, 2444 PCI_PRODUCT_BROADCOM_BCM5788, 2445 "Broadcom BCM5788 Gigabit Ethernet", 2446 }, 2447 { PCI_VENDOR_BROADCOM, 2448 PCI_PRODUCT_BROADCOM_BCM5789, 2449 "Broadcom BCM5789 Gigabit Ethernet", 2450 }, 2451 2452 { PCI_VENDOR_BROADCOM, 2453 PCI_PRODUCT_BROADCOM_BCM5901, 2454 "Broadcom BCM5901 Fast Ethernet", 2455 }, 2456 { PCI_VENDOR_BROADCOM, 2457 PCI_PRODUCT_BROADCOM_BCM5901A2, 2458 "Broadcom BCM5901A2 Fast Ethernet", 2459 }, 2460 2461 { PCI_VENDOR_SCHNEIDERKOCH, 2462 PCI_PRODUCT_SCHNEIDERKOCH_SK_9DX1, 2463 "SysKonnect SK-9Dx1 Gigabit Ethernet", 2464 }, 2465 2466 { PCI_VENDOR_3COM, 2467 PCI_PRODUCT_3COM_3C996, 2468 "3Com 3c996 Gigabit Ethernet", 2469 }, 2470 2471 { PCI_VENDOR_BROADCOM, 2472 PCI_PRODUCT_BROADCOM_BCM5906, 2473 "Broadcom BCM5906 Fast Ethernet", 2474 }, 2475 2476 { PCI_VENDOR_BROADCOM, 2477 PCI_PRODUCT_BROADCOM_BCM5906M, 2478 "Broadcom BCM5906M Fast Ethernet", 2479 }, 2480 2481 { 0, 2482 0, 2483 NULL }, 2484 }; 2485 2486 static const struct bge_product * 2487 bge_lookup(const struct pci_attach_args *pa) 2488 { 2489 const struct bge_product *bp; 2490 2491 for (bp = bge_products; bp->bp_name != NULL; bp++) { 2492 if (PCI_VENDOR(pa->pa_id) == bp->bp_vendor && 2493 PCI_PRODUCT(pa->pa_id) == bp->bp_product) 2494 return (bp); 2495 } 2496 2497 return (NULL); 2498 } 2499 2500 static int 2501 bge_setpowerstate(struct bge_softc *sc, int powerlevel) 2502 { 2503 #ifdef NOTYET 2504 u_int32_t pm_ctl = 0; 2505 2506 /* XXX FIXME: make sure indirect accesses enabled? */ 2507 pm_ctl = pci_conf_read(sc->bge_dev, BGE_PCI_MISC_CTL, 4); 2508 pm_ctl |= BGE_PCIMISCCTL_INDIRECT_ACCESS; 2509 pci_write_config(sc->bge_dev, BGE_PCI_MISC_CTL, pm_ctl, 4); 2510 2511 /* clear the PME_assert bit and power state bits, enable PME */ 2512 pm_ctl = pci_conf_read(sc->bge_dev, BGE_PCI_PWRMGMT_CMD, 2); 2513 pm_ctl &= ~PCIM_PSTAT_DMASK; 2514 pm_ctl |= (1 << 8); 2515 2516 if (powerlevel == 0) { 2517 pm_ctl |= PCIM_PSTAT_D0; 2518 pci_write_config(sc->bge_dev, BGE_PCI_PWRMGMT_CMD, 2519 pm_ctl, 2); 2520 DELAY(10000); 2521 CSR_WRITE_4(sc, BGE_MISC_LOCAL_CTL, sc->bge_local_ctrl_reg); 2522 DELAY(10000); 2523 2524 #ifdef NOTYET 2525 /* XXX FIXME: write 0x02 to phy aux_Ctrl reg */ 2526 bge_miibus_writereg(sc->bge_dev, 1, 0x18, 0x02); 2527 #endif 2528 DELAY(40); DELAY(40); DELAY(40); 2529 DELAY(10000); /* above not quite adequate on 5700 */ 2530 return 0; 2531 } 2532 2533 2534 /* 2535 * Entering ACPI power states D1-D3 is achieved by wiggling 2536 * GMII gpio pins. Example code assumes all hardware vendors 2537 * followed Broadom's sample pcb layout. Until we verify that 2538 * for all supported OEM cards, states D1-D3 are unsupported. 2539 */ 2540 aprint_error_dev(sc->bge_dev, 2541 "power state %d unimplemented; check GPIO pins\n", 2542 powerlevel); 2543 #endif 2544 return EOPNOTSUPP; 2545 } 2546 2547 2548 /* 2549 * Probe for a Broadcom chip. Check the PCI vendor and device IDs 2550 * against our list and return its name if we find a match. Note 2551 * that since the Broadcom controller contains VPD support, we 2552 * can get the device name string from the controller itself instead 2553 * of the compiled-in string. This is a little slow, but it guarantees 2554 * we'll always announce the right product name. 2555 */ 2556 static int 2557 bge_probe(device_t parent, cfdata_t match, void *aux) 2558 { 2559 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 2560 2561 if (bge_lookup(pa) != NULL) 2562 return (1); 2563 2564 return (0); 2565 } 2566 2567 static void 2568 bge_attach(device_t parent, device_t self, void *aux) 2569 { 2570 struct bge_softc *sc = device_private(self); 2571 struct pci_attach_args *pa = aux; 2572 const struct bge_product *bp; 2573 const struct bge_revision *br; 2574 pci_chipset_tag_t pc; 2575 pci_intr_handle_t ih; 2576 const char *intrstr = NULL; 2577 bus_dma_segment_t seg; 2578 int rseg; 2579 u_int32_t hwcfg = 0; 2580 u_int32_t command; 2581 struct ifnet *ifp; 2582 void * kva; 2583 u_char eaddr[ETHER_ADDR_LEN]; 2584 pcireg_t memtype; 2585 bus_addr_t memaddr; 2586 bus_size_t memsize; 2587 u_int32_t pm_ctl; 2588 2589 bp = bge_lookup(pa); 2590 KASSERT(bp != NULL); 2591 2592 sc->sc_pc = pa->pa_pc; 2593 sc->sc_pcitag = pa->pa_tag; 2594 sc->bge_dev = self; 2595 2596 aprint_naive(": Ethernet controller\n"); 2597 aprint_normal(": %s\n", bp->bp_name); 2598 2599 /* 2600 * Map control/status registers. 2601 */ 2602 DPRINTFN(5, ("Map control/status regs\n")); 2603 pc = sc->sc_pc; 2604 command = pci_conf_read(pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG); 2605 command |= PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_MASTER_ENABLE; 2606 pci_conf_write(pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG, command); 2607 command = pci_conf_read(pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG); 2608 2609 if (!(command & PCI_COMMAND_MEM_ENABLE)) { 2610 aprint_error_dev(sc->bge_dev, 2611 "failed to enable memory mapping!\n"); 2612 return; 2613 } 2614 2615 DPRINTFN(5, ("pci_mem_find\n")); 2616 memtype = pci_mapreg_type(sc->sc_pc, sc->sc_pcitag, BGE_PCI_BAR0); 2617 switch (memtype) { 2618 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 2619 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 2620 if (pci_mapreg_map(pa, BGE_PCI_BAR0, 2621 memtype, 0, &sc->bge_btag, &sc->bge_bhandle, 2622 &memaddr, &memsize) == 0) 2623 break; 2624 default: 2625 aprint_error_dev(sc->bge_dev, "can't find mem space\n"); 2626 return; 2627 } 2628 2629 DPRINTFN(5, ("pci_intr_map\n")); 2630 if (pci_intr_map(pa, &ih)) { 2631 aprint_error_dev(sc->bge_dev, "couldn't map interrupt\n"); 2632 return; 2633 } 2634 2635 DPRINTFN(5, ("pci_intr_string\n")); 2636 intrstr = pci_intr_string(pc, ih); 2637 2638 DPRINTFN(5, ("pci_intr_establish\n")); 2639 sc->bge_intrhand = pci_intr_establish(pc, ih, IPL_NET, bge_intr, sc); 2640 2641 if (sc->bge_intrhand == NULL) { 2642 aprint_error_dev(sc->bge_dev, 2643 "couldn't establish interrupt%s%s\n", 2644 intrstr ? " at " : "", intrstr ? intrstr : ""); 2645 return; 2646 } 2647 aprint_normal_dev(sc->bge_dev, "interrupting at %s\n", intrstr); 2648 2649 /* 2650 * Kludge for 5700 Bx bug: a hardware bug (PCIX byte enable?) 2651 * can clobber the chip's PCI config-space power control registers, 2652 * leaving the card in D3 powersave state. 2653 * We do not have memory-mapped registers in this state, 2654 * so force device into D0 state before starting initialization. 2655 */ 2656 pm_ctl = pci_conf_read(pc, sc->sc_pcitag, BGE_PCI_PWRMGMT_CMD); 2657 pm_ctl &= ~(PCI_PWR_D0|PCI_PWR_D1|PCI_PWR_D2|PCI_PWR_D3); 2658 pm_ctl |= (1 << 8) | PCI_PWR_D0 ; /* D0 state */ 2659 pci_conf_write(pc, sc->sc_pcitag, BGE_PCI_PWRMGMT_CMD, pm_ctl); 2660 DELAY(1000); /* 27 usec is allegedly sufficent */ 2661 2662 /* 2663 * Save ASIC rev. Look up any quirks associated with this 2664 * ASIC. 2665 */ 2666 sc->bge_chipid = 2667 pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MISC_CTL) & 2668 BGE_PCIMISCCTL_ASICREV; 2669 2670 /* 2671 * Detect PCI-Express devices 2672 * XXX: guessed from Linux/FreeBSD; no documentation 2673 */ 2674 if (pci_get_capability(sc->sc_pc, sc->sc_pcitag, PCI_CAP_PCIEXPRESS, 2675 NULL, NULL) != 0) 2676 sc->bge_pcie = 1; 2677 else 2678 sc->bge_pcie = 0; 2679 2680 /* Try to reset the chip. */ 2681 DPRINTFN(5, ("bge_reset\n")); 2682 bge_reset(sc); 2683 2684 if (bge_chipinit(sc)) { 2685 aprint_error_dev(sc->bge_dev, "chip initialization failed\n"); 2686 bge_release_resources(sc); 2687 return; 2688 } 2689 2690 /* 2691 * Get station address from the EEPROM. 2692 */ 2693 if (bge_get_eaddr(sc, eaddr)) { 2694 aprint_error_dev(sc->bge_dev, 2695 "failed to reade station address\n"); 2696 bge_release_resources(sc); 2697 return; 2698 } 2699 2700 br = bge_lookup_rev(sc->bge_chipid); 2701 2702 if (br == NULL) { 2703 aprint_normal_dev(sc->bge_dev, "unknown ASIC (0x%04x)", 2704 sc->bge_chipid >> 16); 2705 sc->bge_quirks = 0; 2706 } else { 2707 aprint_normal_dev(sc->bge_dev, "ASIC %s (0x%04x)", 2708 br->br_name, sc->bge_chipid >> 16); 2709 sc->bge_quirks |= br->br_quirks; 2710 } 2711 aprint_normal(", Ethernet address %s\n", ether_sprintf(eaddr)); 2712 2713 /* Allocate the general information block and ring buffers. */ 2714 if (pci_dma64_available(pa)) 2715 sc->bge_dmatag = pa->pa_dmat64; 2716 else 2717 sc->bge_dmatag = pa->pa_dmat; 2718 DPRINTFN(5, ("bus_dmamem_alloc\n")); 2719 if (bus_dmamem_alloc(sc->bge_dmatag, sizeof(struct bge_ring_data), 2720 PAGE_SIZE, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 2721 aprint_error_dev(sc->bge_dev, "can't alloc rx buffers\n"); 2722 return; 2723 } 2724 DPRINTFN(5, ("bus_dmamem_map\n")); 2725 if (bus_dmamem_map(sc->bge_dmatag, &seg, rseg, 2726 sizeof(struct bge_ring_data), &kva, 2727 BUS_DMA_NOWAIT)) { 2728 aprint_error_dev(sc->bge_dev, 2729 "can't map DMA buffers (%zu bytes)\n", 2730 sizeof(struct bge_ring_data)); 2731 bus_dmamem_free(sc->bge_dmatag, &seg, rseg); 2732 return; 2733 } 2734 DPRINTFN(5, ("bus_dmamem_create\n")); 2735 if (bus_dmamap_create(sc->bge_dmatag, sizeof(struct bge_ring_data), 1, 2736 sizeof(struct bge_ring_data), 0, 2737 BUS_DMA_NOWAIT, &sc->bge_ring_map)) { 2738 aprint_error_dev(sc->bge_dev, "can't create DMA map\n"); 2739 bus_dmamem_unmap(sc->bge_dmatag, kva, 2740 sizeof(struct bge_ring_data)); 2741 bus_dmamem_free(sc->bge_dmatag, &seg, rseg); 2742 return; 2743 } 2744 DPRINTFN(5, ("bus_dmamem_load\n")); 2745 if (bus_dmamap_load(sc->bge_dmatag, sc->bge_ring_map, kva, 2746 sizeof(struct bge_ring_data), NULL, 2747 BUS_DMA_NOWAIT)) { 2748 bus_dmamap_destroy(sc->bge_dmatag, sc->bge_ring_map); 2749 bus_dmamem_unmap(sc->bge_dmatag, kva, 2750 sizeof(struct bge_ring_data)); 2751 bus_dmamem_free(sc->bge_dmatag, &seg, rseg); 2752 return; 2753 } 2754 2755 DPRINTFN(5, ("bzero\n")); 2756 sc->bge_rdata = (struct bge_ring_data *)kva; 2757 2758 memset(sc->bge_rdata, 0, sizeof(struct bge_ring_data)); 2759 2760 /* Try to allocate memory for jumbo buffers. */ 2761 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 2762 if (bge_alloc_jumbo_mem(sc)) { 2763 aprint_error_dev(sc->bge_dev, 2764 "jumbo buffer allocation failed\n"); 2765 } else 2766 sc->ethercom.ec_capabilities |= ETHERCAP_JUMBO_MTU; 2767 } 2768 2769 /* Set default tuneable values. */ 2770 sc->bge_stat_ticks = BGE_TICKS_PER_SEC; 2771 sc->bge_rx_coal_ticks = 150; 2772 sc->bge_rx_max_coal_bds = 64; 2773 #ifdef ORIG_WPAUL_VALUES 2774 sc->bge_tx_coal_ticks = 150; 2775 sc->bge_tx_max_coal_bds = 128; 2776 #else 2777 sc->bge_tx_coal_ticks = 300; 2778 sc->bge_tx_max_coal_bds = 400; 2779 #endif 2780 if (sc->bge_quirks & BGE_QUIRK_5705_CORE) { 2781 sc->bge_tx_coal_ticks = (12 * 5); 2782 sc->bge_tx_max_coal_bds = (12 * 5); 2783 aprint_verbose_dev(sc->bge_dev, 2784 "setting short Tx thresholds\n"); 2785 } 2786 2787 /* Set up ifnet structure */ 2788 ifp = &sc->ethercom.ec_if; 2789 ifp->if_softc = sc; 2790 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 2791 ifp->if_ioctl = bge_ioctl; 2792 ifp->if_stop = bge_stop; 2793 ifp->if_start = bge_start; 2794 ifp->if_init = bge_init; 2795 ifp->if_watchdog = bge_watchdog; 2796 IFQ_SET_MAXLEN(&ifp->if_snd, max(BGE_TX_RING_CNT - 1, IFQ_MAXLEN)); 2797 IFQ_SET_READY(&ifp->if_snd); 2798 DPRINTFN(5, ("strcpy if_xname\n")); 2799 strcpy(ifp->if_xname, device_xname(sc->bge_dev)); 2800 2801 if ((sc->bge_quirks & BGE_QUIRK_CSUM_BROKEN) == 0) 2802 sc->ethercom.ec_if.if_capabilities |= 2803 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 2804 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 2805 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 2806 sc->ethercom.ec_capabilities |= 2807 ETHERCAP_VLAN_HWTAGGING | ETHERCAP_VLAN_MTU; 2808 2809 if (sc->bge_pcie) 2810 sc->ethercom.ec_if.if_capabilities |= IFCAP_TSOv4; 2811 2812 /* 2813 * Do MII setup. 2814 */ 2815 DPRINTFN(5, ("mii setup\n")); 2816 sc->bge_mii.mii_ifp = ifp; 2817 sc->bge_mii.mii_readreg = bge_miibus_readreg; 2818 sc->bge_mii.mii_writereg = bge_miibus_writereg; 2819 sc->bge_mii.mii_statchg = bge_miibus_statchg; 2820 2821 /* 2822 * Figure out what sort of media we have by checking the 2823 * hardware config word in the first 32k of NIC internal memory, 2824 * or fall back to the config word in the EEPROM. Note: on some BCM5700 2825 * cards, this value appears to be unset. If that's the 2826 * case, we have to rely on identifying the NIC by its PCI 2827 * subsystem ID, as we do below for the SysKonnect SK-9D41. 2828 */ 2829 if (bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_SIG) == BGE_MAGIC_NUMBER) { 2830 hwcfg = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_NICCFG); 2831 } else { 2832 bge_read_eeprom(sc, (void *)&hwcfg, 2833 BGE_EE_HWCFG_OFFSET, sizeof(hwcfg)); 2834 hwcfg = be32toh(hwcfg); 2835 } 2836 if ((hwcfg & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER) 2837 sc->bge_tbi = 1; 2838 2839 /* The SysKonnect SK-9D41 is a 1000baseSX card. */ 2840 if ((pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_SUBSYS) >> 16) == 2841 SK_SUBSYSID_9D41) 2842 sc->bge_tbi = 1; 2843 2844 if (sc->bge_tbi) { 2845 ifmedia_init(&sc->bge_ifmedia, IFM_IMASK, bge_ifmedia_upd, 2846 bge_ifmedia_sts); 2847 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL); 2848 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_1000_SX|IFM_FDX, 2849 0, NULL); 2850 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL); 2851 ifmedia_set(&sc->bge_ifmedia, IFM_ETHER|IFM_AUTO); 2852 /* Pretend the user requested this setting */ 2853 sc->bge_ifmedia.ifm_media = 2854 sc->bge_ifmedia.ifm_cur->ifm_media; 2855 } else { 2856 /* 2857 * Do transceiver setup. 2858 */ 2859 ifmedia_init(&sc->bge_mii.mii_media, 0, bge_ifmedia_upd, 2860 bge_ifmedia_sts); 2861 mii_attach(sc->bge_dev, &sc->bge_mii, 0xffffffff, 2862 MII_PHY_ANY, MII_OFFSET_ANY, 2863 MIIF_FORCEANEG|MIIF_DOPAUSE); 2864 2865 if (LIST_EMPTY(&sc->bge_mii.mii_phys)) { 2866 aprint_error_dev(sc->bge_dev, "no PHY found!\n"); 2867 ifmedia_add(&sc->bge_mii.mii_media, 2868 IFM_ETHER|IFM_MANUAL, 0, NULL); 2869 ifmedia_set(&sc->bge_mii.mii_media, 2870 IFM_ETHER|IFM_MANUAL); 2871 } else 2872 ifmedia_set(&sc->bge_mii.mii_media, 2873 IFM_ETHER|IFM_AUTO); 2874 } 2875 2876 /* 2877 * When using the BCM5701 in PCI-X mode, data corruption has 2878 * been observed in the first few bytes of some received packets. 2879 * Aligning the packet buffer in memory eliminates the corruption. 2880 * Unfortunately, this misaligns the packet payloads. On platforms 2881 * which do not support unaligned accesses, we will realign the 2882 * payloads by copying the received packets. 2883 */ 2884 if (sc->bge_quirks & BGE_QUIRK_PCIX_DMA_ALIGN_BUG) { 2885 /* If in PCI-X mode, work around the alignment bug. */ 2886 if ((pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_PCISTATE) & 2887 (BGE_PCISTATE_PCI_BUSMODE | BGE_PCISTATE_PCI_BUSSPEED)) == 2888 BGE_PCISTATE_PCI_BUSSPEED) 2889 sc->bge_rx_alignment_bug = 1; 2890 } 2891 2892 /* 2893 * Call MI attach routine. 2894 */ 2895 DPRINTFN(5, ("if_attach\n")); 2896 if_attach(ifp); 2897 DPRINTFN(5, ("ether_ifattach\n")); 2898 ether_ifattach(ifp, eaddr); 2899 #if NRND > 0 2900 rnd_attach_source(&sc->rnd_source, device_xname(sc->bge_dev), 2901 RND_TYPE_NET, 0); 2902 #endif 2903 #ifdef BGE_EVENT_COUNTERS 2904 /* 2905 * Attach event counters. 2906 */ 2907 evcnt_attach_dynamic(&sc->bge_ev_intr, EVCNT_TYPE_INTR, 2908 NULL, device_xname(sc->bge_dev), "intr"); 2909 evcnt_attach_dynamic(&sc->bge_ev_tx_xoff, EVCNT_TYPE_MISC, 2910 NULL, device_xname(sc->bge_dev), "tx_xoff"); 2911 evcnt_attach_dynamic(&sc->bge_ev_tx_xon, EVCNT_TYPE_MISC, 2912 NULL, device_xname(sc->bge_dev), "tx_xon"); 2913 evcnt_attach_dynamic(&sc->bge_ev_rx_xoff, EVCNT_TYPE_MISC, 2914 NULL, device_xname(sc->bge_dev), "rx_xoff"); 2915 evcnt_attach_dynamic(&sc->bge_ev_rx_xon, EVCNT_TYPE_MISC, 2916 NULL, device_xname(sc->bge_dev), "rx_xon"); 2917 evcnt_attach_dynamic(&sc->bge_ev_rx_macctl, EVCNT_TYPE_MISC, 2918 NULL, device_xname(sc->bge_dev), "rx_macctl"); 2919 evcnt_attach_dynamic(&sc->bge_ev_xoffentered, EVCNT_TYPE_MISC, 2920 NULL, device_xname(sc->bge_dev), "xoffentered"); 2921 #endif /* BGE_EVENT_COUNTERS */ 2922 DPRINTFN(5, ("callout_init\n")); 2923 callout_init(&sc->bge_timeout, 0); 2924 2925 if (!pmf_device_register(self, NULL, NULL)) 2926 aprint_error_dev(self, "couldn't establish power handler\n"); 2927 else 2928 pmf_class_network_register(self, ifp); 2929 } 2930 2931 static void 2932 bge_release_resources(struct bge_softc *sc) 2933 { 2934 if (sc->bge_vpd_prodname != NULL) 2935 free(sc->bge_vpd_prodname, M_DEVBUF); 2936 2937 if (sc->bge_vpd_readonly != NULL) 2938 free(sc->bge_vpd_readonly, M_DEVBUF); 2939 } 2940 2941 static void 2942 bge_reset(struct bge_softc *sc) 2943 { 2944 u_int32_t cachesize, command, pcistate, new_pcistate; 2945 int i, val; 2946 void (*write_op)(struct bge_softc *, int, int); 2947 2948 if (BGE_IS_5750_OR_BEYOND(sc) && !BGE_IS_5714_FAMILY(sc) && 2949 (BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5906)) { 2950 if (sc->bge_pcie) { 2951 write_op = bge_writemem_direct; 2952 } else { 2953 write_op = bge_writemem_ind; 2954 } 2955 } else { 2956 write_op = bge_writereg_ind; 2957 } 2958 2959 2960 /* Save some important PCI state. */ 2961 cachesize = pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CACHESZ); 2962 command = pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CMD); 2963 pcistate = pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_PCISTATE); 2964 2965 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MISC_CTL, 2966 BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR| 2967 BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_PCISTATE_RW); 2968 2969 /* 2970 * Disable the firmware fastboot feature on 5752 ASIC 2971 * to avoid firmware timeout. 2972 */ 2973 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5752 || 2974 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5755 || 2975 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5787) 2976 CSR_WRITE_4(sc, BGE_FASTBOOT_PC, 0); 2977 2978 val = BGE_MISCCFG_RESET_CORE_CLOCKS | (65<<1); 2979 /* 2980 * XXX: from FreeBSD/Linux; no documentation 2981 */ 2982 if (sc->bge_pcie) { 2983 if (CSR_READ_4(sc, BGE_PCIE_CTL1) == 0x60) 2984 CSR_WRITE_4(sc, BGE_PCIE_CTL1, 0x20); 2985 if (sc->bge_chipid != BGE_CHIPID_BCM5750_A0) { 2986 /* No idea what that actually means */ 2987 CSR_WRITE_4(sc, BGE_MISC_CFG, 1 << 29); 2988 val |= (1<<29); 2989 } 2990 } 2991 2992 /* Issue global reset */ 2993 write_op(sc, BGE_MISC_CFG, val); 2994 2995 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 2996 i = CSR_READ_4(sc, BGE_VCPU_STATUS); 2997 CSR_WRITE_4(sc, BGE_VCPU_STATUS, 2998 i | BGE_VCPU_STATUS_DRV_RESET); 2999 i = CSR_READ_4(sc, BGE_VCPU_EXT_CTRL); 3000 CSR_WRITE_4(sc, BGE_VCPU_EXT_CTRL, 3001 i & ~BGE_VCPU_EXT_CTRL_HALT_CPU); 3002 } 3003 3004 3005 3006 DELAY(1000); 3007 3008 /* 3009 * XXX: from FreeBSD/Linux; no documentation 3010 */ 3011 if (sc->bge_pcie) { 3012 if (sc->bge_chipid == BGE_CHIPID_BCM5750_A0) { 3013 pcireg_t reg; 3014 3015 DELAY(500000); 3016 /* XXX: Magic Numbers */ 3017 reg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_UNKNOWN0); 3018 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_UNKNOWN0, 3019 reg | (1 << 15)); 3020 } 3021 /* 3022 * XXX: Magic Numbers. 3023 * Sets maximal PCI-e payload and clears any PCI-e errors. 3024 * Should be replaced with references to PCI config-space 3025 * capability block for PCI-Express. 3026 */ 3027 pci_conf_write(sc->sc_pc, sc->sc_pcitag, 3028 BGE_PCI_CONF_DEV_CTRL, 0xf5000); 3029 3030 } 3031 3032 /* Reset some of the PCI state that got zapped by reset */ 3033 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MISC_CTL, 3034 BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR| 3035 BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_PCISTATE_RW); 3036 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CMD, command); 3037 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CACHESZ, cachesize); 3038 write_op(sc, BGE_MISC_CFG, (65 << 1)); 3039 3040 /* Enable memory arbiter. */ 3041 { 3042 uint32_t marbmode = 0; 3043 if (BGE_IS_5714_FAMILY(sc)) { 3044 marbmode = CSR_READ_4(sc, BGE_MARB_MODE); 3045 } 3046 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE | marbmode); 3047 } 3048 3049 3050 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 3051 for (i = 0; i < BGE_TIMEOUT; i++) { 3052 val = CSR_READ_4(sc, BGE_VCPU_STATUS); 3053 if (val & BGE_VCPU_STATUS_INIT_DONE) 3054 break; 3055 DELAY(100); 3056 } 3057 if (i == BGE_TIMEOUT) { 3058 aprint_error_dev(sc->bge_dev, "reset timed out\n"); 3059 return; 3060 } 3061 } else { 3062 /* 3063 * Write the magic number to the firmware mailbox at 0xb50 3064 * so that the driver can synchronize with the firmware. 3065 */ 3066 bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM, BGE_MAGIC_NUMBER); 3067 3068 /* 3069 * Poll the value location we just wrote until 3070 * we see the 1's complement of the magic number. 3071 * This indicates that the firmware initialization 3072 * is complete. 3073 */ 3074 for (i = 0; i < BGE_TIMEOUT; i++) { 3075 val = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM); 3076 if (val == ~BGE_MAGIC_NUMBER) 3077 break; 3078 DELAY(1000); 3079 } 3080 3081 if (i >= BGE_TIMEOUT) { 3082 aprint_error_dev(sc->bge_dev, 3083 "firmware handshake timed out, val = %x\n", val); 3084 /* 3085 * XXX: occasionally fired on bcm5721, but without 3086 * apparent harm. For now, keep going if we timeout 3087 * against PCI-E devices. 3088 */ 3089 if (!sc->bge_pcie) 3090 return; 3091 } 3092 } 3093 3094 /* 3095 * XXX Wait for the value of the PCISTATE register to 3096 * return to its original pre-reset state. This is a 3097 * fairly good indicator of reset completion. If we don't 3098 * wait for the reset to fully complete, trying to read 3099 * from the device's non-PCI registers may yield garbage 3100 * results. 3101 */ 3102 for (i = 0; i < 10000; i++) { 3103 new_pcistate = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 3104 BGE_PCI_PCISTATE); 3105 if ((new_pcistate & ~BGE_PCISTATE_RESERVED) == 3106 (pcistate & ~BGE_PCISTATE_RESERVED)) 3107 break; 3108 DELAY(10); 3109 } 3110 if ((new_pcistate & ~BGE_PCISTATE_RESERVED) != 3111 (pcistate & ~BGE_PCISTATE_RESERVED)) { 3112 aprint_error_dev(sc->bge_dev, "pcistate failed to revert\n"); 3113 } 3114 3115 /* XXX: from FreeBSD/Linux; no documentation */ 3116 if (sc->bge_pcie && sc->bge_chipid != BGE_CHIPID_BCM5750_A0) 3117 CSR_WRITE_4(sc, BGE_PCIE_CTL0, CSR_READ_4(sc, BGE_PCIE_CTL0) | (1<<25)); 3118 3119 /* Enable memory arbiter. */ 3120 /* XXX why do this twice? */ 3121 { 3122 uint32_t marbmode = 0; 3123 if (BGE_IS_5714_FAMILY(sc)) { 3124 marbmode = CSR_READ_4(sc, BGE_MARB_MODE); 3125 } 3126 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE | marbmode); 3127 } 3128 3129 /* Fix up byte swapping */ 3130 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS); 3131 3132 CSR_WRITE_4(sc, BGE_MAC_MODE, 0); 3133 3134 DELAY(10000); 3135 } 3136 3137 /* 3138 * Frame reception handling. This is called if there's a frame 3139 * on the receive return list. 3140 * 3141 * Note: we have to be able to handle two possibilities here: 3142 * 1) the frame is from the jumbo recieve ring 3143 * 2) the frame is from the standard receive ring 3144 */ 3145 3146 static void 3147 bge_rxeof(struct bge_softc *sc) 3148 { 3149 struct ifnet *ifp; 3150 int stdcnt = 0, jumbocnt = 0; 3151 bus_dmamap_t dmamap; 3152 bus_addr_t offset, toff; 3153 bus_size_t tlen; 3154 int tosync; 3155 3156 ifp = &sc->ethercom.ec_if; 3157 3158 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 3159 offsetof(struct bge_ring_data, bge_status_block), 3160 sizeof (struct bge_status_block), 3161 BUS_DMASYNC_POSTREAD); 3162 3163 offset = offsetof(struct bge_ring_data, bge_rx_return_ring); 3164 tosync = sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx - 3165 sc->bge_rx_saved_considx; 3166 3167 #if NRND > 0 3168 if (tosync != 0 && RND_ENABLED(&sc->rnd_source)) 3169 rnd_add_uint32(&sc->rnd_source, tosync); 3170 #endif 3171 3172 toff = offset + (sc->bge_rx_saved_considx * sizeof (struct bge_rx_bd)); 3173 3174 if (tosync < 0) { 3175 tlen = (sc->bge_return_ring_cnt - sc->bge_rx_saved_considx) * 3176 sizeof (struct bge_rx_bd); 3177 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 3178 toff, tlen, BUS_DMASYNC_POSTREAD); 3179 tosync = -tosync; 3180 } 3181 3182 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 3183 offset, tosync * sizeof (struct bge_rx_bd), 3184 BUS_DMASYNC_POSTREAD); 3185 3186 while(sc->bge_rx_saved_considx != 3187 sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx) { 3188 struct bge_rx_bd *cur_rx; 3189 u_int32_t rxidx; 3190 struct mbuf *m = NULL; 3191 3192 cur_rx = &sc->bge_rdata-> 3193 bge_rx_return_ring[sc->bge_rx_saved_considx]; 3194 3195 rxidx = cur_rx->bge_idx; 3196 BGE_INC(sc->bge_rx_saved_considx, sc->bge_return_ring_cnt); 3197 3198 if (cur_rx->bge_flags & BGE_RXBDFLAG_JUMBO_RING) { 3199 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT); 3200 m = sc->bge_cdata.bge_rx_jumbo_chain[rxidx]; 3201 sc->bge_cdata.bge_rx_jumbo_chain[rxidx] = NULL; 3202 jumbocnt++; 3203 bus_dmamap_sync(sc->bge_dmatag, 3204 sc->bge_cdata.bge_rx_jumbo_map, 3205 mtod(m, char *) - (char *)sc->bge_cdata.bge_jumbo_buf, 3206 BGE_JLEN, BUS_DMASYNC_POSTREAD); 3207 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 3208 ifp->if_ierrors++; 3209 bge_newbuf_jumbo(sc, sc->bge_jumbo, m); 3210 continue; 3211 } 3212 if (bge_newbuf_jumbo(sc, sc->bge_jumbo, 3213 NULL)== ENOBUFS) { 3214 ifp->if_ierrors++; 3215 bge_newbuf_jumbo(sc, sc->bge_jumbo, m); 3216 continue; 3217 } 3218 } else { 3219 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT); 3220 m = sc->bge_cdata.bge_rx_std_chain[rxidx]; 3221 3222 sc->bge_cdata.bge_rx_std_chain[rxidx] = NULL; 3223 stdcnt++; 3224 dmamap = sc->bge_cdata.bge_rx_std_map[rxidx]; 3225 sc->bge_cdata.bge_rx_std_map[rxidx] = 0; 3226 bus_dmamap_sync(sc->bge_dmatag, dmamap, 0, 3227 dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 3228 bus_dmamap_unload(sc->bge_dmatag, dmamap); 3229 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 3230 ifp->if_ierrors++; 3231 bge_newbuf_std(sc, sc->bge_std, m, dmamap); 3232 continue; 3233 } 3234 if (bge_newbuf_std(sc, sc->bge_std, 3235 NULL, dmamap) == ENOBUFS) { 3236 ifp->if_ierrors++; 3237 bge_newbuf_std(sc, sc->bge_std, m, dmamap); 3238 continue; 3239 } 3240 } 3241 3242 ifp->if_ipackets++; 3243 #ifndef __NO_STRICT_ALIGNMENT 3244 /* 3245 * XXX: if the 5701 PCIX-Rx-DMA workaround is in effect, 3246 * the Rx buffer has the layer-2 header unaligned. 3247 * If our CPU requires alignment, re-align by copying. 3248 */ 3249 if (sc->bge_rx_alignment_bug) { 3250 memmove(mtod(m, char *) + ETHER_ALIGN, m->m_data, 3251 cur_rx->bge_len); 3252 m->m_data += ETHER_ALIGN; 3253 } 3254 #endif 3255 3256 m->m_pkthdr.len = m->m_len = cur_rx->bge_len - ETHER_CRC_LEN; 3257 m->m_pkthdr.rcvif = ifp; 3258 3259 #if NBPFILTER > 0 3260 /* 3261 * Handle BPF listeners. Let the BPF user see the packet. 3262 */ 3263 if (ifp->if_bpf) 3264 bpf_mtap(ifp->if_bpf, m); 3265 #endif 3266 3267 m->m_pkthdr.csum_flags = M_CSUM_IPv4; 3268 3269 if ((cur_rx->bge_ip_csum ^ 0xffff) != 0) 3270 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 3271 /* 3272 * Rx transport checksum-offload may also 3273 * have bugs with packets which, when transmitted, 3274 * were `runts' requiring padding. 3275 */ 3276 if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM && 3277 (/* (sc->_bge_quirks & BGE_QUIRK_SHORT_CKSUM_BUG) == 0 ||*/ 3278 m->m_pkthdr.len >= ETHER_MIN_NOPAD)) { 3279 m->m_pkthdr.csum_data = 3280 cur_rx->bge_tcp_udp_csum; 3281 m->m_pkthdr.csum_flags |= 3282 (M_CSUM_TCPv4|M_CSUM_UDPv4| 3283 M_CSUM_DATA|M_CSUM_NO_PSEUDOHDR); 3284 } 3285 3286 /* 3287 * If we received a packet with a vlan tag, pass it 3288 * to vlan_input() instead of ether_input(). 3289 */ 3290 if (cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) { 3291 VLAN_INPUT_TAG(ifp, m, cur_rx->bge_vlan_tag, continue); 3292 } 3293 3294 (*ifp->if_input)(ifp, m); 3295 } 3296 3297 bge_writembx(sc, BGE_MBX_RX_CONS0_LO, sc->bge_rx_saved_considx); 3298 if (stdcnt) 3299 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std); 3300 if (jumbocnt) 3301 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo); 3302 } 3303 3304 static void 3305 bge_txeof(struct bge_softc *sc) 3306 { 3307 struct bge_tx_bd *cur_tx = NULL; 3308 struct ifnet *ifp; 3309 struct txdmamap_pool_entry *dma; 3310 bus_addr_t offset, toff; 3311 bus_size_t tlen; 3312 int tosync; 3313 struct mbuf *m; 3314 3315 ifp = &sc->ethercom.ec_if; 3316 3317 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 3318 offsetof(struct bge_ring_data, bge_status_block), 3319 sizeof (struct bge_status_block), 3320 BUS_DMASYNC_POSTREAD); 3321 3322 offset = offsetof(struct bge_ring_data, bge_tx_ring); 3323 tosync = sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx - 3324 sc->bge_tx_saved_considx; 3325 3326 #if NRND > 0 3327 if (tosync != 0 && RND_ENABLED(&sc->rnd_source)) 3328 rnd_add_uint32(&sc->rnd_source, tosync); 3329 #endif 3330 3331 toff = offset + (sc->bge_tx_saved_considx * sizeof (struct bge_tx_bd)); 3332 3333 if (tosync < 0) { 3334 tlen = (BGE_TX_RING_CNT - sc->bge_tx_saved_considx) * 3335 sizeof (struct bge_tx_bd); 3336 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 3337 toff, tlen, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 3338 tosync = -tosync; 3339 } 3340 3341 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 3342 offset, tosync * sizeof (struct bge_tx_bd), 3343 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 3344 3345 /* 3346 * Go through our tx ring and free mbufs for those 3347 * frames that have been sent. 3348 */ 3349 while (sc->bge_tx_saved_considx != 3350 sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx) { 3351 u_int32_t idx = 0; 3352 3353 idx = sc->bge_tx_saved_considx; 3354 cur_tx = &sc->bge_rdata->bge_tx_ring[idx]; 3355 if (cur_tx->bge_flags & BGE_TXBDFLAG_END) 3356 ifp->if_opackets++; 3357 m = sc->bge_cdata.bge_tx_chain[idx]; 3358 if (m != NULL) { 3359 sc->bge_cdata.bge_tx_chain[idx] = NULL; 3360 dma = sc->txdma[idx]; 3361 bus_dmamap_sync(sc->bge_dmatag, dma->dmamap, 0, 3362 dma->dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 3363 bus_dmamap_unload(sc->bge_dmatag, dma->dmamap); 3364 SLIST_INSERT_HEAD(&sc->txdma_list, dma, link); 3365 sc->txdma[idx] = NULL; 3366 3367 m_freem(m); 3368 } 3369 sc->bge_txcnt--; 3370 BGE_INC(sc->bge_tx_saved_considx, BGE_TX_RING_CNT); 3371 ifp->if_timer = 0; 3372 } 3373 3374 if (cur_tx != NULL) 3375 ifp->if_flags &= ~IFF_OACTIVE; 3376 } 3377 3378 static int 3379 bge_intr(void *xsc) 3380 { 3381 struct bge_softc *sc; 3382 struct ifnet *ifp; 3383 3384 sc = xsc; 3385 ifp = &sc->ethercom.ec_if; 3386 3387 /* 3388 * Ascertain whether the interrupt is from this bge device. 3389 * Do the cheap test first. 3390 */ 3391 if ((sc->bge_rdata->bge_status_block.bge_status & 3392 BGE_STATFLAG_UPDATED) == 0) { 3393 /* 3394 * Sometimes, the interrupt comes in before the 3395 * DMA update of the status block (performed prior 3396 * to the interrupt itself) has completed. 3397 * In that case, do the (extremely expensive!) 3398 * PCI-config-space register read. 3399 */ 3400 uint32_t pcistate = 3401 pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_PCISTATE); 3402 3403 if (pcistate & BGE_PCISTATE_INTR_STATE) 3404 return (0); 3405 3406 } 3407 /* 3408 * If we reach here, then the interrupt is for us. 3409 */ 3410 3411 /* Ack interrupt and stop others from occuring. */ 3412 bge_writembx(sc, BGE_MBX_IRQ0_LO, 1); 3413 3414 BGE_EVCNT_INCR(sc->bge_ev_intr); 3415 3416 /* 3417 * Process link state changes. 3418 * Grrr. The link status word in the status block does 3419 * not work correctly on the BCM5700 rev AX and BX chips, 3420 * according to all available information. Hence, we have 3421 * to enable MII interrupts in order to properly obtain 3422 * async link changes. Unfortunately, this also means that 3423 * we have to read the MAC status register to detect link 3424 * changes, thereby adding an additional register access to 3425 * the interrupt handler. 3426 */ 3427 3428 if (sc->bge_quirks & BGE_QUIRK_LINK_STATE_BROKEN) { 3429 u_int32_t status; 3430 3431 status = CSR_READ_4(sc, BGE_MAC_STS); 3432 if (status & BGE_MACSTAT_MI_INTERRUPT) { 3433 sc->bge_link = 0; 3434 callout_stop(&sc->bge_timeout); 3435 bge_tick(sc); 3436 /* Clear the interrupt */ 3437 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, 3438 BGE_EVTENB_MI_INTERRUPT); 3439 bge_miibus_readreg(sc->bge_dev, 1, BRGPHY_MII_ISR); 3440 bge_miibus_writereg(sc->bge_dev, 1, BRGPHY_MII_IMR, 3441 BRGPHY_INTRS); 3442 } 3443 } else { 3444 u_int32_t status; 3445 3446 status = CSR_READ_4(sc, BGE_MAC_STS); 3447 if (status & BGE_MACSTAT_LINK_CHANGED) { 3448 sc->bge_link = 0; 3449 callout_stop(&sc->bge_timeout); 3450 bge_tick(sc); 3451 /* Clear the interrupt */ 3452 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED| 3453 BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE| 3454 BGE_MACSTAT_LINK_CHANGED); 3455 } 3456 } 3457 3458 if (ifp->if_flags & IFF_RUNNING) { 3459 /* Check RX return ring producer/consumer */ 3460 bge_rxeof(sc); 3461 3462 /* Check TX ring producer/consumer */ 3463 bge_txeof(sc); 3464 } 3465 3466 if (sc->bge_pending_rxintr_change) { 3467 uint32_t rx_ticks = sc->bge_rx_coal_ticks; 3468 uint32_t rx_bds = sc->bge_rx_max_coal_bds; 3469 uint32_t junk; 3470 3471 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, rx_ticks); 3472 DELAY(10); 3473 junk = CSR_READ_4(sc, BGE_HCC_RX_COAL_TICKS); 3474 3475 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, rx_bds); 3476 DELAY(10); 3477 junk = CSR_READ_4(sc, BGE_HCC_RX_MAX_COAL_BDS); 3478 3479 sc->bge_pending_rxintr_change = 0; 3480 } 3481 bge_handle_events(sc); 3482 3483 /* Re-enable interrupts. */ 3484 bge_writembx(sc, BGE_MBX_IRQ0_LO, 0); 3485 3486 if (ifp->if_flags & IFF_RUNNING && !IFQ_IS_EMPTY(&ifp->if_snd)) 3487 bge_start(ifp); 3488 3489 return (1); 3490 } 3491 3492 static void 3493 bge_tick(void *xsc) 3494 { 3495 struct bge_softc *sc = xsc; 3496 struct mii_data *mii = &sc->bge_mii; 3497 int s; 3498 3499 s = splnet(); 3500 3501 bge_stats_update(sc); 3502 callout_reset(&sc->bge_timeout, hz, bge_tick, sc); 3503 3504 if (sc->bge_tbi) { 3505 if (CSR_READ_4(sc, BGE_MAC_STS) & 3506 BGE_MACSTAT_TBI_PCS_SYNCHED) { 3507 CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF); 3508 } 3509 } else 3510 mii_tick(mii); 3511 3512 splx(s); 3513 } 3514 3515 static void 3516 bge_stats_update(struct bge_softc *sc) 3517 { 3518 struct ifnet *ifp = &sc->ethercom.ec_if; 3519 bus_size_t stats = BGE_MEMWIN_START + BGE_STATS_BLOCK; 3520 bus_size_t rstats = BGE_RX_STATS; 3521 3522 #define READ_RSTAT(sc, stats, stat) \ 3523 CSR_READ_4(sc, stats + offsetof(struct bge_mac_stats_regs, stat)) 3524 3525 if (sc->bge_quirks & BGE_QUIRK_5705_CORE) { 3526 ifp->if_collisions += 3527 READ_RSTAT(sc, rstats, dot3StatsSingleCollisionFrames) + 3528 READ_RSTAT(sc, rstats, dot3StatsMultipleCollisionFrames) + 3529 READ_RSTAT(sc, rstats, dot3StatsExcessiveCollisions) + 3530 READ_RSTAT(sc, rstats, dot3StatsLateCollisions); 3531 3532 BGE_EVCNT_ADD(sc->bge_ev_tx_xoff, 3533 READ_RSTAT(sc, rstats, outXoffSent)); 3534 BGE_EVCNT_ADD(sc->bge_ev_tx_xon, 3535 READ_RSTAT(sc, rstats, outXonSent)); 3536 BGE_EVCNT_ADD(sc->bge_ev_rx_xoff, 3537 READ_RSTAT(sc, rstats, xoffPauseFramesReceived)); 3538 BGE_EVCNT_ADD(sc->bge_ev_rx_xon, 3539 READ_RSTAT(sc, rstats, xonPauseFramesReceived)); 3540 BGE_EVCNT_ADD(sc->bge_ev_rx_macctl, 3541 READ_RSTAT(sc, rstats, macControlFramesReceived)); 3542 BGE_EVCNT_ADD(sc->bge_ev_xoffentered, 3543 READ_RSTAT(sc, rstats, xoffStateEntered)); 3544 return; 3545 } 3546 3547 #undef READ_RSTAT 3548 #define READ_STAT(sc, stats, stat) \ 3549 CSR_READ_4(sc, stats + offsetof(struct bge_stats, stat)) 3550 3551 ifp->if_collisions += 3552 (READ_STAT(sc, stats, dot3StatsSingleCollisionFrames.bge_addr_lo) + 3553 READ_STAT(sc, stats, dot3StatsMultipleCollisionFrames.bge_addr_lo) + 3554 READ_STAT(sc, stats, dot3StatsExcessiveCollisions.bge_addr_lo) + 3555 READ_STAT(sc, stats, dot3StatsLateCollisions.bge_addr_lo)) - 3556 ifp->if_collisions; 3557 3558 BGE_EVCNT_UPD(sc->bge_ev_tx_xoff, 3559 READ_STAT(sc, stats, outXoffSent.bge_addr_lo)); 3560 BGE_EVCNT_UPD(sc->bge_ev_tx_xon, 3561 READ_STAT(sc, stats, outXonSent.bge_addr_lo)); 3562 BGE_EVCNT_UPD(sc->bge_ev_rx_xoff, 3563 READ_STAT(sc, stats, 3564 xoffPauseFramesReceived.bge_addr_lo)); 3565 BGE_EVCNT_UPD(sc->bge_ev_rx_xon, 3566 READ_STAT(sc, stats, xonPauseFramesReceived.bge_addr_lo)); 3567 BGE_EVCNT_UPD(sc->bge_ev_rx_macctl, 3568 READ_STAT(sc, stats, 3569 macControlFramesReceived.bge_addr_lo)); 3570 BGE_EVCNT_UPD(sc->bge_ev_xoffentered, 3571 READ_STAT(sc, stats, xoffStateEntered.bge_addr_lo)); 3572 3573 #undef READ_STAT 3574 3575 #ifdef notdef 3576 ifp->if_collisions += 3577 (sc->bge_rdata->bge_info.bge_stats.dot3StatsSingleCollisionFrames + 3578 sc->bge_rdata->bge_info.bge_stats.dot3StatsMultipleCollisionFrames + 3579 sc->bge_rdata->bge_info.bge_stats.dot3StatsExcessiveCollisions + 3580 sc->bge_rdata->bge_info.bge_stats.dot3StatsLateCollisions) - 3581 ifp->if_collisions; 3582 #endif 3583 } 3584 3585 /* 3586 * Pad outbound frame to ETHER_MIN_NOPAD for an unusual reason. 3587 * The bge hardware will pad out Tx runts to ETHER_MIN_NOPAD, 3588 * but when such padded frames employ the bge IP/TCP checksum offload, 3589 * the hardware checksum assist gives incorrect results (possibly 3590 * from incorporating its own padding into the UDP/TCP checksum; who knows). 3591 * If we pad such runts with zeros, the onboard checksum comes out correct. 3592 */ 3593 static inline int 3594 bge_cksum_pad(struct mbuf *pkt) 3595 { 3596 struct mbuf *last = NULL; 3597 int padlen; 3598 3599 padlen = ETHER_MIN_NOPAD - pkt->m_pkthdr.len; 3600 3601 /* if there's only the packet-header and we can pad there, use it. */ 3602 if (pkt->m_pkthdr.len == pkt->m_len && 3603 M_TRAILINGSPACE(pkt) >= padlen) { 3604 last = pkt; 3605 } else { 3606 /* 3607 * Walk packet chain to find last mbuf. We will either 3608 * pad there, or append a new mbuf and pad it 3609 * (thus perhaps avoiding the bcm5700 dma-min bug). 3610 */ 3611 for (last = pkt; last->m_next != NULL; last = last->m_next) { 3612 continue; /* do nothing */ 3613 } 3614 3615 /* `last' now points to last in chain. */ 3616 if (M_TRAILINGSPACE(last) < padlen) { 3617 /* Allocate new empty mbuf, pad it. Compact later. */ 3618 struct mbuf *n; 3619 MGET(n, M_DONTWAIT, MT_DATA); 3620 if (n == NULL) 3621 return ENOBUFS; 3622 n->m_len = 0; 3623 last->m_next = n; 3624 last = n; 3625 } 3626 } 3627 3628 KDASSERT(!M_READONLY(last)); 3629 KDASSERT(M_TRAILINGSPACE(last) >= padlen); 3630 3631 /* Now zero the pad area, to avoid the bge cksum-assist bug */ 3632 memset(mtod(last, char *) + last->m_len, 0, padlen); 3633 last->m_len += padlen; 3634 pkt->m_pkthdr.len += padlen; 3635 return 0; 3636 } 3637 3638 /* 3639 * Compact outbound packets to avoid bug with DMA segments less than 8 bytes. 3640 */ 3641 static inline int 3642 bge_compact_dma_runt(struct mbuf *pkt) 3643 { 3644 struct mbuf *m, *prev; 3645 int totlen, prevlen; 3646 3647 prev = NULL; 3648 totlen = 0; 3649 prevlen = -1; 3650 3651 for (m = pkt; m != NULL; prev = m,m = m->m_next) { 3652 int mlen = m->m_len; 3653 int shortfall = 8 - mlen ; 3654 3655 totlen += mlen; 3656 if (mlen == 0) { 3657 continue; 3658 } 3659 if (mlen >= 8) 3660 continue; 3661 3662 /* If we get here, mbuf data is too small for DMA engine. 3663 * Try to fix by shuffling data to prev or next in chain. 3664 * If that fails, do a compacting deep-copy of the whole chain. 3665 */ 3666 3667 /* Internal frag. If fits in prev, copy it there. */ 3668 if (prev && M_TRAILINGSPACE(prev) >= m->m_len) { 3669 memcpy(prev->m_data + prev->m_len, m->m_data, mlen); 3670 prev->m_len += mlen; 3671 m->m_len = 0; 3672 /* XXX stitch chain */ 3673 prev->m_next = m_free(m); 3674 m = prev; 3675 continue; 3676 } 3677 else if (m->m_next != NULL && 3678 M_TRAILINGSPACE(m) >= shortfall && 3679 m->m_next->m_len >= (8 + shortfall)) { 3680 /* m is writable and have enough data in next, pull up. */ 3681 3682 memcpy(m->m_data + m->m_len, m->m_next->m_data, 3683 shortfall); 3684 m->m_len += shortfall; 3685 m->m_next->m_len -= shortfall; 3686 m->m_next->m_data += shortfall; 3687 } 3688 else if (m->m_next == NULL || 1) { 3689 /* Got a runt at the very end of the packet. 3690 * borrow data from the tail of the preceding mbuf and 3691 * update its length in-place. (The original data is still 3692 * valid, so we can do this even if prev is not writable.) 3693 */ 3694 3695 /* if we'd make prev a runt, just move all of its data. */ 3696 KASSERT(prev != NULL /*, ("runt but null PREV")*/); 3697 KASSERT(prev->m_len >= 8 /*, ("runt prev")*/); 3698 3699 if ((prev->m_len - shortfall) < 8) 3700 shortfall = prev->m_len; 3701 3702 #ifdef notyet /* just do the safe slow thing for now */ 3703 if (!M_READONLY(m)) { 3704 if (M_LEADINGSPACE(m) < shorfall) { 3705 void *m_dat; 3706 m_dat = (m->m_flags & M_PKTHDR) ? 3707 m->m_pktdat : m->dat; 3708 memmove(m_dat, mtod(m, void*), m->m_len); 3709 m->m_data = m_dat; 3710 } 3711 } else 3712 #endif /* just do the safe slow thing */ 3713 { 3714 struct mbuf * n = NULL; 3715 int newprevlen = prev->m_len - shortfall; 3716 3717 MGET(n, M_NOWAIT, MT_DATA); 3718 if (n == NULL) 3719 return ENOBUFS; 3720 KASSERT(m->m_len + shortfall < MLEN 3721 /*, 3722 ("runt %d +prev %d too big\n", m->m_len, shortfall)*/); 3723 3724 /* first copy the data we're stealing from prev */ 3725 memcpy(n->m_data, prev->m_data + newprevlen, 3726 shortfall); 3727 3728 /* update prev->m_len accordingly */ 3729 prev->m_len -= shortfall; 3730 3731 /* copy data from runt m */ 3732 memcpy(n->m_data + shortfall, m->m_data, 3733 m->m_len); 3734 3735 /* n holds what we stole from prev, plus m */ 3736 n->m_len = shortfall + m->m_len; 3737 3738 /* stitch n into chain and free m */ 3739 n->m_next = m->m_next; 3740 prev->m_next = n; 3741 /* KASSERT(m->m_next == NULL); */ 3742 m->m_next = NULL; 3743 m_free(m); 3744 m = n; /* for continuing loop */ 3745 } 3746 } 3747 prevlen = m->m_len; 3748 } 3749 return 0; 3750 } 3751 3752 /* 3753 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data 3754 * pointers to descriptors. 3755 */ 3756 static int 3757 bge_encap(struct bge_softc *sc, struct mbuf *m_head, u_int32_t *txidx) 3758 { 3759 struct bge_tx_bd *f = NULL; 3760 u_int32_t frag, cur; 3761 u_int16_t csum_flags = 0; 3762 u_int16_t txbd_tso_flags = 0; 3763 struct txdmamap_pool_entry *dma; 3764 bus_dmamap_t dmamap; 3765 int i = 0; 3766 struct m_tag *mtag; 3767 int use_tso, maxsegsize, error; 3768 3769 cur = frag = *txidx; 3770 3771 if (m_head->m_pkthdr.csum_flags) { 3772 if (m_head->m_pkthdr.csum_flags & M_CSUM_IPv4) 3773 csum_flags |= BGE_TXBDFLAG_IP_CSUM; 3774 if (m_head->m_pkthdr.csum_flags & (M_CSUM_TCPv4|M_CSUM_UDPv4)) 3775 csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM; 3776 } 3777 3778 /* 3779 * If we were asked to do an outboard checksum, and the NIC 3780 * has the bug where it sometimes adds in the Ethernet padding, 3781 * explicitly pad with zeros so the cksum will be correct either way. 3782 * (For now, do this for all chip versions, until newer 3783 * are confirmed to not require the workaround.) 3784 */ 3785 if ((csum_flags & BGE_TXBDFLAG_TCP_UDP_CSUM) == 0 || 3786 #ifdef notyet 3787 (sc->bge_quirks & BGE_QUIRK_SHORT_CKSUM_BUG) == 0 || 3788 #endif 3789 m_head->m_pkthdr.len >= ETHER_MIN_NOPAD) 3790 goto check_dma_bug; 3791 3792 if (bge_cksum_pad(m_head) != 0) { 3793 return ENOBUFS; 3794 } 3795 3796 check_dma_bug: 3797 if (!(sc->bge_quirks & BGE_QUIRK_5700_SMALLDMA)) 3798 goto doit; 3799 /* 3800 * bcm5700 Revision B silicon cannot handle DMA descriptors with 3801 * less than eight bytes. If we encounter a teeny mbuf 3802 * at the end of a chain, we can pad. Otherwise, copy. 3803 */ 3804 if (bge_compact_dma_runt(m_head) != 0) 3805 return ENOBUFS; 3806 3807 doit: 3808 dma = SLIST_FIRST(&sc->txdma_list); 3809 if (dma == NULL) 3810 return ENOBUFS; 3811 dmamap = dma->dmamap; 3812 3813 /* 3814 * Set up any necessary TSO state before we start packing... 3815 */ 3816 use_tso = (m_head->m_pkthdr.csum_flags & M_CSUM_TSOv4) != 0; 3817 if (!use_tso) { 3818 maxsegsize = 0; 3819 } else { /* TSO setup */ 3820 unsigned mss; 3821 struct ether_header *eh; 3822 unsigned ip_tcp_hlen, iptcp_opt_words, tcp_seg_flags, offset; 3823 struct mbuf * m0 = m_head; 3824 struct ip *ip; 3825 struct tcphdr *th; 3826 int iphl, hlen; 3827 3828 /* 3829 * XXX It would be nice if the mbuf pkthdr had offset 3830 * fields for the protocol headers. 3831 */ 3832 3833 eh = mtod(m0, struct ether_header *); 3834 switch (htons(eh->ether_type)) { 3835 case ETHERTYPE_IP: 3836 offset = ETHER_HDR_LEN; 3837 break; 3838 3839 case ETHERTYPE_VLAN: 3840 offset = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 3841 break; 3842 3843 default: 3844 /* 3845 * Don't support this protocol or encapsulation. 3846 */ 3847 return (ENOBUFS); 3848 } 3849 3850 /* 3851 * TCP/IP headers are in the first mbuf; we can do 3852 * this the easy way. 3853 */ 3854 iphl = M_CSUM_DATA_IPv4_IPHL(m0->m_pkthdr.csum_data); 3855 hlen = iphl + offset; 3856 if (__predict_false(m0->m_len < 3857 (hlen + sizeof(struct tcphdr)))) { 3858 3859 aprint_debug_dev(sc->bge_dev, 3860 "TSO: hard case m0->m_len == %d < ip/tcp hlen %zd," 3861 "not handled yet\n", 3862 m0->m_len, hlen+ sizeof(struct tcphdr)); 3863 #ifdef NOTYET 3864 /* 3865 * XXX jonathan (at) NetBSD.org: untested. 3866 * how to force this branch to be taken? 3867 */ 3868 BGE_EVCNT_INCR(&sc->sc_ev_txtsopain); 3869 3870 m_copydata(m0, offset, sizeof(ip), &ip); 3871 m_copydata(m0, hlen, sizeof(th), &th); 3872 3873 ip.ip_len = 0; 3874 3875 m_copyback(m0, hlen + offsetof(struct ip, ip_len), 3876 sizeof(ip.ip_len), &ip.ip_len); 3877 3878 th.th_sum = in_cksum_phdr(ip.ip_src.s_addr, 3879 ip.ip_dst.s_addr, htons(IPPROTO_TCP)); 3880 3881 m_copyback(m0, hlen + offsetof(struct tcphdr, th_sum), 3882 sizeof(th.th_sum), &th.th_sum); 3883 3884 hlen += th.th_off << 2; 3885 iptcp_opt_words = hlen; 3886 #else 3887 /* 3888 * if_wm "hard" case not yet supported, can we not 3889 * mandate it out of existence? 3890 */ 3891 (void) ip; (void)th; (void) ip_tcp_hlen; 3892 3893 return ENOBUFS; 3894 #endif 3895 } else { 3896 ip = (struct ip *) (mtod(m0, char *) + offset); 3897 th = (struct tcphdr *) (mtod(m0, char *) + hlen); 3898 ip_tcp_hlen = iphl + (th->th_off << 2); 3899 3900 /* Total IP/TCP options, in 32-bit words */ 3901 iptcp_opt_words = (ip_tcp_hlen 3902 - sizeof(struct tcphdr) 3903 - sizeof(struct ip)) >> 2; 3904 } 3905 if (BGE_IS_5750_OR_BEYOND(sc)) { 3906 th->th_sum = 0; 3907 csum_flags &= ~(BGE_TXBDFLAG_TCP_UDP_CSUM); 3908 } else { 3909 /* 3910 * XXX jonathan (at) NetBSD.org: 5705 untested. 3911 * Requires TSO firmware patch for 5701/5703/5704. 3912 */ 3913 th->th_sum = in_cksum_phdr(ip->ip_src.s_addr, 3914 ip->ip_dst.s_addr, htons(IPPROTO_TCP)); 3915 } 3916 3917 mss = m_head->m_pkthdr.segsz; 3918 txbd_tso_flags |= 3919 BGE_TXBDFLAG_CPU_PRE_DMA | 3920 BGE_TXBDFLAG_CPU_POST_DMA; 3921 3922 /* 3923 * Our NIC TSO-assist assumes TSO has standard, optionless 3924 * IPv4 and TCP headers, which total 40 bytes. By default, 3925 * the NIC copies 40 bytes of IP/TCP header from the 3926 * supplied header into the IP/TCP header portion of 3927 * each post-TSO-segment. If the supplied packet has IP or 3928 * TCP options, we need to tell the NIC to copy those extra 3929 * bytes into each post-TSO header, in addition to the normal 3930 * 40-byte IP/TCP header (and to leave space accordingly). 3931 * Unfortunately, the driver encoding of option length 3932 * varies across different ASIC families. 3933 */ 3934 tcp_seg_flags = 0; 3935 if (iptcp_opt_words) { 3936 if ( BGE_IS_5705_OR_BEYOND(sc)) { 3937 tcp_seg_flags = 3938 iptcp_opt_words << 11; 3939 } else { 3940 txbd_tso_flags |= 3941 iptcp_opt_words << 12; 3942 } 3943 } 3944 maxsegsize = mss | tcp_seg_flags; 3945 ip->ip_len = htons(mss + ip_tcp_hlen); 3946 3947 } /* TSO setup */ 3948 3949 /* 3950 * Start packing the mbufs in this chain into 3951 * the fragment pointers. Stop when we run out 3952 * of fragments or hit the end of the mbuf chain. 3953 */ 3954 error = bus_dmamap_load_mbuf(sc->bge_dmatag, dmamap, m_head, 3955 BUS_DMA_NOWAIT); 3956 if (error) { 3957 return(ENOBUFS); 3958 } 3959 /* 3960 * Sanity check: avoid coming within 16 descriptors 3961 * of the end of the ring. 3962 */ 3963 if (dmamap->dm_nsegs > (BGE_TX_RING_CNT - sc->bge_txcnt - 16)) { 3964 BGE_TSO_PRINTF(("%s: " 3965 " dmamap_load_mbuf too close to ring wrap\n", 3966 device_xname(sc->bge_dev))); 3967 goto fail_unload; 3968 } 3969 3970 mtag = sc->ethercom.ec_nvlans ? 3971 m_tag_find(m_head, PACKET_TAG_VLAN, NULL) : NULL; 3972 3973 3974 /* Iterate over dmap-map fragments. */ 3975 for (i = 0; i < dmamap->dm_nsegs; i++) { 3976 f = &sc->bge_rdata->bge_tx_ring[frag]; 3977 if (sc->bge_cdata.bge_tx_chain[frag] != NULL) 3978 break; 3979 3980 bge_set_hostaddr(&f->bge_addr, dmamap->dm_segs[i].ds_addr); 3981 f->bge_len = dmamap->dm_segs[i].ds_len; 3982 3983 /* 3984 * For 5751 and follow-ons, for TSO we must turn 3985 * off checksum-assist flag in the tx-descr, and 3986 * supply the ASIC-revision-specific encoding 3987 * of TSO flags and segsize. 3988 */ 3989 if (use_tso) { 3990 if (BGE_IS_5750_OR_BEYOND(sc) || i == 0) { 3991 f->bge_rsvd = maxsegsize; 3992 f->bge_flags = csum_flags | txbd_tso_flags; 3993 } else { 3994 f->bge_rsvd = 0; 3995 f->bge_flags = 3996 (csum_flags | txbd_tso_flags) & 0x0fff; 3997 } 3998 } else { 3999 f->bge_rsvd = 0; 4000 f->bge_flags = csum_flags; 4001 } 4002 4003 if (mtag != NULL) { 4004 f->bge_flags |= BGE_TXBDFLAG_VLAN_TAG; 4005 f->bge_vlan_tag = VLAN_TAG_VALUE(mtag); 4006 } else { 4007 f->bge_vlan_tag = 0; 4008 } 4009 cur = frag; 4010 BGE_INC(frag, BGE_TX_RING_CNT); 4011 } 4012 4013 if (i < dmamap->dm_nsegs) { 4014 BGE_TSO_PRINTF(("%s: reached %d < dm_nsegs %d\n", 4015 device_xname(sc->bge_dev), i, dmamap->dm_nsegs)); 4016 goto fail_unload; 4017 } 4018 4019 bus_dmamap_sync(sc->bge_dmatag, dmamap, 0, dmamap->dm_mapsize, 4020 BUS_DMASYNC_PREWRITE); 4021 4022 if (frag == sc->bge_tx_saved_considx) { 4023 BGE_TSO_PRINTF(("%s: frag %d = wrapped id %d?\n", 4024 device_xname(sc->bge_dev), frag, sc->bge_tx_saved_considx)); 4025 4026 goto fail_unload; 4027 } 4028 4029 sc->bge_rdata->bge_tx_ring[cur].bge_flags |= BGE_TXBDFLAG_END; 4030 sc->bge_cdata.bge_tx_chain[cur] = m_head; 4031 SLIST_REMOVE_HEAD(&sc->txdma_list, link); 4032 sc->txdma[cur] = dma; 4033 sc->bge_txcnt += dmamap->dm_nsegs; 4034 4035 *txidx = frag; 4036 4037 return(0); 4038 4039 fail_unload: 4040 bus_dmamap_unload(sc->bge_dmatag, dmamap); 4041 4042 return ENOBUFS; 4043 } 4044 4045 /* 4046 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 4047 * to the mbuf data regions directly in the transmit descriptors. 4048 */ 4049 static void 4050 bge_start(struct ifnet *ifp) 4051 { 4052 struct bge_softc *sc; 4053 struct mbuf *m_head = NULL; 4054 u_int32_t prodidx; 4055 int pkts = 0; 4056 4057 sc = ifp->if_softc; 4058 4059 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 4060 return; 4061 4062 prodidx = sc->bge_tx_prodidx; 4063 4064 while(sc->bge_cdata.bge_tx_chain[prodidx] == NULL) { 4065 IFQ_POLL(&ifp->if_snd, m_head); 4066 if (m_head == NULL) 4067 break; 4068 4069 #if 0 4070 /* 4071 * XXX 4072 * safety overkill. If this is a fragmented packet chain 4073 * with delayed TCP/UDP checksums, then only encapsulate 4074 * it if we have enough descriptors to handle the entire 4075 * chain at once. 4076 * (paranoia -- may not actually be needed) 4077 */ 4078 if (m_head->m_flags & M_FIRSTFRAG && 4079 m_head->m_pkthdr.csum_flags & (CSUM_DELAY_DATA)) { 4080 if ((BGE_TX_RING_CNT - sc->bge_txcnt) < 4081 M_CSUM_DATA_IPv4_OFFSET(m_head->m_pkthdr.csum_data) + 16) { 4082 ifp->if_flags |= IFF_OACTIVE; 4083 break; 4084 } 4085 } 4086 #endif 4087 4088 /* 4089 * Pack the data into the transmit ring. If we 4090 * don't have room, set the OACTIVE flag and wait 4091 * for the NIC to drain the ring. 4092 */ 4093 if (bge_encap(sc, m_head, &prodidx)) { 4094 ifp->if_flags |= IFF_OACTIVE; 4095 break; 4096 } 4097 4098 /* now we are committed to transmit the packet */ 4099 IFQ_DEQUEUE(&ifp->if_snd, m_head); 4100 pkts++; 4101 4102 #if NBPFILTER > 0 4103 /* 4104 * If there's a BPF listener, bounce a copy of this frame 4105 * to him. 4106 */ 4107 if (ifp->if_bpf) 4108 bpf_mtap(ifp->if_bpf, m_head); 4109 #endif 4110 } 4111 if (pkts == 0) 4112 return; 4113 4114 /* Transmit */ 4115 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); 4116 if (sc->bge_quirks & BGE_QUIRK_PRODUCER_BUG) /* 5700 b2 errata */ 4117 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); 4118 4119 sc->bge_tx_prodidx = prodidx; 4120 4121 /* 4122 * Set a timeout in case the chip goes out to lunch. 4123 */ 4124 ifp->if_timer = 5; 4125 } 4126 4127 static int 4128 bge_init(struct ifnet *ifp) 4129 { 4130 struct bge_softc *sc = ifp->if_softc; 4131 const u_int16_t *m; 4132 int s, error = 0; 4133 4134 s = splnet(); 4135 4136 ifp = &sc->ethercom.ec_if; 4137 4138 /* Cancel pending I/O and flush buffers. */ 4139 bge_stop(ifp, 0); 4140 bge_reset(sc); 4141 bge_chipinit(sc); 4142 4143 /* 4144 * Init the various state machines, ring 4145 * control blocks and firmware. 4146 */ 4147 error = bge_blockinit(sc); 4148 if (error != 0) { 4149 aprint_error_dev(sc->bge_dev, "initialization error %d\n", 4150 error); 4151 splx(s); 4152 return error; 4153 } 4154 4155 ifp = &sc->ethercom.ec_if; 4156 4157 /* Specify MTU. */ 4158 CSR_WRITE_4(sc, BGE_RX_MTU, ifp->if_mtu + 4159 ETHER_HDR_LEN + ETHER_CRC_LEN + ETHER_VLAN_ENCAP_LEN); 4160 4161 /* Load our MAC address. */ 4162 m = (const u_int16_t *)&(CLLADDR(ifp->if_sadl)[0]); 4163 CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0])); 4164 CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, (htons(m[1]) << 16) | htons(m[2])); 4165 4166 /* Enable or disable promiscuous mode as needed. */ 4167 if (ifp->if_flags & IFF_PROMISC) { 4168 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 4169 } else { 4170 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 4171 } 4172 4173 /* Program multicast filter. */ 4174 bge_setmulti(sc); 4175 4176 /* Init RX ring. */ 4177 bge_init_rx_ring_std(sc); 4178 4179 /* Init jumbo RX ring. */ 4180 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 4181 bge_init_rx_ring_jumbo(sc); 4182 4183 /* Init our RX return ring index */ 4184 sc->bge_rx_saved_considx = 0; 4185 4186 /* Init TX ring. */ 4187 bge_init_tx_ring(sc); 4188 4189 /* Turn on transmitter */ 4190 BGE_SETBIT(sc, BGE_TX_MODE, BGE_TXMODE_ENABLE); 4191 4192 /* Turn on receiver */ 4193 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE); 4194 4195 CSR_WRITE_4(sc, BGE_MAX_RX_FRAME_LOWAT, 2); 4196 4197 /* Tell firmware we're alive. */ 4198 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 4199 4200 /* Enable host interrupts. */ 4201 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA); 4202 BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); 4203 bge_writembx(sc, BGE_MBX_IRQ0_LO, 0); 4204 4205 if ((error = bge_ifmedia_upd(ifp)) != 0) 4206 goto out; 4207 4208 ifp->if_flags |= IFF_RUNNING; 4209 ifp->if_flags &= ~IFF_OACTIVE; 4210 4211 callout_reset(&sc->bge_timeout, hz, bge_tick, sc); 4212 4213 out: 4214 splx(s); 4215 4216 return error; 4217 } 4218 4219 /* 4220 * Set media options. 4221 */ 4222 static int 4223 bge_ifmedia_upd(struct ifnet *ifp) 4224 { 4225 struct bge_softc *sc = ifp->if_softc; 4226 struct mii_data *mii = &sc->bge_mii; 4227 struct ifmedia *ifm = &sc->bge_ifmedia; 4228 int rc; 4229 4230 /* If this is a 1000baseX NIC, enable the TBI port. */ 4231 if (sc->bge_tbi) { 4232 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 4233 return(EINVAL); 4234 switch(IFM_SUBTYPE(ifm->ifm_media)) { 4235 case IFM_AUTO: 4236 break; 4237 case IFM_1000_SX: 4238 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 4239 BGE_CLRBIT(sc, BGE_MAC_MODE, 4240 BGE_MACMODE_HALF_DUPLEX); 4241 } else { 4242 BGE_SETBIT(sc, BGE_MAC_MODE, 4243 BGE_MACMODE_HALF_DUPLEX); 4244 } 4245 break; 4246 default: 4247 return(EINVAL); 4248 } 4249 /* XXX 802.3x flow control for 1000BASE-SX */ 4250 return(0); 4251 } 4252 4253 sc->bge_link = 0; 4254 if ((rc = mii_mediachg(mii)) == ENXIO) 4255 return 0; 4256 return rc; 4257 } 4258 4259 /* 4260 * Report current media status. 4261 */ 4262 static void 4263 bge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 4264 { 4265 struct bge_softc *sc = ifp->if_softc; 4266 struct mii_data *mii = &sc->bge_mii; 4267 4268 if (sc->bge_tbi) { 4269 ifmr->ifm_status = IFM_AVALID; 4270 ifmr->ifm_active = IFM_ETHER; 4271 if (CSR_READ_4(sc, BGE_MAC_STS) & 4272 BGE_MACSTAT_TBI_PCS_SYNCHED) 4273 ifmr->ifm_status |= IFM_ACTIVE; 4274 ifmr->ifm_active |= IFM_1000_SX; 4275 if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX) 4276 ifmr->ifm_active |= IFM_HDX; 4277 else 4278 ifmr->ifm_active |= IFM_FDX; 4279 return; 4280 } 4281 4282 mii_pollstat(mii); 4283 ifmr->ifm_status = mii->mii_media_status; 4284 ifmr->ifm_active = (mii->mii_media_active & ~IFM_ETH_FMASK) | 4285 sc->bge_flowflags; 4286 } 4287 4288 static int 4289 bge_ioctl(struct ifnet *ifp, u_long command, void *data) 4290 { 4291 struct bge_softc *sc = ifp->if_softc; 4292 struct ifreq *ifr = (struct ifreq *) data; 4293 int s, error = 0; 4294 struct mii_data *mii; 4295 4296 s = splnet(); 4297 4298 switch(command) { 4299 case SIOCSIFFLAGS: 4300 if ((error = ifioctl_common(ifp, command, data)) != 0) 4301 break; 4302 if (ifp->if_flags & IFF_UP) { 4303 /* 4304 * If only the state of the PROMISC flag changed, 4305 * then just use the 'set promisc mode' command 4306 * instead of reinitializing the entire NIC. Doing 4307 * a full re-init means reloading the firmware and 4308 * waiting for it to start up, which may take a 4309 * second or two. 4310 */ 4311 if (ifp->if_flags & IFF_RUNNING && 4312 ifp->if_flags & IFF_PROMISC && 4313 !(sc->bge_if_flags & IFF_PROMISC)) { 4314 BGE_SETBIT(sc, BGE_RX_MODE, 4315 BGE_RXMODE_RX_PROMISC); 4316 } else if (ifp->if_flags & IFF_RUNNING && 4317 !(ifp->if_flags & IFF_PROMISC) && 4318 sc->bge_if_flags & IFF_PROMISC) { 4319 BGE_CLRBIT(sc, BGE_RX_MODE, 4320 BGE_RXMODE_RX_PROMISC); 4321 } else if (!(sc->bge_if_flags & IFF_UP)) 4322 bge_init(ifp); 4323 } else { 4324 if (ifp->if_flags & IFF_RUNNING) 4325 bge_stop(ifp, 1); 4326 } 4327 sc->bge_if_flags = ifp->if_flags; 4328 error = 0; 4329 break; 4330 case SIOCSIFMEDIA: 4331 /* XXX Flow control is not supported for 1000BASE-SX */ 4332 if (sc->bge_tbi) { 4333 ifr->ifr_media &= ~IFM_ETH_FMASK; 4334 sc->bge_flowflags = 0; 4335 } 4336 4337 /* Flow control requires full-duplex mode. */ 4338 if (IFM_SUBTYPE(ifr->ifr_media) == IFM_AUTO || 4339 (ifr->ifr_media & IFM_FDX) == 0) { 4340 ifr->ifr_media &= ~IFM_ETH_FMASK; 4341 } 4342 if (IFM_SUBTYPE(ifr->ifr_media) != IFM_AUTO) { 4343 if ((ifr->ifr_media & IFM_ETH_FMASK) == IFM_FLOW) { 4344 /* We an do both TXPAUSE and RXPAUSE. */ 4345 ifr->ifr_media |= 4346 IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE; 4347 } 4348 sc->bge_flowflags = ifr->ifr_media & IFM_ETH_FMASK; 4349 } 4350 /* FALLTHROUGH */ 4351 case SIOCGIFMEDIA: 4352 if (sc->bge_tbi) { 4353 error = ifmedia_ioctl(ifp, ifr, &sc->bge_ifmedia, 4354 command); 4355 } else { 4356 mii = &sc->bge_mii; 4357 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, 4358 command); 4359 } 4360 break; 4361 default: 4362 if ((error = ether_ioctl(ifp, command, data)) != ENETRESET) 4363 break; 4364 4365 error = 0; 4366 4367 if (command != SIOCADDMULTI && command != SIOCDELMULTI) 4368 ; 4369 else if (ifp->if_flags & IFF_RUNNING) 4370 bge_setmulti(sc); 4371 break; 4372 } 4373 4374 splx(s); 4375 4376 return(error); 4377 } 4378 4379 static void 4380 bge_watchdog(struct ifnet *ifp) 4381 { 4382 struct bge_softc *sc; 4383 4384 sc = ifp->if_softc; 4385 4386 aprint_error_dev(sc->bge_dev, "watchdog timeout -- resetting\n"); 4387 4388 ifp->if_flags &= ~IFF_RUNNING; 4389 bge_init(ifp); 4390 4391 ifp->if_oerrors++; 4392 } 4393 4394 static void 4395 bge_stop_block(struct bge_softc *sc, bus_addr_t reg, uint32_t bit) 4396 { 4397 int i; 4398 4399 BGE_CLRBIT(sc, reg, bit); 4400 4401 for (i = 0; i < BGE_TIMEOUT; i++) { 4402 if ((CSR_READ_4(sc, reg) & bit) == 0) 4403 return; 4404 delay(100); 4405 if (sc->bge_pcie) 4406 DELAY(1000); 4407 } 4408 4409 aprint_error_dev(sc->bge_dev, 4410 "block failed to stop: reg 0x%lx, bit 0x%08x\n", (u_long)reg, bit); 4411 } 4412 4413 /* 4414 * Stop the adapter and free any mbufs allocated to the 4415 * RX and TX lists. 4416 */ 4417 static void 4418 bge_stop(struct ifnet *ifp, int disable) 4419 { 4420 struct bge_softc *sc = ifp->if_softc; 4421 4422 callout_stop(&sc->bge_timeout); 4423 4424 /* 4425 * Disable all of the receiver blocks 4426 */ 4427 bge_stop_block(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE); 4428 bge_stop_block(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 4429 bge_stop_block(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 4430 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 4431 bge_stop_block(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 4432 } 4433 bge_stop_block(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE); 4434 bge_stop_block(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 4435 bge_stop_block(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE); 4436 4437 /* 4438 * Disable all of the transmit blocks 4439 */ 4440 bge_stop_block(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 4441 bge_stop_block(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 4442 bge_stop_block(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 4443 bge_stop_block(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE); 4444 bge_stop_block(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE); 4445 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 4446 bge_stop_block(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 4447 } 4448 bge_stop_block(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 4449 4450 /* 4451 * Shut down all of the memory managers and related 4452 * state machines. 4453 */ 4454 bge_stop_block(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE); 4455 bge_stop_block(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE); 4456 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 4457 bge_stop_block(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 4458 } 4459 4460 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 4461 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 4462 4463 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 4464 bge_stop_block(sc, BGE_BMAN_MODE, BGE_BMANMODE_ENABLE); 4465 bge_stop_block(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 4466 } 4467 4468 /* Disable host interrupts. */ 4469 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); 4470 bge_writembx(sc, BGE_MBX_IRQ0_LO, 1); 4471 4472 /* 4473 * Tell firmware we're shutting down. 4474 */ 4475 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 4476 4477 /* Free the RX lists. */ 4478 bge_free_rx_ring_std(sc); 4479 4480 /* Free jumbo RX list. */ 4481 bge_free_rx_ring_jumbo(sc); 4482 4483 /* Free TX buffers. */ 4484 bge_free_tx_ring(sc); 4485 4486 /* 4487 * Isolate/power down the PHY. 4488 */ 4489 if (!sc->bge_tbi) 4490 mii_down(&sc->bge_mii); 4491 4492 sc->bge_link = 0; 4493 4494 sc->bge_tx_saved_considx = BGE_TXCONS_UNSET; 4495 4496 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 4497 } 4498 4499 static int 4500 sysctl_bge_verify(SYSCTLFN_ARGS) 4501 { 4502 int error, t; 4503 struct sysctlnode node; 4504 4505 node = *rnode; 4506 t = *(int*)rnode->sysctl_data; 4507 node.sysctl_data = &t; 4508 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 4509 if (error || newp == NULL) 4510 return (error); 4511 4512 #if 0 4513 DPRINTF2(("%s: t = %d, nodenum = %d, rnodenum = %d\n", __func__, t, 4514 node.sysctl_num, rnode->sysctl_num)); 4515 #endif 4516 4517 if (node.sysctl_num == bge_rxthresh_nodenum) { 4518 if (t < 0 || t >= NBGE_RX_THRESH) 4519 return (EINVAL); 4520 bge_update_all_threshes(t); 4521 } else 4522 return (EINVAL); 4523 4524 *(int*)rnode->sysctl_data = t; 4525 4526 return (0); 4527 } 4528 4529 /* 4530 * Set up sysctl(3) MIB, hw.bge.*. 4531 * 4532 * TBD condition SYSCTL_PERMANENT on being an LKM or not 4533 */ 4534 SYSCTL_SETUP(sysctl_bge, "sysctl bge subtree setup") 4535 { 4536 int rc, bge_root_num; 4537 const struct sysctlnode *node; 4538 4539 if ((rc = sysctl_createv(clog, 0, NULL, NULL, 4540 CTLFLAG_PERMANENT, CTLTYPE_NODE, "hw", NULL, 4541 NULL, 0, NULL, 0, CTL_HW, CTL_EOL)) != 0) { 4542 goto err; 4543 } 4544 4545 if ((rc = sysctl_createv(clog, 0, NULL, &node, 4546 CTLFLAG_PERMANENT, CTLTYPE_NODE, "bge", 4547 SYSCTL_DESCR("BGE interface controls"), 4548 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL)) != 0) { 4549 goto err; 4550 } 4551 4552 bge_root_num = node->sysctl_num; 4553 4554 /* BGE Rx interrupt mitigation level */ 4555 if ((rc = sysctl_createv(clog, 0, NULL, &node, 4556 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, 4557 CTLTYPE_INT, "rx_lvl", 4558 SYSCTL_DESCR("BGE receive interrupt mitigation level"), 4559 sysctl_bge_verify, 0, 4560 &bge_rx_thresh_lvl, 4561 0, CTL_HW, bge_root_num, CTL_CREATE, 4562 CTL_EOL)) != 0) { 4563 goto err; 4564 } 4565 4566 bge_rxthresh_nodenum = node->sysctl_num; 4567 4568 return; 4569 4570 err: 4571 aprint_error("%s: sysctl_createv failed (rc = %d)\n", __func__, rc); 4572 } 4573 4574 static int 4575 bge_get_eaddr_mem(struct bge_softc *sc, u_int8_t ether_addr[]) 4576 { 4577 u_int32_t mac_addr; 4578 4579 mac_addr = bge_readmem_ind(sc, 0x0c14); 4580 if ((mac_addr >> 16) == 0x484b) { 4581 ether_addr[0] = (uint8_t)(mac_addr >> 8); 4582 ether_addr[1] = (uint8_t)mac_addr; 4583 mac_addr = bge_readmem_ind(sc, 0x0c18); 4584 ether_addr[2] = (uint8_t)(mac_addr >> 24); 4585 ether_addr[3] = (uint8_t)(mac_addr >> 16); 4586 ether_addr[4] = (uint8_t)(mac_addr >> 8); 4587 ether_addr[5] = (uint8_t)mac_addr; 4588 return (0); 4589 } 4590 return (1); 4591 } 4592 4593 static int 4594 bge_get_eaddr_nvram(struct bge_softc *sc, u_int8_t ether_addr[]) 4595 { 4596 int mac_offset = BGE_EE_MAC_OFFSET; 4597 4598 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 4599 mac_offset = BGE_EE_MAC_OFFSET_5906; 4600 } 4601 4602 return (bge_read_nvram(sc, ether_addr, mac_offset + 2, 4603 ETHER_ADDR_LEN)); 4604 } 4605 4606 static int 4607 bge_get_eaddr_eeprom(struct bge_softc *sc, u_int8_t ether_addr[]) 4608 { 4609 4610 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 4611 return (1); 4612 } 4613 4614 return (bge_read_eeprom(sc, ether_addr, BGE_EE_MAC_OFFSET + 2, 4615 ETHER_ADDR_LEN)); 4616 } 4617 4618 static int 4619 bge_get_eaddr(struct bge_softc *sc, u_int8_t eaddr[]) 4620 { 4621 static const bge_eaddr_fcn_t bge_eaddr_funcs[] = { 4622 /* NOTE: Order is critical */ 4623 bge_get_eaddr_mem, 4624 bge_get_eaddr_nvram, 4625 bge_get_eaddr_eeprom, 4626 NULL 4627 }; 4628 const bge_eaddr_fcn_t *func; 4629 4630 for (func = bge_eaddr_funcs; *func != NULL; ++func) { 4631 if ((*func)(sc, eaddr) == 0) 4632 break; 4633 } 4634 return (*func == NULL ? ENXIO : 0); 4635 } 4636
Indexes created Thu Sep 25 06:09:39 GMT 2025