if_bge.c revision 1.16
1 /* $NetBSD: if_bge.c,v 1.16 2002/07/13 22:21:20 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 2001 Wind River Systems 5 * Copyright (c) 1997, 1998, 1999, 2001 6 * Bill Paul <wpaul (at) windriver.com>. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Bill Paul. 19 * 4. Neither the name of the author nor the names of any co-contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 33 * THE POSSIBILITY OF SUCH DAMAGE. 34 * 35 * $FreeBSD: if_bge.c,v 1.13 2002/04/04 06:01:31 wpaul Exp $ 36 */ 37 38 /* 39 * Broadcom BCM570x family gigabit ethernet driver for NetBSD. 40 * 41 * NetBSD version by: 42 * 43 * Frank van der Linden <fvdl (at) wasabisystems.com> 44 * Jason Thorpe <thorpej (at) wasabisystems.com> 45 * 46 * Originally written for FreeBSD by Bill Paul <wpaul (at) windriver.com> 47 * Senior Engineer, Wind River Systems 48 */ 49 50 /* 51 * The Broadcom BCM5700 is based on technology originally developed by 52 * Alteon Networks as part of the Tigon I and Tigon II gigabit ethernet 53 * MAC chips. The BCM5700, sometimes refered to as the Tigon III, has 54 * two on-board MIPS R4000 CPUs and can have as much as 16MB of external 55 * SSRAM. The BCM5700 supports TCP, UDP and IP checksum offload, jumbo 56 * frames, highly configurable RX filtering, and 16 RX and TX queues 57 * (which, along with RX filter rules, can be used for QOS applications). 58 * Other features, such as TCP segmentation, may be available as part 59 * of value-added firmware updates. Unlike the Tigon I and Tigon II, 60 * firmware images can be stored in hardware and need not be compiled 61 * into the driver. 62 * 63 * The BCM5700 supports the PCI v2.2 and PCI-X v1.0 standards, and will 64 * function in a 32-bit/64-bit 33/66Mhz bus, or a 64-bit/133Mhz bus. 65 * 66 * The BCM5701 is a single-chip solution incorporating both the BCM5700 67 * MAC and a BCM5401 10/100/1000 PHY. Unlike the BCM5700, the BCM5700 68 * does not support external SSRAM. 69 * 70 * Broadcom also produces a variation of the BCM5700 under the "Altima" 71 * brand name, which is functionally similar but lacks PCI-X support. 72 * 73 * Without external SSRAM, you can only have at most 4 TX rings, 74 * and the use of the mini RX ring is disabled. This seems to imply 75 * that these features are simply not available on the BCM5701. As a 76 * result, this driver does not implement any support for the mini RX 77 * ring. 78 */ 79 80 #include "bpfilter.h" 81 #include "vlan.h" 82 83 #include <sys/param.h> 84 #include <sys/systm.h> 85 #include <sys/callout.h> 86 #include <sys/sockio.h> 87 #include <sys/mbuf.h> 88 #include <sys/malloc.h> 89 #include <sys/kernel.h> 90 #include <sys/device.h> 91 #include <sys/socket.h> 92 93 #include <net/if.h> 94 #include <net/if_dl.h> 95 #include <net/if_media.h> 96 #include <net/if_ether.h> 97 98 #ifdef INET 99 #include <netinet/in.h> 100 #include <netinet/in_systm.h> 101 #include <netinet/in_var.h> 102 #include <netinet/ip.h> 103 #endif 104 105 #if NBPFILTER > 0 106 #include <net/bpf.h> 107 #endif 108 109 #include <dev/pci/pcireg.h> 110 #include <dev/pci/pcivar.h> 111 #include <dev/pci/pcidevs.h> 112 113 #include <dev/mii/mii.h> 114 #include <dev/mii/miivar.h> 115 #include <dev/mii/miidevs.h> 116 #include <dev/mii/brgphyreg.h> 117 118 #include <dev/pci/if_bgereg.h> 119 120 #include <uvm/uvm_extern.h> 121 122 /* #define BGE_CHECKSUM */ 123 124 int bge_probe(struct device *, struct cfdata *, void *); 125 void bge_attach(struct device *, struct device *, void *); 126 void bge_release_resources(struct bge_softc *); 127 void bge_txeof(struct bge_softc *); 128 void bge_rxeof(struct bge_softc *); 129 130 void bge_tick(void *); 131 void bge_stats_update(struct bge_softc *); 132 int bge_encap(struct bge_softc *, struct mbuf *, u_int32_t *); 133 134 int bge_intr(void *); 135 void bge_start(struct ifnet *); 136 int bge_ioctl(struct ifnet *, u_long, caddr_t); 137 int bge_init(struct ifnet *); 138 void bge_stop(struct bge_softc *); 139 void bge_watchdog(struct ifnet *); 140 void bge_shutdown(void *); 141 int bge_ifmedia_upd(struct ifnet *); 142 void bge_ifmedia_sts(struct ifnet *, struct ifmediareq *); 143 144 u_int8_t bge_eeprom_getbyte(struct bge_softc *, int, u_int8_t *); 145 int bge_read_eeprom(struct bge_softc *, caddr_t, int, int); 146 147 void bge_setmulti(struct bge_softc *); 148 149 void bge_handle_events(struct bge_softc *); 150 int bge_alloc_jumbo_mem(struct bge_softc *); 151 void bge_free_jumbo_mem(struct bge_softc *); 152 void *bge_jalloc(struct bge_softc *); 153 void bge_jfree(struct mbuf *, caddr_t, u_int, void *); 154 int bge_newbuf_std(struct bge_softc *, int, struct mbuf *, bus_dmamap_t); 155 int bge_newbuf_jumbo(struct bge_softc *, int, struct mbuf *); 156 int bge_init_rx_ring_std(struct bge_softc *); 157 void bge_free_rx_ring_std(struct bge_softc *); 158 int bge_init_rx_ring_jumbo(struct bge_softc *); 159 void bge_free_rx_ring_jumbo(struct bge_softc *); 160 void bge_free_tx_ring(struct bge_softc *); 161 int bge_init_tx_ring(struct bge_softc *); 162 163 int bge_chipinit(struct bge_softc *); 164 int bge_blockinit(struct bge_softc *); 165 166 #ifdef notdef 167 u_int8_t bge_vpd_readbyte(struct bge_softc *, int); 168 void bge_vpd_read_res(struct bge_softc *, struct vpd_res *, int); 169 void bge_vpd_read(struct bge_softc *); 170 #endif 171 172 u_int32_t bge_readmem_ind(struct bge_softc *, int); 173 void bge_writemem_ind(struct bge_softc *, int, int); 174 #ifdef notdef 175 u_int32_t bge_readreg_ind(struct bge_softc *, int); 176 #endif 177 void bge_writereg_ind(struct bge_softc *, int, int); 178 179 int bge_miibus_readreg(struct device *, int, int); 180 void bge_miibus_writereg(struct device *, int, int, int); 181 void bge_miibus_statchg(struct device *); 182 183 void bge_reset(struct bge_softc *); 184 185 void bge_dump_status(struct bge_softc *); 186 void bge_dump_rxbd(struct bge_rx_bd *); 187 188 #define BGE_DEBUG 189 #ifdef BGE_DEBUG 190 #define DPRINTF(x) if (bgedebug) printf x 191 #define DPRINTFN(n,x) if (bgedebug >= (n)) printf x 192 int bgedebug = 0; 193 #else 194 #define DPRINTF(x) 195 #define DPRINTFN(n,x) 196 #endif 197 198 struct cfattach bge_ca = { 199 sizeof(struct bge_softc), bge_probe, bge_attach 200 }; 201 202 u_int32_t 203 bge_readmem_ind(sc, off) 204 struct bge_softc *sc; 205 int off; 206 { 207 struct pci_attach_args *pa = &(sc->bge_pa); 208 pcireg_t val; 209 210 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_MEMWIN_BASEADDR, off); 211 val = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_MEMWIN_DATA); 212 return val; 213 } 214 215 void 216 bge_writemem_ind(sc, off, val) 217 struct bge_softc *sc; 218 int off, val; 219 { 220 struct pci_attach_args *pa = &(sc->bge_pa); 221 222 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_MEMWIN_BASEADDR, off); 223 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_MEMWIN_DATA, val); 224 } 225 226 #ifdef notdef 227 u_int32_t 228 bge_readreg_ind(sc, off) 229 struct bge_softc *sc; 230 int off; 231 { 232 struct pci_attach_args *pa = &(sc->bge_pa); 233 234 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_REG_BASEADDR, off); 235 return(pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_REG_DATA)); 236 } 237 #endif 238 239 void 240 bge_writereg_ind(sc, off, val) 241 struct bge_softc *sc; 242 int off, val; 243 { 244 struct pci_attach_args *pa = &(sc->bge_pa); 245 246 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_REG_BASEADDR, off); 247 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_REG_DATA, val); 248 } 249 250 #ifdef notdef 251 u_int8_t 252 bge_vpd_readbyte(sc, addr) 253 struct bge_softc *sc; 254 int addr; 255 { 256 int i; 257 u_int32_t val; 258 struct pci_attach_args *pa = &(sc->bge_pa); 259 260 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_VPD_ADDR, addr); 261 for (i = 0; i < BGE_TIMEOUT * 10; i++) { 262 DELAY(10); 263 if (pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_VPD_ADDR) & 264 BGE_VPD_FLAG) 265 break; 266 } 267 268 if (i == BGE_TIMEOUT) { 269 printf("%s: VPD read timed out\n", sc->bge_dev.dv_xname); 270 return(0); 271 } 272 273 val = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_VPD_DATA); 274 275 return((val >> ((addr % 4) * 8)) & 0xFF); 276 } 277 278 void 279 bge_vpd_read_res(sc, res, addr) 280 struct bge_softc *sc; 281 struct vpd_res *res; 282 int addr; 283 { 284 int i; 285 u_int8_t *ptr; 286 287 ptr = (u_int8_t *)res; 288 for (i = 0; i < sizeof(struct vpd_res); i++) 289 ptr[i] = bge_vpd_readbyte(sc, i + addr); 290 } 291 292 void 293 bge_vpd_read(sc) 294 struct bge_softc *sc; 295 { 296 int pos = 0, i; 297 struct vpd_res res; 298 299 if (sc->bge_vpd_prodname != NULL) 300 free(sc->bge_vpd_prodname, M_DEVBUF); 301 if (sc->bge_vpd_readonly != NULL) 302 free(sc->bge_vpd_readonly, M_DEVBUF); 303 sc->bge_vpd_prodname = NULL; 304 sc->bge_vpd_readonly = NULL; 305 306 bge_vpd_read_res(sc, &res, pos); 307 308 if (res.vr_id != VPD_RES_ID) { 309 printf("%s: bad VPD resource id: expected %x got %x\n", 310 sc->bge_dev.dv_xname, VPD_RES_ID, res.vr_id); 311 return; 312 } 313 314 pos += sizeof(res); 315 sc->bge_vpd_prodname = malloc(res.vr_len + 1, M_DEVBUF, M_NOWAIT); 316 if (sc->bge_vpd_prodname == NULL) 317 panic("bge_vpd_read"); 318 for (i = 0; i < res.vr_len; i++) 319 sc->bge_vpd_prodname[i] = bge_vpd_readbyte(sc, i + pos); 320 sc->bge_vpd_prodname[i] = '\0'; 321 pos += i; 322 323 bge_vpd_read_res(sc, &res, pos); 324 325 if (res.vr_id != VPD_RES_READ) { 326 printf("%s: bad VPD resource id: expected %x got %x\n", 327 sc->bge_dev.dv_xname, VPD_RES_READ, res.vr_id); 328 return; 329 } 330 331 pos += sizeof(res); 332 sc->bge_vpd_readonly = malloc(res.vr_len, M_DEVBUF, M_NOWAIT); 333 if (sc->bge_vpd_readonly == NULL) 334 panic("bge_vpd_read"); 335 for (i = 0; i < res.vr_len + 1; i++) 336 sc->bge_vpd_readonly[i] = bge_vpd_readbyte(sc, i + pos); 337 } 338 #endif 339 340 /* 341 * Read a byte of data stored in the EEPROM at address 'addr.' The 342 * BCM570x supports both the traditional bitbang interface and an 343 * auto access interface for reading the EEPROM. We use the auto 344 * access method. 345 */ 346 u_int8_t 347 bge_eeprom_getbyte(sc, addr, dest) 348 struct bge_softc *sc; 349 int addr; 350 u_int8_t *dest; 351 { 352 int i; 353 u_int32_t byte = 0; 354 355 /* 356 * Enable use of auto EEPROM access so we can avoid 357 * having to use the bitbang method. 358 */ 359 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM); 360 361 /* Reset the EEPROM, load the clock period. */ 362 CSR_WRITE_4(sc, BGE_EE_ADDR, 363 BGE_EEADDR_RESET|BGE_EEHALFCLK(BGE_HALFCLK_384SCL)); 364 DELAY(20); 365 366 /* Issue the read EEPROM command. */ 367 CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr); 368 369 /* Wait for completion */ 370 for(i = 0; i < BGE_TIMEOUT * 10; i++) { 371 DELAY(10); 372 if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE) 373 break; 374 } 375 376 if (i == BGE_TIMEOUT) { 377 printf("%s: eeprom read timed out\n", sc->bge_dev.dv_xname); 378 return(0); 379 } 380 381 /* Get result. */ 382 byte = CSR_READ_4(sc, BGE_EE_DATA); 383 384 *dest = (byte >> ((addr % 4) * 8)) & 0xFF; 385 386 return(0); 387 } 388 389 /* 390 * Read a sequence of bytes from the EEPROM. 391 */ 392 int 393 bge_read_eeprom(sc, dest, off, cnt) 394 struct bge_softc *sc; 395 caddr_t dest; 396 int off; 397 int cnt; 398 { 399 int err = 0, i; 400 u_int8_t byte = 0; 401 402 for (i = 0; i < cnt; i++) { 403 err = bge_eeprom_getbyte(sc, off + i, &byte); 404 if (err) 405 break; 406 *(dest + i) = byte; 407 } 408 409 return(err ? 1 : 0); 410 } 411 412 int 413 bge_miibus_readreg(dev, phy, reg) 414 struct device *dev; 415 int phy, reg; 416 { 417 struct bge_softc *sc = (struct bge_softc *)dev; 418 struct ifnet *ifp; 419 u_int32_t val; 420 int i; 421 422 ifp = &sc->ethercom.ec_if; 423 424 if (sc->bge_asicrev == BGE_ASICREV_BCM5701_B5 && phy != 1) 425 return(0); 426 427 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_READ|BGE_MICOMM_BUSY| 428 BGE_MIPHY(phy)|BGE_MIREG(reg)); 429 430 for (i = 0; i < BGE_TIMEOUT; i++) { 431 val = CSR_READ_4(sc, BGE_MI_COMM); 432 if (!(val & BGE_MICOMM_BUSY)) 433 break; 434 delay(10); 435 } 436 437 if (i == BGE_TIMEOUT) { 438 printf("%s: PHY read timed out\n", sc->bge_dev.dv_xname); 439 return(0); 440 } 441 442 val = CSR_READ_4(sc, BGE_MI_COMM); 443 444 if (val & BGE_MICOMM_READFAIL) 445 return(0); 446 447 return(val & 0xFFFF); 448 } 449 450 void 451 bge_miibus_writereg(dev, phy, reg, val) 452 struct device *dev; 453 int phy, reg, val; 454 { 455 struct bge_softc *sc = (struct bge_softc *)dev; 456 int i; 457 458 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_WRITE|BGE_MICOMM_BUSY| 459 BGE_MIPHY(phy)|BGE_MIREG(reg)|val); 460 461 for (i = 0; i < BGE_TIMEOUT; i++) { 462 if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY)) 463 break; 464 delay(10); 465 } 466 467 if (i == BGE_TIMEOUT) { 468 printf("%s: PHY read timed out\n", sc->bge_dev.dv_xname); 469 } 470 } 471 472 void 473 bge_miibus_statchg(dev) 474 struct device *dev; 475 { 476 struct bge_softc *sc = (struct bge_softc *)dev; 477 struct mii_data *mii = &sc->bge_mii; 478 479 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_PORTMODE); 480 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) { 481 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_GMII); 482 } else { 483 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_MII); 484 } 485 486 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 487 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX); 488 } else { 489 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX); 490 } 491 } 492 493 /* 494 * Handle events that have triggered interrupts. 495 */ 496 void 497 bge_handle_events(sc) 498 struct bge_softc *sc; 499 { 500 501 return; 502 } 503 504 /* 505 * Memory management for jumbo frames. 506 */ 507 508 int 509 bge_alloc_jumbo_mem(sc) 510 struct bge_softc *sc; 511 { 512 caddr_t ptr, kva; 513 bus_dma_segment_t seg; 514 int i, rseg, state, error; 515 struct bge_jpool_entry *entry; 516 517 state = error = 0; 518 519 /* Grab a big chunk o' storage. */ 520 if (bus_dmamem_alloc(sc->bge_dmatag, BGE_JMEM, PAGE_SIZE, 0, 521 &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 522 printf("%s: can't alloc rx buffers\n", sc->bge_dev.dv_xname); 523 return ENOBUFS; 524 } 525 526 state = 1; 527 if (bus_dmamem_map(sc->bge_dmatag, &seg, rseg, BGE_JMEM, &kva, 528 BUS_DMA_NOWAIT)) { 529 printf("%s: can't map dma buffers (%d bytes)\n", 530 sc->bge_dev.dv_xname, (int)BGE_JMEM); 531 error = ENOBUFS; 532 goto out; 533 } 534 535 state = 2; 536 if (bus_dmamap_create(sc->bge_dmatag, BGE_JMEM, 1, BGE_JMEM, 0, 537 BUS_DMA_NOWAIT, &sc->bge_cdata.bge_rx_jumbo_map)) { 538 printf("%s: can't create dma map\n", sc->bge_dev.dv_xname); 539 error = ENOBUFS; 540 goto out; 541 } 542 543 state = 3; 544 if (bus_dmamap_load(sc->bge_dmatag, sc->bge_cdata.bge_rx_jumbo_map, 545 kva, BGE_JMEM, NULL, BUS_DMA_NOWAIT)) { 546 printf("%s: can't load dma map\n", sc->bge_dev.dv_xname); 547 error = ENOBUFS; 548 goto out; 549 } 550 551 state = 4; 552 sc->bge_cdata.bge_jumbo_buf = (caddr_t)kva; 553 DPRINTFN(1,("bge_jumbo_buf = 0x%p\n", sc->bge_cdata.bge_jumbo_buf)); 554 555 SLIST_INIT(&sc->bge_jfree_listhead); 556 SLIST_INIT(&sc->bge_jinuse_listhead); 557 558 /* 559 * Now divide it up into 9K pieces and save the addresses 560 * in an array. 561 */ 562 ptr = sc->bge_cdata.bge_jumbo_buf; 563 for (i = 0; i < BGE_JSLOTS; i++) { 564 sc->bge_cdata.bge_jslots[i] = ptr; 565 ptr += BGE_JLEN; 566 entry = malloc(sizeof(struct bge_jpool_entry), 567 M_DEVBUF, M_NOWAIT); 568 if (entry == NULL) { 569 printf("%s: no memory for jumbo buffer queue!\n", 570 sc->bge_dev.dv_xname); 571 error = ENOBUFS; 572 goto out; 573 } 574 entry->slot = i; 575 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, 576 entry, jpool_entries); 577 } 578 out: 579 if (error != 0) { 580 switch (state) { 581 case 4: 582 bus_dmamap_unload(sc->bge_dmatag, 583 sc->bge_cdata.bge_rx_jumbo_map); 584 case 3: 585 bus_dmamap_destroy(sc->bge_dmatag, 586 sc->bge_cdata.bge_rx_jumbo_map); 587 case 2: 588 bus_dmamem_unmap(sc->bge_dmatag, kva, BGE_JMEM); 589 case 1: 590 bus_dmamem_free(sc->bge_dmatag, &seg, rseg); 591 break; 592 default: 593 break; 594 } 595 } 596 597 return error; 598 } 599 600 /* 601 * Allocate a jumbo buffer. 602 */ 603 void * 604 bge_jalloc(sc) 605 struct bge_softc *sc; 606 { 607 struct bge_jpool_entry *entry; 608 609 entry = SLIST_FIRST(&sc->bge_jfree_listhead); 610 611 if (entry == NULL) { 612 printf("%s: no free jumbo buffers\n", sc->bge_dev.dv_xname); 613 return(NULL); 614 } 615 616 SLIST_REMOVE_HEAD(&sc->bge_jfree_listhead, jpool_entries); 617 SLIST_INSERT_HEAD(&sc->bge_jinuse_listhead, entry, jpool_entries); 618 return(sc->bge_cdata.bge_jslots[entry->slot]); 619 } 620 621 /* 622 * Release a jumbo buffer. 623 */ 624 void 625 bge_jfree(m, buf, size, arg) 626 struct mbuf *m; 627 caddr_t buf; 628 u_int size; 629 void *arg; 630 { 631 struct bge_jpool_entry *entry; 632 struct bge_softc *sc; 633 int i, s; 634 635 /* Extract the softc struct pointer. */ 636 sc = (struct bge_softc *)arg; 637 638 if (sc == NULL) 639 panic("bge_jfree: can't find softc pointer!"); 640 641 /* calculate the slot this buffer belongs to */ 642 643 i = ((caddr_t)buf 644 - (caddr_t)sc->bge_cdata.bge_jumbo_buf) / BGE_JLEN; 645 646 if ((i < 0) || (i >= BGE_JSLOTS)) 647 panic("bge_jfree: asked to free buffer that we don't manage!"); 648 649 s = splvm(); 650 entry = SLIST_FIRST(&sc->bge_jinuse_listhead); 651 if (entry == NULL) 652 panic("bge_jfree: buffer not in use!"); 653 entry->slot = i; 654 SLIST_REMOVE_HEAD(&sc->bge_jinuse_listhead, jpool_entries); 655 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, entry, jpool_entries); 656 657 if (__predict_true(m != NULL)) 658 pool_cache_put(&mbpool_cache, m); 659 splx(s); 660 } 661 662 663 /* 664 * Intialize a standard receive ring descriptor. 665 */ 666 int 667 bge_newbuf_std(sc, i, m, dmamap) 668 struct bge_softc *sc; 669 int i; 670 struct mbuf *m; 671 bus_dmamap_t dmamap; 672 { 673 struct mbuf *m_new = NULL; 674 struct bge_rx_bd *r; 675 int error; 676 677 if (dmamap == NULL) { 678 error = bus_dmamap_create(sc->bge_dmatag, MCLBYTES, 1, 679 MCLBYTES, 0, BUS_DMA_NOWAIT, &dmamap); 680 if (error != 0) 681 return error; 682 } 683 684 sc->bge_cdata.bge_rx_std_map[i] = dmamap; 685 686 if (m == NULL) { 687 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 688 if (m_new == NULL) { 689 return(ENOBUFS); 690 } 691 692 MCLGET(m_new, M_DONTWAIT); 693 if (!(m_new->m_flags & M_EXT)) { 694 m_freem(m_new); 695 return(ENOBUFS); 696 } 697 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 698 m_adj(m_new, ETHER_ALIGN); 699 700 if (bus_dmamap_load_mbuf(sc->bge_dmatag, dmamap, m_new, 701 BUS_DMA_READ|BUS_DMA_NOWAIT)) 702 return(ENOBUFS); 703 } else { 704 m_new = m; 705 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 706 m_new->m_data = m_new->m_ext.ext_buf; 707 m_adj(m_new, ETHER_ALIGN); 708 } 709 710 sc->bge_cdata.bge_rx_std_chain[i] = m_new; 711 r = &sc->bge_rdata->bge_rx_std_ring[i]; 712 bge_set_hostaddr(&r->bge_addr, 713 dmamap->dm_segs[0].ds_addr); 714 r->bge_flags = BGE_RXBDFLAG_END; 715 r->bge_len = m_new->m_len; 716 r->bge_idx = i; 717 718 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 719 offsetof(struct bge_ring_data, bge_rx_std_ring) + 720 i * sizeof (struct bge_rx_bd), 721 sizeof (struct bge_rx_bd), 722 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 723 724 return(0); 725 } 726 727 /* 728 * Initialize a jumbo receive ring descriptor. This allocates 729 * a jumbo buffer from the pool managed internally by the driver. 730 */ 731 int 732 bge_newbuf_jumbo(sc, i, m) 733 struct bge_softc *sc; 734 int i; 735 struct mbuf *m; 736 { 737 struct mbuf *m_new = NULL; 738 struct bge_rx_bd *r; 739 740 if (m == NULL) { 741 caddr_t *buf = NULL; 742 743 /* Allocate the mbuf. */ 744 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 745 if (m_new == NULL) { 746 return(ENOBUFS); 747 } 748 749 /* Allocate the jumbo buffer */ 750 buf = bge_jalloc(sc); 751 if (buf == NULL) { 752 m_freem(m_new); 753 printf("%s: jumbo allocation failed " 754 "-- packet dropped!\n", sc->bge_dev.dv_xname); 755 return(ENOBUFS); 756 } 757 758 /* Attach the buffer to the mbuf. */ 759 m_new->m_len = m_new->m_pkthdr.len = BGE_JUMBO_FRAMELEN; 760 MEXTADD(m_new, buf, BGE_JUMBO_FRAMELEN, M_DEVBUF, 761 bge_jfree, sc); 762 } else { 763 m_new = m; 764 m_new->m_data = m_new->m_ext.ext_buf; 765 m_new->m_ext.ext_size = BGE_JUMBO_FRAMELEN; 766 } 767 768 m_adj(m_new, ETHER_ALIGN); 769 /* Set up the descriptor. */ 770 r = &sc->bge_rdata->bge_rx_jumbo_ring[i]; 771 sc->bge_cdata.bge_rx_jumbo_chain[i] = m_new; 772 bge_set_hostaddr(&r->bge_addr, BGE_JUMBO_DMA_ADDR(sc, m_new)); 773 r->bge_flags = BGE_RXBDFLAG_END|BGE_RXBDFLAG_JUMBO_RING; 774 r->bge_len = m_new->m_len; 775 r->bge_idx = i; 776 777 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 778 offsetof(struct bge_ring_data, bge_rx_jumbo_ring) + 779 i * sizeof (struct bge_rx_bd), 780 sizeof (struct bge_rx_bd), 781 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 782 783 return(0); 784 } 785 786 /* 787 * The standard receive ring has 512 entries in it. At 2K per mbuf cluster, 788 * that's 1MB or memory, which is a lot. For now, we fill only the first 789 * 256 ring entries and hope that our CPU is fast enough to keep up with 790 * the NIC. 791 */ 792 int 793 bge_init_rx_ring_std(sc) 794 struct bge_softc *sc; 795 { 796 int i; 797 798 if (sc->bge_flags & BGE_RXRING_VALID) 799 return 0; 800 801 for (i = 0; i < BGE_SSLOTS; i++) { 802 if (bge_newbuf_std(sc, i, NULL, 0) == ENOBUFS) 803 return(ENOBUFS); 804 } 805 806 sc->bge_std = i - 1; 807 CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std); 808 809 sc->bge_flags |= BGE_RXRING_VALID; 810 811 return(0); 812 } 813 814 void 815 bge_free_rx_ring_std(sc) 816 struct bge_softc *sc; 817 { 818 int i; 819 820 if (!(sc->bge_flags & BGE_RXRING_VALID)) 821 return; 822 823 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { 824 if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) { 825 m_freem(sc->bge_cdata.bge_rx_std_chain[i]); 826 sc->bge_cdata.bge_rx_std_chain[i] = NULL; 827 bus_dmamap_destroy(sc->bge_dmatag, 828 sc->bge_cdata.bge_rx_std_map[i]); 829 } 830 memset((char *)&sc->bge_rdata->bge_rx_std_ring[i], 0, 831 sizeof(struct bge_rx_bd)); 832 } 833 834 sc->bge_flags &= ~BGE_RXRING_VALID; 835 } 836 837 int 838 bge_init_rx_ring_jumbo(sc) 839 struct bge_softc *sc; 840 { 841 int i; 842 struct bge_rcb *rcb; 843 struct bge_rcb_opaque *rcbo; 844 845 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 846 if (bge_newbuf_jumbo(sc, i, NULL) == ENOBUFS) 847 return(ENOBUFS); 848 }; 849 850 sc->bge_jumbo = i - 1; 851 852 rcb = &sc->bge_rdata->bge_info.bge_jumbo_rx_rcb; 853 rcbo = (struct bge_rcb_opaque *)rcb; 854 rcb->bge_flags = 0; 855 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcbo->bge_reg2); 856 857 CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo); 858 859 return(0); 860 } 861 862 void 863 bge_free_rx_ring_jumbo(sc) 864 struct bge_softc *sc; 865 { 866 int i; 867 868 if (!(sc->bge_flags & BGE_JUMBO_RXRING_VALID)) 869 return; 870 871 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 872 if (sc->bge_cdata.bge_rx_jumbo_chain[i] != NULL) { 873 m_freem(sc->bge_cdata.bge_rx_jumbo_chain[i]); 874 sc->bge_cdata.bge_rx_jumbo_chain[i] = NULL; 875 } 876 memset((char *)&sc->bge_rdata->bge_rx_jumbo_ring[i], 0, 877 sizeof(struct bge_rx_bd)); 878 } 879 880 sc->bge_flags &= ~BGE_JUMBO_RXRING_VALID; 881 } 882 883 void 884 bge_free_tx_ring(sc) 885 struct bge_softc *sc; 886 { 887 int i, freed; 888 struct txdmamap_pool_entry *dma; 889 890 if (!(sc->bge_flags & BGE_TXRING_VALID)) 891 return; 892 893 freed = 0; 894 895 for (i = 0; i < BGE_TX_RING_CNT; i++) { 896 if (sc->bge_cdata.bge_tx_chain[i] != NULL) { 897 freed++; 898 m_freem(sc->bge_cdata.bge_tx_chain[i]); 899 sc->bge_cdata.bge_tx_chain[i] = NULL; 900 SLIST_INSERT_HEAD(&sc->txdma_list, sc->txdma[i], 901 link); 902 sc->txdma[i] = 0; 903 } 904 memset((char *)&sc->bge_rdata->bge_tx_ring[i], 0, 905 sizeof(struct bge_tx_bd)); 906 } 907 908 while ((dma = SLIST_FIRST(&sc->txdma_list))) { 909 SLIST_REMOVE_HEAD(&sc->txdma_list, link); 910 bus_dmamap_destroy(sc->bge_dmatag, dma->dmamap); 911 free(dma, M_DEVBUF); 912 } 913 914 sc->bge_flags &= ~BGE_TXRING_VALID; 915 } 916 917 int 918 bge_init_tx_ring(sc) 919 struct bge_softc *sc; 920 { 921 int i; 922 bus_dmamap_t dmamap; 923 struct txdmamap_pool_entry *dma; 924 925 if (sc->bge_flags & BGE_TXRING_VALID) 926 return 0; 927 928 sc->bge_txcnt = 0; 929 sc->bge_tx_saved_considx = 0; 930 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, 0); 931 CSR_WRITE_4(sc, BGE_MBX_TX_NIC_PROD0_LO, 0); 932 933 SLIST_INIT(&sc->txdma_list); 934 for (i = 0; i < BGE_RSLOTS; i++) { 935 if (bus_dmamap_create(sc->bge_dmatag, ETHER_MAX_LEN_JUMBO, 936 BGE_NTXSEG, ETHER_MAX_LEN_JUMBO, 0, BUS_DMA_NOWAIT, 937 &dmamap)) 938 return(ENOBUFS); 939 if (dmamap == NULL) 940 panic("dmamap NULL in bge_init_tx_ring"); 941 dma = malloc(sizeof(*dma), M_DEVBUF, M_NOWAIT); 942 if (dma == NULL) { 943 printf("%s: can't alloc txdmamap_pool_entry\n", 944 sc->bge_dev.dv_xname); 945 bus_dmamap_destroy(sc->bge_dmatag, dmamap); 946 return (ENOMEM); 947 } 948 dma->dmamap = dmamap; 949 SLIST_INSERT_HEAD(&sc->txdma_list, dma, link); 950 } 951 952 sc->bge_flags |= BGE_TXRING_VALID; 953 954 return(0); 955 } 956 957 void 958 bge_setmulti(sc) 959 struct bge_softc *sc; 960 { 961 struct ethercom *ac = &sc->ethercom; 962 struct ifnet *ifp = &ac->ec_if; 963 struct ether_multi *enm; 964 struct ether_multistep step; 965 u_int32_t hashes[4] = { 0, 0, 0, 0 }; 966 u_int32_t h; 967 int i; 968 969 if (ifp->if_flags & IFF_PROMISC) 970 goto allmulti; 971 972 /* Now program new ones. */ 973 ETHER_FIRST_MULTI(step, ac, enm); 974 while (enm != NULL) { 975 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 976 /* 977 * We must listen to a range of multicast addresses. 978 * For now, just accept all multicasts, rather than 979 * trying to set only those filter bits needed to match 980 * the range. (At this time, the only use of address 981 * ranges is for IP multicast routing, for which the 982 * range is big enough to require all bits set.) 983 */ 984 goto allmulti; 985 } 986 987 h = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN); 988 989 /* Just want the 7 least-significant bits. */ 990 h &= 0x7f; 991 992 hashes[(h & 0x60) >> 5] |= 1 << (h & 0x1F); 993 ETHER_NEXT_MULTI(step, enm); 994 } 995 996 ifp->if_flags &= ~IFF_ALLMULTI; 997 goto setit; 998 999 allmulti: 1000 ifp->if_flags |= IFF_ALLMULTI; 1001 hashes[0] = hashes[1] = hashes[2] = hashes[3] = 0xffffffff; 1002 1003 setit: 1004 for (i = 0; i < 4; i++) 1005 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]); 1006 } 1007 1008 int bge_swapbits[] = { 1009 0, 1010 BGE_MODECTL_BYTESWAP_DATA, 1011 BGE_MODECTL_WORDSWAP_DATA, 1012 BGE_MODECTL_BYTESWAP_NONFRAME, 1013 BGE_MODECTL_WORDSWAP_NONFRAME, 1014 1015 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA, 1016 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_BYTESWAP_NONFRAME, 1017 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_NONFRAME, 1018 1019 BGE_MODECTL_WORDSWAP_DATA|BGE_MODECTL_BYTESWAP_NONFRAME, 1020 BGE_MODECTL_WORDSWAP_DATA|BGE_MODECTL_WORDSWAP_NONFRAME, 1021 1022 BGE_MODECTL_BYTESWAP_NONFRAME|BGE_MODECTL_WORDSWAP_NONFRAME, 1023 1024 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA| 1025 BGE_MODECTL_BYTESWAP_NONFRAME, 1026 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA| 1027 BGE_MODECTL_WORDSWAP_NONFRAME, 1028 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_BYTESWAP_NONFRAME| 1029 BGE_MODECTL_WORDSWAP_NONFRAME, 1030 BGE_MODECTL_WORDSWAP_DATA|BGE_MODECTL_BYTESWAP_NONFRAME| 1031 BGE_MODECTL_WORDSWAP_NONFRAME, 1032 1033 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA| 1034 BGE_MODECTL_BYTESWAP_NONFRAME|BGE_MODECTL_WORDSWAP_NONFRAME, 1035 }; 1036 1037 int bge_swapindex = 0; 1038 1039 /* 1040 * Do endian, PCI and DMA initialization. Also check the on-board ROM 1041 * self-test results. 1042 */ 1043 int 1044 bge_chipinit(sc) 1045 struct bge_softc *sc; 1046 { 1047 u_int32_t cachesize; 1048 int i; 1049 struct pci_attach_args *pa = &(sc->bge_pa); 1050 1051 1052 /* Set endianness before we access any non-PCI registers. */ 1053 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_MISC_CTL, 1054 BGE_INIT); 1055 1056 /* 1057 * Check the 'ROM failed' bit on the RX CPU to see if 1058 * self-tests passed. 1059 */ 1060 if (CSR_READ_4(sc, BGE_RXCPU_MODE) & BGE_RXCPUMODE_ROMFAIL) { 1061 printf("%s: RX CPU self-diagnostics failed!\n", 1062 sc->bge_dev.dv_xname); 1063 return(ENODEV); 1064 } 1065 1066 /* Clear the MAC control register */ 1067 CSR_WRITE_4(sc, BGE_MAC_MODE, 0); 1068 1069 /* 1070 * Clear the MAC statistics block in the NIC's 1071 * internal memory. 1072 */ 1073 for (i = BGE_STATS_BLOCK; 1074 i < BGE_STATS_BLOCK_END + 1; i += sizeof(u_int32_t)) 1075 BGE_MEMWIN_WRITE(pa->pa_pc, pa->pa_tag, i, 0); 1076 1077 for (i = BGE_STATUS_BLOCK; 1078 i < BGE_STATUS_BLOCK_END + 1; i += sizeof(u_int32_t)) 1079 BGE_MEMWIN_WRITE(pa->pa_pc, pa->pa_tag, i, 0); 1080 1081 /* Set up the PCI DMA control register. */ 1082 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_DMA_RW_CTL, 1083 BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD|0x0F); 1084 1085 /* 1086 * Set up general mode register. 1087 */ 1088 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS| 1089 BGE_MODECTL_MAC_ATTN_INTR|BGE_MODECTL_HOST_SEND_BDS| 1090 BGE_MODECTL_NO_RX_CRC|BGE_MODECTL_TX_NO_PHDR_CSUM| 1091 BGE_MODECTL_RX_NO_PHDR_CSUM); 1092 1093 /* Get cache line size. */ 1094 cachesize = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_CACHESZ); 1095 1096 /* 1097 * Avoid violating PCI spec on certain chip revs. 1098 */ 1099 if (pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_CMD) & 1100 PCIM_CMD_MWIEN) { 1101 switch(cachesize) { 1102 case 1: 1103 PCI_SETBIT(pa->pa_pc, pa->pa_tag, BGE_PCI_DMA_RW_CTL, 1104 BGE_PCI_WRITE_BNDRY_16BYTES); 1105 break; 1106 case 2: 1107 PCI_SETBIT(pa->pa_pc, pa->pa_tag, BGE_PCI_DMA_RW_CTL, 1108 BGE_PCI_WRITE_BNDRY_32BYTES); 1109 break; 1110 case 4: 1111 PCI_SETBIT(pa->pa_pc, pa->pa_tag, BGE_PCI_DMA_RW_CTL, 1112 BGE_PCI_WRITE_BNDRY_64BYTES); 1113 break; 1114 case 8: 1115 PCI_SETBIT(pa->pa_pc, pa->pa_tag, BGE_PCI_DMA_RW_CTL, 1116 BGE_PCI_WRITE_BNDRY_128BYTES); 1117 break; 1118 case 16: 1119 PCI_SETBIT(pa->pa_pc, pa->pa_tag, BGE_PCI_DMA_RW_CTL, 1120 BGE_PCI_WRITE_BNDRY_256BYTES); 1121 break; 1122 case 32: 1123 PCI_SETBIT(pa->pa_pc, pa->pa_tag, BGE_PCI_DMA_RW_CTL, 1124 BGE_PCI_WRITE_BNDRY_512BYTES); 1125 break; 1126 case 64: 1127 PCI_SETBIT(pa->pa_pc, pa->pa_tag, BGE_PCI_DMA_RW_CTL, 1128 BGE_PCI_WRITE_BNDRY_1024BYTES); 1129 break; 1130 default: 1131 /* Disable PCI memory write and invalidate. */ 1132 #if 0 1133 if (bootverbose) 1134 printf("%s: cache line size %d not " 1135 "supported; disabling PCI MWI\n", 1136 sc->bge_dev.dv_xname, cachesize); 1137 #endif 1138 PCI_CLRBIT(pa->pa_pc, pa->pa_tag, BGE_PCI_CMD, 1139 PCIM_CMD_MWIEN); 1140 break; 1141 } 1142 } 1143 1144 #ifdef __brokenalpha__ 1145 /* 1146 * Must insure that we do not cross an 8K (bytes) boundary 1147 * for DMA reads. Our highest limit is 1K bytes. This is a 1148 * restriction on some ALPHA platforms with early revision 1149 * 21174 PCI chipsets, such as the AlphaPC 164lx 1150 */ 1151 PCI_SETBIT(sc, BGE_PCI_DMA_RW_CTL, BGE_PCI_READ_BNDRY_1024, 4); 1152 #endif 1153 1154 /* Set the timer prescaler (always 66Mhz) */ 1155 CSR_WRITE_4(sc, BGE_MISC_CFG, 65 << 1/*BGE_32BITTIME_66MHZ*/); 1156 1157 return(0); 1158 } 1159 1160 int 1161 bge_blockinit(sc) 1162 struct bge_softc *sc; 1163 { 1164 struct bge_rcb *rcb; 1165 struct bge_rcb_opaque *rcbo; 1166 bus_size_t rcb_addr; 1167 int i; 1168 struct ifnet *ifp = &sc->ethercom.ec_if; 1169 bge_hostaddr taddr; 1170 1171 /* 1172 * Initialize the memory window pointer register so that 1173 * we can access the first 32K of internal NIC RAM. This will 1174 * allow us to set up the TX send ring RCBs and the RX return 1175 * ring RCBs, plus other things which live in NIC memory. 1176 */ 1177 1178 pci_conf_write(sc->bge_pa.pa_pc, sc->bge_pa.pa_tag, 1179 BGE_PCI_MEMWIN_BASEADDR, 0); 1180 1181 /* Configure mbuf memory pool */ 1182 if (sc->bge_extram) { 1183 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, BGE_EXT_SSRAM); 1184 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000); 1185 } else { 1186 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, BGE_BUFFPOOL_1); 1187 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000); 1188 } 1189 1190 /* Configure DMA resource pool */ 1191 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_BASEADDR, BGE_DMA_DESCRIPTORS); 1192 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LEN, 0x2000); 1193 1194 /* Configure mbuf pool watermarks */ 1195 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 24); 1196 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 24); 1197 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 48); 1198 1199 /* Configure DMA resource watermarks */ 1200 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5); 1201 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10); 1202 1203 /* Enable buffer manager */ 1204 CSR_WRITE_4(sc, BGE_BMAN_MODE, 1205 BGE_BMANMODE_ENABLE|BGE_BMANMODE_LOMBUF_ATTN); 1206 1207 /* Poll for buffer manager start indication */ 1208 for (i = 0; i < BGE_TIMEOUT; i++) { 1209 if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE) 1210 break; 1211 DELAY(10); 1212 } 1213 1214 if (i == BGE_TIMEOUT) { 1215 printf("%s: buffer manager failed to start\n", 1216 sc->bge_dev.dv_xname); 1217 return(ENXIO); 1218 } 1219 1220 /* Enable flow-through queues */ 1221 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 1222 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 1223 1224 /* Wait until queue initialization is complete */ 1225 for (i = 0; i < BGE_TIMEOUT; i++) { 1226 if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0) 1227 break; 1228 DELAY(10); 1229 } 1230 1231 if (i == BGE_TIMEOUT) { 1232 printf("%s: flow-through queue init failed\n", 1233 sc->bge_dev.dv_xname); 1234 return(ENXIO); 1235 } 1236 1237 /* Initialize the standard RX ring control block */ 1238 rcb = &sc->bge_rdata->bge_info.bge_std_rx_rcb; 1239 bge_set_hostaddr(&rcb->bge_hostaddr, 1240 BGE_RING_DMA_ADDR(sc, bge_rx_std_ring)); 1241 rcb->bge_max_len = BGE_MAX_FRAMELEN; 1242 if (sc->bge_extram) 1243 rcb->bge_nicaddr = BGE_EXT_STD_RX_RINGS; 1244 else 1245 rcb->bge_nicaddr = BGE_STD_RX_RINGS; 1246 rcb->bge_flags = 0; 1247 rcbo = (struct bge_rcb_opaque *)rcb; 1248 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcbo->bge_reg0); 1249 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcbo->bge_reg1); 1250 CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcbo->bge_reg2); 1251 CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcbo->bge_reg3); 1252 1253 /* 1254 * Initialize the jumbo RX ring control block 1255 * We set the 'ring disabled' bit in the flags 1256 * field until we're actually ready to start 1257 * using this ring (i.e. once we set the MTU 1258 * high enough to require it). 1259 */ 1260 rcb = &sc->bge_rdata->bge_info.bge_jumbo_rx_rcb; 1261 bge_set_hostaddr(&rcb->bge_hostaddr, 1262 BGE_RING_DMA_ADDR(sc, bge_rx_jumbo_ring)); 1263 rcb->bge_max_len = BGE_MAX_FRAMELEN; 1264 if (sc->bge_extram) 1265 rcb->bge_nicaddr = BGE_EXT_JUMBO_RX_RINGS; 1266 else 1267 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS; 1268 rcb->bge_flags = BGE_RCB_FLAG_RING_DISABLED; 1269 1270 rcbo = (struct bge_rcb_opaque *)rcb; 1271 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI, rcbo->bge_reg0); 1272 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO, rcbo->bge_reg1); 1273 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcbo->bge_reg2); 1274 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcbo->bge_reg3); 1275 1276 /* Set up dummy disabled mini ring RCB */ 1277 rcb = &sc->bge_rdata->bge_info.bge_mini_rx_rcb; 1278 rcb->bge_flags = BGE_RCB_FLAG_RING_DISABLED; 1279 rcbo = (struct bge_rcb_opaque *)rcb; 1280 CSR_WRITE_4(sc, BGE_RX_MINI_RCB_MAXLEN_FLAGS, rcbo->bge_reg2); 1281 1282 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 1283 offsetof(struct bge_ring_data, bge_info), sizeof (struct bge_gib), 1284 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1285 1286 /* 1287 * Set the BD ring replentish thresholds. The recommended 1288 * values are 1/8th the number of descriptors allocated to 1289 * each ring. 1290 */ 1291 CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, BGE_STD_RX_RING_CNT/8); 1292 CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH, BGE_JUMBO_RX_RING_CNT/8); 1293 1294 /* 1295 * Disable all unused send rings by setting the 'ring disabled' 1296 * bit in the flags field of all the TX send ring control blocks. 1297 * These are located in NIC memory. 1298 */ 1299 rcb_addr = BGE_MEMWIN_START + BGE_SEND_RING_RCB; 1300 for (i = 0; i < BGE_TX_RINGS_EXTSSRAM_MAX; i++) { 1301 RCB_WRITE_2(sc, rcb_addr, bge_flags, 1302 BGE_RCB_FLAG_RING_DISABLED); 1303 RCB_WRITE_2(sc, rcb_addr, bge_max_len, 0); 1304 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 0); 1305 rcb_addr += sizeof(struct bge_rcb); 1306 } 1307 1308 /* Configure TX RCB 0 (we use only the first ring) */ 1309 rcb_addr = BGE_MEMWIN_START + BGE_SEND_RING_RCB; 1310 bge_set_hostaddr(&taddr, BGE_RING_DMA_ADDR(sc, bge_tx_ring)); 1311 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi); 1312 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo); 1313 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 1314 BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT)); 1315 RCB_WRITE_2(sc, rcb_addr, bge_max_len, BGE_TX_RING_CNT); 1316 RCB_WRITE_2(sc, rcb_addr, bge_flags, 0); 1317 1318 /* Disable all unused RX return rings */ 1319 rcb_addr = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB; 1320 for (i = 0; i < BGE_RX_RINGS_MAX; i++) { 1321 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_hi, 0); 1322 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_lo, 0); 1323 RCB_WRITE_2(sc, rcb_addr, bge_flags, 1324 BGE_RCB_FLAG_RING_DISABLED); 1325 RCB_WRITE_2(sc, rcb_addr, bge_max_len, BGE_RETURN_RING_CNT); 1326 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 0); 1327 CSR_WRITE_4(sc, BGE_MBX_RX_CONS0_LO + 1328 (i * (sizeof(u_int64_t))), 0); 1329 rcb_addr += sizeof(struct bge_rcb); 1330 } 1331 1332 /* Initialize RX ring indexes */ 1333 CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, 0); 1334 CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0); 1335 CSR_WRITE_4(sc, BGE_MBX_RX_MINI_PROD_LO, 0); 1336 1337 /* 1338 * Set up RX return ring 0 1339 * Note that the NIC address for RX return rings is 0x00000000. 1340 * The return rings live entirely within the host, so the 1341 * nicaddr field in the RCB isn't used. 1342 */ 1343 rcb_addr = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB; 1344 bge_set_hostaddr(&taddr, BGE_RING_DMA_ADDR(sc, bge_rx_return_ring)); 1345 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi); 1346 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo); 1347 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 0x00000000); 1348 RCB_WRITE_2(sc, rcb_addr, bge_max_len, BGE_RETURN_RING_CNT); 1349 RCB_WRITE_2(sc, rcb_addr, bge_flags, 0); 1350 1351 /* Set random backoff seed for TX */ 1352 CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF, 1353 LLADDR(ifp->if_sadl)[0] + LLADDR(ifp->if_sadl)[1] + 1354 LLADDR(ifp->if_sadl)[2] + LLADDR(ifp->if_sadl)[3] + 1355 LLADDR(ifp->if_sadl)[4] + LLADDR(ifp->if_sadl)[5] + 1356 BGE_TX_BACKOFF_SEED_MASK); 1357 1358 /* Set inter-packet gap */ 1359 CSR_WRITE_4(sc, BGE_TX_LENGTHS, 0x2620); 1360 1361 /* 1362 * Specify which ring to use for packets that don't match 1363 * any RX rules. 1364 */ 1365 CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08); 1366 1367 /* 1368 * Configure number of RX lists. One interrupt distribution 1369 * list, sixteen active lists, one bad frames class. 1370 */ 1371 CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181); 1372 1373 /* Inialize RX list placement stats mask. */ 1374 CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF); 1375 CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1); 1376 1377 /* Disable host coalescing until we get it set up */ 1378 CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000); 1379 1380 /* Poll to make sure it's shut down. */ 1381 for (i = 0; i < BGE_TIMEOUT; i++) { 1382 if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE)) 1383 break; 1384 DELAY(10); 1385 } 1386 1387 if (i == BGE_TIMEOUT) { 1388 printf("%s: host coalescing engine failed to idle\n", 1389 sc->bge_dev.dv_xname); 1390 return(ENXIO); 1391 } 1392 1393 /* Set up host coalescing defaults */ 1394 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bge_rx_coal_ticks); 1395 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bge_tx_coal_ticks); 1396 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bge_rx_max_coal_bds); 1397 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bge_tx_max_coal_bds); 1398 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT, 0); 1399 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT, 0); 1400 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 0); 1401 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 0); 1402 CSR_WRITE_4(sc, BGE_HCC_STATS_TICKS, sc->bge_stat_ticks); 1403 1404 /* Set up address of statistics block */ 1405 bge_set_hostaddr(&taddr, BGE_RING_DMA_ADDR(sc, bge_info.bge_stats)); 1406 CSR_WRITE_4(sc, BGE_HCC_STATS_BASEADDR, BGE_STATS_BLOCK); 1407 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_HI, taddr.bge_addr_hi); 1408 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_LO, taddr.bge_addr_lo); 1409 1410 /* Set up address of status block */ 1411 bge_set_hostaddr(&taddr, BGE_RING_DMA_ADDR(sc, bge_status_block)); 1412 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_BASEADDR, BGE_STATUS_BLOCK); 1413 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI, taddr.bge_addr_hi); 1414 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO, taddr.bge_addr_lo); 1415 sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx = 0; 1416 sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx = 0; 1417 1418 /* Turn on host coalescing state machine */ 1419 CSR_WRITE_4(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE); 1420 1421 /* Turn on RX BD completion state machine and enable attentions */ 1422 CSR_WRITE_4(sc, BGE_RBDC_MODE, 1423 BGE_RBDCMODE_ENABLE|BGE_RBDCMODE_ATTN); 1424 1425 /* Turn on RX list placement state machine */ 1426 CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 1427 1428 /* Turn on RX list selector state machine. */ 1429 CSR_WRITE_4(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 1430 1431 /* Turn on DMA, clear stats */ 1432 CSR_WRITE_4(sc, BGE_MAC_MODE, BGE_MACMODE_TXDMA_ENB| 1433 BGE_MACMODE_RXDMA_ENB|BGE_MACMODE_RX_STATS_CLEAR| 1434 BGE_MACMODE_TX_STATS_CLEAR|BGE_MACMODE_RX_STATS_ENB| 1435 BGE_MACMODE_TX_STATS_ENB|BGE_MACMODE_FRMHDR_DMA_ENB| 1436 (sc->bge_tbi ? BGE_PORTMODE_TBI : BGE_PORTMODE_MII)); 1437 1438 /* Set misc. local control, enable interrupts on attentions */ 1439 CSR_WRITE_4(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_ONATTN); 1440 1441 #ifdef notdef 1442 /* Assert GPIO pins for PHY reset */ 1443 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUT0| 1444 BGE_MLC_MISCIO_OUT1|BGE_MLC_MISCIO_OUT2); 1445 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUTEN0| 1446 BGE_MLC_MISCIO_OUTEN1|BGE_MLC_MISCIO_OUTEN2); 1447 #endif 1448 1449 /* Turn on DMA completion state machine */ 1450 CSR_WRITE_4(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 1451 1452 /* Turn on write DMA state machine */ 1453 CSR_WRITE_4(sc, BGE_WDMA_MODE, 1454 BGE_WDMAMODE_ENABLE|BGE_WDMAMODE_ALL_ATTNS); 1455 1456 /* Turn on read DMA state machine */ 1457 CSR_WRITE_4(sc, BGE_RDMA_MODE, 1458 BGE_RDMAMODE_ENABLE|BGE_RDMAMODE_ALL_ATTNS); 1459 1460 /* Turn on RX data completion state machine */ 1461 CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 1462 1463 /* Turn on RX BD initiator state machine */ 1464 CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 1465 1466 /* Turn on RX data and RX BD initiator state machine */ 1467 CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE); 1468 1469 /* Turn on Mbuf cluster free state machine */ 1470 CSR_WRITE_4(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 1471 1472 /* Turn on send BD completion state machine */ 1473 CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 1474 1475 /* Turn on send data completion state machine */ 1476 CSR_WRITE_4(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE); 1477 1478 /* Turn on send data initiator state machine */ 1479 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 1480 1481 /* Turn on send BD initiator state machine */ 1482 CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 1483 1484 /* Turn on send BD selector state machine */ 1485 CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 1486 1487 CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF); 1488 CSR_WRITE_4(sc, BGE_SDI_STATS_CTL, 1489 BGE_SDISTATSCTL_ENABLE|BGE_SDISTATSCTL_FASTER); 1490 1491 /* init LED register */ 1492 CSR_WRITE_4(sc, BGE_MAC_LED_CTL, 0x00000000); 1493 1494 /* ack/clear link change events */ 1495 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED| 1496 BGE_MACSTAT_CFG_CHANGED); 1497 CSR_WRITE_4(sc, BGE_MI_STS, 0); 1498 1499 /* Enable PHY auto polling (for MII/GMII only) */ 1500 if (sc->bge_tbi) { 1501 CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK); 1502 } else { 1503 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL|10<<16); 1504 if (BGE_IS_5700_Ax_Bx(sc->bge_asicrev)) 1505 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, 1506 BGE_EVTENB_MI_INTERRUPT); 1507 } 1508 1509 /* Enable link state change attentions. */ 1510 BGE_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED); 1511 1512 return(0); 1513 } 1514 1515 static const struct bge_revision { 1516 uint32_t br_asicrev; 1517 uint32_t br_quirks; 1518 const char *br_name; 1519 } bge_revisions[] = { 1520 { BGE_ASICREV_BCM5700_A0, 1521 0, 1522 "BCM5700 A0" }, 1523 1524 { BGE_ASICREV_BCM5700_A1, 1525 0, 1526 "BCM5700 A1" }, 1527 1528 { BGE_ASICREV_BCM5700_B0, 1529 0, 1530 "BCM5700 B0" }, 1531 1532 { BGE_ASICREV_BCM5700_B1, 1533 0, 1534 "BCM5700 B1" }, 1535 1536 { BGE_ASICREV_BCM5700_B2, 1537 0, 1538 "BCM5700 B2" }, 1539 1540 { BGE_ASICREV_BCM5700_ALTIMA, 1541 0, 1542 "BCM5700 Altima" }, 1543 1544 { BGE_ASICREV_BCM5700_C0, 1545 0, 1546 "BCM5700 C0" }, 1547 1548 { BGE_ASICREV_BCM5701_A0, 1549 0, 1550 "BCM5701 A0" }, 1551 1552 { BGE_ASICREV_BCM5701_B0, 1553 0, 1554 "BCM5701 B0" }, 1555 1556 { BGE_ASICREV_BCM5701_B2, 1557 0, 1558 "BCM5701 B2" }, 1559 1560 { BGE_ASICREV_BCM5701_B5, 1561 0, 1562 "BCM5701 B5" }, 1563 1564 { BGE_ASICREV_BCM5703_A0, 1565 0, 1566 "BCM5703 A0" }, 1567 1568 { BGE_ASICREV_BCM5703_A1, 1569 0, 1570 "BCM5703 A1" }, 1571 1572 { BGE_ASICREV_BCM5703_A2, 1573 0, 1574 "BCM5703 A2" }, 1575 1576 { 0, 0, NULL } 1577 }; 1578 1579 static const struct bge_revision * 1580 bge_lookup_rev(uint32_t asicrev) 1581 { 1582 const struct bge_revision *br; 1583 1584 for (br = bge_revisions; br->br_name != NULL; br++) { 1585 if (br->br_asicrev == asicrev) 1586 return (br); 1587 } 1588 1589 return (NULL); 1590 } 1591 1592 static const struct bge_product { 1593 pci_vendor_id_t bp_vendor; 1594 pci_product_id_t bp_product; 1595 const char *bp_name; 1596 } bge_products[] = { 1597 /* 1598 * The BCM5700 documentation seems to indicate that the hardware 1599 * still has the Alteon vendor ID burned into it, though it 1600 * should always be overridden by the value in the EEPROM. We'll 1601 * check for it anyway. 1602 */ 1603 { PCI_VENDOR_ALTEON, 1604 PCI_PRODUCT_ALTEON_BCM5700, 1605 "Broadcom BCM5700 Gigabit Ethernet" }, 1606 { PCI_VENDOR_ALTEON, 1607 PCI_PRODUCT_ALTEON_BCM5701, 1608 "Broadcom BCM5701 Gigabit Ethernet" }, 1609 1610 { PCI_VENDOR_ALTIMA, 1611 PCI_PRODUCT_ALTIMA_AC1000, 1612 "Altima AC1000 Gigabit Ethernet" }, 1613 { PCI_VENDOR_ALTIMA, 1614 PCI_PRODUCT_ALTIMA_AC1001, 1615 "Altima AC1001 Gigabit Ethernet" }, 1616 { PCI_VENDOR_ALTIMA, 1617 PCI_PRODUCT_ALTIMA_AC9100, 1618 "Altima AC9100 Gigabit Ethernet" }, 1619 1620 { PCI_VENDOR_BROADCOM, 1621 PCI_PRODUCT_BROADCOM_BCM5700, 1622 "Broadcom BCM5700 Gigabit Ethernet" }, 1623 { PCI_VENDOR_BROADCOM, 1624 PCI_PRODUCT_BROADCOM_BCM5701, 1625 "Broadcom BCM5700 Gigabit Ethernet" }, 1626 1627 { PCI_VENDOR_SCHNEIDERKOCH, 1628 PCI_PRODUCT_SCHNEIDERKOCH_SK_9DX1, 1629 "SysKonnect SK-9Dx1 Gigabit Ethernet" }, 1630 1631 { PCI_VENDOR_3COM, 1632 PCI_PRODUCT_3COM_3C996, 1633 "3Com 3c996 Gigabit Ethernet" }, 1634 1635 { 0, 1636 0, 1637 NULL }, 1638 }; 1639 1640 static const struct bge_product * 1641 bge_lookup(const struct pci_attach_args *pa) 1642 { 1643 const struct bge_product *bp; 1644 1645 for (bp = bge_products; bp->bp_name != NULL; bp++) { 1646 if (PCI_VENDOR(pa->pa_id) == bp->bp_vendor && 1647 PCI_PRODUCT(pa->pa_id) == bp->bp_product) 1648 return (bp); 1649 } 1650 1651 return (NULL); 1652 } 1653 1654 /* 1655 * Probe for a Broadcom chip. Check the PCI vendor and device IDs 1656 * against our list and return its name if we find a match. Note 1657 * that since the Broadcom controller contains VPD support, we 1658 * can get the device name string from the controller itself instead 1659 * of the compiled-in string. This is a little slow, but it guarantees 1660 * we'll always announce the right product name. 1661 */ 1662 int 1663 bge_probe(parent, match, aux) 1664 struct device *parent; 1665 struct cfdata *match; 1666 void *aux; 1667 { 1668 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 1669 1670 if (bge_lookup(pa) != NULL) 1671 return (1); 1672 1673 return (0); 1674 } 1675 1676 void 1677 bge_attach(parent, self, aux) 1678 struct device *parent, *self; 1679 void *aux; 1680 { 1681 struct bge_softc *sc = (struct bge_softc *)self; 1682 struct pci_attach_args *pa = aux; 1683 const struct bge_product *bp; 1684 const struct bge_revision *br; 1685 pci_chipset_tag_t pc = pa->pa_pc; 1686 pci_intr_handle_t ih; 1687 const char *intrstr = NULL; 1688 bus_dma_segment_t seg; 1689 int rseg; 1690 u_int32_t hwcfg = 0; 1691 u_int32_t command; 1692 struct ifnet *ifp; 1693 int unit; 1694 caddr_t kva; 1695 u_char eaddr[ETHER_ADDR_LEN]; 1696 pcireg_t memtype; 1697 bus_addr_t memaddr; 1698 bus_size_t memsize; 1699 1700 bp = bge_lookup(pa); 1701 KASSERT(bp != NULL); 1702 1703 sc->bge_pa = *pa; 1704 1705 printf(": %s\n", bp->bp_name); 1706 1707 /* 1708 * Map control/status registers. 1709 */ 1710 DPRINTFN(5, ("Map control/status regs\n")); 1711 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 1712 command |= PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_MASTER_ENABLE; 1713 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, command); 1714 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 1715 1716 if (!(command & PCI_COMMAND_MEM_ENABLE)) { 1717 printf("%s: failed to enable memory mapping!\n", 1718 sc->bge_dev.dv_xname); 1719 return; 1720 } 1721 1722 DPRINTFN(5, ("pci_mem_find\n")); 1723 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, BGE_PCI_BAR0); 1724 switch (memtype) { 1725 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 1726 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 1727 if (pci_mapreg_map(pa, BGE_PCI_BAR0, 1728 memtype, 0, &sc->bge_btag, &sc->bge_bhandle, 1729 &memaddr, &memsize) == 0) 1730 break; 1731 default: 1732 printf("%s: can't find mem space\n", 1733 sc->bge_dev.dv_xname); 1734 return; 1735 } 1736 1737 DPRINTFN(5, ("pci_intr_map\n")); 1738 if (pci_intr_map(pa, &ih)) { 1739 printf("%s: couldn't map interrupt\n", 1740 sc->bge_dev.dv_xname); 1741 return; 1742 } 1743 1744 DPRINTFN(5, ("pci_intr_string\n")); 1745 intrstr = pci_intr_string(pc, ih); 1746 1747 DPRINTFN(5, ("pci_intr_establish\n")); 1748 sc->bge_intrhand = pci_intr_establish(pc, ih, IPL_NET, bge_intr, sc); 1749 1750 if (sc->bge_intrhand == NULL) { 1751 printf("%s: couldn't establish interrupt", 1752 sc->bge_dev.dv_xname); 1753 if (intrstr != NULL) 1754 printf(" at %s", intrstr); 1755 printf("\n"); 1756 return; 1757 } 1758 printf("%s: interrupting at %s\n", sc->bge_dev.dv_xname, intrstr); 1759 1760 /* Try to reset the chip. */ 1761 DPRINTFN(5, ("bge_reset\n")); 1762 bge_reset(sc); 1763 1764 if (bge_chipinit(sc)) { 1765 printf("%s: chip initializatino failed\n", 1766 sc->bge_dev.dv_xname); 1767 bge_release_resources(sc); 1768 return; 1769 } 1770 1771 /* 1772 * Get station address from the EEPROM. 1773 */ 1774 if (bge_read_eeprom(sc, (caddr_t)eaddr, 1775 BGE_EE_MAC_OFFSET + 2, ETHER_ADDR_LEN)) { 1776 printf("bge%d: failed to read station address\n", unit); 1777 bge_release_resources(sc); 1778 return; 1779 } 1780 1781 /* 1782 * Save ASIC rev. Look up any quirks associated with this 1783 * ASIC. 1784 */ 1785 sc->bge_asicrev = 1786 pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_MISC_CTL) & 1787 BGE_PCIMISCCTL_ASICREV; 1788 br = bge_lookup_rev(sc->bge_asicrev); 1789 1790 printf("%s: ", sc->bge_dev.dv_xname); 1791 if (br == NULL) { 1792 printf("unknown ASIC 0x%08x", sc->bge_asicrev); 1793 sc->bge_quirks = 0; 1794 } else { 1795 printf("ASIC %s", br->br_name); 1796 sc->bge_quirks = br->br_quirks; 1797 } 1798 printf(", Ethernet address %s\n", ether_sprintf(eaddr)); 1799 1800 /* Allocate the general information block and ring buffers. */ 1801 sc->bge_dmatag = pa->pa_dmat; 1802 DPRINTFN(5, ("bus_dmamem_alloc\n")); 1803 if (bus_dmamem_alloc(sc->bge_dmatag, sizeof(struct bge_ring_data), 1804 PAGE_SIZE, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 1805 printf("%s: can't alloc rx buffers\n", sc->bge_dev.dv_xname); 1806 return; 1807 } 1808 DPRINTFN(5, ("bus_dmamem_map\n")); 1809 if (bus_dmamem_map(sc->bge_dmatag, &seg, rseg, 1810 sizeof(struct bge_ring_data), &kva, 1811 BUS_DMA_NOWAIT)) { 1812 printf("%s: can't map dma buffers (%d bytes)\n", 1813 sc->bge_dev.dv_xname, (int)sizeof(struct bge_ring_data)); 1814 bus_dmamem_free(sc->bge_dmatag, &seg, rseg); 1815 return; 1816 } 1817 DPRINTFN(5, ("bus_dmamem_create\n")); 1818 if (bus_dmamap_create(sc->bge_dmatag, sizeof(struct bge_ring_data), 1, 1819 sizeof(struct bge_ring_data), 0, 1820 BUS_DMA_NOWAIT, &sc->bge_ring_map)) { 1821 printf("%s: can't create dma map\n", sc->bge_dev.dv_xname); 1822 bus_dmamem_unmap(sc->bge_dmatag, kva, 1823 sizeof(struct bge_ring_data)); 1824 bus_dmamem_free(sc->bge_dmatag, &seg, rseg); 1825 return; 1826 } 1827 DPRINTFN(5, ("bus_dmamem_load\n")); 1828 if (bus_dmamap_load(sc->bge_dmatag, sc->bge_ring_map, kva, 1829 sizeof(struct bge_ring_data), NULL, 1830 BUS_DMA_NOWAIT)) { 1831 bus_dmamap_destroy(sc->bge_dmatag, sc->bge_ring_map); 1832 bus_dmamem_unmap(sc->bge_dmatag, kva, 1833 sizeof(struct bge_ring_data)); 1834 bus_dmamem_free(sc->bge_dmatag, &seg, rseg); 1835 return; 1836 } 1837 1838 DPRINTFN(5, ("bzero\n")); 1839 sc->bge_rdata = (struct bge_ring_data *)kva; 1840 1841 memset(sc->bge_rdata, sizeof(struct bge_ring_data), 0); 1842 1843 /* Try to allocate memory for jumbo buffers. */ 1844 if (bge_alloc_jumbo_mem(sc)) { 1845 printf("%s: jumbo buffer allocation failed\n", 1846 sc->bge_dev.dv_xname); 1847 } else 1848 sc->ethercom.ec_capabilities |= ETHERCAP_JUMBO_MTU; 1849 1850 /* Set default tuneable values. */ 1851 sc->bge_stat_ticks = BGE_TICKS_PER_SEC; 1852 sc->bge_rx_coal_ticks = 150; 1853 sc->bge_tx_coal_ticks = 150; 1854 sc->bge_rx_max_coal_bds = 64; 1855 sc->bge_tx_max_coal_bds = 128; 1856 1857 /* Set up ifnet structure */ 1858 ifp = &sc->ethercom.ec_if; 1859 ifp->if_softc = sc; 1860 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1861 ifp->if_ioctl = bge_ioctl; 1862 ifp->if_start = bge_start; 1863 ifp->if_init = bge_init; 1864 ifp->if_watchdog = bge_watchdog; 1865 IFQ_SET_MAXLEN(&ifp->if_snd, BGE_TX_RING_CNT - 1); 1866 IFQ_SET_READY(&ifp->if_snd); 1867 DPRINTFN(5, ("bcopy\n")); 1868 strcpy(ifp->if_xname, sc->bge_dev.dv_xname); 1869 1870 sc->ethercom.ec_if.if_capabilities |= 1871 IFCAP_CSUM_IPv4 | IFCAP_CSUM_TCPv4 | IFCAP_CSUM_UDPv4; 1872 sc->ethercom.ec_capabilities |= 1873 ETHERCAP_VLAN_HWTAGGING | ETHERCAP_VLAN_MTU; 1874 1875 /* 1876 * Do MII setup. 1877 */ 1878 DPRINTFN(5, ("mii setup\n")); 1879 sc->bge_mii.mii_ifp = ifp; 1880 sc->bge_mii.mii_readreg = bge_miibus_readreg; 1881 sc->bge_mii.mii_writereg = bge_miibus_writereg; 1882 sc->bge_mii.mii_statchg = bge_miibus_statchg; 1883 1884 /* 1885 * Figure out what sort of media we have by checking the 1886 * hardware config word in the EEPROM. Note: on some BCM5700 1887 * cards, this value appears to be unset. If that's the 1888 * case, we have to rely on identifying the NIC by its PCI 1889 * subsystem ID, as we do below for the SysKonnect SK-9D41. 1890 */ 1891 bge_read_eeprom(sc, (caddr_t)&hwcfg, 1892 BGE_EE_HWCFG_OFFSET, sizeof(hwcfg)); 1893 if ((be32toh(hwcfg) & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER) 1894 sc->bge_tbi = 1; 1895 1896 /* The SysKonnect SK-9D41 is a 1000baseSX card. */ 1897 if ((pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_SUBSYS) >> 16) == 1898 SK_SUBSYSID_9D41) 1899 sc->bge_tbi = 1; 1900 1901 if (sc->bge_tbi) { 1902 ifmedia_init(&sc->bge_ifmedia, IFM_IMASK, bge_ifmedia_upd, 1903 bge_ifmedia_sts); 1904 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL); 1905 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_1000_SX|IFM_FDX, 1906 0, NULL); 1907 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL); 1908 ifmedia_set(&sc->bge_ifmedia, IFM_ETHER|IFM_AUTO); 1909 } else { 1910 /* 1911 * Do transceiver setup. 1912 */ 1913 ifmedia_init(&sc->bge_mii.mii_media, 0, bge_ifmedia_upd, 1914 bge_ifmedia_sts); 1915 mii_attach(&sc->bge_dev, &sc->bge_mii, 0xffffffff, 1916 MII_PHY_ANY, MII_OFFSET_ANY, 0); 1917 1918 if (LIST_FIRST(&sc->bge_mii.mii_phys) == NULL) { 1919 printf("%s: no PHY found!\n", sc->bge_dev.dv_xname); 1920 ifmedia_add(&sc->bge_mii.mii_media, 1921 IFM_ETHER|IFM_MANUAL, 0, NULL); 1922 ifmedia_set(&sc->bge_mii.mii_media, 1923 IFM_ETHER|IFM_MANUAL); 1924 } else 1925 ifmedia_set(&sc->bge_mii.mii_media, 1926 IFM_ETHER|IFM_AUTO); 1927 } 1928 1929 /* 1930 * Call MI attach routine. 1931 */ 1932 DPRINTFN(5, ("if_attach\n")); 1933 if_attach(ifp); 1934 DPRINTFN(5, ("ether_ifattach\n")); 1935 ether_ifattach(ifp, eaddr); 1936 DPRINTFN(5, ("callout_init\n")); 1937 callout_init(&sc->bge_timeout); 1938 } 1939 1940 void 1941 bge_release_resources(sc) 1942 struct bge_softc *sc; 1943 { 1944 if (sc->bge_vpd_prodname != NULL) 1945 free(sc->bge_vpd_prodname, M_DEVBUF); 1946 1947 if (sc->bge_vpd_readonly != NULL) 1948 free(sc->bge_vpd_readonly, M_DEVBUF); 1949 } 1950 1951 void 1952 bge_reset(sc) 1953 struct bge_softc *sc; 1954 { 1955 struct pci_attach_args *pa = &sc->bge_pa; 1956 u_int32_t cachesize, command, pcistate; 1957 int i, val = 0; 1958 1959 /* Save some important PCI state. */ 1960 cachesize = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_CACHESZ); 1961 command = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_CMD); 1962 pcistate = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_PCISTATE); 1963 1964 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_MISC_CTL, 1965 BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR| 1966 BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_PCISTATE_RW); 1967 1968 /* Issue global reset */ 1969 bge_writereg_ind(sc, BGE_MISC_CFG, 1970 BGE_MISCCFG_RESET_CORE_CLOCKS|(65<<1)); 1971 1972 DELAY(1000); 1973 1974 /* Reset some of the PCI state that got zapped by reset */ 1975 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_MISC_CTL, 1976 BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR| 1977 BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_PCISTATE_RW); 1978 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_CMD, command); 1979 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_CACHESZ, cachesize); 1980 bge_writereg_ind(sc, BGE_MISC_CFG, (65 << 1)); 1981 1982 /* Enable memory arbiter. */ 1983 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 1984 1985 /* 1986 * Prevent PXE restart: write a magic number to the 1987 * general communications memory at 0xB50. 1988 */ 1989 bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM, BGE_MAGIC_NUMBER); 1990 1991 /* 1992 * Poll the value location we just wrote until 1993 * we see the 1's complement of the magic number. 1994 * This indicates that the firmware initialization 1995 * is complete. 1996 */ 1997 for (i = 0; i < 750; i++) { 1998 val = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM); 1999 if (val == ~BGE_MAGIC_NUMBER) 2000 break; 2001 DELAY(1000); 2002 } 2003 2004 if (i == 750) { 2005 printf("%s: firmware handshake timed out, val = %x\n", 2006 sc->bge_dev.dv_xname, val); 2007 return; 2008 } 2009 2010 /* 2011 * XXX Wait for the value of the PCISTATE register to 2012 * return to its original pre-reset state. This is a 2013 * fairly good indicator of reset completion. If we don't 2014 * wait for the reset to fully complete, trying to read 2015 * from the device's non-PCI registers may yield garbage 2016 * results. 2017 */ 2018 for (i = 0; i < BGE_TIMEOUT; i++) { 2019 if (pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_PCISTATE) == 2020 pcistate) 2021 break; 2022 DELAY(10); 2023 } 2024 2025 /* Enable memory arbiter. */ 2026 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 2027 2028 /* Fix up byte swapping */ 2029 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS); 2030 2031 CSR_WRITE_4(sc, BGE_MAC_MODE, 0); 2032 2033 DELAY(10000); 2034 } 2035 2036 /* 2037 * Frame reception handling. This is called if there's a frame 2038 * on the receive return list. 2039 * 2040 * Note: we have to be able to handle two possibilities here: 2041 * 1) the frame is from the jumbo recieve ring 2042 * 2) the frame is from the standard receive ring 2043 */ 2044 2045 void 2046 bge_rxeof(sc) 2047 struct bge_softc *sc; 2048 { 2049 struct ifnet *ifp; 2050 int stdcnt = 0, jumbocnt = 0; 2051 int have_tag = 0; 2052 u_int16_t vlan_tag = 0; 2053 bus_dmamap_t dmamap; 2054 bus_addr_t offset, toff; 2055 bus_size_t tlen; 2056 int tosync; 2057 2058 ifp = &sc->ethercom.ec_if; 2059 2060 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 2061 offsetof(struct bge_ring_data, bge_status_block), 2062 sizeof (struct bge_status_block), 2063 BUS_DMASYNC_POSTREAD); 2064 2065 offset = offsetof(struct bge_ring_data, bge_rx_return_ring); 2066 tosync = sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx - 2067 sc->bge_rx_saved_considx; 2068 2069 toff = offset + (sc->bge_rx_saved_considx * sizeof (struct bge_rx_bd)); 2070 2071 if (tosync < 0) { 2072 tlen = (BGE_RETURN_RING_CNT - sc->bge_rx_saved_considx) * 2073 sizeof (struct bge_rx_bd); 2074 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 2075 toff, tlen, BUS_DMASYNC_POSTREAD); 2076 tosync = -tosync; 2077 } 2078 2079 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 2080 offset, tosync * sizeof (struct bge_rx_bd), 2081 BUS_DMASYNC_POSTREAD); 2082 2083 while(sc->bge_rx_saved_considx != 2084 sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx) { 2085 struct bge_rx_bd *cur_rx; 2086 u_int32_t rxidx; 2087 struct mbuf *m = NULL; 2088 2089 cur_rx = &sc->bge_rdata-> 2090 bge_rx_return_ring[sc->bge_rx_saved_considx]; 2091 2092 rxidx = cur_rx->bge_idx; 2093 BGE_INC(sc->bge_rx_saved_considx, BGE_RETURN_RING_CNT); 2094 2095 if (cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) { 2096 have_tag = 1; 2097 vlan_tag = cur_rx->bge_vlan_tag; 2098 } 2099 2100 if (cur_rx->bge_flags & BGE_RXBDFLAG_JUMBO_RING) { 2101 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT); 2102 m = sc->bge_cdata.bge_rx_jumbo_chain[rxidx]; 2103 sc->bge_cdata.bge_rx_jumbo_chain[rxidx] = NULL; 2104 jumbocnt++; 2105 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 2106 ifp->if_ierrors++; 2107 bge_newbuf_jumbo(sc, sc->bge_jumbo, m); 2108 continue; 2109 } 2110 if (bge_newbuf_jumbo(sc, sc->bge_jumbo, 2111 NULL)== ENOBUFS) { 2112 ifp->if_ierrors++; 2113 bge_newbuf_jumbo(sc, sc->bge_jumbo, m); 2114 continue; 2115 } 2116 } else { 2117 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT); 2118 m = sc->bge_cdata.bge_rx_std_chain[rxidx]; 2119 sc->bge_cdata.bge_rx_std_chain[rxidx] = NULL; 2120 stdcnt++; 2121 dmamap = sc->bge_cdata.bge_rx_std_map[rxidx]; 2122 sc->bge_cdata.bge_rx_std_map[rxidx] = 0; 2123 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 2124 ifp->if_ierrors++; 2125 bge_newbuf_std(sc, sc->bge_std, m, dmamap); 2126 continue; 2127 } 2128 if (bge_newbuf_std(sc, sc->bge_std, 2129 NULL, dmamap) == ENOBUFS) { 2130 ifp->if_ierrors++; 2131 bge_newbuf_std(sc, sc->bge_std, m, dmamap); 2132 continue; 2133 } 2134 } 2135 2136 ifp->if_ipackets++; 2137 m->m_pkthdr.len = m->m_len = cur_rx->bge_len; 2138 m->m_pkthdr.rcvif = ifp; 2139 2140 #if NBPFILTER > 0 2141 /* 2142 * Handle BPF listeners. Let the BPF user see the packet. 2143 */ 2144 if (ifp->if_bpf) 2145 bpf_mtap(ifp->if_bpf, m); 2146 #endif 2147 2148 if (sc->bge_asicrev != BGE_ASICREV_BCM5700_B0) { 2149 m->m_pkthdr.csum_flags |= M_CSUM_IPv4; 2150 if ((cur_rx->bge_ip_csum ^ 0xffff) != 0) 2151 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 2152 #if 0 /* XXX appears to be broken */ 2153 if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM) { 2154 m->m_pkthdr.csum_data = 2155 cur_rx->bge_tcp_udp_csum; 2156 m->m_pkthdr.csum_flags |= 2157 (M_CSUM_TCPv4|M_CSUM_UDPv4|M_CSUM_DATA); 2158 } 2159 #endif 2160 } 2161 2162 /* 2163 * If we received a packet with a vlan tag, pass it 2164 * to vlan_input() instead of ether_input(). 2165 */ 2166 if (have_tag) { 2167 struct mbuf *n; 2168 2169 n = m_aux_add(m, AF_LINK, ETHERTYPE_VLAN); 2170 if (n != NULL) { 2171 *mtod(n, int *) = vlan_tag; 2172 n->m_len = sizeof(int); 2173 have_tag = vlan_tag = 0; 2174 } else { 2175 printf("%s: no mbuf for tag\n", ifp->if_xname); 2176 m_freem(m); 2177 have_tag = vlan_tag = 0; 2178 continue; 2179 } 2180 } 2181 (*ifp->if_input)(ifp, m); 2182 } 2183 2184 CSR_WRITE_4(sc, BGE_MBX_RX_CONS0_LO, sc->bge_rx_saved_considx); 2185 if (stdcnt) 2186 CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std); 2187 if (jumbocnt) 2188 CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo); 2189 } 2190 2191 void 2192 bge_txeof(sc) 2193 struct bge_softc *sc; 2194 { 2195 struct bge_tx_bd *cur_tx = NULL; 2196 struct ifnet *ifp; 2197 struct txdmamap_pool_entry *dma; 2198 bus_addr_t offset, toff; 2199 bus_size_t tlen; 2200 int tosync; 2201 struct mbuf *m; 2202 2203 ifp = &sc->ethercom.ec_if; 2204 2205 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 2206 offsetof(struct bge_ring_data, bge_status_block), 2207 sizeof (struct bge_status_block), 2208 BUS_DMASYNC_POSTREAD); 2209 2210 offset = offsetof(struct bge_ring_data, bge_tx_ring); 2211 tosync = sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx - 2212 sc->bge_tx_saved_considx; 2213 2214 toff = offset + (sc->bge_tx_saved_considx * sizeof (struct bge_tx_bd)); 2215 2216 if (tosync < 0) { 2217 tlen = (BGE_TX_RING_CNT - sc->bge_tx_saved_considx) * 2218 sizeof (struct bge_tx_bd); 2219 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 2220 toff, tlen, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2221 tosync = -tosync; 2222 } 2223 2224 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 2225 offset, tosync * sizeof (struct bge_tx_bd), 2226 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2227 2228 /* 2229 * Go through our tx ring and free mbufs for those 2230 * frames that have been sent. 2231 */ 2232 while (sc->bge_tx_saved_considx != 2233 sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx) { 2234 u_int32_t idx = 0; 2235 2236 idx = sc->bge_tx_saved_considx; 2237 cur_tx = &sc->bge_rdata->bge_tx_ring[idx]; 2238 if (cur_tx->bge_flags & BGE_TXBDFLAG_END) 2239 ifp->if_opackets++; 2240 m = sc->bge_cdata.bge_tx_chain[idx]; 2241 if (m != NULL) { 2242 sc->bge_cdata.bge_tx_chain[idx] = NULL; 2243 dma = sc->txdma[idx]; 2244 bus_dmamap_sync(sc->bge_dmatag, dma->dmamap, 0, 2245 dma->dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 2246 bus_dmamap_unload(sc->bge_dmatag, dma->dmamap); 2247 SLIST_INSERT_HEAD(&sc->txdma_list, dma, link); 2248 sc->txdma[idx] = NULL; 2249 2250 m_freem(m); 2251 } 2252 sc->bge_txcnt--; 2253 BGE_INC(sc->bge_tx_saved_considx, BGE_TX_RING_CNT); 2254 ifp->if_timer = 0; 2255 } 2256 2257 if (cur_tx != NULL) 2258 ifp->if_flags &= ~IFF_OACTIVE; 2259 } 2260 2261 int 2262 bge_intr(xsc) 2263 void *xsc; 2264 { 2265 struct bge_softc *sc; 2266 struct ifnet *ifp; 2267 2268 sc = xsc; 2269 ifp = &sc->ethercom.ec_if; 2270 2271 #ifdef notdef 2272 /* Avoid this for now -- checking this register is expensive. */ 2273 /* Make sure this is really our interrupt. */ 2274 if (!(CSR_READ_4(sc, BGE_MISC_LOCAL_CTL) & BGE_MLC_INTR_STATE)) 2275 return (0); 2276 #endif 2277 /* Ack interrupt and stop others from occuring. */ 2278 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 1); 2279 2280 /* 2281 * Process link state changes. 2282 * Grrr. The link status word in the status block does 2283 * not work correctly on the BCM5700 rev AX and BX chips, 2284 * according to all avaibable information. Hence, we have 2285 * to enable MII interrupts in order to properly obtain 2286 * async link changes. Unfortunately, this also means that 2287 * we have to read the MAC status register to detect link 2288 * changes, thereby adding an additional register access to 2289 * the interrupt handler. 2290 */ 2291 2292 if (BGE_IS_5700_Ax_Bx(sc->bge_asicrev)) { 2293 u_int32_t status; 2294 2295 status = CSR_READ_4(sc, BGE_MAC_STS); 2296 if (status & BGE_MACSTAT_MI_INTERRUPT) { 2297 sc->bge_link = 0; 2298 callout_stop(&sc->bge_timeout); 2299 bge_tick(sc); 2300 /* Clear the interrupt */ 2301 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, 2302 BGE_EVTENB_MI_INTERRUPT); 2303 bge_miibus_readreg(&sc->bge_dev, 1, BRGPHY_MII_ISR); 2304 bge_miibus_writereg(&sc->bge_dev, 1, BRGPHY_MII_IMR, 2305 BRGPHY_INTRS); 2306 } 2307 } else { 2308 if (sc->bge_rdata->bge_status_block.bge_status & 2309 BGE_STATFLAG_LINKSTATE_CHANGED) { 2310 sc->bge_link = 0; 2311 callout_stop(&sc->bge_timeout); 2312 bge_tick(sc); 2313 /* Clear the interrupt */ 2314 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED| 2315 BGE_MACSTAT_CFG_CHANGED); 2316 } 2317 } 2318 2319 if (ifp->if_flags & IFF_RUNNING) { 2320 /* Check RX return ring producer/consumer */ 2321 bge_rxeof(sc); 2322 2323 /* Check TX ring producer/consumer */ 2324 bge_txeof(sc); 2325 } 2326 2327 bge_handle_events(sc); 2328 2329 /* Re-enable interrupts. */ 2330 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 0); 2331 2332 if (ifp->if_flags & IFF_RUNNING && !IFQ_IS_EMPTY(&ifp->if_snd)) 2333 bge_start(ifp); 2334 2335 return (1); 2336 } 2337 2338 void 2339 bge_tick(xsc) 2340 void *xsc; 2341 { 2342 struct bge_softc *sc = xsc; 2343 struct mii_data *mii = &sc->bge_mii; 2344 struct ifmedia *ifm = NULL; 2345 struct ifnet *ifp = &sc->ethercom.ec_if; 2346 int s; 2347 2348 s = splnet(); 2349 2350 bge_stats_update(sc); 2351 callout_reset(&sc->bge_timeout, hz, bge_tick, sc); 2352 if (sc->bge_link) { 2353 splx(s); 2354 return; 2355 } 2356 2357 if (sc->bge_tbi) { 2358 ifm = &sc->bge_ifmedia; 2359 if (CSR_READ_4(sc, BGE_MAC_STS) & 2360 BGE_MACSTAT_TBI_PCS_SYNCHED) { 2361 sc->bge_link++; 2362 CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF); 2363 printf("%s: gigabit link up\n", sc->bge_dev.dv_xname); 2364 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 2365 bge_start(ifp); 2366 } 2367 splx(s); 2368 return; 2369 } 2370 2371 mii_tick(mii); 2372 2373 if (!sc->bge_link && mii->mii_media_status & IFM_ACTIVE && 2374 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 2375 sc->bge_link++; 2376 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T || 2377 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX) 2378 printf("%s: gigabit link up\n", sc->bge_dev.dv_xname); 2379 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 2380 bge_start(ifp); 2381 } 2382 2383 splx(s); 2384 } 2385 2386 void 2387 bge_stats_update(sc) 2388 struct bge_softc *sc; 2389 { 2390 struct ifnet *ifp = &sc->ethercom.ec_if; 2391 bus_size_t stats = BGE_MEMWIN_START + BGE_STATS_BLOCK; 2392 2393 #define READ_STAT(sc, stats, stat) \ 2394 CSR_READ_4(sc, stats + offsetof(struct bge_stats, stat)) 2395 2396 ifp->if_collisions += 2397 (READ_STAT(sc, stats, dot3StatsSingleCollisionFrames.bge_addr_lo) + 2398 READ_STAT(sc, stats, dot3StatsMultipleCollisionFrames.bge_addr_lo) + 2399 READ_STAT(sc, stats, dot3StatsExcessiveCollisions.bge_addr_lo) + 2400 READ_STAT(sc, stats, dot3StatsLateCollisions.bge_addr_lo)) - 2401 ifp->if_collisions; 2402 2403 #undef READ_STAT 2404 2405 #ifdef notdef 2406 ifp->if_collisions += 2407 (sc->bge_rdata->bge_info.bge_stats.dot3StatsSingleCollisionFrames + 2408 sc->bge_rdata->bge_info.bge_stats.dot3StatsMultipleCollisionFrames + 2409 sc->bge_rdata->bge_info.bge_stats.dot3StatsExcessiveCollisions + 2410 sc->bge_rdata->bge_info.bge_stats.dot3StatsLateCollisions) - 2411 ifp->if_collisions; 2412 #endif 2413 } 2414 2415 /* 2416 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data 2417 * pointers to descriptors. 2418 */ 2419 int 2420 bge_encap(sc, m_head, txidx) 2421 struct bge_softc *sc; 2422 struct mbuf *m_head; 2423 u_int32_t *txidx; 2424 { 2425 struct bge_tx_bd *f = NULL; 2426 u_int32_t frag, cur, cnt = 0; 2427 u_int16_t csum_flags = 0; 2428 struct txdmamap_pool_entry *dma; 2429 bus_dmamap_t dmamap; 2430 int i = 0; 2431 struct mbuf *n; 2432 2433 cur = frag = *txidx; 2434 2435 if (m_head->m_pkthdr.csum_flags) { 2436 if (m_head->m_pkthdr.csum_flags & M_CSUM_IPv4) 2437 csum_flags |= BGE_TXBDFLAG_IP_CSUM; 2438 if (m_head->m_pkthdr.csum_flags & (M_CSUM_TCPv4|M_CSUM_UDPv4)) 2439 csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM; 2440 } 2441 2442 dma = SLIST_FIRST(&sc->txdma_list); 2443 if (dma == NULL) 2444 return ENOBUFS; 2445 dmamap = dma->dmamap; 2446 2447 /* 2448 * Start packing the mbufs in this chain into 2449 * the fragment pointers. Stop when we run out 2450 * of fragments or hit the end of the mbuf chain. 2451 */ 2452 if (bus_dmamap_load_mbuf(sc->bge_dmatag, dmamap, m_head, 2453 BUS_DMA_NOWAIT)) 2454 return(ENOBUFS); 2455 2456 n = sc->ethercom.ec_nvlans ? 2457 m_aux_find(m_head, AF_LINK, ETHERTYPE_VLAN) : NULL; 2458 2459 for (i = 0; i < dmamap->dm_nsegs; i++) { 2460 f = &sc->bge_rdata->bge_tx_ring[frag]; 2461 if (sc->bge_cdata.bge_tx_chain[frag] != NULL) 2462 break; 2463 bge_set_hostaddr(&f->bge_addr, dmamap->dm_segs[i].ds_addr); 2464 f->bge_len = dmamap->dm_segs[i].ds_len; 2465 f->bge_flags = csum_flags; 2466 2467 if (n != NULL) { 2468 f->bge_flags |= BGE_TXBDFLAG_VLAN_TAG; 2469 f->bge_vlan_tag = *mtod(n, int *); 2470 } else { 2471 f->bge_vlan_tag = 0; 2472 } 2473 /* 2474 * Sanity check: avoid coming within 16 descriptors 2475 * of the end of the ring. 2476 */ 2477 if ((BGE_TX_RING_CNT - (sc->bge_txcnt + cnt)) < 16) 2478 return(ENOBUFS); 2479 cur = frag; 2480 BGE_INC(frag, BGE_TX_RING_CNT); 2481 cnt++; 2482 } 2483 2484 if (i < dmamap->dm_nsegs) 2485 return ENOBUFS; 2486 2487 bus_dmamap_sync(sc->bge_dmatag, dmamap, 0, dmamap->dm_mapsize, 2488 BUS_DMASYNC_PREWRITE); 2489 2490 if (frag == sc->bge_tx_saved_considx) 2491 return(ENOBUFS); 2492 2493 sc->bge_rdata->bge_tx_ring[cur].bge_flags |= BGE_TXBDFLAG_END; 2494 sc->bge_cdata.bge_tx_chain[cur] = m_head; 2495 SLIST_REMOVE_HEAD(&sc->txdma_list, link); 2496 sc->txdma[cur] = dma; 2497 sc->bge_txcnt += cnt; 2498 2499 *txidx = frag; 2500 2501 return(0); 2502 } 2503 2504 /* 2505 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 2506 * to the mbuf data regions directly in the transmit descriptors. 2507 */ 2508 void 2509 bge_start(ifp) 2510 struct ifnet *ifp; 2511 { 2512 struct bge_softc *sc; 2513 struct mbuf *m_head = NULL; 2514 u_int32_t prodidx = 0; 2515 int pkts = 0; 2516 2517 sc = ifp->if_softc; 2518 2519 if (!sc->bge_link && ifp->if_snd.ifq_len < 10) 2520 return; 2521 2522 prodidx = CSR_READ_4(sc, BGE_MBX_TX_HOST_PROD0_LO); 2523 2524 while(sc->bge_cdata.bge_tx_chain[prodidx] == NULL) { 2525 IFQ_POLL(&ifp->if_snd, m_head); 2526 if (m_head == NULL) 2527 break; 2528 2529 #if 0 2530 /* 2531 * XXX 2532 * safety overkill. If this is a fragmented packet chain 2533 * with delayed TCP/UDP checksums, then only encapsulate 2534 * it if we have enough descriptors to handle the entire 2535 * chain at once. 2536 * (paranoia -- may not actually be needed) 2537 */ 2538 if (m_head->m_flags & M_FIRSTFRAG && 2539 m_head->m_pkthdr.csum_flags & (CSUM_DELAY_DATA)) { 2540 if ((BGE_TX_RING_CNT - sc->bge_txcnt) < 2541 m_head->m_pkthdr.csum_data + 16) { 2542 ifp->if_flags |= IFF_OACTIVE; 2543 break; 2544 } 2545 } 2546 #endif 2547 2548 /* 2549 * Pack the data into the transmit ring. If we 2550 * don't have room, set the OACTIVE flag and wait 2551 * for the NIC to drain the ring. 2552 */ 2553 if (bge_encap(sc, m_head, &prodidx)) { 2554 ifp->if_flags |= IFF_OACTIVE; 2555 break; 2556 } 2557 2558 /* now we are committed to transmit the packet */ 2559 IFQ_DEQUEUE(&ifp->if_snd, m_head); 2560 pkts++; 2561 2562 #if NBPFILTER > 0 2563 /* 2564 * If there's a BPF listener, bounce a copy of this frame 2565 * to him. 2566 */ 2567 if (ifp->if_bpf) 2568 bpf_mtap(ifp->if_bpf, m_head); 2569 #endif 2570 } 2571 if (pkts == 0) 2572 return; 2573 2574 /* Transmit */ 2575 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); 2576 2577 /* 2578 * Set a timeout in case the chip goes out to lunch. 2579 */ 2580 ifp->if_timer = 5; 2581 } 2582 2583 int 2584 bge_init(ifp) 2585 struct ifnet *ifp; 2586 { 2587 struct bge_softc *sc = ifp->if_softc; 2588 u_int16_t *m; 2589 int s, error; 2590 2591 s = splnet(); 2592 2593 ifp = &sc->ethercom.ec_if; 2594 2595 /* Cancel pending I/O and flush buffers. */ 2596 bge_stop(sc); 2597 bge_reset(sc); 2598 bge_chipinit(sc); 2599 2600 /* 2601 * Init the various state machines, ring 2602 * control blocks and firmware. 2603 */ 2604 error = bge_blockinit(sc); 2605 if (error != 0) { 2606 printf("%s: initialization error %d\n", sc->bge_dev.dv_xname, 2607 error); 2608 splx(s); 2609 return error; 2610 } 2611 2612 ifp = &sc->ethercom.ec_if; 2613 2614 /* Specify MTU. */ 2615 CSR_WRITE_4(sc, BGE_RX_MTU, ifp->if_mtu + 2616 ETHER_HDR_LEN + ETHER_CRC_LEN); 2617 2618 /* Load our MAC address. */ 2619 m = (u_int16_t *)&(LLADDR(ifp->if_sadl)[0]); 2620 CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0])); 2621 CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, (htons(m[1]) << 16) | htons(m[2])); 2622 2623 /* Enable or disable promiscuous mode as needed. */ 2624 if (ifp->if_flags & IFF_PROMISC) { 2625 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 2626 } else { 2627 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 2628 } 2629 2630 /* Program multicast filter. */ 2631 bge_setmulti(sc); 2632 2633 /* Init RX ring. */ 2634 bge_init_rx_ring_std(sc); 2635 2636 /* Init jumbo RX ring. */ 2637 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 2638 bge_init_rx_ring_jumbo(sc); 2639 2640 /* Init our RX return ring index */ 2641 sc->bge_rx_saved_considx = 0; 2642 2643 /* Init TX ring. */ 2644 bge_init_tx_ring(sc); 2645 2646 /* Turn on transmitter */ 2647 BGE_SETBIT(sc, BGE_TX_MODE, BGE_TXMODE_ENABLE); 2648 2649 /* Turn on receiver */ 2650 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE); 2651 2652 /* Tell firmware we're alive. */ 2653 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 2654 2655 /* Enable host interrupts. */ 2656 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA); 2657 BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); 2658 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 0); 2659 2660 bge_ifmedia_upd(ifp); 2661 2662 ifp->if_flags |= IFF_RUNNING; 2663 ifp->if_flags &= ~IFF_OACTIVE; 2664 2665 splx(s); 2666 2667 callout_reset(&sc->bge_timeout, hz, bge_tick, sc); 2668 2669 return 0; 2670 } 2671 2672 /* 2673 * Set media options. 2674 */ 2675 int 2676 bge_ifmedia_upd(ifp) 2677 struct ifnet *ifp; 2678 { 2679 struct bge_softc *sc = ifp->if_softc; 2680 struct mii_data *mii = &sc->bge_mii; 2681 struct ifmedia *ifm = &sc->bge_ifmedia; 2682 2683 /* If this is a 1000baseX NIC, enable the TBI port. */ 2684 if (sc->bge_tbi) { 2685 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 2686 return(EINVAL); 2687 switch(IFM_SUBTYPE(ifm->ifm_media)) { 2688 case IFM_AUTO: 2689 break; 2690 case IFM_1000_SX: 2691 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 2692 BGE_CLRBIT(sc, BGE_MAC_MODE, 2693 BGE_MACMODE_HALF_DUPLEX); 2694 } else { 2695 BGE_SETBIT(sc, BGE_MAC_MODE, 2696 BGE_MACMODE_HALF_DUPLEX); 2697 } 2698 break; 2699 default: 2700 return(EINVAL); 2701 } 2702 return(0); 2703 } 2704 2705 sc->bge_link = 0; 2706 mii_mediachg(mii); 2707 2708 return(0); 2709 } 2710 2711 /* 2712 * Report current media status. 2713 */ 2714 void 2715 bge_ifmedia_sts(ifp, ifmr) 2716 struct ifnet *ifp; 2717 struct ifmediareq *ifmr; 2718 { 2719 struct bge_softc *sc = ifp->if_softc; 2720 struct mii_data *mii = &sc->bge_mii; 2721 2722 if (sc->bge_tbi) { 2723 ifmr->ifm_status = IFM_AVALID; 2724 ifmr->ifm_active = IFM_ETHER; 2725 if (CSR_READ_4(sc, BGE_MAC_STS) & 2726 BGE_MACSTAT_TBI_PCS_SYNCHED) 2727 ifmr->ifm_status |= IFM_ACTIVE; 2728 ifmr->ifm_active |= IFM_1000_SX; 2729 if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX) 2730 ifmr->ifm_active |= IFM_HDX; 2731 else 2732 ifmr->ifm_active |= IFM_FDX; 2733 return; 2734 } 2735 2736 mii_pollstat(mii); 2737 ifmr->ifm_active = mii->mii_media_active; 2738 ifmr->ifm_status = mii->mii_media_status; 2739 } 2740 2741 int 2742 bge_ioctl(ifp, command, data) 2743 struct ifnet *ifp; 2744 u_long command; 2745 caddr_t data; 2746 { 2747 struct bge_softc *sc = ifp->if_softc; 2748 struct ifreq *ifr = (struct ifreq *) data; 2749 int s, error = 0; 2750 struct mii_data *mii; 2751 2752 s = splnet(); 2753 2754 switch(command) { 2755 case SIOCSIFFLAGS: 2756 if (ifp->if_flags & IFF_UP) { 2757 /* 2758 * If only the state of the PROMISC flag changed, 2759 * then just use the 'set promisc mode' command 2760 * instead of reinitializing the entire NIC. Doing 2761 * a full re-init means reloading the firmware and 2762 * waiting for it to start up, which may take a 2763 * second or two. 2764 */ 2765 if (ifp->if_flags & IFF_RUNNING && 2766 ifp->if_flags & IFF_PROMISC && 2767 !(sc->bge_if_flags & IFF_PROMISC)) { 2768 BGE_SETBIT(sc, BGE_RX_MODE, 2769 BGE_RXMODE_RX_PROMISC); 2770 } else if (ifp->if_flags & IFF_RUNNING && 2771 !(ifp->if_flags & IFF_PROMISC) && 2772 sc->bge_if_flags & IFF_PROMISC) { 2773 BGE_CLRBIT(sc, BGE_RX_MODE, 2774 BGE_RXMODE_RX_PROMISC); 2775 } else 2776 bge_init(ifp); 2777 } else { 2778 if (ifp->if_flags & IFF_RUNNING) { 2779 bge_stop(sc); 2780 } 2781 } 2782 sc->bge_if_flags = ifp->if_flags; 2783 error = 0; 2784 break; 2785 case SIOCSIFMEDIA: 2786 case SIOCGIFMEDIA: 2787 if (sc->bge_tbi) { 2788 error = ifmedia_ioctl(ifp, ifr, &sc->bge_ifmedia, 2789 command); 2790 } else { 2791 mii = &sc->bge_mii; 2792 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, 2793 command); 2794 } 2795 error = 0; 2796 break; 2797 default: 2798 error = ether_ioctl(ifp, command, data); 2799 if (error == ENETRESET) { 2800 bge_setmulti(sc); 2801 error = 0; 2802 } 2803 break; 2804 } 2805 2806 splx(s); 2807 2808 return(error); 2809 } 2810 2811 void 2812 bge_watchdog(ifp) 2813 struct ifnet *ifp; 2814 { 2815 struct bge_softc *sc; 2816 2817 sc = ifp->if_softc; 2818 2819 printf("%s: watchdog timeout -- resetting\n", sc->bge_dev.dv_xname); 2820 2821 ifp->if_flags &= ~IFF_RUNNING; 2822 bge_init(ifp); 2823 2824 ifp->if_oerrors++; 2825 } 2826 2827 static void 2828 bge_stop_block(struct bge_softc *sc, bus_addr_t reg, uint32_t bit) 2829 { 2830 int i; 2831 2832 BGE_CLRBIT(sc, reg, bit); 2833 2834 for (i = 0; i < BGE_TIMEOUT; i++) { 2835 if ((CSR_READ_4(sc, reg) & bit) == 0) 2836 return; 2837 delay(100); 2838 } 2839 2840 printf("%s: block failed to stop: reg 0x%lx, bit 0x%08x\n", 2841 sc->bge_dev.dv_xname, (u_long) reg, bit); 2842 } 2843 2844 /* 2845 * Stop the adapter and free any mbufs allocated to the 2846 * RX and TX lists. 2847 */ 2848 void 2849 bge_stop(sc) 2850 struct bge_softc *sc; 2851 { 2852 struct ifnet *ifp = &sc->ethercom.ec_if; 2853 2854 callout_stop(&sc->bge_timeout); 2855 2856 /* 2857 * Disable all of the receiver blocks 2858 */ 2859 bge_stop_block(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE); 2860 bge_stop_block(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 2861 bge_stop_block(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 2862 bge_stop_block(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 2863 bge_stop_block(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE); 2864 bge_stop_block(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 2865 bge_stop_block(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE); 2866 2867 /* 2868 * Disable all of the transmit blocks 2869 */ 2870 bge_stop_block(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 2871 bge_stop_block(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 2872 bge_stop_block(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 2873 bge_stop_block(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE); 2874 bge_stop_block(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE); 2875 bge_stop_block(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 2876 bge_stop_block(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 2877 2878 /* 2879 * Shut down all of the memory managers and related 2880 * state machines. 2881 */ 2882 bge_stop_block(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE); 2883 bge_stop_block(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE); 2884 bge_stop_block(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 2885 2886 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 2887 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 2888 2889 bge_stop_block(sc, BGE_BMAN_MODE, BGE_BMANMODE_ENABLE); 2890 bge_stop_block(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 2891 2892 /* Disable host interrupts. */ 2893 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); 2894 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 1); 2895 2896 /* 2897 * Tell firmware we're shutting down. 2898 */ 2899 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 2900 2901 /* Free the RX lists. */ 2902 bge_free_rx_ring_std(sc); 2903 2904 /* Free jumbo RX list. */ 2905 bge_free_rx_ring_jumbo(sc); 2906 2907 /* Free TX buffers. */ 2908 bge_free_tx_ring(sc); 2909 2910 /* 2911 * Isolate/power down the PHY. 2912 */ 2913 if (!sc->bge_tbi) 2914 mii_down(&sc->bge_mii); 2915 2916 sc->bge_link = 0; 2917 2918 sc->bge_tx_saved_considx = BGE_TXCONS_UNSET; 2919 2920 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2921 } 2922 2923 /* 2924 * Stop all chip I/O so that the kernel's probe routines don't 2925 * get confused by errant DMAs when rebooting. 2926 */ 2927 void 2928 bge_shutdown(xsc) 2929 void *xsc; 2930 { 2931 struct bge_softc *sc = (struct bge_softc *)xsc; 2932 2933 bge_stop(sc); 2934 bge_reset(sc); 2935 } 2936
Indexes created Mon Sep 22 05:09:51 GMT 2025