if_bge.c revision 1.160
1 /* $NetBSD: if_bge.c,v 1.160 2009/04/16 01:35:24 msaitoh Exp $ */ 2 3 /* 4 * Copyright (c) 2001 Wind River Systems 5 * Copyright (c) 1997, 1998, 1999, 2001 6 * Bill Paul <wpaul (at) windriver.com>. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Bill Paul. 19 * 4. Neither the name of the author nor the names of any co-contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 33 * THE POSSIBILITY OF SUCH DAMAGE. 34 * 35 * $FreeBSD: if_bge.c,v 1.13 2002/04/04 06:01:31 wpaul Exp $ 36 */ 37 38 /* 39 * Broadcom BCM570x family gigabit ethernet driver for NetBSD. 40 * 41 * NetBSD version by: 42 * 43 * Frank van der Linden <fvdl (at) wasabisystems.com> 44 * Jason Thorpe <thorpej (at) wasabisystems.com> 45 * Jonathan Stone <jonathan (at) dsg.stanford.edu> 46 * 47 * Originally written for FreeBSD by Bill Paul <wpaul (at) windriver.com> 48 * Senior Engineer, Wind River Systems 49 */ 50 51 /* 52 * The Broadcom BCM5700 is based on technology originally developed by 53 * Alteon Networks as part of the Tigon I and Tigon II gigabit ethernet 54 * MAC chips. The BCM5700, sometimes refered to as the Tigon III, has 55 * two on-board MIPS R4000 CPUs and can have as much as 16MB of external 56 * SSRAM. The BCM5700 supports TCP, UDP and IP checksum offload, jumbo 57 * frames, highly configurable RX filtering, and 16 RX and TX queues 58 * (which, along with RX filter rules, can be used for QOS applications). 59 * Other features, such as TCP segmentation, may be available as part 60 * of value-added firmware updates. Unlike the Tigon I and Tigon II, 61 * firmware images can be stored in hardware and need not be compiled 62 * into the driver. 63 * 64 * The BCM5700 supports the PCI v2.2 and PCI-X v1.0 standards, and will 65 * function in a 32-bit/64-bit 33/66MHz bus, or a 64-bit/133MHz bus. 66 * 67 * The BCM5701 is a single-chip solution incorporating both the BCM5700 68 * MAC and a BCM5401 10/100/1000 PHY. Unlike the BCM5700, the BCM5701 69 * does not support external SSRAM. 70 * 71 * Broadcom also produces a variation of the BCM5700 under the "Altima" 72 * brand name, which is functionally similar but lacks PCI-X support. 73 * 74 * Without external SSRAM, you can only have at most 4 TX rings, 75 * and the use of the mini RX ring is disabled. This seems to imply 76 * that these features are simply not available on the BCM5701. As a 77 * result, this driver does not implement any support for the mini RX 78 * ring. 79 */ 80 81 #include <sys/cdefs.h> 82 __KERNEL_RCSID(0, "$NetBSD: if_bge.c,v 1.160 2009/04/16 01:35:24 msaitoh Exp $"); 83 84 #include "bpfilter.h" 85 #include "vlan.h" 86 #include "rnd.h" 87 88 #include <sys/param.h> 89 #include <sys/systm.h> 90 #include <sys/callout.h> 91 #include <sys/sockio.h> 92 #include <sys/mbuf.h> 93 #include <sys/malloc.h> 94 #include <sys/kernel.h> 95 #include <sys/device.h> 96 #include <sys/socket.h> 97 #include <sys/sysctl.h> 98 99 #include <net/if.h> 100 #include <net/if_dl.h> 101 #include <net/if_media.h> 102 #include <net/if_ether.h> 103 104 #if NRND > 0 105 #include <sys/rnd.h> 106 #endif 107 108 #ifdef INET 109 #include <netinet/in.h> 110 #include <netinet/in_systm.h> 111 #include <netinet/in_var.h> 112 #include <netinet/ip.h> 113 #endif 114 115 /* Headers for TCP Segmentation Offload (TSO) */ 116 #include <netinet/in_systm.h> /* n_time for <netinet/ip.h>... */ 117 #include <netinet/in.h> /* ip_{src,dst}, for <netinet/ip.h> */ 118 #include <netinet/ip.h> /* for struct ip */ 119 #include <netinet/tcp.h> /* for struct tcphdr */ 120 121 122 #if NBPFILTER > 0 123 #include <net/bpf.h> 124 #endif 125 126 #include <dev/pci/pcireg.h> 127 #include <dev/pci/pcivar.h> 128 #include <dev/pci/pcidevs.h> 129 130 #include <dev/mii/mii.h> 131 #include <dev/mii/miivar.h> 132 #include <dev/mii/miidevs.h> 133 #include <dev/mii/brgphyreg.h> 134 135 #include <dev/pci/if_bgereg.h> 136 137 #include <uvm/uvm_extern.h> 138 139 #define ETHER_MIN_NOPAD (ETHER_MIN_LEN - ETHER_CRC_LEN) /* i.e., 60 */ 140 141 142 /* 143 * Tunable thresholds for rx-side bge interrupt mitigation. 144 */ 145 146 /* 147 * The pairs of values below were obtained from empirical measurement 148 * on bcm5700 rev B2; they ar designed to give roughly 1 receive 149 * interrupt for every N packets received, where N is, approximately, 150 * the second value (rx_max_bds) in each pair. The values are chosen 151 * such that moving from one pair to the succeeding pair was observed 152 * to roughly halve interrupt rate under sustained input packet load. 153 * The values were empirically chosen to avoid overflowing internal 154 * limits on the bcm5700: inreasing rx_ticks much beyond 600 155 * results in internal wrapping and higher interrupt rates. 156 * The limit of 46 frames was chosen to match NFS workloads. 157 * 158 * These values also work well on bcm5701, bcm5704C, and (less 159 * tested) bcm5703. On other chipsets, (including the Altima chip 160 * family), the larger values may overflow internal chip limits, 161 * leading to increasing interrupt rates rather than lower interrupt 162 * rates. 163 * 164 * Applications using heavy interrupt mitigation (interrupting every 165 * 32 or 46 frames) in both directions may need to increase the TCP 166 * windowsize to above 131072 bytes (e.g., to 199608 bytes) to sustain 167 * full link bandwidth, due to ACKs and window updates lingering 168 * in the RX queue during the 30-to-40-frame interrupt-mitigation window. 169 */ 170 static const struct bge_load_rx_thresh { 171 int rx_ticks; 172 int rx_max_bds; } 173 bge_rx_threshes[] = { 174 { 32, 2 }, 175 { 50, 4 }, 176 { 100, 8 }, 177 { 192, 16 }, 178 { 416, 32 }, 179 { 598, 46 } 180 }; 181 #define NBGE_RX_THRESH (sizeof(bge_rx_threshes) / sizeof(bge_rx_threshes[0])) 182 183 /* XXX patchable; should be sysctl'able */ 184 static int bge_auto_thresh = 1; 185 static int bge_rx_thresh_lvl; 186 187 static int bge_rxthresh_nodenum; 188 189 typedef int (*bge_eaddr_fcn_t)(struct bge_softc *, u_int8_t[]); 190 191 static int bge_probe(device_t, cfdata_t, void *); 192 static void bge_attach(device_t, device_t, void *); 193 static void bge_release_resources(struct bge_softc *); 194 static void bge_txeof(struct bge_softc *); 195 static void bge_rxeof(struct bge_softc *); 196 197 static int bge_get_eaddr_mem(struct bge_softc *, u_int8_t[]); 198 static int bge_get_eaddr_nvram(struct bge_softc *, u_int8_t[]); 199 static int bge_get_eaddr_eeprom(struct bge_softc *, u_int8_t[]); 200 static int bge_get_eaddr(struct bge_softc *, u_int8_t[]); 201 202 static void bge_tick(void *); 203 static void bge_stats_update(struct bge_softc *); 204 static int bge_encap(struct bge_softc *, struct mbuf *, u_int32_t *); 205 206 static int bge_intr(void *); 207 static void bge_start(struct ifnet *); 208 static int bge_ioctl(struct ifnet *, u_long, void *); 209 static int bge_init(struct ifnet *); 210 static void bge_stop(struct ifnet *, int); 211 static void bge_watchdog(struct ifnet *); 212 static int bge_ifmedia_upd(struct ifnet *); 213 static void bge_ifmedia_sts(struct ifnet *, struct ifmediareq *); 214 215 static void bge_setmulti(struct bge_softc *); 216 217 static void bge_handle_events(struct bge_softc *); 218 static int bge_alloc_jumbo_mem(struct bge_softc *); 219 #if 0 /* XXX */ 220 static void bge_free_jumbo_mem(struct bge_softc *); 221 #endif 222 static void *bge_jalloc(struct bge_softc *); 223 static void bge_jfree(struct mbuf *, void *, size_t, void *); 224 static int bge_newbuf_std(struct bge_softc *, int, struct mbuf *, 225 bus_dmamap_t); 226 static int bge_newbuf_jumbo(struct bge_softc *, int, struct mbuf *); 227 static int bge_init_rx_ring_std(struct bge_softc *); 228 static void bge_free_rx_ring_std(struct bge_softc *); 229 static int bge_init_rx_ring_jumbo(struct bge_softc *); 230 static void bge_free_rx_ring_jumbo(struct bge_softc *); 231 static void bge_free_tx_ring(struct bge_softc *); 232 static int bge_init_tx_ring(struct bge_softc *); 233 234 static int bge_chipinit(struct bge_softc *); 235 static int bge_blockinit(struct bge_softc *); 236 static int bge_setpowerstate(struct bge_softc *, int); 237 238 static void bge_reset(struct bge_softc *); 239 240 #define BGE_DEBUG 241 #ifdef BGE_DEBUG 242 #define DPRINTF(x) if (bgedebug) printf x 243 #define DPRINTFN(n,x) if (bgedebug >= (n)) printf x 244 #define BGE_TSO_PRINTF(x) do { if (bge_tso_debug) printf x ;} while (0) 245 int bgedebug = 0; 246 int bge_tso_debug = 0; 247 #else 248 #define DPRINTF(x) 249 #define DPRINTFN(n,x) 250 #define BGE_TSO_PRINTF(x) 251 #endif 252 253 #ifdef BGE_EVENT_COUNTERS 254 #define BGE_EVCNT_INCR(ev) (ev).ev_count++ 255 #define BGE_EVCNT_ADD(ev, val) (ev).ev_count += (val) 256 #define BGE_EVCNT_UPD(ev, val) (ev).ev_count = (val) 257 #else 258 #define BGE_EVCNT_INCR(ev) /* nothing */ 259 #define BGE_EVCNT_ADD(ev, val) /* nothing */ 260 #define BGE_EVCNT_UPD(ev, val) /* nothing */ 261 #endif 262 263 static const struct bge_product { 264 pci_vendor_id_t bp_vendor; 265 pci_product_id_t bp_product; 266 const char *bp_name; 267 } bge_products[] = { 268 /* 269 * The BCM5700 documentation seems to indicate that the hardware 270 * still has the Alteon vendor ID burned into it, though it 271 * should always be overridden by the value in the EEPROM. We'll 272 * check for it anyway. 273 */ 274 { PCI_VENDOR_ALTEON, 275 PCI_PRODUCT_ALTEON_BCM5700, 276 "Broadcom BCM5700 Gigabit Ethernet", 277 }, 278 { PCI_VENDOR_ALTEON, 279 PCI_PRODUCT_ALTEON_BCM5701, 280 "Broadcom BCM5701 Gigabit Ethernet", 281 }, 282 { PCI_VENDOR_ALTIMA, 283 PCI_PRODUCT_ALTIMA_AC1000, 284 "Altima AC1000 Gigabit Ethernet", 285 }, 286 { PCI_VENDOR_ALTIMA, 287 PCI_PRODUCT_ALTIMA_AC1001, 288 "Altima AC1001 Gigabit Ethernet", 289 }, 290 { PCI_VENDOR_ALTIMA, 291 PCI_PRODUCT_ALTIMA_AC9100, 292 "Altima AC9100 Gigabit Ethernet", 293 }, 294 { PCI_VENDOR_BROADCOM, 295 PCI_PRODUCT_BROADCOM_BCM5700, 296 "Broadcom BCM5700 Gigabit Ethernet", 297 }, 298 { PCI_VENDOR_BROADCOM, 299 PCI_PRODUCT_BROADCOM_BCM5701, 300 "Broadcom BCM5701 Gigabit Ethernet", 301 }, 302 { PCI_VENDOR_BROADCOM, 303 PCI_PRODUCT_BROADCOM_BCM5702, 304 "Broadcom BCM5702 Gigabit Ethernet", 305 }, 306 { PCI_VENDOR_BROADCOM, 307 PCI_PRODUCT_BROADCOM_BCM5702X, 308 "Broadcom BCM5702X Gigabit Ethernet" }, 309 { PCI_VENDOR_BROADCOM, 310 PCI_PRODUCT_BROADCOM_BCM5703, 311 "Broadcom BCM5703 Gigabit Ethernet", 312 }, 313 { PCI_VENDOR_BROADCOM, 314 PCI_PRODUCT_BROADCOM_BCM5703X, 315 "Broadcom BCM5703X Gigabit Ethernet", 316 }, 317 { PCI_VENDOR_BROADCOM, 318 PCI_PRODUCT_BROADCOM_BCM5703_ALT, 319 "Broadcom BCM5703 Gigabit Ethernet", 320 }, 321 { PCI_VENDOR_BROADCOM, 322 PCI_PRODUCT_BROADCOM_BCM5704C, 323 "Broadcom BCM5704C Dual Gigabit Ethernet", 324 }, 325 { PCI_VENDOR_BROADCOM, 326 PCI_PRODUCT_BROADCOM_BCM5704S, 327 "Broadcom BCM5704S Dual Gigabit Ethernet", 328 }, 329 { PCI_VENDOR_BROADCOM, 330 PCI_PRODUCT_BROADCOM_BCM5705, 331 "Broadcom BCM5705 Gigabit Ethernet", 332 }, 333 { PCI_VENDOR_BROADCOM, 334 PCI_PRODUCT_BROADCOM_BCM5705K, 335 "Broadcom BCM5705K Gigabit Ethernet", 336 }, 337 { PCI_VENDOR_BROADCOM, 338 PCI_PRODUCT_BROADCOM_BCM5705M, 339 "Broadcom BCM5705M Gigabit Ethernet", 340 }, 341 { PCI_VENDOR_BROADCOM, 342 PCI_PRODUCT_BROADCOM_BCM5705M_ALT, 343 "Broadcom BCM5705M Gigabit Ethernet", 344 }, 345 { PCI_VENDOR_BROADCOM, 346 PCI_PRODUCT_BROADCOM_BCM5714, 347 "Broadcom BCM5714/5715 Gigabit Ethernet", 348 }, 349 { PCI_VENDOR_BROADCOM, 350 PCI_PRODUCT_BROADCOM_BCM5715, 351 "Broadcom BCM5714/5715 Gigabit Ethernet", 352 }, 353 { PCI_VENDOR_BROADCOM, 354 PCI_PRODUCT_BROADCOM_BCM5789, 355 "Broadcom BCM5789 Gigabit Ethernet", 356 }, 357 { PCI_VENDOR_BROADCOM, 358 PCI_PRODUCT_BROADCOM_BCM5721, 359 "Broadcom BCM5721 Gigabit Ethernet", 360 }, 361 { PCI_VENDOR_BROADCOM, 362 PCI_PRODUCT_BROADCOM_BCM5722, 363 "Broadcom BCM5722 Gigabit Ethernet", 364 }, 365 { PCI_VENDOR_BROADCOM, 366 PCI_PRODUCT_BROADCOM_BCM5750, 367 "Broadcom BCM5750 Gigabit Ethernet", 368 }, 369 { PCI_VENDOR_BROADCOM, 370 PCI_PRODUCT_BROADCOM_BCM5750M, 371 "Broadcom BCM5750M Gigabit Ethernet", 372 }, 373 { PCI_VENDOR_BROADCOM, 374 PCI_PRODUCT_BROADCOM_BCM5751, 375 "Broadcom BCM5751 Gigabit Ethernet", 376 }, 377 { PCI_VENDOR_BROADCOM, 378 PCI_PRODUCT_BROADCOM_BCM5751M, 379 "Broadcom BCM5751M Gigabit Ethernet", 380 }, 381 { PCI_VENDOR_BROADCOM, 382 PCI_PRODUCT_BROADCOM_BCM5752, 383 "Broadcom BCM5752 Gigabit Ethernet", 384 }, 385 { PCI_VENDOR_BROADCOM, 386 PCI_PRODUCT_BROADCOM_BCM5752M, 387 "Broadcom BCM5752M Gigabit Ethernet", 388 }, 389 { PCI_VENDOR_BROADCOM, 390 PCI_PRODUCT_BROADCOM_BCM5753, 391 "Broadcom BCM5753 Gigabit Ethernet", 392 }, 393 { PCI_VENDOR_BROADCOM, 394 PCI_PRODUCT_BROADCOM_BCM5753M, 395 "Broadcom BCM5753M Gigabit Ethernet", 396 }, 397 { PCI_VENDOR_BROADCOM, 398 PCI_PRODUCT_BROADCOM_BCM5754, 399 "Broadcom BCM5754 Gigabit Ethernet", 400 }, 401 { PCI_VENDOR_BROADCOM, 402 PCI_PRODUCT_BROADCOM_BCM5754M, 403 "Broadcom BCM5754M Gigabit Ethernet", 404 }, 405 { PCI_VENDOR_BROADCOM, 406 PCI_PRODUCT_BROADCOM_BCM5755, 407 "Broadcom BCM5755 Gigabit Ethernet", 408 }, 409 { PCI_VENDOR_BROADCOM, 410 PCI_PRODUCT_BROADCOM_BCM5755M, 411 "Broadcom BCM5755M Gigabit Ethernet", 412 }, 413 { PCI_VENDOR_BROADCOM, 414 PCI_PRODUCT_BROADCOM_BCM5780, 415 "Broadcom BCM5780 Gigabit Ethernet", 416 }, 417 { PCI_VENDOR_BROADCOM, 418 PCI_PRODUCT_BROADCOM_BCM5780S, 419 "Broadcom BCM5780S Gigabit Ethernet", 420 }, 421 { PCI_VENDOR_BROADCOM, 422 PCI_PRODUCT_BROADCOM_BCM5782, 423 "Broadcom BCM5782 Gigabit Ethernet", 424 }, 425 { PCI_VENDOR_BROADCOM, 426 PCI_PRODUCT_BROADCOM_BCM5786, 427 "Broadcom BCM5786 Gigabit Ethernet", 428 }, 429 { PCI_VENDOR_BROADCOM, 430 PCI_PRODUCT_BROADCOM_BCM5787, 431 "Broadcom BCM5787 Gigabit Ethernet", 432 }, 433 { PCI_VENDOR_BROADCOM, 434 PCI_PRODUCT_BROADCOM_BCM5787M, 435 "Broadcom BCM5787M Gigabit Ethernet", 436 }, 437 { PCI_VENDOR_BROADCOM, 438 PCI_PRODUCT_BROADCOM_BCM5788, 439 "Broadcom BCM5788 Gigabit Ethernet", 440 }, 441 { PCI_VENDOR_BROADCOM, 442 PCI_PRODUCT_BROADCOM_BCM5789, 443 "Broadcom BCM5789 Gigabit Ethernet", 444 }, 445 { PCI_VENDOR_BROADCOM, 446 PCI_PRODUCT_BROADCOM_BCM5901, 447 "Broadcom BCM5901 Fast Ethernet", 448 }, 449 { PCI_VENDOR_BROADCOM, 450 PCI_PRODUCT_BROADCOM_BCM5901A2, 451 "Broadcom BCM5901A2 Fast Ethernet", 452 }, 453 { PCI_VENDOR_SCHNEIDERKOCH, 454 PCI_PRODUCT_SCHNEIDERKOCH_SK_9DX1, 455 "SysKonnect SK-9Dx1 Gigabit Ethernet", 456 }, 457 { PCI_VENDOR_3COM, 458 PCI_PRODUCT_3COM_3C996, 459 "3Com 3c996 Gigabit Ethernet", 460 }, 461 { PCI_VENDOR_BROADCOM, 462 PCI_PRODUCT_BROADCOM_BCM5906, 463 "Broadcom BCM5906 Fast Ethernet", 464 }, 465 { PCI_VENDOR_BROADCOM, 466 PCI_PRODUCT_BROADCOM_BCM5906M, 467 "Broadcom BCM5906M Fast Ethernet", 468 }, 469 { 0, 470 0, 471 NULL }, 472 }; 473 474 /* 475 * XXX: how to handle variants based on 5750 and derivatives: 476 * 5750 5751, 5721, possibly 5714, 5752, and 5708?, which 477 * in general behave like a 5705, except with additional quirks. 478 * This driver's current handling of the 5721 is wrong; 479 * how we map ASIC revision to "quirks" needs more thought. 480 * (defined here until the thought is done). 481 */ 482 #define BGE_IS_5714_FAMILY(sc) \ 483 (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5714_A0 || \ 484 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5780 || \ 485 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5714 ) 486 487 #define BGE_IS_5750_OR_BEYOND(sc) \ 488 (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5750 || \ 489 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5752 || \ 490 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5755 || \ 491 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5787 || \ 492 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906 || \ 493 BGE_IS_5714_FAMILY(sc) ) 494 495 #define BGE_IS_5705_OR_BEYOND(sc) \ 496 (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5705 || \ 497 (BGE_IS_5750_OR_BEYOND(sc))) 498 499 static const struct bge_revision { 500 uint32_t br_chipid; 501 const char *br_name; 502 } bge_revisions[] = { 503 { BGE_CHIPID_BCM5700_A0, "BCM5700 A0" }, 504 { BGE_CHIPID_BCM5700_A1, "BCM5700 A1" }, 505 { BGE_CHIPID_BCM5700_B0, "BCM5700 B0" }, 506 { BGE_CHIPID_BCM5700_B1, "BCM5700 B1" }, 507 { BGE_CHIPID_BCM5700_B2, "BCM5700 B2" }, 508 { BGE_CHIPID_BCM5700_B3, "BCM5700 B3" }, 509 /* This is treated like a BCM5700 Bx */ 510 { BGE_CHIPID_BCM5700_ALTIMA, "BCM5700 Altima" }, 511 { BGE_CHIPID_BCM5700_C0, "BCM5700 C0" }, 512 { BGE_CHIPID_BCM5701_A0, "BCM5701 A0" }, 513 { BGE_CHIPID_BCM5701_B0, "BCM5701 B0" }, 514 { BGE_CHIPID_BCM5701_B2, "BCM5701 B2" }, 515 { BGE_CHIPID_BCM5701_B5, "BCM5701 B5" }, 516 { BGE_CHIPID_BCM5703_A0, "BCM5703 A0" }, 517 { BGE_CHIPID_BCM5703_A1, "BCM5703 A1" }, 518 { BGE_CHIPID_BCM5703_A2, "BCM5703 A2" }, 519 { BGE_CHIPID_BCM5703_A3, "BCM5703 A3" }, 520 { BGE_CHIPID_BCM5703_B0, "BCM5703 B0" }, 521 { BGE_CHIPID_BCM5704_A0, "BCM5704 A0" }, 522 { BGE_CHIPID_BCM5704_A1, "BCM5704 A1" }, 523 { BGE_CHIPID_BCM5704_A2, "BCM5704 A2" }, 524 { BGE_CHIPID_BCM5704_A3, "BCM5704 A3" }, 525 { BGE_CHIPID_BCM5704_B0, "BCM5704 B0" }, 526 { BGE_CHIPID_BCM5705_A0, "BCM5705 A0" }, 527 { BGE_CHIPID_BCM5705_A1, "BCM5705 A1" }, 528 { BGE_CHIPID_BCM5705_A2, "BCM5705 A2" }, 529 { BGE_CHIPID_BCM5705_A3, "BCM5705 A3" }, 530 { BGE_CHIPID_BCM5750_A0, "BCM5750 A0" }, 531 { BGE_CHIPID_BCM5750_A1, "BCM5750 A1" }, 532 { BGE_CHIPID_BCM5751_A1, "BCM5751 A1" }, 533 { BGE_CHIPID_BCM5752_A0, "BCM5752 A0" }, 534 { BGE_CHIPID_BCM5752_A1, "BCM5752 A1" }, 535 { BGE_CHIPID_BCM5752_A2, "BCM5752 A2" }, 536 { BGE_CHIPID_BCM5714_A0, "BCM5714 A0" }, 537 { BGE_CHIPID_BCM5714_B0, "BCM5714 B0" }, 538 { BGE_CHIPID_BCM5714_B3, "BCM5714 B3" }, 539 { BGE_CHIPID_BCM5715_A0, "BCM5715 A0" }, 540 { BGE_CHIPID_BCM5715_A1, "BCM5715 A1" }, 541 { BGE_CHIPID_BCM5715_A3, "BCM5715 A3" }, 542 { BGE_CHIPID_BCM5755_A0, "BCM5755 A0" }, 543 { BGE_CHIPID_BCM5755_A1, "BCM5755 A1" }, 544 { BGE_CHIPID_BCM5755_A2, "BCM5755 A2" }, 545 { BGE_CHIPID_BCM5755_C0, "BCM5755 C0" }, 546 { BGE_CHIPID_BCM5787_A0, "BCM5754/5787 A0" }, 547 { BGE_CHIPID_BCM5787_A1, "BCM5754/5787 A1" }, 548 { BGE_CHIPID_BCM5787_A2, "BCM5754/5787 A2" }, 549 { 0, NULL } 550 }; 551 552 /* 553 * Some defaults for major revisions, so that newer steppings 554 * that we don't know about have a shot at working. 555 */ 556 static const struct bge_revision bge_majorrevs[] = { 557 { BGE_ASICREV_BCM5700, "unknown BCM5700" }, 558 { BGE_ASICREV_BCM5701, "unknown BCM5701" }, 559 { BGE_ASICREV_BCM5703, "unknown BCM5703" }, 560 { BGE_ASICREV_BCM5704, "unknown BCM5704" }, 561 { BGE_ASICREV_BCM5705, "unknown BCM5705" }, 562 { BGE_ASICREV_BCM5750, "unknown BCM575x family" }, 563 { BGE_ASICREV_BCM5714_A0, "unknown BCM5714" }, 564 { BGE_ASICREV_BCM5714, "unknown BCM5714" }, 565 { BGE_ASICREV_BCM5752, "unknown BCM5752 family" }, 566 { BGE_ASICREV_BCM5755, "unknown BCM5755" }, 567 { BGE_ASICREV_BCM5780, "unknown BCM5780" }, 568 { BGE_ASICREV_BCM5787, "unknown BCM5787" }, 569 { BGE_ASICREV_BCM5906, "unknown BCM5906" }, 570 { 0, NULL } 571 }; 572 573 CFATTACH_DECL_NEW(bge, sizeof(struct bge_softc), 574 bge_probe, bge_attach, NULL, NULL); 575 576 static u_int32_t 577 bge_readmem_ind(struct bge_softc *sc, int off) 578 { 579 pcireg_t val; 580 581 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_BASEADDR, off); 582 val = pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_DATA); 583 return val; 584 } 585 586 static void 587 bge_writemem_ind(struct bge_softc *sc, int off, int val) 588 { 589 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_BASEADDR, off); 590 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_DATA, val); 591 } 592 593 #ifdef notdef 594 static u_int32_t 595 bge_readreg_ind(struct bge_softc *sc, int off) 596 { 597 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_REG_BASEADDR, off); 598 return (pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_REG_DATA)); 599 } 600 #endif 601 602 static void 603 bge_writereg_ind(struct bge_softc *sc, int off, int val) 604 { 605 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_REG_BASEADDR, off); 606 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_REG_DATA, val); 607 } 608 609 static void 610 bge_writemem_direct(struct bge_softc *sc, int off, int val) 611 { 612 CSR_WRITE_4(sc, off, val); 613 } 614 615 static void 616 bge_writembx(struct bge_softc *sc, int off, int val) 617 { 618 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 619 off += BGE_LPMBX_IRQ0_HI - BGE_MBX_IRQ0_HI; 620 621 CSR_WRITE_4(sc, off, val); 622 } 623 624 static u_int8_t 625 bge_nvram_getbyte(struct bge_softc *sc, int addr, u_int8_t *dest) 626 { 627 u_int32_t access, byte = 0; 628 int i; 629 630 /* Lock. */ 631 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_SET1); 632 for (i = 0; i < 8000; i++) { 633 if (CSR_READ_4(sc, BGE_NVRAM_SWARB) & BGE_NVRAMSWARB_GNT1) 634 break; 635 DELAY(20); 636 } 637 if (i == 8000) 638 return (1); 639 640 /* Enable access. */ 641 access = CSR_READ_4(sc, BGE_NVRAM_ACCESS); 642 CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access | BGE_NVRAMACC_ENABLE); 643 644 CSR_WRITE_4(sc, BGE_NVRAM_ADDR, addr & 0xfffffffc); 645 CSR_WRITE_4(sc, BGE_NVRAM_CMD, BGE_NVRAM_READCMD); 646 for (i = 0; i < BGE_TIMEOUT * 10; i++) { 647 DELAY(10); 648 if (CSR_READ_4(sc, BGE_NVRAM_CMD) & BGE_NVRAMCMD_DONE) { 649 DELAY(10); 650 break; 651 } 652 } 653 654 if (i == BGE_TIMEOUT * 10) { 655 aprint_error_dev(sc->bge_dev, "nvram read timed out\n"); 656 return (1); 657 } 658 659 /* Get result. */ 660 byte = CSR_READ_4(sc, BGE_NVRAM_RDDATA); 661 662 *dest = (bswap32(byte) >> ((addr % 4) * 8)) & 0xFF; 663 664 /* Disable access. */ 665 CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access); 666 667 /* Unlock. */ 668 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_CLR1); 669 CSR_READ_4(sc, BGE_NVRAM_SWARB); 670 671 return (0); 672 } 673 674 /* 675 * Read a sequence of bytes from NVRAM. 676 */ 677 static int 678 bge_read_nvram(struct bge_softc *sc, u_int8_t *dest, int off, int cnt) 679 { 680 int err = 0, i; 681 u_int8_t byte = 0; 682 683 if (BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5906) 684 return (1); 685 686 for (i = 0; i < cnt; i++) { 687 err = bge_nvram_getbyte(sc, off + i, &byte); 688 if (err) 689 break; 690 *(dest + i) = byte; 691 } 692 693 return (err ? 1 : 0); 694 } 695 696 /* 697 * Read a byte of data stored in the EEPROM at address 'addr.' The 698 * BCM570x supports both the traditional bitbang interface and an 699 * auto access interface for reading the EEPROM. We use the auto 700 * access method. 701 */ 702 static u_int8_t 703 bge_eeprom_getbyte(struct bge_softc *sc, int addr, u_int8_t *dest) 704 { 705 int i; 706 u_int32_t byte = 0; 707 708 /* 709 * Enable use of auto EEPROM access so we can avoid 710 * having to use the bitbang method. 711 */ 712 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM); 713 714 /* Reset the EEPROM, load the clock period. */ 715 CSR_WRITE_4(sc, BGE_EE_ADDR, 716 BGE_EEADDR_RESET|BGE_EEHALFCLK(BGE_HALFCLK_384SCL)); 717 DELAY(20); 718 719 /* Issue the read EEPROM command. */ 720 CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr); 721 722 /* Wait for completion */ 723 for(i = 0; i < BGE_TIMEOUT * 10; i++) { 724 DELAY(10); 725 if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE) 726 break; 727 } 728 729 if (i == BGE_TIMEOUT) { 730 aprint_error_dev(sc->bge_dev, "eeprom read timed out\n"); 731 return (0); 732 } 733 734 /* Get result. */ 735 byte = CSR_READ_4(sc, BGE_EE_DATA); 736 737 *dest = (byte >> ((addr % 4) * 8)) & 0xFF; 738 739 return (0); 740 } 741 742 /* 743 * Read a sequence of bytes from the EEPROM. 744 */ 745 static int 746 bge_read_eeprom(struct bge_softc *sc, void *destv, int off, int cnt) 747 { 748 int err = 0, i; 749 u_int8_t byte = 0; 750 char *dest = destv; 751 752 for (i = 0; i < cnt; i++) { 753 err = bge_eeprom_getbyte(sc, off + i, &byte); 754 if (err) 755 break; 756 *(dest + i) = byte; 757 } 758 759 return (err ? 1 : 0); 760 } 761 762 static int 763 bge_miibus_readreg(device_t dev, int phy, int reg) 764 { 765 struct bge_softc *sc = device_private(dev); 766 u_int32_t val; 767 u_int32_t saved_autopoll; 768 int i; 769 770 /* 771 * Broadcom's own driver always assumes the internal 772 * PHY is at GMII address 1. On some chips, the PHY responds 773 * to accesses at all addresses, which could cause us to 774 * bogusly attach the PHY 32 times at probe type. Always 775 * restricting the lookup to address 1 is simpler than 776 * trying to figure out which chips revisions should be 777 * special-cased. 778 */ 779 if (phy != 1) 780 return (0); 781 782 /* Reading with autopolling on may trigger PCI errors */ 783 saved_autopoll = CSR_READ_4(sc, BGE_MI_MODE); 784 if (saved_autopoll & BGE_MIMODE_AUTOPOLL) { 785 CSR_WRITE_4(sc, BGE_MI_MODE, 786 saved_autopoll &~ BGE_MIMODE_AUTOPOLL); 787 DELAY(40); 788 } 789 790 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_READ|BGE_MICOMM_BUSY| 791 BGE_MIPHY(phy)|BGE_MIREG(reg)); 792 793 for (i = 0; i < BGE_TIMEOUT; i++) { 794 val = CSR_READ_4(sc, BGE_MI_COMM); 795 if (!(val & BGE_MICOMM_BUSY)) 796 break; 797 delay(10); 798 } 799 800 if (i == BGE_TIMEOUT) { 801 aprint_error_dev(sc->bge_dev, "PHY read timed out\n"); 802 val = 0; 803 goto done; 804 } 805 806 val = CSR_READ_4(sc, BGE_MI_COMM); 807 808 done: 809 if (saved_autopoll & BGE_MIMODE_AUTOPOLL) { 810 CSR_WRITE_4(sc, BGE_MI_MODE, saved_autopoll); 811 DELAY(40); 812 } 813 814 if (val & BGE_MICOMM_READFAIL) 815 return (0); 816 817 return (val & 0xFFFF); 818 } 819 820 static void 821 bge_miibus_writereg(device_t dev, int phy, int reg, int val) 822 { 823 struct bge_softc *sc = device_private(dev); 824 u_int32_t saved_autopoll; 825 int i; 826 827 if (phy!=1) { 828 return; 829 } 830 831 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906 && 832 (reg == BRGPHY_MII_1000CTL || reg == BRGPHY_MII_AUXCTL)) { 833 return; 834 } 835 836 /* Touching the PHY while autopolling is on may trigger PCI errors */ 837 saved_autopoll = CSR_READ_4(sc, BGE_MI_MODE); 838 if (saved_autopoll & BGE_MIMODE_AUTOPOLL) { 839 delay(40); 840 CSR_WRITE_4(sc, BGE_MI_MODE, 841 saved_autopoll & (~BGE_MIMODE_AUTOPOLL)); 842 delay(10); /* 40 usec is supposed to be adequate */ 843 } 844 845 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_WRITE|BGE_MICOMM_BUSY| 846 BGE_MIPHY(phy)|BGE_MIREG(reg)|val); 847 848 for (i = 0; i < BGE_TIMEOUT; i++) { 849 delay(10); 850 if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY)) { 851 delay(5); 852 CSR_READ_4(sc, BGE_MI_COMM); 853 break; 854 } 855 } 856 857 if (saved_autopoll & BGE_MIMODE_AUTOPOLL) { 858 CSR_WRITE_4(sc, BGE_MI_MODE, saved_autopoll); 859 delay(40); 860 } 861 862 if (i == BGE_TIMEOUT) 863 aprint_error_dev(sc->bge_dev, "PHY read timed out\n"); 864 } 865 866 static void 867 bge_miibus_statchg(device_t dev) 868 { 869 struct bge_softc *sc = device_private(dev); 870 struct mii_data *mii = &sc->bge_mii; 871 872 /* 873 * Get flow control negotiation result. 874 */ 875 if (IFM_SUBTYPE(mii->mii_media.ifm_cur->ifm_media) == IFM_AUTO && 876 (mii->mii_media_active & IFM_ETH_FMASK) != sc->bge_flowflags) { 877 sc->bge_flowflags = mii->mii_media_active & IFM_ETH_FMASK; 878 mii->mii_media_active &= ~IFM_ETH_FMASK; 879 } 880 881 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_PORTMODE); 882 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) { 883 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_GMII); 884 } else 885 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_MII); 886 887 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) 888 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX); 889 else 890 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX); 891 892 /* 893 * 802.3x flow control 894 */ 895 if (sc->bge_flowflags & IFM_ETH_RXPAUSE) 896 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_FLOWCTL_ENABLE); 897 else 898 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_FLOWCTL_ENABLE); 899 900 if (sc->bge_flowflags & IFM_ETH_TXPAUSE) 901 BGE_SETBIT(sc, BGE_TX_MODE, BGE_TXMODE_FLOWCTL_ENABLE); 902 else 903 BGE_CLRBIT(sc, BGE_TX_MODE, BGE_TXMODE_FLOWCTL_ENABLE); 904 } 905 906 /* 907 * Update rx threshold levels to values in a particular slot 908 * of the interrupt-mitigation table bge_rx_threshes. 909 */ 910 static void 911 bge_set_thresh(struct ifnet *ifp, int lvl) 912 { 913 struct bge_softc *sc = ifp->if_softc; 914 int s; 915 916 /* For now, just save the new Rx-intr thresholds and record 917 * that a threshold update is pending. Updating the hardware 918 * registers here (even at splhigh()) is observed to 919 * occasionaly cause glitches where Rx-interrupts are not 920 * honoured for up to 10 seconds. jonathan (at) NetBSD.org, 2003-04-05 921 */ 922 s = splnet(); 923 sc->bge_rx_coal_ticks = bge_rx_threshes[lvl].rx_ticks; 924 sc->bge_rx_max_coal_bds = bge_rx_threshes[lvl].rx_max_bds; 925 sc->bge_pending_rxintr_change = 1; 926 splx(s); 927 928 return; 929 } 930 931 932 /* 933 * Update Rx thresholds of all bge devices 934 */ 935 static void 936 bge_update_all_threshes(int lvl) 937 { 938 struct ifnet *ifp; 939 const char * const namebuf = "bge"; 940 int namelen; 941 942 if (lvl < 0) 943 lvl = 0; 944 else if( lvl >= NBGE_RX_THRESH) 945 lvl = NBGE_RX_THRESH - 1; 946 947 namelen = strlen(namebuf); 948 /* 949 * Now search all the interfaces for this name/number 950 */ 951 IFNET_FOREACH(ifp) { 952 if (strncmp(ifp->if_xname, namebuf, namelen) != 0) 953 continue; 954 /* We got a match: update if doing auto-threshold-tuning */ 955 if (bge_auto_thresh) 956 bge_set_thresh(ifp, lvl); 957 } 958 } 959 960 /* 961 * Handle events that have triggered interrupts. 962 */ 963 static void 964 bge_handle_events(struct bge_softc *sc) 965 { 966 967 return; 968 } 969 970 /* 971 * Memory management for jumbo frames. 972 */ 973 974 static int 975 bge_alloc_jumbo_mem(struct bge_softc *sc) 976 { 977 char *ptr, *kva; 978 bus_dma_segment_t seg; 979 int i, rseg, state, error; 980 struct bge_jpool_entry *entry; 981 982 state = error = 0; 983 984 /* Grab a big chunk o' storage. */ 985 if (bus_dmamem_alloc(sc->bge_dmatag, BGE_JMEM, PAGE_SIZE, 0, 986 &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 987 aprint_error_dev(sc->bge_dev, "can't alloc rx buffers\n"); 988 return ENOBUFS; 989 } 990 991 state = 1; 992 if (bus_dmamem_map(sc->bge_dmatag, &seg, rseg, BGE_JMEM, (void **)&kva, 993 BUS_DMA_NOWAIT)) { 994 aprint_error_dev(sc->bge_dev, 995 "can't map DMA buffers (%d bytes)\n", (int)BGE_JMEM); 996 error = ENOBUFS; 997 goto out; 998 } 999 1000 state = 2; 1001 if (bus_dmamap_create(sc->bge_dmatag, BGE_JMEM, 1, BGE_JMEM, 0, 1002 BUS_DMA_NOWAIT, &sc->bge_cdata.bge_rx_jumbo_map)) { 1003 aprint_error_dev(sc->bge_dev, "can't create DMA map\n"); 1004 error = ENOBUFS; 1005 goto out; 1006 } 1007 1008 state = 3; 1009 if (bus_dmamap_load(sc->bge_dmatag, sc->bge_cdata.bge_rx_jumbo_map, 1010 kva, BGE_JMEM, NULL, BUS_DMA_NOWAIT)) { 1011 aprint_error_dev(sc->bge_dev, "can't load DMA map\n"); 1012 error = ENOBUFS; 1013 goto out; 1014 } 1015 1016 state = 4; 1017 sc->bge_cdata.bge_jumbo_buf = (void *)kva; 1018 DPRINTFN(1,("bge_jumbo_buf = %p\n", sc->bge_cdata.bge_jumbo_buf)); 1019 1020 SLIST_INIT(&sc->bge_jfree_listhead); 1021 SLIST_INIT(&sc->bge_jinuse_listhead); 1022 1023 /* 1024 * Now divide it up into 9K pieces and save the addresses 1025 * in an array. 1026 */ 1027 ptr = sc->bge_cdata.bge_jumbo_buf; 1028 for (i = 0; i < BGE_JSLOTS; i++) { 1029 sc->bge_cdata.bge_jslots[i] = ptr; 1030 ptr += BGE_JLEN; 1031 entry = malloc(sizeof(struct bge_jpool_entry), 1032 M_DEVBUF, M_NOWAIT); 1033 if (entry == NULL) { 1034 aprint_error_dev(sc->bge_dev, 1035 "no memory for jumbo buffer queue!\n"); 1036 error = ENOBUFS; 1037 goto out; 1038 } 1039 entry->slot = i; 1040 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, 1041 entry, jpool_entries); 1042 } 1043 out: 1044 if (error != 0) { 1045 switch (state) { 1046 case 4: 1047 bus_dmamap_unload(sc->bge_dmatag, 1048 sc->bge_cdata.bge_rx_jumbo_map); 1049 case 3: 1050 bus_dmamap_destroy(sc->bge_dmatag, 1051 sc->bge_cdata.bge_rx_jumbo_map); 1052 case 2: 1053 bus_dmamem_unmap(sc->bge_dmatag, kva, BGE_JMEM); 1054 case 1: 1055 bus_dmamem_free(sc->bge_dmatag, &seg, rseg); 1056 break; 1057 default: 1058 break; 1059 } 1060 } 1061 1062 return error; 1063 } 1064 1065 /* 1066 * Allocate a jumbo buffer. 1067 */ 1068 static void * 1069 bge_jalloc(struct bge_softc *sc) 1070 { 1071 struct bge_jpool_entry *entry; 1072 1073 entry = SLIST_FIRST(&sc->bge_jfree_listhead); 1074 1075 if (entry == NULL) { 1076 aprint_error_dev(sc->bge_dev, "no free jumbo buffers\n"); 1077 return (NULL); 1078 } 1079 1080 SLIST_REMOVE_HEAD(&sc->bge_jfree_listhead, jpool_entries); 1081 SLIST_INSERT_HEAD(&sc->bge_jinuse_listhead, entry, jpool_entries); 1082 return (sc->bge_cdata.bge_jslots[entry->slot]); 1083 } 1084 1085 /* 1086 * Release a jumbo buffer. 1087 */ 1088 static void 1089 bge_jfree(struct mbuf *m, void *buf, size_t size, void *arg) 1090 { 1091 struct bge_jpool_entry *entry; 1092 struct bge_softc *sc; 1093 int i, s; 1094 1095 /* Extract the softc struct pointer. */ 1096 sc = (struct bge_softc *)arg; 1097 1098 if (sc == NULL) 1099 panic("bge_jfree: can't find softc pointer!"); 1100 1101 /* calculate the slot this buffer belongs to */ 1102 1103 i = ((char *)buf 1104 - (char *)sc->bge_cdata.bge_jumbo_buf) / BGE_JLEN; 1105 1106 if ((i < 0) || (i >= BGE_JSLOTS)) 1107 panic("bge_jfree: asked to free buffer that we don't manage!"); 1108 1109 s = splvm(); 1110 entry = SLIST_FIRST(&sc->bge_jinuse_listhead); 1111 if (entry == NULL) 1112 panic("bge_jfree: buffer not in use!"); 1113 entry->slot = i; 1114 SLIST_REMOVE_HEAD(&sc->bge_jinuse_listhead, jpool_entries); 1115 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, entry, jpool_entries); 1116 1117 if (__predict_true(m != NULL)) 1118 pool_cache_put(mb_cache, m); 1119 splx(s); 1120 } 1121 1122 1123 /* 1124 * Intialize a standard receive ring descriptor. 1125 */ 1126 static int 1127 bge_newbuf_std(struct bge_softc *sc, int i, struct mbuf *m, bus_dmamap_t dmamap) 1128 { 1129 struct mbuf *m_new = NULL; 1130 struct bge_rx_bd *r; 1131 int error; 1132 1133 if (dmamap == NULL) { 1134 error = bus_dmamap_create(sc->bge_dmatag, MCLBYTES, 1, 1135 MCLBYTES, 0, BUS_DMA_NOWAIT, &dmamap); 1136 if (error != 0) 1137 return error; 1138 } 1139 1140 sc->bge_cdata.bge_rx_std_map[i] = dmamap; 1141 1142 if (m == NULL) { 1143 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1144 if (m_new == NULL) 1145 return (ENOBUFS); 1146 1147 MCLGET(m_new, M_DONTWAIT); 1148 if (!(m_new->m_flags & M_EXT)) { 1149 m_freem(m_new); 1150 return (ENOBUFS); 1151 } 1152 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1153 1154 } else { 1155 m_new = m; 1156 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1157 m_new->m_data = m_new->m_ext.ext_buf; 1158 } 1159 if (!(sc->bge_flags & BGE_RX_ALIGNBUG)) 1160 m_adj(m_new, ETHER_ALIGN); 1161 if (bus_dmamap_load_mbuf(sc->bge_dmatag, dmamap, m_new, 1162 BUS_DMA_READ|BUS_DMA_NOWAIT)) 1163 return (ENOBUFS); 1164 bus_dmamap_sync(sc->bge_dmatag, dmamap, 0, dmamap->dm_mapsize, 1165 BUS_DMASYNC_PREREAD); 1166 1167 sc->bge_cdata.bge_rx_std_chain[i] = m_new; 1168 r = &sc->bge_rdata->bge_rx_std_ring[i]; 1169 bge_set_hostaddr(&r->bge_addr, 1170 dmamap->dm_segs[0].ds_addr); 1171 r->bge_flags = BGE_RXBDFLAG_END; 1172 r->bge_len = m_new->m_len; 1173 r->bge_idx = i; 1174 1175 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 1176 offsetof(struct bge_ring_data, bge_rx_std_ring) + 1177 i * sizeof (struct bge_rx_bd), 1178 sizeof (struct bge_rx_bd), 1179 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1180 1181 return (0); 1182 } 1183 1184 /* 1185 * Initialize a jumbo receive ring descriptor. This allocates 1186 * a jumbo buffer from the pool managed internally by the driver. 1187 */ 1188 static int 1189 bge_newbuf_jumbo(struct bge_softc *sc, int i, struct mbuf *m) 1190 { 1191 struct mbuf *m_new = NULL; 1192 struct bge_rx_bd *r; 1193 void *buf = NULL; 1194 1195 if (m == NULL) { 1196 1197 /* Allocate the mbuf. */ 1198 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1199 if (m_new == NULL) 1200 return (ENOBUFS); 1201 1202 /* Allocate the jumbo buffer */ 1203 buf = bge_jalloc(sc); 1204 if (buf == NULL) { 1205 m_freem(m_new); 1206 aprint_error_dev(sc->bge_dev, 1207 "jumbo allocation failed -- packet dropped!\n"); 1208 return (ENOBUFS); 1209 } 1210 1211 /* Attach the buffer to the mbuf. */ 1212 m_new->m_len = m_new->m_pkthdr.len = BGE_JUMBO_FRAMELEN; 1213 MEXTADD(m_new, buf, BGE_JUMBO_FRAMELEN, M_DEVBUF, 1214 bge_jfree, sc); 1215 m_new->m_flags |= M_EXT_RW; 1216 } else { 1217 m_new = m; 1218 buf = m_new->m_data = m_new->m_ext.ext_buf; 1219 m_new->m_ext.ext_size = BGE_JUMBO_FRAMELEN; 1220 } 1221 if (!(sc->bge_flags & BGE_RX_ALIGNBUG)) 1222 m_adj(m_new, ETHER_ALIGN); 1223 bus_dmamap_sync(sc->bge_dmatag, sc->bge_cdata.bge_rx_jumbo_map, 1224 mtod(m_new, char *) - (char *)sc->bge_cdata.bge_jumbo_buf, BGE_JLEN, 1225 BUS_DMASYNC_PREREAD); 1226 /* Set up the descriptor. */ 1227 r = &sc->bge_rdata->bge_rx_jumbo_ring[i]; 1228 sc->bge_cdata.bge_rx_jumbo_chain[i] = m_new; 1229 bge_set_hostaddr(&r->bge_addr, BGE_JUMBO_DMA_ADDR(sc, m_new)); 1230 r->bge_flags = BGE_RXBDFLAG_END|BGE_RXBDFLAG_JUMBO_RING; 1231 r->bge_len = m_new->m_len; 1232 r->bge_idx = i; 1233 1234 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 1235 offsetof(struct bge_ring_data, bge_rx_jumbo_ring) + 1236 i * sizeof (struct bge_rx_bd), 1237 sizeof (struct bge_rx_bd), 1238 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1239 1240 return (0); 1241 } 1242 1243 /* 1244 * The standard receive ring has 512 entries in it. At 2K per mbuf cluster, 1245 * that's 1MB or memory, which is a lot. For now, we fill only the first 1246 * 256 ring entries and hope that our CPU is fast enough to keep up with 1247 * the NIC. 1248 */ 1249 static int 1250 bge_init_rx_ring_std(struct bge_softc *sc) 1251 { 1252 int i; 1253 1254 if (sc->bge_flags & BGE_RXRING_VALID) 1255 return 0; 1256 1257 for (i = 0; i < BGE_SSLOTS; i++) { 1258 if (bge_newbuf_std(sc, i, NULL, 0) == ENOBUFS) 1259 return (ENOBUFS); 1260 } 1261 1262 sc->bge_std = i - 1; 1263 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std); 1264 1265 sc->bge_flags |= BGE_RXRING_VALID; 1266 1267 return (0); 1268 } 1269 1270 static void 1271 bge_free_rx_ring_std(struct bge_softc *sc) 1272 { 1273 int i; 1274 1275 if (!(sc->bge_flags & BGE_RXRING_VALID)) 1276 return; 1277 1278 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { 1279 if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) { 1280 m_freem(sc->bge_cdata.bge_rx_std_chain[i]); 1281 sc->bge_cdata.bge_rx_std_chain[i] = NULL; 1282 bus_dmamap_destroy(sc->bge_dmatag, 1283 sc->bge_cdata.bge_rx_std_map[i]); 1284 } 1285 memset((char *)&sc->bge_rdata->bge_rx_std_ring[i], 0, 1286 sizeof(struct bge_rx_bd)); 1287 } 1288 1289 sc->bge_flags &= ~BGE_RXRING_VALID; 1290 } 1291 1292 static int 1293 bge_init_rx_ring_jumbo(struct bge_softc *sc) 1294 { 1295 int i; 1296 volatile struct bge_rcb *rcb; 1297 1298 if (sc->bge_flags & BGE_JUMBO_RXRING_VALID) 1299 return 0; 1300 1301 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 1302 if (bge_newbuf_jumbo(sc, i, NULL) == ENOBUFS) 1303 return (ENOBUFS); 1304 }; 1305 1306 sc->bge_jumbo = i - 1; 1307 sc->bge_flags |= BGE_JUMBO_RXRING_VALID; 1308 1309 rcb = &sc->bge_rdata->bge_info.bge_jumbo_rx_rcb; 1310 rcb->bge_maxlen_flags = 0; 1311 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 1312 1313 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo); 1314 1315 return (0); 1316 } 1317 1318 static void 1319 bge_free_rx_ring_jumbo(struct bge_softc *sc) 1320 { 1321 int i; 1322 1323 if (!(sc->bge_flags & BGE_JUMBO_RXRING_VALID)) 1324 return; 1325 1326 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 1327 if (sc->bge_cdata.bge_rx_jumbo_chain[i] != NULL) { 1328 m_freem(sc->bge_cdata.bge_rx_jumbo_chain[i]); 1329 sc->bge_cdata.bge_rx_jumbo_chain[i] = NULL; 1330 } 1331 memset((char *)&sc->bge_rdata->bge_rx_jumbo_ring[i], 0, 1332 sizeof(struct bge_rx_bd)); 1333 } 1334 1335 sc->bge_flags &= ~BGE_JUMBO_RXRING_VALID; 1336 } 1337 1338 static void 1339 bge_free_tx_ring(struct bge_softc *sc) 1340 { 1341 int i, freed; 1342 struct txdmamap_pool_entry *dma; 1343 1344 if (!(sc->bge_flags & BGE_TXRING_VALID)) 1345 return; 1346 1347 freed = 0; 1348 1349 for (i = 0; i < BGE_TX_RING_CNT; i++) { 1350 if (sc->bge_cdata.bge_tx_chain[i] != NULL) { 1351 freed++; 1352 m_freem(sc->bge_cdata.bge_tx_chain[i]); 1353 sc->bge_cdata.bge_tx_chain[i] = NULL; 1354 SLIST_INSERT_HEAD(&sc->txdma_list, sc->txdma[i], 1355 link); 1356 sc->txdma[i] = 0; 1357 } 1358 memset((char *)&sc->bge_rdata->bge_tx_ring[i], 0, 1359 sizeof(struct bge_tx_bd)); 1360 } 1361 1362 while ((dma = SLIST_FIRST(&sc->txdma_list))) { 1363 SLIST_REMOVE_HEAD(&sc->txdma_list, link); 1364 bus_dmamap_destroy(sc->bge_dmatag, dma->dmamap); 1365 free(dma, M_DEVBUF); 1366 } 1367 1368 sc->bge_flags &= ~BGE_TXRING_VALID; 1369 } 1370 1371 static int 1372 bge_init_tx_ring(struct bge_softc *sc) 1373 { 1374 int i; 1375 bus_dmamap_t dmamap; 1376 struct txdmamap_pool_entry *dma; 1377 1378 if (sc->bge_flags & BGE_TXRING_VALID) 1379 return 0; 1380 1381 sc->bge_txcnt = 0; 1382 sc->bge_tx_saved_considx = 0; 1383 1384 /* Initialize transmit producer index for host-memory send ring. */ 1385 sc->bge_tx_prodidx = 0; 1386 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx); 1387 /* 5700 b2 errata */ 1388 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX) 1389 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx); 1390 1391 /* NIC-memory send ring not used; initialize to zero. */ 1392 bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0); 1393 /* 5700 b2 errata */ 1394 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX) 1395 bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0); 1396 1397 SLIST_INIT(&sc->txdma_list); 1398 for (i = 0; i < BGE_RSLOTS; i++) { 1399 if (bus_dmamap_create(sc->bge_dmatag, BGE_TXDMA_MAX, 1400 BGE_NTXSEG, ETHER_MAX_LEN_JUMBO, 0, BUS_DMA_NOWAIT, 1401 &dmamap)) 1402 return (ENOBUFS); 1403 if (dmamap == NULL) 1404 panic("dmamap NULL in bge_init_tx_ring"); 1405 dma = malloc(sizeof(*dma), M_DEVBUF, M_NOWAIT); 1406 if (dma == NULL) { 1407 aprint_error_dev(sc->bge_dev, 1408 "can't alloc txdmamap_pool_entry\n"); 1409 bus_dmamap_destroy(sc->bge_dmatag, dmamap); 1410 return (ENOMEM); 1411 } 1412 dma->dmamap = dmamap; 1413 SLIST_INSERT_HEAD(&sc->txdma_list, dma, link); 1414 } 1415 1416 sc->bge_flags |= BGE_TXRING_VALID; 1417 1418 return (0); 1419 } 1420 1421 static void 1422 bge_setmulti(struct bge_softc *sc) 1423 { 1424 struct ethercom *ac = &sc->ethercom; 1425 struct ifnet *ifp = &ac->ec_if; 1426 struct ether_multi *enm; 1427 struct ether_multistep step; 1428 u_int32_t hashes[4] = { 0, 0, 0, 0 }; 1429 u_int32_t h; 1430 int i; 1431 1432 if (ifp->if_flags & IFF_PROMISC) 1433 goto allmulti; 1434 1435 /* Now program new ones. */ 1436 ETHER_FIRST_MULTI(step, ac, enm); 1437 while (enm != NULL) { 1438 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1439 /* 1440 * We must listen to a range of multicast addresses. 1441 * For now, just accept all multicasts, rather than 1442 * trying to set only those filter bits needed to match 1443 * the range. (At this time, the only use of address 1444 * ranges is for IP multicast routing, for which the 1445 * range is big enough to require all bits set.) 1446 */ 1447 goto allmulti; 1448 } 1449 1450 h = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN); 1451 1452 /* Just want the 7 least-significant bits. */ 1453 h &= 0x7f; 1454 1455 hashes[(h & 0x60) >> 5] |= 1 << (h & 0x1F); 1456 ETHER_NEXT_MULTI(step, enm); 1457 } 1458 1459 ifp->if_flags &= ~IFF_ALLMULTI; 1460 goto setit; 1461 1462 allmulti: 1463 ifp->if_flags |= IFF_ALLMULTI; 1464 hashes[0] = hashes[1] = hashes[2] = hashes[3] = 0xffffffff; 1465 1466 setit: 1467 for (i = 0; i < 4; i++) 1468 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]); 1469 } 1470 1471 const int bge_swapbits[] = { 1472 0, 1473 BGE_MODECTL_BYTESWAP_DATA, 1474 BGE_MODECTL_WORDSWAP_DATA, 1475 BGE_MODECTL_BYTESWAP_NONFRAME, 1476 BGE_MODECTL_WORDSWAP_NONFRAME, 1477 1478 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA, 1479 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_BYTESWAP_NONFRAME, 1480 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_NONFRAME, 1481 1482 BGE_MODECTL_WORDSWAP_DATA|BGE_MODECTL_BYTESWAP_NONFRAME, 1483 BGE_MODECTL_WORDSWAP_DATA|BGE_MODECTL_WORDSWAP_NONFRAME, 1484 1485 BGE_MODECTL_BYTESWAP_NONFRAME|BGE_MODECTL_WORDSWAP_NONFRAME, 1486 1487 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA| 1488 BGE_MODECTL_BYTESWAP_NONFRAME, 1489 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA| 1490 BGE_MODECTL_WORDSWAP_NONFRAME, 1491 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_BYTESWAP_NONFRAME| 1492 BGE_MODECTL_WORDSWAP_NONFRAME, 1493 BGE_MODECTL_WORDSWAP_DATA|BGE_MODECTL_BYTESWAP_NONFRAME| 1494 BGE_MODECTL_WORDSWAP_NONFRAME, 1495 1496 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA| 1497 BGE_MODECTL_BYTESWAP_NONFRAME|BGE_MODECTL_WORDSWAP_NONFRAME, 1498 }; 1499 1500 int bge_swapindex = 0; 1501 1502 /* 1503 * Do endian, PCI and DMA initialization. Also check the on-board ROM 1504 * self-test results. 1505 */ 1506 static int 1507 bge_chipinit(struct bge_softc *sc) 1508 { 1509 u_int32_t cachesize; 1510 int i; 1511 u_int32_t dma_rw_ctl; 1512 1513 1514 /* Set endianness before we access any non-PCI registers. */ 1515 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MISC_CTL, 1516 BGE_INIT); 1517 1518 /* Set power state to D0. */ 1519 bge_setpowerstate(sc, 0); 1520 1521 /* 1522 * Check the 'ROM failed' bit on the RX CPU to see if 1523 * self-tests passed. 1524 */ 1525 if (CSR_READ_4(sc, BGE_RXCPU_MODE) & BGE_RXCPUMODE_ROMFAIL) { 1526 aprint_error_dev(sc->bge_dev, 1527 "RX CPU self-diagnostics failed!\n"); 1528 return (ENODEV); 1529 } 1530 1531 /* Clear the MAC control register */ 1532 CSR_WRITE_4(sc, BGE_MAC_MODE, 0); 1533 1534 /* 1535 * Clear the MAC statistics block in the NIC's 1536 * internal memory. 1537 */ 1538 for (i = BGE_STATS_BLOCK; 1539 i < BGE_STATS_BLOCK_END + 1; i += sizeof(u_int32_t)) 1540 BGE_MEMWIN_WRITE(sc->sc_pc, sc->sc_pcitag, i, 0); 1541 1542 for (i = BGE_STATUS_BLOCK; 1543 i < BGE_STATUS_BLOCK_END + 1; i += sizeof(u_int32_t)) 1544 BGE_MEMWIN_WRITE(sc->sc_pc, sc->sc_pcitag, i, 0); 1545 1546 /* Set up the PCI DMA control register. */ 1547 if (sc->bge_flags & BGE_PCIE) { 1548 u_int32_t device_ctl; 1549 1550 /* From FreeBSD */ 1551 DPRINTFN(4, ("(%s: PCI-Express DMA setting)\n", 1552 device_xname(sc->bge_dev))); 1553 dma_rw_ctl = (BGE_PCI_READ_CMD | BGE_PCI_WRITE_CMD | 1554 (0xf << BGE_PCIDMARWCTL_RD_WAT_SHIFT) | 1555 (0x2 << BGE_PCIDMARWCTL_WR_WAT_SHIFT)); 1556 1557 /* jonathan: alternative from Linux driver */ 1558 #define DMA_CTRL_WRITE_PCIE_H20MARK_128 0x00180000 1559 #define DMA_CTRL_WRITE_PCIE_H20MARK_256 0x00380000 1560 1561 dma_rw_ctl = 0x76000000; /* XXX XXX XXX */; 1562 device_ctl = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 1563 BGE_PCI_CONF_DEV_CTRL); 1564 aprint_debug_dev(sc->bge_dev, "pcie mode=0x%x\n", device_ctl); 1565 1566 if ((device_ctl & 0x00e0) && 0) { 1567 /* 1568 * XXX jonathan (at) NetBSD.org: 1569 * This clause is exactly what the Broadcom-supplied 1570 * Linux does; but given overall register programming 1571 * by if_bge(4), this larger DMA-write watermark 1572 * value causes bcm5721 chips to totally wedge. 1573 */ 1574 dma_rw_ctl |= BGE_PCIDMA_RWCTL_PCIE_WRITE_WATRMARK_256; 1575 } else { 1576 dma_rw_ctl |= BGE_PCIDMA_RWCTL_PCIE_WRITE_WATRMARK_128; 1577 } 1578 } else if (sc->bge_flags & BGE_PCIX){ 1579 DPRINTFN(4, ("(:%s: PCI-X DMA setting)\n", 1580 device_xname(sc->bge_dev))); 1581 /* PCI-X bus */ 1582 dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD | 1583 (0x3 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) | 1584 (0x3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT) | 1585 (0x0F); 1586 /* 1587 * 5703 and 5704 need ONEDMA_AT_ONCE as a workaround 1588 * for hardware bugs, which means we should also clear 1589 * the low-order MINDMA bits. In addition, the 5704 1590 * uses a different encoding of read/write watermarks. 1591 */ 1592 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) { 1593 dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD | 1594 /* should be 0x1f0000 */ 1595 (0x7 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) | 1596 (0x3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT); 1597 dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE; 1598 } 1599 else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5703) { 1600 dma_rw_ctl &= 0xfffffff0; 1601 dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE; 1602 } 1603 else if (BGE_IS_5714_FAMILY(sc)) { 1604 dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD; 1605 dma_rw_ctl &= ~BGE_PCIDMARWCTL_ONEDMA_ATONCE; /* XXX */ 1606 /* XXX magic values, Broadcom-supplied Linux driver */ 1607 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5780) 1608 dma_rw_ctl |= (1 << 20) | (1 << 18) | 1609 BGE_PCIDMARWCTL_ONEDMA_ATONCE; 1610 else 1611 dma_rw_ctl |= (1<<20) | (1<<18) | (1 << 15); 1612 } 1613 } else { 1614 /* Conventional PCI bus */ 1615 DPRINTFN(4, ("(%s: PCI 2.2 DMA setting)\n", 1616 device_xname(sc->bge_dev))); 1617 dma_rw_ctl = (BGE_PCI_READ_CMD | BGE_PCI_WRITE_CMD | 1618 (0x7 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) | 1619 (0x7 << BGE_PCIDMARWCTL_WR_WAT_SHIFT)); 1620 if (BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5705 && 1621 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5750) 1622 dma_rw_ctl |= 0x0F; 1623 } 1624 1625 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_DMA_RW_CTL, dma_rw_ctl); 1626 1627 /* 1628 * Set up general mode register. 1629 */ 1630 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS| 1631 BGE_MODECTL_MAC_ATTN_INTR|BGE_MODECTL_HOST_SEND_BDS| 1632 BGE_MODECTL_TX_NO_PHDR_CSUM|BGE_MODECTL_RX_NO_PHDR_CSUM); 1633 1634 /* Get cache line size. */ 1635 cachesize = pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CACHESZ); 1636 1637 /* 1638 * Avoid violating PCI spec on certain chip revs. 1639 */ 1640 if (pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CMD) & 1641 PCIM_CMD_MWIEN) { 1642 switch(cachesize) { 1643 case 1: 1644 PCI_SETBIT(sc->sc_pc, sc->sc_pcitag, BGE_PCI_DMA_RW_CTL, 1645 BGE_PCI_WRITE_BNDRY_16BYTES); 1646 break; 1647 case 2: 1648 PCI_SETBIT(sc->sc_pc, sc->sc_pcitag, BGE_PCI_DMA_RW_CTL, 1649 BGE_PCI_WRITE_BNDRY_32BYTES); 1650 break; 1651 case 4: 1652 PCI_SETBIT(sc->sc_pc, sc->sc_pcitag, BGE_PCI_DMA_RW_CTL, 1653 BGE_PCI_WRITE_BNDRY_64BYTES); 1654 break; 1655 case 8: 1656 PCI_SETBIT(sc->sc_pc, sc->sc_pcitag, BGE_PCI_DMA_RW_CTL, 1657 BGE_PCI_WRITE_BNDRY_128BYTES); 1658 break; 1659 case 16: 1660 PCI_SETBIT(sc->sc_pc, sc->sc_pcitag, BGE_PCI_DMA_RW_CTL, 1661 BGE_PCI_WRITE_BNDRY_256BYTES); 1662 break; 1663 case 32: 1664 PCI_SETBIT(sc->sc_pc, sc->sc_pcitag, BGE_PCI_DMA_RW_CTL, 1665 BGE_PCI_WRITE_BNDRY_512BYTES); 1666 break; 1667 case 64: 1668 PCI_SETBIT(sc->sc_pc, sc->sc_pcitag, BGE_PCI_DMA_RW_CTL, 1669 BGE_PCI_WRITE_BNDRY_1024BYTES); 1670 break; 1671 default: 1672 /* Disable PCI memory write and invalidate. */ 1673 #if 0 1674 if (bootverbose) 1675 aprint_error_dev(sc->bge_dev, 1676 "cache line size %d not supported " 1677 "disabling PCI MWI\n", 1678 #endif 1679 PCI_CLRBIT(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CMD, 1680 PCIM_CMD_MWIEN); 1681 break; 1682 } 1683 } 1684 1685 /* 1686 * Disable memory write invalidate. Apparently it is not supported 1687 * properly by these devices. 1688 */ 1689 PCI_CLRBIT(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CMD, PCIM_CMD_MWIEN); 1690 1691 1692 #ifdef __brokenalpha__ 1693 /* 1694 * Must insure that we do not cross an 8K (bytes) boundary 1695 * for DMA reads. Our highest limit is 1K bytes. This is a 1696 * restriction on some ALPHA platforms with early revision 1697 * 21174 PCI chipsets, such as the AlphaPC 164lx 1698 */ 1699 PCI_SETBIT(sc, BGE_PCI_DMA_RW_CTL, BGE_PCI_READ_BNDRY_1024, 4); 1700 #endif 1701 1702 /* Set the timer prescaler (always 66MHz) */ 1703 CSR_WRITE_4(sc, BGE_MISC_CFG, 65 << 1/*BGE_32BITTIME_66MHZ*/); 1704 1705 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 1706 DELAY(40); /* XXX */ 1707 1708 /* Put PHY into ready state */ 1709 BGE_CLRBIT(sc, BGE_MISC_CFG, BGE_MISCCFG_EPHY_IDDQ); 1710 CSR_READ_4(sc, BGE_MISC_CFG); /* Flush */ 1711 DELAY(40); 1712 } 1713 1714 return (0); 1715 } 1716 1717 static int 1718 bge_blockinit(struct bge_softc *sc) 1719 { 1720 volatile struct bge_rcb *rcb; 1721 bus_size_t rcb_addr; 1722 int i; 1723 struct ifnet *ifp = &sc->ethercom.ec_if; 1724 bge_hostaddr taddr; 1725 1726 /* 1727 * Initialize the memory window pointer register so that 1728 * we can access the first 32K of internal NIC RAM. This will 1729 * allow us to set up the TX send ring RCBs and the RX return 1730 * ring RCBs, plus other things which live in NIC memory. 1731 */ 1732 1733 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_BASEADDR, 0); 1734 1735 /* Configure mbuf memory pool */ 1736 if (!(BGE_IS_5705_OR_BEYOND(sc))) { 1737 if (sc->bge_extram) { 1738 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, 1739 BGE_EXT_SSRAM); 1740 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) 1741 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000); 1742 else 1743 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000); 1744 } else { 1745 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, 1746 BGE_BUFFPOOL_1); 1747 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) 1748 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000); 1749 else 1750 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000); 1751 } 1752 1753 /* Configure DMA resource pool */ 1754 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_BASEADDR, 1755 BGE_DMA_DESCRIPTORS); 1756 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LEN, 0x2000); 1757 } 1758 1759 /* Configure mbuf pool watermarks */ 1760 #ifdef ORIG_WPAUL_VALUES 1761 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 24); 1762 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 24); 1763 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 48); 1764 #else 1765 1766 /* new broadcom docs strongly recommend these: */ 1767 if (!BGE_IS_5705_OR_BEYOND(sc)) { 1768 if (ifp->if_mtu > ETHER_MAX_LEN) { 1769 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x50); 1770 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x20); 1771 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60); 1772 } else { 1773 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 304); 1774 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 152); 1775 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 380); 1776 } 1777 } else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 1778 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0); 1779 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x04); 1780 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x10); 1781 } else { 1782 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0); 1783 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x10); 1784 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60); 1785 } 1786 #endif 1787 1788 /* Configure DMA resource watermarks */ 1789 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5); 1790 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10); 1791 1792 /* Enable buffer manager */ 1793 if (!BGE_IS_5705_OR_BEYOND(sc)) { 1794 CSR_WRITE_4(sc, BGE_BMAN_MODE, 1795 BGE_BMANMODE_ENABLE|BGE_BMANMODE_LOMBUF_ATTN); 1796 1797 /* Poll for buffer manager start indication */ 1798 for (i = 0; i < BGE_TIMEOUT; i++) { 1799 if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE) 1800 break; 1801 DELAY(10); 1802 } 1803 1804 if (i == BGE_TIMEOUT) { 1805 aprint_error_dev(sc->bge_dev, 1806 "buffer manager failed to start\n"); 1807 return (ENXIO); 1808 } 1809 } 1810 1811 /* Enable flow-through queues */ 1812 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 1813 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 1814 1815 /* Wait until queue initialization is complete */ 1816 for (i = 0; i < BGE_TIMEOUT; i++) { 1817 if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0) 1818 break; 1819 DELAY(10); 1820 } 1821 1822 if (i == BGE_TIMEOUT) { 1823 aprint_error_dev(sc->bge_dev, 1824 "flow-through queue init failed\n"); 1825 return (ENXIO); 1826 } 1827 1828 /* Initialize the standard RX ring control block */ 1829 rcb = &sc->bge_rdata->bge_info.bge_std_rx_rcb; 1830 bge_set_hostaddr(&rcb->bge_hostaddr, 1831 BGE_RING_DMA_ADDR(sc, bge_rx_std_ring)); 1832 if (BGE_IS_5705_OR_BEYOND(sc)) 1833 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(512, 0); 1834 else 1835 rcb->bge_maxlen_flags = 1836 BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 0); 1837 if (sc->bge_extram) 1838 rcb->bge_nicaddr = BGE_EXT_STD_RX_RINGS; 1839 else 1840 rcb->bge_nicaddr = BGE_STD_RX_RINGS; 1841 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcb->bge_hostaddr.bge_addr_hi); 1842 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcb->bge_hostaddr.bge_addr_lo); 1843 CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 1844 CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcb->bge_nicaddr); 1845 1846 if (BGE_IS_5705_OR_BEYOND(sc)) 1847 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT_5705; 1848 else 1849 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT; 1850 1851 /* 1852 * Initialize the jumbo RX ring control block 1853 * We set the 'ring disabled' bit in the flags 1854 * field until we're actually ready to start 1855 * using this ring (i.e. once we set the MTU 1856 * high enough to require it). 1857 */ 1858 if (!BGE_IS_5705_OR_BEYOND(sc)) { 1859 rcb = &sc->bge_rdata->bge_info.bge_jumbo_rx_rcb; 1860 bge_set_hostaddr(&rcb->bge_hostaddr, 1861 BGE_RING_DMA_ADDR(sc, bge_rx_jumbo_ring)); 1862 rcb->bge_maxlen_flags = 1863 BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 1864 BGE_RCB_FLAG_RING_DISABLED); 1865 if (sc->bge_extram) 1866 rcb->bge_nicaddr = BGE_EXT_JUMBO_RX_RINGS; 1867 else 1868 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS; 1869 1870 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI, 1871 rcb->bge_hostaddr.bge_addr_hi); 1872 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO, 1873 rcb->bge_hostaddr.bge_addr_lo); 1874 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, 1875 rcb->bge_maxlen_flags); 1876 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcb->bge_nicaddr); 1877 1878 /* Set up dummy disabled mini ring RCB */ 1879 rcb = &sc->bge_rdata->bge_info.bge_mini_rx_rcb; 1880 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0, 1881 BGE_RCB_FLAG_RING_DISABLED); 1882 CSR_WRITE_4(sc, BGE_RX_MINI_RCB_MAXLEN_FLAGS, 1883 rcb->bge_maxlen_flags); 1884 1885 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 1886 offsetof(struct bge_ring_data, bge_info), 1887 sizeof (struct bge_gib), 1888 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1889 } 1890 1891 /* 1892 * Set the BD ring replenish thresholds. The recommended 1893 * values are 1/8th the number of descriptors allocated to 1894 * each ring. 1895 */ 1896 i = BGE_STD_RX_RING_CNT / 8; 1897 1898 /* 1899 * Use a value of 8 for the following chips to workaround HW errata. 1900 * Some of these chips have been added based on empirical 1901 * evidence (they don't work unless this is done). 1902 */ 1903 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5750 || 1904 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5752 || 1905 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5755 || 1906 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5787 || 1907 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 1908 i = 8; 1909 1910 CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, i); 1911 CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH, BGE_JUMBO_RX_RING_CNT/8); 1912 1913 /* 1914 * Disable all unused send rings by setting the 'ring disabled' 1915 * bit in the flags field of all the TX send ring control blocks. 1916 * These are located in NIC memory. 1917 */ 1918 rcb_addr = BGE_MEMWIN_START + BGE_SEND_RING_RCB; 1919 for (i = 0; i < BGE_TX_RINGS_EXTSSRAM_MAX; i++) { 1920 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 1921 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED)); 1922 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 0); 1923 rcb_addr += sizeof(struct bge_rcb); 1924 } 1925 1926 /* Configure TX RCB 0 (we use only the first ring) */ 1927 rcb_addr = BGE_MEMWIN_START + BGE_SEND_RING_RCB; 1928 bge_set_hostaddr(&taddr, BGE_RING_DMA_ADDR(sc, bge_tx_ring)); 1929 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi); 1930 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo); 1931 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 1932 BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT)); 1933 if (!(BGE_IS_5705_OR_BEYOND(sc))) 1934 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 1935 BGE_RCB_MAXLEN_FLAGS(BGE_TX_RING_CNT, 0)); 1936 1937 /* Disable all unused RX return rings */ 1938 rcb_addr = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB; 1939 for (i = 0; i < BGE_RX_RINGS_MAX; i++) { 1940 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_hi, 0); 1941 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_lo, 0); 1942 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 1943 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 1944 BGE_RCB_FLAG_RING_DISABLED)); 1945 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 0); 1946 bge_writembx(sc, BGE_MBX_RX_CONS0_LO + 1947 (i * (sizeof(u_int64_t))), 0); 1948 rcb_addr += sizeof(struct bge_rcb); 1949 } 1950 1951 /* Initialize RX ring indexes */ 1952 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, 0); 1953 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0); 1954 bge_writembx(sc, BGE_MBX_RX_MINI_PROD_LO, 0); 1955 1956 /* 1957 * Set up RX return ring 0 1958 * Note that the NIC address for RX return rings is 0x00000000. 1959 * The return rings live entirely within the host, so the 1960 * nicaddr field in the RCB isn't used. 1961 */ 1962 rcb_addr = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB; 1963 bge_set_hostaddr(&taddr, BGE_RING_DMA_ADDR(sc, bge_rx_return_ring)); 1964 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi); 1965 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo); 1966 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 0x00000000); 1967 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 1968 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 0)); 1969 1970 /* Set random backoff seed for TX */ 1971 CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF, 1972 CLLADDR(ifp->if_sadl)[0] + CLLADDR(ifp->if_sadl)[1] + 1973 CLLADDR(ifp->if_sadl)[2] + CLLADDR(ifp->if_sadl)[3] + 1974 CLLADDR(ifp->if_sadl)[4] + CLLADDR(ifp->if_sadl)[5] + 1975 BGE_TX_BACKOFF_SEED_MASK); 1976 1977 /* Set inter-packet gap */ 1978 CSR_WRITE_4(sc, BGE_TX_LENGTHS, 0x2620); 1979 1980 /* 1981 * Specify which ring to use for packets that don't match 1982 * any RX rules. 1983 */ 1984 CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08); 1985 1986 /* 1987 * Configure number of RX lists. One interrupt distribution 1988 * list, sixteen active lists, one bad frames class. 1989 */ 1990 CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181); 1991 1992 /* Inialize RX list placement stats mask. */ 1993 CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF); 1994 CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1); 1995 1996 /* Disable host coalescing until we get it set up */ 1997 CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000); 1998 1999 /* Poll to make sure it's shut down. */ 2000 for (i = 0; i < BGE_TIMEOUT; i++) { 2001 if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE)) 2002 break; 2003 DELAY(10); 2004 } 2005 2006 if (i == BGE_TIMEOUT) { 2007 aprint_error_dev(sc->bge_dev, 2008 "host coalescing engine failed to idle\n"); 2009 return (ENXIO); 2010 } 2011 2012 /* Set up host coalescing defaults */ 2013 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bge_rx_coal_ticks); 2014 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bge_tx_coal_ticks); 2015 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bge_rx_max_coal_bds); 2016 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bge_tx_max_coal_bds); 2017 if (!(BGE_IS_5705_OR_BEYOND(sc))) { 2018 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT, 0); 2019 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT, 0); 2020 } 2021 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 0); 2022 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 0); 2023 2024 /* Set up address of statistics block */ 2025 if (!(BGE_IS_5705_OR_BEYOND(sc))) { 2026 bge_set_hostaddr(&taddr, 2027 BGE_RING_DMA_ADDR(sc, bge_info.bge_stats)); 2028 CSR_WRITE_4(sc, BGE_HCC_STATS_TICKS, sc->bge_stat_ticks); 2029 CSR_WRITE_4(sc, BGE_HCC_STATS_BASEADDR, BGE_STATS_BLOCK); 2030 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_HI, taddr.bge_addr_hi); 2031 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_LO, taddr.bge_addr_lo); 2032 } 2033 2034 /* Set up address of status block */ 2035 bge_set_hostaddr(&taddr, BGE_RING_DMA_ADDR(sc, bge_status_block)); 2036 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_BASEADDR, BGE_STATUS_BLOCK); 2037 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI, taddr.bge_addr_hi); 2038 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO, taddr.bge_addr_lo); 2039 sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx = 0; 2040 sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx = 0; 2041 2042 /* Turn on host coalescing state machine */ 2043 CSR_WRITE_4(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE); 2044 2045 /* Turn on RX BD completion state machine and enable attentions */ 2046 CSR_WRITE_4(sc, BGE_RBDC_MODE, 2047 BGE_RBDCMODE_ENABLE|BGE_RBDCMODE_ATTN); 2048 2049 /* Turn on RX list placement state machine */ 2050 CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 2051 2052 /* Turn on RX list selector state machine. */ 2053 if (!(BGE_IS_5705_OR_BEYOND(sc))) 2054 CSR_WRITE_4(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 2055 2056 /* Turn on DMA, clear stats */ 2057 CSR_WRITE_4(sc, BGE_MAC_MODE, BGE_MACMODE_TXDMA_ENB| 2058 BGE_MACMODE_RXDMA_ENB|BGE_MACMODE_RX_STATS_CLEAR| 2059 BGE_MACMODE_TX_STATS_CLEAR|BGE_MACMODE_RX_STATS_ENB| 2060 BGE_MACMODE_TX_STATS_ENB|BGE_MACMODE_FRMHDR_DMA_ENB| 2061 ((sc->bge_flags & BGE_PHY_FIBER_TBI) ? BGE_PORTMODE_TBI 2062 : BGE_PORTMODE_MII)); 2063 2064 /* Set misc. local control, enable interrupts on attentions */ 2065 sc->bge_local_ctrl_reg = BGE_MLC_INTR_ONATTN | BGE_MLC_AUTO_EEPROM; 2066 2067 #ifdef notdef 2068 /* Assert GPIO pins for PHY reset */ 2069 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUT0| 2070 BGE_MLC_MISCIO_OUT1|BGE_MLC_MISCIO_OUT2); 2071 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUTEN0| 2072 BGE_MLC_MISCIO_OUTEN1|BGE_MLC_MISCIO_OUTEN2); 2073 #endif 2074 2075 #if defined(not_quite_yet) 2076 /* Linux driver enables enable gpio pin #1 on 5700s */ 2077 if (sc->bge_chipid == BGE_CHIPID_BCM5700) { 2078 sc->bge_local_ctrl_reg |= 2079 (BGE_MLC_MISCIO_OUT1|BGE_MLC_MISCIO_OUTEN1); 2080 } 2081 #endif 2082 CSR_WRITE_4(sc, BGE_MISC_LOCAL_CTL, sc->bge_local_ctrl_reg); 2083 2084 /* Turn on DMA completion state machine */ 2085 if (!(BGE_IS_5705_OR_BEYOND(sc))) 2086 CSR_WRITE_4(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 2087 2088 /* Turn on write DMA state machine */ 2089 { 2090 uint32_t bge_wdma_mode = 2091 BGE_WDMAMODE_ENABLE|BGE_WDMAMODE_ALL_ATTNS; 2092 2093 /* Enable host coalescing bug fix; see Linux tg3.c */ 2094 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5755 || 2095 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5787) 2096 bge_wdma_mode |= (1 << 29); 2097 2098 CSR_WRITE_4(sc, BGE_WDMA_MODE, bge_wdma_mode); 2099 } 2100 2101 /* Turn on read DMA state machine */ 2102 { 2103 uint32_t dma_read_modebits; 2104 2105 dma_read_modebits = 2106 BGE_RDMAMODE_ENABLE | BGE_RDMAMODE_ALL_ATTNS; 2107 2108 if ((sc->bge_flags & BGE_PCIE) && 0) { 2109 dma_read_modebits |= BGE_RDMA_MODE_FIFO_LONG_BURST; 2110 } else if (BGE_IS_5705_OR_BEYOND(sc)) { 2111 dma_read_modebits |= BGE_RDMA_MODE_FIFO_SIZE_128; 2112 } 2113 2114 /* XXX broadcom-supplied linux driver; undocumented */ 2115 if (BGE_IS_5750_OR_BEYOND(sc)) { 2116 /* 2117 * XXX: magic values. 2118 * From Broadcom-supplied Linux driver; apparently 2119 * required to workaround a DMA bug affecting TSO 2120 * on bcm575x/bcm5721? 2121 */ 2122 dma_read_modebits |= (1 << 27); 2123 } 2124 CSR_WRITE_4(sc, BGE_RDMA_MODE, dma_read_modebits); 2125 } 2126 2127 /* Turn on RX data completion state machine */ 2128 CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 2129 2130 /* Turn on RX BD initiator state machine */ 2131 CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 2132 2133 /* Turn on RX data and RX BD initiator state machine */ 2134 CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE); 2135 2136 /* Turn on Mbuf cluster free state machine */ 2137 if (!(BGE_IS_5705_OR_BEYOND(sc))) 2138 CSR_WRITE_4(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 2139 2140 /* Turn on send BD completion state machine */ 2141 CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 2142 2143 /* Turn on send data completion state machine */ 2144 CSR_WRITE_4(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE); 2145 2146 /* Turn on send data initiator state machine */ 2147 if (BGE_IS_5750_OR_BEYOND(sc)) { 2148 /* XXX: magic value from Linux driver */ 2149 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE | 0x08); 2150 } else { 2151 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 2152 } 2153 2154 /* Turn on send BD initiator state machine */ 2155 CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 2156 2157 /* Turn on send BD selector state machine */ 2158 CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 2159 2160 CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF); 2161 CSR_WRITE_4(sc, BGE_SDI_STATS_CTL, 2162 BGE_SDISTATSCTL_ENABLE|BGE_SDISTATSCTL_FASTER); 2163 2164 /* ack/clear link change events */ 2165 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED| 2166 BGE_MACSTAT_CFG_CHANGED); 2167 CSR_WRITE_4(sc, BGE_MI_STS, 0); 2168 2169 /* Enable PHY auto polling (for MII/GMII only) */ 2170 if (sc->bge_flags & BGE_PHY_FIBER_TBI) { 2171 CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK); 2172 } else { 2173 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL|10<<16); 2174 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700) 2175 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, 2176 BGE_EVTENB_MI_INTERRUPT); 2177 } 2178 2179 /* Enable link state change attentions. */ 2180 BGE_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED); 2181 2182 return (0); 2183 } 2184 2185 static const struct bge_revision * 2186 bge_lookup_rev(uint32_t chipid) 2187 { 2188 const struct bge_revision *br; 2189 2190 for (br = bge_revisions; br->br_name != NULL; br++) { 2191 if (br->br_chipid == chipid) 2192 return (br); 2193 } 2194 2195 for (br = bge_majorrevs; br->br_name != NULL; br++) { 2196 if (br->br_chipid == BGE_ASICREV(chipid)) 2197 return (br); 2198 } 2199 2200 return (NULL); 2201 } 2202 2203 static const struct bge_product * 2204 bge_lookup(const struct pci_attach_args *pa) 2205 { 2206 const struct bge_product *bp; 2207 2208 for (bp = bge_products; bp->bp_name != NULL; bp++) { 2209 if (PCI_VENDOR(pa->pa_id) == bp->bp_vendor && 2210 PCI_PRODUCT(pa->pa_id) == bp->bp_product) 2211 return (bp); 2212 } 2213 2214 return (NULL); 2215 } 2216 2217 static int 2218 bge_setpowerstate(struct bge_softc *sc, int powerlevel) 2219 { 2220 #ifdef NOTYET 2221 u_int32_t pm_ctl = 0; 2222 2223 /* XXX FIXME: make sure indirect accesses enabled? */ 2224 pm_ctl = pci_conf_read(sc->bge_dev, BGE_PCI_MISC_CTL, 4); 2225 pm_ctl |= BGE_PCIMISCCTL_INDIRECT_ACCESS; 2226 pci_write_config(sc->bge_dev, BGE_PCI_MISC_CTL, pm_ctl, 4); 2227 2228 /* clear the PME_assert bit and power state bits, enable PME */ 2229 pm_ctl = pci_conf_read(sc->bge_dev, BGE_PCI_PWRMGMT_CMD, 2); 2230 pm_ctl &= ~PCIM_PSTAT_DMASK; 2231 pm_ctl |= (1 << 8); 2232 2233 if (powerlevel == 0) { 2234 pm_ctl |= PCIM_PSTAT_D0; 2235 pci_write_config(sc->bge_dev, BGE_PCI_PWRMGMT_CMD, 2236 pm_ctl, 2); 2237 DELAY(10000); 2238 CSR_WRITE_4(sc, BGE_MISC_LOCAL_CTL, sc->bge_local_ctrl_reg); 2239 DELAY(10000); 2240 2241 #ifdef NOTYET 2242 /* XXX FIXME: write 0x02 to phy aux_Ctrl reg */ 2243 bge_miibus_writereg(sc->bge_dev, 1, 0x18, 0x02); 2244 #endif 2245 DELAY(40); DELAY(40); DELAY(40); 2246 DELAY(10000); /* above not quite adequate on 5700 */ 2247 return 0; 2248 } 2249 2250 2251 /* 2252 * Entering ACPI power states D1-D3 is achieved by wiggling 2253 * GMII gpio pins. Example code assumes all hardware vendors 2254 * followed Broadom's sample pcb layout. Until we verify that 2255 * for all supported OEM cards, states D1-D3 are unsupported. 2256 */ 2257 aprint_error_dev(sc->bge_dev, 2258 "power state %d unimplemented; check GPIO pins\n", 2259 powerlevel); 2260 #endif 2261 return EOPNOTSUPP; 2262 } 2263 2264 2265 /* 2266 * Probe for a Broadcom chip. Check the PCI vendor and device IDs 2267 * against our list and return its name if we find a match. Note 2268 * that since the Broadcom controller contains VPD support, we 2269 * can get the device name string from the controller itself instead 2270 * of the compiled-in string. This is a little slow, but it guarantees 2271 * we'll always announce the right product name. 2272 */ 2273 static int 2274 bge_probe(device_t parent, cfdata_t match, void *aux) 2275 { 2276 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 2277 2278 if (bge_lookup(pa) != NULL) 2279 return (1); 2280 2281 return (0); 2282 } 2283 2284 static void 2285 bge_attach(device_t parent, device_t self, void *aux) 2286 { 2287 struct bge_softc *sc = device_private(self); 2288 struct pci_attach_args *pa = aux; 2289 const struct bge_product *bp; 2290 const struct bge_revision *br; 2291 pci_chipset_tag_t pc; 2292 pci_intr_handle_t ih; 2293 const char *intrstr = NULL; 2294 bus_dma_segment_t seg; 2295 int rseg; 2296 u_int32_t hwcfg = 0; 2297 u_int32_t command; 2298 struct ifnet *ifp; 2299 void * kva; 2300 u_char eaddr[ETHER_ADDR_LEN]; 2301 pcireg_t memtype; 2302 bus_addr_t memaddr; 2303 bus_size_t memsize; 2304 u_int32_t pm_ctl; 2305 2306 bp = bge_lookup(pa); 2307 KASSERT(bp != NULL); 2308 2309 sc->sc_pc = pa->pa_pc; 2310 sc->sc_pcitag = pa->pa_tag; 2311 sc->bge_dev = self; 2312 2313 aprint_naive(": Ethernet controller\n"); 2314 aprint_normal(": %s\n", bp->bp_name); 2315 2316 /* 2317 * Map control/status registers. 2318 */ 2319 DPRINTFN(5, ("Map control/status regs\n")); 2320 pc = sc->sc_pc; 2321 command = pci_conf_read(pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG); 2322 command |= PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_MASTER_ENABLE; 2323 pci_conf_write(pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG, command); 2324 command = pci_conf_read(pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG); 2325 2326 if (!(command & PCI_COMMAND_MEM_ENABLE)) { 2327 aprint_error_dev(sc->bge_dev, 2328 "failed to enable memory mapping!\n"); 2329 return; 2330 } 2331 2332 DPRINTFN(5, ("pci_mem_find\n")); 2333 memtype = pci_mapreg_type(sc->sc_pc, sc->sc_pcitag, BGE_PCI_BAR0); 2334 switch (memtype) { 2335 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 2336 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 2337 if (pci_mapreg_map(pa, BGE_PCI_BAR0, 2338 memtype, 0, &sc->bge_btag, &sc->bge_bhandle, 2339 &memaddr, &memsize) == 0) 2340 break; 2341 default: 2342 aprint_error_dev(sc->bge_dev, "can't find mem space\n"); 2343 return; 2344 } 2345 2346 DPRINTFN(5, ("pci_intr_map\n")); 2347 if (pci_intr_map(pa, &ih)) { 2348 aprint_error_dev(sc->bge_dev, "couldn't map interrupt\n"); 2349 return; 2350 } 2351 2352 DPRINTFN(5, ("pci_intr_string\n")); 2353 intrstr = pci_intr_string(pc, ih); 2354 2355 DPRINTFN(5, ("pci_intr_establish\n")); 2356 sc->bge_intrhand = pci_intr_establish(pc, ih, IPL_NET, bge_intr, sc); 2357 2358 if (sc->bge_intrhand == NULL) { 2359 aprint_error_dev(sc->bge_dev, 2360 "couldn't establish interrupt%s%s\n", 2361 intrstr ? " at " : "", intrstr ? intrstr : ""); 2362 return; 2363 } 2364 aprint_normal_dev(sc->bge_dev, "interrupting at %s\n", intrstr); 2365 2366 /* 2367 * Kludge for 5700 Bx bug: a hardware bug (PCIX byte enable?) 2368 * can clobber the chip's PCI config-space power control registers, 2369 * leaving the card in D3 powersave state. 2370 * We do not have memory-mapped registers in this state, 2371 * so force device into D0 state before starting initialization. 2372 */ 2373 pm_ctl = pci_conf_read(pc, sc->sc_pcitag, BGE_PCI_PWRMGMT_CMD); 2374 pm_ctl &= ~(PCI_PWR_D0|PCI_PWR_D1|PCI_PWR_D2|PCI_PWR_D3); 2375 pm_ctl |= (1 << 8) | PCI_PWR_D0 ; /* D0 state */ 2376 pci_conf_write(pc, sc->sc_pcitag, BGE_PCI_PWRMGMT_CMD, pm_ctl); 2377 DELAY(1000); /* 27 usec is allegedly sufficent */ 2378 2379 /* 2380 * Save ASIC rev. Look up any quirks associated with this 2381 * ASIC. 2382 */ 2383 sc->bge_chipid = 2384 pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MISC_CTL) & 2385 BGE_PCIMISCCTL_ASICREV; 2386 2387 /* 2388 * Detect PCI-Express devices 2389 * XXX: guessed from Linux/FreeBSD; no documentation 2390 */ 2391 if (pci_get_capability(sc->sc_pc, sc->sc_pcitag, PCI_CAP_PCIEXPRESS, 2392 NULL, NULL) != 0) 2393 sc->bge_flags |= BGE_PCIE; 2394 2395 /* 2396 * PCI-X check. 2397 */ 2398 if ((pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_PCISTATE) & 2399 BGE_PCISTATE_PCI_BUSMODE) == 0) 2400 sc->bge_flags |= BGE_PCIX; 2401 2402 /* Try to reset the chip. */ 2403 DPRINTFN(5, ("bge_reset\n")); 2404 bge_reset(sc); 2405 2406 if (bge_chipinit(sc)) { 2407 aprint_error_dev(sc->bge_dev, "chip initialization failed\n"); 2408 bge_release_resources(sc); 2409 return; 2410 } 2411 2412 /* 2413 * Get station address from the EEPROM. 2414 */ 2415 if (bge_get_eaddr(sc, eaddr)) { 2416 aprint_error_dev(sc->bge_dev, 2417 "failed to reade station address\n"); 2418 bge_release_resources(sc); 2419 return; 2420 } 2421 2422 br = bge_lookup_rev(sc->bge_chipid); 2423 2424 if (br == NULL) { 2425 aprint_normal_dev(sc->bge_dev, "unknown ASIC (0x%04x)", 2426 sc->bge_chipid >> 16); 2427 } else { 2428 aprint_normal_dev(sc->bge_dev, "ASIC %s (0x%04x)", 2429 br->br_name, sc->bge_chipid >> 16); 2430 } 2431 aprint_normal(", Ethernet address %s\n", ether_sprintf(eaddr)); 2432 2433 /* Allocate the general information block and ring buffers. */ 2434 if (pci_dma64_available(pa)) 2435 sc->bge_dmatag = pa->pa_dmat64; 2436 else 2437 sc->bge_dmatag = pa->pa_dmat; 2438 DPRINTFN(5, ("bus_dmamem_alloc\n")); 2439 if (bus_dmamem_alloc(sc->bge_dmatag, sizeof(struct bge_ring_data), 2440 PAGE_SIZE, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 2441 aprint_error_dev(sc->bge_dev, "can't alloc rx buffers\n"); 2442 return; 2443 } 2444 DPRINTFN(5, ("bus_dmamem_map\n")); 2445 if (bus_dmamem_map(sc->bge_dmatag, &seg, rseg, 2446 sizeof(struct bge_ring_data), &kva, 2447 BUS_DMA_NOWAIT)) { 2448 aprint_error_dev(sc->bge_dev, 2449 "can't map DMA buffers (%zu bytes)\n", 2450 sizeof(struct bge_ring_data)); 2451 bus_dmamem_free(sc->bge_dmatag, &seg, rseg); 2452 return; 2453 } 2454 DPRINTFN(5, ("bus_dmamem_create\n")); 2455 if (bus_dmamap_create(sc->bge_dmatag, sizeof(struct bge_ring_data), 1, 2456 sizeof(struct bge_ring_data), 0, 2457 BUS_DMA_NOWAIT, &sc->bge_ring_map)) { 2458 aprint_error_dev(sc->bge_dev, "can't create DMA map\n"); 2459 bus_dmamem_unmap(sc->bge_dmatag, kva, 2460 sizeof(struct bge_ring_data)); 2461 bus_dmamem_free(sc->bge_dmatag, &seg, rseg); 2462 return; 2463 } 2464 DPRINTFN(5, ("bus_dmamem_load\n")); 2465 if (bus_dmamap_load(sc->bge_dmatag, sc->bge_ring_map, kva, 2466 sizeof(struct bge_ring_data), NULL, 2467 BUS_DMA_NOWAIT)) { 2468 bus_dmamap_destroy(sc->bge_dmatag, sc->bge_ring_map); 2469 bus_dmamem_unmap(sc->bge_dmatag, kva, 2470 sizeof(struct bge_ring_data)); 2471 bus_dmamem_free(sc->bge_dmatag, &seg, rseg); 2472 return; 2473 } 2474 2475 DPRINTFN(5, ("bzero\n")); 2476 sc->bge_rdata = (struct bge_ring_data *)kva; 2477 2478 memset(sc->bge_rdata, 0, sizeof(struct bge_ring_data)); 2479 2480 /* Try to allocate memory for jumbo buffers. */ 2481 if (!(BGE_IS_5705_OR_BEYOND(sc))) { 2482 if (bge_alloc_jumbo_mem(sc)) { 2483 aprint_error_dev(sc->bge_dev, 2484 "jumbo buffer allocation failed\n"); 2485 } else 2486 sc->ethercom.ec_capabilities |= ETHERCAP_JUMBO_MTU; 2487 } 2488 2489 /* Set default tuneable values. */ 2490 sc->bge_stat_ticks = BGE_TICKS_PER_SEC; 2491 sc->bge_rx_coal_ticks = 150; 2492 sc->bge_rx_max_coal_bds = 64; 2493 #ifdef ORIG_WPAUL_VALUES 2494 sc->bge_tx_coal_ticks = 150; 2495 sc->bge_tx_max_coal_bds = 128; 2496 #else 2497 sc->bge_tx_coal_ticks = 300; 2498 sc->bge_tx_max_coal_bds = 400; 2499 #endif 2500 if (BGE_IS_5705_OR_BEYOND(sc)) { 2501 sc->bge_tx_coal_ticks = (12 * 5); 2502 sc->bge_tx_max_coal_bds = (12 * 5); 2503 aprint_verbose_dev(sc->bge_dev, 2504 "setting short Tx thresholds\n"); 2505 } 2506 2507 /* Set up ifnet structure */ 2508 ifp = &sc->ethercom.ec_if; 2509 ifp->if_softc = sc; 2510 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 2511 ifp->if_ioctl = bge_ioctl; 2512 ifp->if_stop = bge_stop; 2513 ifp->if_start = bge_start; 2514 ifp->if_init = bge_init; 2515 ifp->if_watchdog = bge_watchdog; 2516 IFQ_SET_MAXLEN(&ifp->if_snd, max(BGE_TX_RING_CNT - 1, IFQ_MAXLEN)); 2517 IFQ_SET_READY(&ifp->if_snd); 2518 DPRINTFN(5, ("strcpy if_xname\n")); 2519 strcpy(ifp->if_xname, device_xname(sc->bge_dev)); 2520 2521 if (sc->bge_chipid != BGE_CHIPID_BCM5700_B0) 2522 sc->ethercom.ec_if.if_capabilities |= 2523 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 2524 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 2525 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 2526 sc->ethercom.ec_capabilities |= 2527 ETHERCAP_VLAN_HWTAGGING | ETHERCAP_VLAN_MTU; 2528 2529 if (sc->bge_flags & BGE_PCIE) 2530 sc->ethercom.ec_if.if_capabilities |= IFCAP_TSOv4; 2531 2532 /* 2533 * Do MII setup. 2534 */ 2535 DPRINTFN(5, ("mii setup\n")); 2536 sc->bge_mii.mii_ifp = ifp; 2537 sc->bge_mii.mii_readreg = bge_miibus_readreg; 2538 sc->bge_mii.mii_writereg = bge_miibus_writereg; 2539 sc->bge_mii.mii_statchg = bge_miibus_statchg; 2540 2541 /* 2542 * Figure out what sort of media we have by checking the 2543 * hardware config word in the first 32k of NIC internal memory, 2544 * or fall back to the config word in the EEPROM. Note: on some BCM5700 2545 * cards, this value appears to be unset. If that's the 2546 * case, we have to rely on identifying the NIC by its PCI 2547 * subsystem ID, as we do below for the SysKonnect SK-9D41. 2548 */ 2549 if (bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_SIG) == BGE_MAGIC_NUMBER) { 2550 hwcfg = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_NICCFG); 2551 } else { 2552 bge_read_eeprom(sc, (void *)&hwcfg, 2553 BGE_EE_HWCFG_OFFSET, sizeof(hwcfg)); 2554 hwcfg = be32toh(hwcfg); 2555 } 2556 if ((hwcfg & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER) 2557 sc->bge_flags |= BGE_PHY_FIBER_TBI; 2558 2559 /* The SysKonnect SK-9D41 is a 1000baseSX card. */ 2560 if ((pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_SUBSYS) >> 16) == 2561 SK_SUBSYSID_9D41) 2562 sc->bge_flags |= BGE_PHY_FIBER_TBI; 2563 2564 if (sc->bge_flags & BGE_PHY_FIBER_TBI) { 2565 ifmedia_init(&sc->bge_ifmedia, IFM_IMASK, bge_ifmedia_upd, 2566 bge_ifmedia_sts); 2567 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL); 2568 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_1000_SX|IFM_FDX, 2569 0, NULL); 2570 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL); 2571 ifmedia_set(&sc->bge_ifmedia, IFM_ETHER|IFM_AUTO); 2572 /* Pretend the user requested this setting */ 2573 sc->bge_ifmedia.ifm_media = 2574 sc->bge_ifmedia.ifm_cur->ifm_media; 2575 } else { 2576 /* 2577 * Do transceiver setup. 2578 */ 2579 ifmedia_init(&sc->bge_mii.mii_media, 0, bge_ifmedia_upd, 2580 bge_ifmedia_sts); 2581 mii_attach(sc->bge_dev, &sc->bge_mii, 0xffffffff, 2582 MII_PHY_ANY, MII_OFFSET_ANY, 2583 MIIF_FORCEANEG|MIIF_DOPAUSE); 2584 2585 if (LIST_EMPTY(&sc->bge_mii.mii_phys)) { 2586 aprint_error_dev(sc->bge_dev, "no PHY found!\n"); 2587 ifmedia_add(&sc->bge_mii.mii_media, 2588 IFM_ETHER|IFM_MANUAL, 0, NULL); 2589 ifmedia_set(&sc->bge_mii.mii_media, 2590 IFM_ETHER|IFM_MANUAL); 2591 } else 2592 ifmedia_set(&sc->bge_mii.mii_media, 2593 IFM_ETHER|IFM_AUTO); 2594 } 2595 2596 /* 2597 * When using the BCM5701 in PCI-X mode, data corruption has 2598 * been observed in the first few bytes of some received packets. 2599 * Aligning the packet buffer in memory eliminates the corruption. 2600 * Unfortunately, this misaligns the packet payloads. On platforms 2601 * which do not support unaligned accesses, we will realign the 2602 * payloads by copying the received packets. 2603 */ 2604 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5701 && 2605 sc->bge_flags & BGE_PCIX) 2606 sc->bge_flags |= BGE_RX_ALIGNBUG; 2607 2608 /* 2609 * Call MI attach routine. 2610 */ 2611 DPRINTFN(5, ("if_attach\n")); 2612 if_attach(ifp); 2613 DPRINTFN(5, ("ether_ifattach\n")); 2614 ether_ifattach(ifp, eaddr); 2615 #if NRND > 0 2616 rnd_attach_source(&sc->rnd_source, device_xname(sc->bge_dev), 2617 RND_TYPE_NET, 0); 2618 #endif 2619 #ifdef BGE_EVENT_COUNTERS 2620 /* 2621 * Attach event counters. 2622 */ 2623 evcnt_attach_dynamic(&sc->bge_ev_intr, EVCNT_TYPE_INTR, 2624 NULL, device_xname(sc->bge_dev), "intr"); 2625 evcnt_attach_dynamic(&sc->bge_ev_tx_xoff, EVCNT_TYPE_MISC, 2626 NULL, device_xname(sc->bge_dev), "tx_xoff"); 2627 evcnt_attach_dynamic(&sc->bge_ev_tx_xon, EVCNT_TYPE_MISC, 2628 NULL, device_xname(sc->bge_dev), "tx_xon"); 2629 evcnt_attach_dynamic(&sc->bge_ev_rx_xoff, EVCNT_TYPE_MISC, 2630 NULL, device_xname(sc->bge_dev), "rx_xoff"); 2631 evcnt_attach_dynamic(&sc->bge_ev_rx_xon, EVCNT_TYPE_MISC, 2632 NULL, device_xname(sc->bge_dev), "rx_xon"); 2633 evcnt_attach_dynamic(&sc->bge_ev_rx_macctl, EVCNT_TYPE_MISC, 2634 NULL, device_xname(sc->bge_dev), "rx_macctl"); 2635 evcnt_attach_dynamic(&sc->bge_ev_xoffentered, EVCNT_TYPE_MISC, 2636 NULL, device_xname(sc->bge_dev), "xoffentered"); 2637 #endif /* BGE_EVENT_COUNTERS */ 2638 DPRINTFN(5, ("callout_init\n")); 2639 callout_init(&sc->bge_timeout, 0); 2640 2641 if (!pmf_device_register(self, NULL, NULL)) 2642 aprint_error_dev(self, "couldn't establish power handler\n"); 2643 else 2644 pmf_class_network_register(self, ifp); 2645 } 2646 2647 static void 2648 bge_release_resources(struct bge_softc *sc) 2649 { 2650 if (sc->bge_vpd_prodname != NULL) 2651 free(sc->bge_vpd_prodname, M_DEVBUF); 2652 2653 if (sc->bge_vpd_readonly != NULL) 2654 free(sc->bge_vpd_readonly, M_DEVBUF); 2655 } 2656 2657 static void 2658 bge_reset(struct bge_softc *sc) 2659 { 2660 u_int32_t cachesize, command, pcistate, new_pcistate; 2661 int i, val; 2662 void (*write_op)(struct bge_softc *, int, int); 2663 2664 if (BGE_IS_5750_OR_BEYOND(sc) && !BGE_IS_5714_FAMILY(sc) && 2665 (BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5906)) { 2666 if (sc->bge_flags & BGE_PCIE) { 2667 write_op = bge_writemem_direct; 2668 } else { 2669 write_op = bge_writemem_ind; 2670 } 2671 } else { 2672 write_op = bge_writereg_ind; 2673 } 2674 2675 2676 /* Save some important PCI state. */ 2677 cachesize = pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CACHESZ); 2678 command = pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CMD); 2679 pcistate = pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_PCISTATE); 2680 2681 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MISC_CTL, 2682 BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR| 2683 BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_PCISTATE_RW); 2684 2685 /* 2686 * Disable the firmware fastboot feature on 5752 ASIC 2687 * to avoid firmware timeout. 2688 */ 2689 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5752 || 2690 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5755 || 2691 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5787) 2692 CSR_WRITE_4(sc, BGE_FASTBOOT_PC, 0); 2693 2694 val = BGE_MISCCFG_RESET_CORE_CLOCKS | (65<<1); 2695 /* 2696 * XXX: from FreeBSD/Linux; no documentation 2697 */ 2698 if (sc->bge_flags & BGE_PCIE) { 2699 if (CSR_READ_4(sc, BGE_PCIE_CTL1) == 0x60) 2700 /* PCI Express 1.0 system */ 2701 CSR_WRITE_4(sc, BGE_PCIE_CTL1, 0x20); 2702 if (sc->bge_chipid != BGE_CHIPID_BCM5750_A0) { 2703 /* 2704 * Prevent PCI Express link training 2705 * during global reset. 2706 */ 2707 CSR_WRITE_4(sc, BGE_MISC_CFG, 1 << 29); 2708 val |= (1<<29); 2709 } 2710 } 2711 2712 /* Issue global reset */ 2713 write_op(sc, BGE_MISC_CFG, val); 2714 2715 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 2716 i = CSR_READ_4(sc, BGE_VCPU_STATUS); 2717 CSR_WRITE_4(sc, BGE_VCPU_STATUS, 2718 i | BGE_VCPU_STATUS_DRV_RESET); 2719 i = CSR_READ_4(sc, BGE_VCPU_EXT_CTRL); 2720 CSR_WRITE_4(sc, BGE_VCPU_EXT_CTRL, 2721 i & ~BGE_VCPU_EXT_CTRL_HALT_CPU); 2722 } 2723 2724 2725 2726 DELAY(1000); 2727 2728 /* 2729 * XXX: from FreeBSD/Linux; no documentation 2730 */ 2731 if (sc->bge_flags & BGE_PCIE) { 2732 if (sc->bge_chipid == BGE_CHIPID_BCM5750_A0) { 2733 pcireg_t reg; 2734 2735 DELAY(500000); 2736 /* XXX: Magic Numbers */ 2737 reg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_UNKNOWN0); 2738 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_UNKNOWN0, 2739 reg | (1 << 15)); 2740 } 2741 /* 2742 * XXX: Magic Numbers. 2743 * Sets maximal PCI-e payload and clears any PCI-e errors. 2744 * Should be replaced with references to PCI config-space 2745 * capability block for PCI-Express. 2746 */ 2747 pci_conf_write(sc->sc_pc, sc->sc_pcitag, 2748 BGE_PCI_CONF_DEV_CTRL, 0xf5000); 2749 2750 } 2751 2752 /* Reset some of the PCI state that got zapped by reset */ 2753 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MISC_CTL, 2754 BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR| 2755 BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_PCISTATE_RW); 2756 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CMD, command); 2757 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CACHESZ, cachesize); 2758 write_op(sc, BGE_MISC_CFG, (65 << 1)); 2759 2760 /* Enable memory arbiter. */ 2761 { 2762 uint32_t marbmode = 0; 2763 if (BGE_IS_5714_FAMILY(sc)) { 2764 marbmode = CSR_READ_4(sc, BGE_MARB_MODE); 2765 } 2766 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE | marbmode); 2767 } 2768 2769 2770 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 2771 for (i = 0; i < BGE_TIMEOUT; i++) { 2772 val = CSR_READ_4(sc, BGE_VCPU_STATUS); 2773 if (val & BGE_VCPU_STATUS_INIT_DONE) 2774 break; 2775 DELAY(100); 2776 } 2777 if (i == BGE_TIMEOUT) { 2778 aprint_error_dev(sc->bge_dev, "reset timed out\n"); 2779 return; 2780 } 2781 } else { 2782 /* 2783 * Write the magic number to the firmware mailbox at 0xb50 2784 * so that the driver can synchronize with the firmware. 2785 */ 2786 bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM, BGE_MAGIC_NUMBER); 2787 2788 /* 2789 * Poll the value location we just wrote until 2790 * we see the 1's complement of the magic number. 2791 * This indicates that the firmware initialization 2792 * is complete. 2793 */ 2794 for (i = 0; i < BGE_TIMEOUT; i++) { 2795 val = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM); 2796 if (val == ~BGE_MAGIC_NUMBER) 2797 break; 2798 DELAY(1000); 2799 } 2800 2801 if (i >= BGE_TIMEOUT) { 2802 aprint_error_dev(sc->bge_dev, 2803 "firmware handshake timed out, val = %x\n", val); 2804 /* 2805 * XXX: occasionally fired on bcm5721, but without 2806 * apparent harm. For now, keep going if we timeout 2807 * against PCI-E devices. 2808 */ 2809 if ((sc->bge_flags & BGE_PCIE) == 0) 2810 return; 2811 } 2812 } 2813 2814 /* 2815 * XXX Wait for the value of the PCISTATE register to 2816 * return to its original pre-reset state. This is a 2817 * fairly good indicator of reset completion. If we don't 2818 * wait for the reset to fully complete, trying to read 2819 * from the device's non-PCI registers may yield garbage 2820 * results. 2821 */ 2822 for (i = 0; i < 10000; i++) { 2823 new_pcistate = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 2824 BGE_PCI_PCISTATE); 2825 if ((new_pcistate & ~BGE_PCISTATE_RESERVED) == 2826 (pcistate & ~BGE_PCISTATE_RESERVED)) 2827 break; 2828 DELAY(10); 2829 } 2830 if ((new_pcistate & ~BGE_PCISTATE_RESERVED) != 2831 (pcistate & ~BGE_PCISTATE_RESERVED)) { 2832 aprint_error_dev(sc->bge_dev, "pcistate failed to revert\n"); 2833 } 2834 2835 /* XXX: from FreeBSD/Linux; no documentation */ 2836 if (sc->bge_flags & BGE_PCIE && 2837 sc->bge_chipid != BGE_CHIPID_BCM5750_A0) 2838 CSR_WRITE_4(sc, BGE_PCIE_CTL0, CSR_READ_4(sc, BGE_PCIE_CTL0) | (1<<25)); 2839 2840 /* Enable memory arbiter. */ 2841 /* XXX why do this twice? */ 2842 { 2843 uint32_t marbmode = 0; 2844 if (BGE_IS_5714_FAMILY(sc)) { 2845 marbmode = CSR_READ_4(sc, BGE_MARB_MODE); 2846 } 2847 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE | marbmode); 2848 } 2849 2850 /* Fix up byte swapping */ 2851 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS); 2852 2853 CSR_WRITE_4(sc, BGE_MAC_MODE, 0); 2854 2855 DELAY(10000); 2856 } 2857 2858 /* 2859 * Frame reception handling. This is called if there's a frame 2860 * on the receive return list. 2861 * 2862 * Note: we have to be able to handle two possibilities here: 2863 * 1) the frame is from the jumbo recieve ring 2864 * 2) the frame is from the standard receive ring 2865 */ 2866 2867 static void 2868 bge_rxeof(struct bge_softc *sc) 2869 { 2870 struct ifnet *ifp; 2871 int stdcnt = 0, jumbocnt = 0; 2872 bus_dmamap_t dmamap; 2873 bus_addr_t offset, toff; 2874 bus_size_t tlen; 2875 int tosync; 2876 2877 ifp = &sc->ethercom.ec_if; 2878 2879 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 2880 offsetof(struct bge_ring_data, bge_status_block), 2881 sizeof (struct bge_status_block), 2882 BUS_DMASYNC_POSTREAD); 2883 2884 offset = offsetof(struct bge_ring_data, bge_rx_return_ring); 2885 tosync = sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx - 2886 sc->bge_rx_saved_considx; 2887 2888 #if NRND > 0 2889 if (tosync != 0 && RND_ENABLED(&sc->rnd_source)) 2890 rnd_add_uint32(&sc->rnd_source, tosync); 2891 #endif 2892 2893 toff = offset + (sc->bge_rx_saved_considx * sizeof (struct bge_rx_bd)); 2894 2895 if (tosync < 0) { 2896 tlen = (sc->bge_return_ring_cnt - sc->bge_rx_saved_considx) * 2897 sizeof (struct bge_rx_bd); 2898 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 2899 toff, tlen, BUS_DMASYNC_POSTREAD); 2900 tosync = -tosync; 2901 } 2902 2903 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 2904 offset, tosync * sizeof (struct bge_rx_bd), 2905 BUS_DMASYNC_POSTREAD); 2906 2907 while(sc->bge_rx_saved_considx != 2908 sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx) { 2909 struct bge_rx_bd *cur_rx; 2910 u_int32_t rxidx; 2911 struct mbuf *m = NULL; 2912 2913 cur_rx = &sc->bge_rdata-> 2914 bge_rx_return_ring[sc->bge_rx_saved_considx]; 2915 2916 rxidx = cur_rx->bge_idx; 2917 BGE_INC(sc->bge_rx_saved_considx, sc->bge_return_ring_cnt); 2918 2919 if (cur_rx->bge_flags & BGE_RXBDFLAG_JUMBO_RING) { 2920 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT); 2921 m = sc->bge_cdata.bge_rx_jumbo_chain[rxidx]; 2922 sc->bge_cdata.bge_rx_jumbo_chain[rxidx] = NULL; 2923 jumbocnt++; 2924 bus_dmamap_sync(sc->bge_dmatag, 2925 sc->bge_cdata.bge_rx_jumbo_map, 2926 mtod(m, char *) - (char *)sc->bge_cdata.bge_jumbo_buf, 2927 BGE_JLEN, BUS_DMASYNC_POSTREAD); 2928 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 2929 ifp->if_ierrors++; 2930 bge_newbuf_jumbo(sc, sc->bge_jumbo, m); 2931 continue; 2932 } 2933 if (bge_newbuf_jumbo(sc, sc->bge_jumbo, 2934 NULL)== ENOBUFS) { 2935 ifp->if_ierrors++; 2936 bge_newbuf_jumbo(sc, sc->bge_jumbo, m); 2937 continue; 2938 } 2939 } else { 2940 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT); 2941 m = sc->bge_cdata.bge_rx_std_chain[rxidx]; 2942 2943 sc->bge_cdata.bge_rx_std_chain[rxidx] = NULL; 2944 stdcnt++; 2945 dmamap = sc->bge_cdata.bge_rx_std_map[rxidx]; 2946 sc->bge_cdata.bge_rx_std_map[rxidx] = 0; 2947 bus_dmamap_sync(sc->bge_dmatag, dmamap, 0, 2948 dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 2949 bus_dmamap_unload(sc->bge_dmatag, dmamap); 2950 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 2951 ifp->if_ierrors++; 2952 bge_newbuf_std(sc, sc->bge_std, m, dmamap); 2953 continue; 2954 } 2955 if (bge_newbuf_std(sc, sc->bge_std, 2956 NULL, dmamap) == ENOBUFS) { 2957 ifp->if_ierrors++; 2958 bge_newbuf_std(sc, sc->bge_std, m, dmamap); 2959 continue; 2960 } 2961 } 2962 2963 ifp->if_ipackets++; 2964 #ifndef __NO_STRICT_ALIGNMENT 2965 /* 2966 * XXX: if the 5701 PCIX-Rx-DMA workaround is in effect, 2967 * the Rx buffer has the layer-2 header unaligned. 2968 * If our CPU requires alignment, re-align by copying. 2969 */ 2970 if (sc->bge_flags & BGE_RX_ALIGNBUG) { 2971 memmove(mtod(m, char *) + ETHER_ALIGN, m->m_data, 2972 cur_rx->bge_len); 2973 m->m_data += ETHER_ALIGN; 2974 } 2975 #endif 2976 2977 m->m_pkthdr.len = m->m_len = cur_rx->bge_len - ETHER_CRC_LEN; 2978 m->m_pkthdr.rcvif = ifp; 2979 2980 #if NBPFILTER > 0 2981 /* 2982 * Handle BPF listeners. Let the BPF user see the packet. 2983 */ 2984 if (ifp->if_bpf) 2985 bpf_mtap(ifp->if_bpf, m); 2986 #endif 2987 2988 m->m_pkthdr.csum_flags = M_CSUM_IPv4; 2989 2990 if ((cur_rx->bge_ip_csum ^ 0xffff) != 0) 2991 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 2992 /* 2993 * Rx transport checksum-offload may also 2994 * have bugs with packets which, when transmitted, 2995 * were `runts' requiring padding. 2996 */ 2997 if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM && 2998 (/* (sc->_bge_quirks & BGE_QUIRK_SHORT_CKSUM_BUG) == 0 ||*/ 2999 m->m_pkthdr.len >= ETHER_MIN_NOPAD)) { 3000 m->m_pkthdr.csum_data = 3001 cur_rx->bge_tcp_udp_csum; 3002 m->m_pkthdr.csum_flags |= 3003 (M_CSUM_TCPv4|M_CSUM_UDPv4| 3004 M_CSUM_DATA|M_CSUM_NO_PSEUDOHDR); 3005 } 3006 3007 /* 3008 * If we received a packet with a vlan tag, pass it 3009 * to vlan_input() instead of ether_input(). 3010 */ 3011 if (cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) { 3012 VLAN_INPUT_TAG(ifp, m, cur_rx->bge_vlan_tag, continue); 3013 } 3014 3015 (*ifp->if_input)(ifp, m); 3016 } 3017 3018 bge_writembx(sc, BGE_MBX_RX_CONS0_LO, sc->bge_rx_saved_considx); 3019 if (stdcnt) 3020 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std); 3021 if (jumbocnt) 3022 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo); 3023 } 3024 3025 static void 3026 bge_txeof(struct bge_softc *sc) 3027 { 3028 struct bge_tx_bd *cur_tx = NULL; 3029 struct ifnet *ifp; 3030 struct txdmamap_pool_entry *dma; 3031 bus_addr_t offset, toff; 3032 bus_size_t tlen; 3033 int tosync; 3034 struct mbuf *m; 3035 3036 ifp = &sc->ethercom.ec_if; 3037 3038 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 3039 offsetof(struct bge_ring_data, bge_status_block), 3040 sizeof (struct bge_status_block), 3041 BUS_DMASYNC_POSTREAD); 3042 3043 offset = offsetof(struct bge_ring_data, bge_tx_ring); 3044 tosync = sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx - 3045 sc->bge_tx_saved_considx; 3046 3047 #if NRND > 0 3048 if (tosync != 0 && RND_ENABLED(&sc->rnd_source)) 3049 rnd_add_uint32(&sc->rnd_source, tosync); 3050 #endif 3051 3052 toff = offset + (sc->bge_tx_saved_considx * sizeof (struct bge_tx_bd)); 3053 3054 if (tosync < 0) { 3055 tlen = (BGE_TX_RING_CNT - sc->bge_tx_saved_considx) * 3056 sizeof (struct bge_tx_bd); 3057 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 3058 toff, tlen, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 3059 tosync = -tosync; 3060 } 3061 3062 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 3063 offset, tosync * sizeof (struct bge_tx_bd), 3064 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 3065 3066 /* 3067 * Go through our tx ring and free mbufs for those 3068 * frames that have been sent. 3069 */ 3070 while (sc->bge_tx_saved_considx != 3071 sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx) { 3072 u_int32_t idx = 0; 3073 3074 idx = sc->bge_tx_saved_considx; 3075 cur_tx = &sc->bge_rdata->bge_tx_ring[idx]; 3076 if (cur_tx->bge_flags & BGE_TXBDFLAG_END) 3077 ifp->if_opackets++; 3078 m = sc->bge_cdata.bge_tx_chain[idx]; 3079 if (m != NULL) { 3080 sc->bge_cdata.bge_tx_chain[idx] = NULL; 3081 dma = sc->txdma[idx]; 3082 bus_dmamap_sync(sc->bge_dmatag, dma->dmamap, 0, 3083 dma->dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 3084 bus_dmamap_unload(sc->bge_dmatag, dma->dmamap); 3085 SLIST_INSERT_HEAD(&sc->txdma_list, dma, link); 3086 sc->txdma[idx] = NULL; 3087 3088 m_freem(m); 3089 } 3090 sc->bge_txcnt--; 3091 BGE_INC(sc->bge_tx_saved_considx, BGE_TX_RING_CNT); 3092 ifp->if_timer = 0; 3093 } 3094 3095 if (cur_tx != NULL) 3096 ifp->if_flags &= ~IFF_OACTIVE; 3097 } 3098 3099 static int 3100 bge_intr(void *xsc) 3101 { 3102 struct bge_softc *sc; 3103 struct ifnet *ifp; 3104 3105 sc = xsc; 3106 ifp = &sc->ethercom.ec_if; 3107 3108 /* 3109 * Ascertain whether the interrupt is from this bge device. 3110 * Do the cheap test first. 3111 */ 3112 if ((sc->bge_rdata->bge_status_block.bge_status & 3113 BGE_STATFLAG_UPDATED) == 0) { 3114 /* 3115 * Sometimes, the interrupt comes in before the 3116 * DMA update of the status block (performed prior 3117 * to the interrupt itself) has completed. 3118 * In that case, do the (extremely expensive!) 3119 * PCI-config-space register read. 3120 */ 3121 uint32_t pcistate = 3122 pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_PCISTATE); 3123 3124 if (pcistate & BGE_PCISTATE_INTR_STATE) 3125 return (0); 3126 3127 } 3128 /* 3129 * If we reach here, then the interrupt is for us. 3130 */ 3131 3132 /* Ack interrupt and stop others from occuring. */ 3133 bge_writembx(sc, BGE_MBX_IRQ0_LO, 1); 3134 3135 BGE_EVCNT_INCR(sc->bge_ev_intr); 3136 3137 /* 3138 * Process link state changes. 3139 * Grrr. The link status word in the status block does 3140 * not work correctly on the BCM5700 rev AX and BX chips, 3141 * according to all available information. Hence, we have 3142 * to enable MII interrupts in order to properly obtain 3143 * async link changes. Unfortunately, this also means that 3144 * we have to read the MAC status register to detect link 3145 * changes, thereby adding an additional register access to 3146 * the interrupt handler. 3147 */ 3148 3149 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700) { 3150 u_int32_t status; 3151 3152 status = CSR_READ_4(sc, BGE_MAC_STS); 3153 if (status & BGE_MACSTAT_MI_INTERRUPT) { 3154 sc->bge_link = 0; 3155 callout_stop(&sc->bge_timeout); 3156 bge_tick(sc); 3157 /* Clear the interrupt */ 3158 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, 3159 BGE_EVTENB_MI_INTERRUPT); 3160 bge_miibus_readreg(sc->bge_dev, 1, BRGPHY_MII_ISR); 3161 bge_miibus_writereg(sc->bge_dev, 1, BRGPHY_MII_IMR, 3162 BRGPHY_INTRS); 3163 } 3164 } else { 3165 u_int32_t status; 3166 3167 status = CSR_READ_4(sc, BGE_MAC_STS); 3168 if (status & BGE_MACSTAT_LINK_CHANGED) { 3169 sc->bge_link = 0; 3170 callout_stop(&sc->bge_timeout); 3171 bge_tick(sc); 3172 /* Clear the interrupt */ 3173 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED| 3174 BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE| 3175 BGE_MACSTAT_LINK_CHANGED); 3176 } 3177 } 3178 3179 if (ifp->if_flags & IFF_RUNNING) { 3180 /* Check RX return ring producer/consumer */ 3181 bge_rxeof(sc); 3182 3183 /* Check TX ring producer/consumer */ 3184 bge_txeof(sc); 3185 } 3186 3187 if (sc->bge_pending_rxintr_change) { 3188 uint32_t rx_ticks = sc->bge_rx_coal_ticks; 3189 uint32_t rx_bds = sc->bge_rx_max_coal_bds; 3190 uint32_t junk; 3191 3192 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, rx_ticks); 3193 DELAY(10); 3194 junk = CSR_READ_4(sc, BGE_HCC_RX_COAL_TICKS); 3195 3196 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, rx_bds); 3197 DELAY(10); 3198 junk = CSR_READ_4(sc, BGE_HCC_RX_MAX_COAL_BDS); 3199 3200 sc->bge_pending_rxintr_change = 0; 3201 } 3202 bge_handle_events(sc); 3203 3204 /* Re-enable interrupts. */ 3205 bge_writembx(sc, BGE_MBX_IRQ0_LO, 0); 3206 3207 if (ifp->if_flags & IFF_RUNNING && !IFQ_IS_EMPTY(&ifp->if_snd)) 3208 bge_start(ifp); 3209 3210 return (1); 3211 } 3212 3213 static void 3214 bge_tick(void *xsc) 3215 { 3216 struct bge_softc *sc = xsc; 3217 struct mii_data *mii = &sc->bge_mii; 3218 int s; 3219 3220 s = splnet(); 3221 3222 bge_stats_update(sc); 3223 callout_reset(&sc->bge_timeout, hz, bge_tick, sc); 3224 3225 if (sc->bge_flags & BGE_PHY_FIBER_TBI) { 3226 if (CSR_READ_4(sc, BGE_MAC_STS) & 3227 BGE_MACSTAT_TBI_PCS_SYNCHED) { 3228 CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF); 3229 } 3230 } else 3231 mii_tick(mii); 3232 3233 splx(s); 3234 } 3235 3236 static void 3237 bge_stats_update(struct bge_softc *sc) 3238 { 3239 struct ifnet *ifp = &sc->ethercom.ec_if; 3240 bus_size_t stats = BGE_MEMWIN_START + BGE_STATS_BLOCK; 3241 bus_size_t rstats = BGE_RX_STATS; 3242 3243 #define READ_RSTAT(sc, stats, stat) \ 3244 CSR_READ_4(sc, stats + offsetof(struct bge_mac_stats_regs, stat)) 3245 3246 if (BGE_IS_5705_OR_BEYOND(sc)) { 3247 ifp->if_collisions += 3248 READ_RSTAT(sc, rstats, dot3StatsSingleCollisionFrames) + 3249 READ_RSTAT(sc, rstats, dot3StatsMultipleCollisionFrames) + 3250 READ_RSTAT(sc, rstats, dot3StatsExcessiveCollisions) + 3251 READ_RSTAT(sc, rstats, dot3StatsLateCollisions); 3252 3253 BGE_EVCNT_ADD(sc->bge_ev_tx_xoff, 3254 READ_RSTAT(sc, rstats, outXoffSent)); 3255 BGE_EVCNT_ADD(sc->bge_ev_tx_xon, 3256 READ_RSTAT(sc, rstats, outXonSent)); 3257 BGE_EVCNT_ADD(sc->bge_ev_rx_xoff, 3258 READ_RSTAT(sc, rstats, xoffPauseFramesReceived)); 3259 BGE_EVCNT_ADD(sc->bge_ev_rx_xon, 3260 READ_RSTAT(sc, rstats, xonPauseFramesReceived)); 3261 BGE_EVCNT_ADD(sc->bge_ev_rx_macctl, 3262 READ_RSTAT(sc, rstats, macControlFramesReceived)); 3263 BGE_EVCNT_ADD(sc->bge_ev_xoffentered, 3264 READ_RSTAT(sc, rstats, xoffStateEntered)); 3265 return; 3266 } 3267 3268 #undef READ_RSTAT 3269 #define READ_STAT(sc, stats, stat) \ 3270 CSR_READ_4(sc, stats + offsetof(struct bge_stats, stat)) 3271 3272 ifp->if_collisions += 3273 (READ_STAT(sc, stats, dot3StatsSingleCollisionFrames.bge_addr_lo) + 3274 READ_STAT(sc, stats, dot3StatsMultipleCollisionFrames.bge_addr_lo) + 3275 READ_STAT(sc, stats, dot3StatsExcessiveCollisions.bge_addr_lo) + 3276 READ_STAT(sc, stats, dot3StatsLateCollisions.bge_addr_lo)) - 3277 ifp->if_collisions; 3278 3279 BGE_EVCNT_UPD(sc->bge_ev_tx_xoff, 3280 READ_STAT(sc, stats, outXoffSent.bge_addr_lo)); 3281 BGE_EVCNT_UPD(sc->bge_ev_tx_xon, 3282 READ_STAT(sc, stats, outXonSent.bge_addr_lo)); 3283 BGE_EVCNT_UPD(sc->bge_ev_rx_xoff, 3284 READ_STAT(sc, stats, 3285 xoffPauseFramesReceived.bge_addr_lo)); 3286 BGE_EVCNT_UPD(sc->bge_ev_rx_xon, 3287 READ_STAT(sc, stats, xonPauseFramesReceived.bge_addr_lo)); 3288 BGE_EVCNT_UPD(sc->bge_ev_rx_macctl, 3289 READ_STAT(sc, stats, 3290 macControlFramesReceived.bge_addr_lo)); 3291 BGE_EVCNT_UPD(sc->bge_ev_xoffentered, 3292 READ_STAT(sc, stats, xoffStateEntered.bge_addr_lo)); 3293 3294 #undef READ_STAT 3295 3296 #ifdef notdef 3297 ifp->if_collisions += 3298 (sc->bge_rdata->bge_info.bge_stats.dot3StatsSingleCollisionFrames + 3299 sc->bge_rdata->bge_info.bge_stats.dot3StatsMultipleCollisionFrames + 3300 sc->bge_rdata->bge_info.bge_stats.dot3StatsExcessiveCollisions + 3301 sc->bge_rdata->bge_info.bge_stats.dot3StatsLateCollisions) - 3302 ifp->if_collisions; 3303 #endif 3304 } 3305 3306 /* 3307 * Pad outbound frame to ETHER_MIN_NOPAD for an unusual reason. 3308 * The bge hardware will pad out Tx runts to ETHER_MIN_NOPAD, 3309 * but when such padded frames employ the bge IP/TCP checksum offload, 3310 * the hardware checksum assist gives incorrect results (possibly 3311 * from incorporating its own padding into the UDP/TCP checksum; who knows). 3312 * If we pad such runts with zeros, the onboard checksum comes out correct. 3313 */ 3314 static inline int 3315 bge_cksum_pad(struct mbuf *pkt) 3316 { 3317 struct mbuf *last = NULL; 3318 int padlen; 3319 3320 padlen = ETHER_MIN_NOPAD - pkt->m_pkthdr.len; 3321 3322 /* if there's only the packet-header and we can pad there, use it. */ 3323 if (pkt->m_pkthdr.len == pkt->m_len && 3324 M_TRAILINGSPACE(pkt) >= padlen) { 3325 last = pkt; 3326 } else { 3327 /* 3328 * Walk packet chain to find last mbuf. We will either 3329 * pad there, or append a new mbuf and pad it 3330 * (thus perhaps avoiding the bcm5700 dma-min bug). 3331 */ 3332 for (last = pkt; last->m_next != NULL; last = last->m_next) { 3333 continue; /* do nothing */ 3334 } 3335 3336 /* `last' now points to last in chain. */ 3337 if (M_TRAILINGSPACE(last) < padlen) { 3338 /* Allocate new empty mbuf, pad it. Compact later. */ 3339 struct mbuf *n; 3340 MGET(n, M_DONTWAIT, MT_DATA); 3341 if (n == NULL) 3342 return ENOBUFS; 3343 n->m_len = 0; 3344 last->m_next = n; 3345 last = n; 3346 } 3347 } 3348 3349 KDASSERT(!M_READONLY(last)); 3350 KDASSERT(M_TRAILINGSPACE(last) >= padlen); 3351 3352 /* Now zero the pad area, to avoid the bge cksum-assist bug */ 3353 memset(mtod(last, char *) + last->m_len, 0, padlen); 3354 last->m_len += padlen; 3355 pkt->m_pkthdr.len += padlen; 3356 return 0; 3357 } 3358 3359 /* 3360 * Compact outbound packets to avoid bug with DMA segments less than 8 bytes. 3361 */ 3362 static inline int 3363 bge_compact_dma_runt(struct mbuf *pkt) 3364 { 3365 struct mbuf *m, *prev; 3366 int totlen, prevlen; 3367 3368 prev = NULL; 3369 totlen = 0; 3370 prevlen = -1; 3371 3372 for (m = pkt; m != NULL; prev = m,m = m->m_next) { 3373 int mlen = m->m_len; 3374 int shortfall = 8 - mlen ; 3375 3376 totlen += mlen; 3377 if (mlen == 0) { 3378 continue; 3379 } 3380 if (mlen >= 8) 3381 continue; 3382 3383 /* If we get here, mbuf data is too small for DMA engine. 3384 * Try to fix by shuffling data to prev or next in chain. 3385 * If that fails, do a compacting deep-copy of the whole chain. 3386 */ 3387 3388 /* Internal frag. If fits in prev, copy it there. */ 3389 if (prev && M_TRAILINGSPACE(prev) >= m->m_len) { 3390 memcpy(prev->m_data + prev->m_len, m->m_data, mlen); 3391 prev->m_len += mlen; 3392 m->m_len = 0; 3393 /* XXX stitch chain */ 3394 prev->m_next = m_free(m); 3395 m = prev; 3396 continue; 3397 } 3398 else if (m->m_next != NULL && 3399 M_TRAILINGSPACE(m) >= shortfall && 3400 m->m_next->m_len >= (8 + shortfall)) { 3401 /* m is writable and have enough data in next, pull up. */ 3402 3403 memcpy(m->m_data + m->m_len, m->m_next->m_data, 3404 shortfall); 3405 m->m_len += shortfall; 3406 m->m_next->m_len -= shortfall; 3407 m->m_next->m_data += shortfall; 3408 } 3409 else if (m->m_next == NULL || 1) { 3410 /* Got a runt at the very end of the packet. 3411 * borrow data from the tail of the preceding mbuf and 3412 * update its length in-place. (The original data is still 3413 * valid, so we can do this even if prev is not writable.) 3414 */ 3415 3416 /* if we'd make prev a runt, just move all of its data. */ 3417 KASSERT(prev != NULL /*, ("runt but null PREV")*/); 3418 KASSERT(prev->m_len >= 8 /*, ("runt prev")*/); 3419 3420 if ((prev->m_len - shortfall) < 8) 3421 shortfall = prev->m_len; 3422 3423 #ifdef notyet /* just do the safe slow thing for now */ 3424 if (!M_READONLY(m)) { 3425 if (M_LEADINGSPACE(m) < shorfall) { 3426 void *m_dat; 3427 m_dat = (m->m_flags & M_PKTHDR) ? 3428 m->m_pktdat : m->dat; 3429 memmove(m_dat, mtod(m, void*), m->m_len); 3430 m->m_data = m_dat; 3431 } 3432 } else 3433 #endif /* just do the safe slow thing */ 3434 { 3435 struct mbuf * n = NULL; 3436 int newprevlen = prev->m_len - shortfall; 3437 3438 MGET(n, M_NOWAIT, MT_DATA); 3439 if (n == NULL) 3440 return ENOBUFS; 3441 KASSERT(m->m_len + shortfall < MLEN 3442 /*, 3443 ("runt %d +prev %d too big\n", m->m_len, shortfall)*/); 3444 3445 /* first copy the data we're stealing from prev */ 3446 memcpy(n->m_data, prev->m_data + newprevlen, 3447 shortfall); 3448 3449 /* update prev->m_len accordingly */ 3450 prev->m_len -= shortfall; 3451 3452 /* copy data from runt m */ 3453 memcpy(n->m_data + shortfall, m->m_data, 3454 m->m_len); 3455 3456 /* n holds what we stole from prev, plus m */ 3457 n->m_len = shortfall + m->m_len; 3458 3459 /* stitch n into chain and free m */ 3460 n->m_next = m->m_next; 3461 prev->m_next = n; 3462 /* KASSERT(m->m_next == NULL); */ 3463 m->m_next = NULL; 3464 m_free(m); 3465 m = n; /* for continuing loop */ 3466 } 3467 } 3468 prevlen = m->m_len; 3469 } 3470 return 0; 3471 } 3472 3473 /* 3474 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data 3475 * pointers to descriptors. 3476 */ 3477 static int 3478 bge_encap(struct bge_softc *sc, struct mbuf *m_head, u_int32_t *txidx) 3479 { 3480 struct bge_tx_bd *f = NULL; 3481 u_int32_t frag, cur; 3482 u_int16_t csum_flags = 0; 3483 u_int16_t txbd_tso_flags = 0; 3484 struct txdmamap_pool_entry *dma; 3485 bus_dmamap_t dmamap; 3486 int i = 0; 3487 struct m_tag *mtag; 3488 int use_tso, maxsegsize, error; 3489 3490 cur = frag = *txidx; 3491 3492 if (m_head->m_pkthdr.csum_flags) { 3493 if (m_head->m_pkthdr.csum_flags & M_CSUM_IPv4) 3494 csum_flags |= BGE_TXBDFLAG_IP_CSUM; 3495 if (m_head->m_pkthdr.csum_flags & (M_CSUM_TCPv4|M_CSUM_UDPv4)) 3496 csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM; 3497 } 3498 3499 /* 3500 * If we were asked to do an outboard checksum, and the NIC 3501 * has the bug where it sometimes adds in the Ethernet padding, 3502 * explicitly pad with zeros so the cksum will be correct either way. 3503 * (For now, do this for all chip versions, until newer 3504 * are confirmed to not require the workaround.) 3505 */ 3506 if ((csum_flags & BGE_TXBDFLAG_TCP_UDP_CSUM) == 0 || 3507 #ifdef notyet 3508 (sc->bge_quirks & BGE_QUIRK_SHORT_CKSUM_BUG) == 0 || 3509 #endif 3510 m_head->m_pkthdr.len >= ETHER_MIN_NOPAD) 3511 goto check_dma_bug; 3512 3513 if (bge_cksum_pad(m_head) != 0) { 3514 return ENOBUFS; 3515 } 3516 3517 check_dma_bug: 3518 if (!(BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX)) 3519 goto doit; 3520 3521 /* 3522 * bcm5700 Revision B silicon cannot handle DMA descriptors with 3523 * less than eight bytes. If we encounter a teeny mbuf 3524 * at the end of a chain, we can pad. Otherwise, copy. 3525 */ 3526 if (bge_compact_dma_runt(m_head) != 0) 3527 return ENOBUFS; 3528 3529 doit: 3530 dma = SLIST_FIRST(&sc->txdma_list); 3531 if (dma == NULL) 3532 return ENOBUFS; 3533 dmamap = dma->dmamap; 3534 3535 /* 3536 * Set up any necessary TSO state before we start packing... 3537 */ 3538 use_tso = (m_head->m_pkthdr.csum_flags & M_CSUM_TSOv4) != 0; 3539 if (!use_tso) { 3540 maxsegsize = 0; 3541 } else { /* TSO setup */ 3542 unsigned mss; 3543 struct ether_header *eh; 3544 unsigned ip_tcp_hlen, iptcp_opt_words, tcp_seg_flags, offset; 3545 struct mbuf * m0 = m_head; 3546 struct ip *ip; 3547 struct tcphdr *th; 3548 int iphl, hlen; 3549 3550 /* 3551 * XXX It would be nice if the mbuf pkthdr had offset 3552 * fields for the protocol headers. 3553 */ 3554 3555 eh = mtod(m0, struct ether_header *); 3556 switch (htons(eh->ether_type)) { 3557 case ETHERTYPE_IP: 3558 offset = ETHER_HDR_LEN; 3559 break; 3560 3561 case ETHERTYPE_VLAN: 3562 offset = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 3563 break; 3564 3565 default: 3566 /* 3567 * Don't support this protocol or encapsulation. 3568 */ 3569 return (ENOBUFS); 3570 } 3571 3572 /* 3573 * TCP/IP headers are in the first mbuf; we can do 3574 * this the easy way. 3575 */ 3576 iphl = M_CSUM_DATA_IPv4_IPHL(m0->m_pkthdr.csum_data); 3577 hlen = iphl + offset; 3578 if (__predict_false(m0->m_len < 3579 (hlen + sizeof(struct tcphdr)))) { 3580 3581 aprint_debug_dev(sc->bge_dev, 3582 "TSO: hard case m0->m_len == %d < ip/tcp hlen %zd," 3583 "not handled yet\n", 3584 m0->m_len, hlen+ sizeof(struct tcphdr)); 3585 #ifdef NOTYET 3586 /* 3587 * XXX jonathan (at) NetBSD.org: untested. 3588 * how to force this branch to be taken? 3589 */ 3590 BGE_EVCNT_INCR(&sc->sc_ev_txtsopain); 3591 3592 m_copydata(m0, offset, sizeof(ip), &ip); 3593 m_copydata(m0, hlen, sizeof(th), &th); 3594 3595 ip.ip_len = 0; 3596 3597 m_copyback(m0, hlen + offsetof(struct ip, ip_len), 3598 sizeof(ip.ip_len), &ip.ip_len); 3599 3600 th.th_sum = in_cksum_phdr(ip.ip_src.s_addr, 3601 ip.ip_dst.s_addr, htons(IPPROTO_TCP)); 3602 3603 m_copyback(m0, hlen + offsetof(struct tcphdr, th_sum), 3604 sizeof(th.th_sum), &th.th_sum); 3605 3606 hlen += th.th_off << 2; 3607 iptcp_opt_words = hlen; 3608 #else 3609 /* 3610 * if_wm "hard" case not yet supported, can we not 3611 * mandate it out of existence? 3612 */ 3613 (void) ip; (void)th; (void) ip_tcp_hlen; 3614 3615 return ENOBUFS; 3616 #endif 3617 } else { 3618 ip = (struct ip *) (mtod(m0, char *) + offset); 3619 th = (struct tcphdr *) (mtod(m0, char *) + hlen); 3620 ip_tcp_hlen = iphl + (th->th_off << 2); 3621 3622 /* Total IP/TCP options, in 32-bit words */ 3623 iptcp_opt_words = (ip_tcp_hlen 3624 - sizeof(struct tcphdr) 3625 - sizeof(struct ip)) >> 2; 3626 } 3627 if (BGE_IS_5750_OR_BEYOND(sc)) { 3628 th->th_sum = 0; 3629 csum_flags &= ~(BGE_TXBDFLAG_TCP_UDP_CSUM); 3630 } else { 3631 /* 3632 * XXX jonathan (at) NetBSD.org: 5705 untested. 3633 * Requires TSO firmware patch for 5701/5703/5704. 3634 */ 3635 th->th_sum = in_cksum_phdr(ip->ip_src.s_addr, 3636 ip->ip_dst.s_addr, htons(IPPROTO_TCP)); 3637 } 3638 3639 mss = m_head->m_pkthdr.segsz; 3640 txbd_tso_flags |= 3641 BGE_TXBDFLAG_CPU_PRE_DMA | 3642 BGE_TXBDFLAG_CPU_POST_DMA; 3643 3644 /* 3645 * Our NIC TSO-assist assumes TSO has standard, optionless 3646 * IPv4 and TCP headers, which total 40 bytes. By default, 3647 * the NIC copies 40 bytes of IP/TCP header from the 3648 * supplied header into the IP/TCP header portion of 3649 * each post-TSO-segment. If the supplied packet has IP or 3650 * TCP options, we need to tell the NIC to copy those extra 3651 * bytes into each post-TSO header, in addition to the normal 3652 * 40-byte IP/TCP header (and to leave space accordingly). 3653 * Unfortunately, the driver encoding of option length 3654 * varies across different ASIC families. 3655 */ 3656 tcp_seg_flags = 0; 3657 if (iptcp_opt_words) { 3658 if ( BGE_IS_5705_OR_BEYOND(sc)) { 3659 tcp_seg_flags = 3660 iptcp_opt_words << 11; 3661 } else { 3662 txbd_tso_flags |= 3663 iptcp_opt_words << 12; 3664 } 3665 } 3666 maxsegsize = mss | tcp_seg_flags; 3667 ip->ip_len = htons(mss + ip_tcp_hlen); 3668 3669 } /* TSO setup */ 3670 3671 /* 3672 * Start packing the mbufs in this chain into 3673 * the fragment pointers. Stop when we run out 3674 * of fragments or hit the end of the mbuf chain. 3675 */ 3676 error = bus_dmamap_load_mbuf(sc->bge_dmatag, dmamap, m_head, 3677 BUS_DMA_NOWAIT); 3678 if (error) { 3679 return (ENOBUFS); 3680 } 3681 /* 3682 * Sanity check: avoid coming within 16 descriptors 3683 * of the end of the ring. 3684 */ 3685 if (dmamap->dm_nsegs > (BGE_TX_RING_CNT - sc->bge_txcnt - 16)) { 3686 BGE_TSO_PRINTF(("%s: " 3687 " dmamap_load_mbuf too close to ring wrap\n", 3688 device_xname(sc->bge_dev))); 3689 goto fail_unload; 3690 } 3691 3692 mtag = sc->ethercom.ec_nvlans ? 3693 m_tag_find(m_head, PACKET_TAG_VLAN, NULL) : NULL; 3694 3695 3696 /* Iterate over dmap-map fragments. */ 3697 for (i = 0; i < dmamap->dm_nsegs; i++) { 3698 f = &sc->bge_rdata->bge_tx_ring[frag]; 3699 if (sc->bge_cdata.bge_tx_chain[frag] != NULL) 3700 break; 3701 3702 bge_set_hostaddr(&f->bge_addr, dmamap->dm_segs[i].ds_addr); 3703 f->bge_len = dmamap->dm_segs[i].ds_len; 3704 3705 /* 3706 * For 5751 and follow-ons, for TSO we must turn 3707 * off checksum-assist flag in the tx-descr, and 3708 * supply the ASIC-revision-specific encoding 3709 * of TSO flags and segsize. 3710 */ 3711 if (use_tso) { 3712 if (BGE_IS_5750_OR_BEYOND(sc) || i == 0) { 3713 f->bge_rsvd = maxsegsize; 3714 f->bge_flags = csum_flags | txbd_tso_flags; 3715 } else { 3716 f->bge_rsvd = 0; 3717 f->bge_flags = 3718 (csum_flags | txbd_tso_flags) & 0x0fff; 3719 } 3720 } else { 3721 f->bge_rsvd = 0; 3722 f->bge_flags = csum_flags; 3723 } 3724 3725 if (mtag != NULL) { 3726 f->bge_flags |= BGE_TXBDFLAG_VLAN_TAG; 3727 f->bge_vlan_tag = VLAN_TAG_VALUE(mtag); 3728 } else { 3729 f->bge_vlan_tag = 0; 3730 } 3731 cur = frag; 3732 BGE_INC(frag, BGE_TX_RING_CNT); 3733 } 3734 3735 if (i < dmamap->dm_nsegs) { 3736 BGE_TSO_PRINTF(("%s: reached %d < dm_nsegs %d\n", 3737 device_xname(sc->bge_dev), i, dmamap->dm_nsegs)); 3738 goto fail_unload; 3739 } 3740 3741 bus_dmamap_sync(sc->bge_dmatag, dmamap, 0, dmamap->dm_mapsize, 3742 BUS_DMASYNC_PREWRITE); 3743 3744 if (frag == sc->bge_tx_saved_considx) { 3745 BGE_TSO_PRINTF(("%s: frag %d = wrapped id %d?\n", 3746 device_xname(sc->bge_dev), frag, sc->bge_tx_saved_considx)); 3747 3748 goto fail_unload; 3749 } 3750 3751 sc->bge_rdata->bge_tx_ring[cur].bge_flags |= BGE_TXBDFLAG_END; 3752 sc->bge_cdata.bge_tx_chain[cur] = m_head; 3753 SLIST_REMOVE_HEAD(&sc->txdma_list, link); 3754 sc->txdma[cur] = dma; 3755 sc->bge_txcnt += dmamap->dm_nsegs; 3756 3757 *txidx = frag; 3758 3759 return (0); 3760 3761 fail_unload: 3762 bus_dmamap_unload(sc->bge_dmatag, dmamap); 3763 3764 return ENOBUFS; 3765 } 3766 3767 /* 3768 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 3769 * to the mbuf data regions directly in the transmit descriptors. 3770 */ 3771 static void 3772 bge_start(struct ifnet *ifp) 3773 { 3774 struct bge_softc *sc; 3775 struct mbuf *m_head = NULL; 3776 u_int32_t prodidx; 3777 int pkts = 0; 3778 3779 sc = ifp->if_softc; 3780 3781 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 3782 return; 3783 3784 prodidx = sc->bge_tx_prodidx; 3785 3786 while(sc->bge_cdata.bge_tx_chain[prodidx] == NULL) { 3787 IFQ_POLL(&ifp->if_snd, m_head); 3788 if (m_head == NULL) 3789 break; 3790 3791 #if 0 3792 /* 3793 * XXX 3794 * safety overkill. If this is a fragmented packet chain 3795 * with delayed TCP/UDP checksums, then only encapsulate 3796 * it if we have enough descriptors to handle the entire 3797 * chain at once. 3798 * (paranoia -- may not actually be needed) 3799 */ 3800 if (m_head->m_flags & M_FIRSTFRAG && 3801 m_head->m_pkthdr.csum_flags & (CSUM_DELAY_DATA)) { 3802 if ((BGE_TX_RING_CNT - sc->bge_txcnt) < 3803 M_CSUM_DATA_IPv4_OFFSET(m_head->m_pkthdr.csum_data) + 16) { 3804 ifp->if_flags |= IFF_OACTIVE; 3805 break; 3806 } 3807 } 3808 #endif 3809 3810 /* 3811 * Pack the data into the transmit ring. If we 3812 * don't have room, set the OACTIVE flag and wait 3813 * for the NIC to drain the ring. 3814 */ 3815 if (bge_encap(sc, m_head, &prodidx)) { 3816 ifp->if_flags |= IFF_OACTIVE; 3817 break; 3818 } 3819 3820 /* now we are committed to transmit the packet */ 3821 IFQ_DEQUEUE(&ifp->if_snd, m_head); 3822 pkts++; 3823 3824 #if NBPFILTER > 0 3825 /* 3826 * If there's a BPF listener, bounce a copy of this frame 3827 * to him. 3828 */ 3829 if (ifp->if_bpf) 3830 bpf_mtap(ifp->if_bpf, m_head); 3831 #endif 3832 } 3833 if (pkts == 0) 3834 return; 3835 3836 /* Transmit */ 3837 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); 3838 /* 5700 b2 errata */ 3839 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX) 3840 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); 3841 3842 sc->bge_tx_prodidx = prodidx; 3843 3844 /* 3845 * Set a timeout in case the chip goes out to lunch. 3846 */ 3847 ifp->if_timer = 5; 3848 } 3849 3850 static int 3851 bge_init(struct ifnet *ifp) 3852 { 3853 struct bge_softc *sc = ifp->if_softc; 3854 const u_int16_t *m; 3855 int s, error = 0; 3856 3857 s = splnet(); 3858 3859 ifp = &sc->ethercom.ec_if; 3860 3861 /* Cancel pending I/O and flush buffers. */ 3862 bge_stop(ifp, 0); 3863 bge_reset(sc); 3864 bge_chipinit(sc); 3865 3866 /* 3867 * Init the various state machines, ring 3868 * control blocks and firmware. 3869 */ 3870 error = bge_blockinit(sc); 3871 if (error != 0) { 3872 aprint_error_dev(sc->bge_dev, "initialization error %d\n", 3873 error); 3874 splx(s); 3875 return error; 3876 } 3877 3878 ifp = &sc->ethercom.ec_if; 3879 3880 /* Specify MTU. */ 3881 CSR_WRITE_4(sc, BGE_RX_MTU, ifp->if_mtu + 3882 ETHER_HDR_LEN + ETHER_CRC_LEN + ETHER_VLAN_ENCAP_LEN); 3883 3884 /* Load our MAC address. */ 3885 m = (const u_int16_t *)&(CLLADDR(ifp->if_sadl)[0]); 3886 CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0])); 3887 CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, (htons(m[1]) << 16) | htons(m[2])); 3888 3889 /* Enable or disable promiscuous mode as needed. */ 3890 if (ifp->if_flags & IFF_PROMISC) { 3891 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 3892 } else { 3893 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 3894 } 3895 3896 /* Program multicast filter. */ 3897 bge_setmulti(sc); 3898 3899 /* Init RX ring. */ 3900 bge_init_rx_ring_std(sc); 3901 3902 /* Init jumbo RX ring. */ 3903 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 3904 bge_init_rx_ring_jumbo(sc); 3905 3906 /* Init our RX return ring index */ 3907 sc->bge_rx_saved_considx = 0; 3908 3909 /* Init TX ring. */ 3910 bge_init_tx_ring(sc); 3911 3912 /* Turn on transmitter */ 3913 BGE_SETBIT(sc, BGE_TX_MODE, BGE_TXMODE_ENABLE); 3914 3915 /* Turn on receiver */ 3916 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE); 3917 3918 CSR_WRITE_4(sc, BGE_MAX_RX_FRAME_LOWAT, 2); 3919 3920 /* Tell firmware we're alive. */ 3921 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 3922 3923 /* Enable host interrupts. */ 3924 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA); 3925 BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); 3926 bge_writembx(sc, BGE_MBX_IRQ0_LO, 0); 3927 3928 if ((error = bge_ifmedia_upd(ifp)) != 0) 3929 goto out; 3930 3931 ifp->if_flags |= IFF_RUNNING; 3932 ifp->if_flags &= ~IFF_OACTIVE; 3933 3934 callout_reset(&sc->bge_timeout, hz, bge_tick, sc); 3935 3936 out: 3937 splx(s); 3938 3939 return error; 3940 } 3941 3942 /* 3943 * Set media options. 3944 */ 3945 static int 3946 bge_ifmedia_upd(struct ifnet *ifp) 3947 { 3948 struct bge_softc *sc = ifp->if_softc; 3949 struct mii_data *mii = &sc->bge_mii; 3950 struct ifmedia *ifm = &sc->bge_ifmedia; 3951 int rc; 3952 3953 /* If this is a 1000baseX NIC, enable the TBI port. */ 3954 if (sc->bge_flags & BGE_PHY_FIBER_TBI) { 3955 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 3956 return (EINVAL); 3957 switch(IFM_SUBTYPE(ifm->ifm_media)) { 3958 case IFM_AUTO: 3959 break; 3960 case IFM_1000_SX: 3961 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 3962 BGE_CLRBIT(sc, BGE_MAC_MODE, 3963 BGE_MACMODE_HALF_DUPLEX); 3964 } else { 3965 BGE_SETBIT(sc, BGE_MAC_MODE, 3966 BGE_MACMODE_HALF_DUPLEX); 3967 } 3968 break; 3969 default: 3970 return (EINVAL); 3971 } 3972 /* XXX 802.3x flow control for 1000BASE-SX */ 3973 return (0); 3974 } 3975 3976 sc->bge_link = 0; 3977 if ((rc = mii_mediachg(mii)) == ENXIO) 3978 return 0; 3979 return rc; 3980 } 3981 3982 /* 3983 * Report current media status. 3984 */ 3985 static void 3986 bge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 3987 { 3988 struct bge_softc *sc = ifp->if_softc; 3989 struct mii_data *mii = &sc->bge_mii; 3990 3991 if (sc->bge_flags & BGE_PHY_FIBER_TBI) { 3992 ifmr->ifm_status = IFM_AVALID; 3993 ifmr->ifm_active = IFM_ETHER; 3994 if (CSR_READ_4(sc, BGE_MAC_STS) & 3995 BGE_MACSTAT_TBI_PCS_SYNCHED) 3996 ifmr->ifm_status |= IFM_ACTIVE; 3997 ifmr->ifm_active |= IFM_1000_SX; 3998 if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX) 3999 ifmr->ifm_active |= IFM_HDX; 4000 else 4001 ifmr->ifm_active |= IFM_FDX; 4002 return; 4003 } 4004 4005 mii_pollstat(mii); 4006 ifmr->ifm_status = mii->mii_media_status; 4007 ifmr->ifm_active = (mii->mii_media_active & ~IFM_ETH_FMASK) | 4008 sc->bge_flowflags; 4009 } 4010 4011 static int 4012 bge_ioctl(struct ifnet *ifp, u_long command, void *data) 4013 { 4014 struct bge_softc *sc = ifp->if_softc; 4015 struct ifreq *ifr = (struct ifreq *) data; 4016 int s, error = 0; 4017 struct mii_data *mii; 4018 4019 s = splnet(); 4020 4021 switch(command) { 4022 case SIOCSIFFLAGS: 4023 if ((error = ifioctl_common(ifp, command, data)) != 0) 4024 break; 4025 if (ifp->if_flags & IFF_UP) { 4026 /* 4027 * If only the state of the PROMISC flag changed, 4028 * then just use the 'set promisc mode' command 4029 * instead of reinitializing the entire NIC. Doing 4030 * a full re-init means reloading the firmware and 4031 * waiting for it to start up, which may take a 4032 * second or two. 4033 */ 4034 if (ifp->if_flags & IFF_RUNNING && 4035 ifp->if_flags & IFF_PROMISC && 4036 !(sc->bge_if_flags & IFF_PROMISC)) { 4037 BGE_SETBIT(sc, BGE_RX_MODE, 4038 BGE_RXMODE_RX_PROMISC); 4039 } else if (ifp->if_flags & IFF_RUNNING && 4040 !(ifp->if_flags & IFF_PROMISC) && 4041 sc->bge_if_flags & IFF_PROMISC) { 4042 BGE_CLRBIT(sc, BGE_RX_MODE, 4043 BGE_RXMODE_RX_PROMISC); 4044 } else if (!(sc->bge_if_flags & IFF_UP)) 4045 bge_init(ifp); 4046 } else { 4047 if (ifp->if_flags & IFF_RUNNING) 4048 bge_stop(ifp, 1); 4049 } 4050 sc->bge_if_flags = ifp->if_flags; 4051 error = 0; 4052 break; 4053 case SIOCSIFMEDIA: 4054 /* XXX Flow control is not supported for 1000BASE-SX */ 4055 if (sc->bge_flags & BGE_PHY_FIBER_TBI) { 4056 ifr->ifr_media &= ~IFM_ETH_FMASK; 4057 sc->bge_flowflags = 0; 4058 } 4059 4060 /* Flow control requires full-duplex mode. */ 4061 if (IFM_SUBTYPE(ifr->ifr_media) == IFM_AUTO || 4062 (ifr->ifr_media & IFM_FDX) == 0) { 4063 ifr->ifr_media &= ~IFM_ETH_FMASK; 4064 } 4065 if (IFM_SUBTYPE(ifr->ifr_media) != IFM_AUTO) { 4066 if ((ifr->ifr_media & IFM_ETH_FMASK) == IFM_FLOW) { 4067 /* We can do both TXPAUSE and RXPAUSE. */ 4068 ifr->ifr_media |= 4069 IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE; 4070 } 4071 sc->bge_flowflags = ifr->ifr_media & IFM_ETH_FMASK; 4072 } 4073 /* FALLTHROUGH */ 4074 case SIOCGIFMEDIA: 4075 if (sc->bge_flags & BGE_PHY_FIBER_TBI) { 4076 error = ifmedia_ioctl(ifp, ifr, &sc->bge_ifmedia, 4077 command); 4078 } else { 4079 mii = &sc->bge_mii; 4080 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, 4081 command); 4082 } 4083 break; 4084 default: 4085 if ((error = ether_ioctl(ifp, command, data)) != ENETRESET) 4086 break; 4087 4088 error = 0; 4089 4090 if (command != SIOCADDMULTI && command != SIOCDELMULTI) 4091 ; 4092 else if (ifp->if_flags & IFF_RUNNING) 4093 bge_setmulti(sc); 4094 break; 4095 } 4096 4097 splx(s); 4098 4099 return (error); 4100 } 4101 4102 static void 4103 bge_watchdog(struct ifnet *ifp) 4104 { 4105 struct bge_softc *sc; 4106 4107 sc = ifp->if_softc; 4108 4109 aprint_error_dev(sc->bge_dev, "watchdog timeout -- resetting\n"); 4110 4111 ifp->if_flags &= ~IFF_RUNNING; 4112 bge_init(ifp); 4113 4114 ifp->if_oerrors++; 4115 } 4116 4117 static void 4118 bge_stop_block(struct bge_softc *sc, bus_addr_t reg, uint32_t bit) 4119 { 4120 int i; 4121 4122 BGE_CLRBIT(sc, reg, bit); 4123 4124 for (i = 0; i < BGE_TIMEOUT; i++) { 4125 if ((CSR_READ_4(sc, reg) & bit) == 0) 4126 return; 4127 delay(100); 4128 if (sc->bge_flags & BGE_PCIE) 4129 DELAY(1000); 4130 } 4131 4132 aprint_error_dev(sc->bge_dev, 4133 "block failed to stop: reg 0x%lx, bit 0x%08x\n", (u_long)reg, bit); 4134 } 4135 4136 /* 4137 * Stop the adapter and free any mbufs allocated to the 4138 * RX and TX lists. 4139 */ 4140 static void 4141 bge_stop(struct ifnet *ifp, int disable) 4142 { 4143 struct bge_softc *sc = ifp->if_softc; 4144 4145 callout_stop(&sc->bge_timeout); 4146 4147 /* 4148 * Disable all of the receiver blocks 4149 */ 4150 bge_stop_block(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE); 4151 bge_stop_block(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 4152 bge_stop_block(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 4153 if (!(BGE_IS_5705_OR_BEYOND(sc))) 4154 bge_stop_block(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 4155 bge_stop_block(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE); 4156 bge_stop_block(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 4157 bge_stop_block(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE); 4158 4159 /* 4160 * Disable all of the transmit blocks 4161 */ 4162 bge_stop_block(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 4163 bge_stop_block(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 4164 bge_stop_block(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 4165 bge_stop_block(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE); 4166 bge_stop_block(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE); 4167 if (!(BGE_IS_5705_OR_BEYOND(sc))) 4168 bge_stop_block(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 4169 bge_stop_block(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 4170 4171 /* 4172 * Shut down all of the memory managers and related 4173 * state machines. 4174 */ 4175 bge_stop_block(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE); 4176 bge_stop_block(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE); 4177 if (!(BGE_IS_5705_OR_BEYOND(sc))) 4178 bge_stop_block(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 4179 4180 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 4181 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 4182 4183 if (!(BGE_IS_5705_OR_BEYOND(sc))) { 4184 bge_stop_block(sc, BGE_BMAN_MODE, BGE_BMANMODE_ENABLE); 4185 bge_stop_block(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 4186 } 4187 4188 /* Disable host interrupts. */ 4189 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); 4190 bge_writembx(sc, BGE_MBX_IRQ0_LO, 1); 4191 4192 /* 4193 * Tell firmware we're shutting down. 4194 */ 4195 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 4196 4197 /* Free the RX lists. */ 4198 bge_free_rx_ring_std(sc); 4199 4200 /* Free jumbo RX list. */ 4201 bge_free_rx_ring_jumbo(sc); 4202 4203 /* Free TX buffers. */ 4204 bge_free_tx_ring(sc); 4205 4206 /* 4207 * Isolate/power down the PHY. 4208 */ 4209 if (!(sc->bge_flags & BGE_PHY_FIBER_TBI)) 4210 mii_down(&sc->bge_mii); 4211 4212 sc->bge_link = 0; 4213 4214 sc->bge_tx_saved_considx = BGE_TXCONS_UNSET; 4215 4216 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 4217 } 4218 4219 static int 4220 sysctl_bge_verify(SYSCTLFN_ARGS) 4221 { 4222 int error, t; 4223 struct sysctlnode node; 4224 4225 node = *rnode; 4226 t = *(int*)rnode->sysctl_data; 4227 node.sysctl_data = &t; 4228 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 4229 if (error || newp == NULL) 4230 return (error); 4231 4232 #if 0 4233 DPRINTF2(("%s: t = %d, nodenum = %d, rnodenum = %d\n", __func__, t, 4234 node.sysctl_num, rnode->sysctl_num)); 4235 #endif 4236 4237 if (node.sysctl_num == bge_rxthresh_nodenum) { 4238 if (t < 0 || t >= NBGE_RX_THRESH) 4239 return (EINVAL); 4240 bge_update_all_threshes(t); 4241 } else 4242 return (EINVAL); 4243 4244 *(int*)rnode->sysctl_data = t; 4245 4246 return (0); 4247 } 4248 4249 /* 4250 * Set up sysctl(3) MIB, hw.bge.*. 4251 * 4252 * TBD condition SYSCTL_PERMANENT on being an LKM or not 4253 */ 4254 SYSCTL_SETUP(sysctl_bge, "sysctl bge subtree setup") 4255 { 4256 int rc, bge_root_num; 4257 const struct sysctlnode *node; 4258 4259 if ((rc = sysctl_createv(clog, 0, NULL, NULL, 4260 CTLFLAG_PERMANENT, CTLTYPE_NODE, "hw", NULL, 4261 NULL, 0, NULL, 0, CTL_HW, CTL_EOL)) != 0) { 4262 goto err; 4263 } 4264 4265 if ((rc = sysctl_createv(clog, 0, NULL, &node, 4266 CTLFLAG_PERMANENT, CTLTYPE_NODE, "bge", 4267 SYSCTL_DESCR("BGE interface controls"), 4268 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL)) != 0) { 4269 goto err; 4270 } 4271 4272 bge_root_num = node->sysctl_num; 4273 4274 /* BGE Rx interrupt mitigation level */ 4275 if ((rc = sysctl_createv(clog, 0, NULL, &node, 4276 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, 4277 CTLTYPE_INT, "rx_lvl", 4278 SYSCTL_DESCR("BGE receive interrupt mitigation level"), 4279 sysctl_bge_verify, 0, 4280 &bge_rx_thresh_lvl, 4281 0, CTL_HW, bge_root_num, CTL_CREATE, 4282 CTL_EOL)) != 0) { 4283 goto err; 4284 } 4285 4286 bge_rxthresh_nodenum = node->sysctl_num; 4287 4288 return; 4289 4290 err: 4291 aprint_error("%s: sysctl_createv failed (rc = %d)\n", __func__, rc); 4292 } 4293 4294 static int 4295 bge_get_eaddr_mem(struct bge_softc *sc, u_int8_t ether_addr[]) 4296 { 4297 u_int32_t mac_addr; 4298 4299 mac_addr = bge_readmem_ind(sc, 0x0c14); 4300 if ((mac_addr >> 16) == 0x484b) { 4301 ether_addr[0] = (uint8_t)(mac_addr >> 8); 4302 ether_addr[1] = (uint8_t)mac_addr; 4303 mac_addr = bge_readmem_ind(sc, 0x0c18); 4304 ether_addr[2] = (uint8_t)(mac_addr >> 24); 4305 ether_addr[3] = (uint8_t)(mac_addr >> 16); 4306 ether_addr[4] = (uint8_t)(mac_addr >> 8); 4307 ether_addr[5] = (uint8_t)mac_addr; 4308 return (0); 4309 } 4310 return (1); 4311 } 4312 4313 static int 4314 bge_get_eaddr_nvram(struct bge_softc *sc, u_int8_t ether_addr[]) 4315 { 4316 int mac_offset = BGE_EE_MAC_OFFSET; 4317 4318 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 4319 mac_offset = BGE_EE_MAC_OFFSET_5906; 4320 } 4321 4322 return (bge_read_nvram(sc, ether_addr, mac_offset + 2, 4323 ETHER_ADDR_LEN)); 4324 } 4325 4326 static int 4327 bge_get_eaddr_eeprom(struct bge_softc *sc, u_int8_t ether_addr[]) 4328 { 4329 4330 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 4331 return (1); 4332 } 4333 4334 return (bge_read_eeprom(sc, ether_addr, BGE_EE_MAC_OFFSET + 2, 4335 ETHER_ADDR_LEN)); 4336 } 4337 4338 static int 4339 bge_get_eaddr(struct bge_softc *sc, u_int8_t eaddr[]) 4340 { 4341 static const bge_eaddr_fcn_t bge_eaddr_funcs[] = { 4342 /* NOTE: Order is critical */ 4343 bge_get_eaddr_mem, 4344 bge_get_eaddr_nvram, 4345 bge_get_eaddr_eeprom, 4346 NULL 4347 }; 4348 const bge_eaddr_fcn_t *func; 4349 4350 for (func = bge_eaddr_funcs; *func != NULL; ++func) { 4351 if ((*func)(sc, eaddr) == 0) 4352 break; 4353 } 4354 return (*func == NULL ? ENXIO : 0); 4355 } 4356
Indexes created Wed Sep 24 05:09:52 GMT 2025