if_bge.c revision 1.164
1 /* $NetBSD: if_bge.c,v 1.164 2009/04/23 10:47:44 msaitoh Exp $ */ 2 3 /* 4 * Copyright (c) 2001 Wind River Systems 5 * Copyright (c) 1997, 1998, 1999, 2001 6 * Bill Paul <wpaul (at) windriver.com>. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Bill Paul. 19 * 4. Neither the name of the author nor the names of any co-contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 33 * THE POSSIBILITY OF SUCH DAMAGE. 34 * 35 * $FreeBSD: if_bge.c,v 1.13 2002/04/04 06:01:31 wpaul Exp $ 36 */ 37 38 /* 39 * Broadcom BCM570x family gigabit ethernet driver for NetBSD. 40 * 41 * NetBSD version by: 42 * 43 * Frank van der Linden <fvdl (at) wasabisystems.com> 44 * Jason Thorpe <thorpej (at) wasabisystems.com> 45 * Jonathan Stone <jonathan (at) dsg.stanford.edu> 46 * 47 * Originally written for FreeBSD by Bill Paul <wpaul (at) windriver.com> 48 * Senior Engineer, Wind River Systems 49 */ 50 51 /* 52 * The Broadcom BCM5700 is based on technology originally developed by 53 * Alteon Networks as part of the Tigon I and Tigon II gigabit ethernet 54 * MAC chips. The BCM5700, sometimes refered to as the Tigon III, has 55 * two on-board MIPS R4000 CPUs and can have as much as 16MB of external 56 * SSRAM. The BCM5700 supports TCP, UDP and IP checksum offload, jumbo 57 * frames, highly configurable RX filtering, and 16 RX and TX queues 58 * (which, along with RX filter rules, can be used for QOS applications). 59 * Other features, such as TCP segmentation, may be available as part 60 * of value-added firmware updates. Unlike the Tigon I and Tigon II, 61 * firmware images can be stored in hardware and need not be compiled 62 * into the driver. 63 * 64 * The BCM5700 supports the PCI v2.2 and PCI-X v1.0 standards, and will 65 * function in a 32-bit/64-bit 33/66MHz bus, or a 64-bit/133MHz bus. 66 * 67 * The BCM5701 is a single-chip solution incorporating both the BCM5700 68 * MAC and a BCM5401 10/100/1000 PHY. Unlike the BCM5700, the BCM5701 69 * does not support external SSRAM. 70 * 71 * Broadcom also produces a variation of the BCM5700 under the "Altima" 72 * brand name, which is functionally similar but lacks PCI-X support. 73 * 74 * Without external SSRAM, you can only have at most 4 TX rings, 75 * and the use of the mini RX ring is disabled. This seems to imply 76 * that these features are simply not available on the BCM5701. As a 77 * result, this driver does not implement any support for the mini RX 78 * ring. 79 */ 80 81 #include <sys/cdefs.h> 82 __KERNEL_RCSID(0, "$NetBSD: if_bge.c,v 1.164 2009/04/23 10:47:44 msaitoh Exp $"); 83 84 #include "bpfilter.h" 85 #include "vlan.h" 86 #include "rnd.h" 87 88 #include <sys/param.h> 89 #include <sys/systm.h> 90 #include <sys/callout.h> 91 #include <sys/sockio.h> 92 #include <sys/mbuf.h> 93 #include <sys/malloc.h> 94 #include <sys/kernel.h> 95 #include <sys/device.h> 96 #include <sys/socket.h> 97 #include <sys/sysctl.h> 98 99 #include <net/if.h> 100 #include <net/if_dl.h> 101 #include <net/if_media.h> 102 #include <net/if_ether.h> 103 104 #if NRND > 0 105 #include <sys/rnd.h> 106 #endif 107 108 #ifdef INET 109 #include <netinet/in.h> 110 #include <netinet/in_systm.h> 111 #include <netinet/in_var.h> 112 #include <netinet/ip.h> 113 #endif 114 115 /* Headers for TCP Segmentation Offload (TSO) */ 116 #include <netinet/in_systm.h> /* n_time for <netinet/ip.h>... */ 117 #include <netinet/in.h> /* ip_{src,dst}, for <netinet/ip.h> */ 118 #include <netinet/ip.h> /* for struct ip */ 119 #include <netinet/tcp.h> /* for struct tcphdr */ 120 121 122 #if NBPFILTER > 0 123 #include <net/bpf.h> 124 #endif 125 126 #include <dev/pci/pcireg.h> 127 #include <dev/pci/pcivar.h> 128 #include <dev/pci/pcidevs.h> 129 130 #include <dev/mii/mii.h> 131 #include <dev/mii/miivar.h> 132 #include <dev/mii/miidevs.h> 133 #include <dev/mii/brgphyreg.h> 134 135 #include <dev/pci/if_bgereg.h> 136 #include <dev/pci/if_bgevar.h> 137 138 #include <uvm/uvm_extern.h> 139 #include <prop/proplib.h> 140 141 #define ETHER_MIN_NOPAD (ETHER_MIN_LEN - ETHER_CRC_LEN) /* i.e., 60 */ 142 143 144 /* 145 * Tunable thresholds for rx-side bge interrupt mitigation. 146 */ 147 148 /* 149 * The pairs of values below were obtained from empirical measurement 150 * on bcm5700 rev B2; they ar designed to give roughly 1 receive 151 * interrupt for every N packets received, where N is, approximately, 152 * the second value (rx_max_bds) in each pair. The values are chosen 153 * such that moving from one pair to the succeeding pair was observed 154 * to roughly halve interrupt rate under sustained input packet load. 155 * The values were empirically chosen to avoid overflowing internal 156 * limits on the bcm5700: inreasing rx_ticks much beyond 600 157 * results in internal wrapping and higher interrupt rates. 158 * The limit of 46 frames was chosen to match NFS workloads. 159 * 160 * These values also work well on bcm5701, bcm5704C, and (less 161 * tested) bcm5703. On other chipsets, (including the Altima chip 162 * family), the larger values may overflow internal chip limits, 163 * leading to increasing interrupt rates rather than lower interrupt 164 * rates. 165 * 166 * Applications using heavy interrupt mitigation (interrupting every 167 * 32 or 46 frames) in both directions may need to increase the TCP 168 * windowsize to above 131072 bytes (e.g., to 199608 bytes) to sustain 169 * full link bandwidth, due to ACKs and window updates lingering 170 * in the RX queue during the 30-to-40-frame interrupt-mitigation window. 171 */ 172 static const struct bge_load_rx_thresh { 173 int rx_ticks; 174 int rx_max_bds; } 175 bge_rx_threshes[] = { 176 { 32, 2 }, 177 { 50, 4 }, 178 { 100, 8 }, 179 { 192, 16 }, 180 { 416, 32 }, 181 { 598, 46 } 182 }; 183 #define NBGE_RX_THRESH (sizeof(bge_rx_threshes) / sizeof(bge_rx_threshes[0])) 184 185 /* XXX patchable; should be sysctl'able */ 186 static int bge_auto_thresh = 1; 187 static int bge_rx_thresh_lvl; 188 189 static int bge_rxthresh_nodenum; 190 191 typedef int (*bge_eaddr_fcn_t)(struct bge_softc *, u_int8_t[]); 192 193 static int bge_probe(device_t, cfdata_t, void *); 194 static void bge_attach(device_t, device_t, void *); 195 static void bge_release_resources(struct bge_softc *); 196 static void bge_txeof(struct bge_softc *); 197 static void bge_rxeof(struct bge_softc *); 198 199 static int bge_get_eaddr_mem(struct bge_softc *, u_int8_t[]); 200 static int bge_get_eaddr_nvram(struct bge_softc *, u_int8_t[]); 201 static int bge_get_eaddr_eeprom(struct bge_softc *, u_int8_t[]); 202 static int bge_get_eaddr(struct bge_softc *, u_int8_t[]); 203 204 static void bge_tick(void *); 205 static void bge_stats_update(struct bge_softc *); 206 static int bge_encap(struct bge_softc *, struct mbuf *, u_int32_t *); 207 208 static int bge_intr(void *); 209 static void bge_start(struct ifnet *); 210 static int bge_ioctl(struct ifnet *, u_long, void *); 211 static int bge_init(struct ifnet *); 212 static void bge_stop(struct ifnet *, int); 213 static void bge_watchdog(struct ifnet *); 214 static int bge_ifmedia_upd(struct ifnet *); 215 static void bge_ifmedia_sts(struct ifnet *, struct ifmediareq *); 216 217 static void bge_setmulti(struct bge_softc *); 218 219 static void bge_handle_events(struct bge_softc *); 220 static int bge_alloc_jumbo_mem(struct bge_softc *); 221 #if 0 /* XXX */ 222 static void bge_free_jumbo_mem(struct bge_softc *); 223 #endif 224 static void *bge_jalloc(struct bge_softc *); 225 static void bge_jfree(struct mbuf *, void *, size_t, void *); 226 static int bge_newbuf_std(struct bge_softc *, int, struct mbuf *, 227 bus_dmamap_t); 228 static int bge_newbuf_jumbo(struct bge_softc *, int, struct mbuf *); 229 static int bge_init_rx_ring_std(struct bge_softc *); 230 static void bge_free_rx_ring_std(struct bge_softc *); 231 static int bge_init_rx_ring_jumbo(struct bge_softc *); 232 static void bge_free_rx_ring_jumbo(struct bge_softc *); 233 static void bge_free_tx_ring(struct bge_softc *); 234 static int bge_init_tx_ring(struct bge_softc *); 235 236 static int bge_chipinit(struct bge_softc *); 237 static int bge_blockinit(struct bge_softc *); 238 static int bge_setpowerstate(struct bge_softc *, int); 239 240 static void bge_reset(struct bge_softc *); 241 static void bge_link_upd(struct bge_softc *); 242 243 #define BGE_DEBUG 244 #ifdef BGE_DEBUG 245 #define DPRINTF(x) if (bgedebug) printf x 246 #define DPRINTFN(n,x) if (bgedebug >= (n)) printf x 247 #define BGE_TSO_PRINTF(x) do { if (bge_tso_debug) printf x ;} while (0) 248 int bgedebug = 0; 249 int bge_tso_debug = 0; 250 #else 251 #define DPRINTF(x) 252 #define DPRINTFN(n,x) 253 #define BGE_TSO_PRINTF(x) 254 #endif 255 256 #ifdef BGE_EVENT_COUNTERS 257 #define BGE_EVCNT_INCR(ev) (ev).ev_count++ 258 #define BGE_EVCNT_ADD(ev, val) (ev).ev_count += (val) 259 #define BGE_EVCNT_UPD(ev, val) (ev).ev_count = (val) 260 #else 261 #define BGE_EVCNT_INCR(ev) /* nothing */ 262 #define BGE_EVCNT_ADD(ev, val) /* nothing */ 263 #define BGE_EVCNT_UPD(ev, val) /* nothing */ 264 #endif 265 266 static const struct bge_product { 267 pci_vendor_id_t bp_vendor; 268 pci_product_id_t bp_product; 269 const char *bp_name; 270 } bge_products[] = { 271 /* 272 * The BCM5700 documentation seems to indicate that the hardware 273 * still has the Alteon vendor ID burned into it, though it 274 * should always be overridden by the value in the EEPROM. We'll 275 * check for it anyway. 276 */ 277 { PCI_VENDOR_ALTEON, 278 PCI_PRODUCT_ALTEON_BCM5700, 279 "Broadcom BCM5700 Gigabit Ethernet", 280 }, 281 { PCI_VENDOR_ALTEON, 282 PCI_PRODUCT_ALTEON_BCM5701, 283 "Broadcom BCM5701 Gigabit Ethernet", 284 }, 285 { PCI_VENDOR_ALTIMA, 286 PCI_PRODUCT_ALTIMA_AC1000, 287 "Altima AC1000 Gigabit Ethernet", 288 }, 289 { PCI_VENDOR_ALTIMA, 290 PCI_PRODUCT_ALTIMA_AC1001, 291 "Altima AC1001 Gigabit Ethernet", 292 }, 293 { PCI_VENDOR_ALTIMA, 294 PCI_PRODUCT_ALTIMA_AC9100, 295 "Altima AC9100 Gigabit Ethernet", 296 }, 297 { PCI_VENDOR_BROADCOM, 298 PCI_PRODUCT_BROADCOM_BCM5700, 299 "Broadcom BCM5700 Gigabit Ethernet", 300 }, 301 { PCI_VENDOR_BROADCOM, 302 PCI_PRODUCT_BROADCOM_BCM5701, 303 "Broadcom BCM5701 Gigabit Ethernet", 304 }, 305 { PCI_VENDOR_BROADCOM, 306 PCI_PRODUCT_BROADCOM_BCM5702, 307 "Broadcom BCM5702 Gigabit Ethernet", 308 }, 309 { PCI_VENDOR_BROADCOM, 310 PCI_PRODUCT_BROADCOM_BCM5702X, 311 "Broadcom BCM5702X Gigabit Ethernet" }, 312 { PCI_VENDOR_BROADCOM, 313 PCI_PRODUCT_BROADCOM_BCM5703, 314 "Broadcom BCM5703 Gigabit Ethernet", 315 }, 316 { PCI_VENDOR_BROADCOM, 317 PCI_PRODUCT_BROADCOM_BCM5703X, 318 "Broadcom BCM5703X Gigabit Ethernet", 319 }, 320 { PCI_VENDOR_BROADCOM, 321 PCI_PRODUCT_BROADCOM_BCM5703_ALT, 322 "Broadcom BCM5703 Gigabit Ethernet", 323 }, 324 { PCI_VENDOR_BROADCOM, 325 PCI_PRODUCT_BROADCOM_BCM5704C, 326 "Broadcom BCM5704C Dual Gigabit Ethernet", 327 }, 328 { PCI_VENDOR_BROADCOM, 329 PCI_PRODUCT_BROADCOM_BCM5704S, 330 "Broadcom BCM5704S Dual Gigabit Ethernet", 331 }, 332 { PCI_VENDOR_BROADCOM, 333 PCI_PRODUCT_BROADCOM_BCM5705, 334 "Broadcom BCM5705 Gigabit Ethernet", 335 }, 336 { PCI_VENDOR_BROADCOM, 337 PCI_PRODUCT_BROADCOM_BCM5705K, 338 "Broadcom BCM5705K Gigabit Ethernet", 339 }, 340 { PCI_VENDOR_BROADCOM, 341 PCI_PRODUCT_BROADCOM_BCM5705M, 342 "Broadcom BCM5705M Gigabit Ethernet", 343 }, 344 { PCI_VENDOR_BROADCOM, 345 PCI_PRODUCT_BROADCOM_BCM5705M_ALT, 346 "Broadcom BCM5705M Gigabit Ethernet", 347 }, 348 { PCI_VENDOR_BROADCOM, 349 PCI_PRODUCT_BROADCOM_BCM5714, 350 "Broadcom BCM5714/5715 Gigabit Ethernet", 351 }, 352 { PCI_VENDOR_BROADCOM, 353 PCI_PRODUCT_BROADCOM_BCM5715, 354 "Broadcom BCM5714/5715 Gigabit Ethernet", 355 }, 356 { PCI_VENDOR_BROADCOM, 357 PCI_PRODUCT_BROADCOM_BCM5789, 358 "Broadcom BCM5789 Gigabit Ethernet", 359 }, 360 { PCI_VENDOR_BROADCOM, 361 PCI_PRODUCT_BROADCOM_BCM5721, 362 "Broadcom BCM5721 Gigabit Ethernet", 363 }, 364 { PCI_VENDOR_BROADCOM, 365 PCI_PRODUCT_BROADCOM_BCM5722, 366 "Broadcom BCM5722 Gigabit Ethernet", 367 }, 368 { PCI_VENDOR_BROADCOM, 369 PCI_PRODUCT_BROADCOM_BCM5750, 370 "Broadcom BCM5750 Gigabit Ethernet", 371 }, 372 { PCI_VENDOR_BROADCOM, 373 PCI_PRODUCT_BROADCOM_BCM5750M, 374 "Broadcom BCM5750M Gigabit Ethernet", 375 }, 376 { PCI_VENDOR_BROADCOM, 377 PCI_PRODUCT_BROADCOM_BCM5751, 378 "Broadcom BCM5751 Gigabit Ethernet", 379 }, 380 { PCI_VENDOR_BROADCOM, 381 PCI_PRODUCT_BROADCOM_BCM5751M, 382 "Broadcom BCM5751M Gigabit Ethernet", 383 }, 384 { PCI_VENDOR_BROADCOM, 385 PCI_PRODUCT_BROADCOM_BCM5752, 386 "Broadcom BCM5752 Gigabit Ethernet", 387 }, 388 { PCI_VENDOR_BROADCOM, 389 PCI_PRODUCT_BROADCOM_BCM5752M, 390 "Broadcom BCM5752M Gigabit Ethernet", 391 }, 392 { PCI_VENDOR_BROADCOM, 393 PCI_PRODUCT_BROADCOM_BCM5753, 394 "Broadcom BCM5753 Gigabit Ethernet", 395 }, 396 { PCI_VENDOR_BROADCOM, 397 PCI_PRODUCT_BROADCOM_BCM5753M, 398 "Broadcom BCM5753M Gigabit Ethernet", 399 }, 400 { PCI_VENDOR_BROADCOM, 401 PCI_PRODUCT_BROADCOM_BCM5754, 402 "Broadcom BCM5754 Gigabit Ethernet", 403 }, 404 { PCI_VENDOR_BROADCOM, 405 PCI_PRODUCT_BROADCOM_BCM5754M, 406 "Broadcom BCM5754M Gigabit Ethernet", 407 }, 408 { PCI_VENDOR_BROADCOM, 409 PCI_PRODUCT_BROADCOM_BCM5755, 410 "Broadcom BCM5755 Gigabit Ethernet", 411 }, 412 { PCI_VENDOR_BROADCOM, 413 PCI_PRODUCT_BROADCOM_BCM5755M, 414 "Broadcom BCM5755M Gigabit Ethernet", 415 }, 416 { PCI_VENDOR_BROADCOM, 417 PCI_PRODUCT_BROADCOM_BCM5780, 418 "Broadcom BCM5780 Gigabit Ethernet", 419 }, 420 { PCI_VENDOR_BROADCOM, 421 PCI_PRODUCT_BROADCOM_BCM5780S, 422 "Broadcom BCM5780S Gigabit Ethernet", 423 }, 424 { PCI_VENDOR_BROADCOM, 425 PCI_PRODUCT_BROADCOM_BCM5782, 426 "Broadcom BCM5782 Gigabit Ethernet", 427 }, 428 { PCI_VENDOR_BROADCOM, 429 PCI_PRODUCT_BROADCOM_BCM5786, 430 "Broadcom BCM5786 Gigabit Ethernet", 431 }, 432 { PCI_VENDOR_BROADCOM, 433 PCI_PRODUCT_BROADCOM_BCM5787, 434 "Broadcom BCM5787 Gigabit Ethernet", 435 }, 436 { PCI_VENDOR_BROADCOM, 437 PCI_PRODUCT_BROADCOM_BCM5787M, 438 "Broadcom BCM5787M Gigabit Ethernet", 439 }, 440 { PCI_VENDOR_BROADCOM, 441 PCI_PRODUCT_BROADCOM_BCM5788, 442 "Broadcom BCM5788 Gigabit Ethernet", 443 }, 444 { PCI_VENDOR_BROADCOM, 445 PCI_PRODUCT_BROADCOM_BCM5789, 446 "Broadcom BCM5789 Gigabit Ethernet", 447 }, 448 { PCI_VENDOR_BROADCOM, 449 PCI_PRODUCT_BROADCOM_BCM5901, 450 "Broadcom BCM5901 Fast Ethernet", 451 }, 452 { PCI_VENDOR_BROADCOM, 453 PCI_PRODUCT_BROADCOM_BCM5901A2, 454 "Broadcom BCM5901A2 Fast Ethernet", 455 }, 456 { PCI_VENDOR_SCHNEIDERKOCH, 457 PCI_PRODUCT_SCHNEIDERKOCH_SK_9DX1, 458 "SysKonnect SK-9Dx1 Gigabit Ethernet", 459 }, 460 { PCI_VENDOR_3COM, 461 PCI_PRODUCT_3COM_3C996, 462 "3Com 3c996 Gigabit Ethernet", 463 }, 464 { PCI_VENDOR_BROADCOM, 465 PCI_PRODUCT_BROADCOM_BCM5906, 466 "Broadcom BCM5906 Fast Ethernet", 467 }, 468 { PCI_VENDOR_BROADCOM, 469 PCI_PRODUCT_BROADCOM_BCM5906M, 470 "Broadcom BCM5906M Fast Ethernet", 471 }, 472 { 0, 473 0, 474 NULL }, 475 }; 476 477 /* 478 * XXX: how to handle variants based on 5750 and derivatives: 479 * 5750 5751, 5721, possibly 5714, 5752, and 5708?, which 480 * in general behave like a 5705, except with additional quirks. 481 * This driver's current handling of the 5721 is wrong; 482 * how we map ASIC revision to "quirks" needs more thought. 483 * (defined here until the thought is done). 484 */ 485 #define BGE_IS_5714_FAMILY(sc) \ 486 (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5714_A0 || \ 487 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5780 || \ 488 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5714 ) 489 490 #define BGE_IS_5750_OR_BEYOND(sc) \ 491 (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5750 || \ 492 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5752 || \ 493 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5755 || \ 494 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5787 || \ 495 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906 || \ 496 BGE_IS_5714_FAMILY(sc) ) 497 498 #define BGE_IS_5705_OR_BEYOND(sc) \ 499 (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5705 || \ 500 (BGE_IS_5750_OR_BEYOND(sc))) 501 502 static const struct bge_revision { 503 uint32_t br_chipid; 504 const char *br_name; 505 } bge_revisions[] = { 506 { BGE_CHIPID_BCM5700_A0, "BCM5700 A0" }, 507 { BGE_CHIPID_BCM5700_A1, "BCM5700 A1" }, 508 { BGE_CHIPID_BCM5700_B0, "BCM5700 B0" }, 509 { BGE_CHIPID_BCM5700_B1, "BCM5700 B1" }, 510 { BGE_CHIPID_BCM5700_B2, "BCM5700 B2" }, 511 { BGE_CHIPID_BCM5700_B3, "BCM5700 B3" }, 512 /* This is treated like a BCM5700 Bx */ 513 { BGE_CHIPID_BCM5700_ALTIMA, "BCM5700 Altima" }, 514 { BGE_CHIPID_BCM5700_C0, "BCM5700 C0" }, 515 { BGE_CHIPID_BCM5701_A0, "BCM5701 A0" }, 516 { BGE_CHIPID_BCM5701_B0, "BCM5701 B0" }, 517 { BGE_CHIPID_BCM5701_B2, "BCM5701 B2" }, 518 { BGE_CHIPID_BCM5701_B5, "BCM5701 B5" }, 519 { BGE_CHIPID_BCM5703_A0, "BCM5703 A0" }, 520 { BGE_CHIPID_BCM5703_A1, "BCM5703 A1" }, 521 { BGE_CHIPID_BCM5703_A2, "BCM5703 A2" }, 522 { BGE_CHIPID_BCM5703_A3, "BCM5703 A3" }, 523 { BGE_CHIPID_BCM5703_B0, "BCM5703 B0" }, 524 { BGE_CHIPID_BCM5704_A0, "BCM5704 A0" }, 525 { BGE_CHIPID_BCM5704_A1, "BCM5704 A1" }, 526 { BGE_CHIPID_BCM5704_A2, "BCM5704 A2" }, 527 { BGE_CHIPID_BCM5704_A3, "BCM5704 A3" }, 528 { BGE_CHIPID_BCM5704_B0, "BCM5704 B0" }, 529 { BGE_CHIPID_BCM5705_A0, "BCM5705 A0" }, 530 { BGE_CHIPID_BCM5705_A1, "BCM5705 A1" }, 531 { BGE_CHIPID_BCM5705_A2, "BCM5705 A2" }, 532 { BGE_CHIPID_BCM5705_A3, "BCM5705 A3" }, 533 { BGE_CHIPID_BCM5750_A0, "BCM5750 A0" }, 534 { BGE_CHIPID_BCM5750_A1, "BCM5750 A1" }, 535 { BGE_CHIPID_BCM5750_A3, "BCM5750 A3" }, 536 { BGE_CHIPID_BCM5750_B0, "BCM5750 B0" }, 537 { BGE_CHIPID_BCM5750_B1, "BCM5750 B1" }, 538 { BGE_CHIPID_BCM5750_C0, "BCM5750 C0" }, 539 { BGE_CHIPID_BCM5750_C1, "BCM5750 C1" }, 540 { BGE_CHIPID_BCM5750_C2, "BCM5750 C2" }, 541 { BGE_CHIPID_BCM5752_A0, "BCM5752 A0" }, 542 { BGE_CHIPID_BCM5752_A1, "BCM5752 A1" }, 543 { BGE_CHIPID_BCM5752_A2, "BCM5752 A2" }, 544 { BGE_CHIPID_BCM5714_A0, "BCM5714 A0" }, 545 { BGE_CHIPID_BCM5714_B0, "BCM5714 B0" }, 546 { BGE_CHIPID_BCM5714_B3, "BCM5714 B3" }, 547 { BGE_CHIPID_BCM5715_A0, "BCM5715 A0" }, 548 { BGE_CHIPID_BCM5715_A1, "BCM5715 A1" }, 549 { BGE_CHIPID_BCM5715_A3, "BCM5715 A3" }, 550 { BGE_CHIPID_BCM5755_A0, "BCM5755 A0" }, 551 { BGE_CHIPID_BCM5755_A1, "BCM5755 A1" }, 552 { BGE_CHIPID_BCM5755_A2, "BCM5755 A2" }, 553 { BGE_CHIPID_BCM5755_C0, "BCM5755 C0" }, 554 { BGE_CHIPID_BCM5787_A0, "BCM5754/5787 A0" }, 555 { BGE_CHIPID_BCM5787_A1, "BCM5754/5787 A1" }, 556 { BGE_CHIPID_BCM5787_A2, "BCM5754/5787 A2" }, 557 { BGE_CHIPID_BCM5906_A1, "BCM5906 A1" }, 558 { BGE_CHIPID_BCM5906_A2, "BCM5906 A2" }, 559 { 0, NULL } 560 }; 561 562 /* 563 * Some defaults for major revisions, so that newer steppings 564 * that we don't know about have a shot at working. 565 */ 566 static const struct bge_revision bge_majorrevs[] = { 567 { BGE_ASICREV_BCM5700, "unknown BCM5700" }, 568 { BGE_ASICREV_BCM5701, "unknown BCM5701" }, 569 { BGE_ASICREV_BCM5703, "unknown BCM5703" }, 570 { BGE_ASICREV_BCM5704, "unknown BCM5704" }, 571 { BGE_ASICREV_BCM5705, "unknown BCM5705" }, 572 { BGE_ASICREV_BCM5750, "unknown BCM5750" }, 573 { BGE_ASICREV_BCM5714_A0, "unknown BCM5714" }, 574 { BGE_ASICREV_BCM5714, "unknown BCM5714" }, 575 { BGE_ASICREV_BCM5752, "unknown BCM5752 family" }, 576 { BGE_ASICREV_BCM5755, "unknown BCM5755" }, 577 { BGE_ASICREV_BCM5780, "unknown BCM5780" }, 578 /* 5754 and 5787 share the same ASIC ID */ 579 { BGE_ASICREV_BCM5787, "unknown BCM5787/5787" }, 580 { BGE_ASICREV_BCM5906, "unknown BCM5906" }, 581 { 0, NULL } 582 }; 583 584 CFATTACH_DECL_NEW(bge, sizeof(struct bge_softc), 585 bge_probe, bge_attach, NULL, NULL); 586 587 static u_int32_t 588 bge_readmem_ind(struct bge_softc *sc, int off) 589 { 590 pcireg_t val; 591 592 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_BASEADDR, off); 593 val = pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_DATA); 594 return val; 595 } 596 597 static void 598 bge_writemem_ind(struct bge_softc *sc, int off, int val) 599 { 600 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_BASEADDR, off); 601 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_DATA, val); 602 } 603 604 #ifdef notdef 605 static u_int32_t 606 bge_readreg_ind(struct bge_softc *sc, int off) 607 { 608 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_REG_BASEADDR, off); 609 return (pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_REG_DATA)); 610 } 611 #endif 612 613 static void 614 bge_writereg_ind(struct bge_softc *sc, int off, int val) 615 { 616 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_REG_BASEADDR, off); 617 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_REG_DATA, val); 618 } 619 620 static void 621 bge_writemem_direct(struct bge_softc *sc, int off, int val) 622 { 623 CSR_WRITE_4(sc, off, val); 624 } 625 626 static void 627 bge_writembx(struct bge_softc *sc, int off, int val) 628 { 629 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 630 off += BGE_LPMBX_IRQ0_HI - BGE_MBX_IRQ0_HI; 631 632 CSR_WRITE_4(sc, off, val); 633 } 634 635 static u_int8_t 636 bge_nvram_getbyte(struct bge_softc *sc, int addr, u_int8_t *dest) 637 { 638 u_int32_t access, byte = 0; 639 int i; 640 641 /* Lock. */ 642 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_SET1); 643 for (i = 0; i < 8000; i++) { 644 if (CSR_READ_4(sc, BGE_NVRAM_SWARB) & BGE_NVRAMSWARB_GNT1) 645 break; 646 DELAY(20); 647 } 648 if (i == 8000) 649 return (1); 650 651 /* Enable access. */ 652 access = CSR_READ_4(sc, BGE_NVRAM_ACCESS); 653 CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access | BGE_NVRAMACC_ENABLE); 654 655 CSR_WRITE_4(sc, BGE_NVRAM_ADDR, addr & 0xfffffffc); 656 CSR_WRITE_4(sc, BGE_NVRAM_CMD, BGE_NVRAM_READCMD); 657 for (i = 0; i < BGE_TIMEOUT * 10; i++) { 658 DELAY(10); 659 if (CSR_READ_4(sc, BGE_NVRAM_CMD) & BGE_NVRAMCMD_DONE) { 660 DELAY(10); 661 break; 662 } 663 } 664 665 if (i == BGE_TIMEOUT * 10) { 666 aprint_error_dev(sc->bge_dev, "nvram read timed out\n"); 667 return (1); 668 } 669 670 /* Get result. */ 671 byte = CSR_READ_4(sc, BGE_NVRAM_RDDATA); 672 673 *dest = (bswap32(byte) >> ((addr % 4) * 8)) & 0xFF; 674 675 /* Disable access. */ 676 CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access); 677 678 /* Unlock. */ 679 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_CLR1); 680 CSR_READ_4(sc, BGE_NVRAM_SWARB); 681 682 return (0); 683 } 684 685 /* 686 * Read a sequence of bytes from NVRAM. 687 */ 688 static int 689 bge_read_nvram(struct bge_softc *sc, u_int8_t *dest, int off, int cnt) 690 { 691 int err = 0, i; 692 u_int8_t byte = 0; 693 694 if (BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5906) 695 return (1); 696 697 for (i = 0; i < cnt; i++) { 698 err = bge_nvram_getbyte(sc, off + i, &byte); 699 if (err) 700 break; 701 *(dest + i) = byte; 702 } 703 704 return (err ? 1 : 0); 705 } 706 707 /* 708 * Read a byte of data stored in the EEPROM at address 'addr.' The 709 * BCM570x supports both the traditional bitbang interface and an 710 * auto access interface for reading the EEPROM. We use the auto 711 * access method. 712 */ 713 static u_int8_t 714 bge_eeprom_getbyte(struct bge_softc *sc, int addr, u_int8_t *dest) 715 { 716 int i; 717 u_int32_t byte = 0; 718 719 /* 720 * Enable use of auto EEPROM access so we can avoid 721 * having to use the bitbang method. 722 */ 723 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM); 724 725 /* Reset the EEPROM, load the clock period. */ 726 CSR_WRITE_4(sc, BGE_EE_ADDR, 727 BGE_EEADDR_RESET | BGE_EEHALFCLK(BGE_HALFCLK_384SCL)); 728 DELAY(20); 729 730 /* Issue the read EEPROM command. */ 731 CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr); 732 733 /* Wait for completion */ 734 for(i = 0; i < BGE_TIMEOUT * 10; i++) { 735 DELAY(10); 736 if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE) 737 break; 738 } 739 740 if (i == BGE_TIMEOUT) { 741 aprint_error_dev(sc->bge_dev, "eeprom read timed out\n"); 742 return (0); 743 } 744 745 /* Get result. */ 746 byte = CSR_READ_4(sc, BGE_EE_DATA); 747 748 *dest = (byte >> ((addr % 4) * 8)) & 0xFF; 749 750 return (0); 751 } 752 753 /* 754 * Read a sequence of bytes from the EEPROM. 755 */ 756 static int 757 bge_read_eeprom(struct bge_softc *sc, void *destv, int off, int cnt) 758 { 759 int err = 0, i; 760 u_int8_t byte = 0; 761 char *dest = destv; 762 763 for (i = 0; i < cnt; i++) { 764 err = bge_eeprom_getbyte(sc, off + i, &byte); 765 if (err) 766 break; 767 *(dest + i) = byte; 768 } 769 770 return (err ? 1 : 0); 771 } 772 773 static int 774 bge_miibus_readreg(device_t dev, int phy, int reg) 775 { 776 struct bge_softc *sc = device_private(dev); 777 u_int32_t val; 778 u_int32_t saved_autopoll; 779 int i; 780 781 /* 782 * Broadcom's own driver always assumes the internal 783 * PHY is at GMII address 1. On some chips, the PHY responds 784 * to accesses at all addresses, which could cause us to 785 * bogusly attach the PHY 32 times at probe type. Always 786 * restricting the lookup to address 1 is simpler than 787 * trying to figure out which chips revisions should be 788 * special-cased. 789 */ 790 if (phy != 1) 791 return (0); 792 793 /* Reading with autopolling on may trigger PCI errors */ 794 saved_autopoll = CSR_READ_4(sc, BGE_MI_MODE); 795 if (saved_autopoll & BGE_MIMODE_AUTOPOLL) { 796 BGE_STS_CLRBIT(sc, BGE_STS_AUTOPOLL); 797 CSR_WRITE_4(sc, BGE_MI_MODE, 798 saved_autopoll &~ BGE_MIMODE_AUTOPOLL); 799 DELAY(40); 800 } 801 802 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_READ|BGE_MICOMM_BUSY| 803 BGE_MIPHY(phy)|BGE_MIREG(reg)); 804 805 for (i = 0; i < BGE_TIMEOUT; i++) { 806 val = CSR_READ_4(sc, BGE_MI_COMM); 807 if (!(val & BGE_MICOMM_BUSY)) 808 break; 809 delay(10); 810 } 811 812 if (i == BGE_TIMEOUT) { 813 aprint_error_dev(sc->bge_dev, "PHY read timed out\n"); 814 val = 0; 815 goto done; 816 } 817 818 val = CSR_READ_4(sc, BGE_MI_COMM); 819 820 done: 821 if (saved_autopoll & BGE_MIMODE_AUTOPOLL) { 822 BGE_STS_SETBIT(sc, BGE_STS_AUTOPOLL); 823 CSR_WRITE_4(sc, BGE_MI_MODE, saved_autopoll); 824 DELAY(40); 825 } 826 827 if (val & BGE_MICOMM_READFAIL) 828 return (0); 829 830 return (val & 0xFFFF); 831 } 832 833 static void 834 bge_miibus_writereg(device_t dev, int phy, int reg, int val) 835 { 836 struct bge_softc *sc = device_private(dev); 837 u_int32_t saved_autopoll; 838 int i; 839 840 if (phy!=1) { 841 return; 842 } 843 844 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906 && 845 (reg == BRGPHY_MII_1000CTL || reg == BRGPHY_MII_AUXCTL)) { 846 return; 847 } 848 849 /* Reading with autopolling on may trigger PCI errors */ 850 saved_autopoll = CSR_READ_4(sc, BGE_MI_MODE); 851 if (saved_autopoll & BGE_MIMODE_AUTOPOLL) { 852 delay(40); 853 BGE_STS_CLRBIT(sc, BGE_STS_AUTOPOLL); 854 CSR_WRITE_4(sc, BGE_MI_MODE, 855 saved_autopoll & (~BGE_MIMODE_AUTOPOLL)); 856 delay(10); /* 40 usec is supposed to be adequate */ 857 } 858 859 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_WRITE | BGE_MICOMM_BUSY | 860 BGE_MIPHY(phy) | BGE_MIREG(reg)|val); 861 862 for (i = 0; i < BGE_TIMEOUT; i++) { 863 delay(10); 864 if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY)) { 865 delay(5); 866 CSR_READ_4(sc, BGE_MI_COMM); 867 break; 868 } 869 } 870 871 if (saved_autopoll & BGE_MIMODE_AUTOPOLL) { 872 BGE_STS_SETBIT(sc, BGE_STS_AUTOPOLL); 873 CSR_WRITE_4(sc, BGE_MI_MODE, saved_autopoll); 874 delay(40); 875 } 876 877 if (i == BGE_TIMEOUT) 878 aprint_error_dev(sc->bge_dev, "PHY read timed out\n"); 879 } 880 881 static void 882 bge_miibus_statchg(device_t dev) 883 { 884 struct bge_softc *sc = device_private(dev); 885 struct mii_data *mii = &sc->bge_mii; 886 887 /* 888 * Get flow control negotiation result. 889 */ 890 if (IFM_SUBTYPE(mii->mii_media.ifm_cur->ifm_media) == IFM_AUTO && 891 (mii->mii_media_active & IFM_ETH_FMASK) != sc->bge_flowflags) { 892 sc->bge_flowflags = mii->mii_media_active & IFM_ETH_FMASK; 893 mii->mii_media_active &= ~IFM_ETH_FMASK; 894 } 895 896 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_PORTMODE); 897 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T || 898 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX) 899 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_GMII); 900 else 901 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_MII); 902 903 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) 904 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX); 905 else 906 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX); 907 908 /* 909 * 802.3x flow control 910 */ 911 if (sc->bge_flowflags & IFM_ETH_RXPAUSE) 912 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_FLOWCTL_ENABLE); 913 else 914 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_FLOWCTL_ENABLE); 915 916 if (sc->bge_flowflags & IFM_ETH_TXPAUSE) 917 BGE_SETBIT(sc, BGE_TX_MODE, BGE_TXMODE_FLOWCTL_ENABLE); 918 else 919 BGE_CLRBIT(sc, BGE_TX_MODE, BGE_TXMODE_FLOWCTL_ENABLE); 920 } 921 922 /* 923 * Update rx threshold levels to values in a particular slot 924 * of the interrupt-mitigation table bge_rx_threshes. 925 */ 926 static void 927 bge_set_thresh(struct ifnet *ifp, int lvl) 928 { 929 struct bge_softc *sc = ifp->if_softc; 930 int s; 931 932 /* For now, just save the new Rx-intr thresholds and record 933 * that a threshold update is pending. Updating the hardware 934 * registers here (even at splhigh()) is observed to 935 * occasionaly cause glitches where Rx-interrupts are not 936 * honoured for up to 10 seconds. jonathan (at) NetBSD.org, 2003-04-05 937 */ 938 s = splnet(); 939 sc->bge_rx_coal_ticks = bge_rx_threshes[lvl].rx_ticks; 940 sc->bge_rx_max_coal_bds = bge_rx_threshes[lvl].rx_max_bds; 941 sc->bge_pending_rxintr_change = 1; 942 splx(s); 943 944 return; 945 } 946 947 948 /* 949 * Update Rx thresholds of all bge devices 950 */ 951 static void 952 bge_update_all_threshes(int lvl) 953 { 954 struct ifnet *ifp; 955 const char * const namebuf = "bge"; 956 int namelen; 957 958 if (lvl < 0) 959 lvl = 0; 960 else if( lvl >= NBGE_RX_THRESH) 961 lvl = NBGE_RX_THRESH - 1; 962 963 namelen = strlen(namebuf); 964 /* 965 * Now search all the interfaces for this name/number 966 */ 967 IFNET_FOREACH(ifp) { 968 if (strncmp(ifp->if_xname, namebuf, namelen) != 0) 969 continue; 970 /* We got a match: update if doing auto-threshold-tuning */ 971 if (bge_auto_thresh) 972 bge_set_thresh(ifp, lvl); 973 } 974 } 975 976 /* 977 * Handle events that have triggered interrupts. 978 */ 979 static void 980 bge_handle_events(struct bge_softc *sc) 981 { 982 983 return; 984 } 985 986 /* 987 * Memory management for jumbo frames. 988 */ 989 990 static int 991 bge_alloc_jumbo_mem(struct bge_softc *sc) 992 { 993 char *ptr, *kva; 994 bus_dma_segment_t seg; 995 int i, rseg, state, error; 996 struct bge_jpool_entry *entry; 997 998 state = error = 0; 999 1000 /* Grab a big chunk o' storage. */ 1001 if (bus_dmamem_alloc(sc->bge_dmatag, BGE_JMEM, PAGE_SIZE, 0, 1002 &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 1003 aprint_error_dev(sc->bge_dev, "can't alloc rx buffers\n"); 1004 return ENOBUFS; 1005 } 1006 1007 state = 1; 1008 if (bus_dmamem_map(sc->bge_dmatag, &seg, rseg, BGE_JMEM, (void **)&kva, 1009 BUS_DMA_NOWAIT)) { 1010 aprint_error_dev(sc->bge_dev, 1011 "can't map DMA buffers (%d bytes)\n", (int)BGE_JMEM); 1012 error = ENOBUFS; 1013 goto out; 1014 } 1015 1016 state = 2; 1017 if (bus_dmamap_create(sc->bge_dmatag, BGE_JMEM, 1, BGE_JMEM, 0, 1018 BUS_DMA_NOWAIT, &sc->bge_cdata.bge_rx_jumbo_map)) { 1019 aprint_error_dev(sc->bge_dev, "can't create DMA map\n"); 1020 error = ENOBUFS; 1021 goto out; 1022 } 1023 1024 state = 3; 1025 if (bus_dmamap_load(sc->bge_dmatag, sc->bge_cdata.bge_rx_jumbo_map, 1026 kva, BGE_JMEM, NULL, BUS_DMA_NOWAIT)) { 1027 aprint_error_dev(sc->bge_dev, "can't load DMA map\n"); 1028 error = ENOBUFS; 1029 goto out; 1030 } 1031 1032 state = 4; 1033 sc->bge_cdata.bge_jumbo_buf = (void *)kva; 1034 DPRINTFN(1,("bge_jumbo_buf = %p\n", sc->bge_cdata.bge_jumbo_buf)); 1035 1036 SLIST_INIT(&sc->bge_jfree_listhead); 1037 SLIST_INIT(&sc->bge_jinuse_listhead); 1038 1039 /* 1040 * Now divide it up into 9K pieces and save the addresses 1041 * in an array. 1042 */ 1043 ptr = sc->bge_cdata.bge_jumbo_buf; 1044 for (i = 0; i < BGE_JSLOTS; i++) { 1045 sc->bge_cdata.bge_jslots[i] = ptr; 1046 ptr += BGE_JLEN; 1047 entry = malloc(sizeof(struct bge_jpool_entry), 1048 M_DEVBUF, M_NOWAIT); 1049 if (entry == NULL) { 1050 aprint_error_dev(sc->bge_dev, 1051 "no memory for jumbo buffer queue!\n"); 1052 error = ENOBUFS; 1053 goto out; 1054 } 1055 entry->slot = i; 1056 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, 1057 entry, jpool_entries); 1058 } 1059 out: 1060 if (error != 0) { 1061 switch (state) { 1062 case 4: 1063 bus_dmamap_unload(sc->bge_dmatag, 1064 sc->bge_cdata.bge_rx_jumbo_map); 1065 case 3: 1066 bus_dmamap_destroy(sc->bge_dmatag, 1067 sc->bge_cdata.bge_rx_jumbo_map); 1068 case 2: 1069 bus_dmamem_unmap(sc->bge_dmatag, kva, BGE_JMEM); 1070 case 1: 1071 bus_dmamem_free(sc->bge_dmatag, &seg, rseg); 1072 break; 1073 default: 1074 break; 1075 } 1076 } 1077 1078 return error; 1079 } 1080 1081 /* 1082 * Allocate a jumbo buffer. 1083 */ 1084 static void * 1085 bge_jalloc(struct bge_softc *sc) 1086 { 1087 struct bge_jpool_entry *entry; 1088 1089 entry = SLIST_FIRST(&sc->bge_jfree_listhead); 1090 1091 if (entry == NULL) { 1092 aprint_error_dev(sc->bge_dev, "no free jumbo buffers\n"); 1093 return (NULL); 1094 } 1095 1096 SLIST_REMOVE_HEAD(&sc->bge_jfree_listhead, jpool_entries); 1097 SLIST_INSERT_HEAD(&sc->bge_jinuse_listhead, entry, jpool_entries); 1098 return (sc->bge_cdata.bge_jslots[entry->slot]); 1099 } 1100 1101 /* 1102 * Release a jumbo buffer. 1103 */ 1104 static void 1105 bge_jfree(struct mbuf *m, void *buf, size_t size, void *arg) 1106 { 1107 struct bge_jpool_entry *entry; 1108 struct bge_softc *sc; 1109 int i, s; 1110 1111 /* Extract the softc struct pointer. */ 1112 sc = (struct bge_softc *)arg; 1113 1114 if (sc == NULL) 1115 panic("bge_jfree: can't find softc pointer!"); 1116 1117 /* calculate the slot this buffer belongs to */ 1118 1119 i = ((char *)buf 1120 - (char *)sc->bge_cdata.bge_jumbo_buf) / BGE_JLEN; 1121 1122 if ((i < 0) || (i >= BGE_JSLOTS)) 1123 panic("bge_jfree: asked to free buffer that we don't manage!"); 1124 1125 s = splvm(); 1126 entry = SLIST_FIRST(&sc->bge_jinuse_listhead); 1127 if (entry == NULL) 1128 panic("bge_jfree: buffer not in use!"); 1129 entry->slot = i; 1130 SLIST_REMOVE_HEAD(&sc->bge_jinuse_listhead, jpool_entries); 1131 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, entry, jpool_entries); 1132 1133 if (__predict_true(m != NULL)) 1134 pool_cache_put(mb_cache, m); 1135 splx(s); 1136 } 1137 1138 1139 /* 1140 * Intialize a standard receive ring descriptor. 1141 */ 1142 static int 1143 bge_newbuf_std(struct bge_softc *sc, int i, struct mbuf *m, bus_dmamap_t dmamap) 1144 { 1145 struct mbuf *m_new = NULL; 1146 struct bge_rx_bd *r; 1147 int error; 1148 1149 if (dmamap == NULL) { 1150 error = bus_dmamap_create(sc->bge_dmatag, MCLBYTES, 1, 1151 MCLBYTES, 0, BUS_DMA_NOWAIT, &dmamap); 1152 if (error != 0) 1153 return error; 1154 } 1155 1156 sc->bge_cdata.bge_rx_std_map[i] = dmamap; 1157 1158 if (m == NULL) { 1159 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1160 if (m_new == NULL) 1161 return (ENOBUFS); 1162 1163 MCLGET(m_new, M_DONTWAIT); 1164 if (!(m_new->m_flags & M_EXT)) { 1165 m_freem(m_new); 1166 return (ENOBUFS); 1167 } 1168 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1169 1170 } else { 1171 m_new = m; 1172 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1173 m_new->m_data = m_new->m_ext.ext_buf; 1174 } 1175 if (!(sc->bge_flags & BGE_RX_ALIGNBUG)) 1176 m_adj(m_new, ETHER_ALIGN); 1177 if (bus_dmamap_load_mbuf(sc->bge_dmatag, dmamap, m_new, 1178 BUS_DMA_READ|BUS_DMA_NOWAIT)) 1179 return (ENOBUFS); 1180 bus_dmamap_sync(sc->bge_dmatag, dmamap, 0, dmamap->dm_mapsize, 1181 BUS_DMASYNC_PREREAD); 1182 1183 sc->bge_cdata.bge_rx_std_chain[i] = m_new; 1184 r = &sc->bge_rdata->bge_rx_std_ring[i]; 1185 bge_set_hostaddr(&r->bge_addr, 1186 dmamap->dm_segs[0].ds_addr); 1187 r->bge_flags = BGE_RXBDFLAG_END; 1188 r->bge_len = m_new->m_len; 1189 r->bge_idx = i; 1190 1191 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 1192 offsetof(struct bge_ring_data, bge_rx_std_ring) + 1193 i * sizeof (struct bge_rx_bd), 1194 sizeof (struct bge_rx_bd), 1195 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1196 1197 return (0); 1198 } 1199 1200 /* 1201 * Initialize a jumbo receive ring descriptor. This allocates 1202 * a jumbo buffer from the pool managed internally by the driver. 1203 */ 1204 static int 1205 bge_newbuf_jumbo(struct bge_softc *sc, int i, struct mbuf *m) 1206 { 1207 struct mbuf *m_new = NULL; 1208 struct bge_rx_bd *r; 1209 void *buf = NULL; 1210 1211 if (m == NULL) { 1212 1213 /* Allocate the mbuf. */ 1214 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1215 if (m_new == NULL) 1216 return (ENOBUFS); 1217 1218 /* Allocate the jumbo buffer */ 1219 buf = bge_jalloc(sc); 1220 if (buf == NULL) { 1221 m_freem(m_new); 1222 aprint_error_dev(sc->bge_dev, 1223 "jumbo allocation failed -- packet dropped!\n"); 1224 return (ENOBUFS); 1225 } 1226 1227 /* Attach the buffer to the mbuf. */ 1228 m_new->m_len = m_new->m_pkthdr.len = BGE_JUMBO_FRAMELEN; 1229 MEXTADD(m_new, buf, BGE_JUMBO_FRAMELEN, M_DEVBUF, 1230 bge_jfree, sc); 1231 m_new->m_flags |= M_EXT_RW; 1232 } else { 1233 m_new = m; 1234 buf = m_new->m_data = m_new->m_ext.ext_buf; 1235 m_new->m_ext.ext_size = BGE_JUMBO_FRAMELEN; 1236 } 1237 if (!(sc->bge_flags & BGE_RX_ALIGNBUG)) 1238 m_adj(m_new, ETHER_ALIGN); 1239 bus_dmamap_sync(sc->bge_dmatag, sc->bge_cdata.bge_rx_jumbo_map, 1240 mtod(m_new, char *) - (char *)sc->bge_cdata.bge_jumbo_buf, BGE_JLEN, 1241 BUS_DMASYNC_PREREAD); 1242 /* Set up the descriptor. */ 1243 r = &sc->bge_rdata->bge_rx_jumbo_ring[i]; 1244 sc->bge_cdata.bge_rx_jumbo_chain[i] = m_new; 1245 bge_set_hostaddr(&r->bge_addr, BGE_JUMBO_DMA_ADDR(sc, m_new)); 1246 r->bge_flags = BGE_RXBDFLAG_END|BGE_RXBDFLAG_JUMBO_RING; 1247 r->bge_len = m_new->m_len; 1248 r->bge_idx = i; 1249 1250 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 1251 offsetof(struct bge_ring_data, bge_rx_jumbo_ring) + 1252 i * sizeof (struct bge_rx_bd), 1253 sizeof (struct bge_rx_bd), 1254 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1255 1256 return (0); 1257 } 1258 1259 /* 1260 * The standard receive ring has 512 entries in it. At 2K per mbuf cluster, 1261 * that's 1MB or memory, which is a lot. For now, we fill only the first 1262 * 256 ring entries and hope that our CPU is fast enough to keep up with 1263 * the NIC. 1264 */ 1265 static int 1266 bge_init_rx_ring_std(struct bge_softc *sc) 1267 { 1268 int i; 1269 1270 if (sc->bge_flags & BGE_RXRING_VALID) 1271 return 0; 1272 1273 for (i = 0; i < BGE_SSLOTS; i++) { 1274 if (bge_newbuf_std(sc, i, NULL, 0) == ENOBUFS) 1275 return (ENOBUFS); 1276 } 1277 1278 sc->bge_std = i - 1; 1279 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std); 1280 1281 sc->bge_flags |= BGE_RXRING_VALID; 1282 1283 return (0); 1284 } 1285 1286 static void 1287 bge_free_rx_ring_std(struct bge_softc *sc) 1288 { 1289 int i; 1290 1291 if (!(sc->bge_flags & BGE_RXRING_VALID)) 1292 return; 1293 1294 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { 1295 if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) { 1296 m_freem(sc->bge_cdata.bge_rx_std_chain[i]); 1297 sc->bge_cdata.bge_rx_std_chain[i] = NULL; 1298 bus_dmamap_destroy(sc->bge_dmatag, 1299 sc->bge_cdata.bge_rx_std_map[i]); 1300 } 1301 memset((char *)&sc->bge_rdata->bge_rx_std_ring[i], 0, 1302 sizeof(struct bge_rx_bd)); 1303 } 1304 1305 sc->bge_flags &= ~BGE_RXRING_VALID; 1306 } 1307 1308 static int 1309 bge_init_rx_ring_jumbo(struct bge_softc *sc) 1310 { 1311 int i; 1312 volatile struct bge_rcb *rcb; 1313 1314 if (sc->bge_flags & BGE_JUMBO_RXRING_VALID) 1315 return 0; 1316 1317 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 1318 if (bge_newbuf_jumbo(sc, i, NULL) == ENOBUFS) 1319 return (ENOBUFS); 1320 }; 1321 1322 sc->bge_jumbo = i - 1; 1323 sc->bge_flags |= BGE_JUMBO_RXRING_VALID; 1324 1325 rcb = &sc->bge_rdata->bge_info.bge_jumbo_rx_rcb; 1326 rcb->bge_maxlen_flags = 0; 1327 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 1328 1329 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo); 1330 1331 return (0); 1332 } 1333 1334 static void 1335 bge_free_rx_ring_jumbo(struct bge_softc *sc) 1336 { 1337 int i; 1338 1339 if (!(sc->bge_flags & BGE_JUMBO_RXRING_VALID)) 1340 return; 1341 1342 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 1343 if (sc->bge_cdata.bge_rx_jumbo_chain[i] != NULL) { 1344 m_freem(sc->bge_cdata.bge_rx_jumbo_chain[i]); 1345 sc->bge_cdata.bge_rx_jumbo_chain[i] = NULL; 1346 } 1347 memset((char *)&sc->bge_rdata->bge_rx_jumbo_ring[i], 0, 1348 sizeof(struct bge_rx_bd)); 1349 } 1350 1351 sc->bge_flags &= ~BGE_JUMBO_RXRING_VALID; 1352 } 1353 1354 static void 1355 bge_free_tx_ring(struct bge_softc *sc) 1356 { 1357 int i, freed; 1358 struct txdmamap_pool_entry *dma; 1359 1360 if (!(sc->bge_flags & BGE_TXRING_VALID)) 1361 return; 1362 1363 freed = 0; 1364 1365 for (i = 0; i < BGE_TX_RING_CNT; i++) { 1366 if (sc->bge_cdata.bge_tx_chain[i] != NULL) { 1367 freed++; 1368 m_freem(sc->bge_cdata.bge_tx_chain[i]); 1369 sc->bge_cdata.bge_tx_chain[i] = NULL; 1370 SLIST_INSERT_HEAD(&sc->txdma_list, sc->txdma[i], 1371 link); 1372 sc->txdma[i] = 0; 1373 } 1374 memset((char *)&sc->bge_rdata->bge_tx_ring[i], 0, 1375 sizeof(struct bge_tx_bd)); 1376 } 1377 1378 while ((dma = SLIST_FIRST(&sc->txdma_list))) { 1379 SLIST_REMOVE_HEAD(&sc->txdma_list, link); 1380 bus_dmamap_destroy(sc->bge_dmatag, dma->dmamap); 1381 free(dma, M_DEVBUF); 1382 } 1383 1384 sc->bge_flags &= ~BGE_TXRING_VALID; 1385 } 1386 1387 static int 1388 bge_init_tx_ring(struct bge_softc *sc) 1389 { 1390 int i; 1391 bus_dmamap_t dmamap; 1392 struct txdmamap_pool_entry *dma; 1393 1394 if (sc->bge_flags & BGE_TXRING_VALID) 1395 return 0; 1396 1397 sc->bge_txcnt = 0; 1398 sc->bge_tx_saved_considx = 0; 1399 1400 /* Initialize transmit producer index for host-memory send ring. */ 1401 sc->bge_tx_prodidx = 0; 1402 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx); 1403 /* 5700 b2 errata */ 1404 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX) 1405 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx); 1406 1407 /* NIC-memory send ring not used; initialize to zero. */ 1408 bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0); 1409 /* 5700 b2 errata */ 1410 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX) 1411 bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0); 1412 1413 SLIST_INIT(&sc->txdma_list); 1414 for (i = 0; i < BGE_RSLOTS; i++) { 1415 if (bus_dmamap_create(sc->bge_dmatag, BGE_TXDMA_MAX, 1416 BGE_NTXSEG, ETHER_MAX_LEN_JUMBO, 0, BUS_DMA_NOWAIT, 1417 &dmamap)) 1418 return (ENOBUFS); 1419 if (dmamap == NULL) 1420 panic("dmamap NULL in bge_init_tx_ring"); 1421 dma = malloc(sizeof(*dma), M_DEVBUF, M_NOWAIT); 1422 if (dma == NULL) { 1423 aprint_error_dev(sc->bge_dev, 1424 "can't alloc txdmamap_pool_entry\n"); 1425 bus_dmamap_destroy(sc->bge_dmatag, dmamap); 1426 return (ENOMEM); 1427 } 1428 dma->dmamap = dmamap; 1429 SLIST_INSERT_HEAD(&sc->txdma_list, dma, link); 1430 } 1431 1432 sc->bge_flags |= BGE_TXRING_VALID; 1433 1434 return (0); 1435 } 1436 1437 static void 1438 bge_setmulti(struct bge_softc *sc) 1439 { 1440 struct ethercom *ac = &sc->ethercom; 1441 struct ifnet *ifp = &ac->ec_if; 1442 struct ether_multi *enm; 1443 struct ether_multistep step; 1444 u_int32_t hashes[4] = { 0, 0, 0, 0 }; 1445 u_int32_t h; 1446 int i; 1447 1448 if (ifp->if_flags & IFF_PROMISC) 1449 goto allmulti; 1450 1451 /* Now program new ones. */ 1452 ETHER_FIRST_MULTI(step, ac, enm); 1453 while (enm != NULL) { 1454 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1455 /* 1456 * We must listen to a range of multicast addresses. 1457 * For now, just accept all multicasts, rather than 1458 * trying to set only those filter bits needed to match 1459 * the range. (At this time, the only use of address 1460 * ranges is for IP multicast routing, for which the 1461 * range is big enough to require all bits set.) 1462 */ 1463 goto allmulti; 1464 } 1465 1466 h = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN); 1467 1468 /* Just want the 7 least-significant bits. */ 1469 h &= 0x7f; 1470 1471 hashes[(h & 0x60) >> 5] |= 1 << (h & 0x1F); 1472 ETHER_NEXT_MULTI(step, enm); 1473 } 1474 1475 ifp->if_flags &= ~IFF_ALLMULTI; 1476 goto setit; 1477 1478 allmulti: 1479 ifp->if_flags |= IFF_ALLMULTI; 1480 hashes[0] = hashes[1] = hashes[2] = hashes[3] = 0xffffffff; 1481 1482 setit: 1483 for (i = 0; i < 4; i++) 1484 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]); 1485 } 1486 1487 const int bge_swapbits[] = { 1488 0, 1489 BGE_MODECTL_BYTESWAP_DATA, 1490 BGE_MODECTL_WORDSWAP_DATA, 1491 BGE_MODECTL_BYTESWAP_NONFRAME, 1492 BGE_MODECTL_WORDSWAP_NONFRAME, 1493 1494 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA, 1495 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_BYTESWAP_NONFRAME, 1496 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_NONFRAME, 1497 1498 BGE_MODECTL_WORDSWAP_DATA|BGE_MODECTL_BYTESWAP_NONFRAME, 1499 BGE_MODECTL_WORDSWAP_DATA|BGE_MODECTL_WORDSWAP_NONFRAME, 1500 1501 BGE_MODECTL_BYTESWAP_NONFRAME|BGE_MODECTL_WORDSWAP_NONFRAME, 1502 1503 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA| 1504 BGE_MODECTL_BYTESWAP_NONFRAME, 1505 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA| 1506 BGE_MODECTL_WORDSWAP_NONFRAME, 1507 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_BYTESWAP_NONFRAME| 1508 BGE_MODECTL_WORDSWAP_NONFRAME, 1509 BGE_MODECTL_WORDSWAP_DATA|BGE_MODECTL_BYTESWAP_NONFRAME| 1510 BGE_MODECTL_WORDSWAP_NONFRAME, 1511 1512 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA| 1513 BGE_MODECTL_BYTESWAP_NONFRAME|BGE_MODECTL_WORDSWAP_NONFRAME, 1514 }; 1515 1516 int bge_swapindex = 0; 1517 1518 /* 1519 * Do endian, PCI and DMA initialization. Also check the on-board ROM 1520 * self-test results. 1521 */ 1522 static int 1523 bge_chipinit(struct bge_softc *sc) 1524 { 1525 int i; 1526 u_int32_t dma_rw_ctl; 1527 1528 1529 /* Set endianness before we access any non-PCI registers. */ 1530 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MISC_CTL, 1531 BGE_INIT); 1532 1533 /* Set power state to D0. */ 1534 bge_setpowerstate(sc, 0); 1535 1536 /* 1537 * Check the 'ROM failed' bit on the RX CPU to see if 1538 * self-tests passed. 1539 */ 1540 if (CSR_READ_4(sc, BGE_RXCPU_MODE) & BGE_RXCPUMODE_ROMFAIL) { 1541 aprint_error_dev(sc->bge_dev, 1542 "RX CPU self-diagnostics failed!\n"); 1543 return (ENODEV); 1544 } 1545 1546 /* Clear the MAC control register */ 1547 CSR_WRITE_4(sc, BGE_MAC_MODE, 0); 1548 1549 /* 1550 * Clear the MAC statistics block in the NIC's 1551 * internal memory. 1552 */ 1553 for (i = BGE_STATS_BLOCK; 1554 i < BGE_STATS_BLOCK_END + 1; i += sizeof(u_int32_t)) 1555 BGE_MEMWIN_WRITE(sc->sc_pc, sc->sc_pcitag, i, 0); 1556 1557 for (i = BGE_STATUS_BLOCK; 1558 i < BGE_STATUS_BLOCK_END + 1; i += sizeof(u_int32_t)) 1559 BGE_MEMWIN_WRITE(sc->sc_pc, sc->sc_pcitag, i, 0); 1560 1561 /* Set up the PCI DMA control register. */ 1562 if (sc->bge_flags & BGE_PCIE) { 1563 u_int32_t device_ctl; 1564 1565 /* From FreeBSD */ 1566 DPRINTFN(4, ("(%s: PCI-Express DMA setting)\n", 1567 device_xname(sc->bge_dev))); 1568 dma_rw_ctl = (BGE_PCI_READ_CMD | BGE_PCI_WRITE_CMD | 1569 (0xf << BGE_PCIDMARWCTL_RD_WAT_SHIFT) | 1570 (0x2 << BGE_PCIDMARWCTL_WR_WAT_SHIFT)); 1571 1572 /* jonathan: alternative from Linux driver */ 1573 #define DMA_CTRL_WRITE_PCIE_H20MARK_128 0x00180000 1574 #define DMA_CTRL_WRITE_PCIE_H20MARK_256 0x00380000 1575 1576 dma_rw_ctl = 0x76000000; /* XXX XXX XXX */; 1577 device_ctl = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 1578 BGE_PCI_CONF_DEV_CTRL); 1579 aprint_debug_dev(sc->bge_dev, "pcie mode=0x%x\n", device_ctl); 1580 1581 if ((device_ctl & 0x00e0) && 0) { 1582 /* 1583 * XXX jonathan (at) NetBSD.org: 1584 * This clause is exactly what the Broadcom-supplied 1585 * Linux does; but given overall register programming 1586 * by if_bge(4), this larger DMA-write watermark 1587 * value causes bcm5721 chips to totally wedge. 1588 */ 1589 dma_rw_ctl |= BGE_PCIDMA_RWCTL_PCIE_WRITE_WATRMARK_256; 1590 } else { 1591 dma_rw_ctl |= BGE_PCIDMA_RWCTL_PCIE_WRITE_WATRMARK_128; 1592 } 1593 } else if (sc->bge_flags & BGE_PCIX){ 1594 DPRINTFN(4, ("(:%s: PCI-X DMA setting)\n", 1595 device_xname(sc->bge_dev))); 1596 /* PCI-X bus */ 1597 dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD | 1598 (0x3 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) | 1599 (0x3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT) | 1600 (0x0F); 1601 /* 1602 * 5703 and 5704 need ONEDMA_AT_ONCE as a workaround 1603 * for hardware bugs, which means we should also clear 1604 * the low-order MINDMA bits. In addition, the 5704 1605 * uses a different encoding of read/write watermarks. 1606 */ 1607 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) { 1608 dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD | 1609 /* should be 0x1f0000 */ 1610 (0x7 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) | 1611 (0x3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT); 1612 dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE; 1613 } 1614 else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5703) { 1615 dma_rw_ctl &= 0xfffffff0; 1616 dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE; 1617 } 1618 else if (BGE_IS_5714_FAMILY(sc)) { 1619 dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD; 1620 dma_rw_ctl &= ~BGE_PCIDMARWCTL_ONEDMA_ATONCE; /* XXX */ 1621 /* XXX magic values, Broadcom-supplied Linux driver */ 1622 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5780) 1623 dma_rw_ctl |= (1 << 20) | (1 << 18) | 1624 BGE_PCIDMARWCTL_ONEDMA_ATONCE; 1625 else 1626 dma_rw_ctl |= (1<<20) | (1<<18) | (1 << 15); 1627 } 1628 } else { 1629 /* Conventional PCI bus */ 1630 DPRINTFN(4, ("(%s: PCI 2.2 DMA setting)\n", 1631 device_xname(sc->bge_dev))); 1632 dma_rw_ctl = (BGE_PCI_READ_CMD | BGE_PCI_WRITE_CMD | 1633 (0x7 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) | 1634 (0x7 << BGE_PCIDMARWCTL_WR_WAT_SHIFT)); 1635 if (BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5705 && 1636 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5750) 1637 dma_rw_ctl |= 0x0F; 1638 } 1639 1640 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 1641 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5701) 1642 dma_rw_ctl |= BGE_PCIDMARWCTL_USE_MRM | 1643 BGE_PCIDMARWCTL_ASRT_ALL_BE; 1644 1645 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5703 || 1646 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) 1647 dma_rw_ctl &= ~BGE_PCIDMARWCTL_MINDMA; 1648 1649 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_DMA_RW_CTL, dma_rw_ctl); 1650 1651 /* 1652 * Set up general mode register. 1653 */ 1654 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS | 1655 BGE_MODECTL_MAC_ATTN_INTR | BGE_MODECTL_HOST_SEND_BDS | 1656 BGE_MODECTL_TX_NO_PHDR_CSUM | BGE_MODECTL_RX_NO_PHDR_CSUM); 1657 1658 /* 1659 * Disable memory write invalidate. Apparently it is not supported 1660 * properly by these devices. 1661 */ 1662 PCI_CLRBIT(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CMD, PCIM_CMD_MWIEN); 1663 1664 1665 #ifdef __brokenalpha__ 1666 /* 1667 * Must insure that we do not cross an 8K (bytes) boundary 1668 * for DMA reads. Our highest limit is 1K bytes. This is a 1669 * restriction on some ALPHA platforms with early revision 1670 * 21174 PCI chipsets, such as the AlphaPC 164lx 1671 */ 1672 PCI_SETBIT(sc, BGE_PCI_DMA_RW_CTL, BGE_PCI_READ_BNDRY_1024, 4); 1673 #endif 1674 1675 /* Set the timer prescaler (always 66MHz) */ 1676 CSR_WRITE_4(sc, BGE_MISC_CFG, 65 << 1/*BGE_32BITTIME_66MHZ*/); 1677 1678 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 1679 DELAY(40); /* XXX */ 1680 1681 /* Put PHY into ready state */ 1682 BGE_CLRBIT(sc, BGE_MISC_CFG, BGE_MISCCFG_EPHY_IDDQ); 1683 CSR_READ_4(sc, BGE_MISC_CFG); /* Flush */ 1684 DELAY(40); 1685 } 1686 1687 return (0); 1688 } 1689 1690 static int 1691 bge_blockinit(struct bge_softc *sc) 1692 { 1693 volatile struct bge_rcb *rcb; 1694 bus_size_t rcb_addr; 1695 int i; 1696 struct ifnet *ifp = &sc->ethercom.ec_if; 1697 bge_hostaddr taddr; 1698 u_int32_t val; 1699 1700 /* 1701 * Initialize the memory window pointer register so that 1702 * we can access the first 32K of internal NIC RAM. This will 1703 * allow us to set up the TX send ring RCBs and the RX return 1704 * ring RCBs, plus other things which live in NIC memory. 1705 */ 1706 1707 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_BASEADDR, 0); 1708 1709 /* Configure mbuf memory pool */ 1710 if (!(BGE_IS_5705_OR_BEYOND(sc))) { 1711 if (sc->bge_extram) { 1712 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, 1713 BGE_EXT_SSRAM); 1714 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) 1715 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000); 1716 else 1717 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000); 1718 } else { 1719 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, 1720 BGE_BUFFPOOL_1); 1721 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) 1722 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000); 1723 else 1724 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000); 1725 } 1726 1727 /* Configure DMA resource pool */ 1728 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_BASEADDR, 1729 BGE_DMA_DESCRIPTORS); 1730 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LEN, 0x2000); 1731 } 1732 1733 /* Configure mbuf pool watermarks */ 1734 #ifdef ORIG_WPAUL_VALUES 1735 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 24); 1736 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 24); 1737 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 48); 1738 #else 1739 1740 /* new broadcom docs strongly recommend these: */ 1741 if (!BGE_IS_5705_OR_BEYOND(sc)) { 1742 if (ifp->if_mtu > ETHER_MAX_LEN) { 1743 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x50); 1744 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x20); 1745 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60); 1746 } else { 1747 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 304); 1748 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 152); 1749 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 380); 1750 } 1751 } else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 1752 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0); 1753 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x04); 1754 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x10); 1755 } else { 1756 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0); 1757 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x10); 1758 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60); 1759 } 1760 #endif 1761 1762 /* Configure DMA resource watermarks */ 1763 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5); 1764 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10); 1765 1766 /* Enable buffer manager */ 1767 if (!BGE_IS_5705_OR_BEYOND(sc)) { 1768 CSR_WRITE_4(sc, BGE_BMAN_MODE, 1769 BGE_BMANMODE_ENABLE | BGE_BMANMODE_LOMBUF_ATTN); 1770 1771 /* Poll for buffer manager start indication */ 1772 for (i = 0; i < BGE_TIMEOUT; i++) { 1773 if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE) 1774 break; 1775 DELAY(10); 1776 } 1777 1778 if (i == BGE_TIMEOUT) { 1779 aprint_error_dev(sc->bge_dev, 1780 "buffer manager failed to start\n"); 1781 return (ENXIO); 1782 } 1783 } 1784 1785 /* Enable flow-through queues */ 1786 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 1787 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 1788 1789 /* Wait until queue initialization is complete */ 1790 for (i = 0; i < BGE_TIMEOUT; i++) { 1791 if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0) 1792 break; 1793 DELAY(10); 1794 } 1795 1796 if (i == BGE_TIMEOUT) { 1797 aprint_error_dev(sc->bge_dev, 1798 "flow-through queue init failed\n"); 1799 return (ENXIO); 1800 } 1801 1802 /* Initialize the standard RX ring control block */ 1803 rcb = &sc->bge_rdata->bge_info.bge_std_rx_rcb; 1804 bge_set_hostaddr(&rcb->bge_hostaddr, 1805 BGE_RING_DMA_ADDR(sc, bge_rx_std_ring)); 1806 if (BGE_IS_5705_OR_BEYOND(sc)) 1807 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(512, 0); 1808 else 1809 rcb->bge_maxlen_flags = 1810 BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 0); 1811 if (sc->bge_extram) 1812 rcb->bge_nicaddr = BGE_EXT_STD_RX_RINGS; 1813 else 1814 rcb->bge_nicaddr = BGE_STD_RX_RINGS; 1815 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcb->bge_hostaddr.bge_addr_hi); 1816 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcb->bge_hostaddr.bge_addr_lo); 1817 CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 1818 CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcb->bge_nicaddr); 1819 1820 if (BGE_IS_5705_OR_BEYOND(sc)) 1821 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT_5705; 1822 else 1823 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT; 1824 1825 /* 1826 * Initialize the jumbo RX ring control block 1827 * We set the 'ring disabled' bit in the flags 1828 * field until we're actually ready to start 1829 * using this ring (i.e. once we set the MTU 1830 * high enough to require it). 1831 */ 1832 if (!BGE_IS_5705_OR_BEYOND(sc)) { 1833 rcb = &sc->bge_rdata->bge_info.bge_jumbo_rx_rcb; 1834 bge_set_hostaddr(&rcb->bge_hostaddr, 1835 BGE_RING_DMA_ADDR(sc, bge_rx_jumbo_ring)); 1836 rcb->bge_maxlen_flags = 1837 BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 1838 BGE_RCB_FLAG_RING_DISABLED); 1839 if (sc->bge_extram) 1840 rcb->bge_nicaddr = BGE_EXT_JUMBO_RX_RINGS; 1841 else 1842 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS; 1843 1844 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI, 1845 rcb->bge_hostaddr.bge_addr_hi); 1846 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO, 1847 rcb->bge_hostaddr.bge_addr_lo); 1848 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, 1849 rcb->bge_maxlen_flags); 1850 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcb->bge_nicaddr); 1851 1852 /* Set up dummy disabled mini ring RCB */ 1853 rcb = &sc->bge_rdata->bge_info.bge_mini_rx_rcb; 1854 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0, 1855 BGE_RCB_FLAG_RING_DISABLED); 1856 CSR_WRITE_4(sc, BGE_RX_MINI_RCB_MAXLEN_FLAGS, 1857 rcb->bge_maxlen_flags); 1858 1859 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 1860 offsetof(struct bge_ring_data, bge_info), 1861 sizeof (struct bge_gib), 1862 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1863 } 1864 1865 /* 1866 * Set the BD ring replenish thresholds. The recommended 1867 * values are 1/8th the number of descriptors allocated to 1868 * each ring. 1869 */ 1870 i = BGE_STD_RX_RING_CNT / 8; 1871 1872 /* 1873 * Use a value of 8 for the following chips to workaround HW errata. 1874 * Some of these chips have been added based on empirical 1875 * evidence (they don't work unless this is done). 1876 */ 1877 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5750 || 1878 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5752 || 1879 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5755 || 1880 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5787 || 1881 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 1882 i = 8; 1883 1884 CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, i); 1885 CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH, BGE_JUMBO_RX_RING_CNT / 8); 1886 1887 /* 1888 * Disable all unused send rings by setting the 'ring disabled' 1889 * bit in the flags field of all the TX send ring control blocks. 1890 * These are located in NIC memory. 1891 */ 1892 rcb_addr = BGE_MEMWIN_START + BGE_SEND_RING_RCB; 1893 for (i = 0; i < BGE_TX_RINGS_EXTSSRAM_MAX; i++) { 1894 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 1895 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED)); 1896 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 0); 1897 rcb_addr += sizeof(struct bge_rcb); 1898 } 1899 1900 /* Configure TX RCB 0 (we use only the first ring) */ 1901 rcb_addr = BGE_MEMWIN_START + BGE_SEND_RING_RCB; 1902 bge_set_hostaddr(&taddr, BGE_RING_DMA_ADDR(sc, bge_tx_ring)); 1903 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi); 1904 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo); 1905 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 1906 BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT)); 1907 if (!(BGE_IS_5705_OR_BEYOND(sc))) 1908 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 1909 BGE_RCB_MAXLEN_FLAGS(BGE_TX_RING_CNT, 0)); 1910 1911 /* Disable all unused RX return rings */ 1912 rcb_addr = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB; 1913 for (i = 0; i < BGE_RX_RINGS_MAX; i++) { 1914 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_hi, 0); 1915 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_lo, 0); 1916 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 1917 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 1918 BGE_RCB_FLAG_RING_DISABLED)); 1919 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 0); 1920 bge_writembx(sc, BGE_MBX_RX_CONS0_LO + 1921 (i * (sizeof(u_int64_t))), 0); 1922 rcb_addr += sizeof(struct bge_rcb); 1923 } 1924 1925 /* Initialize RX ring indexes */ 1926 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, 0); 1927 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0); 1928 bge_writembx(sc, BGE_MBX_RX_MINI_PROD_LO, 0); 1929 1930 /* 1931 * Set up RX return ring 0 1932 * Note that the NIC address for RX return rings is 0x00000000. 1933 * The return rings live entirely within the host, so the 1934 * nicaddr field in the RCB isn't used. 1935 */ 1936 rcb_addr = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB; 1937 bge_set_hostaddr(&taddr, BGE_RING_DMA_ADDR(sc, bge_rx_return_ring)); 1938 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi); 1939 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo); 1940 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 0x00000000); 1941 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 1942 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 0)); 1943 1944 /* Set random backoff seed for TX */ 1945 CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF, 1946 CLLADDR(ifp->if_sadl)[0] + CLLADDR(ifp->if_sadl)[1] + 1947 CLLADDR(ifp->if_sadl)[2] + CLLADDR(ifp->if_sadl)[3] + 1948 CLLADDR(ifp->if_sadl)[4] + CLLADDR(ifp->if_sadl)[5] + 1949 BGE_TX_BACKOFF_SEED_MASK); 1950 1951 /* Set inter-packet gap */ 1952 CSR_WRITE_4(sc, BGE_TX_LENGTHS, 0x2620); 1953 1954 /* 1955 * Specify which ring to use for packets that don't match 1956 * any RX rules. 1957 */ 1958 CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08); 1959 1960 /* 1961 * Configure number of RX lists. One interrupt distribution 1962 * list, sixteen active lists, one bad frames class. 1963 */ 1964 CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181); 1965 1966 /* Inialize RX list placement stats mask. */ 1967 CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF); 1968 CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1); 1969 1970 /* Disable host coalescing until we get it set up */ 1971 CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000); 1972 1973 /* Poll to make sure it's shut down. */ 1974 for (i = 0; i < BGE_TIMEOUT; i++) { 1975 if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE)) 1976 break; 1977 DELAY(10); 1978 } 1979 1980 if (i == BGE_TIMEOUT) { 1981 aprint_error_dev(sc->bge_dev, 1982 "host coalescing engine failed to idle\n"); 1983 return (ENXIO); 1984 } 1985 1986 /* Set up host coalescing defaults */ 1987 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bge_rx_coal_ticks); 1988 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bge_tx_coal_ticks); 1989 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bge_rx_max_coal_bds); 1990 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bge_tx_max_coal_bds); 1991 if (!(BGE_IS_5705_OR_BEYOND(sc))) { 1992 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT, 0); 1993 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT, 0); 1994 } 1995 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 0); 1996 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 0); 1997 1998 /* Set up address of statistics block */ 1999 if (!(BGE_IS_5705_OR_BEYOND(sc))) { 2000 bge_set_hostaddr(&taddr, 2001 BGE_RING_DMA_ADDR(sc, bge_info.bge_stats)); 2002 CSR_WRITE_4(sc, BGE_HCC_STATS_TICKS, sc->bge_stat_ticks); 2003 CSR_WRITE_4(sc, BGE_HCC_STATS_BASEADDR, BGE_STATS_BLOCK); 2004 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_HI, taddr.bge_addr_hi); 2005 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_LO, taddr.bge_addr_lo); 2006 } 2007 2008 /* Set up address of status block */ 2009 bge_set_hostaddr(&taddr, BGE_RING_DMA_ADDR(sc, bge_status_block)); 2010 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_BASEADDR, BGE_STATUS_BLOCK); 2011 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI, taddr.bge_addr_hi); 2012 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO, taddr.bge_addr_lo); 2013 sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx = 0; 2014 sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx = 0; 2015 2016 /* Turn on host coalescing state machine */ 2017 CSR_WRITE_4(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE); 2018 2019 /* Turn on RX BD completion state machine and enable attentions */ 2020 CSR_WRITE_4(sc, BGE_RBDC_MODE, 2021 BGE_RBDCMODE_ENABLE | BGE_RBDCMODE_ATTN); 2022 2023 /* Turn on RX list placement state machine */ 2024 CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 2025 2026 /* Turn on RX list selector state machine. */ 2027 if (!(BGE_IS_5705_OR_BEYOND(sc))) 2028 CSR_WRITE_4(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 2029 2030 val = BGE_MACMODE_TXDMA_ENB | BGE_MACMODE_RXDMA_ENB | 2031 BGE_MACMODE_RX_STATS_CLEAR | BGE_MACMODE_TX_STATS_CLEAR | 2032 BGE_MACMODE_RX_STATS_ENB | BGE_MACMODE_TX_STATS_ENB | 2033 BGE_MACMODE_FRMHDR_DMA_ENB; 2034 2035 if (sc->bge_flags & BGE_PHY_FIBER_TBI) 2036 val |= BGE_PORTMODE_TBI; 2037 else if (sc->bge_flags & BGE_PHY_FIBER_MII) 2038 val |= BGE_PORTMODE_GMII; 2039 else 2040 val |= BGE_PORTMODE_MII; 2041 2042 /* Turn on DMA, clear stats */ 2043 CSR_WRITE_4(sc, BGE_MAC_MODE, val); 2044 2045 2046 /* Set misc. local control, enable interrupts on attentions */ 2047 sc->bge_local_ctrl_reg = BGE_MLC_INTR_ONATTN | BGE_MLC_AUTO_EEPROM; 2048 2049 #ifdef notdef 2050 /* Assert GPIO pins for PHY reset */ 2051 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUT0| 2052 BGE_MLC_MISCIO_OUT1|BGE_MLC_MISCIO_OUT2); 2053 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUTEN0| 2054 BGE_MLC_MISCIO_OUTEN1|BGE_MLC_MISCIO_OUTEN2); 2055 #endif 2056 2057 #if defined(not_quite_yet) 2058 /* Linux driver enables enable gpio pin #1 on 5700s */ 2059 if (sc->bge_chipid == BGE_CHIPID_BCM5700) { 2060 sc->bge_local_ctrl_reg |= 2061 (BGE_MLC_MISCIO_OUT1|BGE_MLC_MISCIO_OUTEN1); 2062 } 2063 #endif 2064 CSR_WRITE_4(sc, BGE_MISC_LOCAL_CTL, sc->bge_local_ctrl_reg); 2065 2066 /* Turn on DMA completion state machine */ 2067 if (!(BGE_IS_5705_OR_BEYOND(sc))) 2068 CSR_WRITE_4(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 2069 2070 /* Turn on write DMA state machine */ 2071 { 2072 uint32_t bge_wdma_mode = 2073 BGE_WDMAMODE_ENABLE|BGE_WDMAMODE_ALL_ATTNS; 2074 2075 /* Enable host coalescing bug fix; see Linux tg3.c */ 2076 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5755 || 2077 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5787) 2078 bge_wdma_mode |= (1 << 29); 2079 2080 CSR_WRITE_4(sc, BGE_WDMA_MODE, bge_wdma_mode); 2081 } 2082 2083 /* Turn on read DMA state machine */ 2084 { 2085 uint32_t dma_read_modebits; 2086 2087 dma_read_modebits = 2088 BGE_RDMAMODE_ENABLE | BGE_RDMAMODE_ALL_ATTNS; 2089 2090 if ((sc->bge_flags & BGE_PCIE) && 0) { 2091 dma_read_modebits |= BGE_RDMA_MODE_FIFO_LONG_BURST; 2092 } else if (BGE_IS_5705_OR_BEYOND(sc)) { 2093 dma_read_modebits |= BGE_RDMA_MODE_FIFO_SIZE_128; 2094 } 2095 2096 /* XXX broadcom-supplied linux driver; undocumented */ 2097 if (BGE_IS_5750_OR_BEYOND(sc)) { 2098 /* 2099 * XXX: magic values. 2100 * From Broadcom-supplied Linux driver; apparently 2101 * required to workaround a DMA bug affecting TSO 2102 * on bcm575x/bcm5721? 2103 */ 2104 dma_read_modebits |= (1 << 27); 2105 } 2106 CSR_WRITE_4(sc, BGE_RDMA_MODE, dma_read_modebits); 2107 } 2108 2109 /* Turn on RX data completion state machine */ 2110 CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 2111 2112 /* Turn on RX BD initiator state machine */ 2113 CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 2114 2115 /* Turn on RX data and RX BD initiator state machine */ 2116 CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE); 2117 2118 /* Turn on Mbuf cluster free state machine */ 2119 if (!(BGE_IS_5705_OR_BEYOND(sc))) 2120 CSR_WRITE_4(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 2121 2122 /* Turn on send BD completion state machine */ 2123 CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 2124 2125 /* Turn on send data completion state machine */ 2126 CSR_WRITE_4(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE); 2127 2128 /* Turn on send data initiator state machine */ 2129 if (BGE_IS_5750_OR_BEYOND(sc)) { 2130 /* XXX: magic value from Linux driver */ 2131 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE | 0x08); 2132 } else { 2133 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 2134 } 2135 2136 /* Turn on send BD initiator state machine */ 2137 CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 2138 2139 /* Turn on send BD selector state machine */ 2140 CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 2141 2142 CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF); 2143 CSR_WRITE_4(sc, BGE_SDI_STATS_CTL, 2144 BGE_SDISTATSCTL_ENABLE | BGE_SDISTATSCTL_FASTER); 2145 2146 /* ack/clear link change events */ 2147 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED | 2148 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE | 2149 BGE_MACSTAT_CFG_CHANGED); 2150 CSR_WRITE_4(sc, BGE_MI_STS, 0); 2151 2152 /* Enable PHY auto polling (for MII/GMII only) */ 2153 if (sc->bge_flags & BGE_PHY_FIBER_TBI) { 2154 CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK); 2155 } else { 2156 BGE_STS_SETBIT(sc, BGE_STS_AUTOPOLL); 2157 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL | (10 << 16)); 2158 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700) 2159 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, 2160 BGE_EVTENB_MI_INTERRUPT); 2161 } 2162 2163 /* 2164 * Clear any pending link state attention. 2165 * Otherwise some link state change events may be lost until attention 2166 * is cleared by bge_intr() -> bge_link_upd() sequence. 2167 * It's not necessary on newer BCM chips - perhaps enabling link 2168 * state change attentions implies clearing pending attention. 2169 */ 2170 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED | 2171 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE | 2172 BGE_MACSTAT_LINK_CHANGED); 2173 2174 /* Enable link state change attentions. */ 2175 BGE_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED); 2176 2177 return (0); 2178 } 2179 2180 static const struct bge_revision * 2181 bge_lookup_rev(uint32_t chipid) 2182 { 2183 const struct bge_revision *br; 2184 2185 for (br = bge_revisions; br->br_name != NULL; br++) { 2186 if (br->br_chipid == chipid) 2187 return (br); 2188 } 2189 2190 for (br = bge_majorrevs; br->br_name != NULL; br++) { 2191 if (br->br_chipid == BGE_ASICREV(chipid)) 2192 return (br); 2193 } 2194 2195 return (NULL); 2196 } 2197 2198 static const struct bge_product * 2199 bge_lookup(const struct pci_attach_args *pa) 2200 { 2201 const struct bge_product *bp; 2202 2203 for (bp = bge_products; bp->bp_name != NULL; bp++) { 2204 if (PCI_VENDOR(pa->pa_id) == bp->bp_vendor && 2205 PCI_PRODUCT(pa->pa_id) == bp->bp_product) 2206 return (bp); 2207 } 2208 2209 return (NULL); 2210 } 2211 2212 static int 2213 bge_setpowerstate(struct bge_softc *sc, int powerlevel) 2214 { 2215 #ifdef NOTYET 2216 u_int32_t pm_ctl = 0; 2217 2218 /* XXX FIXME: make sure indirect accesses enabled? */ 2219 pm_ctl = pci_conf_read(sc->bge_dev, BGE_PCI_MISC_CTL, 4); 2220 pm_ctl |= BGE_PCIMISCCTL_INDIRECT_ACCESS; 2221 pci_write_config(sc->bge_dev, BGE_PCI_MISC_CTL, pm_ctl, 4); 2222 2223 /* clear the PME_assert bit and power state bits, enable PME */ 2224 pm_ctl = pci_conf_read(sc->bge_dev, BGE_PCI_PWRMGMT_CMD, 2); 2225 pm_ctl &= ~PCIM_PSTAT_DMASK; 2226 pm_ctl |= (1 << 8); 2227 2228 if (powerlevel == 0) { 2229 pm_ctl |= PCIM_PSTAT_D0; 2230 pci_write_config(sc->bge_dev, BGE_PCI_PWRMGMT_CMD, 2231 pm_ctl, 2); 2232 DELAY(10000); 2233 CSR_WRITE_4(sc, BGE_MISC_LOCAL_CTL, sc->bge_local_ctrl_reg); 2234 DELAY(10000); 2235 2236 #ifdef NOTYET 2237 /* XXX FIXME: write 0x02 to phy aux_Ctrl reg */ 2238 bge_miibus_writereg(sc->bge_dev, 1, 0x18, 0x02); 2239 #endif 2240 DELAY(40); DELAY(40); DELAY(40); 2241 DELAY(10000); /* above not quite adequate on 5700 */ 2242 return 0; 2243 } 2244 2245 2246 /* 2247 * Entering ACPI power states D1-D3 is achieved by wiggling 2248 * GMII gpio pins. Example code assumes all hardware vendors 2249 * followed Broadom's sample pcb layout. Until we verify that 2250 * for all supported OEM cards, states D1-D3 are unsupported. 2251 */ 2252 aprint_error_dev(sc->bge_dev, 2253 "power state %d unimplemented; check GPIO pins\n", 2254 powerlevel); 2255 #endif 2256 return EOPNOTSUPP; 2257 } 2258 2259 2260 /* 2261 * Probe for a Broadcom chip. Check the PCI vendor and device IDs 2262 * against our list and return its name if we find a match. Note 2263 * that since the Broadcom controller contains VPD support, we 2264 * can get the device name string from the controller itself instead 2265 * of the compiled-in string. This is a little slow, but it guarantees 2266 * we'll always announce the right product name. 2267 */ 2268 static int 2269 bge_probe(device_t parent, cfdata_t match, void *aux) 2270 { 2271 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 2272 2273 if (bge_lookup(pa) != NULL) 2274 return (1); 2275 2276 return (0); 2277 } 2278 2279 static void 2280 bge_attach(device_t parent, device_t self, void *aux) 2281 { 2282 struct bge_softc *sc = device_private(self); 2283 struct pci_attach_args *pa = aux; 2284 prop_dictionary_t dict; 2285 const struct bge_product *bp; 2286 const struct bge_revision *br; 2287 pci_chipset_tag_t pc; 2288 pci_intr_handle_t ih; 2289 const char *intrstr = NULL; 2290 bus_dma_segment_t seg; 2291 int rseg; 2292 u_int32_t hwcfg = 0; 2293 u_int32_t command; 2294 struct ifnet *ifp; 2295 u_int32_t misccfg; 2296 void * kva; 2297 u_char eaddr[ETHER_ADDR_LEN]; 2298 pcireg_t memtype; 2299 bus_addr_t memaddr; 2300 bus_size_t memsize; 2301 u_int32_t pm_ctl; 2302 2303 bp = bge_lookup(pa); 2304 KASSERT(bp != NULL); 2305 2306 sc->sc_pc = pa->pa_pc; 2307 sc->sc_pcitag = pa->pa_tag; 2308 sc->bge_dev = self; 2309 2310 aprint_naive(": Ethernet controller\n"); 2311 aprint_normal(": %s\n", bp->bp_name); 2312 2313 /* 2314 * Map control/status registers. 2315 */ 2316 DPRINTFN(5, ("Map control/status regs\n")); 2317 pc = sc->sc_pc; 2318 command = pci_conf_read(pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG); 2319 command |= PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_MASTER_ENABLE; 2320 pci_conf_write(pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG, command); 2321 command = pci_conf_read(pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG); 2322 2323 if (!(command & PCI_COMMAND_MEM_ENABLE)) { 2324 aprint_error_dev(sc->bge_dev, 2325 "failed to enable memory mapping!\n"); 2326 return; 2327 } 2328 2329 DPRINTFN(5, ("pci_mem_find\n")); 2330 memtype = pci_mapreg_type(sc->sc_pc, sc->sc_pcitag, BGE_PCI_BAR0); 2331 switch (memtype) { 2332 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 2333 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 2334 if (pci_mapreg_map(pa, BGE_PCI_BAR0, 2335 memtype, 0, &sc->bge_btag, &sc->bge_bhandle, 2336 &memaddr, &memsize) == 0) 2337 break; 2338 default: 2339 aprint_error_dev(sc->bge_dev, "can't find mem space\n"); 2340 return; 2341 } 2342 2343 DPRINTFN(5, ("pci_intr_map\n")); 2344 if (pci_intr_map(pa, &ih)) { 2345 aprint_error_dev(sc->bge_dev, "couldn't map interrupt\n"); 2346 return; 2347 } 2348 2349 DPRINTFN(5, ("pci_intr_string\n")); 2350 intrstr = pci_intr_string(pc, ih); 2351 2352 DPRINTFN(5, ("pci_intr_establish\n")); 2353 sc->bge_intrhand = pci_intr_establish(pc, ih, IPL_NET, bge_intr, sc); 2354 2355 if (sc->bge_intrhand == NULL) { 2356 aprint_error_dev(sc->bge_dev, 2357 "couldn't establish interrupt%s%s\n", 2358 intrstr ? " at " : "", intrstr ? intrstr : ""); 2359 return; 2360 } 2361 aprint_normal_dev(sc->bge_dev, "interrupting at %s\n", intrstr); 2362 2363 /* 2364 * Kludge for 5700 Bx bug: a hardware bug (PCIX byte enable?) 2365 * can clobber the chip's PCI config-space power control registers, 2366 * leaving the card in D3 powersave state. 2367 * We do not have memory-mapped registers in this state, 2368 * so force device into D0 state before starting initialization. 2369 */ 2370 pm_ctl = pci_conf_read(pc, sc->sc_pcitag, BGE_PCI_PWRMGMT_CMD); 2371 pm_ctl &= ~(PCI_PWR_D0|PCI_PWR_D1|PCI_PWR_D2|PCI_PWR_D3); 2372 pm_ctl |= (1 << 8) | PCI_PWR_D0 ; /* D0 state */ 2373 pci_conf_write(pc, sc->sc_pcitag, BGE_PCI_PWRMGMT_CMD, pm_ctl); 2374 DELAY(1000); /* 27 usec is allegedly sufficent */ 2375 2376 /* 2377 * Save ASIC rev. 2378 */ 2379 sc->bge_chipid = 2380 pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MISC_CTL) & 2381 BGE_PCIMISCCTL_ASICREV; 2382 2383 /* 2384 * Detect PCI-Express devices 2385 * XXX: guessed from Linux/FreeBSD; no documentation 2386 */ 2387 if (pci_get_capability(sc->sc_pc, sc->sc_pcitag, PCI_CAP_PCIEXPRESS, 2388 NULL, NULL) != 0) 2389 sc->bge_flags |= BGE_PCIE; 2390 2391 /* 2392 * PCI-X check. 2393 */ 2394 if ((pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_PCISTATE) & 2395 BGE_PCISTATE_PCI_BUSMODE) == 0) 2396 sc->bge_flags |= BGE_PCIX; 2397 2398 if (sc->bge_chipid == BGE_CHIPID_BCM5701_A0 || 2399 sc->bge_chipid == BGE_CHIPID_BCM5701_B0) 2400 sc->bge_flags |= BGE_PHY_CRC_BUG; 2401 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5703_AX || 2402 BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5704_AX) 2403 sc->bge_flags |= BGE_PHY_ADC_BUG; 2404 if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0) 2405 sc->bge_flags |= BGE_PHY_5704_A0_BUG; 2406 2407 if (BGE_IS_5705_OR_BEYOND(sc)) { 2408 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5755 || 2409 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5787) { 2410 if (PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_BROADCOM_BCM5722 && 2411 PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_BROADCOM_BCM5756) 2412 sc->bge_flags |= BGE_PHY_JITTER_BUG; 2413 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5755M) 2414 sc->bge_flags |= BGE_PHY_ADJUST_TRIM; 2415 } else if (BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5906) 2416 sc->bge_flags |= BGE_PHY_BER_BUG; 2417 } 2418 2419 /* Try to reset the chip. */ 2420 DPRINTFN(5, ("bge_reset\n")); 2421 bge_reset(sc); 2422 2423 if (bge_chipinit(sc)) { 2424 aprint_error_dev(sc->bge_dev, "chip initialization failed\n"); 2425 bge_release_resources(sc); 2426 return; 2427 } 2428 2429 /* 2430 * Get station address from the EEPROM. 2431 */ 2432 if (bge_get_eaddr(sc, eaddr)) { 2433 aprint_error_dev(sc->bge_dev, 2434 "failed to reade station address\n"); 2435 bge_release_resources(sc); 2436 return; 2437 } 2438 2439 br = bge_lookup_rev(sc->bge_chipid); 2440 2441 if (br == NULL) { 2442 aprint_normal_dev(sc->bge_dev, "unknown ASIC (0x%04x)", 2443 sc->bge_chipid >> 16); 2444 } else { 2445 aprint_normal_dev(sc->bge_dev, "ASIC %s (0x%04x)", 2446 br->br_name, sc->bge_chipid >> 16); 2447 } 2448 aprint_normal(", Ethernet address %s\n", ether_sprintf(eaddr)); 2449 2450 /* Allocate the general information block and ring buffers. */ 2451 if (pci_dma64_available(pa)) 2452 sc->bge_dmatag = pa->pa_dmat64; 2453 else 2454 sc->bge_dmatag = pa->pa_dmat; 2455 DPRINTFN(5, ("bus_dmamem_alloc\n")); 2456 if (bus_dmamem_alloc(sc->bge_dmatag, sizeof(struct bge_ring_data), 2457 PAGE_SIZE, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 2458 aprint_error_dev(sc->bge_dev, "can't alloc rx buffers\n"); 2459 return; 2460 } 2461 DPRINTFN(5, ("bus_dmamem_map\n")); 2462 if (bus_dmamem_map(sc->bge_dmatag, &seg, rseg, 2463 sizeof(struct bge_ring_data), &kva, 2464 BUS_DMA_NOWAIT)) { 2465 aprint_error_dev(sc->bge_dev, 2466 "can't map DMA buffers (%zu bytes)\n", 2467 sizeof(struct bge_ring_data)); 2468 bus_dmamem_free(sc->bge_dmatag, &seg, rseg); 2469 return; 2470 } 2471 DPRINTFN(5, ("bus_dmamem_create\n")); 2472 if (bus_dmamap_create(sc->bge_dmatag, sizeof(struct bge_ring_data), 1, 2473 sizeof(struct bge_ring_data), 0, 2474 BUS_DMA_NOWAIT, &sc->bge_ring_map)) { 2475 aprint_error_dev(sc->bge_dev, "can't create DMA map\n"); 2476 bus_dmamem_unmap(sc->bge_dmatag, kva, 2477 sizeof(struct bge_ring_data)); 2478 bus_dmamem_free(sc->bge_dmatag, &seg, rseg); 2479 return; 2480 } 2481 DPRINTFN(5, ("bus_dmamem_load\n")); 2482 if (bus_dmamap_load(sc->bge_dmatag, sc->bge_ring_map, kva, 2483 sizeof(struct bge_ring_data), NULL, 2484 BUS_DMA_NOWAIT)) { 2485 bus_dmamap_destroy(sc->bge_dmatag, sc->bge_ring_map); 2486 bus_dmamem_unmap(sc->bge_dmatag, kva, 2487 sizeof(struct bge_ring_data)); 2488 bus_dmamem_free(sc->bge_dmatag, &seg, rseg); 2489 return; 2490 } 2491 2492 DPRINTFN(5, ("bzero\n")); 2493 sc->bge_rdata = (struct bge_ring_data *)kva; 2494 2495 memset(sc->bge_rdata, 0, sizeof(struct bge_ring_data)); 2496 2497 /* Try to allocate memory for jumbo buffers. */ 2498 if (!(BGE_IS_5705_OR_BEYOND(sc))) { 2499 if (bge_alloc_jumbo_mem(sc)) { 2500 aprint_error_dev(sc->bge_dev, 2501 "jumbo buffer allocation failed\n"); 2502 } else 2503 sc->ethercom.ec_capabilities |= ETHERCAP_JUMBO_MTU; 2504 } 2505 2506 /* Set default tuneable values. */ 2507 sc->bge_stat_ticks = BGE_TICKS_PER_SEC; 2508 sc->bge_rx_coal_ticks = 150; 2509 sc->bge_rx_max_coal_bds = 64; 2510 #ifdef ORIG_WPAUL_VALUES 2511 sc->bge_tx_coal_ticks = 150; 2512 sc->bge_tx_max_coal_bds = 128; 2513 #else 2514 sc->bge_tx_coal_ticks = 300; 2515 sc->bge_tx_max_coal_bds = 400; 2516 #endif 2517 if (BGE_IS_5705_OR_BEYOND(sc)) { 2518 sc->bge_tx_coal_ticks = (12 * 5); 2519 sc->bge_tx_max_coal_bds = (12 * 5); 2520 aprint_verbose_dev(sc->bge_dev, 2521 "setting short Tx thresholds\n"); 2522 } 2523 2524 /* Set up ifnet structure */ 2525 ifp = &sc->ethercom.ec_if; 2526 ifp->if_softc = sc; 2527 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 2528 ifp->if_ioctl = bge_ioctl; 2529 ifp->if_stop = bge_stop; 2530 ifp->if_start = bge_start; 2531 ifp->if_init = bge_init; 2532 ifp->if_watchdog = bge_watchdog; 2533 IFQ_SET_MAXLEN(&ifp->if_snd, max(BGE_TX_RING_CNT - 1, IFQ_MAXLEN)); 2534 IFQ_SET_READY(&ifp->if_snd); 2535 DPRINTFN(5, ("strcpy if_xname\n")); 2536 strcpy(ifp->if_xname, device_xname(sc->bge_dev)); 2537 2538 if (sc->bge_chipid != BGE_CHIPID_BCM5700_B0) 2539 sc->ethercom.ec_if.if_capabilities |= 2540 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 2541 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 2542 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 2543 sc->ethercom.ec_capabilities |= 2544 ETHERCAP_VLAN_HWTAGGING | ETHERCAP_VLAN_MTU; 2545 2546 if (sc->bge_flags & BGE_PCIE) 2547 sc->ethercom.ec_if.if_capabilities |= IFCAP_TSOv4; 2548 2549 /* 2550 * Do MII setup. 2551 */ 2552 DPRINTFN(5, ("mii setup\n")); 2553 sc->bge_mii.mii_ifp = ifp; 2554 sc->bge_mii.mii_readreg = bge_miibus_readreg; 2555 sc->bge_mii.mii_writereg = bge_miibus_writereg; 2556 sc->bge_mii.mii_statchg = bge_miibus_statchg; 2557 2558 /* 2559 * Figure out what sort of media we have by checking the 2560 * hardware config word in the first 32k of NIC internal memory, 2561 * or fall back to the config word in the EEPROM. Note: on some BCM5700 2562 * cards, this value appears to be unset. If that's the 2563 * case, we have to rely on identifying the NIC by its PCI 2564 * subsystem ID, as we do below for the SysKonnect SK-9D41. 2565 */ 2566 if (bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_SIG) == BGE_MAGIC_NUMBER) { 2567 hwcfg = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_NICCFG); 2568 } else { 2569 bge_read_eeprom(sc, (void *)&hwcfg, 2570 BGE_EE_HWCFG_OFFSET, sizeof(hwcfg)); 2571 hwcfg = be32toh(hwcfg); 2572 } 2573 /* The SysKonnect SK-9D41 is a 1000baseSX card. */ 2574 if (PCI_PRODUCT(pa->pa_id) == SK_SUBSYSID_9D41 || 2575 (hwcfg & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER) { 2576 if (BGE_IS_5714_FAMILY(sc)) 2577 sc->bge_flags |= BGE_PHY_FIBER_MII; 2578 else 2579 sc->bge_flags |= BGE_PHY_FIBER_TBI; 2580 } 2581 2582 if (sc->bge_flags & BGE_PHY_FIBER_TBI) { 2583 ifmedia_init(&sc->bge_ifmedia, IFM_IMASK, bge_ifmedia_upd, 2584 bge_ifmedia_sts); 2585 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL); 2586 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_1000_SX|IFM_FDX, 2587 0, NULL); 2588 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL); 2589 ifmedia_set(&sc->bge_ifmedia, IFM_ETHER|IFM_AUTO); 2590 /* Pretend the user requested this setting */ 2591 sc->bge_ifmedia.ifm_media = sc->bge_ifmedia.ifm_cur->ifm_media; 2592 } else { 2593 /* 2594 * Do transceiver setup. 2595 */ 2596 ifmedia_init(&sc->bge_mii.mii_media, 0, bge_ifmedia_upd, 2597 bge_ifmedia_sts); 2598 mii_attach(sc->bge_dev, &sc->bge_mii, 0xffffffff, 2599 MII_PHY_ANY, MII_OFFSET_ANY, 2600 MIIF_FORCEANEG|MIIF_DOPAUSE); 2601 2602 if (LIST_EMPTY(&sc->bge_mii.mii_phys)) { 2603 aprint_error_dev(sc->bge_dev, "no PHY found!\n"); 2604 ifmedia_add(&sc->bge_mii.mii_media, 2605 IFM_ETHER|IFM_MANUAL, 0, NULL); 2606 ifmedia_set(&sc->bge_mii.mii_media, 2607 IFM_ETHER|IFM_MANUAL); 2608 } else 2609 ifmedia_set(&sc->bge_mii.mii_media, 2610 IFM_ETHER|IFM_AUTO); 2611 } 2612 2613 /* 2614 * When using the BCM5701 in PCI-X mode, data corruption has 2615 * been observed in the first few bytes of some received packets. 2616 * Aligning the packet buffer in memory eliminates the corruption. 2617 * Unfortunately, this misaligns the packet payloads. On platforms 2618 * which do not support unaligned accesses, we will realign the 2619 * payloads by copying the received packets. 2620 */ 2621 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5701 && 2622 sc->bge_flags & BGE_PCIX) 2623 sc->bge_flags |= BGE_RX_ALIGNBUG; 2624 2625 misccfg = CSR_READ_4(sc, BGE_MISC_CFG); 2626 misccfg &= BGE_MISCCFG_BOARD_ID_MASK; 2627 2628 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5705 && 2629 (misccfg == BGE_MISCCFG_BOARD_ID_5788 || 2630 misccfg == BGE_MISCCFG_BOARD_ID_5788M)) 2631 sc->bge_flags |= BGE_IS_5788; 2632 2633 /* 2634 * Call MI attach routine. 2635 */ 2636 DPRINTFN(5, ("if_attach\n")); 2637 if_attach(ifp); 2638 DPRINTFN(5, ("ether_ifattach\n")); 2639 ether_ifattach(ifp, eaddr); 2640 #if NRND > 0 2641 rnd_attach_source(&sc->rnd_source, device_xname(sc->bge_dev), 2642 RND_TYPE_NET, 0); 2643 #endif 2644 #ifdef BGE_EVENT_COUNTERS 2645 /* 2646 * Attach event counters. 2647 */ 2648 evcnt_attach_dynamic(&sc->bge_ev_intr, EVCNT_TYPE_INTR, 2649 NULL, device_xname(sc->bge_dev), "intr"); 2650 evcnt_attach_dynamic(&sc->bge_ev_tx_xoff, EVCNT_TYPE_MISC, 2651 NULL, device_xname(sc->bge_dev), "tx_xoff"); 2652 evcnt_attach_dynamic(&sc->bge_ev_tx_xon, EVCNT_TYPE_MISC, 2653 NULL, device_xname(sc->bge_dev), "tx_xon"); 2654 evcnt_attach_dynamic(&sc->bge_ev_rx_xoff, EVCNT_TYPE_MISC, 2655 NULL, device_xname(sc->bge_dev), "rx_xoff"); 2656 evcnt_attach_dynamic(&sc->bge_ev_rx_xon, EVCNT_TYPE_MISC, 2657 NULL, device_xname(sc->bge_dev), "rx_xon"); 2658 evcnt_attach_dynamic(&sc->bge_ev_rx_macctl, EVCNT_TYPE_MISC, 2659 NULL, device_xname(sc->bge_dev), "rx_macctl"); 2660 evcnt_attach_dynamic(&sc->bge_ev_xoffentered, EVCNT_TYPE_MISC, 2661 NULL, device_xname(sc->bge_dev), "xoffentered"); 2662 #endif /* BGE_EVENT_COUNTERS */ 2663 DPRINTFN(5, ("callout_init\n")); 2664 callout_init(&sc->bge_timeout, 0); 2665 2666 if (!pmf_device_register(self, NULL, NULL)) 2667 aprint_error_dev(self, "couldn't establish power handler\n"); 2668 else 2669 pmf_class_network_register(self, ifp); 2670 2671 dict = device_properties(self); 2672 prop_dictionary_set_uint32(dict, "phyflags", sc->bge_flags); 2673 } 2674 2675 static void 2676 bge_release_resources(struct bge_softc *sc) 2677 { 2678 if (sc->bge_vpd_prodname != NULL) 2679 free(sc->bge_vpd_prodname, M_DEVBUF); 2680 2681 if (sc->bge_vpd_readonly != NULL) 2682 free(sc->bge_vpd_readonly, M_DEVBUF); 2683 } 2684 2685 static void 2686 bge_reset(struct bge_softc *sc) 2687 { 2688 u_int32_t cachesize, command, pcistate, new_pcistate; 2689 int i, val; 2690 void (*write_op)(struct bge_softc *, int, int); 2691 2692 if (BGE_IS_5750_OR_BEYOND(sc) && !BGE_IS_5714_FAMILY(sc) && 2693 (BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5906)) { 2694 if (sc->bge_flags & BGE_PCIE) { 2695 write_op = bge_writemem_direct; 2696 } else { 2697 write_op = bge_writemem_ind; 2698 } 2699 } else { 2700 write_op = bge_writereg_ind; 2701 } 2702 2703 2704 /* Save some important PCI state. */ 2705 cachesize = pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CACHESZ); 2706 command = pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CMD); 2707 pcistate = pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_PCISTATE); 2708 2709 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MISC_CTL, 2710 BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR| 2711 BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_PCISTATE_RW); 2712 2713 /* Disable fastboot on controllers that support it. */ 2714 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5752 || 2715 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5755 || 2716 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5787) 2717 CSR_WRITE_4(sc, BGE_FASTBOOT_PC, 0); 2718 2719 val = BGE_MISCCFG_RESET_CORE_CLOCKS | (65<<1); 2720 /* 2721 * XXX: from FreeBSD/Linux; no documentation 2722 */ 2723 if (sc->bge_flags & BGE_PCIE) { 2724 if (CSR_READ_4(sc, BGE_PCIE_CTL1) == 0x60) 2725 /* PCI Express 1.0 system */ 2726 CSR_WRITE_4(sc, BGE_PCIE_CTL1, 0x20); 2727 if (sc->bge_chipid != BGE_CHIPID_BCM5750_A0) { 2728 /* 2729 * Prevent PCI Express link training 2730 * during global reset. 2731 */ 2732 CSR_WRITE_4(sc, BGE_MISC_CFG, 1 << 29); 2733 val |= (1<<29); 2734 } 2735 } 2736 2737 /* 2738 * Set GPHY Power Down Override to leave GPHY 2739 * powered up in D0 uninitialized. 2740 */ 2741 if (BGE_IS_5705_OR_BEYOND(sc)) 2742 val |= BGE_MISCCFG_KEEP_GPHY_POWER; 2743 2744 /* Issue global reset */ 2745 write_op(sc, BGE_MISC_CFG, val); 2746 2747 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 2748 i = CSR_READ_4(sc, BGE_VCPU_STATUS); 2749 CSR_WRITE_4(sc, BGE_VCPU_STATUS, 2750 i | BGE_VCPU_STATUS_DRV_RESET); 2751 i = CSR_READ_4(sc, BGE_VCPU_EXT_CTRL); 2752 CSR_WRITE_4(sc, BGE_VCPU_EXT_CTRL, 2753 i & ~BGE_VCPU_EXT_CTRL_HALT_CPU); 2754 } 2755 2756 DELAY(1000); 2757 2758 /* 2759 * XXX: from FreeBSD/Linux; no documentation 2760 */ 2761 if (sc->bge_flags & BGE_PCIE) { 2762 if (sc->bge_chipid == BGE_CHIPID_BCM5750_A0) { 2763 pcireg_t reg; 2764 2765 DELAY(500000); 2766 /* XXX: Magic Numbers */ 2767 reg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_UNKNOWN0); 2768 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_UNKNOWN0, 2769 reg | (1 << 15)); 2770 } 2771 /* 2772 * XXX: Magic Numbers. 2773 * Sets maximal PCI-e payload and clears any PCI-e errors. 2774 * Should be replaced with references to PCI config-space 2775 * capability block for PCI-Express. 2776 */ 2777 pci_conf_write(sc->sc_pc, sc->sc_pcitag, 2778 BGE_PCI_CONF_DEV_CTRL, 0xf5000); 2779 2780 } 2781 2782 /* Reset some of the PCI state that got zapped by reset */ 2783 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MISC_CTL, 2784 BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR| 2785 BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_PCISTATE_RW); 2786 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CMD, command); 2787 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CACHESZ, cachesize); 2788 write_op(sc, BGE_MISC_CFG, (65 << 1)); 2789 2790 /* Enable memory arbiter. */ 2791 { 2792 uint32_t marbmode = 0; 2793 if (BGE_IS_5714_FAMILY(sc)) { 2794 marbmode = CSR_READ_4(sc, BGE_MARB_MODE); 2795 } 2796 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE | marbmode); 2797 } 2798 2799 2800 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 2801 for (i = 0; i < BGE_TIMEOUT; i++) { 2802 val = CSR_READ_4(sc, BGE_VCPU_STATUS); 2803 if (val & BGE_VCPU_STATUS_INIT_DONE) 2804 break; 2805 DELAY(100); 2806 } 2807 if (i == BGE_TIMEOUT) { 2808 aprint_error_dev(sc->bge_dev, "reset timed out\n"); 2809 return; 2810 } 2811 } else { 2812 /* 2813 * Write the magic number to the firmware mailbox at 0xb50 2814 * so that the driver can synchronize with the firmware. 2815 */ 2816 bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM, BGE_MAGIC_NUMBER); 2817 2818 /* 2819 * Poll the value location we just wrote until 2820 * we see the 1's complement of the magic number. 2821 * This indicates that the firmware initialization 2822 * is complete. 2823 */ 2824 for (i = 0; i < BGE_TIMEOUT; i++) { 2825 val = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM); 2826 if (val == ~BGE_MAGIC_NUMBER) 2827 break; 2828 DELAY(1000); 2829 } 2830 2831 if (i >= BGE_TIMEOUT) { 2832 aprint_error_dev(sc->bge_dev, 2833 "firmware handshake timed out, val = %x\n", val); 2834 /* 2835 * XXX: occasionally fired on bcm5721, but without 2836 * apparent harm. For now, keep going if we timeout 2837 * against PCI-E devices. 2838 */ 2839 if ((sc->bge_flags & BGE_PCIE) == 0) 2840 return; 2841 } 2842 } 2843 2844 /* 2845 * XXX Wait for the value of the PCISTATE register to 2846 * return to its original pre-reset state. This is a 2847 * fairly good indicator of reset completion. If we don't 2848 * wait for the reset to fully complete, trying to read 2849 * from the device's non-PCI registers may yield garbage 2850 * results. 2851 */ 2852 for (i = 0; i < 10000; i++) { 2853 new_pcistate = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 2854 BGE_PCI_PCISTATE); 2855 if ((new_pcistate & ~BGE_PCISTATE_RESERVED) == 2856 (pcistate & ~BGE_PCISTATE_RESERVED)) 2857 break; 2858 DELAY(10); 2859 } 2860 if ((new_pcistate & ~BGE_PCISTATE_RESERVED) != 2861 (pcistate & ~BGE_PCISTATE_RESERVED)) { 2862 aprint_error_dev(sc->bge_dev, "pcistate failed to revert\n"); 2863 } 2864 2865 /* Enable memory arbiter. */ 2866 /* XXX why do this twice? */ 2867 { 2868 uint32_t marbmode = 0; 2869 if (BGE_IS_5714_FAMILY(sc)) { 2870 marbmode = CSR_READ_4(sc, BGE_MARB_MODE); 2871 } 2872 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE | marbmode); 2873 } 2874 2875 /* Fix up byte swapping */ 2876 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS); 2877 2878 CSR_WRITE_4(sc, BGE_MAC_MODE, 0); 2879 2880 /* 2881 * The 5704 in TBI mode apparently needs some special 2882 * adjustment to insure the SERDES drive level is set 2883 * to 1.2V. 2884 */ 2885 if (sc->bge_flags & BGE_PHY_FIBER_TBI && 2886 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) { 2887 u_int32_t serdescfg; 2888 2889 serdescfg = CSR_READ_4(sc, BGE_SERDES_CFG); 2890 serdescfg = (serdescfg & ~0xFFF) | 0x880; 2891 CSR_WRITE_4(sc, BGE_SERDES_CFG, serdescfg); 2892 } 2893 2894 /* XXX: from FreeBSD/Linux; no documentation */ 2895 if (sc->bge_flags & BGE_PCIE && 2896 sc->bge_chipid != BGE_CHIPID_BCM5750_A0) 2897 CSR_WRITE_4(sc, BGE_PCIE_CTL0, CSR_READ_4(sc, BGE_PCIE_CTL0) | (1<<25)); 2898 DELAY(10000); 2899 } 2900 2901 /* 2902 * Frame reception handling. This is called if there's a frame 2903 * on the receive return list. 2904 * 2905 * Note: we have to be able to handle two possibilities here: 2906 * 1) the frame is from the jumbo recieve ring 2907 * 2) the frame is from the standard receive ring 2908 */ 2909 2910 static void 2911 bge_rxeof(struct bge_softc *sc) 2912 { 2913 struct ifnet *ifp; 2914 int stdcnt = 0, jumbocnt = 0; 2915 bus_dmamap_t dmamap; 2916 bus_addr_t offset, toff; 2917 bus_size_t tlen; 2918 int tosync; 2919 2920 ifp = &sc->ethercom.ec_if; 2921 2922 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 2923 offsetof(struct bge_ring_data, bge_status_block), 2924 sizeof (struct bge_status_block), 2925 BUS_DMASYNC_POSTREAD); 2926 2927 offset = offsetof(struct bge_ring_data, bge_rx_return_ring); 2928 tosync = sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx - 2929 sc->bge_rx_saved_considx; 2930 2931 #if NRND > 0 2932 if (tosync != 0 && RND_ENABLED(&sc->rnd_source)) 2933 rnd_add_uint32(&sc->rnd_source, tosync); 2934 #endif 2935 2936 toff = offset + (sc->bge_rx_saved_considx * sizeof (struct bge_rx_bd)); 2937 2938 if (tosync < 0) { 2939 tlen = (sc->bge_return_ring_cnt - sc->bge_rx_saved_considx) * 2940 sizeof (struct bge_rx_bd); 2941 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 2942 toff, tlen, BUS_DMASYNC_POSTREAD); 2943 tosync = -tosync; 2944 } 2945 2946 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 2947 offset, tosync * sizeof (struct bge_rx_bd), 2948 BUS_DMASYNC_POSTREAD); 2949 2950 while(sc->bge_rx_saved_considx != 2951 sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx) { 2952 struct bge_rx_bd *cur_rx; 2953 u_int32_t rxidx; 2954 struct mbuf *m = NULL; 2955 2956 cur_rx = &sc->bge_rdata-> 2957 bge_rx_return_ring[sc->bge_rx_saved_considx]; 2958 2959 rxidx = cur_rx->bge_idx; 2960 BGE_INC(sc->bge_rx_saved_considx, sc->bge_return_ring_cnt); 2961 2962 if (cur_rx->bge_flags & BGE_RXBDFLAG_JUMBO_RING) { 2963 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT); 2964 m = sc->bge_cdata.bge_rx_jumbo_chain[rxidx]; 2965 sc->bge_cdata.bge_rx_jumbo_chain[rxidx] = NULL; 2966 jumbocnt++; 2967 bus_dmamap_sync(sc->bge_dmatag, 2968 sc->bge_cdata.bge_rx_jumbo_map, 2969 mtod(m, char *) - (char *)sc->bge_cdata.bge_jumbo_buf, 2970 BGE_JLEN, BUS_DMASYNC_POSTREAD); 2971 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 2972 ifp->if_ierrors++; 2973 bge_newbuf_jumbo(sc, sc->bge_jumbo, m); 2974 continue; 2975 } 2976 if (bge_newbuf_jumbo(sc, sc->bge_jumbo, 2977 NULL)== ENOBUFS) { 2978 ifp->if_ierrors++; 2979 bge_newbuf_jumbo(sc, sc->bge_jumbo, m); 2980 continue; 2981 } 2982 } else { 2983 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT); 2984 m = sc->bge_cdata.bge_rx_std_chain[rxidx]; 2985 2986 sc->bge_cdata.bge_rx_std_chain[rxidx] = NULL; 2987 stdcnt++; 2988 dmamap = sc->bge_cdata.bge_rx_std_map[rxidx]; 2989 sc->bge_cdata.bge_rx_std_map[rxidx] = 0; 2990 bus_dmamap_sync(sc->bge_dmatag, dmamap, 0, 2991 dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 2992 bus_dmamap_unload(sc->bge_dmatag, dmamap); 2993 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 2994 ifp->if_ierrors++; 2995 bge_newbuf_std(sc, sc->bge_std, m, dmamap); 2996 continue; 2997 } 2998 if (bge_newbuf_std(sc, sc->bge_std, 2999 NULL, dmamap) == ENOBUFS) { 3000 ifp->if_ierrors++; 3001 bge_newbuf_std(sc, sc->bge_std, m, dmamap); 3002 continue; 3003 } 3004 } 3005 3006 ifp->if_ipackets++; 3007 #ifndef __NO_STRICT_ALIGNMENT 3008 /* 3009 * XXX: if the 5701 PCIX-Rx-DMA workaround is in effect, 3010 * the Rx buffer has the layer-2 header unaligned. 3011 * If our CPU requires alignment, re-align by copying. 3012 */ 3013 if (sc->bge_flags & BGE_RX_ALIGNBUG) { 3014 memmove(mtod(m, char *) + ETHER_ALIGN, m->m_data, 3015 cur_rx->bge_len); 3016 m->m_data += ETHER_ALIGN; 3017 } 3018 #endif 3019 3020 m->m_pkthdr.len = m->m_len = cur_rx->bge_len - ETHER_CRC_LEN; 3021 m->m_pkthdr.rcvif = ifp; 3022 3023 #if NBPFILTER > 0 3024 /* 3025 * Handle BPF listeners. Let the BPF user see the packet. 3026 */ 3027 if (ifp->if_bpf) 3028 bpf_mtap(ifp->if_bpf, m); 3029 #endif 3030 3031 m->m_pkthdr.csum_flags = M_CSUM_IPv4; 3032 3033 if ((cur_rx->bge_ip_csum ^ 0xffff) != 0) 3034 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 3035 /* 3036 * Rx transport checksum-offload may also 3037 * have bugs with packets which, when transmitted, 3038 * were `runts' requiring padding. 3039 */ 3040 if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM && 3041 (/* (sc->_bge_quirks & BGE_QUIRK_SHORT_CKSUM_BUG) == 0 ||*/ 3042 m->m_pkthdr.len >= ETHER_MIN_NOPAD)) { 3043 m->m_pkthdr.csum_data = 3044 cur_rx->bge_tcp_udp_csum; 3045 m->m_pkthdr.csum_flags |= 3046 (M_CSUM_TCPv4|M_CSUM_UDPv4| 3047 M_CSUM_DATA|M_CSUM_NO_PSEUDOHDR); 3048 } 3049 3050 /* 3051 * If we received a packet with a vlan tag, pass it 3052 * to vlan_input() instead of ether_input(). 3053 */ 3054 if (cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) { 3055 VLAN_INPUT_TAG(ifp, m, cur_rx->bge_vlan_tag, continue); 3056 } 3057 3058 (*ifp->if_input)(ifp, m); 3059 } 3060 3061 bge_writembx(sc, BGE_MBX_RX_CONS0_LO, sc->bge_rx_saved_considx); 3062 if (stdcnt) 3063 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std); 3064 if (jumbocnt) 3065 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo); 3066 } 3067 3068 static void 3069 bge_txeof(struct bge_softc *sc) 3070 { 3071 struct bge_tx_bd *cur_tx = NULL; 3072 struct ifnet *ifp; 3073 struct txdmamap_pool_entry *dma; 3074 bus_addr_t offset, toff; 3075 bus_size_t tlen; 3076 int tosync; 3077 struct mbuf *m; 3078 3079 ifp = &sc->ethercom.ec_if; 3080 3081 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 3082 offsetof(struct bge_ring_data, bge_status_block), 3083 sizeof (struct bge_status_block), 3084 BUS_DMASYNC_POSTREAD); 3085 3086 offset = offsetof(struct bge_ring_data, bge_tx_ring); 3087 tosync = sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx - 3088 sc->bge_tx_saved_considx; 3089 3090 #if NRND > 0 3091 if (tosync != 0 && RND_ENABLED(&sc->rnd_source)) 3092 rnd_add_uint32(&sc->rnd_source, tosync); 3093 #endif 3094 3095 toff = offset + (sc->bge_tx_saved_considx * sizeof (struct bge_tx_bd)); 3096 3097 if (tosync < 0) { 3098 tlen = (BGE_TX_RING_CNT - sc->bge_tx_saved_considx) * 3099 sizeof (struct bge_tx_bd); 3100 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 3101 toff, tlen, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 3102 tosync = -tosync; 3103 } 3104 3105 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 3106 offset, tosync * sizeof (struct bge_tx_bd), 3107 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 3108 3109 /* 3110 * Go through our tx ring and free mbufs for those 3111 * frames that have been sent. 3112 */ 3113 while (sc->bge_tx_saved_considx != 3114 sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx) { 3115 u_int32_t idx = 0; 3116 3117 idx = sc->bge_tx_saved_considx; 3118 cur_tx = &sc->bge_rdata->bge_tx_ring[idx]; 3119 if (cur_tx->bge_flags & BGE_TXBDFLAG_END) 3120 ifp->if_opackets++; 3121 m = sc->bge_cdata.bge_tx_chain[idx]; 3122 if (m != NULL) { 3123 sc->bge_cdata.bge_tx_chain[idx] = NULL; 3124 dma = sc->txdma[idx]; 3125 bus_dmamap_sync(sc->bge_dmatag, dma->dmamap, 0, 3126 dma->dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 3127 bus_dmamap_unload(sc->bge_dmatag, dma->dmamap); 3128 SLIST_INSERT_HEAD(&sc->txdma_list, dma, link); 3129 sc->txdma[idx] = NULL; 3130 3131 m_freem(m); 3132 } 3133 sc->bge_txcnt--; 3134 BGE_INC(sc->bge_tx_saved_considx, BGE_TX_RING_CNT); 3135 ifp->if_timer = 0; 3136 } 3137 3138 if (cur_tx != NULL) 3139 ifp->if_flags &= ~IFF_OACTIVE; 3140 } 3141 3142 static int 3143 bge_intr(void *xsc) 3144 { 3145 struct bge_softc *sc; 3146 struct ifnet *ifp; 3147 uint32_t statusword; 3148 3149 sc = xsc; 3150 ifp = &sc->ethercom.ec_if; 3151 3152 /* It is possible for the interrupt to arrive before 3153 * the status block is updated prior to the interrupt. 3154 * Reading the PCI State register will confirm whether the 3155 * interrupt is ours and will flush the status block. 3156 */ 3157 3158 /* read status word from status block */ 3159 statusword = sc->bge_rdata->bge_status_block.bge_status; 3160 3161 if ((statusword & BGE_STATFLAG_UPDATED) || 3162 (!(CSR_READ_4(sc, BGE_PCI_PCISTATE) & BGE_PCISTATE_INTR_NOT_ACTIVE))) { 3163 /* Ack interrupt and stop others from occuring. */ 3164 bge_writembx(sc, BGE_MBX_IRQ0_LO, 1); 3165 3166 BGE_EVCNT_INCR(sc->bge_ev_intr); 3167 3168 /* clear status word */ 3169 sc->bge_rdata->bge_status_block.bge_status = 0; 3170 3171 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 3172 statusword & BGE_STATFLAG_LINKSTATE_CHANGED || 3173 BGE_STS_BIT(sc, BGE_STS_LINK_EVT)) 3174 bge_link_upd(sc); 3175 3176 if (ifp->if_flags & IFF_RUNNING) { 3177 /* Check RX return ring producer/consumer */ 3178 bge_rxeof(sc); 3179 3180 /* Check TX ring producer/consumer */ 3181 bge_txeof(sc); 3182 } 3183 3184 if (sc->bge_pending_rxintr_change) { 3185 uint32_t rx_ticks = sc->bge_rx_coal_ticks; 3186 uint32_t rx_bds = sc->bge_rx_max_coal_bds; 3187 uint32_t junk; 3188 3189 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, rx_ticks); 3190 DELAY(10); 3191 junk = CSR_READ_4(sc, BGE_HCC_RX_COAL_TICKS); 3192 3193 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, rx_bds); 3194 DELAY(10); 3195 junk = CSR_READ_4(sc, BGE_HCC_RX_MAX_COAL_BDS); 3196 3197 sc->bge_pending_rxintr_change = 0; 3198 } 3199 bge_handle_events(sc); 3200 3201 /* Re-enable interrupts. */ 3202 bge_writembx(sc, BGE_MBX_IRQ0_LO, 0); 3203 3204 if (ifp->if_flags & IFF_RUNNING && !IFQ_IS_EMPTY(&ifp->if_snd)) 3205 bge_start(ifp); 3206 3207 return (1); 3208 } else 3209 return (0); 3210 } 3211 3212 static void 3213 bge_tick(void *xsc) 3214 { 3215 struct bge_softc *sc = xsc; 3216 struct mii_data *mii = &sc->bge_mii; 3217 int s; 3218 3219 s = splnet(); 3220 3221 bge_stats_update(sc); 3222 3223 if (sc->bge_flags & BGE_PHY_FIBER_TBI) { 3224 /* 3225 * Since in TBI mode auto-polling can't be used we should poll 3226 * link status manually. Here we register pending link event 3227 * and trigger interrupt. 3228 */ 3229 BGE_STS_SETBIT(sc, BGE_STS_LINK_EVT); 3230 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET); 3231 } else { 3232 /* 3233 * Do not touch PHY if we have link up. This could break 3234 * IPMI/ASF mode or produce extra input errors. 3235 * (extra input errors was reported for bcm5701 & bcm5704). 3236 */ 3237 if (!BGE_STS_BIT(sc, BGE_STS_LINK)) 3238 mii_tick(mii); 3239 } 3240 3241 callout_reset(&sc->bge_timeout, hz, bge_tick, sc); 3242 3243 splx(s); 3244 } 3245 3246 static void 3247 bge_stats_update(struct bge_softc *sc) 3248 { 3249 struct ifnet *ifp = &sc->ethercom.ec_if; 3250 bus_size_t stats = BGE_MEMWIN_START + BGE_STATS_BLOCK; 3251 bus_size_t rstats = BGE_RX_STATS; 3252 3253 #define READ_RSTAT(sc, stats, stat) \ 3254 CSR_READ_4(sc, stats + offsetof(struct bge_mac_stats_regs, stat)) 3255 3256 if (BGE_IS_5705_OR_BEYOND(sc)) { 3257 ifp->if_collisions += 3258 READ_RSTAT(sc, rstats, dot3StatsSingleCollisionFrames) + 3259 READ_RSTAT(sc, rstats, dot3StatsMultipleCollisionFrames) + 3260 READ_RSTAT(sc, rstats, dot3StatsExcessiveCollisions) + 3261 READ_RSTAT(sc, rstats, dot3StatsLateCollisions); 3262 3263 BGE_EVCNT_ADD(sc->bge_ev_tx_xoff, 3264 READ_RSTAT(sc, rstats, outXoffSent)); 3265 BGE_EVCNT_ADD(sc->bge_ev_tx_xon, 3266 READ_RSTAT(sc, rstats, outXonSent)); 3267 BGE_EVCNT_ADD(sc->bge_ev_rx_xoff, 3268 READ_RSTAT(sc, rstats, xoffPauseFramesReceived)); 3269 BGE_EVCNT_ADD(sc->bge_ev_rx_xon, 3270 READ_RSTAT(sc, rstats, xonPauseFramesReceived)); 3271 BGE_EVCNT_ADD(sc->bge_ev_rx_macctl, 3272 READ_RSTAT(sc, rstats, macControlFramesReceived)); 3273 BGE_EVCNT_ADD(sc->bge_ev_xoffentered, 3274 READ_RSTAT(sc, rstats, xoffStateEntered)); 3275 return; 3276 } 3277 3278 #undef READ_RSTAT 3279 #define READ_STAT(sc, stats, stat) \ 3280 CSR_READ_4(sc, stats + offsetof(struct bge_stats, stat)) 3281 3282 ifp->if_collisions += 3283 (READ_STAT(sc, stats, dot3StatsSingleCollisionFrames.bge_addr_lo) + 3284 READ_STAT(sc, stats, dot3StatsMultipleCollisionFrames.bge_addr_lo) + 3285 READ_STAT(sc, stats, dot3StatsExcessiveCollisions.bge_addr_lo) + 3286 READ_STAT(sc, stats, dot3StatsLateCollisions.bge_addr_lo)) - 3287 ifp->if_collisions; 3288 3289 BGE_EVCNT_UPD(sc->bge_ev_tx_xoff, 3290 READ_STAT(sc, stats, outXoffSent.bge_addr_lo)); 3291 BGE_EVCNT_UPD(sc->bge_ev_tx_xon, 3292 READ_STAT(sc, stats, outXonSent.bge_addr_lo)); 3293 BGE_EVCNT_UPD(sc->bge_ev_rx_xoff, 3294 READ_STAT(sc, stats, 3295 xoffPauseFramesReceived.bge_addr_lo)); 3296 BGE_EVCNT_UPD(sc->bge_ev_rx_xon, 3297 READ_STAT(sc, stats, xonPauseFramesReceived.bge_addr_lo)); 3298 BGE_EVCNT_UPD(sc->bge_ev_rx_macctl, 3299 READ_STAT(sc, stats, 3300 macControlFramesReceived.bge_addr_lo)); 3301 BGE_EVCNT_UPD(sc->bge_ev_xoffentered, 3302 READ_STAT(sc, stats, xoffStateEntered.bge_addr_lo)); 3303 3304 #undef READ_STAT 3305 3306 #ifdef notdef 3307 ifp->if_collisions += 3308 (sc->bge_rdata->bge_info.bge_stats.dot3StatsSingleCollisionFrames + 3309 sc->bge_rdata->bge_info.bge_stats.dot3StatsMultipleCollisionFrames + 3310 sc->bge_rdata->bge_info.bge_stats.dot3StatsExcessiveCollisions + 3311 sc->bge_rdata->bge_info.bge_stats.dot3StatsLateCollisions) - 3312 ifp->if_collisions; 3313 #endif 3314 } 3315 3316 /* 3317 * Pad outbound frame to ETHER_MIN_NOPAD for an unusual reason. 3318 * The bge hardware will pad out Tx runts to ETHER_MIN_NOPAD, 3319 * but when such padded frames employ the bge IP/TCP checksum offload, 3320 * the hardware checksum assist gives incorrect results (possibly 3321 * from incorporating its own padding into the UDP/TCP checksum; who knows). 3322 * If we pad such runts with zeros, the onboard checksum comes out correct. 3323 */ 3324 static inline int 3325 bge_cksum_pad(struct mbuf *pkt) 3326 { 3327 struct mbuf *last = NULL; 3328 int padlen; 3329 3330 padlen = ETHER_MIN_NOPAD - pkt->m_pkthdr.len; 3331 3332 /* if there's only the packet-header and we can pad there, use it. */ 3333 if (pkt->m_pkthdr.len == pkt->m_len && 3334 M_TRAILINGSPACE(pkt) >= padlen) { 3335 last = pkt; 3336 } else { 3337 /* 3338 * Walk packet chain to find last mbuf. We will either 3339 * pad there, or append a new mbuf and pad it 3340 * (thus perhaps avoiding the bcm5700 dma-min bug). 3341 */ 3342 for (last = pkt; last->m_next != NULL; last = last->m_next) { 3343 continue; /* do nothing */ 3344 } 3345 3346 /* `last' now points to last in chain. */ 3347 if (M_TRAILINGSPACE(last) < padlen) { 3348 /* Allocate new empty mbuf, pad it. Compact later. */ 3349 struct mbuf *n; 3350 MGET(n, M_DONTWAIT, MT_DATA); 3351 if (n == NULL) 3352 return ENOBUFS; 3353 n->m_len = 0; 3354 last->m_next = n; 3355 last = n; 3356 } 3357 } 3358 3359 KDASSERT(!M_READONLY(last)); 3360 KDASSERT(M_TRAILINGSPACE(last) >= padlen); 3361 3362 /* Now zero the pad area, to avoid the bge cksum-assist bug */ 3363 memset(mtod(last, char *) + last->m_len, 0, padlen); 3364 last->m_len += padlen; 3365 pkt->m_pkthdr.len += padlen; 3366 return 0; 3367 } 3368 3369 /* 3370 * Compact outbound packets to avoid bug with DMA segments less than 8 bytes. 3371 */ 3372 static inline int 3373 bge_compact_dma_runt(struct mbuf *pkt) 3374 { 3375 struct mbuf *m, *prev; 3376 int totlen, prevlen; 3377 3378 prev = NULL; 3379 totlen = 0; 3380 prevlen = -1; 3381 3382 for (m = pkt; m != NULL; prev = m,m = m->m_next) { 3383 int mlen = m->m_len; 3384 int shortfall = 8 - mlen ; 3385 3386 totlen += mlen; 3387 if (mlen == 0) { 3388 continue; 3389 } 3390 if (mlen >= 8) 3391 continue; 3392 3393 /* If we get here, mbuf data is too small for DMA engine. 3394 * Try to fix by shuffling data to prev or next in chain. 3395 * If that fails, do a compacting deep-copy of the whole chain. 3396 */ 3397 3398 /* Internal frag. If fits in prev, copy it there. */ 3399 if (prev && M_TRAILINGSPACE(prev) >= m->m_len) { 3400 memcpy(prev->m_data + prev->m_len, m->m_data, mlen); 3401 prev->m_len += mlen; 3402 m->m_len = 0; 3403 /* XXX stitch chain */ 3404 prev->m_next = m_free(m); 3405 m = prev; 3406 continue; 3407 } 3408 else if (m->m_next != NULL && 3409 M_TRAILINGSPACE(m) >= shortfall && 3410 m->m_next->m_len >= (8 + shortfall)) { 3411 /* m is writable and have enough data in next, pull up. */ 3412 3413 memcpy(m->m_data + m->m_len, m->m_next->m_data, 3414 shortfall); 3415 m->m_len += shortfall; 3416 m->m_next->m_len -= shortfall; 3417 m->m_next->m_data += shortfall; 3418 } 3419 else if (m->m_next == NULL || 1) { 3420 /* Got a runt at the very end of the packet. 3421 * borrow data from the tail of the preceding mbuf and 3422 * update its length in-place. (The original data is still 3423 * valid, so we can do this even if prev is not writable.) 3424 */ 3425 3426 /* if we'd make prev a runt, just move all of its data. */ 3427 KASSERT(prev != NULL /*, ("runt but null PREV")*/); 3428 KASSERT(prev->m_len >= 8 /*, ("runt prev")*/); 3429 3430 if ((prev->m_len - shortfall) < 8) 3431 shortfall = prev->m_len; 3432 3433 #ifdef notyet /* just do the safe slow thing for now */ 3434 if (!M_READONLY(m)) { 3435 if (M_LEADINGSPACE(m) < shorfall) { 3436 void *m_dat; 3437 m_dat = (m->m_flags & M_PKTHDR) ? 3438 m->m_pktdat : m->dat; 3439 memmove(m_dat, mtod(m, void*), m->m_len); 3440 m->m_data = m_dat; 3441 } 3442 } else 3443 #endif /* just do the safe slow thing */ 3444 { 3445 struct mbuf * n = NULL; 3446 int newprevlen = prev->m_len - shortfall; 3447 3448 MGET(n, M_NOWAIT, MT_DATA); 3449 if (n == NULL) 3450 return ENOBUFS; 3451 KASSERT(m->m_len + shortfall < MLEN 3452 /*, 3453 ("runt %d +prev %d too big\n", m->m_len, shortfall)*/); 3454 3455 /* first copy the data we're stealing from prev */ 3456 memcpy(n->m_data, prev->m_data + newprevlen, 3457 shortfall); 3458 3459 /* update prev->m_len accordingly */ 3460 prev->m_len -= shortfall; 3461 3462 /* copy data from runt m */ 3463 memcpy(n->m_data + shortfall, m->m_data, 3464 m->m_len); 3465 3466 /* n holds what we stole from prev, plus m */ 3467 n->m_len = shortfall + m->m_len; 3468 3469 /* stitch n into chain and free m */ 3470 n->m_next = m->m_next; 3471 prev->m_next = n; 3472 /* KASSERT(m->m_next == NULL); */ 3473 m->m_next = NULL; 3474 m_free(m); 3475 m = n; /* for continuing loop */ 3476 } 3477 } 3478 prevlen = m->m_len; 3479 } 3480 return 0; 3481 } 3482 3483 /* 3484 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data 3485 * pointers to descriptors. 3486 */ 3487 static int 3488 bge_encap(struct bge_softc *sc, struct mbuf *m_head, u_int32_t *txidx) 3489 { 3490 struct bge_tx_bd *f = NULL; 3491 u_int32_t frag, cur; 3492 u_int16_t csum_flags = 0; 3493 u_int16_t txbd_tso_flags = 0; 3494 struct txdmamap_pool_entry *dma; 3495 bus_dmamap_t dmamap; 3496 int i = 0; 3497 struct m_tag *mtag; 3498 int use_tso, maxsegsize, error; 3499 3500 cur = frag = *txidx; 3501 3502 if (m_head->m_pkthdr.csum_flags) { 3503 if (m_head->m_pkthdr.csum_flags & M_CSUM_IPv4) 3504 csum_flags |= BGE_TXBDFLAG_IP_CSUM; 3505 if (m_head->m_pkthdr.csum_flags & (M_CSUM_TCPv4|M_CSUM_UDPv4)) 3506 csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM; 3507 } 3508 3509 /* 3510 * If we were asked to do an outboard checksum, and the NIC 3511 * has the bug where it sometimes adds in the Ethernet padding, 3512 * explicitly pad with zeros so the cksum will be correct either way. 3513 * (For now, do this for all chip versions, until newer 3514 * are confirmed to not require the workaround.) 3515 */ 3516 if ((csum_flags & BGE_TXBDFLAG_TCP_UDP_CSUM) == 0 || 3517 #ifdef notyet 3518 (sc->bge_quirks & BGE_QUIRK_SHORT_CKSUM_BUG) == 0 || 3519 #endif 3520 m_head->m_pkthdr.len >= ETHER_MIN_NOPAD) 3521 goto check_dma_bug; 3522 3523 if (bge_cksum_pad(m_head) != 0) { 3524 return ENOBUFS; 3525 } 3526 3527 check_dma_bug: 3528 if (!(BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX)) 3529 goto doit; 3530 3531 /* 3532 * bcm5700 Revision B silicon cannot handle DMA descriptors with 3533 * less than eight bytes. If we encounter a teeny mbuf 3534 * at the end of a chain, we can pad. Otherwise, copy. 3535 */ 3536 if (bge_compact_dma_runt(m_head) != 0) 3537 return ENOBUFS; 3538 3539 doit: 3540 dma = SLIST_FIRST(&sc->txdma_list); 3541 if (dma == NULL) 3542 return ENOBUFS; 3543 dmamap = dma->dmamap; 3544 3545 /* 3546 * Set up any necessary TSO state before we start packing... 3547 */ 3548 use_tso = (m_head->m_pkthdr.csum_flags & M_CSUM_TSOv4) != 0; 3549 if (!use_tso) { 3550 maxsegsize = 0; 3551 } else { /* TSO setup */ 3552 unsigned mss; 3553 struct ether_header *eh; 3554 unsigned ip_tcp_hlen, iptcp_opt_words, tcp_seg_flags, offset; 3555 struct mbuf * m0 = m_head; 3556 struct ip *ip; 3557 struct tcphdr *th; 3558 int iphl, hlen; 3559 3560 /* 3561 * XXX It would be nice if the mbuf pkthdr had offset 3562 * fields for the protocol headers. 3563 */ 3564 3565 eh = mtod(m0, struct ether_header *); 3566 switch (htons(eh->ether_type)) { 3567 case ETHERTYPE_IP: 3568 offset = ETHER_HDR_LEN; 3569 break; 3570 3571 case ETHERTYPE_VLAN: 3572 offset = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 3573 break; 3574 3575 default: 3576 /* 3577 * Don't support this protocol or encapsulation. 3578 */ 3579 return (ENOBUFS); 3580 } 3581 3582 /* 3583 * TCP/IP headers are in the first mbuf; we can do 3584 * this the easy way. 3585 */ 3586 iphl = M_CSUM_DATA_IPv4_IPHL(m0->m_pkthdr.csum_data); 3587 hlen = iphl + offset; 3588 if (__predict_false(m0->m_len < 3589 (hlen + sizeof(struct tcphdr)))) { 3590 3591 aprint_debug_dev(sc->bge_dev, 3592 "TSO: hard case m0->m_len == %d < ip/tcp hlen %zd," 3593 "not handled yet\n", 3594 m0->m_len, hlen+ sizeof(struct tcphdr)); 3595 #ifdef NOTYET 3596 /* 3597 * XXX jonathan (at) NetBSD.org: untested. 3598 * how to force this branch to be taken? 3599 */ 3600 BGE_EVCNT_INCR(&sc->sc_ev_txtsopain); 3601 3602 m_copydata(m0, offset, sizeof(ip), &ip); 3603 m_copydata(m0, hlen, sizeof(th), &th); 3604 3605 ip.ip_len = 0; 3606 3607 m_copyback(m0, hlen + offsetof(struct ip, ip_len), 3608 sizeof(ip.ip_len), &ip.ip_len); 3609 3610 th.th_sum = in_cksum_phdr(ip.ip_src.s_addr, 3611 ip.ip_dst.s_addr, htons(IPPROTO_TCP)); 3612 3613 m_copyback(m0, hlen + offsetof(struct tcphdr, th_sum), 3614 sizeof(th.th_sum), &th.th_sum); 3615 3616 hlen += th.th_off << 2; 3617 iptcp_opt_words = hlen; 3618 #else 3619 /* 3620 * if_wm "hard" case not yet supported, can we not 3621 * mandate it out of existence? 3622 */ 3623 (void) ip; (void)th; (void) ip_tcp_hlen; 3624 3625 return ENOBUFS; 3626 #endif 3627 } else { 3628 ip = (struct ip *) (mtod(m0, char *) + offset); 3629 th = (struct tcphdr *) (mtod(m0, char *) + hlen); 3630 ip_tcp_hlen = iphl + (th->th_off << 2); 3631 3632 /* Total IP/TCP options, in 32-bit words */ 3633 iptcp_opt_words = (ip_tcp_hlen 3634 - sizeof(struct tcphdr) 3635 - sizeof(struct ip)) >> 2; 3636 } 3637 if (BGE_IS_5750_OR_BEYOND(sc)) { 3638 th->th_sum = 0; 3639 csum_flags &= ~(BGE_TXBDFLAG_TCP_UDP_CSUM); 3640 } else { 3641 /* 3642 * XXX jonathan (at) NetBSD.org: 5705 untested. 3643 * Requires TSO firmware patch for 5701/5703/5704. 3644 */ 3645 th->th_sum = in_cksum_phdr(ip->ip_src.s_addr, 3646 ip->ip_dst.s_addr, htons(IPPROTO_TCP)); 3647 } 3648 3649 mss = m_head->m_pkthdr.segsz; 3650 txbd_tso_flags |= 3651 BGE_TXBDFLAG_CPU_PRE_DMA | 3652 BGE_TXBDFLAG_CPU_POST_DMA; 3653 3654 /* 3655 * Our NIC TSO-assist assumes TSO has standard, optionless 3656 * IPv4 and TCP headers, which total 40 bytes. By default, 3657 * the NIC copies 40 bytes of IP/TCP header from the 3658 * supplied header into the IP/TCP header portion of 3659 * each post-TSO-segment. If the supplied packet has IP or 3660 * TCP options, we need to tell the NIC to copy those extra 3661 * bytes into each post-TSO header, in addition to the normal 3662 * 40-byte IP/TCP header (and to leave space accordingly). 3663 * Unfortunately, the driver encoding of option length 3664 * varies across different ASIC families. 3665 */ 3666 tcp_seg_flags = 0; 3667 if (iptcp_opt_words) { 3668 if ( BGE_IS_5705_OR_BEYOND(sc)) { 3669 tcp_seg_flags = 3670 iptcp_opt_words << 11; 3671 } else { 3672 txbd_tso_flags |= 3673 iptcp_opt_words << 12; 3674 } 3675 } 3676 maxsegsize = mss | tcp_seg_flags; 3677 ip->ip_len = htons(mss + ip_tcp_hlen); 3678 3679 } /* TSO setup */ 3680 3681 /* 3682 * Start packing the mbufs in this chain into 3683 * the fragment pointers. Stop when we run out 3684 * of fragments or hit the end of the mbuf chain. 3685 */ 3686 error = bus_dmamap_load_mbuf(sc->bge_dmatag, dmamap, m_head, 3687 BUS_DMA_NOWAIT); 3688 if (error) { 3689 return (ENOBUFS); 3690 } 3691 /* 3692 * Sanity check: avoid coming within 16 descriptors 3693 * of the end of the ring. 3694 */ 3695 if (dmamap->dm_nsegs > (BGE_TX_RING_CNT - sc->bge_txcnt - 16)) { 3696 BGE_TSO_PRINTF(("%s: " 3697 " dmamap_load_mbuf too close to ring wrap\n", 3698 device_xname(sc->bge_dev))); 3699 goto fail_unload; 3700 } 3701 3702 mtag = sc->ethercom.ec_nvlans ? 3703 m_tag_find(m_head, PACKET_TAG_VLAN, NULL) : NULL; 3704 3705 3706 /* Iterate over dmap-map fragments. */ 3707 for (i = 0; i < dmamap->dm_nsegs; i++) { 3708 f = &sc->bge_rdata->bge_tx_ring[frag]; 3709 if (sc->bge_cdata.bge_tx_chain[frag] != NULL) 3710 break; 3711 3712 bge_set_hostaddr(&f->bge_addr, dmamap->dm_segs[i].ds_addr); 3713 f->bge_len = dmamap->dm_segs[i].ds_len; 3714 3715 /* 3716 * For 5751 and follow-ons, for TSO we must turn 3717 * off checksum-assist flag in the tx-descr, and 3718 * supply the ASIC-revision-specific encoding 3719 * of TSO flags and segsize. 3720 */ 3721 if (use_tso) { 3722 if (BGE_IS_5750_OR_BEYOND(sc) || i == 0) { 3723 f->bge_rsvd = maxsegsize; 3724 f->bge_flags = csum_flags | txbd_tso_flags; 3725 } else { 3726 f->bge_rsvd = 0; 3727 f->bge_flags = 3728 (csum_flags | txbd_tso_flags) & 0x0fff; 3729 } 3730 } else { 3731 f->bge_rsvd = 0; 3732 f->bge_flags = csum_flags; 3733 } 3734 3735 if (mtag != NULL) { 3736 f->bge_flags |= BGE_TXBDFLAG_VLAN_TAG; 3737 f->bge_vlan_tag = VLAN_TAG_VALUE(mtag); 3738 } else { 3739 f->bge_vlan_tag = 0; 3740 } 3741 cur = frag; 3742 BGE_INC(frag, BGE_TX_RING_CNT); 3743 } 3744 3745 if (i < dmamap->dm_nsegs) { 3746 BGE_TSO_PRINTF(("%s: reached %d < dm_nsegs %d\n", 3747 device_xname(sc->bge_dev), i, dmamap->dm_nsegs)); 3748 goto fail_unload; 3749 } 3750 3751 bus_dmamap_sync(sc->bge_dmatag, dmamap, 0, dmamap->dm_mapsize, 3752 BUS_DMASYNC_PREWRITE); 3753 3754 if (frag == sc->bge_tx_saved_considx) { 3755 BGE_TSO_PRINTF(("%s: frag %d = wrapped id %d?\n", 3756 device_xname(sc->bge_dev), frag, sc->bge_tx_saved_considx)); 3757 3758 goto fail_unload; 3759 } 3760 3761 sc->bge_rdata->bge_tx_ring[cur].bge_flags |= BGE_TXBDFLAG_END; 3762 sc->bge_cdata.bge_tx_chain[cur] = m_head; 3763 SLIST_REMOVE_HEAD(&sc->txdma_list, link); 3764 sc->txdma[cur] = dma; 3765 sc->bge_txcnt += dmamap->dm_nsegs; 3766 3767 *txidx = frag; 3768 3769 return (0); 3770 3771 fail_unload: 3772 bus_dmamap_unload(sc->bge_dmatag, dmamap); 3773 3774 return ENOBUFS; 3775 } 3776 3777 /* 3778 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 3779 * to the mbuf data regions directly in the transmit descriptors. 3780 */ 3781 static void 3782 bge_start(struct ifnet *ifp) 3783 { 3784 struct bge_softc *sc; 3785 struct mbuf *m_head = NULL; 3786 u_int32_t prodidx; 3787 int pkts = 0; 3788 3789 sc = ifp->if_softc; 3790 3791 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 3792 return; 3793 3794 prodidx = sc->bge_tx_prodidx; 3795 3796 while(sc->bge_cdata.bge_tx_chain[prodidx] == NULL) { 3797 IFQ_POLL(&ifp->if_snd, m_head); 3798 if (m_head == NULL) 3799 break; 3800 3801 #if 0 3802 /* 3803 * XXX 3804 * safety overkill. If this is a fragmented packet chain 3805 * with delayed TCP/UDP checksums, then only encapsulate 3806 * it if we have enough descriptors to handle the entire 3807 * chain at once. 3808 * (paranoia -- may not actually be needed) 3809 */ 3810 if (m_head->m_flags & M_FIRSTFRAG && 3811 m_head->m_pkthdr.csum_flags & (CSUM_DELAY_DATA)) { 3812 if ((BGE_TX_RING_CNT - sc->bge_txcnt) < 3813 M_CSUM_DATA_IPv4_OFFSET(m_head->m_pkthdr.csum_data) + 16) { 3814 ifp->if_flags |= IFF_OACTIVE; 3815 break; 3816 } 3817 } 3818 #endif 3819 3820 /* 3821 * Pack the data into the transmit ring. If we 3822 * don't have room, set the OACTIVE flag and wait 3823 * for the NIC to drain the ring. 3824 */ 3825 if (bge_encap(sc, m_head, &prodidx)) { 3826 ifp->if_flags |= IFF_OACTIVE; 3827 break; 3828 } 3829 3830 /* now we are committed to transmit the packet */ 3831 IFQ_DEQUEUE(&ifp->if_snd, m_head); 3832 pkts++; 3833 3834 #if NBPFILTER > 0 3835 /* 3836 * If there's a BPF listener, bounce a copy of this frame 3837 * to him. 3838 */ 3839 if (ifp->if_bpf) 3840 bpf_mtap(ifp->if_bpf, m_head); 3841 #endif 3842 } 3843 if (pkts == 0) 3844 return; 3845 3846 /* Transmit */ 3847 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); 3848 /* 5700 b2 errata */ 3849 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX) 3850 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); 3851 3852 sc->bge_tx_prodidx = prodidx; 3853 3854 /* 3855 * Set a timeout in case the chip goes out to lunch. 3856 */ 3857 ifp->if_timer = 5; 3858 } 3859 3860 static int 3861 bge_init(struct ifnet *ifp) 3862 { 3863 struct bge_softc *sc = ifp->if_softc; 3864 const u_int16_t *m; 3865 int s, error = 0; 3866 3867 s = splnet(); 3868 3869 ifp = &sc->ethercom.ec_if; 3870 3871 /* Cancel pending I/O and flush buffers. */ 3872 bge_stop(ifp, 0); 3873 bge_reset(sc); 3874 bge_chipinit(sc); 3875 3876 /* 3877 * Init the various state machines, ring 3878 * control blocks and firmware. 3879 */ 3880 error = bge_blockinit(sc); 3881 if (error != 0) { 3882 aprint_error_dev(sc->bge_dev, "initialization error %d\n", 3883 error); 3884 splx(s); 3885 return error; 3886 } 3887 3888 ifp = &sc->ethercom.ec_if; 3889 3890 /* Specify MTU. */ 3891 CSR_WRITE_4(sc, BGE_RX_MTU, ifp->if_mtu + 3892 ETHER_HDR_LEN + ETHER_CRC_LEN + ETHER_VLAN_ENCAP_LEN); 3893 3894 /* Load our MAC address. */ 3895 m = (const u_int16_t *)&(CLLADDR(ifp->if_sadl)[0]); 3896 CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0])); 3897 CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, (htons(m[1]) << 16) | htons(m[2])); 3898 3899 /* Enable or disable promiscuous mode as needed. */ 3900 if (ifp->if_flags & IFF_PROMISC) { 3901 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 3902 } else { 3903 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 3904 } 3905 3906 /* Program multicast filter. */ 3907 bge_setmulti(sc); 3908 3909 /* Init RX ring. */ 3910 bge_init_rx_ring_std(sc); 3911 3912 /* 3913 * Workaround for a bug in 5705 ASIC rev A0. Poll the NIC's 3914 * memory to insure that the chip has in fact read the first 3915 * entry of the ring. 3916 */ 3917 if (sc->bge_chipid == BGE_CHIPID_BCM5705_A0) { 3918 u_int32_t v, i; 3919 for (i = 0; i < 10; i++) { 3920 DELAY(20); 3921 v = bge_readmem_ind(sc, BGE_STD_RX_RINGS + 8); 3922 if (v == (MCLBYTES - ETHER_ALIGN)) 3923 break; 3924 } 3925 if (i == 10) 3926 aprint_error_dev(sc->bge_dev, 3927 "5705 A0 chip failed to load RX ring\n"); 3928 } 3929 3930 /* Init jumbo RX ring. */ 3931 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 3932 bge_init_rx_ring_jumbo(sc); 3933 3934 /* Init our RX return ring index */ 3935 sc->bge_rx_saved_considx = 0; 3936 3937 /* Init TX ring. */ 3938 bge_init_tx_ring(sc); 3939 3940 /* Turn on transmitter */ 3941 BGE_SETBIT(sc, BGE_TX_MODE, BGE_TXMODE_ENABLE); 3942 3943 /* Turn on receiver */ 3944 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE); 3945 3946 CSR_WRITE_4(sc, BGE_MAX_RX_FRAME_LOWAT, 2); 3947 3948 /* Tell firmware we're alive. */ 3949 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 3950 3951 /* Enable host interrupts. */ 3952 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA); 3953 BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); 3954 bge_writembx(sc, BGE_MBX_IRQ0_LO, 0); 3955 3956 if ((error = bge_ifmedia_upd(ifp)) != 0) 3957 goto out; 3958 3959 ifp->if_flags |= IFF_RUNNING; 3960 ifp->if_flags &= ~IFF_OACTIVE; 3961 3962 callout_reset(&sc->bge_timeout, hz, bge_tick, sc); 3963 3964 out: 3965 splx(s); 3966 3967 return error; 3968 } 3969 3970 /* 3971 * Set media options. 3972 */ 3973 static int 3974 bge_ifmedia_upd(struct ifnet *ifp) 3975 { 3976 struct bge_softc *sc = ifp->if_softc; 3977 struct mii_data *mii = &sc->bge_mii; 3978 struct ifmedia *ifm = &sc->bge_ifmedia; 3979 int rc; 3980 3981 /* If this is a 1000baseX NIC, enable the TBI port. */ 3982 if (sc->bge_flags & BGE_PHY_FIBER_TBI) { 3983 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 3984 return (EINVAL); 3985 switch(IFM_SUBTYPE(ifm->ifm_media)) { 3986 case IFM_AUTO: 3987 /* 3988 * The BCM5704 ASIC appears to have a special 3989 * mechanism for programming the autoneg 3990 * advertisement registers in TBI mode. 3991 */ 3992 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) { 3993 u_int32_t sgdig; 3994 sgdig = CSR_READ_4(sc, BGE_SGDIG_STS); 3995 if (sgdig & BGE_SGDIGSTS_DONE) { 3996 CSR_WRITE_4(sc, BGE_TX_TBI_AUTONEG, 0); 3997 sgdig = CSR_READ_4(sc, BGE_SGDIG_CFG); 3998 sgdig |= BGE_SGDIGCFG_AUTO | 3999 BGE_SGDIGCFG_PAUSE_CAP | 4000 BGE_SGDIGCFG_ASYM_PAUSE; 4001 CSR_WRITE_4(sc, BGE_SGDIG_CFG, 4002 sgdig | BGE_SGDIGCFG_SEND); 4003 DELAY(5); 4004 CSR_WRITE_4(sc, BGE_SGDIG_CFG, sgdig); 4005 } 4006 } 4007 break; 4008 case IFM_1000_SX: 4009 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 4010 BGE_CLRBIT(sc, BGE_MAC_MODE, 4011 BGE_MACMODE_HALF_DUPLEX); 4012 } else { 4013 BGE_SETBIT(sc, BGE_MAC_MODE, 4014 BGE_MACMODE_HALF_DUPLEX); 4015 } 4016 break; 4017 default: 4018 return (EINVAL); 4019 } 4020 /* XXX 802.3x flow control for 1000BASE-SX */ 4021 return (0); 4022 } 4023 4024 BGE_STS_SETBIT(sc, BGE_STS_LINK_EVT); 4025 if ((rc = mii_mediachg(mii)) == ENXIO) 4026 return 0; 4027 4028 /* 4029 * Force an interrupt so that we will call bge_link_upd 4030 * if needed and clear any pending link state attention. 4031 * Without this we are not getting any further interrupts 4032 * for link state changes and thus will not UP the link and 4033 * not be able to send in bge_start. The only way to get 4034 * things working was to receive a packet and get a RX intr. 4035 */ 4036 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 4037 sc->bge_flags & BGE_IS_5788) 4038 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET); 4039 else 4040 BGE_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW); 4041 4042 return rc; 4043 } 4044 4045 /* 4046 * Report current media status. 4047 */ 4048 static void 4049 bge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 4050 { 4051 struct bge_softc *sc = ifp->if_softc; 4052 struct mii_data *mii = &sc->bge_mii; 4053 4054 if (sc->bge_flags & BGE_PHY_FIBER_TBI) { 4055 ifmr->ifm_status = IFM_AVALID; 4056 ifmr->ifm_active = IFM_ETHER; 4057 if (CSR_READ_4(sc, BGE_MAC_STS) & 4058 BGE_MACSTAT_TBI_PCS_SYNCHED) 4059 ifmr->ifm_status |= IFM_ACTIVE; 4060 ifmr->ifm_active |= IFM_1000_SX; 4061 if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX) 4062 ifmr->ifm_active |= IFM_HDX; 4063 else 4064 ifmr->ifm_active |= IFM_FDX; 4065 return; 4066 } 4067 4068 mii_pollstat(mii); 4069 ifmr->ifm_status = mii->mii_media_status; 4070 ifmr->ifm_active = (mii->mii_media_active & ~IFM_ETH_FMASK) | 4071 sc->bge_flowflags; 4072 } 4073 4074 static int 4075 bge_ioctl(struct ifnet *ifp, u_long command, void *data) 4076 { 4077 struct bge_softc *sc = ifp->if_softc; 4078 struct ifreq *ifr = (struct ifreq *) data; 4079 int s, error = 0; 4080 struct mii_data *mii; 4081 4082 s = splnet(); 4083 4084 switch(command) { 4085 case SIOCSIFFLAGS: 4086 if ((error = ifioctl_common(ifp, command, data)) != 0) 4087 break; 4088 if (ifp->if_flags & IFF_UP) { 4089 /* 4090 * If only the state of the PROMISC flag changed, 4091 * then just use the 'set promisc mode' command 4092 * instead of reinitializing the entire NIC. Doing 4093 * a full re-init means reloading the firmware and 4094 * waiting for it to start up, which may take a 4095 * second or two. 4096 */ 4097 if (ifp->if_flags & IFF_RUNNING && 4098 ifp->if_flags & IFF_PROMISC && 4099 !(sc->bge_if_flags & IFF_PROMISC)) { 4100 BGE_SETBIT(sc, BGE_RX_MODE, 4101 BGE_RXMODE_RX_PROMISC); 4102 } else if (ifp->if_flags & IFF_RUNNING && 4103 !(ifp->if_flags & IFF_PROMISC) && 4104 sc->bge_if_flags & IFF_PROMISC) { 4105 BGE_CLRBIT(sc, BGE_RX_MODE, 4106 BGE_RXMODE_RX_PROMISC); 4107 } else if (!(sc->bge_if_flags & IFF_UP)) 4108 bge_init(ifp); 4109 } else { 4110 if (ifp->if_flags & IFF_RUNNING) 4111 bge_stop(ifp, 1); 4112 } 4113 sc->bge_if_flags = ifp->if_flags; 4114 error = 0; 4115 break; 4116 case SIOCSIFMEDIA: 4117 /* XXX Flow control is not supported for 1000BASE-SX */ 4118 if (sc->bge_flags & BGE_PHY_FIBER_TBI) { 4119 ifr->ifr_media &= ~IFM_ETH_FMASK; 4120 sc->bge_flowflags = 0; 4121 } 4122 4123 /* Flow control requires full-duplex mode. */ 4124 if (IFM_SUBTYPE(ifr->ifr_media) == IFM_AUTO || 4125 (ifr->ifr_media & IFM_FDX) == 0) { 4126 ifr->ifr_media &= ~IFM_ETH_FMASK; 4127 } 4128 if (IFM_SUBTYPE(ifr->ifr_media) != IFM_AUTO) { 4129 if ((ifr->ifr_media & IFM_ETH_FMASK) == IFM_FLOW) { 4130 /* We can do both TXPAUSE and RXPAUSE. */ 4131 ifr->ifr_media |= 4132 IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE; 4133 } 4134 sc->bge_flowflags = ifr->ifr_media & IFM_ETH_FMASK; 4135 } 4136 /* FALLTHROUGH */ 4137 case SIOCGIFMEDIA: 4138 if (sc->bge_flags & BGE_PHY_FIBER_TBI) { 4139 error = ifmedia_ioctl(ifp, ifr, &sc->bge_ifmedia, 4140 command); 4141 } else { 4142 mii = &sc->bge_mii; 4143 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, 4144 command); 4145 } 4146 break; 4147 default: 4148 if ((error = ether_ioctl(ifp, command, data)) != ENETRESET) 4149 break; 4150 4151 error = 0; 4152 4153 if (command != SIOCADDMULTI && command != SIOCDELMULTI) 4154 ; 4155 else if (ifp->if_flags & IFF_RUNNING) 4156 bge_setmulti(sc); 4157 break; 4158 } 4159 4160 splx(s); 4161 4162 return (error); 4163 } 4164 4165 static void 4166 bge_watchdog(struct ifnet *ifp) 4167 { 4168 struct bge_softc *sc; 4169 4170 sc = ifp->if_softc; 4171 4172 aprint_error_dev(sc->bge_dev, "watchdog timeout -- resetting\n"); 4173 4174 ifp->if_flags &= ~IFF_RUNNING; 4175 bge_init(ifp); 4176 4177 ifp->if_oerrors++; 4178 } 4179 4180 static void 4181 bge_stop_block(struct bge_softc *sc, bus_addr_t reg, uint32_t bit) 4182 { 4183 int i; 4184 4185 BGE_CLRBIT(sc, reg, bit); 4186 4187 for (i = 0; i < BGE_TIMEOUT; i++) { 4188 if ((CSR_READ_4(sc, reg) & bit) == 0) 4189 return; 4190 delay(100); 4191 if (sc->bge_flags & BGE_PCIE) 4192 DELAY(1000); 4193 } 4194 4195 aprint_error_dev(sc->bge_dev, 4196 "block failed to stop: reg 0x%lx, bit 0x%08x\n", (u_long)reg, bit); 4197 } 4198 4199 /* 4200 * Stop the adapter and free any mbufs allocated to the 4201 * RX and TX lists. 4202 */ 4203 static void 4204 bge_stop(struct ifnet *ifp, int disable) 4205 { 4206 struct bge_softc *sc = ifp->if_softc; 4207 4208 callout_stop(&sc->bge_timeout); 4209 4210 /* 4211 * Disable all of the receiver blocks 4212 */ 4213 bge_stop_block(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE); 4214 bge_stop_block(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 4215 bge_stop_block(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 4216 if (!(BGE_IS_5705_OR_BEYOND(sc))) 4217 bge_stop_block(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 4218 bge_stop_block(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE); 4219 bge_stop_block(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 4220 bge_stop_block(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE); 4221 4222 /* 4223 * Disable all of the transmit blocks 4224 */ 4225 bge_stop_block(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 4226 bge_stop_block(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 4227 bge_stop_block(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 4228 bge_stop_block(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE); 4229 bge_stop_block(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE); 4230 if (!(BGE_IS_5705_OR_BEYOND(sc))) 4231 bge_stop_block(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 4232 bge_stop_block(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 4233 4234 /* 4235 * Shut down all of the memory managers and related 4236 * state machines. 4237 */ 4238 bge_stop_block(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE); 4239 bge_stop_block(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE); 4240 if (!(BGE_IS_5705_OR_BEYOND(sc))) 4241 bge_stop_block(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 4242 4243 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 4244 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 4245 4246 if (!(BGE_IS_5705_OR_BEYOND(sc))) { 4247 bge_stop_block(sc, BGE_BMAN_MODE, BGE_BMANMODE_ENABLE); 4248 bge_stop_block(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 4249 } 4250 4251 /* Disable host interrupts. */ 4252 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); 4253 bge_writembx(sc, BGE_MBX_IRQ0_LO, 1); 4254 4255 /* 4256 * Tell firmware we're shutting down. 4257 */ 4258 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 4259 4260 /* Free the RX lists. */ 4261 bge_free_rx_ring_std(sc); 4262 4263 /* Free jumbo RX list. */ 4264 bge_free_rx_ring_jumbo(sc); 4265 4266 /* Free TX buffers. */ 4267 bge_free_tx_ring(sc); 4268 4269 /* 4270 * Isolate/power down the PHY. 4271 */ 4272 if (!(sc->bge_flags & BGE_PHY_FIBER_TBI)) 4273 mii_down(&sc->bge_mii); 4274 4275 sc->bge_tx_saved_considx = BGE_TXCONS_UNSET; 4276 4277 /* Clear MAC's link state (PHY may still have link UP). */ 4278 BGE_STS_CLRBIT(sc, BGE_STS_LINK); 4279 4280 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 4281 } 4282 4283 static void 4284 bge_link_upd(struct bge_softc *sc) 4285 { 4286 struct ifnet *ifp = &sc->ethercom.ec_if; 4287 struct mii_data *mii = &sc->bge_mii; 4288 u_int32_t status; 4289 int link; 4290 4291 /* Clear 'pending link event' flag */ 4292 BGE_STS_CLRBIT(sc, BGE_STS_LINK_EVT); 4293 4294 /* 4295 * Process link state changes. 4296 * Grrr. The link status word in the status block does 4297 * not work correctly on the BCM5700 rev AX and BX chips, 4298 * according to all available information. Hence, we have 4299 * to enable MII interrupts in order to properly obtain 4300 * async link changes. Unfortunately, this also means that 4301 * we have to read the MAC status register to detect link 4302 * changes, thereby adding an additional register access to 4303 * the interrupt handler. 4304 */ 4305 4306 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700) { 4307 status = CSR_READ_4(sc, BGE_MAC_STS); 4308 if (status & BGE_MACSTAT_MI_INTERRUPT) { 4309 mii_pollstat(mii); 4310 4311 if (!BGE_STS_BIT(sc, BGE_STS_LINK) && 4312 mii->mii_media_status & IFM_ACTIVE && 4313 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) 4314 BGE_STS_SETBIT(sc, BGE_STS_LINK); 4315 else if (BGE_STS_BIT(sc, BGE_STS_LINK) && 4316 (!(mii->mii_media_status & IFM_ACTIVE) || 4317 IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) 4318 BGE_STS_CLRBIT(sc, BGE_STS_LINK); 4319 4320 /* Clear the interrupt */ 4321 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, 4322 BGE_EVTENB_MI_INTERRUPT); 4323 bge_miibus_readreg(sc->bge_dev, 1, BRGPHY_MII_ISR); 4324 bge_miibus_writereg(sc->bge_dev, 1, BRGPHY_MII_IMR, 4325 BRGPHY_INTRS); 4326 } 4327 return; 4328 } 4329 4330 if (sc->bge_flags & BGE_PHY_FIBER_TBI) { 4331 status = CSR_READ_4(sc, BGE_MAC_STS); 4332 if (status & BGE_MACSTAT_TBI_PCS_SYNCHED) { 4333 if (!BGE_STS_BIT(sc, BGE_STS_LINK)) { 4334 BGE_STS_SETBIT(sc, BGE_STS_LINK); 4335 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) 4336 BGE_CLRBIT(sc, BGE_MAC_MODE, 4337 BGE_MACMODE_TBI_SEND_CFGS); 4338 CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF); 4339 if_link_state_change(ifp, LINK_STATE_UP); 4340 } 4341 } else if (BGE_STS_BIT(sc, BGE_STS_LINK)) { 4342 BGE_STS_CLRBIT(sc, BGE_STS_LINK); 4343 if_link_state_change(ifp, LINK_STATE_DOWN); 4344 } 4345 /* 4346 * Discard link events for MII/GMII cards if MI auto-polling disabled. 4347 * This should not happen since mii callouts are locked now, but 4348 * we keep this check for debug. 4349 */ 4350 } else if (BGE_STS_BIT(sc, BGE_STS_AUTOPOLL)) { 4351 /* 4352 * Some broken BCM chips have BGE_STATFLAG_LINKSTATE_CHANGED 4353 * bit in status word always set. Workaround this bug by 4354 * reading PHY link status directly. 4355 */ 4356 link = (CSR_READ_4(sc, BGE_MI_STS) & BGE_MISTS_LINK)? 4357 BGE_STS_LINK : 0; 4358 4359 if (BGE_STS_BIT(sc, BGE_STS_LINK) != link) { 4360 mii_pollstat(mii); 4361 4362 if (!BGE_STS_BIT(sc, BGE_STS_LINK) && 4363 mii->mii_media_status & IFM_ACTIVE && 4364 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) 4365 BGE_STS_SETBIT(sc, BGE_STS_LINK); 4366 else if (BGE_STS_BIT(sc, BGE_STS_LINK) && 4367 (!(mii->mii_media_status & IFM_ACTIVE) || 4368 IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) 4369 BGE_STS_CLRBIT(sc, BGE_STS_LINK); 4370 } 4371 } 4372 4373 /* Clear the attention */ 4374 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED| 4375 BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE| 4376 BGE_MACSTAT_LINK_CHANGED); 4377 } 4378 4379 static int 4380 sysctl_bge_verify(SYSCTLFN_ARGS) 4381 { 4382 int error, t; 4383 struct sysctlnode node; 4384 4385 node = *rnode; 4386 t = *(int*)rnode->sysctl_data; 4387 node.sysctl_data = &t; 4388 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 4389 if (error || newp == NULL) 4390 return (error); 4391 4392 #if 0 4393 DPRINTF2(("%s: t = %d, nodenum = %d, rnodenum = %d\n", __func__, t, 4394 node.sysctl_num, rnode->sysctl_num)); 4395 #endif 4396 4397 if (node.sysctl_num == bge_rxthresh_nodenum) { 4398 if (t < 0 || t >= NBGE_RX_THRESH) 4399 return (EINVAL); 4400 bge_update_all_threshes(t); 4401 } else 4402 return (EINVAL); 4403 4404 *(int*)rnode->sysctl_data = t; 4405 4406 return (0); 4407 } 4408 4409 /* 4410 * Set up sysctl(3) MIB, hw.bge.*. 4411 * 4412 * TBD condition SYSCTL_PERMANENT on being an LKM or not 4413 */ 4414 SYSCTL_SETUP(sysctl_bge, "sysctl bge subtree setup") 4415 { 4416 int rc, bge_root_num; 4417 const struct sysctlnode *node; 4418 4419 if ((rc = sysctl_createv(clog, 0, NULL, NULL, 4420 CTLFLAG_PERMANENT, CTLTYPE_NODE, "hw", NULL, 4421 NULL, 0, NULL, 0, CTL_HW, CTL_EOL)) != 0) { 4422 goto err; 4423 } 4424 4425 if ((rc = sysctl_createv(clog, 0, NULL, &node, 4426 CTLFLAG_PERMANENT, CTLTYPE_NODE, "bge", 4427 SYSCTL_DESCR("BGE interface controls"), 4428 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL)) != 0) { 4429 goto err; 4430 } 4431 4432 bge_root_num = node->sysctl_num; 4433 4434 /* BGE Rx interrupt mitigation level */ 4435 if ((rc = sysctl_createv(clog, 0, NULL, &node, 4436 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, 4437 CTLTYPE_INT, "rx_lvl", 4438 SYSCTL_DESCR("BGE receive interrupt mitigation level"), 4439 sysctl_bge_verify, 0, 4440 &bge_rx_thresh_lvl, 4441 0, CTL_HW, bge_root_num, CTL_CREATE, 4442 CTL_EOL)) != 0) { 4443 goto err; 4444 } 4445 4446 bge_rxthresh_nodenum = node->sysctl_num; 4447 4448 return; 4449 4450 err: 4451 aprint_error("%s: sysctl_createv failed (rc = %d)\n", __func__, rc); 4452 } 4453 4454 static int 4455 bge_get_eaddr_mem(struct bge_softc *sc, u_int8_t ether_addr[]) 4456 { 4457 u_int32_t mac_addr; 4458 4459 mac_addr = bge_readmem_ind(sc, 0x0c14); 4460 if ((mac_addr >> 16) == 0x484b) { 4461 ether_addr[0] = (uint8_t)(mac_addr >> 8); 4462 ether_addr[1] = (uint8_t)mac_addr; 4463 mac_addr = bge_readmem_ind(sc, 0x0c18); 4464 ether_addr[2] = (uint8_t)(mac_addr >> 24); 4465 ether_addr[3] = (uint8_t)(mac_addr >> 16); 4466 ether_addr[4] = (uint8_t)(mac_addr >> 8); 4467 ether_addr[5] = (uint8_t)mac_addr; 4468 return (0); 4469 } 4470 return (1); 4471 } 4472 4473 static int 4474 bge_get_eaddr_nvram(struct bge_softc *sc, u_int8_t ether_addr[]) 4475 { 4476 int mac_offset = BGE_EE_MAC_OFFSET; 4477 4478 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 4479 mac_offset = BGE_EE_MAC_OFFSET_5906; 4480 } 4481 4482 return (bge_read_nvram(sc, ether_addr, mac_offset + 2, 4483 ETHER_ADDR_LEN)); 4484 } 4485 4486 static int 4487 bge_get_eaddr_eeprom(struct bge_softc *sc, u_int8_t ether_addr[]) 4488 { 4489 4490 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 4491 return (1); 4492 } 4493 4494 return (bge_read_eeprom(sc, ether_addr, BGE_EE_MAC_OFFSET + 2, 4495 ETHER_ADDR_LEN)); 4496 } 4497 4498 static int 4499 bge_get_eaddr(struct bge_softc *sc, u_int8_t eaddr[]) 4500 { 4501 static const bge_eaddr_fcn_t bge_eaddr_funcs[] = { 4502 /* NOTE: Order is critical */ 4503 bge_get_eaddr_mem, 4504 bge_get_eaddr_nvram, 4505 bge_get_eaddr_eeprom, 4506 NULL 4507 }; 4508 const bge_eaddr_fcn_t *func; 4509 4510 for (func = bge_eaddr_funcs; *func != NULL; ++func) { 4511 if ((*func)(sc, eaddr) == 0) 4512 break; 4513 } 4514 return (*func == NULL ? ENXIO : 0); 4515 } 4516
Indexes created Thu Sep 25 02:09:54 GMT 2025