if_bge.c revision 1.169
1 /* $NetBSD: if_bge.c,v 1.169 2010/01/19 22:07:00 pooka Exp $ */ 2 3 /* 4 * Copyright (c) 2001 Wind River Systems 5 * Copyright (c) 1997, 1998, 1999, 2001 6 * Bill Paul <wpaul (at) windriver.com>. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Bill Paul. 19 * 4. Neither the name of the author nor the names of any co-contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 33 * THE POSSIBILITY OF SUCH DAMAGE. 34 * 35 * $FreeBSD: if_bge.c,v 1.13 2002/04/04 06:01:31 wpaul Exp $ 36 */ 37 38 /* 39 * Broadcom BCM570x family gigabit ethernet driver for NetBSD. 40 * 41 * NetBSD version by: 42 * 43 * Frank van der Linden <fvdl (at) wasabisystems.com> 44 * Jason Thorpe <thorpej (at) wasabisystems.com> 45 * Jonathan Stone <jonathan (at) dsg.stanford.edu> 46 * 47 * Originally written for FreeBSD by Bill Paul <wpaul (at) windriver.com> 48 * Senior Engineer, Wind River Systems 49 */ 50 51 /* 52 * The Broadcom BCM5700 is based on technology originally developed by 53 * Alteon Networks as part of the Tigon I and Tigon II gigabit ethernet 54 * MAC chips. The BCM5700, sometimes refered to as the Tigon III, has 55 * two on-board MIPS R4000 CPUs and can have as much as 16MB of external 56 * SSRAM. The BCM5700 supports TCP, UDP and IP checksum offload, jumbo 57 * frames, highly configurable RX filtering, and 16 RX and TX queues 58 * (which, along with RX filter rules, can be used for QOS applications). 59 * Other features, such as TCP segmentation, may be available as part 60 * of value-added firmware updates. Unlike the Tigon I and Tigon II, 61 * firmware images can be stored in hardware and need not be compiled 62 * into the driver. 63 * 64 * The BCM5700 supports the PCI v2.2 and PCI-X v1.0 standards, and will 65 * function in a 32-bit/64-bit 33/66MHz bus, or a 64-bit/133MHz bus. 66 * 67 * The BCM5701 is a single-chip solution incorporating both the BCM5700 68 * MAC and a BCM5401 10/100/1000 PHY. Unlike the BCM5700, the BCM5701 69 * does not support external SSRAM. 70 * 71 * Broadcom also produces a variation of the BCM5700 under the "Altima" 72 * brand name, which is functionally similar but lacks PCI-X support. 73 * 74 * Without external SSRAM, you can only have at most 4 TX rings, 75 * and the use of the mini RX ring is disabled. This seems to imply 76 * that these features are simply not available on the BCM5701. As a 77 * result, this driver does not implement any support for the mini RX 78 * ring. 79 */ 80 81 #include <sys/cdefs.h> 82 __KERNEL_RCSID(0, "$NetBSD: if_bge.c,v 1.169 2010/01/19 22:07:00 pooka Exp $"); 83 84 #include "vlan.h" 85 #include "rnd.h" 86 87 #include <sys/param.h> 88 #include <sys/systm.h> 89 #include <sys/callout.h> 90 #include <sys/sockio.h> 91 #include <sys/mbuf.h> 92 #include <sys/malloc.h> 93 #include <sys/kernel.h> 94 #include <sys/device.h> 95 #include <sys/socket.h> 96 #include <sys/sysctl.h> 97 98 #include <net/if.h> 99 #include <net/if_dl.h> 100 #include <net/if_media.h> 101 #include <net/if_ether.h> 102 103 #if NRND > 0 104 #include <sys/rnd.h> 105 #endif 106 107 #ifdef INET 108 #include <netinet/in.h> 109 #include <netinet/in_systm.h> 110 #include <netinet/in_var.h> 111 #include <netinet/ip.h> 112 #endif 113 114 /* Headers for TCP Segmentation Offload (TSO) */ 115 #include <netinet/in_systm.h> /* n_time for <netinet/ip.h>... */ 116 #include <netinet/in.h> /* ip_{src,dst}, for <netinet/ip.h> */ 117 #include <netinet/ip.h> /* for struct ip */ 118 #include <netinet/tcp.h> /* for struct tcphdr */ 119 120 121 #include <net/bpf.h> 122 123 #include <dev/pci/pcireg.h> 124 #include <dev/pci/pcivar.h> 125 #include <dev/pci/pcidevs.h> 126 127 #include <dev/mii/mii.h> 128 #include <dev/mii/miivar.h> 129 #include <dev/mii/miidevs.h> 130 #include <dev/mii/brgphyreg.h> 131 132 #include <dev/pci/if_bgereg.h> 133 #include <dev/pci/if_bgevar.h> 134 135 #include <uvm/uvm_extern.h> 136 #include <prop/proplib.h> 137 138 #define ETHER_MIN_NOPAD (ETHER_MIN_LEN - ETHER_CRC_LEN) /* i.e., 60 */ 139 140 141 /* 142 * Tunable thresholds for rx-side bge interrupt mitigation. 143 */ 144 145 /* 146 * The pairs of values below were obtained from empirical measurement 147 * on bcm5700 rev B2; they ar designed to give roughly 1 receive 148 * interrupt for every N packets received, where N is, approximately, 149 * the second value (rx_max_bds) in each pair. The values are chosen 150 * such that moving from one pair to the succeeding pair was observed 151 * to roughly halve interrupt rate under sustained input packet load. 152 * The values were empirically chosen to avoid overflowing internal 153 * limits on the bcm5700: inreasing rx_ticks much beyond 600 154 * results in internal wrapping and higher interrupt rates. 155 * The limit of 46 frames was chosen to match NFS workloads. 156 * 157 * These values also work well on bcm5701, bcm5704C, and (less 158 * tested) bcm5703. On other chipsets, (including the Altima chip 159 * family), the larger values may overflow internal chip limits, 160 * leading to increasing interrupt rates rather than lower interrupt 161 * rates. 162 * 163 * Applications using heavy interrupt mitigation (interrupting every 164 * 32 or 46 frames) in both directions may need to increase the TCP 165 * windowsize to above 131072 bytes (e.g., to 199608 bytes) to sustain 166 * full link bandwidth, due to ACKs and window updates lingering 167 * in the RX queue during the 30-to-40-frame interrupt-mitigation window. 168 */ 169 static const struct bge_load_rx_thresh { 170 int rx_ticks; 171 int rx_max_bds; } 172 bge_rx_threshes[] = { 173 { 32, 2 }, 174 { 50, 4 }, 175 { 100, 8 }, 176 { 192, 16 }, 177 { 416, 32 }, 178 { 598, 46 } 179 }; 180 #define NBGE_RX_THRESH (sizeof(bge_rx_threshes) / sizeof(bge_rx_threshes[0])) 181 182 /* XXX patchable; should be sysctl'able */ 183 static int bge_auto_thresh = 1; 184 static int bge_rx_thresh_lvl; 185 186 static int bge_rxthresh_nodenum; 187 188 typedef int (*bge_eaddr_fcn_t)(struct bge_softc *, u_int8_t[]); 189 190 static int bge_probe(device_t, cfdata_t, void *); 191 static void bge_attach(device_t, device_t, void *); 192 static void bge_release_resources(struct bge_softc *); 193 static void bge_txeof(struct bge_softc *); 194 static void bge_rxeof(struct bge_softc *); 195 196 static int bge_get_eaddr_mem(struct bge_softc *, u_int8_t[]); 197 static int bge_get_eaddr_nvram(struct bge_softc *, u_int8_t[]); 198 static int bge_get_eaddr_eeprom(struct bge_softc *, u_int8_t[]); 199 static int bge_get_eaddr(struct bge_softc *, u_int8_t[]); 200 201 static void bge_tick(void *); 202 static void bge_stats_update(struct bge_softc *); 203 static int bge_encap(struct bge_softc *, struct mbuf *, u_int32_t *); 204 205 static int bge_intr(void *); 206 static void bge_start(struct ifnet *); 207 static int bge_ioctl(struct ifnet *, u_long, void *); 208 static int bge_init(struct ifnet *); 209 static void bge_stop(struct ifnet *, int); 210 static void bge_watchdog(struct ifnet *); 211 static int bge_ifmedia_upd(struct ifnet *); 212 static void bge_ifmedia_sts(struct ifnet *, struct ifmediareq *); 213 214 static void bge_setmulti(struct bge_softc *); 215 216 static void bge_handle_events(struct bge_softc *); 217 static int bge_alloc_jumbo_mem(struct bge_softc *); 218 #if 0 /* XXX */ 219 static void bge_free_jumbo_mem(struct bge_softc *); 220 #endif 221 static void *bge_jalloc(struct bge_softc *); 222 static void bge_jfree(struct mbuf *, void *, size_t, void *); 223 static int bge_newbuf_std(struct bge_softc *, int, struct mbuf *, 224 bus_dmamap_t); 225 static int bge_newbuf_jumbo(struct bge_softc *, int, struct mbuf *); 226 static int bge_init_rx_ring_std(struct bge_softc *); 227 static void bge_free_rx_ring_std(struct bge_softc *); 228 static int bge_init_rx_ring_jumbo(struct bge_softc *); 229 static void bge_free_rx_ring_jumbo(struct bge_softc *); 230 static void bge_free_tx_ring(struct bge_softc *); 231 static int bge_init_tx_ring(struct bge_softc *); 232 233 static int bge_chipinit(struct bge_softc *); 234 static int bge_blockinit(struct bge_softc *); 235 static int bge_setpowerstate(struct bge_softc *, int); 236 237 static void bge_reset(struct bge_softc *); 238 static void bge_link_upd(struct bge_softc *); 239 240 #define BGE_DEBUG 241 #ifdef BGE_DEBUG 242 #define DPRINTF(x) if (bgedebug) printf x 243 #define DPRINTFN(n,x) if (bgedebug >= (n)) printf x 244 #define BGE_TSO_PRINTF(x) do { if (bge_tso_debug) printf x ;} while (0) 245 int bgedebug = 0; 246 int bge_tso_debug = 0; 247 #else 248 #define DPRINTF(x) 249 #define DPRINTFN(n,x) 250 #define BGE_TSO_PRINTF(x) 251 #endif 252 253 #ifdef BGE_EVENT_COUNTERS 254 #define BGE_EVCNT_INCR(ev) (ev).ev_count++ 255 #define BGE_EVCNT_ADD(ev, val) (ev).ev_count += (val) 256 #define BGE_EVCNT_UPD(ev, val) (ev).ev_count = (val) 257 #else 258 #define BGE_EVCNT_INCR(ev) /* nothing */ 259 #define BGE_EVCNT_ADD(ev, val) /* nothing */ 260 #define BGE_EVCNT_UPD(ev, val) /* nothing */ 261 #endif 262 263 static const struct bge_product { 264 pci_vendor_id_t bp_vendor; 265 pci_product_id_t bp_product; 266 const char *bp_name; 267 } bge_products[] = { 268 /* 269 * The BCM5700 documentation seems to indicate that the hardware 270 * still has the Alteon vendor ID burned into it, though it 271 * should always be overridden by the value in the EEPROM. We'll 272 * check for it anyway. 273 */ 274 { PCI_VENDOR_ALTEON, 275 PCI_PRODUCT_ALTEON_BCM5700, 276 "Broadcom BCM5700 Gigabit Ethernet", 277 }, 278 { PCI_VENDOR_ALTEON, 279 PCI_PRODUCT_ALTEON_BCM5701, 280 "Broadcom BCM5701 Gigabit Ethernet", 281 }, 282 { PCI_VENDOR_ALTIMA, 283 PCI_PRODUCT_ALTIMA_AC1000, 284 "Altima AC1000 Gigabit Ethernet", 285 }, 286 { PCI_VENDOR_ALTIMA, 287 PCI_PRODUCT_ALTIMA_AC1001, 288 "Altima AC1001 Gigabit Ethernet", 289 }, 290 { PCI_VENDOR_ALTIMA, 291 PCI_PRODUCT_ALTIMA_AC9100, 292 "Altima AC9100 Gigabit Ethernet", 293 }, 294 { PCI_VENDOR_BROADCOM, 295 PCI_PRODUCT_BROADCOM_BCM5700, 296 "Broadcom BCM5700 Gigabit Ethernet", 297 }, 298 { PCI_VENDOR_BROADCOM, 299 PCI_PRODUCT_BROADCOM_BCM5701, 300 "Broadcom BCM5701 Gigabit Ethernet", 301 }, 302 { PCI_VENDOR_BROADCOM, 303 PCI_PRODUCT_BROADCOM_BCM5702, 304 "Broadcom BCM5702 Gigabit Ethernet", 305 }, 306 { PCI_VENDOR_BROADCOM, 307 PCI_PRODUCT_BROADCOM_BCM5702X, 308 "Broadcom BCM5702X Gigabit Ethernet" }, 309 { PCI_VENDOR_BROADCOM, 310 PCI_PRODUCT_BROADCOM_BCM5703, 311 "Broadcom BCM5703 Gigabit Ethernet", 312 }, 313 { PCI_VENDOR_BROADCOM, 314 PCI_PRODUCT_BROADCOM_BCM5703X, 315 "Broadcom BCM5703X Gigabit Ethernet", 316 }, 317 { PCI_VENDOR_BROADCOM, 318 PCI_PRODUCT_BROADCOM_BCM5703_ALT, 319 "Broadcom BCM5703 Gigabit Ethernet", 320 }, 321 { PCI_VENDOR_BROADCOM, 322 PCI_PRODUCT_BROADCOM_BCM5704C, 323 "Broadcom BCM5704C Dual Gigabit Ethernet", 324 }, 325 { PCI_VENDOR_BROADCOM, 326 PCI_PRODUCT_BROADCOM_BCM5704S, 327 "Broadcom BCM5704S Dual Gigabit Ethernet", 328 }, 329 { PCI_VENDOR_BROADCOM, 330 PCI_PRODUCT_BROADCOM_BCM5705, 331 "Broadcom BCM5705 Gigabit Ethernet", 332 }, 333 { PCI_VENDOR_BROADCOM, 334 PCI_PRODUCT_BROADCOM_BCM5705K, 335 "Broadcom BCM5705K Gigabit Ethernet", 336 }, 337 { PCI_VENDOR_BROADCOM, 338 PCI_PRODUCT_BROADCOM_BCM5705M, 339 "Broadcom BCM5705M Gigabit Ethernet", 340 }, 341 { PCI_VENDOR_BROADCOM, 342 PCI_PRODUCT_BROADCOM_BCM5705M_ALT, 343 "Broadcom BCM5705M Gigabit Ethernet", 344 }, 345 { PCI_VENDOR_BROADCOM, 346 PCI_PRODUCT_BROADCOM_BCM5714, 347 "Broadcom BCM5714/5715 Gigabit Ethernet", 348 }, 349 { PCI_VENDOR_BROADCOM, 350 PCI_PRODUCT_BROADCOM_BCM5715, 351 "Broadcom BCM5714/5715 Gigabit Ethernet", 352 }, 353 { PCI_VENDOR_BROADCOM, 354 PCI_PRODUCT_BROADCOM_BCM5789, 355 "Broadcom BCM5789 Gigabit Ethernet", 356 }, 357 { PCI_VENDOR_BROADCOM, 358 PCI_PRODUCT_BROADCOM_BCM5721, 359 "Broadcom BCM5721 Gigabit Ethernet", 360 }, 361 { PCI_VENDOR_BROADCOM, 362 PCI_PRODUCT_BROADCOM_BCM5722, 363 "Broadcom BCM5722 Gigabit Ethernet", 364 }, 365 { PCI_VENDOR_BROADCOM, 366 PCI_PRODUCT_BROADCOM_BCM5750, 367 "Broadcom BCM5750 Gigabit Ethernet", 368 }, 369 { PCI_VENDOR_BROADCOM, 370 PCI_PRODUCT_BROADCOM_BCM5750M, 371 "Broadcom BCM5750M Gigabit Ethernet", 372 }, 373 { PCI_VENDOR_BROADCOM, 374 PCI_PRODUCT_BROADCOM_BCM5751, 375 "Broadcom BCM5751 Gigabit Ethernet", 376 }, 377 { PCI_VENDOR_BROADCOM, 378 PCI_PRODUCT_BROADCOM_BCM5751M, 379 "Broadcom BCM5751M Gigabit Ethernet", 380 }, 381 { PCI_VENDOR_BROADCOM, 382 PCI_PRODUCT_BROADCOM_BCM5752, 383 "Broadcom BCM5752 Gigabit Ethernet", 384 }, 385 { PCI_VENDOR_BROADCOM, 386 PCI_PRODUCT_BROADCOM_BCM5752M, 387 "Broadcom BCM5752M Gigabit Ethernet", 388 }, 389 { PCI_VENDOR_BROADCOM, 390 PCI_PRODUCT_BROADCOM_BCM5753, 391 "Broadcom BCM5753 Gigabit Ethernet", 392 }, 393 { PCI_VENDOR_BROADCOM, 394 PCI_PRODUCT_BROADCOM_BCM5753M, 395 "Broadcom BCM5753M Gigabit Ethernet", 396 }, 397 { PCI_VENDOR_BROADCOM, 398 PCI_PRODUCT_BROADCOM_BCM5754, 399 "Broadcom BCM5754 Gigabit Ethernet", 400 }, 401 { PCI_VENDOR_BROADCOM, 402 PCI_PRODUCT_BROADCOM_BCM5754M, 403 "Broadcom BCM5754M Gigabit Ethernet", 404 }, 405 { PCI_VENDOR_BROADCOM, 406 PCI_PRODUCT_BROADCOM_BCM5755, 407 "Broadcom BCM5755 Gigabit Ethernet", 408 }, 409 { PCI_VENDOR_BROADCOM, 410 PCI_PRODUCT_BROADCOM_BCM5755M, 411 "Broadcom BCM5755M Gigabit Ethernet", 412 }, 413 { PCI_VENDOR_BROADCOM, 414 PCI_PRODUCT_BROADCOM_BCM5780, 415 "Broadcom BCM5780 Gigabit Ethernet", 416 }, 417 { PCI_VENDOR_BROADCOM, 418 PCI_PRODUCT_BROADCOM_BCM5780S, 419 "Broadcom BCM5780S Gigabit Ethernet", 420 }, 421 { PCI_VENDOR_BROADCOM, 422 PCI_PRODUCT_BROADCOM_BCM5782, 423 "Broadcom BCM5782 Gigabit Ethernet", 424 }, 425 { PCI_VENDOR_BROADCOM, 426 PCI_PRODUCT_BROADCOM_BCM5786, 427 "Broadcom BCM5786 Gigabit Ethernet", 428 }, 429 { PCI_VENDOR_BROADCOM, 430 PCI_PRODUCT_BROADCOM_BCM5787, 431 "Broadcom BCM5787 Gigabit Ethernet", 432 }, 433 { PCI_VENDOR_BROADCOM, 434 PCI_PRODUCT_BROADCOM_BCM5787M, 435 "Broadcom BCM5787M Gigabit Ethernet", 436 }, 437 { PCI_VENDOR_BROADCOM, 438 PCI_PRODUCT_BROADCOM_BCM5788, 439 "Broadcom BCM5788 Gigabit Ethernet", 440 }, 441 { PCI_VENDOR_BROADCOM, 442 PCI_PRODUCT_BROADCOM_BCM5789, 443 "Broadcom BCM5789 Gigabit Ethernet", 444 }, 445 { PCI_VENDOR_BROADCOM, 446 PCI_PRODUCT_BROADCOM_BCM5901, 447 "Broadcom BCM5901 Fast Ethernet", 448 }, 449 { PCI_VENDOR_BROADCOM, 450 PCI_PRODUCT_BROADCOM_BCM5901A2, 451 "Broadcom BCM5901A2 Fast Ethernet", 452 }, 453 { PCI_VENDOR_SCHNEIDERKOCH, 454 PCI_PRODUCT_SCHNEIDERKOCH_SK_9DX1, 455 "SysKonnect SK-9Dx1 Gigabit Ethernet", 456 }, 457 { PCI_VENDOR_3COM, 458 PCI_PRODUCT_3COM_3C996, 459 "3Com 3c996 Gigabit Ethernet", 460 }, 461 { PCI_VENDOR_BROADCOM, 462 PCI_PRODUCT_BROADCOM_BCM5906, 463 "Broadcom BCM5906 Fast Ethernet", 464 }, 465 { PCI_VENDOR_BROADCOM, 466 PCI_PRODUCT_BROADCOM_BCM5906M, 467 "Broadcom BCM5906M Fast Ethernet", 468 }, 469 { 0, 470 0, 471 NULL }, 472 }; 473 474 /* 475 * XXX: how to handle variants based on 5750 and derivatives: 476 * 5750 5751, 5721, possibly 5714, 5752, and 5708?, which 477 * in general behave like a 5705, except with additional quirks. 478 * This driver's current handling of the 5721 is wrong; 479 * how we map ASIC revision to "quirks" needs more thought. 480 * (defined here until the thought is done). 481 */ 482 #define BGE_IS_5714_FAMILY(sc) \ 483 (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5714_A0 || \ 484 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5780 || \ 485 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5714 ) 486 487 #define BGE_IS_5750_OR_BEYOND(sc) \ 488 (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5750 || \ 489 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5752 || \ 490 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5755 || \ 491 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5787 || \ 492 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906 || \ 493 BGE_IS_5714_FAMILY(sc) ) 494 495 #define BGE_IS_5705_OR_BEYOND(sc) \ 496 (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5705 || \ 497 (BGE_IS_5750_OR_BEYOND(sc))) 498 499 #define BGE_IS_JUMBO_CAPABLE(sc) \ 500 (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || \ 501 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5701 || \ 502 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5703 || \ 503 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) 504 505 506 static const struct bge_revision { 507 uint32_t br_chipid; 508 const char *br_name; 509 } bge_revisions[] = { 510 { BGE_CHIPID_BCM5700_A0, "BCM5700 A0" }, 511 { BGE_CHIPID_BCM5700_A1, "BCM5700 A1" }, 512 { BGE_CHIPID_BCM5700_B0, "BCM5700 B0" }, 513 { BGE_CHIPID_BCM5700_B1, "BCM5700 B1" }, 514 { BGE_CHIPID_BCM5700_B2, "BCM5700 B2" }, 515 { BGE_CHIPID_BCM5700_B3, "BCM5700 B3" }, 516 /* This is treated like a BCM5700 Bx */ 517 { BGE_CHIPID_BCM5700_ALTIMA, "BCM5700 Altima" }, 518 { BGE_CHIPID_BCM5700_C0, "BCM5700 C0" }, 519 { BGE_CHIPID_BCM5701_A0, "BCM5701 A0" }, 520 { BGE_CHIPID_BCM5701_B0, "BCM5701 B0" }, 521 { BGE_CHIPID_BCM5701_B2, "BCM5701 B2" }, 522 { BGE_CHIPID_BCM5701_B5, "BCM5701 B5" }, 523 { BGE_CHIPID_BCM5703_A0, "BCM5703 A0" }, 524 { BGE_CHIPID_BCM5703_A1, "BCM5703 A1" }, 525 { BGE_CHIPID_BCM5703_A2, "BCM5703 A2" }, 526 { BGE_CHIPID_BCM5703_A3, "BCM5703 A3" }, 527 { BGE_CHIPID_BCM5703_B0, "BCM5703 B0" }, 528 { BGE_CHIPID_BCM5704_A0, "BCM5704 A0" }, 529 { BGE_CHIPID_BCM5704_A1, "BCM5704 A1" }, 530 { BGE_CHIPID_BCM5704_A2, "BCM5704 A2" }, 531 { BGE_CHIPID_BCM5704_A3, "BCM5704 A3" }, 532 { BGE_CHIPID_BCM5704_B0, "BCM5704 B0" }, 533 { BGE_CHIPID_BCM5705_A0, "BCM5705 A0" }, 534 { BGE_CHIPID_BCM5705_A1, "BCM5705 A1" }, 535 { BGE_CHIPID_BCM5705_A2, "BCM5705 A2" }, 536 { BGE_CHIPID_BCM5705_A3, "BCM5705 A3" }, 537 { BGE_CHIPID_BCM5750_A0, "BCM5750 A0" }, 538 { BGE_CHIPID_BCM5750_A1, "BCM5750 A1" }, 539 { BGE_CHIPID_BCM5750_A3, "BCM5750 A3" }, 540 { BGE_CHIPID_BCM5750_B0, "BCM5750 B0" }, 541 { BGE_CHIPID_BCM5750_B1, "BCM5750 B1" }, 542 { BGE_CHIPID_BCM5750_C0, "BCM5750 C0" }, 543 { BGE_CHIPID_BCM5750_C1, "BCM5750 C1" }, 544 { BGE_CHIPID_BCM5750_C2, "BCM5750 C2" }, 545 { BGE_CHIPID_BCM5752_A0, "BCM5752 A0" }, 546 { BGE_CHIPID_BCM5752_A1, "BCM5752 A1" }, 547 { BGE_CHIPID_BCM5752_A2, "BCM5752 A2" }, 548 { BGE_CHIPID_BCM5714_A0, "BCM5714 A0" }, 549 { BGE_CHIPID_BCM5714_B0, "BCM5714 B0" }, 550 { BGE_CHIPID_BCM5714_B3, "BCM5714 B3" }, 551 { BGE_CHIPID_BCM5715_A0, "BCM5715 A0" }, 552 { BGE_CHIPID_BCM5715_A1, "BCM5715 A1" }, 553 { BGE_CHIPID_BCM5715_A3, "BCM5715 A3" }, 554 { BGE_CHIPID_BCM5755_A0, "BCM5755 A0" }, 555 { BGE_CHIPID_BCM5755_A1, "BCM5755 A1" }, 556 { BGE_CHIPID_BCM5755_A2, "BCM5755 A2" }, 557 { BGE_CHIPID_BCM5755_C0, "BCM5755 C0" }, 558 { BGE_CHIPID_BCM5787_A0, "BCM5754/5787 A0" }, 559 { BGE_CHIPID_BCM5787_A1, "BCM5754/5787 A1" }, 560 { BGE_CHIPID_BCM5787_A2, "BCM5754/5787 A2" }, 561 { BGE_CHIPID_BCM5906_A1, "BCM5906 A1" }, 562 { BGE_CHIPID_BCM5906_A2, "BCM5906 A2" }, 563 { 0, NULL } 564 }; 565 566 /* 567 * Some defaults for major revisions, so that newer steppings 568 * that we don't know about have a shot at working. 569 */ 570 static const struct bge_revision bge_majorrevs[] = { 571 { BGE_ASICREV_BCM5700, "unknown BCM5700" }, 572 { BGE_ASICREV_BCM5701, "unknown BCM5701" }, 573 { BGE_ASICREV_BCM5703, "unknown BCM5703" }, 574 { BGE_ASICREV_BCM5704, "unknown BCM5704" }, 575 { BGE_ASICREV_BCM5705, "unknown BCM5705" }, 576 { BGE_ASICREV_BCM5750, "unknown BCM5750" }, 577 { BGE_ASICREV_BCM5714_A0, "unknown BCM5714" }, 578 { BGE_ASICREV_BCM5714, "unknown BCM5714" }, 579 { BGE_ASICREV_BCM5752, "unknown BCM5752 family" }, 580 { BGE_ASICREV_BCM5755, "unknown BCM5755" }, 581 { BGE_ASICREV_BCM5780, "unknown BCM5780" }, 582 /* 5754 and 5787 share the same ASIC ID */ 583 { BGE_ASICREV_BCM5787, "unknown BCM5754/5787" }, 584 { BGE_ASICREV_BCM5906, "unknown BCM5906" }, 585 { 0, NULL } 586 }; 587 588 CFATTACH_DECL_NEW(bge, sizeof(struct bge_softc), 589 bge_probe, bge_attach, NULL, NULL); 590 591 static u_int32_t 592 bge_readmem_ind(struct bge_softc *sc, int off) 593 { 594 pcireg_t val; 595 596 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_BASEADDR, off); 597 val = pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_DATA); 598 return val; 599 } 600 601 static void 602 bge_writemem_ind(struct bge_softc *sc, int off, int val) 603 { 604 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_BASEADDR, off); 605 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_DATA, val); 606 } 607 608 #ifdef notdef 609 static u_int32_t 610 bge_readreg_ind(struct bge_softc *sc, int off) 611 { 612 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_REG_BASEADDR, off); 613 return (pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_REG_DATA)); 614 } 615 #endif 616 617 static void 618 bge_writereg_ind(struct bge_softc *sc, int off, int val) 619 { 620 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_REG_BASEADDR, off); 621 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_REG_DATA, val); 622 } 623 624 static void 625 bge_writemem_direct(struct bge_softc *sc, int off, int val) 626 { 627 CSR_WRITE_4(sc, off, val); 628 } 629 630 static void 631 bge_writembx(struct bge_softc *sc, int off, int val) 632 { 633 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 634 off += BGE_LPMBX_IRQ0_HI - BGE_MBX_IRQ0_HI; 635 636 CSR_WRITE_4(sc, off, val); 637 } 638 639 static u_int8_t 640 bge_nvram_getbyte(struct bge_softc *sc, int addr, u_int8_t *dest) 641 { 642 u_int32_t access, byte = 0; 643 int i; 644 645 /* Lock. */ 646 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_SET1); 647 for (i = 0; i < 8000; i++) { 648 if (CSR_READ_4(sc, BGE_NVRAM_SWARB) & BGE_NVRAMSWARB_GNT1) 649 break; 650 DELAY(20); 651 } 652 if (i == 8000) 653 return (1); 654 655 /* Enable access. */ 656 access = CSR_READ_4(sc, BGE_NVRAM_ACCESS); 657 CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access | BGE_NVRAMACC_ENABLE); 658 659 CSR_WRITE_4(sc, BGE_NVRAM_ADDR, addr & 0xfffffffc); 660 CSR_WRITE_4(sc, BGE_NVRAM_CMD, BGE_NVRAM_READCMD); 661 for (i = 0; i < BGE_TIMEOUT * 10; i++) { 662 DELAY(10); 663 if (CSR_READ_4(sc, BGE_NVRAM_CMD) & BGE_NVRAMCMD_DONE) { 664 DELAY(10); 665 break; 666 } 667 } 668 669 if (i == BGE_TIMEOUT * 10) { 670 aprint_error_dev(sc->bge_dev, "nvram read timed out\n"); 671 return (1); 672 } 673 674 /* Get result. */ 675 byte = CSR_READ_4(sc, BGE_NVRAM_RDDATA); 676 677 *dest = (bswap32(byte) >> ((addr % 4) * 8)) & 0xFF; 678 679 /* Disable access. */ 680 CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access); 681 682 /* Unlock. */ 683 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_CLR1); 684 CSR_READ_4(sc, BGE_NVRAM_SWARB); 685 686 return (0); 687 } 688 689 /* 690 * Read a sequence of bytes from NVRAM. 691 */ 692 static int 693 bge_read_nvram(struct bge_softc *sc, u_int8_t *dest, int off, int cnt) 694 { 695 int err = 0, i; 696 u_int8_t byte = 0; 697 698 if (BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5906) 699 return (1); 700 701 for (i = 0; i < cnt; i++) { 702 err = bge_nvram_getbyte(sc, off + i, &byte); 703 if (err) 704 break; 705 *(dest + i) = byte; 706 } 707 708 return (err ? 1 : 0); 709 } 710 711 /* 712 * Read a byte of data stored in the EEPROM at address 'addr.' The 713 * BCM570x supports both the traditional bitbang interface and an 714 * auto access interface for reading the EEPROM. We use the auto 715 * access method. 716 */ 717 static u_int8_t 718 bge_eeprom_getbyte(struct bge_softc *sc, int addr, u_int8_t *dest) 719 { 720 int i; 721 u_int32_t byte = 0; 722 723 /* 724 * Enable use of auto EEPROM access so we can avoid 725 * having to use the bitbang method. 726 */ 727 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM); 728 729 /* Reset the EEPROM, load the clock period. */ 730 CSR_WRITE_4(sc, BGE_EE_ADDR, 731 BGE_EEADDR_RESET | BGE_EEHALFCLK(BGE_HALFCLK_384SCL)); 732 DELAY(20); 733 734 /* Issue the read EEPROM command. */ 735 CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr); 736 737 /* Wait for completion */ 738 for(i = 0; i < BGE_TIMEOUT * 10; i++) { 739 DELAY(10); 740 if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE) 741 break; 742 } 743 744 if (i == BGE_TIMEOUT) { 745 aprint_error_dev(sc->bge_dev, "eeprom read timed out\n"); 746 return (0); 747 } 748 749 /* Get result. */ 750 byte = CSR_READ_4(sc, BGE_EE_DATA); 751 752 *dest = (byte >> ((addr % 4) * 8)) & 0xFF; 753 754 return (0); 755 } 756 757 /* 758 * Read a sequence of bytes from the EEPROM. 759 */ 760 static int 761 bge_read_eeprom(struct bge_softc *sc, void *destv, int off, int cnt) 762 { 763 int err = 0, i; 764 u_int8_t byte = 0; 765 char *dest = destv; 766 767 for (i = 0; i < cnt; i++) { 768 err = bge_eeprom_getbyte(sc, off + i, &byte); 769 if (err) 770 break; 771 *(dest + i) = byte; 772 } 773 774 return (err ? 1 : 0); 775 } 776 777 static int 778 bge_miibus_readreg(device_t dev, int phy, int reg) 779 { 780 struct bge_softc *sc = device_private(dev); 781 u_int32_t val; 782 u_int32_t saved_autopoll; 783 int i; 784 785 /* 786 * Broadcom's own driver always assumes the internal 787 * PHY is at GMII address 1. On some chips, the PHY responds 788 * to accesses at all addresses, which could cause us to 789 * bogusly attach the PHY 32 times at probe type. Always 790 * restricting the lookup to address 1 is simpler than 791 * trying to figure out which chips revisions should be 792 * special-cased. 793 */ 794 if (phy != 1) 795 return (0); 796 797 /* Reading with autopolling on may trigger PCI errors */ 798 saved_autopoll = CSR_READ_4(sc, BGE_MI_MODE); 799 if (saved_autopoll & BGE_MIMODE_AUTOPOLL) { 800 BGE_STS_CLRBIT(sc, BGE_STS_AUTOPOLL); 801 CSR_WRITE_4(sc, BGE_MI_MODE, 802 saved_autopoll &~ BGE_MIMODE_AUTOPOLL); 803 DELAY(40); 804 } 805 806 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_READ|BGE_MICOMM_BUSY| 807 BGE_MIPHY(phy)|BGE_MIREG(reg)); 808 809 for (i = 0; i < BGE_TIMEOUT; i++) { 810 val = CSR_READ_4(sc, BGE_MI_COMM); 811 if (!(val & BGE_MICOMM_BUSY)) 812 break; 813 delay(10); 814 } 815 816 if (i == BGE_TIMEOUT) { 817 aprint_error_dev(sc->bge_dev, "PHY read timed out\n"); 818 val = 0; 819 goto done; 820 } 821 822 val = CSR_READ_4(sc, BGE_MI_COMM); 823 824 done: 825 if (saved_autopoll & BGE_MIMODE_AUTOPOLL) { 826 BGE_STS_SETBIT(sc, BGE_STS_AUTOPOLL); 827 CSR_WRITE_4(sc, BGE_MI_MODE, saved_autopoll); 828 DELAY(40); 829 } 830 831 if (val & BGE_MICOMM_READFAIL) 832 return (0); 833 834 return (val & 0xFFFF); 835 } 836 837 static void 838 bge_miibus_writereg(device_t dev, int phy, int reg, int val) 839 { 840 struct bge_softc *sc = device_private(dev); 841 u_int32_t saved_autopoll; 842 int i; 843 844 if (phy!=1) { 845 return; 846 } 847 848 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906 && 849 (reg == BRGPHY_MII_1000CTL || reg == BRGPHY_MII_AUXCTL)) { 850 return; 851 } 852 853 /* Reading with autopolling on may trigger PCI errors */ 854 saved_autopoll = CSR_READ_4(sc, BGE_MI_MODE); 855 if (saved_autopoll & BGE_MIMODE_AUTOPOLL) { 856 delay(40); 857 BGE_STS_CLRBIT(sc, BGE_STS_AUTOPOLL); 858 CSR_WRITE_4(sc, BGE_MI_MODE, 859 saved_autopoll & (~BGE_MIMODE_AUTOPOLL)); 860 delay(10); /* 40 usec is supposed to be adequate */ 861 } 862 863 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_WRITE | BGE_MICOMM_BUSY | 864 BGE_MIPHY(phy) | BGE_MIREG(reg)|val); 865 866 for (i = 0; i < BGE_TIMEOUT; i++) { 867 delay(10); 868 if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY)) { 869 delay(5); 870 CSR_READ_4(sc, BGE_MI_COMM); 871 break; 872 } 873 } 874 875 if (saved_autopoll & BGE_MIMODE_AUTOPOLL) { 876 BGE_STS_SETBIT(sc, BGE_STS_AUTOPOLL); 877 CSR_WRITE_4(sc, BGE_MI_MODE, saved_autopoll); 878 delay(40); 879 } 880 881 if (i == BGE_TIMEOUT) 882 aprint_error_dev(sc->bge_dev, "PHY read timed out\n"); 883 } 884 885 static void 886 bge_miibus_statchg(device_t dev) 887 { 888 struct bge_softc *sc = device_private(dev); 889 struct mii_data *mii = &sc->bge_mii; 890 891 /* 892 * Get flow control negotiation result. 893 */ 894 if (IFM_SUBTYPE(mii->mii_media.ifm_cur->ifm_media) == IFM_AUTO && 895 (mii->mii_media_active & IFM_ETH_FMASK) != sc->bge_flowflags) { 896 sc->bge_flowflags = mii->mii_media_active & IFM_ETH_FMASK; 897 mii->mii_media_active &= ~IFM_ETH_FMASK; 898 } 899 900 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_PORTMODE); 901 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T || 902 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX) 903 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_GMII); 904 else 905 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_MII); 906 907 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) 908 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX); 909 else 910 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX); 911 912 /* 913 * 802.3x flow control 914 */ 915 if (sc->bge_flowflags & IFM_ETH_RXPAUSE) 916 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_FLOWCTL_ENABLE); 917 else 918 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_FLOWCTL_ENABLE); 919 920 if (sc->bge_flowflags & IFM_ETH_TXPAUSE) 921 BGE_SETBIT(sc, BGE_TX_MODE, BGE_TXMODE_FLOWCTL_ENABLE); 922 else 923 BGE_CLRBIT(sc, BGE_TX_MODE, BGE_TXMODE_FLOWCTL_ENABLE); 924 } 925 926 /* 927 * Update rx threshold levels to values in a particular slot 928 * of the interrupt-mitigation table bge_rx_threshes. 929 */ 930 static void 931 bge_set_thresh(struct ifnet *ifp, int lvl) 932 { 933 struct bge_softc *sc = ifp->if_softc; 934 int s; 935 936 /* For now, just save the new Rx-intr thresholds and record 937 * that a threshold update is pending. Updating the hardware 938 * registers here (even at splhigh()) is observed to 939 * occasionaly cause glitches where Rx-interrupts are not 940 * honoured for up to 10 seconds. jonathan (at) NetBSD.org, 2003-04-05 941 */ 942 s = splnet(); 943 sc->bge_rx_coal_ticks = bge_rx_threshes[lvl].rx_ticks; 944 sc->bge_rx_max_coal_bds = bge_rx_threshes[lvl].rx_max_bds; 945 sc->bge_pending_rxintr_change = 1; 946 splx(s); 947 948 return; 949 } 950 951 952 /* 953 * Update Rx thresholds of all bge devices 954 */ 955 static void 956 bge_update_all_threshes(int lvl) 957 { 958 struct ifnet *ifp; 959 const char * const namebuf = "bge"; 960 int namelen; 961 962 if (lvl < 0) 963 lvl = 0; 964 else if( lvl >= NBGE_RX_THRESH) 965 lvl = NBGE_RX_THRESH - 1; 966 967 namelen = strlen(namebuf); 968 /* 969 * Now search all the interfaces for this name/number 970 */ 971 IFNET_FOREACH(ifp) { 972 if (strncmp(ifp->if_xname, namebuf, namelen) != 0) 973 continue; 974 /* We got a match: update if doing auto-threshold-tuning */ 975 if (bge_auto_thresh) 976 bge_set_thresh(ifp, lvl); 977 } 978 } 979 980 /* 981 * Handle events that have triggered interrupts. 982 */ 983 static void 984 bge_handle_events(struct bge_softc *sc) 985 { 986 987 return; 988 } 989 990 /* 991 * Memory management for jumbo frames. 992 */ 993 994 static int 995 bge_alloc_jumbo_mem(struct bge_softc *sc) 996 { 997 char *ptr, *kva; 998 bus_dma_segment_t seg; 999 int i, rseg, state, error; 1000 struct bge_jpool_entry *entry; 1001 1002 state = error = 0; 1003 1004 /* Grab a big chunk o' storage. */ 1005 if (bus_dmamem_alloc(sc->bge_dmatag, BGE_JMEM, PAGE_SIZE, 0, 1006 &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 1007 aprint_error_dev(sc->bge_dev, "can't alloc rx buffers\n"); 1008 return ENOBUFS; 1009 } 1010 1011 state = 1; 1012 if (bus_dmamem_map(sc->bge_dmatag, &seg, rseg, BGE_JMEM, (void **)&kva, 1013 BUS_DMA_NOWAIT)) { 1014 aprint_error_dev(sc->bge_dev, 1015 "can't map DMA buffers (%d bytes)\n", (int)BGE_JMEM); 1016 error = ENOBUFS; 1017 goto out; 1018 } 1019 1020 state = 2; 1021 if (bus_dmamap_create(sc->bge_dmatag, BGE_JMEM, 1, BGE_JMEM, 0, 1022 BUS_DMA_NOWAIT, &sc->bge_cdata.bge_rx_jumbo_map)) { 1023 aprint_error_dev(sc->bge_dev, "can't create DMA map\n"); 1024 error = ENOBUFS; 1025 goto out; 1026 } 1027 1028 state = 3; 1029 if (bus_dmamap_load(sc->bge_dmatag, sc->bge_cdata.bge_rx_jumbo_map, 1030 kva, BGE_JMEM, NULL, BUS_DMA_NOWAIT)) { 1031 aprint_error_dev(sc->bge_dev, "can't load DMA map\n"); 1032 error = ENOBUFS; 1033 goto out; 1034 } 1035 1036 state = 4; 1037 sc->bge_cdata.bge_jumbo_buf = (void *)kva; 1038 DPRINTFN(1,("bge_jumbo_buf = %p\n", sc->bge_cdata.bge_jumbo_buf)); 1039 1040 SLIST_INIT(&sc->bge_jfree_listhead); 1041 SLIST_INIT(&sc->bge_jinuse_listhead); 1042 1043 /* 1044 * Now divide it up into 9K pieces and save the addresses 1045 * in an array. 1046 */ 1047 ptr = sc->bge_cdata.bge_jumbo_buf; 1048 for (i = 0; i < BGE_JSLOTS; i++) { 1049 sc->bge_cdata.bge_jslots[i] = ptr; 1050 ptr += BGE_JLEN; 1051 entry = malloc(sizeof(struct bge_jpool_entry), 1052 M_DEVBUF, M_NOWAIT); 1053 if (entry == NULL) { 1054 aprint_error_dev(sc->bge_dev, 1055 "no memory for jumbo buffer queue!\n"); 1056 error = ENOBUFS; 1057 goto out; 1058 } 1059 entry->slot = i; 1060 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, 1061 entry, jpool_entries); 1062 } 1063 out: 1064 if (error != 0) { 1065 switch (state) { 1066 case 4: 1067 bus_dmamap_unload(sc->bge_dmatag, 1068 sc->bge_cdata.bge_rx_jumbo_map); 1069 case 3: 1070 bus_dmamap_destroy(sc->bge_dmatag, 1071 sc->bge_cdata.bge_rx_jumbo_map); 1072 case 2: 1073 bus_dmamem_unmap(sc->bge_dmatag, kva, BGE_JMEM); 1074 case 1: 1075 bus_dmamem_free(sc->bge_dmatag, &seg, rseg); 1076 break; 1077 default: 1078 break; 1079 } 1080 } 1081 1082 return error; 1083 } 1084 1085 /* 1086 * Allocate a jumbo buffer. 1087 */ 1088 static void * 1089 bge_jalloc(struct bge_softc *sc) 1090 { 1091 struct bge_jpool_entry *entry; 1092 1093 entry = SLIST_FIRST(&sc->bge_jfree_listhead); 1094 1095 if (entry == NULL) { 1096 aprint_error_dev(sc->bge_dev, "no free jumbo buffers\n"); 1097 return (NULL); 1098 } 1099 1100 SLIST_REMOVE_HEAD(&sc->bge_jfree_listhead, jpool_entries); 1101 SLIST_INSERT_HEAD(&sc->bge_jinuse_listhead, entry, jpool_entries); 1102 return (sc->bge_cdata.bge_jslots[entry->slot]); 1103 } 1104 1105 /* 1106 * Release a jumbo buffer. 1107 */ 1108 static void 1109 bge_jfree(struct mbuf *m, void *buf, size_t size, void *arg) 1110 { 1111 struct bge_jpool_entry *entry; 1112 struct bge_softc *sc; 1113 int i, s; 1114 1115 /* Extract the softc struct pointer. */ 1116 sc = (struct bge_softc *)arg; 1117 1118 if (sc == NULL) 1119 panic("bge_jfree: can't find softc pointer!"); 1120 1121 /* calculate the slot this buffer belongs to */ 1122 1123 i = ((char *)buf 1124 - (char *)sc->bge_cdata.bge_jumbo_buf) / BGE_JLEN; 1125 1126 if ((i < 0) || (i >= BGE_JSLOTS)) 1127 panic("bge_jfree: asked to free buffer that we don't manage!"); 1128 1129 s = splvm(); 1130 entry = SLIST_FIRST(&sc->bge_jinuse_listhead); 1131 if (entry == NULL) 1132 panic("bge_jfree: buffer not in use!"); 1133 entry->slot = i; 1134 SLIST_REMOVE_HEAD(&sc->bge_jinuse_listhead, jpool_entries); 1135 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, entry, jpool_entries); 1136 1137 if (__predict_true(m != NULL)) 1138 pool_cache_put(mb_cache, m); 1139 splx(s); 1140 } 1141 1142 1143 /* 1144 * Intialize a standard receive ring descriptor. 1145 */ 1146 static int 1147 bge_newbuf_std(struct bge_softc *sc, int i, struct mbuf *m, bus_dmamap_t dmamap) 1148 { 1149 struct mbuf *m_new = NULL; 1150 struct bge_rx_bd *r; 1151 int error; 1152 1153 if (dmamap == NULL) { 1154 error = bus_dmamap_create(sc->bge_dmatag, MCLBYTES, 1, 1155 MCLBYTES, 0, BUS_DMA_NOWAIT, &dmamap); 1156 if (error != 0) 1157 return error; 1158 } 1159 1160 sc->bge_cdata.bge_rx_std_map[i] = dmamap; 1161 1162 if (m == NULL) { 1163 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1164 if (m_new == NULL) 1165 return (ENOBUFS); 1166 1167 MCLGET(m_new, M_DONTWAIT); 1168 if (!(m_new->m_flags & M_EXT)) { 1169 m_freem(m_new); 1170 return (ENOBUFS); 1171 } 1172 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1173 1174 } else { 1175 m_new = m; 1176 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1177 m_new->m_data = m_new->m_ext.ext_buf; 1178 } 1179 if (!(sc->bge_flags & BGE_RX_ALIGNBUG)) 1180 m_adj(m_new, ETHER_ALIGN); 1181 if (bus_dmamap_load_mbuf(sc->bge_dmatag, dmamap, m_new, 1182 BUS_DMA_READ|BUS_DMA_NOWAIT)) 1183 return (ENOBUFS); 1184 bus_dmamap_sync(sc->bge_dmatag, dmamap, 0, dmamap->dm_mapsize, 1185 BUS_DMASYNC_PREREAD); 1186 1187 sc->bge_cdata.bge_rx_std_chain[i] = m_new; 1188 r = &sc->bge_rdata->bge_rx_std_ring[i]; 1189 bge_set_hostaddr(&r->bge_addr, 1190 dmamap->dm_segs[0].ds_addr); 1191 r->bge_flags = BGE_RXBDFLAG_END; 1192 r->bge_len = m_new->m_len; 1193 r->bge_idx = i; 1194 1195 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 1196 offsetof(struct bge_ring_data, bge_rx_std_ring) + 1197 i * sizeof (struct bge_rx_bd), 1198 sizeof (struct bge_rx_bd), 1199 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1200 1201 return (0); 1202 } 1203 1204 /* 1205 * Initialize a jumbo receive ring descriptor. This allocates 1206 * a jumbo buffer from the pool managed internally by the driver. 1207 */ 1208 static int 1209 bge_newbuf_jumbo(struct bge_softc *sc, int i, struct mbuf *m) 1210 { 1211 struct mbuf *m_new = NULL; 1212 struct bge_rx_bd *r; 1213 void *buf = NULL; 1214 1215 if (m == NULL) { 1216 1217 /* Allocate the mbuf. */ 1218 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1219 if (m_new == NULL) 1220 return (ENOBUFS); 1221 1222 /* Allocate the jumbo buffer */ 1223 buf = bge_jalloc(sc); 1224 if (buf == NULL) { 1225 m_freem(m_new); 1226 aprint_error_dev(sc->bge_dev, 1227 "jumbo allocation failed -- packet dropped!\n"); 1228 return (ENOBUFS); 1229 } 1230 1231 /* Attach the buffer to the mbuf. */ 1232 m_new->m_len = m_new->m_pkthdr.len = BGE_JUMBO_FRAMELEN; 1233 MEXTADD(m_new, buf, BGE_JUMBO_FRAMELEN, M_DEVBUF, 1234 bge_jfree, sc); 1235 m_new->m_flags |= M_EXT_RW; 1236 } else { 1237 m_new = m; 1238 buf = m_new->m_data = m_new->m_ext.ext_buf; 1239 m_new->m_ext.ext_size = BGE_JUMBO_FRAMELEN; 1240 } 1241 if (!(sc->bge_flags & BGE_RX_ALIGNBUG)) 1242 m_adj(m_new, ETHER_ALIGN); 1243 bus_dmamap_sync(sc->bge_dmatag, sc->bge_cdata.bge_rx_jumbo_map, 1244 mtod(m_new, char *) - (char *)sc->bge_cdata.bge_jumbo_buf, BGE_JLEN, 1245 BUS_DMASYNC_PREREAD); 1246 /* Set up the descriptor. */ 1247 r = &sc->bge_rdata->bge_rx_jumbo_ring[i]; 1248 sc->bge_cdata.bge_rx_jumbo_chain[i] = m_new; 1249 bge_set_hostaddr(&r->bge_addr, BGE_JUMBO_DMA_ADDR(sc, m_new)); 1250 r->bge_flags = BGE_RXBDFLAG_END|BGE_RXBDFLAG_JUMBO_RING; 1251 r->bge_len = m_new->m_len; 1252 r->bge_idx = i; 1253 1254 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 1255 offsetof(struct bge_ring_data, bge_rx_jumbo_ring) + 1256 i * sizeof (struct bge_rx_bd), 1257 sizeof (struct bge_rx_bd), 1258 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1259 1260 return (0); 1261 } 1262 1263 /* 1264 * The standard receive ring has 512 entries in it. At 2K per mbuf cluster, 1265 * that's 1MB or memory, which is a lot. For now, we fill only the first 1266 * 256 ring entries and hope that our CPU is fast enough to keep up with 1267 * the NIC. 1268 */ 1269 static int 1270 bge_init_rx_ring_std(struct bge_softc *sc) 1271 { 1272 int i; 1273 1274 if (sc->bge_flags & BGE_RXRING_VALID) 1275 return 0; 1276 1277 for (i = 0; i < BGE_SSLOTS; i++) { 1278 if (bge_newbuf_std(sc, i, NULL, 0) == ENOBUFS) 1279 return (ENOBUFS); 1280 } 1281 1282 sc->bge_std = i - 1; 1283 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std); 1284 1285 sc->bge_flags |= BGE_RXRING_VALID; 1286 1287 return (0); 1288 } 1289 1290 static void 1291 bge_free_rx_ring_std(struct bge_softc *sc) 1292 { 1293 int i; 1294 1295 if (!(sc->bge_flags & BGE_RXRING_VALID)) 1296 return; 1297 1298 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { 1299 if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) { 1300 m_freem(sc->bge_cdata.bge_rx_std_chain[i]); 1301 sc->bge_cdata.bge_rx_std_chain[i] = NULL; 1302 bus_dmamap_destroy(sc->bge_dmatag, 1303 sc->bge_cdata.bge_rx_std_map[i]); 1304 } 1305 memset((char *)&sc->bge_rdata->bge_rx_std_ring[i], 0, 1306 sizeof(struct bge_rx_bd)); 1307 } 1308 1309 sc->bge_flags &= ~BGE_RXRING_VALID; 1310 } 1311 1312 static int 1313 bge_init_rx_ring_jumbo(struct bge_softc *sc) 1314 { 1315 int i; 1316 volatile struct bge_rcb *rcb; 1317 1318 if (sc->bge_flags & BGE_JUMBO_RXRING_VALID) 1319 return 0; 1320 1321 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 1322 if (bge_newbuf_jumbo(sc, i, NULL) == ENOBUFS) 1323 return (ENOBUFS); 1324 }; 1325 1326 sc->bge_jumbo = i - 1; 1327 sc->bge_flags |= BGE_JUMBO_RXRING_VALID; 1328 1329 rcb = &sc->bge_rdata->bge_info.bge_jumbo_rx_rcb; 1330 rcb->bge_maxlen_flags = 0; 1331 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 1332 1333 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo); 1334 1335 return (0); 1336 } 1337 1338 static void 1339 bge_free_rx_ring_jumbo(struct bge_softc *sc) 1340 { 1341 int i; 1342 1343 if (!(sc->bge_flags & BGE_JUMBO_RXRING_VALID)) 1344 return; 1345 1346 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 1347 if (sc->bge_cdata.bge_rx_jumbo_chain[i] != NULL) { 1348 m_freem(sc->bge_cdata.bge_rx_jumbo_chain[i]); 1349 sc->bge_cdata.bge_rx_jumbo_chain[i] = NULL; 1350 } 1351 memset((char *)&sc->bge_rdata->bge_rx_jumbo_ring[i], 0, 1352 sizeof(struct bge_rx_bd)); 1353 } 1354 1355 sc->bge_flags &= ~BGE_JUMBO_RXRING_VALID; 1356 } 1357 1358 static void 1359 bge_free_tx_ring(struct bge_softc *sc) 1360 { 1361 int i, freed; 1362 struct txdmamap_pool_entry *dma; 1363 1364 if (!(sc->bge_flags & BGE_TXRING_VALID)) 1365 return; 1366 1367 freed = 0; 1368 1369 for (i = 0; i < BGE_TX_RING_CNT; i++) { 1370 if (sc->bge_cdata.bge_tx_chain[i] != NULL) { 1371 freed++; 1372 m_freem(sc->bge_cdata.bge_tx_chain[i]); 1373 sc->bge_cdata.bge_tx_chain[i] = NULL; 1374 SLIST_INSERT_HEAD(&sc->txdma_list, sc->txdma[i], 1375 link); 1376 sc->txdma[i] = 0; 1377 } 1378 memset((char *)&sc->bge_rdata->bge_tx_ring[i], 0, 1379 sizeof(struct bge_tx_bd)); 1380 } 1381 1382 while ((dma = SLIST_FIRST(&sc->txdma_list))) { 1383 SLIST_REMOVE_HEAD(&sc->txdma_list, link); 1384 bus_dmamap_destroy(sc->bge_dmatag, dma->dmamap); 1385 free(dma, M_DEVBUF); 1386 } 1387 1388 sc->bge_flags &= ~BGE_TXRING_VALID; 1389 } 1390 1391 static int 1392 bge_init_tx_ring(struct bge_softc *sc) 1393 { 1394 int i; 1395 bus_dmamap_t dmamap; 1396 struct txdmamap_pool_entry *dma; 1397 1398 if (sc->bge_flags & BGE_TXRING_VALID) 1399 return 0; 1400 1401 sc->bge_txcnt = 0; 1402 sc->bge_tx_saved_considx = 0; 1403 1404 /* Initialize transmit producer index for host-memory send ring. */ 1405 sc->bge_tx_prodidx = 0; 1406 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx); 1407 /* 5700 b2 errata */ 1408 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX) 1409 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx); 1410 1411 /* NIC-memory send ring not used; initialize to zero. */ 1412 bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0); 1413 /* 5700 b2 errata */ 1414 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX) 1415 bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0); 1416 1417 SLIST_INIT(&sc->txdma_list); 1418 for (i = 0; i < BGE_RSLOTS; i++) { 1419 if (bus_dmamap_create(sc->bge_dmatag, BGE_TXDMA_MAX, 1420 BGE_NTXSEG, ETHER_MAX_LEN_JUMBO, 0, BUS_DMA_NOWAIT, 1421 &dmamap)) 1422 return (ENOBUFS); 1423 if (dmamap == NULL) 1424 panic("dmamap NULL in bge_init_tx_ring"); 1425 dma = malloc(sizeof(*dma), M_DEVBUF, M_NOWAIT); 1426 if (dma == NULL) { 1427 aprint_error_dev(sc->bge_dev, 1428 "can't alloc txdmamap_pool_entry\n"); 1429 bus_dmamap_destroy(sc->bge_dmatag, dmamap); 1430 return (ENOMEM); 1431 } 1432 dma->dmamap = dmamap; 1433 SLIST_INSERT_HEAD(&sc->txdma_list, dma, link); 1434 } 1435 1436 sc->bge_flags |= BGE_TXRING_VALID; 1437 1438 return (0); 1439 } 1440 1441 static void 1442 bge_setmulti(struct bge_softc *sc) 1443 { 1444 struct ethercom *ac = &sc->ethercom; 1445 struct ifnet *ifp = &ac->ec_if; 1446 struct ether_multi *enm; 1447 struct ether_multistep step; 1448 u_int32_t hashes[4] = { 0, 0, 0, 0 }; 1449 u_int32_t h; 1450 int i; 1451 1452 if (ifp->if_flags & IFF_PROMISC) 1453 goto allmulti; 1454 1455 /* Now program new ones. */ 1456 ETHER_FIRST_MULTI(step, ac, enm); 1457 while (enm != NULL) { 1458 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1459 /* 1460 * We must listen to a range of multicast addresses. 1461 * For now, just accept all multicasts, rather than 1462 * trying to set only those filter bits needed to match 1463 * the range. (At this time, the only use of address 1464 * ranges is for IP multicast routing, for which the 1465 * range is big enough to require all bits set.) 1466 */ 1467 goto allmulti; 1468 } 1469 1470 h = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN); 1471 1472 /* Just want the 7 least-significant bits. */ 1473 h &= 0x7f; 1474 1475 hashes[(h & 0x60) >> 5] |= 1 << (h & 0x1F); 1476 ETHER_NEXT_MULTI(step, enm); 1477 } 1478 1479 ifp->if_flags &= ~IFF_ALLMULTI; 1480 goto setit; 1481 1482 allmulti: 1483 ifp->if_flags |= IFF_ALLMULTI; 1484 hashes[0] = hashes[1] = hashes[2] = hashes[3] = 0xffffffff; 1485 1486 setit: 1487 for (i = 0; i < 4; i++) 1488 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]); 1489 } 1490 1491 const int bge_swapbits[] = { 1492 0, 1493 BGE_MODECTL_BYTESWAP_DATA, 1494 BGE_MODECTL_WORDSWAP_DATA, 1495 BGE_MODECTL_BYTESWAP_NONFRAME, 1496 BGE_MODECTL_WORDSWAP_NONFRAME, 1497 1498 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA, 1499 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_BYTESWAP_NONFRAME, 1500 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_NONFRAME, 1501 1502 BGE_MODECTL_WORDSWAP_DATA|BGE_MODECTL_BYTESWAP_NONFRAME, 1503 BGE_MODECTL_WORDSWAP_DATA|BGE_MODECTL_WORDSWAP_NONFRAME, 1504 1505 BGE_MODECTL_BYTESWAP_NONFRAME|BGE_MODECTL_WORDSWAP_NONFRAME, 1506 1507 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA| 1508 BGE_MODECTL_BYTESWAP_NONFRAME, 1509 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA| 1510 BGE_MODECTL_WORDSWAP_NONFRAME, 1511 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_BYTESWAP_NONFRAME| 1512 BGE_MODECTL_WORDSWAP_NONFRAME, 1513 BGE_MODECTL_WORDSWAP_DATA|BGE_MODECTL_BYTESWAP_NONFRAME| 1514 BGE_MODECTL_WORDSWAP_NONFRAME, 1515 1516 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA| 1517 BGE_MODECTL_BYTESWAP_NONFRAME|BGE_MODECTL_WORDSWAP_NONFRAME, 1518 }; 1519 1520 int bge_swapindex = 0; 1521 1522 /* 1523 * Do endian, PCI and DMA initialization. Also check the on-board ROM 1524 * self-test results. 1525 */ 1526 static int 1527 bge_chipinit(struct bge_softc *sc) 1528 { 1529 int i; 1530 u_int32_t dma_rw_ctl; 1531 1532 1533 /* Set endianness before we access any non-PCI registers. */ 1534 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MISC_CTL, 1535 BGE_INIT); 1536 1537 /* Set power state to D0. */ 1538 bge_setpowerstate(sc, 0); 1539 1540 /* 1541 * Check the 'ROM failed' bit on the RX CPU to see if 1542 * self-tests passed. 1543 */ 1544 if (CSR_READ_4(sc, BGE_RXCPU_MODE) & BGE_RXCPUMODE_ROMFAIL) { 1545 aprint_error_dev(sc->bge_dev, 1546 "RX CPU self-diagnostics failed!\n"); 1547 return (ENODEV); 1548 } 1549 1550 /* Clear the MAC control register */ 1551 CSR_WRITE_4(sc, BGE_MAC_MODE, 0); 1552 1553 /* 1554 * Clear the MAC statistics block in the NIC's 1555 * internal memory. 1556 */ 1557 for (i = BGE_STATS_BLOCK; 1558 i < BGE_STATS_BLOCK_END + 1; i += sizeof(u_int32_t)) 1559 BGE_MEMWIN_WRITE(sc->sc_pc, sc->sc_pcitag, i, 0); 1560 1561 for (i = BGE_STATUS_BLOCK; 1562 i < BGE_STATUS_BLOCK_END + 1; i += sizeof(u_int32_t)) 1563 BGE_MEMWIN_WRITE(sc->sc_pc, sc->sc_pcitag, i, 0); 1564 1565 /* Set up the PCI DMA control register. */ 1566 dma_rw_ctl = BGE_PCI_READ_CMD | BGE_PCI_WRITE_CMD; 1567 if (sc->bge_flags & BGE_PCIE) { 1568 /* Read watermark not used, 128 bytes for write. */ 1569 DPRINTFN(4, ("(%s: PCI-Express DMA setting)\n", 1570 device_xname(sc->bge_dev))); 1571 dma_rw_ctl |= (0x3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT); 1572 } else if (sc->bge_flags & BGE_PCIX){ 1573 DPRINTFN(4, ("(:%s: PCI-X DMA setting)\n", 1574 device_xname(sc->bge_dev))); 1575 /* PCI-X bus */ 1576 dma_rw_ctl |= (0x3 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) | 1577 (0x3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT) | 1578 (0x0F); 1579 /* 1580 * 5703 and 5704 need ONEDMA_AT_ONCE as a workaround 1581 * for hardware bugs, which means we should also clear 1582 * the low-order MINDMA bits. In addition, the 5704 1583 * uses a different encoding of read/write watermarks. 1584 */ 1585 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) { 1586 dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD | 1587 /* should be 0x1f0000 */ 1588 (0x7 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) | 1589 (0x3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT); 1590 dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE; 1591 } 1592 else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5703) { 1593 dma_rw_ctl &= 0xfffffff0; 1594 dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE; 1595 } 1596 else if (BGE_IS_5714_FAMILY(sc)) { 1597 dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD; 1598 dma_rw_ctl &= ~BGE_PCIDMARWCTL_ONEDMA_ATONCE; /* XXX */ 1599 /* XXX magic values, Broadcom-supplied Linux driver */ 1600 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5780) 1601 dma_rw_ctl |= (1 << 20) | (1 << 18) | 1602 BGE_PCIDMARWCTL_ONEDMA_ATONCE; 1603 else 1604 dma_rw_ctl |= (1<<20) | (1<<18) | (1 << 15); 1605 } 1606 } else { 1607 /* Conventional PCI bus */ 1608 DPRINTFN(4, ("(%s: PCI 2.2 DMA setting)\n", 1609 device_xname(sc->bge_dev))); 1610 dma_rw_ctl = (0x7 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) | 1611 (0x7 << BGE_PCIDMARWCTL_WR_WAT_SHIFT); 1612 if (BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5705 && 1613 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5750) 1614 dma_rw_ctl |= 0x0F; 1615 } 1616 1617 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 1618 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5701) 1619 dma_rw_ctl |= BGE_PCIDMARWCTL_USE_MRM | 1620 BGE_PCIDMARWCTL_ASRT_ALL_BE; 1621 1622 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5703 || 1623 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) 1624 dma_rw_ctl &= ~BGE_PCIDMARWCTL_MINDMA; 1625 1626 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_DMA_RW_CTL, dma_rw_ctl); 1627 1628 /* 1629 * Set up general mode register. 1630 */ 1631 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS | 1632 BGE_MODECTL_MAC_ATTN_INTR | BGE_MODECTL_HOST_SEND_BDS | 1633 BGE_MODECTL_TX_NO_PHDR_CSUM | BGE_MODECTL_RX_NO_PHDR_CSUM); 1634 1635 /* 1636 * Disable memory write invalidate. Apparently it is not supported 1637 * properly by these devices. 1638 */ 1639 PCI_CLRBIT(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CMD, PCIM_CMD_MWIEN); 1640 1641 1642 #ifdef __brokenalpha__ 1643 /* 1644 * Must insure that we do not cross an 8K (bytes) boundary 1645 * for DMA reads. Our highest limit is 1K bytes. This is a 1646 * restriction on some ALPHA platforms with early revision 1647 * 21174 PCI chipsets, such as the AlphaPC 164lx 1648 */ 1649 PCI_SETBIT(sc, BGE_PCI_DMA_RW_CTL, BGE_PCI_READ_BNDRY_1024, 4); 1650 #endif 1651 1652 /* Set the timer prescaler (always 66MHz) */ 1653 CSR_WRITE_4(sc, BGE_MISC_CFG, 65 << 1/*BGE_32BITTIME_66MHZ*/); 1654 1655 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 1656 DELAY(40); /* XXX */ 1657 1658 /* Put PHY into ready state */ 1659 BGE_CLRBIT(sc, BGE_MISC_CFG, BGE_MISCCFG_EPHY_IDDQ); 1660 CSR_READ_4(sc, BGE_MISC_CFG); /* Flush */ 1661 DELAY(40); 1662 } 1663 1664 return (0); 1665 } 1666 1667 static int 1668 bge_blockinit(struct bge_softc *sc) 1669 { 1670 volatile struct bge_rcb *rcb; 1671 bus_size_t rcb_addr; 1672 int i; 1673 struct ifnet *ifp = &sc->ethercom.ec_if; 1674 bge_hostaddr taddr; 1675 u_int32_t val; 1676 1677 /* 1678 * Initialize the memory window pointer register so that 1679 * we can access the first 32K of internal NIC RAM. This will 1680 * allow us to set up the TX send ring RCBs and the RX return 1681 * ring RCBs, plus other things which live in NIC memory. 1682 */ 1683 1684 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_BASEADDR, 0); 1685 1686 /* Configure mbuf memory pool */ 1687 if (!(BGE_IS_5705_OR_BEYOND(sc))) { 1688 if (sc->bge_extram) { 1689 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, 1690 BGE_EXT_SSRAM); 1691 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) 1692 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000); 1693 else 1694 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000); 1695 } else { 1696 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, 1697 BGE_BUFFPOOL_1); 1698 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) 1699 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000); 1700 else 1701 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000); 1702 } 1703 1704 /* Configure DMA resource pool */ 1705 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_BASEADDR, 1706 BGE_DMA_DESCRIPTORS); 1707 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LEN, 0x2000); 1708 } 1709 1710 /* Configure mbuf pool watermarks */ 1711 #ifdef ORIG_WPAUL_VALUES 1712 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 24); 1713 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 24); 1714 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 48); 1715 #else 1716 1717 /* new broadcom docs strongly recommend these: */ 1718 if (!BGE_IS_5705_OR_BEYOND(sc)) { 1719 if (ifp->if_mtu > ETHER_MAX_LEN) { 1720 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x50); 1721 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x20); 1722 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60); 1723 } else { 1724 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 304); 1725 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 152); 1726 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 380); 1727 } 1728 } else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 1729 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0); 1730 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x04); 1731 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x10); 1732 } else { 1733 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0); 1734 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x10); 1735 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60); 1736 } 1737 #endif 1738 1739 /* Configure DMA resource watermarks */ 1740 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5); 1741 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10); 1742 1743 /* Enable buffer manager */ 1744 if (!BGE_IS_5705_OR_BEYOND(sc)) { 1745 CSR_WRITE_4(sc, BGE_BMAN_MODE, 1746 BGE_BMANMODE_ENABLE | BGE_BMANMODE_LOMBUF_ATTN); 1747 1748 /* Poll for buffer manager start indication */ 1749 for (i = 0; i < BGE_TIMEOUT; i++) { 1750 if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE) 1751 break; 1752 DELAY(10); 1753 } 1754 1755 if (i == BGE_TIMEOUT) { 1756 aprint_error_dev(sc->bge_dev, 1757 "buffer manager failed to start\n"); 1758 return (ENXIO); 1759 } 1760 } 1761 1762 /* Enable flow-through queues */ 1763 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 1764 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 1765 1766 /* Wait until queue initialization is complete */ 1767 for (i = 0; i < BGE_TIMEOUT; i++) { 1768 if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0) 1769 break; 1770 DELAY(10); 1771 } 1772 1773 if (i == BGE_TIMEOUT) { 1774 aprint_error_dev(sc->bge_dev, 1775 "flow-through queue init failed\n"); 1776 return (ENXIO); 1777 } 1778 1779 /* Initialize the standard RX ring control block */ 1780 rcb = &sc->bge_rdata->bge_info.bge_std_rx_rcb; 1781 bge_set_hostaddr(&rcb->bge_hostaddr, 1782 BGE_RING_DMA_ADDR(sc, bge_rx_std_ring)); 1783 if (BGE_IS_5705_OR_BEYOND(sc)) 1784 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(512, 0); 1785 else 1786 rcb->bge_maxlen_flags = 1787 BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 0); 1788 if (sc->bge_extram) 1789 rcb->bge_nicaddr = BGE_EXT_STD_RX_RINGS; 1790 else 1791 rcb->bge_nicaddr = BGE_STD_RX_RINGS; 1792 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcb->bge_hostaddr.bge_addr_hi); 1793 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcb->bge_hostaddr.bge_addr_lo); 1794 CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 1795 CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcb->bge_nicaddr); 1796 1797 if (BGE_IS_5705_OR_BEYOND(sc)) 1798 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT_5705; 1799 else 1800 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT; 1801 1802 /* 1803 * Initialize the jumbo RX ring control block 1804 * We set the 'ring disabled' bit in the flags 1805 * field until we're actually ready to start 1806 * using this ring (i.e. once we set the MTU 1807 * high enough to require it). 1808 */ 1809 if (BGE_IS_JUMBO_CAPABLE(sc)) { 1810 rcb = &sc->bge_rdata->bge_info.bge_jumbo_rx_rcb; 1811 bge_set_hostaddr(&rcb->bge_hostaddr, 1812 BGE_RING_DMA_ADDR(sc, bge_rx_jumbo_ring)); 1813 rcb->bge_maxlen_flags = 1814 BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 1815 BGE_RCB_FLAG_RING_DISABLED); 1816 if (sc->bge_extram) 1817 rcb->bge_nicaddr = BGE_EXT_JUMBO_RX_RINGS; 1818 else 1819 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS; 1820 1821 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI, 1822 rcb->bge_hostaddr.bge_addr_hi); 1823 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO, 1824 rcb->bge_hostaddr.bge_addr_lo); 1825 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, 1826 rcb->bge_maxlen_flags); 1827 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcb->bge_nicaddr); 1828 1829 /* Set up dummy disabled mini ring RCB */ 1830 rcb = &sc->bge_rdata->bge_info.bge_mini_rx_rcb; 1831 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0, 1832 BGE_RCB_FLAG_RING_DISABLED); 1833 CSR_WRITE_4(sc, BGE_RX_MINI_RCB_MAXLEN_FLAGS, 1834 rcb->bge_maxlen_flags); 1835 1836 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 1837 offsetof(struct bge_ring_data, bge_info), 1838 sizeof (struct bge_gib), 1839 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1840 } 1841 1842 /* 1843 * Set the BD ring replenish thresholds. The recommended 1844 * values are 1/8th the number of descriptors allocated to 1845 * each ring. 1846 */ 1847 i = BGE_STD_RX_RING_CNT / 8; 1848 1849 /* 1850 * Use a value of 8 for the following chips to workaround HW errata. 1851 * Some of these chips have been added based on empirical 1852 * evidence (they don't work unless this is done). 1853 */ 1854 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5750 || 1855 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5752 || 1856 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5755 || 1857 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5787 || 1858 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 1859 i = 8; 1860 1861 CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, i); 1862 CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH, BGE_JUMBO_RX_RING_CNT / 8); 1863 1864 /* 1865 * Disable all unused send rings by setting the 'ring disabled' 1866 * bit in the flags field of all the TX send ring control blocks. 1867 * These are located in NIC memory. 1868 */ 1869 rcb_addr = BGE_MEMWIN_START + BGE_SEND_RING_RCB; 1870 for (i = 0; i < BGE_TX_RINGS_EXTSSRAM_MAX; i++) { 1871 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 1872 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED)); 1873 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 0); 1874 rcb_addr += sizeof(struct bge_rcb); 1875 } 1876 1877 /* Configure TX RCB 0 (we use only the first ring) */ 1878 rcb_addr = BGE_MEMWIN_START + BGE_SEND_RING_RCB; 1879 bge_set_hostaddr(&taddr, BGE_RING_DMA_ADDR(sc, bge_tx_ring)); 1880 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi); 1881 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo); 1882 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 1883 BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT)); 1884 if (!(BGE_IS_5705_OR_BEYOND(sc))) 1885 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 1886 BGE_RCB_MAXLEN_FLAGS(BGE_TX_RING_CNT, 0)); 1887 1888 /* Disable all unused RX return rings */ 1889 rcb_addr = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB; 1890 for (i = 0; i < BGE_RX_RINGS_MAX; i++) { 1891 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_hi, 0); 1892 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_lo, 0); 1893 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 1894 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 1895 BGE_RCB_FLAG_RING_DISABLED)); 1896 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 0); 1897 bge_writembx(sc, BGE_MBX_RX_CONS0_LO + 1898 (i * (sizeof(u_int64_t))), 0); 1899 rcb_addr += sizeof(struct bge_rcb); 1900 } 1901 1902 /* Initialize RX ring indexes */ 1903 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, 0); 1904 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0); 1905 bge_writembx(sc, BGE_MBX_RX_MINI_PROD_LO, 0); 1906 1907 /* 1908 * Set up RX return ring 0 1909 * Note that the NIC address for RX return rings is 0x00000000. 1910 * The return rings live entirely within the host, so the 1911 * nicaddr field in the RCB isn't used. 1912 */ 1913 rcb_addr = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB; 1914 bge_set_hostaddr(&taddr, BGE_RING_DMA_ADDR(sc, bge_rx_return_ring)); 1915 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi); 1916 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo); 1917 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 0x00000000); 1918 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 1919 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 0)); 1920 1921 /* Set random backoff seed for TX */ 1922 CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF, 1923 CLLADDR(ifp->if_sadl)[0] + CLLADDR(ifp->if_sadl)[1] + 1924 CLLADDR(ifp->if_sadl)[2] + CLLADDR(ifp->if_sadl)[3] + 1925 CLLADDR(ifp->if_sadl)[4] + CLLADDR(ifp->if_sadl)[5] + 1926 BGE_TX_BACKOFF_SEED_MASK); 1927 1928 /* Set inter-packet gap */ 1929 CSR_WRITE_4(sc, BGE_TX_LENGTHS, 0x2620); 1930 1931 /* 1932 * Specify which ring to use for packets that don't match 1933 * any RX rules. 1934 */ 1935 CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08); 1936 1937 /* 1938 * Configure number of RX lists. One interrupt distribution 1939 * list, sixteen active lists, one bad frames class. 1940 */ 1941 CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181); 1942 1943 /* Inialize RX list placement stats mask. */ 1944 CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF); 1945 CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1); 1946 1947 /* Disable host coalescing until we get it set up */ 1948 CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000); 1949 1950 /* Poll to make sure it's shut down. */ 1951 for (i = 0; i < BGE_TIMEOUT; i++) { 1952 if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE)) 1953 break; 1954 DELAY(10); 1955 } 1956 1957 if (i == BGE_TIMEOUT) { 1958 aprint_error_dev(sc->bge_dev, 1959 "host coalescing engine failed to idle\n"); 1960 return (ENXIO); 1961 } 1962 1963 /* Set up host coalescing defaults */ 1964 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bge_rx_coal_ticks); 1965 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bge_tx_coal_ticks); 1966 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bge_rx_max_coal_bds); 1967 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bge_tx_max_coal_bds); 1968 if (!(BGE_IS_5705_OR_BEYOND(sc))) { 1969 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT, 0); 1970 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT, 0); 1971 } 1972 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 0); 1973 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 0); 1974 1975 /* Set up address of statistics block */ 1976 if (!(BGE_IS_5705_OR_BEYOND(sc))) { 1977 bge_set_hostaddr(&taddr, 1978 BGE_RING_DMA_ADDR(sc, bge_info.bge_stats)); 1979 CSR_WRITE_4(sc, BGE_HCC_STATS_TICKS, sc->bge_stat_ticks); 1980 CSR_WRITE_4(sc, BGE_HCC_STATS_BASEADDR, BGE_STATS_BLOCK); 1981 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_HI, taddr.bge_addr_hi); 1982 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_LO, taddr.bge_addr_lo); 1983 } 1984 1985 /* Set up address of status block */ 1986 bge_set_hostaddr(&taddr, BGE_RING_DMA_ADDR(sc, bge_status_block)); 1987 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_BASEADDR, BGE_STATUS_BLOCK); 1988 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI, taddr.bge_addr_hi); 1989 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO, taddr.bge_addr_lo); 1990 sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx = 0; 1991 sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx = 0; 1992 1993 /* Turn on host coalescing state machine */ 1994 CSR_WRITE_4(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE); 1995 1996 /* Turn on RX BD completion state machine and enable attentions */ 1997 CSR_WRITE_4(sc, BGE_RBDC_MODE, 1998 BGE_RBDCMODE_ENABLE | BGE_RBDCMODE_ATTN); 1999 2000 /* Turn on RX list placement state machine */ 2001 CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 2002 2003 /* Turn on RX list selector state machine. */ 2004 if (!(BGE_IS_5705_OR_BEYOND(sc))) 2005 CSR_WRITE_4(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 2006 2007 val = BGE_MACMODE_TXDMA_ENB | BGE_MACMODE_RXDMA_ENB | 2008 BGE_MACMODE_RX_STATS_CLEAR | BGE_MACMODE_TX_STATS_CLEAR | 2009 BGE_MACMODE_RX_STATS_ENB | BGE_MACMODE_TX_STATS_ENB | 2010 BGE_MACMODE_FRMHDR_DMA_ENB; 2011 2012 if (sc->bge_flags & BGE_PHY_FIBER_TBI) 2013 val |= BGE_PORTMODE_TBI; 2014 else if (sc->bge_flags & BGE_PHY_FIBER_MII) 2015 val |= BGE_PORTMODE_GMII; 2016 else 2017 val |= BGE_PORTMODE_MII; 2018 2019 /* Turn on DMA, clear stats */ 2020 CSR_WRITE_4(sc, BGE_MAC_MODE, val); 2021 2022 2023 /* Set misc. local control, enable interrupts on attentions */ 2024 sc->bge_local_ctrl_reg = BGE_MLC_INTR_ONATTN | BGE_MLC_AUTO_EEPROM; 2025 2026 #ifdef notdef 2027 /* Assert GPIO pins for PHY reset */ 2028 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUT0| 2029 BGE_MLC_MISCIO_OUT1|BGE_MLC_MISCIO_OUT2); 2030 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUTEN0| 2031 BGE_MLC_MISCIO_OUTEN1|BGE_MLC_MISCIO_OUTEN2); 2032 #endif 2033 2034 #if defined(not_quite_yet) 2035 /* Linux driver enables enable gpio pin #1 on 5700s */ 2036 if (sc->bge_chipid == BGE_CHIPID_BCM5700) { 2037 sc->bge_local_ctrl_reg |= 2038 (BGE_MLC_MISCIO_OUT1|BGE_MLC_MISCIO_OUTEN1); 2039 } 2040 #endif 2041 CSR_WRITE_4(sc, BGE_MISC_LOCAL_CTL, sc->bge_local_ctrl_reg); 2042 2043 /* Turn on DMA completion state machine */ 2044 if (!(BGE_IS_5705_OR_BEYOND(sc))) 2045 CSR_WRITE_4(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 2046 2047 /* Turn on write DMA state machine */ 2048 { 2049 uint32_t bge_wdma_mode = 2050 BGE_WDMAMODE_ENABLE|BGE_WDMAMODE_ALL_ATTNS; 2051 2052 /* Enable host coalescing bug fix; see Linux tg3.c */ 2053 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5755 || 2054 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5787) 2055 bge_wdma_mode |= (1 << 29); 2056 2057 CSR_WRITE_4(sc, BGE_WDMA_MODE, bge_wdma_mode); 2058 } 2059 2060 /* Turn on read DMA state machine */ 2061 { 2062 uint32_t dma_read_modebits; 2063 2064 dma_read_modebits = 2065 BGE_RDMAMODE_ENABLE | BGE_RDMAMODE_ALL_ATTNS; 2066 2067 if ((sc->bge_flags & BGE_PCIE) && 0) { 2068 dma_read_modebits |= BGE_RDMA_MODE_FIFO_LONG_BURST; 2069 } else if (BGE_IS_5705_OR_BEYOND(sc)) { 2070 dma_read_modebits |= BGE_RDMA_MODE_FIFO_SIZE_128; 2071 } 2072 2073 /* XXX broadcom-supplied linux driver; undocumented */ 2074 if (BGE_IS_5750_OR_BEYOND(sc)) { 2075 /* 2076 * XXX: magic values. 2077 * From Broadcom-supplied Linux driver; apparently 2078 * required to workaround a DMA bug affecting TSO 2079 * on bcm575x/bcm5721? 2080 */ 2081 dma_read_modebits |= (1 << 27); 2082 } 2083 CSR_WRITE_4(sc, BGE_RDMA_MODE, dma_read_modebits); 2084 } 2085 2086 /* Turn on RX data completion state machine */ 2087 CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 2088 2089 /* Turn on RX BD initiator state machine */ 2090 CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 2091 2092 /* Turn on RX data and RX BD initiator state machine */ 2093 CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE); 2094 2095 /* Turn on Mbuf cluster free state machine */ 2096 if (!(BGE_IS_5705_OR_BEYOND(sc))) 2097 CSR_WRITE_4(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 2098 2099 /* Turn on send BD completion state machine */ 2100 CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 2101 2102 /* Turn on send data completion state machine */ 2103 CSR_WRITE_4(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE); 2104 2105 /* Turn on send data initiator state machine */ 2106 if (BGE_IS_5750_OR_BEYOND(sc)) { 2107 /* XXX: magic value from Linux driver */ 2108 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE | 0x08); 2109 } else { 2110 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 2111 } 2112 2113 /* Turn on send BD initiator state machine */ 2114 CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 2115 2116 /* Turn on send BD selector state machine */ 2117 CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 2118 2119 CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF); 2120 CSR_WRITE_4(sc, BGE_SDI_STATS_CTL, 2121 BGE_SDISTATSCTL_ENABLE | BGE_SDISTATSCTL_FASTER); 2122 2123 /* ack/clear link change events */ 2124 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED | 2125 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE | 2126 BGE_MACSTAT_CFG_CHANGED); 2127 CSR_WRITE_4(sc, BGE_MI_STS, 0); 2128 2129 /* Enable PHY auto polling (for MII/GMII only) */ 2130 if (sc->bge_flags & BGE_PHY_FIBER_TBI) { 2131 CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK); 2132 } else { 2133 BGE_STS_SETBIT(sc, BGE_STS_AUTOPOLL); 2134 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL | (10 << 16)); 2135 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700) 2136 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, 2137 BGE_EVTENB_MI_INTERRUPT); 2138 } 2139 2140 /* 2141 * Clear any pending link state attention. 2142 * Otherwise some link state change events may be lost until attention 2143 * is cleared by bge_intr() -> bge_link_upd() sequence. 2144 * It's not necessary on newer BCM chips - perhaps enabling link 2145 * state change attentions implies clearing pending attention. 2146 */ 2147 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED | 2148 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE | 2149 BGE_MACSTAT_LINK_CHANGED); 2150 2151 /* Enable link state change attentions. */ 2152 BGE_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED); 2153 2154 return (0); 2155 } 2156 2157 static const struct bge_revision * 2158 bge_lookup_rev(uint32_t chipid) 2159 { 2160 const struct bge_revision *br; 2161 2162 for (br = bge_revisions; br->br_name != NULL; br++) { 2163 if (br->br_chipid == chipid) 2164 return (br); 2165 } 2166 2167 for (br = bge_majorrevs; br->br_name != NULL; br++) { 2168 if (br->br_chipid == BGE_ASICREV(chipid)) 2169 return (br); 2170 } 2171 2172 return (NULL); 2173 } 2174 2175 static const struct bge_product * 2176 bge_lookup(const struct pci_attach_args *pa) 2177 { 2178 const struct bge_product *bp; 2179 2180 for (bp = bge_products; bp->bp_name != NULL; bp++) { 2181 if (PCI_VENDOR(pa->pa_id) == bp->bp_vendor && 2182 PCI_PRODUCT(pa->pa_id) == bp->bp_product) 2183 return (bp); 2184 } 2185 2186 return (NULL); 2187 } 2188 2189 static int 2190 bge_setpowerstate(struct bge_softc *sc, int powerlevel) 2191 { 2192 #ifdef NOTYET 2193 u_int32_t pm_ctl = 0; 2194 2195 /* XXX FIXME: make sure indirect accesses enabled? */ 2196 pm_ctl = pci_conf_read(sc->bge_dev, BGE_PCI_MISC_CTL, 4); 2197 pm_ctl |= BGE_PCIMISCCTL_INDIRECT_ACCESS; 2198 pci_write_config(sc->bge_dev, BGE_PCI_MISC_CTL, pm_ctl, 4); 2199 2200 /* clear the PME_assert bit and power state bits, enable PME */ 2201 pm_ctl = pci_conf_read(sc->bge_dev, BGE_PCI_PWRMGMT_CMD, 2); 2202 pm_ctl &= ~PCIM_PSTAT_DMASK; 2203 pm_ctl |= (1 << 8); 2204 2205 if (powerlevel == 0) { 2206 pm_ctl |= PCIM_PSTAT_D0; 2207 pci_write_config(sc->bge_dev, BGE_PCI_PWRMGMT_CMD, 2208 pm_ctl, 2); 2209 DELAY(10000); 2210 CSR_WRITE_4(sc, BGE_MISC_LOCAL_CTL, sc->bge_local_ctrl_reg); 2211 DELAY(10000); 2212 2213 #ifdef NOTYET 2214 /* XXX FIXME: write 0x02 to phy aux_Ctrl reg */ 2215 bge_miibus_writereg(sc->bge_dev, 1, 0x18, 0x02); 2216 #endif 2217 DELAY(40); DELAY(40); DELAY(40); 2218 DELAY(10000); /* above not quite adequate on 5700 */ 2219 return 0; 2220 } 2221 2222 2223 /* 2224 * Entering ACPI power states D1-D3 is achieved by wiggling 2225 * GMII gpio pins. Example code assumes all hardware vendors 2226 * followed Broadom's sample pcb layout. Until we verify that 2227 * for all supported OEM cards, states D1-D3 are unsupported. 2228 */ 2229 aprint_error_dev(sc->bge_dev, 2230 "power state %d unimplemented; check GPIO pins\n", 2231 powerlevel); 2232 #endif 2233 return EOPNOTSUPP; 2234 } 2235 2236 2237 /* 2238 * Probe for a Broadcom chip. Check the PCI vendor and device IDs 2239 * against our list and return its name if we find a match. Note 2240 * that since the Broadcom controller contains VPD support, we 2241 * can get the device name string from the controller itself instead 2242 * of the compiled-in string. This is a little slow, but it guarantees 2243 * we'll always announce the right product name. 2244 */ 2245 static int 2246 bge_probe(device_t parent, cfdata_t match, void *aux) 2247 { 2248 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 2249 2250 if (bge_lookup(pa) != NULL) 2251 return (1); 2252 2253 return (0); 2254 } 2255 2256 static void 2257 bge_attach(device_t parent, device_t self, void *aux) 2258 { 2259 struct bge_softc *sc = device_private(self); 2260 struct pci_attach_args *pa = aux; 2261 prop_dictionary_t dict; 2262 const struct bge_product *bp; 2263 const struct bge_revision *br; 2264 pci_chipset_tag_t pc; 2265 pci_intr_handle_t ih; 2266 const char *intrstr = NULL; 2267 bus_dma_segment_t seg; 2268 int rseg; 2269 u_int32_t hwcfg = 0; 2270 u_int32_t command; 2271 struct ifnet *ifp; 2272 u_int32_t misccfg; 2273 void * kva; 2274 u_char eaddr[ETHER_ADDR_LEN]; 2275 pcireg_t memtype; 2276 bus_addr_t memaddr; 2277 bus_size_t memsize; 2278 u_int32_t pm_ctl; 2279 2280 bp = bge_lookup(pa); 2281 KASSERT(bp != NULL); 2282 2283 sc->sc_pc = pa->pa_pc; 2284 sc->sc_pcitag = pa->pa_tag; 2285 sc->bge_dev = self; 2286 2287 aprint_naive(": Ethernet controller\n"); 2288 aprint_normal(": %s\n", bp->bp_name); 2289 2290 /* 2291 * Map control/status registers. 2292 */ 2293 DPRINTFN(5, ("Map control/status regs\n")); 2294 pc = sc->sc_pc; 2295 command = pci_conf_read(pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG); 2296 command |= PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_MASTER_ENABLE; 2297 pci_conf_write(pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG, command); 2298 command = pci_conf_read(pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG); 2299 2300 if (!(command & PCI_COMMAND_MEM_ENABLE)) { 2301 aprint_error_dev(sc->bge_dev, 2302 "failed to enable memory mapping!\n"); 2303 return; 2304 } 2305 2306 DPRINTFN(5, ("pci_mem_find\n")); 2307 memtype = pci_mapreg_type(sc->sc_pc, sc->sc_pcitag, BGE_PCI_BAR0); 2308 switch (memtype) { 2309 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 2310 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 2311 if (pci_mapreg_map(pa, BGE_PCI_BAR0, 2312 memtype, 0, &sc->bge_btag, &sc->bge_bhandle, 2313 &memaddr, &memsize) == 0) 2314 break; 2315 default: 2316 aprint_error_dev(sc->bge_dev, "can't find mem space\n"); 2317 return; 2318 } 2319 2320 DPRINTFN(5, ("pci_intr_map\n")); 2321 if (pci_intr_map(pa, &ih)) { 2322 aprint_error_dev(sc->bge_dev, "couldn't map interrupt\n"); 2323 return; 2324 } 2325 2326 DPRINTFN(5, ("pci_intr_string\n")); 2327 intrstr = pci_intr_string(pc, ih); 2328 2329 DPRINTFN(5, ("pci_intr_establish\n")); 2330 sc->bge_intrhand = pci_intr_establish(pc, ih, IPL_NET, bge_intr, sc); 2331 2332 if (sc->bge_intrhand == NULL) { 2333 aprint_error_dev(sc->bge_dev, 2334 "couldn't establish interrupt%s%s\n", 2335 intrstr ? " at " : "", intrstr ? intrstr : ""); 2336 return; 2337 } 2338 aprint_normal_dev(sc->bge_dev, "interrupting at %s\n", intrstr); 2339 2340 /* 2341 * Kludge for 5700 Bx bug: a hardware bug (PCIX byte enable?) 2342 * can clobber the chip's PCI config-space power control registers, 2343 * leaving the card in D3 powersave state. 2344 * We do not have memory-mapped registers in this state, 2345 * so force device into D0 state before starting initialization. 2346 */ 2347 pm_ctl = pci_conf_read(pc, sc->sc_pcitag, BGE_PCI_PWRMGMT_CMD); 2348 pm_ctl &= ~(PCI_PWR_D0|PCI_PWR_D1|PCI_PWR_D2|PCI_PWR_D3); 2349 pm_ctl |= (1 << 8) | PCI_PWR_D0 ; /* D0 state */ 2350 pci_conf_write(pc, sc->sc_pcitag, BGE_PCI_PWRMGMT_CMD, pm_ctl); 2351 DELAY(1000); /* 27 usec is allegedly sufficent */ 2352 2353 /* 2354 * Save ASIC rev. 2355 */ 2356 sc->bge_chipid = 2357 pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MISC_CTL) & 2358 BGE_PCIMISCCTL_ASICREV; 2359 2360 /* 2361 * Detect PCI-Express devices 2362 * XXX: guessed from Linux/FreeBSD; no documentation 2363 */ 2364 if (pci_get_capability(sc->sc_pc, sc->sc_pcitag, PCI_CAP_PCIEXPRESS, 2365 NULL, NULL) != 0) 2366 sc->bge_flags |= BGE_PCIE; 2367 2368 /* 2369 * PCI-X check. 2370 */ 2371 if ((pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_PCISTATE) & 2372 BGE_PCISTATE_PCI_BUSMODE) == 0) 2373 sc->bge_flags |= BGE_PCIX; 2374 2375 if (sc->bge_chipid == BGE_CHIPID_BCM5701_A0 || 2376 sc->bge_chipid == BGE_CHIPID_BCM5701_B0) 2377 sc->bge_flags |= BGE_PHY_CRC_BUG; 2378 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5703_AX || 2379 BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5704_AX) 2380 sc->bge_flags |= BGE_PHY_ADC_BUG; 2381 if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0) 2382 sc->bge_flags |= BGE_PHY_5704_A0_BUG; 2383 2384 if (BGE_IS_5705_OR_BEYOND(sc)) { 2385 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5755 || 2386 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5787) { 2387 if (PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_BROADCOM_BCM5722 && 2388 PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_BROADCOM_BCM5756) 2389 sc->bge_flags |= BGE_PHY_JITTER_BUG; 2390 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5755M) 2391 sc->bge_flags |= BGE_PHY_ADJUST_TRIM; 2392 } else if (BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5906) 2393 sc->bge_flags |= BGE_PHY_BER_BUG; 2394 } 2395 2396 /* Try to reset the chip. */ 2397 DPRINTFN(5, ("bge_reset\n")); 2398 bge_reset(sc); 2399 2400 if (bge_chipinit(sc)) { 2401 aprint_error_dev(sc->bge_dev, "chip initialization failed\n"); 2402 bge_release_resources(sc); 2403 return; 2404 } 2405 2406 /* 2407 * Get station address from the EEPROM. 2408 */ 2409 if (bge_get_eaddr(sc, eaddr)) { 2410 aprint_error_dev(sc->bge_dev, 2411 "failed to reade station address\n"); 2412 bge_release_resources(sc); 2413 return; 2414 } 2415 2416 br = bge_lookup_rev(sc->bge_chipid); 2417 2418 if (br == NULL) { 2419 aprint_normal_dev(sc->bge_dev, "unknown ASIC (0x%04x)", 2420 sc->bge_chipid >> 16); 2421 } else { 2422 aprint_normal_dev(sc->bge_dev, "ASIC %s (0x%04x)", 2423 br->br_name, sc->bge_chipid >> 16); 2424 } 2425 aprint_normal(", Ethernet address %s\n", ether_sprintf(eaddr)); 2426 2427 /* Allocate the general information block and ring buffers. */ 2428 if (pci_dma64_available(pa)) 2429 sc->bge_dmatag = pa->pa_dmat64; 2430 else 2431 sc->bge_dmatag = pa->pa_dmat; 2432 DPRINTFN(5, ("bus_dmamem_alloc\n")); 2433 if (bus_dmamem_alloc(sc->bge_dmatag, sizeof(struct bge_ring_data), 2434 PAGE_SIZE, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 2435 aprint_error_dev(sc->bge_dev, "can't alloc rx buffers\n"); 2436 return; 2437 } 2438 DPRINTFN(5, ("bus_dmamem_map\n")); 2439 if (bus_dmamem_map(sc->bge_dmatag, &seg, rseg, 2440 sizeof(struct bge_ring_data), &kva, 2441 BUS_DMA_NOWAIT)) { 2442 aprint_error_dev(sc->bge_dev, 2443 "can't map DMA buffers (%zu bytes)\n", 2444 sizeof(struct bge_ring_data)); 2445 bus_dmamem_free(sc->bge_dmatag, &seg, rseg); 2446 return; 2447 } 2448 DPRINTFN(5, ("bus_dmamem_create\n")); 2449 if (bus_dmamap_create(sc->bge_dmatag, sizeof(struct bge_ring_data), 1, 2450 sizeof(struct bge_ring_data), 0, 2451 BUS_DMA_NOWAIT, &sc->bge_ring_map)) { 2452 aprint_error_dev(sc->bge_dev, "can't create DMA map\n"); 2453 bus_dmamem_unmap(sc->bge_dmatag, kva, 2454 sizeof(struct bge_ring_data)); 2455 bus_dmamem_free(sc->bge_dmatag, &seg, rseg); 2456 return; 2457 } 2458 DPRINTFN(5, ("bus_dmamem_load\n")); 2459 if (bus_dmamap_load(sc->bge_dmatag, sc->bge_ring_map, kva, 2460 sizeof(struct bge_ring_data), NULL, 2461 BUS_DMA_NOWAIT)) { 2462 bus_dmamap_destroy(sc->bge_dmatag, sc->bge_ring_map); 2463 bus_dmamem_unmap(sc->bge_dmatag, kva, 2464 sizeof(struct bge_ring_data)); 2465 bus_dmamem_free(sc->bge_dmatag, &seg, rseg); 2466 return; 2467 } 2468 2469 DPRINTFN(5, ("bzero\n")); 2470 sc->bge_rdata = (struct bge_ring_data *)kva; 2471 2472 memset(sc->bge_rdata, 0, sizeof(struct bge_ring_data)); 2473 2474 /* Try to allocate memory for jumbo buffers. */ 2475 if (BGE_IS_JUMBO_CAPABLE(sc)) { 2476 if (bge_alloc_jumbo_mem(sc)) { 2477 aprint_error_dev(sc->bge_dev, 2478 "jumbo buffer allocation failed\n"); 2479 } else 2480 sc->ethercom.ec_capabilities |= ETHERCAP_JUMBO_MTU; 2481 } 2482 2483 /* Set default tuneable values. */ 2484 sc->bge_stat_ticks = BGE_TICKS_PER_SEC; 2485 sc->bge_rx_coal_ticks = 150; 2486 sc->bge_rx_max_coal_bds = 64; 2487 #ifdef ORIG_WPAUL_VALUES 2488 sc->bge_tx_coal_ticks = 150; 2489 sc->bge_tx_max_coal_bds = 128; 2490 #else 2491 sc->bge_tx_coal_ticks = 300; 2492 sc->bge_tx_max_coal_bds = 400; 2493 #endif 2494 if (BGE_IS_5705_OR_BEYOND(sc)) { 2495 sc->bge_tx_coal_ticks = (12 * 5); 2496 sc->bge_tx_max_coal_bds = (12 * 5); 2497 aprint_verbose_dev(sc->bge_dev, 2498 "setting short Tx thresholds\n"); 2499 } 2500 2501 /* Set up ifnet structure */ 2502 ifp = &sc->ethercom.ec_if; 2503 ifp->if_softc = sc; 2504 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 2505 ifp->if_ioctl = bge_ioctl; 2506 ifp->if_stop = bge_stop; 2507 ifp->if_start = bge_start; 2508 ifp->if_init = bge_init; 2509 ifp->if_watchdog = bge_watchdog; 2510 IFQ_SET_MAXLEN(&ifp->if_snd, max(BGE_TX_RING_CNT - 1, IFQ_MAXLEN)); 2511 IFQ_SET_READY(&ifp->if_snd); 2512 DPRINTFN(5, ("strcpy if_xname\n")); 2513 strcpy(ifp->if_xname, device_xname(sc->bge_dev)); 2514 2515 if (sc->bge_chipid != BGE_CHIPID_BCM5700_B0) 2516 sc->ethercom.ec_if.if_capabilities |= 2517 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 2518 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 2519 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 2520 sc->ethercom.ec_capabilities |= 2521 ETHERCAP_VLAN_HWTAGGING | ETHERCAP_VLAN_MTU; 2522 2523 if (sc->bge_flags & BGE_PCIE) 2524 sc->ethercom.ec_if.if_capabilities |= IFCAP_TSOv4; 2525 2526 /* 2527 * Do MII setup. 2528 */ 2529 DPRINTFN(5, ("mii setup\n")); 2530 sc->bge_mii.mii_ifp = ifp; 2531 sc->bge_mii.mii_readreg = bge_miibus_readreg; 2532 sc->bge_mii.mii_writereg = bge_miibus_writereg; 2533 sc->bge_mii.mii_statchg = bge_miibus_statchg; 2534 2535 /* 2536 * Figure out what sort of media we have by checking the 2537 * hardware config word in the first 32k of NIC internal memory, 2538 * or fall back to the config word in the EEPROM. Note: on some BCM5700 2539 * cards, this value appears to be unset. If that's the 2540 * case, we have to rely on identifying the NIC by its PCI 2541 * subsystem ID, as we do below for the SysKonnect SK-9D41. 2542 */ 2543 if (bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_SIG) == BGE_MAGIC_NUMBER) { 2544 hwcfg = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_NICCFG); 2545 } else { 2546 bge_read_eeprom(sc, (void *)&hwcfg, 2547 BGE_EE_HWCFG_OFFSET, sizeof(hwcfg)); 2548 hwcfg = be32toh(hwcfg); 2549 } 2550 /* The SysKonnect SK-9D41 is a 1000baseSX card. */ 2551 if (PCI_PRODUCT(pa->pa_id) == SK_SUBSYSID_9D41 || 2552 (hwcfg & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER) { 2553 if (BGE_IS_5714_FAMILY(sc)) 2554 sc->bge_flags |= BGE_PHY_FIBER_MII; 2555 else 2556 sc->bge_flags |= BGE_PHY_FIBER_TBI; 2557 } 2558 2559 /* set phyflags before mii_attach() */ 2560 dict = device_properties(self); 2561 prop_dictionary_set_uint32(dict, "phyflags", sc->bge_flags); 2562 2563 if (sc->bge_flags & BGE_PHY_FIBER_TBI) { 2564 ifmedia_init(&sc->bge_ifmedia, IFM_IMASK, bge_ifmedia_upd, 2565 bge_ifmedia_sts); 2566 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL); 2567 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_1000_SX|IFM_FDX, 2568 0, NULL); 2569 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL); 2570 ifmedia_set(&sc->bge_ifmedia, IFM_ETHER|IFM_AUTO); 2571 /* Pretend the user requested this setting */ 2572 sc->bge_ifmedia.ifm_media = sc->bge_ifmedia.ifm_cur->ifm_media; 2573 } else { 2574 /* 2575 * Do transceiver setup. 2576 */ 2577 ifmedia_init(&sc->bge_mii.mii_media, 0, bge_ifmedia_upd, 2578 bge_ifmedia_sts); 2579 mii_attach(sc->bge_dev, &sc->bge_mii, 0xffffffff, 2580 MII_PHY_ANY, MII_OFFSET_ANY, 2581 MIIF_FORCEANEG|MIIF_DOPAUSE); 2582 2583 if (LIST_EMPTY(&sc->bge_mii.mii_phys)) { 2584 aprint_error_dev(sc->bge_dev, "no PHY found!\n"); 2585 ifmedia_add(&sc->bge_mii.mii_media, 2586 IFM_ETHER|IFM_MANUAL, 0, NULL); 2587 ifmedia_set(&sc->bge_mii.mii_media, 2588 IFM_ETHER|IFM_MANUAL); 2589 } else 2590 ifmedia_set(&sc->bge_mii.mii_media, 2591 IFM_ETHER|IFM_AUTO); 2592 } 2593 2594 /* 2595 * When using the BCM5701 in PCI-X mode, data corruption has 2596 * been observed in the first few bytes of some received packets. 2597 * Aligning the packet buffer in memory eliminates the corruption. 2598 * Unfortunately, this misaligns the packet payloads. On platforms 2599 * which do not support unaligned accesses, we will realign the 2600 * payloads by copying the received packets. 2601 */ 2602 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5701 && 2603 sc->bge_flags & BGE_PCIX) 2604 sc->bge_flags |= BGE_RX_ALIGNBUG; 2605 2606 misccfg = CSR_READ_4(sc, BGE_MISC_CFG); 2607 misccfg &= BGE_MISCCFG_BOARD_ID_MASK; 2608 2609 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5705 && 2610 (misccfg == BGE_MISCCFG_BOARD_ID_5788 || 2611 misccfg == BGE_MISCCFG_BOARD_ID_5788M)) 2612 sc->bge_flags |= BGE_IS_5788; 2613 2614 /* 2615 * Call MI attach routine. 2616 */ 2617 DPRINTFN(5, ("if_attach\n")); 2618 if_attach(ifp); 2619 DPRINTFN(5, ("ether_ifattach\n")); 2620 ether_ifattach(ifp, eaddr); 2621 #if NRND > 0 2622 rnd_attach_source(&sc->rnd_source, device_xname(sc->bge_dev), 2623 RND_TYPE_NET, 0); 2624 #endif 2625 #ifdef BGE_EVENT_COUNTERS 2626 /* 2627 * Attach event counters. 2628 */ 2629 evcnt_attach_dynamic(&sc->bge_ev_intr, EVCNT_TYPE_INTR, 2630 NULL, device_xname(sc->bge_dev), "intr"); 2631 evcnt_attach_dynamic(&sc->bge_ev_tx_xoff, EVCNT_TYPE_MISC, 2632 NULL, device_xname(sc->bge_dev), "tx_xoff"); 2633 evcnt_attach_dynamic(&sc->bge_ev_tx_xon, EVCNT_TYPE_MISC, 2634 NULL, device_xname(sc->bge_dev), "tx_xon"); 2635 evcnt_attach_dynamic(&sc->bge_ev_rx_xoff, EVCNT_TYPE_MISC, 2636 NULL, device_xname(sc->bge_dev), "rx_xoff"); 2637 evcnt_attach_dynamic(&sc->bge_ev_rx_xon, EVCNT_TYPE_MISC, 2638 NULL, device_xname(sc->bge_dev), "rx_xon"); 2639 evcnt_attach_dynamic(&sc->bge_ev_rx_macctl, EVCNT_TYPE_MISC, 2640 NULL, device_xname(sc->bge_dev), "rx_macctl"); 2641 evcnt_attach_dynamic(&sc->bge_ev_xoffentered, EVCNT_TYPE_MISC, 2642 NULL, device_xname(sc->bge_dev), "xoffentered"); 2643 #endif /* BGE_EVENT_COUNTERS */ 2644 DPRINTFN(5, ("callout_init\n")); 2645 callout_init(&sc->bge_timeout, 0); 2646 2647 if (pmf_device_register(self, NULL, NULL)) 2648 pmf_class_network_register(self, ifp); 2649 else 2650 aprint_error_dev(self, "couldn't establish power handler\n"); 2651 } 2652 2653 static void 2654 bge_release_resources(struct bge_softc *sc) 2655 { 2656 if (sc->bge_vpd_prodname != NULL) 2657 free(sc->bge_vpd_prodname, M_DEVBUF); 2658 2659 if (sc->bge_vpd_readonly != NULL) 2660 free(sc->bge_vpd_readonly, M_DEVBUF); 2661 } 2662 2663 static void 2664 bge_reset(struct bge_softc *sc) 2665 { 2666 u_int32_t cachesize, command, pcistate, new_pcistate; 2667 int i, val; 2668 void (*write_op)(struct bge_softc *, int, int); 2669 2670 if (BGE_IS_5750_OR_BEYOND(sc) && !BGE_IS_5714_FAMILY(sc) && 2671 (BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5906)) { 2672 if (sc->bge_flags & BGE_PCIE) { 2673 write_op = bge_writemem_direct; 2674 } else { 2675 write_op = bge_writemem_ind; 2676 } 2677 } else { 2678 write_op = bge_writereg_ind; 2679 } 2680 2681 2682 /* Save some important PCI state. */ 2683 cachesize = pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CACHESZ); 2684 command = pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CMD); 2685 pcistate = pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_PCISTATE); 2686 2687 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MISC_CTL, 2688 BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR| 2689 BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_PCISTATE_RW); 2690 2691 /* Disable fastboot on controllers that support it. */ 2692 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5752 || 2693 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5755 || 2694 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5787) 2695 CSR_WRITE_4(sc, BGE_FASTBOOT_PC, 0); 2696 2697 val = BGE_MISCCFG_RESET_CORE_CLOCKS | (65<<1); 2698 /* 2699 * XXX: from FreeBSD/Linux; no documentation 2700 */ 2701 if (sc->bge_flags & BGE_PCIE) { 2702 if (CSR_READ_4(sc, BGE_PCIE_CTL1) == 0x60) 2703 /* PCI Express 1.0 system */ 2704 CSR_WRITE_4(sc, BGE_PCIE_CTL1, 0x20); 2705 if (sc->bge_chipid != BGE_CHIPID_BCM5750_A0) { 2706 /* 2707 * Prevent PCI Express link training 2708 * during global reset. 2709 */ 2710 CSR_WRITE_4(sc, BGE_MISC_CFG, 1 << 29); 2711 val |= (1<<29); 2712 } 2713 } 2714 2715 /* 2716 * Set GPHY Power Down Override to leave GPHY 2717 * powered up in D0 uninitialized. 2718 */ 2719 if (BGE_IS_5705_OR_BEYOND(sc)) 2720 val |= BGE_MISCCFG_KEEP_GPHY_POWER; 2721 2722 /* Issue global reset */ 2723 write_op(sc, BGE_MISC_CFG, val); 2724 2725 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 2726 i = CSR_READ_4(sc, BGE_VCPU_STATUS); 2727 CSR_WRITE_4(sc, BGE_VCPU_STATUS, 2728 i | BGE_VCPU_STATUS_DRV_RESET); 2729 i = CSR_READ_4(sc, BGE_VCPU_EXT_CTRL); 2730 CSR_WRITE_4(sc, BGE_VCPU_EXT_CTRL, 2731 i & ~BGE_VCPU_EXT_CTRL_HALT_CPU); 2732 } 2733 2734 DELAY(1000); 2735 2736 /* 2737 * XXX: from FreeBSD/Linux; no documentation 2738 */ 2739 if (sc->bge_flags & BGE_PCIE) { 2740 if (sc->bge_chipid == BGE_CHIPID_BCM5750_A0) { 2741 pcireg_t reg; 2742 2743 DELAY(500000); 2744 /* XXX: Magic Numbers */ 2745 reg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_UNKNOWN0); 2746 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_UNKNOWN0, 2747 reg | (1 << 15)); 2748 } 2749 /* 2750 * XXX: Magic Numbers. 2751 * Sets maximal PCI-e payload and clears any PCI-e errors. 2752 * Should be replaced with references to PCI config-space 2753 * capability block for PCI-Express. 2754 */ 2755 pci_conf_write(sc->sc_pc, sc->sc_pcitag, 2756 BGE_PCI_CONF_DEV_CTRL, 0xf5000); 2757 2758 } 2759 2760 /* Reset some of the PCI state that got zapped by reset */ 2761 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MISC_CTL, 2762 BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR| 2763 BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_PCISTATE_RW); 2764 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CMD, command); 2765 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CACHESZ, cachesize); 2766 write_op(sc, BGE_MISC_CFG, (65 << 1)); 2767 2768 /* Enable memory arbiter. */ 2769 { 2770 uint32_t marbmode = 0; 2771 if (BGE_IS_5714_FAMILY(sc)) { 2772 marbmode = CSR_READ_4(sc, BGE_MARB_MODE); 2773 } 2774 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE | marbmode); 2775 } 2776 2777 2778 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 2779 for (i = 0; i < BGE_TIMEOUT; i++) { 2780 val = CSR_READ_4(sc, BGE_VCPU_STATUS); 2781 if (val & BGE_VCPU_STATUS_INIT_DONE) 2782 break; 2783 DELAY(100); 2784 } 2785 if (i == BGE_TIMEOUT) { 2786 aprint_error_dev(sc->bge_dev, "reset timed out\n"); 2787 return; 2788 } 2789 } else { 2790 /* 2791 * Write the magic number to the firmware mailbox at 0xb50 2792 * so that the driver can synchronize with the firmware. 2793 */ 2794 bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM, BGE_MAGIC_NUMBER); 2795 2796 /* 2797 * Poll the value location we just wrote until 2798 * we see the 1's complement of the magic number. 2799 * This indicates that the firmware initialization 2800 * is complete. 2801 */ 2802 for (i = 0; i < BGE_TIMEOUT; i++) { 2803 val = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM); 2804 if (val == ~BGE_MAGIC_NUMBER) 2805 break; 2806 DELAY(1000); 2807 } 2808 2809 if (i >= BGE_TIMEOUT) { 2810 aprint_error_dev(sc->bge_dev, 2811 "firmware handshake timed out, val = %x\n", val); 2812 /* 2813 * XXX: occasionally fired on bcm5721, but without 2814 * apparent harm. For now, keep going if we timeout 2815 * against PCI-E devices. 2816 */ 2817 if ((sc->bge_flags & BGE_PCIE) == 0) 2818 return; 2819 } 2820 } 2821 2822 /* 2823 * XXX Wait for the value of the PCISTATE register to 2824 * return to its original pre-reset state. This is a 2825 * fairly good indicator of reset completion. If we don't 2826 * wait for the reset to fully complete, trying to read 2827 * from the device's non-PCI registers may yield garbage 2828 * results. 2829 */ 2830 for (i = 0; i < 10000; i++) { 2831 new_pcistate = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 2832 BGE_PCI_PCISTATE); 2833 if ((new_pcistate & ~BGE_PCISTATE_RESERVED) == 2834 (pcistate & ~BGE_PCISTATE_RESERVED)) 2835 break; 2836 DELAY(10); 2837 } 2838 if ((new_pcistate & ~BGE_PCISTATE_RESERVED) != 2839 (pcistate & ~BGE_PCISTATE_RESERVED)) { 2840 aprint_error_dev(sc->bge_dev, "pcistate failed to revert\n"); 2841 } 2842 2843 /* Enable memory arbiter. */ 2844 /* XXX why do this twice? */ 2845 { 2846 uint32_t marbmode = 0; 2847 if (BGE_IS_5714_FAMILY(sc)) { 2848 marbmode = CSR_READ_4(sc, BGE_MARB_MODE); 2849 } 2850 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE | marbmode); 2851 } 2852 2853 /* Fix up byte swapping */ 2854 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS); 2855 2856 CSR_WRITE_4(sc, BGE_MAC_MODE, 0); 2857 2858 /* 2859 * The 5704 in TBI mode apparently needs some special 2860 * adjustment to insure the SERDES drive level is set 2861 * to 1.2V. 2862 */ 2863 if (sc->bge_flags & BGE_PHY_FIBER_TBI && 2864 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) { 2865 u_int32_t serdescfg; 2866 2867 serdescfg = CSR_READ_4(sc, BGE_SERDES_CFG); 2868 serdescfg = (serdescfg & ~0xFFF) | 0x880; 2869 CSR_WRITE_4(sc, BGE_SERDES_CFG, serdescfg); 2870 } 2871 2872 /* XXX: from FreeBSD/Linux; no documentation */ 2873 if (sc->bge_flags & BGE_PCIE && 2874 sc->bge_chipid != BGE_CHIPID_BCM5750_A0) 2875 CSR_WRITE_4(sc, BGE_PCIE_CTL0, CSR_READ_4(sc, BGE_PCIE_CTL0) | (1<<25)); 2876 DELAY(10000); 2877 } 2878 2879 /* 2880 * Frame reception handling. This is called if there's a frame 2881 * on the receive return list. 2882 * 2883 * Note: we have to be able to handle two possibilities here: 2884 * 1) the frame is from the jumbo recieve ring 2885 * 2) the frame is from the standard receive ring 2886 */ 2887 2888 static void 2889 bge_rxeof(struct bge_softc *sc) 2890 { 2891 struct ifnet *ifp; 2892 int stdcnt = 0, jumbocnt = 0; 2893 bus_dmamap_t dmamap; 2894 bus_addr_t offset, toff; 2895 bus_size_t tlen; 2896 int tosync; 2897 2898 ifp = &sc->ethercom.ec_if; 2899 2900 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 2901 offsetof(struct bge_ring_data, bge_status_block), 2902 sizeof (struct bge_status_block), 2903 BUS_DMASYNC_POSTREAD); 2904 2905 offset = offsetof(struct bge_ring_data, bge_rx_return_ring); 2906 tosync = sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx - 2907 sc->bge_rx_saved_considx; 2908 2909 #if NRND > 0 2910 if (tosync != 0 && RND_ENABLED(&sc->rnd_source)) 2911 rnd_add_uint32(&sc->rnd_source, tosync); 2912 #endif 2913 2914 toff = offset + (sc->bge_rx_saved_considx * sizeof (struct bge_rx_bd)); 2915 2916 if (tosync < 0) { 2917 tlen = (sc->bge_return_ring_cnt - sc->bge_rx_saved_considx) * 2918 sizeof (struct bge_rx_bd); 2919 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 2920 toff, tlen, BUS_DMASYNC_POSTREAD); 2921 tosync = -tosync; 2922 } 2923 2924 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 2925 offset, tosync * sizeof (struct bge_rx_bd), 2926 BUS_DMASYNC_POSTREAD); 2927 2928 while(sc->bge_rx_saved_considx != 2929 sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx) { 2930 struct bge_rx_bd *cur_rx; 2931 u_int32_t rxidx; 2932 struct mbuf *m = NULL; 2933 2934 cur_rx = &sc->bge_rdata-> 2935 bge_rx_return_ring[sc->bge_rx_saved_considx]; 2936 2937 rxidx = cur_rx->bge_idx; 2938 BGE_INC(sc->bge_rx_saved_considx, sc->bge_return_ring_cnt); 2939 2940 if (cur_rx->bge_flags & BGE_RXBDFLAG_JUMBO_RING) { 2941 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT); 2942 m = sc->bge_cdata.bge_rx_jumbo_chain[rxidx]; 2943 sc->bge_cdata.bge_rx_jumbo_chain[rxidx] = NULL; 2944 jumbocnt++; 2945 bus_dmamap_sync(sc->bge_dmatag, 2946 sc->bge_cdata.bge_rx_jumbo_map, 2947 mtod(m, char *) - (char *)sc->bge_cdata.bge_jumbo_buf, 2948 BGE_JLEN, BUS_DMASYNC_POSTREAD); 2949 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 2950 ifp->if_ierrors++; 2951 bge_newbuf_jumbo(sc, sc->bge_jumbo, m); 2952 continue; 2953 } 2954 if (bge_newbuf_jumbo(sc, sc->bge_jumbo, 2955 NULL)== ENOBUFS) { 2956 ifp->if_ierrors++; 2957 bge_newbuf_jumbo(sc, sc->bge_jumbo, m); 2958 continue; 2959 } 2960 } else { 2961 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT); 2962 m = sc->bge_cdata.bge_rx_std_chain[rxidx]; 2963 2964 sc->bge_cdata.bge_rx_std_chain[rxidx] = NULL; 2965 stdcnt++; 2966 dmamap = sc->bge_cdata.bge_rx_std_map[rxidx]; 2967 sc->bge_cdata.bge_rx_std_map[rxidx] = 0; 2968 bus_dmamap_sync(sc->bge_dmatag, dmamap, 0, 2969 dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 2970 bus_dmamap_unload(sc->bge_dmatag, dmamap); 2971 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 2972 ifp->if_ierrors++; 2973 bge_newbuf_std(sc, sc->bge_std, m, dmamap); 2974 continue; 2975 } 2976 if (bge_newbuf_std(sc, sc->bge_std, 2977 NULL, dmamap) == ENOBUFS) { 2978 ifp->if_ierrors++; 2979 bge_newbuf_std(sc, sc->bge_std, m, dmamap); 2980 continue; 2981 } 2982 } 2983 2984 ifp->if_ipackets++; 2985 #ifndef __NO_STRICT_ALIGNMENT 2986 /* 2987 * XXX: if the 5701 PCIX-Rx-DMA workaround is in effect, 2988 * the Rx buffer has the layer-2 header unaligned. 2989 * If our CPU requires alignment, re-align by copying. 2990 */ 2991 if (sc->bge_flags & BGE_RX_ALIGNBUG) { 2992 memmove(mtod(m, char *) + ETHER_ALIGN, m->m_data, 2993 cur_rx->bge_len); 2994 m->m_data += ETHER_ALIGN; 2995 } 2996 #endif 2997 2998 m->m_pkthdr.len = m->m_len = cur_rx->bge_len - ETHER_CRC_LEN; 2999 m->m_pkthdr.rcvif = ifp; 3000 3001 /* 3002 * Handle BPF listeners. Let the BPF user see the packet. 3003 */ 3004 if (ifp->if_bpf) 3005 bpf_ops->bpf_mtap(ifp->if_bpf, m); 3006 3007 m->m_pkthdr.csum_flags = M_CSUM_IPv4; 3008 3009 if ((cur_rx->bge_ip_csum ^ 0xffff) != 0) 3010 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 3011 /* 3012 * Rx transport checksum-offload may also 3013 * have bugs with packets which, when transmitted, 3014 * were `runts' requiring padding. 3015 */ 3016 if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM && 3017 (/* (sc->_bge_quirks & BGE_QUIRK_SHORT_CKSUM_BUG) == 0 ||*/ 3018 m->m_pkthdr.len >= ETHER_MIN_NOPAD)) { 3019 m->m_pkthdr.csum_data = 3020 cur_rx->bge_tcp_udp_csum; 3021 m->m_pkthdr.csum_flags |= 3022 (M_CSUM_TCPv4|M_CSUM_UDPv4| 3023 M_CSUM_DATA|M_CSUM_NO_PSEUDOHDR); 3024 } 3025 3026 /* 3027 * If we received a packet with a vlan tag, pass it 3028 * to vlan_input() instead of ether_input(). 3029 */ 3030 if (cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) { 3031 VLAN_INPUT_TAG(ifp, m, cur_rx->bge_vlan_tag, continue); 3032 } 3033 3034 (*ifp->if_input)(ifp, m); 3035 } 3036 3037 bge_writembx(sc, BGE_MBX_RX_CONS0_LO, sc->bge_rx_saved_considx); 3038 if (stdcnt) 3039 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std); 3040 if (jumbocnt) 3041 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo); 3042 } 3043 3044 static void 3045 bge_txeof(struct bge_softc *sc) 3046 { 3047 struct bge_tx_bd *cur_tx = NULL; 3048 struct ifnet *ifp; 3049 struct txdmamap_pool_entry *dma; 3050 bus_addr_t offset, toff; 3051 bus_size_t tlen; 3052 int tosync; 3053 struct mbuf *m; 3054 3055 ifp = &sc->ethercom.ec_if; 3056 3057 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 3058 offsetof(struct bge_ring_data, bge_status_block), 3059 sizeof (struct bge_status_block), 3060 BUS_DMASYNC_POSTREAD); 3061 3062 offset = offsetof(struct bge_ring_data, bge_tx_ring); 3063 tosync = sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx - 3064 sc->bge_tx_saved_considx; 3065 3066 #if NRND > 0 3067 if (tosync != 0 && RND_ENABLED(&sc->rnd_source)) 3068 rnd_add_uint32(&sc->rnd_source, tosync); 3069 #endif 3070 3071 toff = offset + (sc->bge_tx_saved_considx * sizeof (struct bge_tx_bd)); 3072 3073 if (tosync < 0) { 3074 tlen = (BGE_TX_RING_CNT - sc->bge_tx_saved_considx) * 3075 sizeof (struct bge_tx_bd); 3076 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 3077 toff, tlen, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 3078 tosync = -tosync; 3079 } 3080 3081 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 3082 offset, tosync * sizeof (struct bge_tx_bd), 3083 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 3084 3085 /* 3086 * Go through our tx ring and free mbufs for those 3087 * frames that have been sent. 3088 */ 3089 while (sc->bge_tx_saved_considx != 3090 sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx) { 3091 u_int32_t idx = 0; 3092 3093 idx = sc->bge_tx_saved_considx; 3094 cur_tx = &sc->bge_rdata->bge_tx_ring[idx]; 3095 if (cur_tx->bge_flags & BGE_TXBDFLAG_END) 3096 ifp->if_opackets++; 3097 m = sc->bge_cdata.bge_tx_chain[idx]; 3098 if (m != NULL) { 3099 sc->bge_cdata.bge_tx_chain[idx] = NULL; 3100 dma = sc->txdma[idx]; 3101 bus_dmamap_sync(sc->bge_dmatag, dma->dmamap, 0, 3102 dma->dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 3103 bus_dmamap_unload(sc->bge_dmatag, dma->dmamap); 3104 SLIST_INSERT_HEAD(&sc->txdma_list, dma, link); 3105 sc->txdma[idx] = NULL; 3106 3107 m_freem(m); 3108 } 3109 sc->bge_txcnt--; 3110 BGE_INC(sc->bge_tx_saved_considx, BGE_TX_RING_CNT); 3111 ifp->if_timer = 0; 3112 } 3113 3114 if (cur_tx != NULL) 3115 ifp->if_flags &= ~IFF_OACTIVE; 3116 } 3117 3118 static int 3119 bge_intr(void *xsc) 3120 { 3121 struct bge_softc *sc; 3122 struct ifnet *ifp; 3123 uint32_t statusword; 3124 3125 sc = xsc; 3126 ifp = &sc->ethercom.ec_if; 3127 3128 /* It is possible for the interrupt to arrive before 3129 * the status block is updated prior to the interrupt. 3130 * Reading the PCI State register will confirm whether the 3131 * interrupt is ours and will flush the status block. 3132 */ 3133 3134 /* read status word from status block */ 3135 statusword = sc->bge_rdata->bge_status_block.bge_status; 3136 3137 if ((statusword & BGE_STATFLAG_UPDATED) || 3138 (!(CSR_READ_4(sc, BGE_PCI_PCISTATE) & BGE_PCISTATE_INTR_NOT_ACTIVE))) { 3139 /* Ack interrupt and stop others from occuring. */ 3140 bge_writembx(sc, BGE_MBX_IRQ0_LO, 1); 3141 3142 BGE_EVCNT_INCR(sc->bge_ev_intr); 3143 3144 /* clear status word */ 3145 sc->bge_rdata->bge_status_block.bge_status = 0; 3146 3147 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 3148 statusword & BGE_STATFLAG_LINKSTATE_CHANGED || 3149 BGE_STS_BIT(sc, BGE_STS_LINK_EVT)) 3150 bge_link_upd(sc); 3151 3152 if (ifp->if_flags & IFF_RUNNING) { 3153 /* Check RX return ring producer/consumer */ 3154 bge_rxeof(sc); 3155 3156 /* Check TX ring producer/consumer */ 3157 bge_txeof(sc); 3158 } 3159 3160 if (sc->bge_pending_rxintr_change) { 3161 uint32_t rx_ticks = sc->bge_rx_coal_ticks; 3162 uint32_t rx_bds = sc->bge_rx_max_coal_bds; 3163 uint32_t junk; 3164 3165 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, rx_ticks); 3166 DELAY(10); 3167 junk = CSR_READ_4(sc, BGE_HCC_RX_COAL_TICKS); 3168 3169 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, rx_bds); 3170 DELAY(10); 3171 junk = CSR_READ_4(sc, BGE_HCC_RX_MAX_COAL_BDS); 3172 3173 sc->bge_pending_rxintr_change = 0; 3174 } 3175 bge_handle_events(sc); 3176 3177 /* Re-enable interrupts. */ 3178 bge_writembx(sc, BGE_MBX_IRQ0_LO, 0); 3179 3180 if (ifp->if_flags & IFF_RUNNING && !IFQ_IS_EMPTY(&ifp->if_snd)) 3181 bge_start(ifp); 3182 3183 return (1); 3184 } else 3185 return (0); 3186 } 3187 3188 static void 3189 bge_tick(void *xsc) 3190 { 3191 struct bge_softc *sc = xsc; 3192 struct mii_data *mii = &sc->bge_mii; 3193 int s; 3194 3195 s = splnet(); 3196 3197 bge_stats_update(sc); 3198 3199 if (sc->bge_flags & BGE_PHY_FIBER_TBI) { 3200 /* 3201 * Since in TBI mode auto-polling can't be used we should poll 3202 * link status manually. Here we register pending link event 3203 * and trigger interrupt. 3204 */ 3205 BGE_STS_SETBIT(sc, BGE_STS_LINK_EVT); 3206 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET); 3207 } else { 3208 /* 3209 * Do not touch PHY if we have link up. This could break 3210 * IPMI/ASF mode or produce extra input errors. 3211 * (extra input errors was reported for bcm5701 & bcm5704). 3212 */ 3213 if (!BGE_STS_BIT(sc, BGE_STS_LINK)) 3214 mii_tick(mii); 3215 } 3216 3217 callout_reset(&sc->bge_timeout, hz, bge_tick, sc); 3218 3219 splx(s); 3220 } 3221 3222 static void 3223 bge_stats_update(struct bge_softc *sc) 3224 { 3225 struct ifnet *ifp = &sc->ethercom.ec_if; 3226 bus_size_t stats = BGE_MEMWIN_START + BGE_STATS_BLOCK; 3227 bus_size_t rstats = BGE_RX_STATS; 3228 3229 #define READ_RSTAT(sc, stats, stat) \ 3230 CSR_READ_4(sc, stats + offsetof(struct bge_mac_stats_regs, stat)) 3231 3232 if (BGE_IS_5705_OR_BEYOND(sc)) { 3233 ifp->if_collisions += 3234 READ_RSTAT(sc, rstats, dot3StatsSingleCollisionFrames) + 3235 READ_RSTAT(sc, rstats, dot3StatsMultipleCollisionFrames) + 3236 READ_RSTAT(sc, rstats, dot3StatsExcessiveCollisions) + 3237 READ_RSTAT(sc, rstats, dot3StatsLateCollisions); 3238 3239 BGE_EVCNT_ADD(sc->bge_ev_tx_xoff, 3240 READ_RSTAT(sc, rstats, outXoffSent)); 3241 BGE_EVCNT_ADD(sc->bge_ev_tx_xon, 3242 READ_RSTAT(sc, rstats, outXonSent)); 3243 BGE_EVCNT_ADD(sc->bge_ev_rx_xoff, 3244 READ_RSTAT(sc, rstats, xoffPauseFramesReceived)); 3245 BGE_EVCNT_ADD(sc->bge_ev_rx_xon, 3246 READ_RSTAT(sc, rstats, xonPauseFramesReceived)); 3247 BGE_EVCNT_ADD(sc->bge_ev_rx_macctl, 3248 READ_RSTAT(sc, rstats, macControlFramesReceived)); 3249 BGE_EVCNT_ADD(sc->bge_ev_xoffentered, 3250 READ_RSTAT(sc, rstats, xoffStateEntered)); 3251 return; 3252 } 3253 3254 #undef READ_RSTAT 3255 #define READ_STAT(sc, stats, stat) \ 3256 CSR_READ_4(sc, stats + offsetof(struct bge_stats, stat)) 3257 3258 ifp->if_collisions += 3259 (READ_STAT(sc, stats, dot3StatsSingleCollisionFrames.bge_addr_lo) + 3260 READ_STAT(sc, stats, dot3StatsMultipleCollisionFrames.bge_addr_lo) + 3261 READ_STAT(sc, stats, dot3StatsExcessiveCollisions.bge_addr_lo) + 3262 READ_STAT(sc, stats, dot3StatsLateCollisions.bge_addr_lo)) - 3263 ifp->if_collisions; 3264 3265 BGE_EVCNT_UPD(sc->bge_ev_tx_xoff, 3266 READ_STAT(sc, stats, outXoffSent.bge_addr_lo)); 3267 BGE_EVCNT_UPD(sc->bge_ev_tx_xon, 3268 READ_STAT(sc, stats, outXonSent.bge_addr_lo)); 3269 BGE_EVCNT_UPD(sc->bge_ev_rx_xoff, 3270 READ_STAT(sc, stats, 3271 xoffPauseFramesReceived.bge_addr_lo)); 3272 BGE_EVCNT_UPD(sc->bge_ev_rx_xon, 3273 READ_STAT(sc, stats, xonPauseFramesReceived.bge_addr_lo)); 3274 BGE_EVCNT_UPD(sc->bge_ev_rx_macctl, 3275 READ_STAT(sc, stats, 3276 macControlFramesReceived.bge_addr_lo)); 3277 BGE_EVCNT_UPD(sc->bge_ev_xoffentered, 3278 READ_STAT(sc, stats, xoffStateEntered.bge_addr_lo)); 3279 3280 #undef READ_STAT 3281 3282 #ifdef notdef 3283 ifp->if_collisions += 3284 (sc->bge_rdata->bge_info.bge_stats.dot3StatsSingleCollisionFrames + 3285 sc->bge_rdata->bge_info.bge_stats.dot3StatsMultipleCollisionFrames + 3286 sc->bge_rdata->bge_info.bge_stats.dot3StatsExcessiveCollisions + 3287 sc->bge_rdata->bge_info.bge_stats.dot3StatsLateCollisions) - 3288 ifp->if_collisions; 3289 #endif 3290 } 3291 3292 /* 3293 * Pad outbound frame to ETHER_MIN_NOPAD for an unusual reason. 3294 * The bge hardware will pad out Tx runts to ETHER_MIN_NOPAD, 3295 * but when such padded frames employ the bge IP/TCP checksum offload, 3296 * the hardware checksum assist gives incorrect results (possibly 3297 * from incorporating its own padding into the UDP/TCP checksum; who knows). 3298 * If we pad such runts with zeros, the onboard checksum comes out correct. 3299 */ 3300 static inline int 3301 bge_cksum_pad(struct mbuf *pkt) 3302 { 3303 struct mbuf *last = NULL; 3304 int padlen; 3305 3306 padlen = ETHER_MIN_NOPAD - pkt->m_pkthdr.len; 3307 3308 /* if there's only the packet-header and we can pad there, use it. */ 3309 if (pkt->m_pkthdr.len == pkt->m_len && 3310 M_TRAILINGSPACE(pkt) >= padlen) { 3311 last = pkt; 3312 } else { 3313 /* 3314 * Walk packet chain to find last mbuf. We will either 3315 * pad there, or append a new mbuf and pad it 3316 * (thus perhaps avoiding the bcm5700 dma-min bug). 3317 */ 3318 for (last = pkt; last->m_next != NULL; last = last->m_next) { 3319 continue; /* do nothing */ 3320 } 3321 3322 /* `last' now points to last in chain. */ 3323 if (M_TRAILINGSPACE(last) < padlen) { 3324 /* Allocate new empty mbuf, pad it. Compact later. */ 3325 struct mbuf *n; 3326 MGET(n, M_DONTWAIT, MT_DATA); 3327 if (n == NULL) 3328 return ENOBUFS; 3329 n->m_len = 0; 3330 last->m_next = n; 3331 last = n; 3332 } 3333 } 3334 3335 KDASSERT(!M_READONLY(last)); 3336 KDASSERT(M_TRAILINGSPACE(last) >= padlen); 3337 3338 /* Now zero the pad area, to avoid the bge cksum-assist bug */ 3339 memset(mtod(last, char *) + last->m_len, 0, padlen); 3340 last->m_len += padlen; 3341 pkt->m_pkthdr.len += padlen; 3342 return 0; 3343 } 3344 3345 /* 3346 * Compact outbound packets to avoid bug with DMA segments less than 8 bytes. 3347 */ 3348 static inline int 3349 bge_compact_dma_runt(struct mbuf *pkt) 3350 { 3351 struct mbuf *m, *prev; 3352 int totlen, prevlen; 3353 3354 prev = NULL; 3355 totlen = 0; 3356 prevlen = -1; 3357 3358 for (m = pkt; m != NULL; prev = m,m = m->m_next) { 3359 int mlen = m->m_len; 3360 int shortfall = 8 - mlen ; 3361 3362 totlen += mlen; 3363 if (mlen == 0) { 3364 continue; 3365 } 3366 if (mlen >= 8) 3367 continue; 3368 3369 /* If we get here, mbuf data is too small for DMA engine. 3370 * Try to fix by shuffling data to prev or next in chain. 3371 * If that fails, do a compacting deep-copy of the whole chain. 3372 */ 3373 3374 /* Internal frag. If fits in prev, copy it there. */ 3375 if (prev && M_TRAILINGSPACE(prev) >= m->m_len) { 3376 memcpy(prev->m_data + prev->m_len, m->m_data, mlen); 3377 prev->m_len += mlen; 3378 m->m_len = 0; 3379 /* XXX stitch chain */ 3380 prev->m_next = m_free(m); 3381 m = prev; 3382 continue; 3383 } 3384 else if (m->m_next != NULL && 3385 M_TRAILINGSPACE(m) >= shortfall && 3386 m->m_next->m_len >= (8 + shortfall)) { 3387 /* m is writable and have enough data in next, pull up. */ 3388 3389 memcpy(m->m_data + m->m_len, m->m_next->m_data, 3390 shortfall); 3391 m->m_len += shortfall; 3392 m->m_next->m_len -= shortfall; 3393 m->m_next->m_data += shortfall; 3394 } 3395 else if (m->m_next == NULL || 1) { 3396 /* Got a runt at the very end of the packet. 3397 * borrow data from the tail of the preceding mbuf and 3398 * update its length in-place. (The original data is still 3399 * valid, so we can do this even if prev is not writable.) 3400 */ 3401 3402 /* if we'd make prev a runt, just move all of its data. */ 3403 KASSERT(prev != NULL /*, ("runt but null PREV")*/); 3404 KASSERT(prev->m_len >= 8 /*, ("runt prev")*/); 3405 3406 if ((prev->m_len - shortfall) < 8) 3407 shortfall = prev->m_len; 3408 3409 #ifdef notyet /* just do the safe slow thing for now */ 3410 if (!M_READONLY(m)) { 3411 if (M_LEADINGSPACE(m) < shorfall) { 3412 void *m_dat; 3413 m_dat = (m->m_flags & M_PKTHDR) ? 3414 m->m_pktdat : m->dat; 3415 memmove(m_dat, mtod(m, void*), m->m_len); 3416 m->m_data = m_dat; 3417 } 3418 } else 3419 #endif /* just do the safe slow thing */ 3420 { 3421 struct mbuf * n = NULL; 3422 int newprevlen = prev->m_len - shortfall; 3423 3424 MGET(n, M_NOWAIT, MT_DATA); 3425 if (n == NULL) 3426 return ENOBUFS; 3427 KASSERT(m->m_len + shortfall < MLEN 3428 /*, 3429 ("runt %d +prev %d too big\n", m->m_len, shortfall)*/); 3430 3431 /* first copy the data we're stealing from prev */ 3432 memcpy(n->m_data, prev->m_data + newprevlen, 3433 shortfall); 3434 3435 /* update prev->m_len accordingly */ 3436 prev->m_len -= shortfall; 3437 3438 /* copy data from runt m */ 3439 memcpy(n->m_data + shortfall, m->m_data, 3440 m->m_len); 3441 3442 /* n holds what we stole from prev, plus m */ 3443 n->m_len = shortfall + m->m_len; 3444 3445 /* stitch n into chain and free m */ 3446 n->m_next = m->m_next; 3447 prev->m_next = n; 3448 /* KASSERT(m->m_next == NULL); */ 3449 m->m_next = NULL; 3450 m_free(m); 3451 m = n; /* for continuing loop */ 3452 } 3453 } 3454 prevlen = m->m_len; 3455 } 3456 return 0; 3457 } 3458 3459 /* 3460 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data 3461 * pointers to descriptors. 3462 */ 3463 static int 3464 bge_encap(struct bge_softc *sc, struct mbuf *m_head, u_int32_t *txidx) 3465 { 3466 struct bge_tx_bd *f = NULL; 3467 u_int32_t frag, cur; 3468 u_int16_t csum_flags = 0; 3469 u_int16_t txbd_tso_flags = 0; 3470 struct txdmamap_pool_entry *dma; 3471 bus_dmamap_t dmamap; 3472 int i = 0; 3473 struct m_tag *mtag; 3474 int use_tso, maxsegsize, error; 3475 3476 cur = frag = *txidx; 3477 3478 if (m_head->m_pkthdr.csum_flags) { 3479 if (m_head->m_pkthdr.csum_flags & M_CSUM_IPv4) 3480 csum_flags |= BGE_TXBDFLAG_IP_CSUM; 3481 if (m_head->m_pkthdr.csum_flags & (M_CSUM_TCPv4|M_CSUM_UDPv4)) 3482 csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM; 3483 } 3484 3485 /* 3486 * If we were asked to do an outboard checksum, and the NIC 3487 * has the bug where it sometimes adds in the Ethernet padding, 3488 * explicitly pad with zeros so the cksum will be correct either way. 3489 * (For now, do this for all chip versions, until newer 3490 * are confirmed to not require the workaround.) 3491 */ 3492 if ((csum_flags & BGE_TXBDFLAG_TCP_UDP_CSUM) == 0 || 3493 #ifdef notyet 3494 (sc->bge_quirks & BGE_QUIRK_SHORT_CKSUM_BUG) == 0 || 3495 #endif 3496 m_head->m_pkthdr.len >= ETHER_MIN_NOPAD) 3497 goto check_dma_bug; 3498 3499 if (bge_cksum_pad(m_head) != 0) { 3500 return ENOBUFS; 3501 } 3502 3503 check_dma_bug: 3504 if (!(BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX)) 3505 goto doit; 3506 3507 /* 3508 * bcm5700 Revision B silicon cannot handle DMA descriptors with 3509 * less than eight bytes. If we encounter a teeny mbuf 3510 * at the end of a chain, we can pad. Otherwise, copy. 3511 */ 3512 if (bge_compact_dma_runt(m_head) != 0) 3513 return ENOBUFS; 3514 3515 doit: 3516 dma = SLIST_FIRST(&sc->txdma_list); 3517 if (dma == NULL) 3518 return ENOBUFS; 3519 dmamap = dma->dmamap; 3520 3521 /* 3522 * Set up any necessary TSO state before we start packing... 3523 */ 3524 use_tso = (m_head->m_pkthdr.csum_flags & M_CSUM_TSOv4) != 0; 3525 if (!use_tso) { 3526 maxsegsize = 0; 3527 } else { /* TSO setup */ 3528 unsigned mss; 3529 struct ether_header *eh; 3530 unsigned ip_tcp_hlen, iptcp_opt_words, tcp_seg_flags, offset; 3531 struct mbuf * m0 = m_head; 3532 struct ip *ip; 3533 struct tcphdr *th; 3534 int iphl, hlen; 3535 3536 /* 3537 * XXX It would be nice if the mbuf pkthdr had offset 3538 * fields for the protocol headers. 3539 */ 3540 3541 eh = mtod(m0, struct ether_header *); 3542 switch (htons(eh->ether_type)) { 3543 case ETHERTYPE_IP: 3544 offset = ETHER_HDR_LEN; 3545 break; 3546 3547 case ETHERTYPE_VLAN: 3548 offset = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 3549 break; 3550 3551 default: 3552 /* 3553 * Don't support this protocol or encapsulation. 3554 */ 3555 return (ENOBUFS); 3556 } 3557 3558 /* 3559 * TCP/IP headers are in the first mbuf; we can do 3560 * this the easy way. 3561 */ 3562 iphl = M_CSUM_DATA_IPv4_IPHL(m0->m_pkthdr.csum_data); 3563 hlen = iphl + offset; 3564 if (__predict_false(m0->m_len < 3565 (hlen + sizeof(struct tcphdr)))) { 3566 3567 aprint_debug_dev(sc->bge_dev, 3568 "TSO: hard case m0->m_len == %d < ip/tcp hlen %zd," 3569 "not handled yet\n", 3570 m0->m_len, hlen+ sizeof(struct tcphdr)); 3571 #ifdef NOTYET 3572 /* 3573 * XXX jonathan (at) NetBSD.org: untested. 3574 * how to force this branch to be taken? 3575 */ 3576 BGE_EVCNT_INCR(&sc->sc_ev_txtsopain); 3577 3578 m_copydata(m0, offset, sizeof(ip), &ip); 3579 m_copydata(m0, hlen, sizeof(th), &th); 3580 3581 ip.ip_len = 0; 3582 3583 m_copyback(m0, hlen + offsetof(struct ip, ip_len), 3584 sizeof(ip.ip_len), &ip.ip_len); 3585 3586 th.th_sum = in_cksum_phdr(ip.ip_src.s_addr, 3587 ip.ip_dst.s_addr, htons(IPPROTO_TCP)); 3588 3589 m_copyback(m0, hlen + offsetof(struct tcphdr, th_sum), 3590 sizeof(th.th_sum), &th.th_sum); 3591 3592 hlen += th.th_off << 2; 3593 iptcp_opt_words = hlen; 3594 #else 3595 /* 3596 * if_wm "hard" case not yet supported, can we not 3597 * mandate it out of existence? 3598 */ 3599 (void) ip; (void)th; (void) ip_tcp_hlen; 3600 3601 return ENOBUFS; 3602 #endif 3603 } else { 3604 ip = (struct ip *) (mtod(m0, char *) + offset); 3605 th = (struct tcphdr *) (mtod(m0, char *) + hlen); 3606 ip_tcp_hlen = iphl + (th->th_off << 2); 3607 3608 /* Total IP/TCP options, in 32-bit words */ 3609 iptcp_opt_words = (ip_tcp_hlen 3610 - sizeof(struct tcphdr) 3611 - sizeof(struct ip)) >> 2; 3612 } 3613 if (BGE_IS_5750_OR_BEYOND(sc)) { 3614 th->th_sum = 0; 3615 csum_flags &= ~(BGE_TXBDFLAG_TCP_UDP_CSUM); 3616 } else { 3617 /* 3618 * XXX jonathan (at) NetBSD.org: 5705 untested. 3619 * Requires TSO firmware patch for 5701/5703/5704. 3620 */ 3621 th->th_sum = in_cksum_phdr(ip->ip_src.s_addr, 3622 ip->ip_dst.s_addr, htons(IPPROTO_TCP)); 3623 } 3624 3625 mss = m_head->m_pkthdr.segsz; 3626 txbd_tso_flags |= 3627 BGE_TXBDFLAG_CPU_PRE_DMA | 3628 BGE_TXBDFLAG_CPU_POST_DMA; 3629 3630 /* 3631 * Our NIC TSO-assist assumes TSO has standard, optionless 3632 * IPv4 and TCP headers, which total 40 bytes. By default, 3633 * the NIC copies 40 bytes of IP/TCP header from the 3634 * supplied header into the IP/TCP header portion of 3635 * each post-TSO-segment. If the supplied packet has IP or 3636 * TCP options, we need to tell the NIC to copy those extra 3637 * bytes into each post-TSO header, in addition to the normal 3638 * 40-byte IP/TCP header (and to leave space accordingly). 3639 * Unfortunately, the driver encoding of option length 3640 * varies across different ASIC families. 3641 */ 3642 tcp_seg_flags = 0; 3643 if (iptcp_opt_words) { 3644 if ( BGE_IS_5705_OR_BEYOND(sc)) { 3645 tcp_seg_flags = 3646 iptcp_opt_words << 11; 3647 } else { 3648 txbd_tso_flags |= 3649 iptcp_opt_words << 12; 3650 } 3651 } 3652 maxsegsize = mss | tcp_seg_flags; 3653 ip->ip_len = htons(mss + ip_tcp_hlen); 3654 3655 } /* TSO setup */ 3656 3657 /* 3658 * Start packing the mbufs in this chain into 3659 * the fragment pointers. Stop when we run out 3660 * of fragments or hit the end of the mbuf chain. 3661 */ 3662 error = bus_dmamap_load_mbuf(sc->bge_dmatag, dmamap, m_head, 3663 BUS_DMA_NOWAIT); 3664 if (error) { 3665 return (ENOBUFS); 3666 } 3667 /* 3668 * Sanity check: avoid coming within 16 descriptors 3669 * of the end of the ring. 3670 */ 3671 if (dmamap->dm_nsegs > (BGE_TX_RING_CNT - sc->bge_txcnt - 16)) { 3672 BGE_TSO_PRINTF(("%s: " 3673 " dmamap_load_mbuf too close to ring wrap\n", 3674 device_xname(sc->bge_dev))); 3675 goto fail_unload; 3676 } 3677 3678 mtag = sc->ethercom.ec_nvlans ? 3679 m_tag_find(m_head, PACKET_TAG_VLAN, NULL) : NULL; 3680 3681 3682 /* Iterate over dmap-map fragments. */ 3683 for (i = 0; i < dmamap->dm_nsegs; i++) { 3684 f = &sc->bge_rdata->bge_tx_ring[frag]; 3685 if (sc->bge_cdata.bge_tx_chain[frag] != NULL) 3686 break; 3687 3688 bge_set_hostaddr(&f->bge_addr, dmamap->dm_segs[i].ds_addr); 3689 f->bge_len = dmamap->dm_segs[i].ds_len; 3690 3691 /* 3692 * For 5751 and follow-ons, for TSO we must turn 3693 * off checksum-assist flag in the tx-descr, and 3694 * supply the ASIC-revision-specific encoding 3695 * of TSO flags and segsize. 3696 */ 3697 if (use_tso) { 3698 if (BGE_IS_5750_OR_BEYOND(sc) || i == 0) { 3699 f->bge_rsvd = maxsegsize; 3700 f->bge_flags = csum_flags | txbd_tso_flags; 3701 } else { 3702 f->bge_rsvd = 0; 3703 f->bge_flags = 3704 (csum_flags | txbd_tso_flags) & 0x0fff; 3705 } 3706 } else { 3707 f->bge_rsvd = 0; 3708 f->bge_flags = csum_flags; 3709 } 3710 3711 if (mtag != NULL) { 3712 f->bge_flags |= BGE_TXBDFLAG_VLAN_TAG; 3713 f->bge_vlan_tag = VLAN_TAG_VALUE(mtag); 3714 } else { 3715 f->bge_vlan_tag = 0; 3716 } 3717 cur = frag; 3718 BGE_INC(frag, BGE_TX_RING_CNT); 3719 } 3720 3721 if (i < dmamap->dm_nsegs) { 3722 BGE_TSO_PRINTF(("%s: reached %d < dm_nsegs %d\n", 3723 device_xname(sc->bge_dev), i, dmamap->dm_nsegs)); 3724 goto fail_unload; 3725 } 3726 3727 bus_dmamap_sync(sc->bge_dmatag, dmamap, 0, dmamap->dm_mapsize, 3728 BUS_DMASYNC_PREWRITE); 3729 3730 if (frag == sc->bge_tx_saved_considx) { 3731 BGE_TSO_PRINTF(("%s: frag %d = wrapped id %d?\n", 3732 device_xname(sc->bge_dev), frag, sc->bge_tx_saved_considx)); 3733 3734 goto fail_unload; 3735 } 3736 3737 sc->bge_rdata->bge_tx_ring[cur].bge_flags |= BGE_TXBDFLAG_END; 3738 sc->bge_cdata.bge_tx_chain[cur] = m_head; 3739 SLIST_REMOVE_HEAD(&sc->txdma_list, link); 3740 sc->txdma[cur] = dma; 3741 sc->bge_txcnt += dmamap->dm_nsegs; 3742 3743 *txidx = frag; 3744 3745 return (0); 3746 3747 fail_unload: 3748 bus_dmamap_unload(sc->bge_dmatag, dmamap); 3749 3750 return ENOBUFS; 3751 } 3752 3753 /* 3754 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 3755 * to the mbuf data regions directly in the transmit descriptors. 3756 */ 3757 static void 3758 bge_start(struct ifnet *ifp) 3759 { 3760 struct bge_softc *sc; 3761 struct mbuf *m_head = NULL; 3762 u_int32_t prodidx; 3763 int pkts = 0; 3764 3765 sc = ifp->if_softc; 3766 3767 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 3768 return; 3769 3770 prodidx = sc->bge_tx_prodidx; 3771 3772 while(sc->bge_cdata.bge_tx_chain[prodidx] == NULL) { 3773 IFQ_POLL(&ifp->if_snd, m_head); 3774 if (m_head == NULL) 3775 break; 3776 3777 #if 0 3778 /* 3779 * XXX 3780 * safety overkill. If this is a fragmented packet chain 3781 * with delayed TCP/UDP checksums, then only encapsulate 3782 * it if we have enough descriptors to handle the entire 3783 * chain at once. 3784 * (paranoia -- may not actually be needed) 3785 */ 3786 if (m_head->m_flags & M_FIRSTFRAG && 3787 m_head->m_pkthdr.csum_flags & (CSUM_DELAY_DATA)) { 3788 if ((BGE_TX_RING_CNT - sc->bge_txcnt) < 3789 M_CSUM_DATA_IPv4_OFFSET(m_head->m_pkthdr.csum_data) + 16) { 3790 ifp->if_flags |= IFF_OACTIVE; 3791 break; 3792 } 3793 } 3794 #endif 3795 3796 /* 3797 * Pack the data into the transmit ring. If we 3798 * don't have room, set the OACTIVE flag and wait 3799 * for the NIC to drain the ring. 3800 */ 3801 if (bge_encap(sc, m_head, &prodidx)) { 3802 ifp->if_flags |= IFF_OACTIVE; 3803 break; 3804 } 3805 3806 /* now we are committed to transmit the packet */ 3807 IFQ_DEQUEUE(&ifp->if_snd, m_head); 3808 pkts++; 3809 3810 /* 3811 * If there's a BPF listener, bounce a copy of this frame 3812 * to him. 3813 */ 3814 if (ifp->if_bpf) 3815 bpf_ops->bpf_mtap(ifp->if_bpf, m_head); 3816 } 3817 if (pkts == 0) 3818 return; 3819 3820 /* Transmit */ 3821 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); 3822 /* 5700 b2 errata */ 3823 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX) 3824 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); 3825 3826 sc->bge_tx_prodidx = prodidx; 3827 3828 /* 3829 * Set a timeout in case the chip goes out to lunch. 3830 */ 3831 ifp->if_timer = 5; 3832 } 3833 3834 static int 3835 bge_init(struct ifnet *ifp) 3836 { 3837 struct bge_softc *sc = ifp->if_softc; 3838 const u_int16_t *m; 3839 int s, error = 0; 3840 3841 s = splnet(); 3842 3843 ifp = &sc->ethercom.ec_if; 3844 3845 /* Cancel pending I/O and flush buffers. */ 3846 bge_stop(ifp, 0); 3847 bge_reset(sc); 3848 bge_chipinit(sc); 3849 3850 /* 3851 * Init the various state machines, ring 3852 * control blocks and firmware. 3853 */ 3854 error = bge_blockinit(sc); 3855 if (error != 0) { 3856 aprint_error_dev(sc->bge_dev, "initialization error %d\n", 3857 error); 3858 splx(s); 3859 return error; 3860 } 3861 3862 ifp = &sc->ethercom.ec_if; 3863 3864 /* Specify MTU. */ 3865 CSR_WRITE_4(sc, BGE_RX_MTU, ifp->if_mtu + 3866 ETHER_HDR_LEN + ETHER_CRC_LEN + ETHER_VLAN_ENCAP_LEN); 3867 3868 /* Load our MAC address. */ 3869 m = (const u_int16_t *)&(CLLADDR(ifp->if_sadl)[0]); 3870 CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0])); 3871 CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, (htons(m[1]) << 16) | htons(m[2])); 3872 3873 /* Enable or disable promiscuous mode as needed. */ 3874 if (ifp->if_flags & IFF_PROMISC) { 3875 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 3876 } else { 3877 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 3878 } 3879 3880 /* Program multicast filter. */ 3881 bge_setmulti(sc); 3882 3883 /* Init RX ring. */ 3884 bge_init_rx_ring_std(sc); 3885 3886 /* 3887 * Workaround for a bug in 5705 ASIC rev A0. Poll the NIC's 3888 * memory to insure that the chip has in fact read the first 3889 * entry of the ring. 3890 */ 3891 if (sc->bge_chipid == BGE_CHIPID_BCM5705_A0) { 3892 u_int32_t v, i; 3893 for (i = 0; i < 10; i++) { 3894 DELAY(20); 3895 v = bge_readmem_ind(sc, BGE_STD_RX_RINGS + 8); 3896 if (v == (MCLBYTES - ETHER_ALIGN)) 3897 break; 3898 } 3899 if (i == 10) 3900 aprint_error_dev(sc->bge_dev, 3901 "5705 A0 chip failed to load RX ring\n"); 3902 } 3903 3904 /* Init jumbo RX ring. */ 3905 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 3906 bge_init_rx_ring_jumbo(sc); 3907 3908 /* Init our RX return ring index */ 3909 sc->bge_rx_saved_considx = 0; 3910 3911 /* Init TX ring. */ 3912 bge_init_tx_ring(sc); 3913 3914 /* Turn on transmitter */ 3915 BGE_SETBIT(sc, BGE_TX_MODE, BGE_TXMODE_ENABLE); 3916 3917 /* Turn on receiver */ 3918 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE); 3919 3920 CSR_WRITE_4(sc, BGE_MAX_RX_FRAME_LOWAT, 2); 3921 3922 /* Tell firmware we're alive. */ 3923 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 3924 3925 /* Enable host interrupts. */ 3926 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA); 3927 BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); 3928 bge_writembx(sc, BGE_MBX_IRQ0_LO, 0); 3929 3930 if ((error = bge_ifmedia_upd(ifp)) != 0) 3931 goto out; 3932 3933 ifp->if_flags |= IFF_RUNNING; 3934 ifp->if_flags &= ~IFF_OACTIVE; 3935 3936 callout_reset(&sc->bge_timeout, hz, bge_tick, sc); 3937 3938 out: 3939 splx(s); 3940 3941 return error; 3942 } 3943 3944 /* 3945 * Set media options. 3946 */ 3947 static int 3948 bge_ifmedia_upd(struct ifnet *ifp) 3949 { 3950 struct bge_softc *sc = ifp->if_softc; 3951 struct mii_data *mii = &sc->bge_mii; 3952 struct ifmedia *ifm = &sc->bge_ifmedia; 3953 int rc; 3954 3955 /* If this is a 1000baseX NIC, enable the TBI port. */ 3956 if (sc->bge_flags & BGE_PHY_FIBER_TBI) { 3957 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 3958 return (EINVAL); 3959 switch(IFM_SUBTYPE(ifm->ifm_media)) { 3960 case IFM_AUTO: 3961 /* 3962 * The BCM5704 ASIC appears to have a special 3963 * mechanism for programming the autoneg 3964 * advertisement registers in TBI mode. 3965 */ 3966 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) { 3967 u_int32_t sgdig; 3968 sgdig = CSR_READ_4(sc, BGE_SGDIG_STS); 3969 if (sgdig & BGE_SGDIGSTS_DONE) { 3970 CSR_WRITE_4(sc, BGE_TX_TBI_AUTONEG, 0); 3971 sgdig = CSR_READ_4(sc, BGE_SGDIG_CFG); 3972 sgdig |= BGE_SGDIGCFG_AUTO | 3973 BGE_SGDIGCFG_PAUSE_CAP | 3974 BGE_SGDIGCFG_ASYM_PAUSE; 3975 CSR_WRITE_4(sc, BGE_SGDIG_CFG, 3976 sgdig | BGE_SGDIGCFG_SEND); 3977 DELAY(5); 3978 CSR_WRITE_4(sc, BGE_SGDIG_CFG, sgdig); 3979 } 3980 } 3981 break; 3982 case IFM_1000_SX: 3983 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 3984 BGE_CLRBIT(sc, BGE_MAC_MODE, 3985 BGE_MACMODE_HALF_DUPLEX); 3986 } else { 3987 BGE_SETBIT(sc, BGE_MAC_MODE, 3988 BGE_MACMODE_HALF_DUPLEX); 3989 } 3990 break; 3991 default: 3992 return (EINVAL); 3993 } 3994 /* XXX 802.3x flow control for 1000BASE-SX */ 3995 return (0); 3996 } 3997 3998 BGE_STS_SETBIT(sc, BGE_STS_LINK_EVT); 3999 if ((rc = mii_mediachg(mii)) == ENXIO) 4000 return 0; 4001 4002 /* 4003 * Force an interrupt so that we will call bge_link_upd 4004 * if needed and clear any pending link state attention. 4005 * Without this we are not getting any further interrupts 4006 * for link state changes and thus will not UP the link and 4007 * not be able to send in bge_start. The only way to get 4008 * things working was to receive a packet and get a RX intr. 4009 */ 4010 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 4011 sc->bge_flags & BGE_IS_5788) 4012 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET); 4013 else 4014 BGE_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW); 4015 4016 return rc; 4017 } 4018 4019 /* 4020 * Report current media status. 4021 */ 4022 static void 4023 bge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 4024 { 4025 struct bge_softc *sc = ifp->if_softc; 4026 struct mii_data *mii = &sc->bge_mii; 4027 4028 if (sc->bge_flags & BGE_PHY_FIBER_TBI) { 4029 ifmr->ifm_status = IFM_AVALID; 4030 ifmr->ifm_active = IFM_ETHER; 4031 if (CSR_READ_4(sc, BGE_MAC_STS) & 4032 BGE_MACSTAT_TBI_PCS_SYNCHED) 4033 ifmr->ifm_status |= IFM_ACTIVE; 4034 ifmr->ifm_active |= IFM_1000_SX; 4035 if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX) 4036 ifmr->ifm_active |= IFM_HDX; 4037 else 4038 ifmr->ifm_active |= IFM_FDX; 4039 return; 4040 } 4041 4042 mii_pollstat(mii); 4043 ifmr->ifm_status = mii->mii_media_status; 4044 ifmr->ifm_active = (mii->mii_media_active & ~IFM_ETH_FMASK) | 4045 sc->bge_flowflags; 4046 } 4047 4048 static int 4049 bge_ioctl(struct ifnet *ifp, u_long command, void *data) 4050 { 4051 struct bge_softc *sc = ifp->if_softc; 4052 struct ifreq *ifr = (struct ifreq *) data; 4053 int s, error = 0; 4054 struct mii_data *mii; 4055 4056 s = splnet(); 4057 4058 switch(command) { 4059 case SIOCSIFFLAGS: 4060 if ((error = ifioctl_common(ifp, command, data)) != 0) 4061 break; 4062 if (ifp->if_flags & IFF_UP) { 4063 /* 4064 * If only the state of the PROMISC flag changed, 4065 * then just use the 'set promisc mode' command 4066 * instead of reinitializing the entire NIC. Doing 4067 * a full re-init means reloading the firmware and 4068 * waiting for it to start up, which may take a 4069 * second or two. 4070 */ 4071 if (ifp->if_flags & IFF_RUNNING && 4072 ifp->if_flags & IFF_PROMISC && 4073 !(sc->bge_if_flags & IFF_PROMISC)) { 4074 BGE_SETBIT(sc, BGE_RX_MODE, 4075 BGE_RXMODE_RX_PROMISC); 4076 } else if (ifp->if_flags & IFF_RUNNING && 4077 !(ifp->if_flags & IFF_PROMISC) && 4078 sc->bge_if_flags & IFF_PROMISC) { 4079 BGE_CLRBIT(sc, BGE_RX_MODE, 4080 BGE_RXMODE_RX_PROMISC); 4081 } else if (!(sc->bge_if_flags & IFF_UP)) 4082 bge_init(ifp); 4083 } else { 4084 if (ifp->if_flags & IFF_RUNNING) 4085 bge_stop(ifp, 1); 4086 } 4087 sc->bge_if_flags = ifp->if_flags; 4088 error = 0; 4089 break; 4090 case SIOCSIFMEDIA: 4091 /* XXX Flow control is not supported for 1000BASE-SX */ 4092 if (sc->bge_flags & BGE_PHY_FIBER_TBI) { 4093 ifr->ifr_media &= ~IFM_ETH_FMASK; 4094 sc->bge_flowflags = 0; 4095 } 4096 4097 /* Flow control requires full-duplex mode. */ 4098 if (IFM_SUBTYPE(ifr->ifr_media) == IFM_AUTO || 4099 (ifr->ifr_media & IFM_FDX) == 0) { 4100 ifr->ifr_media &= ~IFM_ETH_FMASK; 4101 } 4102 if (IFM_SUBTYPE(ifr->ifr_media) != IFM_AUTO) { 4103 if ((ifr->ifr_media & IFM_ETH_FMASK) == IFM_FLOW) { 4104 /* We can do both TXPAUSE and RXPAUSE. */ 4105 ifr->ifr_media |= 4106 IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE; 4107 } 4108 sc->bge_flowflags = ifr->ifr_media & IFM_ETH_FMASK; 4109 } 4110 /* FALLTHROUGH */ 4111 case SIOCGIFMEDIA: 4112 if (sc->bge_flags & BGE_PHY_FIBER_TBI) { 4113 error = ifmedia_ioctl(ifp, ifr, &sc->bge_ifmedia, 4114 command); 4115 } else { 4116 mii = &sc->bge_mii; 4117 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, 4118 command); 4119 } 4120 break; 4121 default: 4122 if ((error = ether_ioctl(ifp, command, data)) != ENETRESET) 4123 break; 4124 4125 error = 0; 4126 4127 if (command != SIOCADDMULTI && command != SIOCDELMULTI) 4128 ; 4129 else if (ifp->if_flags & IFF_RUNNING) 4130 bge_setmulti(sc); 4131 break; 4132 } 4133 4134 splx(s); 4135 4136 return (error); 4137 } 4138 4139 static void 4140 bge_watchdog(struct ifnet *ifp) 4141 { 4142 struct bge_softc *sc; 4143 4144 sc = ifp->if_softc; 4145 4146 aprint_error_dev(sc->bge_dev, "watchdog timeout -- resetting\n"); 4147 4148 ifp->if_flags &= ~IFF_RUNNING; 4149 bge_init(ifp); 4150 4151 ifp->if_oerrors++; 4152 } 4153 4154 static void 4155 bge_stop_block(struct bge_softc *sc, bus_addr_t reg, uint32_t bit) 4156 { 4157 int i; 4158 4159 BGE_CLRBIT(sc, reg, bit); 4160 4161 for (i = 0; i < BGE_TIMEOUT; i++) { 4162 if ((CSR_READ_4(sc, reg) & bit) == 0) 4163 return; 4164 delay(100); 4165 if (sc->bge_flags & BGE_PCIE) 4166 DELAY(1000); 4167 } 4168 4169 /* 4170 * Doesn't print only when the register is BGE_SRS_MODE. It occurs 4171 * on some environment (and once after boot?) 4172 */ 4173 if (reg != BGE_SRS_MODE) 4174 aprint_error_dev(sc->bge_dev, 4175 "block failed to stop: reg 0x%lx, bit 0x%08x\n", 4176 (u_long)reg, bit); 4177 } 4178 4179 /* 4180 * Stop the adapter and free any mbufs allocated to the 4181 * RX and TX lists. 4182 */ 4183 static void 4184 bge_stop(struct ifnet *ifp, int disable) 4185 { 4186 struct bge_softc *sc = ifp->if_softc; 4187 4188 callout_stop(&sc->bge_timeout); 4189 4190 /* 4191 * Disable all of the receiver blocks 4192 */ 4193 bge_stop_block(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE); 4194 bge_stop_block(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 4195 bge_stop_block(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 4196 if (!(BGE_IS_5705_OR_BEYOND(sc))) 4197 bge_stop_block(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 4198 bge_stop_block(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE); 4199 bge_stop_block(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 4200 bge_stop_block(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE); 4201 4202 /* 4203 * Disable all of the transmit blocks 4204 */ 4205 bge_stop_block(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 4206 bge_stop_block(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 4207 bge_stop_block(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 4208 bge_stop_block(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE); 4209 bge_stop_block(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE); 4210 if (!(BGE_IS_5705_OR_BEYOND(sc))) 4211 bge_stop_block(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 4212 bge_stop_block(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 4213 4214 /* 4215 * Shut down all of the memory managers and related 4216 * state machines. 4217 */ 4218 bge_stop_block(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE); 4219 bge_stop_block(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE); 4220 if (!(BGE_IS_5705_OR_BEYOND(sc))) 4221 bge_stop_block(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 4222 4223 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 4224 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 4225 4226 if (!(BGE_IS_5705_OR_BEYOND(sc))) { 4227 bge_stop_block(sc, BGE_BMAN_MODE, BGE_BMANMODE_ENABLE); 4228 bge_stop_block(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 4229 } 4230 4231 /* Disable host interrupts. */ 4232 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); 4233 bge_writembx(sc, BGE_MBX_IRQ0_LO, 1); 4234 4235 /* 4236 * Tell firmware we're shutting down. 4237 */ 4238 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 4239 4240 /* Free the RX lists. */ 4241 bge_free_rx_ring_std(sc); 4242 4243 /* Free jumbo RX list. */ 4244 bge_free_rx_ring_jumbo(sc); 4245 4246 /* Free TX buffers. */ 4247 bge_free_tx_ring(sc); 4248 4249 /* 4250 * Isolate/power down the PHY. 4251 */ 4252 if (!(sc->bge_flags & BGE_PHY_FIBER_TBI)) 4253 mii_down(&sc->bge_mii); 4254 4255 sc->bge_tx_saved_considx = BGE_TXCONS_UNSET; 4256 4257 /* Clear MAC's link state (PHY may still have link UP). */ 4258 BGE_STS_CLRBIT(sc, BGE_STS_LINK); 4259 4260 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 4261 } 4262 4263 static void 4264 bge_link_upd(struct bge_softc *sc) 4265 { 4266 struct ifnet *ifp = &sc->ethercom.ec_if; 4267 struct mii_data *mii = &sc->bge_mii; 4268 u_int32_t status; 4269 int link; 4270 4271 /* Clear 'pending link event' flag */ 4272 BGE_STS_CLRBIT(sc, BGE_STS_LINK_EVT); 4273 4274 /* 4275 * Process link state changes. 4276 * Grrr. The link status word in the status block does 4277 * not work correctly on the BCM5700 rev AX and BX chips, 4278 * according to all available information. Hence, we have 4279 * to enable MII interrupts in order to properly obtain 4280 * async link changes. Unfortunately, this also means that 4281 * we have to read the MAC status register to detect link 4282 * changes, thereby adding an additional register access to 4283 * the interrupt handler. 4284 */ 4285 4286 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700) { 4287 status = CSR_READ_4(sc, BGE_MAC_STS); 4288 if (status & BGE_MACSTAT_MI_INTERRUPT) { 4289 mii_pollstat(mii); 4290 4291 if (!BGE_STS_BIT(sc, BGE_STS_LINK) && 4292 mii->mii_media_status & IFM_ACTIVE && 4293 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) 4294 BGE_STS_SETBIT(sc, BGE_STS_LINK); 4295 else if (BGE_STS_BIT(sc, BGE_STS_LINK) && 4296 (!(mii->mii_media_status & IFM_ACTIVE) || 4297 IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) 4298 BGE_STS_CLRBIT(sc, BGE_STS_LINK); 4299 4300 /* Clear the interrupt */ 4301 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, 4302 BGE_EVTENB_MI_INTERRUPT); 4303 bge_miibus_readreg(sc->bge_dev, 1, BRGPHY_MII_ISR); 4304 bge_miibus_writereg(sc->bge_dev, 1, BRGPHY_MII_IMR, 4305 BRGPHY_INTRS); 4306 } 4307 return; 4308 } 4309 4310 if (sc->bge_flags & BGE_PHY_FIBER_TBI) { 4311 status = CSR_READ_4(sc, BGE_MAC_STS); 4312 if (status & BGE_MACSTAT_TBI_PCS_SYNCHED) { 4313 if (!BGE_STS_BIT(sc, BGE_STS_LINK)) { 4314 BGE_STS_SETBIT(sc, BGE_STS_LINK); 4315 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) 4316 BGE_CLRBIT(sc, BGE_MAC_MODE, 4317 BGE_MACMODE_TBI_SEND_CFGS); 4318 CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF); 4319 if_link_state_change(ifp, LINK_STATE_UP); 4320 } 4321 } else if (BGE_STS_BIT(sc, BGE_STS_LINK)) { 4322 BGE_STS_CLRBIT(sc, BGE_STS_LINK); 4323 if_link_state_change(ifp, LINK_STATE_DOWN); 4324 } 4325 /* 4326 * Discard link events for MII/GMII cards if MI auto-polling disabled. 4327 * This should not happen since mii callouts are locked now, but 4328 * we keep this check for debug. 4329 */ 4330 } else if (BGE_STS_BIT(sc, BGE_STS_AUTOPOLL)) { 4331 /* 4332 * Some broken BCM chips have BGE_STATFLAG_LINKSTATE_CHANGED 4333 * bit in status word always set. Workaround this bug by 4334 * reading PHY link status directly. 4335 */ 4336 link = (CSR_READ_4(sc, BGE_MI_STS) & BGE_MISTS_LINK)? 4337 BGE_STS_LINK : 0; 4338 4339 if (BGE_STS_BIT(sc, BGE_STS_LINK) != link) { 4340 mii_pollstat(mii); 4341 4342 if (!BGE_STS_BIT(sc, BGE_STS_LINK) && 4343 mii->mii_media_status & IFM_ACTIVE && 4344 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) 4345 BGE_STS_SETBIT(sc, BGE_STS_LINK); 4346 else if (BGE_STS_BIT(sc, BGE_STS_LINK) && 4347 (!(mii->mii_media_status & IFM_ACTIVE) || 4348 IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) 4349 BGE_STS_CLRBIT(sc, BGE_STS_LINK); 4350 } 4351 } 4352 4353 /* Clear the attention */ 4354 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED| 4355 BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE| 4356 BGE_MACSTAT_LINK_CHANGED); 4357 } 4358 4359 static int 4360 sysctl_bge_verify(SYSCTLFN_ARGS) 4361 { 4362 int error, t; 4363 struct sysctlnode node; 4364 4365 node = *rnode; 4366 t = *(int*)rnode->sysctl_data; 4367 node.sysctl_data = &t; 4368 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 4369 if (error || newp == NULL) 4370 return (error); 4371 4372 #if 0 4373 DPRINTF2(("%s: t = %d, nodenum = %d, rnodenum = %d\n", __func__, t, 4374 node.sysctl_num, rnode->sysctl_num)); 4375 #endif 4376 4377 if (node.sysctl_num == bge_rxthresh_nodenum) { 4378 if (t < 0 || t >= NBGE_RX_THRESH) 4379 return (EINVAL); 4380 bge_update_all_threshes(t); 4381 } else 4382 return (EINVAL); 4383 4384 *(int*)rnode->sysctl_data = t; 4385 4386 return (0); 4387 } 4388 4389 /* 4390 * Set up sysctl(3) MIB, hw.bge.*. 4391 * 4392 * TBD condition SYSCTL_PERMANENT on being an LKM or not 4393 */ 4394 SYSCTL_SETUP(sysctl_bge, "sysctl bge subtree setup") 4395 { 4396 int rc, bge_root_num; 4397 const struct sysctlnode *node; 4398 4399 if ((rc = sysctl_createv(clog, 0, NULL, NULL, 4400 CTLFLAG_PERMANENT, CTLTYPE_NODE, "hw", NULL, 4401 NULL, 0, NULL, 0, CTL_HW, CTL_EOL)) != 0) { 4402 goto err; 4403 } 4404 4405 if ((rc = sysctl_createv(clog, 0, NULL, &node, 4406 CTLFLAG_PERMANENT, CTLTYPE_NODE, "bge", 4407 SYSCTL_DESCR("BGE interface controls"), 4408 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL)) != 0) { 4409 goto err; 4410 } 4411 4412 bge_root_num = node->sysctl_num; 4413 4414 /* BGE Rx interrupt mitigation level */ 4415 if ((rc = sysctl_createv(clog, 0, NULL, &node, 4416 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, 4417 CTLTYPE_INT, "rx_lvl", 4418 SYSCTL_DESCR("BGE receive interrupt mitigation level"), 4419 sysctl_bge_verify, 0, 4420 &bge_rx_thresh_lvl, 4421 0, CTL_HW, bge_root_num, CTL_CREATE, 4422 CTL_EOL)) != 0) { 4423 goto err; 4424 } 4425 4426 bge_rxthresh_nodenum = node->sysctl_num; 4427 4428 return; 4429 4430 err: 4431 aprint_error("%s: sysctl_createv failed (rc = %d)\n", __func__, rc); 4432 } 4433 4434 static int 4435 bge_get_eaddr_mem(struct bge_softc *sc, u_int8_t ether_addr[]) 4436 { 4437 u_int32_t mac_addr; 4438 4439 mac_addr = bge_readmem_ind(sc, 0x0c14); 4440 if ((mac_addr >> 16) == 0x484b) { 4441 ether_addr[0] = (uint8_t)(mac_addr >> 8); 4442 ether_addr[1] = (uint8_t)mac_addr; 4443 mac_addr = bge_readmem_ind(sc, 0x0c18); 4444 ether_addr[2] = (uint8_t)(mac_addr >> 24); 4445 ether_addr[3] = (uint8_t)(mac_addr >> 16); 4446 ether_addr[4] = (uint8_t)(mac_addr >> 8); 4447 ether_addr[5] = (uint8_t)mac_addr; 4448 return (0); 4449 } 4450 return (1); 4451 } 4452 4453 static int 4454 bge_get_eaddr_nvram(struct bge_softc *sc, u_int8_t ether_addr[]) 4455 { 4456 int mac_offset = BGE_EE_MAC_OFFSET; 4457 4458 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 4459 mac_offset = BGE_EE_MAC_OFFSET_5906; 4460 } 4461 4462 return (bge_read_nvram(sc, ether_addr, mac_offset + 2, 4463 ETHER_ADDR_LEN)); 4464 } 4465 4466 static int 4467 bge_get_eaddr_eeprom(struct bge_softc *sc, u_int8_t ether_addr[]) 4468 { 4469 4470 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 4471 return (1); 4472 } 4473 4474 return (bge_read_eeprom(sc, ether_addr, BGE_EE_MAC_OFFSET + 2, 4475 ETHER_ADDR_LEN)); 4476 } 4477 4478 static int 4479 bge_get_eaddr(struct bge_softc *sc, u_int8_t eaddr[]) 4480 { 4481 static const bge_eaddr_fcn_t bge_eaddr_funcs[] = { 4482 /* NOTE: Order is critical */ 4483 bge_get_eaddr_mem, 4484 bge_get_eaddr_nvram, 4485 bge_get_eaddr_eeprom, 4486 NULL 4487 }; 4488 const bge_eaddr_fcn_t *func; 4489 4490 for (func = bge_eaddr_funcs; *func != NULL; ++func) { 4491 if ((*func)(sc, eaddr) == 0) 4492 break; 4493 } 4494 return (*func == NULL ? ENXIO : 0); 4495 } 4496
Indexes created Mon Sep 22 13:09:51 GMT 2025