if_bge.c revision 1.171
1 /* $NetBSD: if_bge.c,v 1.171 2010/01/24 15:29:10 msaitoh Exp $ */ 2 3 /* 4 * Copyright (c) 2001 Wind River Systems 5 * Copyright (c) 1997, 1998, 1999, 2001 6 * Bill Paul <wpaul (at) windriver.com>. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Bill Paul. 19 * 4. Neither the name of the author nor the names of any co-contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 33 * THE POSSIBILITY OF SUCH DAMAGE. 34 * 35 * $FreeBSD: if_bge.c,v 1.13 2002/04/04 06:01:31 wpaul Exp $ 36 */ 37 38 /* 39 * Broadcom BCM570x family gigabit ethernet driver for NetBSD. 40 * 41 * NetBSD version by: 42 * 43 * Frank van der Linden <fvdl (at) wasabisystems.com> 44 * Jason Thorpe <thorpej (at) wasabisystems.com> 45 * Jonathan Stone <jonathan (at) dsg.stanford.edu> 46 * 47 * Originally written for FreeBSD by Bill Paul <wpaul (at) windriver.com> 48 * Senior Engineer, Wind River Systems 49 */ 50 51 /* 52 * The Broadcom BCM5700 is based on technology originally developed by 53 * Alteon Networks as part of the Tigon I and Tigon II gigabit ethernet 54 * MAC chips. The BCM5700, sometimes refered to as the Tigon III, has 55 * two on-board MIPS R4000 CPUs and can have as much as 16MB of external 56 * SSRAM. The BCM5700 supports TCP, UDP and IP checksum offload, jumbo 57 * frames, highly configurable RX filtering, and 16 RX and TX queues 58 * (which, along with RX filter rules, can be used for QOS applications). 59 * Other features, such as TCP segmentation, may be available as part 60 * of value-added firmware updates. Unlike the Tigon I and Tigon II, 61 * firmware images can be stored in hardware and need not be compiled 62 * into the driver. 63 * 64 * The BCM5700 supports the PCI v2.2 and PCI-X v1.0 standards, and will 65 * function in a 32-bit/64-bit 33/66MHz bus, or a 64-bit/133MHz bus. 66 * 67 * The BCM5701 is a single-chip solution incorporating both the BCM5700 68 * MAC and a BCM5401 10/100/1000 PHY. Unlike the BCM5700, the BCM5701 69 * does not support external SSRAM. 70 * 71 * Broadcom also produces a variation of the BCM5700 under the "Altima" 72 * brand name, which is functionally similar but lacks PCI-X support. 73 * 74 * Without external SSRAM, you can only have at most 4 TX rings, 75 * and the use of the mini RX ring is disabled. This seems to imply 76 * that these features are simply not available on the BCM5701. As a 77 * result, this driver does not implement any support for the mini RX 78 * ring. 79 */ 80 81 #include <sys/cdefs.h> 82 __KERNEL_RCSID(0, "$NetBSD: if_bge.c,v 1.171 2010/01/24 15:29:10 msaitoh Exp $"); 83 84 #include "vlan.h" 85 #include "rnd.h" 86 87 #include <sys/param.h> 88 #include <sys/systm.h> 89 #include <sys/callout.h> 90 #include <sys/sockio.h> 91 #include <sys/mbuf.h> 92 #include <sys/malloc.h> 93 #include <sys/kernel.h> 94 #include <sys/device.h> 95 #include <sys/socket.h> 96 #include <sys/sysctl.h> 97 98 #include <net/if.h> 99 #include <net/if_dl.h> 100 #include <net/if_media.h> 101 #include <net/if_ether.h> 102 103 #if NRND > 0 104 #include <sys/rnd.h> 105 #endif 106 107 #ifdef INET 108 #include <netinet/in.h> 109 #include <netinet/in_systm.h> 110 #include <netinet/in_var.h> 111 #include <netinet/ip.h> 112 #endif 113 114 /* Headers for TCP Segmentation Offload (TSO) */ 115 #include <netinet/in_systm.h> /* n_time for <netinet/ip.h>... */ 116 #include <netinet/in.h> /* ip_{src,dst}, for <netinet/ip.h> */ 117 #include <netinet/ip.h> /* for struct ip */ 118 #include <netinet/tcp.h> /* for struct tcphdr */ 119 120 121 #include <net/bpf.h> 122 123 #include <dev/pci/pcireg.h> 124 #include <dev/pci/pcivar.h> 125 #include <dev/pci/pcidevs.h> 126 127 #include <dev/mii/mii.h> 128 #include <dev/mii/miivar.h> 129 #include <dev/mii/miidevs.h> 130 #include <dev/mii/brgphyreg.h> 131 132 #include <dev/pci/if_bgereg.h> 133 #include <dev/pci/if_bgevar.h> 134 135 #include <uvm/uvm_extern.h> 136 #include <prop/proplib.h> 137 138 #define ETHER_MIN_NOPAD (ETHER_MIN_LEN - ETHER_CRC_LEN) /* i.e., 60 */ 139 140 141 /* 142 * Tunable thresholds for rx-side bge interrupt mitigation. 143 */ 144 145 /* 146 * The pairs of values below were obtained from empirical measurement 147 * on bcm5700 rev B2; they ar designed to give roughly 1 receive 148 * interrupt for every N packets received, where N is, approximately, 149 * the second value (rx_max_bds) in each pair. The values are chosen 150 * such that moving from one pair to the succeeding pair was observed 151 * to roughly halve interrupt rate under sustained input packet load. 152 * The values were empirically chosen to avoid overflowing internal 153 * limits on the bcm5700: inreasing rx_ticks much beyond 600 154 * results in internal wrapping and higher interrupt rates. 155 * The limit of 46 frames was chosen to match NFS workloads. 156 * 157 * These values also work well on bcm5701, bcm5704C, and (less 158 * tested) bcm5703. On other chipsets, (including the Altima chip 159 * family), the larger values may overflow internal chip limits, 160 * leading to increasing interrupt rates rather than lower interrupt 161 * rates. 162 * 163 * Applications using heavy interrupt mitigation (interrupting every 164 * 32 or 46 frames) in both directions may need to increase the TCP 165 * windowsize to above 131072 bytes (e.g., to 199608 bytes) to sustain 166 * full link bandwidth, due to ACKs and window updates lingering 167 * in the RX queue during the 30-to-40-frame interrupt-mitigation window. 168 */ 169 static const struct bge_load_rx_thresh { 170 int rx_ticks; 171 int rx_max_bds; } 172 bge_rx_threshes[] = { 173 { 32, 2 }, 174 { 50, 4 }, 175 { 100, 8 }, 176 { 192, 16 }, 177 { 416, 32 }, 178 { 598, 46 } 179 }; 180 #define NBGE_RX_THRESH (sizeof(bge_rx_threshes) / sizeof(bge_rx_threshes[0])) 181 182 /* XXX patchable; should be sysctl'able */ 183 static int bge_auto_thresh = 1; 184 static int bge_rx_thresh_lvl; 185 186 static int bge_rxthresh_nodenum; 187 188 typedef int (*bge_eaddr_fcn_t)(struct bge_softc *, uint8_t[]); 189 190 static int bge_probe(device_t, cfdata_t, void *); 191 static void bge_attach(device_t, device_t, void *); 192 static void bge_release_resources(struct bge_softc *); 193 static void bge_txeof(struct bge_softc *); 194 static void bge_rxeof(struct bge_softc *); 195 196 static int bge_get_eaddr_mem(struct bge_softc *, uint8_t[]); 197 static int bge_get_eaddr_nvram(struct bge_softc *, uint8_t[]); 198 static int bge_get_eaddr_eeprom(struct bge_softc *, uint8_t[]); 199 static int bge_get_eaddr(struct bge_softc *, uint8_t[]); 200 201 static void bge_tick(void *); 202 static void bge_stats_update(struct bge_softc *); 203 static int bge_encap(struct bge_softc *, struct mbuf *, uint32_t *); 204 205 static int bge_intr(void *); 206 static void bge_start(struct ifnet *); 207 static int bge_ioctl(struct ifnet *, u_long, void *); 208 static int bge_init(struct ifnet *); 209 static void bge_stop(struct ifnet *, int); 210 static void bge_watchdog(struct ifnet *); 211 static int bge_ifmedia_upd(struct ifnet *); 212 static void bge_ifmedia_sts(struct ifnet *, struct ifmediareq *); 213 214 static void bge_setmulti(struct bge_softc *); 215 216 static void bge_handle_events(struct bge_softc *); 217 static int bge_alloc_jumbo_mem(struct bge_softc *); 218 #if 0 /* XXX */ 219 static void bge_free_jumbo_mem(struct bge_softc *); 220 #endif 221 static void *bge_jalloc(struct bge_softc *); 222 static void bge_jfree(struct mbuf *, void *, size_t, void *); 223 static int bge_newbuf_std(struct bge_softc *, int, struct mbuf *, 224 bus_dmamap_t); 225 static int bge_newbuf_jumbo(struct bge_softc *, int, struct mbuf *); 226 static int bge_init_rx_ring_std(struct bge_softc *); 227 static void bge_free_rx_ring_std(struct bge_softc *); 228 static int bge_init_rx_ring_jumbo(struct bge_softc *); 229 static void bge_free_rx_ring_jumbo(struct bge_softc *); 230 static void bge_free_tx_ring(struct bge_softc *); 231 static int bge_init_tx_ring(struct bge_softc *); 232 233 static int bge_chipinit(struct bge_softc *); 234 static int bge_blockinit(struct bge_softc *); 235 static int bge_setpowerstate(struct bge_softc *, int); 236 237 static void bge_reset(struct bge_softc *); 238 static void bge_link_upd(struct bge_softc *); 239 240 #define BGE_DEBUG 241 #ifdef BGE_DEBUG 242 #define DPRINTF(x) if (bgedebug) printf x 243 #define DPRINTFN(n,x) if (bgedebug >= (n)) printf x 244 #define BGE_TSO_PRINTF(x) do { if (bge_tso_debug) printf x ;} while (0) 245 int bgedebug = 0; 246 int bge_tso_debug = 0; 247 #else 248 #define DPRINTF(x) 249 #define DPRINTFN(n,x) 250 #define BGE_TSO_PRINTF(x) 251 #endif 252 253 #ifdef BGE_EVENT_COUNTERS 254 #define BGE_EVCNT_INCR(ev) (ev).ev_count++ 255 #define BGE_EVCNT_ADD(ev, val) (ev).ev_count += (val) 256 #define BGE_EVCNT_UPD(ev, val) (ev).ev_count = (val) 257 #else 258 #define BGE_EVCNT_INCR(ev) /* nothing */ 259 #define BGE_EVCNT_ADD(ev, val) /* nothing */ 260 #define BGE_EVCNT_UPD(ev, val) /* nothing */ 261 #endif 262 263 static const struct bge_product { 264 pci_vendor_id_t bp_vendor; 265 pci_product_id_t bp_product; 266 const char *bp_name; 267 } bge_products[] = { 268 /* 269 * The BCM5700 documentation seems to indicate that the hardware 270 * still has the Alteon vendor ID burned into it, though it 271 * should always be overridden by the value in the EEPROM. We'll 272 * check for it anyway. 273 */ 274 { PCI_VENDOR_ALTEON, 275 PCI_PRODUCT_ALTEON_BCM5700, 276 "Broadcom BCM5700 Gigabit Ethernet", 277 }, 278 { PCI_VENDOR_ALTEON, 279 PCI_PRODUCT_ALTEON_BCM5701, 280 "Broadcom BCM5701 Gigabit Ethernet", 281 }, 282 { PCI_VENDOR_ALTIMA, 283 PCI_PRODUCT_ALTIMA_AC1000, 284 "Altima AC1000 Gigabit Ethernet", 285 }, 286 { PCI_VENDOR_ALTIMA, 287 PCI_PRODUCT_ALTIMA_AC1001, 288 "Altima AC1001 Gigabit Ethernet", 289 }, 290 { PCI_VENDOR_ALTIMA, 291 PCI_PRODUCT_ALTIMA_AC9100, 292 "Altima AC9100 Gigabit Ethernet", 293 }, 294 { PCI_VENDOR_BROADCOM, 295 PCI_PRODUCT_BROADCOM_BCM5700, 296 "Broadcom BCM5700 Gigabit Ethernet", 297 }, 298 { PCI_VENDOR_BROADCOM, 299 PCI_PRODUCT_BROADCOM_BCM5701, 300 "Broadcom BCM5701 Gigabit Ethernet", 301 }, 302 { PCI_VENDOR_BROADCOM, 303 PCI_PRODUCT_BROADCOM_BCM5702, 304 "Broadcom BCM5702 Gigabit Ethernet", 305 }, 306 { PCI_VENDOR_BROADCOM, 307 PCI_PRODUCT_BROADCOM_BCM5702X, 308 "Broadcom BCM5702X Gigabit Ethernet" }, 309 { PCI_VENDOR_BROADCOM, 310 PCI_PRODUCT_BROADCOM_BCM5703, 311 "Broadcom BCM5703 Gigabit Ethernet", 312 }, 313 { PCI_VENDOR_BROADCOM, 314 PCI_PRODUCT_BROADCOM_BCM5703X, 315 "Broadcom BCM5703X Gigabit Ethernet", 316 }, 317 { PCI_VENDOR_BROADCOM, 318 PCI_PRODUCT_BROADCOM_BCM5703_ALT, 319 "Broadcom BCM5703 Gigabit Ethernet", 320 }, 321 { PCI_VENDOR_BROADCOM, 322 PCI_PRODUCT_BROADCOM_BCM5704C, 323 "Broadcom BCM5704C Dual Gigabit Ethernet", 324 }, 325 { PCI_VENDOR_BROADCOM, 326 PCI_PRODUCT_BROADCOM_BCM5704S, 327 "Broadcom BCM5704S Dual Gigabit Ethernet", 328 }, 329 { PCI_VENDOR_BROADCOM, 330 PCI_PRODUCT_BROADCOM_BCM5705, 331 "Broadcom BCM5705 Gigabit Ethernet", 332 }, 333 { PCI_VENDOR_BROADCOM, 334 PCI_PRODUCT_BROADCOM_BCM5705K, 335 "Broadcom BCM5705K Gigabit Ethernet", 336 }, 337 { PCI_VENDOR_BROADCOM, 338 PCI_PRODUCT_BROADCOM_BCM5705M, 339 "Broadcom BCM5705M Gigabit Ethernet", 340 }, 341 { PCI_VENDOR_BROADCOM, 342 PCI_PRODUCT_BROADCOM_BCM5705M_ALT, 343 "Broadcom BCM5705M Gigabit Ethernet", 344 }, 345 { PCI_VENDOR_BROADCOM, 346 PCI_PRODUCT_BROADCOM_BCM5714, 347 "Broadcom BCM5714/5715 Gigabit Ethernet", 348 }, 349 { PCI_VENDOR_BROADCOM, 350 PCI_PRODUCT_BROADCOM_BCM5715, 351 "Broadcom BCM5714/5715 Gigabit Ethernet", 352 }, 353 { PCI_VENDOR_BROADCOM, 354 PCI_PRODUCT_BROADCOM_BCM5789, 355 "Broadcom BCM5789 Gigabit Ethernet", 356 }, 357 { PCI_VENDOR_BROADCOM, 358 PCI_PRODUCT_BROADCOM_BCM5721, 359 "Broadcom BCM5721 Gigabit Ethernet", 360 }, 361 { PCI_VENDOR_BROADCOM, 362 PCI_PRODUCT_BROADCOM_BCM5722, 363 "Broadcom BCM5722 Gigabit Ethernet", 364 }, 365 { PCI_VENDOR_BROADCOM, 366 PCI_PRODUCT_BROADCOM_BCM5750, 367 "Broadcom BCM5750 Gigabit Ethernet", 368 }, 369 { PCI_VENDOR_BROADCOM, 370 PCI_PRODUCT_BROADCOM_BCM5750M, 371 "Broadcom BCM5750M Gigabit Ethernet", 372 }, 373 { PCI_VENDOR_BROADCOM, 374 PCI_PRODUCT_BROADCOM_BCM5751, 375 "Broadcom BCM5751 Gigabit Ethernet", 376 }, 377 { PCI_VENDOR_BROADCOM, 378 PCI_PRODUCT_BROADCOM_BCM5751M, 379 "Broadcom BCM5751M Gigabit Ethernet", 380 }, 381 { PCI_VENDOR_BROADCOM, 382 PCI_PRODUCT_BROADCOM_BCM5752, 383 "Broadcom BCM5752 Gigabit Ethernet", 384 }, 385 { PCI_VENDOR_BROADCOM, 386 PCI_PRODUCT_BROADCOM_BCM5752M, 387 "Broadcom BCM5752M Gigabit Ethernet", 388 }, 389 { PCI_VENDOR_BROADCOM, 390 PCI_PRODUCT_BROADCOM_BCM5753, 391 "Broadcom BCM5753 Gigabit Ethernet", 392 }, 393 { PCI_VENDOR_BROADCOM, 394 PCI_PRODUCT_BROADCOM_BCM5753M, 395 "Broadcom BCM5753M Gigabit Ethernet", 396 }, 397 { PCI_VENDOR_BROADCOM, 398 PCI_PRODUCT_BROADCOM_BCM5754, 399 "Broadcom BCM5754 Gigabit Ethernet", 400 }, 401 { PCI_VENDOR_BROADCOM, 402 PCI_PRODUCT_BROADCOM_BCM5754M, 403 "Broadcom BCM5754M Gigabit Ethernet", 404 }, 405 { PCI_VENDOR_BROADCOM, 406 PCI_PRODUCT_BROADCOM_BCM5755, 407 "Broadcom BCM5755 Gigabit Ethernet", 408 }, 409 { PCI_VENDOR_BROADCOM, 410 PCI_PRODUCT_BROADCOM_BCM5755M, 411 "Broadcom BCM5755M Gigabit Ethernet", 412 }, 413 { PCI_VENDOR_BROADCOM, 414 PCI_PRODUCT_BROADCOM_BCM5780, 415 "Broadcom BCM5780 Gigabit Ethernet", 416 }, 417 { PCI_VENDOR_BROADCOM, 418 PCI_PRODUCT_BROADCOM_BCM5780S, 419 "Broadcom BCM5780S Gigabit Ethernet", 420 }, 421 { PCI_VENDOR_BROADCOM, 422 PCI_PRODUCT_BROADCOM_BCM5782, 423 "Broadcom BCM5782 Gigabit Ethernet", 424 }, 425 { PCI_VENDOR_BROADCOM, 426 PCI_PRODUCT_BROADCOM_BCM5786, 427 "Broadcom BCM5786 Gigabit Ethernet", 428 }, 429 { PCI_VENDOR_BROADCOM, 430 PCI_PRODUCT_BROADCOM_BCM5787, 431 "Broadcom BCM5787 Gigabit Ethernet", 432 }, 433 { PCI_VENDOR_BROADCOM, 434 PCI_PRODUCT_BROADCOM_BCM5787M, 435 "Broadcom BCM5787M Gigabit Ethernet", 436 }, 437 { PCI_VENDOR_BROADCOM, 438 PCI_PRODUCT_BROADCOM_BCM5788, 439 "Broadcom BCM5788 Gigabit Ethernet", 440 }, 441 { PCI_VENDOR_BROADCOM, 442 PCI_PRODUCT_BROADCOM_BCM5789, 443 "Broadcom BCM5789 Gigabit Ethernet", 444 }, 445 { PCI_VENDOR_BROADCOM, 446 PCI_PRODUCT_BROADCOM_BCM5901, 447 "Broadcom BCM5901 Fast Ethernet", 448 }, 449 { PCI_VENDOR_BROADCOM, 450 PCI_PRODUCT_BROADCOM_BCM5901A2, 451 "Broadcom BCM5901A2 Fast Ethernet", 452 }, 453 { PCI_VENDOR_SCHNEIDERKOCH, 454 PCI_PRODUCT_SCHNEIDERKOCH_SK_9DX1, 455 "SysKonnect SK-9Dx1 Gigabit Ethernet", 456 }, 457 { PCI_VENDOR_3COM, 458 PCI_PRODUCT_3COM_3C996, 459 "3Com 3c996 Gigabit Ethernet", 460 }, 461 { PCI_VENDOR_BROADCOM, 462 PCI_PRODUCT_BROADCOM_BCM5906, 463 "Broadcom BCM5906 Fast Ethernet", 464 }, 465 { PCI_VENDOR_BROADCOM, 466 PCI_PRODUCT_BROADCOM_BCM5906M, 467 "Broadcom BCM5906M Fast Ethernet", 468 }, 469 { 0, 470 0, 471 NULL }, 472 }; 473 474 /* 475 * XXX: how to handle variants based on 5750 and derivatives: 476 * 5750 5751, 5721, possibly 5714, 5752, and 5708?, which 477 * in general behave like a 5705, except with additional quirks. 478 * This driver's current handling of the 5721 is wrong; 479 * how we map ASIC revision to "quirks" needs more thought. 480 * (defined here until the thought is done). 481 */ 482 #define BGE_IS_5714_FAMILY(sc) \ 483 (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5714_A0 || \ 484 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5780 || \ 485 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5714 ) 486 487 #define BGE_IS_5750_OR_BEYOND(sc) \ 488 (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5750 || \ 489 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5752 || \ 490 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5755 || \ 491 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5787 || \ 492 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906 || \ 493 BGE_IS_5714_FAMILY(sc) ) 494 495 #define BGE_IS_5705_OR_BEYOND(sc) \ 496 (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5705 || \ 497 (BGE_IS_5750_OR_BEYOND(sc))) 498 499 #define BGE_IS_JUMBO_CAPABLE(sc) \ 500 (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || \ 501 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5701 || \ 502 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5703 || \ 503 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) 504 505 506 static const struct bge_revision { 507 uint32_t br_chipid; 508 const char *br_name; 509 } bge_revisions[] = { 510 { BGE_CHIPID_BCM5700_A0, "BCM5700 A0" }, 511 { BGE_CHIPID_BCM5700_A1, "BCM5700 A1" }, 512 { BGE_CHIPID_BCM5700_B0, "BCM5700 B0" }, 513 { BGE_CHIPID_BCM5700_B1, "BCM5700 B1" }, 514 { BGE_CHIPID_BCM5700_B2, "BCM5700 B2" }, 515 { BGE_CHIPID_BCM5700_B3, "BCM5700 B3" }, 516 /* This is treated like a BCM5700 Bx */ 517 { BGE_CHIPID_BCM5700_ALTIMA, "BCM5700 Altima" }, 518 { BGE_CHIPID_BCM5700_C0, "BCM5700 C0" }, 519 { BGE_CHIPID_BCM5701_A0, "BCM5701 A0" }, 520 { BGE_CHIPID_BCM5701_B0, "BCM5701 B0" }, 521 { BGE_CHIPID_BCM5701_B2, "BCM5701 B2" }, 522 { BGE_CHIPID_BCM5701_B5, "BCM5701 B5" }, 523 { BGE_CHIPID_BCM5703_A0, "BCM5703 A0" }, 524 { BGE_CHIPID_BCM5703_A1, "BCM5703 A1" }, 525 { BGE_CHIPID_BCM5703_A2, "BCM5703 A2" }, 526 { BGE_CHIPID_BCM5703_A3, "BCM5703 A3" }, 527 { BGE_CHIPID_BCM5703_B0, "BCM5703 B0" }, 528 { BGE_CHIPID_BCM5704_A0, "BCM5704 A0" }, 529 { BGE_CHIPID_BCM5704_A1, "BCM5704 A1" }, 530 { BGE_CHIPID_BCM5704_A2, "BCM5704 A2" }, 531 { BGE_CHIPID_BCM5704_A3, "BCM5704 A3" }, 532 { BGE_CHIPID_BCM5704_B0, "BCM5704 B0" }, 533 { BGE_CHIPID_BCM5705_A0, "BCM5705 A0" }, 534 { BGE_CHIPID_BCM5705_A1, "BCM5705 A1" }, 535 { BGE_CHIPID_BCM5705_A2, "BCM5705 A2" }, 536 { BGE_CHIPID_BCM5705_A3, "BCM5705 A3" }, 537 { BGE_CHIPID_BCM5750_A0, "BCM5750 A0" }, 538 { BGE_CHIPID_BCM5750_A1, "BCM5750 A1" }, 539 { BGE_CHIPID_BCM5750_A3, "BCM5750 A3" }, 540 { BGE_CHIPID_BCM5750_B0, "BCM5750 B0" }, 541 { BGE_CHIPID_BCM5750_B1, "BCM5750 B1" }, 542 { BGE_CHIPID_BCM5750_C0, "BCM5750 C0" }, 543 { BGE_CHIPID_BCM5750_C1, "BCM5750 C1" }, 544 { BGE_CHIPID_BCM5750_C2, "BCM5750 C2" }, 545 { BGE_CHIPID_BCM5752_A0, "BCM5752 A0" }, 546 { BGE_CHIPID_BCM5752_A1, "BCM5752 A1" }, 547 { BGE_CHIPID_BCM5752_A2, "BCM5752 A2" }, 548 { BGE_CHIPID_BCM5714_A0, "BCM5714 A0" }, 549 { BGE_CHIPID_BCM5714_B0, "BCM5714 B0" }, 550 { BGE_CHIPID_BCM5714_B3, "BCM5714 B3" }, 551 { BGE_CHIPID_BCM5715_A0, "BCM5715 A0" }, 552 { BGE_CHIPID_BCM5715_A1, "BCM5715 A1" }, 553 { BGE_CHIPID_BCM5715_A3, "BCM5715 A3" }, 554 { BGE_CHIPID_BCM5755_A0, "BCM5755 A0" }, 555 { BGE_CHIPID_BCM5755_A1, "BCM5755 A1" }, 556 { BGE_CHIPID_BCM5755_A2, "BCM5755 A2" }, 557 { BGE_CHIPID_BCM5755_C0, "BCM5755 C0" }, 558 { BGE_CHIPID_BCM5787_A0, "BCM5754/5787 A0" }, 559 { BGE_CHIPID_BCM5787_A1, "BCM5754/5787 A1" }, 560 { BGE_CHIPID_BCM5787_A2, "BCM5754/5787 A2" }, 561 { BGE_CHIPID_BCM5906_A1, "BCM5906 A1" }, 562 { BGE_CHIPID_BCM5906_A2, "BCM5906 A2" }, 563 { 0, NULL } 564 }; 565 566 /* 567 * Some defaults for major revisions, so that newer steppings 568 * that we don't know about have a shot at working. 569 */ 570 static const struct bge_revision bge_majorrevs[] = { 571 { BGE_ASICREV_BCM5700, "unknown BCM5700" }, 572 { BGE_ASICREV_BCM5701, "unknown BCM5701" }, 573 { BGE_ASICREV_BCM5703, "unknown BCM5703" }, 574 { BGE_ASICREV_BCM5704, "unknown BCM5704" }, 575 { BGE_ASICREV_BCM5705, "unknown BCM5705" }, 576 { BGE_ASICREV_BCM5750, "unknown BCM5750" }, 577 { BGE_ASICREV_BCM5714_A0, "unknown BCM5714" }, 578 { BGE_ASICREV_BCM5714, "unknown BCM5714" }, 579 { BGE_ASICREV_BCM5752, "unknown BCM5752 family" }, 580 { BGE_ASICREV_BCM5755, "unknown BCM5755" }, 581 { BGE_ASICREV_BCM5780, "unknown BCM5780" }, 582 /* 5754 and 5787 share the same ASIC ID */ 583 { BGE_ASICREV_BCM5787, "unknown BCM5754/5787" }, 584 { BGE_ASICREV_BCM5906, "unknown BCM5906" }, 585 { 0, NULL } 586 }; 587 588 CFATTACH_DECL_NEW(bge, sizeof(struct bge_softc), 589 bge_probe, bge_attach, NULL, NULL); 590 591 static uint32_t 592 bge_readmem_ind(struct bge_softc *sc, int off) 593 { 594 pcireg_t val; 595 596 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_BASEADDR, off); 597 val = pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_DATA); 598 return val; 599 } 600 601 static void 602 bge_writemem_ind(struct bge_softc *sc, int off, int val) 603 { 604 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_BASEADDR, off); 605 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_DATA, val); 606 } 607 608 #ifdef notdef 609 static uint32_t 610 bge_readreg_ind(struct bge_softc *sc, int off) 611 { 612 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_REG_BASEADDR, off); 613 return (pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_REG_DATA)); 614 } 615 #endif 616 617 static void 618 bge_writereg_ind(struct bge_softc *sc, int off, int val) 619 { 620 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_REG_BASEADDR, off); 621 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_REG_DATA, val); 622 } 623 624 static void 625 bge_writemem_direct(struct bge_softc *sc, int off, int val) 626 { 627 CSR_WRITE_4(sc, off, val); 628 } 629 630 static void 631 bge_writembx(struct bge_softc *sc, int off, int val) 632 { 633 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 634 off += BGE_LPMBX_IRQ0_HI - BGE_MBX_IRQ0_HI; 635 636 CSR_WRITE_4(sc, off, val); 637 } 638 639 static uint8_t 640 bge_nvram_getbyte(struct bge_softc *sc, int addr, uint8_t *dest) 641 { 642 uint32_t access, byte = 0; 643 int i; 644 645 /* Lock. */ 646 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_SET1); 647 for (i = 0; i < 8000; i++) { 648 if (CSR_READ_4(sc, BGE_NVRAM_SWARB) & BGE_NVRAMSWARB_GNT1) 649 break; 650 DELAY(20); 651 } 652 if (i == 8000) 653 return 1; 654 655 /* Enable access. */ 656 access = CSR_READ_4(sc, BGE_NVRAM_ACCESS); 657 CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access | BGE_NVRAMACC_ENABLE); 658 659 CSR_WRITE_4(sc, BGE_NVRAM_ADDR, addr & 0xfffffffc); 660 CSR_WRITE_4(sc, BGE_NVRAM_CMD, BGE_NVRAM_READCMD); 661 for (i = 0; i < BGE_TIMEOUT * 10; i++) { 662 DELAY(10); 663 if (CSR_READ_4(sc, BGE_NVRAM_CMD) & BGE_NVRAMCMD_DONE) { 664 DELAY(10); 665 break; 666 } 667 } 668 669 if (i == BGE_TIMEOUT * 10) { 670 aprint_error_dev(sc->bge_dev, "nvram read timed out\n"); 671 return 1; 672 } 673 674 /* Get result. */ 675 byte = CSR_READ_4(sc, BGE_NVRAM_RDDATA); 676 677 *dest = (bswap32(byte) >> ((addr % 4) * 8)) & 0xFF; 678 679 /* Disable access. */ 680 CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access); 681 682 /* Unlock. */ 683 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_CLR1); 684 CSR_READ_4(sc, BGE_NVRAM_SWARB); 685 686 return 0; 687 } 688 689 /* 690 * Read a sequence of bytes from NVRAM. 691 */ 692 static int 693 bge_read_nvram(struct bge_softc *sc, uint8_t *dest, int off, int cnt) 694 { 695 int err = 0, i; 696 uint8_t byte = 0; 697 698 if (BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5906) 699 return 1; 700 701 for (i = 0; i < cnt; i++) { 702 err = bge_nvram_getbyte(sc, off + i, &byte); 703 if (err) 704 break; 705 *(dest + i) = byte; 706 } 707 708 return (err ? 1 : 0); 709 } 710 711 /* 712 * Read a byte of data stored in the EEPROM at address 'addr.' The 713 * BCM570x supports both the traditional bitbang interface and an 714 * auto access interface for reading the EEPROM. We use the auto 715 * access method. 716 */ 717 static uint8_t 718 bge_eeprom_getbyte(struct bge_softc *sc, int addr, uint8_t *dest) 719 { 720 int i; 721 uint32_t byte = 0; 722 723 /* 724 * Enable use of auto EEPROM access so we can avoid 725 * having to use the bitbang method. 726 */ 727 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM); 728 729 /* Reset the EEPROM, load the clock period. */ 730 CSR_WRITE_4(sc, BGE_EE_ADDR, 731 BGE_EEADDR_RESET | BGE_EEHALFCLK(BGE_HALFCLK_384SCL)); 732 DELAY(20); 733 734 /* Issue the read EEPROM command. */ 735 CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr); 736 737 /* Wait for completion */ 738 for (i = 0; i < BGE_TIMEOUT * 10; i++) { 739 DELAY(10); 740 if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE) 741 break; 742 } 743 744 if (i == BGE_TIMEOUT) { 745 aprint_error_dev(sc->bge_dev, "eeprom read timed out\n"); 746 return 0; 747 } 748 749 /* Get result. */ 750 byte = CSR_READ_4(sc, BGE_EE_DATA); 751 752 *dest = (byte >> ((addr % 4) * 8)) & 0xFF; 753 754 return 0; 755 } 756 757 /* 758 * Read a sequence of bytes from the EEPROM. 759 */ 760 static int 761 bge_read_eeprom(struct bge_softc *sc, void *destv, int off, int cnt) 762 { 763 int err = 0, i; 764 uint8_t byte = 0; 765 char *dest = destv; 766 767 for (i = 0; i < cnt; i++) { 768 err = bge_eeprom_getbyte(sc, off + i, &byte); 769 if (err) 770 break; 771 *(dest + i) = byte; 772 } 773 774 return (err ? 1 : 0); 775 } 776 777 static int 778 bge_miibus_readreg(device_t dev, int phy, int reg) 779 { 780 struct bge_softc *sc = device_private(dev); 781 uint32_t val; 782 uint32_t saved_autopoll; 783 int i; 784 785 /* 786 * Broadcom's own driver always assumes the internal 787 * PHY is at GMII address 1. On some chips, the PHY responds 788 * to accesses at all addresses, which could cause us to 789 * bogusly attach the PHY 32 times at probe type. Always 790 * restricting the lookup to address 1 is simpler than 791 * trying to figure out which chips revisions should be 792 * special-cased. 793 */ 794 if (phy != 1) 795 return 0; 796 797 /* Reading with autopolling on may trigger PCI errors */ 798 saved_autopoll = CSR_READ_4(sc, BGE_MI_MODE); 799 if (saved_autopoll & BGE_MIMODE_AUTOPOLL) { 800 BGE_STS_CLRBIT(sc, BGE_STS_AUTOPOLL); 801 CSR_WRITE_4(sc, BGE_MI_MODE, 802 saved_autopoll &~ BGE_MIMODE_AUTOPOLL); 803 DELAY(40); 804 } 805 806 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_READ|BGE_MICOMM_BUSY| 807 BGE_MIPHY(phy)|BGE_MIREG(reg)); 808 809 for (i = 0; i < BGE_TIMEOUT; i++) { 810 val = CSR_READ_4(sc, BGE_MI_COMM); 811 if (!(val & BGE_MICOMM_BUSY)) 812 break; 813 delay(10); 814 } 815 816 if (i == BGE_TIMEOUT) { 817 aprint_error_dev(sc->bge_dev, "PHY read timed out\n"); 818 val = 0; 819 goto done; 820 } 821 822 val = CSR_READ_4(sc, BGE_MI_COMM); 823 824 done: 825 if (saved_autopoll & BGE_MIMODE_AUTOPOLL) { 826 BGE_STS_SETBIT(sc, BGE_STS_AUTOPOLL); 827 CSR_WRITE_4(sc, BGE_MI_MODE, saved_autopoll); 828 DELAY(40); 829 } 830 831 if (val & BGE_MICOMM_READFAIL) 832 return 0; 833 834 return (val & 0xFFFF); 835 } 836 837 static void 838 bge_miibus_writereg(device_t dev, int phy, int reg, int val) 839 { 840 struct bge_softc *sc = device_private(dev); 841 uint32_t saved_autopoll; 842 int i; 843 844 if (phy!=1) { 845 return; 846 } 847 848 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906 && 849 (reg == BRGPHY_MII_1000CTL || reg == BRGPHY_MII_AUXCTL)) { 850 return; 851 } 852 853 /* Reading with autopolling on may trigger PCI errors */ 854 saved_autopoll = CSR_READ_4(sc, BGE_MI_MODE); 855 if (saved_autopoll & BGE_MIMODE_AUTOPOLL) { 856 delay(40); 857 BGE_STS_CLRBIT(sc, BGE_STS_AUTOPOLL); 858 CSR_WRITE_4(sc, BGE_MI_MODE, 859 saved_autopoll & (~BGE_MIMODE_AUTOPOLL)); 860 delay(10); /* 40 usec is supposed to be adequate */ 861 } 862 863 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_WRITE | BGE_MICOMM_BUSY | 864 BGE_MIPHY(phy) | BGE_MIREG(reg)|val); 865 866 for (i = 0; i < BGE_TIMEOUT; i++) { 867 delay(10); 868 if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY)) { 869 delay(5); 870 CSR_READ_4(sc, BGE_MI_COMM); 871 break; 872 } 873 } 874 875 if (saved_autopoll & BGE_MIMODE_AUTOPOLL) { 876 BGE_STS_SETBIT(sc, BGE_STS_AUTOPOLL); 877 CSR_WRITE_4(sc, BGE_MI_MODE, saved_autopoll); 878 delay(40); 879 } 880 881 if (i == BGE_TIMEOUT) 882 aprint_error_dev(sc->bge_dev, "PHY read timed out\n"); 883 } 884 885 static void 886 bge_miibus_statchg(device_t dev) 887 { 888 struct bge_softc *sc = device_private(dev); 889 struct mii_data *mii = &sc->bge_mii; 890 891 /* 892 * Get flow control negotiation result. 893 */ 894 if (IFM_SUBTYPE(mii->mii_media.ifm_cur->ifm_media) == IFM_AUTO && 895 (mii->mii_media_active & IFM_ETH_FMASK) != sc->bge_flowflags) { 896 sc->bge_flowflags = mii->mii_media_active & IFM_ETH_FMASK; 897 mii->mii_media_active &= ~IFM_ETH_FMASK; 898 } 899 900 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_PORTMODE); 901 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T || 902 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX) 903 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_GMII); 904 else 905 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_MII); 906 907 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) 908 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX); 909 else 910 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX); 911 912 /* 913 * 802.3x flow control 914 */ 915 if (sc->bge_flowflags & IFM_ETH_RXPAUSE) 916 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_FLOWCTL_ENABLE); 917 else 918 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_FLOWCTL_ENABLE); 919 920 if (sc->bge_flowflags & IFM_ETH_TXPAUSE) 921 BGE_SETBIT(sc, BGE_TX_MODE, BGE_TXMODE_FLOWCTL_ENABLE); 922 else 923 BGE_CLRBIT(sc, BGE_TX_MODE, BGE_TXMODE_FLOWCTL_ENABLE); 924 } 925 926 /* 927 * Update rx threshold levels to values in a particular slot 928 * of the interrupt-mitigation table bge_rx_threshes. 929 */ 930 static void 931 bge_set_thresh(struct ifnet *ifp, int lvl) 932 { 933 struct bge_softc *sc = ifp->if_softc; 934 int s; 935 936 /* For now, just save the new Rx-intr thresholds and record 937 * that a threshold update is pending. Updating the hardware 938 * registers here (even at splhigh()) is observed to 939 * occasionaly cause glitches where Rx-interrupts are not 940 * honoured for up to 10 seconds. jonathan (at) NetBSD.org, 2003-04-05 941 */ 942 s = splnet(); 943 sc->bge_rx_coal_ticks = bge_rx_threshes[lvl].rx_ticks; 944 sc->bge_rx_max_coal_bds = bge_rx_threshes[lvl].rx_max_bds; 945 sc->bge_pending_rxintr_change = 1; 946 splx(s); 947 948 return; 949 } 950 951 952 /* 953 * Update Rx thresholds of all bge devices 954 */ 955 static void 956 bge_update_all_threshes(int lvl) 957 { 958 struct ifnet *ifp; 959 const char * const namebuf = "bge"; 960 int namelen; 961 962 if (lvl < 0) 963 lvl = 0; 964 else if (lvl >= NBGE_RX_THRESH) 965 lvl = NBGE_RX_THRESH - 1; 966 967 namelen = strlen(namebuf); 968 /* 969 * Now search all the interfaces for this name/number 970 */ 971 IFNET_FOREACH(ifp) { 972 if (strncmp(ifp->if_xname, namebuf, namelen) != 0) 973 continue; 974 /* We got a match: update if doing auto-threshold-tuning */ 975 if (bge_auto_thresh) 976 bge_set_thresh(ifp, lvl); 977 } 978 } 979 980 /* 981 * Handle events that have triggered interrupts. 982 */ 983 static void 984 bge_handle_events(struct bge_softc *sc) 985 { 986 987 return; 988 } 989 990 /* 991 * Memory management for jumbo frames. 992 */ 993 994 static int 995 bge_alloc_jumbo_mem(struct bge_softc *sc) 996 { 997 char *ptr, *kva; 998 bus_dma_segment_t seg; 999 int i, rseg, state, error; 1000 struct bge_jpool_entry *entry; 1001 1002 state = error = 0; 1003 1004 /* Grab a big chunk o' storage. */ 1005 if (bus_dmamem_alloc(sc->bge_dmatag, BGE_JMEM, PAGE_SIZE, 0, 1006 &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 1007 aprint_error_dev(sc->bge_dev, "can't alloc rx buffers\n"); 1008 return ENOBUFS; 1009 } 1010 1011 state = 1; 1012 if (bus_dmamem_map(sc->bge_dmatag, &seg, rseg, BGE_JMEM, (void **)&kva, 1013 BUS_DMA_NOWAIT)) { 1014 aprint_error_dev(sc->bge_dev, 1015 "can't map DMA buffers (%d bytes)\n", (int)BGE_JMEM); 1016 error = ENOBUFS; 1017 goto out; 1018 } 1019 1020 state = 2; 1021 if (bus_dmamap_create(sc->bge_dmatag, BGE_JMEM, 1, BGE_JMEM, 0, 1022 BUS_DMA_NOWAIT, &sc->bge_cdata.bge_rx_jumbo_map)) { 1023 aprint_error_dev(sc->bge_dev, "can't create DMA map\n"); 1024 error = ENOBUFS; 1025 goto out; 1026 } 1027 1028 state = 3; 1029 if (bus_dmamap_load(sc->bge_dmatag, sc->bge_cdata.bge_rx_jumbo_map, 1030 kva, BGE_JMEM, NULL, BUS_DMA_NOWAIT)) { 1031 aprint_error_dev(sc->bge_dev, "can't load DMA map\n"); 1032 error = ENOBUFS; 1033 goto out; 1034 } 1035 1036 state = 4; 1037 sc->bge_cdata.bge_jumbo_buf = (void *)kva; 1038 DPRINTFN(1,("bge_jumbo_buf = %p\n", sc->bge_cdata.bge_jumbo_buf)); 1039 1040 SLIST_INIT(&sc->bge_jfree_listhead); 1041 SLIST_INIT(&sc->bge_jinuse_listhead); 1042 1043 /* 1044 * Now divide it up into 9K pieces and save the addresses 1045 * in an array. 1046 */ 1047 ptr = sc->bge_cdata.bge_jumbo_buf; 1048 for (i = 0; i < BGE_JSLOTS; i++) { 1049 sc->bge_cdata.bge_jslots[i] = ptr; 1050 ptr += BGE_JLEN; 1051 entry = malloc(sizeof(struct bge_jpool_entry), 1052 M_DEVBUF, M_NOWAIT); 1053 if (entry == NULL) { 1054 aprint_error_dev(sc->bge_dev, 1055 "no memory for jumbo buffer queue!\n"); 1056 error = ENOBUFS; 1057 goto out; 1058 } 1059 entry->slot = i; 1060 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, 1061 entry, jpool_entries); 1062 } 1063 out: 1064 if (error != 0) { 1065 switch (state) { 1066 case 4: 1067 bus_dmamap_unload(sc->bge_dmatag, 1068 sc->bge_cdata.bge_rx_jumbo_map); 1069 case 3: 1070 bus_dmamap_destroy(sc->bge_dmatag, 1071 sc->bge_cdata.bge_rx_jumbo_map); 1072 case 2: 1073 bus_dmamem_unmap(sc->bge_dmatag, kva, BGE_JMEM); 1074 case 1: 1075 bus_dmamem_free(sc->bge_dmatag, &seg, rseg); 1076 break; 1077 default: 1078 break; 1079 } 1080 } 1081 1082 return error; 1083 } 1084 1085 /* 1086 * Allocate a jumbo buffer. 1087 */ 1088 static void * 1089 bge_jalloc(struct bge_softc *sc) 1090 { 1091 struct bge_jpool_entry *entry; 1092 1093 entry = SLIST_FIRST(&sc->bge_jfree_listhead); 1094 1095 if (entry == NULL) { 1096 aprint_error_dev(sc->bge_dev, "no free jumbo buffers\n"); 1097 return NULL; 1098 } 1099 1100 SLIST_REMOVE_HEAD(&sc->bge_jfree_listhead, jpool_entries); 1101 SLIST_INSERT_HEAD(&sc->bge_jinuse_listhead, entry, jpool_entries); 1102 return (sc->bge_cdata.bge_jslots[entry->slot]); 1103 } 1104 1105 /* 1106 * Release a jumbo buffer. 1107 */ 1108 static void 1109 bge_jfree(struct mbuf *m, void *buf, size_t size, void *arg) 1110 { 1111 struct bge_jpool_entry *entry; 1112 struct bge_softc *sc; 1113 int i, s; 1114 1115 /* Extract the softc struct pointer. */ 1116 sc = (struct bge_softc *)arg; 1117 1118 if (sc == NULL) 1119 panic("bge_jfree: can't find softc pointer!"); 1120 1121 /* calculate the slot this buffer belongs to */ 1122 1123 i = ((char *)buf 1124 - (char *)sc->bge_cdata.bge_jumbo_buf) / BGE_JLEN; 1125 1126 if ((i < 0) || (i >= BGE_JSLOTS)) 1127 panic("bge_jfree: asked to free buffer that we don't manage!"); 1128 1129 s = splvm(); 1130 entry = SLIST_FIRST(&sc->bge_jinuse_listhead); 1131 if (entry == NULL) 1132 panic("bge_jfree: buffer not in use!"); 1133 entry->slot = i; 1134 SLIST_REMOVE_HEAD(&sc->bge_jinuse_listhead, jpool_entries); 1135 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, entry, jpool_entries); 1136 1137 if (__predict_true(m != NULL)) 1138 pool_cache_put(mb_cache, m); 1139 splx(s); 1140 } 1141 1142 1143 /* 1144 * Intialize a standard receive ring descriptor. 1145 */ 1146 static int 1147 bge_newbuf_std(struct bge_softc *sc, int i, struct mbuf *m, bus_dmamap_t dmamap) 1148 { 1149 struct mbuf *m_new = NULL; 1150 struct bge_rx_bd *r; 1151 int error; 1152 1153 if (dmamap == NULL) { 1154 error = bus_dmamap_create(sc->bge_dmatag, MCLBYTES, 1, 1155 MCLBYTES, 0, BUS_DMA_NOWAIT, &dmamap); 1156 if (error != 0) 1157 return error; 1158 } 1159 1160 sc->bge_cdata.bge_rx_std_map[i] = dmamap; 1161 1162 if (m == NULL) { 1163 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1164 if (m_new == NULL) 1165 return ENOBUFS; 1166 1167 MCLGET(m_new, M_DONTWAIT); 1168 if (!(m_new->m_flags & M_EXT)) { 1169 m_freem(m_new); 1170 return ENOBUFS; 1171 } 1172 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1173 1174 } else { 1175 m_new = m; 1176 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1177 m_new->m_data = m_new->m_ext.ext_buf; 1178 } 1179 if (!(sc->bge_flags & BGE_RX_ALIGNBUG)) 1180 m_adj(m_new, ETHER_ALIGN); 1181 if (bus_dmamap_load_mbuf(sc->bge_dmatag, dmamap, m_new, 1182 BUS_DMA_READ|BUS_DMA_NOWAIT)) 1183 return ENOBUFS; 1184 bus_dmamap_sync(sc->bge_dmatag, dmamap, 0, dmamap->dm_mapsize, 1185 BUS_DMASYNC_PREREAD); 1186 1187 sc->bge_cdata.bge_rx_std_chain[i] = m_new; 1188 r = &sc->bge_rdata->bge_rx_std_ring[i]; 1189 bge_set_hostaddr(&r->bge_addr, 1190 dmamap->dm_segs[0].ds_addr); 1191 r->bge_flags = BGE_RXBDFLAG_END; 1192 r->bge_len = m_new->m_len; 1193 r->bge_idx = i; 1194 1195 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 1196 offsetof(struct bge_ring_data, bge_rx_std_ring) + 1197 i * sizeof (struct bge_rx_bd), 1198 sizeof (struct bge_rx_bd), 1199 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1200 1201 return 0; 1202 } 1203 1204 /* 1205 * Initialize a jumbo receive ring descriptor. This allocates 1206 * a jumbo buffer from the pool managed internally by the driver. 1207 */ 1208 static int 1209 bge_newbuf_jumbo(struct bge_softc *sc, int i, struct mbuf *m) 1210 { 1211 struct mbuf *m_new = NULL; 1212 struct bge_rx_bd *r; 1213 void *buf = NULL; 1214 1215 if (m == NULL) { 1216 1217 /* Allocate the mbuf. */ 1218 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1219 if (m_new == NULL) 1220 return ENOBUFS; 1221 1222 /* Allocate the jumbo buffer */ 1223 buf = bge_jalloc(sc); 1224 if (buf == NULL) { 1225 m_freem(m_new); 1226 aprint_error_dev(sc->bge_dev, 1227 "jumbo allocation failed -- packet dropped!\n"); 1228 return ENOBUFS; 1229 } 1230 1231 /* Attach the buffer to the mbuf. */ 1232 m_new->m_len = m_new->m_pkthdr.len = BGE_JUMBO_FRAMELEN; 1233 MEXTADD(m_new, buf, BGE_JUMBO_FRAMELEN, M_DEVBUF, 1234 bge_jfree, sc); 1235 m_new->m_flags |= M_EXT_RW; 1236 } else { 1237 m_new = m; 1238 buf = m_new->m_data = m_new->m_ext.ext_buf; 1239 m_new->m_ext.ext_size = BGE_JUMBO_FRAMELEN; 1240 } 1241 if (!(sc->bge_flags & BGE_RX_ALIGNBUG)) 1242 m_adj(m_new, ETHER_ALIGN); 1243 bus_dmamap_sync(sc->bge_dmatag, sc->bge_cdata.bge_rx_jumbo_map, 1244 mtod(m_new, char *) - (char *)sc->bge_cdata.bge_jumbo_buf, BGE_JLEN, 1245 BUS_DMASYNC_PREREAD); 1246 /* Set up the descriptor. */ 1247 r = &sc->bge_rdata->bge_rx_jumbo_ring[i]; 1248 sc->bge_cdata.bge_rx_jumbo_chain[i] = m_new; 1249 bge_set_hostaddr(&r->bge_addr, BGE_JUMBO_DMA_ADDR(sc, m_new)); 1250 r->bge_flags = BGE_RXBDFLAG_END|BGE_RXBDFLAG_JUMBO_RING; 1251 r->bge_len = m_new->m_len; 1252 r->bge_idx = i; 1253 1254 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 1255 offsetof(struct bge_ring_data, bge_rx_jumbo_ring) + 1256 i * sizeof (struct bge_rx_bd), 1257 sizeof (struct bge_rx_bd), 1258 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1259 1260 return 0; 1261 } 1262 1263 /* 1264 * The standard receive ring has 512 entries in it. At 2K per mbuf cluster, 1265 * that's 1MB or memory, which is a lot. For now, we fill only the first 1266 * 256 ring entries and hope that our CPU is fast enough to keep up with 1267 * the NIC. 1268 */ 1269 static int 1270 bge_init_rx_ring_std(struct bge_softc *sc) 1271 { 1272 int i; 1273 1274 if (sc->bge_flags & BGE_RXRING_VALID) 1275 return 0; 1276 1277 for (i = 0; i < BGE_SSLOTS; i++) { 1278 if (bge_newbuf_std(sc, i, NULL, 0) == ENOBUFS) 1279 return ENOBUFS; 1280 } 1281 1282 sc->bge_std = i - 1; 1283 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std); 1284 1285 sc->bge_flags |= BGE_RXRING_VALID; 1286 1287 return 0; 1288 } 1289 1290 static void 1291 bge_free_rx_ring_std(struct bge_softc *sc) 1292 { 1293 int i; 1294 1295 if (!(sc->bge_flags & BGE_RXRING_VALID)) 1296 return; 1297 1298 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { 1299 if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) { 1300 m_freem(sc->bge_cdata.bge_rx_std_chain[i]); 1301 sc->bge_cdata.bge_rx_std_chain[i] = NULL; 1302 bus_dmamap_destroy(sc->bge_dmatag, 1303 sc->bge_cdata.bge_rx_std_map[i]); 1304 } 1305 memset((char *)&sc->bge_rdata->bge_rx_std_ring[i], 0, 1306 sizeof(struct bge_rx_bd)); 1307 } 1308 1309 sc->bge_flags &= ~BGE_RXRING_VALID; 1310 } 1311 1312 static int 1313 bge_init_rx_ring_jumbo(struct bge_softc *sc) 1314 { 1315 int i; 1316 volatile struct bge_rcb *rcb; 1317 1318 if (sc->bge_flags & BGE_JUMBO_RXRING_VALID) 1319 return 0; 1320 1321 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 1322 if (bge_newbuf_jumbo(sc, i, NULL) == ENOBUFS) 1323 return ENOBUFS; 1324 }; 1325 1326 sc->bge_jumbo = i - 1; 1327 sc->bge_flags |= BGE_JUMBO_RXRING_VALID; 1328 1329 rcb = &sc->bge_rdata->bge_info.bge_jumbo_rx_rcb; 1330 rcb->bge_maxlen_flags = 0; 1331 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 1332 1333 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo); 1334 1335 return 0; 1336 } 1337 1338 static void 1339 bge_free_rx_ring_jumbo(struct bge_softc *sc) 1340 { 1341 int i; 1342 1343 if (!(sc->bge_flags & BGE_JUMBO_RXRING_VALID)) 1344 return; 1345 1346 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 1347 if (sc->bge_cdata.bge_rx_jumbo_chain[i] != NULL) { 1348 m_freem(sc->bge_cdata.bge_rx_jumbo_chain[i]); 1349 sc->bge_cdata.bge_rx_jumbo_chain[i] = NULL; 1350 } 1351 memset((char *)&sc->bge_rdata->bge_rx_jumbo_ring[i], 0, 1352 sizeof(struct bge_rx_bd)); 1353 } 1354 1355 sc->bge_flags &= ~BGE_JUMBO_RXRING_VALID; 1356 } 1357 1358 static void 1359 bge_free_tx_ring(struct bge_softc *sc) 1360 { 1361 int i, freed; 1362 struct txdmamap_pool_entry *dma; 1363 1364 if (!(sc->bge_flags & BGE_TXRING_VALID)) 1365 return; 1366 1367 freed = 0; 1368 1369 for (i = 0; i < BGE_TX_RING_CNT; i++) { 1370 if (sc->bge_cdata.bge_tx_chain[i] != NULL) { 1371 freed++; 1372 m_freem(sc->bge_cdata.bge_tx_chain[i]); 1373 sc->bge_cdata.bge_tx_chain[i] = NULL; 1374 SLIST_INSERT_HEAD(&sc->txdma_list, sc->txdma[i], 1375 link); 1376 sc->txdma[i] = 0; 1377 } 1378 memset((char *)&sc->bge_rdata->bge_tx_ring[i], 0, 1379 sizeof(struct bge_tx_bd)); 1380 } 1381 1382 while ((dma = SLIST_FIRST(&sc->txdma_list))) { 1383 SLIST_REMOVE_HEAD(&sc->txdma_list, link); 1384 bus_dmamap_destroy(sc->bge_dmatag, dma->dmamap); 1385 free(dma, M_DEVBUF); 1386 } 1387 1388 sc->bge_flags &= ~BGE_TXRING_VALID; 1389 } 1390 1391 static int 1392 bge_init_tx_ring(struct bge_softc *sc) 1393 { 1394 int i; 1395 bus_dmamap_t dmamap; 1396 struct txdmamap_pool_entry *dma; 1397 1398 if (sc->bge_flags & BGE_TXRING_VALID) 1399 return 0; 1400 1401 sc->bge_txcnt = 0; 1402 sc->bge_tx_saved_considx = 0; 1403 1404 /* Initialize transmit producer index for host-memory send ring. */ 1405 sc->bge_tx_prodidx = 0; 1406 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx); 1407 /* 5700 b2 errata */ 1408 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX) 1409 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx); 1410 1411 /* NIC-memory send ring not used; initialize to zero. */ 1412 bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0); 1413 /* 5700 b2 errata */ 1414 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX) 1415 bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0); 1416 1417 SLIST_INIT(&sc->txdma_list); 1418 for (i = 0; i < BGE_RSLOTS; i++) { 1419 if (bus_dmamap_create(sc->bge_dmatag, BGE_TXDMA_MAX, 1420 BGE_NTXSEG, ETHER_MAX_LEN_JUMBO, 0, BUS_DMA_NOWAIT, 1421 &dmamap)) 1422 return ENOBUFS; 1423 if (dmamap == NULL) 1424 panic("dmamap NULL in bge_init_tx_ring"); 1425 dma = malloc(sizeof(*dma), M_DEVBUF, M_NOWAIT); 1426 if (dma == NULL) { 1427 aprint_error_dev(sc->bge_dev, 1428 "can't alloc txdmamap_pool_entry\n"); 1429 bus_dmamap_destroy(sc->bge_dmatag, dmamap); 1430 return ENOMEM; 1431 } 1432 dma->dmamap = dmamap; 1433 SLIST_INSERT_HEAD(&sc->txdma_list, dma, link); 1434 } 1435 1436 sc->bge_flags |= BGE_TXRING_VALID; 1437 1438 return 0; 1439 } 1440 1441 static void 1442 bge_setmulti(struct bge_softc *sc) 1443 { 1444 struct ethercom *ac = &sc->ethercom; 1445 struct ifnet *ifp = &ac->ec_if; 1446 struct ether_multi *enm; 1447 struct ether_multistep step; 1448 uint32_t hashes[4] = { 0, 0, 0, 0 }; 1449 uint32_t h; 1450 int i; 1451 1452 if (ifp->if_flags & IFF_PROMISC) 1453 goto allmulti; 1454 1455 /* Now program new ones. */ 1456 ETHER_FIRST_MULTI(step, ac, enm); 1457 while (enm != NULL) { 1458 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1459 /* 1460 * We must listen to a range of multicast addresses. 1461 * For now, just accept all multicasts, rather than 1462 * trying to set only those filter bits needed to match 1463 * the range. (At this time, the only use of address 1464 * ranges is for IP multicast routing, for which the 1465 * range is big enough to require all bits set.) 1466 */ 1467 goto allmulti; 1468 } 1469 1470 h = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN); 1471 1472 /* Just want the 7 least-significant bits. */ 1473 h &= 0x7f; 1474 1475 hashes[(h & 0x60) >> 5] |= 1 << (h & 0x1F); 1476 ETHER_NEXT_MULTI(step, enm); 1477 } 1478 1479 ifp->if_flags &= ~IFF_ALLMULTI; 1480 goto setit; 1481 1482 allmulti: 1483 ifp->if_flags |= IFF_ALLMULTI; 1484 hashes[0] = hashes[1] = hashes[2] = hashes[3] = 0xffffffff; 1485 1486 setit: 1487 for (i = 0; i < 4; i++) 1488 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]); 1489 } 1490 1491 const int bge_swapbits[] = { 1492 0, 1493 BGE_MODECTL_BYTESWAP_DATA, 1494 BGE_MODECTL_WORDSWAP_DATA, 1495 BGE_MODECTL_BYTESWAP_NONFRAME, 1496 BGE_MODECTL_WORDSWAP_NONFRAME, 1497 1498 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA, 1499 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_BYTESWAP_NONFRAME, 1500 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_NONFRAME, 1501 1502 BGE_MODECTL_WORDSWAP_DATA|BGE_MODECTL_BYTESWAP_NONFRAME, 1503 BGE_MODECTL_WORDSWAP_DATA|BGE_MODECTL_WORDSWAP_NONFRAME, 1504 1505 BGE_MODECTL_BYTESWAP_NONFRAME|BGE_MODECTL_WORDSWAP_NONFRAME, 1506 1507 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA| 1508 BGE_MODECTL_BYTESWAP_NONFRAME, 1509 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA| 1510 BGE_MODECTL_WORDSWAP_NONFRAME, 1511 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_BYTESWAP_NONFRAME| 1512 BGE_MODECTL_WORDSWAP_NONFRAME, 1513 BGE_MODECTL_WORDSWAP_DATA|BGE_MODECTL_BYTESWAP_NONFRAME| 1514 BGE_MODECTL_WORDSWAP_NONFRAME, 1515 1516 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA| 1517 BGE_MODECTL_BYTESWAP_NONFRAME|BGE_MODECTL_WORDSWAP_NONFRAME, 1518 }; 1519 1520 int bge_swapindex = 0; 1521 1522 /* 1523 * Do endian, PCI and DMA initialization. Also check the on-board ROM 1524 * self-test results. 1525 */ 1526 static int 1527 bge_chipinit(struct bge_softc *sc) 1528 { 1529 int i; 1530 uint32_t dma_rw_ctl; 1531 1532 1533 /* Set endianness before we access any non-PCI registers. */ 1534 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MISC_CTL, 1535 BGE_INIT); 1536 1537 /* Set power state to D0. */ 1538 bge_setpowerstate(sc, 0); 1539 1540 /* 1541 * Check the 'ROM failed' bit on the RX CPU to see if 1542 * self-tests passed. 1543 */ 1544 if (CSR_READ_4(sc, BGE_RXCPU_MODE) & BGE_RXCPUMODE_ROMFAIL) { 1545 aprint_error_dev(sc->bge_dev, 1546 "RX CPU self-diagnostics failed!\n"); 1547 return ENODEV; 1548 } 1549 1550 /* Clear the MAC control register */ 1551 CSR_WRITE_4(sc, BGE_MAC_MODE, 0); 1552 1553 /* 1554 * Clear the MAC statistics block in the NIC's 1555 * internal memory. 1556 */ 1557 for (i = BGE_STATS_BLOCK; 1558 i < BGE_STATS_BLOCK_END + 1; i += sizeof(uint32_t)) 1559 BGE_MEMWIN_WRITE(sc->sc_pc, sc->sc_pcitag, i, 0); 1560 1561 for (i = BGE_STATUS_BLOCK; 1562 i < BGE_STATUS_BLOCK_END + 1; i += sizeof(uint32_t)) 1563 BGE_MEMWIN_WRITE(sc->sc_pc, sc->sc_pcitag, i, 0); 1564 1565 /* Set up the PCI DMA control register. */ 1566 dma_rw_ctl = BGE_PCI_READ_CMD | BGE_PCI_WRITE_CMD; 1567 if (sc->bge_flags & BGE_PCIE) { 1568 /* Read watermark not used, 128 bytes for write. */ 1569 DPRINTFN(4, ("(%s: PCI-Express DMA setting)\n", 1570 device_xname(sc->bge_dev))); 1571 dma_rw_ctl |= (0x3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT); 1572 } else if (sc->bge_flags & BGE_PCIX) { 1573 DPRINTFN(4, ("(:%s: PCI-X DMA setting)\n", 1574 device_xname(sc->bge_dev))); 1575 /* PCI-X bus */ 1576 dma_rw_ctl |= (0x3 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) | 1577 (0x3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT) | 1578 (0x0F); 1579 /* 1580 * 5703 and 5704 need ONEDMA_AT_ONCE as a workaround 1581 * for hardware bugs, which means we should also clear 1582 * the low-order MINDMA bits. In addition, the 5704 1583 * uses a different encoding of read/write watermarks. 1584 */ 1585 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) { 1586 dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD | 1587 /* should be 0x1f0000 */ 1588 (0x7 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) | 1589 (0x3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT); 1590 dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE; 1591 } 1592 else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5703) { 1593 dma_rw_ctl &= 0xfffffff0; 1594 dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE; 1595 } 1596 else if (BGE_IS_5714_FAMILY(sc)) { 1597 dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD; 1598 dma_rw_ctl &= ~BGE_PCIDMARWCTL_ONEDMA_ATONCE; /* XXX */ 1599 /* XXX magic values, Broadcom-supplied Linux driver */ 1600 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5780) 1601 dma_rw_ctl |= (1 << 20) | (1 << 18) | 1602 BGE_PCIDMARWCTL_ONEDMA_ATONCE; 1603 else 1604 dma_rw_ctl |= (1<<20) | (1<<18) | (1 << 15); 1605 } 1606 } else { 1607 /* Conventional PCI bus */ 1608 DPRINTFN(4, ("(%s: PCI 2.2 DMA setting)\n", 1609 device_xname(sc->bge_dev))); 1610 dma_rw_ctl = (0x7 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) | 1611 (0x7 << BGE_PCIDMARWCTL_WR_WAT_SHIFT); 1612 if (BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5705 && 1613 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5750) 1614 dma_rw_ctl |= 0x0F; 1615 } 1616 1617 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 1618 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5701) 1619 dma_rw_ctl |= BGE_PCIDMARWCTL_USE_MRM | 1620 BGE_PCIDMARWCTL_ASRT_ALL_BE; 1621 1622 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5703 || 1623 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) 1624 dma_rw_ctl &= ~BGE_PCIDMARWCTL_MINDMA; 1625 1626 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_DMA_RW_CTL, dma_rw_ctl); 1627 1628 /* 1629 * Set up general mode register. 1630 */ 1631 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS | 1632 BGE_MODECTL_MAC_ATTN_INTR | BGE_MODECTL_HOST_SEND_BDS | 1633 BGE_MODECTL_TX_NO_PHDR_CSUM | BGE_MODECTL_RX_NO_PHDR_CSUM); 1634 1635 /* 1636 * Disable memory write invalidate. Apparently it is not supported 1637 * properly by these devices. 1638 */ 1639 PCI_CLRBIT(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CMD, PCIM_CMD_MWIEN); 1640 1641 1642 #ifdef __brokenalpha__ 1643 /* 1644 * Must insure that we do not cross an 8K (bytes) boundary 1645 * for DMA reads. Our highest limit is 1K bytes. This is a 1646 * restriction on some ALPHA platforms with early revision 1647 * 21174 PCI chipsets, such as the AlphaPC 164lx 1648 */ 1649 PCI_SETBIT(sc, BGE_PCI_DMA_RW_CTL, BGE_PCI_READ_BNDRY_1024, 4); 1650 #endif 1651 1652 /* Set the timer prescaler (always 66MHz) */ 1653 CSR_WRITE_4(sc, BGE_MISC_CFG, 65 << 1/*BGE_32BITTIME_66MHZ*/); 1654 1655 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 1656 DELAY(40); /* XXX */ 1657 1658 /* Put PHY into ready state */ 1659 BGE_CLRBIT(sc, BGE_MISC_CFG, BGE_MISCCFG_EPHY_IDDQ); 1660 CSR_READ_4(sc, BGE_MISC_CFG); /* Flush */ 1661 DELAY(40); 1662 } 1663 1664 return 0; 1665 } 1666 1667 static int 1668 bge_blockinit(struct bge_softc *sc) 1669 { 1670 volatile struct bge_rcb *rcb; 1671 bus_size_t rcb_addr; 1672 int i; 1673 struct ifnet *ifp = &sc->ethercom.ec_if; 1674 bge_hostaddr taddr; 1675 uint32_t val; 1676 1677 /* 1678 * Initialize the memory window pointer register so that 1679 * we can access the first 32K of internal NIC RAM. This will 1680 * allow us to set up the TX send ring RCBs and the RX return 1681 * ring RCBs, plus other things which live in NIC memory. 1682 */ 1683 1684 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_BASEADDR, 0); 1685 1686 /* Configure mbuf memory pool */ 1687 if (!(BGE_IS_5705_OR_BEYOND(sc))) { 1688 if (sc->bge_extram) { 1689 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, 1690 BGE_EXT_SSRAM); 1691 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) 1692 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000); 1693 else 1694 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000); 1695 } else { 1696 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, 1697 BGE_BUFFPOOL_1); 1698 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) 1699 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000); 1700 else 1701 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000); 1702 } 1703 1704 /* Configure DMA resource pool */ 1705 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_BASEADDR, 1706 BGE_DMA_DESCRIPTORS); 1707 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LEN, 0x2000); 1708 } 1709 1710 /* Configure mbuf pool watermarks */ 1711 #ifdef ORIG_WPAUL_VALUES 1712 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 24); 1713 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 24); 1714 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 48); 1715 #else 1716 1717 /* new broadcom docs strongly recommend these: */ 1718 if (!BGE_IS_5705_OR_BEYOND(sc)) { 1719 if (ifp->if_mtu > ETHER_MAX_LEN) { 1720 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x50); 1721 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x20); 1722 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60); 1723 } else { 1724 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 304); 1725 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 152); 1726 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 380); 1727 } 1728 } else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 1729 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0); 1730 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x04); 1731 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x10); 1732 } else { 1733 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0); 1734 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x10); 1735 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60); 1736 } 1737 #endif 1738 1739 /* Configure DMA resource watermarks */ 1740 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5); 1741 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10); 1742 1743 /* Enable buffer manager */ 1744 if (!BGE_IS_5705_OR_BEYOND(sc)) { 1745 CSR_WRITE_4(sc, BGE_BMAN_MODE, 1746 BGE_BMANMODE_ENABLE | BGE_BMANMODE_LOMBUF_ATTN); 1747 1748 /* Poll for buffer manager start indication */ 1749 for (i = 0; i < BGE_TIMEOUT; i++) { 1750 if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE) 1751 break; 1752 DELAY(10); 1753 } 1754 1755 if (i == BGE_TIMEOUT) { 1756 aprint_error_dev(sc->bge_dev, 1757 "buffer manager failed to start\n"); 1758 return ENXIO; 1759 } 1760 } 1761 1762 /* Enable flow-through queues */ 1763 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 1764 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 1765 1766 /* Wait until queue initialization is complete */ 1767 for (i = 0; i < BGE_TIMEOUT; i++) { 1768 if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0) 1769 break; 1770 DELAY(10); 1771 } 1772 1773 if (i == BGE_TIMEOUT) { 1774 aprint_error_dev(sc->bge_dev, 1775 "flow-through queue init failed\n"); 1776 return ENXIO; 1777 } 1778 1779 /* Initialize the standard RX ring control block */ 1780 rcb = &sc->bge_rdata->bge_info.bge_std_rx_rcb; 1781 bge_set_hostaddr(&rcb->bge_hostaddr, 1782 BGE_RING_DMA_ADDR(sc, bge_rx_std_ring)); 1783 if (BGE_IS_5705_OR_BEYOND(sc)) 1784 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(512, 0); 1785 else 1786 rcb->bge_maxlen_flags = 1787 BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 0); 1788 if (sc->bge_extram) 1789 rcb->bge_nicaddr = BGE_EXT_STD_RX_RINGS; 1790 else 1791 rcb->bge_nicaddr = BGE_STD_RX_RINGS; 1792 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcb->bge_hostaddr.bge_addr_hi); 1793 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcb->bge_hostaddr.bge_addr_lo); 1794 CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 1795 CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcb->bge_nicaddr); 1796 1797 if (BGE_IS_5705_OR_BEYOND(sc)) 1798 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT_5705; 1799 else 1800 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT; 1801 1802 /* 1803 * Initialize the jumbo RX ring control block 1804 * We set the 'ring disabled' bit in the flags 1805 * field until we're actually ready to start 1806 * using this ring (i.e. once we set the MTU 1807 * high enough to require it). 1808 */ 1809 if (BGE_IS_JUMBO_CAPABLE(sc)) { 1810 rcb = &sc->bge_rdata->bge_info.bge_jumbo_rx_rcb; 1811 bge_set_hostaddr(&rcb->bge_hostaddr, 1812 BGE_RING_DMA_ADDR(sc, bge_rx_jumbo_ring)); 1813 rcb->bge_maxlen_flags = 1814 BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 1815 BGE_RCB_FLAG_RING_DISABLED); 1816 if (sc->bge_extram) 1817 rcb->bge_nicaddr = BGE_EXT_JUMBO_RX_RINGS; 1818 else 1819 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS; 1820 1821 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI, 1822 rcb->bge_hostaddr.bge_addr_hi); 1823 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO, 1824 rcb->bge_hostaddr.bge_addr_lo); 1825 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, 1826 rcb->bge_maxlen_flags); 1827 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcb->bge_nicaddr); 1828 1829 /* Set up dummy disabled mini ring RCB */ 1830 rcb = &sc->bge_rdata->bge_info.bge_mini_rx_rcb; 1831 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0, 1832 BGE_RCB_FLAG_RING_DISABLED); 1833 CSR_WRITE_4(sc, BGE_RX_MINI_RCB_MAXLEN_FLAGS, 1834 rcb->bge_maxlen_flags); 1835 1836 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 1837 offsetof(struct bge_ring_data, bge_info), 1838 sizeof (struct bge_gib), 1839 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1840 } 1841 1842 /* 1843 * Set the BD ring replenish thresholds. The recommended 1844 * values are 1/8th the number of descriptors allocated to 1845 * each ring. 1846 */ 1847 i = BGE_STD_RX_RING_CNT / 8; 1848 1849 /* 1850 * Use a value of 8 for the following chips to workaround HW errata. 1851 * Some of these chips have been added based on empirical 1852 * evidence (they don't work unless this is done). 1853 */ 1854 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5750 || 1855 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5752 || 1856 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5755 || 1857 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5787 || 1858 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 1859 i = 8; 1860 1861 CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, i); 1862 CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH, BGE_JUMBO_RX_RING_CNT / 8); 1863 1864 /* 1865 * Disable all unused send rings by setting the 'ring disabled' 1866 * bit in the flags field of all the TX send ring control blocks. 1867 * These are located in NIC memory. 1868 */ 1869 rcb_addr = BGE_MEMWIN_START + BGE_SEND_RING_RCB; 1870 for (i = 0; i < BGE_TX_RINGS_EXTSSRAM_MAX; i++) { 1871 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 1872 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED)); 1873 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 0); 1874 rcb_addr += sizeof(struct bge_rcb); 1875 } 1876 1877 /* Configure TX RCB 0 (we use only the first ring) */ 1878 rcb_addr = BGE_MEMWIN_START + BGE_SEND_RING_RCB; 1879 bge_set_hostaddr(&taddr, BGE_RING_DMA_ADDR(sc, bge_tx_ring)); 1880 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi); 1881 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo); 1882 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 1883 BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT)); 1884 if (!(BGE_IS_5705_OR_BEYOND(sc))) 1885 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 1886 BGE_RCB_MAXLEN_FLAGS(BGE_TX_RING_CNT, 0)); 1887 1888 /* Disable all unused RX return rings */ 1889 rcb_addr = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB; 1890 for (i = 0; i < BGE_RX_RINGS_MAX; i++) { 1891 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_hi, 0); 1892 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_lo, 0); 1893 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 1894 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 1895 BGE_RCB_FLAG_RING_DISABLED)); 1896 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 0); 1897 bge_writembx(sc, BGE_MBX_RX_CONS0_LO + 1898 (i * (sizeof(uint64_t))), 0); 1899 rcb_addr += sizeof(struct bge_rcb); 1900 } 1901 1902 /* Initialize RX ring indexes */ 1903 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, 0); 1904 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0); 1905 bge_writembx(sc, BGE_MBX_RX_MINI_PROD_LO, 0); 1906 1907 /* 1908 * Set up RX return ring 0 1909 * Note that the NIC address for RX return rings is 0x00000000. 1910 * The return rings live entirely within the host, so the 1911 * nicaddr field in the RCB isn't used. 1912 */ 1913 rcb_addr = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB; 1914 bge_set_hostaddr(&taddr, BGE_RING_DMA_ADDR(sc, bge_rx_return_ring)); 1915 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi); 1916 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo); 1917 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 0x00000000); 1918 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 1919 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 0)); 1920 1921 /* Set random backoff seed for TX */ 1922 CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF, 1923 CLLADDR(ifp->if_sadl)[0] + CLLADDR(ifp->if_sadl)[1] + 1924 CLLADDR(ifp->if_sadl)[2] + CLLADDR(ifp->if_sadl)[3] + 1925 CLLADDR(ifp->if_sadl)[4] + CLLADDR(ifp->if_sadl)[5] + 1926 BGE_TX_BACKOFF_SEED_MASK); 1927 1928 /* Set inter-packet gap */ 1929 CSR_WRITE_4(sc, BGE_TX_LENGTHS, 0x2620); 1930 1931 /* 1932 * Specify which ring to use for packets that don't match 1933 * any RX rules. 1934 */ 1935 CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08); 1936 1937 /* 1938 * Configure number of RX lists. One interrupt distribution 1939 * list, sixteen active lists, one bad frames class. 1940 */ 1941 CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181); 1942 1943 /* Inialize RX list placement stats mask. */ 1944 CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF); 1945 CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1); 1946 1947 /* Disable host coalescing until we get it set up */ 1948 CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000); 1949 1950 /* Poll to make sure it's shut down. */ 1951 for (i = 0; i < BGE_TIMEOUT; i++) { 1952 if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE)) 1953 break; 1954 DELAY(10); 1955 } 1956 1957 if (i == BGE_TIMEOUT) { 1958 aprint_error_dev(sc->bge_dev, 1959 "host coalescing engine failed to idle\n"); 1960 return ENXIO; 1961 } 1962 1963 /* Set up host coalescing defaults */ 1964 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bge_rx_coal_ticks); 1965 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bge_tx_coal_ticks); 1966 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bge_rx_max_coal_bds); 1967 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bge_tx_max_coal_bds); 1968 if (!(BGE_IS_5705_OR_BEYOND(sc))) { 1969 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT, 0); 1970 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT, 0); 1971 } 1972 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 0); 1973 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 0); 1974 1975 /* Set up address of statistics block */ 1976 if (!(BGE_IS_5705_OR_BEYOND(sc))) { 1977 bge_set_hostaddr(&taddr, 1978 BGE_RING_DMA_ADDR(sc, bge_info.bge_stats)); 1979 CSR_WRITE_4(sc, BGE_HCC_STATS_TICKS, sc->bge_stat_ticks); 1980 CSR_WRITE_4(sc, BGE_HCC_STATS_BASEADDR, BGE_STATS_BLOCK); 1981 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_HI, taddr.bge_addr_hi); 1982 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_LO, taddr.bge_addr_lo); 1983 } 1984 1985 /* Set up address of status block */ 1986 bge_set_hostaddr(&taddr, BGE_RING_DMA_ADDR(sc, bge_status_block)); 1987 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_BASEADDR, BGE_STATUS_BLOCK); 1988 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI, taddr.bge_addr_hi); 1989 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO, taddr.bge_addr_lo); 1990 sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx = 0; 1991 sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx = 0; 1992 1993 /* Turn on host coalescing state machine */ 1994 CSR_WRITE_4(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE); 1995 1996 /* Turn on RX BD completion state machine and enable attentions */ 1997 CSR_WRITE_4(sc, BGE_RBDC_MODE, 1998 BGE_RBDCMODE_ENABLE | BGE_RBDCMODE_ATTN); 1999 2000 /* Turn on RX list placement state machine */ 2001 CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 2002 2003 /* Turn on RX list selector state machine. */ 2004 if (!(BGE_IS_5705_OR_BEYOND(sc))) 2005 CSR_WRITE_4(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 2006 2007 val = BGE_MACMODE_TXDMA_ENB | BGE_MACMODE_RXDMA_ENB | 2008 BGE_MACMODE_RX_STATS_CLEAR | BGE_MACMODE_TX_STATS_CLEAR | 2009 BGE_MACMODE_RX_STATS_ENB | BGE_MACMODE_TX_STATS_ENB | 2010 BGE_MACMODE_FRMHDR_DMA_ENB; 2011 2012 if (sc->bge_flags & BGE_PHY_FIBER_TBI) 2013 val |= BGE_PORTMODE_TBI; 2014 else if (sc->bge_flags & BGE_PHY_FIBER_MII) 2015 val |= BGE_PORTMODE_GMII; 2016 else 2017 val |= BGE_PORTMODE_MII; 2018 2019 /* Turn on DMA, clear stats */ 2020 CSR_WRITE_4(sc, BGE_MAC_MODE, val); 2021 2022 2023 /* Set misc. local control, enable interrupts on attentions */ 2024 sc->bge_local_ctrl_reg = BGE_MLC_INTR_ONATTN | BGE_MLC_AUTO_EEPROM; 2025 2026 #ifdef notdef 2027 /* Assert GPIO pins for PHY reset */ 2028 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUT0| 2029 BGE_MLC_MISCIO_OUT1|BGE_MLC_MISCIO_OUT2); 2030 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUTEN0| 2031 BGE_MLC_MISCIO_OUTEN1|BGE_MLC_MISCIO_OUTEN2); 2032 #endif 2033 2034 #if defined(not_quite_yet) 2035 /* Linux driver enables enable gpio pin #1 on 5700s */ 2036 if (sc->bge_chipid == BGE_CHIPID_BCM5700) { 2037 sc->bge_local_ctrl_reg |= 2038 (BGE_MLC_MISCIO_OUT1|BGE_MLC_MISCIO_OUTEN1); 2039 } 2040 #endif 2041 CSR_WRITE_4(sc, BGE_MISC_LOCAL_CTL, sc->bge_local_ctrl_reg); 2042 2043 /* Turn on DMA completion state machine */ 2044 if (!(BGE_IS_5705_OR_BEYOND(sc))) 2045 CSR_WRITE_4(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 2046 2047 /* Turn on write DMA state machine */ 2048 { 2049 uint32_t bge_wdma_mode = 2050 BGE_WDMAMODE_ENABLE|BGE_WDMAMODE_ALL_ATTNS; 2051 2052 /* Enable host coalescing bug fix; see Linux tg3.c */ 2053 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5755 || 2054 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5787) 2055 bge_wdma_mode |= (1 << 29); 2056 2057 CSR_WRITE_4(sc, BGE_WDMA_MODE, bge_wdma_mode); 2058 } 2059 2060 /* Turn on read DMA state machine */ 2061 { 2062 uint32_t dma_read_modebits; 2063 2064 dma_read_modebits = 2065 BGE_RDMAMODE_ENABLE | BGE_RDMAMODE_ALL_ATTNS; 2066 2067 if ((sc->bge_flags & BGE_PCIE) && 0) { 2068 dma_read_modebits |= BGE_RDMA_MODE_FIFO_LONG_BURST; 2069 } else if (BGE_IS_5705_OR_BEYOND(sc)) { 2070 dma_read_modebits |= BGE_RDMA_MODE_FIFO_SIZE_128; 2071 } 2072 2073 /* XXX broadcom-supplied linux driver; undocumented */ 2074 if (BGE_IS_5750_OR_BEYOND(sc)) { 2075 /* 2076 * XXX: magic values. 2077 * From Broadcom-supplied Linux driver; apparently 2078 * required to workaround a DMA bug affecting TSO 2079 * on bcm575x/bcm5721? 2080 */ 2081 dma_read_modebits |= (1 << 27); 2082 } 2083 CSR_WRITE_4(sc, BGE_RDMA_MODE, dma_read_modebits); 2084 } 2085 2086 /* Turn on RX data completion state machine */ 2087 CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 2088 2089 /* Turn on RX BD initiator state machine */ 2090 CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 2091 2092 /* Turn on RX data and RX BD initiator state machine */ 2093 CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE); 2094 2095 /* Turn on Mbuf cluster free state machine */ 2096 if (!(BGE_IS_5705_OR_BEYOND(sc))) 2097 CSR_WRITE_4(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 2098 2099 /* Turn on send BD completion state machine */ 2100 CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 2101 2102 /* Turn on send data completion state machine */ 2103 CSR_WRITE_4(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE); 2104 2105 /* Turn on send data initiator state machine */ 2106 if (BGE_IS_5750_OR_BEYOND(sc)) { 2107 /* XXX: magic value from Linux driver */ 2108 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE | 0x08); 2109 } else { 2110 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 2111 } 2112 2113 /* Turn on send BD initiator state machine */ 2114 CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 2115 2116 /* Turn on send BD selector state machine */ 2117 CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 2118 2119 CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF); 2120 CSR_WRITE_4(sc, BGE_SDI_STATS_CTL, 2121 BGE_SDISTATSCTL_ENABLE | BGE_SDISTATSCTL_FASTER); 2122 2123 /* ack/clear link change events */ 2124 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED | 2125 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE | 2126 BGE_MACSTAT_CFG_CHANGED); 2127 CSR_WRITE_4(sc, BGE_MI_STS, 0); 2128 2129 /* Enable PHY auto polling (for MII/GMII only) */ 2130 if (sc->bge_flags & BGE_PHY_FIBER_TBI) { 2131 CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK); 2132 } else { 2133 BGE_STS_SETBIT(sc, BGE_STS_AUTOPOLL); 2134 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL | (10 << 16)); 2135 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700) 2136 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, 2137 BGE_EVTENB_MI_INTERRUPT); 2138 } 2139 2140 /* 2141 * Clear any pending link state attention. 2142 * Otherwise some link state change events may be lost until attention 2143 * is cleared by bge_intr() -> bge_link_upd() sequence. 2144 * It's not necessary on newer BCM chips - perhaps enabling link 2145 * state change attentions implies clearing pending attention. 2146 */ 2147 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED | 2148 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE | 2149 BGE_MACSTAT_LINK_CHANGED); 2150 2151 /* Enable link state change attentions. */ 2152 BGE_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED); 2153 2154 return 0; 2155 } 2156 2157 static const struct bge_revision * 2158 bge_lookup_rev(uint32_t chipid) 2159 { 2160 const struct bge_revision *br; 2161 2162 for (br = bge_revisions; br->br_name != NULL; br++) { 2163 if (br->br_chipid == chipid) 2164 return br; 2165 } 2166 2167 for (br = bge_majorrevs; br->br_name != NULL; br++) { 2168 if (br->br_chipid == BGE_ASICREV(chipid)) 2169 return br; 2170 } 2171 2172 return NULL; 2173 } 2174 2175 static const struct bge_product * 2176 bge_lookup(const struct pci_attach_args *pa) 2177 { 2178 const struct bge_product *bp; 2179 2180 for (bp = bge_products; bp->bp_name != NULL; bp++) { 2181 if (PCI_VENDOR(pa->pa_id) == bp->bp_vendor && 2182 PCI_PRODUCT(pa->pa_id) == bp->bp_product) 2183 return bp; 2184 } 2185 2186 return NULL; 2187 } 2188 2189 static int 2190 bge_setpowerstate(struct bge_softc *sc, int powerlevel) 2191 { 2192 #ifdef NOTYET 2193 uint32_t pm_ctl = 0; 2194 2195 /* XXX FIXME: make sure indirect accesses enabled? */ 2196 pm_ctl = pci_conf_read(sc->bge_dev, BGE_PCI_MISC_CTL, 4); 2197 pm_ctl |= BGE_PCIMISCCTL_INDIRECT_ACCESS; 2198 pci_write_config(sc->bge_dev, BGE_PCI_MISC_CTL, pm_ctl, 4); 2199 2200 /* clear the PME_assert bit and power state bits, enable PME */ 2201 pm_ctl = pci_conf_read(sc->bge_dev, BGE_PCI_PWRMGMT_CMD, 2); 2202 pm_ctl &= ~PCIM_PSTAT_DMASK; 2203 pm_ctl |= (1 << 8); 2204 2205 if (powerlevel == 0) { 2206 pm_ctl |= PCIM_PSTAT_D0; 2207 pci_write_config(sc->bge_dev, BGE_PCI_PWRMGMT_CMD, 2208 pm_ctl, 2); 2209 DELAY(10000); 2210 CSR_WRITE_4(sc, BGE_MISC_LOCAL_CTL, sc->bge_local_ctrl_reg); 2211 DELAY(10000); 2212 2213 #ifdef NOTYET 2214 /* XXX FIXME: write 0x02 to phy aux_Ctrl reg */ 2215 bge_miibus_writereg(sc->bge_dev, 1, 0x18, 0x02); 2216 #endif 2217 DELAY(40); DELAY(40); DELAY(40); 2218 DELAY(10000); /* above not quite adequate on 5700 */ 2219 return 0; 2220 } 2221 2222 2223 /* 2224 * Entering ACPI power states D1-D3 is achieved by wiggling 2225 * GMII gpio pins. Example code assumes all hardware vendors 2226 * followed Broadom's sample pcb layout. Until we verify that 2227 * for all supported OEM cards, states D1-D3 are unsupported. 2228 */ 2229 aprint_error_dev(sc->bge_dev, 2230 "power state %d unimplemented; check GPIO pins\n", 2231 powerlevel); 2232 #endif 2233 return EOPNOTSUPP; 2234 } 2235 2236 2237 /* 2238 * Probe for a Broadcom chip. Check the PCI vendor and device IDs 2239 * against our list and return its name if we find a match. Note 2240 * that since the Broadcom controller contains VPD support, we 2241 * can get the device name string from the controller itself instead 2242 * of the compiled-in string. This is a little slow, but it guarantees 2243 * we'll always announce the right product name. 2244 */ 2245 static int 2246 bge_probe(device_t parent, cfdata_t match, void *aux) 2247 { 2248 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 2249 2250 if (bge_lookup(pa) != NULL) 2251 return 1; 2252 2253 return 0; 2254 } 2255 2256 static void 2257 bge_attach(device_t parent, device_t self, void *aux) 2258 { 2259 struct bge_softc *sc = device_private(self); 2260 struct pci_attach_args *pa = aux; 2261 prop_dictionary_t dict; 2262 const struct bge_product *bp; 2263 const struct bge_revision *br; 2264 pci_chipset_tag_t pc; 2265 pci_intr_handle_t ih; 2266 const char *intrstr = NULL; 2267 bus_dma_segment_t seg; 2268 int rseg; 2269 uint32_t hwcfg = 0; 2270 uint32_t command; 2271 struct ifnet *ifp; 2272 uint32_t misccfg; 2273 void * kva; 2274 u_char eaddr[ETHER_ADDR_LEN]; 2275 pcireg_t memtype; 2276 bus_addr_t memaddr; 2277 bus_size_t memsize; 2278 uint32_t pm_ctl; 2279 2280 bp = bge_lookup(pa); 2281 KASSERT(bp != NULL); 2282 2283 sc->sc_pc = pa->pa_pc; 2284 sc->sc_pcitag = pa->pa_tag; 2285 sc->bge_dev = self; 2286 2287 aprint_naive(": Ethernet controller\n"); 2288 aprint_normal(": %s\n", bp->bp_name); 2289 2290 /* 2291 * Map control/status registers. 2292 */ 2293 DPRINTFN(5, ("Map control/status regs\n")); 2294 pc = sc->sc_pc; 2295 command = pci_conf_read(pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG); 2296 command |= PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_MASTER_ENABLE; 2297 pci_conf_write(pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG, command); 2298 command = pci_conf_read(pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG); 2299 2300 if (!(command & PCI_COMMAND_MEM_ENABLE)) { 2301 aprint_error_dev(sc->bge_dev, 2302 "failed to enable memory mapping!\n"); 2303 return; 2304 } 2305 2306 DPRINTFN(5, ("pci_mem_find\n")); 2307 memtype = pci_mapreg_type(sc->sc_pc, sc->sc_pcitag, BGE_PCI_BAR0); 2308 switch (memtype) { 2309 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 2310 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 2311 if (pci_mapreg_map(pa, BGE_PCI_BAR0, 2312 memtype, 0, &sc->bge_btag, &sc->bge_bhandle, 2313 &memaddr, &memsize) == 0) 2314 break; 2315 default: 2316 aprint_error_dev(sc->bge_dev, "can't find mem space\n"); 2317 return; 2318 } 2319 2320 DPRINTFN(5, ("pci_intr_map\n")); 2321 if (pci_intr_map(pa, &ih)) { 2322 aprint_error_dev(sc->bge_dev, "couldn't map interrupt\n"); 2323 return; 2324 } 2325 2326 DPRINTFN(5, ("pci_intr_string\n")); 2327 intrstr = pci_intr_string(pc, ih); 2328 2329 DPRINTFN(5, ("pci_intr_establish\n")); 2330 sc->bge_intrhand = pci_intr_establish(pc, ih, IPL_NET, bge_intr, sc); 2331 2332 if (sc->bge_intrhand == NULL) { 2333 aprint_error_dev(sc->bge_dev, 2334 "couldn't establish interrupt%s%s\n", 2335 intrstr ? " at " : "", intrstr ? intrstr : ""); 2336 return; 2337 } 2338 aprint_normal_dev(sc->bge_dev, "interrupting at %s\n", intrstr); 2339 2340 /* 2341 * Kludge for 5700 Bx bug: a hardware bug (PCIX byte enable?) 2342 * can clobber the chip's PCI config-space power control registers, 2343 * leaving the card in D3 powersave state. 2344 * We do not have memory-mapped registers in this state, 2345 * so force device into D0 state before starting initialization. 2346 */ 2347 pm_ctl = pci_conf_read(pc, sc->sc_pcitag, BGE_PCI_PWRMGMT_CMD); 2348 pm_ctl &= ~(PCI_PWR_D0|PCI_PWR_D1|PCI_PWR_D2|PCI_PWR_D3); 2349 pm_ctl |= (1 << 8) | PCI_PWR_D0 ; /* D0 state */ 2350 pci_conf_write(pc, sc->sc_pcitag, BGE_PCI_PWRMGMT_CMD, pm_ctl); 2351 DELAY(1000); /* 27 usec is allegedly sufficent */ 2352 2353 /* 2354 * Save ASIC rev. 2355 */ 2356 sc->bge_chipid = 2357 pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MISC_CTL) & 2358 BGE_PCIMISCCTL_ASICREV; 2359 2360 if (pci_get_capability(sc->sc_pc, sc->sc_pcitag, PCI_CAP_PCIEXPRESS, 2361 NULL, NULL) != 0) { 2362 /* PCIe */ 2363 sc->bge_flags |= BGE_PCIE; 2364 } else if ((pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_PCISTATE) & 2365 BGE_PCISTATE_PCI_BUSMODE) == 0) { 2366 /* PCI-X */ 2367 sc->bge_flags |= BGE_PCIX; 2368 } 2369 2370 if (sc->bge_chipid == BGE_CHIPID_BCM5701_A0 || 2371 sc->bge_chipid == BGE_CHIPID_BCM5701_B0) 2372 sc->bge_flags |= BGE_PHY_CRC_BUG; 2373 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5703_AX || 2374 BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5704_AX) 2375 sc->bge_flags |= BGE_PHY_ADC_BUG; 2376 if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0) 2377 sc->bge_flags |= BGE_PHY_5704_A0_BUG; 2378 2379 if (BGE_IS_5705_OR_BEYOND(sc)) { 2380 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5755 || 2381 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5787) { 2382 if (PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_BROADCOM_BCM5722 && 2383 PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_BROADCOM_BCM5756) 2384 sc->bge_flags |= BGE_PHY_JITTER_BUG; 2385 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5755M) 2386 sc->bge_flags |= BGE_PHY_ADJUST_TRIM; 2387 } else if (BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5906) 2388 sc->bge_flags |= BGE_PHY_BER_BUG; 2389 } 2390 2391 /* Try to reset the chip. */ 2392 DPRINTFN(5, ("bge_reset\n")); 2393 bge_reset(sc); 2394 2395 if (bge_chipinit(sc)) { 2396 aprint_error_dev(sc->bge_dev, "chip initialization failed\n"); 2397 bge_release_resources(sc); 2398 return; 2399 } 2400 2401 /* 2402 * Get station address from the EEPROM. 2403 */ 2404 if (bge_get_eaddr(sc, eaddr)) { 2405 aprint_error_dev(sc->bge_dev, 2406 "failed to read station address\n"); 2407 bge_release_resources(sc); 2408 return; 2409 } 2410 2411 br = bge_lookup_rev(sc->bge_chipid); 2412 2413 if (br == NULL) { 2414 aprint_normal_dev(sc->bge_dev, "unknown ASIC (0x%04x)", 2415 sc->bge_chipid >> 16); 2416 } else { 2417 aprint_normal_dev(sc->bge_dev, "ASIC %s (0x%04x)", 2418 br->br_name, sc->bge_chipid >> 16); 2419 } 2420 aprint_normal(", Ethernet address %s\n", ether_sprintf(eaddr)); 2421 2422 /* Allocate the general information block and ring buffers. */ 2423 if (pci_dma64_available(pa)) 2424 sc->bge_dmatag = pa->pa_dmat64; 2425 else 2426 sc->bge_dmatag = pa->pa_dmat; 2427 DPRINTFN(5, ("bus_dmamem_alloc\n")); 2428 if (bus_dmamem_alloc(sc->bge_dmatag, sizeof(struct bge_ring_data), 2429 PAGE_SIZE, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 2430 aprint_error_dev(sc->bge_dev, "can't alloc rx buffers\n"); 2431 return; 2432 } 2433 DPRINTFN(5, ("bus_dmamem_map\n")); 2434 if (bus_dmamem_map(sc->bge_dmatag, &seg, rseg, 2435 sizeof(struct bge_ring_data), &kva, 2436 BUS_DMA_NOWAIT)) { 2437 aprint_error_dev(sc->bge_dev, 2438 "can't map DMA buffers (%zu bytes)\n", 2439 sizeof(struct bge_ring_data)); 2440 bus_dmamem_free(sc->bge_dmatag, &seg, rseg); 2441 return; 2442 } 2443 DPRINTFN(5, ("bus_dmamem_create\n")); 2444 if (bus_dmamap_create(sc->bge_dmatag, sizeof(struct bge_ring_data), 1, 2445 sizeof(struct bge_ring_data), 0, 2446 BUS_DMA_NOWAIT, &sc->bge_ring_map)) { 2447 aprint_error_dev(sc->bge_dev, "can't create DMA map\n"); 2448 bus_dmamem_unmap(sc->bge_dmatag, kva, 2449 sizeof(struct bge_ring_data)); 2450 bus_dmamem_free(sc->bge_dmatag, &seg, rseg); 2451 return; 2452 } 2453 DPRINTFN(5, ("bus_dmamem_load\n")); 2454 if (bus_dmamap_load(sc->bge_dmatag, sc->bge_ring_map, kva, 2455 sizeof(struct bge_ring_data), NULL, 2456 BUS_DMA_NOWAIT)) { 2457 bus_dmamap_destroy(sc->bge_dmatag, sc->bge_ring_map); 2458 bus_dmamem_unmap(sc->bge_dmatag, kva, 2459 sizeof(struct bge_ring_data)); 2460 bus_dmamem_free(sc->bge_dmatag, &seg, rseg); 2461 return; 2462 } 2463 2464 DPRINTFN(5, ("bzero\n")); 2465 sc->bge_rdata = (struct bge_ring_data *)kva; 2466 2467 memset(sc->bge_rdata, 0, sizeof(struct bge_ring_data)); 2468 2469 /* Try to allocate memory for jumbo buffers. */ 2470 if (BGE_IS_JUMBO_CAPABLE(sc)) { 2471 if (bge_alloc_jumbo_mem(sc)) { 2472 aprint_error_dev(sc->bge_dev, 2473 "jumbo buffer allocation failed\n"); 2474 } else 2475 sc->ethercom.ec_capabilities |= ETHERCAP_JUMBO_MTU; 2476 } 2477 2478 /* Set default tuneable values. */ 2479 sc->bge_stat_ticks = BGE_TICKS_PER_SEC; 2480 sc->bge_rx_coal_ticks = 150; 2481 sc->bge_rx_max_coal_bds = 64; 2482 #ifdef ORIG_WPAUL_VALUES 2483 sc->bge_tx_coal_ticks = 150; 2484 sc->bge_tx_max_coal_bds = 128; 2485 #else 2486 sc->bge_tx_coal_ticks = 300; 2487 sc->bge_tx_max_coal_bds = 400; 2488 #endif 2489 if (BGE_IS_5705_OR_BEYOND(sc)) { 2490 sc->bge_tx_coal_ticks = (12 * 5); 2491 sc->bge_tx_max_coal_bds = (12 * 5); 2492 aprint_verbose_dev(sc->bge_dev, 2493 "setting short Tx thresholds\n"); 2494 } 2495 2496 /* Set up ifnet structure */ 2497 ifp = &sc->ethercom.ec_if; 2498 ifp->if_softc = sc; 2499 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 2500 ifp->if_ioctl = bge_ioctl; 2501 ifp->if_stop = bge_stop; 2502 ifp->if_start = bge_start; 2503 ifp->if_init = bge_init; 2504 ifp->if_watchdog = bge_watchdog; 2505 IFQ_SET_MAXLEN(&ifp->if_snd, max(BGE_TX_RING_CNT - 1, IFQ_MAXLEN)); 2506 IFQ_SET_READY(&ifp->if_snd); 2507 DPRINTFN(5, ("strcpy if_xname\n")); 2508 strcpy(ifp->if_xname, device_xname(sc->bge_dev)); 2509 2510 if (sc->bge_chipid != BGE_CHIPID_BCM5700_B0) 2511 sc->ethercom.ec_if.if_capabilities |= 2512 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 2513 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 2514 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 2515 sc->ethercom.ec_capabilities |= 2516 ETHERCAP_VLAN_HWTAGGING | ETHERCAP_VLAN_MTU; 2517 2518 if (sc->bge_flags & BGE_PCIE) 2519 sc->ethercom.ec_if.if_capabilities |= IFCAP_TSOv4; 2520 2521 /* 2522 * Do MII setup. 2523 */ 2524 DPRINTFN(5, ("mii setup\n")); 2525 sc->bge_mii.mii_ifp = ifp; 2526 sc->bge_mii.mii_readreg = bge_miibus_readreg; 2527 sc->bge_mii.mii_writereg = bge_miibus_writereg; 2528 sc->bge_mii.mii_statchg = bge_miibus_statchg; 2529 2530 /* 2531 * Figure out what sort of media we have by checking the 2532 * hardware config word in the first 32k of NIC internal memory, 2533 * or fall back to the config word in the EEPROM. Note: on some BCM5700 2534 * cards, this value appears to be unset. If that's the 2535 * case, we have to rely on identifying the NIC by its PCI 2536 * subsystem ID, as we do below for the SysKonnect SK-9D41. 2537 */ 2538 if (bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_SIG) == BGE_MAGIC_NUMBER) { 2539 hwcfg = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_NICCFG); 2540 } else { 2541 bge_read_eeprom(sc, (void *)&hwcfg, 2542 BGE_EE_HWCFG_OFFSET, sizeof(hwcfg)); 2543 hwcfg = be32toh(hwcfg); 2544 } 2545 /* The SysKonnect SK-9D41 is a 1000baseSX card. */ 2546 if (PCI_PRODUCT(pa->pa_id) == SK_SUBSYSID_9D41 || 2547 (hwcfg & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER) { 2548 if (BGE_IS_5714_FAMILY(sc)) 2549 sc->bge_flags |= BGE_PHY_FIBER_MII; 2550 else 2551 sc->bge_flags |= BGE_PHY_FIBER_TBI; 2552 } 2553 2554 /* set phyflags before mii_attach() */ 2555 dict = device_properties(self); 2556 prop_dictionary_set_uint32(dict, "phyflags", sc->bge_flags); 2557 2558 if (sc->bge_flags & BGE_PHY_FIBER_TBI) { 2559 ifmedia_init(&sc->bge_ifmedia, IFM_IMASK, bge_ifmedia_upd, 2560 bge_ifmedia_sts); 2561 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL); 2562 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_1000_SX|IFM_FDX, 2563 0, NULL); 2564 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL); 2565 ifmedia_set(&sc->bge_ifmedia, IFM_ETHER|IFM_AUTO); 2566 /* Pretend the user requested this setting */ 2567 sc->bge_ifmedia.ifm_media = sc->bge_ifmedia.ifm_cur->ifm_media; 2568 } else { 2569 /* 2570 * Do transceiver setup. 2571 */ 2572 ifmedia_init(&sc->bge_mii.mii_media, 0, bge_ifmedia_upd, 2573 bge_ifmedia_sts); 2574 mii_attach(sc->bge_dev, &sc->bge_mii, 0xffffffff, 2575 MII_PHY_ANY, MII_OFFSET_ANY, 2576 MIIF_FORCEANEG|MIIF_DOPAUSE); 2577 2578 if (LIST_EMPTY(&sc->bge_mii.mii_phys)) { 2579 aprint_error_dev(sc->bge_dev, "no PHY found!\n"); 2580 ifmedia_add(&sc->bge_mii.mii_media, 2581 IFM_ETHER|IFM_MANUAL, 0, NULL); 2582 ifmedia_set(&sc->bge_mii.mii_media, 2583 IFM_ETHER|IFM_MANUAL); 2584 } else 2585 ifmedia_set(&sc->bge_mii.mii_media, 2586 IFM_ETHER|IFM_AUTO); 2587 } 2588 2589 /* 2590 * When using the BCM5701 in PCI-X mode, data corruption has 2591 * been observed in the first few bytes of some received packets. 2592 * Aligning the packet buffer in memory eliminates the corruption. 2593 * Unfortunately, this misaligns the packet payloads. On platforms 2594 * which do not support unaligned accesses, we will realign the 2595 * payloads by copying the received packets. 2596 */ 2597 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5701 && 2598 sc->bge_flags & BGE_PCIX) 2599 sc->bge_flags |= BGE_RX_ALIGNBUG; 2600 2601 misccfg = CSR_READ_4(sc, BGE_MISC_CFG); 2602 misccfg &= BGE_MISCCFG_BOARD_ID_MASK; 2603 2604 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5705 && 2605 (misccfg == BGE_MISCCFG_BOARD_ID_5788 || 2606 misccfg == BGE_MISCCFG_BOARD_ID_5788M)) 2607 sc->bge_flags |= BGE_IS_5788; 2608 2609 /* 2610 * Call MI attach routine. 2611 */ 2612 DPRINTFN(5, ("if_attach\n")); 2613 if_attach(ifp); 2614 DPRINTFN(5, ("ether_ifattach\n")); 2615 ether_ifattach(ifp, eaddr); 2616 #if NRND > 0 2617 rnd_attach_source(&sc->rnd_source, device_xname(sc->bge_dev), 2618 RND_TYPE_NET, 0); 2619 #endif 2620 #ifdef BGE_EVENT_COUNTERS 2621 /* 2622 * Attach event counters. 2623 */ 2624 evcnt_attach_dynamic(&sc->bge_ev_intr, EVCNT_TYPE_INTR, 2625 NULL, device_xname(sc->bge_dev), "intr"); 2626 evcnt_attach_dynamic(&sc->bge_ev_tx_xoff, EVCNT_TYPE_MISC, 2627 NULL, device_xname(sc->bge_dev), "tx_xoff"); 2628 evcnt_attach_dynamic(&sc->bge_ev_tx_xon, EVCNT_TYPE_MISC, 2629 NULL, device_xname(sc->bge_dev), "tx_xon"); 2630 evcnt_attach_dynamic(&sc->bge_ev_rx_xoff, EVCNT_TYPE_MISC, 2631 NULL, device_xname(sc->bge_dev), "rx_xoff"); 2632 evcnt_attach_dynamic(&sc->bge_ev_rx_xon, EVCNT_TYPE_MISC, 2633 NULL, device_xname(sc->bge_dev), "rx_xon"); 2634 evcnt_attach_dynamic(&sc->bge_ev_rx_macctl, EVCNT_TYPE_MISC, 2635 NULL, device_xname(sc->bge_dev), "rx_macctl"); 2636 evcnt_attach_dynamic(&sc->bge_ev_xoffentered, EVCNT_TYPE_MISC, 2637 NULL, device_xname(sc->bge_dev), "xoffentered"); 2638 #endif /* BGE_EVENT_COUNTERS */ 2639 DPRINTFN(5, ("callout_init\n")); 2640 callout_init(&sc->bge_timeout, 0); 2641 2642 if (pmf_device_register(self, NULL, NULL)) 2643 pmf_class_network_register(self, ifp); 2644 else 2645 aprint_error_dev(self, "couldn't establish power handler\n"); 2646 } 2647 2648 static void 2649 bge_release_resources(struct bge_softc *sc) 2650 { 2651 if (sc->bge_vpd_prodname != NULL) 2652 free(sc->bge_vpd_prodname, M_DEVBUF); 2653 2654 if (sc->bge_vpd_readonly != NULL) 2655 free(sc->bge_vpd_readonly, M_DEVBUF); 2656 } 2657 2658 static void 2659 bge_reset(struct bge_softc *sc) 2660 { 2661 uint32_t cachesize, command, pcistate, new_pcistate; 2662 int i, val; 2663 void (*write_op)(struct bge_softc *, int, int); 2664 2665 if (BGE_IS_5750_OR_BEYOND(sc) && !BGE_IS_5714_FAMILY(sc) && 2666 (BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5906)) { 2667 if (sc->bge_flags & BGE_PCIE) { 2668 write_op = bge_writemem_direct; 2669 } else { 2670 write_op = bge_writemem_ind; 2671 } 2672 } else { 2673 write_op = bge_writereg_ind; 2674 } 2675 2676 2677 /* Save some important PCI state. */ 2678 cachesize = pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CACHESZ); 2679 command = pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CMD); 2680 pcistate = pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_PCISTATE); 2681 2682 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MISC_CTL, 2683 BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR| 2684 BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_PCISTATE_RW); 2685 2686 /* Disable fastboot on controllers that support it. */ 2687 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5752 || 2688 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5755 || 2689 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5787) 2690 CSR_WRITE_4(sc, BGE_FASTBOOT_PC, 0); 2691 2692 val = BGE_MISCCFG_RESET_CORE_CLOCKS | (65<<1); 2693 /* 2694 * XXX: from FreeBSD/Linux; no documentation 2695 */ 2696 if (sc->bge_flags & BGE_PCIE) { 2697 if (CSR_READ_4(sc, BGE_PCIE_CTL1) == 0x60) 2698 /* PCI Express 1.0 system */ 2699 CSR_WRITE_4(sc, BGE_PCIE_CTL1, 0x20); 2700 if (sc->bge_chipid != BGE_CHIPID_BCM5750_A0) { 2701 /* 2702 * Prevent PCI Express link training 2703 * during global reset. 2704 */ 2705 CSR_WRITE_4(sc, BGE_MISC_CFG, 1 << 29); 2706 val |= (1<<29); 2707 } 2708 } 2709 2710 /* 2711 * Set GPHY Power Down Override to leave GPHY 2712 * powered up in D0 uninitialized. 2713 */ 2714 if (BGE_IS_5705_OR_BEYOND(sc)) 2715 val |= BGE_MISCCFG_KEEP_GPHY_POWER; 2716 2717 /* Issue global reset */ 2718 write_op(sc, BGE_MISC_CFG, val); 2719 2720 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 2721 i = CSR_READ_4(sc, BGE_VCPU_STATUS); 2722 CSR_WRITE_4(sc, BGE_VCPU_STATUS, 2723 i | BGE_VCPU_STATUS_DRV_RESET); 2724 i = CSR_READ_4(sc, BGE_VCPU_EXT_CTRL); 2725 CSR_WRITE_4(sc, BGE_VCPU_EXT_CTRL, 2726 i & ~BGE_VCPU_EXT_CTRL_HALT_CPU); 2727 } 2728 2729 DELAY(1000); 2730 2731 /* 2732 * XXX: from FreeBSD/Linux; no documentation 2733 */ 2734 if (sc->bge_flags & BGE_PCIE) { 2735 if (sc->bge_chipid == BGE_CHIPID_BCM5750_A0) { 2736 pcireg_t reg; 2737 2738 DELAY(500000); 2739 /* XXX: Magic Numbers */ 2740 reg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 2741 BGE_PCI_UNKNOWN0); 2742 pci_conf_write(sc->sc_pc, sc->sc_pcitag, 2743 BGE_PCI_UNKNOWN0, 2744 reg | (1 << 15)); 2745 } 2746 /* 2747 * XXX: Magic Numbers. 2748 * Sets maximal PCI-e payload and clears any PCI-e errors. 2749 * Should be replaced with references to PCI config-space 2750 * capability block for PCI-Express. 2751 */ 2752 pci_conf_write(sc->sc_pc, sc->sc_pcitag, 2753 BGE_PCI_CONF_DEV_CTRL, 0xf5000); 2754 2755 } 2756 2757 /* Reset some of the PCI state that got zapped by reset */ 2758 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MISC_CTL, 2759 BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR| 2760 BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_PCISTATE_RW); 2761 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CMD, command); 2762 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CACHESZ, cachesize); 2763 write_op(sc, BGE_MISC_CFG, (65 << 1)); 2764 2765 /* Enable memory arbiter. */ 2766 { 2767 uint32_t marbmode = 0; 2768 if (BGE_IS_5714_FAMILY(sc)) { 2769 marbmode = CSR_READ_4(sc, BGE_MARB_MODE); 2770 } 2771 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE | marbmode); 2772 } 2773 2774 2775 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 2776 for (i = 0; i < BGE_TIMEOUT; i++) { 2777 val = CSR_READ_4(sc, BGE_VCPU_STATUS); 2778 if (val & BGE_VCPU_STATUS_INIT_DONE) 2779 break; 2780 DELAY(100); 2781 } 2782 if (i == BGE_TIMEOUT) { 2783 aprint_error_dev(sc->bge_dev, "reset timed out\n"); 2784 return; 2785 } 2786 } else { 2787 /* 2788 * Write the magic number to the firmware mailbox at 0xb50 2789 * so that the driver can synchronize with the firmware. 2790 */ 2791 bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM, BGE_MAGIC_NUMBER); 2792 2793 /* 2794 * Poll the value location we just wrote until 2795 * we see the 1's complement of the magic number. 2796 * This indicates that the firmware initialization 2797 * is complete. 2798 */ 2799 for (i = 0; i < BGE_TIMEOUT; i++) { 2800 val = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM); 2801 if (val == ~BGE_MAGIC_NUMBER) 2802 break; 2803 DELAY(1000); 2804 } 2805 2806 if (i >= BGE_TIMEOUT) { 2807 aprint_error_dev(sc->bge_dev, 2808 "firmware handshake timed out, val = %x\n", val); 2809 /* 2810 * XXX: occasionally fired on bcm5721, but without 2811 * apparent harm. For now, keep going if we timeout 2812 * against PCI-E devices. 2813 */ 2814 if ((sc->bge_flags & BGE_PCIE) == 0) 2815 return; 2816 } 2817 } 2818 2819 /* 2820 * XXX Wait for the value of the PCISTATE register to 2821 * return to its original pre-reset state. This is a 2822 * fairly good indicator of reset completion. If we don't 2823 * wait for the reset to fully complete, trying to read 2824 * from the device's non-PCI registers may yield garbage 2825 * results. 2826 */ 2827 for (i = 0; i < 10000; i++) { 2828 new_pcistate = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 2829 BGE_PCI_PCISTATE); 2830 if ((new_pcistate & ~BGE_PCISTATE_RESERVED) == 2831 (pcistate & ~BGE_PCISTATE_RESERVED)) 2832 break; 2833 DELAY(10); 2834 } 2835 if ((new_pcistate & ~BGE_PCISTATE_RESERVED) != 2836 (pcistate & ~BGE_PCISTATE_RESERVED)) { 2837 aprint_error_dev(sc->bge_dev, "pcistate failed to revert\n"); 2838 } 2839 2840 /* Enable memory arbiter. */ 2841 /* XXX why do this twice? */ 2842 { 2843 uint32_t marbmode = 0; 2844 if (BGE_IS_5714_FAMILY(sc)) { 2845 marbmode = CSR_READ_4(sc, BGE_MARB_MODE); 2846 } 2847 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE | marbmode); 2848 } 2849 2850 /* Fix up byte swapping */ 2851 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS); 2852 2853 CSR_WRITE_4(sc, BGE_MAC_MODE, 0); 2854 2855 /* 2856 * The 5704 in TBI mode apparently needs some special 2857 * adjustment to insure the SERDES drive level is set 2858 * to 1.2V. 2859 */ 2860 if (sc->bge_flags & BGE_PHY_FIBER_TBI && 2861 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) { 2862 uint32_t serdescfg; 2863 2864 serdescfg = CSR_READ_4(sc, BGE_SERDES_CFG); 2865 serdescfg = (serdescfg & ~0xFFF) | 0x880; 2866 CSR_WRITE_4(sc, BGE_SERDES_CFG, serdescfg); 2867 } 2868 2869 /* XXX: from FreeBSD/Linux; no documentation */ 2870 if (sc->bge_flags & BGE_PCIE && 2871 sc->bge_chipid != BGE_CHIPID_BCM5750_A0) 2872 CSR_WRITE_4(sc, BGE_PCIE_CTL0, CSR_READ_4(sc, BGE_PCIE_CTL0) | (1<<25)); 2873 DELAY(10000); 2874 } 2875 2876 /* 2877 * Frame reception handling. This is called if there's a frame 2878 * on the receive return list. 2879 * 2880 * Note: we have to be able to handle two possibilities here: 2881 * 1) the frame is from the jumbo recieve ring 2882 * 2) the frame is from the standard receive ring 2883 */ 2884 2885 static void 2886 bge_rxeof(struct bge_softc *sc) 2887 { 2888 struct ifnet *ifp; 2889 int stdcnt = 0, jumbocnt = 0; 2890 bus_dmamap_t dmamap; 2891 bus_addr_t offset, toff; 2892 bus_size_t tlen; 2893 int tosync; 2894 2895 ifp = &sc->ethercom.ec_if; 2896 2897 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 2898 offsetof(struct bge_ring_data, bge_status_block), 2899 sizeof (struct bge_status_block), 2900 BUS_DMASYNC_POSTREAD); 2901 2902 offset = offsetof(struct bge_ring_data, bge_rx_return_ring); 2903 tosync = sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx - 2904 sc->bge_rx_saved_considx; 2905 2906 #if NRND > 0 2907 if (tosync != 0 && RND_ENABLED(&sc->rnd_source)) 2908 rnd_add_uint32(&sc->rnd_source, tosync); 2909 #endif 2910 2911 toff = offset + (sc->bge_rx_saved_considx * sizeof (struct bge_rx_bd)); 2912 2913 if (tosync < 0) { 2914 tlen = (sc->bge_return_ring_cnt - sc->bge_rx_saved_considx) * 2915 sizeof (struct bge_rx_bd); 2916 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 2917 toff, tlen, BUS_DMASYNC_POSTREAD); 2918 tosync = -tosync; 2919 } 2920 2921 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 2922 offset, tosync * sizeof (struct bge_rx_bd), 2923 BUS_DMASYNC_POSTREAD); 2924 2925 while (sc->bge_rx_saved_considx != 2926 sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx) { 2927 struct bge_rx_bd *cur_rx; 2928 uint32_t rxidx; 2929 struct mbuf *m = NULL; 2930 2931 cur_rx = &sc->bge_rdata-> 2932 bge_rx_return_ring[sc->bge_rx_saved_considx]; 2933 2934 rxidx = cur_rx->bge_idx; 2935 BGE_INC(sc->bge_rx_saved_considx, sc->bge_return_ring_cnt); 2936 2937 if (cur_rx->bge_flags & BGE_RXBDFLAG_JUMBO_RING) { 2938 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT); 2939 m = sc->bge_cdata.bge_rx_jumbo_chain[rxidx]; 2940 sc->bge_cdata.bge_rx_jumbo_chain[rxidx] = NULL; 2941 jumbocnt++; 2942 bus_dmamap_sync(sc->bge_dmatag, 2943 sc->bge_cdata.bge_rx_jumbo_map, 2944 mtod(m, char *) - (char *)sc->bge_cdata.bge_jumbo_buf, 2945 BGE_JLEN, BUS_DMASYNC_POSTREAD); 2946 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 2947 ifp->if_ierrors++; 2948 bge_newbuf_jumbo(sc, sc->bge_jumbo, m); 2949 continue; 2950 } 2951 if (bge_newbuf_jumbo(sc, sc->bge_jumbo, 2952 NULL)== ENOBUFS) { 2953 ifp->if_ierrors++; 2954 bge_newbuf_jumbo(sc, sc->bge_jumbo, m); 2955 continue; 2956 } 2957 } else { 2958 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT); 2959 m = sc->bge_cdata.bge_rx_std_chain[rxidx]; 2960 2961 sc->bge_cdata.bge_rx_std_chain[rxidx] = NULL; 2962 stdcnt++; 2963 dmamap = sc->bge_cdata.bge_rx_std_map[rxidx]; 2964 sc->bge_cdata.bge_rx_std_map[rxidx] = 0; 2965 bus_dmamap_sync(sc->bge_dmatag, dmamap, 0, 2966 dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 2967 bus_dmamap_unload(sc->bge_dmatag, dmamap); 2968 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 2969 ifp->if_ierrors++; 2970 bge_newbuf_std(sc, sc->bge_std, m, dmamap); 2971 continue; 2972 } 2973 if (bge_newbuf_std(sc, sc->bge_std, 2974 NULL, dmamap) == ENOBUFS) { 2975 ifp->if_ierrors++; 2976 bge_newbuf_std(sc, sc->bge_std, m, dmamap); 2977 continue; 2978 } 2979 } 2980 2981 ifp->if_ipackets++; 2982 #ifndef __NO_STRICT_ALIGNMENT 2983 /* 2984 * XXX: if the 5701 PCIX-Rx-DMA workaround is in effect, 2985 * the Rx buffer has the layer-2 header unaligned. 2986 * If our CPU requires alignment, re-align by copying. 2987 */ 2988 if (sc->bge_flags & BGE_RX_ALIGNBUG) { 2989 memmove(mtod(m, char *) + ETHER_ALIGN, m->m_data, 2990 cur_rx->bge_len); 2991 m->m_data += ETHER_ALIGN; 2992 } 2993 #endif 2994 2995 m->m_pkthdr.len = m->m_len = cur_rx->bge_len - ETHER_CRC_LEN; 2996 m->m_pkthdr.rcvif = ifp; 2997 2998 /* 2999 * Handle BPF listeners. Let the BPF user see the packet. 3000 */ 3001 if (ifp->if_bpf) 3002 bpf_ops->bpf_mtap(ifp->if_bpf, m); 3003 3004 m->m_pkthdr.csum_flags = M_CSUM_IPv4; 3005 3006 if ((cur_rx->bge_ip_csum ^ 0xffff) != 0) 3007 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 3008 /* 3009 * Rx transport checksum-offload may also 3010 * have bugs with packets which, when transmitted, 3011 * were `runts' requiring padding. 3012 */ 3013 if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM && 3014 (/* (sc->_bge_quirks & BGE_QUIRK_SHORT_CKSUM_BUG) == 0 ||*/ 3015 m->m_pkthdr.len >= ETHER_MIN_NOPAD)) { 3016 m->m_pkthdr.csum_data = 3017 cur_rx->bge_tcp_udp_csum; 3018 m->m_pkthdr.csum_flags |= 3019 (M_CSUM_TCPv4|M_CSUM_UDPv4| 3020 M_CSUM_DATA|M_CSUM_NO_PSEUDOHDR); 3021 } 3022 3023 /* 3024 * If we received a packet with a vlan tag, pass it 3025 * to vlan_input() instead of ether_input(). 3026 */ 3027 if (cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) { 3028 VLAN_INPUT_TAG(ifp, m, cur_rx->bge_vlan_tag, continue); 3029 } 3030 3031 (*ifp->if_input)(ifp, m); 3032 } 3033 3034 bge_writembx(sc, BGE_MBX_RX_CONS0_LO, sc->bge_rx_saved_considx); 3035 if (stdcnt) 3036 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std); 3037 if (jumbocnt) 3038 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo); 3039 } 3040 3041 static void 3042 bge_txeof(struct bge_softc *sc) 3043 { 3044 struct bge_tx_bd *cur_tx = NULL; 3045 struct ifnet *ifp; 3046 struct txdmamap_pool_entry *dma; 3047 bus_addr_t offset, toff; 3048 bus_size_t tlen; 3049 int tosync; 3050 struct mbuf *m; 3051 3052 ifp = &sc->ethercom.ec_if; 3053 3054 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 3055 offsetof(struct bge_ring_data, bge_status_block), 3056 sizeof (struct bge_status_block), 3057 BUS_DMASYNC_POSTREAD); 3058 3059 offset = offsetof(struct bge_ring_data, bge_tx_ring); 3060 tosync = sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx - 3061 sc->bge_tx_saved_considx; 3062 3063 #if NRND > 0 3064 if (tosync != 0 && RND_ENABLED(&sc->rnd_source)) 3065 rnd_add_uint32(&sc->rnd_source, tosync); 3066 #endif 3067 3068 toff = offset + (sc->bge_tx_saved_considx * sizeof (struct bge_tx_bd)); 3069 3070 if (tosync < 0) { 3071 tlen = (BGE_TX_RING_CNT - sc->bge_tx_saved_considx) * 3072 sizeof (struct bge_tx_bd); 3073 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 3074 toff, tlen, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 3075 tosync = -tosync; 3076 } 3077 3078 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 3079 offset, tosync * sizeof (struct bge_tx_bd), 3080 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 3081 3082 /* 3083 * Go through our tx ring and free mbufs for those 3084 * frames that have been sent. 3085 */ 3086 while (sc->bge_tx_saved_considx != 3087 sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx) { 3088 uint32_t idx = 0; 3089 3090 idx = sc->bge_tx_saved_considx; 3091 cur_tx = &sc->bge_rdata->bge_tx_ring[idx]; 3092 if (cur_tx->bge_flags & BGE_TXBDFLAG_END) 3093 ifp->if_opackets++; 3094 m = sc->bge_cdata.bge_tx_chain[idx]; 3095 if (m != NULL) { 3096 sc->bge_cdata.bge_tx_chain[idx] = NULL; 3097 dma = sc->txdma[idx]; 3098 bus_dmamap_sync(sc->bge_dmatag, dma->dmamap, 0, 3099 dma->dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 3100 bus_dmamap_unload(sc->bge_dmatag, dma->dmamap); 3101 SLIST_INSERT_HEAD(&sc->txdma_list, dma, link); 3102 sc->txdma[idx] = NULL; 3103 3104 m_freem(m); 3105 } 3106 sc->bge_txcnt--; 3107 BGE_INC(sc->bge_tx_saved_considx, BGE_TX_RING_CNT); 3108 ifp->if_timer = 0; 3109 } 3110 3111 if (cur_tx != NULL) 3112 ifp->if_flags &= ~IFF_OACTIVE; 3113 } 3114 3115 static int 3116 bge_intr(void *xsc) 3117 { 3118 struct bge_softc *sc; 3119 struct ifnet *ifp; 3120 uint32_t statusword; 3121 3122 sc = xsc; 3123 ifp = &sc->ethercom.ec_if; 3124 3125 /* It is possible for the interrupt to arrive before 3126 * the status block is updated prior to the interrupt. 3127 * Reading the PCI State register will confirm whether the 3128 * interrupt is ours and will flush the status block. 3129 */ 3130 3131 /* read status word from status block */ 3132 statusword = sc->bge_rdata->bge_status_block.bge_status; 3133 3134 if ((statusword & BGE_STATFLAG_UPDATED) || 3135 (!(CSR_READ_4(sc, BGE_PCI_PCISTATE) & BGE_PCISTATE_INTR_NOT_ACTIVE))) { 3136 /* Ack interrupt and stop others from occuring. */ 3137 bge_writembx(sc, BGE_MBX_IRQ0_LO, 1); 3138 3139 BGE_EVCNT_INCR(sc->bge_ev_intr); 3140 3141 /* clear status word */ 3142 sc->bge_rdata->bge_status_block.bge_status = 0; 3143 3144 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 3145 statusword & BGE_STATFLAG_LINKSTATE_CHANGED || 3146 BGE_STS_BIT(sc, BGE_STS_LINK_EVT)) 3147 bge_link_upd(sc); 3148 3149 if (ifp->if_flags & IFF_RUNNING) { 3150 /* Check RX return ring producer/consumer */ 3151 bge_rxeof(sc); 3152 3153 /* Check TX ring producer/consumer */ 3154 bge_txeof(sc); 3155 } 3156 3157 if (sc->bge_pending_rxintr_change) { 3158 uint32_t rx_ticks = sc->bge_rx_coal_ticks; 3159 uint32_t rx_bds = sc->bge_rx_max_coal_bds; 3160 uint32_t junk; 3161 3162 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, rx_ticks); 3163 DELAY(10); 3164 junk = CSR_READ_4(sc, BGE_HCC_RX_COAL_TICKS); 3165 3166 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, rx_bds); 3167 DELAY(10); 3168 junk = CSR_READ_4(sc, BGE_HCC_RX_MAX_COAL_BDS); 3169 3170 sc->bge_pending_rxintr_change = 0; 3171 } 3172 bge_handle_events(sc); 3173 3174 /* Re-enable interrupts. */ 3175 bge_writembx(sc, BGE_MBX_IRQ0_LO, 0); 3176 3177 if (ifp->if_flags & IFF_RUNNING && !IFQ_IS_EMPTY(&ifp->if_snd)) 3178 bge_start(ifp); 3179 3180 return 1; 3181 } else 3182 return 0; 3183 } 3184 3185 static void 3186 bge_tick(void *xsc) 3187 { 3188 struct bge_softc *sc = xsc; 3189 struct mii_data *mii = &sc->bge_mii; 3190 int s; 3191 3192 s = splnet(); 3193 3194 bge_stats_update(sc); 3195 3196 if (sc->bge_flags & BGE_PHY_FIBER_TBI) { 3197 /* 3198 * Since in TBI mode auto-polling can't be used we should poll 3199 * link status manually. Here we register pending link event 3200 * and trigger interrupt. 3201 */ 3202 BGE_STS_SETBIT(sc, BGE_STS_LINK_EVT); 3203 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET); 3204 } else { 3205 /* 3206 * Do not touch PHY if we have link up. This could break 3207 * IPMI/ASF mode or produce extra input errors. 3208 * (extra input errors was reported for bcm5701 & bcm5704). 3209 */ 3210 if (!BGE_STS_BIT(sc, BGE_STS_LINK)) 3211 mii_tick(mii); 3212 } 3213 3214 callout_reset(&sc->bge_timeout, hz, bge_tick, sc); 3215 3216 splx(s); 3217 } 3218 3219 static void 3220 bge_stats_update(struct bge_softc *sc) 3221 { 3222 struct ifnet *ifp = &sc->ethercom.ec_if; 3223 bus_size_t stats = BGE_MEMWIN_START + BGE_STATS_BLOCK; 3224 bus_size_t rstats = BGE_RX_STATS; 3225 3226 #define READ_RSTAT(sc, stats, stat) \ 3227 CSR_READ_4(sc, stats + offsetof(struct bge_mac_stats_regs, stat)) 3228 3229 if (BGE_IS_5705_OR_BEYOND(sc)) { 3230 ifp->if_collisions += 3231 READ_RSTAT(sc, rstats, dot3StatsSingleCollisionFrames) + 3232 READ_RSTAT(sc, rstats, dot3StatsMultipleCollisionFrames) + 3233 READ_RSTAT(sc, rstats, dot3StatsExcessiveCollisions) + 3234 READ_RSTAT(sc, rstats, dot3StatsLateCollisions); 3235 3236 BGE_EVCNT_ADD(sc->bge_ev_tx_xoff, 3237 READ_RSTAT(sc, rstats, outXoffSent)); 3238 BGE_EVCNT_ADD(sc->bge_ev_tx_xon, 3239 READ_RSTAT(sc, rstats, outXonSent)); 3240 BGE_EVCNT_ADD(sc->bge_ev_rx_xoff, 3241 READ_RSTAT(sc, rstats, xoffPauseFramesReceived)); 3242 BGE_EVCNT_ADD(sc->bge_ev_rx_xon, 3243 READ_RSTAT(sc, rstats, xonPauseFramesReceived)); 3244 BGE_EVCNT_ADD(sc->bge_ev_rx_macctl, 3245 READ_RSTAT(sc, rstats, macControlFramesReceived)); 3246 BGE_EVCNT_ADD(sc->bge_ev_xoffentered, 3247 READ_RSTAT(sc, rstats, xoffStateEntered)); 3248 return; 3249 } 3250 3251 #undef READ_RSTAT 3252 #define READ_STAT(sc, stats, stat) \ 3253 CSR_READ_4(sc, stats + offsetof(struct bge_stats, stat)) 3254 3255 ifp->if_collisions += 3256 (READ_STAT(sc, stats, dot3StatsSingleCollisionFrames.bge_addr_lo) + 3257 READ_STAT(sc, stats, dot3StatsMultipleCollisionFrames.bge_addr_lo) + 3258 READ_STAT(sc, stats, dot3StatsExcessiveCollisions.bge_addr_lo) + 3259 READ_STAT(sc, stats, dot3StatsLateCollisions.bge_addr_lo)) - 3260 ifp->if_collisions; 3261 3262 BGE_EVCNT_UPD(sc->bge_ev_tx_xoff, 3263 READ_STAT(sc, stats, outXoffSent.bge_addr_lo)); 3264 BGE_EVCNT_UPD(sc->bge_ev_tx_xon, 3265 READ_STAT(sc, stats, outXonSent.bge_addr_lo)); 3266 BGE_EVCNT_UPD(sc->bge_ev_rx_xoff, 3267 READ_STAT(sc, stats, 3268 xoffPauseFramesReceived.bge_addr_lo)); 3269 BGE_EVCNT_UPD(sc->bge_ev_rx_xon, 3270 READ_STAT(sc, stats, xonPauseFramesReceived.bge_addr_lo)); 3271 BGE_EVCNT_UPD(sc->bge_ev_rx_macctl, 3272 READ_STAT(sc, stats, 3273 macControlFramesReceived.bge_addr_lo)); 3274 BGE_EVCNT_UPD(sc->bge_ev_xoffentered, 3275 READ_STAT(sc, stats, xoffStateEntered.bge_addr_lo)); 3276 3277 #undef READ_STAT 3278 3279 #ifdef notdef 3280 ifp->if_collisions += 3281 (sc->bge_rdata->bge_info.bge_stats.dot3StatsSingleCollisionFrames + 3282 sc->bge_rdata->bge_info.bge_stats.dot3StatsMultipleCollisionFrames + 3283 sc->bge_rdata->bge_info.bge_stats.dot3StatsExcessiveCollisions + 3284 sc->bge_rdata->bge_info.bge_stats.dot3StatsLateCollisions) - 3285 ifp->if_collisions; 3286 #endif 3287 } 3288 3289 /* 3290 * Pad outbound frame to ETHER_MIN_NOPAD for an unusual reason. 3291 * The bge hardware will pad out Tx runts to ETHER_MIN_NOPAD, 3292 * but when such padded frames employ the bge IP/TCP checksum offload, 3293 * the hardware checksum assist gives incorrect results (possibly 3294 * from incorporating its own padding into the UDP/TCP checksum; who knows). 3295 * If we pad such runts with zeros, the onboard checksum comes out correct. 3296 */ 3297 static inline int 3298 bge_cksum_pad(struct mbuf *pkt) 3299 { 3300 struct mbuf *last = NULL; 3301 int padlen; 3302 3303 padlen = ETHER_MIN_NOPAD - pkt->m_pkthdr.len; 3304 3305 /* if there's only the packet-header and we can pad there, use it. */ 3306 if (pkt->m_pkthdr.len == pkt->m_len && 3307 M_TRAILINGSPACE(pkt) >= padlen) { 3308 last = pkt; 3309 } else { 3310 /* 3311 * Walk packet chain to find last mbuf. We will either 3312 * pad there, or append a new mbuf and pad it 3313 * (thus perhaps avoiding the bcm5700 dma-min bug). 3314 */ 3315 for (last = pkt; last->m_next != NULL; last = last->m_next) { 3316 continue; /* do nothing */ 3317 } 3318 3319 /* `last' now points to last in chain. */ 3320 if (M_TRAILINGSPACE(last) < padlen) { 3321 /* Allocate new empty mbuf, pad it. Compact later. */ 3322 struct mbuf *n; 3323 MGET(n, M_DONTWAIT, MT_DATA); 3324 if (n == NULL) 3325 return ENOBUFS; 3326 n->m_len = 0; 3327 last->m_next = n; 3328 last = n; 3329 } 3330 } 3331 3332 KDASSERT(!M_READONLY(last)); 3333 KDASSERT(M_TRAILINGSPACE(last) >= padlen); 3334 3335 /* Now zero the pad area, to avoid the bge cksum-assist bug */ 3336 memset(mtod(last, char *) + last->m_len, 0, padlen); 3337 last->m_len += padlen; 3338 pkt->m_pkthdr.len += padlen; 3339 return 0; 3340 } 3341 3342 /* 3343 * Compact outbound packets to avoid bug with DMA segments less than 8 bytes. 3344 */ 3345 static inline int 3346 bge_compact_dma_runt(struct mbuf *pkt) 3347 { 3348 struct mbuf *m, *prev; 3349 int totlen, prevlen; 3350 3351 prev = NULL; 3352 totlen = 0; 3353 prevlen = -1; 3354 3355 for (m = pkt; m != NULL; prev = m,m = m->m_next) { 3356 int mlen = m->m_len; 3357 int shortfall = 8 - mlen ; 3358 3359 totlen += mlen; 3360 if (mlen == 0) { 3361 continue; 3362 } 3363 if (mlen >= 8) 3364 continue; 3365 3366 /* If we get here, mbuf data is too small for DMA engine. 3367 * Try to fix by shuffling data to prev or next in chain. 3368 * If that fails, do a compacting deep-copy of the whole chain. 3369 */ 3370 3371 /* Internal frag. If fits in prev, copy it there. */ 3372 if (prev && M_TRAILINGSPACE(prev) >= m->m_len) { 3373 memcpy(prev->m_data + prev->m_len, m->m_data, mlen); 3374 prev->m_len += mlen; 3375 m->m_len = 0; 3376 /* XXX stitch chain */ 3377 prev->m_next = m_free(m); 3378 m = prev; 3379 continue; 3380 } 3381 else if (m->m_next != NULL && 3382 M_TRAILINGSPACE(m) >= shortfall && 3383 m->m_next->m_len >= (8 + shortfall)) { 3384 /* m is writable and have enough data in next, pull up. */ 3385 3386 memcpy(m->m_data + m->m_len, m->m_next->m_data, 3387 shortfall); 3388 m->m_len += shortfall; 3389 m->m_next->m_len -= shortfall; 3390 m->m_next->m_data += shortfall; 3391 } 3392 else if (m->m_next == NULL || 1) { 3393 /* Got a runt at the very end of the packet. 3394 * borrow data from the tail of the preceding mbuf and 3395 * update its length in-place. (The original data is still 3396 * valid, so we can do this even if prev is not writable.) 3397 */ 3398 3399 /* if we'd make prev a runt, just move all of its data. */ 3400 KASSERT(prev != NULL /*, ("runt but null PREV")*/); 3401 KASSERT(prev->m_len >= 8 /*, ("runt prev")*/); 3402 3403 if ((prev->m_len - shortfall) < 8) 3404 shortfall = prev->m_len; 3405 3406 #ifdef notyet /* just do the safe slow thing for now */ 3407 if (!M_READONLY(m)) { 3408 if (M_LEADINGSPACE(m) < shorfall) { 3409 void *m_dat; 3410 m_dat = (m->m_flags & M_PKTHDR) ? 3411 m->m_pktdat : m->dat; 3412 memmove(m_dat, mtod(m, void*), m->m_len); 3413 m->m_data = m_dat; 3414 } 3415 } else 3416 #endif /* just do the safe slow thing */ 3417 { 3418 struct mbuf * n = NULL; 3419 int newprevlen = prev->m_len - shortfall; 3420 3421 MGET(n, M_NOWAIT, MT_DATA); 3422 if (n == NULL) 3423 return ENOBUFS; 3424 KASSERT(m->m_len + shortfall < MLEN 3425 /*, 3426 ("runt %d +prev %d too big\n", m->m_len, shortfall)*/); 3427 3428 /* first copy the data we're stealing from prev */ 3429 memcpy(n->m_data, prev->m_data + newprevlen, 3430 shortfall); 3431 3432 /* update prev->m_len accordingly */ 3433 prev->m_len -= shortfall; 3434 3435 /* copy data from runt m */ 3436 memcpy(n->m_data + shortfall, m->m_data, 3437 m->m_len); 3438 3439 /* n holds what we stole from prev, plus m */ 3440 n->m_len = shortfall + m->m_len; 3441 3442 /* stitch n into chain and free m */ 3443 n->m_next = m->m_next; 3444 prev->m_next = n; 3445 /* KASSERT(m->m_next == NULL); */ 3446 m->m_next = NULL; 3447 m_free(m); 3448 m = n; /* for continuing loop */ 3449 } 3450 } 3451 prevlen = m->m_len; 3452 } 3453 return 0; 3454 } 3455 3456 /* 3457 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data 3458 * pointers to descriptors. 3459 */ 3460 static int 3461 bge_encap(struct bge_softc *sc, struct mbuf *m_head, uint32_t *txidx) 3462 { 3463 struct bge_tx_bd *f = NULL; 3464 uint32_t frag, cur; 3465 uint16_t csum_flags = 0; 3466 uint16_t txbd_tso_flags = 0; 3467 struct txdmamap_pool_entry *dma; 3468 bus_dmamap_t dmamap; 3469 int i = 0; 3470 struct m_tag *mtag; 3471 int use_tso, maxsegsize, error; 3472 3473 cur = frag = *txidx; 3474 3475 if (m_head->m_pkthdr.csum_flags) { 3476 if (m_head->m_pkthdr.csum_flags & M_CSUM_IPv4) 3477 csum_flags |= BGE_TXBDFLAG_IP_CSUM; 3478 if (m_head->m_pkthdr.csum_flags & (M_CSUM_TCPv4|M_CSUM_UDPv4)) 3479 csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM; 3480 } 3481 3482 /* 3483 * If we were asked to do an outboard checksum, and the NIC 3484 * has the bug where it sometimes adds in the Ethernet padding, 3485 * explicitly pad with zeros so the cksum will be correct either way. 3486 * (For now, do this for all chip versions, until newer 3487 * are confirmed to not require the workaround.) 3488 */ 3489 if ((csum_flags & BGE_TXBDFLAG_TCP_UDP_CSUM) == 0 || 3490 #ifdef notyet 3491 (sc->bge_quirks & BGE_QUIRK_SHORT_CKSUM_BUG) == 0 || 3492 #endif 3493 m_head->m_pkthdr.len >= ETHER_MIN_NOPAD) 3494 goto check_dma_bug; 3495 3496 if (bge_cksum_pad(m_head) != 0) 3497 return ENOBUFS; 3498 3499 check_dma_bug: 3500 if (!(BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX)) 3501 goto doit; 3502 3503 /* 3504 * bcm5700 Revision B silicon cannot handle DMA descriptors with 3505 * less than eight bytes. If we encounter a teeny mbuf 3506 * at the end of a chain, we can pad. Otherwise, copy. 3507 */ 3508 if (bge_compact_dma_runt(m_head) != 0) 3509 return ENOBUFS; 3510 3511 doit: 3512 dma = SLIST_FIRST(&sc->txdma_list); 3513 if (dma == NULL) 3514 return ENOBUFS; 3515 dmamap = dma->dmamap; 3516 3517 /* 3518 * Set up any necessary TSO state before we start packing... 3519 */ 3520 use_tso = (m_head->m_pkthdr.csum_flags & M_CSUM_TSOv4) != 0; 3521 if (!use_tso) { 3522 maxsegsize = 0; 3523 } else { /* TSO setup */ 3524 unsigned mss; 3525 struct ether_header *eh; 3526 unsigned ip_tcp_hlen, iptcp_opt_words, tcp_seg_flags, offset; 3527 struct mbuf * m0 = m_head; 3528 struct ip *ip; 3529 struct tcphdr *th; 3530 int iphl, hlen; 3531 3532 /* 3533 * XXX It would be nice if the mbuf pkthdr had offset 3534 * fields for the protocol headers. 3535 */ 3536 3537 eh = mtod(m0, struct ether_header *); 3538 switch (htons(eh->ether_type)) { 3539 case ETHERTYPE_IP: 3540 offset = ETHER_HDR_LEN; 3541 break; 3542 3543 case ETHERTYPE_VLAN: 3544 offset = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 3545 break; 3546 3547 default: 3548 /* 3549 * Don't support this protocol or encapsulation. 3550 */ 3551 return ENOBUFS; 3552 } 3553 3554 /* 3555 * TCP/IP headers are in the first mbuf; we can do 3556 * this the easy way. 3557 */ 3558 iphl = M_CSUM_DATA_IPv4_IPHL(m0->m_pkthdr.csum_data); 3559 hlen = iphl + offset; 3560 if (__predict_false(m0->m_len < 3561 (hlen + sizeof(struct tcphdr)))) { 3562 3563 aprint_debug_dev(sc->bge_dev, 3564 "TSO: hard case m0->m_len == %d < ip/tcp hlen %zd," 3565 "not handled yet\n", 3566 m0->m_len, hlen+ sizeof(struct tcphdr)); 3567 #ifdef NOTYET 3568 /* 3569 * XXX jonathan (at) NetBSD.org: untested. 3570 * how to force this branch to be taken? 3571 */ 3572 BGE_EVCNT_INCR(&sc->sc_ev_txtsopain); 3573 3574 m_copydata(m0, offset, sizeof(ip), &ip); 3575 m_copydata(m0, hlen, sizeof(th), &th); 3576 3577 ip.ip_len = 0; 3578 3579 m_copyback(m0, hlen + offsetof(struct ip, ip_len), 3580 sizeof(ip.ip_len), &ip.ip_len); 3581 3582 th.th_sum = in_cksum_phdr(ip.ip_src.s_addr, 3583 ip.ip_dst.s_addr, htons(IPPROTO_TCP)); 3584 3585 m_copyback(m0, hlen + offsetof(struct tcphdr, th_sum), 3586 sizeof(th.th_sum), &th.th_sum); 3587 3588 hlen += th.th_off << 2; 3589 iptcp_opt_words = hlen; 3590 #else 3591 /* 3592 * if_wm "hard" case not yet supported, can we not 3593 * mandate it out of existence? 3594 */ 3595 (void) ip; (void)th; (void) ip_tcp_hlen; 3596 3597 return ENOBUFS; 3598 #endif 3599 } else { 3600 ip = (struct ip *) (mtod(m0, char *) + offset); 3601 th = (struct tcphdr *) (mtod(m0, char *) + hlen); 3602 ip_tcp_hlen = iphl + (th->th_off << 2); 3603 3604 /* Total IP/TCP options, in 32-bit words */ 3605 iptcp_opt_words = (ip_tcp_hlen 3606 - sizeof(struct tcphdr) 3607 - sizeof(struct ip)) >> 2; 3608 } 3609 if (BGE_IS_5750_OR_BEYOND(sc)) { 3610 th->th_sum = 0; 3611 csum_flags &= ~(BGE_TXBDFLAG_TCP_UDP_CSUM); 3612 } else { 3613 /* 3614 * XXX jonathan (at) NetBSD.org: 5705 untested. 3615 * Requires TSO firmware patch for 5701/5703/5704. 3616 */ 3617 th->th_sum = in_cksum_phdr(ip->ip_src.s_addr, 3618 ip->ip_dst.s_addr, htons(IPPROTO_TCP)); 3619 } 3620 3621 mss = m_head->m_pkthdr.segsz; 3622 txbd_tso_flags |= 3623 BGE_TXBDFLAG_CPU_PRE_DMA | 3624 BGE_TXBDFLAG_CPU_POST_DMA; 3625 3626 /* 3627 * Our NIC TSO-assist assumes TSO has standard, optionless 3628 * IPv4 and TCP headers, which total 40 bytes. By default, 3629 * the NIC copies 40 bytes of IP/TCP header from the 3630 * supplied header into the IP/TCP header portion of 3631 * each post-TSO-segment. If the supplied packet has IP or 3632 * TCP options, we need to tell the NIC to copy those extra 3633 * bytes into each post-TSO header, in addition to the normal 3634 * 40-byte IP/TCP header (and to leave space accordingly). 3635 * Unfortunately, the driver encoding of option length 3636 * varies across different ASIC families. 3637 */ 3638 tcp_seg_flags = 0; 3639 if (iptcp_opt_words) { 3640 if (BGE_IS_5705_OR_BEYOND(sc)) { 3641 tcp_seg_flags = 3642 iptcp_opt_words << 11; 3643 } else { 3644 txbd_tso_flags |= 3645 iptcp_opt_words << 12; 3646 } 3647 } 3648 maxsegsize = mss | tcp_seg_flags; 3649 ip->ip_len = htons(mss + ip_tcp_hlen); 3650 3651 } /* TSO setup */ 3652 3653 /* 3654 * Start packing the mbufs in this chain into 3655 * the fragment pointers. Stop when we run out 3656 * of fragments or hit the end of the mbuf chain. 3657 */ 3658 error = bus_dmamap_load_mbuf(sc->bge_dmatag, dmamap, m_head, 3659 BUS_DMA_NOWAIT); 3660 if (error) 3661 return ENOBUFS; 3662 /* 3663 * Sanity check: avoid coming within 16 descriptors 3664 * of the end of the ring. 3665 */ 3666 if (dmamap->dm_nsegs > (BGE_TX_RING_CNT - sc->bge_txcnt - 16)) { 3667 BGE_TSO_PRINTF(("%s: " 3668 " dmamap_load_mbuf too close to ring wrap\n", 3669 device_xname(sc->bge_dev))); 3670 goto fail_unload; 3671 } 3672 3673 mtag = sc->ethercom.ec_nvlans ? 3674 m_tag_find(m_head, PACKET_TAG_VLAN, NULL) : NULL; 3675 3676 3677 /* Iterate over dmap-map fragments. */ 3678 for (i = 0; i < dmamap->dm_nsegs; i++) { 3679 f = &sc->bge_rdata->bge_tx_ring[frag]; 3680 if (sc->bge_cdata.bge_tx_chain[frag] != NULL) 3681 break; 3682 3683 bge_set_hostaddr(&f->bge_addr, dmamap->dm_segs[i].ds_addr); 3684 f->bge_len = dmamap->dm_segs[i].ds_len; 3685 3686 /* 3687 * For 5751 and follow-ons, for TSO we must turn 3688 * off checksum-assist flag in the tx-descr, and 3689 * supply the ASIC-revision-specific encoding 3690 * of TSO flags and segsize. 3691 */ 3692 if (use_tso) { 3693 if (BGE_IS_5750_OR_BEYOND(sc) || i == 0) { 3694 f->bge_rsvd = maxsegsize; 3695 f->bge_flags = csum_flags | txbd_tso_flags; 3696 } else { 3697 f->bge_rsvd = 0; 3698 f->bge_flags = 3699 (csum_flags | txbd_tso_flags) & 0x0fff; 3700 } 3701 } else { 3702 f->bge_rsvd = 0; 3703 f->bge_flags = csum_flags; 3704 } 3705 3706 if (mtag != NULL) { 3707 f->bge_flags |= BGE_TXBDFLAG_VLAN_TAG; 3708 f->bge_vlan_tag = VLAN_TAG_VALUE(mtag); 3709 } else { 3710 f->bge_vlan_tag = 0; 3711 } 3712 cur = frag; 3713 BGE_INC(frag, BGE_TX_RING_CNT); 3714 } 3715 3716 if (i < dmamap->dm_nsegs) { 3717 BGE_TSO_PRINTF(("%s: reached %d < dm_nsegs %d\n", 3718 device_xname(sc->bge_dev), i, dmamap->dm_nsegs)); 3719 goto fail_unload; 3720 } 3721 3722 bus_dmamap_sync(sc->bge_dmatag, dmamap, 0, dmamap->dm_mapsize, 3723 BUS_DMASYNC_PREWRITE); 3724 3725 if (frag == sc->bge_tx_saved_considx) { 3726 BGE_TSO_PRINTF(("%s: frag %d = wrapped id %d?\n", 3727 device_xname(sc->bge_dev), frag, sc->bge_tx_saved_considx)); 3728 3729 goto fail_unload; 3730 } 3731 3732 sc->bge_rdata->bge_tx_ring[cur].bge_flags |= BGE_TXBDFLAG_END; 3733 sc->bge_cdata.bge_tx_chain[cur] = m_head; 3734 SLIST_REMOVE_HEAD(&sc->txdma_list, link); 3735 sc->txdma[cur] = dma; 3736 sc->bge_txcnt += dmamap->dm_nsegs; 3737 3738 *txidx = frag; 3739 3740 return 0; 3741 3742 fail_unload: 3743 bus_dmamap_unload(sc->bge_dmatag, dmamap); 3744 3745 return ENOBUFS; 3746 } 3747 3748 /* 3749 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 3750 * to the mbuf data regions directly in the transmit descriptors. 3751 */ 3752 static void 3753 bge_start(struct ifnet *ifp) 3754 { 3755 struct bge_softc *sc; 3756 struct mbuf *m_head = NULL; 3757 uint32_t prodidx; 3758 int pkts = 0; 3759 3760 sc = ifp->if_softc; 3761 3762 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 3763 return; 3764 3765 prodidx = sc->bge_tx_prodidx; 3766 3767 while (sc->bge_cdata.bge_tx_chain[prodidx] == NULL) { 3768 IFQ_POLL(&ifp->if_snd, m_head); 3769 if (m_head == NULL) 3770 break; 3771 3772 #if 0 3773 /* 3774 * XXX 3775 * safety overkill. If this is a fragmented packet chain 3776 * with delayed TCP/UDP checksums, then only encapsulate 3777 * it if we have enough descriptors to handle the entire 3778 * chain at once. 3779 * (paranoia -- may not actually be needed) 3780 */ 3781 if (m_head->m_flags & M_FIRSTFRAG && 3782 m_head->m_pkthdr.csum_flags & (CSUM_DELAY_DATA)) { 3783 if ((BGE_TX_RING_CNT - sc->bge_txcnt) < 3784 M_CSUM_DATA_IPv4_OFFSET(m_head->m_pkthdr.csum_data) + 16) { 3785 ifp->if_flags |= IFF_OACTIVE; 3786 break; 3787 } 3788 } 3789 #endif 3790 3791 /* 3792 * Pack the data into the transmit ring. If we 3793 * don't have room, set the OACTIVE flag and wait 3794 * for the NIC to drain the ring. 3795 */ 3796 if (bge_encap(sc, m_head, &prodidx)) { 3797 ifp->if_flags |= IFF_OACTIVE; 3798 break; 3799 } 3800 3801 /* now we are committed to transmit the packet */ 3802 IFQ_DEQUEUE(&ifp->if_snd, m_head); 3803 pkts++; 3804 3805 /* 3806 * If there's a BPF listener, bounce a copy of this frame 3807 * to him. 3808 */ 3809 if (ifp->if_bpf) 3810 bpf_ops->bpf_mtap(ifp->if_bpf, m_head); 3811 } 3812 if (pkts == 0) 3813 return; 3814 3815 /* Transmit */ 3816 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); 3817 /* 5700 b2 errata */ 3818 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX) 3819 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); 3820 3821 sc->bge_tx_prodidx = prodidx; 3822 3823 /* 3824 * Set a timeout in case the chip goes out to lunch. 3825 */ 3826 ifp->if_timer = 5; 3827 } 3828 3829 static int 3830 bge_init(struct ifnet *ifp) 3831 { 3832 struct bge_softc *sc = ifp->if_softc; 3833 const uint16_t *m; 3834 int s, error = 0; 3835 3836 s = splnet(); 3837 3838 ifp = &sc->ethercom.ec_if; 3839 3840 /* Cancel pending I/O and flush buffers. */ 3841 bge_stop(ifp, 0); 3842 bge_reset(sc); 3843 bge_chipinit(sc); 3844 3845 /* 3846 * Init the various state machines, ring 3847 * control blocks and firmware. 3848 */ 3849 error = bge_blockinit(sc); 3850 if (error != 0) { 3851 aprint_error_dev(sc->bge_dev, "initialization error %d\n", 3852 error); 3853 splx(s); 3854 return error; 3855 } 3856 3857 ifp = &sc->ethercom.ec_if; 3858 3859 /* Specify MTU. */ 3860 CSR_WRITE_4(sc, BGE_RX_MTU, ifp->if_mtu + 3861 ETHER_HDR_LEN + ETHER_CRC_LEN + ETHER_VLAN_ENCAP_LEN); 3862 3863 /* Load our MAC address. */ 3864 m = (const uint16_t *)&(CLLADDR(ifp->if_sadl)[0]); 3865 CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0])); 3866 CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, (htons(m[1]) << 16) | htons(m[2])); 3867 3868 /* Enable or disable promiscuous mode as needed. */ 3869 if (ifp->if_flags & IFF_PROMISC) { 3870 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 3871 } else { 3872 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 3873 } 3874 3875 /* Program multicast filter. */ 3876 bge_setmulti(sc); 3877 3878 /* Init RX ring. */ 3879 bge_init_rx_ring_std(sc); 3880 3881 /* 3882 * Workaround for a bug in 5705 ASIC rev A0. Poll the NIC's 3883 * memory to insure that the chip has in fact read the first 3884 * entry of the ring. 3885 */ 3886 if (sc->bge_chipid == BGE_CHIPID_BCM5705_A0) { 3887 uint32_t v, i; 3888 for (i = 0; i < 10; i++) { 3889 DELAY(20); 3890 v = bge_readmem_ind(sc, BGE_STD_RX_RINGS + 8); 3891 if (v == (MCLBYTES - ETHER_ALIGN)) 3892 break; 3893 } 3894 if (i == 10) 3895 aprint_error_dev(sc->bge_dev, 3896 "5705 A0 chip failed to load RX ring\n"); 3897 } 3898 3899 /* Init jumbo RX ring. */ 3900 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 3901 bge_init_rx_ring_jumbo(sc); 3902 3903 /* Init our RX return ring index */ 3904 sc->bge_rx_saved_considx = 0; 3905 3906 /* Init TX ring. */ 3907 bge_init_tx_ring(sc); 3908 3909 /* Turn on transmitter */ 3910 BGE_SETBIT(sc, BGE_TX_MODE, BGE_TXMODE_ENABLE); 3911 3912 /* Turn on receiver */ 3913 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE); 3914 3915 CSR_WRITE_4(sc, BGE_MAX_RX_FRAME_LOWAT, 2); 3916 3917 /* Tell firmware we're alive. */ 3918 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 3919 3920 /* Enable host interrupts. */ 3921 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA); 3922 BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); 3923 bge_writembx(sc, BGE_MBX_IRQ0_LO, 0); 3924 3925 if ((error = bge_ifmedia_upd(ifp)) != 0) 3926 goto out; 3927 3928 ifp->if_flags |= IFF_RUNNING; 3929 ifp->if_flags &= ~IFF_OACTIVE; 3930 3931 callout_reset(&sc->bge_timeout, hz, bge_tick, sc); 3932 3933 out: 3934 splx(s); 3935 3936 return error; 3937 } 3938 3939 /* 3940 * Set media options. 3941 */ 3942 static int 3943 bge_ifmedia_upd(struct ifnet *ifp) 3944 { 3945 struct bge_softc *sc = ifp->if_softc; 3946 struct mii_data *mii = &sc->bge_mii; 3947 struct ifmedia *ifm = &sc->bge_ifmedia; 3948 int rc; 3949 3950 /* If this is a 1000baseX NIC, enable the TBI port. */ 3951 if (sc->bge_flags & BGE_PHY_FIBER_TBI) { 3952 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 3953 return EINVAL; 3954 switch (IFM_SUBTYPE(ifm->ifm_media)) { 3955 case IFM_AUTO: 3956 /* 3957 * The BCM5704 ASIC appears to have a special 3958 * mechanism for programming the autoneg 3959 * advertisement registers in TBI mode. 3960 */ 3961 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) { 3962 uint32_t sgdig; 3963 sgdig = CSR_READ_4(sc, BGE_SGDIG_STS); 3964 if (sgdig & BGE_SGDIGSTS_DONE) { 3965 CSR_WRITE_4(sc, BGE_TX_TBI_AUTONEG, 0); 3966 sgdig = CSR_READ_4(sc, BGE_SGDIG_CFG); 3967 sgdig |= BGE_SGDIGCFG_AUTO | 3968 BGE_SGDIGCFG_PAUSE_CAP | 3969 BGE_SGDIGCFG_ASYM_PAUSE; 3970 CSR_WRITE_4(sc, BGE_SGDIG_CFG, 3971 sgdig | BGE_SGDIGCFG_SEND); 3972 DELAY(5); 3973 CSR_WRITE_4(sc, BGE_SGDIG_CFG, sgdig); 3974 } 3975 } 3976 break; 3977 case IFM_1000_SX: 3978 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 3979 BGE_CLRBIT(sc, BGE_MAC_MODE, 3980 BGE_MACMODE_HALF_DUPLEX); 3981 } else { 3982 BGE_SETBIT(sc, BGE_MAC_MODE, 3983 BGE_MACMODE_HALF_DUPLEX); 3984 } 3985 break; 3986 default: 3987 return EINVAL; 3988 } 3989 /* XXX 802.3x flow control for 1000BASE-SX */ 3990 return 0; 3991 } 3992 3993 BGE_STS_SETBIT(sc, BGE_STS_LINK_EVT); 3994 if ((rc = mii_mediachg(mii)) == ENXIO) 3995 return 0; 3996 3997 /* 3998 * Force an interrupt so that we will call bge_link_upd 3999 * if needed and clear any pending link state attention. 4000 * Without this we are not getting any further interrupts 4001 * for link state changes and thus will not UP the link and 4002 * not be able to send in bge_start. The only way to get 4003 * things working was to receive a packet and get a RX intr. 4004 */ 4005 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 4006 sc->bge_flags & BGE_IS_5788) 4007 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET); 4008 else 4009 BGE_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW); 4010 4011 return rc; 4012 } 4013 4014 /* 4015 * Report current media status. 4016 */ 4017 static void 4018 bge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 4019 { 4020 struct bge_softc *sc = ifp->if_softc; 4021 struct mii_data *mii = &sc->bge_mii; 4022 4023 if (sc->bge_flags & BGE_PHY_FIBER_TBI) { 4024 ifmr->ifm_status = IFM_AVALID; 4025 ifmr->ifm_active = IFM_ETHER; 4026 if (CSR_READ_4(sc, BGE_MAC_STS) & 4027 BGE_MACSTAT_TBI_PCS_SYNCHED) 4028 ifmr->ifm_status |= IFM_ACTIVE; 4029 ifmr->ifm_active |= IFM_1000_SX; 4030 if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX) 4031 ifmr->ifm_active |= IFM_HDX; 4032 else 4033 ifmr->ifm_active |= IFM_FDX; 4034 return; 4035 } 4036 4037 mii_pollstat(mii); 4038 ifmr->ifm_status = mii->mii_media_status; 4039 ifmr->ifm_active = (mii->mii_media_active & ~IFM_ETH_FMASK) | 4040 sc->bge_flowflags; 4041 } 4042 4043 static int 4044 bge_ioctl(struct ifnet *ifp, u_long command, void *data) 4045 { 4046 struct bge_softc *sc = ifp->if_softc; 4047 struct ifreq *ifr = (struct ifreq *) data; 4048 int s, error = 0; 4049 struct mii_data *mii; 4050 4051 s = splnet(); 4052 4053 switch (command) { 4054 case SIOCSIFFLAGS: 4055 if ((error = ifioctl_common(ifp, command, data)) != 0) 4056 break; 4057 if (ifp->if_flags & IFF_UP) { 4058 /* 4059 * If only the state of the PROMISC flag changed, 4060 * then just use the 'set promisc mode' command 4061 * instead of reinitializing the entire NIC. Doing 4062 * a full re-init means reloading the firmware and 4063 * waiting for it to start up, which may take a 4064 * second or two. 4065 */ 4066 if (ifp->if_flags & IFF_RUNNING && 4067 ifp->if_flags & IFF_PROMISC && 4068 !(sc->bge_if_flags & IFF_PROMISC)) { 4069 BGE_SETBIT(sc, BGE_RX_MODE, 4070 BGE_RXMODE_RX_PROMISC); 4071 } else if (ifp->if_flags & IFF_RUNNING && 4072 !(ifp->if_flags & IFF_PROMISC) && 4073 sc->bge_if_flags & IFF_PROMISC) { 4074 BGE_CLRBIT(sc, BGE_RX_MODE, 4075 BGE_RXMODE_RX_PROMISC); 4076 } else if (!(sc->bge_if_flags & IFF_UP)) 4077 bge_init(ifp); 4078 } else { 4079 if (ifp->if_flags & IFF_RUNNING) 4080 bge_stop(ifp, 1); 4081 } 4082 sc->bge_if_flags = ifp->if_flags; 4083 error = 0; 4084 break; 4085 case SIOCSIFMEDIA: 4086 /* XXX Flow control is not supported for 1000BASE-SX */ 4087 if (sc->bge_flags & BGE_PHY_FIBER_TBI) { 4088 ifr->ifr_media &= ~IFM_ETH_FMASK; 4089 sc->bge_flowflags = 0; 4090 } 4091 4092 /* Flow control requires full-duplex mode. */ 4093 if (IFM_SUBTYPE(ifr->ifr_media) == IFM_AUTO || 4094 (ifr->ifr_media & IFM_FDX) == 0) { 4095 ifr->ifr_media &= ~IFM_ETH_FMASK; 4096 } 4097 if (IFM_SUBTYPE(ifr->ifr_media) != IFM_AUTO) { 4098 if ((ifr->ifr_media & IFM_ETH_FMASK) == IFM_FLOW) { 4099 /* We can do both TXPAUSE and RXPAUSE. */ 4100 ifr->ifr_media |= 4101 IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE; 4102 } 4103 sc->bge_flowflags = ifr->ifr_media & IFM_ETH_FMASK; 4104 } 4105 /* FALLTHROUGH */ 4106 case SIOCGIFMEDIA: 4107 if (sc->bge_flags & BGE_PHY_FIBER_TBI) { 4108 error = ifmedia_ioctl(ifp, ifr, &sc->bge_ifmedia, 4109 command); 4110 } else { 4111 mii = &sc->bge_mii; 4112 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, 4113 command); 4114 } 4115 break; 4116 default: 4117 if ((error = ether_ioctl(ifp, command, data)) != ENETRESET) 4118 break; 4119 4120 error = 0; 4121 4122 if (command != SIOCADDMULTI && command != SIOCDELMULTI) 4123 ; 4124 else if (ifp->if_flags & IFF_RUNNING) 4125 bge_setmulti(sc); 4126 break; 4127 } 4128 4129 splx(s); 4130 4131 return error; 4132 } 4133 4134 static void 4135 bge_watchdog(struct ifnet *ifp) 4136 { 4137 struct bge_softc *sc; 4138 4139 sc = ifp->if_softc; 4140 4141 aprint_error_dev(sc->bge_dev, "watchdog timeout -- resetting\n"); 4142 4143 ifp->if_flags &= ~IFF_RUNNING; 4144 bge_init(ifp); 4145 4146 ifp->if_oerrors++; 4147 } 4148 4149 static void 4150 bge_stop_block(struct bge_softc *sc, bus_addr_t reg, uint32_t bit) 4151 { 4152 int i; 4153 4154 BGE_CLRBIT(sc, reg, bit); 4155 4156 for (i = 0; i < BGE_TIMEOUT; i++) { 4157 if ((CSR_READ_4(sc, reg) & bit) == 0) 4158 return; 4159 delay(100); 4160 if (sc->bge_flags & BGE_PCIE) 4161 DELAY(1000); 4162 } 4163 4164 /* 4165 * Doesn't print only when the register is BGE_SRS_MODE. It occurs 4166 * on some environment (and once after boot?) 4167 */ 4168 if (reg != BGE_SRS_MODE) 4169 aprint_error_dev(sc->bge_dev, 4170 "block failed to stop: reg 0x%lx, bit 0x%08x\n", 4171 (u_long)reg, bit); 4172 } 4173 4174 /* 4175 * Stop the adapter and free any mbufs allocated to the 4176 * RX and TX lists. 4177 */ 4178 static void 4179 bge_stop(struct ifnet *ifp, int disable) 4180 { 4181 struct bge_softc *sc = ifp->if_softc; 4182 4183 callout_stop(&sc->bge_timeout); 4184 4185 /* 4186 * Disable all of the receiver blocks 4187 */ 4188 bge_stop_block(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE); 4189 bge_stop_block(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 4190 bge_stop_block(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 4191 if (!(BGE_IS_5705_OR_BEYOND(sc))) 4192 bge_stop_block(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 4193 bge_stop_block(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE); 4194 bge_stop_block(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 4195 bge_stop_block(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE); 4196 4197 /* 4198 * Disable all of the transmit blocks 4199 */ 4200 bge_stop_block(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 4201 bge_stop_block(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 4202 bge_stop_block(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 4203 bge_stop_block(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE); 4204 bge_stop_block(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE); 4205 if (!(BGE_IS_5705_OR_BEYOND(sc))) 4206 bge_stop_block(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 4207 bge_stop_block(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 4208 4209 /* 4210 * Shut down all of the memory managers and related 4211 * state machines. 4212 */ 4213 bge_stop_block(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE); 4214 bge_stop_block(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE); 4215 if (!(BGE_IS_5705_OR_BEYOND(sc))) 4216 bge_stop_block(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 4217 4218 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 4219 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 4220 4221 if (!(BGE_IS_5705_OR_BEYOND(sc))) { 4222 bge_stop_block(sc, BGE_BMAN_MODE, BGE_BMANMODE_ENABLE); 4223 bge_stop_block(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 4224 } 4225 4226 /* Disable host interrupts. */ 4227 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); 4228 bge_writembx(sc, BGE_MBX_IRQ0_LO, 1); 4229 4230 /* 4231 * Tell firmware we're shutting down. 4232 */ 4233 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 4234 4235 /* Free the RX lists. */ 4236 bge_free_rx_ring_std(sc); 4237 4238 /* Free jumbo RX list. */ 4239 bge_free_rx_ring_jumbo(sc); 4240 4241 /* Free TX buffers. */ 4242 bge_free_tx_ring(sc); 4243 4244 /* 4245 * Isolate/power down the PHY. 4246 */ 4247 if (!(sc->bge_flags & BGE_PHY_FIBER_TBI)) 4248 mii_down(&sc->bge_mii); 4249 4250 sc->bge_tx_saved_considx = BGE_TXCONS_UNSET; 4251 4252 /* Clear MAC's link state (PHY may still have link UP). */ 4253 BGE_STS_CLRBIT(sc, BGE_STS_LINK); 4254 4255 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 4256 } 4257 4258 static void 4259 bge_link_upd(struct bge_softc *sc) 4260 { 4261 struct ifnet *ifp = &sc->ethercom.ec_if; 4262 struct mii_data *mii = &sc->bge_mii; 4263 uint32_t status; 4264 int link; 4265 4266 /* Clear 'pending link event' flag */ 4267 BGE_STS_CLRBIT(sc, BGE_STS_LINK_EVT); 4268 4269 /* 4270 * Process link state changes. 4271 * Grrr. The link status word in the status block does 4272 * not work correctly on the BCM5700 rev AX and BX chips, 4273 * according to all available information. Hence, we have 4274 * to enable MII interrupts in order to properly obtain 4275 * async link changes. Unfortunately, this also means that 4276 * we have to read the MAC status register to detect link 4277 * changes, thereby adding an additional register access to 4278 * the interrupt handler. 4279 */ 4280 4281 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700) { 4282 status = CSR_READ_4(sc, BGE_MAC_STS); 4283 if (status & BGE_MACSTAT_MI_INTERRUPT) { 4284 mii_pollstat(mii); 4285 4286 if (!BGE_STS_BIT(sc, BGE_STS_LINK) && 4287 mii->mii_media_status & IFM_ACTIVE && 4288 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) 4289 BGE_STS_SETBIT(sc, BGE_STS_LINK); 4290 else if (BGE_STS_BIT(sc, BGE_STS_LINK) && 4291 (!(mii->mii_media_status & IFM_ACTIVE) || 4292 IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) 4293 BGE_STS_CLRBIT(sc, BGE_STS_LINK); 4294 4295 /* Clear the interrupt */ 4296 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, 4297 BGE_EVTENB_MI_INTERRUPT); 4298 bge_miibus_readreg(sc->bge_dev, 1, BRGPHY_MII_ISR); 4299 bge_miibus_writereg(sc->bge_dev, 1, BRGPHY_MII_IMR, 4300 BRGPHY_INTRS); 4301 } 4302 return; 4303 } 4304 4305 if (sc->bge_flags & BGE_PHY_FIBER_TBI) { 4306 status = CSR_READ_4(sc, BGE_MAC_STS); 4307 if (status & BGE_MACSTAT_TBI_PCS_SYNCHED) { 4308 if (!BGE_STS_BIT(sc, BGE_STS_LINK)) { 4309 BGE_STS_SETBIT(sc, BGE_STS_LINK); 4310 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) 4311 BGE_CLRBIT(sc, BGE_MAC_MODE, 4312 BGE_MACMODE_TBI_SEND_CFGS); 4313 CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF); 4314 if_link_state_change(ifp, LINK_STATE_UP); 4315 } 4316 } else if (BGE_STS_BIT(sc, BGE_STS_LINK)) { 4317 BGE_STS_CLRBIT(sc, BGE_STS_LINK); 4318 if_link_state_change(ifp, LINK_STATE_DOWN); 4319 } 4320 /* 4321 * Discard link events for MII/GMII cards if MI auto-polling disabled. 4322 * This should not happen since mii callouts are locked now, but 4323 * we keep this check for debug. 4324 */ 4325 } else if (BGE_STS_BIT(sc, BGE_STS_AUTOPOLL)) { 4326 /* 4327 * Some broken BCM chips have BGE_STATFLAG_LINKSTATE_CHANGED 4328 * bit in status word always set. Workaround this bug by 4329 * reading PHY link status directly. 4330 */ 4331 link = (CSR_READ_4(sc, BGE_MI_STS) & BGE_MISTS_LINK)? 4332 BGE_STS_LINK : 0; 4333 4334 if (BGE_STS_BIT(sc, BGE_STS_LINK) != link) { 4335 mii_pollstat(mii); 4336 4337 if (!BGE_STS_BIT(sc, BGE_STS_LINK) && 4338 mii->mii_media_status & IFM_ACTIVE && 4339 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) 4340 BGE_STS_SETBIT(sc, BGE_STS_LINK); 4341 else if (BGE_STS_BIT(sc, BGE_STS_LINK) && 4342 (!(mii->mii_media_status & IFM_ACTIVE) || 4343 IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) 4344 BGE_STS_CLRBIT(sc, BGE_STS_LINK); 4345 } 4346 } 4347 4348 /* Clear the attention */ 4349 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED| 4350 BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE| 4351 BGE_MACSTAT_LINK_CHANGED); 4352 } 4353 4354 static int 4355 sysctl_bge_verify(SYSCTLFN_ARGS) 4356 { 4357 int error, t; 4358 struct sysctlnode node; 4359 4360 node = *rnode; 4361 t = *(int*)rnode->sysctl_data; 4362 node.sysctl_data = &t; 4363 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 4364 if (error || newp == NULL) 4365 return error; 4366 4367 #if 0 4368 DPRINTF2(("%s: t = %d, nodenum = %d, rnodenum = %d\n", __func__, t, 4369 node.sysctl_num, rnode->sysctl_num)); 4370 #endif 4371 4372 if (node.sysctl_num == bge_rxthresh_nodenum) { 4373 if (t < 0 || t >= NBGE_RX_THRESH) 4374 return EINVAL; 4375 bge_update_all_threshes(t); 4376 } else 4377 return EINVAL; 4378 4379 *(int*)rnode->sysctl_data = t; 4380 4381 return 0; 4382 } 4383 4384 /* 4385 * Set up sysctl(3) MIB, hw.bge.*. 4386 * 4387 * TBD condition SYSCTL_PERMANENT on being an LKM or not 4388 */ 4389 SYSCTL_SETUP(sysctl_bge, "sysctl bge subtree setup") 4390 { 4391 int rc, bge_root_num; 4392 const struct sysctlnode *node; 4393 4394 if ((rc = sysctl_createv(clog, 0, NULL, NULL, 4395 CTLFLAG_PERMANENT, CTLTYPE_NODE, "hw", NULL, 4396 NULL, 0, NULL, 0, CTL_HW, CTL_EOL)) != 0) { 4397 goto err; 4398 } 4399 4400 if ((rc = sysctl_createv(clog, 0, NULL, &node, 4401 CTLFLAG_PERMANENT, CTLTYPE_NODE, "bge", 4402 SYSCTL_DESCR("BGE interface controls"), 4403 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL)) != 0) { 4404 goto err; 4405 } 4406 4407 bge_root_num = node->sysctl_num; 4408 4409 /* BGE Rx interrupt mitigation level */ 4410 if ((rc = sysctl_createv(clog, 0, NULL, &node, 4411 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, 4412 CTLTYPE_INT, "rx_lvl", 4413 SYSCTL_DESCR("BGE receive interrupt mitigation level"), 4414 sysctl_bge_verify, 0, 4415 &bge_rx_thresh_lvl, 4416 0, CTL_HW, bge_root_num, CTL_CREATE, 4417 CTL_EOL)) != 0) { 4418 goto err; 4419 } 4420 4421 bge_rxthresh_nodenum = node->sysctl_num; 4422 4423 return; 4424 4425 err: 4426 aprint_error("%s: sysctl_createv failed (rc = %d)\n", __func__, rc); 4427 } 4428 4429 static int 4430 bge_get_eaddr_mem(struct bge_softc *sc, uint8_t ether_addr[]) 4431 { 4432 uint32_t mac_addr; 4433 4434 mac_addr = bge_readmem_ind(sc, 0x0c14); 4435 if ((mac_addr >> 16) == 0x484b) { 4436 ether_addr[0] = (uint8_t)(mac_addr >> 8); 4437 ether_addr[1] = (uint8_t)mac_addr; 4438 mac_addr = bge_readmem_ind(sc, 0x0c18); 4439 ether_addr[2] = (uint8_t)(mac_addr >> 24); 4440 ether_addr[3] = (uint8_t)(mac_addr >> 16); 4441 ether_addr[4] = (uint8_t)(mac_addr >> 8); 4442 ether_addr[5] = (uint8_t)mac_addr; 4443 return 0; 4444 } 4445 return 1; 4446 } 4447 4448 static int 4449 bge_get_eaddr_nvram(struct bge_softc *sc, uint8_t ether_addr[]) 4450 { 4451 int mac_offset = BGE_EE_MAC_OFFSET; 4452 4453 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 4454 mac_offset = BGE_EE_MAC_OFFSET_5906; 4455 } 4456 4457 return (bge_read_nvram(sc, ether_addr, mac_offset + 2, 4458 ETHER_ADDR_LEN)); 4459 } 4460 4461 static int 4462 bge_get_eaddr_eeprom(struct bge_softc *sc, uint8_t ether_addr[]) 4463 { 4464 4465 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 4466 return 1; 4467 4468 return (bge_read_eeprom(sc, ether_addr, BGE_EE_MAC_OFFSET + 2, 4469 ETHER_ADDR_LEN)); 4470 } 4471 4472 static int 4473 bge_get_eaddr(struct bge_softc *sc, uint8_t eaddr[]) 4474 { 4475 static const bge_eaddr_fcn_t bge_eaddr_funcs[] = { 4476 /* NOTE: Order is critical */ 4477 bge_get_eaddr_mem, 4478 bge_get_eaddr_nvram, 4479 bge_get_eaddr_eeprom, 4480 NULL 4481 }; 4482 const bge_eaddr_fcn_t *func; 4483 4484 for (func = bge_eaddr_funcs; *func != NULL; ++func) { 4485 if ((*func)(sc, eaddr) == 0) 4486 break; 4487 } 4488 return (*func == NULL ? ENXIO : 0); 4489 } 4490
Indexes created Mon Sep 22 13:09:51 GMT 2025