if_bge.c revision 1.175
1 /* $NetBSD: if_bge.c,v 1.175 2010/01/24 23:27:39 martin Exp $ */ 2 3 /* 4 * Copyright (c) 2001 Wind River Systems 5 * Copyright (c) 1997, 1998, 1999, 2001 6 * Bill Paul <wpaul (at) windriver.com>. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Bill Paul. 19 * 4. Neither the name of the author nor the names of any co-contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 33 * THE POSSIBILITY OF SUCH DAMAGE. 34 * 35 * $FreeBSD: if_bge.c,v 1.13 2002/04/04 06:01:31 wpaul Exp $ 36 */ 37 38 /* 39 * Broadcom BCM570x family gigabit ethernet driver for NetBSD. 40 * 41 * NetBSD version by: 42 * 43 * Frank van der Linden <fvdl (at) wasabisystems.com> 44 * Jason Thorpe <thorpej (at) wasabisystems.com> 45 * Jonathan Stone <jonathan (at) dsg.stanford.edu> 46 * 47 * Originally written for FreeBSD by Bill Paul <wpaul (at) windriver.com> 48 * Senior Engineer, Wind River Systems 49 */ 50 51 /* 52 * The Broadcom BCM5700 is based on technology originally developed by 53 * Alteon Networks as part of the Tigon I and Tigon II gigabit ethernet 54 * MAC chips. The BCM5700, sometimes refered to as the Tigon III, has 55 * two on-board MIPS R4000 CPUs and can have as much as 16MB of external 56 * SSRAM. The BCM5700 supports TCP, UDP and IP checksum offload, jumbo 57 * frames, highly configurable RX filtering, and 16 RX and TX queues 58 * (which, along with RX filter rules, can be used for QOS applications). 59 * Other features, such as TCP segmentation, may be available as part 60 * of value-added firmware updates. Unlike the Tigon I and Tigon II, 61 * firmware images can be stored in hardware and need not be compiled 62 * into the driver. 63 * 64 * The BCM5700 supports the PCI v2.2 and PCI-X v1.0 standards, and will 65 * function in a 32-bit/64-bit 33/66MHz bus, or a 64-bit/133MHz bus. 66 * 67 * The BCM5701 is a single-chip solution incorporating both the BCM5700 68 * MAC and a BCM5401 10/100/1000 PHY. Unlike the BCM5700, the BCM5701 69 * does not support external SSRAM. 70 * 71 * Broadcom also produces a variation of the BCM5700 under the "Altima" 72 * brand name, which is functionally similar but lacks PCI-X support. 73 * 74 * Without external SSRAM, you can only have at most 4 TX rings, 75 * and the use of the mini RX ring is disabled. This seems to imply 76 * that these features are simply not available on the BCM5701. As a 77 * result, this driver does not implement any support for the mini RX 78 * ring. 79 */ 80 81 #include <sys/cdefs.h> 82 __KERNEL_RCSID(0, "$NetBSD: if_bge.c,v 1.175 2010/01/24 23:27:39 martin Exp $"); 83 84 #include "vlan.h" 85 #include "rnd.h" 86 87 #include <sys/param.h> 88 #include <sys/systm.h> 89 #include <sys/callout.h> 90 #include <sys/sockio.h> 91 #include <sys/mbuf.h> 92 #include <sys/malloc.h> 93 #include <sys/kernel.h> 94 #include <sys/device.h> 95 #include <sys/socket.h> 96 #include <sys/sysctl.h> 97 98 #include <net/if.h> 99 #include <net/if_dl.h> 100 #include <net/if_media.h> 101 #include <net/if_ether.h> 102 103 #if NRND > 0 104 #include <sys/rnd.h> 105 #endif 106 107 #ifdef INET 108 #include <netinet/in.h> 109 #include <netinet/in_systm.h> 110 #include <netinet/in_var.h> 111 #include <netinet/ip.h> 112 #endif 113 114 /* Headers for TCP Segmentation Offload (TSO) */ 115 #include <netinet/in_systm.h> /* n_time for <netinet/ip.h>... */ 116 #include <netinet/in.h> /* ip_{src,dst}, for <netinet/ip.h> */ 117 #include <netinet/ip.h> /* for struct ip */ 118 #include <netinet/tcp.h> /* for struct tcphdr */ 119 120 121 #include <net/bpf.h> 122 123 #include <dev/pci/pcireg.h> 124 #include <dev/pci/pcivar.h> 125 #include <dev/pci/pcidevs.h> 126 127 #include <dev/mii/mii.h> 128 #include <dev/mii/miivar.h> 129 #include <dev/mii/miidevs.h> 130 #include <dev/mii/brgphyreg.h> 131 132 #include <dev/pci/if_bgereg.h> 133 #include <dev/pci/if_bgevar.h> 134 135 #include <uvm/uvm_extern.h> 136 #include <prop/proplib.h> 137 138 #define ETHER_MIN_NOPAD (ETHER_MIN_LEN - ETHER_CRC_LEN) /* i.e., 60 */ 139 140 141 /* 142 * Tunable thresholds for rx-side bge interrupt mitigation. 143 */ 144 145 /* 146 * The pairs of values below were obtained from empirical measurement 147 * on bcm5700 rev B2; they ar designed to give roughly 1 receive 148 * interrupt for every N packets received, where N is, approximately, 149 * the second value (rx_max_bds) in each pair. The values are chosen 150 * such that moving from one pair to the succeeding pair was observed 151 * to roughly halve interrupt rate under sustained input packet load. 152 * The values were empirically chosen to avoid overflowing internal 153 * limits on the bcm5700: inreasing rx_ticks much beyond 600 154 * results in internal wrapping and higher interrupt rates. 155 * The limit of 46 frames was chosen to match NFS workloads. 156 * 157 * These values also work well on bcm5701, bcm5704C, and (less 158 * tested) bcm5703. On other chipsets, (including the Altima chip 159 * family), the larger values may overflow internal chip limits, 160 * leading to increasing interrupt rates rather than lower interrupt 161 * rates. 162 * 163 * Applications using heavy interrupt mitigation (interrupting every 164 * 32 or 46 frames) in both directions may need to increase the TCP 165 * windowsize to above 131072 bytes (e.g., to 199608 bytes) to sustain 166 * full link bandwidth, due to ACKs and window updates lingering 167 * in the RX queue during the 30-to-40-frame interrupt-mitigation window. 168 */ 169 static const struct bge_load_rx_thresh { 170 int rx_ticks; 171 int rx_max_bds; } 172 bge_rx_threshes[] = { 173 { 32, 2 }, 174 { 50, 4 }, 175 { 100, 8 }, 176 { 192, 16 }, 177 { 416, 32 }, 178 { 598, 46 } 179 }; 180 #define NBGE_RX_THRESH (sizeof(bge_rx_threshes) / sizeof(bge_rx_threshes[0])) 181 182 /* XXX patchable; should be sysctl'able */ 183 static int bge_auto_thresh = 1; 184 static int bge_rx_thresh_lvl; 185 186 static int bge_rxthresh_nodenum; 187 188 typedef int (*bge_eaddr_fcn_t)(struct bge_softc *, uint8_t[]); 189 190 static int bge_probe(device_t, cfdata_t, void *); 191 static void bge_attach(device_t, device_t, void *); 192 static void bge_release_resources(struct bge_softc *); 193 static void bge_txeof(struct bge_softc *); 194 static void bge_rxeof(struct bge_softc *); 195 196 static int bge_get_eaddr_fw(struct bge_softc *, uint8_t[]); 197 static int bge_get_eaddr_mem(struct bge_softc *, uint8_t[]); 198 static int bge_get_eaddr_nvram(struct bge_softc *, uint8_t[]); 199 static int bge_get_eaddr_eeprom(struct bge_softc *, uint8_t[]); 200 static int bge_get_eaddr(struct bge_softc *, uint8_t[]); 201 202 static void bge_tick(void *); 203 static void bge_stats_update(struct bge_softc *); 204 static void bge_stats_update_regs(struct bge_softc *); 205 static int bge_encap(struct bge_softc *, struct mbuf *, uint32_t *); 206 207 static int bge_intr(void *); 208 static void bge_start(struct ifnet *); 209 static int bge_ioctl(struct ifnet *, u_long, void *); 210 static int bge_init(struct ifnet *); 211 static void bge_stop(struct ifnet *, int); 212 static void bge_watchdog(struct ifnet *); 213 static int bge_ifmedia_upd(struct ifnet *); 214 static void bge_ifmedia_sts(struct ifnet *, struct ifmediareq *); 215 216 static void bge_setmulti(struct bge_softc *); 217 218 static void bge_handle_events(struct bge_softc *); 219 static int bge_alloc_jumbo_mem(struct bge_softc *); 220 #if 0 /* XXX */ 221 static void bge_free_jumbo_mem(struct bge_softc *); 222 #endif 223 static void *bge_jalloc(struct bge_softc *); 224 static void bge_jfree(struct mbuf *, void *, size_t, void *); 225 static int bge_newbuf_std(struct bge_softc *, int, struct mbuf *, 226 bus_dmamap_t); 227 static int bge_newbuf_jumbo(struct bge_softc *, int, struct mbuf *); 228 static int bge_init_rx_ring_std(struct bge_softc *); 229 static void bge_free_rx_ring_std(struct bge_softc *); 230 static int bge_init_rx_ring_jumbo(struct bge_softc *); 231 static void bge_free_rx_ring_jumbo(struct bge_softc *); 232 static void bge_free_tx_ring(struct bge_softc *); 233 static int bge_init_tx_ring(struct bge_softc *); 234 235 static int bge_chipinit(struct bge_softc *); 236 static int bge_blockinit(struct bge_softc *); 237 static int bge_setpowerstate(struct bge_softc *, int); 238 239 static void bge_reset(struct bge_softc *); 240 static void bge_link_upd(struct bge_softc *); 241 242 #ifdef BGE_DEBUG 243 #define DPRINTF(x) if (bgedebug) printf x 244 #define DPRINTFN(n,x) if (bgedebug >= (n)) printf x 245 #define BGE_TSO_PRINTF(x) do { if (bge_tso_debug) printf x ;} while (0) 246 int bgedebug = 0; 247 int bge_tso_debug = 0; 248 void bge_debug_info(struct bge_softc *); 249 #else 250 #define DPRINTF(x) 251 #define DPRINTFN(n,x) 252 #define BGE_TSO_PRINTF(x) 253 #endif 254 255 #ifdef BGE_EVENT_COUNTERS 256 #define BGE_EVCNT_INCR(ev) (ev).ev_count++ 257 #define BGE_EVCNT_ADD(ev, val) (ev).ev_count += (val) 258 #define BGE_EVCNT_UPD(ev, val) (ev).ev_count = (val) 259 #else 260 #define BGE_EVCNT_INCR(ev) /* nothing */ 261 #define BGE_EVCNT_ADD(ev, val) /* nothing */ 262 #define BGE_EVCNT_UPD(ev, val) /* nothing */ 263 #endif 264 265 static const struct bge_product { 266 pci_vendor_id_t bp_vendor; 267 pci_product_id_t bp_product; 268 const char *bp_name; 269 } bge_products[] = { 270 /* 271 * The BCM5700 documentation seems to indicate that the hardware 272 * still has the Alteon vendor ID burned into it, though it 273 * should always be overridden by the value in the EEPROM. We'll 274 * check for it anyway. 275 */ 276 { PCI_VENDOR_ALTEON, 277 PCI_PRODUCT_ALTEON_BCM5700, 278 "Broadcom BCM5700 Gigabit Ethernet", 279 }, 280 { PCI_VENDOR_ALTEON, 281 PCI_PRODUCT_ALTEON_BCM5701, 282 "Broadcom BCM5701 Gigabit Ethernet", 283 }, 284 { PCI_VENDOR_ALTIMA, 285 PCI_PRODUCT_ALTIMA_AC1000, 286 "Altima AC1000 Gigabit Ethernet", 287 }, 288 { PCI_VENDOR_ALTIMA, 289 PCI_PRODUCT_ALTIMA_AC1001, 290 "Altima AC1001 Gigabit Ethernet", 291 }, 292 { PCI_VENDOR_ALTIMA, 293 PCI_PRODUCT_ALTIMA_AC9100, 294 "Altima AC9100 Gigabit Ethernet", 295 }, 296 { PCI_VENDOR_BROADCOM, 297 PCI_PRODUCT_BROADCOM_BCM5700, 298 "Broadcom BCM5700 Gigabit Ethernet", 299 }, 300 { PCI_VENDOR_BROADCOM, 301 PCI_PRODUCT_BROADCOM_BCM5701, 302 "Broadcom BCM5701 Gigabit Ethernet", 303 }, 304 { PCI_VENDOR_BROADCOM, 305 PCI_PRODUCT_BROADCOM_BCM5702, 306 "Broadcom BCM5702 Gigabit Ethernet", 307 }, 308 { PCI_VENDOR_BROADCOM, 309 PCI_PRODUCT_BROADCOM_BCM5702X, 310 "Broadcom BCM5702X Gigabit Ethernet" }, 311 { PCI_VENDOR_BROADCOM, 312 PCI_PRODUCT_BROADCOM_BCM5703, 313 "Broadcom BCM5703 Gigabit Ethernet", 314 }, 315 { PCI_VENDOR_BROADCOM, 316 PCI_PRODUCT_BROADCOM_BCM5703X, 317 "Broadcom BCM5703X Gigabit Ethernet", 318 }, 319 { PCI_VENDOR_BROADCOM, 320 PCI_PRODUCT_BROADCOM_BCM5703_ALT, 321 "Broadcom BCM5703 Gigabit Ethernet", 322 }, 323 { PCI_VENDOR_BROADCOM, 324 PCI_PRODUCT_BROADCOM_BCM5704C, 325 "Broadcom BCM5704C Dual Gigabit Ethernet", 326 }, 327 { PCI_VENDOR_BROADCOM, 328 PCI_PRODUCT_BROADCOM_BCM5704S, 329 "Broadcom BCM5704S Dual Gigabit Ethernet", 330 }, 331 { PCI_VENDOR_BROADCOM, 332 PCI_PRODUCT_BROADCOM_BCM5705, 333 "Broadcom BCM5705 Gigabit Ethernet", 334 }, 335 { PCI_VENDOR_BROADCOM, 336 PCI_PRODUCT_BROADCOM_BCM5705F, 337 "Broadcom BCM5705F Gigabit Ethernet", 338 }, 339 { PCI_VENDOR_BROADCOM, 340 PCI_PRODUCT_BROADCOM_BCM5705K, 341 "Broadcom BCM5705K Gigabit Ethernet", 342 }, 343 { PCI_VENDOR_BROADCOM, 344 PCI_PRODUCT_BROADCOM_BCM5705M, 345 "Broadcom BCM5705M Gigabit Ethernet", 346 }, 347 { PCI_VENDOR_BROADCOM, 348 PCI_PRODUCT_BROADCOM_BCM5705M_ALT, 349 "Broadcom BCM5705M Gigabit Ethernet", 350 }, 351 { PCI_VENDOR_BROADCOM, 352 PCI_PRODUCT_BROADCOM_BCM5714, 353 "Broadcom BCM5714 Gigabit Ethernet", 354 }, 355 { PCI_VENDOR_BROADCOM, 356 PCI_PRODUCT_BROADCOM_BCM5714S, 357 "Broadcom BCM5714S Gigabit Ethernet", 358 }, 359 { PCI_VENDOR_BROADCOM, 360 PCI_PRODUCT_BROADCOM_BCM5715, 361 "Broadcom BCM5715 Gigabit Ethernet", 362 }, 363 { PCI_VENDOR_BROADCOM, 364 PCI_PRODUCT_BROADCOM_BCM5715S, 365 "Broadcom BCM5715S Gigabit Ethernet", 366 }, 367 { PCI_VENDOR_BROADCOM, 368 PCI_PRODUCT_BROADCOM_BCM5717, 369 "Broadcom BCM5717 Gigabit Ethernet", 370 }, 371 { PCI_VENDOR_BROADCOM, 372 PCI_PRODUCT_BROADCOM_BCM5718, 373 "Broadcom BCM5718 Gigabit Ethernet", 374 }, 375 { PCI_VENDOR_BROADCOM, 376 PCI_PRODUCT_BROADCOM_BCM5720, 377 "Broadcom BCM5720 Gigabit Ethernet", 378 }, 379 { PCI_VENDOR_BROADCOM, 380 PCI_PRODUCT_BROADCOM_BCM5721, 381 "Broadcom BCM5721 Gigabit Ethernet", 382 }, 383 { PCI_VENDOR_BROADCOM, 384 PCI_PRODUCT_BROADCOM_BCM5722, 385 "Broadcom BCM5722 Gigabit Ethernet", 386 }, 387 { PCI_VENDOR_BROADCOM, 388 PCI_PRODUCT_BROADCOM_BCM5723, 389 "Broadcom BCM5723 Gigabit Ethernet", 390 }, 391 { PCI_VENDOR_BROADCOM, 392 PCI_PRODUCT_BROADCOM_BCM5724, 393 "Broadcom BCM5724 Gigabit Ethernet", 394 }, 395 { PCI_VENDOR_BROADCOM, 396 PCI_PRODUCT_BROADCOM_BCM5750, 397 "Broadcom BCM5750 Gigabit Ethernet", 398 }, 399 { PCI_VENDOR_BROADCOM, 400 PCI_PRODUCT_BROADCOM_BCM5750M, 401 "Broadcom BCM5750M Gigabit Ethernet", 402 }, 403 { PCI_VENDOR_BROADCOM, 404 PCI_PRODUCT_BROADCOM_BCM5751, 405 "Broadcom BCM5751 Gigabit Ethernet", 406 }, 407 { PCI_VENDOR_BROADCOM, 408 PCI_PRODUCT_BROADCOM_BCM5751F, 409 "Broadcom BCM5751F Gigabit Ethernet", 410 }, 411 { PCI_VENDOR_BROADCOM, 412 PCI_PRODUCT_BROADCOM_BCM5751M, 413 "Broadcom BCM5751M Gigabit Ethernet", 414 }, 415 { PCI_VENDOR_BROADCOM, 416 PCI_PRODUCT_BROADCOM_BCM5752, 417 "Broadcom BCM5752 Gigabit Ethernet", 418 }, 419 { PCI_VENDOR_BROADCOM, 420 PCI_PRODUCT_BROADCOM_BCM5752M, 421 "Broadcom BCM5752M Gigabit Ethernet", 422 }, 423 { PCI_VENDOR_BROADCOM, 424 PCI_PRODUCT_BROADCOM_BCM5753, 425 "Broadcom BCM5753 Gigabit Ethernet", 426 }, 427 { PCI_VENDOR_BROADCOM, 428 PCI_PRODUCT_BROADCOM_BCM5753F, 429 "Broadcom BCM5753F Gigabit Ethernet", 430 }, 431 { PCI_VENDOR_BROADCOM, 432 PCI_PRODUCT_BROADCOM_BCM5753M, 433 "Broadcom BCM5753M Gigabit Ethernet", 434 }, 435 { PCI_VENDOR_BROADCOM, 436 PCI_PRODUCT_BROADCOM_BCM5754, 437 "Broadcom BCM5754 Gigabit Ethernet", 438 }, 439 { PCI_VENDOR_BROADCOM, 440 PCI_PRODUCT_BROADCOM_BCM5754M, 441 "Broadcom BCM5754M Gigabit Ethernet", 442 }, 443 { PCI_VENDOR_BROADCOM, 444 PCI_PRODUCT_BROADCOM_BCM5755, 445 "Broadcom BCM5755 Gigabit Ethernet", 446 }, 447 { PCI_VENDOR_BROADCOM, 448 PCI_PRODUCT_BROADCOM_BCM5755M, 449 "Broadcom BCM5755M Gigabit Ethernet", 450 }, 451 { PCI_VENDOR_BROADCOM, 452 PCI_PRODUCT_BROADCOM_BCM5756, 453 "Broadcom BCM5756 Gigabit Ethernet", 454 }, 455 { PCI_VENDOR_BROADCOM, 456 PCI_PRODUCT_BROADCOM_BCM5761, 457 "Broadcom BCM5761 Gigabit Ethernet", 458 }, 459 { PCI_VENDOR_BROADCOM, 460 PCI_PRODUCT_BROADCOM_BCM5761E, 461 "Broadcom BCM5761E Gigabit Ethernet", 462 }, 463 { PCI_VENDOR_BROADCOM, 464 PCI_PRODUCT_BROADCOM_BCM5761S, 465 "Broadcom BCM5761S Gigabit Ethernet", 466 }, 467 { PCI_VENDOR_BROADCOM, 468 PCI_PRODUCT_BROADCOM_BCM5761SE, 469 "Broadcom BCM5761SE Gigabit Ethernet", 470 }, 471 { PCI_VENDOR_BROADCOM, 472 PCI_PRODUCT_BROADCOM_BCM5764, 473 "Broadcom BCM5764 Gigabit Ethernet", 474 }, 475 { PCI_VENDOR_BROADCOM, 476 PCI_PRODUCT_BROADCOM_BCM5780, 477 "Broadcom BCM5780 Gigabit Ethernet", 478 }, 479 { PCI_VENDOR_BROADCOM, 480 PCI_PRODUCT_BROADCOM_BCM5780S, 481 "Broadcom BCM5780S Gigabit Ethernet", 482 }, 483 { PCI_VENDOR_BROADCOM, 484 PCI_PRODUCT_BROADCOM_BCM5781, 485 "Broadcom BCM5781 Gigabit Ethernet", 486 }, 487 { PCI_VENDOR_BROADCOM, 488 PCI_PRODUCT_BROADCOM_BCM5782, 489 "Broadcom BCM5782 Gigabit Ethernet", 490 }, 491 { PCI_VENDOR_BROADCOM, 492 PCI_PRODUCT_BROADCOM_BCM5784M, 493 "BCM5784M NetLink 1000baseT Ethernet", 494 }, 495 { PCI_VENDOR_BROADCOM, 496 PCI_PRODUCT_BROADCOM_BCM5786, 497 "Broadcom BCM5786 Gigabit Ethernet", 498 }, 499 { PCI_VENDOR_BROADCOM, 500 PCI_PRODUCT_BROADCOM_BCM5787, 501 "Broadcom BCM5787 Gigabit Ethernet", 502 }, 503 { PCI_VENDOR_BROADCOM, 504 PCI_PRODUCT_BROADCOM_BCM5787M, 505 "Broadcom BCM5787M Gigabit Ethernet", 506 }, 507 { PCI_VENDOR_BROADCOM, 508 PCI_PRODUCT_BROADCOM_BCM5788, 509 "Broadcom BCM5788 Gigabit Ethernet", 510 }, 511 { PCI_VENDOR_BROADCOM, 512 PCI_PRODUCT_BROADCOM_BCM5789, 513 "Broadcom BCM5789 Gigabit Ethernet", 514 }, 515 { PCI_VENDOR_BROADCOM, 516 PCI_PRODUCT_BROADCOM_BCM5901, 517 "Broadcom BCM5901 Fast Ethernet", 518 }, 519 { PCI_VENDOR_BROADCOM, 520 PCI_PRODUCT_BROADCOM_BCM5901A2, 521 "Broadcom BCM5901A2 Fast Ethernet", 522 }, 523 { PCI_VENDOR_BROADCOM, 524 PCI_PRODUCT_BROADCOM_BCM5903M, 525 "Broadcom BCM5903M Fast Ethernet", 526 }, 527 { PCI_VENDOR_BROADCOM, 528 PCI_PRODUCT_BROADCOM_BCM5906, 529 "Broadcom BCM5906 Fast Ethernet", 530 }, 531 { PCI_VENDOR_BROADCOM, 532 PCI_PRODUCT_BROADCOM_BCM5906M, 533 "Broadcom BCM5906M Fast Ethernet", 534 }, 535 { PCI_VENDOR_BROADCOM, 536 PCI_PRODUCT_BROADCOM_BCM57760, 537 "Broadcom BCM57760 Fast Ethernet", 538 }, 539 { PCI_VENDOR_BROADCOM, 540 PCI_PRODUCT_BROADCOM_BCM57761, 541 "Broadcom BCM57761 Fast Ethernet", 542 }, 543 { PCI_VENDOR_BROADCOM, 544 PCI_PRODUCT_BROADCOM_BCM57765, 545 "Broadcom BCM57765 Fast Ethernet", 546 }, 547 { PCI_VENDOR_BROADCOM, 548 PCI_PRODUCT_BROADCOM_BCM57780, 549 "Broadcom BCM57780 Fast Ethernet", 550 }, 551 { PCI_VENDOR_BROADCOM, 552 PCI_PRODUCT_BROADCOM_BCM57781, 553 "Broadcom BCM57781 Fast Ethernet", 554 }, 555 { PCI_VENDOR_BROADCOM, 556 PCI_PRODUCT_BROADCOM_BCM57785, 557 "Broadcom BCM57785 Fast Ethernet", 558 }, 559 { PCI_VENDOR_BROADCOM, 560 PCI_PRODUCT_BROADCOM_BCM57788, 561 "Broadcom BCM57788 Fast Ethernet", 562 }, 563 { PCI_VENDOR_BROADCOM, 564 PCI_PRODUCT_BROADCOM_BCM57790, 565 "Broadcom BCM57790 Fast Ethernet", 566 }, 567 { PCI_VENDOR_BROADCOM, 568 PCI_PRODUCT_BROADCOM_BCM57791, 569 "Broadcom BCM57791 Fast Ethernet", 570 }, 571 { PCI_VENDOR_BROADCOM, 572 PCI_PRODUCT_BROADCOM_BCM57795, 573 "Broadcom BCM57795 Fast Ethernet", 574 }, 575 { PCI_VENDOR_SCHNEIDERKOCH, 576 PCI_PRODUCT_SCHNEIDERKOCH_SK_9DX1, 577 "SysKonnect SK-9Dx1 Gigabit Ethernet", 578 }, 579 { PCI_VENDOR_3COM, 580 PCI_PRODUCT_3COM_3C996, 581 "3Com 3c996 Gigabit Ethernet", 582 }, 583 { 0, 584 0, 585 NULL }, 586 }; 587 588 /* 589 * XXX: how to handle variants based on 5750 and derivatives: 590 * 5750 5751, 5721, possibly 5714, 5752, and 5708?, which 591 * in general behave like a 5705, except with additional quirks. 592 * This driver's current handling of the 5721 is wrong; 593 * how we map ASIC revision to "quirks" needs more thought. 594 * (defined here until the thought is done). 595 */ 596 #define BGE_IS_5700_FAMILY(sc) ((sc)->bge_flags & BGE_5700_FAMILY) 597 #define BGE_IS_5714_FAMILY(sc) ((sc)->bge_flags & BGE_5714_FAMILY) 598 #define BGE_IS_5705_PLUS(sc) ((sc)->bge_flags & BGE_5705_PLUS) 599 #define BGE_IS_5750_OR_BEYOND(sc) ((sc)->bge_flags & BGE_5750_PLUS) 600 #define BGE_IS_5755_PLUS(sc) ((sc)->bge_flags & BGE_5755_PLUS) 601 #define BGE_IS_JUMBO_CAPABLE(sc) ((sc)->bge_flags & BGE_JUMBO_CAPABLE) 602 603 static const struct bge_revision { 604 uint32_t br_chipid; 605 const char *br_name; 606 } bge_revisions[] = { 607 { BGE_CHIPID_BCM5700_A0, "BCM5700 A0" }, 608 { BGE_CHIPID_BCM5700_A1, "BCM5700 A1" }, 609 { BGE_CHIPID_BCM5700_B0, "BCM5700 B0" }, 610 { BGE_CHIPID_BCM5700_B1, "BCM5700 B1" }, 611 { BGE_CHIPID_BCM5700_B2, "BCM5700 B2" }, 612 { BGE_CHIPID_BCM5700_B3, "BCM5700 B3" }, 613 /* This is treated like a BCM5700 Bx */ 614 { BGE_CHIPID_BCM5700_ALTIMA, "BCM5700 Altima" }, 615 { BGE_CHIPID_BCM5700_C0, "BCM5700 C0" }, 616 { BGE_CHIPID_BCM5701_A0, "BCM5701 A0" }, 617 { BGE_CHIPID_BCM5701_B0, "BCM5701 B0" }, 618 { BGE_CHIPID_BCM5701_B2, "BCM5701 B2" }, 619 { BGE_CHIPID_BCM5701_B5, "BCM5701 B5" }, 620 { BGE_CHIPID_BCM5703_A0, "BCM5702/5703 A0" }, 621 { BGE_CHIPID_BCM5703_A1, "BCM5702/5703 A1" }, 622 { BGE_CHIPID_BCM5703_A2, "BCM5702/5703 A2" }, 623 { BGE_CHIPID_BCM5703_A3, "BCM5702/5703 A3" }, 624 { BGE_CHIPID_BCM5703_B0, "BCM5702/5703 B0" }, 625 { BGE_CHIPID_BCM5704_A0, "BCM5704 A0" }, 626 { BGE_CHIPID_BCM5704_A1, "BCM5704 A1" }, 627 { BGE_CHIPID_BCM5704_A2, "BCM5704 A2" }, 628 { BGE_CHIPID_BCM5704_A3, "BCM5704 A3" }, 629 { BGE_CHIPID_BCM5704_B0, "BCM5704 B0" }, 630 { BGE_CHIPID_BCM5705_A0, "BCM5705 A0" }, 631 { BGE_CHIPID_BCM5705_A1, "BCM5705 A1" }, 632 { BGE_CHIPID_BCM5705_A2, "BCM5705 A2" }, 633 { BGE_CHIPID_BCM5705_A3, "BCM5705 A3" }, 634 { BGE_CHIPID_BCM5750_A0, "BCM5750 A0" }, 635 { BGE_CHIPID_BCM5750_A1, "BCM5750 A1" }, 636 { BGE_CHIPID_BCM5750_A3, "BCM5750 A3" }, 637 { BGE_CHIPID_BCM5750_B0, "BCM5750 B0" }, 638 { BGE_CHIPID_BCM5750_B1, "BCM5750 B1" }, 639 { BGE_CHIPID_BCM5750_C0, "BCM5750 C0" }, 640 { BGE_CHIPID_BCM5750_C1, "BCM5750 C1" }, 641 { BGE_CHIPID_BCM5750_C2, "BCM5750 C2" }, 642 { BGE_CHIPID_BCM5752_A0, "BCM5752 A0" }, 643 { BGE_CHIPID_BCM5752_A1, "BCM5752 A1" }, 644 { BGE_CHIPID_BCM5752_A2, "BCM5752 A2" }, 645 { BGE_CHIPID_BCM5714_A0, "BCM5714 A0" }, 646 { BGE_CHIPID_BCM5714_B0, "BCM5714 B0" }, 647 { BGE_CHIPID_BCM5714_B3, "BCM5714 B3" }, 648 { BGE_CHIPID_BCM5715_A0, "BCM5715 A0" }, 649 { BGE_CHIPID_BCM5715_A1, "BCM5715 A1" }, 650 { BGE_CHIPID_BCM5715_A3, "BCM5715 A3" }, 651 { BGE_CHIPID_BCM5755_A0, "BCM5755 A0" }, 652 { BGE_CHIPID_BCM5755_A1, "BCM5755 A1" }, 653 { BGE_CHIPID_BCM5755_A2, "BCM5755 A2" }, 654 { BGE_CHIPID_BCM5755_C0, "BCM5755 C0" }, 655 { BGE_CHIPID_BCM5761_A0, "BCM5761 A0" }, 656 { BGE_CHIPID_BCM5761_A1, "BCM5761 A1" }, 657 { BGE_CHIPID_BCM5784_A0, "BCM5784 A0" }, 658 { BGE_CHIPID_BCM5784_A1, "BCM5784 A1" }, 659 /* 5754 and 5787 share the same ASIC ID */ 660 { BGE_CHIPID_BCM5787_A0, "BCM5754/5787 A0" }, 661 { BGE_CHIPID_BCM5787_A1, "BCM5754/5787 A1" }, 662 { BGE_CHIPID_BCM5787_A2, "BCM5754/5787 A2" }, 663 { BGE_CHIPID_BCM5906_A1, "BCM5906 A1" }, 664 { BGE_CHIPID_BCM5906_A2, "BCM5906 A2" }, 665 { BGE_CHIPID_BCM57780_A0, "BCM57780 A0" }, 666 { BGE_CHIPID_BCM57780_A1, "BCM57780 A1" }, 667 668 { 0, NULL } 669 }; 670 671 /* 672 * Some defaults for major revisions, so that newer steppings 673 * that we don't know about have a shot at working. 674 */ 675 static const struct bge_revision bge_majorrevs[] = { 676 { BGE_ASICREV_BCM5700, "unknown BCM5700" }, 677 { BGE_ASICREV_BCM5701, "unknown BCM5701" }, 678 { BGE_ASICREV_BCM5703, "unknown BCM5703" }, 679 { BGE_ASICREV_BCM5704, "unknown BCM5704" }, 680 { BGE_ASICREV_BCM5705, "unknown BCM5705" }, 681 { BGE_ASICREV_BCM5750, "unknown BCM5750" }, 682 { BGE_ASICREV_BCM5714_A0, "unknown BCM5714" }, 683 { BGE_ASICREV_BCM5752, "unknown BCM5752" }, 684 { BGE_ASICREV_BCM5780, "unknown BCM5780" }, 685 { BGE_ASICREV_BCM5714, "unknown BCM5714" }, 686 { BGE_ASICREV_BCM5755, "unknown BCM5755" }, 687 { BGE_ASICREV_BCM5761, "unknown BCM5761" }, 688 { BGE_ASICREV_BCM5784, "unknown BCM5784" }, 689 { BGE_ASICREV_BCM5785, "unknown BCM5785" }, 690 /* 5754 and 5787 share the same ASIC ID */ 691 { BGE_ASICREV_BCM5787, "unknown BCM5754/5787" }, 692 { BGE_ASICREV_BCM5906, "unknown BCM5906" }, 693 { BGE_ASICREV_BCM57780, "unknown BCM57780" }, 694 { BGE_ASICREV_BCM5717, "unknown BCM5717" }, 695 { BGE_ASICREV_BCM57765, "unknown BCM57765" }, 696 697 { 0, NULL } 698 }; 699 700 CFATTACH_DECL_NEW(bge, sizeof(struct bge_softc), 701 bge_probe, bge_attach, NULL, NULL); 702 703 static uint32_t 704 bge_readmem_ind(struct bge_softc *sc, int off) 705 { 706 pcireg_t val; 707 708 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_BASEADDR, off); 709 val = pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_DATA); 710 return val; 711 } 712 713 static void 714 bge_writemem_ind(struct bge_softc *sc, int off, int val) 715 { 716 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_BASEADDR, off); 717 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_DATA, val); 718 } 719 720 #ifdef notdef 721 static uint32_t 722 bge_readreg_ind(struct bge_softc *sc, int off) 723 { 724 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_REG_BASEADDR, off); 725 return (pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_REG_DATA)); 726 } 727 #endif 728 729 static void 730 bge_writereg_ind(struct bge_softc *sc, int off, int val) 731 { 732 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_REG_BASEADDR, off); 733 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_REG_DATA, val); 734 } 735 736 static void 737 bge_writemem_direct(struct bge_softc *sc, int off, int val) 738 { 739 CSR_WRITE_4(sc, off, val); 740 } 741 742 static void 743 bge_writembx(struct bge_softc *sc, int off, int val) 744 { 745 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 746 off += BGE_LPMBX_IRQ0_HI - BGE_MBX_IRQ0_HI; 747 748 CSR_WRITE_4(sc, off, val); 749 } 750 751 static uint8_t 752 bge_nvram_getbyte(struct bge_softc *sc, int addr, uint8_t *dest) 753 { 754 uint32_t access, byte = 0; 755 int i; 756 757 /* Lock. */ 758 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_SET1); 759 for (i = 0; i < 8000; i++) { 760 if (CSR_READ_4(sc, BGE_NVRAM_SWARB) & BGE_NVRAMSWARB_GNT1) 761 break; 762 DELAY(20); 763 } 764 if (i == 8000) 765 return 1; 766 767 /* Enable access. */ 768 access = CSR_READ_4(sc, BGE_NVRAM_ACCESS); 769 CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access | BGE_NVRAMACC_ENABLE); 770 771 CSR_WRITE_4(sc, BGE_NVRAM_ADDR, addr & 0xfffffffc); 772 CSR_WRITE_4(sc, BGE_NVRAM_CMD, BGE_NVRAM_READCMD); 773 for (i = 0; i < BGE_TIMEOUT * 10; i++) { 774 DELAY(10); 775 if (CSR_READ_4(sc, BGE_NVRAM_CMD) & BGE_NVRAMCMD_DONE) { 776 DELAY(10); 777 break; 778 } 779 } 780 781 if (i == BGE_TIMEOUT * 10) { 782 aprint_error_dev(sc->bge_dev, "nvram read timed out\n"); 783 return 1; 784 } 785 786 /* Get result. */ 787 byte = CSR_READ_4(sc, BGE_NVRAM_RDDATA); 788 789 *dest = (bswap32(byte) >> ((addr % 4) * 8)) & 0xFF; 790 791 /* Disable access. */ 792 CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access); 793 794 /* Unlock. */ 795 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_CLR1); 796 CSR_READ_4(sc, BGE_NVRAM_SWARB); 797 798 return 0; 799 } 800 801 /* 802 * Read a sequence of bytes from NVRAM. 803 */ 804 static int 805 bge_read_nvram(struct bge_softc *sc, uint8_t *dest, int off, int cnt) 806 { 807 int err = 0, i; 808 uint8_t byte = 0; 809 810 if (BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5906) 811 return 1; 812 813 for (i = 0; i < cnt; i++) { 814 err = bge_nvram_getbyte(sc, off + i, &byte); 815 if (err) 816 break; 817 *(dest + i) = byte; 818 } 819 820 return (err ? 1 : 0); 821 } 822 823 /* 824 * Read a byte of data stored in the EEPROM at address 'addr.' The 825 * BCM570x supports both the traditional bitbang interface and an 826 * auto access interface for reading the EEPROM. We use the auto 827 * access method. 828 */ 829 static uint8_t 830 bge_eeprom_getbyte(struct bge_softc *sc, int addr, uint8_t *dest) 831 { 832 int i; 833 uint32_t byte = 0; 834 835 /* 836 * Enable use of auto EEPROM access so we can avoid 837 * having to use the bitbang method. 838 */ 839 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM); 840 841 /* Reset the EEPROM, load the clock period. */ 842 CSR_WRITE_4(sc, BGE_EE_ADDR, 843 BGE_EEADDR_RESET | BGE_EEHALFCLK(BGE_HALFCLK_384SCL)); 844 DELAY(20); 845 846 /* Issue the read EEPROM command. */ 847 CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr); 848 849 /* Wait for completion */ 850 for (i = 0; i < BGE_TIMEOUT * 10; i++) { 851 DELAY(10); 852 if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE) 853 break; 854 } 855 856 if (i == BGE_TIMEOUT * 10) { 857 aprint_error_dev(sc->bge_dev, "eeprom read timed out\n"); 858 return 0; 859 } 860 861 /* Get result. */ 862 byte = CSR_READ_4(sc, BGE_EE_DATA); 863 864 *dest = (byte >> ((addr % 4) * 8)) & 0xFF; 865 866 return 0; 867 } 868 869 /* 870 * Read a sequence of bytes from the EEPROM. 871 */ 872 static int 873 bge_read_eeprom(struct bge_softc *sc, void *destv, int off, int cnt) 874 { 875 int err = 0, i; 876 uint8_t byte = 0; 877 char *dest = destv; 878 879 for (i = 0; i < cnt; i++) { 880 err = bge_eeprom_getbyte(sc, off + i, &byte); 881 if (err) 882 break; 883 *(dest + i) = byte; 884 } 885 886 return (err ? 1 : 0); 887 } 888 889 static int 890 bge_miibus_readreg(device_t dev, int phy, int reg) 891 { 892 struct bge_softc *sc = device_private(dev); 893 uint32_t val; 894 uint32_t autopoll; 895 int i; 896 897 /* 898 * Broadcom's own driver always assumes the internal 899 * PHY is at GMII address 1. On some chips, the PHY responds 900 * to accesses at all addresses, which could cause us to 901 * bogusly attach the PHY 32 times at probe type. Always 902 * restricting the lookup to address 1 is simpler than 903 * trying to figure out which chips revisions should be 904 * special-cased. 905 */ 906 if (phy != 1) 907 return 0; 908 909 /* Reading with autopolling on may trigger PCI errors */ 910 autopoll = CSR_READ_4(sc, BGE_MI_MODE); 911 if (autopoll & BGE_MIMODE_AUTOPOLL) { 912 BGE_STS_CLRBIT(sc, BGE_STS_AUTOPOLL); 913 BGE_CLRBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 914 DELAY(40); 915 } 916 917 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_READ | BGE_MICOMM_BUSY | 918 BGE_MIPHY(phy) | BGE_MIREG(reg)); 919 920 for (i = 0; i < BGE_TIMEOUT; i++) { 921 val = CSR_READ_4(sc, BGE_MI_COMM); 922 if (!(val & BGE_MICOMM_BUSY)) 923 break; 924 delay(10); 925 } 926 927 if (i == BGE_TIMEOUT) { 928 aprint_error_dev(sc->bge_dev, "PHY read timed out\n"); 929 val = 0; 930 goto done; 931 } 932 933 val = CSR_READ_4(sc, BGE_MI_COMM); 934 935 done: 936 if (autopoll & BGE_MIMODE_AUTOPOLL) { 937 BGE_STS_SETBIT(sc, BGE_STS_AUTOPOLL); 938 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 939 DELAY(40); 940 } 941 942 if (val & BGE_MICOMM_READFAIL) 943 return 0; 944 945 return (val & 0xFFFF); 946 } 947 948 static void 949 bge_miibus_writereg(device_t dev, int phy, int reg, int val) 950 { 951 struct bge_softc *sc = device_private(dev); 952 uint32_t autopoll; 953 int i; 954 955 if (phy!=1) { 956 return; 957 } 958 959 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906 && 960 (reg == BRGPHY_MII_1000CTL || reg == BRGPHY_MII_AUXCTL)) { 961 return; 962 } 963 964 /* Reading with autopolling on may trigger PCI errors */ 965 autopoll = CSR_READ_4(sc, BGE_MI_MODE); 966 if (autopoll & BGE_MIMODE_AUTOPOLL) { 967 delay(40); 968 BGE_STS_CLRBIT(sc, BGE_STS_AUTOPOLL); 969 BGE_CLRBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 970 delay(10); /* 40 usec is supposed to be adequate */ 971 } 972 973 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_WRITE | BGE_MICOMM_BUSY | 974 BGE_MIPHY(phy) | BGE_MIREG(reg)|val); 975 976 for (i = 0; i < BGE_TIMEOUT; i++) { 977 delay(10); 978 if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY)) { 979 delay(5); 980 CSR_READ_4(sc, BGE_MI_COMM); 981 break; 982 } 983 } 984 985 if (autopoll & BGE_MIMODE_AUTOPOLL) { 986 BGE_STS_SETBIT(sc, BGE_STS_AUTOPOLL); 987 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 988 delay(40); 989 } 990 991 if (i == BGE_TIMEOUT) 992 aprint_error_dev(sc->bge_dev, "PHY read timed out\n"); 993 } 994 995 static void 996 bge_miibus_statchg(device_t dev) 997 { 998 struct bge_softc *sc = device_private(dev); 999 struct mii_data *mii = &sc->bge_mii; 1000 1001 /* 1002 * Get flow control negotiation result. 1003 */ 1004 if (IFM_SUBTYPE(mii->mii_media.ifm_cur->ifm_media) == IFM_AUTO && 1005 (mii->mii_media_active & IFM_ETH_FMASK) != sc->bge_flowflags) { 1006 sc->bge_flowflags = mii->mii_media_active & IFM_ETH_FMASK; 1007 mii->mii_media_active &= ~IFM_ETH_FMASK; 1008 } 1009 1010 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_PORTMODE); 1011 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T || 1012 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX) 1013 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_GMII); 1014 else 1015 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_MII); 1016 1017 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) 1018 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX); 1019 else 1020 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX); 1021 1022 /* 1023 * 802.3x flow control 1024 */ 1025 if (sc->bge_flowflags & IFM_ETH_RXPAUSE) 1026 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_FLOWCTL_ENABLE); 1027 else 1028 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_FLOWCTL_ENABLE); 1029 1030 if (sc->bge_flowflags & IFM_ETH_TXPAUSE) 1031 BGE_SETBIT(sc, BGE_TX_MODE, BGE_TXMODE_FLOWCTL_ENABLE); 1032 else 1033 BGE_CLRBIT(sc, BGE_TX_MODE, BGE_TXMODE_FLOWCTL_ENABLE); 1034 } 1035 1036 /* 1037 * Update rx threshold levels to values in a particular slot 1038 * of the interrupt-mitigation table bge_rx_threshes. 1039 */ 1040 static void 1041 bge_set_thresh(struct ifnet *ifp, int lvl) 1042 { 1043 struct bge_softc *sc = ifp->if_softc; 1044 int s; 1045 1046 /* For now, just save the new Rx-intr thresholds and record 1047 * that a threshold update is pending. Updating the hardware 1048 * registers here (even at splhigh()) is observed to 1049 * occasionaly cause glitches where Rx-interrupts are not 1050 * honoured for up to 10 seconds. jonathan (at) NetBSD.org, 2003-04-05 1051 */ 1052 s = splnet(); 1053 sc->bge_rx_coal_ticks = bge_rx_threshes[lvl].rx_ticks; 1054 sc->bge_rx_max_coal_bds = bge_rx_threshes[lvl].rx_max_bds; 1055 sc->bge_pending_rxintr_change = 1; 1056 splx(s); 1057 1058 return; 1059 } 1060 1061 1062 /* 1063 * Update Rx thresholds of all bge devices 1064 */ 1065 static void 1066 bge_update_all_threshes(int lvl) 1067 { 1068 struct ifnet *ifp; 1069 const char * const namebuf = "bge"; 1070 int namelen; 1071 1072 if (lvl < 0) 1073 lvl = 0; 1074 else if (lvl >= NBGE_RX_THRESH) 1075 lvl = NBGE_RX_THRESH - 1; 1076 1077 namelen = strlen(namebuf); 1078 /* 1079 * Now search all the interfaces for this name/number 1080 */ 1081 IFNET_FOREACH(ifp) { 1082 if (strncmp(ifp->if_xname, namebuf, namelen) != 0) 1083 continue; 1084 /* We got a match: update if doing auto-threshold-tuning */ 1085 if (bge_auto_thresh) 1086 bge_set_thresh(ifp, lvl); 1087 } 1088 } 1089 1090 /* 1091 * Handle events that have triggered interrupts. 1092 */ 1093 static void 1094 bge_handle_events(struct bge_softc *sc) 1095 { 1096 1097 return; 1098 } 1099 1100 /* 1101 * Memory management for jumbo frames. 1102 */ 1103 1104 static int 1105 bge_alloc_jumbo_mem(struct bge_softc *sc) 1106 { 1107 char *ptr, *kva; 1108 bus_dma_segment_t seg; 1109 int i, rseg, state, error; 1110 struct bge_jpool_entry *entry; 1111 1112 state = error = 0; 1113 1114 /* Grab a big chunk o' storage. */ 1115 if (bus_dmamem_alloc(sc->bge_dmatag, BGE_JMEM, PAGE_SIZE, 0, 1116 &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 1117 aprint_error_dev(sc->bge_dev, "can't alloc rx buffers\n"); 1118 return ENOBUFS; 1119 } 1120 1121 state = 1; 1122 if (bus_dmamem_map(sc->bge_dmatag, &seg, rseg, BGE_JMEM, (void **)&kva, 1123 BUS_DMA_NOWAIT)) { 1124 aprint_error_dev(sc->bge_dev, 1125 "can't map DMA buffers (%d bytes)\n", (int)BGE_JMEM); 1126 error = ENOBUFS; 1127 goto out; 1128 } 1129 1130 state = 2; 1131 if (bus_dmamap_create(sc->bge_dmatag, BGE_JMEM, 1, BGE_JMEM, 0, 1132 BUS_DMA_NOWAIT, &sc->bge_cdata.bge_rx_jumbo_map)) { 1133 aprint_error_dev(sc->bge_dev, "can't create DMA map\n"); 1134 error = ENOBUFS; 1135 goto out; 1136 } 1137 1138 state = 3; 1139 if (bus_dmamap_load(sc->bge_dmatag, sc->bge_cdata.bge_rx_jumbo_map, 1140 kva, BGE_JMEM, NULL, BUS_DMA_NOWAIT)) { 1141 aprint_error_dev(sc->bge_dev, "can't load DMA map\n"); 1142 error = ENOBUFS; 1143 goto out; 1144 } 1145 1146 state = 4; 1147 sc->bge_cdata.bge_jumbo_buf = (void *)kva; 1148 DPRINTFN(1,("bge_jumbo_buf = %p\n", sc->bge_cdata.bge_jumbo_buf)); 1149 1150 SLIST_INIT(&sc->bge_jfree_listhead); 1151 SLIST_INIT(&sc->bge_jinuse_listhead); 1152 1153 /* 1154 * Now divide it up into 9K pieces and save the addresses 1155 * in an array. 1156 */ 1157 ptr = sc->bge_cdata.bge_jumbo_buf; 1158 for (i = 0; i < BGE_JSLOTS; i++) { 1159 sc->bge_cdata.bge_jslots[i] = ptr; 1160 ptr += BGE_JLEN; 1161 entry = malloc(sizeof(struct bge_jpool_entry), 1162 M_DEVBUF, M_NOWAIT); 1163 if (entry == NULL) { 1164 aprint_error_dev(sc->bge_dev, 1165 "no memory for jumbo buffer queue!\n"); 1166 error = ENOBUFS; 1167 goto out; 1168 } 1169 entry->slot = i; 1170 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, 1171 entry, jpool_entries); 1172 } 1173 out: 1174 if (error != 0) { 1175 switch (state) { 1176 case 4: 1177 bus_dmamap_unload(sc->bge_dmatag, 1178 sc->bge_cdata.bge_rx_jumbo_map); 1179 case 3: 1180 bus_dmamap_destroy(sc->bge_dmatag, 1181 sc->bge_cdata.bge_rx_jumbo_map); 1182 case 2: 1183 bus_dmamem_unmap(sc->bge_dmatag, kva, BGE_JMEM); 1184 case 1: 1185 bus_dmamem_free(sc->bge_dmatag, &seg, rseg); 1186 break; 1187 default: 1188 break; 1189 } 1190 } 1191 1192 return error; 1193 } 1194 1195 /* 1196 * Allocate a jumbo buffer. 1197 */ 1198 static void * 1199 bge_jalloc(struct bge_softc *sc) 1200 { 1201 struct bge_jpool_entry *entry; 1202 1203 entry = SLIST_FIRST(&sc->bge_jfree_listhead); 1204 1205 if (entry == NULL) { 1206 aprint_error_dev(sc->bge_dev, "no free jumbo buffers\n"); 1207 return NULL; 1208 } 1209 1210 SLIST_REMOVE_HEAD(&sc->bge_jfree_listhead, jpool_entries); 1211 SLIST_INSERT_HEAD(&sc->bge_jinuse_listhead, entry, jpool_entries); 1212 return (sc->bge_cdata.bge_jslots[entry->slot]); 1213 } 1214 1215 /* 1216 * Release a jumbo buffer. 1217 */ 1218 static void 1219 bge_jfree(struct mbuf *m, void *buf, size_t size, void *arg) 1220 { 1221 struct bge_jpool_entry *entry; 1222 struct bge_softc *sc; 1223 int i, s; 1224 1225 /* Extract the softc struct pointer. */ 1226 sc = (struct bge_softc *)arg; 1227 1228 if (sc == NULL) 1229 panic("bge_jfree: can't find softc pointer!"); 1230 1231 /* calculate the slot this buffer belongs to */ 1232 1233 i = ((char *)buf 1234 - (char *)sc->bge_cdata.bge_jumbo_buf) / BGE_JLEN; 1235 1236 if ((i < 0) || (i >= BGE_JSLOTS)) 1237 panic("bge_jfree: asked to free buffer that we don't manage!"); 1238 1239 s = splvm(); 1240 entry = SLIST_FIRST(&sc->bge_jinuse_listhead); 1241 if (entry == NULL) 1242 panic("bge_jfree: buffer not in use!"); 1243 entry->slot = i; 1244 SLIST_REMOVE_HEAD(&sc->bge_jinuse_listhead, jpool_entries); 1245 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, entry, jpool_entries); 1246 1247 if (__predict_true(m != NULL)) 1248 pool_cache_put(mb_cache, m); 1249 splx(s); 1250 } 1251 1252 1253 /* 1254 * Intialize a standard receive ring descriptor. 1255 */ 1256 static int 1257 bge_newbuf_std(struct bge_softc *sc, int i, struct mbuf *m, bus_dmamap_t dmamap) 1258 { 1259 struct mbuf *m_new = NULL; 1260 struct bge_rx_bd *r; 1261 int error; 1262 1263 if (dmamap == NULL) { 1264 error = bus_dmamap_create(sc->bge_dmatag, MCLBYTES, 1, 1265 MCLBYTES, 0, BUS_DMA_NOWAIT, &dmamap); 1266 if (error != 0) 1267 return error; 1268 } 1269 1270 sc->bge_cdata.bge_rx_std_map[i] = dmamap; 1271 1272 if (m == NULL) { 1273 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1274 if (m_new == NULL) 1275 return ENOBUFS; 1276 1277 MCLGET(m_new, M_DONTWAIT); 1278 if (!(m_new->m_flags & M_EXT)) { 1279 m_freem(m_new); 1280 return ENOBUFS; 1281 } 1282 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1283 1284 } else { 1285 m_new = m; 1286 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1287 m_new->m_data = m_new->m_ext.ext_buf; 1288 } 1289 if (!(sc->bge_flags & BGE_RX_ALIGNBUG)) 1290 m_adj(m_new, ETHER_ALIGN); 1291 if (bus_dmamap_load_mbuf(sc->bge_dmatag, dmamap, m_new, 1292 BUS_DMA_READ|BUS_DMA_NOWAIT)) 1293 return ENOBUFS; 1294 bus_dmamap_sync(sc->bge_dmatag, dmamap, 0, dmamap->dm_mapsize, 1295 BUS_DMASYNC_PREREAD); 1296 1297 sc->bge_cdata.bge_rx_std_chain[i] = m_new; 1298 r = &sc->bge_rdata->bge_rx_std_ring[i]; 1299 BGE_HOSTADDR(r->bge_addr, dmamap->dm_segs[0].ds_addr); 1300 r->bge_flags = BGE_RXBDFLAG_END; 1301 r->bge_len = m_new->m_len; 1302 r->bge_idx = i; 1303 1304 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 1305 offsetof(struct bge_ring_data, bge_rx_std_ring) + 1306 i * sizeof (struct bge_rx_bd), 1307 sizeof (struct bge_rx_bd), 1308 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1309 1310 return 0; 1311 } 1312 1313 /* 1314 * Initialize a jumbo receive ring descriptor. This allocates 1315 * a jumbo buffer from the pool managed internally by the driver. 1316 */ 1317 static int 1318 bge_newbuf_jumbo(struct bge_softc *sc, int i, struct mbuf *m) 1319 { 1320 struct mbuf *m_new = NULL; 1321 struct bge_rx_bd *r; 1322 void *buf = NULL; 1323 1324 if (m == NULL) { 1325 1326 /* Allocate the mbuf. */ 1327 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1328 if (m_new == NULL) 1329 return ENOBUFS; 1330 1331 /* Allocate the jumbo buffer */ 1332 buf = bge_jalloc(sc); 1333 if (buf == NULL) { 1334 m_freem(m_new); 1335 aprint_error_dev(sc->bge_dev, 1336 "jumbo allocation failed -- packet dropped!\n"); 1337 return ENOBUFS; 1338 } 1339 1340 /* Attach the buffer to the mbuf. */ 1341 m_new->m_len = m_new->m_pkthdr.len = BGE_JUMBO_FRAMELEN; 1342 MEXTADD(m_new, buf, BGE_JUMBO_FRAMELEN, M_DEVBUF, 1343 bge_jfree, sc); 1344 m_new->m_flags |= M_EXT_RW; 1345 } else { 1346 m_new = m; 1347 buf = m_new->m_data = m_new->m_ext.ext_buf; 1348 m_new->m_ext.ext_size = BGE_JUMBO_FRAMELEN; 1349 } 1350 if (!(sc->bge_flags & BGE_RX_ALIGNBUG)) 1351 m_adj(m_new, ETHER_ALIGN); 1352 bus_dmamap_sync(sc->bge_dmatag, sc->bge_cdata.bge_rx_jumbo_map, 1353 mtod(m_new, char *) - (char *)sc->bge_cdata.bge_jumbo_buf, BGE_JLEN, 1354 BUS_DMASYNC_PREREAD); 1355 /* Set up the descriptor. */ 1356 r = &sc->bge_rdata->bge_rx_jumbo_ring[i]; 1357 sc->bge_cdata.bge_rx_jumbo_chain[i] = m_new; 1358 BGE_HOSTADDR(r->bge_addr, BGE_JUMBO_DMA_ADDR(sc, m_new)); 1359 r->bge_flags = BGE_RXBDFLAG_END|BGE_RXBDFLAG_JUMBO_RING; 1360 r->bge_len = m_new->m_len; 1361 r->bge_idx = i; 1362 1363 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 1364 offsetof(struct bge_ring_data, bge_rx_jumbo_ring) + 1365 i * sizeof (struct bge_rx_bd), 1366 sizeof (struct bge_rx_bd), 1367 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1368 1369 return 0; 1370 } 1371 1372 /* 1373 * The standard receive ring has 512 entries in it. At 2K per mbuf cluster, 1374 * that's 1MB or memory, which is a lot. For now, we fill only the first 1375 * 256 ring entries and hope that our CPU is fast enough to keep up with 1376 * the NIC. 1377 */ 1378 static int 1379 bge_init_rx_ring_std(struct bge_softc *sc) 1380 { 1381 int i; 1382 1383 if (sc->bge_flags & BGE_RXRING_VALID) 1384 return 0; 1385 1386 for (i = 0; i < BGE_SSLOTS; i++) { 1387 if (bge_newbuf_std(sc, i, NULL, 0) == ENOBUFS) 1388 return ENOBUFS; 1389 } 1390 1391 sc->bge_std = i - 1; 1392 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std); 1393 1394 sc->bge_flags |= BGE_RXRING_VALID; 1395 1396 return 0; 1397 } 1398 1399 static void 1400 bge_free_rx_ring_std(struct bge_softc *sc) 1401 { 1402 int i; 1403 1404 if (!(sc->bge_flags & BGE_RXRING_VALID)) 1405 return; 1406 1407 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { 1408 if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) { 1409 m_freem(sc->bge_cdata.bge_rx_std_chain[i]); 1410 sc->bge_cdata.bge_rx_std_chain[i] = NULL; 1411 bus_dmamap_destroy(sc->bge_dmatag, 1412 sc->bge_cdata.bge_rx_std_map[i]); 1413 } 1414 memset((char *)&sc->bge_rdata->bge_rx_std_ring[i], 0, 1415 sizeof(struct bge_rx_bd)); 1416 } 1417 1418 sc->bge_flags &= ~BGE_RXRING_VALID; 1419 } 1420 1421 static int 1422 bge_init_rx_ring_jumbo(struct bge_softc *sc) 1423 { 1424 int i; 1425 volatile struct bge_rcb *rcb; 1426 1427 if (sc->bge_flags & BGE_JUMBO_RXRING_VALID) 1428 return 0; 1429 1430 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 1431 if (bge_newbuf_jumbo(sc, i, NULL) == ENOBUFS) 1432 return ENOBUFS; 1433 }; 1434 1435 sc->bge_jumbo = i - 1; 1436 sc->bge_flags |= BGE_JUMBO_RXRING_VALID; 1437 1438 rcb = &sc->bge_rdata->bge_info.bge_jumbo_rx_rcb; 1439 rcb->bge_maxlen_flags = 0; 1440 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 1441 1442 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo); 1443 1444 return 0; 1445 } 1446 1447 static void 1448 bge_free_rx_ring_jumbo(struct bge_softc *sc) 1449 { 1450 int i; 1451 1452 if (!(sc->bge_flags & BGE_JUMBO_RXRING_VALID)) 1453 return; 1454 1455 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 1456 if (sc->bge_cdata.bge_rx_jumbo_chain[i] != NULL) { 1457 m_freem(sc->bge_cdata.bge_rx_jumbo_chain[i]); 1458 sc->bge_cdata.bge_rx_jumbo_chain[i] = NULL; 1459 } 1460 memset((char *)&sc->bge_rdata->bge_rx_jumbo_ring[i], 0, 1461 sizeof(struct bge_rx_bd)); 1462 } 1463 1464 sc->bge_flags &= ~BGE_JUMBO_RXRING_VALID; 1465 } 1466 1467 static void 1468 bge_free_tx_ring(struct bge_softc *sc) 1469 { 1470 int i, freed; 1471 struct txdmamap_pool_entry *dma; 1472 1473 if (!(sc->bge_flags & BGE_TXRING_VALID)) 1474 return; 1475 1476 freed = 0; 1477 1478 for (i = 0; i < BGE_TX_RING_CNT; i++) { 1479 if (sc->bge_cdata.bge_tx_chain[i] != NULL) { 1480 freed++; 1481 m_freem(sc->bge_cdata.bge_tx_chain[i]); 1482 sc->bge_cdata.bge_tx_chain[i] = NULL; 1483 SLIST_INSERT_HEAD(&sc->txdma_list, sc->txdma[i], 1484 link); 1485 sc->txdma[i] = 0; 1486 } 1487 memset((char *)&sc->bge_rdata->bge_tx_ring[i], 0, 1488 sizeof(struct bge_tx_bd)); 1489 } 1490 1491 while ((dma = SLIST_FIRST(&sc->txdma_list))) { 1492 SLIST_REMOVE_HEAD(&sc->txdma_list, link); 1493 bus_dmamap_destroy(sc->bge_dmatag, dma->dmamap); 1494 free(dma, M_DEVBUF); 1495 } 1496 1497 sc->bge_flags &= ~BGE_TXRING_VALID; 1498 } 1499 1500 static int 1501 bge_init_tx_ring(struct bge_softc *sc) 1502 { 1503 int i; 1504 bus_dmamap_t dmamap; 1505 struct txdmamap_pool_entry *dma; 1506 1507 if (sc->bge_flags & BGE_TXRING_VALID) 1508 return 0; 1509 1510 sc->bge_txcnt = 0; 1511 sc->bge_tx_saved_considx = 0; 1512 1513 /* Initialize transmit producer index for host-memory send ring. */ 1514 sc->bge_tx_prodidx = 0; 1515 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx); 1516 /* 5700 b2 errata */ 1517 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX) 1518 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx); 1519 1520 /* NIC-memory send ring not used; initialize to zero. */ 1521 bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0); 1522 /* 5700 b2 errata */ 1523 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX) 1524 bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0); 1525 1526 SLIST_INIT(&sc->txdma_list); 1527 for (i = 0; i < BGE_RSLOTS; i++) { 1528 if (bus_dmamap_create(sc->bge_dmatag, BGE_TXDMA_MAX, 1529 BGE_NTXSEG, ETHER_MAX_LEN_JUMBO, 0, BUS_DMA_NOWAIT, 1530 &dmamap)) 1531 return ENOBUFS; 1532 if (dmamap == NULL) 1533 panic("dmamap NULL in bge_init_tx_ring"); 1534 dma = malloc(sizeof(*dma), M_DEVBUF, M_NOWAIT); 1535 if (dma == NULL) { 1536 aprint_error_dev(sc->bge_dev, 1537 "can't alloc txdmamap_pool_entry\n"); 1538 bus_dmamap_destroy(sc->bge_dmatag, dmamap); 1539 return ENOMEM; 1540 } 1541 dma->dmamap = dmamap; 1542 SLIST_INSERT_HEAD(&sc->txdma_list, dma, link); 1543 } 1544 1545 sc->bge_flags |= BGE_TXRING_VALID; 1546 1547 return 0; 1548 } 1549 1550 static void 1551 bge_setmulti(struct bge_softc *sc) 1552 { 1553 struct ethercom *ac = &sc->ethercom; 1554 struct ifnet *ifp = &ac->ec_if; 1555 struct ether_multi *enm; 1556 struct ether_multistep step; 1557 uint32_t hashes[4] = { 0, 0, 0, 0 }; 1558 uint32_t h; 1559 int i; 1560 1561 if (ifp->if_flags & IFF_PROMISC) 1562 goto allmulti; 1563 1564 /* Now program new ones. */ 1565 ETHER_FIRST_MULTI(step, ac, enm); 1566 while (enm != NULL) { 1567 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1568 /* 1569 * We must listen to a range of multicast addresses. 1570 * For now, just accept all multicasts, rather than 1571 * trying to set only those filter bits needed to match 1572 * the range. (At this time, the only use of address 1573 * ranges is for IP multicast routing, for which the 1574 * range is big enough to require all bits set.) 1575 */ 1576 goto allmulti; 1577 } 1578 1579 h = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN); 1580 1581 /* Just want the 7 least-significant bits. */ 1582 h &= 0x7f; 1583 1584 hashes[(h & 0x60) >> 5] |= 1 << (h & 0x1F); 1585 ETHER_NEXT_MULTI(step, enm); 1586 } 1587 1588 ifp->if_flags &= ~IFF_ALLMULTI; 1589 goto setit; 1590 1591 allmulti: 1592 ifp->if_flags |= IFF_ALLMULTI; 1593 hashes[0] = hashes[1] = hashes[2] = hashes[3] = 0xffffffff; 1594 1595 setit: 1596 for (i = 0; i < 4; i++) 1597 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]); 1598 } 1599 1600 const int bge_swapbits[] = { 1601 0, 1602 BGE_MODECTL_BYTESWAP_DATA, 1603 BGE_MODECTL_WORDSWAP_DATA, 1604 BGE_MODECTL_BYTESWAP_NONFRAME, 1605 BGE_MODECTL_WORDSWAP_NONFRAME, 1606 1607 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA, 1608 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_BYTESWAP_NONFRAME, 1609 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_NONFRAME, 1610 1611 BGE_MODECTL_WORDSWAP_DATA|BGE_MODECTL_BYTESWAP_NONFRAME, 1612 BGE_MODECTL_WORDSWAP_DATA|BGE_MODECTL_WORDSWAP_NONFRAME, 1613 1614 BGE_MODECTL_BYTESWAP_NONFRAME|BGE_MODECTL_WORDSWAP_NONFRAME, 1615 1616 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA| 1617 BGE_MODECTL_BYTESWAP_NONFRAME, 1618 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA| 1619 BGE_MODECTL_WORDSWAP_NONFRAME, 1620 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_BYTESWAP_NONFRAME| 1621 BGE_MODECTL_WORDSWAP_NONFRAME, 1622 BGE_MODECTL_WORDSWAP_DATA|BGE_MODECTL_BYTESWAP_NONFRAME| 1623 BGE_MODECTL_WORDSWAP_NONFRAME, 1624 1625 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA| 1626 BGE_MODECTL_BYTESWAP_NONFRAME|BGE_MODECTL_WORDSWAP_NONFRAME, 1627 }; 1628 1629 int bge_swapindex = 0; 1630 1631 /* 1632 * Do endian, PCI and DMA initialization. Also check the on-board ROM 1633 * self-test results. 1634 */ 1635 static int 1636 bge_chipinit(struct bge_softc *sc) 1637 { 1638 int i; 1639 uint32_t dma_rw_ctl; 1640 1641 1642 /* Set endianness before we access any non-PCI registers. */ 1643 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MISC_CTL, 1644 BGE_INIT); 1645 1646 /* Set power state to D0. */ 1647 bge_setpowerstate(sc, 0); 1648 1649 /* Clear the MAC control register */ 1650 CSR_WRITE_4(sc, BGE_MAC_MODE, 0); 1651 1652 /* 1653 * Clear the MAC statistics block in the NIC's 1654 * internal memory. 1655 */ 1656 for (i = BGE_STATS_BLOCK; 1657 i < BGE_STATS_BLOCK_END + 1; i += sizeof(uint32_t)) 1658 BGE_MEMWIN_WRITE(sc->sc_pc, sc->sc_pcitag, i, 0); 1659 1660 for (i = BGE_STATUS_BLOCK; 1661 i < BGE_STATUS_BLOCK_END + 1; i += sizeof(uint32_t)) 1662 BGE_MEMWIN_WRITE(sc->sc_pc, sc->sc_pcitag, i, 0); 1663 1664 /* Set up the PCI DMA control register. */ 1665 dma_rw_ctl = BGE_PCI_READ_CMD | BGE_PCI_WRITE_CMD; 1666 if (sc->bge_flags & BGE_PCIE) { 1667 /* Read watermark not used, 128 bytes for write. */ 1668 DPRINTFN(4, ("(%s: PCI-Express DMA setting)\n", 1669 device_xname(sc->bge_dev))); 1670 dma_rw_ctl |= (0x3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT); 1671 } else if (sc->bge_flags & BGE_PCIX) { 1672 DPRINTFN(4, ("(:%s: PCI-X DMA setting)\n", 1673 device_xname(sc->bge_dev))); 1674 /* PCI-X bus */ 1675 if (BGE_IS_5714_FAMILY(sc)) { 1676 /* 256 bytes for read and write. */ 1677 dma_rw_ctl |= (0x02 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) | 1678 (0x02 << BGE_PCIDMARWCTL_WR_WAT_SHIFT); 1679 1680 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5780) 1681 dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL; 1682 else 1683 dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE_LOCAL; 1684 } else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) { 1685 /* 1536 bytes for read, 384 bytes for write. */ 1686 dma_rw_ctl |= 1687 (0x7 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) | 1688 (0x3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT); 1689 } else { 1690 /* 384 bytes for read and write. */ 1691 dma_rw_ctl |= (0x03 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) | 1692 (0x03 << BGE_PCIDMARWCTL_WR_WAT_SHIFT) | 1693 (0x0F); 1694 } 1695 1696 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5703 || 1697 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) { 1698 uint32_t tmp; 1699 1700 /* Set ONEDMA_ATONCE for hardware workaround. */ 1701 tmp = CSR_READ_4(sc, BGE_PCI_CLKCTL) & 0x1f; 1702 if (tmp == 6 || tmp == 7) 1703 dma_rw_ctl |= 1704 BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL; 1705 1706 /* Set PCI-X DMA write workaround. */ 1707 dma_rw_ctl |= BGE_PCIDMARWCTL_ASRT_ALL_BE; 1708 } 1709 } else { 1710 /* Conventional PCI bus: 256 bytes for read and write. */ 1711 DPRINTFN(4, ("(%s: PCI 2.2 DMA setting)\n", 1712 device_xname(sc->bge_dev))); 1713 dma_rw_ctl = (0x7 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) | 1714 (0x7 << BGE_PCIDMARWCTL_WR_WAT_SHIFT); 1715 if (BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5705 && 1716 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5750) 1717 dma_rw_ctl |= 0x0F; 1718 } 1719 1720 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 1721 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5701) 1722 dma_rw_ctl |= BGE_PCIDMARWCTL_USE_MRM | 1723 BGE_PCIDMARWCTL_ASRT_ALL_BE; 1724 1725 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5703 || 1726 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) 1727 dma_rw_ctl &= ~BGE_PCIDMARWCTL_MINDMA; 1728 1729 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_DMA_RW_CTL, dma_rw_ctl); 1730 1731 /* 1732 * Set up general mode register. 1733 */ 1734 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS | 1735 BGE_MODECTL_MAC_ATTN_INTR | BGE_MODECTL_HOST_SEND_BDS | 1736 BGE_MODECTL_TX_NO_PHDR_CSUM | BGE_MODECTL_RX_NO_PHDR_CSUM); 1737 1738 /* 1739 * BCM5701 B5 have a bug causing data corruption when using 1740 * 64-bit DMA reads, which can be terminated early and then 1741 * completed later as 32-bit accesses, in combination with 1742 * certain bridges. 1743 */ 1744 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5701 && 1745 sc->bge_chipid == BGE_CHIPID_BCM5701_B5) 1746 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_FORCE_PCI32); 1747 1748 /* 1749 * Disable memory write invalidate. Apparently it is not supported 1750 * properly by these devices. 1751 */ 1752 PCI_CLRBIT(sc->sc_pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG, 1753 PCI_COMMAND_INVALIDATE_ENABLE); 1754 1755 #ifdef __brokenalpha__ 1756 /* 1757 * Must insure that we do not cross an 8K (bytes) boundary 1758 * for DMA reads. Our highest limit is 1K bytes. This is a 1759 * restriction on some ALPHA platforms with early revision 1760 * 21174 PCI chipsets, such as the AlphaPC 164lx 1761 */ 1762 PCI_SETBIT(sc, BGE_PCI_DMA_RW_CTL, BGE_PCI_READ_BNDRY_1024, 4); 1763 #endif 1764 1765 /* Set the timer prescaler (always 66MHz) */ 1766 CSR_WRITE_4(sc, BGE_MISC_CFG, 65 << 1/*BGE_32BITTIME_66MHZ*/); 1767 1768 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 1769 DELAY(40); /* XXX */ 1770 1771 /* Put PHY into ready state */ 1772 BGE_CLRBIT(sc, BGE_MISC_CFG, BGE_MISCCFG_EPHY_IDDQ); 1773 CSR_READ_4(sc, BGE_MISC_CFG); /* Flush */ 1774 DELAY(40); 1775 } 1776 1777 return 0; 1778 } 1779 1780 static int 1781 bge_blockinit(struct bge_softc *sc) 1782 { 1783 volatile struct bge_rcb *rcb; 1784 bus_size_t rcb_addr; 1785 int i; 1786 struct ifnet *ifp = &sc->ethercom.ec_if; 1787 bge_hostaddr taddr; 1788 uint32_t val; 1789 1790 /* 1791 * Initialize the memory window pointer register so that 1792 * we can access the first 32K of internal NIC RAM. This will 1793 * allow us to set up the TX send ring RCBs and the RX return 1794 * ring RCBs, plus other things which live in NIC memory. 1795 */ 1796 1797 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_BASEADDR, 0); 1798 1799 /* Configure mbuf memory pool */ 1800 if (BGE_IS_5700_FAMILY(sc)) { 1801 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, 1802 BGE_BUFFPOOL_1); 1803 1804 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) 1805 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000); 1806 else 1807 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000); 1808 1809 /* Configure DMA resource pool */ 1810 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_BASEADDR, 1811 BGE_DMA_DESCRIPTORS); 1812 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LEN, 0x2000); 1813 } 1814 1815 /* Configure mbuf pool watermarks */ 1816 #ifdef ORIG_WPAUL_VALUES 1817 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 24); 1818 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 24); 1819 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 48); 1820 #else 1821 1822 /* new broadcom docs strongly recommend these: */ 1823 if (!BGE_IS_5705_PLUS(sc)) { 1824 if (ifp->if_mtu > ETHER_MAX_LEN) { 1825 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x50); 1826 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x20); 1827 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60); 1828 } else { 1829 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 304); 1830 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 152); 1831 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 380); 1832 } 1833 } else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 1834 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0); 1835 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x04); 1836 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x10); 1837 } else { 1838 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0); 1839 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x10); 1840 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60); 1841 } 1842 #endif 1843 1844 /* Configure DMA resource watermarks */ 1845 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5); 1846 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10); 1847 1848 /* Enable buffer manager */ 1849 CSR_WRITE_4(sc, BGE_BMAN_MODE, 1850 BGE_BMANMODE_ENABLE | BGE_BMANMODE_LOMBUF_ATTN); 1851 1852 /* Poll for buffer manager start indication */ 1853 for (i = 0; i < BGE_TIMEOUT * 2; i++) { 1854 if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE) 1855 break; 1856 DELAY(10); 1857 } 1858 1859 if (i == BGE_TIMEOUT * 2) { 1860 aprint_error_dev(sc->bge_dev, 1861 "buffer manager failed to start\n"); 1862 return ENXIO; 1863 } 1864 1865 /* Enable flow-through queues */ 1866 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 1867 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 1868 1869 /* Wait until queue initialization is complete */ 1870 for (i = 0; i < BGE_TIMEOUT * 2; i++) { 1871 if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0) 1872 break; 1873 DELAY(10); 1874 } 1875 1876 if (i == BGE_TIMEOUT * 2) { 1877 aprint_error_dev(sc->bge_dev, 1878 "flow-through queue init failed\n"); 1879 return ENXIO; 1880 } 1881 1882 /* Initialize the standard RX ring control block */ 1883 rcb = &sc->bge_rdata->bge_info.bge_std_rx_rcb; 1884 BGE_HOSTADDR(rcb->bge_hostaddr, BGE_RING_DMA_ADDR(sc, bge_rx_std_ring)); 1885 if (BGE_IS_5705_PLUS(sc)) 1886 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(512, 0); 1887 else 1888 rcb->bge_maxlen_flags = 1889 BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 0); 1890 rcb->bge_nicaddr = BGE_STD_RX_RINGS; 1891 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcb->bge_hostaddr.bge_addr_hi); 1892 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcb->bge_hostaddr.bge_addr_lo); 1893 CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 1894 CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcb->bge_nicaddr); 1895 1896 /* 1897 * Initialize the jumbo RX ring control block 1898 * We set the 'ring disabled' bit in the flags 1899 * field until we're actually ready to start 1900 * using this ring (i.e. once we set the MTU 1901 * high enough to require it). 1902 */ 1903 if (BGE_IS_JUMBO_CAPABLE(sc)) { 1904 rcb = &sc->bge_rdata->bge_info.bge_jumbo_rx_rcb; 1905 BGE_HOSTADDR(rcb->bge_hostaddr, 1906 BGE_RING_DMA_ADDR(sc, bge_rx_jumbo_ring)); 1907 rcb->bge_maxlen_flags = 1908 BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 1909 BGE_RCB_FLAG_RING_DISABLED); 1910 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS; 1911 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI, 1912 rcb->bge_hostaddr.bge_addr_hi); 1913 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO, 1914 rcb->bge_hostaddr.bge_addr_lo); 1915 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, 1916 rcb->bge_maxlen_flags); 1917 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcb->bge_nicaddr); 1918 1919 /* Set up dummy disabled mini ring RCB */ 1920 rcb = &sc->bge_rdata->bge_info.bge_mini_rx_rcb; 1921 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0, 1922 BGE_RCB_FLAG_RING_DISABLED); 1923 CSR_WRITE_4(sc, BGE_RX_MINI_RCB_MAXLEN_FLAGS, 1924 rcb->bge_maxlen_flags); 1925 1926 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 1927 offsetof(struct bge_ring_data, bge_info), 1928 sizeof (struct bge_gib), 1929 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1930 } 1931 1932 /* 1933 * Set the BD ring replenish thresholds. The recommended 1934 * values are 1/8th the number of descriptors allocated to 1935 * each ring. 1936 */ 1937 i = BGE_STD_RX_RING_CNT / 8; 1938 1939 /* 1940 * Use a value of 8 for the following chips to workaround HW errata. 1941 * Some of these chips have been added based on empirical 1942 * evidence (they don't work unless this is done). 1943 */ 1944 if (BGE_IS_5705_PLUS(sc)) 1945 i = 8; 1946 1947 CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, i); 1948 CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH, BGE_JUMBO_RX_RING_CNT / 8); 1949 1950 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5717 || 1951 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57765) { 1952 CSR_WRITE_4(sc, BGE_STD_REPL_LWM, 4); 1953 CSR_WRITE_4(sc, BGE_JUMBO_REPL_LWM, 4); 1954 } 1955 1956 /* 1957 * Disable all unused send rings by setting the 'ring disabled' 1958 * bit in the flags field of all the TX send ring control blocks. 1959 * These are located in NIC memory. 1960 */ 1961 rcb_addr = BGE_MEMWIN_START + BGE_SEND_RING_RCB; 1962 for (i = 0; i < BGE_TX_RINGS_EXTSSRAM_MAX; i++) { 1963 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 1964 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED)); 1965 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 0); 1966 rcb_addr += sizeof(struct bge_rcb); 1967 } 1968 1969 /* Configure TX RCB 0 (we use only the first ring) */ 1970 rcb_addr = BGE_MEMWIN_START + BGE_SEND_RING_RCB; 1971 BGE_HOSTADDR(taddr, BGE_RING_DMA_ADDR(sc, bge_tx_ring)); 1972 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi); 1973 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo); 1974 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 1975 BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT)); 1976 if (BGE_IS_5700_FAMILY(sc)) 1977 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 1978 BGE_RCB_MAXLEN_FLAGS(BGE_TX_RING_CNT, 0)); 1979 1980 /* Disable all unused RX return rings */ 1981 rcb_addr = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB; 1982 for (i = 0; i < BGE_RX_RINGS_MAX; i++) { 1983 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_hi, 0); 1984 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_lo, 0); 1985 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 1986 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 1987 BGE_RCB_FLAG_RING_DISABLED)); 1988 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 0); 1989 bge_writembx(sc, BGE_MBX_RX_CONS0_LO + 1990 (i * (sizeof(uint64_t))), 0); 1991 rcb_addr += sizeof(struct bge_rcb); 1992 } 1993 1994 /* Initialize RX ring indexes */ 1995 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, 0); 1996 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0); 1997 bge_writembx(sc, BGE_MBX_RX_MINI_PROD_LO, 0); 1998 1999 /* 2000 * Set up RX return ring 0 2001 * Note that the NIC address for RX return rings is 0x00000000. 2002 * The return rings live entirely within the host, so the 2003 * nicaddr field in the RCB isn't used. 2004 */ 2005 rcb_addr = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB; 2006 BGE_HOSTADDR(taddr, BGE_RING_DMA_ADDR(sc, bge_rx_return_ring)); 2007 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi); 2008 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo); 2009 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 0x00000000); 2010 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 2011 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 0)); 2012 2013 /* Set random backoff seed for TX */ 2014 CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF, 2015 CLLADDR(ifp->if_sadl)[0] + CLLADDR(ifp->if_sadl)[1] + 2016 CLLADDR(ifp->if_sadl)[2] + CLLADDR(ifp->if_sadl)[3] + 2017 CLLADDR(ifp->if_sadl)[4] + CLLADDR(ifp->if_sadl)[5] + 2018 BGE_TX_BACKOFF_SEED_MASK); 2019 2020 /* Set inter-packet gap */ 2021 CSR_WRITE_4(sc, BGE_TX_LENGTHS, 0x2620); 2022 2023 /* 2024 * Specify which ring to use for packets that don't match 2025 * any RX rules. 2026 */ 2027 CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08); 2028 2029 /* 2030 * Configure number of RX lists. One interrupt distribution 2031 * list, sixteen active lists, one bad frames class. 2032 */ 2033 CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181); 2034 2035 /* Inialize RX list placement stats mask. */ 2036 CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF); 2037 CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1); 2038 2039 /* Disable host coalescing until we get it set up */ 2040 CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000); 2041 2042 /* Poll to make sure it's shut down. */ 2043 for (i = 0; i < BGE_TIMEOUT * 2; i++) { 2044 if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE)) 2045 break; 2046 DELAY(10); 2047 } 2048 2049 if (i == BGE_TIMEOUT * 2) { 2050 aprint_error_dev(sc->bge_dev, 2051 "host coalescing engine failed to idle\n"); 2052 return ENXIO; 2053 } 2054 2055 /* Set up host coalescing defaults */ 2056 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bge_rx_coal_ticks); 2057 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bge_tx_coal_ticks); 2058 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bge_rx_max_coal_bds); 2059 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bge_tx_max_coal_bds); 2060 if (BGE_IS_5700_FAMILY(sc)) { 2061 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT, 0); 2062 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT, 0); 2063 } 2064 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 0); 2065 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 0); 2066 2067 /* Set up address of statistics block */ 2068 if (BGE_IS_5700_FAMILY(sc)) { 2069 BGE_HOSTADDR(taddr, BGE_RING_DMA_ADDR(sc, bge_info.bge_stats)); 2070 CSR_WRITE_4(sc, BGE_HCC_STATS_TICKS, sc->bge_stat_ticks); 2071 CSR_WRITE_4(sc, BGE_HCC_STATS_BASEADDR, BGE_STATS_BLOCK); 2072 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_HI, taddr.bge_addr_hi); 2073 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_LO, taddr.bge_addr_lo); 2074 } 2075 2076 /* Set up address of status block */ 2077 BGE_HOSTADDR(taddr, BGE_RING_DMA_ADDR(sc, bge_status_block)); 2078 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_BASEADDR, BGE_STATUS_BLOCK); 2079 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI, taddr.bge_addr_hi); 2080 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO, taddr.bge_addr_lo); 2081 sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx = 0; 2082 sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx = 0; 2083 2084 /* Turn on host coalescing state machine */ 2085 CSR_WRITE_4(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE); 2086 2087 /* Turn on RX BD completion state machine and enable attentions */ 2088 CSR_WRITE_4(sc, BGE_RBDC_MODE, 2089 BGE_RBDCMODE_ENABLE | BGE_RBDCMODE_ATTN); 2090 2091 /* Turn on RX list placement state machine */ 2092 CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 2093 2094 /* Turn on RX list selector state machine. */ 2095 if (BGE_IS_5700_FAMILY(sc)) 2096 CSR_WRITE_4(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 2097 2098 val = BGE_MACMODE_TXDMA_ENB | BGE_MACMODE_RXDMA_ENB | 2099 BGE_MACMODE_RX_STATS_CLEAR | BGE_MACMODE_TX_STATS_CLEAR | 2100 BGE_MACMODE_RX_STATS_ENB | BGE_MACMODE_TX_STATS_ENB | 2101 BGE_MACMODE_FRMHDR_DMA_ENB; 2102 2103 if (sc->bge_flags & BGE_PHY_FIBER_TBI) 2104 val |= BGE_PORTMODE_TBI; 2105 else if (sc->bge_flags & BGE_PHY_FIBER_MII) 2106 val |= BGE_PORTMODE_GMII; 2107 else 2108 val |= BGE_PORTMODE_MII; 2109 2110 /* Turn on DMA, clear stats */ 2111 CSR_WRITE_4(sc, BGE_MAC_MODE, val); 2112 2113 2114 /* Set misc. local control, enable interrupts on attentions */ 2115 sc->bge_local_ctrl_reg = BGE_MLC_INTR_ONATTN | BGE_MLC_AUTO_EEPROM; 2116 2117 #ifdef notdef 2118 /* Assert GPIO pins for PHY reset */ 2119 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUT0| 2120 BGE_MLC_MISCIO_OUT1|BGE_MLC_MISCIO_OUT2); 2121 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUTEN0| 2122 BGE_MLC_MISCIO_OUTEN1|BGE_MLC_MISCIO_OUTEN2); 2123 #endif 2124 2125 #if defined(not_quite_yet) 2126 /* Linux driver enables enable gpio pin #1 on 5700s */ 2127 if (sc->bge_chipid == BGE_CHIPID_BCM5700) { 2128 sc->bge_local_ctrl_reg |= 2129 (BGE_MLC_MISCIO_OUT1|BGE_MLC_MISCIO_OUTEN1); 2130 } 2131 #endif 2132 CSR_WRITE_4(sc, BGE_MISC_LOCAL_CTL, sc->bge_local_ctrl_reg); 2133 2134 /* Turn on DMA completion state machine */ 2135 if (BGE_IS_5700_FAMILY(sc)) 2136 CSR_WRITE_4(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 2137 2138 /* Turn on write DMA state machine */ 2139 { 2140 uint32_t bge_wdma_mode = 2141 BGE_WDMAMODE_ENABLE|BGE_WDMAMODE_ALL_ATTNS; 2142 2143 /* Enable host coalescing bug fix; see Linux tg3.c */ 2144 if (BGE_IS_5755_PLUS(sc)) 2145 bge_wdma_mode |= BGE_WDMAMODE_STATUS_TAG_FIX; 2146 2147 CSR_WRITE_4(sc, BGE_WDMA_MODE, bge_wdma_mode); 2148 } 2149 2150 /* Turn on read DMA state machine */ 2151 { 2152 uint32_t dma_read_modebits; 2153 2154 dma_read_modebits = 2155 BGE_RDMAMODE_ENABLE | BGE_RDMAMODE_ALL_ATTNS; 2156 2157 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5784 || 2158 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785 || 2159 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57780) 2160 dma_read_modebits |= BGE_RDMAMODE_BD_SBD_CRPT_ATTN | 2161 BGE_RDMAMODE_MBUF_RBD_CRPT_ATTN | 2162 BGE_RDMAMODE_MBUF_SBD_CRPT_ATTN; 2163 2164 if (sc->bge_flags & BGE_PCIE) 2165 dma_read_modebits |= BGE_RDMA_MODE_FIFO_LONG_BURST; 2166 if (sc->bge_flags & BGE_TSO) 2167 dma_read_modebits |= BGE_RDMAMODE_TSO4_ENABLE; 2168 CSR_WRITE_4(sc, BGE_RDMA_MODE, dma_read_modebits); 2169 delay(40); 2170 } 2171 2172 /* Turn on RX data completion state machine */ 2173 CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 2174 2175 /* Turn on RX BD initiator state machine */ 2176 CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 2177 2178 /* Turn on RX data and RX BD initiator state machine */ 2179 CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE); 2180 2181 /* Turn on Mbuf cluster free state machine */ 2182 if (BGE_IS_5700_FAMILY(sc)) 2183 CSR_WRITE_4(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 2184 2185 /* Turn on send BD completion state machine */ 2186 CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 2187 2188 /* Turn on send data completion state machine */ 2189 val = BGE_SDCMODE_ENABLE; 2190 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761) 2191 val |= BGE_SDCMODE_CDELAY; 2192 CSR_WRITE_4(sc, BGE_SDC_MODE, val); 2193 2194 /* Turn on send data initiator state machine */ 2195 if (sc->bge_flags & BGE_TSO) { 2196 /* XXX: magic value from Linux driver */ 2197 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE | 0x08); 2198 } else { 2199 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 2200 } 2201 2202 /* Turn on send BD initiator state machine */ 2203 CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 2204 2205 /* Turn on send BD selector state machine */ 2206 CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 2207 2208 CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF); 2209 CSR_WRITE_4(sc, BGE_SDI_STATS_CTL, 2210 BGE_SDISTATSCTL_ENABLE | BGE_SDISTATSCTL_FASTER); 2211 2212 /* ack/clear link change events */ 2213 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED | 2214 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE | 2215 BGE_MACSTAT_LINK_CHANGED); 2216 CSR_WRITE_4(sc, BGE_MI_STS, 0); 2217 2218 /* Enable PHY auto polling (for MII/GMII only) */ 2219 if (sc->bge_flags & BGE_PHY_FIBER_TBI) { 2220 CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK); 2221 } else { 2222 BGE_STS_SETBIT(sc, BGE_STS_AUTOPOLL); 2223 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL | (10 << 16)); 2224 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700) 2225 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, 2226 BGE_EVTENB_MI_INTERRUPT); 2227 } 2228 2229 /* 2230 * Clear any pending link state attention. 2231 * Otherwise some link state change events may be lost until attention 2232 * is cleared by bge_intr() -> bge_link_upd() sequence. 2233 * It's not necessary on newer BCM chips - perhaps enabling link 2234 * state change attentions implies clearing pending attention. 2235 */ 2236 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED | 2237 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE | 2238 BGE_MACSTAT_LINK_CHANGED); 2239 2240 /* Enable link state change attentions. */ 2241 BGE_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED); 2242 2243 return 0; 2244 } 2245 2246 static const struct bge_revision * 2247 bge_lookup_rev(uint32_t chipid) 2248 { 2249 const struct bge_revision *br; 2250 2251 for (br = bge_revisions; br->br_name != NULL; br++) { 2252 if (br->br_chipid == chipid) 2253 return br; 2254 } 2255 2256 for (br = bge_majorrevs; br->br_name != NULL; br++) { 2257 if (br->br_chipid == BGE_ASICREV(chipid)) 2258 return br; 2259 } 2260 2261 return NULL; 2262 } 2263 2264 static const struct bge_product * 2265 bge_lookup(const struct pci_attach_args *pa) 2266 { 2267 const struct bge_product *bp; 2268 2269 for (bp = bge_products; bp->bp_name != NULL; bp++) { 2270 if (PCI_VENDOR(pa->pa_id) == bp->bp_vendor && 2271 PCI_PRODUCT(pa->pa_id) == bp->bp_product) 2272 return bp; 2273 } 2274 2275 return NULL; 2276 } 2277 2278 static int 2279 bge_setpowerstate(struct bge_softc *sc, int powerlevel) 2280 { 2281 #ifdef NOTYET 2282 uint32_t pm_ctl = 0; 2283 2284 /* XXX FIXME: make sure indirect accesses enabled? */ 2285 pm_ctl = pci_conf_read(sc->bge_dev, BGE_PCI_MISC_CTL, 4); 2286 pm_ctl |= BGE_PCIMISCCTL_INDIRECT_ACCESS; 2287 pci_write_config(sc->bge_dev, BGE_PCI_MISC_CTL, pm_ctl, 4); 2288 2289 /* clear the PME_assert bit and power state bits, enable PME */ 2290 pm_ctl = pci_conf_read(sc->bge_dev, BGE_PCI_PWRMGMT_CMD, 2); 2291 pm_ctl &= ~PCIM_PSTAT_DMASK; 2292 pm_ctl |= (1 << 8); 2293 2294 if (powerlevel == 0) { 2295 pm_ctl |= PCIM_PSTAT_D0; 2296 pci_write_config(sc->bge_dev, BGE_PCI_PWRMGMT_CMD, 2297 pm_ctl, 2); 2298 DELAY(10000); 2299 CSR_WRITE_4(sc, BGE_MISC_LOCAL_CTL, sc->bge_local_ctrl_reg); 2300 DELAY(10000); 2301 2302 #ifdef NOTYET 2303 /* XXX FIXME: write 0x02 to phy aux_Ctrl reg */ 2304 bge_miibus_writereg(sc->bge_dev, 1, 0x18, 0x02); 2305 #endif 2306 DELAY(40); DELAY(40); DELAY(40); 2307 DELAY(10000); /* above not quite adequate on 5700 */ 2308 return 0; 2309 } 2310 2311 2312 /* 2313 * Entering ACPI power states D1-D3 is achieved by wiggling 2314 * GMII gpio pins. Example code assumes all hardware vendors 2315 * followed Broadom's sample pcb layout. Until we verify that 2316 * for all supported OEM cards, states D1-D3 are unsupported. 2317 */ 2318 aprint_error_dev(sc->bge_dev, 2319 "power state %d unimplemented; check GPIO pins\n", 2320 powerlevel); 2321 #endif 2322 return EOPNOTSUPP; 2323 } 2324 2325 2326 /* 2327 * Probe for a Broadcom chip. Check the PCI vendor and device IDs 2328 * against our list and return its name if we find a match. Note 2329 * that since the Broadcom controller contains VPD support, we 2330 * can get the device name string from the controller itself instead 2331 * of the compiled-in string. This is a little slow, but it guarantees 2332 * we'll always announce the right product name. 2333 */ 2334 static int 2335 bge_probe(device_t parent, cfdata_t match, void *aux) 2336 { 2337 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 2338 2339 if (bge_lookup(pa) != NULL) 2340 return 1; 2341 2342 return 0; 2343 } 2344 2345 static void 2346 bge_attach(device_t parent, device_t self, void *aux) 2347 { 2348 struct bge_softc *sc = device_private(self); 2349 struct pci_attach_args *pa = aux; 2350 prop_dictionary_t dict; 2351 const struct bge_product *bp; 2352 const struct bge_revision *br; 2353 pci_chipset_tag_t pc; 2354 pci_intr_handle_t ih; 2355 const char *intrstr = NULL; 2356 bus_dma_segment_t seg; 2357 int rseg; 2358 uint32_t hwcfg = 0; 2359 uint32_t command; 2360 struct ifnet *ifp; 2361 uint32_t misccfg; 2362 void * kva; 2363 u_char eaddr[ETHER_ADDR_LEN]; 2364 pcireg_t memtype, subid; 2365 bus_addr_t memaddr; 2366 bus_size_t memsize; 2367 uint32_t pm_ctl; 2368 prop_data_t eaddrprop; 2369 bool no_seeprom; 2370 2371 bp = bge_lookup(pa); 2372 KASSERT(bp != NULL); 2373 2374 sc->sc_pc = pa->pa_pc; 2375 sc->sc_pcitag = pa->pa_tag; 2376 sc->bge_dev = self; 2377 2378 pc = sc->sc_pc; 2379 subid = pci_conf_read(pc, sc->sc_pcitag, PCI_SUBSYS_ID_REG); 2380 2381 aprint_naive(": Ethernet controller\n"); 2382 aprint_normal(": %s\n", bp->bp_name); 2383 2384 /* 2385 * Map control/status registers. 2386 */ 2387 DPRINTFN(5, ("Map control/status regs\n")); 2388 command = pci_conf_read(pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG); 2389 command |= PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_MASTER_ENABLE; 2390 pci_conf_write(pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG, command); 2391 command = pci_conf_read(pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG); 2392 2393 if (!(command & PCI_COMMAND_MEM_ENABLE)) { 2394 aprint_error_dev(sc->bge_dev, 2395 "failed to enable memory mapping!\n"); 2396 return; 2397 } 2398 2399 DPRINTFN(5, ("pci_mem_find\n")); 2400 memtype = pci_mapreg_type(sc->sc_pc, sc->sc_pcitag, BGE_PCI_BAR0); 2401 switch (memtype) { 2402 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 2403 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 2404 if (pci_mapreg_map(pa, BGE_PCI_BAR0, 2405 memtype, 0, &sc->bge_btag, &sc->bge_bhandle, 2406 &memaddr, &memsize) == 0) 2407 break; 2408 default: 2409 aprint_error_dev(sc->bge_dev, "can't find mem space\n"); 2410 return; 2411 } 2412 2413 DPRINTFN(5, ("pci_intr_map\n")); 2414 if (pci_intr_map(pa, &ih)) { 2415 aprint_error_dev(sc->bge_dev, "couldn't map interrupt\n"); 2416 return; 2417 } 2418 2419 DPRINTFN(5, ("pci_intr_string\n")); 2420 intrstr = pci_intr_string(pc, ih); 2421 2422 DPRINTFN(5, ("pci_intr_establish\n")); 2423 sc->bge_intrhand = pci_intr_establish(pc, ih, IPL_NET, bge_intr, sc); 2424 2425 if (sc->bge_intrhand == NULL) { 2426 aprint_error_dev(sc->bge_dev, 2427 "couldn't establish interrupt%s%s\n", 2428 intrstr ? " at " : "", intrstr ? intrstr : ""); 2429 return; 2430 } 2431 aprint_normal_dev(sc->bge_dev, "interrupting at %s\n", intrstr); 2432 2433 /* 2434 * Kludge for 5700 Bx bug: a hardware bug (PCIX byte enable?) 2435 * can clobber the chip's PCI config-space power control registers, 2436 * leaving the card in D3 powersave state. 2437 * We do not have memory-mapped registers in this state, 2438 * so force device into D0 state before starting initialization. 2439 */ 2440 pm_ctl = pci_conf_read(pc, sc->sc_pcitag, BGE_PCI_PWRMGMT_CMD); 2441 pm_ctl &= ~(PCI_PWR_D0|PCI_PWR_D1|PCI_PWR_D2|PCI_PWR_D3); 2442 pm_ctl |= (1 << 8) | PCI_PWR_D0 ; /* D0 state */ 2443 pci_conf_write(pc, sc->sc_pcitag, BGE_PCI_PWRMGMT_CMD, pm_ctl); 2444 DELAY(1000); /* 27 usec is allegedly sufficent */ 2445 2446 /* 2447 * Save ASIC rev. 2448 */ 2449 sc->bge_chipid = 2450 pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_MISC_CTL) 2451 >> BGE_PCIMISCCTL_ASICREV_SHIFT; 2452 2453 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_USE_PRODID_REG) { 2454 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5717 || 2455 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5718 || 2456 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5724) 2457 sc->bge_chipid = pci_conf_read(pc, pa->pa_tag, 2458 BGE_PCI_GEN2_PRODID_ASICREV); 2459 else if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM57761 || 2460 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM57765 || 2461 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM57781 || 2462 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM57785 || 2463 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM57791 || 2464 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM57795) 2465 sc->bge_chipid = pci_conf_read(pc, pa->pa_tag, 2466 BGE_PCI_GEN15_PRODID_ASICREV); 2467 else 2468 sc->bge_chipid = pci_conf_read(pc, pa->pa_tag, 2469 BGE_PCI_PRODID_ASICREV); 2470 } 2471 2472 if (pci_get_capability(sc->sc_pc, sc->sc_pcitag, PCI_CAP_PCIEXPRESS, 2473 NULL, NULL) != 0) { 2474 /* PCIe */ 2475 sc->bge_flags |= BGE_PCIE; 2476 } else if ((pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_PCISTATE) & 2477 BGE_PCISTATE_PCI_BUSMODE) == 0) { 2478 /* PCI-X */ 2479 sc->bge_flags |= BGE_PCIX; 2480 } 2481 2482 /* chipid */ 2483 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 2484 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5701 || 2485 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5703 || 2486 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) 2487 sc->bge_flags |= BGE_5700_FAMILY; 2488 2489 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5714_A0 || 2490 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5780 || 2491 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5714) 2492 sc->bge_flags |= BGE_5714_FAMILY; 2493 2494 /* Intentionally exclude BGE_ASICREV_BCM5906 */ 2495 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5717 || 2496 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5755 || 2497 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761 || 2498 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5784 || 2499 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785 || 2500 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5787 || 2501 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57765 || 2502 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57780) 2503 sc->bge_flags |= BGE_5755_PLUS; 2504 2505 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5750 || 2506 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5752 || 2507 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906 || 2508 BGE_IS_5755_PLUS(sc) || 2509 BGE_IS_5714_FAMILY(sc)) 2510 sc->bge_flags |= BGE_5750_PLUS; 2511 2512 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5705 || 2513 BGE_IS_5750_OR_BEYOND(sc)) 2514 sc->bge_flags |= BGE_5705_PLUS; 2515 2516 /* 2517 * When using the BCM5701 in PCI-X mode, data corruption has 2518 * been observed in the first few bytes of some received packets. 2519 * Aligning the packet buffer in memory eliminates the corruption. 2520 * Unfortunately, this misaligns the packet payloads. On platforms 2521 * which do not support unaligned accesses, we will realign the 2522 * payloads by copying the received packets. 2523 */ 2524 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5701 && 2525 sc->bge_flags & BGE_PCIX) 2526 sc->bge_flags |= BGE_RX_ALIGNBUG; 2527 2528 if (BGE_IS_5700_FAMILY(sc)) 2529 sc->bge_flags |= BGE_JUMBO_CAPABLE; 2530 2531 if ((BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 2532 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5701) && 2533 PCI_VENDOR(subid) == PCI_VENDOR_DELL) 2534 sc->bge_flags |= BGE_NO_3LED; 2535 2536 misccfg = CSR_READ_4(sc, BGE_MISC_CFG); 2537 misccfg &= BGE_MISCCFG_BOARD_ID_MASK; 2538 2539 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5705 && 2540 (misccfg == BGE_MISCCFG_BOARD_ID_5788 || 2541 misccfg == BGE_MISCCFG_BOARD_ID_5788M)) 2542 sc->bge_flags |= BGE_IS_5788; 2543 2544 /* 2545 * Some controllers seem to require a special firmware to use 2546 * TSO. But the firmware is not available to FreeBSD and Linux 2547 * claims that the TSO performed by the firmware is slower than 2548 * hardware based TSO. Moreover the firmware based TSO has one 2549 * known bug which can't handle TSO if ethernet header + IP/TCP 2550 * header is greater than 80 bytes. The workaround for the TSO 2551 * bug exist but it seems it's too expensive than not using 2552 * TSO at all. Some hardwares also have the TSO bug so limit 2553 * the TSO to the controllers that are not affected TSO issues 2554 * (e.g. 5755 or higher). 2555 */ 2556 if (BGE_IS_5755_PLUS(sc)) { 2557 /* 2558 * BCM5754 and BCM5787 shares the same ASIC id so 2559 * explicit device id check is required. 2560 */ 2561 if ((PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_BROADCOM_BCM5754) && 2562 (PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_BROADCOM_BCM5754M)) 2563 sc->bge_flags |= BGE_TSO; 2564 } 2565 2566 if ((BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5703 && 2567 (misccfg == 0x4000 || misccfg == 0x8000)) || 2568 (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5705 && 2569 PCI_VENDOR(pa->pa_id) == PCI_VENDOR_BROADCOM && 2570 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5901 || 2571 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5901A2 || 2572 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5705F)) || 2573 (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_BROADCOM && 2574 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5751F || 2575 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5753F || 2576 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5787F)) || 2577 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM57790 || 2578 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 2579 sc->bge_flags |= BGE_10_100_ONLY; 2580 2581 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 2582 (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5705 && 2583 (sc->bge_chipid != BGE_CHIPID_BCM5705_A0 && 2584 sc->bge_chipid != BGE_CHIPID_BCM5705_A1)) || 2585 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 2586 sc->bge_flags |= BGE_NO_ETH_WIRE_SPEED; 2587 2588 if (sc->bge_chipid == BGE_CHIPID_BCM5701_A0 || 2589 sc->bge_chipid == BGE_CHIPID_BCM5701_B0) 2590 sc->bge_flags |= BGE_PHY_CRC_BUG; 2591 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5703_AX || 2592 BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5704_AX) 2593 sc->bge_flags |= BGE_PHY_ADC_BUG; 2594 if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0) 2595 sc->bge_flags |= BGE_PHY_5704_A0_BUG; 2596 2597 if (BGE_IS_5705_PLUS(sc) && 2598 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5906 && 2599 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5717 && 2600 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5785 && 2601 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM57765 && 2602 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM57780) { 2603 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5755 || 2604 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761 || 2605 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5784 || 2606 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5787) { 2607 if (PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_BROADCOM_BCM5722 && 2608 PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_BROADCOM_BCM5756) 2609 sc->bge_flags |= BGE_PHY_JITTER_BUG; 2610 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5755M) 2611 sc->bge_flags |= BGE_PHY_ADJUST_TRIM; 2612 } else if (BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5906) 2613 sc->bge_flags |= BGE_PHY_BER_BUG; 2614 } 2615 2616 /* 2617 * SEEPROM check. 2618 * First check if firmware knows we do not have SEEPROM. 2619 */ 2620 if (prop_dictionary_get_bool(device_properties(self), 2621 "without-seeprom", &no_seeprom) && no_seeprom) 2622 sc->bge_flags |= BGE_NO_EEPROM; 2623 2624 /* Now check the 'ROM failed' bit on the RX CPU */ 2625 else if (CSR_READ_4(sc, BGE_RXCPU_MODE) & BGE_RXCPUMODE_ROMFAIL) 2626 sc->bge_flags |= BGE_NO_EEPROM; 2627 2628 /* Try to reset the chip. */ 2629 DPRINTFN(5, ("bge_reset\n")); 2630 bge_reset(sc); 2631 2632 if (bge_chipinit(sc)) { 2633 aprint_error_dev(sc->bge_dev, "chip initialization failed\n"); 2634 bge_release_resources(sc); 2635 return; 2636 } 2637 2638 /* 2639 * Get station address from the EEPROM (or use firmware values 2640 * if provided via device properties) 2641 */ 2642 eaddrprop = prop_dictionary_get(device_properties(self), "mac-address"); 2643 2644 if (eaddrprop != NULL && prop_data_size(eaddrprop) == ETHER_ADDR_LEN) { 2645 memcpy(eaddr, prop_data_data_nocopy(eaddrprop), 2646 ETHER_ADDR_LEN); 2647 goto got_eaddr; 2648 } 2649 2650 if (bge_get_eaddr(sc, eaddr)) { 2651 aprint_error_dev(sc->bge_dev, 2652 "failed to read station address\n"); 2653 bge_release_resources(sc); 2654 return; 2655 } 2656 2657 got_eaddr: 2658 br = bge_lookup_rev(sc->bge_chipid); 2659 2660 if (br == NULL) { 2661 aprint_normal_dev(sc->bge_dev, "unknown ASIC (0x%x)", 2662 sc->bge_chipid); 2663 } else { 2664 aprint_normal_dev(sc->bge_dev, "ASIC %s (0x%x)", 2665 br->br_name, sc->bge_chipid); 2666 } 2667 aprint_normal(", Ethernet address %s\n", ether_sprintf(eaddr)); 2668 2669 /* Allocate the general information block and ring buffers. */ 2670 if (pci_dma64_available(pa)) 2671 sc->bge_dmatag = pa->pa_dmat64; 2672 else 2673 sc->bge_dmatag = pa->pa_dmat; 2674 DPRINTFN(5, ("bus_dmamem_alloc\n")); 2675 if (bus_dmamem_alloc(sc->bge_dmatag, sizeof(struct bge_ring_data), 2676 PAGE_SIZE, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 2677 aprint_error_dev(sc->bge_dev, "can't alloc rx buffers\n"); 2678 return; 2679 } 2680 DPRINTFN(5, ("bus_dmamem_map\n")); 2681 if (bus_dmamem_map(sc->bge_dmatag, &seg, rseg, 2682 sizeof(struct bge_ring_data), &kva, 2683 BUS_DMA_NOWAIT)) { 2684 aprint_error_dev(sc->bge_dev, 2685 "can't map DMA buffers (%zu bytes)\n", 2686 sizeof(struct bge_ring_data)); 2687 bus_dmamem_free(sc->bge_dmatag, &seg, rseg); 2688 return; 2689 } 2690 DPRINTFN(5, ("bus_dmamem_create\n")); 2691 if (bus_dmamap_create(sc->bge_dmatag, sizeof(struct bge_ring_data), 1, 2692 sizeof(struct bge_ring_data), 0, 2693 BUS_DMA_NOWAIT, &sc->bge_ring_map)) { 2694 aprint_error_dev(sc->bge_dev, "can't create DMA map\n"); 2695 bus_dmamem_unmap(sc->bge_dmatag, kva, 2696 sizeof(struct bge_ring_data)); 2697 bus_dmamem_free(sc->bge_dmatag, &seg, rseg); 2698 return; 2699 } 2700 DPRINTFN(5, ("bus_dmamem_load\n")); 2701 if (bus_dmamap_load(sc->bge_dmatag, sc->bge_ring_map, kva, 2702 sizeof(struct bge_ring_data), NULL, 2703 BUS_DMA_NOWAIT)) { 2704 bus_dmamap_destroy(sc->bge_dmatag, sc->bge_ring_map); 2705 bus_dmamem_unmap(sc->bge_dmatag, kva, 2706 sizeof(struct bge_ring_data)); 2707 bus_dmamem_free(sc->bge_dmatag, &seg, rseg); 2708 return; 2709 } 2710 2711 DPRINTFN(5, ("bzero\n")); 2712 sc->bge_rdata = (struct bge_ring_data *)kva; 2713 2714 memset(sc->bge_rdata, 0, sizeof(struct bge_ring_data)); 2715 2716 /* Try to allocate memory for jumbo buffers. */ 2717 if (BGE_IS_JUMBO_CAPABLE(sc)) { 2718 if (bge_alloc_jumbo_mem(sc)) { 2719 aprint_error_dev(sc->bge_dev, 2720 "jumbo buffer allocation failed\n"); 2721 } else 2722 sc->ethercom.ec_capabilities |= ETHERCAP_JUMBO_MTU; 2723 } 2724 2725 /* Set default tuneable values. */ 2726 sc->bge_stat_ticks = BGE_TICKS_PER_SEC; 2727 sc->bge_rx_coal_ticks = 150; 2728 sc->bge_rx_max_coal_bds = 64; 2729 #ifdef ORIG_WPAUL_VALUES 2730 sc->bge_tx_coal_ticks = 150; 2731 sc->bge_tx_max_coal_bds = 128; 2732 #else 2733 sc->bge_tx_coal_ticks = 300; 2734 sc->bge_tx_max_coal_bds = 400; 2735 #endif 2736 if (BGE_IS_5705_PLUS(sc)) { 2737 sc->bge_tx_coal_ticks = (12 * 5); 2738 sc->bge_tx_max_coal_bds = (12 * 5); 2739 aprint_verbose_dev(sc->bge_dev, 2740 "setting short Tx thresholds\n"); 2741 } 2742 2743 if (BGE_IS_5705_PLUS(sc)) 2744 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT_5705; 2745 else 2746 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT; 2747 2748 /* Set up ifnet structure */ 2749 ifp = &sc->ethercom.ec_if; 2750 ifp->if_softc = sc; 2751 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 2752 ifp->if_ioctl = bge_ioctl; 2753 ifp->if_stop = bge_stop; 2754 ifp->if_start = bge_start; 2755 ifp->if_init = bge_init; 2756 ifp->if_watchdog = bge_watchdog; 2757 IFQ_SET_MAXLEN(&ifp->if_snd, max(BGE_TX_RING_CNT - 1, IFQ_MAXLEN)); 2758 IFQ_SET_READY(&ifp->if_snd); 2759 DPRINTFN(5, ("strcpy if_xname\n")); 2760 strcpy(ifp->if_xname, device_xname(sc->bge_dev)); 2761 2762 if (sc->bge_chipid != BGE_CHIPID_BCM5700_B0) 2763 sc->ethercom.ec_if.if_capabilities |= 2764 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx; 2765 #if 1 /* XXX TCP/UDP checksum offload breaks with pf(4) */ 2766 sc->ethercom.ec_if.if_capabilities |= 2767 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 2768 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 2769 #endif 2770 sc->ethercom.ec_capabilities |= 2771 ETHERCAP_VLAN_HWTAGGING | ETHERCAP_VLAN_MTU; 2772 2773 if (sc->bge_flags & BGE_TSO) 2774 sc->ethercom.ec_if.if_capabilities |= IFCAP_TSOv4; 2775 2776 /* 2777 * Do MII setup. 2778 */ 2779 DPRINTFN(5, ("mii setup\n")); 2780 sc->bge_mii.mii_ifp = ifp; 2781 sc->bge_mii.mii_readreg = bge_miibus_readreg; 2782 sc->bge_mii.mii_writereg = bge_miibus_writereg; 2783 sc->bge_mii.mii_statchg = bge_miibus_statchg; 2784 2785 /* 2786 * Figure out what sort of media we have by checking the 2787 * hardware config word in the first 32k of NIC internal memory, 2788 * or fall back to the config word in the EEPROM. Note: on some BCM5700 2789 * cards, this value appears to be unset. If that's the 2790 * case, we have to rely on identifying the NIC by its PCI 2791 * subsystem ID, as we do below for the SysKonnect SK-9D41. 2792 */ 2793 if (bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_SIG) == BGE_MAGIC_NUMBER) { 2794 hwcfg = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_NICCFG); 2795 } else if (!(sc->bge_flags & BGE_NO_EEPROM)) { 2796 bge_read_eeprom(sc, (void *)&hwcfg, 2797 BGE_EE_HWCFG_OFFSET, sizeof(hwcfg)); 2798 hwcfg = be32toh(hwcfg); 2799 } 2800 /* The SysKonnect SK-9D41 is a 1000baseSX card. */ 2801 if (PCI_PRODUCT(pa->pa_id) == SK_SUBSYSID_9D41 || 2802 (hwcfg & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER) { 2803 if (BGE_IS_5714_FAMILY(sc)) 2804 sc->bge_flags |= BGE_PHY_FIBER_MII; 2805 else 2806 sc->bge_flags |= BGE_PHY_FIBER_TBI; 2807 } 2808 2809 /* set phyflags before mii_attach() */ 2810 dict = device_properties(self); 2811 prop_dictionary_set_uint32(dict, "phyflags", sc->bge_flags); 2812 2813 if (sc->bge_flags & BGE_PHY_FIBER_TBI) { 2814 ifmedia_init(&sc->bge_ifmedia, IFM_IMASK, bge_ifmedia_upd, 2815 bge_ifmedia_sts); 2816 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL); 2817 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_1000_SX|IFM_FDX, 2818 0, NULL); 2819 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL); 2820 ifmedia_set(&sc->bge_ifmedia, IFM_ETHER|IFM_AUTO); 2821 /* Pretend the user requested this setting */ 2822 sc->bge_ifmedia.ifm_media = sc->bge_ifmedia.ifm_cur->ifm_media; 2823 } else { 2824 /* 2825 * Do transceiver setup. 2826 */ 2827 ifmedia_init(&sc->bge_mii.mii_media, 0, bge_ifmedia_upd, 2828 bge_ifmedia_sts); 2829 mii_attach(sc->bge_dev, &sc->bge_mii, 0xffffffff, 2830 MII_PHY_ANY, MII_OFFSET_ANY, 2831 MIIF_FORCEANEG|MIIF_DOPAUSE); 2832 2833 if (LIST_EMPTY(&sc->bge_mii.mii_phys)) { 2834 aprint_error_dev(sc->bge_dev, "no PHY found!\n"); 2835 ifmedia_add(&sc->bge_mii.mii_media, 2836 IFM_ETHER|IFM_MANUAL, 0, NULL); 2837 ifmedia_set(&sc->bge_mii.mii_media, 2838 IFM_ETHER|IFM_MANUAL); 2839 } else 2840 ifmedia_set(&sc->bge_mii.mii_media, 2841 IFM_ETHER|IFM_AUTO); 2842 } 2843 2844 /* 2845 * Call MI attach routine. 2846 */ 2847 DPRINTFN(5, ("if_attach\n")); 2848 if_attach(ifp); 2849 DPRINTFN(5, ("ether_ifattach\n")); 2850 ether_ifattach(ifp, eaddr); 2851 #if NRND > 0 2852 rnd_attach_source(&sc->rnd_source, device_xname(sc->bge_dev), 2853 RND_TYPE_NET, 0); 2854 #endif 2855 #ifdef BGE_EVENT_COUNTERS 2856 /* 2857 * Attach event counters. 2858 */ 2859 evcnt_attach_dynamic(&sc->bge_ev_intr, EVCNT_TYPE_INTR, 2860 NULL, device_xname(sc->bge_dev), "intr"); 2861 evcnt_attach_dynamic(&sc->bge_ev_tx_xoff, EVCNT_TYPE_MISC, 2862 NULL, device_xname(sc->bge_dev), "tx_xoff"); 2863 evcnt_attach_dynamic(&sc->bge_ev_tx_xon, EVCNT_TYPE_MISC, 2864 NULL, device_xname(sc->bge_dev), "tx_xon"); 2865 evcnt_attach_dynamic(&sc->bge_ev_rx_xoff, EVCNT_TYPE_MISC, 2866 NULL, device_xname(sc->bge_dev), "rx_xoff"); 2867 evcnt_attach_dynamic(&sc->bge_ev_rx_xon, EVCNT_TYPE_MISC, 2868 NULL, device_xname(sc->bge_dev), "rx_xon"); 2869 evcnt_attach_dynamic(&sc->bge_ev_rx_macctl, EVCNT_TYPE_MISC, 2870 NULL, device_xname(sc->bge_dev), "rx_macctl"); 2871 evcnt_attach_dynamic(&sc->bge_ev_xoffentered, EVCNT_TYPE_MISC, 2872 NULL, device_xname(sc->bge_dev), "xoffentered"); 2873 #endif /* BGE_EVENT_COUNTERS */ 2874 DPRINTFN(5, ("callout_init\n")); 2875 callout_init(&sc->bge_timeout, 0); 2876 2877 if (pmf_device_register(self, NULL, NULL)) 2878 pmf_class_network_register(self, ifp); 2879 else 2880 aprint_error_dev(self, "couldn't establish power handler\n"); 2881 2882 #ifdef BGE_DEBUG 2883 bge_debug_info(sc); 2884 #endif 2885 } 2886 2887 static void 2888 bge_release_resources(struct bge_softc *sc) 2889 { 2890 if (sc->bge_vpd_prodname != NULL) 2891 free(sc->bge_vpd_prodname, M_DEVBUF); 2892 2893 if (sc->bge_vpd_readonly != NULL) 2894 free(sc->bge_vpd_readonly, M_DEVBUF); 2895 } 2896 2897 static void 2898 bge_reset(struct bge_softc *sc) 2899 { 2900 uint32_t cachesize, command, pcistate, new_pcistate; 2901 int i, val; 2902 void (*write_op)(struct bge_softc *, int, int); 2903 2904 if (BGE_IS_5750_OR_BEYOND(sc) && !BGE_IS_5714_FAMILY(sc) && 2905 (BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5906)) { 2906 if (sc->bge_flags & BGE_PCIE) { 2907 write_op = bge_writemem_direct; 2908 } else { 2909 write_op = bge_writemem_ind; 2910 } 2911 } else { 2912 write_op = bge_writereg_ind; 2913 } 2914 2915 2916 /* Save some important PCI state. */ 2917 cachesize = pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CACHESZ); 2918 command = pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CMD); 2919 pcistate = pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_PCISTATE); 2920 2921 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MISC_CTL, 2922 BGE_PCIMISCCTL_INDIRECT_ACCESS | BGE_PCIMISCCTL_MASK_PCI_INTR | 2923 BGE_HIF_SWAP_OPTIONS | BGE_PCIMISCCTL_PCISTATE_RW); 2924 2925 /* Disable fastboot on controllers that support it. */ 2926 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5752 || 2927 BGE_IS_5755_PLUS(sc)) 2928 CSR_WRITE_4(sc, BGE_FASTBOOT_PC, 0); 2929 2930 val = BGE_MISCCFG_RESET_CORE_CLOCKS | (65<<1); 2931 /* 2932 * XXX: from FreeBSD/Linux; no documentation 2933 */ 2934 if (sc->bge_flags & BGE_PCIE) { 2935 if (CSR_READ_4(sc, BGE_PCIE_CTL1) == 0x60) 2936 /* PCI Express 1.0 system */ 2937 CSR_WRITE_4(sc, BGE_PCIE_CTL1, 0x20); 2938 if (sc->bge_chipid != BGE_CHIPID_BCM5750_A0) { 2939 /* 2940 * Prevent PCI Express link training 2941 * during global reset. 2942 */ 2943 CSR_WRITE_4(sc, BGE_MISC_CFG, 1 << 29); 2944 val |= (1<<29); 2945 } 2946 } 2947 2948 /* 2949 * Set GPHY Power Down Override to leave GPHY 2950 * powered up in D0 uninitialized. 2951 */ 2952 if (BGE_IS_5705_PLUS(sc)) 2953 val |= BGE_MISCCFG_KEEP_GPHY_POWER; 2954 2955 /* Issue global reset */ 2956 write_op(sc, BGE_MISC_CFG, val); 2957 2958 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 2959 i = CSR_READ_4(sc, BGE_VCPU_STATUS); 2960 CSR_WRITE_4(sc, BGE_VCPU_STATUS, 2961 i | BGE_VCPU_STATUS_DRV_RESET); 2962 i = CSR_READ_4(sc, BGE_VCPU_EXT_CTRL); 2963 CSR_WRITE_4(sc, BGE_VCPU_EXT_CTRL, 2964 i & ~BGE_VCPU_EXT_CTRL_HALT_CPU); 2965 } 2966 2967 DELAY(1000); 2968 2969 /* 2970 * XXX: from FreeBSD/Linux; no documentation 2971 */ 2972 if (sc->bge_flags & BGE_PCIE) { 2973 if (sc->bge_chipid == BGE_CHIPID_BCM5750_A0) { 2974 pcireg_t reg; 2975 2976 DELAY(500000); 2977 /* XXX: Magic Numbers */ 2978 reg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 2979 BGE_PCI_UNKNOWN0); 2980 pci_conf_write(sc->sc_pc, sc->sc_pcitag, 2981 BGE_PCI_UNKNOWN0, 2982 reg | (1 << 15)); 2983 } 2984 /* 2985 * XXX: Magic Numbers. 2986 * Sets maximal PCI-e payload and clears any PCI-e errors. 2987 * Should be replaced with references to PCI config-space 2988 * capability block for PCI-Express. 2989 */ 2990 pci_conf_write(sc->sc_pc, sc->sc_pcitag, 2991 BGE_PCI_CONF_DEV_CTRL, 0xf5000); 2992 2993 } 2994 2995 /* Reset some of the PCI state that got zapped by reset */ 2996 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MISC_CTL, 2997 BGE_PCIMISCCTL_INDIRECT_ACCESS | BGE_PCIMISCCTL_MASK_PCI_INTR | 2998 BGE_HIF_SWAP_OPTIONS | BGE_PCIMISCCTL_PCISTATE_RW); 2999 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CACHESZ, cachesize); 3000 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CMD, command); 3001 write_op(sc, BGE_MISC_CFG, (65 << 1)); 3002 3003 /* Enable memory arbiter. */ 3004 { 3005 uint32_t marbmode = 0; 3006 if (BGE_IS_5714_FAMILY(sc)) { 3007 marbmode = CSR_READ_4(sc, BGE_MARB_MODE); 3008 } 3009 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE | marbmode); 3010 } 3011 3012 /* 3013 * Prevent PXE restart: write a magic number to the 3014 * general communications memory at 0xB50. 3015 */ 3016 bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM, BGE_MAGIC_NUMBER); 3017 3018 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 3019 for (i = 0; i < BGE_TIMEOUT; i++) { 3020 val = CSR_READ_4(sc, BGE_VCPU_STATUS); 3021 if (val & BGE_VCPU_STATUS_INIT_DONE) 3022 break; 3023 DELAY(100); 3024 } 3025 if (i == BGE_TIMEOUT) { 3026 aprint_error_dev(sc->bge_dev, "reset timed out\n"); 3027 return; 3028 } 3029 } else { 3030 /* 3031 * Poll the value location we just wrote until 3032 * we see the 1's complement of the magic number. 3033 * This indicates that the firmware initialization 3034 * is complete. 3035 */ 3036 for (i = 0; i < BGE_TIMEOUT; i++) { 3037 val = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM); 3038 if (val == ~BGE_MAGIC_NUMBER) 3039 break; 3040 DELAY(10); 3041 } 3042 3043 if (i >= BGE_TIMEOUT && (!(sc->bge_flags & BGE_NO_EEPROM))) { 3044 aprint_error_dev(sc->bge_dev, 3045 "firmware handshake timed out, val = %x\n", val); 3046 /* 3047 * XXX: occasionally fired on bcm5721, but without 3048 * apparent harm. For now, keep going if we timeout 3049 * against PCI-E devices. 3050 */ 3051 if ((sc->bge_flags & BGE_PCIE) == 0) 3052 return; 3053 } 3054 } 3055 3056 /* 3057 * XXX Wait for the value of the PCISTATE register to 3058 * return to its original pre-reset state. This is a 3059 * fairly good indicator of reset completion. If we don't 3060 * wait for the reset to fully complete, trying to read 3061 * from the device's non-PCI registers may yield garbage 3062 * results. 3063 */ 3064 for (i = 0; i < BGE_TIMEOUT; i++) { 3065 new_pcistate = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 3066 BGE_PCI_PCISTATE); 3067 if ((new_pcistate & ~BGE_PCISTATE_RESERVED) == 3068 (pcistate & ~BGE_PCISTATE_RESERVED)) 3069 break; 3070 DELAY(10); 3071 } 3072 if ((new_pcistate & ~BGE_PCISTATE_RESERVED) != 3073 (pcistate & ~BGE_PCISTATE_RESERVED)) { 3074 aprint_error_dev(sc->bge_dev, "pcistate failed to revert\n"); 3075 } 3076 3077 #if 0 3078 /* Enable memory arbiter. */ 3079 /* XXX why do this twice? */ 3080 { 3081 uint32_t marbmode = 0; 3082 if (BGE_IS_5714_FAMILY(sc)) { 3083 marbmode = CSR_READ_4(sc, BGE_MARB_MODE); 3084 } 3085 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE | marbmode); 3086 } 3087 #endif 3088 3089 /* Fix up byte swapping */ 3090 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS); 3091 3092 CSR_WRITE_4(sc, BGE_MAC_MODE, 0); 3093 3094 /* 3095 * The 5704 in TBI mode apparently needs some special 3096 * adjustment to insure the SERDES drive level is set 3097 * to 1.2V. 3098 */ 3099 if (sc->bge_flags & BGE_PHY_FIBER_TBI && 3100 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) { 3101 uint32_t serdescfg; 3102 3103 serdescfg = CSR_READ_4(sc, BGE_SERDES_CFG); 3104 serdescfg = (serdescfg & ~0xFFF) | 0x880; 3105 CSR_WRITE_4(sc, BGE_SERDES_CFG, serdescfg); 3106 } 3107 3108 if (sc->bge_flags & BGE_PCIE && 3109 sc->bge_chipid != BGE_CHIPID_BCM5750_A0 && 3110 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5717 && 3111 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5785 && 3112 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM57765) { 3113 uint32_t v; 3114 3115 /* Enable PCI Express bug fix */ 3116 v = CSR_READ_4(sc, 0x7c00); 3117 CSR_WRITE_4(sc, 0x7c00, v | (1<<25)); 3118 } 3119 DELAY(10000); 3120 } 3121 3122 /* 3123 * Frame reception handling. This is called if there's a frame 3124 * on the receive return list. 3125 * 3126 * Note: we have to be able to handle two possibilities here: 3127 * 1) the frame is from the jumbo recieve ring 3128 * 2) the frame is from the standard receive ring 3129 */ 3130 3131 static void 3132 bge_rxeof(struct bge_softc *sc) 3133 { 3134 struct ifnet *ifp; 3135 uint16_t rx_prod, rx_cons; 3136 int stdcnt = 0, jumbocnt = 0; 3137 bus_dmamap_t dmamap; 3138 bus_addr_t offset, toff; 3139 bus_size_t tlen; 3140 int tosync; 3141 3142 rx_cons = sc->bge_rx_saved_considx; 3143 rx_prod = sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx; 3144 3145 /* Nothing to do */ 3146 if (rx_cons == rx_prod) 3147 return; 3148 3149 ifp = &sc->ethercom.ec_if; 3150 3151 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 3152 offsetof(struct bge_ring_data, bge_status_block), 3153 sizeof (struct bge_status_block), 3154 BUS_DMASYNC_POSTREAD); 3155 3156 offset = offsetof(struct bge_ring_data, bge_rx_return_ring); 3157 tosync = rx_prod - rx_cons; 3158 3159 #if NRND > 0 3160 if (tosync != 0 && RND_ENABLED(&sc->rnd_source)) 3161 rnd_add_uint32(&sc->rnd_source, tosync); 3162 #endif 3163 3164 toff = offset + (rx_cons * sizeof (struct bge_rx_bd)); 3165 3166 if (tosync < 0) { 3167 tlen = (sc->bge_return_ring_cnt - rx_cons) * 3168 sizeof (struct bge_rx_bd); 3169 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 3170 toff, tlen, BUS_DMASYNC_POSTREAD); 3171 tosync = -tosync; 3172 } 3173 3174 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 3175 offset, tosync * sizeof (struct bge_rx_bd), 3176 BUS_DMASYNC_POSTREAD); 3177 3178 while (rx_cons != rx_prod) { 3179 struct bge_rx_bd *cur_rx; 3180 uint32_t rxidx; 3181 struct mbuf *m = NULL; 3182 3183 cur_rx = &sc->bge_rdata->bge_rx_return_ring[rx_cons]; 3184 3185 rxidx = cur_rx->bge_idx; 3186 BGE_INC(rx_cons, sc->bge_return_ring_cnt); 3187 3188 if (cur_rx->bge_flags & BGE_RXBDFLAG_JUMBO_RING) { 3189 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT); 3190 m = sc->bge_cdata.bge_rx_jumbo_chain[rxidx]; 3191 sc->bge_cdata.bge_rx_jumbo_chain[rxidx] = NULL; 3192 jumbocnt++; 3193 bus_dmamap_sync(sc->bge_dmatag, 3194 sc->bge_cdata.bge_rx_jumbo_map, 3195 mtod(m, char *) - (char *)sc->bge_cdata.bge_jumbo_buf, 3196 BGE_JLEN, BUS_DMASYNC_POSTREAD); 3197 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 3198 ifp->if_ierrors++; 3199 bge_newbuf_jumbo(sc, sc->bge_jumbo, m); 3200 continue; 3201 } 3202 if (bge_newbuf_jumbo(sc, sc->bge_jumbo, 3203 NULL)== ENOBUFS) { 3204 ifp->if_ierrors++; 3205 bge_newbuf_jumbo(sc, sc->bge_jumbo, m); 3206 continue; 3207 } 3208 } else { 3209 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT); 3210 m = sc->bge_cdata.bge_rx_std_chain[rxidx]; 3211 3212 sc->bge_cdata.bge_rx_std_chain[rxidx] = NULL; 3213 stdcnt++; 3214 dmamap = sc->bge_cdata.bge_rx_std_map[rxidx]; 3215 sc->bge_cdata.bge_rx_std_map[rxidx] = 0; 3216 bus_dmamap_sync(sc->bge_dmatag, dmamap, 0, 3217 dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 3218 bus_dmamap_unload(sc->bge_dmatag, dmamap); 3219 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 3220 ifp->if_ierrors++; 3221 bge_newbuf_std(sc, sc->bge_std, m, dmamap); 3222 continue; 3223 } 3224 if (bge_newbuf_std(sc, sc->bge_std, 3225 NULL, dmamap) == ENOBUFS) { 3226 ifp->if_ierrors++; 3227 bge_newbuf_std(sc, sc->bge_std, m, dmamap); 3228 continue; 3229 } 3230 } 3231 3232 ifp->if_ipackets++; 3233 #ifndef __NO_STRICT_ALIGNMENT 3234 /* 3235 * XXX: if the 5701 PCIX-Rx-DMA workaround is in effect, 3236 * the Rx buffer has the layer-2 header unaligned. 3237 * If our CPU requires alignment, re-align by copying. 3238 */ 3239 if (sc->bge_flags & BGE_RX_ALIGNBUG) { 3240 memmove(mtod(m, char *) + ETHER_ALIGN, m->m_data, 3241 cur_rx->bge_len); 3242 m->m_data += ETHER_ALIGN; 3243 } 3244 #endif 3245 3246 m->m_pkthdr.len = m->m_len = cur_rx->bge_len - ETHER_CRC_LEN; 3247 m->m_pkthdr.rcvif = ifp; 3248 3249 /* 3250 * Handle BPF listeners. Let the BPF user see the packet. 3251 */ 3252 if (ifp->if_bpf) 3253 bpf_ops->bpf_mtap(ifp->if_bpf, m); 3254 3255 m->m_pkthdr.csum_flags = M_CSUM_IPv4; 3256 3257 if ((cur_rx->bge_ip_csum ^ 0xffff) != 0) 3258 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 3259 /* 3260 * Rx transport checksum-offload may also 3261 * have bugs with packets which, when transmitted, 3262 * were `runts' requiring padding. 3263 */ 3264 if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM && 3265 (/* (sc->_bge_quirks & BGE_QUIRK_SHORT_CKSUM_BUG) == 0 ||*/ 3266 m->m_pkthdr.len >= ETHER_MIN_NOPAD)) { 3267 m->m_pkthdr.csum_data = 3268 cur_rx->bge_tcp_udp_csum; 3269 m->m_pkthdr.csum_flags |= 3270 (M_CSUM_TCPv4|M_CSUM_UDPv4| 3271 M_CSUM_DATA|M_CSUM_NO_PSEUDOHDR); 3272 } 3273 3274 /* 3275 * If we received a packet with a vlan tag, pass it 3276 * to vlan_input() instead of ether_input(). 3277 */ 3278 if (cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) { 3279 VLAN_INPUT_TAG(ifp, m, cur_rx->bge_vlan_tag, continue); 3280 } 3281 3282 (*ifp->if_input)(ifp, m); 3283 } 3284 3285 sc->bge_rx_saved_considx = rx_cons; 3286 bge_writembx(sc, BGE_MBX_RX_CONS0_LO, sc->bge_rx_saved_considx); 3287 if (stdcnt) 3288 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std); 3289 if (jumbocnt) 3290 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo); 3291 } 3292 3293 static void 3294 bge_txeof(struct bge_softc *sc) 3295 { 3296 struct bge_tx_bd *cur_tx = NULL; 3297 struct ifnet *ifp; 3298 struct txdmamap_pool_entry *dma; 3299 bus_addr_t offset, toff; 3300 bus_size_t tlen; 3301 int tosync; 3302 struct mbuf *m; 3303 3304 ifp = &sc->ethercom.ec_if; 3305 3306 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 3307 offsetof(struct bge_ring_data, bge_status_block), 3308 sizeof (struct bge_status_block), 3309 BUS_DMASYNC_POSTREAD); 3310 3311 offset = offsetof(struct bge_ring_data, bge_tx_ring); 3312 tosync = sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx - 3313 sc->bge_tx_saved_considx; 3314 3315 #if NRND > 0 3316 if (tosync != 0 && RND_ENABLED(&sc->rnd_source)) 3317 rnd_add_uint32(&sc->rnd_source, tosync); 3318 #endif 3319 3320 toff = offset + (sc->bge_tx_saved_considx * sizeof (struct bge_tx_bd)); 3321 3322 if (tosync < 0) { 3323 tlen = (BGE_TX_RING_CNT - sc->bge_tx_saved_considx) * 3324 sizeof (struct bge_tx_bd); 3325 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 3326 toff, tlen, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 3327 tosync = -tosync; 3328 } 3329 3330 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 3331 offset, tosync * sizeof (struct bge_tx_bd), 3332 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 3333 3334 /* 3335 * Go through our tx ring and free mbufs for those 3336 * frames that have been sent. 3337 */ 3338 while (sc->bge_tx_saved_considx != 3339 sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx) { 3340 uint32_t idx = 0; 3341 3342 idx = sc->bge_tx_saved_considx; 3343 cur_tx = &sc->bge_rdata->bge_tx_ring[idx]; 3344 if (cur_tx->bge_flags & BGE_TXBDFLAG_END) 3345 ifp->if_opackets++; 3346 m = sc->bge_cdata.bge_tx_chain[idx]; 3347 if (m != NULL) { 3348 sc->bge_cdata.bge_tx_chain[idx] = NULL; 3349 dma = sc->txdma[idx]; 3350 bus_dmamap_sync(sc->bge_dmatag, dma->dmamap, 0, 3351 dma->dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 3352 bus_dmamap_unload(sc->bge_dmatag, dma->dmamap); 3353 SLIST_INSERT_HEAD(&sc->txdma_list, dma, link); 3354 sc->txdma[idx] = NULL; 3355 3356 m_freem(m); 3357 } 3358 sc->bge_txcnt--; 3359 BGE_INC(sc->bge_tx_saved_considx, BGE_TX_RING_CNT); 3360 ifp->if_timer = 0; 3361 } 3362 3363 if (cur_tx != NULL) 3364 ifp->if_flags &= ~IFF_OACTIVE; 3365 } 3366 3367 static int 3368 bge_intr(void *xsc) 3369 { 3370 struct bge_softc *sc; 3371 struct ifnet *ifp; 3372 uint32_t statusword; 3373 3374 sc = xsc; 3375 ifp = &sc->ethercom.ec_if; 3376 3377 /* It is possible for the interrupt to arrive before 3378 * the status block is updated prior to the interrupt. 3379 * Reading the PCI State register will confirm whether the 3380 * interrupt is ours and will flush the status block. 3381 */ 3382 3383 /* read status word from status block */ 3384 statusword = sc->bge_rdata->bge_status_block.bge_status; 3385 3386 if ((statusword & BGE_STATFLAG_UPDATED) || 3387 (!(CSR_READ_4(sc, BGE_PCI_PCISTATE) & BGE_PCISTATE_INTR_NOT_ACTIVE))) { 3388 /* Ack interrupt and stop others from occuring. */ 3389 bge_writembx(sc, BGE_MBX_IRQ0_LO, 1); 3390 3391 BGE_EVCNT_INCR(sc->bge_ev_intr); 3392 3393 /* clear status word */ 3394 sc->bge_rdata->bge_status_block.bge_status = 0; 3395 3396 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 3397 statusword & BGE_STATFLAG_LINKSTATE_CHANGED || 3398 BGE_STS_BIT(sc, BGE_STS_LINK_EVT)) 3399 bge_link_upd(sc); 3400 3401 if (ifp->if_flags & IFF_RUNNING) { 3402 /* Check RX return ring producer/consumer */ 3403 bge_rxeof(sc); 3404 3405 /* Check TX ring producer/consumer */ 3406 bge_txeof(sc); 3407 } 3408 3409 if (sc->bge_pending_rxintr_change) { 3410 uint32_t rx_ticks = sc->bge_rx_coal_ticks; 3411 uint32_t rx_bds = sc->bge_rx_max_coal_bds; 3412 uint32_t junk; 3413 3414 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, rx_ticks); 3415 DELAY(10); 3416 junk = CSR_READ_4(sc, BGE_HCC_RX_COAL_TICKS); 3417 3418 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, rx_bds); 3419 DELAY(10); 3420 junk = CSR_READ_4(sc, BGE_HCC_RX_MAX_COAL_BDS); 3421 3422 sc->bge_pending_rxintr_change = 0; 3423 } 3424 bge_handle_events(sc); 3425 3426 /* Re-enable interrupts. */ 3427 bge_writembx(sc, BGE_MBX_IRQ0_LO, 0); 3428 3429 if (ifp->if_flags & IFF_RUNNING && !IFQ_IS_EMPTY(&ifp->if_snd)) 3430 bge_start(ifp); 3431 3432 return 1; 3433 } else 3434 return 0; 3435 } 3436 3437 static void 3438 bge_tick(void *xsc) 3439 { 3440 struct bge_softc *sc = xsc; 3441 struct mii_data *mii = &sc->bge_mii; 3442 int s; 3443 3444 s = splnet(); 3445 3446 if (BGE_IS_5705_PLUS(sc)) 3447 bge_stats_update_regs(sc); 3448 else 3449 bge_stats_update(sc); 3450 3451 if (sc->bge_flags & BGE_PHY_FIBER_TBI) { 3452 /* 3453 * Since in TBI mode auto-polling can't be used we should poll 3454 * link status manually. Here we register pending link event 3455 * and trigger interrupt. 3456 */ 3457 BGE_STS_SETBIT(sc, BGE_STS_LINK_EVT); 3458 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET); 3459 } else { 3460 /* 3461 * Do not touch PHY if we have link up. This could break 3462 * IPMI/ASF mode or produce extra input errors. 3463 * (extra input errors was reported for bcm5701 & bcm5704). 3464 */ 3465 if (!BGE_STS_BIT(sc, BGE_STS_LINK)) 3466 mii_tick(mii); 3467 } 3468 3469 callout_reset(&sc->bge_timeout, hz, bge_tick, sc); 3470 3471 splx(s); 3472 } 3473 3474 static void 3475 bge_stats_update_regs(struct bge_softc *sc) 3476 { 3477 struct ifnet *ifp = &sc->ethercom.ec_if; 3478 3479 ifp->if_collisions += CSR_READ_4(sc, BGE_MAC_STATS + 3480 offsetof(struct bge_mac_stats_regs, etherStatsCollisions)); 3481 3482 ifp->if_ierrors += CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_DROPS); 3483 ifp->if_ierrors += CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_ERRORS); 3484 ifp->if_ierrors += CSR_READ_4(sc, BGE_RXLP_LOCSTAT_OUT_OF_BDS); 3485 } 3486 3487 static void 3488 bge_stats_update(struct bge_softc *sc) 3489 { 3490 struct ifnet *ifp = &sc->ethercom.ec_if; 3491 bus_size_t stats = BGE_MEMWIN_START + BGE_STATS_BLOCK; 3492 3493 #define READ_STAT(sc, stats, stat) \ 3494 CSR_READ_4(sc, stats + offsetof(struct bge_stats, stat)) 3495 3496 ifp->if_collisions += 3497 (READ_STAT(sc, stats, dot3StatsSingleCollisionFrames.bge_addr_lo) + 3498 READ_STAT(sc, stats, dot3StatsMultipleCollisionFrames.bge_addr_lo) + 3499 READ_STAT(sc, stats, dot3StatsExcessiveCollisions.bge_addr_lo) + 3500 READ_STAT(sc, stats, dot3StatsLateCollisions.bge_addr_lo)) - 3501 ifp->if_collisions; 3502 3503 BGE_EVCNT_UPD(sc->bge_ev_tx_xoff, 3504 READ_STAT(sc, stats, outXoffSent.bge_addr_lo)); 3505 BGE_EVCNT_UPD(sc->bge_ev_tx_xon, 3506 READ_STAT(sc, stats, outXonSent.bge_addr_lo)); 3507 BGE_EVCNT_UPD(sc->bge_ev_rx_xoff, 3508 READ_STAT(sc, stats, 3509 xoffPauseFramesReceived.bge_addr_lo)); 3510 BGE_EVCNT_UPD(sc->bge_ev_rx_xon, 3511 READ_STAT(sc, stats, xonPauseFramesReceived.bge_addr_lo)); 3512 BGE_EVCNT_UPD(sc->bge_ev_rx_macctl, 3513 READ_STAT(sc, stats, 3514 macControlFramesReceived.bge_addr_lo)); 3515 BGE_EVCNT_UPD(sc->bge_ev_xoffentered, 3516 READ_STAT(sc, stats, xoffStateEntered.bge_addr_lo)); 3517 3518 #undef READ_STAT 3519 3520 #ifdef notdef 3521 ifp->if_collisions += 3522 (sc->bge_rdata->bge_info.bge_stats.dot3StatsSingleCollisionFrames + 3523 sc->bge_rdata->bge_info.bge_stats.dot3StatsMultipleCollisionFrames + 3524 sc->bge_rdata->bge_info.bge_stats.dot3StatsExcessiveCollisions + 3525 sc->bge_rdata->bge_info.bge_stats.dot3StatsLateCollisions) - 3526 ifp->if_collisions; 3527 #endif 3528 } 3529 3530 /* 3531 * Pad outbound frame to ETHER_MIN_NOPAD for an unusual reason. 3532 * The bge hardware will pad out Tx runts to ETHER_MIN_NOPAD, 3533 * but when such padded frames employ the bge IP/TCP checksum offload, 3534 * the hardware checksum assist gives incorrect results (possibly 3535 * from incorporating its own padding into the UDP/TCP checksum; who knows). 3536 * If we pad such runts with zeros, the onboard checksum comes out correct. 3537 */ 3538 static inline int 3539 bge_cksum_pad(struct mbuf *pkt) 3540 { 3541 struct mbuf *last = NULL; 3542 int padlen; 3543 3544 padlen = ETHER_MIN_NOPAD - pkt->m_pkthdr.len; 3545 3546 /* if there's only the packet-header and we can pad there, use it. */ 3547 if (pkt->m_pkthdr.len == pkt->m_len && 3548 M_TRAILINGSPACE(pkt) >= padlen) { 3549 last = pkt; 3550 } else { 3551 /* 3552 * Walk packet chain to find last mbuf. We will either 3553 * pad there, or append a new mbuf and pad it 3554 * (thus perhaps avoiding the bcm5700 dma-min bug). 3555 */ 3556 for (last = pkt; last->m_next != NULL; last = last->m_next) { 3557 continue; /* do nothing */ 3558 } 3559 3560 /* `last' now points to last in chain. */ 3561 if (M_TRAILINGSPACE(last) < padlen) { 3562 /* Allocate new empty mbuf, pad it. Compact later. */ 3563 struct mbuf *n; 3564 MGET(n, M_DONTWAIT, MT_DATA); 3565 if (n == NULL) 3566 return ENOBUFS; 3567 n->m_len = 0; 3568 last->m_next = n; 3569 last = n; 3570 } 3571 } 3572 3573 KDASSERT(!M_READONLY(last)); 3574 KDASSERT(M_TRAILINGSPACE(last) >= padlen); 3575 3576 /* Now zero the pad area, to avoid the bge cksum-assist bug */ 3577 memset(mtod(last, char *) + last->m_len, 0, padlen); 3578 last->m_len += padlen; 3579 pkt->m_pkthdr.len += padlen; 3580 return 0; 3581 } 3582 3583 /* 3584 * Compact outbound packets to avoid bug with DMA segments less than 8 bytes. 3585 */ 3586 static inline int 3587 bge_compact_dma_runt(struct mbuf *pkt) 3588 { 3589 struct mbuf *m, *prev; 3590 int totlen, prevlen; 3591 3592 prev = NULL; 3593 totlen = 0; 3594 prevlen = -1; 3595 3596 for (m = pkt; m != NULL; prev = m,m = m->m_next) { 3597 int mlen = m->m_len; 3598 int shortfall = 8 - mlen ; 3599 3600 totlen += mlen; 3601 if (mlen == 0) { 3602 continue; 3603 } 3604 if (mlen >= 8) 3605 continue; 3606 3607 /* If we get here, mbuf data is too small for DMA engine. 3608 * Try to fix by shuffling data to prev or next in chain. 3609 * If that fails, do a compacting deep-copy of the whole chain. 3610 */ 3611 3612 /* Internal frag. If fits in prev, copy it there. */ 3613 if (prev && M_TRAILINGSPACE(prev) >= m->m_len) { 3614 memcpy(prev->m_data + prev->m_len, m->m_data, mlen); 3615 prev->m_len += mlen; 3616 m->m_len = 0; 3617 /* XXX stitch chain */ 3618 prev->m_next = m_free(m); 3619 m = prev; 3620 continue; 3621 } 3622 else if (m->m_next != NULL && 3623 M_TRAILINGSPACE(m) >= shortfall && 3624 m->m_next->m_len >= (8 + shortfall)) { 3625 /* m is writable and have enough data in next, pull up. */ 3626 3627 memcpy(m->m_data + m->m_len, m->m_next->m_data, 3628 shortfall); 3629 m->m_len += shortfall; 3630 m->m_next->m_len -= shortfall; 3631 m->m_next->m_data += shortfall; 3632 } 3633 else if (m->m_next == NULL || 1) { 3634 /* Got a runt at the very end of the packet. 3635 * borrow data from the tail of the preceding mbuf and 3636 * update its length in-place. (The original data is still 3637 * valid, so we can do this even if prev is not writable.) 3638 */ 3639 3640 /* if we'd make prev a runt, just move all of its data. */ 3641 KASSERT(prev != NULL /*, ("runt but null PREV")*/); 3642 KASSERT(prev->m_len >= 8 /*, ("runt prev")*/); 3643 3644 if ((prev->m_len - shortfall) < 8) 3645 shortfall = prev->m_len; 3646 3647 #ifdef notyet /* just do the safe slow thing for now */ 3648 if (!M_READONLY(m)) { 3649 if (M_LEADINGSPACE(m) < shorfall) { 3650 void *m_dat; 3651 m_dat = (m->m_flags & M_PKTHDR) ? 3652 m->m_pktdat : m->dat; 3653 memmove(m_dat, mtod(m, void*), m->m_len); 3654 m->m_data = m_dat; 3655 } 3656 } else 3657 #endif /* just do the safe slow thing */ 3658 { 3659 struct mbuf * n = NULL; 3660 int newprevlen = prev->m_len - shortfall; 3661 3662 MGET(n, M_NOWAIT, MT_DATA); 3663 if (n == NULL) 3664 return ENOBUFS; 3665 KASSERT(m->m_len + shortfall < MLEN 3666 /*, 3667 ("runt %d +prev %d too big\n", m->m_len, shortfall)*/); 3668 3669 /* first copy the data we're stealing from prev */ 3670 memcpy(n->m_data, prev->m_data + newprevlen, 3671 shortfall); 3672 3673 /* update prev->m_len accordingly */ 3674 prev->m_len -= shortfall; 3675 3676 /* copy data from runt m */ 3677 memcpy(n->m_data + shortfall, m->m_data, 3678 m->m_len); 3679 3680 /* n holds what we stole from prev, plus m */ 3681 n->m_len = shortfall + m->m_len; 3682 3683 /* stitch n into chain and free m */ 3684 n->m_next = m->m_next; 3685 prev->m_next = n; 3686 /* KASSERT(m->m_next == NULL); */ 3687 m->m_next = NULL; 3688 m_free(m); 3689 m = n; /* for continuing loop */ 3690 } 3691 } 3692 prevlen = m->m_len; 3693 } 3694 return 0; 3695 } 3696 3697 /* 3698 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data 3699 * pointers to descriptors. 3700 */ 3701 static int 3702 bge_encap(struct bge_softc *sc, struct mbuf *m_head, uint32_t *txidx) 3703 { 3704 struct bge_tx_bd *f = NULL; 3705 uint32_t frag, cur; 3706 uint16_t csum_flags = 0; 3707 uint16_t txbd_tso_flags = 0; 3708 struct txdmamap_pool_entry *dma; 3709 bus_dmamap_t dmamap; 3710 int i = 0; 3711 struct m_tag *mtag; 3712 int use_tso, maxsegsize, error; 3713 3714 cur = frag = *txidx; 3715 3716 if (m_head->m_pkthdr.csum_flags) { 3717 if (m_head->m_pkthdr.csum_flags & M_CSUM_IPv4) 3718 csum_flags |= BGE_TXBDFLAG_IP_CSUM; 3719 if (m_head->m_pkthdr.csum_flags & (M_CSUM_TCPv4|M_CSUM_UDPv4)) 3720 csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM; 3721 } 3722 3723 /* 3724 * If we were asked to do an outboard checksum, and the NIC 3725 * has the bug where it sometimes adds in the Ethernet padding, 3726 * explicitly pad with zeros so the cksum will be correct either way. 3727 * (For now, do this for all chip versions, until newer 3728 * are confirmed to not require the workaround.) 3729 */ 3730 if ((csum_flags & BGE_TXBDFLAG_TCP_UDP_CSUM) == 0 || 3731 #ifdef notyet 3732 (sc->bge_quirks & BGE_QUIRK_SHORT_CKSUM_BUG) == 0 || 3733 #endif 3734 m_head->m_pkthdr.len >= ETHER_MIN_NOPAD) 3735 goto check_dma_bug; 3736 3737 if (bge_cksum_pad(m_head) != 0) 3738 return ENOBUFS; 3739 3740 check_dma_bug: 3741 if (!(BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX)) 3742 goto doit; 3743 3744 /* 3745 * bcm5700 Revision B silicon cannot handle DMA descriptors with 3746 * less than eight bytes. If we encounter a teeny mbuf 3747 * at the end of a chain, we can pad. Otherwise, copy. 3748 */ 3749 if (bge_compact_dma_runt(m_head) != 0) 3750 return ENOBUFS; 3751 3752 doit: 3753 dma = SLIST_FIRST(&sc->txdma_list); 3754 if (dma == NULL) 3755 return ENOBUFS; 3756 dmamap = dma->dmamap; 3757 3758 /* 3759 * Set up any necessary TSO state before we start packing... 3760 */ 3761 use_tso = (m_head->m_pkthdr.csum_flags & M_CSUM_TSOv4) != 0; 3762 if (!use_tso) { 3763 maxsegsize = 0; 3764 } else { /* TSO setup */ 3765 unsigned mss; 3766 struct ether_header *eh; 3767 unsigned ip_tcp_hlen, iptcp_opt_words, tcp_seg_flags, offset; 3768 struct mbuf * m0 = m_head; 3769 struct ip *ip; 3770 struct tcphdr *th; 3771 int iphl, hlen; 3772 3773 /* 3774 * XXX It would be nice if the mbuf pkthdr had offset 3775 * fields for the protocol headers. 3776 */ 3777 3778 eh = mtod(m0, struct ether_header *); 3779 switch (htons(eh->ether_type)) { 3780 case ETHERTYPE_IP: 3781 offset = ETHER_HDR_LEN; 3782 break; 3783 3784 case ETHERTYPE_VLAN: 3785 offset = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 3786 break; 3787 3788 default: 3789 /* 3790 * Don't support this protocol or encapsulation. 3791 */ 3792 return ENOBUFS; 3793 } 3794 3795 /* 3796 * TCP/IP headers are in the first mbuf; we can do 3797 * this the easy way. 3798 */ 3799 iphl = M_CSUM_DATA_IPv4_IPHL(m0->m_pkthdr.csum_data); 3800 hlen = iphl + offset; 3801 if (__predict_false(m0->m_len < 3802 (hlen + sizeof(struct tcphdr)))) { 3803 3804 aprint_debug_dev(sc->bge_dev, 3805 "TSO: hard case m0->m_len == %d < ip/tcp hlen %zd," 3806 "not handled yet\n", 3807 m0->m_len, hlen+ sizeof(struct tcphdr)); 3808 #ifdef NOTYET 3809 /* 3810 * XXX jonathan (at) NetBSD.org: untested. 3811 * how to force this branch to be taken? 3812 */ 3813 BGE_EVCNT_INCR(&sc->sc_ev_txtsopain); 3814 3815 m_copydata(m0, offset, sizeof(ip), &ip); 3816 m_copydata(m0, hlen, sizeof(th), &th); 3817 3818 ip.ip_len = 0; 3819 3820 m_copyback(m0, hlen + offsetof(struct ip, ip_len), 3821 sizeof(ip.ip_len), &ip.ip_len); 3822 3823 th.th_sum = in_cksum_phdr(ip.ip_src.s_addr, 3824 ip.ip_dst.s_addr, htons(IPPROTO_TCP)); 3825 3826 m_copyback(m0, hlen + offsetof(struct tcphdr, th_sum), 3827 sizeof(th.th_sum), &th.th_sum); 3828 3829 hlen += th.th_off << 2; 3830 iptcp_opt_words = hlen; 3831 #else 3832 /* 3833 * if_wm "hard" case not yet supported, can we not 3834 * mandate it out of existence? 3835 */ 3836 (void) ip; (void)th; (void) ip_tcp_hlen; 3837 3838 return ENOBUFS; 3839 #endif 3840 } else { 3841 ip = (struct ip *) (mtod(m0, char *) + offset); 3842 th = (struct tcphdr *) (mtod(m0, char *) + hlen); 3843 ip_tcp_hlen = iphl + (th->th_off << 2); 3844 3845 /* Total IP/TCP options, in 32-bit words */ 3846 iptcp_opt_words = (ip_tcp_hlen 3847 - sizeof(struct tcphdr) 3848 - sizeof(struct ip)) >> 2; 3849 } 3850 if (BGE_IS_5750_OR_BEYOND(sc)) { 3851 th->th_sum = 0; 3852 csum_flags &= ~(BGE_TXBDFLAG_TCP_UDP_CSUM); 3853 } else { 3854 /* 3855 * XXX jonathan (at) NetBSD.org: 5705 untested. 3856 * Requires TSO firmware patch for 5701/5703/5704. 3857 */ 3858 th->th_sum = in_cksum_phdr(ip->ip_src.s_addr, 3859 ip->ip_dst.s_addr, htons(IPPROTO_TCP)); 3860 } 3861 3862 mss = m_head->m_pkthdr.segsz; 3863 txbd_tso_flags |= 3864 BGE_TXBDFLAG_CPU_PRE_DMA | 3865 BGE_TXBDFLAG_CPU_POST_DMA; 3866 3867 /* 3868 * Our NIC TSO-assist assumes TSO has standard, optionless 3869 * IPv4 and TCP headers, which total 40 bytes. By default, 3870 * the NIC copies 40 bytes of IP/TCP header from the 3871 * supplied header into the IP/TCP header portion of 3872 * each post-TSO-segment. If the supplied packet has IP or 3873 * TCP options, we need to tell the NIC to copy those extra 3874 * bytes into each post-TSO header, in addition to the normal 3875 * 40-byte IP/TCP header (and to leave space accordingly). 3876 * Unfortunately, the driver encoding of option length 3877 * varies across different ASIC families. 3878 */ 3879 tcp_seg_flags = 0; 3880 if (iptcp_opt_words) { 3881 if (BGE_IS_5705_PLUS(sc)) { 3882 tcp_seg_flags = 3883 iptcp_opt_words << 11; 3884 } else { 3885 txbd_tso_flags |= 3886 iptcp_opt_words << 12; 3887 } 3888 } 3889 maxsegsize = mss | tcp_seg_flags; 3890 ip->ip_len = htons(mss + ip_tcp_hlen); 3891 3892 } /* TSO setup */ 3893 3894 /* 3895 * Start packing the mbufs in this chain into 3896 * the fragment pointers. Stop when we run out 3897 * of fragments or hit the end of the mbuf chain. 3898 */ 3899 error = bus_dmamap_load_mbuf(sc->bge_dmatag, dmamap, m_head, 3900 BUS_DMA_NOWAIT); 3901 if (error) 3902 return ENOBUFS; 3903 /* 3904 * Sanity check: avoid coming within 16 descriptors 3905 * of the end of the ring. 3906 */ 3907 if (dmamap->dm_nsegs > (BGE_TX_RING_CNT - sc->bge_txcnt - 16)) { 3908 BGE_TSO_PRINTF(("%s: " 3909 " dmamap_load_mbuf too close to ring wrap\n", 3910 device_xname(sc->bge_dev))); 3911 goto fail_unload; 3912 } 3913 3914 mtag = sc->ethercom.ec_nvlans ? 3915 m_tag_find(m_head, PACKET_TAG_VLAN, NULL) : NULL; 3916 3917 3918 /* Iterate over dmap-map fragments. */ 3919 for (i = 0; i < dmamap->dm_nsegs; i++) { 3920 f = &sc->bge_rdata->bge_tx_ring[frag]; 3921 if (sc->bge_cdata.bge_tx_chain[frag] != NULL) 3922 break; 3923 3924 BGE_HOSTADDR(f->bge_addr, dmamap->dm_segs[i].ds_addr); 3925 f->bge_len = dmamap->dm_segs[i].ds_len; 3926 3927 /* 3928 * For 5751 and follow-ons, for TSO we must turn 3929 * off checksum-assist flag in the tx-descr, and 3930 * supply the ASIC-revision-specific encoding 3931 * of TSO flags and segsize. 3932 */ 3933 if (use_tso) { 3934 if (BGE_IS_5750_OR_BEYOND(sc) || i == 0) { 3935 f->bge_rsvd = maxsegsize; 3936 f->bge_flags = csum_flags | txbd_tso_flags; 3937 } else { 3938 f->bge_rsvd = 0; 3939 f->bge_flags = 3940 (csum_flags | txbd_tso_flags) & 0x0fff; 3941 } 3942 } else { 3943 f->bge_rsvd = 0; 3944 f->bge_flags = csum_flags; 3945 } 3946 3947 if (mtag != NULL) { 3948 f->bge_flags |= BGE_TXBDFLAG_VLAN_TAG; 3949 f->bge_vlan_tag = VLAN_TAG_VALUE(mtag); 3950 } else { 3951 f->bge_vlan_tag = 0; 3952 } 3953 cur = frag; 3954 BGE_INC(frag, BGE_TX_RING_CNT); 3955 } 3956 3957 if (i < dmamap->dm_nsegs) { 3958 BGE_TSO_PRINTF(("%s: reached %d < dm_nsegs %d\n", 3959 device_xname(sc->bge_dev), i, dmamap->dm_nsegs)); 3960 goto fail_unload; 3961 } 3962 3963 bus_dmamap_sync(sc->bge_dmatag, dmamap, 0, dmamap->dm_mapsize, 3964 BUS_DMASYNC_PREWRITE); 3965 3966 if (frag == sc->bge_tx_saved_considx) { 3967 BGE_TSO_PRINTF(("%s: frag %d = wrapped id %d?\n", 3968 device_xname(sc->bge_dev), frag, sc->bge_tx_saved_considx)); 3969 3970 goto fail_unload; 3971 } 3972 3973 sc->bge_rdata->bge_tx_ring[cur].bge_flags |= BGE_TXBDFLAG_END; 3974 sc->bge_cdata.bge_tx_chain[cur] = m_head; 3975 SLIST_REMOVE_HEAD(&sc->txdma_list, link); 3976 sc->txdma[cur] = dma; 3977 sc->bge_txcnt += dmamap->dm_nsegs; 3978 3979 *txidx = frag; 3980 3981 return 0; 3982 3983 fail_unload: 3984 bus_dmamap_unload(sc->bge_dmatag, dmamap); 3985 3986 return ENOBUFS; 3987 } 3988 3989 /* 3990 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 3991 * to the mbuf data regions directly in the transmit descriptors. 3992 */ 3993 static void 3994 bge_start(struct ifnet *ifp) 3995 { 3996 struct bge_softc *sc; 3997 struct mbuf *m_head = NULL; 3998 uint32_t prodidx; 3999 int pkts = 0; 4000 4001 sc = ifp->if_softc; 4002 4003 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 4004 return; 4005 4006 prodidx = sc->bge_tx_prodidx; 4007 4008 while (sc->bge_cdata.bge_tx_chain[prodidx] == NULL) { 4009 IFQ_POLL(&ifp->if_snd, m_head); 4010 if (m_head == NULL) 4011 break; 4012 4013 #if 0 4014 /* 4015 * XXX 4016 * safety overkill. If this is a fragmented packet chain 4017 * with delayed TCP/UDP checksums, then only encapsulate 4018 * it if we have enough descriptors to handle the entire 4019 * chain at once. 4020 * (paranoia -- may not actually be needed) 4021 */ 4022 if (m_head->m_flags & M_FIRSTFRAG && 4023 m_head->m_pkthdr.csum_flags & (CSUM_DELAY_DATA)) { 4024 if ((BGE_TX_RING_CNT - sc->bge_txcnt) < 4025 M_CSUM_DATA_IPv4_OFFSET(m_head->m_pkthdr.csum_data) + 16) { 4026 ifp->if_flags |= IFF_OACTIVE; 4027 break; 4028 } 4029 } 4030 #endif 4031 4032 /* 4033 * Pack the data into the transmit ring. If we 4034 * don't have room, set the OACTIVE flag and wait 4035 * for the NIC to drain the ring. 4036 */ 4037 if (bge_encap(sc, m_head, &prodidx)) { 4038 ifp->if_flags |= IFF_OACTIVE; 4039 break; 4040 } 4041 4042 /* now we are committed to transmit the packet */ 4043 IFQ_DEQUEUE(&ifp->if_snd, m_head); 4044 pkts++; 4045 4046 /* 4047 * If there's a BPF listener, bounce a copy of this frame 4048 * to him. 4049 */ 4050 if (ifp->if_bpf) 4051 bpf_ops->bpf_mtap(ifp->if_bpf, m_head); 4052 } 4053 if (pkts == 0) 4054 return; 4055 4056 /* Transmit */ 4057 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); 4058 /* 5700 b2 errata */ 4059 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX) 4060 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); 4061 4062 sc->bge_tx_prodidx = prodidx; 4063 4064 /* 4065 * Set a timeout in case the chip goes out to lunch. 4066 */ 4067 ifp->if_timer = 5; 4068 } 4069 4070 static int 4071 bge_init(struct ifnet *ifp) 4072 { 4073 struct bge_softc *sc = ifp->if_softc; 4074 const uint16_t *m; 4075 int s, error = 0; 4076 4077 s = splnet(); 4078 4079 ifp = &sc->ethercom.ec_if; 4080 4081 /* Cancel pending I/O and flush buffers. */ 4082 bge_stop(ifp, 0); 4083 bge_reset(sc); 4084 bge_chipinit(sc); 4085 4086 /* 4087 * Init the various state machines, ring 4088 * control blocks and firmware. 4089 */ 4090 error = bge_blockinit(sc); 4091 if (error != 0) { 4092 aprint_error_dev(sc->bge_dev, "initialization error %d\n", 4093 error); 4094 splx(s); 4095 return error; 4096 } 4097 4098 ifp = &sc->ethercom.ec_if; 4099 4100 /* Specify MTU. */ 4101 CSR_WRITE_4(sc, BGE_RX_MTU, ifp->if_mtu + 4102 ETHER_HDR_LEN + ETHER_CRC_LEN + ETHER_VLAN_ENCAP_LEN); 4103 4104 /* Load our MAC address. */ 4105 m = (const uint16_t *)&(CLLADDR(ifp->if_sadl)[0]); 4106 CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0])); 4107 CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, (htons(m[1]) << 16) | htons(m[2])); 4108 4109 /* Enable or disable promiscuous mode as needed. */ 4110 if (ifp->if_flags & IFF_PROMISC) { 4111 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 4112 } else { 4113 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 4114 } 4115 4116 /* Program multicast filter. */ 4117 bge_setmulti(sc); 4118 4119 /* Init RX ring. */ 4120 bge_init_rx_ring_std(sc); 4121 4122 /* 4123 * Workaround for a bug in 5705 ASIC rev A0. Poll the NIC's 4124 * memory to insure that the chip has in fact read the first 4125 * entry of the ring. 4126 */ 4127 if (sc->bge_chipid == BGE_CHIPID_BCM5705_A0) { 4128 uint32_t v, i; 4129 for (i = 0; i < 10; i++) { 4130 DELAY(20); 4131 v = bge_readmem_ind(sc, BGE_STD_RX_RINGS + 8); 4132 if (v == (MCLBYTES - ETHER_ALIGN)) 4133 break; 4134 } 4135 if (i == 10) 4136 aprint_error_dev(sc->bge_dev, 4137 "5705 A0 chip failed to load RX ring\n"); 4138 } 4139 4140 /* Init jumbo RX ring. */ 4141 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 4142 bge_init_rx_ring_jumbo(sc); 4143 4144 /* Init our RX return ring index */ 4145 sc->bge_rx_saved_considx = 0; 4146 4147 /* Init TX ring. */ 4148 bge_init_tx_ring(sc); 4149 4150 /* Turn on transmitter */ 4151 BGE_SETBIT(sc, BGE_TX_MODE, BGE_TXMODE_ENABLE); 4152 4153 /* Turn on receiver */ 4154 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE); 4155 4156 CSR_WRITE_4(sc, BGE_MAX_RX_FRAME_LOWAT, 2); 4157 4158 /* Tell firmware we're alive. */ 4159 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 4160 4161 /* Enable host interrupts. */ 4162 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA); 4163 BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); 4164 bge_writembx(sc, BGE_MBX_IRQ0_LO, 0); 4165 4166 if ((error = bge_ifmedia_upd(ifp)) != 0) 4167 goto out; 4168 4169 ifp->if_flags |= IFF_RUNNING; 4170 ifp->if_flags &= ~IFF_OACTIVE; 4171 4172 callout_reset(&sc->bge_timeout, hz, bge_tick, sc); 4173 4174 out: 4175 splx(s); 4176 4177 return error; 4178 } 4179 4180 /* 4181 * Set media options. 4182 */ 4183 static int 4184 bge_ifmedia_upd(struct ifnet *ifp) 4185 { 4186 struct bge_softc *sc = ifp->if_softc; 4187 struct mii_data *mii = &sc->bge_mii; 4188 struct ifmedia *ifm = &sc->bge_ifmedia; 4189 int rc; 4190 4191 /* If this is a 1000baseX NIC, enable the TBI port. */ 4192 if (sc->bge_flags & BGE_PHY_FIBER_TBI) { 4193 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 4194 return EINVAL; 4195 switch (IFM_SUBTYPE(ifm->ifm_media)) { 4196 case IFM_AUTO: 4197 /* 4198 * The BCM5704 ASIC appears to have a special 4199 * mechanism for programming the autoneg 4200 * advertisement registers in TBI mode. 4201 */ 4202 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) { 4203 uint32_t sgdig; 4204 sgdig = CSR_READ_4(sc, BGE_SGDIG_STS); 4205 if (sgdig & BGE_SGDIGSTS_DONE) { 4206 CSR_WRITE_4(sc, BGE_TX_TBI_AUTONEG, 0); 4207 sgdig = CSR_READ_4(sc, BGE_SGDIG_CFG); 4208 sgdig |= BGE_SGDIGCFG_AUTO | 4209 BGE_SGDIGCFG_PAUSE_CAP | 4210 BGE_SGDIGCFG_ASYM_PAUSE; 4211 CSR_WRITE_4(sc, BGE_SGDIG_CFG, 4212 sgdig | BGE_SGDIGCFG_SEND); 4213 DELAY(5); 4214 CSR_WRITE_4(sc, BGE_SGDIG_CFG, sgdig); 4215 } 4216 } 4217 break; 4218 case IFM_1000_SX: 4219 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 4220 BGE_CLRBIT(sc, BGE_MAC_MODE, 4221 BGE_MACMODE_HALF_DUPLEX); 4222 } else { 4223 BGE_SETBIT(sc, BGE_MAC_MODE, 4224 BGE_MACMODE_HALF_DUPLEX); 4225 } 4226 break; 4227 default: 4228 return EINVAL; 4229 } 4230 /* XXX 802.3x flow control for 1000BASE-SX */ 4231 return 0; 4232 } 4233 4234 BGE_STS_SETBIT(sc, BGE_STS_LINK_EVT); 4235 if ((rc = mii_mediachg(mii)) == ENXIO) 4236 return 0; 4237 4238 /* 4239 * Force an interrupt so that we will call bge_link_upd 4240 * if needed and clear any pending link state attention. 4241 * Without this we are not getting any further interrupts 4242 * for link state changes and thus will not UP the link and 4243 * not be able to send in bge_start. The only way to get 4244 * things working was to receive a packet and get a RX intr. 4245 */ 4246 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 4247 sc->bge_flags & BGE_IS_5788) 4248 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET); 4249 else 4250 BGE_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW); 4251 4252 return rc; 4253 } 4254 4255 /* 4256 * Report current media status. 4257 */ 4258 static void 4259 bge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 4260 { 4261 struct bge_softc *sc = ifp->if_softc; 4262 struct mii_data *mii = &sc->bge_mii; 4263 4264 if (sc->bge_flags & BGE_PHY_FIBER_TBI) { 4265 ifmr->ifm_status = IFM_AVALID; 4266 ifmr->ifm_active = IFM_ETHER; 4267 if (CSR_READ_4(sc, BGE_MAC_STS) & 4268 BGE_MACSTAT_TBI_PCS_SYNCHED) 4269 ifmr->ifm_status |= IFM_ACTIVE; 4270 ifmr->ifm_active |= IFM_1000_SX; 4271 if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX) 4272 ifmr->ifm_active |= IFM_HDX; 4273 else 4274 ifmr->ifm_active |= IFM_FDX; 4275 return; 4276 } 4277 4278 mii_pollstat(mii); 4279 ifmr->ifm_status = mii->mii_media_status; 4280 ifmr->ifm_active = (mii->mii_media_active & ~IFM_ETH_FMASK) | 4281 sc->bge_flowflags; 4282 } 4283 4284 static int 4285 bge_ioctl(struct ifnet *ifp, u_long command, void *data) 4286 { 4287 struct bge_softc *sc = ifp->if_softc; 4288 struct ifreq *ifr = (struct ifreq *) data; 4289 int s, error = 0; 4290 struct mii_data *mii; 4291 4292 s = splnet(); 4293 4294 switch (command) { 4295 case SIOCSIFFLAGS: 4296 if ((error = ifioctl_common(ifp, command, data)) != 0) 4297 break; 4298 if (ifp->if_flags & IFF_UP) { 4299 /* 4300 * If only the state of the PROMISC flag changed, 4301 * then just use the 'set promisc mode' command 4302 * instead of reinitializing the entire NIC. Doing 4303 * a full re-init means reloading the firmware and 4304 * waiting for it to start up, which may take a 4305 * second or two. 4306 */ 4307 if (ifp->if_flags & IFF_RUNNING && 4308 ifp->if_flags & IFF_PROMISC && 4309 !(sc->bge_if_flags & IFF_PROMISC)) { 4310 BGE_SETBIT(sc, BGE_RX_MODE, 4311 BGE_RXMODE_RX_PROMISC); 4312 } else if (ifp->if_flags & IFF_RUNNING && 4313 !(ifp->if_flags & IFF_PROMISC) && 4314 sc->bge_if_flags & IFF_PROMISC) { 4315 BGE_CLRBIT(sc, BGE_RX_MODE, 4316 BGE_RXMODE_RX_PROMISC); 4317 } else if (!(sc->bge_if_flags & IFF_UP)) 4318 bge_init(ifp); 4319 } else { 4320 if (ifp->if_flags & IFF_RUNNING) 4321 bge_stop(ifp, 1); 4322 } 4323 sc->bge_if_flags = ifp->if_flags; 4324 error = 0; 4325 break; 4326 case SIOCSIFMEDIA: 4327 /* XXX Flow control is not supported for 1000BASE-SX */ 4328 if (sc->bge_flags & BGE_PHY_FIBER_TBI) { 4329 ifr->ifr_media &= ~IFM_ETH_FMASK; 4330 sc->bge_flowflags = 0; 4331 } 4332 4333 /* Flow control requires full-duplex mode. */ 4334 if (IFM_SUBTYPE(ifr->ifr_media) == IFM_AUTO || 4335 (ifr->ifr_media & IFM_FDX) == 0) { 4336 ifr->ifr_media &= ~IFM_ETH_FMASK; 4337 } 4338 if (IFM_SUBTYPE(ifr->ifr_media) != IFM_AUTO) { 4339 if ((ifr->ifr_media & IFM_ETH_FMASK) == IFM_FLOW) { 4340 /* We can do both TXPAUSE and RXPAUSE. */ 4341 ifr->ifr_media |= 4342 IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE; 4343 } 4344 sc->bge_flowflags = ifr->ifr_media & IFM_ETH_FMASK; 4345 } 4346 /* FALLTHROUGH */ 4347 case SIOCGIFMEDIA: 4348 if (sc->bge_flags & BGE_PHY_FIBER_TBI) { 4349 error = ifmedia_ioctl(ifp, ifr, &sc->bge_ifmedia, 4350 command); 4351 } else { 4352 mii = &sc->bge_mii; 4353 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, 4354 command); 4355 } 4356 break; 4357 default: 4358 if ((error = ether_ioctl(ifp, command, data)) != ENETRESET) 4359 break; 4360 4361 error = 0; 4362 4363 if (command != SIOCADDMULTI && command != SIOCDELMULTI) 4364 ; 4365 else if (ifp->if_flags & IFF_RUNNING) 4366 bge_setmulti(sc); 4367 break; 4368 } 4369 4370 splx(s); 4371 4372 return error; 4373 } 4374 4375 static void 4376 bge_watchdog(struct ifnet *ifp) 4377 { 4378 struct bge_softc *sc; 4379 4380 sc = ifp->if_softc; 4381 4382 aprint_error_dev(sc->bge_dev, "watchdog timeout -- resetting\n"); 4383 4384 ifp->if_flags &= ~IFF_RUNNING; 4385 bge_init(ifp); 4386 4387 ifp->if_oerrors++; 4388 } 4389 4390 static void 4391 bge_stop_block(struct bge_softc *sc, bus_addr_t reg, uint32_t bit) 4392 { 4393 int i; 4394 4395 BGE_CLRBIT(sc, reg, bit); 4396 4397 for (i = 0; i < BGE_TIMEOUT; i++) { 4398 if ((CSR_READ_4(sc, reg) & bit) == 0) 4399 return; 4400 delay(100); 4401 if (sc->bge_flags & BGE_PCIE) 4402 DELAY(1000); 4403 } 4404 4405 /* 4406 * Doesn't print only when the register is BGE_SRS_MODE. It occurs 4407 * on some environment (and once after boot?) 4408 */ 4409 if (reg != BGE_SRS_MODE) 4410 aprint_error_dev(sc->bge_dev, 4411 "block failed to stop: reg 0x%lx, bit 0x%08x\n", 4412 (u_long)reg, bit); 4413 } 4414 4415 /* 4416 * Stop the adapter and free any mbufs allocated to the 4417 * RX and TX lists. 4418 */ 4419 static void 4420 bge_stop(struct ifnet *ifp, int disable) 4421 { 4422 struct bge_softc *sc = ifp->if_softc; 4423 4424 callout_stop(&sc->bge_timeout); 4425 4426 /* 4427 * Disable all of the receiver blocks 4428 */ 4429 bge_stop_block(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE); 4430 bge_stop_block(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 4431 bge_stop_block(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 4432 if (BGE_IS_5700_FAMILY(sc)) 4433 bge_stop_block(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 4434 bge_stop_block(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE); 4435 bge_stop_block(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 4436 bge_stop_block(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE); 4437 4438 /* 4439 * Disable all of the transmit blocks 4440 */ 4441 bge_stop_block(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 4442 bge_stop_block(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 4443 bge_stop_block(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 4444 bge_stop_block(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE); 4445 bge_stop_block(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE); 4446 if (BGE_IS_5700_FAMILY(sc)) 4447 bge_stop_block(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 4448 bge_stop_block(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 4449 4450 /* 4451 * Shut down all of the memory managers and related 4452 * state machines. 4453 */ 4454 bge_stop_block(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE); 4455 bge_stop_block(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE); 4456 if (BGE_IS_5700_FAMILY(sc)) 4457 bge_stop_block(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 4458 4459 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 4460 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 4461 4462 if (BGE_IS_5700_FAMILY(sc)) { 4463 bge_stop_block(sc, BGE_BMAN_MODE, BGE_BMANMODE_ENABLE); 4464 bge_stop_block(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 4465 } 4466 4467 /* Disable host interrupts. */ 4468 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); 4469 bge_writembx(sc, BGE_MBX_IRQ0_LO, 1); 4470 4471 /* 4472 * Tell firmware we're shutting down. 4473 */ 4474 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 4475 4476 /* Free the RX lists. */ 4477 bge_free_rx_ring_std(sc); 4478 4479 /* Free jumbo RX list. */ 4480 if (BGE_IS_JUMBO_CAPABLE(sc)) 4481 bge_free_rx_ring_jumbo(sc); 4482 4483 /* Free TX buffers. */ 4484 bge_free_tx_ring(sc); 4485 4486 /* 4487 * Isolate/power down the PHY. 4488 */ 4489 if (!(sc->bge_flags & BGE_PHY_FIBER_TBI)) 4490 mii_down(&sc->bge_mii); 4491 4492 sc->bge_tx_saved_considx = BGE_TXCONS_UNSET; 4493 4494 /* Clear MAC's link state (PHY may still have link UP). */ 4495 BGE_STS_CLRBIT(sc, BGE_STS_LINK); 4496 4497 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 4498 } 4499 4500 static void 4501 bge_link_upd(struct bge_softc *sc) 4502 { 4503 struct ifnet *ifp = &sc->ethercom.ec_if; 4504 struct mii_data *mii = &sc->bge_mii; 4505 uint32_t status; 4506 int link; 4507 4508 /* Clear 'pending link event' flag */ 4509 BGE_STS_CLRBIT(sc, BGE_STS_LINK_EVT); 4510 4511 /* 4512 * Process link state changes. 4513 * Grrr. The link status word in the status block does 4514 * not work correctly on the BCM5700 rev AX and BX chips, 4515 * according to all available information. Hence, we have 4516 * to enable MII interrupts in order to properly obtain 4517 * async link changes. Unfortunately, this also means that 4518 * we have to read the MAC status register to detect link 4519 * changes, thereby adding an additional register access to 4520 * the interrupt handler. 4521 */ 4522 4523 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700) { 4524 status = CSR_READ_4(sc, BGE_MAC_STS); 4525 if (status & BGE_MACSTAT_MI_INTERRUPT) { 4526 mii_pollstat(mii); 4527 4528 if (!BGE_STS_BIT(sc, BGE_STS_LINK) && 4529 mii->mii_media_status & IFM_ACTIVE && 4530 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) 4531 BGE_STS_SETBIT(sc, BGE_STS_LINK); 4532 else if (BGE_STS_BIT(sc, BGE_STS_LINK) && 4533 (!(mii->mii_media_status & IFM_ACTIVE) || 4534 IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) 4535 BGE_STS_CLRBIT(sc, BGE_STS_LINK); 4536 4537 /* Clear the interrupt */ 4538 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, 4539 BGE_EVTENB_MI_INTERRUPT); 4540 bge_miibus_readreg(sc->bge_dev, 1, BRGPHY_MII_ISR); 4541 bge_miibus_writereg(sc->bge_dev, 1, BRGPHY_MII_IMR, 4542 BRGPHY_INTRS); 4543 } 4544 return; 4545 } 4546 4547 if (sc->bge_flags & BGE_PHY_FIBER_TBI) { 4548 status = CSR_READ_4(sc, BGE_MAC_STS); 4549 if (status & BGE_MACSTAT_TBI_PCS_SYNCHED) { 4550 if (!BGE_STS_BIT(sc, BGE_STS_LINK)) { 4551 BGE_STS_SETBIT(sc, BGE_STS_LINK); 4552 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) 4553 BGE_CLRBIT(sc, BGE_MAC_MODE, 4554 BGE_MACMODE_TBI_SEND_CFGS); 4555 CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF); 4556 if_link_state_change(ifp, LINK_STATE_UP); 4557 } 4558 } else if (BGE_STS_BIT(sc, BGE_STS_LINK)) { 4559 BGE_STS_CLRBIT(sc, BGE_STS_LINK); 4560 if_link_state_change(ifp, LINK_STATE_DOWN); 4561 } 4562 /* 4563 * Discard link events for MII/GMII cards if MI auto-polling disabled. 4564 * This should not happen since mii callouts are locked now, but 4565 * we keep this check for debug. 4566 */ 4567 } else if (BGE_STS_BIT(sc, BGE_STS_AUTOPOLL)) { 4568 /* 4569 * Some broken BCM chips have BGE_STATFLAG_LINKSTATE_CHANGED 4570 * bit in status word always set. Workaround this bug by 4571 * reading PHY link status directly. 4572 */ 4573 link = (CSR_READ_4(sc, BGE_MI_STS) & BGE_MISTS_LINK)? 4574 BGE_STS_LINK : 0; 4575 4576 if (BGE_STS_BIT(sc, BGE_STS_LINK) != link) { 4577 mii_pollstat(mii); 4578 4579 if (!BGE_STS_BIT(sc, BGE_STS_LINK) && 4580 mii->mii_media_status & IFM_ACTIVE && 4581 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) 4582 BGE_STS_SETBIT(sc, BGE_STS_LINK); 4583 else if (BGE_STS_BIT(sc, BGE_STS_LINK) && 4584 (!(mii->mii_media_status & IFM_ACTIVE) || 4585 IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) 4586 BGE_STS_CLRBIT(sc, BGE_STS_LINK); 4587 } 4588 } 4589 4590 /* Clear the attention */ 4591 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED| 4592 BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE| 4593 BGE_MACSTAT_LINK_CHANGED); 4594 } 4595 4596 static int 4597 sysctl_bge_verify(SYSCTLFN_ARGS) 4598 { 4599 int error, t; 4600 struct sysctlnode node; 4601 4602 node = *rnode; 4603 t = *(int*)rnode->sysctl_data; 4604 node.sysctl_data = &t; 4605 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 4606 if (error || newp == NULL) 4607 return error; 4608 4609 #if 0 4610 DPRINTF2(("%s: t = %d, nodenum = %d, rnodenum = %d\n", __func__, t, 4611 node.sysctl_num, rnode->sysctl_num)); 4612 #endif 4613 4614 if (node.sysctl_num == bge_rxthresh_nodenum) { 4615 if (t < 0 || t >= NBGE_RX_THRESH) 4616 return EINVAL; 4617 bge_update_all_threshes(t); 4618 } else 4619 return EINVAL; 4620 4621 *(int*)rnode->sysctl_data = t; 4622 4623 return 0; 4624 } 4625 4626 /* 4627 * Set up sysctl(3) MIB, hw.bge.*. 4628 * 4629 * TBD condition SYSCTL_PERMANENT on being an LKM or not 4630 */ 4631 SYSCTL_SETUP(sysctl_bge, "sysctl bge subtree setup") 4632 { 4633 int rc, bge_root_num; 4634 const struct sysctlnode *node; 4635 4636 if ((rc = sysctl_createv(clog, 0, NULL, NULL, 4637 CTLFLAG_PERMANENT, CTLTYPE_NODE, "hw", NULL, 4638 NULL, 0, NULL, 0, CTL_HW, CTL_EOL)) != 0) { 4639 goto err; 4640 } 4641 4642 if ((rc = sysctl_createv(clog, 0, NULL, &node, 4643 CTLFLAG_PERMANENT, CTLTYPE_NODE, "bge", 4644 SYSCTL_DESCR("BGE interface controls"), 4645 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL)) != 0) { 4646 goto err; 4647 } 4648 4649 bge_root_num = node->sysctl_num; 4650 4651 /* BGE Rx interrupt mitigation level */ 4652 if ((rc = sysctl_createv(clog, 0, NULL, &node, 4653 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, 4654 CTLTYPE_INT, "rx_lvl", 4655 SYSCTL_DESCR("BGE receive interrupt mitigation level"), 4656 sysctl_bge_verify, 0, 4657 &bge_rx_thresh_lvl, 4658 0, CTL_HW, bge_root_num, CTL_CREATE, 4659 CTL_EOL)) != 0) { 4660 goto err; 4661 } 4662 4663 bge_rxthresh_nodenum = node->sysctl_num; 4664 4665 return; 4666 4667 err: 4668 aprint_error("%s: sysctl_createv failed (rc = %d)\n", __func__, rc); 4669 } 4670 4671 #ifdef BGE_DEBUG 4672 void 4673 bge_debug_info(struct bge_softc *sc) 4674 { 4675 4676 printf("Hardware Flags:\n"); 4677 if (BGE_IS_5755_PLUS(sc)) 4678 printf(" - 5755 Plus\n"); 4679 if (BGE_IS_5750_OR_BEYOND(sc)) 4680 printf(" - 5750 Plus\n"); 4681 if (BGE_IS_5705_PLUS(sc)) 4682 printf(" - 5705 Plus\n"); 4683 if (BGE_IS_5714_FAMILY(sc)) 4684 printf(" - 5714 Family\n"); 4685 if (BGE_IS_5700_FAMILY(sc)) 4686 printf(" - 5700 Family\n"); 4687 if (sc->bge_flags & BGE_IS_5788) 4688 printf(" - 5788\n"); 4689 if (sc->bge_flags & BGE_JUMBO_CAPABLE) 4690 printf(" - Supports Jumbo Frames\n"); 4691 if (sc->bge_flags & BGE_NO_EEPROM) 4692 printf(" - No EEPROM\n"); 4693 if (sc->bge_flags & BGE_PCIX) 4694 printf(" - PCI-X Bus\n"); 4695 if (sc->bge_flags & BGE_PCIE) 4696 printf(" - PCI Express Bus\n"); 4697 if (sc->bge_flags & BGE_NO_3LED) 4698 printf(" - No 3 LEDs\n"); 4699 if (sc->bge_flags & BGE_RX_ALIGNBUG) 4700 printf(" - RX Alignment Bug\n"); 4701 if (sc->bge_flags & BGE_TSO) 4702 printf(" - TSO\n"); 4703 } 4704 #endif /* BGE_DEBUG */ 4705 4706 static int 4707 bge_get_eaddr_fw(struct bge_softc *sc, uint8_t ether_addr[]) 4708 { 4709 prop_dictionary_t dict; 4710 prop_data_t ea; 4711 4712 if ((sc->bge_flags & BGE_NO_EEPROM) == 0) 4713 return 1; 4714 4715 dict = device_properties(sc->bge_dev); 4716 ea = prop_dictionary_get(dict, "mac-address"); 4717 if (ea != NULL) { 4718 KASSERT(prop_object_type(ea) == PROP_TYPE_DATA); 4719 KASSERT(prop_data_size(ea) == ETHER_ADDR_LEN); 4720 memcpy(ether_addr, prop_data_data_nocopy(ea), ETHER_ADDR_LEN); 4721 return 0; 4722 } 4723 4724 return 1; 4725 } 4726 4727 static int 4728 bge_get_eaddr_mem(struct bge_softc *sc, uint8_t ether_addr[]) 4729 { 4730 uint32_t mac_addr; 4731 4732 mac_addr = bge_readmem_ind(sc, 0x0c14); 4733 if ((mac_addr >> 16) == 0x484b) { 4734 ether_addr[0] = (uint8_t)(mac_addr >> 8); 4735 ether_addr[1] = (uint8_t)mac_addr; 4736 mac_addr = bge_readmem_ind(sc, 0x0c18); 4737 ether_addr[2] = (uint8_t)(mac_addr >> 24); 4738 ether_addr[3] = (uint8_t)(mac_addr >> 16); 4739 ether_addr[4] = (uint8_t)(mac_addr >> 8); 4740 ether_addr[5] = (uint8_t)mac_addr; 4741 return 0; 4742 } 4743 return 1; 4744 } 4745 4746 static int 4747 bge_get_eaddr_nvram(struct bge_softc *sc, uint8_t ether_addr[]) 4748 { 4749 int mac_offset = BGE_EE_MAC_OFFSET; 4750 4751 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 4752 mac_offset = BGE_EE_MAC_OFFSET_5906; 4753 } 4754 4755 return (bge_read_nvram(sc, ether_addr, mac_offset + 2, 4756 ETHER_ADDR_LEN)); 4757 } 4758 4759 static int 4760 bge_get_eaddr_eeprom(struct bge_softc *sc, uint8_t ether_addr[]) 4761 { 4762 4763 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 4764 return 1; 4765 4766 return (bge_read_eeprom(sc, ether_addr, BGE_EE_MAC_OFFSET + 2, 4767 ETHER_ADDR_LEN)); 4768 } 4769 4770 static int 4771 bge_get_eaddr(struct bge_softc *sc, uint8_t eaddr[]) 4772 { 4773 static const bge_eaddr_fcn_t bge_eaddr_funcs[] = { 4774 /* NOTE: Order is critical */ 4775 bge_get_eaddr_fw, 4776 bge_get_eaddr_mem, 4777 bge_get_eaddr_nvram, 4778 bge_get_eaddr_eeprom, 4779 NULL 4780 }; 4781 const bge_eaddr_fcn_t *func; 4782 4783 for (func = bge_eaddr_funcs; *func != NULL; ++func) { 4784 if ((*func)(sc, eaddr) == 0) 4785 break; 4786 } 4787 return (*func == NULL ? ENXIO : 0); 4788 } 4789
Indexes created Tue Sep 23 07:09:52 GMT 2025