if_bge.c revision 1.176
1 /* $NetBSD: if_bge.c,v 1.176 2010/01/25 10:25:30 martin Exp $ */ 2 3 /* 4 * Copyright (c) 2001 Wind River Systems 5 * Copyright (c) 1997, 1998, 1999, 2001 6 * Bill Paul <wpaul (at) windriver.com>. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Bill Paul. 19 * 4. Neither the name of the author nor the names of any co-contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 33 * THE POSSIBILITY OF SUCH DAMAGE. 34 * 35 * $FreeBSD: if_bge.c,v 1.13 2002/04/04 06:01:31 wpaul Exp $ 36 */ 37 38 /* 39 * Broadcom BCM570x family gigabit ethernet driver for NetBSD. 40 * 41 * NetBSD version by: 42 * 43 * Frank van der Linden <fvdl (at) wasabisystems.com> 44 * Jason Thorpe <thorpej (at) wasabisystems.com> 45 * Jonathan Stone <jonathan (at) dsg.stanford.edu> 46 * 47 * Originally written for FreeBSD by Bill Paul <wpaul (at) windriver.com> 48 * Senior Engineer, Wind River Systems 49 */ 50 51 /* 52 * The Broadcom BCM5700 is based on technology originally developed by 53 * Alteon Networks as part of the Tigon I and Tigon II gigabit ethernet 54 * MAC chips. The BCM5700, sometimes refered to as the Tigon III, has 55 * two on-board MIPS R4000 CPUs and can have as much as 16MB of external 56 * SSRAM. The BCM5700 supports TCP, UDP and IP checksum offload, jumbo 57 * frames, highly configurable RX filtering, and 16 RX and TX queues 58 * (which, along with RX filter rules, can be used for QOS applications). 59 * Other features, such as TCP segmentation, may be available as part 60 * of value-added firmware updates. Unlike the Tigon I and Tigon II, 61 * firmware images can be stored in hardware and need not be compiled 62 * into the driver. 63 * 64 * The BCM5700 supports the PCI v2.2 and PCI-X v1.0 standards, and will 65 * function in a 32-bit/64-bit 33/66MHz bus, or a 64-bit/133MHz bus. 66 * 67 * The BCM5701 is a single-chip solution incorporating both the BCM5700 68 * MAC and a BCM5401 10/100/1000 PHY. Unlike the BCM5700, the BCM5701 69 * does not support external SSRAM. 70 * 71 * Broadcom also produces a variation of the BCM5700 under the "Altima" 72 * brand name, which is functionally similar but lacks PCI-X support. 73 * 74 * Without external SSRAM, you can only have at most 4 TX rings, 75 * and the use of the mini RX ring is disabled. This seems to imply 76 * that these features are simply not available on the BCM5701. As a 77 * result, this driver does not implement any support for the mini RX 78 * ring. 79 */ 80 81 #include <sys/cdefs.h> 82 __KERNEL_RCSID(0, "$NetBSD: if_bge.c,v 1.176 2010/01/25 10:25:30 martin Exp $"); 83 84 #include "vlan.h" 85 #include "rnd.h" 86 87 #include <sys/param.h> 88 #include <sys/systm.h> 89 #include <sys/callout.h> 90 #include <sys/sockio.h> 91 #include <sys/mbuf.h> 92 #include <sys/malloc.h> 93 #include <sys/kernel.h> 94 #include <sys/device.h> 95 #include <sys/socket.h> 96 #include <sys/sysctl.h> 97 98 #include <net/if.h> 99 #include <net/if_dl.h> 100 #include <net/if_media.h> 101 #include <net/if_ether.h> 102 103 #if NRND > 0 104 #include <sys/rnd.h> 105 #endif 106 107 #ifdef INET 108 #include <netinet/in.h> 109 #include <netinet/in_systm.h> 110 #include <netinet/in_var.h> 111 #include <netinet/ip.h> 112 #endif 113 114 /* Headers for TCP Segmentation Offload (TSO) */ 115 #include <netinet/in_systm.h> /* n_time for <netinet/ip.h>... */ 116 #include <netinet/in.h> /* ip_{src,dst}, for <netinet/ip.h> */ 117 #include <netinet/ip.h> /* for struct ip */ 118 #include <netinet/tcp.h> /* for struct tcphdr */ 119 120 121 #include <net/bpf.h> 122 123 #include <dev/pci/pcireg.h> 124 #include <dev/pci/pcivar.h> 125 #include <dev/pci/pcidevs.h> 126 127 #include <dev/mii/mii.h> 128 #include <dev/mii/miivar.h> 129 #include <dev/mii/miidevs.h> 130 #include <dev/mii/brgphyreg.h> 131 132 #include <dev/pci/if_bgereg.h> 133 #include <dev/pci/if_bgevar.h> 134 135 #include <uvm/uvm_extern.h> 136 #include <prop/proplib.h> 137 138 #define ETHER_MIN_NOPAD (ETHER_MIN_LEN - ETHER_CRC_LEN) /* i.e., 60 */ 139 140 141 /* 142 * Tunable thresholds for rx-side bge interrupt mitigation. 143 */ 144 145 /* 146 * The pairs of values below were obtained from empirical measurement 147 * on bcm5700 rev B2; they ar designed to give roughly 1 receive 148 * interrupt for every N packets received, where N is, approximately, 149 * the second value (rx_max_bds) in each pair. The values are chosen 150 * such that moving from one pair to the succeeding pair was observed 151 * to roughly halve interrupt rate under sustained input packet load. 152 * The values were empirically chosen to avoid overflowing internal 153 * limits on the bcm5700: inreasing rx_ticks much beyond 600 154 * results in internal wrapping and higher interrupt rates. 155 * The limit of 46 frames was chosen to match NFS workloads. 156 * 157 * These values also work well on bcm5701, bcm5704C, and (less 158 * tested) bcm5703. On other chipsets, (including the Altima chip 159 * family), the larger values may overflow internal chip limits, 160 * leading to increasing interrupt rates rather than lower interrupt 161 * rates. 162 * 163 * Applications using heavy interrupt mitigation (interrupting every 164 * 32 or 46 frames) in both directions may need to increase the TCP 165 * windowsize to above 131072 bytes (e.g., to 199608 bytes) to sustain 166 * full link bandwidth, due to ACKs and window updates lingering 167 * in the RX queue during the 30-to-40-frame interrupt-mitigation window. 168 */ 169 static const struct bge_load_rx_thresh { 170 int rx_ticks; 171 int rx_max_bds; } 172 bge_rx_threshes[] = { 173 { 32, 2 }, 174 { 50, 4 }, 175 { 100, 8 }, 176 { 192, 16 }, 177 { 416, 32 }, 178 { 598, 46 } 179 }; 180 #define NBGE_RX_THRESH (sizeof(bge_rx_threshes) / sizeof(bge_rx_threshes[0])) 181 182 /* XXX patchable; should be sysctl'able */ 183 static int bge_auto_thresh = 1; 184 static int bge_rx_thresh_lvl; 185 186 static int bge_rxthresh_nodenum; 187 188 typedef int (*bge_eaddr_fcn_t)(struct bge_softc *, uint8_t[]); 189 190 static int bge_probe(device_t, cfdata_t, void *); 191 static void bge_attach(device_t, device_t, void *); 192 static void bge_release_resources(struct bge_softc *); 193 static void bge_txeof(struct bge_softc *); 194 static void bge_rxeof(struct bge_softc *); 195 196 static int bge_get_eaddr_fw(struct bge_softc *, uint8_t[]); 197 static int bge_get_eaddr_mem(struct bge_softc *, uint8_t[]); 198 static int bge_get_eaddr_nvram(struct bge_softc *, uint8_t[]); 199 static int bge_get_eaddr_eeprom(struct bge_softc *, uint8_t[]); 200 static int bge_get_eaddr(struct bge_softc *, uint8_t[]); 201 202 static void bge_tick(void *); 203 static void bge_stats_update(struct bge_softc *); 204 static void bge_stats_update_regs(struct bge_softc *); 205 static int bge_encap(struct bge_softc *, struct mbuf *, uint32_t *); 206 207 static int bge_intr(void *); 208 static void bge_start(struct ifnet *); 209 static int bge_ioctl(struct ifnet *, u_long, void *); 210 static int bge_init(struct ifnet *); 211 static void bge_stop(struct ifnet *, int); 212 static void bge_watchdog(struct ifnet *); 213 static int bge_ifmedia_upd(struct ifnet *); 214 static void bge_ifmedia_sts(struct ifnet *, struct ifmediareq *); 215 216 static void bge_setmulti(struct bge_softc *); 217 218 static void bge_handle_events(struct bge_softc *); 219 static int bge_alloc_jumbo_mem(struct bge_softc *); 220 #if 0 /* XXX */ 221 static void bge_free_jumbo_mem(struct bge_softc *); 222 #endif 223 static void *bge_jalloc(struct bge_softc *); 224 static void bge_jfree(struct mbuf *, void *, size_t, void *); 225 static int bge_newbuf_std(struct bge_softc *, int, struct mbuf *, 226 bus_dmamap_t); 227 static int bge_newbuf_jumbo(struct bge_softc *, int, struct mbuf *); 228 static int bge_init_rx_ring_std(struct bge_softc *); 229 static void bge_free_rx_ring_std(struct bge_softc *); 230 static int bge_init_rx_ring_jumbo(struct bge_softc *); 231 static void bge_free_rx_ring_jumbo(struct bge_softc *); 232 static void bge_free_tx_ring(struct bge_softc *); 233 static int bge_init_tx_ring(struct bge_softc *); 234 235 static int bge_chipinit(struct bge_softc *); 236 static int bge_blockinit(struct bge_softc *); 237 static int bge_setpowerstate(struct bge_softc *, int); 238 239 static void bge_reset(struct bge_softc *); 240 static void bge_link_upd(struct bge_softc *); 241 242 #ifdef BGE_DEBUG 243 #define DPRINTF(x) if (bgedebug) printf x 244 #define DPRINTFN(n,x) if (bgedebug >= (n)) printf x 245 #define BGE_TSO_PRINTF(x) do { if (bge_tso_debug) printf x ;} while (0) 246 int bgedebug = 0; 247 int bge_tso_debug = 0; 248 void bge_debug_info(struct bge_softc *); 249 #else 250 #define DPRINTF(x) 251 #define DPRINTFN(n,x) 252 #define BGE_TSO_PRINTF(x) 253 #endif 254 255 #ifdef BGE_EVENT_COUNTERS 256 #define BGE_EVCNT_INCR(ev) (ev).ev_count++ 257 #define BGE_EVCNT_ADD(ev, val) (ev).ev_count += (val) 258 #define BGE_EVCNT_UPD(ev, val) (ev).ev_count = (val) 259 #else 260 #define BGE_EVCNT_INCR(ev) /* nothing */ 261 #define BGE_EVCNT_ADD(ev, val) /* nothing */ 262 #define BGE_EVCNT_UPD(ev, val) /* nothing */ 263 #endif 264 265 static const struct bge_product { 266 pci_vendor_id_t bp_vendor; 267 pci_product_id_t bp_product; 268 const char *bp_name; 269 } bge_products[] = { 270 /* 271 * The BCM5700 documentation seems to indicate that the hardware 272 * still has the Alteon vendor ID burned into it, though it 273 * should always be overridden by the value in the EEPROM. We'll 274 * check for it anyway. 275 */ 276 { PCI_VENDOR_ALTEON, 277 PCI_PRODUCT_ALTEON_BCM5700, 278 "Broadcom BCM5700 Gigabit Ethernet", 279 }, 280 { PCI_VENDOR_ALTEON, 281 PCI_PRODUCT_ALTEON_BCM5701, 282 "Broadcom BCM5701 Gigabit Ethernet", 283 }, 284 { PCI_VENDOR_ALTIMA, 285 PCI_PRODUCT_ALTIMA_AC1000, 286 "Altima AC1000 Gigabit Ethernet", 287 }, 288 { PCI_VENDOR_ALTIMA, 289 PCI_PRODUCT_ALTIMA_AC1001, 290 "Altima AC1001 Gigabit Ethernet", 291 }, 292 { PCI_VENDOR_ALTIMA, 293 PCI_PRODUCT_ALTIMA_AC9100, 294 "Altima AC9100 Gigabit Ethernet", 295 }, 296 { PCI_VENDOR_BROADCOM, 297 PCI_PRODUCT_BROADCOM_BCM5700, 298 "Broadcom BCM5700 Gigabit Ethernet", 299 }, 300 { PCI_VENDOR_BROADCOM, 301 PCI_PRODUCT_BROADCOM_BCM5701, 302 "Broadcom BCM5701 Gigabit Ethernet", 303 }, 304 { PCI_VENDOR_BROADCOM, 305 PCI_PRODUCT_BROADCOM_BCM5702, 306 "Broadcom BCM5702 Gigabit Ethernet", 307 }, 308 { PCI_VENDOR_BROADCOM, 309 PCI_PRODUCT_BROADCOM_BCM5702X, 310 "Broadcom BCM5702X Gigabit Ethernet" }, 311 { PCI_VENDOR_BROADCOM, 312 PCI_PRODUCT_BROADCOM_BCM5703, 313 "Broadcom BCM5703 Gigabit Ethernet", 314 }, 315 { PCI_VENDOR_BROADCOM, 316 PCI_PRODUCT_BROADCOM_BCM5703X, 317 "Broadcom BCM5703X Gigabit Ethernet", 318 }, 319 { PCI_VENDOR_BROADCOM, 320 PCI_PRODUCT_BROADCOM_BCM5703_ALT, 321 "Broadcom BCM5703 Gigabit Ethernet", 322 }, 323 { PCI_VENDOR_BROADCOM, 324 PCI_PRODUCT_BROADCOM_BCM5704C, 325 "Broadcom BCM5704C Dual Gigabit Ethernet", 326 }, 327 { PCI_VENDOR_BROADCOM, 328 PCI_PRODUCT_BROADCOM_BCM5704S, 329 "Broadcom BCM5704S Dual Gigabit Ethernet", 330 }, 331 { PCI_VENDOR_BROADCOM, 332 PCI_PRODUCT_BROADCOM_BCM5705, 333 "Broadcom BCM5705 Gigabit Ethernet", 334 }, 335 { PCI_VENDOR_BROADCOM, 336 PCI_PRODUCT_BROADCOM_BCM5705F, 337 "Broadcom BCM5705F Gigabit Ethernet", 338 }, 339 { PCI_VENDOR_BROADCOM, 340 PCI_PRODUCT_BROADCOM_BCM5705K, 341 "Broadcom BCM5705K Gigabit Ethernet", 342 }, 343 { PCI_VENDOR_BROADCOM, 344 PCI_PRODUCT_BROADCOM_BCM5705M, 345 "Broadcom BCM5705M Gigabit Ethernet", 346 }, 347 { PCI_VENDOR_BROADCOM, 348 PCI_PRODUCT_BROADCOM_BCM5705M_ALT, 349 "Broadcom BCM5705M Gigabit Ethernet", 350 }, 351 { PCI_VENDOR_BROADCOM, 352 PCI_PRODUCT_BROADCOM_BCM5714, 353 "Broadcom BCM5714 Gigabit Ethernet", 354 }, 355 { PCI_VENDOR_BROADCOM, 356 PCI_PRODUCT_BROADCOM_BCM5714S, 357 "Broadcom BCM5714S Gigabit Ethernet", 358 }, 359 { PCI_VENDOR_BROADCOM, 360 PCI_PRODUCT_BROADCOM_BCM5715, 361 "Broadcom BCM5715 Gigabit Ethernet", 362 }, 363 { PCI_VENDOR_BROADCOM, 364 PCI_PRODUCT_BROADCOM_BCM5715S, 365 "Broadcom BCM5715S Gigabit Ethernet", 366 }, 367 { PCI_VENDOR_BROADCOM, 368 PCI_PRODUCT_BROADCOM_BCM5717, 369 "Broadcom BCM5717 Gigabit Ethernet", 370 }, 371 { PCI_VENDOR_BROADCOM, 372 PCI_PRODUCT_BROADCOM_BCM5718, 373 "Broadcom BCM5718 Gigabit Ethernet", 374 }, 375 { PCI_VENDOR_BROADCOM, 376 PCI_PRODUCT_BROADCOM_BCM5720, 377 "Broadcom BCM5720 Gigabit Ethernet", 378 }, 379 { PCI_VENDOR_BROADCOM, 380 PCI_PRODUCT_BROADCOM_BCM5721, 381 "Broadcom BCM5721 Gigabit Ethernet", 382 }, 383 { PCI_VENDOR_BROADCOM, 384 PCI_PRODUCT_BROADCOM_BCM5722, 385 "Broadcom BCM5722 Gigabit Ethernet", 386 }, 387 { PCI_VENDOR_BROADCOM, 388 PCI_PRODUCT_BROADCOM_BCM5723, 389 "Broadcom BCM5723 Gigabit Ethernet", 390 }, 391 { PCI_VENDOR_BROADCOM, 392 PCI_PRODUCT_BROADCOM_BCM5724, 393 "Broadcom BCM5724 Gigabit Ethernet", 394 }, 395 { PCI_VENDOR_BROADCOM, 396 PCI_PRODUCT_BROADCOM_BCM5750, 397 "Broadcom BCM5750 Gigabit Ethernet", 398 }, 399 { PCI_VENDOR_BROADCOM, 400 PCI_PRODUCT_BROADCOM_BCM5750M, 401 "Broadcom BCM5750M Gigabit Ethernet", 402 }, 403 { PCI_VENDOR_BROADCOM, 404 PCI_PRODUCT_BROADCOM_BCM5751, 405 "Broadcom BCM5751 Gigabit Ethernet", 406 }, 407 { PCI_VENDOR_BROADCOM, 408 PCI_PRODUCT_BROADCOM_BCM5751F, 409 "Broadcom BCM5751F Gigabit Ethernet", 410 }, 411 { PCI_VENDOR_BROADCOM, 412 PCI_PRODUCT_BROADCOM_BCM5751M, 413 "Broadcom BCM5751M Gigabit Ethernet", 414 }, 415 { PCI_VENDOR_BROADCOM, 416 PCI_PRODUCT_BROADCOM_BCM5752, 417 "Broadcom BCM5752 Gigabit Ethernet", 418 }, 419 { PCI_VENDOR_BROADCOM, 420 PCI_PRODUCT_BROADCOM_BCM5752M, 421 "Broadcom BCM5752M Gigabit Ethernet", 422 }, 423 { PCI_VENDOR_BROADCOM, 424 PCI_PRODUCT_BROADCOM_BCM5753, 425 "Broadcom BCM5753 Gigabit Ethernet", 426 }, 427 { PCI_VENDOR_BROADCOM, 428 PCI_PRODUCT_BROADCOM_BCM5753F, 429 "Broadcom BCM5753F Gigabit Ethernet", 430 }, 431 { PCI_VENDOR_BROADCOM, 432 PCI_PRODUCT_BROADCOM_BCM5753M, 433 "Broadcom BCM5753M Gigabit Ethernet", 434 }, 435 { PCI_VENDOR_BROADCOM, 436 PCI_PRODUCT_BROADCOM_BCM5754, 437 "Broadcom BCM5754 Gigabit Ethernet", 438 }, 439 { PCI_VENDOR_BROADCOM, 440 PCI_PRODUCT_BROADCOM_BCM5754M, 441 "Broadcom BCM5754M Gigabit Ethernet", 442 }, 443 { PCI_VENDOR_BROADCOM, 444 PCI_PRODUCT_BROADCOM_BCM5755, 445 "Broadcom BCM5755 Gigabit Ethernet", 446 }, 447 { PCI_VENDOR_BROADCOM, 448 PCI_PRODUCT_BROADCOM_BCM5755M, 449 "Broadcom BCM5755M Gigabit Ethernet", 450 }, 451 { PCI_VENDOR_BROADCOM, 452 PCI_PRODUCT_BROADCOM_BCM5756, 453 "Broadcom BCM5756 Gigabit Ethernet", 454 }, 455 { PCI_VENDOR_BROADCOM, 456 PCI_PRODUCT_BROADCOM_BCM5761, 457 "Broadcom BCM5761 Gigabit Ethernet", 458 }, 459 { PCI_VENDOR_BROADCOM, 460 PCI_PRODUCT_BROADCOM_BCM5761E, 461 "Broadcom BCM5761E Gigabit Ethernet", 462 }, 463 { PCI_VENDOR_BROADCOM, 464 PCI_PRODUCT_BROADCOM_BCM5761S, 465 "Broadcom BCM5761S Gigabit Ethernet", 466 }, 467 { PCI_VENDOR_BROADCOM, 468 PCI_PRODUCT_BROADCOM_BCM5761SE, 469 "Broadcom BCM5761SE Gigabit Ethernet", 470 }, 471 { PCI_VENDOR_BROADCOM, 472 PCI_PRODUCT_BROADCOM_BCM5764, 473 "Broadcom BCM5764 Gigabit Ethernet", 474 }, 475 { PCI_VENDOR_BROADCOM, 476 PCI_PRODUCT_BROADCOM_BCM5780, 477 "Broadcom BCM5780 Gigabit Ethernet", 478 }, 479 { PCI_VENDOR_BROADCOM, 480 PCI_PRODUCT_BROADCOM_BCM5780S, 481 "Broadcom BCM5780S Gigabit Ethernet", 482 }, 483 { PCI_VENDOR_BROADCOM, 484 PCI_PRODUCT_BROADCOM_BCM5781, 485 "Broadcom BCM5781 Gigabit Ethernet", 486 }, 487 { PCI_VENDOR_BROADCOM, 488 PCI_PRODUCT_BROADCOM_BCM5782, 489 "Broadcom BCM5782 Gigabit Ethernet", 490 }, 491 { PCI_VENDOR_BROADCOM, 492 PCI_PRODUCT_BROADCOM_BCM5784M, 493 "BCM5784M NetLink 1000baseT Ethernet", 494 }, 495 { PCI_VENDOR_BROADCOM, 496 PCI_PRODUCT_BROADCOM_BCM5786, 497 "Broadcom BCM5786 Gigabit Ethernet", 498 }, 499 { PCI_VENDOR_BROADCOM, 500 PCI_PRODUCT_BROADCOM_BCM5787, 501 "Broadcom BCM5787 Gigabit Ethernet", 502 }, 503 { PCI_VENDOR_BROADCOM, 504 PCI_PRODUCT_BROADCOM_BCM5787M, 505 "Broadcom BCM5787M Gigabit Ethernet", 506 }, 507 { PCI_VENDOR_BROADCOM, 508 PCI_PRODUCT_BROADCOM_BCM5788, 509 "Broadcom BCM5788 Gigabit Ethernet", 510 }, 511 { PCI_VENDOR_BROADCOM, 512 PCI_PRODUCT_BROADCOM_BCM5789, 513 "Broadcom BCM5789 Gigabit Ethernet", 514 }, 515 { PCI_VENDOR_BROADCOM, 516 PCI_PRODUCT_BROADCOM_BCM5901, 517 "Broadcom BCM5901 Fast Ethernet", 518 }, 519 { PCI_VENDOR_BROADCOM, 520 PCI_PRODUCT_BROADCOM_BCM5901A2, 521 "Broadcom BCM5901A2 Fast Ethernet", 522 }, 523 { PCI_VENDOR_BROADCOM, 524 PCI_PRODUCT_BROADCOM_BCM5903M, 525 "Broadcom BCM5903M Fast Ethernet", 526 }, 527 { PCI_VENDOR_BROADCOM, 528 PCI_PRODUCT_BROADCOM_BCM5906, 529 "Broadcom BCM5906 Fast Ethernet", 530 }, 531 { PCI_VENDOR_BROADCOM, 532 PCI_PRODUCT_BROADCOM_BCM5906M, 533 "Broadcom BCM5906M Fast Ethernet", 534 }, 535 { PCI_VENDOR_BROADCOM, 536 PCI_PRODUCT_BROADCOM_BCM57760, 537 "Broadcom BCM57760 Fast Ethernet", 538 }, 539 { PCI_VENDOR_BROADCOM, 540 PCI_PRODUCT_BROADCOM_BCM57761, 541 "Broadcom BCM57761 Fast Ethernet", 542 }, 543 { PCI_VENDOR_BROADCOM, 544 PCI_PRODUCT_BROADCOM_BCM57765, 545 "Broadcom BCM57765 Fast Ethernet", 546 }, 547 { PCI_VENDOR_BROADCOM, 548 PCI_PRODUCT_BROADCOM_BCM57780, 549 "Broadcom BCM57780 Fast Ethernet", 550 }, 551 { PCI_VENDOR_BROADCOM, 552 PCI_PRODUCT_BROADCOM_BCM57781, 553 "Broadcom BCM57781 Fast Ethernet", 554 }, 555 { PCI_VENDOR_BROADCOM, 556 PCI_PRODUCT_BROADCOM_BCM57785, 557 "Broadcom BCM57785 Fast Ethernet", 558 }, 559 { PCI_VENDOR_BROADCOM, 560 PCI_PRODUCT_BROADCOM_BCM57788, 561 "Broadcom BCM57788 Fast Ethernet", 562 }, 563 { PCI_VENDOR_BROADCOM, 564 PCI_PRODUCT_BROADCOM_BCM57790, 565 "Broadcom BCM57790 Fast Ethernet", 566 }, 567 { PCI_VENDOR_BROADCOM, 568 PCI_PRODUCT_BROADCOM_BCM57791, 569 "Broadcom BCM57791 Fast Ethernet", 570 }, 571 { PCI_VENDOR_BROADCOM, 572 PCI_PRODUCT_BROADCOM_BCM57795, 573 "Broadcom BCM57795 Fast Ethernet", 574 }, 575 { PCI_VENDOR_SCHNEIDERKOCH, 576 PCI_PRODUCT_SCHNEIDERKOCH_SK_9DX1, 577 "SysKonnect SK-9Dx1 Gigabit Ethernet", 578 }, 579 { PCI_VENDOR_3COM, 580 PCI_PRODUCT_3COM_3C996, 581 "3Com 3c996 Gigabit Ethernet", 582 }, 583 { 0, 584 0, 585 NULL }, 586 }; 587 588 /* 589 * XXX: how to handle variants based on 5750 and derivatives: 590 * 5750 5751, 5721, possibly 5714, 5752, and 5708?, which 591 * in general behave like a 5705, except with additional quirks. 592 * This driver's current handling of the 5721 is wrong; 593 * how we map ASIC revision to "quirks" needs more thought. 594 * (defined here until the thought is done). 595 */ 596 #define BGE_IS_5700_FAMILY(sc) ((sc)->bge_flags & BGE_5700_FAMILY) 597 #define BGE_IS_5714_FAMILY(sc) ((sc)->bge_flags & BGE_5714_FAMILY) 598 #define BGE_IS_5705_PLUS(sc) ((sc)->bge_flags & BGE_5705_PLUS) 599 #define BGE_IS_5750_OR_BEYOND(sc) ((sc)->bge_flags & BGE_5750_PLUS) 600 #define BGE_IS_5755_PLUS(sc) ((sc)->bge_flags & BGE_5755_PLUS) 601 #define BGE_IS_JUMBO_CAPABLE(sc) ((sc)->bge_flags & BGE_JUMBO_CAPABLE) 602 603 static const struct bge_revision { 604 uint32_t br_chipid; 605 const char *br_name; 606 } bge_revisions[] = { 607 { BGE_CHIPID_BCM5700_A0, "BCM5700 A0" }, 608 { BGE_CHIPID_BCM5700_A1, "BCM5700 A1" }, 609 { BGE_CHIPID_BCM5700_B0, "BCM5700 B0" }, 610 { BGE_CHIPID_BCM5700_B1, "BCM5700 B1" }, 611 { BGE_CHIPID_BCM5700_B2, "BCM5700 B2" }, 612 { BGE_CHIPID_BCM5700_B3, "BCM5700 B3" }, 613 /* This is treated like a BCM5700 Bx */ 614 { BGE_CHIPID_BCM5700_ALTIMA, "BCM5700 Altima" }, 615 { BGE_CHIPID_BCM5700_C0, "BCM5700 C0" }, 616 { BGE_CHIPID_BCM5701_A0, "BCM5701 A0" }, 617 { BGE_CHIPID_BCM5701_B0, "BCM5701 B0" }, 618 { BGE_CHIPID_BCM5701_B2, "BCM5701 B2" }, 619 { BGE_CHIPID_BCM5701_B5, "BCM5701 B5" }, 620 { BGE_CHIPID_BCM5703_A0, "BCM5702/5703 A0" }, 621 { BGE_CHIPID_BCM5703_A1, "BCM5702/5703 A1" }, 622 { BGE_CHIPID_BCM5703_A2, "BCM5702/5703 A2" }, 623 { BGE_CHIPID_BCM5703_A3, "BCM5702/5703 A3" }, 624 { BGE_CHIPID_BCM5703_B0, "BCM5702/5703 B0" }, 625 { BGE_CHIPID_BCM5704_A0, "BCM5704 A0" }, 626 { BGE_CHIPID_BCM5704_A1, "BCM5704 A1" }, 627 { BGE_CHIPID_BCM5704_A2, "BCM5704 A2" }, 628 { BGE_CHIPID_BCM5704_A3, "BCM5704 A3" }, 629 { BGE_CHIPID_BCM5704_B0, "BCM5704 B0" }, 630 { BGE_CHIPID_BCM5705_A0, "BCM5705 A0" }, 631 { BGE_CHIPID_BCM5705_A1, "BCM5705 A1" }, 632 { BGE_CHIPID_BCM5705_A2, "BCM5705 A2" }, 633 { BGE_CHIPID_BCM5705_A3, "BCM5705 A3" }, 634 { BGE_CHIPID_BCM5750_A0, "BCM5750 A0" }, 635 { BGE_CHIPID_BCM5750_A1, "BCM5750 A1" }, 636 { BGE_CHIPID_BCM5750_A3, "BCM5750 A3" }, 637 { BGE_CHIPID_BCM5750_B0, "BCM5750 B0" }, 638 { BGE_CHIPID_BCM5750_B1, "BCM5750 B1" }, 639 { BGE_CHIPID_BCM5750_C0, "BCM5750 C0" }, 640 { BGE_CHIPID_BCM5750_C1, "BCM5750 C1" }, 641 { BGE_CHIPID_BCM5750_C2, "BCM5750 C2" }, 642 { BGE_CHIPID_BCM5752_A0, "BCM5752 A0" }, 643 { BGE_CHIPID_BCM5752_A1, "BCM5752 A1" }, 644 { BGE_CHIPID_BCM5752_A2, "BCM5752 A2" }, 645 { BGE_CHIPID_BCM5714_A0, "BCM5714 A0" }, 646 { BGE_CHIPID_BCM5714_B0, "BCM5714 B0" }, 647 { BGE_CHIPID_BCM5714_B3, "BCM5714 B3" }, 648 { BGE_CHIPID_BCM5715_A0, "BCM5715 A0" }, 649 { BGE_CHIPID_BCM5715_A1, "BCM5715 A1" }, 650 { BGE_CHIPID_BCM5715_A3, "BCM5715 A3" }, 651 { BGE_CHIPID_BCM5755_A0, "BCM5755 A0" }, 652 { BGE_CHIPID_BCM5755_A1, "BCM5755 A1" }, 653 { BGE_CHIPID_BCM5755_A2, "BCM5755 A2" }, 654 { BGE_CHIPID_BCM5755_C0, "BCM5755 C0" }, 655 { BGE_CHIPID_BCM5761_A0, "BCM5761 A0" }, 656 { BGE_CHIPID_BCM5761_A1, "BCM5761 A1" }, 657 { BGE_CHIPID_BCM5784_A0, "BCM5784 A0" }, 658 { BGE_CHIPID_BCM5784_A1, "BCM5784 A1" }, 659 /* 5754 and 5787 share the same ASIC ID */ 660 { BGE_CHIPID_BCM5787_A0, "BCM5754/5787 A0" }, 661 { BGE_CHIPID_BCM5787_A1, "BCM5754/5787 A1" }, 662 { BGE_CHIPID_BCM5787_A2, "BCM5754/5787 A2" }, 663 { BGE_CHIPID_BCM5906_A1, "BCM5906 A1" }, 664 { BGE_CHIPID_BCM5906_A2, "BCM5906 A2" }, 665 { BGE_CHIPID_BCM57780_A0, "BCM57780 A0" }, 666 { BGE_CHIPID_BCM57780_A1, "BCM57780 A1" }, 667 668 { 0, NULL } 669 }; 670 671 /* 672 * Some defaults for major revisions, so that newer steppings 673 * that we don't know about have a shot at working. 674 */ 675 static const struct bge_revision bge_majorrevs[] = { 676 { BGE_ASICREV_BCM5700, "unknown BCM5700" }, 677 { BGE_ASICREV_BCM5701, "unknown BCM5701" }, 678 { BGE_ASICREV_BCM5703, "unknown BCM5703" }, 679 { BGE_ASICREV_BCM5704, "unknown BCM5704" }, 680 { BGE_ASICREV_BCM5705, "unknown BCM5705" }, 681 { BGE_ASICREV_BCM5750, "unknown BCM5750" }, 682 { BGE_ASICREV_BCM5714_A0, "unknown BCM5714" }, 683 { BGE_ASICREV_BCM5752, "unknown BCM5752" }, 684 { BGE_ASICREV_BCM5780, "unknown BCM5780" }, 685 { BGE_ASICREV_BCM5714, "unknown BCM5714" }, 686 { BGE_ASICREV_BCM5755, "unknown BCM5755" }, 687 { BGE_ASICREV_BCM5761, "unknown BCM5761" }, 688 { BGE_ASICREV_BCM5784, "unknown BCM5784" }, 689 { BGE_ASICREV_BCM5785, "unknown BCM5785" }, 690 /* 5754 and 5787 share the same ASIC ID */ 691 { BGE_ASICREV_BCM5787, "unknown BCM5754/5787" }, 692 { BGE_ASICREV_BCM5906, "unknown BCM5906" }, 693 { BGE_ASICREV_BCM57780, "unknown BCM57780" }, 694 { BGE_ASICREV_BCM5717, "unknown BCM5717" }, 695 { BGE_ASICREV_BCM57765, "unknown BCM57765" }, 696 697 { 0, NULL } 698 }; 699 700 CFATTACH_DECL_NEW(bge, sizeof(struct bge_softc), 701 bge_probe, bge_attach, NULL, NULL); 702 703 static uint32_t 704 bge_readmem_ind(struct bge_softc *sc, int off) 705 { 706 pcireg_t val; 707 708 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_BASEADDR, off); 709 val = pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_DATA); 710 return val; 711 } 712 713 static void 714 bge_writemem_ind(struct bge_softc *sc, int off, int val) 715 { 716 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_BASEADDR, off); 717 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_DATA, val); 718 } 719 720 #ifdef notdef 721 static uint32_t 722 bge_readreg_ind(struct bge_softc *sc, int off) 723 { 724 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_REG_BASEADDR, off); 725 return (pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_REG_DATA)); 726 } 727 #endif 728 729 static void 730 bge_writereg_ind(struct bge_softc *sc, int off, int val) 731 { 732 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_REG_BASEADDR, off); 733 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_REG_DATA, val); 734 } 735 736 static void 737 bge_writemem_direct(struct bge_softc *sc, int off, int val) 738 { 739 CSR_WRITE_4(sc, off, val); 740 } 741 742 static void 743 bge_writembx(struct bge_softc *sc, int off, int val) 744 { 745 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 746 off += BGE_LPMBX_IRQ0_HI - BGE_MBX_IRQ0_HI; 747 748 CSR_WRITE_4(sc, off, val); 749 } 750 751 static uint8_t 752 bge_nvram_getbyte(struct bge_softc *sc, int addr, uint8_t *dest) 753 { 754 uint32_t access, byte = 0; 755 int i; 756 757 /* Lock. */ 758 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_SET1); 759 for (i = 0; i < 8000; i++) { 760 if (CSR_READ_4(sc, BGE_NVRAM_SWARB) & BGE_NVRAMSWARB_GNT1) 761 break; 762 DELAY(20); 763 } 764 if (i == 8000) 765 return 1; 766 767 /* Enable access. */ 768 access = CSR_READ_4(sc, BGE_NVRAM_ACCESS); 769 CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access | BGE_NVRAMACC_ENABLE); 770 771 CSR_WRITE_4(sc, BGE_NVRAM_ADDR, addr & 0xfffffffc); 772 CSR_WRITE_4(sc, BGE_NVRAM_CMD, BGE_NVRAM_READCMD); 773 for (i = 0; i < BGE_TIMEOUT * 10; i++) { 774 DELAY(10); 775 if (CSR_READ_4(sc, BGE_NVRAM_CMD) & BGE_NVRAMCMD_DONE) { 776 DELAY(10); 777 break; 778 } 779 } 780 781 if (i == BGE_TIMEOUT * 10) { 782 aprint_error_dev(sc->bge_dev, "nvram read timed out\n"); 783 return 1; 784 } 785 786 /* Get result. */ 787 byte = CSR_READ_4(sc, BGE_NVRAM_RDDATA); 788 789 *dest = (bswap32(byte) >> ((addr % 4) * 8)) & 0xFF; 790 791 /* Disable access. */ 792 CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access); 793 794 /* Unlock. */ 795 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_CLR1); 796 CSR_READ_4(sc, BGE_NVRAM_SWARB); 797 798 return 0; 799 } 800 801 /* 802 * Read a sequence of bytes from NVRAM. 803 */ 804 static int 805 bge_read_nvram(struct bge_softc *sc, uint8_t *dest, int off, int cnt) 806 { 807 int err = 0, i; 808 uint8_t byte = 0; 809 810 if (BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5906) 811 return 1; 812 813 for (i = 0; i < cnt; i++) { 814 err = bge_nvram_getbyte(sc, off + i, &byte); 815 if (err) 816 break; 817 *(dest + i) = byte; 818 } 819 820 return (err ? 1 : 0); 821 } 822 823 /* 824 * Read a byte of data stored in the EEPROM at address 'addr.' The 825 * BCM570x supports both the traditional bitbang interface and an 826 * auto access interface for reading the EEPROM. We use the auto 827 * access method. 828 */ 829 static uint8_t 830 bge_eeprom_getbyte(struct bge_softc *sc, int addr, uint8_t *dest) 831 { 832 int i; 833 uint32_t byte = 0; 834 835 /* 836 * Enable use of auto EEPROM access so we can avoid 837 * having to use the bitbang method. 838 */ 839 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM); 840 841 /* Reset the EEPROM, load the clock period. */ 842 CSR_WRITE_4(sc, BGE_EE_ADDR, 843 BGE_EEADDR_RESET | BGE_EEHALFCLK(BGE_HALFCLK_384SCL)); 844 DELAY(20); 845 846 /* Issue the read EEPROM command. */ 847 CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr); 848 849 /* Wait for completion */ 850 for (i = 0; i < BGE_TIMEOUT * 10; i++) { 851 DELAY(10); 852 if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE) 853 break; 854 } 855 856 if (i == BGE_TIMEOUT * 10) { 857 aprint_error_dev(sc->bge_dev, "eeprom read timed out\n"); 858 return 0; 859 } 860 861 /* Get result. */ 862 byte = CSR_READ_4(sc, BGE_EE_DATA); 863 864 *dest = (byte >> ((addr % 4) * 8)) & 0xFF; 865 866 return 0; 867 } 868 869 /* 870 * Read a sequence of bytes from the EEPROM. 871 */ 872 static int 873 bge_read_eeprom(struct bge_softc *sc, void *destv, int off, int cnt) 874 { 875 int err = 0, i; 876 uint8_t byte = 0; 877 char *dest = destv; 878 879 for (i = 0; i < cnt; i++) { 880 err = bge_eeprom_getbyte(sc, off + i, &byte); 881 if (err) 882 break; 883 *(dest + i) = byte; 884 } 885 886 return (err ? 1 : 0); 887 } 888 889 static int 890 bge_miibus_readreg(device_t dev, int phy, int reg) 891 { 892 struct bge_softc *sc = device_private(dev); 893 uint32_t val; 894 uint32_t autopoll; 895 int i; 896 897 /* 898 * Broadcom's own driver always assumes the internal 899 * PHY is at GMII address 1. On some chips, the PHY responds 900 * to accesses at all addresses, which could cause us to 901 * bogusly attach the PHY 32 times at probe type. Always 902 * restricting the lookup to address 1 is simpler than 903 * trying to figure out which chips revisions should be 904 * special-cased. 905 */ 906 if (phy != 1) 907 return 0; 908 909 /* Reading with autopolling on may trigger PCI errors */ 910 autopoll = CSR_READ_4(sc, BGE_MI_MODE); 911 if (autopoll & BGE_MIMODE_AUTOPOLL) { 912 BGE_STS_CLRBIT(sc, BGE_STS_AUTOPOLL); 913 BGE_CLRBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 914 DELAY(40); 915 } 916 917 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_READ | BGE_MICOMM_BUSY | 918 BGE_MIPHY(phy) | BGE_MIREG(reg)); 919 920 for (i = 0; i < BGE_TIMEOUT; i++) { 921 val = CSR_READ_4(sc, BGE_MI_COMM); 922 if (!(val & BGE_MICOMM_BUSY)) 923 break; 924 delay(10); 925 } 926 927 if (i == BGE_TIMEOUT) { 928 aprint_error_dev(sc->bge_dev, "PHY read timed out\n"); 929 val = 0; 930 goto done; 931 } 932 933 val = CSR_READ_4(sc, BGE_MI_COMM); 934 935 done: 936 if (autopoll & BGE_MIMODE_AUTOPOLL) { 937 BGE_STS_SETBIT(sc, BGE_STS_AUTOPOLL); 938 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 939 DELAY(40); 940 } 941 942 if (val & BGE_MICOMM_READFAIL) 943 return 0; 944 945 return (val & 0xFFFF); 946 } 947 948 static void 949 bge_miibus_writereg(device_t dev, int phy, int reg, int val) 950 { 951 struct bge_softc *sc = device_private(dev); 952 uint32_t autopoll; 953 int i; 954 955 if (phy!=1) { 956 return; 957 } 958 959 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906 && 960 (reg == BRGPHY_MII_1000CTL || reg == BRGPHY_MII_AUXCTL)) { 961 return; 962 } 963 964 /* Reading with autopolling on may trigger PCI errors */ 965 autopoll = CSR_READ_4(sc, BGE_MI_MODE); 966 if (autopoll & BGE_MIMODE_AUTOPOLL) { 967 delay(40); 968 BGE_STS_CLRBIT(sc, BGE_STS_AUTOPOLL); 969 BGE_CLRBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 970 delay(10); /* 40 usec is supposed to be adequate */ 971 } 972 973 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_WRITE | BGE_MICOMM_BUSY | 974 BGE_MIPHY(phy) | BGE_MIREG(reg)|val); 975 976 for (i = 0; i < BGE_TIMEOUT; i++) { 977 delay(10); 978 if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY)) { 979 delay(5); 980 CSR_READ_4(sc, BGE_MI_COMM); 981 break; 982 } 983 } 984 985 if (autopoll & BGE_MIMODE_AUTOPOLL) { 986 BGE_STS_SETBIT(sc, BGE_STS_AUTOPOLL); 987 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 988 delay(40); 989 } 990 991 if (i == BGE_TIMEOUT) 992 aprint_error_dev(sc->bge_dev, "PHY read timed out\n"); 993 } 994 995 static void 996 bge_miibus_statchg(device_t dev) 997 { 998 struct bge_softc *sc = device_private(dev); 999 struct mii_data *mii = &sc->bge_mii; 1000 1001 /* 1002 * Get flow control negotiation result. 1003 */ 1004 if (IFM_SUBTYPE(mii->mii_media.ifm_cur->ifm_media) == IFM_AUTO && 1005 (mii->mii_media_active & IFM_ETH_FMASK) != sc->bge_flowflags) { 1006 sc->bge_flowflags = mii->mii_media_active & IFM_ETH_FMASK; 1007 mii->mii_media_active &= ~IFM_ETH_FMASK; 1008 } 1009 1010 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_PORTMODE); 1011 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T || 1012 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX) 1013 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_GMII); 1014 else 1015 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_MII); 1016 1017 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) 1018 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX); 1019 else 1020 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX); 1021 1022 /* 1023 * 802.3x flow control 1024 */ 1025 if (sc->bge_flowflags & IFM_ETH_RXPAUSE) 1026 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_FLOWCTL_ENABLE); 1027 else 1028 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_FLOWCTL_ENABLE); 1029 1030 if (sc->bge_flowflags & IFM_ETH_TXPAUSE) 1031 BGE_SETBIT(sc, BGE_TX_MODE, BGE_TXMODE_FLOWCTL_ENABLE); 1032 else 1033 BGE_CLRBIT(sc, BGE_TX_MODE, BGE_TXMODE_FLOWCTL_ENABLE); 1034 } 1035 1036 /* 1037 * Update rx threshold levels to values in a particular slot 1038 * of the interrupt-mitigation table bge_rx_threshes. 1039 */ 1040 static void 1041 bge_set_thresh(struct ifnet *ifp, int lvl) 1042 { 1043 struct bge_softc *sc = ifp->if_softc; 1044 int s; 1045 1046 /* For now, just save the new Rx-intr thresholds and record 1047 * that a threshold update is pending. Updating the hardware 1048 * registers here (even at splhigh()) is observed to 1049 * occasionaly cause glitches where Rx-interrupts are not 1050 * honoured for up to 10 seconds. jonathan (at) NetBSD.org, 2003-04-05 1051 */ 1052 s = splnet(); 1053 sc->bge_rx_coal_ticks = bge_rx_threshes[lvl].rx_ticks; 1054 sc->bge_rx_max_coal_bds = bge_rx_threshes[lvl].rx_max_bds; 1055 sc->bge_pending_rxintr_change = 1; 1056 splx(s); 1057 1058 return; 1059 } 1060 1061 1062 /* 1063 * Update Rx thresholds of all bge devices 1064 */ 1065 static void 1066 bge_update_all_threshes(int lvl) 1067 { 1068 struct ifnet *ifp; 1069 const char * const namebuf = "bge"; 1070 int namelen; 1071 1072 if (lvl < 0) 1073 lvl = 0; 1074 else if (lvl >= NBGE_RX_THRESH) 1075 lvl = NBGE_RX_THRESH - 1; 1076 1077 namelen = strlen(namebuf); 1078 /* 1079 * Now search all the interfaces for this name/number 1080 */ 1081 IFNET_FOREACH(ifp) { 1082 if (strncmp(ifp->if_xname, namebuf, namelen) != 0) 1083 continue; 1084 /* We got a match: update if doing auto-threshold-tuning */ 1085 if (bge_auto_thresh) 1086 bge_set_thresh(ifp, lvl); 1087 } 1088 } 1089 1090 /* 1091 * Handle events that have triggered interrupts. 1092 */ 1093 static void 1094 bge_handle_events(struct bge_softc *sc) 1095 { 1096 1097 return; 1098 } 1099 1100 /* 1101 * Memory management for jumbo frames. 1102 */ 1103 1104 static int 1105 bge_alloc_jumbo_mem(struct bge_softc *sc) 1106 { 1107 char *ptr, *kva; 1108 bus_dma_segment_t seg; 1109 int i, rseg, state, error; 1110 struct bge_jpool_entry *entry; 1111 1112 state = error = 0; 1113 1114 /* Grab a big chunk o' storage. */ 1115 if (bus_dmamem_alloc(sc->bge_dmatag, BGE_JMEM, PAGE_SIZE, 0, 1116 &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 1117 aprint_error_dev(sc->bge_dev, "can't alloc rx buffers\n"); 1118 return ENOBUFS; 1119 } 1120 1121 state = 1; 1122 if (bus_dmamem_map(sc->bge_dmatag, &seg, rseg, BGE_JMEM, (void **)&kva, 1123 BUS_DMA_NOWAIT)) { 1124 aprint_error_dev(sc->bge_dev, 1125 "can't map DMA buffers (%d bytes)\n", (int)BGE_JMEM); 1126 error = ENOBUFS; 1127 goto out; 1128 } 1129 1130 state = 2; 1131 if (bus_dmamap_create(sc->bge_dmatag, BGE_JMEM, 1, BGE_JMEM, 0, 1132 BUS_DMA_NOWAIT, &sc->bge_cdata.bge_rx_jumbo_map)) { 1133 aprint_error_dev(sc->bge_dev, "can't create DMA map\n"); 1134 error = ENOBUFS; 1135 goto out; 1136 } 1137 1138 state = 3; 1139 if (bus_dmamap_load(sc->bge_dmatag, sc->bge_cdata.bge_rx_jumbo_map, 1140 kva, BGE_JMEM, NULL, BUS_DMA_NOWAIT)) { 1141 aprint_error_dev(sc->bge_dev, "can't load DMA map\n"); 1142 error = ENOBUFS; 1143 goto out; 1144 } 1145 1146 state = 4; 1147 sc->bge_cdata.bge_jumbo_buf = (void *)kva; 1148 DPRINTFN(1,("bge_jumbo_buf = %p\n", sc->bge_cdata.bge_jumbo_buf)); 1149 1150 SLIST_INIT(&sc->bge_jfree_listhead); 1151 SLIST_INIT(&sc->bge_jinuse_listhead); 1152 1153 /* 1154 * Now divide it up into 9K pieces and save the addresses 1155 * in an array. 1156 */ 1157 ptr = sc->bge_cdata.bge_jumbo_buf; 1158 for (i = 0; i < BGE_JSLOTS; i++) { 1159 sc->bge_cdata.bge_jslots[i] = ptr; 1160 ptr += BGE_JLEN; 1161 entry = malloc(sizeof(struct bge_jpool_entry), 1162 M_DEVBUF, M_NOWAIT); 1163 if (entry == NULL) { 1164 aprint_error_dev(sc->bge_dev, 1165 "no memory for jumbo buffer queue!\n"); 1166 error = ENOBUFS; 1167 goto out; 1168 } 1169 entry->slot = i; 1170 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, 1171 entry, jpool_entries); 1172 } 1173 out: 1174 if (error != 0) { 1175 switch (state) { 1176 case 4: 1177 bus_dmamap_unload(sc->bge_dmatag, 1178 sc->bge_cdata.bge_rx_jumbo_map); 1179 case 3: 1180 bus_dmamap_destroy(sc->bge_dmatag, 1181 sc->bge_cdata.bge_rx_jumbo_map); 1182 case 2: 1183 bus_dmamem_unmap(sc->bge_dmatag, kva, BGE_JMEM); 1184 case 1: 1185 bus_dmamem_free(sc->bge_dmatag, &seg, rseg); 1186 break; 1187 default: 1188 break; 1189 } 1190 } 1191 1192 return error; 1193 } 1194 1195 /* 1196 * Allocate a jumbo buffer. 1197 */ 1198 static void * 1199 bge_jalloc(struct bge_softc *sc) 1200 { 1201 struct bge_jpool_entry *entry; 1202 1203 entry = SLIST_FIRST(&sc->bge_jfree_listhead); 1204 1205 if (entry == NULL) { 1206 aprint_error_dev(sc->bge_dev, "no free jumbo buffers\n"); 1207 return NULL; 1208 } 1209 1210 SLIST_REMOVE_HEAD(&sc->bge_jfree_listhead, jpool_entries); 1211 SLIST_INSERT_HEAD(&sc->bge_jinuse_listhead, entry, jpool_entries); 1212 return (sc->bge_cdata.bge_jslots[entry->slot]); 1213 } 1214 1215 /* 1216 * Release a jumbo buffer. 1217 */ 1218 static void 1219 bge_jfree(struct mbuf *m, void *buf, size_t size, void *arg) 1220 { 1221 struct bge_jpool_entry *entry; 1222 struct bge_softc *sc; 1223 int i, s; 1224 1225 /* Extract the softc struct pointer. */ 1226 sc = (struct bge_softc *)arg; 1227 1228 if (sc == NULL) 1229 panic("bge_jfree: can't find softc pointer!"); 1230 1231 /* calculate the slot this buffer belongs to */ 1232 1233 i = ((char *)buf 1234 - (char *)sc->bge_cdata.bge_jumbo_buf) / BGE_JLEN; 1235 1236 if ((i < 0) || (i >= BGE_JSLOTS)) 1237 panic("bge_jfree: asked to free buffer that we don't manage!"); 1238 1239 s = splvm(); 1240 entry = SLIST_FIRST(&sc->bge_jinuse_listhead); 1241 if (entry == NULL) 1242 panic("bge_jfree: buffer not in use!"); 1243 entry->slot = i; 1244 SLIST_REMOVE_HEAD(&sc->bge_jinuse_listhead, jpool_entries); 1245 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, entry, jpool_entries); 1246 1247 if (__predict_true(m != NULL)) 1248 pool_cache_put(mb_cache, m); 1249 splx(s); 1250 } 1251 1252 1253 /* 1254 * Intialize a standard receive ring descriptor. 1255 */ 1256 static int 1257 bge_newbuf_std(struct bge_softc *sc, int i, struct mbuf *m, bus_dmamap_t dmamap) 1258 { 1259 struct mbuf *m_new = NULL; 1260 struct bge_rx_bd *r; 1261 int error; 1262 1263 if (dmamap == NULL) { 1264 error = bus_dmamap_create(sc->bge_dmatag, MCLBYTES, 1, 1265 MCLBYTES, 0, BUS_DMA_NOWAIT, &dmamap); 1266 if (error != 0) 1267 return error; 1268 } 1269 1270 sc->bge_cdata.bge_rx_std_map[i] = dmamap; 1271 1272 if (m == NULL) { 1273 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1274 if (m_new == NULL) 1275 return ENOBUFS; 1276 1277 MCLGET(m_new, M_DONTWAIT); 1278 if (!(m_new->m_flags & M_EXT)) { 1279 m_freem(m_new); 1280 return ENOBUFS; 1281 } 1282 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1283 1284 } else { 1285 m_new = m; 1286 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1287 m_new->m_data = m_new->m_ext.ext_buf; 1288 } 1289 if (!(sc->bge_flags & BGE_RX_ALIGNBUG)) 1290 m_adj(m_new, ETHER_ALIGN); 1291 if (bus_dmamap_load_mbuf(sc->bge_dmatag, dmamap, m_new, 1292 BUS_DMA_READ|BUS_DMA_NOWAIT)) 1293 return ENOBUFS; 1294 bus_dmamap_sync(sc->bge_dmatag, dmamap, 0, dmamap->dm_mapsize, 1295 BUS_DMASYNC_PREREAD); 1296 1297 sc->bge_cdata.bge_rx_std_chain[i] = m_new; 1298 r = &sc->bge_rdata->bge_rx_std_ring[i]; 1299 BGE_HOSTADDR(r->bge_addr, dmamap->dm_segs[0].ds_addr); 1300 r->bge_flags = BGE_RXBDFLAG_END; 1301 r->bge_len = m_new->m_len; 1302 r->bge_idx = i; 1303 1304 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 1305 offsetof(struct bge_ring_data, bge_rx_std_ring) + 1306 i * sizeof (struct bge_rx_bd), 1307 sizeof (struct bge_rx_bd), 1308 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1309 1310 return 0; 1311 } 1312 1313 /* 1314 * Initialize a jumbo receive ring descriptor. This allocates 1315 * a jumbo buffer from the pool managed internally by the driver. 1316 */ 1317 static int 1318 bge_newbuf_jumbo(struct bge_softc *sc, int i, struct mbuf *m) 1319 { 1320 struct mbuf *m_new = NULL; 1321 struct bge_rx_bd *r; 1322 void *buf = NULL; 1323 1324 if (m == NULL) { 1325 1326 /* Allocate the mbuf. */ 1327 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1328 if (m_new == NULL) 1329 return ENOBUFS; 1330 1331 /* Allocate the jumbo buffer */ 1332 buf = bge_jalloc(sc); 1333 if (buf == NULL) { 1334 m_freem(m_new); 1335 aprint_error_dev(sc->bge_dev, 1336 "jumbo allocation failed -- packet dropped!\n"); 1337 return ENOBUFS; 1338 } 1339 1340 /* Attach the buffer to the mbuf. */ 1341 m_new->m_len = m_new->m_pkthdr.len = BGE_JUMBO_FRAMELEN; 1342 MEXTADD(m_new, buf, BGE_JUMBO_FRAMELEN, M_DEVBUF, 1343 bge_jfree, sc); 1344 m_new->m_flags |= M_EXT_RW; 1345 } else { 1346 m_new = m; 1347 buf = m_new->m_data = m_new->m_ext.ext_buf; 1348 m_new->m_ext.ext_size = BGE_JUMBO_FRAMELEN; 1349 } 1350 if (!(sc->bge_flags & BGE_RX_ALIGNBUG)) 1351 m_adj(m_new, ETHER_ALIGN); 1352 bus_dmamap_sync(sc->bge_dmatag, sc->bge_cdata.bge_rx_jumbo_map, 1353 mtod(m_new, char *) - (char *)sc->bge_cdata.bge_jumbo_buf, BGE_JLEN, 1354 BUS_DMASYNC_PREREAD); 1355 /* Set up the descriptor. */ 1356 r = &sc->bge_rdata->bge_rx_jumbo_ring[i]; 1357 sc->bge_cdata.bge_rx_jumbo_chain[i] = m_new; 1358 BGE_HOSTADDR(r->bge_addr, BGE_JUMBO_DMA_ADDR(sc, m_new)); 1359 r->bge_flags = BGE_RXBDFLAG_END|BGE_RXBDFLAG_JUMBO_RING; 1360 r->bge_len = m_new->m_len; 1361 r->bge_idx = i; 1362 1363 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 1364 offsetof(struct bge_ring_data, bge_rx_jumbo_ring) + 1365 i * sizeof (struct bge_rx_bd), 1366 sizeof (struct bge_rx_bd), 1367 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1368 1369 return 0; 1370 } 1371 1372 /* 1373 * The standard receive ring has 512 entries in it. At 2K per mbuf cluster, 1374 * that's 1MB or memory, which is a lot. For now, we fill only the first 1375 * 256 ring entries and hope that our CPU is fast enough to keep up with 1376 * the NIC. 1377 */ 1378 static int 1379 bge_init_rx_ring_std(struct bge_softc *sc) 1380 { 1381 int i; 1382 1383 if (sc->bge_flags & BGE_RXRING_VALID) 1384 return 0; 1385 1386 for (i = 0; i < BGE_SSLOTS; i++) { 1387 if (bge_newbuf_std(sc, i, NULL, 0) == ENOBUFS) 1388 return ENOBUFS; 1389 } 1390 1391 sc->bge_std = i - 1; 1392 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std); 1393 1394 sc->bge_flags |= BGE_RXRING_VALID; 1395 1396 return 0; 1397 } 1398 1399 static void 1400 bge_free_rx_ring_std(struct bge_softc *sc) 1401 { 1402 int i; 1403 1404 if (!(sc->bge_flags & BGE_RXRING_VALID)) 1405 return; 1406 1407 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { 1408 if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) { 1409 m_freem(sc->bge_cdata.bge_rx_std_chain[i]); 1410 sc->bge_cdata.bge_rx_std_chain[i] = NULL; 1411 bus_dmamap_destroy(sc->bge_dmatag, 1412 sc->bge_cdata.bge_rx_std_map[i]); 1413 } 1414 memset((char *)&sc->bge_rdata->bge_rx_std_ring[i], 0, 1415 sizeof(struct bge_rx_bd)); 1416 } 1417 1418 sc->bge_flags &= ~BGE_RXRING_VALID; 1419 } 1420 1421 static int 1422 bge_init_rx_ring_jumbo(struct bge_softc *sc) 1423 { 1424 int i; 1425 volatile struct bge_rcb *rcb; 1426 1427 if (sc->bge_flags & BGE_JUMBO_RXRING_VALID) 1428 return 0; 1429 1430 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 1431 if (bge_newbuf_jumbo(sc, i, NULL) == ENOBUFS) 1432 return ENOBUFS; 1433 }; 1434 1435 sc->bge_jumbo = i - 1; 1436 sc->bge_flags |= BGE_JUMBO_RXRING_VALID; 1437 1438 rcb = &sc->bge_rdata->bge_info.bge_jumbo_rx_rcb; 1439 rcb->bge_maxlen_flags = 0; 1440 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 1441 1442 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo); 1443 1444 return 0; 1445 } 1446 1447 static void 1448 bge_free_rx_ring_jumbo(struct bge_softc *sc) 1449 { 1450 int i; 1451 1452 if (!(sc->bge_flags & BGE_JUMBO_RXRING_VALID)) 1453 return; 1454 1455 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 1456 if (sc->bge_cdata.bge_rx_jumbo_chain[i] != NULL) { 1457 m_freem(sc->bge_cdata.bge_rx_jumbo_chain[i]); 1458 sc->bge_cdata.bge_rx_jumbo_chain[i] = NULL; 1459 } 1460 memset((char *)&sc->bge_rdata->bge_rx_jumbo_ring[i], 0, 1461 sizeof(struct bge_rx_bd)); 1462 } 1463 1464 sc->bge_flags &= ~BGE_JUMBO_RXRING_VALID; 1465 } 1466 1467 static void 1468 bge_free_tx_ring(struct bge_softc *sc) 1469 { 1470 int i, freed; 1471 struct txdmamap_pool_entry *dma; 1472 1473 if (!(sc->bge_flags & BGE_TXRING_VALID)) 1474 return; 1475 1476 freed = 0; 1477 1478 for (i = 0; i < BGE_TX_RING_CNT; i++) { 1479 if (sc->bge_cdata.bge_tx_chain[i] != NULL) { 1480 freed++; 1481 m_freem(sc->bge_cdata.bge_tx_chain[i]); 1482 sc->bge_cdata.bge_tx_chain[i] = NULL; 1483 SLIST_INSERT_HEAD(&sc->txdma_list, sc->txdma[i], 1484 link); 1485 sc->txdma[i] = 0; 1486 } 1487 memset((char *)&sc->bge_rdata->bge_tx_ring[i], 0, 1488 sizeof(struct bge_tx_bd)); 1489 } 1490 1491 while ((dma = SLIST_FIRST(&sc->txdma_list))) { 1492 SLIST_REMOVE_HEAD(&sc->txdma_list, link); 1493 bus_dmamap_destroy(sc->bge_dmatag, dma->dmamap); 1494 free(dma, M_DEVBUF); 1495 } 1496 1497 sc->bge_flags &= ~BGE_TXRING_VALID; 1498 } 1499 1500 static int 1501 bge_init_tx_ring(struct bge_softc *sc) 1502 { 1503 int i; 1504 bus_dmamap_t dmamap; 1505 struct txdmamap_pool_entry *dma; 1506 1507 if (sc->bge_flags & BGE_TXRING_VALID) 1508 return 0; 1509 1510 sc->bge_txcnt = 0; 1511 sc->bge_tx_saved_considx = 0; 1512 1513 /* Initialize transmit producer index for host-memory send ring. */ 1514 sc->bge_tx_prodidx = 0; 1515 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx); 1516 /* 5700 b2 errata */ 1517 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX) 1518 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx); 1519 1520 /* NIC-memory send ring not used; initialize to zero. */ 1521 bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0); 1522 /* 5700 b2 errata */ 1523 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX) 1524 bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0); 1525 1526 SLIST_INIT(&sc->txdma_list); 1527 for (i = 0; i < BGE_RSLOTS; i++) { 1528 if (bus_dmamap_create(sc->bge_dmatag, BGE_TXDMA_MAX, 1529 BGE_NTXSEG, ETHER_MAX_LEN_JUMBO, 0, BUS_DMA_NOWAIT, 1530 &dmamap)) 1531 return ENOBUFS; 1532 if (dmamap == NULL) 1533 panic("dmamap NULL in bge_init_tx_ring"); 1534 dma = malloc(sizeof(*dma), M_DEVBUF, M_NOWAIT); 1535 if (dma == NULL) { 1536 aprint_error_dev(sc->bge_dev, 1537 "can't alloc txdmamap_pool_entry\n"); 1538 bus_dmamap_destroy(sc->bge_dmatag, dmamap); 1539 return ENOMEM; 1540 } 1541 dma->dmamap = dmamap; 1542 SLIST_INSERT_HEAD(&sc->txdma_list, dma, link); 1543 } 1544 1545 sc->bge_flags |= BGE_TXRING_VALID; 1546 1547 return 0; 1548 } 1549 1550 static void 1551 bge_setmulti(struct bge_softc *sc) 1552 { 1553 struct ethercom *ac = &sc->ethercom; 1554 struct ifnet *ifp = &ac->ec_if; 1555 struct ether_multi *enm; 1556 struct ether_multistep step; 1557 uint32_t hashes[4] = { 0, 0, 0, 0 }; 1558 uint32_t h; 1559 int i; 1560 1561 if (ifp->if_flags & IFF_PROMISC) 1562 goto allmulti; 1563 1564 /* Now program new ones. */ 1565 ETHER_FIRST_MULTI(step, ac, enm); 1566 while (enm != NULL) { 1567 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1568 /* 1569 * We must listen to a range of multicast addresses. 1570 * For now, just accept all multicasts, rather than 1571 * trying to set only those filter bits needed to match 1572 * the range. (At this time, the only use of address 1573 * ranges is for IP multicast routing, for which the 1574 * range is big enough to require all bits set.) 1575 */ 1576 goto allmulti; 1577 } 1578 1579 h = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN); 1580 1581 /* Just want the 7 least-significant bits. */ 1582 h &= 0x7f; 1583 1584 hashes[(h & 0x60) >> 5] |= 1 << (h & 0x1F); 1585 ETHER_NEXT_MULTI(step, enm); 1586 } 1587 1588 ifp->if_flags &= ~IFF_ALLMULTI; 1589 goto setit; 1590 1591 allmulti: 1592 ifp->if_flags |= IFF_ALLMULTI; 1593 hashes[0] = hashes[1] = hashes[2] = hashes[3] = 0xffffffff; 1594 1595 setit: 1596 for (i = 0; i < 4; i++) 1597 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]); 1598 } 1599 1600 const int bge_swapbits[] = { 1601 0, 1602 BGE_MODECTL_BYTESWAP_DATA, 1603 BGE_MODECTL_WORDSWAP_DATA, 1604 BGE_MODECTL_BYTESWAP_NONFRAME, 1605 BGE_MODECTL_WORDSWAP_NONFRAME, 1606 1607 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA, 1608 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_BYTESWAP_NONFRAME, 1609 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_NONFRAME, 1610 1611 BGE_MODECTL_WORDSWAP_DATA|BGE_MODECTL_BYTESWAP_NONFRAME, 1612 BGE_MODECTL_WORDSWAP_DATA|BGE_MODECTL_WORDSWAP_NONFRAME, 1613 1614 BGE_MODECTL_BYTESWAP_NONFRAME|BGE_MODECTL_WORDSWAP_NONFRAME, 1615 1616 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA| 1617 BGE_MODECTL_BYTESWAP_NONFRAME, 1618 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA| 1619 BGE_MODECTL_WORDSWAP_NONFRAME, 1620 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_BYTESWAP_NONFRAME| 1621 BGE_MODECTL_WORDSWAP_NONFRAME, 1622 BGE_MODECTL_WORDSWAP_DATA|BGE_MODECTL_BYTESWAP_NONFRAME| 1623 BGE_MODECTL_WORDSWAP_NONFRAME, 1624 1625 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA| 1626 BGE_MODECTL_BYTESWAP_NONFRAME|BGE_MODECTL_WORDSWAP_NONFRAME, 1627 }; 1628 1629 int bge_swapindex = 0; 1630 1631 /* 1632 * Do endian, PCI and DMA initialization. Also check the on-board ROM 1633 * self-test results. 1634 */ 1635 static int 1636 bge_chipinit(struct bge_softc *sc) 1637 { 1638 int i; 1639 uint32_t dma_rw_ctl; 1640 1641 1642 /* Set endianness before we access any non-PCI registers. */ 1643 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MISC_CTL, 1644 BGE_INIT); 1645 1646 /* Set power state to D0. */ 1647 bge_setpowerstate(sc, 0); 1648 1649 /* Clear the MAC control register */ 1650 CSR_WRITE_4(sc, BGE_MAC_MODE, 0); 1651 1652 /* 1653 * Clear the MAC statistics block in the NIC's 1654 * internal memory. 1655 */ 1656 for (i = BGE_STATS_BLOCK; 1657 i < BGE_STATS_BLOCK_END + 1; i += sizeof(uint32_t)) 1658 BGE_MEMWIN_WRITE(sc->sc_pc, sc->sc_pcitag, i, 0); 1659 1660 for (i = BGE_STATUS_BLOCK; 1661 i < BGE_STATUS_BLOCK_END + 1; i += sizeof(uint32_t)) 1662 BGE_MEMWIN_WRITE(sc->sc_pc, sc->sc_pcitag, i, 0); 1663 1664 /* Set up the PCI DMA control register. */ 1665 dma_rw_ctl = BGE_PCI_READ_CMD | BGE_PCI_WRITE_CMD; 1666 if (sc->bge_flags & BGE_PCIE) { 1667 /* Read watermark not used, 128 bytes for write. */ 1668 DPRINTFN(4, ("(%s: PCI-Express DMA setting)\n", 1669 device_xname(sc->bge_dev))); 1670 dma_rw_ctl |= (0x3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT); 1671 } else if (sc->bge_flags & BGE_PCIX) { 1672 DPRINTFN(4, ("(:%s: PCI-X DMA setting)\n", 1673 device_xname(sc->bge_dev))); 1674 /* PCI-X bus */ 1675 if (BGE_IS_5714_FAMILY(sc)) { 1676 /* 256 bytes for read and write. */ 1677 dma_rw_ctl |= (0x02 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) | 1678 (0x02 << BGE_PCIDMARWCTL_WR_WAT_SHIFT); 1679 1680 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5780) 1681 dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL; 1682 else 1683 dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE_LOCAL; 1684 } else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) { 1685 /* 1536 bytes for read, 384 bytes for write. */ 1686 dma_rw_ctl |= 1687 (0x7 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) | 1688 (0x3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT); 1689 } else { 1690 /* 384 bytes for read and write. */ 1691 dma_rw_ctl |= (0x03 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) | 1692 (0x03 << BGE_PCIDMARWCTL_WR_WAT_SHIFT) | 1693 (0x0F); 1694 } 1695 1696 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5703 || 1697 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) { 1698 uint32_t tmp; 1699 1700 /* Set ONEDMA_ATONCE for hardware workaround. */ 1701 tmp = CSR_READ_4(sc, BGE_PCI_CLKCTL) & 0x1f; 1702 if (tmp == 6 || tmp == 7) 1703 dma_rw_ctl |= 1704 BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL; 1705 1706 /* Set PCI-X DMA write workaround. */ 1707 dma_rw_ctl |= BGE_PCIDMARWCTL_ASRT_ALL_BE; 1708 } 1709 } else { 1710 /* Conventional PCI bus: 256 bytes for read and write. */ 1711 DPRINTFN(4, ("(%s: PCI 2.2 DMA setting)\n", 1712 device_xname(sc->bge_dev))); 1713 dma_rw_ctl = (0x7 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) | 1714 (0x7 << BGE_PCIDMARWCTL_WR_WAT_SHIFT); 1715 if (BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5705 && 1716 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5750) 1717 dma_rw_ctl |= 0x0F; 1718 } 1719 1720 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 1721 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5701) 1722 dma_rw_ctl |= BGE_PCIDMARWCTL_USE_MRM | 1723 BGE_PCIDMARWCTL_ASRT_ALL_BE; 1724 1725 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5703 || 1726 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) 1727 dma_rw_ctl &= ~BGE_PCIDMARWCTL_MINDMA; 1728 1729 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_DMA_RW_CTL, dma_rw_ctl); 1730 1731 /* 1732 * Set up general mode register. 1733 */ 1734 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS | 1735 BGE_MODECTL_MAC_ATTN_INTR | BGE_MODECTL_HOST_SEND_BDS | 1736 BGE_MODECTL_TX_NO_PHDR_CSUM | BGE_MODECTL_RX_NO_PHDR_CSUM); 1737 1738 /* 1739 * BCM5701 B5 have a bug causing data corruption when using 1740 * 64-bit DMA reads, which can be terminated early and then 1741 * completed later as 32-bit accesses, in combination with 1742 * certain bridges. 1743 */ 1744 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5701 && 1745 sc->bge_chipid == BGE_CHIPID_BCM5701_B5) 1746 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_FORCE_PCI32); 1747 1748 /* 1749 * Disable memory write invalidate. Apparently it is not supported 1750 * properly by these devices. 1751 */ 1752 PCI_CLRBIT(sc->sc_pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG, 1753 PCI_COMMAND_INVALIDATE_ENABLE); 1754 1755 #ifdef __brokenalpha__ 1756 /* 1757 * Must insure that we do not cross an 8K (bytes) boundary 1758 * for DMA reads. Our highest limit is 1K bytes. This is a 1759 * restriction on some ALPHA platforms with early revision 1760 * 21174 PCI chipsets, such as the AlphaPC 164lx 1761 */ 1762 PCI_SETBIT(sc, BGE_PCI_DMA_RW_CTL, BGE_PCI_READ_BNDRY_1024, 4); 1763 #endif 1764 1765 /* Set the timer prescaler (always 66MHz) */ 1766 CSR_WRITE_4(sc, BGE_MISC_CFG, 65 << 1/*BGE_32BITTIME_66MHZ*/); 1767 1768 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 1769 DELAY(40); /* XXX */ 1770 1771 /* Put PHY into ready state */ 1772 BGE_CLRBIT(sc, BGE_MISC_CFG, BGE_MISCCFG_EPHY_IDDQ); 1773 CSR_READ_4(sc, BGE_MISC_CFG); /* Flush */ 1774 DELAY(40); 1775 } 1776 1777 return 0; 1778 } 1779 1780 static int 1781 bge_blockinit(struct bge_softc *sc) 1782 { 1783 volatile struct bge_rcb *rcb; 1784 bus_size_t rcb_addr; 1785 int i; 1786 struct ifnet *ifp = &sc->ethercom.ec_if; 1787 bge_hostaddr taddr; 1788 uint32_t val; 1789 1790 /* 1791 * Initialize the memory window pointer register so that 1792 * we can access the first 32K of internal NIC RAM. This will 1793 * allow us to set up the TX send ring RCBs and the RX return 1794 * ring RCBs, plus other things which live in NIC memory. 1795 */ 1796 1797 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_BASEADDR, 0); 1798 1799 /* Configure mbuf memory pool */ 1800 if (BGE_IS_5700_FAMILY(sc)) { 1801 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, 1802 BGE_BUFFPOOL_1); 1803 1804 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) 1805 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000); 1806 else 1807 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000); 1808 1809 /* Configure DMA resource pool */ 1810 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_BASEADDR, 1811 BGE_DMA_DESCRIPTORS); 1812 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LEN, 0x2000); 1813 } 1814 1815 /* Configure mbuf pool watermarks */ 1816 #ifdef ORIG_WPAUL_VALUES 1817 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 24); 1818 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 24); 1819 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 48); 1820 #else 1821 1822 /* new broadcom docs strongly recommend these: */ 1823 if (!BGE_IS_5705_PLUS(sc)) { 1824 if (ifp->if_mtu > ETHER_MAX_LEN) { 1825 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x50); 1826 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x20); 1827 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60); 1828 } else { 1829 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 304); 1830 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 152); 1831 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 380); 1832 } 1833 } else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 1834 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0); 1835 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x04); 1836 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x10); 1837 } else { 1838 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0); 1839 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x10); 1840 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60); 1841 } 1842 #endif 1843 1844 /* Configure DMA resource watermarks */ 1845 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5); 1846 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10); 1847 1848 /* Enable buffer manager */ 1849 CSR_WRITE_4(sc, BGE_BMAN_MODE, 1850 BGE_BMANMODE_ENABLE | BGE_BMANMODE_LOMBUF_ATTN); 1851 1852 /* Poll for buffer manager start indication */ 1853 for (i = 0; i < BGE_TIMEOUT * 2; i++) { 1854 if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE) 1855 break; 1856 DELAY(10); 1857 } 1858 1859 if (i == BGE_TIMEOUT * 2) { 1860 aprint_error_dev(sc->bge_dev, 1861 "buffer manager failed to start\n"); 1862 return ENXIO; 1863 } 1864 1865 /* Enable flow-through queues */ 1866 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 1867 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 1868 1869 /* Wait until queue initialization is complete */ 1870 for (i = 0; i < BGE_TIMEOUT * 2; i++) { 1871 if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0) 1872 break; 1873 DELAY(10); 1874 } 1875 1876 if (i == BGE_TIMEOUT * 2) { 1877 aprint_error_dev(sc->bge_dev, 1878 "flow-through queue init failed\n"); 1879 return ENXIO; 1880 } 1881 1882 /* Initialize the standard RX ring control block */ 1883 rcb = &sc->bge_rdata->bge_info.bge_std_rx_rcb; 1884 BGE_HOSTADDR(rcb->bge_hostaddr, BGE_RING_DMA_ADDR(sc, bge_rx_std_ring)); 1885 if (BGE_IS_5705_PLUS(sc)) 1886 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(512, 0); 1887 else 1888 rcb->bge_maxlen_flags = 1889 BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 0); 1890 rcb->bge_nicaddr = BGE_STD_RX_RINGS; 1891 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcb->bge_hostaddr.bge_addr_hi); 1892 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcb->bge_hostaddr.bge_addr_lo); 1893 CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 1894 CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcb->bge_nicaddr); 1895 1896 /* 1897 * Initialize the jumbo RX ring control block 1898 * We set the 'ring disabled' bit in the flags 1899 * field until we're actually ready to start 1900 * using this ring (i.e. once we set the MTU 1901 * high enough to require it). 1902 */ 1903 if (BGE_IS_JUMBO_CAPABLE(sc)) { 1904 rcb = &sc->bge_rdata->bge_info.bge_jumbo_rx_rcb; 1905 BGE_HOSTADDR(rcb->bge_hostaddr, 1906 BGE_RING_DMA_ADDR(sc, bge_rx_jumbo_ring)); 1907 rcb->bge_maxlen_flags = 1908 BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 1909 BGE_RCB_FLAG_RING_DISABLED); 1910 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS; 1911 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI, 1912 rcb->bge_hostaddr.bge_addr_hi); 1913 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO, 1914 rcb->bge_hostaddr.bge_addr_lo); 1915 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, 1916 rcb->bge_maxlen_flags); 1917 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcb->bge_nicaddr); 1918 1919 /* Set up dummy disabled mini ring RCB */ 1920 rcb = &sc->bge_rdata->bge_info.bge_mini_rx_rcb; 1921 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0, 1922 BGE_RCB_FLAG_RING_DISABLED); 1923 CSR_WRITE_4(sc, BGE_RX_MINI_RCB_MAXLEN_FLAGS, 1924 rcb->bge_maxlen_flags); 1925 1926 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 1927 offsetof(struct bge_ring_data, bge_info), 1928 sizeof (struct bge_gib), 1929 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1930 } 1931 1932 /* 1933 * Set the BD ring replenish thresholds. The recommended 1934 * values are 1/8th the number of descriptors allocated to 1935 * each ring. 1936 */ 1937 i = BGE_STD_RX_RING_CNT / 8; 1938 1939 /* 1940 * Use a value of 8 for the following chips to workaround HW errata. 1941 * Some of these chips have been added based on empirical 1942 * evidence (they don't work unless this is done). 1943 */ 1944 if (BGE_IS_5705_PLUS(sc)) 1945 i = 8; 1946 1947 CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, i); 1948 CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH, BGE_JUMBO_RX_RING_CNT / 8); 1949 1950 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5717 || 1951 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57765) { 1952 CSR_WRITE_4(sc, BGE_STD_REPL_LWM, 4); 1953 CSR_WRITE_4(sc, BGE_JUMBO_REPL_LWM, 4); 1954 } 1955 1956 /* 1957 * Disable all unused send rings by setting the 'ring disabled' 1958 * bit in the flags field of all the TX send ring control blocks. 1959 * These are located in NIC memory. 1960 */ 1961 rcb_addr = BGE_MEMWIN_START + BGE_SEND_RING_RCB; 1962 for (i = 0; i < BGE_TX_RINGS_EXTSSRAM_MAX; i++) { 1963 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 1964 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED)); 1965 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 0); 1966 rcb_addr += sizeof(struct bge_rcb); 1967 } 1968 1969 /* Configure TX RCB 0 (we use only the first ring) */ 1970 rcb_addr = BGE_MEMWIN_START + BGE_SEND_RING_RCB; 1971 BGE_HOSTADDR(taddr, BGE_RING_DMA_ADDR(sc, bge_tx_ring)); 1972 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi); 1973 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo); 1974 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 1975 BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT)); 1976 if (BGE_IS_5700_FAMILY(sc)) 1977 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 1978 BGE_RCB_MAXLEN_FLAGS(BGE_TX_RING_CNT, 0)); 1979 1980 /* Disable all unused RX return rings */ 1981 rcb_addr = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB; 1982 for (i = 0; i < BGE_RX_RINGS_MAX; i++) { 1983 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_hi, 0); 1984 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_lo, 0); 1985 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 1986 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 1987 BGE_RCB_FLAG_RING_DISABLED)); 1988 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 0); 1989 bge_writembx(sc, BGE_MBX_RX_CONS0_LO + 1990 (i * (sizeof(uint64_t))), 0); 1991 rcb_addr += sizeof(struct bge_rcb); 1992 } 1993 1994 /* Initialize RX ring indexes */ 1995 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, 0); 1996 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0); 1997 bge_writembx(sc, BGE_MBX_RX_MINI_PROD_LO, 0); 1998 1999 /* 2000 * Set up RX return ring 0 2001 * Note that the NIC address for RX return rings is 0x00000000. 2002 * The return rings live entirely within the host, so the 2003 * nicaddr field in the RCB isn't used. 2004 */ 2005 rcb_addr = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB; 2006 BGE_HOSTADDR(taddr, BGE_RING_DMA_ADDR(sc, bge_rx_return_ring)); 2007 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi); 2008 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo); 2009 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 0x00000000); 2010 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 2011 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 0)); 2012 2013 /* Set random backoff seed for TX */ 2014 CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF, 2015 CLLADDR(ifp->if_sadl)[0] + CLLADDR(ifp->if_sadl)[1] + 2016 CLLADDR(ifp->if_sadl)[2] + CLLADDR(ifp->if_sadl)[3] + 2017 CLLADDR(ifp->if_sadl)[4] + CLLADDR(ifp->if_sadl)[5] + 2018 BGE_TX_BACKOFF_SEED_MASK); 2019 2020 /* Set inter-packet gap */ 2021 CSR_WRITE_4(sc, BGE_TX_LENGTHS, 0x2620); 2022 2023 /* 2024 * Specify which ring to use for packets that don't match 2025 * any RX rules. 2026 */ 2027 CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08); 2028 2029 /* 2030 * Configure number of RX lists. One interrupt distribution 2031 * list, sixteen active lists, one bad frames class. 2032 */ 2033 CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181); 2034 2035 /* Inialize RX list placement stats mask. */ 2036 CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF); 2037 CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1); 2038 2039 /* Disable host coalescing until we get it set up */ 2040 CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000); 2041 2042 /* Poll to make sure it's shut down. */ 2043 for (i = 0; i < BGE_TIMEOUT * 2; i++) { 2044 if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE)) 2045 break; 2046 DELAY(10); 2047 } 2048 2049 if (i == BGE_TIMEOUT * 2) { 2050 aprint_error_dev(sc->bge_dev, 2051 "host coalescing engine failed to idle\n"); 2052 return ENXIO; 2053 } 2054 2055 /* Set up host coalescing defaults */ 2056 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bge_rx_coal_ticks); 2057 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bge_tx_coal_ticks); 2058 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bge_rx_max_coal_bds); 2059 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bge_tx_max_coal_bds); 2060 if (BGE_IS_5700_FAMILY(sc)) { 2061 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT, 0); 2062 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT, 0); 2063 } 2064 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 0); 2065 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 0); 2066 2067 /* Set up address of statistics block */ 2068 if (BGE_IS_5700_FAMILY(sc)) { 2069 BGE_HOSTADDR(taddr, BGE_RING_DMA_ADDR(sc, bge_info.bge_stats)); 2070 CSR_WRITE_4(sc, BGE_HCC_STATS_TICKS, sc->bge_stat_ticks); 2071 CSR_WRITE_4(sc, BGE_HCC_STATS_BASEADDR, BGE_STATS_BLOCK); 2072 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_HI, taddr.bge_addr_hi); 2073 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_LO, taddr.bge_addr_lo); 2074 } 2075 2076 /* Set up address of status block */ 2077 BGE_HOSTADDR(taddr, BGE_RING_DMA_ADDR(sc, bge_status_block)); 2078 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_BASEADDR, BGE_STATUS_BLOCK); 2079 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI, taddr.bge_addr_hi); 2080 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO, taddr.bge_addr_lo); 2081 sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx = 0; 2082 sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx = 0; 2083 2084 /* Turn on host coalescing state machine */ 2085 CSR_WRITE_4(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE); 2086 2087 /* Turn on RX BD completion state machine and enable attentions */ 2088 CSR_WRITE_4(sc, BGE_RBDC_MODE, 2089 BGE_RBDCMODE_ENABLE | BGE_RBDCMODE_ATTN); 2090 2091 /* Turn on RX list placement state machine */ 2092 CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 2093 2094 /* Turn on RX list selector state machine. */ 2095 if (BGE_IS_5700_FAMILY(sc)) 2096 CSR_WRITE_4(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 2097 2098 val = BGE_MACMODE_TXDMA_ENB | BGE_MACMODE_RXDMA_ENB | 2099 BGE_MACMODE_RX_STATS_CLEAR | BGE_MACMODE_TX_STATS_CLEAR | 2100 BGE_MACMODE_RX_STATS_ENB | BGE_MACMODE_TX_STATS_ENB | 2101 BGE_MACMODE_FRMHDR_DMA_ENB; 2102 2103 if (sc->bge_flags & BGE_PHY_FIBER_TBI) 2104 val |= BGE_PORTMODE_TBI; 2105 else if (sc->bge_flags & BGE_PHY_FIBER_MII) 2106 val |= BGE_PORTMODE_GMII; 2107 else 2108 val |= BGE_PORTMODE_MII; 2109 2110 /* Turn on DMA, clear stats */ 2111 CSR_WRITE_4(sc, BGE_MAC_MODE, val); 2112 2113 2114 /* Set misc. local control, enable interrupts on attentions */ 2115 sc->bge_local_ctrl_reg = BGE_MLC_INTR_ONATTN | BGE_MLC_AUTO_EEPROM; 2116 2117 #ifdef notdef 2118 /* Assert GPIO pins for PHY reset */ 2119 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUT0| 2120 BGE_MLC_MISCIO_OUT1|BGE_MLC_MISCIO_OUT2); 2121 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUTEN0| 2122 BGE_MLC_MISCIO_OUTEN1|BGE_MLC_MISCIO_OUTEN2); 2123 #endif 2124 2125 #if defined(not_quite_yet) 2126 /* Linux driver enables enable gpio pin #1 on 5700s */ 2127 if (sc->bge_chipid == BGE_CHIPID_BCM5700) { 2128 sc->bge_local_ctrl_reg |= 2129 (BGE_MLC_MISCIO_OUT1|BGE_MLC_MISCIO_OUTEN1); 2130 } 2131 #endif 2132 CSR_WRITE_4(sc, BGE_MISC_LOCAL_CTL, sc->bge_local_ctrl_reg); 2133 2134 /* Turn on DMA completion state machine */ 2135 if (BGE_IS_5700_FAMILY(sc)) 2136 CSR_WRITE_4(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 2137 2138 /* Turn on write DMA state machine */ 2139 { 2140 uint32_t bge_wdma_mode = 2141 BGE_WDMAMODE_ENABLE|BGE_WDMAMODE_ALL_ATTNS; 2142 2143 /* Enable host coalescing bug fix; see Linux tg3.c */ 2144 if (BGE_IS_5755_PLUS(sc)) 2145 bge_wdma_mode |= BGE_WDMAMODE_STATUS_TAG_FIX; 2146 2147 CSR_WRITE_4(sc, BGE_WDMA_MODE, bge_wdma_mode); 2148 } 2149 2150 /* Turn on read DMA state machine */ 2151 { 2152 uint32_t dma_read_modebits; 2153 2154 dma_read_modebits = 2155 BGE_RDMAMODE_ENABLE | BGE_RDMAMODE_ALL_ATTNS; 2156 2157 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5784 || 2158 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785 || 2159 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57780) 2160 dma_read_modebits |= BGE_RDMAMODE_BD_SBD_CRPT_ATTN | 2161 BGE_RDMAMODE_MBUF_RBD_CRPT_ATTN | 2162 BGE_RDMAMODE_MBUF_SBD_CRPT_ATTN; 2163 2164 if (sc->bge_flags & BGE_PCIE) 2165 dma_read_modebits |= BGE_RDMA_MODE_FIFO_LONG_BURST; 2166 if (sc->bge_flags & BGE_TSO) 2167 dma_read_modebits |= BGE_RDMAMODE_TSO4_ENABLE; 2168 CSR_WRITE_4(sc, BGE_RDMA_MODE, dma_read_modebits); 2169 delay(40); 2170 } 2171 2172 /* Turn on RX data completion state machine */ 2173 CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 2174 2175 /* Turn on RX BD initiator state machine */ 2176 CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 2177 2178 /* Turn on RX data and RX BD initiator state machine */ 2179 CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE); 2180 2181 /* Turn on Mbuf cluster free state machine */ 2182 if (BGE_IS_5700_FAMILY(sc)) 2183 CSR_WRITE_4(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 2184 2185 /* Turn on send BD completion state machine */ 2186 CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 2187 2188 /* Turn on send data completion state machine */ 2189 val = BGE_SDCMODE_ENABLE; 2190 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761) 2191 val |= BGE_SDCMODE_CDELAY; 2192 CSR_WRITE_4(sc, BGE_SDC_MODE, val); 2193 2194 /* Turn on send data initiator state machine */ 2195 if (sc->bge_flags & BGE_TSO) { 2196 /* XXX: magic value from Linux driver */ 2197 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE | 0x08); 2198 } else { 2199 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 2200 } 2201 2202 /* Turn on send BD initiator state machine */ 2203 CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 2204 2205 /* Turn on send BD selector state machine */ 2206 CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 2207 2208 CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF); 2209 CSR_WRITE_4(sc, BGE_SDI_STATS_CTL, 2210 BGE_SDISTATSCTL_ENABLE | BGE_SDISTATSCTL_FASTER); 2211 2212 /* ack/clear link change events */ 2213 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED | 2214 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE | 2215 BGE_MACSTAT_LINK_CHANGED); 2216 CSR_WRITE_4(sc, BGE_MI_STS, 0); 2217 2218 /* Enable PHY auto polling (for MII/GMII only) */ 2219 if (sc->bge_flags & BGE_PHY_FIBER_TBI) { 2220 CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK); 2221 } else { 2222 BGE_STS_SETBIT(sc, BGE_STS_AUTOPOLL); 2223 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL | (10 << 16)); 2224 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700) 2225 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, 2226 BGE_EVTENB_MI_INTERRUPT); 2227 } 2228 2229 /* 2230 * Clear any pending link state attention. 2231 * Otherwise some link state change events may be lost until attention 2232 * is cleared by bge_intr() -> bge_link_upd() sequence. 2233 * It's not necessary on newer BCM chips - perhaps enabling link 2234 * state change attentions implies clearing pending attention. 2235 */ 2236 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED | 2237 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE | 2238 BGE_MACSTAT_LINK_CHANGED); 2239 2240 /* Enable link state change attentions. */ 2241 BGE_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED); 2242 2243 return 0; 2244 } 2245 2246 static const struct bge_revision * 2247 bge_lookup_rev(uint32_t chipid) 2248 { 2249 const struct bge_revision *br; 2250 2251 for (br = bge_revisions; br->br_name != NULL; br++) { 2252 if (br->br_chipid == chipid) 2253 return br; 2254 } 2255 2256 for (br = bge_majorrevs; br->br_name != NULL; br++) { 2257 if (br->br_chipid == BGE_ASICREV(chipid)) 2258 return br; 2259 } 2260 2261 return NULL; 2262 } 2263 2264 static const struct bge_product * 2265 bge_lookup(const struct pci_attach_args *pa) 2266 { 2267 const struct bge_product *bp; 2268 2269 for (bp = bge_products; bp->bp_name != NULL; bp++) { 2270 if (PCI_VENDOR(pa->pa_id) == bp->bp_vendor && 2271 PCI_PRODUCT(pa->pa_id) == bp->bp_product) 2272 return bp; 2273 } 2274 2275 return NULL; 2276 } 2277 2278 static int 2279 bge_setpowerstate(struct bge_softc *sc, int powerlevel) 2280 { 2281 #ifdef NOTYET 2282 uint32_t pm_ctl = 0; 2283 2284 /* XXX FIXME: make sure indirect accesses enabled? */ 2285 pm_ctl = pci_conf_read(sc->bge_dev, BGE_PCI_MISC_CTL, 4); 2286 pm_ctl |= BGE_PCIMISCCTL_INDIRECT_ACCESS; 2287 pci_write_config(sc->bge_dev, BGE_PCI_MISC_CTL, pm_ctl, 4); 2288 2289 /* clear the PME_assert bit and power state bits, enable PME */ 2290 pm_ctl = pci_conf_read(sc->bge_dev, BGE_PCI_PWRMGMT_CMD, 2); 2291 pm_ctl &= ~PCIM_PSTAT_DMASK; 2292 pm_ctl |= (1 << 8); 2293 2294 if (powerlevel == 0) { 2295 pm_ctl |= PCIM_PSTAT_D0; 2296 pci_write_config(sc->bge_dev, BGE_PCI_PWRMGMT_CMD, 2297 pm_ctl, 2); 2298 DELAY(10000); 2299 CSR_WRITE_4(sc, BGE_MISC_LOCAL_CTL, sc->bge_local_ctrl_reg); 2300 DELAY(10000); 2301 2302 #ifdef NOTYET 2303 /* XXX FIXME: write 0x02 to phy aux_Ctrl reg */ 2304 bge_miibus_writereg(sc->bge_dev, 1, 0x18, 0x02); 2305 #endif 2306 DELAY(40); DELAY(40); DELAY(40); 2307 DELAY(10000); /* above not quite adequate on 5700 */ 2308 return 0; 2309 } 2310 2311 2312 /* 2313 * Entering ACPI power states D1-D3 is achieved by wiggling 2314 * GMII gpio pins. Example code assumes all hardware vendors 2315 * followed Broadom's sample pcb layout. Until we verify that 2316 * for all supported OEM cards, states D1-D3 are unsupported. 2317 */ 2318 aprint_error_dev(sc->bge_dev, 2319 "power state %d unimplemented; check GPIO pins\n", 2320 powerlevel); 2321 #endif 2322 return EOPNOTSUPP; 2323 } 2324 2325 2326 /* 2327 * Probe for a Broadcom chip. Check the PCI vendor and device IDs 2328 * against our list and return its name if we find a match. Note 2329 * that since the Broadcom controller contains VPD support, we 2330 * can get the device name string from the controller itself instead 2331 * of the compiled-in string. This is a little slow, but it guarantees 2332 * we'll always announce the right product name. 2333 */ 2334 static int 2335 bge_probe(device_t parent, cfdata_t match, void *aux) 2336 { 2337 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 2338 2339 if (bge_lookup(pa) != NULL) 2340 return 1; 2341 2342 return 0; 2343 } 2344 2345 static void 2346 bge_attach(device_t parent, device_t self, void *aux) 2347 { 2348 struct bge_softc *sc = device_private(self); 2349 struct pci_attach_args *pa = aux; 2350 prop_dictionary_t dict; 2351 const struct bge_product *bp; 2352 const struct bge_revision *br; 2353 pci_chipset_tag_t pc; 2354 pci_intr_handle_t ih; 2355 const char *intrstr = NULL; 2356 bus_dma_segment_t seg; 2357 int rseg; 2358 uint32_t hwcfg = 0; 2359 uint32_t command; 2360 struct ifnet *ifp; 2361 uint32_t misccfg; 2362 void * kva; 2363 u_char eaddr[ETHER_ADDR_LEN]; 2364 pcireg_t memtype, subid; 2365 bus_addr_t memaddr; 2366 bus_size_t memsize; 2367 uint32_t pm_ctl; 2368 bool no_seeprom; 2369 2370 bp = bge_lookup(pa); 2371 KASSERT(bp != NULL); 2372 2373 sc->sc_pc = pa->pa_pc; 2374 sc->sc_pcitag = pa->pa_tag; 2375 sc->bge_dev = self; 2376 2377 pc = sc->sc_pc; 2378 subid = pci_conf_read(pc, sc->sc_pcitag, PCI_SUBSYS_ID_REG); 2379 2380 aprint_naive(": Ethernet controller\n"); 2381 aprint_normal(": %s\n", bp->bp_name); 2382 2383 /* 2384 * Map control/status registers. 2385 */ 2386 DPRINTFN(5, ("Map control/status regs\n")); 2387 command = pci_conf_read(pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG); 2388 command |= PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_MASTER_ENABLE; 2389 pci_conf_write(pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG, command); 2390 command = pci_conf_read(pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG); 2391 2392 if (!(command & PCI_COMMAND_MEM_ENABLE)) { 2393 aprint_error_dev(sc->bge_dev, 2394 "failed to enable memory mapping!\n"); 2395 return; 2396 } 2397 2398 DPRINTFN(5, ("pci_mem_find\n")); 2399 memtype = pci_mapreg_type(sc->sc_pc, sc->sc_pcitag, BGE_PCI_BAR0); 2400 switch (memtype) { 2401 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 2402 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 2403 if (pci_mapreg_map(pa, BGE_PCI_BAR0, 2404 memtype, 0, &sc->bge_btag, &sc->bge_bhandle, 2405 &memaddr, &memsize) == 0) 2406 break; 2407 default: 2408 aprint_error_dev(sc->bge_dev, "can't find mem space\n"); 2409 return; 2410 } 2411 2412 DPRINTFN(5, ("pci_intr_map\n")); 2413 if (pci_intr_map(pa, &ih)) { 2414 aprint_error_dev(sc->bge_dev, "couldn't map interrupt\n"); 2415 return; 2416 } 2417 2418 DPRINTFN(5, ("pci_intr_string\n")); 2419 intrstr = pci_intr_string(pc, ih); 2420 2421 DPRINTFN(5, ("pci_intr_establish\n")); 2422 sc->bge_intrhand = pci_intr_establish(pc, ih, IPL_NET, bge_intr, sc); 2423 2424 if (sc->bge_intrhand == NULL) { 2425 aprint_error_dev(sc->bge_dev, 2426 "couldn't establish interrupt%s%s\n", 2427 intrstr ? " at " : "", intrstr ? intrstr : ""); 2428 return; 2429 } 2430 aprint_normal_dev(sc->bge_dev, "interrupting at %s\n", intrstr); 2431 2432 /* 2433 * Kludge for 5700 Bx bug: a hardware bug (PCIX byte enable?) 2434 * can clobber the chip's PCI config-space power control registers, 2435 * leaving the card in D3 powersave state. 2436 * We do not have memory-mapped registers in this state, 2437 * so force device into D0 state before starting initialization. 2438 */ 2439 pm_ctl = pci_conf_read(pc, sc->sc_pcitag, BGE_PCI_PWRMGMT_CMD); 2440 pm_ctl &= ~(PCI_PWR_D0|PCI_PWR_D1|PCI_PWR_D2|PCI_PWR_D3); 2441 pm_ctl |= (1 << 8) | PCI_PWR_D0 ; /* D0 state */ 2442 pci_conf_write(pc, sc->sc_pcitag, BGE_PCI_PWRMGMT_CMD, pm_ctl); 2443 DELAY(1000); /* 27 usec is allegedly sufficent */ 2444 2445 /* 2446 * Save ASIC rev. 2447 */ 2448 sc->bge_chipid = 2449 pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_MISC_CTL) 2450 >> BGE_PCIMISCCTL_ASICREV_SHIFT; 2451 2452 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_USE_PRODID_REG) { 2453 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5717 || 2454 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5718 || 2455 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5724) 2456 sc->bge_chipid = pci_conf_read(pc, pa->pa_tag, 2457 BGE_PCI_GEN2_PRODID_ASICREV); 2458 else if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM57761 || 2459 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM57765 || 2460 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM57781 || 2461 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM57785 || 2462 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM57791 || 2463 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM57795) 2464 sc->bge_chipid = pci_conf_read(pc, pa->pa_tag, 2465 BGE_PCI_GEN15_PRODID_ASICREV); 2466 else 2467 sc->bge_chipid = pci_conf_read(pc, pa->pa_tag, 2468 BGE_PCI_PRODID_ASICREV); 2469 } 2470 2471 if (pci_get_capability(sc->sc_pc, sc->sc_pcitag, PCI_CAP_PCIEXPRESS, 2472 NULL, NULL) != 0) { 2473 /* PCIe */ 2474 sc->bge_flags |= BGE_PCIE; 2475 } else if ((pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_PCISTATE) & 2476 BGE_PCISTATE_PCI_BUSMODE) == 0) { 2477 /* PCI-X */ 2478 sc->bge_flags |= BGE_PCIX; 2479 } 2480 2481 /* chipid */ 2482 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 2483 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5701 || 2484 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5703 || 2485 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) 2486 sc->bge_flags |= BGE_5700_FAMILY; 2487 2488 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5714_A0 || 2489 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5780 || 2490 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5714) 2491 sc->bge_flags |= BGE_5714_FAMILY; 2492 2493 /* Intentionally exclude BGE_ASICREV_BCM5906 */ 2494 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5717 || 2495 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5755 || 2496 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761 || 2497 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5784 || 2498 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785 || 2499 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5787 || 2500 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57765 || 2501 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57780) 2502 sc->bge_flags |= BGE_5755_PLUS; 2503 2504 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5750 || 2505 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5752 || 2506 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906 || 2507 BGE_IS_5755_PLUS(sc) || 2508 BGE_IS_5714_FAMILY(sc)) 2509 sc->bge_flags |= BGE_5750_PLUS; 2510 2511 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5705 || 2512 BGE_IS_5750_OR_BEYOND(sc)) 2513 sc->bge_flags |= BGE_5705_PLUS; 2514 2515 /* 2516 * When using the BCM5701 in PCI-X mode, data corruption has 2517 * been observed in the first few bytes of some received packets. 2518 * Aligning the packet buffer in memory eliminates the corruption. 2519 * Unfortunately, this misaligns the packet payloads. On platforms 2520 * which do not support unaligned accesses, we will realign the 2521 * payloads by copying the received packets. 2522 */ 2523 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5701 && 2524 sc->bge_flags & BGE_PCIX) 2525 sc->bge_flags |= BGE_RX_ALIGNBUG; 2526 2527 if (BGE_IS_5700_FAMILY(sc)) 2528 sc->bge_flags |= BGE_JUMBO_CAPABLE; 2529 2530 if ((BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 2531 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5701) && 2532 PCI_VENDOR(subid) == PCI_VENDOR_DELL) 2533 sc->bge_flags |= BGE_NO_3LED; 2534 2535 misccfg = CSR_READ_4(sc, BGE_MISC_CFG); 2536 misccfg &= BGE_MISCCFG_BOARD_ID_MASK; 2537 2538 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5705 && 2539 (misccfg == BGE_MISCCFG_BOARD_ID_5788 || 2540 misccfg == BGE_MISCCFG_BOARD_ID_5788M)) 2541 sc->bge_flags |= BGE_IS_5788; 2542 2543 /* 2544 * Some controllers seem to require a special firmware to use 2545 * TSO. But the firmware is not available to FreeBSD and Linux 2546 * claims that the TSO performed by the firmware is slower than 2547 * hardware based TSO. Moreover the firmware based TSO has one 2548 * known bug which can't handle TSO if ethernet header + IP/TCP 2549 * header is greater than 80 bytes. The workaround for the TSO 2550 * bug exist but it seems it's too expensive than not using 2551 * TSO at all. Some hardwares also have the TSO bug so limit 2552 * the TSO to the controllers that are not affected TSO issues 2553 * (e.g. 5755 or higher). 2554 */ 2555 if (BGE_IS_5755_PLUS(sc)) { 2556 /* 2557 * BCM5754 and BCM5787 shares the same ASIC id so 2558 * explicit device id check is required. 2559 */ 2560 if ((PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_BROADCOM_BCM5754) && 2561 (PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_BROADCOM_BCM5754M)) 2562 sc->bge_flags |= BGE_TSO; 2563 } 2564 2565 if ((BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5703 && 2566 (misccfg == 0x4000 || misccfg == 0x8000)) || 2567 (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5705 && 2568 PCI_VENDOR(pa->pa_id) == PCI_VENDOR_BROADCOM && 2569 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5901 || 2570 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5901A2 || 2571 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5705F)) || 2572 (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_BROADCOM && 2573 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5751F || 2574 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5753F || 2575 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5787F)) || 2576 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM57790 || 2577 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 2578 sc->bge_flags |= BGE_10_100_ONLY; 2579 2580 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 2581 (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5705 && 2582 (sc->bge_chipid != BGE_CHIPID_BCM5705_A0 && 2583 sc->bge_chipid != BGE_CHIPID_BCM5705_A1)) || 2584 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 2585 sc->bge_flags |= BGE_NO_ETH_WIRE_SPEED; 2586 2587 if (sc->bge_chipid == BGE_CHIPID_BCM5701_A0 || 2588 sc->bge_chipid == BGE_CHIPID_BCM5701_B0) 2589 sc->bge_flags |= BGE_PHY_CRC_BUG; 2590 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5703_AX || 2591 BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5704_AX) 2592 sc->bge_flags |= BGE_PHY_ADC_BUG; 2593 if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0) 2594 sc->bge_flags |= BGE_PHY_5704_A0_BUG; 2595 2596 if (BGE_IS_5705_PLUS(sc) && 2597 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5906 && 2598 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5717 && 2599 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5785 && 2600 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM57765 && 2601 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM57780) { 2602 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5755 || 2603 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761 || 2604 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5784 || 2605 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5787) { 2606 if (PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_BROADCOM_BCM5722 && 2607 PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_BROADCOM_BCM5756) 2608 sc->bge_flags |= BGE_PHY_JITTER_BUG; 2609 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5755M) 2610 sc->bge_flags |= BGE_PHY_ADJUST_TRIM; 2611 } else if (BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5906) 2612 sc->bge_flags |= BGE_PHY_BER_BUG; 2613 } 2614 2615 /* 2616 * SEEPROM check. 2617 * First check if firmware knows we do not have SEEPROM. 2618 */ 2619 if (prop_dictionary_get_bool(device_properties(self), 2620 "without-seeprom", &no_seeprom) && no_seeprom) 2621 sc->bge_flags |= BGE_NO_EEPROM; 2622 2623 /* Now check the 'ROM failed' bit on the RX CPU */ 2624 else if (CSR_READ_4(sc, BGE_RXCPU_MODE) & BGE_RXCPUMODE_ROMFAIL) 2625 sc->bge_flags |= BGE_NO_EEPROM; 2626 2627 /* Try to reset the chip. */ 2628 DPRINTFN(5, ("bge_reset\n")); 2629 bge_reset(sc); 2630 2631 if (bge_chipinit(sc)) { 2632 aprint_error_dev(sc->bge_dev, "chip initialization failed\n"); 2633 bge_release_resources(sc); 2634 return; 2635 } 2636 2637 /* 2638 * Get station address from the EEPROM 2639 */ 2640 if (bge_get_eaddr(sc, eaddr)) { 2641 aprint_error_dev(sc->bge_dev, 2642 "failed to read station address\n"); 2643 bge_release_resources(sc); 2644 return; 2645 } 2646 2647 br = bge_lookup_rev(sc->bge_chipid); 2648 2649 if (br == NULL) { 2650 aprint_normal_dev(sc->bge_dev, "unknown ASIC (0x%x)", 2651 sc->bge_chipid); 2652 } else { 2653 aprint_normal_dev(sc->bge_dev, "ASIC %s (0x%x)", 2654 br->br_name, sc->bge_chipid); 2655 } 2656 aprint_normal(", Ethernet address %s\n", ether_sprintf(eaddr)); 2657 2658 /* Allocate the general information block and ring buffers. */ 2659 if (pci_dma64_available(pa)) 2660 sc->bge_dmatag = pa->pa_dmat64; 2661 else 2662 sc->bge_dmatag = pa->pa_dmat; 2663 DPRINTFN(5, ("bus_dmamem_alloc\n")); 2664 if (bus_dmamem_alloc(sc->bge_dmatag, sizeof(struct bge_ring_data), 2665 PAGE_SIZE, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 2666 aprint_error_dev(sc->bge_dev, "can't alloc rx buffers\n"); 2667 return; 2668 } 2669 DPRINTFN(5, ("bus_dmamem_map\n")); 2670 if (bus_dmamem_map(sc->bge_dmatag, &seg, rseg, 2671 sizeof(struct bge_ring_data), &kva, 2672 BUS_DMA_NOWAIT)) { 2673 aprint_error_dev(sc->bge_dev, 2674 "can't map DMA buffers (%zu bytes)\n", 2675 sizeof(struct bge_ring_data)); 2676 bus_dmamem_free(sc->bge_dmatag, &seg, rseg); 2677 return; 2678 } 2679 DPRINTFN(5, ("bus_dmamem_create\n")); 2680 if (bus_dmamap_create(sc->bge_dmatag, sizeof(struct bge_ring_data), 1, 2681 sizeof(struct bge_ring_data), 0, 2682 BUS_DMA_NOWAIT, &sc->bge_ring_map)) { 2683 aprint_error_dev(sc->bge_dev, "can't create DMA map\n"); 2684 bus_dmamem_unmap(sc->bge_dmatag, kva, 2685 sizeof(struct bge_ring_data)); 2686 bus_dmamem_free(sc->bge_dmatag, &seg, rseg); 2687 return; 2688 } 2689 DPRINTFN(5, ("bus_dmamem_load\n")); 2690 if (bus_dmamap_load(sc->bge_dmatag, sc->bge_ring_map, kva, 2691 sizeof(struct bge_ring_data), NULL, 2692 BUS_DMA_NOWAIT)) { 2693 bus_dmamap_destroy(sc->bge_dmatag, sc->bge_ring_map); 2694 bus_dmamem_unmap(sc->bge_dmatag, kva, 2695 sizeof(struct bge_ring_data)); 2696 bus_dmamem_free(sc->bge_dmatag, &seg, rseg); 2697 return; 2698 } 2699 2700 DPRINTFN(5, ("bzero\n")); 2701 sc->bge_rdata = (struct bge_ring_data *)kva; 2702 2703 memset(sc->bge_rdata, 0, sizeof(struct bge_ring_data)); 2704 2705 /* Try to allocate memory for jumbo buffers. */ 2706 if (BGE_IS_JUMBO_CAPABLE(sc)) { 2707 if (bge_alloc_jumbo_mem(sc)) { 2708 aprint_error_dev(sc->bge_dev, 2709 "jumbo buffer allocation failed\n"); 2710 } else 2711 sc->ethercom.ec_capabilities |= ETHERCAP_JUMBO_MTU; 2712 } 2713 2714 /* Set default tuneable values. */ 2715 sc->bge_stat_ticks = BGE_TICKS_PER_SEC; 2716 sc->bge_rx_coal_ticks = 150; 2717 sc->bge_rx_max_coal_bds = 64; 2718 #ifdef ORIG_WPAUL_VALUES 2719 sc->bge_tx_coal_ticks = 150; 2720 sc->bge_tx_max_coal_bds = 128; 2721 #else 2722 sc->bge_tx_coal_ticks = 300; 2723 sc->bge_tx_max_coal_bds = 400; 2724 #endif 2725 if (BGE_IS_5705_PLUS(sc)) { 2726 sc->bge_tx_coal_ticks = (12 * 5); 2727 sc->bge_tx_max_coal_bds = (12 * 5); 2728 aprint_verbose_dev(sc->bge_dev, 2729 "setting short Tx thresholds\n"); 2730 } 2731 2732 if (BGE_IS_5705_PLUS(sc)) 2733 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT_5705; 2734 else 2735 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT; 2736 2737 /* Set up ifnet structure */ 2738 ifp = &sc->ethercom.ec_if; 2739 ifp->if_softc = sc; 2740 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 2741 ifp->if_ioctl = bge_ioctl; 2742 ifp->if_stop = bge_stop; 2743 ifp->if_start = bge_start; 2744 ifp->if_init = bge_init; 2745 ifp->if_watchdog = bge_watchdog; 2746 IFQ_SET_MAXLEN(&ifp->if_snd, max(BGE_TX_RING_CNT - 1, IFQ_MAXLEN)); 2747 IFQ_SET_READY(&ifp->if_snd); 2748 DPRINTFN(5, ("strcpy if_xname\n")); 2749 strcpy(ifp->if_xname, device_xname(sc->bge_dev)); 2750 2751 if (sc->bge_chipid != BGE_CHIPID_BCM5700_B0) 2752 sc->ethercom.ec_if.if_capabilities |= 2753 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx; 2754 #if 1 /* XXX TCP/UDP checksum offload breaks with pf(4) */ 2755 sc->ethercom.ec_if.if_capabilities |= 2756 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 2757 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 2758 #endif 2759 sc->ethercom.ec_capabilities |= 2760 ETHERCAP_VLAN_HWTAGGING | ETHERCAP_VLAN_MTU; 2761 2762 if (sc->bge_flags & BGE_TSO) 2763 sc->ethercom.ec_if.if_capabilities |= IFCAP_TSOv4; 2764 2765 /* 2766 * Do MII setup. 2767 */ 2768 DPRINTFN(5, ("mii setup\n")); 2769 sc->bge_mii.mii_ifp = ifp; 2770 sc->bge_mii.mii_readreg = bge_miibus_readreg; 2771 sc->bge_mii.mii_writereg = bge_miibus_writereg; 2772 sc->bge_mii.mii_statchg = bge_miibus_statchg; 2773 2774 /* 2775 * Figure out what sort of media we have by checking the 2776 * hardware config word in the first 32k of NIC internal memory, 2777 * or fall back to the config word in the EEPROM. Note: on some BCM5700 2778 * cards, this value appears to be unset. If that's the 2779 * case, we have to rely on identifying the NIC by its PCI 2780 * subsystem ID, as we do below for the SysKonnect SK-9D41. 2781 */ 2782 if (bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_SIG) == BGE_MAGIC_NUMBER) { 2783 hwcfg = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_NICCFG); 2784 } else if (!(sc->bge_flags & BGE_NO_EEPROM)) { 2785 bge_read_eeprom(sc, (void *)&hwcfg, 2786 BGE_EE_HWCFG_OFFSET, sizeof(hwcfg)); 2787 hwcfg = be32toh(hwcfg); 2788 } 2789 /* The SysKonnect SK-9D41 is a 1000baseSX card. */ 2790 if (PCI_PRODUCT(pa->pa_id) == SK_SUBSYSID_9D41 || 2791 (hwcfg & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER) { 2792 if (BGE_IS_5714_FAMILY(sc)) 2793 sc->bge_flags |= BGE_PHY_FIBER_MII; 2794 else 2795 sc->bge_flags |= BGE_PHY_FIBER_TBI; 2796 } 2797 2798 /* set phyflags before mii_attach() */ 2799 dict = device_properties(self); 2800 prop_dictionary_set_uint32(dict, "phyflags", sc->bge_flags); 2801 2802 if (sc->bge_flags & BGE_PHY_FIBER_TBI) { 2803 ifmedia_init(&sc->bge_ifmedia, IFM_IMASK, bge_ifmedia_upd, 2804 bge_ifmedia_sts); 2805 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL); 2806 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_1000_SX|IFM_FDX, 2807 0, NULL); 2808 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL); 2809 ifmedia_set(&sc->bge_ifmedia, IFM_ETHER|IFM_AUTO); 2810 /* Pretend the user requested this setting */ 2811 sc->bge_ifmedia.ifm_media = sc->bge_ifmedia.ifm_cur->ifm_media; 2812 } else { 2813 /* 2814 * Do transceiver setup. 2815 */ 2816 ifmedia_init(&sc->bge_mii.mii_media, 0, bge_ifmedia_upd, 2817 bge_ifmedia_sts); 2818 mii_attach(sc->bge_dev, &sc->bge_mii, 0xffffffff, 2819 MII_PHY_ANY, MII_OFFSET_ANY, 2820 MIIF_FORCEANEG|MIIF_DOPAUSE); 2821 2822 if (LIST_EMPTY(&sc->bge_mii.mii_phys)) { 2823 aprint_error_dev(sc->bge_dev, "no PHY found!\n"); 2824 ifmedia_add(&sc->bge_mii.mii_media, 2825 IFM_ETHER|IFM_MANUAL, 0, NULL); 2826 ifmedia_set(&sc->bge_mii.mii_media, 2827 IFM_ETHER|IFM_MANUAL); 2828 } else 2829 ifmedia_set(&sc->bge_mii.mii_media, 2830 IFM_ETHER|IFM_AUTO); 2831 } 2832 2833 /* 2834 * Call MI attach routine. 2835 */ 2836 DPRINTFN(5, ("if_attach\n")); 2837 if_attach(ifp); 2838 DPRINTFN(5, ("ether_ifattach\n")); 2839 ether_ifattach(ifp, eaddr); 2840 #if NRND > 0 2841 rnd_attach_source(&sc->rnd_source, device_xname(sc->bge_dev), 2842 RND_TYPE_NET, 0); 2843 #endif 2844 #ifdef BGE_EVENT_COUNTERS 2845 /* 2846 * Attach event counters. 2847 */ 2848 evcnt_attach_dynamic(&sc->bge_ev_intr, EVCNT_TYPE_INTR, 2849 NULL, device_xname(sc->bge_dev), "intr"); 2850 evcnt_attach_dynamic(&sc->bge_ev_tx_xoff, EVCNT_TYPE_MISC, 2851 NULL, device_xname(sc->bge_dev), "tx_xoff"); 2852 evcnt_attach_dynamic(&sc->bge_ev_tx_xon, EVCNT_TYPE_MISC, 2853 NULL, device_xname(sc->bge_dev), "tx_xon"); 2854 evcnt_attach_dynamic(&sc->bge_ev_rx_xoff, EVCNT_TYPE_MISC, 2855 NULL, device_xname(sc->bge_dev), "rx_xoff"); 2856 evcnt_attach_dynamic(&sc->bge_ev_rx_xon, EVCNT_TYPE_MISC, 2857 NULL, device_xname(sc->bge_dev), "rx_xon"); 2858 evcnt_attach_dynamic(&sc->bge_ev_rx_macctl, EVCNT_TYPE_MISC, 2859 NULL, device_xname(sc->bge_dev), "rx_macctl"); 2860 evcnt_attach_dynamic(&sc->bge_ev_xoffentered, EVCNT_TYPE_MISC, 2861 NULL, device_xname(sc->bge_dev), "xoffentered"); 2862 #endif /* BGE_EVENT_COUNTERS */ 2863 DPRINTFN(5, ("callout_init\n")); 2864 callout_init(&sc->bge_timeout, 0); 2865 2866 if (pmf_device_register(self, NULL, NULL)) 2867 pmf_class_network_register(self, ifp); 2868 else 2869 aprint_error_dev(self, "couldn't establish power handler\n"); 2870 2871 #ifdef BGE_DEBUG 2872 bge_debug_info(sc); 2873 #endif 2874 } 2875 2876 static void 2877 bge_release_resources(struct bge_softc *sc) 2878 { 2879 if (sc->bge_vpd_prodname != NULL) 2880 free(sc->bge_vpd_prodname, M_DEVBUF); 2881 2882 if (sc->bge_vpd_readonly != NULL) 2883 free(sc->bge_vpd_readonly, M_DEVBUF); 2884 } 2885 2886 static void 2887 bge_reset(struct bge_softc *sc) 2888 { 2889 uint32_t cachesize, command, pcistate, new_pcistate; 2890 int i, val; 2891 void (*write_op)(struct bge_softc *, int, int); 2892 2893 if (BGE_IS_5750_OR_BEYOND(sc) && !BGE_IS_5714_FAMILY(sc) && 2894 (BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5906)) { 2895 if (sc->bge_flags & BGE_PCIE) { 2896 write_op = bge_writemem_direct; 2897 } else { 2898 write_op = bge_writemem_ind; 2899 } 2900 } else { 2901 write_op = bge_writereg_ind; 2902 } 2903 2904 2905 /* Save some important PCI state. */ 2906 cachesize = pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CACHESZ); 2907 command = pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CMD); 2908 pcistate = pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_PCISTATE); 2909 2910 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MISC_CTL, 2911 BGE_PCIMISCCTL_INDIRECT_ACCESS | BGE_PCIMISCCTL_MASK_PCI_INTR | 2912 BGE_HIF_SWAP_OPTIONS | BGE_PCIMISCCTL_PCISTATE_RW); 2913 2914 /* Disable fastboot on controllers that support it. */ 2915 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5752 || 2916 BGE_IS_5755_PLUS(sc)) 2917 CSR_WRITE_4(sc, BGE_FASTBOOT_PC, 0); 2918 2919 val = BGE_MISCCFG_RESET_CORE_CLOCKS | (65<<1); 2920 /* 2921 * XXX: from FreeBSD/Linux; no documentation 2922 */ 2923 if (sc->bge_flags & BGE_PCIE) { 2924 if (CSR_READ_4(sc, BGE_PCIE_CTL1) == 0x60) 2925 /* PCI Express 1.0 system */ 2926 CSR_WRITE_4(sc, BGE_PCIE_CTL1, 0x20); 2927 if (sc->bge_chipid != BGE_CHIPID_BCM5750_A0) { 2928 /* 2929 * Prevent PCI Express link training 2930 * during global reset. 2931 */ 2932 CSR_WRITE_4(sc, BGE_MISC_CFG, 1 << 29); 2933 val |= (1<<29); 2934 } 2935 } 2936 2937 /* 2938 * Set GPHY Power Down Override to leave GPHY 2939 * powered up in D0 uninitialized. 2940 */ 2941 if (BGE_IS_5705_PLUS(sc)) 2942 val |= BGE_MISCCFG_KEEP_GPHY_POWER; 2943 2944 /* Issue global reset */ 2945 write_op(sc, BGE_MISC_CFG, val); 2946 2947 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 2948 i = CSR_READ_4(sc, BGE_VCPU_STATUS); 2949 CSR_WRITE_4(sc, BGE_VCPU_STATUS, 2950 i | BGE_VCPU_STATUS_DRV_RESET); 2951 i = CSR_READ_4(sc, BGE_VCPU_EXT_CTRL); 2952 CSR_WRITE_4(sc, BGE_VCPU_EXT_CTRL, 2953 i & ~BGE_VCPU_EXT_CTRL_HALT_CPU); 2954 } 2955 2956 DELAY(1000); 2957 2958 /* 2959 * XXX: from FreeBSD/Linux; no documentation 2960 */ 2961 if (sc->bge_flags & BGE_PCIE) { 2962 if (sc->bge_chipid == BGE_CHIPID_BCM5750_A0) { 2963 pcireg_t reg; 2964 2965 DELAY(500000); 2966 /* XXX: Magic Numbers */ 2967 reg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 2968 BGE_PCI_UNKNOWN0); 2969 pci_conf_write(sc->sc_pc, sc->sc_pcitag, 2970 BGE_PCI_UNKNOWN0, 2971 reg | (1 << 15)); 2972 } 2973 /* 2974 * XXX: Magic Numbers. 2975 * Sets maximal PCI-e payload and clears any PCI-e errors. 2976 * Should be replaced with references to PCI config-space 2977 * capability block for PCI-Express. 2978 */ 2979 pci_conf_write(sc->sc_pc, sc->sc_pcitag, 2980 BGE_PCI_CONF_DEV_CTRL, 0xf5000); 2981 2982 } 2983 2984 /* Reset some of the PCI state that got zapped by reset */ 2985 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MISC_CTL, 2986 BGE_PCIMISCCTL_INDIRECT_ACCESS | BGE_PCIMISCCTL_MASK_PCI_INTR | 2987 BGE_HIF_SWAP_OPTIONS | BGE_PCIMISCCTL_PCISTATE_RW); 2988 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CACHESZ, cachesize); 2989 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CMD, command); 2990 write_op(sc, BGE_MISC_CFG, (65 << 1)); 2991 2992 /* Enable memory arbiter. */ 2993 { 2994 uint32_t marbmode = 0; 2995 if (BGE_IS_5714_FAMILY(sc)) { 2996 marbmode = CSR_READ_4(sc, BGE_MARB_MODE); 2997 } 2998 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE | marbmode); 2999 } 3000 3001 /* 3002 * Prevent PXE restart: write a magic number to the 3003 * general communications memory at 0xB50. 3004 */ 3005 bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM, BGE_MAGIC_NUMBER); 3006 3007 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 3008 for (i = 0; i < BGE_TIMEOUT; i++) { 3009 val = CSR_READ_4(sc, BGE_VCPU_STATUS); 3010 if (val & BGE_VCPU_STATUS_INIT_DONE) 3011 break; 3012 DELAY(100); 3013 } 3014 if (i == BGE_TIMEOUT) { 3015 aprint_error_dev(sc->bge_dev, "reset timed out\n"); 3016 return; 3017 } 3018 } else { 3019 /* 3020 * Poll the value location we just wrote until 3021 * we see the 1's complement of the magic number. 3022 * This indicates that the firmware initialization 3023 * is complete. 3024 */ 3025 for (i = 0; i < BGE_TIMEOUT; i++) { 3026 val = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM); 3027 if (val == ~BGE_MAGIC_NUMBER) 3028 break; 3029 DELAY(10); 3030 } 3031 3032 if (i >= BGE_TIMEOUT && (!(sc->bge_flags & BGE_NO_EEPROM))) { 3033 aprint_error_dev(sc->bge_dev, 3034 "firmware handshake timed out, val = %x\n", val); 3035 /* 3036 * XXX: occasionally fired on bcm5721, but without 3037 * apparent harm. For now, keep going if we timeout 3038 * against PCI-E devices. 3039 */ 3040 if ((sc->bge_flags & BGE_PCIE) == 0) 3041 return; 3042 } 3043 } 3044 3045 /* 3046 * XXX Wait for the value of the PCISTATE register to 3047 * return to its original pre-reset state. This is a 3048 * fairly good indicator of reset completion. If we don't 3049 * wait for the reset to fully complete, trying to read 3050 * from the device's non-PCI registers may yield garbage 3051 * results. 3052 */ 3053 for (i = 0; i < BGE_TIMEOUT; i++) { 3054 new_pcistate = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 3055 BGE_PCI_PCISTATE); 3056 if ((new_pcistate & ~BGE_PCISTATE_RESERVED) == 3057 (pcistate & ~BGE_PCISTATE_RESERVED)) 3058 break; 3059 DELAY(10); 3060 } 3061 if ((new_pcistate & ~BGE_PCISTATE_RESERVED) != 3062 (pcistate & ~BGE_PCISTATE_RESERVED)) { 3063 aprint_error_dev(sc->bge_dev, "pcistate failed to revert\n"); 3064 } 3065 3066 #if 0 3067 /* Enable memory arbiter. */ 3068 /* XXX why do this twice? */ 3069 { 3070 uint32_t marbmode = 0; 3071 if (BGE_IS_5714_FAMILY(sc)) { 3072 marbmode = CSR_READ_4(sc, BGE_MARB_MODE); 3073 } 3074 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE | marbmode); 3075 } 3076 #endif 3077 3078 /* Fix up byte swapping */ 3079 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS); 3080 3081 CSR_WRITE_4(sc, BGE_MAC_MODE, 0); 3082 3083 /* 3084 * The 5704 in TBI mode apparently needs some special 3085 * adjustment to insure the SERDES drive level is set 3086 * to 1.2V. 3087 */ 3088 if (sc->bge_flags & BGE_PHY_FIBER_TBI && 3089 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) { 3090 uint32_t serdescfg; 3091 3092 serdescfg = CSR_READ_4(sc, BGE_SERDES_CFG); 3093 serdescfg = (serdescfg & ~0xFFF) | 0x880; 3094 CSR_WRITE_4(sc, BGE_SERDES_CFG, serdescfg); 3095 } 3096 3097 if (sc->bge_flags & BGE_PCIE && 3098 sc->bge_chipid != BGE_CHIPID_BCM5750_A0 && 3099 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5717 && 3100 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5785 && 3101 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM57765) { 3102 uint32_t v; 3103 3104 /* Enable PCI Express bug fix */ 3105 v = CSR_READ_4(sc, 0x7c00); 3106 CSR_WRITE_4(sc, 0x7c00, v | (1<<25)); 3107 } 3108 DELAY(10000); 3109 } 3110 3111 /* 3112 * Frame reception handling. This is called if there's a frame 3113 * on the receive return list. 3114 * 3115 * Note: we have to be able to handle two possibilities here: 3116 * 1) the frame is from the jumbo recieve ring 3117 * 2) the frame is from the standard receive ring 3118 */ 3119 3120 static void 3121 bge_rxeof(struct bge_softc *sc) 3122 { 3123 struct ifnet *ifp; 3124 uint16_t rx_prod, rx_cons; 3125 int stdcnt = 0, jumbocnt = 0; 3126 bus_dmamap_t dmamap; 3127 bus_addr_t offset, toff; 3128 bus_size_t tlen; 3129 int tosync; 3130 3131 rx_cons = sc->bge_rx_saved_considx; 3132 rx_prod = sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx; 3133 3134 /* Nothing to do */ 3135 if (rx_cons == rx_prod) 3136 return; 3137 3138 ifp = &sc->ethercom.ec_if; 3139 3140 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 3141 offsetof(struct bge_ring_data, bge_status_block), 3142 sizeof (struct bge_status_block), 3143 BUS_DMASYNC_POSTREAD); 3144 3145 offset = offsetof(struct bge_ring_data, bge_rx_return_ring); 3146 tosync = rx_prod - rx_cons; 3147 3148 #if NRND > 0 3149 if (tosync != 0 && RND_ENABLED(&sc->rnd_source)) 3150 rnd_add_uint32(&sc->rnd_source, tosync); 3151 #endif 3152 3153 toff = offset + (rx_cons * sizeof (struct bge_rx_bd)); 3154 3155 if (tosync < 0) { 3156 tlen = (sc->bge_return_ring_cnt - rx_cons) * 3157 sizeof (struct bge_rx_bd); 3158 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 3159 toff, tlen, BUS_DMASYNC_POSTREAD); 3160 tosync = -tosync; 3161 } 3162 3163 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 3164 offset, tosync * sizeof (struct bge_rx_bd), 3165 BUS_DMASYNC_POSTREAD); 3166 3167 while (rx_cons != rx_prod) { 3168 struct bge_rx_bd *cur_rx; 3169 uint32_t rxidx; 3170 struct mbuf *m = NULL; 3171 3172 cur_rx = &sc->bge_rdata->bge_rx_return_ring[rx_cons]; 3173 3174 rxidx = cur_rx->bge_idx; 3175 BGE_INC(rx_cons, sc->bge_return_ring_cnt); 3176 3177 if (cur_rx->bge_flags & BGE_RXBDFLAG_JUMBO_RING) { 3178 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT); 3179 m = sc->bge_cdata.bge_rx_jumbo_chain[rxidx]; 3180 sc->bge_cdata.bge_rx_jumbo_chain[rxidx] = NULL; 3181 jumbocnt++; 3182 bus_dmamap_sync(sc->bge_dmatag, 3183 sc->bge_cdata.bge_rx_jumbo_map, 3184 mtod(m, char *) - (char *)sc->bge_cdata.bge_jumbo_buf, 3185 BGE_JLEN, BUS_DMASYNC_POSTREAD); 3186 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 3187 ifp->if_ierrors++; 3188 bge_newbuf_jumbo(sc, sc->bge_jumbo, m); 3189 continue; 3190 } 3191 if (bge_newbuf_jumbo(sc, sc->bge_jumbo, 3192 NULL)== ENOBUFS) { 3193 ifp->if_ierrors++; 3194 bge_newbuf_jumbo(sc, sc->bge_jumbo, m); 3195 continue; 3196 } 3197 } else { 3198 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT); 3199 m = sc->bge_cdata.bge_rx_std_chain[rxidx]; 3200 3201 sc->bge_cdata.bge_rx_std_chain[rxidx] = NULL; 3202 stdcnt++; 3203 dmamap = sc->bge_cdata.bge_rx_std_map[rxidx]; 3204 sc->bge_cdata.bge_rx_std_map[rxidx] = 0; 3205 bus_dmamap_sync(sc->bge_dmatag, dmamap, 0, 3206 dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 3207 bus_dmamap_unload(sc->bge_dmatag, dmamap); 3208 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 3209 ifp->if_ierrors++; 3210 bge_newbuf_std(sc, sc->bge_std, m, dmamap); 3211 continue; 3212 } 3213 if (bge_newbuf_std(sc, sc->bge_std, 3214 NULL, dmamap) == ENOBUFS) { 3215 ifp->if_ierrors++; 3216 bge_newbuf_std(sc, sc->bge_std, m, dmamap); 3217 continue; 3218 } 3219 } 3220 3221 ifp->if_ipackets++; 3222 #ifndef __NO_STRICT_ALIGNMENT 3223 /* 3224 * XXX: if the 5701 PCIX-Rx-DMA workaround is in effect, 3225 * the Rx buffer has the layer-2 header unaligned. 3226 * If our CPU requires alignment, re-align by copying. 3227 */ 3228 if (sc->bge_flags & BGE_RX_ALIGNBUG) { 3229 memmove(mtod(m, char *) + ETHER_ALIGN, m->m_data, 3230 cur_rx->bge_len); 3231 m->m_data += ETHER_ALIGN; 3232 } 3233 #endif 3234 3235 m->m_pkthdr.len = m->m_len = cur_rx->bge_len - ETHER_CRC_LEN; 3236 m->m_pkthdr.rcvif = ifp; 3237 3238 /* 3239 * Handle BPF listeners. Let the BPF user see the packet. 3240 */ 3241 if (ifp->if_bpf) 3242 bpf_ops->bpf_mtap(ifp->if_bpf, m); 3243 3244 m->m_pkthdr.csum_flags = M_CSUM_IPv4; 3245 3246 if ((cur_rx->bge_ip_csum ^ 0xffff) != 0) 3247 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 3248 /* 3249 * Rx transport checksum-offload may also 3250 * have bugs with packets which, when transmitted, 3251 * were `runts' requiring padding. 3252 */ 3253 if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM && 3254 (/* (sc->_bge_quirks & BGE_QUIRK_SHORT_CKSUM_BUG) == 0 ||*/ 3255 m->m_pkthdr.len >= ETHER_MIN_NOPAD)) { 3256 m->m_pkthdr.csum_data = 3257 cur_rx->bge_tcp_udp_csum; 3258 m->m_pkthdr.csum_flags |= 3259 (M_CSUM_TCPv4|M_CSUM_UDPv4| 3260 M_CSUM_DATA|M_CSUM_NO_PSEUDOHDR); 3261 } 3262 3263 /* 3264 * If we received a packet with a vlan tag, pass it 3265 * to vlan_input() instead of ether_input(). 3266 */ 3267 if (cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) { 3268 VLAN_INPUT_TAG(ifp, m, cur_rx->bge_vlan_tag, continue); 3269 } 3270 3271 (*ifp->if_input)(ifp, m); 3272 } 3273 3274 sc->bge_rx_saved_considx = rx_cons; 3275 bge_writembx(sc, BGE_MBX_RX_CONS0_LO, sc->bge_rx_saved_considx); 3276 if (stdcnt) 3277 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std); 3278 if (jumbocnt) 3279 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo); 3280 } 3281 3282 static void 3283 bge_txeof(struct bge_softc *sc) 3284 { 3285 struct bge_tx_bd *cur_tx = NULL; 3286 struct ifnet *ifp; 3287 struct txdmamap_pool_entry *dma; 3288 bus_addr_t offset, toff; 3289 bus_size_t tlen; 3290 int tosync; 3291 struct mbuf *m; 3292 3293 ifp = &sc->ethercom.ec_if; 3294 3295 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 3296 offsetof(struct bge_ring_data, bge_status_block), 3297 sizeof (struct bge_status_block), 3298 BUS_DMASYNC_POSTREAD); 3299 3300 offset = offsetof(struct bge_ring_data, bge_tx_ring); 3301 tosync = sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx - 3302 sc->bge_tx_saved_considx; 3303 3304 #if NRND > 0 3305 if (tosync != 0 && RND_ENABLED(&sc->rnd_source)) 3306 rnd_add_uint32(&sc->rnd_source, tosync); 3307 #endif 3308 3309 toff = offset + (sc->bge_tx_saved_considx * sizeof (struct bge_tx_bd)); 3310 3311 if (tosync < 0) { 3312 tlen = (BGE_TX_RING_CNT - sc->bge_tx_saved_considx) * 3313 sizeof (struct bge_tx_bd); 3314 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 3315 toff, tlen, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 3316 tosync = -tosync; 3317 } 3318 3319 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 3320 offset, tosync * sizeof (struct bge_tx_bd), 3321 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 3322 3323 /* 3324 * Go through our tx ring and free mbufs for those 3325 * frames that have been sent. 3326 */ 3327 while (sc->bge_tx_saved_considx != 3328 sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx) { 3329 uint32_t idx = 0; 3330 3331 idx = sc->bge_tx_saved_considx; 3332 cur_tx = &sc->bge_rdata->bge_tx_ring[idx]; 3333 if (cur_tx->bge_flags & BGE_TXBDFLAG_END) 3334 ifp->if_opackets++; 3335 m = sc->bge_cdata.bge_tx_chain[idx]; 3336 if (m != NULL) { 3337 sc->bge_cdata.bge_tx_chain[idx] = NULL; 3338 dma = sc->txdma[idx]; 3339 bus_dmamap_sync(sc->bge_dmatag, dma->dmamap, 0, 3340 dma->dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 3341 bus_dmamap_unload(sc->bge_dmatag, dma->dmamap); 3342 SLIST_INSERT_HEAD(&sc->txdma_list, dma, link); 3343 sc->txdma[idx] = NULL; 3344 3345 m_freem(m); 3346 } 3347 sc->bge_txcnt--; 3348 BGE_INC(sc->bge_tx_saved_considx, BGE_TX_RING_CNT); 3349 ifp->if_timer = 0; 3350 } 3351 3352 if (cur_tx != NULL) 3353 ifp->if_flags &= ~IFF_OACTIVE; 3354 } 3355 3356 static int 3357 bge_intr(void *xsc) 3358 { 3359 struct bge_softc *sc; 3360 struct ifnet *ifp; 3361 uint32_t statusword; 3362 3363 sc = xsc; 3364 ifp = &sc->ethercom.ec_if; 3365 3366 /* It is possible for the interrupt to arrive before 3367 * the status block is updated prior to the interrupt. 3368 * Reading the PCI State register will confirm whether the 3369 * interrupt is ours and will flush the status block. 3370 */ 3371 3372 /* read status word from status block */ 3373 statusword = sc->bge_rdata->bge_status_block.bge_status; 3374 3375 if ((statusword & BGE_STATFLAG_UPDATED) || 3376 (!(CSR_READ_4(sc, BGE_PCI_PCISTATE) & BGE_PCISTATE_INTR_NOT_ACTIVE))) { 3377 /* Ack interrupt and stop others from occuring. */ 3378 bge_writembx(sc, BGE_MBX_IRQ0_LO, 1); 3379 3380 BGE_EVCNT_INCR(sc->bge_ev_intr); 3381 3382 /* clear status word */ 3383 sc->bge_rdata->bge_status_block.bge_status = 0; 3384 3385 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 3386 statusword & BGE_STATFLAG_LINKSTATE_CHANGED || 3387 BGE_STS_BIT(sc, BGE_STS_LINK_EVT)) 3388 bge_link_upd(sc); 3389 3390 if (ifp->if_flags & IFF_RUNNING) { 3391 /* Check RX return ring producer/consumer */ 3392 bge_rxeof(sc); 3393 3394 /* Check TX ring producer/consumer */ 3395 bge_txeof(sc); 3396 } 3397 3398 if (sc->bge_pending_rxintr_change) { 3399 uint32_t rx_ticks = sc->bge_rx_coal_ticks; 3400 uint32_t rx_bds = sc->bge_rx_max_coal_bds; 3401 uint32_t junk; 3402 3403 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, rx_ticks); 3404 DELAY(10); 3405 junk = CSR_READ_4(sc, BGE_HCC_RX_COAL_TICKS); 3406 3407 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, rx_bds); 3408 DELAY(10); 3409 junk = CSR_READ_4(sc, BGE_HCC_RX_MAX_COAL_BDS); 3410 3411 sc->bge_pending_rxintr_change = 0; 3412 } 3413 bge_handle_events(sc); 3414 3415 /* Re-enable interrupts. */ 3416 bge_writembx(sc, BGE_MBX_IRQ0_LO, 0); 3417 3418 if (ifp->if_flags & IFF_RUNNING && !IFQ_IS_EMPTY(&ifp->if_snd)) 3419 bge_start(ifp); 3420 3421 return 1; 3422 } else 3423 return 0; 3424 } 3425 3426 static void 3427 bge_tick(void *xsc) 3428 { 3429 struct bge_softc *sc = xsc; 3430 struct mii_data *mii = &sc->bge_mii; 3431 int s; 3432 3433 s = splnet(); 3434 3435 if (BGE_IS_5705_PLUS(sc)) 3436 bge_stats_update_regs(sc); 3437 else 3438 bge_stats_update(sc); 3439 3440 if (sc->bge_flags & BGE_PHY_FIBER_TBI) { 3441 /* 3442 * Since in TBI mode auto-polling can't be used we should poll 3443 * link status manually. Here we register pending link event 3444 * and trigger interrupt. 3445 */ 3446 BGE_STS_SETBIT(sc, BGE_STS_LINK_EVT); 3447 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET); 3448 } else { 3449 /* 3450 * Do not touch PHY if we have link up. This could break 3451 * IPMI/ASF mode or produce extra input errors. 3452 * (extra input errors was reported for bcm5701 & bcm5704). 3453 */ 3454 if (!BGE_STS_BIT(sc, BGE_STS_LINK)) 3455 mii_tick(mii); 3456 } 3457 3458 callout_reset(&sc->bge_timeout, hz, bge_tick, sc); 3459 3460 splx(s); 3461 } 3462 3463 static void 3464 bge_stats_update_regs(struct bge_softc *sc) 3465 { 3466 struct ifnet *ifp = &sc->ethercom.ec_if; 3467 3468 ifp->if_collisions += CSR_READ_4(sc, BGE_MAC_STATS + 3469 offsetof(struct bge_mac_stats_regs, etherStatsCollisions)); 3470 3471 ifp->if_ierrors += CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_DROPS); 3472 ifp->if_ierrors += CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_ERRORS); 3473 ifp->if_ierrors += CSR_READ_4(sc, BGE_RXLP_LOCSTAT_OUT_OF_BDS); 3474 } 3475 3476 static void 3477 bge_stats_update(struct bge_softc *sc) 3478 { 3479 struct ifnet *ifp = &sc->ethercom.ec_if; 3480 bus_size_t stats = BGE_MEMWIN_START + BGE_STATS_BLOCK; 3481 3482 #define READ_STAT(sc, stats, stat) \ 3483 CSR_READ_4(sc, stats + offsetof(struct bge_stats, stat)) 3484 3485 ifp->if_collisions += 3486 (READ_STAT(sc, stats, dot3StatsSingleCollisionFrames.bge_addr_lo) + 3487 READ_STAT(sc, stats, dot3StatsMultipleCollisionFrames.bge_addr_lo) + 3488 READ_STAT(sc, stats, dot3StatsExcessiveCollisions.bge_addr_lo) + 3489 READ_STAT(sc, stats, dot3StatsLateCollisions.bge_addr_lo)) - 3490 ifp->if_collisions; 3491 3492 BGE_EVCNT_UPD(sc->bge_ev_tx_xoff, 3493 READ_STAT(sc, stats, outXoffSent.bge_addr_lo)); 3494 BGE_EVCNT_UPD(sc->bge_ev_tx_xon, 3495 READ_STAT(sc, stats, outXonSent.bge_addr_lo)); 3496 BGE_EVCNT_UPD(sc->bge_ev_rx_xoff, 3497 READ_STAT(sc, stats, 3498 xoffPauseFramesReceived.bge_addr_lo)); 3499 BGE_EVCNT_UPD(sc->bge_ev_rx_xon, 3500 READ_STAT(sc, stats, xonPauseFramesReceived.bge_addr_lo)); 3501 BGE_EVCNT_UPD(sc->bge_ev_rx_macctl, 3502 READ_STAT(sc, stats, 3503 macControlFramesReceived.bge_addr_lo)); 3504 BGE_EVCNT_UPD(sc->bge_ev_xoffentered, 3505 READ_STAT(sc, stats, xoffStateEntered.bge_addr_lo)); 3506 3507 #undef READ_STAT 3508 3509 #ifdef notdef 3510 ifp->if_collisions += 3511 (sc->bge_rdata->bge_info.bge_stats.dot3StatsSingleCollisionFrames + 3512 sc->bge_rdata->bge_info.bge_stats.dot3StatsMultipleCollisionFrames + 3513 sc->bge_rdata->bge_info.bge_stats.dot3StatsExcessiveCollisions + 3514 sc->bge_rdata->bge_info.bge_stats.dot3StatsLateCollisions) - 3515 ifp->if_collisions; 3516 #endif 3517 } 3518 3519 /* 3520 * Pad outbound frame to ETHER_MIN_NOPAD for an unusual reason. 3521 * The bge hardware will pad out Tx runts to ETHER_MIN_NOPAD, 3522 * but when such padded frames employ the bge IP/TCP checksum offload, 3523 * the hardware checksum assist gives incorrect results (possibly 3524 * from incorporating its own padding into the UDP/TCP checksum; who knows). 3525 * If we pad such runts with zeros, the onboard checksum comes out correct. 3526 */ 3527 static inline int 3528 bge_cksum_pad(struct mbuf *pkt) 3529 { 3530 struct mbuf *last = NULL; 3531 int padlen; 3532 3533 padlen = ETHER_MIN_NOPAD - pkt->m_pkthdr.len; 3534 3535 /* if there's only the packet-header and we can pad there, use it. */ 3536 if (pkt->m_pkthdr.len == pkt->m_len && 3537 M_TRAILINGSPACE(pkt) >= padlen) { 3538 last = pkt; 3539 } else { 3540 /* 3541 * Walk packet chain to find last mbuf. We will either 3542 * pad there, or append a new mbuf and pad it 3543 * (thus perhaps avoiding the bcm5700 dma-min bug). 3544 */ 3545 for (last = pkt; last->m_next != NULL; last = last->m_next) { 3546 continue; /* do nothing */ 3547 } 3548 3549 /* `last' now points to last in chain. */ 3550 if (M_TRAILINGSPACE(last) < padlen) { 3551 /* Allocate new empty mbuf, pad it. Compact later. */ 3552 struct mbuf *n; 3553 MGET(n, M_DONTWAIT, MT_DATA); 3554 if (n == NULL) 3555 return ENOBUFS; 3556 n->m_len = 0; 3557 last->m_next = n; 3558 last = n; 3559 } 3560 } 3561 3562 KDASSERT(!M_READONLY(last)); 3563 KDASSERT(M_TRAILINGSPACE(last) >= padlen); 3564 3565 /* Now zero the pad area, to avoid the bge cksum-assist bug */ 3566 memset(mtod(last, char *) + last->m_len, 0, padlen); 3567 last->m_len += padlen; 3568 pkt->m_pkthdr.len += padlen; 3569 return 0; 3570 } 3571 3572 /* 3573 * Compact outbound packets to avoid bug with DMA segments less than 8 bytes. 3574 */ 3575 static inline int 3576 bge_compact_dma_runt(struct mbuf *pkt) 3577 { 3578 struct mbuf *m, *prev; 3579 int totlen, prevlen; 3580 3581 prev = NULL; 3582 totlen = 0; 3583 prevlen = -1; 3584 3585 for (m = pkt; m != NULL; prev = m,m = m->m_next) { 3586 int mlen = m->m_len; 3587 int shortfall = 8 - mlen ; 3588 3589 totlen += mlen; 3590 if (mlen == 0) { 3591 continue; 3592 } 3593 if (mlen >= 8) 3594 continue; 3595 3596 /* If we get here, mbuf data is too small for DMA engine. 3597 * Try to fix by shuffling data to prev or next in chain. 3598 * If that fails, do a compacting deep-copy of the whole chain. 3599 */ 3600 3601 /* Internal frag. If fits in prev, copy it there. */ 3602 if (prev && M_TRAILINGSPACE(prev) >= m->m_len) { 3603 memcpy(prev->m_data + prev->m_len, m->m_data, mlen); 3604 prev->m_len += mlen; 3605 m->m_len = 0; 3606 /* XXX stitch chain */ 3607 prev->m_next = m_free(m); 3608 m = prev; 3609 continue; 3610 } 3611 else if (m->m_next != NULL && 3612 M_TRAILINGSPACE(m) >= shortfall && 3613 m->m_next->m_len >= (8 + shortfall)) { 3614 /* m is writable and have enough data in next, pull up. */ 3615 3616 memcpy(m->m_data + m->m_len, m->m_next->m_data, 3617 shortfall); 3618 m->m_len += shortfall; 3619 m->m_next->m_len -= shortfall; 3620 m->m_next->m_data += shortfall; 3621 } 3622 else if (m->m_next == NULL || 1) { 3623 /* Got a runt at the very end of the packet. 3624 * borrow data from the tail of the preceding mbuf and 3625 * update its length in-place. (The original data is still 3626 * valid, so we can do this even if prev is not writable.) 3627 */ 3628 3629 /* if we'd make prev a runt, just move all of its data. */ 3630 KASSERT(prev != NULL /*, ("runt but null PREV")*/); 3631 KASSERT(prev->m_len >= 8 /*, ("runt prev")*/); 3632 3633 if ((prev->m_len - shortfall) < 8) 3634 shortfall = prev->m_len; 3635 3636 #ifdef notyet /* just do the safe slow thing for now */ 3637 if (!M_READONLY(m)) { 3638 if (M_LEADINGSPACE(m) < shorfall) { 3639 void *m_dat; 3640 m_dat = (m->m_flags & M_PKTHDR) ? 3641 m->m_pktdat : m->dat; 3642 memmove(m_dat, mtod(m, void*), m->m_len); 3643 m->m_data = m_dat; 3644 } 3645 } else 3646 #endif /* just do the safe slow thing */ 3647 { 3648 struct mbuf * n = NULL; 3649 int newprevlen = prev->m_len - shortfall; 3650 3651 MGET(n, M_NOWAIT, MT_DATA); 3652 if (n == NULL) 3653 return ENOBUFS; 3654 KASSERT(m->m_len + shortfall < MLEN 3655 /*, 3656 ("runt %d +prev %d too big\n", m->m_len, shortfall)*/); 3657 3658 /* first copy the data we're stealing from prev */ 3659 memcpy(n->m_data, prev->m_data + newprevlen, 3660 shortfall); 3661 3662 /* update prev->m_len accordingly */ 3663 prev->m_len -= shortfall; 3664 3665 /* copy data from runt m */ 3666 memcpy(n->m_data + shortfall, m->m_data, 3667 m->m_len); 3668 3669 /* n holds what we stole from prev, plus m */ 3670 n->m_len = shortfall + m->m_len; 3671 3672 /* stitch n into chain and free m */ 3673 n->m_next = m->m_next; 3674 prev->m_next = n; 3675 /* KASSERT(m->m_next == NULL); */ 3676 m->m_next = NULL; 3677 m_free(m); 3678 m = n; /* for continuing loop */ 3679 } 3680 } 3681 prevlen = m->m_len; 3682 } 3683 return 0; 3684 } 3685 3686 /* 3687 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data 3688 * pointers to descriptors. 3689 */ 3690 static int 3691 bge_encap(struct bge_softc *sc, struct mbuf *m_head, uint32_t *txidx) 3692 { 3693 struct bge_tx_bd *f = NULL; 3694 uint32_t frag, cur; 3695 uint16_t csum_flags = 0; 3696 uint16_t txbd_tso_flags = 0; 3697 struct txdmamap_pool_entry *dma; 3698 bus_dmamap_t dmamap; 3699 int i = 0; 3700 struct m_tag *mtag; 3701 int use_tso, maxsegsize, error; 3702 3703 cur = frag = *txidx; 3704 3705 if (m_head->m_pkthdr.csum_flags) { 3706 if (m_head->m_pkthdr.csum_flags & M_CSUM_IPv4) 3707 csum_flags |= BGE_TXBDFLAG_IP_CSUM; 3708 if (m_head->m_pkthdr.csum_flags & (M_CSUM_TCPv4|M_CSUM_UDPv4)) 3709 csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM; 3710 } 3711 3712 /* 3713 * If we were asked to do an outboard checksum, and the NIC 3714 * has the bug where it sometimes adds in the Ethernet padding, 3715 * explicitly pad with zeros so the cksum will be correct either way. 3716 * (For now, do this for all chip versions, until newer 3717 * are confirmed to not require the workaround.) 3718 */ 3719 if ((csum_flags & BGE_TXBDFLAG_TCP_UDP_CSUM) == 0 || 3720 #ifdef notyet 3721 (sc->bge_quirks & BGE_QUIRK_SHORT_CKSUM_BUG) == 0 || 3722 #endif 3723 m_head->m_pkthdr.len >= ETHER_MIN_NOPAD) 3724 goto check_dma_bug; 3725 3726 if (bge_cksum_pad(m_head) != 0) 3727 return ENOBUFS; 3728 3729 check_dma_bug: 3730 if (!(BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX)) 3731 goto doit; 3732 3733 /* 3734 * bcm5700 Revision B silicon cannot handle DMA descriptors with 3735 * less than eight bytes. If we encounter a teeny mbuf 3736 * at the end of a chain, we can pad. Otherwise, copy. 3737 */ 3738 if (bge_compact_dma_runt(m_head) != 0) 3739 return ENOBUFS; 3740 3741 doit: 3742 dma = SLIST_FIRST(&sc->txdma_list); 3743 if (dma == NULL) 3744 return ENOBUFS; 3745 dmamap = dma->dmamap; 3746 3747 /* 3748 * Set up any necessary TSO state before we start packing... 3749 */ 3750 use_tso = (m_head->m_pkthdr.csum_flags & M_CSUM_TSOv4) != 0; 3751 if (!use_tso) { 3752 maxsegsize = 0; 3753 } else { /* TSO setup */ 3754 unsigned mss; 3755 struct ether_header *eh; 3756 unsigned ip_tcp_hlen, iptcp_opt_words, tcp_seg_flags, offset; 3757 struct mbuf * m0 = m_head; 3758 struct ip *ip; 3759 struct tcphdr *th; 3760 int iphl, hlen; 3761 3762 /* 3763 * XXX It would be nice if the mbuf pkthdr had offset 3764 * fields for the protocol headers. 3765 */ 3766 3767 eh = mtod(m0, struct ether_header *); 3768 switch (htons(eh->ether_type)) { 3769 case ETHERTYPE_IP: 3770 offset = ETHER_HDR_LEN; 3771 break; 3772 3773 case ETHERTYPE_VLAN: 3774 offset = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 3775 break; 3776 3777 default: 3778 /* 3779 * Don't support this protocol or encapsulation. 3780 */ 3781 return ENOBUFS; 3782 } 3783 3784 /* 3785 * TCP/IP headers are in the first mbuf; we can do 3786 * this the easy way. 3787 */ 3788 iphl = M_CSUM_DATA_IPv4_IPHL(m0->m_pkthdr.csum_data); 3789 hlen = iphl + offset; 3790 if (__predict_false(m0->m_len < 3791 (hlen + sizeof(struct tcphdr)))) { 3792 3793 aprint_debug_dev(sc->bge_dev, 3794 "TSO: hard case m0->m_len == %d < ip/tcp hlen %zd," 3795 "not handled yet\n", 3796 m0->m_len, hlen+ sizeof(struct tcphdr)); 3797 #ifdef NOTYET 3798 /* 3799 * XXX jonathan (at) NetBSD.org: untested. 3800 * how to force this branch to be taken? 3801 */ 3802 BGE_EVCNT_INCR(&sc->sc_ev_txtsopain); 3803 3804 m_copydata(m0, offset, sizeof(ip), &ip); 3805 m_copydata(m0, hlen, sizeof(th), &th); 3806 3807 ip.ip_len = 0; 3808 3809 m_copyback(m0, hlen + offsetof(struct ip, ip_len), 3810 sizeof(ip.ip_len), &ip.ip_len); 3811 3812 th.th_sum = in_cksum_phdr(ip.ip_src.s_addr, 3813 ip.ip_dst.s_addr, htons(IPPROTO_TCP)); 3814 3815 m_copyback(m0, hlen + offsetof(struct tcphdr, th_sum), 3816 sizeof(th.th_sum), &th.th_sum); 3817 3818 hlen += th.th_off << 2; 3819 iptcp_opt_words = hlen; 3820 #else 3821 /* 3822 * if_wm "hard" case not yet supported, can we not 3823 * mandate it out of existence? 3824 */ 3825 (void) ip; (void)th; (void) ip_tcp_hlen; 3826 3827 return ENOBUFS; 3828 #endif 3829 } else { 3830 ip = (struct ip *) (mtod(m0, char *) + offset); 3831 th = (struct tcphdr *) (mtod(m0, char *) + hlen); 3832 ip_tcp_hlen = iphl + (th->th_off << 2); 3833 3834 /* Total IP/TCP options, in 32-bit words */ 3835 iptcp_opt_words = (ip_tcp_hlen 3836 - sizeof(struct tcphdr) 3837 - sizeof(struct ip)) >> 2; 3838 } 3839 if (BGE_IS_5750_OR_BEYOND(sc)) { 3840 th->th_sum = 0; 3841 csum_flags &= ~(BGE_TXBDFLAG_TCP_UDP_CSUM); 3842 } else { 3843 /* 3844 * XXX jonathan (at) NetBSD.org: 5705 untested. 3845 * Requires TSO firmware patch for 5701/5703/5704. 3846 */ 3847 th->th_sum = in_cksum_phdr(ip->ip_src.s_addr, 3848 ip->ip_dst.s_addr, htons(IPPROTO_TCP)); 3849 } 3850 3851 mss = m_head->m_pkthdr.segsz; 3852 txbd_tso_flags |= 3853 BGE_TXBDFLAG_CPU_PRE_DMA | 3854 BGE_TXBDFLAG_CPU_POST_DMA; 3855 3856 /* 3857 * Our NIC TSO-assist assumes TSO has standard, optionless 3858 * IPv4 and TCP headers, which total 40 bytes. By default, 3859 * the NIC copies 40 bytes of IP/TCP header from the 3860 * supplied header into the IP/TCP header portion of 3861 * each post-TSO-segment. If the supplied packet has IP or 3862 * TCP options, we need to tell the NIC to copy those extra 3863 * bytes into each post-TSO header, in addition to the normal 3864 * 40-byte IP/TCP header (and to leave space accordingly). 3865 * Unfortunately, the driver encoding of option length 3866 * varies across different ASIC families. 3867 */ 3868 tcp_seg_flags = 0; 3869 if (iptcp_opt_words) { 3870 if (BGE_IS_5705_PLUS(sc)) { 3871 tcp_seg_flags = 3872 iptcp_opt_words << 11; 3873 } else { 3874 txbd_tso_flags |= 3875 iptcp_opt_words << 12; 3876 } 3877 } 3878 maxsegsize = mss | tcp_seg_flags; 3879 ip->ip_len = htons(mss + ip_tcp_hlen); 3880 3881 } /* TSO setup */ 3882 3883 /* 3884 * Start packing the mbufs in this chain into 3885 * the fragment pointers. Stop when we run out 3886 * of fragments or hit the end of the mbuf chain. 3887 */ 3888 error = bus_dmamap_load_mbuf(sc->bge_dmatag, dmamap, m_head, 3889 BUS_DMA_NOWAIT); 3890 if (error) 3891 return ENOBUFS; 3892 /* 3893 * Sanity check: avoid coming within 16 descriptors 3894 * of the end of the ring. 3895 */ 3896 if (dmamap->dm_nsegs > (BGE_TX_RING_CNT - sc->bge_txcnt - 16)) { 3897 BGE_TSO_PRINTF(("%s: " 3898 " dmamap_load_mbuf too close to ring wrap\n", 3899 device_xname(sc->bge_dev))); 3900 goto fail_unload; 3901 } 3902 3903 mtag = sc->ethercom.ec_nvlans ? 3904 m_tag_find(m_head, PACKET_TAG_VLAN, NULL) : NULL; 3905 3906 3907 /* Iterate over dmap-map fragments. */ 3908 for (i = 0; i < dmamap->dm_nsegs; i++) { 3909 f = &sc->bge_rdata->bge_tx_ring[frag]; 3910 if (sc->bge_cdata.bge_tx_chain[frag] != NULL) 3911 break; 3912 3913 BGE_HOSTADDR(f->bge_addr, dmamap->dm_segs[i].ds_addr); 3914 f->bge_len = dmamap->dm_segs[i].ds_len; 3915 3916 /* 3917 * For 5751 and follow-ons, for TSO we must turn 3918 * off checksum-assist flag in the tx-descr, and 3919 * supply the ASIC-revision-specific encoding 3920 * of TSO flags and segsize. 3921 */ 3922 if (use_tso) { 3923 if (BGE_IS_5750_OR_BEYOND(sc) || i == 0) { 3924 f->bge_rsvd = maxsegsize; 3925 f->bge_flags = csum_flags | txbd_tso_flags; 3926 } else { 3927 f->bge_rsvd = 0; 3928 f->bge_flags = 3929 (csum_flags | txbd_tso_flags) & 0x0fff; 3930 } 3931 } else { 3932 f->bge_rsvd = 0; 3933 f->bge_flags = csum_flags; 3934 } 3935 3936 if (mtag != NULL) { 3937 f->bge_flags |= BGE_TXBDFLAG_VLAN_TAG; 3938 f->bge_vlan_tag = VLAN_TAG_VALUE(mtag); 3939 } else { 3940 f->bge_vlan_tag = 0; 3941 } 3942 cur = frag; 3943 BGE_INC(frag, BGE_TX_RING_CNT); 3944 } 3945 3946 if (i < dmamap->dm_nsegs) { 3947 BGE_TSO_PRINTF(("%s: reached %d < dm_nsegs %d\n", 3948 device_xname(sc->bge_dev), i, dmamap->dm_nsegs)); 3949 goto fail_unload; 3950 } 3951 3952 bus_dmamap_sync(sc->bge_dmatag, dmamap, 0, dmamap->dm_mapsize, 3953 BUS_DMASYNC_PREWRITE); 3954 3955 if (frag == sc->bge_tx_saved_considx) { 3956 BGE_TSO_PRINTF(("%s: frag %d = wrapped id %d?\n", 3957 device_xname(sc->bge_dev), frag, sc->bge_tx_saved_considx)); 3958 3959 goto fail_unload; 3960 } 3961 3962 sc->bge_rdata->bge_tx_ring[cur].bge_flags |= BGE_TXBDFLAG_END; 3963 sc->bge_cdata.bge_tx_chain[cur] = m_head; 3964 SLIST_REMOVE_HEAD(&sc->txdma_list, link); 3965 sc->txdma[cur] = dma; 3966 sc->bge_txcnt += dmamap->dm_nsegs; 3967 3968 *txidx = frag; 3969 3970 return 0; 3971 3972 fail_unload: 3973 bus_dmamap_unload(sc->bge_dmatag, dmamap); 3974 3975 return ENOBUFS; 3976 } 3977 3978 /* 3979 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 3980 * to the mbuf data regions directly in the transmit descriptors. 3981 */ 3982 static void 3983 bge_start(struct ifnet *ifp) 3984 { 3985 struct bge_softc *sc; 3986 struct mbuf *m_head = NULL; 3987 uint32_t prodidx; 3988 int pkts = 0; 3989 3990 sc = ifp->if_softc; 3991 3992 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 3993 return; 3994 3995 prodidx = sc->bge_tx_prodidx; 3996 3997 while (sc->bge_cdata.bge_tx_chain[prodidx] == NULL) { 3998 IFQ_POLL(&ifp->if_snd, m_head); 3999 if (m_head == NULL) 4000 break; 4001 4002 #if 0 4003 /* 4004 * XXX 4005 * safety overkill. If this is a fragmented packet chain 4006 * with delayed TCP/UDP checksums, then only encapsulate 4007 * it if we have enough descriptors to handle the entire 4008 * chain at once. 4009 * (paranoia -- may not actually be needed) 4010 */ 4011 if (m_head->m_flags & M_FIRSTFRAG && 4012 m_head->m_pkthdr.csum_flags & (CSUM_DELAY_DATA)) { 4013 if ((BGE_TX_RING_CNT - sc->bge_txcnt) < 4014 M_CSUM_DATA_IPv4_OFFSET(m_head->m_pkthdr.csum_data) + 16) { 4015 ifp->if_flags |= IFF_OACTIVE; 4016 break; 4017 } 4018 } 4019 #endif 4020 4021 /* 4022 * Pack the data into the transmit ring. If we 4023 * don't have room, set the OACTIVE flag and wait 4024 * for the NIC to drain the ring. 4025 */ 4026 if (bge_encap(sc, m_head, &prodidx)) { 4027 ifp->if_flags |= IFF_OACTIVE; 4028 break; 4029 } 4030 4031 /* now we are committed to transmit the packet */ 4032 IFQ_DEQUEUE(&ifp->if_snd, m_head); 4033 pkts++; 4034 4035 /* 4036 * If there's a BPF listener, bounce a copy of this frame 4037 * to him. 4038 */ 4039 if (ifp->if_bpf) 4040 bpf_ops->bpf_mtap(ifp->if_bpf, m_head); 4041 } 4042 if (pkts == 0) 4043 return; 4044 4045 /* Transmit */ 4046 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); 4047 /* 5700 b2 errata */ 4048 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX) 4049 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); 4050 4051 sc->bge_tx_prodidx = prodidx; 4052 4053 /* 4054 * Set a timeout in case the chip goes out to lunch. 4055 */ 4056 ifp->if_timer = 5; 4057 } 4058 4059 static int 4060 bge_init(struct ifnet *ifp) 4061 { 4062 struct bge_softc *sc = ifp->if_softc; 4063 const uint16_t *m; 4064 int s, error = 0; 4065 4066 s = splnet(); 4067 4068 ifp = &sc->ethercom.ec_if; 4069 4070 /* Cancel pending I/O and flush buffers. */ 4071 bge_stop(ifp, 0); 4072 bge_reset(sc); 4073 bge_chipinit(sc); 4074 4075 /* 4076 * Init the various state machines, ring 4077 * control blocks and firmware. 4078 */ 4079 error = bge_blockinit(sc); 4080 if (error != 0) { 4081 aprint_error_dev(sc->bge_dev, "initialization error %d\n", 4082 error); 4083 splx(s); 4084 return error; 4085 } 4086 4087 ifp = &sc->ethercom.ec_if; 4088 4089 /* Specify MTU. */ 4090 CSR_WRITE_4(sc, BGE_RX_MTU, ifp->if_mtu + 4091 ETHER_HDR_LEN + ETHER_CRC_LEN + ETHER_VLAN_ENCAP_LEN); 4092 4093 /* Load our MAC address. */ 4094 m = (const uint16_t *)&(CLLADDR(ifp->if_sadl)[0]); 4095 CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0])); 4096 CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, (htons(m[1]) << 16) | htons(m[2])); 4097 4098 /* Enable or disable promiscuous mode as needed. */ 4099 if (ifp->if_flags & IFF_PROMISC) { 4100 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 4101 } else { 4102 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 4103 } 4104 4105 /* Program multicast filter. */ 4106 bge_setmulti(sc); 4107 4108 /* Init RX ring. */ 4109 bge_init_rx_ring_std(sc); 4110 4111 /* 4112 * Workaround for a bug in 5705 ASIC rev A0. Poll the NIC's 4113 * memory to insure that the chip has in fact read the first 4114 * entry of the ring. 4115 */ 4116 if (sc->bge_chipid == BGE_CHIPID_BCM5705_A0) { 4117 uint32_t v, i; 4118 for (i = 0; i < 10; i++) { 4119 DELAY(20); 4120 v = bge_readmem_ind(sc, BGE_STD_RX_RINGS + 8); 4121 if (v == (MCLBYTES - ETHER_ALIGN)) 4122 break; 4123 } 4124 if (i == 10) 4125 aprint_error_dev(sc->bge_dev, 4126 "5705 A0 chip failed to load RX ring\n"); 4127 } 4128 4129 /* Init jumbo RX ring. */ 4130 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 4131 bge_init_rx_ring_jumbo(sc); 4132 4133 /* Init our RX return ring index */ 4134 sc->bge_rx_saved_considx = 0; 4135 4136 /* Init TX ring. */ 4137 bge_init_tx_ring(sc); 4138 4139 /* Turn on transmitter */ 4140 BGE_SETBIT(sc, BGE_TX_MODE, BGE_TXMODE_ENABLE); 4141 4142 /* Turn on receiver */ 4143 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE); 4144 4145 CSR_WRITE_4(sc, BGE_MAX_RX_FRAME_LOWAT, 2); 4146 4147 /* Tell firmware we're alive. */ 4148 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 4149 4150 /* Enable host interrupts. */ 4151 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA); 4152 BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); 4153 bge_writembx(sc, BGE_MBX_IRQ0_LO, 0); 4154 4155 if ((error = bge_ifmedia_upd(ifp)) != 0) 4156 goto out; 4157 4158 ifp->if_flags |= IFF_RUNNING; 4159 ifp->if_flags &= ~IFF_OACTIVE; 4160 4161 callout_reset(&sc->bge_timeout, hz, bge_tick, sc); 4162 4163 out: 4164 splx(s); 4165 4166 return error; 4167 } 4168 4169 /* 4170 * Set media options. 4171 */ 4172 static int 4173 bge_ifmedia_upd(struct ifnet *ifp) 4174 { 4175 struct bge_softc *sc = ifp->if_softc; 4176 struct mii_data *mii = &sc->bge_mii; 4177 struct ifmedia *ifm = &sc->bge_ifmedia; 4178 int rc; 4179 4180 /* If this is a 1000baseX NIC, enable the TBI port. */ 4181 if (sc->bge_flags & BGE_PHY_FIBER_TBI) { 4182 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 4183 return EINVAL; 4184 switch (IFM_SUBTYPE(ifm->ifm_media)) { 4185 case IFM_AUTO: 4186 /* 4187 * The BCM5704 ASIC appears to have a special 4188 * mechanism for programming the autoneg 4189 * advertisement registers in TBI mode. 4190 */ 4191 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) { 4192 uint32_t sgdig; 4193 sgdig = CSR_READ_4(sc, BGE_SGDIG_STS); 4194 if (sgdig & BGE_SGDIGSTS_DONE) { 4195 CSR_WRITE_4(sc, BGE_TX_TBI_AUTONEG, 0); 4196 sgdig = CSR_READ_4(sc, BGE_SGDIG_CFG); 4197 sgdig |= BGE_SGDIGCFG_AUTO | 4198 BGE_SGDIGCFG_PAUSE_CAP | 4199 BGE_SGDIGCFG_ASYM_PAUSE; 4200 CSR_WRITE_4(sc, BGE_SGDIG_CFG, 4201 sgdig | BGE_SGDIGCFG_SEND); 4202 DELAY(5); 4203 CSR_WRITE_4(sc, BGE_SGDIG_CFG, sgdig); 4204 } 4205 } 4206 break; 4207 case IFM_1000_SX: 4208 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 4209 BGE_CLRBIT(sc, BGE_MAC_MODE, 4210 BGE_MACMODE_HALF_DUPLEX); 4211 } else { 4212 BGE_SETBIT(sc, BGE_MAC_MODE, 4213 BGE_MACMODE_HALF_DUPLEX); 4214 } 4215 break; 4216 default: 4217 return EINVAL; 4218 } 4219 /* XXX 802.3x flow control for 1000BASE-SX */ 4220 return 0; 4221 } 4222 4223 BGE_STS_SETBIT(sc, BGE_STS_LINK_EVT); 4224 if ((rc = mii_mediachg(mii)) == ENXIO) 4225 return 0; 4226 4227 /* 4228 * Force an interrupt so that we will call bge_link_upd 4229 * if needed and clear any pending link state attention. 4230 * Without this we are not getting any further interrupts 4231 * for link state changes and thus will not UP the link and 4232 * not be able to send in bge_start. The only way to get 4233 * things working was to receive a packet and get a RX intr. 4234 */ 4235 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 4236 sc->bge_flags & BGE_IS_5788) 4237 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET); 4238 else 4239 BGE_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW); 4240 4241 return rc; 4242 } 4243 4244 /* 4245 * Report current media status. 4246 */ 4247 static void 4248 bge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 4249 { 4250 struct bge_softc *sc = ifp->if_softc; 4251 struct mii_data *mii = &sc->bge_mii; 4252 4253 if (sc->bge_flags & BGE_PHY_FIBER_TBI) { 4254 ifmr->ifm_status = IFM_AVALID; 4255 ifmr->ifm_active = IFM_ETHER; 4256 if (CSR_READ_4(sc, BGE_MAC_STS) & 4257 BGE_MACSTAT_TBI_PCS_SYNCHED) 4258 ifmr->ifm_status |= IFM_ACTIVE; 4259 ifmr->ifm_active |= IFM_1000_SX; 4260 if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX) 4261 ifmr->ifm_active |= IFM_HDX; 4262 else 4263 ifmr->ifm_active |= IFM_FDX; 4264 return; 4265 } 4266 4267 mii_pollstat(mii); 4268 ifmr->ifm_status = mii->mii_media_status; 4269 ifmr->ifm_active = (mii->mii_media_active & ~IFM_ETH_FMASK) | 4270 sc->bge_flowflags; 4271 } 4272 4273 static int 4274 bge_ioctl(struct ifnet *ifp, u_long command, void *data) 4275 { 4276 struct bge_softc *sc = ifp->if_softc; 4277 struct ifreq *ifr = (struct ifreq *) data; 4278 int s, error = 0; 4279 struct mii_data *mii; 4280 4281 s = splnet(); 4282 4283 switch (command) { 4284 case SIOCSIFFLAGS: 4285 if ((error = ifioctl_common(ifp, command, data)) != 0) 4286 break; 4287 if (ifp->if_flags & IFF_UP) { 4288 /* 4289 * If only the state of the PROMISC flag changed, 4290 * then just use the 'set promisc mode' command 4291 * instead of reinitializing the entire NIC. Doing 4292 * a full re-init means reloading the firmware and 4293 * waiting for it to start up, which may take a 4294 * second or two. 4295 */ 4296 if (ifp->if_flags & IFF_RUNNING && 4297 ifp->if_flags & IFF_PROMISC && 4298 !(sc->bge_if_flags & IFF_PROMISC)) { 4299 BGE_SETBIT(sc, BGE_RX_MODE, 4300 BGE_RXMODE_RX_PROMISC); 4301 } else if (ifp->if_flags & IFF_RUNNING && 4302 !(ifp->if_flags & IFF_PROMISC) && 4303 sc->bge_if_flags & IFF_PROMISC) { 4304 BGE_CLRBIT(sc, BGE_RX_MODE, 4305 BGE_RXMODE_RX_PROMISC); 4306 } else if (!(sc->bge_if_flags & IFF_UP)) 4307 bge_init(ifp); 4308 } else { 4309 if (ifp->if_flags & IFF_RUNNING) 4310 bge_stop(ifp, 1); 4311 } 4312 sc->bge_if_flags = ifp->if_flags; 4313 error = 0; 4314 break; 4315 case SIOCSIFMEDIA: 4316 /* XXX Flow control is not supported for 1000BASE-SX */ 4317 if (sc->bge_flags & BGE_PHY_FIBER_TBI) { 4318 ifr->ifr_media &= ~IFM_ETH_FMASK; 4319 sc->bge_flowflags = 0; 4320 } 4321 4322 /* Flow control requires full-duplex mode. */ 4323 if (IFM_SUBTYPE(ifr->ifr_media) == IFM_AUTO || 4324 (ifr->ifr_media & IFM_FDX) == 0) { 4325 ifr->ifr_media &= ~IFM_ETH_FMASK; 4326 } 4327 if (IFM_SUBTYPE(ifr->ifr_media) != IFM_AUTO) { 4328 if ((ifr->ifr_media & IFM_ETH_FMASK) == IFM_FLOW) { 4329 /* We can do both TXPAUSE and RXPAUSE. */ 4330 ifr->ifr_media |= 4331 IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE; 4332 } 4333 sc->bge_flowflags = ifr->ifr_media & IFM_ETH_FMASK; 4334 } 4335 /* FALLTHROUGH */ 4336 case SIOCGIFMEDIA: 4337 if (sc->bge_flags & BGE_PHY_FIBER_TBI) { 4338 error = ifmedia_ioctl(ifp, ifr, &sc->bge_ifmedia, 4339 command); 4340 } else { 4341 mii = &sc->bge_mii; 4342 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, 4343 command); 4344 } 4345 break; 4346 default: 4347 if ((error = ether_ioctl(ifp, command, data)) != ENETRESET) 4348 break; 4349 4350 error = 0; 4351 4352 if (command != SIOCADDMULTI && command != SIOCDELMULTI) 4353 ; 4354 else if (ifp->if_flags & IFF_RUNNING) 4355 bge_setmulti(sc); 4356 break; 4357 } 4358 4359 splx(s); 4360 4361 return error; 4362 } 4363 4364 static void 4365 bge_watchdog(struct ifnet *ifp) 4366 { 4367 struct bge_softc *sc; 4368 4369 sc = ifp->if_softc; 4370 4371 aprint_error_dev(sc->bge_dev, "watchdog timeout -- resetting\n"); 4372 4373 ifp->if_flags &= ~IFF_RUNNING; 4374 bge_init(ifp); 4375 4376 ifp->if_oerrors++; 4377 } 4378 4379 static void 4380 bge_stop_block(struct bge_softc *sc, bus_addr_t reg, uint32_t bit) 4381 { 4382 int i; 4383 4384 BGE_CLRBIT(sc, reg, bit); 4385 4386 for (i = 0; i < BGE_TIMEOUT; i++) { 4387 if ((CSR_READ_4(sc, reg) & bit) == 0) 4388 return; 4389 delay(100); 4390 if (sc->bge_flags & BGE_PCIE) 4391 DELAY(1000); 4392 } 4393 4394 /* 4395 * Doesn't print only when the register is BGE_SRS_MODE. It occurs 4396 * on some environment (and once after boot?) 4397 */ 4398 if (reg != BGE_SRS_MODE) 4399 aprint_error_dev(sc->bge_dev, 4400 "block failed to stop: reg 0x%lx, bit 0x%08x\n", 4401 (u_long)reg, bit); 4402 } 4403 4404 /* 4405 * Stop the adapter and free any mbufs allocated to the 4406 * RX and TX lists. 4407 */ 4408 static void 4409 bge_stop(struct ifnet *ifp, int disable) 4410 { 4411 struct bge_softc *sc = ifp->if_softc; 4412 4413 callout_stop(&sc->bge_timeout); 4414 4415 /* 4416 * Disable all of the receiver blocks 4417 */ 4418 bge_stop_block(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE); 4419 bge_stop_block(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 4420 bge_stop_block(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 4421 if (BGE_IS_5700_FAMILY(sc)) 4422 bge_stop_block(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 4423 bge_stop_block(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE); 4424 bge_stop_block(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 4425 bge_stop_block(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE); 4426 4427 /* 4428 * Disable all of the transmit blocks 4429 */ 4430 bge_stop_block(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 4431 bge_stop_block(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 4432 bge_stop_block(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 4433 bge_stop_block(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE); 4434 bge_stop_block(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE); 4435 if (BGE_IS_5700_FAMILY(sc)) 4436 bge_stop_block(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 4437 bge_stop_block(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 4438 4439 /* 4440 * Shut down all of the memory managers and related 4441 * state machines. 4442 */ 4443 bge_stop_block(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE); 4444 bge_stop_block(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE); 4445 if (BGE_IS_5700_FAMILY(sc)) 4446 bge_stop_block(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 4447 4448 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 4449 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 4450 4451 if (BGE_IS_5700_FAMILY(sc)) { 4452 bge_stop_block(sc, BGE_BMAN_MODE, BGE_BMANMODE_ENABLE); 4453 bge_stop_block(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 4454 } 4455 4456 /* Disable host interrupts. */ 4457 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); 4458 bge_writembx(sc, BGE_MBX_IRQ0_LO, 1); 4459 4460 /* 4461 * Tell firmware we're shutting down. 4462 */ 4463 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 4464 4465 /* Free the RX lists. */ 4466 bge_free_rx_ring_std(sc); 4467 4468 /* Free jumbo RX list. */ 4469 if (BGE_IS_JUMBO_CAPABLE(sc)) 4470 bge_free_rx_ring_jumbo(sc); 4471 4472 /* Free TX buffers. */ 4473 bge_free_tx_ring(sc); 4474 4475 /* 4476 * Isolate/power down the PHY. 4477 */ 4478 if (!(sc->bge_flags & BGE_PHY_FIBER_TBI)) 4479 mii_down(&sc->bge_mii); 4480 4481 sc->bge_tx_saved_considx = BGE_TXCONS_UNSET; 4482 4483 /* Clear MAC's link state (PHY may still have link UP). */ 4484 BGE_STS_CLRBIT(sc, BGE_STS_LINK); 4485 4486 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 4487 } 4488 4489 static void 4490 bge_link_upd(struct bge_softc *sc) 4491 { 4492 struct ifnet *ifp = &sc->ethercom.ec_if; 4493 struct mii_data *mii = &sc->bge_mii; 4494 uint32_t status; 4495 int link; 4496 4497 /* Clear 'pending link event' flag */ 4498 BGE_STS_CLRBIT(sc, BGE_STS_LINK_EVT); 4499 4500 /* 4501 * Process link state changes. 4502 * Grrr. The link status word in the status block does 4503 * not work correctly on the BCM5700 rev AX and BX chips, 4504 * according to all available information. Hence, we have 4505 * to enable MII interrupts in order to properly obtain 4506 * async link changes. Unfortunately, this also means that 4507 * we have to read the MAC status register to detect link 4508 * changes, thereby adding an additional register access to 4509 * the interrupt handler. 4510 */ 4511 4512 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700) { 4513 status = CSR_READ_4(sc, BGE_MAC_STS); 4514 if (status & BGE_MACSTAT_MI_INTERRUPT) { 4515 mii_pollstat(mii); 4516 4517 if (!BGE_STS_BIT(sc, BGE_STS_LINK) && 4518 mii->mii_media_status & IFM_ACTIVE && 4519 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) 4520 BGE_STS_SETBIT(sc, BGE_STS_LINK); 4521 else if (BGE_STS_BIT(sc, BGE_STS_LINK) && 4522 (!(mii->mii_media_status & IFM_ACTIVE) || 4523 IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) 4524 BGE_STS_CLRBIT(sc, BGE_STS_LINK); 4525 4526 /* Clear the interrupt */ 4527 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, 4528 BGE_EVTENB_MI_INTERRUPT); 4529 bge_miibus_readreg(sc->bge_dev, 1, BRGPHY_MII_ISR); 4530 bge_miibus_writereg(sc->bge_dev, 1, BRGPHY_MII_IMR, 4531 BRGPHY_INTRS); 4532 } 4533 return; 4534 } 4535 4536 if (sc->bge_flags & BGE_PHY_FIBER_TBI) { 4537 status = CSR_READ_4(sc, BGE_MAC_STS); 4538 if (status & BGE_MACSTAT_TBI_PCS_SYNCHED) { 4539 if (!BGE_STS_BIT(sc, BGE_STS_LINK)) { 4540 BGE_STS_SETBIT(sc, BGE_STS_LINK); 4541 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) 4542 BGE_CLRBIT(sc, BGE_MAC_MODE, 4543 BGE_MACMODE_TBI_SEND_CFGS); 4544 CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF); 4545 if_link_state_change(ifp, LINK_STATE_UP); 4546 } 4547 } else if (BGE_STS_BIT(sc, BGE_STS_LINK)) { 4548 BGE_STS_CLRBIT(sc, BGE_STS_LINK); 4549 if_link_state_change(ifp, LINK_STATE_DOWN); 4550 } 4551 /* 4552 * Discard link events for MII/GMII cards if MI auto-polling disabled. 4553 * This should not happen since mii callouts are locked now, but 4554 * we keep this check for debug. 4555 */ 4556 } else if (BGE_STS_BIT(sc, BGE_STS_AUTOPOLL)) { 4557 /* 4558 * Some broken BCM chips have BGE_STATFLAG_LINKSTATE_CHANGED 4559 * bit in status word always set. Workaround this bug by 4560 * reading PHY link status directly. 4561 */ 4562 link = (CSR_READ_4(sc, BGE_MI_STS) & BGE_MISTS_LINK)? 4563 BGE_STS_LINK : 0; 4564 4565 if (BGE_STS_BIT(sc, BGE_STS_LINK) != link) { 4566 mii_pollstat(mii); 4567 4568 if (!BGE_STS_BIT(sc, BGE_STS_LINK) && 4569 mii->mii_media_status & IFM_ACTIVE && 4570 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) 4571 BGE_STS_SETBIT(sc, BGE_STS_LINK); 4572 else if (BGE_STS_BIT(sc, BGE_STS_LINK) && 4573 (!(mii->mii_media_status & IFM_ACTIVE) || 4574 IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) 4575 BGE_STS_CLRBIT(sc, BGE_STS_LINK); 4576 } 4577 } 4578 4579 /* Clear the attention */ 4580 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED| 4581 BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE| 4582 BGE_MACSTAT_LINK_CHANGED); 4583 } 4584 4585 static int 4586 sysctl_bge_verify(SYSCTLFN_ARGS) 4587 { 4588 int error, t; 4589 struct sysctlnode node; 4590 4591 node = *rnode; 4592 t = *(int*)rnode->sysctl_data; 4593 node.sysctl_data = &t; 4594 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 4595 if (error || newp == NULL) 4596 return error; 4597 4598 #if 0 4599 DPRINTF2(("%s: t = %d, nodenum = %d, rnodenum = %d\n", __func__, t, 4600 node.sysctl_num, rnode->sysctl_num)); 4601 #endif 4602 4603 if (node.sysctl_num == bge_rxthresh_nodenum) { 4604 if (t < 0 || t >= NBGE_RX_THRESH) 4605 return EINVAL; 4606 bge_update_all_threshes(t); 4607 } else 4608 return EINVAL; 4609 4610 *(int*)rnode->sysctl_data = t; 4611 4612 return 0; 4613 } 4614 4615 /* 4616 * Set up sysctl(3) MIB, hw.bge.*. 4617 * 4618 * TBD condition SYSCTL_PERMANENT on being an LKM or not 4619 */ 4620 SYSCTL_SETUP(sysctl_bge, "sysctl bge subtree setup") 4621 { 4622 int rc, bge_root_num; 4623 const struct sysctlnode *node; 4624 4625 if ((rc = sysctl_createv(clog, 0, NULL, NULL, 4626 CTLFLAG_PERMANENT, CTLTYPE_NODE, "hw", NULL, 4627 NULL, 0, NULL, 0, CTL_HW, CTL_EOL)) != 0) { 4628 goto err; 4629 } 4630 4631 if ((rc = sysctl_createv(clog, 0, NULL, &node, 4632 CTLFLAG_PERMANENT, CTLTYPE_NODE, "bge", 4633 SYSCTL_DESCR("BGE interface controls"), 4634 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL)) != 0) { 4635 goto err; 4636 } 4637 4638 bge_root_num = node->sysctl_num; 4639 4640 /* BGE Rx interrupt mitigation level */ 4641 if ((rc = sysctl_createv(clog, 0, NULL, &node, 4642 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, 4643 CTLTYPE_INT, "rx_lvl", 4644 SYSCTL_DESCR("BGE receive interrupt mitigation level"), 4645 sysctl_bge_verify, 0, 4646 &bge_rx_thresh_lvl, 4647 0, CTL_HW, bge_root_num, CTL_CREATE, 4648 CTL_EOL)) != 0) { 4649 goto err; 4650 } 4651 4652 bge_rxthresh_nodenum = node->sysctl_num; 4653 4654 return; 4655 4656 err: 4657 aprint_error("%s: sysctl_createv failed (rc = %d)\n", __func__, rc); 4658 } 4659 4660 #ifdef BGE_DEBUG 4661 void 4662 bge_debug_info(struct bge_softc *sc) 4663 { 4664 4665 printf("Hardware Flags:\n"); 4666 if (BGE_IS_5755_PLUS(sc)) 4667 printf(" - 5755 Plus\n"); 4668 if (BGE_IS_5750_OR_BEYOND(sc)) 4669 printf(" - 5750 Plus\n"); 4670 if (BGE_IS_5705_PLUS(sc)) 4671 printf(" - 5705 Plus\n"); 4672 if (BGE_IS_5714_FAMILY(sc)) 4673 printf(" - 5714 Family\n"); 4674 if (BGE_IS_5700_FAMILY(sc)) 4675 printf(" - 5700 Family\n"); 4676 if (sc->bge_flags & BGE_IS_5788) 4677 printf(" - 5788\n"); 4678 if (sc->bge_flags & BGE_JUMBO_CAPABLE) 4679 printf(" - Supports Jumbo Frames\n"); 4680 if (sc->bge_flags & BGE_NO_EEPROM) 4681 printf(" - No EEPROM\n"); 4682 if (sc->bge_flags & BGE_PCIX) 4683 printf(" - PCI-X Bus\n"); 4684 if (sc->bge_flags & BGE_PCIE) 4685 printf(" - PCI Express Bus\n"); 4686 if (sc->bge_flags & BGE_NO_3LED) 4687 printf(" - No 3 LEDs\n"); 4688 if (sc->bge_flags & BGE_RX_ALIGNBUG) 4689 printf(" - RX Alignment Bug\n"); 4690 if (sc->bge_flags & BGE_TSO) 4691 printf(" - TSO\n"); 4692 } 4693 #endif /* BGE_DEBUG */ 4694 4695 static int 4696 bge_get_eaddr_fw(struct bge_softc *sc, uint8_t ether_addr[]) 4697 { 4698 prop_dictionary_t dict; 4699 prop_data_t ea; 4700 4701 if ((sc->bge_flags & BGE_NO_EEPROM) == 0) 4702 return 1; 4703 4704 dict = device_properties(sc->bge_dev); 4705 ea = prop_dictionary_get(dict, "mac-address"); 4706 if (ea != NULL) { 4707 KASSERT(prop_object_type(ea) == PROP_TYPE_DATA); 4708 KASSERT(prop_data_size(ea) == ETHER_ADDR_LEN); 4709 memcpy(ether_addr, prop_data_data_nocopy(ea), ETHER_ADDR_LEN); 4710 return 0; 4711 } 4712 4713 return 1; 4714 } 4715 4716 static int 4717 bge_get_eaddr_mem(struct bge_softc *sc, uint8_t ether_addr[]) 4718 { 4719 uint32_t mac_addr; 4720 4721 mac_addr = bge_readmem_ind(sc, 0x0c14); 4722 if ((mac_addr >> 16) == 0x484b) { 4723 ether_addr[0] = (uint8_t)(mac_addr >> 8); 4724 ether_addr[1] = (uint8_t)mac_addr; 4725 mac_addr = bge_readmem_ind(sc, 0x0c18); 4726 ether_addr[2] = (uint8_t)(mac_addr >> 24); 4727 ether_addr[3] = (uint8_t)(mac_addr >> 16); 4728 ether_addr[4] = (uint8_t)(mac_addr >> 8); 4729 ether_addr[5] = (uint8_t)mac_addr; 4730 return 0; 4731 } 4732 return 1; 4733 } 4734 4735 static int 4736 bge_get_eaddr_nvram(struct bge_softc *sc, uint8_t ether_addr[]) 4737 { 4738 int mac_offset = BGE_EE_MAC_OFFSET; 4739 4740 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 4741 mac_offset = BGE_EE_MAC_OFFSET_5906; 4742 } 4743 4744 return (bge_read_nvram(sc, ether_addr, mac_offset + 2, 4745 ETHER_ADDR_LEN)); 4746 } 4747 4748 static int 4749 bge_get_eaddr_eeprom(struct bge_softc *sc, uint8_t ether_addr[]) 4750 { 4751 4752 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 4753 return 1; 4754 4755 return (bge_read_eeprom(sc, ether_addr, BGE_EE_MAC_OFFSET + 2, 4756 ETHER_ADDR_LEN)); 4757 } 4758 4759 static int 4760 bge_get_eaddr(struct bge_softc *sc, uint8_t eaddr[]) 4761 { 4762 static const bge_eaddr_fcn_t bge_eaddr_funcs[] = { 4763 /* NOTE: Order is critical */ 4764 bge_get_eaddr_fw, 4765 bge_get_eaddr_mem, 4766 bge_get_eaddr_nvram, 4767 bge_get_eaddr_eeprom, 4768 NULL 4769 }; 4770 const bge_eaddr_fcn_t *func; 4771 4772 for (func = bge_eaddr_funcs; *func != NULL; ++func) { 4773 if ((*func)(sc, eaddr) == 0) 4774 break; 4775 } 4776 return (*func == NULL ? ENXIO : 0); 4777 } 4778
Indexes created Wed Sep 24 05:09:52 GMT 2025