if_bge.c revision 1.177
1 /* $NetBSD: if_bge.c,v 1.177 2010/01/28 03:09:13 msaitoh Exp $ */ 2 3 /* 4 * Copyright (c) 2001 Wind River Systems 5 * Copyright (c) 1997, 1998, 1999, 2001 6 * Bill Paul <wpaul (at) windriver.com>. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Bill Paul. 19 * 4. Neither the name of the author nor the names of any co-contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 33 * THE POSSIBILITY OF SUCH DAMAGE. 34 * 35 * $FreeBSD: if_bge.c,v 1.13 2002/04/04 06:01:31 wpaul Exp $ 36 */ 37 38 /* 39 * Broadcom BCM570x family gigabit ethernet driver for NetBSD. 40 * 41 * NetBSD version by: 42 * 43 * Frank van der Linden <fvdl (at) wasabisystems.com> 44 * Jason Thorpe <thorpej (at) wasabisystems.com> 45 * Jonathan Stone <jonathan (at) dsg.stanford.edu> 46 * 47 * Originally written for FreeBSD by Bill Paul <wpaul (at) windriver.com> 48 * Senior Engineer, Wind River Systems 49 */ 50 51 /* 52 * The Broadcom BCM5700 is based on technology originally developed by 53 * Alteon Networks as part of the Tigon I and Tigon II gigabit ethernet 54 * MAC chips. The BCM5700, sometimes refered to as the Tigon III, has 55 * two on-board MIPS R4000 CPUs and can have as much as 16MB of external 56 * SSRAM. The BCM5700 supports TCP, UDP and IP checksum offload, jumbo 57 * frames, highly configurable RX filtering, and 16 RX and TX queues 58 * (which, along with RX filter rules, can be used for QOS applications). 59 * Other features, such as TCP segmentation, may be available as part 60 * of value-added firmware updates. Unlike the Tigon I and Tigon II, 61 * firmware images can be stored in hardware and need not be compiled 62 * into the driver. 63 * 64 * The BCM5700 supports the PCI v2.2 and PCI-X v1.0 standards, and will 65 * function in a 32-bit/64-bit 33/66MHz bus, or a 64-bit/133MHz bus. 66 * 67 * The BCM5701 is a single-chip solution incorporating both the BCM5700 68 * MAC and a BCM5401 10/100/1000 PHY. Unlike the BCM5700, the BCM5701 69 * does not support external SSRAM. 70 * 71 * Broadcom also produces a variation of the BCM5700 under the "Altima" 72 * brand name, which is functionally similar but lacks PCI-X support. 73 * 74 * Without external SSRAM, you can only have at most 4 TX rings, 75 * and the use of the mini RX ring is disabled. This seems to imply 76 * that these features are simply not available on the BCM5701. As a 77 * result, this driver does not implement any support for the mini RX 78 * ring. 79 */ 80 81 #include <sys/cdefs.h> 82 __KERNEL_RCSID(0, "$NetBSD: if_bge.c,v 1.177 2010/01/28 03:09:13 msaitoh Exp $"); 83 84 #include "vlan.h" 85 #include "rnd.h" 86 87 #include <sys/param.h> 88 #include <sys/systm.h> 89 #include <sys/callout.h> 90 #include <sys/sockio.h> 91 #include <sys/mbuf.h> 92 #include <sys/malloc.h> 93 #include <sys/kernel.h> 94 #include <sys/device.h> 95 #include <sys/socket.h> 96 #include <sys/sysctl.h> 97 98 #include <net/if.h> 99 #include <net/if_dl.h> 100 #include <net/if_media.h> 101 #include <net/if_ether.h> 102 103 #if NRND > 0 104 #include <sys/rnd.h> 105 #endif 106 107 #ifdef INET 108 #include <netinet/in.h> 109 #include <netinet/in_systm.h> 110 #include <netinet/in_var.h> 111 #include <netinet/ip.h> 112 #endif 113 114 /* Headers for TCP Segmentation Offload (TSO) */ 115 #include <netinet/in_systm.h> /* n_time for <netinet/ip.h>... */ 116 #include <netinet/in.h> /* ip_{src,dst}, for <netinet/ip.h> */ 117 #include <netinet/ip.h> /* for struct ip */ 118 #include <netinet/tcp.h> /* for struct tcphdr */ 119 120 121 #include <net/bpf.h> 122 123 #include <dev/pci/pcireg.h> 124 #include <dev/pci/pcivar.h> 125 #include <dev/pci/pcidevs.h> 126 127 #include <dev/mii/mii.h> 128 #include <dev/mii/miivar.h> 129 #include <dev/mii/miidevs.h> 130 #include <dev/mii/brgphyreg.h> 131 132 #include <dev/pci/if_bgereg.h> 133 #include <dev/pci/if_bgevar.h> 134 135 #include <uvm/uvm_extern.h> 136 #include <prop/proplib.h> 137 138 #define ETHER_MIN_NOPAD (ETHER_MIN_LEN - ETHER_CRC_LEN) /* i.e., 60 */ 139 140 141 /* 142 * Tunable thresholds for rx-side bge interrupt mitigation. 143 */ 144 145 /* 146 * The pairs of values below were obtained from empirical measurement 147 * on bcm5700 rev B2; they ar designed to give roughly 1 receive 148 * interrupt for every N packets received, where N is, approximately, 149 * the second value (rx_max_bds) in each pair. The values are chosen 150 * such that moving from one pair to the succeeding pair was observed 151 * to roughly halve interrupt rate under sustained input packet load. 152 * The values were empirically chosen to avoid overflowing internal 153 * limits on the bcm5700: inreasing rx_ticks much beyond 600 154 * results in internal wrapping and higher interrupt rates. 155 * The limit of 46 frames was chosen to match NFS workloads. 156 * 157 * These values also work well on bcm5701, bcm5704C, and (less 158 * tested) bcm5703. On other chipsets, (including the Altima chip 159 * family), the larger values may overflow internal chip limits, 160 * leading to increasing interrupt rates rather than lower interrupt 161 * rates. 162 * 163 * Applications using heavy interrupt mitigation (interrupting every 164 * 32 or 46 frames) in both directions may need to increase the TCP 165 * windowsize to above 131072 bytes (e.g., to 199608 bytes) to sustain 166 * full link bandwidth, due to ACKs and window updates lingering 167 * in the RX queue during the 30-to-40-frame interrupt-mitigation window. 168 */ 169 static const struct bge_load_rx_thresh { 170 int rx_ticks; 171 int rx_max_bds; } 172 bge_rx_threshes[] = { 173 { 32, 2 }, 174 { 50, 4 }, 175 { 100, 8 }, 176 { 192, 16 }, 177 { 416, 32 }, 178 { 598, 46 } 179 }; 180 #define NBGE_RX_THRESH (sizeof(bge_rx_threshes) / sizeof(bge_rx_threshes[0])) 181 182 /* XXX patchable; should be sysctl'able */ 183 static int bge_auto_thresh = 1; 184 static int bge_rx_thresh_lvl; 185 186 static int bge_rxthresh_nodenum; 187 188 typedef int (*bge_eaddr_fcn_t)(struct bge_softc *, uint8_t[]); 189 190 static int bge_probe(device_t, cfdata_t, void *); 191 static void bge_attach(device_t, device_t, void *); 192 static void bge_release_resources(struct bge_softc *); 193 194 static int bge_get_eaddr_fw(struct bge_softc *, uint8_t[]); 195 static int bge_get_eaddr_mem(struct bge_softc *, uint8_t[]); 196 static int bge_get_eaddr_nvram(struct bge_softc *, uint8_t[]); 197 static int bge_get_eaddr_eeprom(struct bge_softc *, uint8_t[]); 198 static int bge_get_eaddr(struct bge_softc *, uint8_t[]); 199 200 static void bge_txeof(struct bge_softc *); 201 static void bge_rxeof(struct bge_softc *); 202 203 static void bge_asf_driver_up (struct bge_softc *); 204 static void bge_tick(void *); 205 static void bge_stats_update(struct bge_softc *); 206 static void bge_stats_update_regs(struct bge_softc *); 207 static int bge_encap(struct bge_softc *, struct mbuf *, uint32_t *); 208 209 static int bge_intr(void *); 210 static void bge_start(struct ifnet *); 211 static int bge_ioctl(struct ifnet *, u_long, void *); 212 static int bge_init(struct ifnet *); 213 static void bge_stop(struct ifnet *, int); 214 static void bge_watchdog(struct ifnet *); 215 static int bge_ifmedia_upd(struct ifnet *); 216 static void bge_ifmedia_sts(struct ifnet *, struct ifmediareq *); 217 218 static uint8_t bge_nvram_getbyte(struct bge_softc *, int, uint8_t *); 219 static int bge_read_nvram(struct bge_softc *, uint8_t *, int, int); 220 221 static uint8_t bge_eeprom_getbyte(struct bge_softc *, int, uint8_t *); 222 static int bge_read_eeprom(struct bge_softc *, void *, int, int); 223 static void bge_setmulti(struct bge_softc *); 224 225 static void bge_handle_events(struct bge_softc *); 226 static int bge_alloc_jumbo_mem(struct bge_softc *); 227 #if 0 /* XXX */ 228 static void bge_free_jumbo_mem(struct bge_softc *); 229 #endif 230 static void *bge_jalloc(struct bge_softc *); 231 static void bge_jfree(struct mbuf *, void *, size_t, void *); 232 static int bge_newbuf_std(struct bge_softc *, int, struct mbuf *, 233 bus_dmamap_t); 234 static int bge_newbuf_jumbo(struct bge_softc *, int, struct mbuf *); 235 static int bge_init_rx_ring_std(struct bge_softc *); 236 static void bge_free_rx_ring_std(struct bge_softc *); 237 static int bge_init_rx_ring_jumbo(struct bge_softc *); 238 static void bge_free_rx_ring_jumbo(struct bge_softc *); 239 static void bge_free_tx_ring(struct bge_softc *); 240 static int bge_init_tx_ring(struct bge_softc *); 241 242 static int bge_chipinit(struct bge_softc *); 243 static int bge_blockinit(struct bge_softc *); 244 static int bge_setpowerstate(struct bge_softc *, int); 245 static uint32_t bge_readmem_ind(struct bge_softc *, int); 246 static void bge_writemem_ind(struct bge_softc *, int, int); 247 static void bge_writembx(struct bge_softc *, int, int); 248 static void bge_writemem_direct(struct bge_softc *, int, int); 249 static void bge_writereg_ind(struct bge_softc *, int, int); 250 static void bge_set_max_readrq(struct bge_softc *); 251 252 static int bge_miibus_readreg(device_t, int, int); 253 static void bge_miibus_writereg(device_t, int, int, int); 254 static void bge_miibus_statchg(device_t); 255 256 #define BGE_RESET_START 1 257 #define BGE_RESET_STOP 2 258 static void bge_sig_post_reset(struct bge_softc *, int); 259 static void bge_sig_legacy(struct bge_softc *, int); 260 static void bge_sig_pre_reset(struct bge_softc *, int); 261 static void bge_stop_fw(struct bge_softc *); 262 static int bge_reset(struct bge_softc *); 263 static void bge_link_upd(struct bge_softc *); 264 265 #ifdef BGE_DEBUG 266 #define DPRINTF(x) if (bgedebug) printf x 267 #define DPRINTFN(n,x) if (bgedebug >= (n)) printf x 268 #define BGE_TSO_PRINTF(x) do { if (bge_tso_debug) printf x ;} while (0) 269 int bgedebug = 0; 270 int bge_tso_debug = 0; 271 void bge_debug_info(struct bge_softc *); 272 #else 273 #define DPRINTF(x) 274 #define DPRINTFN(n,x) 275 #define BGE_TSO_PRINTF(x) 276 #endif 277 278 #ifdef BGE_EVENT_COUNTERS 279 #define BGE_EVCNT_INCR(ev) (ev).ev_count++ 280 #define BGE_EVCNT_ADD(ev, val) (ev).ev_count += (val) 281 #define BGE_EVCNT_UPD(ev, val) (ev).ev_count = (val) 282 #else 283 #define BGE_EVCNT_INCR(ev) /* nothing */ 284 #define BGE_EVCNT_ADD(ev, val) /* nothing */ 285 #define BGE_EVCNT_UPD(ev, val) /* nothing */ 286 #endif 287 288 static const struct bge_product { 289 pci_vendor_id_t bp_vendor; 290 pci_product_id_t bp_product; 291 const char *bp_name; 292 } bge_products[] = { 293 /* 294 * The BCM5700 documentation seems to indicate that the hardware 295 * still has the Alteon vendor ID burned into it, though it 296 * should always be overridden by the value in the EEPROM. We'll 297 * check for it anyway. 298 */ 299 { PCI_VENDOR_ALTEON, 300 PCI_PRODUCT_ALTEON_BCM5700, 301 "Broadcom BCM5700 Gigabit Ethernet", 302 }, 303 { PCI_VENDOR_ALTEON, 304 PCI_PRODUCT_ALTEON_BCM5701, 305 "Broadcom BCM5701 Gigabit Ethernet", 306 }, 307 { PCI_VENDOR_ALTIMA, 308 PCI_PRODUCT_ALTIMA_AC1000, 309 "Altima AC1000 Gigabit Ethernet", 310 }, 311 { PCI_VENDOR_ALTIMA, 312 PCI_PRODUCT_ALTIMA_AC1001, 313 "Altima AC1001 Gigabit Ethernet", 314 }, 315 { PCI_VENDOR_ALTIMA, 316 PCI_PRODUCT_ALTIMA_AC9100, 317 "Altima AC9100 Gigabit Ethernet", 318 }, 319 { PCI_VENDOR_BROADCOM, 320 PCI_PRODUCT_BROADCOM_BCM5700, 321 "Broadcom BCM5700 Gigabit Ethernet", 322 }, 323 { PCI_VENDOR_BROADCOM, 324 PCI_PRODUCT_BROADCOM_BCM5701, 325 "Broadcom BCM5701 Gigabit Ethernet", 326 }, 327 { PCI_VENDOR_BROADCOM, 328 PCI_PRODUCT_BROADCOM_BCM5702, 329 "Broadcom BCM5702 Gigabit Ethernet", 330 }, 331 { PCI_VENDOR_BROADCOM, 332 PCI_PRODUCT_BROADCOM_BCM5702X, 333 "Broadcom BCM5702X Gigabit Ethernet" }, 334 { PCI_VENDOR_BROADCOM, 335 PCI_PRODUCT_BROADCOM_BCM5703, 336 "Broadcom BCM5703 Gigabit Ethernet", 337 }, 338 { PCI_VENDOR_BROADCOM, 339 PCI_PRODUCT_BROADCOM_BCM5703X, 340 "Broadcom BCM5703X Gigabit Ethernet", 341 }, 342 { PCI_VENDOR_BROADCOM, 343 PCI_PRODUCT_BROADCOM_BCM5703_ALT, 344 "Broadcom BCM5703 Gigabit Ethernet", 345 }, 346 { PCI_VENDOR_BROADCOM, 347 PCI_PRODUCT_BROADCOM_BCM5704C, 348 "Broadcom BCM5704C Dual Gigabit Ethernet", 349 }, 350 { PCI_VENDOR_BROADCOM, 351 PCI_PRODUCT_BROADCOM_BCM5704S, 352 "Broadcom BCM5704S Dual Gigabit Ethernet", 353 }, 354 { PCI_VENDOR_BROADCOM, 355 PCI_PRODUCT_BROADCOM_BCM5705, 356 "Broadcom BCM5705 Gigabit Ethernet", 357 }, 358 { PCI_VENDOR_BROADCOM, 359 PCI_PRODUCT_BROADCOM_BCM5705F, 360 "Broadcom BCM5705F Gigabit Ethernet", 361 }, 362 { PCI_VENDOR_BROADCOM, 363 PCI_PRODUCT_BROADCOM_BCM5705K, 364 "Broadcom BCM5705K Gigabit Ethernet", 365 }, 366 { PCI_VENDOR_BROADCOM, 367 PCI_PRODUCT_BROADCOM_BCM5705M, 368 "Broadcom BCM5705M Gigabit Ethernet", 369 }, 370 { PCI_VENDOR_BROADCOM, 371 PCI_PRODUCT_BROADCOM_BCM5705M_ALT, 372 "Broadcom BCM5705M Gigabit Ethernet", 373 }, 374 { PCI_VENDOR_BROADCOM, 375 PCI_PRODUCT_BROADCOM_BCM5714, 376 "Broadcom BCM5714 Gigabit Ethernet", 377 }, 378 { PCI_VENDOR_BROADCOM, 379 PCI_PRODUCT_BROADCOM_BCM5714S, 380 "Broadcom BCM5714S Gigabit Ethernet", 381 }, 382 { PCI_VENDOR_BROADCOM, 383 PCI_PRODUCT_BROADCOM_BCM5715, 384 "Broadcom BCM5715 Gigabit Ethernet", 385 }, 386 { PCI_VENDOR_BROADCOM, 387 PCI_PRODUCT_BROADCOM_BCM5715S, 388 "Broadcom BCM5715S Gigabit Ethernet", 389 }, 390 { PCI_VENDOR_BROADCOM, 391 PCI_PRODUCT_BROADCOM_BCM5717, 392 "Broadcom BCM5717 Gigabit Ethernet", 393 }, 394 { PCI_VENDOR_BROADCOM, 395 PCI_PRODUCT_BROADCOM_BCM5718, 396 "Broadcom BCM5718 Gigabit Ethernet", 397 }, 398 { PCI_VENDOR_BROADCOM, 399 PCI_PRODUCT_BROADCOM_BCM5720, 400 "Broadcom BCM5720 Gigabit Ethernet", 401 }, 402 { PCI_VENDOR_BROADCOM, 403 PCI_PRODUCT_BROADCOM_BCM5721, 404 "Broadcom BCM5721 Gigabit Ethernet", 405 }, 406 { PCI_VENDOR_BROADCOM, 407 PCI_PRODUCT_BROADCOM_BCM5722, 408 "Broadcom BCM5722 Gigabit Ethernet", 409 }, 410 { PCI_VENDOR_BROADCOM, 411 PCI_PRODUCT_BROADCOM_BCM5723, 412 "Broadcom BCM5723 Gigabit Ethernet", 413 }, 414 { PCI_VENDOR_BROADCOM, 415 PCI_PRODUCT_BROADCOM_BCM5724, 416 "Broadcom BCM5724 Gigabit Ethernet", 417 }, 418 { PCI_VENDOR_BROADCOM, 419 PCI_PRODUCT_BROADCOM_BCM5750, 420 "Broadcom BCM5750 Gigabit Ethernet", 421 }, 422 { PCI_VENDOR_BROADCOM, 423 PCI_PRODUCT_BROADCOM_BCM5750M, 424 "Broadcom BCM5750M Gigabit Ethernet", 425 }, 426 { PCI_VENDOR_BROADCOM, 427 PCI_PRODUCT_BROADCOM_BCM5751, 428 "Broadcom BCM5751 Gigabit Ethernet", 429 }, 430 { PCI_VENDOR_BROADCOM, 431 PCI_PRODUCT_BROADCOM_BCM5751F, 432 "Broadcom BCM5751F Gigabit Ethernet", 433 }, 434 { PCI_VENDOR_BROADCOM, 435 PCI_PRODUCT_BROADCOM_BCM5751M, 436 "Broadcom BCM5751M Gigabit Ethernet", 437 }, 438 { PCI_VENDOR_BROADCOM, 439 PCI_PRODUCT_BROADCOM_BCM5752, 440 "Broadcom BCM5752 Gigabit Ethernet", 441 }, 442 { PCI_VENDOR_BROADCOM, 443 PCI_PRODUCT_BROADCOM_BCM5752M, 444 "Broadcom BCM5752M Gigabit Ethernet", 445 }, 446 { PCI_VENDOR_BROADCOM, 447 PCI_PRODUCT_BROADCOM_BCM5753, 448 "Broadcom BCM5753 Gigabit Ethernet", 449 }, 450 { PCI_VENDOR_BROADCOM, 451 PCI_PRODUCT_BROADCOM_BCM5753F, 452 "Broadcom BCM5753F Gigabit Ethernet", 453 }, 454 { PCI_VENDOR_BROADCOM, 455 PCI_PRODUCT_BROADCOM_BCM5753M, 456 "Broadcom BCM5753M Gigabit Ethernet", 457 }, 458 { PCI_VENDOR_BROADCOM, 459 PCI_PRODUCT_BROADCOM_BCM5754, 460 "Broadcom BCM5754 Gigabit Ethernet", 461 }, 462 { PCI_VENDOR_BROADCOM, 463 PCI_PRODUCT_BROADCOM_BCM5754M, 464 "Broadcom BCM5754M Gigabit Ethernet", 465 }, 466 { PCI_VENDOR_BROADCOM, 467 PCI_PRODUCT_BROADCOM_BCM5755, 468 "Broadcom BCM5755 Gigabit Ethernet", 469 }, 470 { PCI_VENDOR_BROADCOM, 471 PCI_PRODUCT_BROADCOM_BCM5755M, 472 "Broadcom BCM5755M Gigabit Ethernet", 473 }, 474 { PCI_VENDOR_BROADCOM, 475 PCI_PRODUCT_BROADCOM_BCM5756, 476 "Broadcom BCM5756 Gigabit Ethernet", 477 }, 478 { PCI_VENDOR_BROADCOM, 479 PCI_PRODUCT_BROADCOM_BCM5761, 480 "Broadcom BCM5761 Gigabit Ethernet", 481 }, 482 { PCI_VENDOR_BROADCOM, 483 PCI_PRODUCT_BROADCOM_BCM5761E, 484 "Broadcom BCM5761E Gigabit Ethernet", 485 }, 486 { PCI_VENDOR_BROADCOM, 487 PCI_PRODUCT_BROADCOM_BCM5761S, 488 "Broadcom BCM5761S Gigabit Ethernet", 489 }, 490 { PCI_VENDOR_BROADCOM, 491 PCI_PRODUCT_BROADCOM_BCM5761SE, 492 "Broadcom BCM5761SE Gigabit Ethernet", 493 }, 494 { PCI_VENDOR_BROADCOM, 495 PCI_PRODUCT_BROADCOM_BCM5764, 496 "Broadcom BCM5764 Gigabit Ethernet", 497 }, 498 { PCI_VENDOR_BROADCOM, 499 PCI_PRODUCT_BROADCOM_BCM5780, 500 "Broadcom BCM5780 Gigabit Ethernet", 501 }, 502 { PCI_VENDOR_BROADCOM, 503 PCI_PRODUCT_BROADCOM_BCM5780S, 504 "Broadcom BCM5780S Gigabit Ethernet", 505 }, 506 { PCI_VENDOR_BROADCOM, 507 PCI_PRODUCT_BROADCOM_BCM5781, 508 "Broadcom BCM5781 Gigabit Ethernet", 509 }, 510 { PCI_VENDOR_BROADCOM, 511 PCI_PRODUCT_BROADCOM_BCM5782, 512 "Broadcom BCM5782 Gigabit Ethernet", 513 }, 514 { PCI_VENDOR_BROADCOM, 515 PCI_PRODUCT_BROADCOM_BCM5784M, 516 "BCM5784M NetLink 1000baseT Ethernet", 517 }, 518 { PCI_VENDOR_BROADCOM, 519 PCI_PRODUCT_BROADCOM_BCM5786, 520 "Broadcom BCM5786 Gigabit Ethernet", 521 }, 522 { PCI_VENDOR_BROADCOM, 523 PCI_PRODUCT_BROADCOM_BCM5787, 524 "Broadcom BCM5787 Gigabit Ethernet", 525 }, 526 { PCI_VENDOR_BROADCOM, 527 PCI_PRODUCT_BROADCOM_BCM5787M, 528 "Broadcom BCM5787M Gigabit Ethernet", 529 }, 530 { PCI_VENDOR_BROADCOM, 531 PCI_PRODUCT_BROADCOM_BCM5788, 532 "Broadcom BCM5788 Gigabit Ethernet", 533 }, 534 { PCI_VENDOR_BROADCOM, 535 PCI_PRODUCT_BROADCOM_BCM5789, 536 "Broadcom BCM5789 Gigabit Ethernet", 537 }, 538 { PCI_VENDOR_BROADCOM, 539 PCI_PRODUCT_BROADCOM_BCM5901, 540 "Broadcom BCM5901 Fast Ethernet", 541 }, 542 { PCI_VENDOR_BROADCOM, 543 PCI_PRODUCT_BROADCOM_BCM5901A2, 544 "Broadcom BCM5901A2 Fast Ethernet", 545 }, 546 { PCI_VENDOR_BROADCOM, 547 PCI_PRODUCT_BROADCOM_BCM5903M, 548 "Broadcom BCM5903M Fast Ethernet", 549 }, 550 { PCI_VENDOR_BROADCOM, 551 PCI_PRODUCT_BROADCOM_BCM5906, 552 "Broadcom BCM5906 Fast Ethernet", 553 }, 554 { PCI_VENDOR_BROADCOM, 555 PCI_PRODUCT_BROADCOM_BCM5906M, 556 "Broadcom BCM5906M Fast Ethernet", 557 }, 558 { PCI_VENDOR_BROADCOM, 559 PCI_PRODUCT_BROADCOM_BCM57760, 560 "Broadcom BCM57760 Fast Ethernet", 561 }, 562 { PCI_VENDOR_BROADCOM, 563 PCI_PRODUCT_BROADCOM_BCM57761, 564 "Broadcom BCM57761 Fast Ethernet", 565 }, 566 { PCI_VENDOR_BROADCOM, 567 PCI_PRODUCT_BROADCOM_BCM57765, 568 "Broadcom BCM57765 Fast Ethernet", 569 }, 570 { PCI_VENDOR_BROADCOM, 571 PCI_PRODUCT_BROADCOM_BCM57780, 572 "Broadcom BCM57780 Fast Ethernet", 573 }, 574 { PCI_VENDOR_BROADCOM, 575 PCI_PRODUCT_BROADCOM_BCM57781, 576 "Broadcom BCM57781 Fast Ethernet", 577 }, 578 { PCI_VENDOR_BROADCOM, 579 PCI_PRODUCT_BROADCOM_BCM57785, 580 "Broadcom BCM57785 Fast Ethernet", 581 }, 582 { PCI_VENDOR_BROADCOM, 583 PCI_PRODUCT_BROADCOM_BCM57788, 584 "Broadcom BCM57788 Fast Ethernet", 585 }, 586 { PCI_VENDOR_BROADCOM, 587 PCI_PRODUCT_BROADCOM_BCM57790, 588 "Broadcom BCM57790 Fast Ethernet", 589 }, 590 { PCI_VENDOR_BROADCOM, 591 PCI_PRODUCT_BROADCOM_BCM57791, 592 "Broadcom BCM57791 Fast Ethernet", 593 }, 594 { PCI_VENDOR_BROADCOM, 595 PCI_PRODUCT_BROADCOM_BCM57795, 596 "Broadcom BCM57795 Fast Ethernet", 597 }, 598 { PCI_VENDOR_SCHNEIDERKOCH, 599 PCI_PRODUCT_SCHNEIDERKOCH_SK_9DX1, 600 "SysKonnect SK-9Dx1 Gigabit Ethernet", 601 }, 602 { PCI_VENDOR_3COM, 603 PCI_PRODUCT_3COM_3C996, 604 "3Com 3c996 Gigabit Ethernet", 605 }, 606 { 0, 607 0, 608 NULL }, 609 }; 610 611 /* 612 * XXX: how to handle variants based on 5750 and derivatives: 613 * 5750 5751, 5721, possibly 5714, 5752, and 5708?, which 614 * in general behave like a 5705, except with additional quirks. 615 * This driver's current handling of the 5721 is wrong; 616 * how we map ASIC revision to "quirks" needs more thought. 617 * (defined here until the thought is done). 618 */ 619 #define BGE_IS_5700_FAMILY(sc) ((sc)->bge_flags & BGE_5700_FAMILY) 620 #define BGE_IS_5714_FAMILY(sc) ((sc)->bge_flags & BGE_5714_FAMILY) 621 #define BGE_IS_5705_PLUS(sc) ((sc)->bge_flags & BGE_5705_PLUS) 622 #define BGE_IS_5750_OR_BEYOND(sc) ((sc)->bge_flags & BGE_5750_PLUS) 623 #define BGE_IS_5755_PLUS(sc) ((sc)->bge_flags & BGE_5755_PLUS) 624 #define BGE_IS_JUMBO_CAPABLE(sc) ((sc)->bge_flags & BGE_JUMBO_CAPABLE) 625 626 static const struct bge_revision { 627 uint32_t br_chipid; 628 const char *br_name; 629 } bge_revisions[] = { 630 { BGE_CHIPID_BCM5700_A0, "BCM5700 A0" }, 631 { BGE_CHIPID_BCM5700_A1, "BCM5700 A1" }, 632 { BGE_CHIPID_BCM5700_B0, "BCM5700 B0" }, 633 { BGE_CHIPID_BCM5700_B1, "BCM5700 B1" }, 634 { BGE_CHIPID_BCM5700_B2, "BCM5700 B2" }, 635 { BGE_CHIPID_BCM5700_B3, "BCM5700 B3" }, 636 /* This is treated like a BCM5700 Bx */ 637 { BGE_CHIPID_BCM5700_ALTIMA, "BCM5700 Altima" }, 638 { BGE_CHIPID_BCM5700_C0, "BCM5700 C0" }, 639 { BGE_CHIPID_BCM5701_A0, "BCM5701 A0" }, 640 { BGE_CHIPID_BCM5701_B0, "BCM5701 B0" }, 641 { BGE_CHIPID_BCM5701_B2, "BCM5701 B2" }, 642 { BGE_CHIPID_BCM5701_B5, "BCM5701 B5" }, 643 { BGE_CHIPID_BCM5703_A0, "BCM5702/5703 A0" }, 644 { BGE_CHIPID_BCM5703_A1, "BCM5702/5703 A1" }, 645 { BGE_CHIPID_BCM5703_A2, "BCM5702/5703 A2" }, 646 { BGE_CHIPID_BCM5703_A3, "BCM5702/5703 A3" }, 647 { BGE_CHIPID_BCM5703_B0, "BCM5702/5703 B0" }, 648 { BGE_CHIPID_BCM5704_A0, "BCM5704 A0" }, 649 { BGE_CHIPID_BCM5704_A1, "BCM5704 A1" }, 650 { BGE_CHIPID_BCM5704_A2, "BCM5704 A2" }, 651 { BGE_CHIPID_BCM5704_A3, "BCM5704 A3" }, 652 { BGE_CHIPID_BCM5704_B0, "BCM5704 B0" }, 653 { BGE_CHIPID_BCM5705_A0, "BCM5705 A0" }, 654 { BGE_CHIPID_BCM5705_A1, "BCM5705 A1" }, 655 { BGE_CHIPID_BCM5705_A2, "BCM5705 A2" }, 656 { BGE_CHIPID_BCM5705_A3, "BCM5705 A3" }, 657 { BGE_CHIPID_BCM5750_A0, "BCM5750 A0" }, 658 { BGE_CHIPID_BCM5750_A1, "BCM5750 A1" }, 659 { BGE_CHIPID_BCM5750_A3, "BCM5750 A3" }, 660 { BGE_CHIPID_BCM5750_B0, "BCM5750 B0" }, 661 { BGE_CHIPID_BCM5750_B1, "BCM5750 B1" }, 662 { BGE_CHIPID_BCM5750_C0, "BCM5750 C0" }, 663 { BGE_CHIPID_BCM5750_C1, "BCM5750 C1" }, 664 { BGE_CHIPID_BCM5750_C2, "BCM5750 C2" }, 665 { BGE_CHIPID_BCM5752_A0, "BCM5752 A0" }, 666 { BGE_CHIPID_BCM5752_A1, "BCM5752 A1" }, 667 { BGE_CHIPID_BCM5752_A2, "BCM5752 A2" }, 668 { BGE_CHIPID_BCM5714_A0, "BCM5714 A0" }, 669 { BGE_CHIPID_BCM5714_B0, "BCM5714 B0" }, 670 { BGE_CHIPID_BCM5714_B3, "BCM5714 B3" }, 671 { BGE_CHIPID_BCM5715_A0, "BCM5715 A0" }, 672 { BGE_CHIPID_BCM5715_A1, "BCM5715 A1" }, 673 { BGE_CHIPID_BCM5715_A3, "BCM5715 A3" }, 674 { BGE_CHIPID_BCM5755_A0, "BCM5755 A0" }, 675 { BGE_CHIPID_BCM5755_A1, "BCM5755 A1" }, 676 { BGE_CHIPID_BCM5755_A2, "BCM5755 A2" }, 677 { BGE_CHIPID_BCM5755_C0, "BCM5755 C0" }, 678 { BGE_CHIPID_BCM5761_A0, "BCM5761 A0" }, 679 { BGE_CHIPID_BCM5761_A1, "BCM5761 A1" }, 680 { BGE_CHIPID_BCM5784_A0, "BCM5784 A0" }, 681 { BGE_CHIPID_BCM5784_A1, "BCM5784 A1" }, 682 /* 5754 and 5787 share the same ASIC ID */ 683 { BGE_CHIPID_BCM5787_A0, "BCM5754/5787 A0" }, 684 { BGE_CHIPID_BCM5787_A1, "BCM5754/5787 A1" }, 685 { BGE_CHIPID_BCM5787_A2, "BCM5754/5787 A2" }, 686 { BGE_CHIPID_BCM5906_A1, "BCM5906 A1" }, 687 { BGE_CHIPID_BCM5906_A2, "BCM5906 A2" }, 688 { BGE_CHIPID_BCM57780_A0, "BCM57780 A0" }, 689 { BGE_CHIPID_BCM57780_A1, "BCM57780 A1" }, 690 691 { 0, NULL } 692 }; 693 694 /* 695 * Some defaults for major revisions, so that newer steppings 696 * that we don't know about have a shot at working. 697 */ 698 static const struct bge_revision bge_majorrevs[] = { 699 { BGE_ASICREV_BCM5700, "unknown BCM5700" }, 700 { BGE_ASICREV_BCM5701, "unknown BCM5701" }, 701 { BGE_ASICREV_BCM5703, "unknown BCM5703" }, 702 { BGE_ASICREV_BCM5704, "unknown BCM5704" }, 703 { BGE_ASICREV_BCM5705, "unknown BCM5705" }, 704 { BGE_ASICREV_BCM5750, "unknown BCM5750" }, 705 { BGE_ASICREV_BCM5714_A0, "unknown BCM5714" }, 706 { BGE_ASICREV_BCM5752, "unknown BCM5752" }, 707 { BGE_ASICREV_BCM5780, "unknown BCM5780" }, 708 { BGE_ASICREV_BCM5714, "unknown BCM5714" }, 709 { BGE_ASICREV_BCM5755, "unknown BCM5755" }, 710 { BGE_ASICREV_BCM5761, "unknown BCM5761" }, 711 { BGE_ASICREV_BCM5784, "unknown BCM5784" }, 712 { BGE_ASICREV_BCM5785, "unknown BCM5785" }, 713 /* 5754 and 5787 share the same ASIC ID */ 714 { BGE_ASICREV_BCM5787, "unknown BCM5754/5787" }, 715 { BGE_ASICREV_BCM5906, "unknown BCM5906" }, 716 { BGE_ASICREV_BCM57780, "unknown BCM57780" }, 717 { BGE_ASICREV_BCM5717, "unknown BCM5717" }, 718 { BGE_ASICREV_BCM57765, "unknown BCM57765" }, 719 720 { 0, NULL } 721 }; 722 723 static int bge_allow_asf = 1; 724 725 CFATTACH_DECL_NEW(bge, sizeof(struct bge_softc), 726 bge_probe, bge_attach, NULL, NULL); 727 728 static uint32_t 729 bge_readmem_ind(struct bge_softc *sc, int off) 730 { 731 pcireg_t val; 732 733 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_BASEADDR, off); 734 val = pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_DATA); 735 return val; 736 } 737 738 static void 739 bge_writemem_ind(struct bge_softc *sc, int off, int val) 740 { 741 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_BASEADDR, off); 742 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_DATA, val); 743 } 744 745 /* 746 * PCI Express only 747 */ 748 static void 749 bge_set_max_readrq(struct bge_softc *sc) 750 { 751 device_t dev; 752 pcireg_t val; 753 754 dev = sc->bge_dev; 755 756 val = pci_conf_read(sc->sc_pc, sc->sc_pcitag, sc->bge_expcap 757 + PCI_PCIE_DCSR); 758 if ((val & PCI_PCIE_DCSR_MAX_READ_REQ) != 759 BGE_PCIE_DEVCTL_MAX_READRQ_4096) { 760 printf("adjust device control 0x%04x ", 761 val); 762 val &= ~PCI_PCIE_DCSR_MAX_READ_REQ; 763 val |= BGE_PCIE_DEVCTL_MAX_READRQ_4096; 764 pci_conf_write(sc->sc_pc, sc->sc_pcitag, sc->bge_expcap 765 + PCI_PCIE_DCSR, val); 766 printf("-> 0x%04x\n", val); 767 } 768 } 769 770 #ifdef notdef 771 static uint32_t 772 bge_readreg_ind(struct bge_softc *sc, int off) 773 { 774 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_REG_BASEADDR, off); 775 return (pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_REG_DATA)); 776 } 777 #endif 778 779 static void 780 bge_writereg_ind(struct bge_softc *sc, int off, int val) 781 { 782 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_REG_BASEADDR, off); 783 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_REG_DATA, val); 784 } 785 786 static void 787 bge_writemem_direct(struct bge_softc *sc, int off, int val) 788 { 789 CSR_WRITE_4(sc, off, val); 790 } 791 792 static void 793 bge_writembx(struct bge_softc *sc, int off, int val) 794 { 795 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 796 off += BGE_LPMBX_IRQ0_HI - BGE_MBX_IRQ0_HI; 797 798 CSR_WRITE_4(sc, off, val); 799 } 800 801 static uint8_t 802 bge_nvram_getbyte(struct bge_softc *sc, int addr, uint8_t *dest) 803 { 804 uint32_t access, byte = 0; 805 int i; 806 807 /* Lock. */ 808 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_SET1); 809 for (i = 0; i < 8000; i++) { 810 if (CSR_READ_4(sc, BGE_NVRAM_SWARB) & BGE_NVRAMSWARB_GNT1) 811 break; 812 DELAY(20); 813 } 814 if (i == 8000) 815 return 1; 816 817 /* Enable access. */ 818 access = CSR_READ_4(sc, BGE_NVRAM_ACCESS); 819 CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access | BGE_NVRAMACC_ENABLE); 820 821 CSR_WRITE_4(sc, BGE_NVRAM_ADDR, addr & 0xfffffffc); 822 CSR_WRITE_4(sc, BGE_NVRAM_CMD, BGE_NVRAM_READCMD); 823 for (i = 0; i < BGE_TIMEOUT * 10; i++) { 824 DELAY(10); 825 if (CSR_READ_4(sc, BGE_NVRAM_CMD) & BGE_NVRAMCMD_DONE) { 826 DELAY(10); 827 break; 828 } 829 } 830 831 if (i == BGE_TIMEOUT * 10) { 832 aprint_error_dev(sc->bge_dev, "nvram read timed out\n"); 833 return 1; 834 } 835 836 /* Get result. */ 837 byte = CSR_READ_4(sc, BGE_NVRAM_RDDATA); 838 839 *dest = (bswap32(byte) >> ((addr % 4) * 8)) & 0xFF; 840 841 /* Disable access. */ 842 CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access); 843 844 /* Unlock. */ 845 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_CLR1); 846 CSR_READ_4(sc, BGE_NVRAM_SWARB); 847 848 return 0; 849 } 850 851 /* 852 * Read a sequence of bytes from NVRAM. 853 */ 854 static int 855 bge_read_nvram(struct bge_softc *sc, uint8_t *dest, int off, int cnt) 856 { 857 int err = 0, i; 858 uint8_t byte = 0; 859 860 if (BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5906) 861 return 1; 862 863 for (i = 0; i < cnt; i++) { 864 err = bge_nvram_getbyte(sc, off + i, &byte); 865 if (err) 866 break; 867 *(dest + i) = byte; 868 } 869 870 return (err ? 1 : 0); 871 } 872 873 /* 874 * Read a byte of data stored in the EEPROM at address 'addr.' The 875 * BCM570x supports both the traditional bitbang interface and an 876 * auto access interface for reading the EEPROM. We use the auto 877 * access method. 878 */ 879 static uint8_t 880 bge_eeprom_getbyte(struct bge_softc *sc, int addr, uint8_t *dest) 881 { 882 int i; 883 uint32_t byte = 0; 884 885 /* 886 * Enable use of auto EEPROM access so we can avoid 887 * having to use the bitbang method. 888 */ 889 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM); 890 891 /* Reset the EEPROM, load the clock period. */ 892 CSR_WRITE_4(sc, BGE_EE_ADDR, 893 BGE_EEADDR_RESET | BGE_EEHALFCLK(BGE_HALFCLK_384SCL)); 894 DELAY(20); 895 896 /* Issue the read EEPROM command. */ 897 CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr); 898 899 /* Wait for completion */ 900 for (i = 0; i < BGE_TIMEOUT * 10; i++) { 901 DELAY(10); 902 if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE) 903 break; 904 } 905 906 if (i == BGE_TIMEOUT * 10) { 907 aprint_error_dev(sc->bge_dev, "eeprom read timed out\n"); 908 return 1; 909 } 910 911 /* Get result. */ 912 byte = CSR_READ_4(sc, BGE_EE_DATA); 913 914 *dest = (byte >> ((addr % 4) * 8)) & 0xFF; 915 916 return 0; 917 } 918 919 /* 920 * Read a sequence of bytes from the EEPROM. 921 */ 922 static int 923 bge_read_eeprom(struct bge_softc *sc, void *destv, int off, int cnt) 924 { 925 int err = 0, i; 926 uint8_t byte = 0; 927 char *dest = destv; 928 929 for (i = 0; i < cnt; i++) { 930 err = bge_eeprom_getbyte(sc, off + i, &byte); 931 if (err) 932 break; 933 *(dest + i) = byte; 934 } 935 936 return (err ? 1 : 0); 937 } 938 939 static int 940 bge_miibus_readreg(device_t dev, int phy, int reg) 941 { 942 struct bge_softc *sc = device_private(dev); 943 uint32_t val; 944 uint32_t autopoll; 945 int i; 946 947 /* 948 * Broadcom's own driver always assumes the internal 949 * PHY is at GMII address 1. On some chips, the PHY responds 950 * to accesses at all addresses, which could cause us to 951 * bogusly attach the PHY 32 times at probe type. Always 952 * restricting the lookup to address 1 is simpler than 953 * trying to figure out which chips revisions should be 954 * special-cased. 955 */ 956 if (phy != 1) 957 return 0; 958 959 /* Reading with autopolling on may trigger PCI errors */ 960 autopoll = CSR_READ_4(sc, BGE_MI_MODE); 961 if (autopoll & BGE_MIMODE_AUTOPOLL) { 962 BGE_STS_CLRBIT(sc, BGE_STS_AUTOPOLL); 963 BGE_CLRBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 964 DELAY(40); 965 } 966 967 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_READ | BGE_MICOMM_BUSY | 968 BGE_MIPHY(phy) | BGE_MIREG(reg)); 969 970 for (i = 0; i < BGE_TIMEOUT; i++) { 971 val = CSR_READ_4(sc, BGE_MI_COMM); 972 if (!(val & BGE_MICOMM_BUSY)) 973 break; 974 delay(10); 975 } 976 977 if (i == BGE_TIMEOUT) { 978 aprint_error_dev(sc->bge_dev, "PHY read timed out\n"); 979 val = 0; 980 goto done; 981 } 982 983 val = CSR_READ_4(sc, BGE_MI_COMM); 984 985 done: 986 if (autopoll & BGE_MIMODE_AUTOPOLL) { 987 BGE_STS_SETBIT(sc, BGE_STS_AUTOPOLL); 988 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 989 DELAY(40); 990 } 991 992 if (val & BGE_MICOMM_READFAIL) 993 return 0; 994 995 return (val & 0xFFFF); 996 } 997 998 static void 999 bge_miibus_writereg(device_t dev, int phy, int reg, int val) 1000 { 1001 struct bge_softc *sc = device_private(dev); 1002 uint32_t autopoll; 1003 int i; 1004 1005 if (phy!=1) { 1006 return; 1007 } 1008 1009 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906 && 1010 (reg == BRGPHY_MII_1000CTL || reg == BRGPHY_MII_AUXCTL)) { 1011 return; 1012 } 1013 1014 /* Reading with autopolling on may trigger PCI errors */ 1015 autopoll = CSR_READ_4(sc, BGE_MI_MODE); 1016 if (autopoll & BGE_MIMODE_AUTOPOLL) { 1017 delay(40); 1018 BGE_STS_CLRBIT(sc, BGE_STS_AUTOPOLL); 1019 BGE_CLRBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 1020 delay(10); /* 40 usec is supposed to be adequate */ 1021 } 1022 1023 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_WRITE | BGE_MICOMM_BUSY | 1024 BGE_MIPHY(phy) | BGE_MIREG(reg) | val); 1025 1026 for (i = 0; i < BGE_TIMEOUT; i++) { 1027 delay(10); 1028 if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY)) { 1029 delay(5); 1030 CSR_READ_4(sc, BGE_MI_COMM); 1031 break; 1032 } 1033 } 1034 1035 if (autopoll & BGE_MIMODE_AUTOPOLL) { 1036 BGE_STS_SETBIT(sc, BGE_STS_AUTOPOLL); 1037 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 1038 delay(40); 1039 } 1040 1041 if (i == BGE_TIMEOUT) 1042 aprint_error_dev(sc->bge_dev, "PHY read timed out\n"); 1043 } 1044 1045 static void 1046 bge_miibus_statchg(device_t dev) 1047 { 1048 struct bge_softc *sc = device_private(dev); 1049 struct mii_data *mii = &sc->bge_mii; 1050 1051 /* 1052 * Get flow control negotiation result. 1053 */ 1054 if (IFM_SUBTYPE(mii->mii_media.ifm_cur->ifm_media) == IFM_AUTO && 1055 (mii->mii_media_active & IFM_ETH_FMASK) != sc->bge_flowflags) { 1056 sc->bge_flowflags = mii->mii_media_active & IFM_ETH_FMASK; 1057 mii->mii_media_active &= ~IFM_ETH_FMASK; 1058 } 1059 1060 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_PORTMODE); 1061 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T || 1062 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX) 1063 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_GMII); 1064 else 1065 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_MII); 1066 1067 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) 1068 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX); 1069 else 1070 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX); 1071 1072 /* 1073 * 802.3x flow control 1074 */ 1075 if (sc->bge_flowflags & IFM_ETH_RXPAUSE) 1076 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_FLOWCTL_ENABLE); 1077 else 1078 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_FLOWCTL_ENABLE); 1079 1080 if (sc->bge_flowflags & IFM_ETH_TXPAUSE) 1081 BGE_SETBIT(sc, BGE_TX_MODE, BGE_TXMODE_FLOWCTL_ENABLE); 1082 else 1083 BGE_CLRBIT(sc, BGE_TX_MODE, BGE_TXMODE_FLOWCTL_ENABLE); 1084 } 1085 1086 /* 1087 * Update rx threshold levels to values in a particular slot 1088 * of the interrupt-mitigation table bge_rx_threshes. 1089 */ 1090 static void 1091 bge_set_thresh(struct ifnet *ifp, int lvl) 1092 { 1093 struct bge_softc *sc = ifp->if_softc; 1094 int s; 1095 1096 /* For now, just save the new Rx-intr thresholds and record 1097 * that a threshold update is pending. Updating the hardware 1098 * registers here (even at splhigh()) is observed to 1099 * occasionaly cause glitches where Rx-interrupts are not 1100 * honoured for up to 10 seconds. jonathan (at) NetBSD.org, 2003-04-05 1101 */ 1102 s = splnet(); 1103 sc->bge_rx_coal_ticks = bge_rx_threshes[lvl].rx_ticks; 1104 sc->bge_rx_max_coal_bds = bge_rx_threshes[lvl].rx_max_bds; 1105 sc->bge_pending_rxintr_change = 1; 1106 splx(s); 1107 1108 return; 1109 } 1110 1111 1112 /* 1113 * Update Rx thresholds of all bge devices 1114 */ 1115 static void 1116 bge_update_all_threshes(int lvl) 1117 { 1118 struct ifnet *ifp; 1119 const char * const namebuf = "bge"; 1120 int namelen; 1121 1122 if (lvl < 0) 1123 lvl = 0; 1124 else if (lvl >= NBGE_RX_THRESH) 1125 lvl = NBGE_RX_THRESH - 1; 1126 1127 namelen = strlen(namebuf); 1128 /* 1129 * Now search all the interfaces for this name/number 1130 */ 1131 IFNET_FOREACH(ifp) { 1132 if (strncmp(ifp->if_xname, namebuf, namelen) != 0) 1133 continue; 1134 /* We got a match: update if doing auto-threshold-tuning */ 1135 if (bge_auto_thresh) 1136 bge_set_thresh(ifp, lvl); 1137 } 1138 } 1139 1140 /* 1141 * Handle events that have triggered interrupts. 1142 */ 1143 static void 1144 bge_handle_events(struct bge_softc *sc) 1145 { 1146 1147 return; 1148 } 1149 1150 /* 1151 * Memory management for jumbo frames. 1152 */ 1153 1154 static int 1155 bge_alloc_jumbo_mem(struct bge_softc *sc) 1156 { 1157 char *ptr, *kva; 1158 bus_dma_segment_t seg; 1159 int i, rseg, state, error; 1160 struct bge_jpool_entry *entry; 1161 1162 state = error = 0; 1163 1164 /* Grab a big chunk o' storage. */ 1165 if (bus_dmamem_alloc(sc->bge_dmatag, BGE_JMEM, PAGE_SIZE, 0, 1166 &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 1167 aprint_error_dev(sc->bge_dev, "can't alloc rx buffers\n"); 1168 return ENOBUFS; 1169 } 1170 1171 state = 1; 1172 if (bus_dmamem_map(sc->bge_dmatag, &seg, rseg, BGE_JMEM, (void **)&kva, 1173 BUS_DMA_NOWAIT)) { 1174 aprint_error_dev(sc->bge_dev, 1175 "can't map DMA buffers (%d bytes)\n", (int)BGE_JMEM); 1176 error = ENOBUFS; 1177 goto out; 1178 } 1179 1180 state = 2; 1181 if (bus_dmamap_create(sc->bge_dmatag, BGE_JMEM, 1, BGE_JMEM, 0, 1182 BUS_DMA_NOWAIT, &sc->bge_cdata.bge_rx_jumbo_map)) { 1183 aprint_error_dev(sc->bge_dev, "can't create DMA map\n"); 1184 error = ENOBUFS; 1185 goto out; 1186 } 1187 1188 state = 3; 1189 if (bus_dmamap_load(sc->bge_dmatag, sc->bge_cdata.bge_rx_jumbo_map, 1190 kva, BGE_JMEM, NULL, BUS_DMA_NOWAIT)) { 1191 aprint_error_dev(sc->bge_dev, "can't load DMA map\n"); 1192 error = ENOBUFS; 1193 goto out; 1194 } 1195 1196 state = 4; 1197 sc->bge_cdata.bge_jumbo_buf = (void *)kva; 1198 DPRINTFN(1,("bge_jumbo_buf = %p\n", sc->bge_cdata.bge_jumbo_buf)); 1199 1200 SLIST_INIT(&sc->bge_jfree_listhead); 1201 SLIST_INIT(&sc->bge_jinuse_listhead); 1202 1203 /* 1204 * Now divide it up into 9K pieces and save the addresses 1205 * in an array. 1206 */ 1207 ptr = sc->bge_cdata.bge_jumbo_buf; 1208 for (i = 0; i < BGE_JSLOTS; i++) { 1209 sc->bge_cdata.bge_jslots[i] = ptr; 1210 ptr += BGE_JLEN; 1211 entry = malloc(sizeof(struct bge_jpool_entry), 1212 M_DEVBUF, M_NOWAIT); 1213 if (entry == NULL) { 1214 aprint_error_dev(sc->bge_dev, 1215 "no memory for jumbo buffer queue!\n"); 1216 error = ENOBUFS; 1217 goto out; 1218 } 1219 entry->slot = i; 1220 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, 1221 entry, jpool_entries); 1222 } 1223 out: 1224 if (error != 0) { 1225 switch (state) { 1226 case 4: 1227 bus_dmamap_unload(sc->bge_dmatag, 1228 sc->bge_cdata.bge_rx_jumbo_map); 1229 case 3: 1230 bus_dmamap_destroy(sc->bge_dmatag, 1231 sc->bge_cdata.bge_rx_jumbo_map); 1232 case 2: 1233 bus_dmamem_unmap(sc->bge_dmatag, kva, BGE_JMEM); 1234 case 1: 1235 bus_dmamem_free(sc->bge_dmatag, &seg, rseg); 1236 break; 1237 default: 1238 break; 1239 } 1240 } 1241 1242 return error; 1243 } 1244 1245 /* 1246 * Allocate a jumbo buffer. 1247 */ 1248 static void * 1249 bge_jalloc(struct bge_softc *sc) 1250 { 1251 struct bge_jpool_entry *entry; 1252 1253 entry = SLIST_FIRST(&sc->bge_jfree_listhead); 1254 1255 if (entry == NULL) { 1256 aprint_error_dev(sc->bge_dev, "no free jumbo buffers\n"); 1257 return NULL; 1258 } 1259 1260 SLIST_REMOVE_HEAD(&sc->bge_jfree_listhead, jpool_entries); 1261 SLIST_INSERT_HEAD(&sc->bge_jinuse_listhead, entry, jpool_entries); 1262 return (sc->bge_cdata.bge_jslots[entry->slot]); 1263 } 1264 1265 /* 1266 * Release a jumbo buffer. 1267 */ 1268 static void 1269 bge_jfree(struct mbuf *m, void *buf, size_t size, void *arg) 1270 { 1271 struct bge_jpool_entry *entry; 1272 struct bge_softc *sc; 1273 int i, s; 1274 1275 /* Extract the softc struct pointer. */ 1276 sc = (struct bge_softc *)arg; 1277 1278 if (sc == NULL) 1279 panic("bge_jfree: can't find softc pointer!"); 1280 1281 /* calculate the slot this buffer belongs to */ 1282 1283 i = ((char *)buf 1284 - (char *)sc->bge_cdata.bge_jumbo_buf) / BGE_JLEN; 1285 1286 if ((i < 0) || (i >= BGE_JSLOTS)) 1287 panic("bge_jfree: asked to free buffer that we don't manage!"); 1288 1289 s = splvm(); 1290 entry = SLIST_FIRST(&sc->bge_jinuse_listhead); 1291 if (entry == NULL) 1292 panic("bge_jfree: buffer not in use!"); 1293 entry->slot = i; 1294 SLIST_REMOVE_HEAD(&sc->bge_jinuse_listhead, jpool_entries); 1295 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, entry, jpool_entries); 1296 1297 if (__predict_true(m != NULL)) 1298 pool_cache_put(mb_cache, m); 1299 splx(s); 1300 } 1301 1302 1303 /* 1304 * Intialize a standard receive ring descriptor. 1305 */ 1306 static int 1307 bge_newbuf_std(struct bge_softc *sc, int i, struct mbuf *m, bus_dmamap_t dmamap) 1308 { 1309 struct mbuf *m_new = NULL; 1310 struct bge_rx_bd *r; 1311 int error; 1312 1313 if (dmamap == NULL) { 1314 error = bus_dmamap_create(sc->bge_dmatag, MCLBYTES, 1, 1315 MCLBYTES, 0, BUS_DMA_NOWAIT, &dmamap); 1316 if (error != 0) 1317 return error; 1318 } 1319 1320 sc->bge_cdata.bge_rx_std_map[i] = dmamap; 1321 1322 if (m == NULL) { 1323 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1324 if (m_new == NULL) 1325 return ENOBUFS; 1326 1327 MCLGET(m_new, M_DONTWAIT); 1328 if (!(m_new->m_flags & M_EXT)) { 1329 m_freem(m_new); 1330 return ENOBUFS; 1331 } 1332 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1333 1334 } else { 1335 m_new = m; 1336 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1337 m_new->m_data = m_new->m_ext.ext_buf; 1338 } 1339 if (!(sc->bge_flags & BGE_RX_ALIGNBUG)) 1340 m_adj(m_new, ETHER_ALIGN); 1341 if (bus_dmamap_load_mbuf(sc->bge_dmatag, dmamap, m_new, 1342 BUS_DMA_READ|BUS_DMA_NOWAIT)) 1343 return ENOBUFS; 1344 bus_dmamap_sync(sc->bge_dmatag, dmamap, 0, dmamap->dm_mapsize, 1345 BUS_DMASYNC_PREREAD); 1346 1347 sc->bge_cdata.bge_rx_std_chain[i] = m_new; 1348 r = &sc->bge_rdata->bge_rx_std_ring[i]; 1349 BGE_HOSTADDR(r->bge_addr, dmamap->dm_segs[0].ds_addr); 1350 r->bge_flags = BGE_RXBDFLAG_END; 1351 r->bge_len = m_new->m_len; 1352 r->bge_idx = i; 1353 1354 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 1355 offsetof(struct bge_ring_data, bge_rx_std_ring) + 1356 i * sizeof (struct bge_rx_bd), 1357 sizeof (struct bge_rx_bd), 1358 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1359 1360 return 0; 1361 } 1362 1363 /* 1364 * Initialize a jumbo receive ring descriptor. This allocates 1365 * a jumbo buffer from the pool managed internally by the driver. 1366 */ 1367 static int 1368 bge_newbuf_jumbo(struct bge_softc *sc, int i, struct mbuf *m) 1369 { 1370 struct mbuf *m_new = NULL; 1371 struct bge_rx_bd *r; 1372 void *buf = NULL; 1373 1374 if (m == NULL) { 1375 1376 /* Allocate the mbuf. */ 1377 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1378 if (m_new == NULL) 1379 return ENOBUFS; 1380 1381 /* Allocate the jumbo buffer */ 1382 buf = bge_jalloc(sc); 1383 if (buf == NULL) { 1384 m_freem(m_new); 1385 aprint_error_dev(sc->bge_dev, 1386 "jumbo allocation failed -- packet dropped!\n"); 1387 return ENOBUFS; 1388 } 1389 1390 /* Attach the buffer to the mbuf. */ 1391 m_new->m_len = m_new->m_pkthdr.len = BGE_JUMBO_FRAMELEN; 1392 MEXTADD(m_new, buf, BGE_JUMBO_FRAMELEN, M_DEVBUF, 1393 bge_jfree, sc); 1394 m_new->m_flags |= M_EXT_RW; 1395 } else { 1396 m_new = m; 1397 buf = m_new->m_data = m_new->m_ext.ext_buf; 1398 m_new->m_ext.ext_size = BGE_JUMBO_FRAMELEN; 1399 } 1400 if (!(sc->bge_flags & BGE_RX_ALIGNBUG)) 1401 m_adj(m_new, ETHER_ALIGN); 1402 bus_dmamap_sync(sc->bge_dmatag, sc->bge_cdata.bge_rx_jumbo_map, 1403 mtod(m_new, char *) - (char *)sc->bge_cdata.bge_jumbo_buf, BGE_JLEN, 1404 BUS_DMASYNC_PREREAD); 1405 /* Set up the descriptor. */ 1406 r = &sc->bge_rdata->bge_rx_jumbo_ring[i]; 1407 sc->bge_cdata.bge_rx_jumbo_chain[i] = m_new; 1408 BGE_HOSTADDR(r->bge_addr, BGE_JUMBO_DMA_ADDR(sc, m_new)); 1409 r->bge_flags = BGE_RXBDFLAG_END|BGE_RXBDFLAG_JUMBO_RING; 1410 r->bge_len = m_new->m_len; 1411 r->bge_idx = i; 1412 1413 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 1414 offsetof(struct bge_ring_data, bge_rx_jumbo_ring) + 1415 i * sizeof (struct bge_rx_bd), 1416 sizeof (struct bge_rx_bd), 1417 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1418 1419 return 0; 1420 } 1421 1422 /* 1423 * The standard receive ring has 512 entries in it. At 2K per mbuf cluster, 1424 * that's 1MB or memory, which is a lot. For now, we fill only the first 1425 * 256 ring entries and hope that our CPU is fast enough to keep up with 1426 * the NIC. 1427 */ 1428 static int 1429 bge_init_rx_ring_std(struct bge_softc *sc) 1430 { 1431 int i; 1432 1433 if (sc->bge_flags & BGE_RXRING_VALID) 1434 return 0; 1435 1436 for (i = 0; i < BGE_SSLOTS; i++) { 1437 if (bge_newbuf_std(sc, i, NULL, 0) == ENOBUFS) 1438 return ENOBUFS; 1439 } 1440 1441 sc->bge_std = i - 1; 1442 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std); 1443 1444 sc->bge_flags |= BGE_RXRING_VALID; 1445 1446 return 0; 1447 } 1448 1449 static void 1450 bge_free_rx_ring_std(struct bge_softc *sc) 1451 { 1452 int i; 1453 1454 if (!(sc->bge_flags & BGE_RXRING_VALID)) 1455 return; 1456 1457 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { 1458 if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) { 1459 m_freem(sc->bge_cdata.bge_rx_std_chain[i]); 1460 sc->bge_cdata.bge_rx_std_chain[i] = NULL; 1461 bus_dmamap_destroy(sc->bge_dmatag, 1462 sc->bge_cdata.bge_rx_std_map[i]); 1463 } 1464 memset((char *)&sc->bge_rdata->bge_rx_std_ring[i], 0, 1465 sizeof(struct bge_rx_bd)); 1466 } 1467 1468 sc->bge_flags &= ~BGE_RXRING_VALID; 1469 } 1470 1471 static int 1472 bge_init_rx_ring_jumbo(struct bge_softc *sc) 1473 { 1474 int i; 1475 volatile struct bge_rcb *rcb; 1476 1477 if (sc->bge_flags & BGE_JUMBO_RXRING_VALID) 1478 return 0; 1479 1480 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 1481 if (bge_newbuf_jumbo(sc, i, NULL) == ENOBUFS) 1482 return ENOBUFS; 1483 }; 1484 1485 sc->bge_jumbo = i - 1; 1486 sc->bge_flags |= BGE_JUMBO_RXRING_VALID; 1487 1488 rcb = &sc->bge_rdata->bge_info.bge_jumbo_rx_rcb; 1489 rcb->bge_maxlen_flags = 0; 1490 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 1491 1492 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo); 1493 1494 return 0; 1495 } 1496 1497 static void 1498 bge_free_rx_ring_jumbo(struct bge_softc *sc) 1499 { 1500 int i; 1501 1502 if (!(sc->bge_flags & BGE_JUMBO_RXRING_VALID)) 1503 return; 1504 1505 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 1506 if (sc->bge_cdata.bge_rx_jumbo_chain[i] != NULL) { 1507 m_freem(sc->bge_cdata.bge_rx_jumbo_chain[i]); 1508 sc->bge_cdata.bge_rx_jumbo_chain[i] = NULL; 1509 } 1510 memset((char *)&sc->bge_rdata->bge_rx_jumbo_ring[i], 0, 1511 sizeof(struct bge_rx_bd)); 1512 } 1513 1514 sc->bge_flags &= ~BGE_JUMBO_RXRING_VALID; 1515 } 1516 1517 static void 1518 bge_free_tx_ring(struct bge_softc *sc) 1519 { 1520 int i, freed; 1521 struct txdmamap_pool_entry *dma; 1522 1523 if (!(sc->bge_flags & BGE_TXRING_VALID)) 1524 return; 1525 1526 freed = 0; 1527 1528 for (i = 0; i < BGE_TX_RING_CNT; i++) { 1529 if (sc->bge_cdata.bge_tx_chain[i] != NULL) { 1530 freed++; 1531 m_freem(sc->bge_cdata.bge_tx_chain[i]); 1532 sc->bge_cdata.bge_tx_chain[i] = NULL; 1533 SLIST_INSERT_HEAD(&sc->txdma_list, sc->txdma[i], 1534 link); 1535 sc->txdma[i] = 0; 1536 } 1537 memset((char *)&sc->bge_rdata->bge_tx_ring[i], 0, 1538 sizeof(struct bge_tx_bd)); 1539 } 1540 1541 while ((dma = SLIST_FIRST(&sc->txdma_list))) { 1542 SLIST_REMOVE_HEAD(&sc->txdma_list, link); 1543 bus_dmamap_destroy(sc->bge_dmatag, dma->dmamap); 1544 free(dma, M_DEVBUF); 1545 } 1546 1547 sc->bge_flags &= ~BGE_TXRING_VALID; 1548 } 1549 1550 static int 1551 bge_init_tx_ring(struct bge_softc *sc) 1552 { 1553 int i; 1554 bus_dmamap_t dmamap; 1555 struct txdmamap_pool_entry *dma; 1556 1557 if (sc->bge_flags & BGE_TXRING_VALID) 1558 return 0; 1559 1560 sc->bge_txcnt = 0; 1561 sc->bge_tx_saved_considx = 0; 1562 1563 /* Initialize transmit producer index for host-memory send ring. */ 1564 sc->bge_tx_prodidx = 0; 1565 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx); 1566 /* 5700 b2 errata */ 1567 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX) 1568 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx); 1569 1570 /* NIC-memory send ring not used; initialize to zero. */ 1571 bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0); 1572 /* 5700 b2 errata */ 1573 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX) 1574 bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0); 1575 1576 SLIST_INIT(&sc->txdma_list); 1577 for (i = 0; i < BGE_RSLOTS; i++) { 1578 if (bus_dmamap_create(sc->bge_dmatag, BGE_TXDMA_MAX, 1579 BGE_NTXSEG, ETHER_MAX_LEN_JUMBO, 0, BUS_DMA_NOWAIT, 1580 &dmamap)) 1581 return ENOBUFS; 1582 if (dmamap == NULL) 1583 panic("dmamap NULL in bge_init_tx_ring"); 1584 dma = malloc(sizeof(*dma), M_DEVBUF, M_NOWAIT); 1585 if (dma == NULL) { 1586 aprint_error_dev(sc->bge_dev, 1587 "can't alloc txdmamap_pool_entry\n"); 1588 bus_dmamap_destroy(sc->bge_dmatag, dmamap); 1589 return ENOMEM; 1590 } 1591 dma->dmamap = dmamap; 1592 SLIST_INSERT_HEAD(&sc->txdma_list, dma, link); 1593 } 1594 1595 sc->bge_flags |= BGE_TXRING_VALID; 1596 1597 return 0; 1598 } 1599 1600 static void 1601 bge_setmulti(struct bge_softc *sc) 1602 { 1603 struct ethercom *ac = &sc->ethercom; 1604 struct ifnet *ifp = &ac->ec_if; 1605 struct ether_multi *enm; 1606 struct ether_multistep step; 1607 uint32_t hashes[4] = { 0, 0, 0, 0 }; 1608 uint32_t h; 1609 int i; 1610 1611 if (ifp->if_flags & IFF_PROMISC) 1612 goto allmulti; 1613 1614 /* Now program new ones. */ 1615 ETHER_FIRST_MULTI(step, ac, enm); 1616 while (enm != NULL) { 1617 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1618 /* 1619 * We must listen to a range of multicast addresses. 1620 * For now, just accept all multicasts, rather than 1621 * trying to set only those filter bits needed to match 1622 * the range. (At this time, the only use of address 1623 * ranges is for IP multicast routing, for which the 1624 * range is big enough to require all bits set.) 1625 */ 1626 goto allmulti; 1627 } 1628 1629 h = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN); 1630 1631 /* Just want the 7 least-significant bits. */ 1632 h &= 0x7f; 1633 1634 hashes[(h & 0x60) >> 5] |= 1 << (h & 0x1F); 1635 ETHER_NEXT_MULTI(step, enm); 1636 } 1637 1638 ifp->if_flags &= ~IFF_ALLMULTI; 1639 goto setit; 1640 1641 allmulti: 1642 ifp->if_flags |= IFF_ALLMULTI; 1643 hashes[0] = hashes[1] = hashes[2] = hashes[3] = 0xffffffff; 1644 1645 setit: 1646 for (i = 0; i < 4; i++) 1647 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]); 1648 } 1649 1650 static void 1651 bge_sig_pre_reset(sc, type) 1652 struct bge_softc *sc; 1653 int type; 1654 { 1655 /* 1656 * Some chips don't like this so only do this if ASF is enabled 1657 */ 1658 if (sc->bge_asf_mode) 1659 bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM, BGE_MAGIC_NUMBER); 1660 1661 if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) { 1662 switch (type) { 1663 case BGE_RESET_START: 1664 bge_writemem_ind(sc, BGE_SDI_STATUS, 0x1); /* START */ 1665 break; 1666 case BGE_RESET_STOP: 1667 bge_writemem_ind(sc, BGE_SDI_STATUS, 0x2); /* UNLOAD */ 1668 break; 1669 } 1670 } 1671 } 1672 1673 static void 1674 bge_sig_post_reset(sc, type) 1675 struct bge_softc *sc; 1676 int type; 1677 { 1678 if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) { 1679 switch (type) { 1680 case BGE_RESET_START: 1681 bge_writemem_ind(sc, BGE_SDI_STATUS, 0x80000001); 1682 /* START DONE */ 1683 break; 1684 case BGE_RESET_STOP: 1685 bge_writemem_ind(sc, BGE_SDI_STATUS, 0x80000002); 1686 break; 1687 } 1688 } 1689 } 1690 1691 static void 1692 bge_sig_legacy(sc, type) 1693 struct bge_softc *sc; 1694 int type; 1695 { 1696 if (sc->bge_asf_mode) { 1697 switch (type) { 1698 case BGE_RESET_START: 1699 bge_writemem_ind(sc, BGE_SDI_STATUS, 0x1); /* START */ 1700 break; 1701 case BGE_RESET_STOP: 1702 bge_writemem_ind(sc, BGE_SDI_STATUS, 0x2); /* UNLOAD */ 1703 break; 1704 } 1705 } 1706 } 1707 1708 static void 1709 bge_stop_fw(sc) 1710 struct bge_softc *sc; 1711 { 1712 int i; 1713 1714 if (sc->bge_asf_mode) { 1715 bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM_FW, BGE_FW_PAUSE); 1716 CSR_WRITE_4(sc, BGE_CPU_EVENT, 1717 CSR_READ_4(sc, BGE_CPU_EVENT) | (1 << 14)); 1718 1719 for (i = 0; i < 100; i++ ) { 1720 if (!(CSR_READ_4(sc, BGE_CPU_EVENT) & (1 << 14))) 1721 break; 1722 DELAY(10); 1723 } 1724 } 1725 } 1726 1727 /* 1728 * Do endian, PCI and DMA initialization. Also check the on-board ROM 1729 * self-test results. 1730 */ 1731 static int 1732 bge_chipinit(struct bge_softc *sc) 1733 { 1734 int i; 1735 uint32_t dma_rw_ctl; 1736 1737 1738 /* Set endianness before we access any non-PCI registers. */ 1739 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MISC_CTL, 1740 BGE_INIT); 1741 1742 /* Set power state to D0. */ 1743 bge_setpowerstate(sc, 0); 1744 1745 /* Clear the MAC control register */ 1746 CSR_WRITE_4(sc, BGE_MAC_MODE, 0); 1747 1748 /* 1749 * Clear the MAC statistics block in the NIC's 1750 * internal memory. 1751 */ 1752 for (i = BGE_STATS_BLOCK; 1753 i < BGE_STATS_BLOCK_END + 1; i += sizeof(uint32_t)) 1754 BGE_MEMWIN_WRITE(sc->sc_pc, sc->sc_pcitag, i, 0); 1755 1756 for (i = BGE_STATUS_BLOCK; 1757 i < BGE_STATUS_BLOCK_END + 1; i += sizeof(uint32_t)) 1758 BGE_MEMWIN_WRITE(sc->sc_pc, sc->sc_pcitag, i, 0); 1759 1760 /* Set up the PCI DMA control register. */ 1761 dma_rw_ctl = BGE_PCI_READ_CMD | BGE_PCI_WRITE_CMD; 1762 if (sc->bge_flags & BGE_PCIE) { 1763 /* Read watermark not used, 128 bytes for write. */ 1764 DPRINTFN(4, ("(%s: PCI-Express DMA setting)\n", 1765 device_xname(sc->bge_dev))); 1766 dma_rw_ctl |= (0x3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT); 1767 } else if (sc->bge_flags & BGE_PCIX) { 1768 DPRINTFN(4, ("(:%s: PCI-X DMA setting)\n", 1769 device_xname(sc->bge_dev))); 1770 /* PCI-X bus */ 1771 if (BGE_IS_5714_FAMILY(sc)) { 1772 /* 256 bytes for read and write. */ 1773 dma_rw_ctl |= (0x02 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) | 1774 (0x02 << BGE_PCIDMARWCTL_WR_WAT_SHIFT); 1775 1776 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5780) 1777 dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL; 1778 else 1779 dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE_LOCAL; 1780 } else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) { 1781 /* 1536 bytes for read, 384 bytes for write. */ 1782 dma_rw_ctl |= 1783 (0x7 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) | 1784 (0x3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT); 1785 } else { 1786 /* 384 bytes for read and write. */ 1787 dma_rw_ctl |= (0x03 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) | 1788 (0x03 << BGE_PCIDMARWCTL_WR_WAT_SHIFT) | 1789 (0x0F); 1790 } 1791 1792 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5703 || 1793 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) { 1794 uint32_t tmp; 1795 1796 /* Set ONEDMA_ATONCE for hardware workaround. */ 1797 tmp = CSR_READ_4(sc, BGE_PCI_CLKCTL) & 0x1f; 1798 if (tmp == 6 || tmp == 7) 1799 dma_rw_ctl |= 1800 BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL; 1801 1802 /* Set PCI-X DMA write workaround. */ 1803 dma_rw_ctl |= BGE_PCIDMARWCTL_ASRT_ALL_BE; 1804 } 1805 } else { 1806 /* Conventional PCI bus: 256 bytes for read and write. */ 1807 DPRINTFN(4, ("(%s: PCI 2.2 DMA setting)\n", 1808 device_xname(sc->bge_dev))); 1809 dma_rw_ctl = (0x7 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) | 1810 (0x7 << BGE_PCIDMARWCTL_WR_WAT_SHIFT); 1811 if (BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5705 && 1812 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5750) 1813 dma_rw_ctl |= 0x0F; 1814 } 1815 1816 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 1817 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5701) 1818 dma_rw_ctl |= BGE_PCIDMARWCTL_USE_MRM | 1819 BGE_PCIDMARWCTL_ASRT_ALL_BE; 1820 1821 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5703 || 1822 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) 1823 dma_rw_ctl &= ~BGE_PCIDMARWCTL_MINDMA; 1824 1825 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_DMA_RW_CTL, 1826 dma_rw_ctl); 1827 1828 /* 1829 * Set up general mode register. 1830 */ 1831 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS | 1832 BGE_MODECTL_MAC_ATTN_INTR | BGE_MODECTL_HOST_SEND_BDS | 1833 BGE_MODECTL_TX_NO_PHDR_CSUM | BGE_MODECTL_RX_NO_PHDR_CSUM); 1834 1835 /* 1836 * BCM5701 B5 have a bug causing data corruption when using 1837 * 64-bit DMA reads, which can be terminated early and then 1838 * completed later as 32-bit accesses, in combination with 1839 * certain bridges. 1840 */ 1841 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5701 && 1842 sc->bge_chipid == BGE_CHIPID_BCM5701_B5) 1843 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_FORCE_PCI32); 1844 1845 /* 1846 * Tell the firmware the driver is running 1847 */ 1848 if (sc->bge_asf_mode & ASF_STACKUP) 1849 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 1850 1851 /* 1852 * Disable memory write invalidate. Apparently it is not supported 1853 * properly by these devices. 1854 */ 1855 PCI_CLRBIT(sc->sc_pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG, 1856 PCI_COMMAND_INVALIDATE_ENABLE); 1857 1858 #ifdef __brokenalpha__ 1859 /* 1860 * Must insure that we do not cross an 8K (bytes) boundary 1861 * for DMA reads. Our highest limit is 1K bytes. This is a 1862 * restriction on some ALPHA platforms with early revision 1863 * 21174 PCI chipsets, such as the AlphaPC 164lx 1864 */ 1865 PCI_SETBIT(sc, BGE_PCI_DMA_RW_CTL, BGE_PCI_READ_BNDRY_1024, 4); 1866 #endif 1867 1868 /* Set the timer prescaler (always 66MHz) */ 1869 CSR_WRITE_4(sc, BGE_MISC_CFG, 65 << 1/*BGE_32BITTIME_66MHZ*/); 1870 1871 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 1872 DELAY(40); /* XXX */ 1873 1874 /* Put PHY into ready state */ 1875 BGE_CLRBIT(sc, BGE_MISC_CFG, BGE_MISCCFG_EPHY_IDDQ); 1876 CSR_READ_4(sc, BGE_MISC_CFG); /* Flush */ 1877 DELAY(40); 1878 } 1879 1880 return 0; 1881 } 1882 1883 static int 1884 bge_blockinit(struct bge_softc *sc) 1885 { 1886 volatile struct bge_rcb *rcb; 1887 bus_size_t rcb_addr; 1888 int i; 1889 struct ifnet *ifp = &sc->ethercom.ec_if; 1890 bge_hostaddr taddr; 1891 uint32_t val; 1892 1893 /* 1894 * Initialize the memory window pointer register so that 1895 * we can access the first 32K of internal NIC RAM. This will 1896 * allow us to set up the TX send ring RCBs and the RX return 1897 * ring RCBs, plus other things which live in NIC memory. 1898 */ 1899 1900 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_BASEADDR, 0); 1901 1902 /* Configure mbuf memory pool */ 1903 if (BGE_IS_5700_FAMILY(sc)) { 1904 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, 1905 BGE_BUFFPOOL_1); 1906 1907 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) 1908 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000); 1909 else 1910 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000); 1911 1912 /* Configure DMA resource pool */ 1913 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_BASEADDR, 1914 BGE_DMA_DESCRIPTORS); 1915 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LEN, 0x2000); 1916 } 1917 1918 /* Configure mbuf pool watermarks */ 1919 #ifdef ORIG_WPAUL_VALUES 1920 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 24); 1921 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 24); 1922 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 48); 1923 #else 1924 1925 /* new broadcom docs strongly recommend these: */ 1926 if (!BGE_IS_5705_PLUS(sc)) { 1927 if (ifp->if_mtu > ETHER_MAX_LEN) { 1928 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x50); 1929 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x20); 1930 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60); 1931 } else { 1932 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 304); 1933 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 152); 1934 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 380); 1935 } 1936 } else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 1937 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0); 1938 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x04); 1939 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x10); 1940 } else { 1941 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0); 1942 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x10); 1943 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60); 1944 } 1945 #endif 1946 1947 /* Configure DMA resource watermarks */ 1948 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5); 1949 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10); 1950 1951 /* Enable buffer manager */ 1952 CSR_WRITE_4(sc, BGE_BMAN_MODE, 1953 BGE_BMANMODE_ENABLE | BGE_BMANMODE_LOMBUF_ATTN); 1954 1955 /* Poll for buffer manager start indication */ 1956 for (i = 0; i < BGE_TIMEOUT * 2; i++) { 1957 if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE) 1958 break; 1959 DELAY(10); 1960 } 1961 1962 if (i == BGE_TIMEOUT * 2) { 1963 aprint_error_dev(sc->bge_dev, 1964 "buffer manager failed to start\n"); 1965 return ENXIO; 1966 } 1967 1968 /* Enable flow-through queues */ 1969 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 1970 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 1971 1972 /* Wait until queue initialization is complete */ 1973 for (i = 0; i < BGE_TIMEOUT * 2; i++) { 1974 if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0) 1975 break; 1976 DELAY(10); 1977 } 1978 1979 if (i == BGE_TIMEOUT * 2) { 1980 aprint_error_dev(sc->bge_dev, 1981 "flow-through queue init failed\n"); 1982 return ENXIO; 1983 } 1984 1985 /* Initialize the standard RX ring control block */ 1986 rcb = &sc->bge_rdata->bge_info.bge_std_rx_rcb; 1987 BGE_HOSTADDR(rcb->bge_hostaddr, BGE_RING_DMA_ADDR(sc, bge_rx_std_ring)); 1988 if (BGE_IS_5705_PLUS(sc)) 1989 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(512, 0); 1990 else 1991 rcb->bge_maxlen_flags = 1992 BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 0); 1993 rcb->bge_nicaddr = BGE_STD_RX_RINGS; 1994 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcb->bge_hostaddr.bge_addr_hi); 1995 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcb->bge_hostaddr.bge_addr_lo); 1996 CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 1997 CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcb->bge_nicaddr); 1998 1999 /* 2000 * Initialize the jumbo RX ring control block 2001 * We set the 'ring disabled' bit in the flags 2002 * field until we're actually ready to start 2003 * using this ring (i.e. once we set the MTU 2004 * high enough to require it). 2005 */ 2006 if (BGE_IS_JUMBO_CAPABLE(sc)) { 2007 rcb = &sc->bge_rdata->bge_info.bge_jumbo_rx_rcb; 2008 BGE_HOSTADDR(rcb->bge_hostaddr, 2009 BGE_RING_DMA_ADDR(sc, bge_rx_jumbo_ring)); 2010 rcb->bge_maxlen_flags = 2011 BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 2012 BGE_RCB_FLAG_RING_DISABLED); 2013 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS; 2014 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI, 2015 rcb->bge_hostaddr.bge_addr_hi); 2016 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO, 2017 rcb->bge_hostaddr.bge_addr_lo); 2018 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, 2019 rcb->bge_maxlen_flags); 2020 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcb->bge_nicaddr); 2021 2022 /* Set up dummy disabled mini ring RCB */ 2023 rcb = &sc->bge_rdata->bge_info.bge_mini_rx_rcb; 2024 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0, 2025 BGE_RCB_FLAG_RING_DISABLED); 2026 CSR_WRITE_4(sc, BGE_RX_MINI_RCB_MAXLEN_FLAGS, 2027 rcb->bge_maxlen_flags); 2028 2029 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 2030 offsetof(struct bge_ring_data, bge_info), 2031 sizeof (struct bge_gib), 2032 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2033 } 2034 2035 /* 2036 * Set the BD ring replenish thresholds. The recommended 2037 * values are 1/8th the number of descriptors allocated to 2038 * each ring. 2039 */ 2040 i = BGE_STD_RX_RING_CNT / 8; 2041 2042 /* 2043 * Use a value of 8 for the following chips to workaround HW errata. 2044 * Some of these chips have been added based on empirical 2045 * evidence (they don't work unless this is done). 2046 */ 2047 if (BGE_IS_5705_PLUS(sc)) 2048 i = 8; 2049 2050 CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, i); 2051 CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH, BGE_JUMBO_RX_RING_CNT / 8); 2052 2053 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5717 || 2054 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57765) { 2055 CSR_WRITE_4(sc, BGE_STD_REPL_LWM, 4); 2056 CSR_WRITE_4(sc, BGE_JUMBO_REPL_LWM, 4); 2057 } 2058 2059 /* 2060 * Disable all unused send rings by setting the 'ring disabled' 2061 * bit in the flags field of all the TX send ring control blocks. 2062 * These are located in NIC memory. 2063 */ 2064 rcb_addr = BGE_MEMWIN_START + BGE_SEND_RING_RCB; 2065 for (i = 0; i < BGE_TX_RINGS_EXTSSRAM_MAX; i++) { 2066 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 2067 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED)); 2068 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 0); 2069 rcb_addr += sizeof(struct bge_rcb); 2070 } 2071 2072 /* Configure TX RCB 0 (we use only the first ring) */ 2073 rcb_addr = BGE_MEMWIN_START + BGE_SEND_RING_RCB; 2074 BGE_HOSTADDR(taddr, BGE_RING_DMA_ADDR(sc, bge_tx_ring)); 2075 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi); 2076 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo); 2077 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 2078 BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT)); 2079 if (BGE_IS_5700_FAMILY(sc)) 2080 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 2081 BGE_RCB_MAXLEN_FLAGS(BGE_TX_RING_CNT, 0)); 2082 2083 /* Disable all unused RX return rings */ 2084 rcb_addr = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB; 2085 for (i = 0; i < BGE_RX_RINGS_MAX; i++) { 2086 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_hi, 0); 2087 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_lo, 0); 2088 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 2089 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 2090 BGE_RCB_FLAG_RING_DISABLED)); 2091 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 0); 2092 bge_writembx(sc, BGE_MBX_RX_CONS0_LO + 2093 (i * (sizeof(uint64_t))), 0); 2094 rcb_addr += sizeof(struct bge_rcb); 2095 } 2096 2097 /* Initialize RX ring indexes */ 2098 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, 0); 2099 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0); 2100 bge_writembx(sc, BGE_MBX_RX_MINI_PROD_LO, 0); 2101 2102 /* 2103 * Set up RX return ring 0 2104 * Note that the NIC address for RX return rings is 0x00000000. 2105 * The return rings live entirely within the host, so the 2106 * nicaddr field in the RCB isn't used. 2107 */ 2108 rcb_addr = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB; 2109 BGE_HOSTADDR(taddr, BGE_RING_DMA_ADDR(sc, bge_rx_return_ring)); 2110 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi); 2111 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo); 2112 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 0x00000000); 2113 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 2114 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 0)); 2115 2116 /* Set random backoff seed for TX */ 2117 CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF, 2118 CLLADDR(ifp->if_sadl)[0] + CLLADDR(ifp->if_sadl)[1] + 2119 CLLADDR(ifp->if_sadl)[2] + CLLADDR(ifp->if_sadl)[3] + 2120 CLLADDR(ifp->if_sadl)[4] + CLLADDR(ifp->if_sadl)[5] + 2121 BGE_TX_BACKOFF_SEED_MASK); 2122 2123 /* Set inter-packet gap */ 2124 CSR_WRITE_4(sc, BGE_TX_LENGTHS, 0x2620); 2125 2126 /* 2127 * Specify which ring to use for packets that don't match 2128 * any RX rules. 2129 */ 2130 CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08); 2131 2132 /* 2133 * Configure number of RX lists. One interrupt distribution 2134 * list, sixteen active lists, one bad frames class. 2135 */ 2136 CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181); 2137 2138 /* Inialize RX list placement stats mask. */ 2139 CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF); 2140 CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1); 2141 2142 /* Disable host coalescing until we get it set up */ 2143 CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000); 2144 2145 /* Poll to make sure it's shut down. */ 2146 for (i = 0; i < BGE_TIMEOUT * 2; i++) { 2147 if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE)) 2148 break; 2149 DELAY(10); 2150 } 2151 2152 if (i == BGE_TIMEOUT * 2) { 2153 aprint_error_dev(sc->bge_dev, 2154 "host coalescing engine failed to idle\n"); 2155 return ENXIO; 2156 } 2157 2158 /* Set up host coalescing defaults */ 2159 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bge_rx_coal_ticks); 2160 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bge_tx_coal_ticks); 2161 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bge_rx_max_coal_bds); 2162 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bge_tx_max_coal_bds); 2163 if (BGE_IS_5700_FAMILY(sc)) { 2164 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT, 0); 2165 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT, 0); 2166 } 2167 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 0); 2168 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 0); 2169 2170 /* Set up address of statistics block */ 2171 if (BGE_IS_5700_FAMILY(sc)) { 2172 BGE_HOSTADDR(taddr, BGE_RING_DMA_ADDR(sc, bge_info.bge_stats)); 2173 CSR_WRITE_4(sc, BGE_HCC_STATS_TICKS, sc->bge_stat_ticks); 2174 CSR_WRITE_4(sc, BGE_HCC_STATS_BASEADDR, BGE_STATS_BLOCK); 2175 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_HI, taddr.bge_addr_hi); 2176 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_LO, taddr.bge_addr_lo); 2177 } 2178 2179 /* Set up address of status block */ 2180 BGE_HOSTADDR(taddr, BGE_RING_DMA_ADDR(sc, bge_status_block)); 2181 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_BASEADDR, BGE_STATUS_BLOCK); 2182 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI, taddr.bge_addr_hi); 2183 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO, taddr.bge_addr_lo); 2184 sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx = 0; 2185 sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx = 0; 2186 2187 /* Turn on host coalescing state machine */ 2188 CSR_WRITE_4(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE); 2189 2190 /* Turn on RX BD completion state machine and enable attentions */ 2191 CSR_WRITE_4(sc, BGE_RBDC_MODE, 2192 BGE_RBDCMODE_ENABLE | BGE_RBDCMODE_ATTN); 2193 2194 /* Turn on RX list placement state machine */ 2195 CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 2196 2197 /* Turn on RX list selector state machine. */ 2198 if (BGE_IS_5700_FAMILY(sc)) 2199 CSR_WRITE_4(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 2200 2201 val = BGE_MACMODE_TXDMA_ENB | BGE_MACMODE_RXDMA_ENB | 2202 BGE_MACMODE_RX_STATS_CLEAR | BGE_MACMODE_TX_STATS_CLEAR | 2203 BGE_MACMODE_RX_STATS_ENB | BGE_MACMODE_TX_STATS_ENB | 2204 BGE_MACMODE_FRMHDR_DMA_ENB; 2205 2206 if (sc->bge_flags & BGE_PHY_FIBER_TBI) 2207 val |= BGE_PORTMODE_TBI; 2208 else if (sc->bge_flags & BGE_PHY_FIBER_MII) 2209 val |= BGE_PORTMODE_GMII; 2210 else 2211 val |= BGE_PORTMODE_MII; 2212 2213 /* Turn on DMA, clear stats */ 2214 CSR_WRITE_4(sc, BGE_MAC_MODE, val); 2215 2216 /* Set misc. local control, enable interrupts on attentions */ 2217 sc->bge_local_ctrl_reg = BGE_MLC_INTR_ONATTN | BGE_MLC_AUTO_EEPROM; 2218 2219 #ifdef notdef 2220 /* Assert GPIO pins for PHY reset */ 2221 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUT0| 2222 BGE_MLC_MISCIO_OUT1|BGE_MLC_MISCIO_OUT2); 2223 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUTEN0| 2224 BGE_MLC_MISCIO_OUTEN1|BGE_MLC_MISCIO_OUTEN2); 2225 #endif 2226 2227 #if defined(not_quite_yet) 2228 /* Linux driver enables enable gpio pin #1 on 5700s */ 2229 if (sc->bge_chipid == BGE_CHIPID_BCM5700) { 2230 sc->bge_local_ctrl_reg |= 2231 (BGE_MLC_MISCIO_OUT1|BGE_MLC_MISCIO_OUTEN1); 2232 } 2233 #endif 2234 CSR_WRITE_4(sc, BGE_MISC_LOCAL_CTL, sc->bge_local_ctrl_reg); 2235 2236 /* Turn on DMA completion state machine */ 2237 if (BGE_IS_5700_FAMILY(sc)) 2238 CSR_WRITE_4(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 2239 2240 /* Turn on write DMA state machine */ 2241 { 2242 uint32_t bge_wdma_mode = 2243 BGE_WDMAMODE_ENABLE|BGE_WDMAMODE_ALL_ATTNS; 2244 2245 /* Enable host coalescing bug fix; see Linux tg3.c */ 2246 if (BGE_IS_5755_PLUS(sc)) 2247 bge_wdma_mode |= BGE_WDMAMODE_STATUS_TAG_FIX; 2248 2249 CSR_WRITE_4(sc, BGE_WDMA_MODE, bge_wdma_mode); 2250 } 2251 2252 /* Turn on read DMA state machine */ 2253 { 2254 uint32_t dma_read_modebits; 2255 2256 dma_read_modebits = 2257 BGE_RDMAMODE_ENABLE | BGE_RDMAMODE_ALL_ATTNS; 2258 2259 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5784 || 2260 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785 || 2261 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57780) 2262 dma_read_modebits |= BGE_RDMAMODE_BD_SBD_CRPT_ATTN | 2263 BGE_RDMAMODE_MBUF_RBD_CRPT_ATTN | 2264 BGE_RDMAMODE_MBUF_SBD_CRPT_ATTN; 2265 2266 if (sc->bge_flags & BGE_PCIE) 2267 dma_read_modebits |= BGE_RDMA_MODE_FIFO_LONG_BURST; 2268 if (sc->bge_flags & BGE_TSO) 2269 dma_read_modebits |= BGE_RDMAMODE_TSO4_ENABLE; 2270 CSR_WRITE_4(sc, BGE_RDMA_MODE, dma_read_modebits); 2271 delay(40); 2272 } 2273 2274 /* Turn on RX data completion state machine */ 2275 CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 2276 2277 /* Turn on RX BD initiator state machine */ 2278 CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 2279 2280 /* Turn on RX data and RX BD initiator state machine */ 2281 CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE); 2282 2283 /* Turn on Mbuf cluster free state machine */ 2284 if (BGE_IS_5700_FAMILY(sc)) 2285 CSR_WRITE_4(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 2286 2287 /* Turn on send BD completion state machine */ 2288 CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 2289 2290 /* Turn on send data completion state machine */ 2291 val = BGE_SDCMODE_ENABLE; 2292 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761) 2293 val |= BGE_SDCMODE_CDELAY; 2294 CSR_WRITE_4(sc, BGE_SDC_MODE, val); 2295 2296 /* Turn on send data initiator state machine */ 2297 if (sc->bge_flags & BGE_TSO) { 2298 /* XXX: magic value from Linux driver */ 2299 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE | 0x08); 2300 } else 2301 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 2302 2303 /* Turn on send BD initiator state machine */ 2304 CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 2305 2306 /* Turn on send BD selector state machine */ 2307 CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 2308 2309 CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF); 2310 CSR_WRITE_4(sc, BGE_SDI_STATS_CTL, 2311 BGE_SDISTATSCTL_ENABLE | BGE_SDISTATSCTL_FASTER); 2312 2313 /* ack/clear link change events */ 2314 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED | 2315 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE | 2316 BGE_MACSTAT_LINK_CHANGED); 2317 CSR_WRITE_4(sc, BGE_MI_STS, 0); 2318 2319 /* Enable PHY auto polling (for MII/GMII only) */ 2320 if (sc->bge_flags & BGE_PHY_FIBER_TBI) { 2321 CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK); 2322 } else { 2323 BGE_STS_SETBIT(sc, BGE_STS_AUTOPOLL); 2324 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL | (10 << 16)); 2325 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700) 2326 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, 2327 BGE_EVTENB_MI_INTERRUPT); 2328 } 2329 2330 /* 2331 * Clear any pending link state attention. 2332 * Otherwise some link state change events may be lost until attention 2333 * is cleared by bge_intr() -> bge_link_upd() sequence. 2334 * It's not necessary on newer BCM chips - perhaps enabling link 2335 * state change attentions implies clearing pending attention. 2336 */ 2337 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED | 2338 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE | 2339 BGE_MACSTAT_LINK_CHANGED); 2340 2341 /* Enable link state change attentions. */ 2342 BGE_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED); 2343 2344 return 0; 2345 } 2346 2347 static const struct bge_revision * 2348 bge_lookup_rev(uint32_t chipid) 2349 { 2350 const struct bge_revision *br; 2351 2352 for (br = bge_revisions; br->br_name != NULL; br++) { 2353 if (br->br_chipid == chipid) 2354 return br; 2355 } 2356 2357 for (br = bge_majorrevs; br->br_name != NULL; br++) { 2358 if (br->br_chipid == BGE_ASICREV(chipid)) 2359 return br; 2360 } 2361 2362 return NULL; 2363 } 2364 2365 static const struct bge_product * 2366 bge_lookup(const struct pci_attach_args *pa) 2367 { 2368 const struct bge_product *bp; 2369 2370 for (bp = bge_products; bp->bp_name != NULL; bp++) { 2371 if (PCI_VENDOR(pa->pa_id) == bp->bp_vendor && 2372 PCI_PRODUCT(pa->pa_id) == bp->bp_product) 2373 return bp; 2374 } 2375 2376 return NULL; 2377 } 2378 2379 static int 2380 bge_setpowerstate(struct bge_softc *sc, int powerlevel) 2381 { 2382 #ifdef NOTYET 2383 uint32_t pm_ctl = 0; 2384 2385 /* XXX FIXME: make sure indirect accesses enabled? */ 2386 pm_ctl = pci_conf_read(sc->bge_dev, BGE_PCI_MISC_CTL, 4); 2387 pm_ctl |= BGE_PCIMISCCTL_INDIRECT_ACCESS; 2388 pci_write_config(sc->bge_dev, BGE_PCI_MISC_CTL, pm_ctl, 4); 2389 2390 /* clear the PME_assert bit and power state bits, enable PME */ 2391 pm_ctl = pci_conf_read(sc->bge_dev, BGE_PCI_PWRMGMT_CMD, 2); 2392 pm_ctl &= ~PCIM_PSTAT_DMASK; 2393 pm_ctl |= (1 << 8); 2394 2395 if (powerlevel == 0) { 2396 pm_ctl |= PCIM_PSTAT_D0; 2397 pci_write_config(sc->bge_dev, BGE_PCI_PWRMGMT_CMD, 2398 pm_ctl, 2); 2399 DELAY(10000); 2400 CSR_WRITE_4(sc, BGE_MISC_LOCAL_CTL, sc->bge_local_ctrl_reg); 2401 DELAY(10000); 2402 2403 #ifdef NOTYET 2404 /* XXX FIXME: write 0x02 to phy aux_Ctrl reg */ 2405 bge_miibus_writereg(sc->bge_dev, 1, 0x18, 0x02); 2406 #endif 2407 DELAY(40); DELAY(40); DELAY(40); 2408 DELAY(10000); /* above not quite adequate on 5700 */ 2409 return 0; 2410 } 2411 2412 2413 /* 2414 * Entering ACPI power states D1-D3 is achieved by wiggling 2415 * GMII gpio pins. Example code assumes all hardware vendors 2416 * followed Broadom's sample pcb layout. Until we verify that 2417 * for all supported OEM cards, states D1-D3 are unsupported. 2418 */ 2419 aprint_error_dev(sc->bge_dev, 2420 "power state %d unimplemented; check GPIO pins\n", 2421 powerlevel); 2422 #endif 2423 return EOPNOTSUPP; 2424 } 2425 2426 2427 /* 2428 * Probe for a Broadcom chip. Check the PCI vendor and device IDs 2429 * against our list and return its name if we find a match. Note 2430 * that since the Broadcom controller contains VPD support, we 2431 * can get the device name string from the controller itself instead 2432 * of the compiled-in string. This is a little slow, but it guarantees 2433 * we'll always announce the right product name. 2434 */ 2435 static int 2436 bge_probe(device_t parent, cfdata_t match, void *aux) 2437 { 2438 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 2439 2440 if (bge_lookup(pa) != NULL) 2441 return 1; 2442 2443 return 0; 2444 } 2445 2446 static void 2447 bge_attach(device_t parent, device_t self, void *aux) 2448 { 2449 struct bge_softc *sc = device_private(self); 2450 struct pci_attach_args *pa = aux; 2451 prop_dictionary_t dict; 2452 const struct bge_product *bp; 2453 const struct bge_revision *br; 2454 pci_chipset_tag_t pc; 2455 pci_intr_handle_t ih; 2456 const char *intrstr = NULL; 2457 bus_dma_segment_t seg; 2458 int rseg; 2459 uint32_t hwcfg = 0; 2460 uint32_t command; 2461 struct ifnet *ifp; 2462 uint32_t misccfg; 2463 void * kva; 2464 u_char eaddr[ETHER_ADDR_LEN]; 2465 pcireg_t memtype, subid; 2466 bus_addr_t memaddr; 2467 bus_size_t memsize; 2468 uint32_t pm_ctl; 2469 bool no_seeprom; 2470 2471 bp = bge_lookup(pa); 2472 KASSERT(bp != NULL); 2473 2474 sc->sc_pc = pa->pa_pc; 2475 sc->sc_pcitag = pa->pa_tag; 2476 sc->bge_dev = self; 2477 2478 pc = sc->sc_pc; 2479 subid = pci_conf_read(pc, sc->sc_pcitag, PCI_SUBSYS_ID_REG); 2480 2481 aprint_naive(": Ethernet controller\n"); 2482 aprint_normal(": %s\n", bp->bp_name); 2483 2484 /* 2485 * Map control/status registers. 2486 */ 2487 DPRINTFN(5, ("Map control/status regs\n")); 2488 command = pci_conf_read(pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG); 2489 command |= PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_MASTER_ENABLE; 2490 pci_conf_write(pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG, command); 2491 command = pci_conf_read(pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG); 2492 2493 if (!(command & PCI_COMMAND_MEM_ENABLE)) { 2494 aprint_error_dev(sc->bge_dev, 2495 "failed to enable memory mapping!\n"); 2496 return; 2497 } 2498 2499 DPRINTFN(5, ("pci_mem_find\n")); 2500 memtype = pci_mapreg_type(sc->sc_pc, sc->sc_pcitag, BGE_PCI_BAR0); 2501 switch (memtype) { 2502 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 2503 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 2504 if (pci_mapreg_map(pa, BGE_PCI_BAR0, 2505 memtype, 0, &sc->bge_btag, &sc->bge_bhandle, 2506 &memaddr, &memsize) == 0) 2507 break; 2508 default: 2509 aprint_error_dev(sc->bge_dev, "can't find mem space\n"); 2510 return; 2511 } 2512 2513 DPRINTFN(5, ("pci_intr_map\n")); 2514 if (pci_intr_map(pa, &ih)) { 2515 aprint_error_dev(sc->bge_dev, "couldn't map interrupt\n"); 2516 return; 2517 } 2518 2519 DPRINTFN(5, ("pci_intr_string\n")); 2520 intrstr = pci_intr_string(pc, ih); 2521 2522 DPRINTFN(5, ("pci_intr_establish\n")); 2523 sc->bge_intrhand = pci_intr_establish(pc, ih, IPL_NET, bge_intr, sc); 2524 2525 if (sc->bge_intrhand == NULL) { 2526 aprint_error_dev(sc->bge_dev, 2527 "couldn't establish interrupt%s%s\n", 2528 intrstr ? " at " : "", intrstr ? intrstr : ""); 2529 return; 2530 } 2531 aprint_normal_dev(sc->bge_dev, "interrupting at %s\n", intrstr); 2532 2533 /* 2534 * Kludge for 5700 Bx bug: a hardware bug (PCIX byte enable?) 2535 * can clobber the chip's PCI config-space power control registers, 2536 * leaving the card in D3 powersave state. 2537 * We do not have memory-mapped registers in this state, 2538 * so force device into D0 state before starting initialization. 2539 */ 2540 pm_ctl = pci_conf_read(pc, sc->sc_pcitag, BGE_PCI_PWRMGMT_CMD); 2541 pm_ctl &= ~(PCI_PWR_D0|PCI_PWR_D1|PCI_PWR_D2|PCI_PWR_D3); 2542 pm_ctl |= (1 << 8) | PCI_PWR_D0 ; /* D0 state */ 2543 pci_conf_write(pc, sc->sc_pcitag, BGE_PCI_PWRMGMT_CMD, pm_ctl); 2544 DELAY(1000); /* 27 usec is allegedly sufficent */ 2545 2546 /* 2547 * Save ASIC rev. 2548 */ 2549 sc->bge_chipid = 2550 pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_MISC_CTL) 2551 >> BGE_PCIMISCCTL_ASICREV_SHIFT; 2552 2553 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_USE_PRODID_REG) { 2554 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5717 || 2555 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5718 || 2556 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5724) 2557 sc->bge_chipid = pci_conf_read(pc, pa->pa_tag, 2558 BGE_PCI_GEN2_PRODID_ASICREV); 2559 else if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM57761 || 2560 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM57765 || 2561 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM57781 || 2562 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM57785 || 2563 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM57791 || 2564 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM57795) 2565 sc->bge_chipid = pci_conf_read(pc, pa->pa_tag, 2566 BGE_PCI_GEN15_PRODID_ASICREV); 2567 else 2568 sc->bge_chipid = pci_conf_read(pc, pa->pa_tag, 2569 BGE_PCI_PRODID_ASICREV); 2570 } 2571 2572 if (pci_get_capability(sc->sc_pc, sc->sc_pcitag, PCI_CAP_PCIEXPRESS, 2573 &sc->bge_expcap, NULL) != 0) { 2574 /* PCIe */ 2575 sc->bge_flags |= BGE_PCIE; 2576 bge_set_max_readrq(sc); 2577 } else if ((pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_PCISTATE) & 2578 BGE_PCISTATE_PCI_BUSMODE) == 0) { 2579 /* PCI-X */ 2580 sc->bge_flags |= BGE_PCIX; 2581 } 2582 2583 /* chipid */ 2584 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 2585 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5701 || 2586 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5703 || 2587 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) 2588 sc->bge_flags |= BGE_5700_FAMILY; 2589 2590 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5714_A0 || 2591 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5780 || 2592 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5714) 2593 sc->bge_flags |= BGE_5714_FAMILY; 2594 2595 /* Intentionally exclude BGE_ASICREV_BCM5906 */ 2596 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5717 || 2597 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5755 || 2598 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761 || 2599 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5784 || 2600 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785 || 2601 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5787 || 2602 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57765 || 2603 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57780) 2604 sc->bge_flags |= BGE_5755_PLUS; 2605 2606 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5750 || 2607 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5752 || 2608 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906 || 2609 BGE_IS_5755_PLUS(sc) || 2610 BGE_IS_5714_FAMILY(sc)) 2611 sc->bge_flags |= BGE_5750_PLUS; 2612 2613 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5705 || 2614 BGE_IS_5750_OR_BEYOND(sc)) 2615 sc->bge_flags |= BGE_5705_PLUS; 2616 2617 /* 2618 * When using the BCM5701 in PCI-X mode, data corruption has 2619 * been observed in the first few bytes of some received packets. 2620 * Aligning the packet buffer in memory eliminates the corruption. 2621 * Unfortunately, this misaligns the packet payloads. On platforms 2622 * which do not support unaligned accesses, we will realign the 2623 * payloads by copying the received packets. 2624 */ 2625 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5701 && 2626 sc->bge_flags & BGE_PCIX) 2627 sc->bge_flags |= BGE_RX_ALIGNBUG; 2628 2629 if (BGE_IS_5700_FAMILY(sc)) 2630 sc->bge_flags |= BGE_JUMBO_CAPABLE; 2631 2632 if ((BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 2633 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5701) && 2634 PCI_VENDOR(subid) == PCI_VENDOR_DELL) 2635 sc->bge_flags |= BGE_NO_3LED; 2636 2637 misccfg = CSR_READ_4(sc, BGE_MISC_CFG); 2638 misccfg &= BGE_MISCCFG_BOARD_ID_MASK; 2639 2640 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5705 && 2641 (misccfg == BGE_MISCCFG_BOARD_ID_5788 || 2642 misccfg == BGE_MISCCFG_BOARD_ID_5788M)) 2643 sc->bge_flags |= BGE_IS_5788; 2644 2645 /* 2646 * Some controllers seem to require a special firmware to use 2647 * TSO. But the firmware is not available to FreeBSD and Linux 2648 * claims that the TSO performed by the firmware is slower than 2649 * hardware based TSO. Moreover the firmware based TSO has one 2650 * known bug which can't handle TSO if ethernet header + IP/TCP 2651 * header is greater than 80 bytes. The workaround for the TSO 2652 * bug exist but it seems it's too expensive than not using 2653 * TSO at all. Some hardwares also have the TSO bug so limit 2654 * the TSO to the controllers that are not affected TSO issues 2655 * (e.g. 5755 or higher). 2656 */ 2657 if (BGE_IS_5755_PLUS(sc)) { 2658 /* 2659 * BCM5754 and BCM5787 shares the same ASIC id so 2660 * explicit device id check is required. 2661 */ 2662 if ((PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_BROADCOM_BCM5754) && 2663 (PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_BROADCOM_BCM5754M)) 2664 sc->bge_flags |= BGE_TSO; 2665 } 2666 2667 if ((BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5703 && 2668 (misccfg == 0x4000 || misccfg == 0x8000)) || 2669 (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5705 && 2670 PCI_VENDOR(pa->pa_id) == PCI_VENDOR_BROADCOM && 2671 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5901 || 2672 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5901A2 || 2673 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5705F)) || 2674 (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_BROADCOM && 2675 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5751F || 2676 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5753F || 2677 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5787F)) || 2678 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM57790 || 2679 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 2680 sc->bge_flags |= BGE_10_100_ONLY; 2681 2682 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 2683 (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5705 && 2684 (sc->bge_chipid != BGE_CHIPID_BCM5705_A0 && 2685 sc->bge_chipid != BGE_CHIPID_BCM5705_A1)) || 2686 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 2687 sc->bge_flags |= BGE_NO_ETH_WIRE_SPEED; 2688 2689 if (sc->bge_chipid == BGE_CHIPID_BCM5701_A0 || 2690 sc->bge_chipid == BGE_CHIPID_BCM5701_B0) 2691 sc->bge_flags |= BGE_PHY_CRC_BUG; 2692 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5703_AX || 2693 BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5704_AX) 2694 sc->bge_flags |= BGE_PHY_ADC_BUG; 2695 if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0) 2696 sc->bge_flags |= BGE_PHY_5704_A0_BUG; 2697 2698 if (BGE_IS_5705_PLUS(sc) && 2699 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5906 && 2700 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5717 && 2701 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5785 && 2702 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM57765 && 2703 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM57780) { 2704 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5755 || 2705 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761 || 2706 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5784 || 2707 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5787) { 2708 if (PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_BROADCOM_BCM5722 && 2709 PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_BROADCOM_BCM5756) 2710 sc->bge_flags |= BGE_PHY_JITTER_BUG; 2711 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5755M) 2712 sc->bge_flags |= BGE_PHY_ADJUST_TRIM; 2713 } else if (BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5906) 2714 sc->bge_flags |= BGE_PHY_BER_BUG; 2715 } 2716 2717 /* 2718 * SEEPROM check. 2719 * First check if firmware knows we do not have SEEPROM. 2720 */ 2721 if (prop_dictionary_get_bool(device_properties(self), 2722 "without-seeprom", &no_seeprom) && no_seeprom) 2723 sc->bge_flags |= BGE_NO_EEPROM; 2724 2725 /* Now check the 'ROM failed' bit on the RX CPU */ 2726 else if (CSR_READ_4(sc, BGE_RXCPU_MODE) & BGE_RXCPUMODE_ROMFAIL) 2727 sc->bge_flags |= BGE_NO_EEPROM; 2728 2729 /* Try to reset the chip. */ 2730 DPRINTFN(5, ("bge_reset\n")); 2731 bge_reset(sc); 2732 2733 sc->bge_asf_mode = 0; 2734 if (bge_allow_asf && (bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_SIG) 2735 == BGE_MAGIC_NUMBER)) { 2736 if (bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_NICCFG) 2737 & BGE_HWCFG_ASF) { 2738 sc->bge_asf_mode |= ASF_ENABLE; 2739 sc->bge_asf_mode |= ASF_STACKUP; 2740 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5750) { 2741 sc->bge_asf_mode |= ASF_NEW_HANDSHAKE; 2742 } 2743 } 2744 } 2745 2746 /* Try to reset the chip again the nice way. */ 2747 bge_stop_fw(sc); 2748 bge_sig_pre_reset(sc, BGE_RESET_STOP); 2749 if (bge_reset(sc)) { 2750 aprint_error_dev(sc->bge_dev, "chip reset failed\n"); 2751 } 2752 2753 bge_sig_legacy(sc, BGE_RESET_STOP); 2754 bge_sig_post_reset(sc, BGE_RESET_STOP); 2755 2756 if (bge_chipinit(sc)) { 2757 aprint_error_dev(sc->bge_dev, "chip initialization failed\n"); 2758 bge_release_resources(sc); 2759 return; 2760 } 2761 2762 /* 2763 * Get station address from the EEPROM 2764 */ 2765 if (bge_get_eaddr(sc, eaddr)) { 2766 aprint_error_dev(sc->bge_dev, 2767 "failed to read station address\n"); 2768 bge_release_resources(sc); 2769 return; 2770 } 2771 2772 br = bge_lookup_rev(sc->bge_chipid); 2773 2774 if (br == NULL) { 2775 aprint_normal_dev(sc->bge_dev, "unknown ASIC (0x%x)", 2776 sc->bge_chipid); 2777 } else { 2778 aprint_normal_dev(sc->bge_dev, "ASIC %s (0x%x)", 2779 br->br_name, sc->bge_chipid); 2780 } 2781 aprint_normal(", Ethernet address %s\n", ether_sprintf(eaddr)); 2782 2783 /* Allocate the general information block and ring buffers. */ 2784 if (pci_dma64_available(pa)) 2785 sc->bge_dmatag = pa->pa_dmat64; 2786 else 2787 sc->bge_dmatag = pa->pa_dmat; 2788 DPRINTFN(5, ("bus_dmamem_alloc\n")); 2789 if (bus_dmamem_alloc(sc->bge_dmatag, sizeof(struct bge_ring_data), 2790 PAGE_SIZE, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 2791 aprint_error_dev(sc->bge_dev, "can't alloc rx buffers\n"); 2792 return; 2793 } 2794 DPRINTFN(5, ("bus_dmamem_map\n")); 2795 if (bus_dmamem_map(sc->bge_dmatag, &seg, rseg, 2796 sizeof(struct bge_ring_data), &kva, 2797 BUS_DMA_NOWAIT)) { 2798 aprint_error_dev(sc->bge_dev, 2799 "can't map DMA buffers (%zu bytes)\n", 2800 sizeof(struct bge_ring_data)); 2801 bus_dmamem_free(sc->bge_dmatag, &seg, rseg); 2802 return; 2803 } 2804 DPRINTFN(5, ("bus_dmamem_create\n")); 2805 if (bus_dmamap_create(sc->bge_dmatag, sizeof(struct bge_ring_data), 1, 2806 sizeof(struct bge_ring_data), 0, 2807 BUS_DMA_NOWAIT, &sc->bge_ring_map)) { 2808 aprint_error_dev(sc->bge_dev, "can't create DMA map\n"); 2809 bus_dmamem_unmap(sc->bge_dmatag, kva, 2810 sizeof(struct bge_ring_data)); 2811 bus_dmamem_free(sc->bge_dmatag, &seg, rseg); 2812 return; 2813 } 2814 DPRINTFN(5, ("bus_dmamem_load\n")); 2815 if (bus_dmamap_load(sc->bge_dmatag, sc->bge_ring_map, kva, 2816 sizeof(struct bge_ring_data), NULL, 2817 BUS_DMA_NOWAIT)) { 2818 bus_dmamap_destroy(sc->bge_dmatag, sc->bge_ring_map); 2819 bus_dmamem_unmap(sc->bge_dmatag, kva, 2820 sizeof(struct bge_ring_data)); 2821 bus_dmamem_free(sc->bge_dmatag, &seg, rseg); 2822 return; 2823 } 2824 2825 DPRINTFN(5, ("bzero\n")); 2826 sc->bge_rdata = (struct bge_ring_data *)kva; 2827 2828 memset(sc->bge_rdata, 0, sizeof(struct bge_ring_data)); 2829 2830 /* Try to allocate memory for jumbo buffers. */ 2831 if (BGE_IS_JUMBO_CAPABLE(sc)) { 2832 if (bge_alloc_jumbo_mem(sc)) { 2833 aprint_error_dev(sc->bge_dev, 2834 "jumbo buffer allocation failed\n"); 2835 } else 2836 sc->ethercom.ec_capabilities |= ETHERCAP_JUMBO_MTU; 2837 } 2838 2839 /* Set default tuneable values. */ 2840 sc->bge_stat_ticks = BGE_TICKS_PER_SEC; 2841 sc->bge_rx_coal_ticks = 150; 2842 sc->bge_rx_max_coal_bds = 64; 2843 #ifdef ORIG_WPAUL_VALUES 2844 sc->bge_tx_coal_ticks = 150; 2845 sc->bge_tx_max_coal_bds = 128; 2846 #else 2847 sc->bge_tx_coal_ticks = 300; 2848 sc->bge_tx_max_coal_bds = 400; 2849 #endif 2850 if (BGE_IS_5705_PLUS(sc)) { 2851 sc->bge_tx_coal_ticks = (12 * 5); 2852 sc->bge_tx_max_coal_bds = (12 * 5); 2853 aprint_verbose_dev(sc->bge_dev, 2854 "setting short Tx thresholds\n"); 2855 } 2856 2857 if (BGE_IS_5705_PLUS(sc)) 2858 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT_5705; 2859 else 2860 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT; 2861 2862 /* Set up ifnet structure */ 2863 ifp = &sc->ethercom.ec_if; 2864 ifp->if_softc = sc; 2865 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 2866 ifp->if_ioctl = bge_ioctl; 2867 ifp->if_stop = bge_stop; 2868 ifp->if_start = bge_start; 2869 ifp->if_init = bge_init; 2870 ifp->if_watchdog = bge_watchdog; 2871 IFQ_SET_MAXLEN(&ifp->if_snd, max(BGE_TX_RING_CNT - 1, IFQ_MAXLEN)); 2872 IFQ_SET_READY(&ifp->if_snd); 2873 DPRINTFN(5, ("strcpy if_xname\n")); 2874 strcpy(ifp->if_xname, device_xname(sc->bge_dev)); 2875 2876 if (sc->bge_chipid != BGE_CHIPID_BCM5700_B0) 2877 sc->ethercom.ec_if.if_capabilities |= 2878 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx; 2879 #if 1 /* XXX TCP/UDP checksum offload breaks with pf(4) */ 2880 sc->ethercom.ec_if.if_capabilities |= 2881 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 2882 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 2883 #endif 2884 sc->ethercom.ec_capabilities |= 2885 ETHERCAP_VLAN_HWTAGGING | ETHERCAP_VLAN_MTU; 2886 2887 if (sc->bge_flags & BGE_TSO) 2888 sc->ethercom.ec_if.if_capabilities |= IFCAP_TSOv4; 2889 2890 /* 2891 * Do MII setup. 2892 */ 2893 DPRINTFN(5, ("mii setup\n")); 2894 sc->bge_mii.mii_ifp = ifp; 2895 sc->bge_mii.mii_readreg = bge_miibus_readreg; 2896 sc->bge_mii.mii_writereg = bge_miibus_writereg; 2897 sc->bge_mii.mii_statchg = bge_miibus_statchg; 2898 2899 /* 2900 * Figure out what sort of media we have by checking the 2901 * hardware config word in the first 32k of NIC internal memory, 2902 * or fall back to the config word in the EEPROM. Note: on some BCM5700 2903 * cards, this value appears to be unset. If that's the 2904 * case, we have to rely on identifying the NIC by its PCI 2905 * subsystem ID, as we do below for the SysKonnect SK-9D41. 2906 */ 2907 if (bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_SIG) == BGE_MAGIC_NUMBER) { 2908 hwcfg = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_NICCFG); 2909 } else if (!(sc->bge_flags & BGE_NO_EEPROM)) { 2910 bge_read_eeprom(sc, (void *)&hwcfg, 2911 BGE_EE_HWCFG_OFFSET, sizeof(hwcfg)); 2912 hwcfg = be32toh(hwcfg); 2913 } 2914 /* The SysKonnect SK-9D41 is a 1000baseSX card. */ 2915 if (PCI_PRODUCT(pa->pa_id) == SK_SUBSYSID_9D41 || 2916 (hwcfg & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER) { 2917 if (BGE_IS_5714_FAMILY(sc)) 2918 sc->bge_flags |= BGE_PHY_FIBER_MII; 2919 else 2920 sc->bge_flags |= BGE_PHY_FIBER_TBI; 2921 } 2922 2923 /* set phyflags before mii_attach() */ 2924 dict = device_properties(self); 2925 prop_dictionary_set_uint32(dict, "phyflags", sc->bge_flags); 2926 2927 if (sc->bge_flags & BGE_PHY_FIBER_TBI) { 2928 ifmedia_init(&sc->bge_ifmedia, IFM_IMASK, bge_ifmedia_upd, 2929 bge_ifmedia_sts); 2930 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER |IFM_1000_SX, 0, NULL); 2931 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_1000_SX|IFM_FDX, 2932 0, NULL); 2933 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_AUTO, 0, NULL); 2934 ifmedia_set(&sc->bge_ifmedia, IFM_ETHER | IFM_AUTO); 2935 /* Pretend the user requested this setting */ 2936 sc->bge_ifmedia.ifm_media = sc->bge_ifmedia.ifm_cur->ifm_media; 2937 } else { 2938 /* 2939 * Do transceiver setup and tell the firmware the 2940 * driver is down so we can try to get access the 2941 * probe if ASF is running. Retry a couple of times 2942 * if we get a conflict with the ASF firmware accessing 2943 * the PHY. 2944 */ 2945 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 2946 bge_asf_driver_up(sc); 2947 2948 ifmedia_init(&sc->bge_mii.mii_media, 0, bge_ifmedia_upd, 2949 bge_ifmedia_sts); 2950 mii_attach(sc->bge_dev, &sc->bge_mii, 0xffffffff, 2951 MII_PHY_ANY, MII_OFFSET_ANY, 2952 MIIF_FORCEANEG|MIIF_DOPAUSE); 2953 2954 if (LIST_EMPTY(&sc->bge_mii.mii_phys)) { 2955 aprint_error_dev(sc->bge_dev, "no PHY found!\n"); 2956 ifmedia_add(&sc->bge_mii.mii_media, 2957 IFM_ETHER|IFM_MANUAL, 0, NULL); 2958 ifmedia_set(&sc->bge_mii.mii_media, 2959 IFM_ETHER|IFM_MANUAL); 2960 } else 2961 ifmedia_set(&sc->bge_mii.mii_media, 2962 IFM_ETHER|IFM_AUTO); 2963 2964 /* 2965 * Now tell the firmware we are going up after probing the PHY 2966 */ 2967 if (sc->bge_asf_mode & ASF_STACKUP) 2968 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 2969 } 2970 2971 /* 2972 * Call MI attach routine. 2973 */ 2974 DPRINTFN(5, ("if_attach\n")); 2975 if_attach(ifp); 2976 DPRINTFN(5, ("ether_ifattach\n")); 2977 ether_ifattach(ifp, eaddr); 2978 #if NRND > 0 2979 rnd_attach_source(&sc->rnd_source, device_xname(sc->bge_dev), 2980 RND_TYPE_NET, 0); 2981 #endif 2982 #ifdef BGE_EVENT_COUNTERS 2983 /* 2984 * Attach event counters. 2985 */ 2986 evcnt_attach_dynamic(&sc->bge_ev_intr, EVCNT_TYPE_INTR, 2987 NULL, device_xname(sc->bge_dev), "intr"); 2988 evcnt_attach_dynamic(&sc->bge_ev_tx_xoff, EVCNT_TYPE_MISC, 2989 NULL, device_xname(sc->bge_dev), "tx_xoff"); 2990 evcnt_attach_dynamic(&sc->bge_ev_tx_xon, EVCNT_TYPE_MISC, 2991 NULL, device_xname(sc->bge_dev), "tx_xon"); 2992 evcnt_attach_dynamic(&sc->bge_ev_rx_xoff, EVCNT_TYPE_MISC, 2993 NULL, device_xname(sc->bge_dev), "rx_xoff"); 2994 evcnt_attach_dynamic(&sc->bge_ev_rx_xon, EVCNT_TYPE_MISC, 2995 NULL, device_xname(sc->bge_dev), "rx_xon"); 2996 evcnt_attach_dynamic(&sc->bge_ev_rx_macctl, EVCNT_TYPE_MISC, 2997 NULL, device_xname(sc->bge_dev), "rx_macctl"); 2998 evcnt_attach_dynamic(&sc->bge_ev_xoffentered, EVCNT_TYPE_MISC, 2999 NULL, device_xname(sc->bge_dev), "xoffentered"); 3000 #endif /* BGE_EVENT_COUNTERS */ 3001 DPRINTFN(5, ("callout_init\n")); 3002 callout_init(&sc->bge_timeout, 0); 3003 3004 if (pmf_device_register(self, NULL, NULL)) 3005 pmf_class_network_register(self, ifp); 3006 else 3007 aprint_error_dev(self, "couldn't establish power handler\n"); 3008 3009 #ifdef BGE_DEBUG 3010 bge_debug_info(sc); 3011 #endif 3012 } 3013 3014 static void 3015 bge_release_resources(struct bge_softc *sc) 3016 { 3017 if (sc->bge_vpd_prodname != NULL) 3018 free(sc->bge_vpd_prodname, M_DEVBUF); 3019 3020 if (sc->bge_vpd_readonly != NULL) 3021 free(sc->bge_vpd_readonly, M_DEVBUF); 3022 } 3023 3024 static int 3025 bge_reset(struct bge_softc *sc) 3026 { 3027 uint32_t cachesize, command, pcistate, new_pcistate; 3028 pcireg_t devctl; 3029 int i, val; 3030 void (*write_op)(struct bge_softc *, int, int); 3031 3032 if (BGE_IS_5750_OR_BEYOND(sc) && !BGE_IS_5714_FAMILY(sc) && 3033 (BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5906)) { 3034 if (sc->bge_flags & BGE_PCIE) { 3035 write_op = bge_writemem_direct; 3036 } else { 3037 write_op = bge_writemem_ind; 3038 } 3039 } else { 3040 write_op = bge_writereg_ind; 3041 } 3042 3043 3044 /* Save some important PCI state. */ 3045 cachesize = pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CACHESZ); 3046 command = pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CMD); 3047 pcistate = pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_PCISTATE); 3048 3049 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MISC_CTL, 3050 BGE_PCIMISCCTL_INDIRECT_ACCESS | BGE_PCIMISCCTL_MASK_PCI_INTR | 3051 BGE_HIF_SWAP_OPTIONS | BGE_PCIMISCCTL_PCISTATE_RW); 3052 3053 /* Disable fastboot on controllers that support it. */ 3054 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5752 || 3055 BGE_IS_5755_PLUS(sc)) 3056 CSR_WRITE_4(sc, BGE_FASTBOOT_PC, 0); 3057 3058 /* 3059 * Write the magic number to SRAM at offset 0xB50. 3060 * When firmware finishes its initialization it will 3061 * write ~BGE_MAGIC_NUMBER to the same location. 3062 */ 3063 bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM, BGE_MAGIC_NUMBER); 3064 3065 val = BGE_MISCCFG_RESET_CORE_CLOCKS | (65<<1); 3066 /* 3067 * XXX: from FreeBSD/Linux; no documentation 3068 */ 3069 if (sc->bge_flags & BGE_PCIE) { 3070 if (CSR_READ_4(sc, BGE_PCIE_CTL1) == 0x60) 3071 /* PCI Express 1.0 system */ 3072 CSR_WRITE_4(sc, BGE_PCIE_CTL1, 0x20); 3073 if (sc->bge_chipid != BGE_CHIPID_BCM5750_A0) { 3074 /* 3075 * Prevent PCI Express link training 3076 * during global reset. 3077 */ 3078 CSR_WRITE_4(sc, BGE_MISC_CFG, 1 << 29); 3079 val |= (1<<29); 3080 } 3081 } 3082 3083 /* 3084 * Set GPHY Power Down Override to leave GPHY 3085 * powered up in D0 uninitialized. 3086 */ 3087 if (BGE_IS_5705_PLUS(sc)) 3088 val |= BGE_MISCCFG_KEEP_GPHY_POWER; 3089 3090 /* Issue global reset */ 3091 write_op(sc, BGE_MISC_CFG, val); 3092 3093 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 3094 i = CSR_READ_4(sc, BGE_VCPU_STATUS); 3095 CSR_WRITE_4(sc, BGE_VCPU_STATUS, 3096 i | BGE_VCPU_STATUS_DRV_RESET); 3097 i = CSR_READ_4(sc, BGE_VCPU_EXT_CTRL); 3098 CSR_WRITE_4(sc, BGE_VCPU_EXT_CTRL, 3099 i & ~BGE_VCPU_EXT_CTRL_HALT_CPU); 3100 } 3101 3102 DELAY(1000); 3103 3104 /* 3105 * XXX: from FreeBSD/Linux; no documentation 3106 */ 3107 if (sc->bge_flags & BGE_PCIE) { 3108 if (sc->bge_chipid == BGE_CHIPID_BCM5750_A0) { 3109 pcireg_t reg; 3110 3111 DELAY(500000); 3112 /* XXX: Magic Numbers */ 3113 reg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 3114 BGE_PCI_UNKNOWN0); 3115 pci_conf_write(sc->sc_pc, sc->sc_pcitag, 3116 BGE_PCI_UNKNOWN0, 3117 reg | (1 << 15)); 3118 } 3119 devctl = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 3120 sc->bge_expcap + PCI_PCIE_DCSR); 3121 /* Clear enable no snoop and disable relaxed ordering. */ 3122 devctl &= ~(0x0010 | PCI_PCIE_DCSR_ENA_NO_SNOOP); 3123 /* Set PCIE max payload size to 128. */ 3124 devctl &= ~(0x00e0); 3125 pci_conf_write(sc->sc_pc, sc->sc_pcitag, 3126 sc->bge_expcap + PCI_PCIE_DCSR, devctl); 3127 pci_conf_write(sc->sc_pc, sc->sc_pcitag, 3128 sc->bge_expcap + PCI_PCIE_DSR, 0); 3129 } 3130 3131 /* Reset some of the PCI state that got zapped by reset */ 3132 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MISC_CTL, 3133 BGE_PCIMISCCTL_INDIRECT_ACCESS | BGE_PCIMISCCTL_MASK_PCI_INTR | 3134 BGE_HIF_SWAP_OPTIONS | BGE_PCIMISCCTL_PCISTATE_RW); 3135 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CACHESZ, cachesize); 3136 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CMD, command); 3137 write_op(sc, BGE_MISC_CFG, (65 << 1)); 3138 3139 /* Enable memory arbiter. */ 3140 { 3141 uint32_t marbmode = 0; 3142 if (BGE_IS_5714_FAMILY(sc)) { 3143 marbmode = CSR_READ_4(sc, BGE_MARB_MODE); 3144 } 3145 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE | marbmode); 3146 } 3147 3148 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 3149 for (i = 0; i < BGE_TIMEOUT; i++) { 3150 val = CSR_READ_4(sc, BGE_VCPU_STATUS); 3151 if (val & BGE_VCPU_STATUS_INIT_DONE) 3152 break; 3153 DELAY(100); 3154 } 3155 if (i == BGE_TIMEOUT) { 3156 aprint_error_dev(sc->bge_dev, "reset timed out\n"); 3157 return 1; 3158 } 3159 } else { 3160 /* 3161 * Poll the value location we just wrote until 3162 * we see the 1's complement of the magic number. 3163 * This indicates that the firmware initialization 3164 * is complete. 3165 */ 3166 for (i = 0; i < BGE_TIMEOUT; i++) { 3167 val = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM); 3168 if (val == ~BGE_MAGIC_NUMBER) 3169 break; 3170 DELAY(10); 3171 } 3172 3173 if (i >= BGE_TIMEOUT && (!(sc->bge_flags & BGE_NO_EEPROM))) 3174 aprint_error_dev(sc->bge_dev, 3175 "firmware handshake timed out, val = %x\n", val); 3176 } 3177 3178 /* 3179 * XXX Wait for the value of the PCISTATE register to 3180 * return to its original pre-reset state. This is a 3181 * fairly good indicator of reset completion. If we don't 3182 * wait for the reset to fully complete, trying to read 3183 * from the device's non-PCI registers may yield garbage 3184 * results. 3185 */ 3186 for (i = 0; i < BGE_TIMEOUT; i++) { 3187 new_pcistate = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 3188 BGE_PCI_PCISTATE); 3189 if ((new_pcistate & ~BGE_PCISTATE_RESERVED) == 3190 (pcistate & ~BGE_PCISTATE_RESERVED)) 3191 break; 3192 DELAY(10); 3193 } 3194 if ((new_pcistate & ~BGE_PCISTATE_RESERVED) != 3195 (pcistate & ~BGE_PCISTATE_RESERVED)) { 3196 aprint_error_dev(sc->bge_dev, "pcistate failed to revert\n"); 3197 } 3198 3199 #if 0 3200 /* Enable memory arbiter. */ 3201 /* XXX why do this twice? */ 3202 { 3203 uint32_t marbmode = 0; 3204 if (BGE_IS_5714_FAMILY(sc)) { 3205 marbmode = CSR_READ_4(sc, BGE_MARB_MODE); 3206 } 3207 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE | marbmode); 3208 } 3209 #endif 3210 3211 /* Fix up byte swapping */ 3212 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS); 3213 3214 /* Tell the ASF firmware we are up */ 3215 if (sc->bge_asf_mode & ASF_STACKUP) 3216 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 3217 3218 CSR_WRITE_4(sc, BGE_MAC_MODE, 0); 3219 3220 /* 3221 * The 5704 in TBI mode apparently needs some special 3222 * adjustment to insure the SERDES drive level is set 3223 * to 1.2V. 3224 */ 3225 if (sc->bge_flags & BGE_PHY_FIBER_TBI && 3226 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) { 3227 uint32_t serdescfg; 3228 3229 serdescfg = CSR_READ_4(sc, BGE_SERDES_CFG); 3230 serdescfg = (serdescfg & ~0xFFF) | 0x880; 3231 CSR_WRITE_4(sc, BGE_SERDES_CFG, serdescfg); 3232 } 3233 3234 if (sc->bge_flags & BGE_PCIE && 3235 sc->bge_chipid != BGE_CHIPID_BCM5750_A0 && 3236 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5717 && 3237 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5785 && 3238 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM57765) { 3239 uint32_t v; 3240 3241 /* Enable PCI Express bug fix */ 3242 v = CSR_READ_4(sc, 0x7c00); 3243 CSR_WRITE_4(sc, 0x7c00, v | (1<<25)); 3244 } 3245 DELAY(10000); 3246 3247 return 0; 3248 } 3249 3250 /* 3251 * Frame reception handling. This is called if there's a frame 3252 * on the receive return list. 3253 * 3254 * Note: we have to be able to handle two possibilities here: 3255 * 1) the frame is from the jumbo recieve ring 3256 * 2) the frame is from the standard receive ring 3257 */ 3258 3259 static void 3260 bge_rxeof(struct bge_softc *sc) 3261 { 3262 struct ifnet *ifp; 3263 uint16_t rx_prod, rx_cons; 3264 int stdcnt = 0, jumbocnt = 0; 3265 bus_dmamap_t dmamap; 3266 bus_addr_t offset, toff; 3267 bus_size_t tlen; 3268 int tosync; 3269 3270 rx_cons = sc->bge_rx_saved_considx; 3271 rx_prod = sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx; 3272 3273 /* Nothing to do */ 3274 if (rx_cons == rx_prod) 3275 return; 3276 3277 ifp = &sc->ethercom.ec_if; 3278 3279 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 3280 offsetof(struct bge_ring_data, bge_status_block), 3281 sizeof (struct bge_status_block), 3282 BUS_DMASYNC_POSTREAD); 3283 3284 offset = offsetof(struct bge_ring_data, bge_rx_return_ring); 3285 tosync = rx_prod - rx_cons; 3286 3287 #if NRND > 0 3288 if (tosync != 0 && RND_ENABLED(&sc->rnd_source)) 3289 rnd_add_uint32(&sc->rnd_source, tosync); 3290 #endif 3291 3292 toff = offset + (rx_cons * sizeof (struct bge_rx_bd)); 3293 3294 if (tosync < 0) { 3295 tlen = (sc->bge_return_ring_cnt - rx_cons) * 3296 sizeof (struct bge_rx_bd); 3297 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 3298 toff, tlen, BUS_DMASYNC_POSTREAD); 3299 tosync = -tosync; 3300 } 3301 3302 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 3303 offset, tosync * sizeof (struct bge_rx_bd), 3304 BUS_DMASYNC_POSTREAD); 3305 3306 while (rx_cons != rx_prod) { 3307 struct bge_rx_bd *cur_rx; 3308 uint32_t rxidx; 3309 struct mbuf *m = NULL; 3310 3311 cur_rx = &sc->bge_rdata->bge_rx_return_ring[rx_cons]; 3312 3313 rxidx = cur_rx->bge_idx; 3314 BGE_INC(rx_cons, sc->bge_return_ring_cnt); 3315 3316 if (cur_rx->bge_flags & BGE_RXBDFLAG_JUMBO_RING) { 3317 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT); 3318 m = sc->bge_cdata.bge_rx_jumbo_chain[rxidx]; 3319 sc->bge_cdata.bge_rx_jumbo_chain[rxidx] = NULL; 3320 jumbocnt++; 3321 bus_dmamap_sync(sc->bge_dmatag, 3322 sc->bge_cdata.bge_rx_jumbo_map, 3323 mtod(m, char *) - (char *)sc->bge_cdata.bge_jumbo_buf, 3324 BGE_JLEN, BUS_DMASYNC_POSTREAD); 3325 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 3326 ifp->if_ierrors++; 3327 bge_newbuf_jumbo(sc, sc->bge_jumbo, m); 3328 continue; 3329 } 3330 if (bge_newbuf_jumbo(sc, sc->bge_jumbo, 3331 NULL)== ENOBUFS) { 3332 ifp->if_ierrors++; 3333 bge_newbuf_jumbo(sc, sc->bge_jumbo, m); 3334 continue; 3335 } 3336 } else { 3337 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT); 3338 m = sc->bge_cdata.bge_rx_std_chain[rxidx]; 3339 3340 sc->bge_cdata.bge_rx_std_chain[rxidx] = NULL; 3341 stdcnt++; 3342 dmamap = sc->bge_cdata.bge_rx_std_map[rxidx]; 3343 sc->bge_cdata.bge_rx_std_map[rxidx] = 0; 3344 bus_dmamap_sync(sc->bge_dmatag, dmamap, 0, 3345 dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 3346 bus_dmamap_unload(sc->bge_dmatag, dmamap); 3347 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 3348 ifp->if_ierrors++; 3349 bge_newbuf_std(sc, sc->bge_std, m, dmamap); 3350 continue; 3351 } 3352 if (bge_newbuf_std(sc, sc->bge_std, 3353 NULL, dmamap) == ENOBUFS) { 3354 ifp->if_ierrors++; 3355 bge_newbuf_std(sc, sc->bge_std, m, dmamap); 3356 continue; 3357 } 3358 } 3359 3360 ifp->if_ipackets++; 3361 #ifndef __NO_STRICT_ALIGNMENT 3362 /* 3363 * XXX: if the 5701 PCIX-Rx-DMA workaround is in effect, 3364 * the Rx buffer has the layer-2 header unaligned. 3365 * If our CPU requires alignment, re-align by copying. 3366 */ 3367 if (sc->bge_flags & BGE_RX_ALIGNBUG) { 3368 memmove(mtod(m, char *) + ETHER_ALIGN, m->m_data, 3369 cur_rx->bge_len); 3370 m->m_data += ETHER_ALIGN; 3371 } 3372 #endif 3373 3374 m->m_pkthdr.len = m->m_len = cur_rx->bge_len - ETHER_CRC_LEN; 3375 m->m_pkthdr.rcvif = ifp; 3376 3377 /* 3378 * Handle BPF listeners. Let the BPF user see the packet. 3379 */ 3380 if (ifp->if_bpf) 3381 bpf_ops->bpf_mtap(ifp->if_bpf, m); 3382 3383 m->m_pkthdr.csum_flags = M_CSUM_IPv4; 3384 3385 if ((cur_rx->bge_ip_csum ^ 0xffff) != 0) 3386 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 3387 /* 3388 * Rx transport checksum-offload may also 3389 * have bugs with packets which, when transmitted, 3390 * were `runts' requiring padding. 3391 */ 3392 if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM && 3393 (/* (sc->_bge_quirks & BGE_QUIRK_SHORT_CKSUM_BUG) == 0 ||*/ 3394 m->m_pkthdr.len >= ETHER_MIN_NOPAD)) { 3395 m->m_pkthdr.csum_data = 3396 cur_rx->bge_tcp_udp_csum; 3397 m->m_pkthdr.csum_flags |= 3398 (M_CSUM_TCPv4|M_CSUM_UDPv4| 3399 M_CSUM_DATA|M_CSUM_NO_PSEUDOHDR); 3400 } 3401 3402 /* 3403 * If we received a packet with a vlan tag, pass it 3404 * to vlan_input() instead of ether_input(). 3405 */ 3406 if (cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) { 3407 VLAN_INPUT_TAG(ifp, m, cur_rx->bge_vlan_tag, continue); 3408 } 3409 3410 (*ifp->if_input)(ifp, m); 3411 } 3412 3413 sc->bge_rx_saved_considx = rx_cons; 3414 bge_writembx(sc, BGE_MBX_RX_CONS0_LO, sc->bge_rx_saved_considx); 3415 if (stdcnt) 3416 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std); 3417 if (jumbocnt) 3418 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo); 3419 } 3420 3421 static void 3422 bge_txeof(struct bge_softc *sc) 3423 { 3424 struct bge_tx_bd *cur_tx = NULL; 3425 struct ifnet *ifp; 3426 struct txdmamap_pool_entry *dma; 3427 bus_addr_t offset, toff; 3428 bus_size_t tlen; 3429 int tosync; 3430 struct mbuf *m; 3431 3432 ifp = &sc->ethercom.ec_if; 3433 3434 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 3435 offsetof(struct bge_ring_data, bge_status_block), 3436 sizeof (struct bge_status_block), 3437 BUS_DMASYNC_POSTREAD); 3438 3439 offset = offsetof(struct bge_ring_data, bge_tx_ring); 3440 tosync = sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx - 3441 sc->bge_tx_saved_considx; 3442 3443 #if NRND > 0 3444 if (tosync != 0 && RND_ENABLED(&sc->rnd_source)) 3445 rnd_add_uint32(&sc->rnd_source, tosync); 3446 #endif 3447 3448 toff = offset + (sc->bge_tx_saved_considx * sizeof (struct bge_tx_bd)); 3449 3450 if (tosync < 0) { 3451 tlen = (BGE_TX_RING_CNT - sc->bge_tx_saved_considx) * 3452 sizeof (struct bge_tx_bd); 3453 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 3454 toff, tlen, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 3455 tosync = -tosync; 3456 } 3457 3458 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 3459 offset, tosync * sizeof (struct bge_tx_bd), 3460 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 3461 3462 /* 3463 * Go through our tx ring and free mbufs for those 3464 * frames that have been sent. 3465 */ 3466 while (sc->bge_tx_saved_considx != 3467 sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx) { 3468 uint32_t idx = 0; 3469 3470 idx = sc->bge_tx_saved_considx; 3471 cur_tx = &sc->bge_rdata->bge_tx_ring[idx]; 3472 if (cur_tx->bge_flags & BGE_TXBDFLAG_END) 3473 ifp->if_opackets++; 3474 m = sc->bge_cdata.bge_tx_chain[idx]; 3475 if (m != NULL) { 3476 sc->bge_cdata.bge_tx_chain[idx] = NULL; 3477 dma = sc->txdma[idx]; 3478 bus_dmamap_sync(sc->bge_dmatag, dma->dmamap, 0, 3479 dma->dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 3480 bus_dmamap_unload(sc->bge_dmatag, dma->dmamap); 3481 SLIST_INSERT_HEAD(&sc->txdma_list, dma, link); 3482 sc->txdma[idx] = NULL; 3483 3484 m_freem(m); 3485 } 3486 sc->bge_txcnt--; 3487 BGE_INC(sc->bge_tx_saved_considx, BGE_TX_RING_CNT); 3488 ifp->if_timer = 0; 3489 } 3490 3491 if (cur_tx != NULL) 3492 ifp->if_flags &= ~IFF_OACTIVE; 3493 } 3494 3495 static int 3496 bge_intr(void *xsc) 3497 { 3498 struct bge_softc *sc; 3499 struct ifnet *ifp; 3500 uint32_t statusword; 3501 3502 sc = xsc; 3503 ifp = &sc->ethercom.ec_if; 3504 3505 /* It is possible for the interrupt to arrive before 3506 * the status block is updated prior to the interrupt. 3507 * Reading the PCI State register will confirm whether the 3508 * interrupt is ours and will flush the status block. 3509 */ 3510 3511 /* read status word from status block */ 3512 statusword = sc->bge_rdata->bge_status_block.bge_status; 3513 3514 if ((statusword & BGE_STATFLAG_UPDATED) || 3515 (!(CSR_READ_4(sc, BGE_PCI_PCISTATE) & BGE_PCISTATE_INTR_NOT_ACTIVE))) { 3516 /* Ack interrupt and stop others from occuring. */ 3517 bge_writembx(sc, BGE_MBX_IRQ0_LO, 1); 3518 3519 BGE_EVCNT_INCR(sc->bge_ev_intr); 3520 3521 /* clear status word */ 3522 sc->bge_rdata->bge_status_block.bge_status = 0; 3523 3524 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 3525 statusword & BGE_STATFLAG_LINKSTATE_CHANGED || 3526 BGE_STS_BIT(sc, BGE_STS_LINK_EVT)) 3527 bge_link_upd(sc); 3528 3529 if (ifp->if_flags & IFF_RUNNING) { 3530 /* Check RX return ring producer/consumer */ 3531 bge_rxeof(sc); 3532 3533 /* Check TX ring producer/consumer */ 3534 bge_txeof(sc); 3535 } 3536 3537 if (sc->bge_pending_rxintr_change) { 3538 uint32_t rx_ticks = sc->bge_rx_coal_ticks; 3539 uint32_t rx_bds = sc->bge_rx_max_coal_bds; 3540 uint32_t junk; 3541 3542 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, rx_ticks); 3543 DELAY(10); 3544 junk = CSR_READ_4(sc, BGE_HCC_RX_COAL_TICKS); 3545 3546 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, rx_bds); 3547 DELAY(10); 3548 junk = CSR_READ_4(sc, BGE_HCC_RX_MAX_COAL_BDS); 3549 3550 sc->bge_pending_rxintr_change = 0; 3551 } 3552 bge_handle_events(sc); 3553 3554 /* Re-enable interrupts. */ 3555 bge_writembx(sc, BGE_MBX_IRQ0_LO, 0); 3556 3557 if (ifp->if_flags & IFF_RUNNING && !IFQ_IS_EMPTY(&ifp->if_snd)) 3558 bge_start(ifp); 3559 3560 return 1; 3561 } else 3562 return 0; 3563 } 3564 3565 static void 3566 bge_asf_driver_up(struct bge_softc *sc) 3567 { 3568 if (sc->bge_asf_mode & ASF_STACKUP) { 3569 /* Send ASF heartbeat aprox. every 2s */ 3570 if (sc->bge_asf_count) 3571 sc->bge_asf_count --; 3572 else { 3573 sc->bge_asf_count = 5; 3574 bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM_FW, 3575 BGE_FW_DRV_ALIVE); 3576 bge_writemem_ind(sc, BGE_SOFTWARE_GENNCOMM_FW_LEN, 4); 3577 bge_writemem_ind(sc, BGE_SOFTWARE_GENNCOMM_FW_DATA, 3); 3578 CSR_WRITE_4(sc, BGE_CPU_EVENT, 3579 CSR_READ_4(sc, BGE_CPU_EVENT) | (1 << 14)); 3580 } 3581 } 3582 } 3583 3584 static void 3585 bge_tick(void *xsc) 3586 { 3587 struct bge_softc *sc = xsc; 3588 struct mii_data *mii = &sc->bge_mii; 3589 int s; 3590 3591 s = splnet(); 3592 3593 if (BGE_IS_5705_PLUS(sc)) 3594 bge_stats_update_regs(sc); 3595 else 3596 bge_stats_update(sc); 3597 3598 if (sc->bge_flags & BGE_PHY_FIBER_TBI) { 3599 /* 3600 * Since in TBI mode auto-polling can't be used we should poll 3601 * link status manually. Here we register pending link event 3602 * and trigger interrupt. 3603 */ 3604 BGE_STS_SETBIT(sc, BGE_STS_LINK_EVT); 3605 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET); 3606 } else { 3607 /* 3608 * Do not touch PHY if we have link up. This could break 3609 * IPMI/ASF mode or produce extra input errors. 3610 * (extra input errors was reported for bcm5701 & bcm5704). 3611 */ 3612 if (!BGE_STS_BIT(sc, BGE_STS_LINK)) 3613 mii_tick(mii); 3614 } 3615 3616 callout_reset(&sc->bge_timeout, hz, bge_tick, sc); 3617 3618 splx(s); 3619 } 3620 3621 static void 3622 bge_stats_update_regs(struct bge_softc *sc) 3623 { 3624 struct ifnet *ifp = &sc->ethercom.ec_if; 3625 3626 ifp->if_collisions += CSR_READ_4(sc, BGE_MAC_STATS + 3627 offsetof(struct bge_mac_stats_regs, etherStatsCollisions)); 3628 3629 ifp->if_ierrors += CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_DROPS); 3630 ifp->if_ierrors += CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_ERRORS); 3631 ifp->if_ierrors += CSR_READ_4(sc, BGE_RXLP_LOCSTAT_OUT_OF_BDS); 3632 } 3633 3634 static void 3635 bge_stats_update(struct bge_softc *sc) 3636 { 3637 struct ifnet *ifp = &sc->ethercom.ec_if; 3638 bus_size_t stats = BGE_MEMWIN_START + BGE_STATS_BLOCK; 3639 3640 #define READ_STAT(sc, stats, stat) \ 3641 CSR_READ_4(sc, stats + offsetof(struct bge_stats, stat)) 3642 3643 ifp->if_collisions += 3644 (READ_STAT(sc, stats, dot3StatsSingleCollisionFrames.bge_addr_lo) + 3645 READ_STAT(sc, stats, dot3StatsMultipleCollisionFrames.bge_addr_lo) + 3646 READ_STAT(sc, stats, dot3StatsExcessiveCollisions.bge_addr_lo) + 3647 READ_STAT(sc, stats, dot3StatsLateCollisions.bge_addr_lo)) - 3648 ifp->if_collisions; 3649 3650 BGE_EVCNT_UPD(sc->bge_ev_tx_xoff, 3651 READ_STAT(sc, stats, outXoffSent.bge_addr_lo)); 3652 BGE_EVCNT_UPD(sc->bge_ev_tx_xon, 3653 READ_STAT(sc, stats, outXonSent.bge_addr_lo)); 3654 BGE_EVCNT_UPD(sc->bge_ev_rx_xoff, 3655 READ_STAT(sc, stats, 3656 xoffPauseFramesReceived.bge_addr_lo)); 3657 BGE_EVCNT_UPD(sc->bge_ev_rx_xon, 3658 READ_STAT(sc, stats, xonPauseFramesReceived.bge_addr_lo)); 3659 BGE_EVCNT_UPD(sc->bge_ev_rx_macctl, 3660 READ_STAT(sc, stats, 3661 macControlFramesReceived.bge_addr_lo)); 3662 BGE_EVCNT_UPD(sc->bge_ev_xoffentered, 3663 READ_STAT(sc, stats, xoffStateEntered.bge_addr_lo)); 3664 3665 #undef READ_STAT 3666 3667 #ifdef notdef 3668 ifp->if_collisions += 3669 (sc->bge_rdata->bge_info.bge_stats.dot3StatsSingleCollisionFrames + 3670 sc->bge_rdata->bge_info.bge_stats.dot3StatsMultipleCollisionFrames + 3671 sc->bge_rdata->bge_info.bge_stats.dot3StatsExcessiveCollisions + 3672 sc->bge_rdata->bge_info.bge_stats.dot3StatsLateCollisions) - 3673 ifp->if_collisions; 3674 #endif 3675 } 3676 3677 /* 3678 * Pad outbound frame to ETHER_MIN_NOPAD for an unusual reason. 3679 * The bge hardware will pad out Tx runts to ETHER_MIN_NOPAD, 3680 * but when such padded frames employ the bge IP/TCP checksum offload, 3681 * the hardware checksum assist gives incorrect results (possibly 3682 * from incorporating its own padding into the UDP/TCP checksum; who knows). 3683 * If we pad such runts with zeros, the onboard checksum comes out correct. 3684 */ 3685 static inline int 3686 bge_cksum_pad(struct mbuf *pkt) 3687 { 3688 struct mbuf *last = NULL; 3689 int padlen; 3690 3691 padlen = ETHER_MIN_NOPAD - pkt->m_pkthdr.len; 3692 3693 /* if there's only the packet-header and we can pad there, use it. */ 3694 if (pkt->m_pkthdr.len == pkt->m_len && 3695 M_TRAILINGSPACE(pkt) >= padlen) { 3696 last = pkt; 3697 } else { 3698 /* 3699 * Walk packet chain to find last mbuf. We will either 3700 * pad there, or append a new mbuf and pad it 3701 * (thus perhaps avoiding the bcm5700 dma-min bug). 3702 */ 3703 for (last = pkt; last->m_next != NULL; last = last->m_next) { 3704 continue; /* do nothing */ 3705 } 3706 3707 /* `last' now points to last in chain. */ 3708 if (M_TRAILINGSPACE(last) < padlen) { 3709 /* Allocate new empty mbuf, pad it. Compact later. */ 3710 struct mbuf *n; 3711 MGET(n, M_DONTWAIT, MT_DATA); 3712 if (n == NULL) 3713 return ENOBUFS; 3714 n->m_len = 0; 3715 last->m_next = n; 3716 last = n; 3717 } 3718 } 3719 3720 KDASSERT(!M_READONLY(last)); 3721 KDASSERT(M_TRAILINGSPACE(last) >= padlen); 3722 3723 /* Now zero the pad area, to avoid the bge cksum-assist bug */ 3724 memset(mtod(last, char *) + last->m_len, 0, padlen); 3725 last->m_len += padlen; 3726 pkt->m_pkthdr.len += padlen; 3727 return 0; 3728 } 3729 3730 /* 3731 * Compact outbound packets to avoid bug with DMA segments less than 8 bytes. 3732 */ 3733 static inline int 3734 bge_compact_dma_runt(struct mbuf *pkt) 3735 { 3736 struct mbuf *m, *prev; 3737 int totlen, prevlen; 3738 3739 prev = NULL; 3740 totlen = 0; 3741 prevlen = -1; 3742 3743 for (m = pkt; m != NULL; prev = m,m = m->m_next) { 3744 int mlen = m->m_len; 3745 int shortfall = 8 - mlen ; 3746 3747 totlen += mlen; 3748 if (mlen == 0) { 3749 continue; 3750 } 3751 if (mlen >= 8) 3752 continue; 3753 3754 /* If we get here, mbuf data is too small for DMA engine. 3755 * Try to fix by shuffling data to prev or next in chain. 3756 * If that fails, do a compacting deep-copy of the whole chain. 3757 */ 3758 3759 /* Internal frag. If fits in prev, copy it there. */ 3760 if (prev && M_TRAILINGSPACE(prev) >= m->m_len) { 3761 memcpy(prev->m_data + prev->m_len, m->m_data, mlen); 3762 prev->m_len += mlen; 3763 m->m_len = 0; 3764 /* XXX stitch chain */ 3765 prev->m_next = m_free(m); 3766 m = prev; 3767 continue; 3768 } 3769 else if (m->m_next != NULL && 3770 M_TRAILINGSPACE(m) >= shortfall && 3771 m->m_next->m_len >= (8 + shortfall)) { 3772 /* m is writable and have enough data in next, pull up. */ 3773 3774 memcpy(m->m_data + m->m_len, m->m_next->m_data, 3775 shortfall); 3776 m->m_len += shortfall; 3777 m->m_next->m_len -= shortfall; 3778 m->m_next->m_data += shortfall; 3779 } 3780 else if (m->m_next == NULL || 1) { 3781 /* Got a runt at the very end of the packet. 3782 * borrow data from the tail of the preceding mbuf and 3783 * update its length in-place. (The original data is still 3784 * valid, so we can do this even if prev is not writable.) 3785 */ 3786 3787 /* if we'd make prev a runt, just move all of its data. */ 3788 KASSERT(prev != NULL /*, ("runt but null PREV")*/); 3789 KASSERT(prev->m_len >= 8 /*, ("runt prev")*/); 3790 3791 if ((prev->m_len - shortfall) < 8) 3792 shortfall = prev->m_len; 3793 3794 #ifdef notyet /* just do the safe slow thing for now */ 3795 if (!M_READONLY(m)) { 3796 if (M_LEADINGSPACE(m) < shorfall) { 3797 void *m_dat; 3798 m_dat = (m->m_flags & M_PKTHDR) ? 3799 m->m_pktdat : m->dat; 3800 memmove(m_dat, mtod(m, void*), m->m_len); 3801 m->m_data = m_dat; 3802 } 3803 } else 3804 #endif /* just do the safe slow thing */ 3805 { 3806 struct mbuf * n = NULL; 3807 int newprevlen = prev->m_len - shortfall; 3808 3809 MGET(n, M_NOWAIT, MT_DATA); 3810 if (n == NULL) 3811 return ENOBUFS; 3812 KASSERT(m->m_len + shortfall < MLEN 3813 /*, 3814 ("runt %d +prev %d too big\n", m->m_len, shortfall)*/); 3815 3816 /* first copy the data we're stealing from prev */ 3817 memcpy(n->m_data, prev->m_data + newprevlen, 3818 shortfall); 3819 3820 /* update prev->m_len accordingly */ 3821 prev->m_len -= shortfall; 3822 3823 /* copy data from runt m */ 3824 memcpy(n->m_data + shortfall, m->m_data, 3825 m->m_len); 3826 3827 /* n holds what we stole from prev, plus m */ 3828 n->m_len = shortfall + m->m_len; 3829 3830 /* stitch n into chain and free m */ 3831 n->m_next = m->m_next; 3832 prev->m_next = n; 3833 /* KASSERT(m->m_next == NULL); */ 3834 m->m_next = NULL; 3835 m_free(m); 3836 m = n; /* for continuing loop */ 3837 } 3838 } 3839 prevlen = m->m_len; 3840 } 3841 return 0; 3842 } 3843 3844 /* 3845 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data 3846 * pointers to descriptors. 3847 */ 3848 static int 3849 bge_encap(struct bge_softc *sc, struct mbuf *m_head, uint32_t *txidx) 3850 { 3851 struct bge_tx_bd *f = NULL; 3852 uint32_t frag, cur; 3853 uint16_t csum_flags = 0; 3854 uint16_t txbd_tso_flags = 0; 3855 struct txdmamap_pool_entry *dma; 3856 bus_dmamap_t dmamap; 3857 int i = 0; 3858 struct m_tag *mtag; 3859 int use_tso, maxsegsize, error; 3860 3861 cur = frag = *txidx; 3862 3863 if (m_head->m_pkthdr.csum_flags) { 3864 if (m_head->m_pkthdr.csum_flags & M_CSUM_IPv4) 3865 csum_flags |= BGE_TXBDFLAG_IP_CSUM; 3866 if (m_head->m_pkthdr.csum_flags & (M_CSUM_TCPv4|M_CSUM_UDPv4)) 3867 csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM; 3868 } 3869 3870 /* 3871 * If we were asked to do an outboard checksum, and the NIC 3872 * has the bug where it sometimes adds in the Ethernet padding, 3873 * explicitly pad with zeros so the cksum will be correct either way. 3874 * (For now, do this for all chip versions, until newer 3875 * are confirmed to not require the workaround.) 3876 */ 3877 if ((csum_flags & BGE_TXBDFLAG_TCP_UDP_CSUM) == 0 || 3878 #ifdef notyet 3879 (sc->bge_quirks & BGE_QUIRK_SHORT_CKSUM_BUG) == 0 || 3880 #endif 3881 m_head->m_pkthdr.len >= ETHER_MIN_NOPAD) 3882 goto check_dma_bug; 3883 3884 if (bge_cksum_pad(m_head) != 0) 3885 return ENOBUFS; 3886 3887 check_dma_bug: 3888 if (!(BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX)) 3889 goto doit; 3890 3891 /* 3892 * bcm5700 Revision B silicon cannot handle DMA descriptors with 3893 * less than eight bytes. If we encounter a teeny mbuf 3894 * at the end of a chain, we can pad. Otherwise, copy. 3895 */ 3896 if (bge_compact_dma_runt(m_head) != 0) 3897 return ENOBUFS; 3898 3899 doit: 3900 dma = SLIST_FIRST(&sc->txdma_list); 3901 if (dma == NULL) 3902 return ENOBUFS; 3903 dmamap = dma->dmamap; 3904 3905 /* 3906 * Set up any necessary TSO state before we start packing... 3907 */ 3908 use_tso = (m_head->m_pkthdr.csum_flags & M_CSUM_TSOv4) != 0; 3909 if (!use_tso) { 3910 maxsegsize = 0; 3911 } else { /* TSO setup */ 3912 unsigned mss; 3913 struct ether_header *eh; 3914 unsigned ip_tcp_hlen, iptcp_opt_words, tcp_seg_flags, offset; 3915 struct mbuf * m0 = m_head; 3916 struct ip *ip; 3917 struct tcphdr *th; 3918 int iphl, hlen; 3919 3920 /* 3921 * XXX It would be nice if the mbuf pkthdr had offset 3922 * fields for the protocol headers. 3923 */ 3924 3925 eh = mtod(m0, struct ether_header *); 3926 switch (htons(eh->ether_type)) { 3927 case ETHERTYPE_IP: 3928 offset = ETHER_HDR_LEN; 3929 break; 3930 3931 case ETHERTYPE_VLAN: 3932 offset = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 3933 break; 3934 3935 default: 3936 /* 3937 * Don't support this protocol or encapsulation. 3938 */ 3939 return ENOBUFS; 3940 } 3941 3942 /* 3943 * TCP/IP headers are in the first mbuf; we can do 3944 * this the easy way. 3945 */ 3946 iphl = M_CSUM_DATA_IPv4_IPHL(m0->m_pkthdr.csum_data); 3947 hlen = iphl + offset; 3948 if (__predict_false(m0->m_len < 3949 (hlen + sizeof(struct tcphdr)))) { 3950 3951 aprint_debug_dev(sc->bge_dev, 3952 "TSO: hard case m0->m_len == %d < ip/tcp hlen %zd," 3953 "not handled yet\n", 3954 m0->m_len, hlen+ sizeof(struct tcphdr)); 3955 #ifdef NOTYET 3956 /* 3957 * XXX jonathan (at) NetBSD.org: untested. 3958 * how to force this branch to be taken? 3959 */ 3960 BGE_EVCNT_INCR(&sc->sc_ev_txtsopain); 3961 3962 m_copydata(m0, offset, sizeof(ip), &ip); 3963 m_copydata(m0, hlen, sizeof(th), &th); 3964 3965 ip.ip_len = 0; 3966 3967 m_copyback(m0, hlen + offsetof(struct ip, ip_len), 3968 sizeof(ip.ip_len), &ip.ip_len); 3969 3970 th.th_sum = in_cksum_phdr(ip.ip_src.s_addr, 3971 ip.ip_dst.s_addr, htons(IPPROTO_TCP)); 3972 3973 m_copyback(m0, hlen + offsetof(struct tcphdr, th_sum), 3974 sizeof(th.th_sum), &th.th_sum); 3975 3976 hlen += th.th_off << 2; 3977 iptcp_opt_words = hlen; 3978 #else 3979 /* 3980 * if_wm "hard" case not yet supported, can we not 3981 * mandate it out of existence? 3982 */ 3983 (void) ip; (void)th; (void) ip_tcp_hlen; 3984 3985 return ENOBUFS; 3986 #endif 3987 } else { 3988 ip = (struct ip *) (mtod(m0, char *) + offset); 3989 th = (struct tcphdr *) (mtod(m0, char *) + hlen); 3990 ip_tcp_hlen = iphl + (th->th_off << 2); 3991 3992 /* Total IP/TCP options, in 32-bit words */ 3993 iptcp_opt_words = (ip_tcp_hlen 3994 - sizeof(struct tcphdr) 3995 - sizeof(struct ip)) >> 2; 3996 } 3997 if (BGE_IS_5750_OR_BEYOND(sc)) { 3998 th->th_sum = 0; 3999 csum_flags &= ~(BGE_TXBDFLAG_TCP_UDP_CSUM); 4000 } else { 4001 /* 4002 * XXX jonathan (at) NetBSD.org: 5705 untested. 4003 * Requires TSO firmware patch for 5701/5703/5704. 4004 */ 4005 th->th_sum = in_cksum_phdr(ip->ip_src.s_addr, 4006 ip->ip_dst.s_addr, htons(IPPROTO_TCP)); 4007 } 4008 4009 mss = m_head->m_pkthdr.segsz; 4010 txbd_tso_flags |= 4011 BGE_TXBDFLAG_CPU_PRE_DMA | 4012 BGE_TXBDFLAG_CPU_POST_DMA; 4013 4014 /* 4015 * Our NIC TSO-assist assumes TSO has standard, optionless 4016 * IPv4 and TCP headers, which total 40 bytes. By default, 4017 * the NIC copies 40 bytes of IP/TCP header from the 4018 * supplied header into the IP/TCP header portion of 4019 * each post-TSO-segment. If the supplied packet has IP or 4020 * TCP options, we need to tell the NIC to copy those extra 4021 * bytes into each post-TSO header, in addition to the normal 4022 * 40-byte IP/TCP header (and to leave space accordingly). 4023 * Unfortunately, the driver encoding of option length 4024 * varies across different ASIC families. 4025 */ 4026 tcp_seg_flags = 0; 4027 if (iptcp_opt_words) { 4028 if (BGE_IS_5705_PLUS(sc)) { 4029 tcp_seg_flags = 4030 iptcp_opt_words << 11; 4031 } else { 4032 txbd_tso_flags |= 4033 iptcp_opt_words << 12; 4034 } 4035 } 4036 maxsegsize = mss | tcp_seg_flags; 4037 ip->ip_len = htons(mss + ip_tcp_hlen); 4038 4039 } /* TSO setup */ 4040 4041 /* 4042 * Start packing the mbufs in this chain into 4043 * the fragment pointers. Stop when we run out 4044 * of fragments or hit the end of the mbuf chain. 4045 */ 4046 error = bus_dmamap_load_mbuf(sc->bge_dmatag, dmamap, m_head, 4047 BUS_DMA_NOWAIT); 4048 if (error) 4049 return ENOBUFS; 4050 /* 4051 * Sanity check: avoid coming within 16 descriptors 4052 * of the end of the ring. 4053 */ 4054 if (dmamap->dm_nsegs > (BGE_TX_RING_CNT - sc->bge_txcnt - 16)) { 4055 BGE_TSO_PRINTF(("%s: " 4056 " dmamap_load_mbuf too close to ring wrap\n", 4057 device_xname(sc->bge_dev))); 4058 goto fail_unload; 4059 } 4060 4061 mtag = sc->ethercom.ec_nvlans ? 4062 m_tag_find(m_head, PACKET_TAG_VLAN, NULL) : NULL; 4063 4064 4065 /* Iterate over dmap-map fragments. */ 4066 for (i = 0; i < dmamap->dm_nsegs; i++) { 4067 f = &sc->bge_rdata->bge_tx_ring[frag]; 4068 if (sc->bge_cdata.bge_tx_chain[frag] != NULL) 4069 break; 4070 4071 BGE_HOSTADDR(f->bge_addr, dmamap->dm_segs[i].ds_addr); 4072 f->bge_len = dmamap->dm_segs[i].ds_len; 4073 4074 /* 4075 * For 5751 and follow-ons, for TSO we must turn 4076 * off checksum-assist flag in the tx-descr, and 4077 * supply the ASIC-revision-specific encoding 4078 * of TSO flags and segsize. 4079 */ 4080 if (use_tso) { 4081 if (BGE_IS_5750_OR_BEYOND(sc) || i == 0) { 4082 f->bge_rsvd = maxsegsize; 4083 f->bge_flags = csum_flags | txbd_tso_flags; 4084 } else { 4085 f->bge_rsvd = 0; 4086 f->bge_flags = 4087 (csum_flags | txbd_tso_flags) & 0x0fff; 4088 } 4089 } else { 4090 f->bge_rsvd = 0; 4091 f->bge_flags = csum_flags; 4092 } 4093 4094 if (mtag != NULL) { 4095 f->bge_flags |= BGE_TXBDFLAG_VLAN_TAG; 4096 f->bge_vlan_tag = VLAN_TAG_VALUE(mtag); 4097 } else { 4098 f->bge_vlan_tag = 0; 4099 } 4100 cur = frag; 4101 BGE_INC(frag, BGE_TX_RING_CNT); 4102 } 4103 4104 if (i < dmamap->dm_nsegs) { 4105 BGE_TSO_PRINTF(("%s: reached %d < dm_nsegs %d\n", 4106 device_xname(sc->bge_dev), i, dmamap->dm_nsegs)); 4107 goto fail_unload; 4108 } 4109 4110 bus_dmamap_sync(sc->bge_dmatag, dmamap, 0, dmamap->dm_mapsize, 4111 BUS_DMASYNC_PREWRITE); 4112 4113 if (frag == sc->bge_tx_saved_considx) { 4114 BGE_TSO_PRINTF(("%s: frag %d = wrapped id %d?\n", 4115 device_xname(sc->bge_dev), frag, sc->bge_tx_saved_considx)); 4116 4117 goto fail_unload; 4118 } 4119 4120 sc->bge_rdata->bge_tx_ring[cur].bge_flags |= BGE_TXBDFLAG_END; 4121 sc->bge_cdata.bge_tx_chain[cur] = m_head; 4122 SLIST_REMOVE_HEAD(&sc->txdma_list, link); 4123 sc->txdma[cur] = dma; 4124 sc->bge_txcnt += dmamap->dm_nsegs; 4125 4126 *txidx = frag; 4127 4128 return 0; 4129 4130 fail_unload: 4131 bus_dmamap_unload(sc->bge_dmatag, dmamap); 4132 4133 return ENOBUFS; 4134 } 4135 4136 /* 4137 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 4138 * to the mbuf data regions directly in the transmit descriptors. 4139 */ 4140 static void 4141 bge_start(struct ifnet *ifp) 4142 { 4143 struct bge_softc *sc; 4144 struct mbuf *m_head = NULL; 4145 uint32_t prodidx; 4146 int pkts = 0; 4147 4148 sc = ifp->if_softc; 4149 4150 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 4151 return; 4152 4153 prodidx = sc->bge_tx_prodidx; 4154 4155 while (sc->bge_cdata.bge_tx_chain[prodidx] == NULL) { 4156 IFQ_POLL(&ifp->if_snd, m_head); 4157 if (m_head == NULL) 4158 break; 4159 4160 #if 0 4161 /* 4162 * XXX 4163 * safety overkill. If this is a fragmented packet chain 4164 * with delayed TCP/UDP checksums, then only encapsulate 4165 * it if we have enough descriptors to handle the entire 4166 * chain at once. 4167 * (paranoia -- may not actually be needed) 4168 */ 4169 if (m_head->m_flags & M_FIRSTFRAG && 4170 m_head->m_pkthdr.csum_flags & (CSUM_DELAY_DATA)) { 4171 if ((BGE_TX_RING_CNT - sc->bge_txcnt) < 4172 M_CSUM_DATA_IPv4_OFFSET(m_head->m_pkthdr.csum_data) + 16) { 4173 ifp->if_flags |= IFF_OACTIVE; 4174 break; 4175 } 4176 } 4177 #endif 4178 4179 /* 4180 * Pack the data into the transmit ring. If we 4181 * don't have room, set the OACTIVE flag and wait 4182 * for the NIC to drain the ring. 4183 */ 4184 if (bge_encap(sc, m_head, &prodidx)) { 4185 ifp->if_flags |= IFF_OACTIVE; 4186 break; 4187 } 4188 4189 /* now we are committed to transmit the packet */ 4190 IFQ_DEQUEUE(&ifp->if_snd, m_head); 4191 pkts++; 4192 4193 /* 4194 * If there's a BPF listener, bounce a copy of this frame 4195 * to him. 4196 */ 4197 if (ifp->if_bpf) 4198 bpf_ops->bpf_mtap(ifp->if_bpf, m_head); 4199 } 4200 if (pkts == 0) 4201 return; 4202 4203 /* Transmit */ 4204 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); 4205 /* 5700 b2 errata */ 4206 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX) 4207 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); 4208 4209 sc->bge_tx_prodidx = prodidx; 4210 4211 /* 4212 * Set a timeout in case the chip goes out to lunch. 4213 */ 4214 ifp->if_timer = 5; 4215 } 4216 4217 static int 4218 bge_init(struct ifnet *ifp) 4219 { 4220 struct bge_softc *sc = ifp->if_softc; 4221 const uint16_t *m; 4222 int s, error = 0; 4223 4224 s = splnet(); 4225 4226 ifp = &sc->ethercom.ec_if; 4227 4228 /* Cancel pending I/O and flush buffers. */ 4229 bge_stop(ifp, 0); 4230 4231 bge_stop_fw(sc); 4232 bge_sig_pre_reset(sc, BGE_RESET_START); 4233 bge_reset(sc); 4234 bge_sig_legacy(sc, BGE_RESET_START); 4235 bge_sig_post_reset(sc, BGE_RESET_START); 4236 4237 bge_chipinit(sc); 4238 4239 /* 4240 * Init the various state machines, ring 4241 * control blocks and firmware. 4242 */ 4243 error = bge_blockinit(sc); 4244 if (error != 0) { 4245 aprint_error_dev(sc->bge_dev, "initialization error %d\n", 4246 error); 4247 splx(s); 4248 return error; 4249 } 4250 4251 ifp = &sc->ethercom.ec_if; 4252 4253 /* Specify MTU. */ 4254 CSR_WRITE_4(sc, BGE_RX_MTU, ifp->if_mtu + 4255 ETHER_HDR_LEN + ETHER_CRC_LEN + ETHER_VLAN_ENCAP_LEN); 4256 4257 /* Load our MAC address. */ 4258 m = (const uint16_t *)&(CLLADDR(ifp->if_sadl)[0]); 4259 CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0])); 4260 CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, (htons(m[1]) << 16) | htons(m[2])); 4261 4262 /* Enable or disable promiscuous mode as needed. */ 4263 if (ifp->if_flags & IFF_PROMISC) { 4264 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 4265 } else { 4266 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 4267 } 4268 4269 /* Program multicast filter. */ 4270 bge_setmulti(sc); 4271 4272 /* Init RX ring. */ 4273 bge_init_rx_ring_std(sc); 4274 4275 /* 4276 * Workaround for a bug in 5705 ASIC rev A0. Poll the NIC's 4277 * memory to insure that the chip has in fact read the first 4278 * entry of the ring. 4279 */ 4280 if (sc->bge_chipid == BGE_CHIPID_BCM5705_A0) { 4281 uint32_t v, i; 4282 for (i = 0; i < 10; i++) { 4283 DELAY(20); 4284 v = bge_readmem_ind(sc, BGE_STD_RX_RINGS + 8); 4285 if (v == (MCLBYTES - ETHER_ALIGN)) 4286 break; 4287 } 4288 if (i == 10) 4289 aprint_error_dev(sc->bge_dev, 4290 "5705 A0 chip failed to load RX ring\n"); 4291 } 4292 4293 /* Init jumbo RX ring. */ 4294 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 4295 bge_init_rx_ring_jumbo(sc); 4296 4297 /* Init our RX return ring index */ 4298 sc->bge_rx_saved_considx = 0; 4299 4300 /* Init TX ring. */ 4301 bge_init_tx_ring(sc); 4302 4303 /* Turn on transmitter */ 4304 BGE_SETBIT(sc, BGE_TX_MODE, BGE_TXMODE_ENABLE); 4305 4306 /* Turn on receiver */ 4307 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE); 4308 4309 CSR_WRITE_4(sc, BGE_MAX_RX_FRAME_LOWAT, 2); 4310 4311 /* Tell firmware we're alive. */ 4312 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 4313 4314 /* Enable host interrupts. */ 4315 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA); 4316 BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); 4317 bge_writembx(sc, BGE_MBX_IRQ0_LO, 0); 4318 4319 if ((error = bge_ifmedia_upd(ifp)) != 0) 4320 goto out; 4321 4322 ifp->if_flags |= IFF_RUNNING; 4323 ifp->if_flags &= ~IFF_OACTIVE; 4324 4325 callout_reset(&sc->bge_timeout, hz, bge_tick, sc); 4326 4327 out: 4328 splx(s); 4329 4330 return error; 4331 } 4332 4333 /* 4334 * Set media options. 4335 */ 4336 static int 4337 bge_ifmedia_upd(struct ifnet *ifp) 4338 { 4339 struct bge_softc *sc = ifp->if_softc; 4340 struct mii_data *mii = &sc->bge_mii; 4341 struct ifmedia *ifm = &sc->bge_ifmedia; 4342 int rc; 4343 4344 /* If this is a 1000baseX NIC, enable the TBI port. */ 4345 if (sc->bge_flags & BGE_PHY_FIBER_TBI) { 4346 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 4347 return EINVAL; 4348 switch (IFM_SUBTYPE(ifm->ifm_media)) { 4349 case IFM_AUTO: 4350 /* 4351 * The BCM5704 ASIC appears to have a special 4352 * mechanism for programming the autoneg 4353 * advertisement registers in TBI mode. 4354 */ 4355 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) { 4356 uint32_t sgdig; 4357 sgdig = CSR_READ_4(sc, BGE_SGDIG_STS); 4358 if (sgdig & BGE_SGDIGSTS_DONE) { 4359 CSR_WRITE_4(sc, BGE_TX_TBI_AUTONEG, 0); 4360 sgdig = CSR_READ_4(sc, BGE_SGDIG_CFG); 4361 sgdig |= BGE_SGDIGCFG_AUTO | 4362 BGE_SGDIGCFG_PAUSE_CAP | 4363 BGE_SGDIGCFG_ASYM_PAUSE; 4364 CSR_WRITE_4(sc, BGE_SGDIG_CFG, 4365 sgdig | BGE_SGDIGCFG_SEND); 4366 DELAY(5); 4367 CSR_WRITE_4(sc, BGE_SGDIG_CFG, sgdig); 4368 } 4369 } 4370 break; 4371 case IFM_1000_SX: 4372 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 4373 BGE_CLRBIT(sc, BGE_MAC_MODE, 4374 BGE_MACMODE_HALF_DUPLEX); 4375 } else { 4376 BGE_SETBIT(sc, BGE_MAC_MODE, 4377 BGE_MACMODE_HALF_DUPLEX); 4378 } 4379 break; 4380 default: 4381 return EINVAL; 4382 } 4383 /* XXX 802.3x flow control for 1000BASE-SX */ 4384 return 0; 4385 } 4386 4387 BGE_STS_SETBIT(sc, BGE_STS_LINK_EVT); 4388 if ((rc = mii_mediachg(mii)) == ENXIO) 4389 return 0; 4390 4391 /* 4392 * Force an interrupt so that we will call bge_link_upd 4393 * if needed and clear any pending link state attention. 4394 * Without this we are not getting any further interrupts 4395 * for link state changes and thus will not UP the link and 4396 * not be able to send in bge_start. The only way to get 4397 * things working was to receive a packet and get a RX intr. 4398 */ 4399 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 4400 sc->bge_flags & BGE_IS_5788) 4401 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET); 4402 else 4403 BGE_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW); 4404 4405 return rc; 4406 } 4407 4408 /* 4409 * Report current media status. 4410 */ 4411 static void 4412 bge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 4413 { 4414 struct bge_softc *sc = ifp->if_softc; 4415 struct mii_data *mii = &sc->bge_mii; 4416 4417 if (sc->bge_flags & BGE_PHY_FIBER_TBI) { 4418 ifmr->ifm_status = IFM_AVALID; 4419 ifmr->ifm_active = IFM_ETHER; 4420 if (CSR_READ_4(sc, BGE_MAC_STS) & 4421 BGE_MACSTAT_TBI_PCS_SYNCHED) 4422 ifmr->ifm_status |= IFM_ACTIVE; 4423 ifmr->ifm_active |= IFM_1000_SX; 4424 if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX) 4425 ifmr->ifm_active |= IFM_HDX; 4426 else 4427 ifmr->ifm_active |= IFM_FDX; 4428 return; 4429 } 4430 4431 mii_pollstat(mii); 4432 ifmr->ifm_status = mii->mii_media_status; 4433 ifmr->ifm_active = (mii->mii_media_active & ~IFM_ETH_FMASK) | 4434 sc->bge_flowflags; 4435 } 4436 4437 static int 4438 bge_ioctl(struct ifnet *ifp, u_long command, void *data) 4439 { 4440 struct bge_softc *sc = ifp->if_softc; 4441 struct ifreq *ifr = (struct ifreq *) data; 4442 int s, error = 0; 4443 struct mii_data *mii; 4444 4445 s = splnet(); 4446 4447 switch (command) { 4448 case SIOCSIFFLAGS: 4449 if ((error = ifioctl_common(ifp, command, data)) != 0) 4450 break; 4451 if (ifp->if_flags & IFF_UP) { 4452 /* 4453 * If only the state of the PROMISC flag changed, 4454 * then just use the 'set promisc mode' command 4455 * instead of reinitializing the entire NIC. Doing 4456 * a full re-init means reloading the firmware and 4457 * waiting for it to start up, which may take a 4458 * second or two. 4459 */ 4460 if (ifp->if_flags & IFF_RUNNING && 4461 ifp->if_flags & IFF_PROMISC && 4462 !(sc->bge_if_flags & IFF_PROMISC)) { 4463 BGE_SETBIT(sc, BGE_RX_MODE, 4464 BGE_RXMODE_RX_PROMISC); 4465 } else if (ifp->if_flags & IFF_RUNNING && 4466 !(ifp->if_flags & IFF_PROMISC) && 4467 sc->bge_if_flags & IFF_PROMISC) { 4468 BGE_CLRBIT(sc, BGE_RX_MODE, 4469 BGE_RXMODE_RX_PROMISC); 4470 } else if (!(sc->bge_if_flags & IFF_UP)) 4471 bge_init(ifp); 4472 } else { 4473 if (ifp->if_flags & IFF_RUNNING) 4474 bge_stop(ifp, 1); 4475 } 4476 sc->bge_if_flags = ifp->if_flags; 4477 error = 0; 4478 break; 4479 case SIOCSIFMEDIA: 4480 /* XXX Flow control is not supported for 1000BASE-SX */ 4481 if (sc->bge_flags & BGE_PHY_FIBER_TBI) { 4482 ifr->ifr_media &= ~IFM_ETH_FMASK; 4483 sc->bge_flowflags = 0; 4484 } 4485 4486 /* Flow control requires full-duplex mode. */ 4487 if (IFM_SUBTYPE(ifr->ifr_media) == IFM_AUTO || 4488 (ifr->ifr_media & IFM_FDX) == 0) { 4489 ifr->ifr_media &= ~IFM_ETH_FMASK; 4490 } 4491 if (IFM_SUBTYPE(ifr->ifr_media) != IFM_AUTO) { 4492 if ((ifr->ifr_media & IFM_ETH_FMASK) == IFM_FLOW) { 4493 /* We can do both TXPAUSE and RXPAUSE. */ 4494 ifr->ifr_media |= 4495 IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE; 4496 } 4497 sc->bge_flowflags = ifr->ifr_media & IFM_ETH_FMASK; 4498 } 4499 /* FALLTHROUGH */ 4500 case SIOCGIFMEDIA: 4501 if (sc->bge_flags & BGE_PHY_FIBER_TBI) { 4502 error = ifmedia_ioctl(ifp, ifr, &sc->bge_ifmedia, 4503 command); 4504 } else { 4505 mii = &sc->bge_mii; 4506 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, 4507 command); 4508 } 4509 break; 4510 default: 4511 if ((error = ether_ioctl(ifp, command, data)) != ENETRESET) 4512 break; 4513 4514 error = 0; 4515 4516 if (command != SIOCADDMULTI && command != SIOCDELMULTI) 4517 ; 4518 else if (ifp->if_flags & IFF_RUNNING) 4519 bge_setmulti(sc); 4520 break; 4521 } 4522 4523 splx(s); 4524 4525 return error; 4526 } 4527 4528 static void 4529 bge_watchdog(struct ifnet *ifp) 4530 { 4531 struct bge_softc *sc; 4532 4533 sc = ifp->if_softc; 4534 4535 aprint_error_dev(sc->bge_dev, "watchdog timeout -- resetting\n"); 4536 4537 ifp->if_flags &= ~IFF_RUNNING; 4538 bge_init(ifp); 4539 4540 ifp->if_oerrors++; 4541 } 4542 4543 static void 4544 bge_stop_block(struct bge_softc *sc, bus_addr_t reg, uint32_t bit) 4545 { 4546 int i; 4547 4548 BGE_CLRBIT(sc, reg, bit); 4549 4550 for (i = 0; i < BGE_TIMEOUT; i++) { 4551 if ((CSR_READ_4(sc, reg) & bit) == 0) 4552 return; 4553 delay(100); 4554 if (sc->bge_flags & BGE_PCIE) 4555 DELAY(1000); 4556 } 4557 4558 /* 4559 * Doesn't print only when the register is BGE_SRS_MODE. It occurs 4560 * on some environment (and once after boot?) 4561 */ 4562 if (reg != BGE_SRS_MODE) 4563 aprint_error_dev(sc->bge_dev, 4564 "block failed to stop: reg 0x%lx, bit 0x%08x\n", 4565 (u_long)reg, bit); 4566 } 4567 4568 /* 4569 * Stop the adapter and free any mbufs allocated to the 4570 * RX and TX lists. 4571 */ 4572 static void 4573 bge_stop(struct ifnet *ifp, int disable) 4574 { 4575 struct bge_softc *sc = ifp->if_softc; 4576 4577 callout_stop(&sc->bge_timeout); 4578 4579 /* 4580 * Tell firmware we're shutting down. 4581 */ 4582 bge_stop_fw(sc); 4583 bge_sig_pre_reset(sc, BGE_RESET_STOP); 4584 4585 /* Disable host interrupts. */ 4586 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); 4587 bge_writembx(sc, BGE_MBX_IRQ0_LO, 1); 4588 4589 /* 4590 * Disable all of the receiver blocks 4591 */ 4592 bge_stop_block(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE); 4593 bge_stop_block(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 4594 bge_stop_block(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 4595 if (BGE_IS_5700_FAMILY(sc)) 4596 bge_stop_block(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 4597 bge_stop_block(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE); 4598 bge_stop_block(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 4599 bge_stop_block(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE); 4600 4601 /* 4602 * Disable all of the transmit blocks 4603 */ 4604 bge_stop_block(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 4605 bge_stop_block(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 4606 bge_stop_block(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 4607 bge_stop_block(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE); 4608 bge_stop_block(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE); 4609 if (BGE_IS_5700_FAMILY(sc)) 4610 bge_stop_block(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 4611 bge_stop_block(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 4612 4613 /* 4614 * Shut down all of the memory managers and related 4615 * state machines. 4616 */ 4617 bge_stop_block(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE); 4618 bge_stop_block(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE); 4619 if (BGE_IS_5700_FAMILY(sc)) 4620 bge_stop_block(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 4621 4622 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 4623 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 4624 4625 if (BGE_IS_5700_FAMILY(sc)) { 4626 bge_stop_block(sc, BGE_BMAN_MODE, BGE_BMANMODE_ENABLE); 4627 bge_stop_block(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 4628 } 4629 4630 bge_reset(sc); 4631 bge_sig_legacy(sc, BGE_RESET_STOP); 4632 bge_sig_post_reset(sc, BGE_RESET_STOP); 4633 4634 /* 4635 * Keep the ASF firmware running if up. 4636 */ 4637 if (sc->bge_asf_mode & ASF_STACKUP) 4638 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 4639 else 4640 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 4641 4642 /* Free the RX lists. */ 4643 bge_free_rx_ring_std(sc); 4644 4645 /* Free jumbo RX list. */ 4646 if (BGE_IS_JUMBO_CAPABLE(sc)) 4647 bge_free_rx_ring_jumbo(sc); 4648 4649 /* Free TX buffers. */ 4650 bge_free_tx_ring(sc); 4651 4652 /* 4653 * Isolate/power down the PHY. 4654 */ 4655 if (!(sc->bge_flags & BGE_PHY_FIBER_TBI)) 4656 mii_down(&sc->bge_mii); 4657 4658 sc->bge_tx_saved_considx = BGE_TXCONS_UNSET; 4659 4660 /* Clear MAC's link state (PHY may still have link UP). */ 4661 BGE_STS_CLRBIT(sc, BGE_STS_LINK); 4662 4663 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 4664 } 4665 4666 static void 4667 bge_link_upd(struct bge_softc *sc) 4668 { 4669 struct ifnet *ifp = &sc->ethercom.ec_if; 4670 struct mii_data *mii = &sc->bge_mii; 4671 uint32_t status; 4672 int link; 4673 4674 /* Clear 'pending link event' flag */ 4675 BGE_STS_CLRBIT(sc, BGE_STS_LINK_EVT); 4676 4677 /* 4678 * Process link state changes. 4679 * Grrr. The link status word in the status block does 4680 * not work correctly on the BCM5700 rev AX and BX chips, 4681 * according to all available information. Hence, we have 4682 * to enable MII interrupts in order to properly obtain 4683 * async link changes. Unfortunately, this also means that 4684 * we have to read the MAC status register to detect link 4685 * changes, thereby adding an additional register access to 4686 * the interrupt handler. 4687 */ 4688 4689 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700) { 4690 status = CSR_READ_4(sc, BGE_MAC_STS); 4691 if (status & BGE_MACSTAT_MI_INTERRUPT) { 4692 mii_pollstat(mii); 4693 4694 if (!BGE_STS_BIT(sc, BGE_STS_LINK) && 4695 mii->mii_media_status & IFM_ACTIVE && 4696 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) 4697 BGE_STS_SETBIT(sc, BGE_STS_LINK); 4698 else if (BGE_STS_BIT(sc, BGE_STS_LINK) && 4699 (!(mii->mii_media_status & IFM_ACTIVE) || 4700 IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) 4701 BGE_STS_CLRBIT(sc, BGE_STS_LINK); 4702 4703 /* Clear the interrupt */ 4704 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, 4705 BGE_EVTENB_MI_INTERRUPT); 4706 bge_miibus_readreg(sc->bge_dev, 1, BRGPHY_MII_ISR); 4707 bge_miibus_writereg(sc->bge_dev, 1, BRGPHY_MII_IMR, 4708 BRGPHY_INTRS); 4709 } 4710 return; 4711 } 4712 4713 if (sc->bge_flags & BGE_PHY_FIBER_TBI) { 4714 status = CSR_READ_4(sc, BGE_MAC_STS); 4715 if (status & BGE_MACSTAT_TBI_PCS_SYNCHED) { 4716 if (!BGE_STS_BIT(sc, BGE_STS_LINK)) { 4717 BGE_STS_SETBIT(sc, BGE_STS_LINK); 4718 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) 4719 BGE_CLRBIT(sc, BGE_MAC_MODE, 4720 BGE_MACMODE_TBI_SEND_CFGS); 4721 CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF); 4722 if_link_state_change(ifp, LINK_STATE_UP); 4723 } 4724 } else if (BGE_STS_BIT(sc, BGE_STS_LINK)) { 4725 BGE_STS_CLRBIT(sc, BGE_STS_LINK); 4726 if_link_state_change(ifp, LINK_STATE_DOWN); 4727 } 4728 /* 4729 * Discard link events for MII/GMII cards if MI auto-polling disabled. 4730 * This should not happen since mii callouts are locked now, but 4731 * we keep this check for debug. 4732 */ 4733 } else if (BGE_STS_BIT(sc, BGE_STS_AUTOPOLL)) { 4734 /* 4735 * Some broken BCM chips have BGE_STATFLAG_LINKSTATE_CHANGED 4736 * bit in status word always set. Workaround this bug by 4737 * reading PHY link status directly. 4738 */ 4739 link = (CSR_READ_4(sc, BGE_MI_STS) & BGE_MISTS_LINK)? 4740 BGE_STS_LINK : 0; 4741 4742 if (BGE_STS_BIT(sc, BGE_STS_LINK) != link) { 4743 mii_pollstat(mii); 4744 4745 if (!BGE_STS_BIT(sc, BGE_STS_LINK) && 4746 mii->mii_media_status & IFM_ACTIVE && 4747 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) 4748 BGE_STS_SETBIT(sc, BGE_STS_LINK); 4749 else if (BGE_STS_BIT(sc, BGE_STS_LINK) && 4750 (!(mii->mii_media_status & IFM_ACTIVE) || 4751 IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) 4752 BGE_STS_CLRBIT(sc, BGE_STS_LINK); 4753 } 4754 } 4755 4756 /* Clear the attention */ 4757 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED| 4758 BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE| 4759 BGE_MACSTAT_LINK_CHANGED); 4760 } 4761 4762 static int 4763 sysctl_bge_verify(SYSCTLFN_ARGS) 4764 { 4765 int error, t; 4766 struct sysctlnode node; 4767 4768 node = *rnode; 4769 t = *(int*)rnode->sysctl_data; 4770 node.sysctl_data = &t; 4771 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 4772 if (error || newp == NULL) 4773 return error; 4774 4775 #if 0 4776 DPRINTF2(("%s: t = %d, nodenum = %d, rnodenum = %d\n", __func__, t, 4777 node.sysctl_num, rnode->sysctl_num)); 4778 #endif 4779 4780 if (node.sysctl_num == bge_rxthresh_nodenum) { 4781 if (t < 0 || t >= NBGE_RX_THRESH) 4782 return EINVAL; 4783 bge_update_all_threshes(t); 4784 } else 4785 return EINVAL; 4786 4787 *(int*)rnode->sysctl_data = t; 4788 4789 return 0; 4790 } 4791 4792 /* 4793 * Set up sysctl(3) MIB, hw.bge.*. 4794 * 4795 * TBD condition SYSCTL_PERMANENT on being an LKM or not 4796 */ 4797 SYSCTL_SETUP(sysctl_bge, "sysctl bge subtree setup") 4798 { 4799 int rc, bge_root_num; 4800 const struct sysctlnode *node; 4801 4802 if ((rc = sysctl_createv(clog, 0, NULL, NULL, 4803 CTLFLAG_PERMANENT, CTLTYPE_NODE, "hw", NULL, 4804 NULL, 0, NULL, 0, CTL_HW, CTL_EOL)) != 0) { 4805 goto err; 4806 } 4807 4808 if ((rc = sysctl_createv(clog, 0, NULL, &node, 4809 CTLFLAG_PERMANENT, CTLTYPE_NODE, "bge", 4810 SYSCTL_DESCR("BGE interface controls"), 4811 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL)) != 0) { 4812 goto err; 4813 } 4814 4815 bge_root_num = node->sysctl_num; 4816 4817 /* BGE Rx interrupt mitigation level */ 4818 if ((rc = sysctl_createv(clog, 0, NULL, &node, 4819 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, 4820 CTLTYPE_INT, "rx_lvl", 4821 SYSCTL_DESCR("BGE receive interrupt mitigation level"), 4822 sysctl_bge_verify, 0, 4823 &bge_rx_thresh_lvl, 4824 0, CTL_HW, bge_root_num, CTL_CREATE, 4825 CTL_EOL)) != 0) { 4826 goto err; 4827 } 4828 4829 bge_rxthresh_nodenum = node->sysctl_num; 4830 4831 return; 4832 4833 err: 4834 aprint_error("%s: sysctl_createv failed (rc = %d)\n", __func__, rc); 4835 } 4836 4837 #ifdef BGE_DEBUG 4838 void 4839 bge_debug_info(struct bge_softc *sc) 4840 { 4841 4842 printf("Hardware Flags:\n"); 4843 if (BGE_IS_5755_PLUS(sc)) 4844 printf(" - 5755 Plus\n"); 4845 if (BGE_IS_5750_OR_BEYOND(sc)) 4846 printf(" - 5750 Plus\n"); 4847 if (BGE_IS_5705_PLUS(sc)) 4848 printf(" - 5705 Plus\n"); 4849 if (BGE_IS_5714_FAMILY(sc)) 4850 printf(" - 5714 Family\n"); 4851 if (BGE_IS_5700_FAMILY(sc)) 4852 printf(" - 5700 Family\n"); 4853 if (sc->bge_flags & BGE_IS_5788) 4854 printf(" - 5788\n"); 4855 if (sc->bge_flags & BGE_JUMBO_CAPABLE) 4856 printf(" - Supports Jumbo Frames\n"); 4857 if (sc->bge_flags & BGE_NO_EEPROM) 4858 printf(" - No EEPROM\n"); 4859 if (sc->bge_flags & BGE_PCIX) 4860 printf(" - PCI-X Bus\n"); 4861 if (sc->bge_flags & BGE_PCIE) 4862 printf(" - PCI Express Bus\n"); 4863 if (sc->bge_flags & BGE_NO_3LED) 4864 printf(" - No 3 LEDs\n"); 4865 if (sc->bge_flags & BGE_RX_ALIGNBUG) 4866 printf(" - RX Alignment Bug\n"); 4867 if (sc->bge_flags & BGE_TSO) 4868 printf(" - TSO\n"); 4869 } 4870 #endif /* BGE_DEBUG */ 4871 4872 static int 4873 bge_get_eaddr_fw(struct bge_softc *sc, uint8_t ether_addr[]) 4874 { 4875 prop_dictionary_t dict; 4876 prop_data_t ea; 4877 4878 if ((sc->bge_flags & BGE_NO_EEPROM) == 0) 4879 return 1; 4880 4881 dict = device_properties(sc->bge_dev); 4882 ea = prop_dictionary_get(dict, "mac-address"); 4883 if (ea != NULL) { 4884 KASSERT(prop_object_type(ea) == PROP_TYPE_DATA); 4885 KASSERT(prop_data_size(ea) == ETHER_ADDR_LEN); 4886 memcpy(ether_addr, prop_data_data_nocopy(ea), ETHER_ADDR_LEN); 4887 return 0; 4888 } 4889 4890 return 1; 4891 } 4892 4893 static int 4894 bge_get_eaddr_mem(struct bge_softc *sc, uint8_t ether_addr[]) 4895 { 4896 uint32_t mac_addr; 4897 4898 mac_addr = bge_readmem_ind(sc, 0x0c14); 4899 if ((mac_addr >> 16) == 0x484b) { 4900 ether_addr[0] = (uint8_t)(mac_addr >> 8); 4901 ether_addr[1] = (uint8_t)mac_addr; 4902 mac_addr = bge_readmem_ind(sc, 0x0c18); 4903 ether_addr[2] = (uint8_t)(mac_addr >> 24); 4904 ether_addr[3] = (uint8_t)(mac_addr >> 16); 4905 ether_addr[4] = (uint8_t)(mac_addr >> 8); 4906 ether_addr[5] = (uint8_t)mac_addr; 4907 return 0; 4908 } 4909 return 1; 4910 } 4911 4912 static int 4913 bge_get_eaddr_nvram(struct bge_softc *sc, uint8_t ether_addr[]) 4914 { 4915 int mac_offset = BGE_EE_MAC_OFFSET; 4916 4917 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 4918 mac_offset = BGE_EE_MAC_OFFSET_5906; 4919 4920 return (bge_read_nvram(sc, ether_addr, mac_offset + 2, 4921 ETHER_ADDR_LEN)); 4922 } 4923 4924 static int 4925 bge_get_eaddr_eeprom(struct bge_softc *sc, uint8_t ether_addr[]) 4926 { 4927 4928 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 4929 return 1; 4930 4931 return (bge_read_eeprom(sc, ether_addr, BGE_EE_MAC_OFFSET + 2, 4932 ETHER_ADDR_LEN)); 4933 } 4934 4935 static int 4936 bge_get_eaddr(struct bge_softc *sc, uint8_t eaddr[]) 4937 { 4938 static const bge_eaddr_fcn_t bge_eaddr_funcs[] = { 4939 /* NOTE: Order is critical */ 4940 bge_get_eaddr_fw, 4941 bge_get_eaddr_mem, 4942 bge_get_eaddr_nvram, 4943 bge_get_eaddr_eeprom, 4944 NULL 4945 }; 4946 const bge_eaddr_fcn_t *func; 4947 4948 for (func = bge_eaddr_funcs; *func != NULL; ++func) { 4949 if ((*func)(sc, eaddr) == 0) 4950 break; 4951 } 4952 return (*func == NULL ? ENXIO : 0); 4953 } 4954
Indexes created Mon Sep 22 13:09:51 GMT 2025