if_bge.c revision 1.2
1 /* $NetBSD: if_bge.c,v 1.2 2002/06/24 01:23:11 fvdl Exp $ */ 2 /* 3 * Copyright (c) 2001 Wind River Systems 4 * Copyright (c) 1997, 1998, 1999, 2001 5 * Bill Paul <wpaul (at) windriver.com>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 * $FreeBSD: if_bge.c,v 1.13 2002/04/04 06:01:31 wpaul Exp $ 35 */ 36 37 /* 38 * Broadcom BCM570x family gigabit ethernet driver for FreeBSD. 39 * 40 * Written by Bill Paul <wpaul (at) windriver.com> 41 * Senior Engineer, Wind River Systems 42 */ 43 44 /* 45 * The Broadcom BCM5700 is based on technology originally developed by 46 * Alteon Networks as part of the Tigon I and Tigon II gigabit ethernet 47 * MAC chips. The BCM5700, sometimes refered to as the Tigon III, has 48 * two on-board MIPS R4000 CPUs and can have as much as 16MB of external 49 * SSRAM. The BCM5700 supports TCP, UDP and IP checksum offload, jumbo 50 * frames, highly configurable RX filtering, and 16 RX and TX queues 51 * (which, along with RX filter rules, can be used for QOS applications). 52 * Other features, such as TCP segmentation, may be available as part 53 * of value-added firmware updates. Unlike the Tigon I and Tigon II, 54 * firmware images can be stored in hardware and need not be compiled 55 * into the driver. 56 * 57 * The BCM5700 supports the PCI v2.2 and PCI-X v1.0 standards, and will 58 * function in a 32-bit/64-bit 33/66Mhz bus, or a 64-bit/133Mhz bus. 59 * 60 * The BCM5701 is a single-chip solution incorporating both the BCM5700 61 * MAC and a BCM5401 10/100/1000 PHY. Unlike the BCM5700, the BCM5700 62 * does not support external SSRAM. 63 * 64 * Broadcom also produces a variation of the BCM5700 under the "Altima" 65 * brand name, which is functionally similar but lacks PCI-X support. 66 * 67 * Without external SSRAM, you can only have at most 4 TX rings, 68 * and the use of the mini RX ring is disabled. This seems to imply 69 * that these features are simply not available on the BCM5701. As a 70 * result, this driver does not implement any support for the mini RX 71 * ring. 72 */ 73 74 #include "bpfilter.h" 75 #include "vlan.h" 76 77 #include <sys/param.h> 78 #include <sys/systm.h> 79 #include <sys/callout.h> 80 #include <sys/sockio.h> 81 #include <sys/mbuf.h> 82 #include <sys/malloc.h> 83 #include <sys/kernel.h> 84 #include <sys/device.h> 85 #include <sys/socket.h> 86 87 #include <net/if.h> 88 #include <net/if_dl.h> 89 #include <net/if_media.h> 90 #include <net/if_ether.h> 91 92 #ifdef INET 93 #include <netinet/in.h> 94 #include <netinet/in_systm.h> 95 #include <netinet/in_var.h> 96 #include <netinet/ip.h> 97 #endif 98 99 #if NBPFILTER > 0 100 #include <net/bpf.h> 101 #endif 102 103 #include <dev/pci/pcireg.h> 104 #include <dev/pci/pcivar.h> 105 #include <dev/pci/pcidevs.h> 106 107 #include <dev/mii/mii.h> 108 #include <dev/mii/miivar.h> 109 #include <dev/mii/miidevs.h> 110 #include <dev/mii/brgphyreg.h> 111 112 #include <dev/pci/if_bgereg.h> 113 114 #include <uvm/uvm_extern.h> 115 116 /* #define BGE_CHECKSUM */ 117 118 int bge_probe(struct device *, struct cfdata *, void *); 119 void bge_attach(struct device *, struct device *, void *); 120 void bge_release_resources(struct bge_softc *); 121 void bge_txeof(struct bge_softc *); 122 void bge_rxeof(struct bge_softc *); 123 124 void bge_tick(void *); 125 void bge_stats_update(struct bge_softc *); 126 int bge_encap(struct bge_softc *, struct mbuf *, u_int32_t *); 127 128 int bge_intr(void *); 129 void bge_start(struct ifnet *); 130 int bge_ioctl(struct ifnet *, u_long, caddr_t); 131 int bge_init(struct ifnet *); 132 void bge_stop(struct bge_softc *); 133 void bge_watchdog(struct ifnet *); 134 void bge_shutdown(void *); 135 int bge_ifmedia_upd(struct ifnet *); 136 void bge_ifmedia_sts(struct ifnet *, struct ifmediareq *); 137 138 u_int8_t bge_eeprom_getbyte(struct bge_softc *, int, u_int8_t *); 139 int bge_read_eeprom(struct bge_softc *, caddr_t, int, int); 140 141 u_int32_t bge_crc(struct bge_softc *, caddr_t); 142 void bge_setmulti(struct bge_softc *); 143 144 void bge_handle_events(struct bge_softc *); 145 int bge_alloc_jumbo_mem(struct bge_softc *); 146 void bge_free_jumbo_mem(struct bge_softc *); 147 void *bge_jalloc(struct bge_softc *); 148 void bge_jfree(struct mbuf *, caddr_t, u_int, void *); 149 int bge_newbuf_std(struct bge_softc *, int, struct mbuf *, bus_dmamap_t); 150 int bge_newbuf_jumbo(struct bge_softc *, int, struct mbuf *); 151 int bge_init_rx_ring_std(struct bge_softc *); 152 void bge_free_rx_ring_std(struct bge_softc *); 153 int bge_init_rx_ring_jumbo(struct bge_softc *); 154 void bge_free_rx_ring_jumbo(struct bge_softc *); 155 void bge_free_tx_ring(struct bge_softc *); 156 int bge_init_tx_ring(struct bge_softc *); 157 158 int bge_chipinit(struct bge_softc *); 159 int bge_blockinit(struct bge_softc *); 160 161 #ifdef notdef 162 u_int8_t bge_vpd_readbyte(struct bge_softc *, int); 163 void bge_vpd_read_res(struct bge_softc *, struct vpd_res *, int); 164 void bge_vpd_read(struct bge_softc *); 165 #endif 166 167 u_int32_t bge_readmem_ind(struct bge_softc *, int); 168 void bge_writemem_ind(struct bge_softc *, int, int); 169 #ifdef notdef 170 u_int32_t bge_readreg_ind(struct bge_softc *, int); 171 #endif 172 void bge_writereg_ind(struct bge_softc *, int, int); 173 174 int bge_miibus_readreg(struct device *, int, int); 175 void bge_miibus_writereg(struct device *, int, int, int); 176 void bge_miibus_statchg(struct device *); 177 178 void bge_reset(struct bge_softc *); 179 void bge_phy_hack(struct bge_softc *); 180 181 void bge_dump_status(struct bge_softc *); 182 void bge_dump_rxbd(struct bge_rx_bd *); 183 184 #define BGE_DEBUG 185 #ifdef BGE_DEBUG 186 #define DPRINTF(x) if (bgedebug) printf x 187 #define DPRINTFN(n,x) if (bgedebug >= (n)) printf x 188 int bgedebug = 0; 189 #else 190 #define DPRINTF(x) 191 #define DPRINTFN(n,x) 192 #endif 193 194 struct cfattach bge_ca = { 195 sizeof(struct bge_softc), bge_probe, bge_attach 196 }; 197 198 u_int32_t 199 bge_readmem_ind(sc, off) 200 struct bge_softc *sc; 201 int off; 202 { 203 struct pci_attach_args *pa = &(sc->bge_pa); 204 pcireg_t val; 205 206 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_MEMWIN_BASEADDR, off); 207 val = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_MEMWIN_DATA); 208 return val; 209 } 210 211 void 212 bge_writemem_ind(sc, off, val) 213 struct bge_softc *sc; 214 int off, val; 215 { 216 struct pci_attach_args *pa = &(sc->bge_pa); 217 218 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_MEMWIN_BASEADDR, off); 219 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_MEMWIN_DATA, val); 220 } 221 222 #ifdef notdef 223 u_int32_t 224 bge_readreg_ind(sc, off) 225 struct bge_softc *sc; 226 int off; 227 { 228 struct pci_attach_args *pa = &(sc->bge_pa); 229 230 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_REG_BASEADDR, off); 231 return(pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_REG_DATA)); 232 } 233 #endif 234 235 void 236 bge_writereg_ind(sc, off, val) 237 struct bge_softc *sc; 238 int off, val; 239 { 240 struct pci_attach_args *pa = &(sc->bge_pa); 241 242 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_REG_BASEADDR, off); 243 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_REG_DATA, val); 244 } 245 246 #ifdef notdef 247 u_int8_t 248 bge_vpd_readbyte(sc, addr) 249 struct bge_softc *sc; 250 int addr; 251 { 252 int i; 253 u_int32_t val; 254 struct pci_attach_args *pa = &(sc->bge_pa); 255 256 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_VPD_ADDR, addr); 257 for (i = 0; i < BGE_TIMEOUT * 10; i++) { 258 DELAY(10); 259 if (pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_VPD_ADDR) & 260 BGE_VPD_FLAG) 261 break; 262 } 263 264 if (i == BGE_TIMEOUT) { 265 printf("%s: VPD read timed out\n", sc->bge_dev.dv_xname); 266 return(0); 267 } 268 269 val = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_VPD_DATA); 270 271 return((val >> ((addr % 4) * 8)) & 0xFF); 272 } 273 274 void 275 bge_vpd_read_res(sc, res, addr) 276 struct bge_softc *sc; 277 struct vpd_res *res; 278 int addr; 279 { 280 int i; 281 u_int8_t *ptr; 282 283 ptr = (u_int8_t *)res; 284 for (i = 0; i < sizeof(struct vpd_res); i++) 285 ptr[i] = bge_vpd_readbyte(sc, i + addr); 286 } 287 288 void 289 bge_vpd_read(sc) 290 struct bge_softc *sc; 291 { 292 int pos = 0, i; 293 struct vpd_res res; 294 295 if (sc->bge_vpd_prodname != NULL) 296 free(sc->bge_vpd_prodname, M_DEVBUF); 297 if (sc->bge_vpd_readonly != NULL) 298 free(sc->bge_vpd_readonly, M_DEVBUF); 299 sc->bge_vpd_prodname = NULL; 300 sc->bge_vpd_readonly = NULL; 301 302 bge_vpd_read_res(sc, &res, pos); 303 304 if (res.vr_id != VPD_RES_ID) { 305 printf("%s: bad VPD resource id: expected %x got %x\n", 306 sc->bge_dev.dv_xname, VPD_RES_ID, res.vr_id); 307 return; 308 } 309 310 pos += sizeof(res); 311 sc->bge_vpd_prodname = malloc(res.vr_len + 1, M_DEVBUF, M_NOWAIT); 312 if (sc->bge_vpd_prodname == NULL) 313 panic("bge_vpd_read"); 314 for (i = 0; i < res.vr_len; i++) 315 sc->bge_vpd_prodname[i] = bge_vpd_readbyte(sc, i + pos); 316 sc->bge_vpd_prodname[i] = '\0'; 317 pos += i; 318 319 bge_vpd_read_res(sc, &res, pos); 320 321 if (res.vr_id != VPD_RES_READ) { 322 printf("%s: bad VPD resource id: expected %x got %x\n", 323 sc->bge_dev.dv_xname, VPD_RES_READ, res.vr_id); 324 return; 325 } 326 327 pos += sizeof(res); 328 sc->bge_vpd_readonly = malloc(res.vr_len, M_DEVBUF, M_NOWAIT); 329 if (sc->bge_vpd_readonly == NULL) 330 panic("bge_vpd_read"); 331 for (i = 0; i < res.vr_len + 1; i++) 332 sc->bge_vpd_readonly[i] = bge_vpd_readbyte(sc, i + pos); 333 } 334 #endif 335 336 /* 337 * Read a byte of data stored in the EEPROM at address 'addr.' The 338 * BCM570x supports both the traditional bitbang interface and an 339 * auto access interface for reading the EEPROM. We use the auto 340 * access method. 341 */ 342 u_int8_t 343 bge_eeprom_getbyte(sc, addr, dest) 344 struct bge_softc *sc; 345 int addr; 346 u_int8_t *dest; 347 { 348 int i; 349 u_int32_t byte = 0; 350 351 /* 352 * Enable use of auto EEPROM access so we can avoid 353 * having to use the bitbang method. 354 */ 355 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM); 356 357 /* Reset the EEPROM, load the clock period. */ 358 CSR_WRITE_4(sc, BGE_EE_ADDR, 359 BGE_EEADDR_RESET|BGE_EEHALFCLK(BGE_HALFCLK_384SCL)); 360 DELAY(20); 361 362 /* Issue the read EEPROM command. */ 363 CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr); 364 365 /* Wait for completion */ 366 for(i = 0; i < BGE_TIMEOUT * 10; i++) { 367 DELAY(10); 368 if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE) 369 break; 370 } 371 372 if (i == BGE_TIMEOUT) { 373 printf("%s: eeprom read timed out\n", sc->bge_dev.dv_xname); 374 return(0); 375 } 376 377 /* Get result. */ 378 byte = CSR_READ_4(sc, BGE_EE_DATA); 379 380 *dest = (byte >> ((addr % 4) * 8)) & 0xFF; 381 382 return(0); 383 } 384 385 /* 386 * Read a sequence of bytes from the EEPROM. 387 */ 388 int 389 bge_read_eeprom(sc, dest, off, cnt) 390 struct bge_softc *sc; 391 caddr_t dest; 392 int off; 393 int cnt; 394 { 395 int err = 0, i; 396 u_int8_t byte = 0; 397 398 for (i = 0; i < cnt; i++) { 399 err = bge_eeprom_getbyte(sc, off + i, &byte); 400 if (err) 401 break; 402 *(dest + i) = byte; 403 } 404 405 return(err ? 1 : 0); 406 } 407 408 int 409 bge_miibus_readreg(dev, phy, reg) 410 struct device *dev; 411 int phy, reg; 412 { 413 struct bge_softc *sc = (struct bge_softc *)dev; 414 struct ifnet *ifp; 415 u_int32_t val; 416 int i; 417 418 ifp = &sc->ethercom.ec_if; 419 420 if (sc->bge_asicrev == BGE_ASICREV_BCM5701_B5 && phy != 1) 421 return(0); 422 423 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_READ|BGE_MICOMM_BUSY| 424 BGE_MIPHY(phy)|BGE_MIREG(reg)); 425 426 for (i = 0; i < BGE_TIMEOUT; i++) { 427 val = CSR_READ_4(sc, BGE_MI_COMM); 428 if (!(val & BGE_MICOMM_BUSY)) 429 break; 430 } 431 432 if (i == BGE_TIMEOUT) { 433 printf("%s: PHY read timed out\n", sc->bge_dev.dv_xname); 434 return(0); 435 } 436 437 val = CSR_READ_4(sc, BGE_MI_COMM); 438 439 if (val & BGE_MICOMM_READFAIL) 440 return(0); 441 442 return(val & 0xFFFF); 443 } 444 445 void 446 bge_miibus_writereg(dev, phy, reg, val) 447 struct device *dev; 448 int phy, reg, val; 449 { 450 struct bge_softc *sc = (struct bge_softc *)dev; 451 int i; 452 453 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_WRITE|BGE_MICOMM_BUSY| 454 BGE_MIPHY(phy)|BGE_MIREG(reg)|val); 455 456 for (i = 0; i < BGE_TIMEOUT; i++) { 457 if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY)) 458 break; 459 } 460 461 if (i == BGE_TIMEOUT) { 462 printf("%s: PHY read timed out\n", sc->bge_dev.dv_xname); 463 } 464 } 465 466 void 467 bge_miibus_statchg(dev) 468 struct device *dev; 469 { 470 struct bge_softc *sc = (struct bge_softc *)dev; 471 struct mii_data *mii = &sc->bge_mii; 472 473 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_PORTMODE); 474 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) { 475 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_GMII); 476 } else { 477 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_MII); 478 } 479 480 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 481 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX); 482 } else { 483 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX); 484 } 485 486 bge_phy_hack(sc); 487 } 488 489 /* 490 * Handle events that have triggered interrupts. 491 */ 492 void 493 bge_handle_events(sc) 494 struct bge_softc *sc; 495 { 496 497 return; 498 } 499 500 /* 501 * Memory management for jumbo frames. 502 */ 503 504 int 505 bge_alloc_jumbo_mem(sc) 506 struct bge_softc *sc; 507 { 508 caddr_t ptr, kva; 509 bus_dma_segment_t seg; 510 int i, rseg, state, error; 511 struct bge_jpool_entry *entry; 512 513 state = error = 0; 514 515 /* Grab a big chunk o' storage. */ 516 if (bus_dmamem_alloc(sc->bge_dmatag, BGE_JMEM, PAGE_SIZE, 0, 517 &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 518 printf("%s: can't alloc rx buffers\n", sc->bge_dev.dv_xname); 519 return ENOBUFS; 520 } 521 522 state = 1; 523 if (bus_dmamem_map(sc->bge_dmatag, &seg, rseg, BGE_JMEM, &kva, 524 BUS_DMA_NOWAIT)) { 525 printf("%s: can't map dma buffers (%d bytes)\n", 526 sc->bge_dev.dv_xname, (int)BGE_JMEM); 527 error = ENOBUFS; 528 goto out; 529 } 530 531 state = 2; 532 if (bus_dmamap_create(sc->bge_dmatag, BGE_JMEM, 1, BGE_JMEM, 0, 533 BUS_DMA_NOWAIT, &sc->bge_cdata.bge_rx_jumbo_map)) { 534 printf("%s: can't create dma map\n", sc->bge_dev.dv_xname); 535 error = ENOBUFS; 536 goto out; 537 } 538 539 state = 3; 540 if (bus_dmamap_load(sc->bge_dmatag, sc->bge_cdata.bge_rx_jumbo_map, 541 kva, BGE_JMEM, NULL, BUS_DMA_NOWAIT)) { 542 printf("%s: can't load dma map\n", sc->bge_dev.dv_xname); 543 error = ENOBUFS; 544 goto out; 545 } 546 547 state = 4; 548 sc->bge_cdata.bge_jumbo_buf = (caddr_t)kva; 549 DPRINTFN(1,("bge_jumbo_buf = 0x%p\n", sc->bge_cdata.bge_jumbo_buf)); 550 551 SLIST_INIT(&sc->bge_jfree_listhead); 552 SLIST_INIT(&sc->bge_jinuse_listhead); 553 554 /* 555 * Now divide it up into 9K pieces and save the addresses 556 * in an array. 557 */ 558 ptr = sc->bge_cdata.bge_jumbo_buf; 559 for (i = 0; i < BGE_JSLOTS; i++) { 560 sc->bge_cdata.bge_jslots[i] = ptr; 561 ptr += BGE_JLEN; 562 entry = malloc(sizeof(struct bge_jpool_entry), 563 M_DEVBUF, M_NOWAIT); 564 if (entry == NULL) { 565 printf("%s: no memory for jumbo buffer queue!\n", 566 sc->bge_dev.dv_xname); 567 error = ENOBUFS; 568 goto out; 569 } 570 entry->slot = i; 571 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, 572 entry, jpool_entries); 573 } 574 out: 575 if (error != 0) { 576 switch (state) { 577 case 4: 578 bus_dmamap_unload(sc->bge_dmatag, 579 sc->bge_cdata.bge_rx_jumbo_map); 580 case 3: 581 bus_dmamap_destroy(sc->bge_dmatag, 582 sc->bge_cdata.bge_rx_jumbo_map); 583 case 2: 584 bus_dmamem_unmap(sc->bge_dmatag, kva, BGE_JMEM); 585 case 1: 586 bus_dmamem_free(sc->bge_dmatag, &seg, rseg); 587 break; 588 default: 589 break; 590 } 591 } 592 593 return error; 594 } 595 596 /* 597 * Allocate a jumbo buffer. 598 */ 599 void * 600 bge_jalloc(sc) 601 struct bge_softc *sc; 602 { 603 struct bge_jpool_entry *entry; 604 605 entry = SLIST_FIRST(&sc->bge_jfree_listhead); 606 607 if (entry == NULL) { 608 printf("%s: no free jumbo buffers\n", sc->bge_dev.dv_xname); 609 return(NULL); 610 } 611 612 SLIST_REMOVE_HEAD(&sc->bge_jfree_listhead, jpool_entries); 613 SLIST_INSERT_HEAD(&sc->bge_jinuse_listhead, entry, jpool_entries); 614 return(sc->bge_cdata.bge_jslots[entry->slot]); 615 } 616 617 /* 618 * Release a jumbo buffer. 619 */ 620 void 621 bge_jfree(m, buf, size, arg) 622 struct mbuf *m; 623 caddr_t buf; 624 u_int size; 625 void *arg; 626 { 627 struct bge_jpool_entry *entry; 628 struct bge_softc *sc; 629 int i, s; 630 631 /* Extract the softc struct pointer. */ 632 sc = (struct bge_softc *)arg; 633 634 if (sc == NULL) 635 panic("bge_jfree: can't find softc pointer!"); 636 637 /* calculate the slot this buffer belongs to */ 638 639 i = ((caddr_t)buf 640 - (caddr_t)sc->bge_cdata.bge_jumbo_buf) / BGE_JLEN; 641 642 if ((i < 0) || (i >= BGE_JSLOTS)) 643 panic("bge_jfree: asked to free buffer that we don't manage!"); 644 645 s = splvm(); 646 entry = SLIST_FIRST(&sc->bge_jinuse_listhead); 647 if (entry == NULL) 648 panic("bge_jfree: buffer not in use!"); 649 entry->slot = i; 650 SLIST_REMOVE_HEAD(&sc->bge_jinuse_listhead, jpool_entries); 651 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, entry, jpool_entries); 652 653 if (__predict_true(m != NULL)) 654 pool_cache_put(&mbpool_cache, m); 655 splx(s); 656 } 657 658 659 /* 660 * Intialize a standard receive ring descriptor. 661 */ 662 int 663 bge_newbuf_std(sc, i, m, dmamap) 664 struct bge_softc *sc; 665 int i; 666 struct mbuf *m; 667 bus_dmamap_t dmamap; 668 { 669 struct mbuf *m_new = NULL; 670 struct bge_rx_bd *r; 671 int error; 672 673 if (dmamap == NULL) { 674 error = bus_dmamap_create(sc->bge_dmatag, MCLBYTES, 1, 675 MCLBYTES, 0, BUS_DMA_NOWAIT, &dmamap); 676 if (error != 0) 677 return error; 678 } 679 680 sc->bge_cdata.bge_rx_std_map[i] = dmamap; 681 682 if (m == NULL) { 683 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 684 if (m_new == NULL) { 685 return(ENOBUFS); 686 } 687 688 MCLGET(m_new, M_DONTWAIT); 689 if (!(m_new->m_flags & M_EXT)) { 690 m_freem(m_new); 691 return(ENOBUFS); 692 } 693 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 694 695 if (bus_dmamap_load_mbuf(sc->bge_dmatag, dmamap, m_new, 696 BUS_DMA_READ|BUS_DMA_NOWAIT)) 697 return(ENOBUFS); 698 } else { 699 m_new = m; 700 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 701 m_new->m_data = m_new->m_ext.ext_buf; 702 } 703 704 m_adj(m_new, ETHER_ALIGN); 705 sc->bge_cdata.bge_rx_std_chain[i] = m_new; 706 r = &sc->bge_rdata->bge_rx_std_ring[i]; 707 bge_set_hostaddr(&r->bge_addr, 708 dmamap->dm_segs[0].ds_addr + ETHER_ALIGN); 709 r->bge_flags = BGE_RXBDFLAG_END; 710 r->bge_len = m_new->m_len; 711 r->bge_idx = i; 712 713 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 714 offsetof(struct bge_ring_data, bge_rx_std_ring) + 715 i * sizeof (struct bge_rx_bd), 716 sizeof (struct bge_rx_bd), 717 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 718 719 return(0); 720 } 721 722 /* 723 * Initialize a jumbo receive ring descriptor. This allocates 724 * a jumbo buffer from the pool managed internally by the driver. 725 */ 726 int 727 bge_newbuf_jumbo(sc, i, m) 728 struct bge_softc *sc; 729 int i; 730 struct mbuf *m; 731 { 732 struct mbuf *m_new = NULL; 733 struct bge_rx_bd *r; 734 735 if (m == NULL) { 736 caddr_t *buf = NULL; 737 738 /* Allocate the mbuf. */ 739 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 740 if (m_new == NULL) { 741 return(ENOBUFS); 742 } 743 744 /* Allocate the jumbo buffer */ 745 buf = bge_jalloc(sc); 746 if (buf == NULL) { 747 m_freem(m_new); 748 printf("%s: jumbo allocation failed " 749 "-- packet dropped!\n", sc->bge_dev.dv_xname); 750 return(ENOBUFS); 751 } 752 753 /* Attach the buffer to the mbuf. */ 754 m_new->m_len = m_new->m_pkthdr.len = BGE_JUMBO_FRAMELEN; 755 MEXTADD(m_new, buf, BGE_JUMBO_FRAMELEN, M_DEVBUF, 756 bge_jfree, sc); 757 } else { 758 m_new = m; 759 m_new->m_data = m_new->m_ext.ext_buf; 760 m_new->m_ext.ext_size = BGE_JUMBO_FRAMELEN; 761 } 762 763 m_adj(m_new, ETHER_ALIGN); 764 /* Set up the descriptor. */ 765 r = &sc->bge_rdata->bge_rx_jumbo_ring[i]; 766 sc->bge_cdata.bge_rx_jumbo_chain[i] = m_new; 767 bge_set_hostaddr(&r->bge_addr, BGE_JUMBO_DMA_ADDR(sc, m_new)); 768 r->bge_flags = BGE_RXBDFLAG_END|BGE_RXBDFLAG_JUMBO_RING; 769 r->bge_len = m_new->m_len; 770 r->bge_idx = i; 771 772 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 773 offsetof(struct bge_ring_data, bge_rx_jumbo_ring) + 774 i * sizeof (struct bge_rx_bd), 775 sizeof (struct bge_rx_bd), 776 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 777 778 return(0); 779 } 780 781 /* 782 * The standard receive ring has 512 entries in it. At 2K per mbuf cluster, 783 * that's 1MB or memory, which is a lot. For now, we fill only the first 784 * 256 ring entries and hope that our CPU is fast enough to keep up with 785 * the NIC. 786 */ 787 int 788 bge_init_rx_ring_std(sc) 789 struct bge_softc *sc; 790 { 791 int i; 792 793 if (sc->bge_flags & BGE_RXRING_VALID) 794 return 0; 795 796 for (i = 0; i < BGE_SSLOTS; i++) { 797 if (bge_newbuf_std(sc, i, NULL, 0) == ENOBUFS) 798 return(ENOBUFS); 799 } 800 801 sc->bge_std = i - 1; 802 CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std); 803 804 sc->bge_flags |= BGE_RXRING_VALID; 805 806 return(0); 807 } 808 809 void 810 bge_free_rx_ring_std(sc) 811 struct bge_softc *sc; 812 { 813 int i; 814 815 if (!(sc->bge_flags & BGE_RXRING_VALID)) 816 return; 817 818 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { 819 if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) { 820 m_freem(sc->bge_cdata.bge_rx_std_chain[i]); 821 sc->bge_cdata.bge_rx_std_chain[i] = NULL; 822 bus_dmamap_destroy(sc->bge_dmatag, 823 sc->bge_cdata.bge_rx_std_map[i]); 824 } 825 memset((char *)&sc->bge_rdata->bge_rx_std_ring[i], 0, 826 sizeof(struct bge_rx_bd)); 827 } 828 829 sc->bge_flags &= ~BGE_RXRING_VALID; 830 } 831 832 int 833 bge_init_rx_ring_jumbo(sc) 834 struct bge_softc *sc; 835 { 836 int i; 837 struct bge_rcb *rcb; 838 struct bge_rcb_opaque *rcbo; 839 840 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 841 if (bge_newbuf_jumbo(sc, i, NULL) == ENOBUFS) 842 return(ENOBUFS); 843 }; 844 845 sc->bge_jumbo = i - 1; 846 847 rcb = &sc->bge_rdata->bge_info.bge_jumbo_rx_rcb; 848 rcbo = (struct bge_rcb_opaque *)rcb; 849 rcb->bge_flags = 0; 850 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcbo->bge_reg2); 851 852 CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo); 853 854 return(0); 855 } 856 857 void 858 bge_free_rx_ring_jumbo(sc) 859 struct bge_softc *sc; 860 { 861 int i; 862 863 if (!(sc->bge_flags & BGE_JUMBO_RXRING_VALID)) 864 return; 865 866 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 867 if (sc->bge_cdata.bge_rx_jumbo_chain[i] != NULL) { 868 m_freem(sc->bge_cdata.bge_rx_jumbo_chain[i]); 869 sc->bge_cdata.bge_rx_jumbo_chain[i] = NULL; 870 } 871 memset((char *)&sc->bge_rdata->bge_rx_jumbo_ring[i], 0, 872 sizeof(struct bge_rx_bd)); 873 } 874 875 sc->bge_flags &= ~BGE_JUMBO_RXRING_VALID; 876 } 877 878 void 879 bge_free_tx_ring(sc) 880 struct bge_softc *sc; 881 { 882 int i, freed; 883 struct txdmamap_pool_entry *dma; 884 885 if (!(sc->bge_flags & BGE_TXRING_VALID)) 886 return; 887 888 freed = 0; 889 890 for (i = 0; i < BGE_TX_RING_CNT; i++) { 891 if (sc->bge_cdata.bge_tx_chain[i] != NULL) { 892 freed++; 893 m_freem(sc->bge_cdata.bge_tx_chain[i]); 894 sc->bge_cdata.bge_tx_chain[i] = NULL; 895 SLIST_INSERT_HEAD(&sc->txdma_list, sc->txdma[i], 896 link); 897 sc->txdma[i] = 0; 898 } 899 memset((char *)&sc->bge_rdata->bge_tx_ring[i], 0, 900 sizeof(struct bge_tx_bd)); 901 } 902 903 while ((dma = SLIST_FIRST(&sc->txdma_list))) { 904 SLIST_REMOVE_HEAD(&sc->txdma_list, link); 905 bus_dmamap_destroy(sc->bge_dmatag, dma->dmamap); 906 free(dma, M_DEVBUF); 907 } 908 909 sc->bge_flags &= ~BGE_TXRING_VALID; 910 } 911 912 int 913 bge_init_tx_ring(sc) 914 struct bge_softc *sc; 915 { 916 int i; 917 bus_dmamap_t dmamap; 918 struct txdmamap_pool_entry *dma; 919 920 if (sc->bge_flags & BGE_TXRING_VALID) 921 return 0; 922 923 sc->bge_txcnt = 0; 924 sc->bge_tx_saved_considx = 0; 925 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, 0); 926 CSR_WRITE_4(sc, BGE_MBX_TX_NIC_PROD0_LO, 0); 927 928 SLIST_INIT(&sc->txdma_list); 929 for (i = 0; i < BGE_RSLOTS; i++) { 930 if (bus_dmamap_create(sc->bge_dmatag, ETHER_MAX_LEN_JUMBO, 931 BGE_NTXSEG, ETHER_MAX_LEN_JUMBO, 0, BUS_DMA_NOWAIT, 932 &dmamap)) 933 return(ENOBUFS); 934 if (dmamap == NULL) 935 panic("dmamap NULL in bge_init_tx_ring"); 936 dma = malloc(sizeof(*dma), M_DEVBUF, M_NOWAIT); 937 if (dma == NULL) { 938 printf("%s: can't alloc txdmamap_pool_entry\n", 939 sc->bge_dev.dv_xname); 940 bus_dmamap_destroy(sc->bge_dmatag, dmamap); 941 return (ENOMEM); 942 } 943 dma->dmamap = dmamap; 944 SLIST_INSERT_HEAD(&sc->txdma_list, dma, link); 945 } 946 947 sc->bge_flags |= BGE_TXRING_VALID; 948 949 return(0); 950 } 951 952 #define BGE_POLY 0xEDB88320 953 954 u_int32_t 955 bge_crc(sc, addr) 956 struct bge_softc *sc; 957 caddr_t addr; 958 { 959 u_int32_t idx, bit, data, crc; 960 961 /* Compute CRC for the address value. */ 962 crc = 0xFFFFFFFF; /* initial value */ 963 964 for (idx = 0; idx < 6; idx++) { 965 for (data = *addr++, bit = 0; bit < 8; bit++, data >>= 1) 966 crc = (crc >> 1) ^ (((crc ^ data) & 1) ? BGE_POLY : 0); 967 } 968 969 return(crc & 0x7F); 970 } 971 972 void 973 bge_setmulti(sc) 974 struct bge_softc *sc; 975 { 976 struct ethercom *ac = &sc->ethercom; 977 struct ifnet *ifp = &ac->ec_if; 978 struct ether_multi *enm; 979 struct ether_multistep step; 980 u_int32_t hashes[4] = { 0, 0, 0, 0 }; 981 u_int32_t h; 982 int i; 983 984 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 985 for (i = 0; i < 4; i++) 986 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0xFFFFFFFF); 987 return; 988 } 989 990 /* First, zot all the existing filters. */ 991 for (i = 0; i < 4; i++) 992 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0); 993 994 /* Now program new ones. */ 995 ETHER_FIRST_MULTI(step, ac, enm); 996 while (enm != NULL) { 997 h = bge_crc(sc, LLADDR((struct sockaddr_dl *)enm->enm_addrlo)); 998 hashes[(h & 0x60) >> 5] |= 1 << (h & 0x1F); 999 ETHER_NEXT_MULTI(step, enm); 1000 } 1001 1002 for (i = 0; i < 4; i++) 1003 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]); 1004 } 1005 1006 int bge_swapbits[] = { 1007 0, 1008 BGE_MODECTL_BYTESWAP_DATA, 1009 BGE_MODECTL_WORDSWAP_DATA, 1010 BGE_MODECTL_BYTESWAP_NONFRAME, 1011 BGE_MODECTL_WORDSWAP_NONFRAME, 1012 1013 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA, 1014 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_BYTESWAP_NONFRAME, 1015 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_NONFRAME, 1016 1017 BGE_MODECTL_WORDSWAP_DATA|BGE_MODECTL_BYTESWAP_NONFRAME, 1018 BGE_MODECTL_WORDSWAP_DATA|BGE_MODECTL_WORDSWAP_NONFRAME, 1019 1020 BGE_MODECTL_BYTESWAP_NONFRAME|BGE_MODECTL_WORDSWAP_NONFRAME, 1021 1022 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA| 1023 BGE_MODECTL_BYTESWAP_NONFRAME, 1024 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA| 1025 BGE_MODECTL_WORDSWAP_NONFRAME, 1026 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_BYTESWAP_NONFRAME| 1027 BGE_MODECTL_WORDSWAP_NONFRAME, 1028 BGE_MODECTL_WORDSWAP_DATA|BGE_MODECTL_BYTESWAP_NONFRAME| 1029 BGE_MODECTL_WORDSWAP_NONFRAME, 1030 1031 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA| 1032 BGE_MODECTL_BYTESWAP_NONFRAME|BGE_MODECTL_WORDSWAP_NONFRAME, 1033 }; 1034 1035 int bge_swapindex = 0; 1036 1037 /* 1038 * Do endian, PCI and DMA initialization. Also check the on-board ROM 1039 * self-test results. 1040 */ 1041 int 1042 bge_chipinit(sc) 1043 struct bge_softc *sc; 1044 { 1045 u_int32_t cachesize; 1046 int i; 1047 struct pci_attach_args *pa = &(sc->bge_pa); 1048 1049 1050 /* Set endianness before we access any non-PCI registers. */ 1051 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_MISC_CTL, 1052 BGE_INIT); 1053 1054 /* 1055 * Check the 'ROM failed' bit on the RX CPU to see if 1056 * self-tests passed. 1057 */ 1058 if (CSR_READ_4(sc, BGE_RXCPU_MODE) & BGE_RXCPUMODE_ROMFAIL) { 1059 printf("%s: RX CPU self-diagnostics failed!\n", 1060 sc->bge_dev.dv_xname); 1061 return(ENODEV); 1062 } 1063 1064 /* Clear the MAC control register */ 1065 CSR_WRITE_4(sc, BGE_MAC_MODE, 0); 1066 1067 /* 1068 * Clear the MAC statistics block in the NIC's 1069 * internal memory. 1070 */ 1071 for (i = BGE_STATS_BLOCK; 1072 i < BGE_STATS_BLOCK_END + 1; i += sizeof(u_int32_t)) 1073 BGE_MEMWIN_WRITE(pa->pa_pc, pa->pa_tag, i, 0); 1074 1075 for (i = BGE_STATUS_BLOCK; 1076 i < BGE_STATUS_BLOCK_END + 1; i += sizeof(u_int32_t)) 1077 BGE_MEMWIN_WRITE(pa->pa_pc, pa->pa_tag, i, 0); 1078 1079 /* Set up the PCI DMA control register. */ 1080 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_DMA_RW_CTL, 1081 BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD|0x0F); 1082 1083 /* 1084 * Set up general mode register. 1085 */ 1086 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS| 1087 BGE_MODECTL_MAC_ATTN_INTR|BGE_MODECTL_HOST_SEND_BDS| 1088 BGE_MODECTL_NO_RX_CRC|BGE_MODECTL_TX_NO_PHDR_CSUM| 1089 BGE_MODECTL_RX_NO_PHDR_CSUM); 1090 1091 /* Get cache line size. */ 1092 cachesize = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_CACHESZ); 1093 1094 /* 1095 * Avoid violating PCI spec on certain chip revs. 1096 */ 1097 if (pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_CMD) & 1098 PCIM_CMD_MWIEN) { 1099 switch(cachesize) { 1100 case 1: 1101 PCI_SETBIT(pa->pa_pc, pa->pa_tag, BGE_PCI_DMA_RW_CTL, 1102 BGE_PCI_WRITE_BNDRY_16BYTES); 1103 break; 1104 case 2: 1105 PCI_SETBIT(pa->pa_pc, pa->pa_tag, BGE_PCI_DMA_RW_CTL, 1106 BGE_PCI_WRITE_BNDRY_32BYTES); 1107 break; 1108 case 4: 1109 PCI_SETBIT(pa->pa_pc, pa->pa_tag, BGE_PCI_DMA_RW_CTL, 1110 BGE_PCI_WRITE_BNDRY_64BYTES); 1111 break; 1112 case 8: 1113 PCI_SETBIT(pa->pa_pc, pa->pa_tag, BGE_PCI_DMA_RW_CTL, 1114 BGE_PCI_WRITE_BNDRY_128BYTES); 1115 break; 1116 case 16: 1117 PCI_SETBIT(pa->pa_pc, pa->pa_tag, BGE_PCI_DMA_RW_CTL, 1118 BGE_PCI_WRITE_BNDRY_256BYTES); 1119 break; 1120 case 32: 1121 PCI_SETBIT(pa->pa_pc, pa->pa_tag, BGE_PCI_DMA_RW_CTL, 1122 BGE_PCI_WRITE_BNDRY_512BYTES); 1123 break; 1124 case 64: 1125 PCI_SETBIT(pa->pa_pc, pa->pa_tag, BGE_PCI_DMA_RW_CTL, 1126 BGE_PCI_WRITE_BNDRY_1024BYTES); 1127 break; 1128 default: 1129 /* Disable PCI memory write and invalidate. */ 1130 #if 0 1131 if (bootverbose) 1132 printf("%s: cache line size %d not " 1133 "supported; disabling PCI MWI\n", 1134 sc->bge_dev.dv_xname, cachesize); 1135 #endif 1136 PCI_CLRBIT(pa->pa_pc, pa->pa_tag, BGE_PCI_CMD, 1137 PCIM_CMD_MWIEN); 1138 break; 1139 } 1140 } 1141 1142 #ifdef __brokenalpha__ 1143 /* 1144 * Must insure that we do not cross an 8K (bytes) boundary 1145 * for DMA reads. Our highest limit is 1K bytes. This is a 1146 * restriction on some ALPHA platforms with early revision 1147 * 21174 PCI chipsets, such as the AlphaPC 164lx 1148 */ 1149 PCI_SETBIT(sc, BGE_PCI_DMA_RW_CTL, BGE_PCI_READ_BNDRY_1024, 4); 1150 #endif 1151 1152 /* Set the timer prescaler (always 66Mhz) */ 1153 CSR_WRITE_4(sc, BGE_MISC_CFG, 65 << 1/*BGE_32BITTIME_66MHZ*/); 1154 1155 return(0); 1156 } 1157 1158 int 1159 bge_blockinit(sc) 1160 struct bge_softc *sc; 1161 { 1162 struct bge_rcb *rcb; 1163 struct bge_rcb_opaque *rcbo; 1164 bus_size_t rcb_addr; 1165 int i; 1166 struct ifnet *ifp = &sc->ethercom.ec_if; 1167 bge_hostaddr taddr; 1168 1169 /* 1170 * Initialize the memory window pointer register so that 1171 * we can access the first 32K of internal NIC RAM. This will 1172 * allow us to set up the TX send ring RCBs and the RX return 1173 * ring RCBs, plus other things which live in NIC memory. 1174 */ 1175 1176 pci_conf_write(sc->bge_pa.pa_pc, sc->bge_pa.pa_tag, 1177 BGE_PCI_MEMWIN_BASEADDR, 0); 1178 1179 /* Configure mbuf memory pool */ 1180 if (sc->bge_extram) { 1181 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, BGE_EXT_SSRAM); 1182 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000); 1183 } else { 1184 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, BGE_BUFFPOOL_1); 1185 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000); 1186 } 1187 1188 /* Configure DMA resource pool */ 1189 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_BASEADDR, BGE_DMA_DESCRIPTORS); 1190 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LEN, 0x2000); 1191 1192 /* Configure mbuf pool watermarks */ 1193 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 24); 1194 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 24); 1195 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 48); 1196 1197 /* Configure DMA resource watermarks */ 1198 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5); 1199 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10); 1200 1201 /* Enable buffer manager */ 1202 CSR_WRITE_4(sc, BGE_BMAN_MODE, 1203 BGE_BMANMODE_ENABLE|BGE_BMANMODE_LOMBUF_ATTN); 1204 1205 /* Poll for buffer manager start indication */ 1206 for (i = 0; i < BGE_TIMEOUT; i++) { 1207 if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE) 1208 break; 1209 DELAY(10); 1210 } 1211 1212 if (i == BGE_TIMEOUT) { 1213 printf("%s: buffer manager failed to start\n", 1214 sc->bge_dev.dv_xname); 1215 return(ENXIO); 1216 } 1217 1218 /* Enable flow-through queues */ 1219 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 1220 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 1221 1222 /* Wait until queue initialization is complete */ 1223 for (i = 0; i < BGE_TIMEOUT; i++) { 1224 if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0) 1225 break; 1226 DELAY(10); 1227 } 1228 1229 if (i == BGE_TIMEOUT) { 1230 printf("%s: flow-through queue init failed\n", 1231 sc->bge_dev.dv_xname); 1232 return(ENXIO); 1233 } 1234 1235 /* Initialize the standard RX ring control block */ 1236 rcb = &sc->bge_rdata->bge_info.bge_std_rx_rcb; 1237 bge_set_hostaddr(&rcb->bge_hostaddr, 1238 BGE_RING_DMA_ADDR(sc, bge_rx_std_ring)); 1239 rcb->bge_max_len = BGE_MAX_FRAMELEN; 1240 if (sc->bge_extram) 1241 rcb->bge_nicaddr = BGE_EXT_STD_RX_RINGS; 1242 else 1243 rcb->bge_nicaddr = BGE_STD_RX_RINGS; 1244 rcb->bge_flags = 0; 1245 rcbo = (struct bge_rcb_opaque *)rcb; 1246 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcbo->bge_reg0); 1247 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcbo->bge_reg1); 1248 CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcbo->bge_reg2); 1249 CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcbo->bge_reg3); 1250 1251 /* 1252 * Initialize the jumbo RX ring control block 1253 * We set the 'ring disabled' bit in the flags 1254 * field until we're actually ready to start 1255 * using this ring (i.e. once we set the MTU 1256 * high enough to require it). 1257 */ 1258 rcb = &sc->bge_rdata->bge_info.bge_jumbo_rx_rcb; 1259 bge_set_hostaddr(&rcb->bge_hostaddr, 1260 BGE_RING_DMA_ADDR(sc, bge_rx_jumbo_ring)); 1261 rcb->bge_max_len = BGE_MAX_FRAMELEN; 1262 if (sc->bge_extram) 1263 rcb->bge_nicaddr = BGE_EXT_JUMBO_RX_RINGS; 1264 else 1265 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS; 1266 rcb->bge_flags = BGE_RCB_FLAG_RING_DISABLED; 1267 1268 rcbo = (struct bge_rcb_opaque *)rcb; 1269 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI, rcbo->bge_reg0); 1270 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO, rcbo->bge_reg1); 1271 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcbo->bge_reg2); 1272 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcbo->bge_reg3); 1273 1274 /* Set up dummy disabled mini ring RCB */ 1275 rcb = &sc->bge_rdata->bge_info.bge_mini_rx_rcb; 1276 rcb->bge_flags = BGE_RCB_FLAG_RING_DISABLED; 1277 rcbo = (struct bge_rcb_opaque *)rcb; 1278 CSR_WRITE_4(sc, BGE_RX_MINI_RCB_MAXLEN_FLAGS, rcbo->bge_reg2); 1279 1280 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 1281 offsetof(struct bge_ring_data, bge_info), sizeof (struct bge_gib), 1282 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1283 1284 /* 1285 * Set the BD ring replentish thresholds. The recommended 1286 * values are 1/8th the number of descriptors allocated to 1287 * each ring. 1288 */ 1289 CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, BGE_STD_RX_RING_CNT/8); 1290 CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH, BGE_JUMBO_RX_RING_CNT/8); 1291 1292 /* 1293 * Disable all unused send rings by setting the 'ring disabled' 1294 * bit in the flags field of all the TX send ring control blocks. 1295 * These are located in NIC memory. 1296 */ 1297 rcb_addr = BGE_MEMWIN_START + BGE_SEND_RING_RCB; 1298 for (i = 0; i < BGE_TX_RINGS_EXTSSRAM_MAX; i++) { 1299 RCB_WRITE_2(sc, rcb_addr, bge_flags, 1300 BGE_RCB_FLAG_RING_DISABLED); 1301 RCB_WRITE_2(sc, rcb_addr, bge_max_len, 0); 1302 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 0); 1303 rcb_addr += sizeof(struct bge_rcb); 1304 } 1305 1306 /* Configure TX RCB 0 (we use only the first ring) */ 1307 rcb_addr = BGE_MEMWIN_START + BGE_SEND_RING_RCB; 1308 bge_set_hostaddr(&taddr, BGE_RING_DMA_ADDR(sc, bge_tx_ring)); 1309 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi); 1310 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo); 1311 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 1312 BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT)); 1313 RCB_WRITE_2(sc, rcb_addr, bge_max_len, BGE_TX_RING_CNT); 1314 RCB_WRITE_2(sc, rcb_addr, bge_flags, 0); 1315 1316 /* Disable all unused RX return rings */ 1317 rcb_addr = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB; 1318 for (i = 0; i < BGE_RX_RINGS_MAX; i++) { 1319 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_hi, 0); 1320 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_lo, 0); 1321 RCB_WRITE_2(sc, rcb_addr, bge_flags, 1322 BGE_RCB_FLAG_RING_DISABLED); 1323 RCB_WRITE_2(sc, rcb_addr, bge_max_len, BGE_RETURN_RING_CNT); 1324 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 0); 1325 CSR_WRITE_4(sc, BGE_MBX_RX_CONS0_LO + 1326 (i * (sizeof(u_int64_t))), 0); 1327 rcb_addr += sizeof(struct bge_rcb); 1328 } 1329 1330 /* Initialize RX ring indexes */ 1331 CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, 0); 1332 CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0); 1333 CSR_WRITE_4(sc, BGE_MBX_RX_MINI_PROD_LO, 0); 1334 1335 /* 1336 * Set up RX return ring 0 1337 * Note that the NIC address for RX return rings is 0x00000000. 1338 * The return rings live entirely within the host, so the 1339 * nicaddr field in the RCB isn't used. 1340 */ 1341 rcb_addr = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB; 1342 bge_set_hostaddr(&taddr, BGE_RING_DMA_ADDR(sc, bge_rx_return_ring)); 1343 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi); 1344 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo); 1345 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 0x00000000); 1346 RCB_WRITE_2(sc, rcb_addr, bge_max_len, BGE_RETURN_RING_CNT); 1347 RCB_WRITE_2(sc, rcb_addr, bge_flags, 0); 1348 1349 /* Set random backoff seed for TX */ 1350 CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF, 1351 LLADDR(ifp->if_sadl)[0] + LLADDR(ifp->if_sadl)[1] + 1352 LLADDR(ifp->if_sadl)[2] + LLADDR(ifp->if_sadl)[3] + 1353 LLADDR(ifp->if_sadl)[4] + LLADDR(ifp->if_sadl)[5] + 1354 BGE_TX_BACKOFF_SEED_MASK); 1355 1356 /* Set inter-packet gap */ 1357 CSR_WRITE_4(sc, BGE_TX_LENGTHS, 0x2620); 1358 1359 /* 1360 * Specify which ring to use for packets that don't match 1361 * any RX rules. 1362 */ 1363 CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08); 1364 1365 /* 1366 * Configure number of RX lists. One interrupt distribution 1367 * list, sixteen active lists, one bad frames class. 1368 */ 1369 CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181); 1370 1371 /* Inialize RX list placement stats mask. */ 1372 CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF); 1373 CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1); 1374 1375 /* Disable host coalescing until we get it set up */ 1376 CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000); 1377 1378 /* Poll to make sure it's shut down. */ 1379 for (i = 0; i < BGE_TIMEOUT; i++) { 1380 if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE)) 1381 break; 1382 DELAY(10); 1383 } 1384 1385 if (i == BGE_TIMEOUT) { 1386 printf("%s: host coalescing engine failed to idle\n", 1387 sc->bge_dev.dv_xname); 1388 return(ENXIO); 1389 } 1390 1391 /* Set up host coalescing defaults */ 1392 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bge_rx_coal_ticks); 1393 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bge_tx_coal_ticks); 1394 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bge_rx_max_coal_bds); 1395 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bge_tx_max_coal_bds); 1396 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT, 0); 1397 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT, 0); 1398 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 0); 1399 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 0); 1400 CSR_WRITE_4(sc, BGE_HCC_STATS_TICKS, sc->bge_stat_ticks); 1401 1402 /* Set up address of statistics block */ 1403 bge_set_hostaddr(&taddr, BGE_RING_DMA_ADDR(sc, bge_info.bge_stats)); 1404 CSR_WRITE_4(sc, BGE_HCC_STATS_BASEADDR, BGE_STATS_BLOCK); 1405 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_HI, taddr.bge_addr_hi); 1406 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_LO, taddr.bge_addr_lo); 1407 1408 /* Set up address of status block */ 1409 bge_set_hostaddr(&taddr, BGE_RING_DMA_ADDR(sc, bge_status_block)); 1410 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_BASEADDR, BGE_STATUS_BLOCK); 1411 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI, taddr.bge_addr_hi); 1412 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO, taddr.bge_addr_lo); 1413 sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx = 0; 1414 sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx = 0; 1415 1416 /* Turn on host coalescing state machine */ 1417 CSR_WRITE_4(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE); 1418 1419 /* Turn on RX BD completion state machine and enable attentions */ 1420 CSR_WRITE_4(sc, BGE_RBDC_MODE, 1421 BGE_RBDCMODE_ENABLE|BGE_RBDCMODE_ATTN); 1422 1423 /* Turn on RX list placement state machine */ 1424 CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 1425 1426 /* Turn on RX list selector state machine. */ 1427 CSR_WRITE_4(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 1428 1429 /* Turn on DMA, clear stats */ 1430 CSR_WRITE_4(sc, BGE_MAC_MODE, BGE_MACMODE_TXDMA_ENB| 1431 BGE_MACMODE_RXDMA_ENB|BGE_MACMODE_RX_STATS_CLEAR| 1432 BGE_MACMODE_TX_STATS_CLEAR|BGE_MACMODE_RX_STATS_ENB| 1433 BGE_MACMODE_TX_STATS_ENB|BGE_MACMODE_FRMHDR_DMA_ENB| 1434 (sc->bge_tbi ? BGE_PORTMODE_TBI : BGE_PORTMODE_MII)); 1435 1436 /* Set misc. local control, enable interrupts on attentions */ 1437 CSR_WRITE_4(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_ONATTN); 1438 1439 #ifdef notdef 1440 /* Assert GPIO pins for PHY reset */ 1441 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUT0| 1442 BGE_MLC_MISCIO_OUT1|BGE_MLC_MISCIO_OUT2); 1443 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUTEN0| 1444 BGE_MLC_MISCIO_OUTEN1|BGE_MLC_MISCIO_OUTEN2); 1445 #endif 1446 1447 /* Turn on DMA completion state machine */ 1448 CSR_WRITE_4(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 1449 1450 /* Turn on write DMA state machine */ 1451 CSR_WRITE_4(sc, BGE_WDMA_MODE, 1452 BGE_WDMAMODE_ENABLE|BGE_WDMAMODE_ALL_ATTNS); 1453 1454 /* Turn on read DMA state machine */ 1455 CSR_WRITE_4(sc, BGE_RDMA_MODE, 1456 BGE_RDMAMODE_ENABLE|BGE_RDMAMODE_ALL_ATTNS); 1457 1458 /* Turn on RX data completion state machine */ 1459 CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 1460 1461 /* Turn on RX BD initiator state machine */ 1462 CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 1463 1464 /* Turn on RX data and RX BD initiator state machine */ 1465 CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE); 1466 1467 /* Turn on Mbuf cluster free state machine */ 1468 CSR_WRITE_4(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 1469 1470 /* Turn on send BD completion state machine */ 1471 CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 1472 1473 /* Turn on send data completion state machine */ 1474 CSR_WRITE_4(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE); 1475 1476 /* Turn on send data initiator state machine */ 1477 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 1478 1479 /* Turn on send BD initiator state machine */ 1480 CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 1481 1482 /* Turn on send BD selector state machine */ 1483 CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 1484 1485 CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF); 1486 CSR_WRITE_4(sc, BGE_SDI_STATS_CTL, 1487 BGE_SDISTATSCTL_ENABLE|BGE_SDISTATSCTL_FASTER); 1488 1489 /* init LED register */ 1490 CSR_WRITE_4(sc, BGE_MAC_LED_CTL, 0x00000000); 1491 1492 /* ack/clear link change events */ 1493 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED| 1494 BGE_MACSTAT_CFG_CHANGED); 1495 CSR_WRITE_4(sc, BGE_MI_STS, 0); 1496 1497 /* Enable PHY auto polling (for MII/GMII only) */ 1498 if (sc->bge_tbi) { 1499 CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK); 1500 } else { 1501 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL|10<<16); 1502 if (BGE_IS_5700_Ax_Bx(sc->bge_asicrev)) 1503 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, 1504 BGE_EVTENB_MI_INTERRUPT); 1505 } 1506 1507 /* Enable link state change attentions. */ 1508 BGE_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED); 1509 1510 return(0); 1511 } 1512 1513 /* 1514 * Probe for a Broadcom chip. Check the PCI vendor and device IDs 1515 * against our list and return its name if we find a match. Note 1516 * that since the Broadcom controller contains VPD support, we 1517 * can get the device name string from the controller itself instead 1518 * of the compiled-in string. This is a little slow, but it guarantees 1519 * we'll always announce the right product name. 1520 */ 1521 int 1522 bge_probe(parent, match, aux) 1523 struct device *parent; 1524 struct cfdata *match; 1525 void *aux; 1526 { 1527 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 1528 1529 /* 1530 * Various supported device vendors/types and their 1531 * names. Note: the spec seems to indicate that the hardware 1532 * still has Alteon's vendor ID burned into it, though it will 1533 * always be overriden by the vendor ID in the EEPROM. Just to 1534 * be safe, we cover all possibilities. 1535 */ 1536 1537 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_ALTEON && 1538 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_ALTEON_BCM5700 || 1539 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_ALTEON_BCM5701)) 1540 return (1); 1541 1542 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_ALTIMA && 1543 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_ALTIMA_AC1000) 1544 return (1); 1545 1546 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_BROADCOM && 1547 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5700 || 1548 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5701)) 1549 return (1); 1550 1551 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_SCHNEIDERKOCH && 1552 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_SCHNEIDERKOCH_SK_9DX1) 1553 return (1); 1554 1555 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_3COM && 1556 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_3COM_3C996) 1557 return (1); 1558 1559 return (0); 1560 } 1561 1562 void 1563 bge_attach(parent, self, aux) 1564 struct device *parent, *self; 1565 void *aux; 1566 { 1567 struct bge_softc *sc = (struct bge_softc *)self; 1568 struct pci_attach_args *pa = aux; 1569 pci_chipset_tag_t pc = pa->pa_pc; 1570 pci_intr_handle_t ih; 1571 const char *intrstr = NULL; 1572 bus_dma_segment_t seg; 1573 int rseg; 1574 u_int32_t hwcfg = 0; 1575 u_int32_t command; 1576 struct ifnet *ifp; 1577 int unit; 1578 caddr_t kva; 1579 u_char eaddr[ETHER_ADDR_LEN]; 1580 pcireg_t memtype; 1581 char devinfo[256]; 1582 bus_addr_t memaddr; 1583 bus_size_t memsize; 1584 1585 sc->bge_pa = *pa; 1586 1587 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo); 1588 printf(": %s (rev. 0x%02x)\n", devinfo, PCI_REVISION(pa->pa_class)); 1589 1590 /* 1591 * Map control/status registers. 1592 */ 1593 DPRINTFN(5, ("Map control/status regs\n")); 1594 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 1595 command |= PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_MASTER_ENABLE; 1596 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, command); 1597 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 1598 1599 if (!(command & PCI_COMMAND_MEM_ENABLE)) { 1600 printf("%s: failed to enable memory mapping!\n", 1601 sc->bge_dev.dv_xname); 1602 return; 1603 } 1604 1605 DPRINTFN(5, ("pci_mem_find\n")); 1606 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, BGE_PCI_BAR0); 1607 switch (memtype) { 1608 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 1609 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 1610 if (pci_mapreg_map(pa, BGE_PCI_BAR0, 1611 memtype, 0, &sc->bge_btag, &sc->bge_bhandle, 1612 &memaddr, &memsize) == 0) 1613 break; 1614 default: 1615 printf("%s: can't find mem space\n", 1616 sc->bge_dev.dv_xname); 1617 return; 1618 } 1619 1620 DPRINTFN(5, ("pci_intr_map\n")); 1621 if (pci_intr_map(pa, &ih)) { 1622 printf("%s: couldn't map interrupt\n", 1623 sc->bge_dev.dv_xname); 1624 return; 1625 } 1626 1627 DPRINTFN(5, ("pci_intr_string\n")); 1628 intrstr = pci_intr_string(pc, ih); 1629 1630 DPRINTFN(5, ("pci_intr_establish\n")); 1631 sc->bge_intrhand = pci_intr_establish(pc, ih, IPL_NET, bge_intr, sc); 1632 1633 if (sc->bge_intrhand == NULL) { 1634 printf("%s: couldn't establish interrupt", 1635 sc->bge_dev.dv_xname); 1636 if (intrstr != NULL) 1637 printf(" at %s", intrstr); 1638 printf("\n"); 1639 return; 1640 } 1641 printf("%s: interrupting at %s\n", sc->bge_dev.dv_xname, intrstr); 1642 1643 /* Try to reset the chip. */ 1644 DPRINTFN(5, ("bge_reset\n")); 1645 bge_reset(sc); 1646 1647 if (bge_chipinit(sc)) { 1648 printf("%s: chip initializatino failed\n", 1649 sc->bge_dev.dv_xname); 1650 bge_release_resources(sc); 1651 return; 1652 } 1653 1654 /* 1655 * Get station address from the EEPROM. 1656 */ 1657 if (bge_read_eeprom(sc, (caddr_t)eaddr, 1658 BGE_EE_MAC_OFFSET + 2, ETHER_ADDR_LEN)) { 1659 printf("bge%d: failed to read station address\n", unit); 1660 bge_release_resources(sc); 1661 return; 1662 } 1663 1664 /* 1665 * A Broadcom chip was detected. Inform the world. 1666 */ 1667 printf("%s: Ethernet address %s\n", sc->bge_dev.dv_xname, 1668 ether_sprintf(eaddr)); 1669 1670 /* Allocate the general information block and ring buffers. */ 1671 sc->bge_dmatag = pa->pa_dmat; 1672 DPRINTFN(5, ("bus_dmamem_alloc\n")); 1673 if (bus_dmamem_alloc(sc->bge_dmatag, sizeof(struct bge_ring_data), 1674 PAGE_SIZE, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 1675 printf("%s: can't alloc rx buffers\n", sc->bge_dev.dv_xname); 1676 return; 1677 } 1678 DPRINTFN(5, ("bus_dmamem_map\n")); 1679 if (bus_dmamem_map(sc->bge_dmatag, &seg, rseg, 1680 sizeof(struct bge_ring_data), &kva, 1681 BUS_DMA_NOWAIT)) { 1682 printf("%s: can't map dma buffers (%d bytes)\n", 1683 sc->bge_dev.dv_xname, (int)sizeof(struct bge_ring_data)); 1684 bus_dmamem_free(sc->bge_dmatag, &seg, rseg); 1685 return; 1686 } 1687 DPRINTFN(5, ("bus_dmamem_create\n")); 1688 if (bus_dmamap_create(sc->bge_dmatag, sizeof(struct bge_ring_data), 1, 1689 sizeof(struct bge_ring_data), 0, 1690 BUS_DMA_NOWAIT, &sc->bge_ring_map)) { 1691 printf("%s: can't create dma map\n", sc->bge_dev.dv_xname); 1692 bus_dmamem_unmap(sc->bge_dmatag, kva, 1693 sizeof(struct bge_ring_data)); 1694 bus_dmamem_free(sc->bge_dmatag, &seg, rseg); 1695 return; 1696 } 1697 DPRINTFN(5, ("bus_dmamem_load\n")); 1698 if (bus_dmamap_load(sc->bge_dmatag, sc->bge_ring_map, kva, 1699 sizeof(struct bge_ring_data), NULL, 1700 BUS_DMA_NOWAIT)) { 1701 bus_dmamap_destroy(sc->bge_dmatag, sc->bge_ring_map); 1702 bus_dmamem_unmap(sc->bge_dmatag, kva, 1703 sizeof(struct bge_ring_data)); 1704 bus_dmamem_free(sc->bge_dmatag, &seg, rseg); 1705 return; 1706 } 1707 1708 DPRINTFN(5, ("bzero\n")); 1709 sc->bge_rdata = (struct bge_ring_data *)kva; 1710 1711 memset(sc->bge_rdata, sizeof(struct bge_ring_data), 0); 1712 1713 /* Try to allocate memory for jumbo buffers. */ 1714 if (bge_alloc_jumbo_mem(sc)) { 1715 printf("%s: jumbo buffer allocation failed\n", 1716 sc->bge_dev.dv_xname); 1717 } 1718 1719 /* Set default tuneable values. */ 1720 sc->bge_stat_ticks = BGE_TICKS_PER_SEC; 1721 sc->bge_rx_coal_ticks = 150; 1722 sc->bge_tx_coal_ticks = 150; 1723 sc->bge_rx_max_coal_bds = 64; 1724 sc->bge_tx_max_coal_bds = 128; 1725 1726 /* Set up ifnet structure */ 1727 ifp = &sc->ethercom.ec_if; 1728 ifp->if_softc = sc; 1729 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1730 ifp->if_ioctl = bge_ioctl; 1731 ifp->if_start = bge_start; 1732 ifp->if_init = bge_init; 1733 ifp->if_watchdog = bge_watchdog; 1734 IFQ_SET_MAXLEN(&ifp->if_snd, BGE_TX_RING_CNT - 1); 1735 IFQ_SET_READY(&ifp->if_snd); 1736 DPRINTFN(5, ("bcopy\n")); 1737 strcpy(ifp->if_xname, sc->bge_dev.dv_xname); 1738 1739 sc->ethercom.ec_capabilities |= ETHERCAP_JUMBO_MTU; 1740 1741 sc->ethercom.ec_if.if_capabilities |= 1742 IFCAP_CSUM_IPv4 | IFCAP_CSUM_TCPv4 | IFCAP_CSUM_UDPv4; 1743 sc->ethercom.ec_capabilities |= 1744 ETHERCAP_VLAN_HWTAGGING | ETHERCAP_VLAN_MTU; 1745 1746 /* 1747 * Do MII setup. 1748 */ 1749 DPRINTFN(5, ("mii setup\n")); 1750 sc->bge_mii.mii_ifp = ifp; 1751 sc->bge_mii.mii_readreg = bge_miibus_readreg; 1752 sc->bge_mii.mii_writereg = bge_miibus_writereg; 1753 sc->bge_mii.mii_statchg = bge_miibus_statchg; 1754 1755 /* Save ASIC rev. */ 1756 1757 sc->bge_asicrev = 1758 pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_MISC_CTL) & 1759 BGE_PCIMISCCTL_ASICREV; 1760 1761 /* 1762 * Figure out what sort of media we have by checking the 1763 * hardware config word in the EEPROM. Note: on some BCM5700 1764 * cards, this value appears to be unset. If that's the 1765 * case, we have to rely on identifying the NIC by its PCI 1766 * subsystem ID, as we do below for the SysKonnect SK-9D41. 1767 */ 1768 bge_read_eeprom(sc, (caddr_t)&hwcfg, 1769 BGE_EE_HWCFG_OFFSET, sizeof(hwcfg)); 1770 if ((be32toh(hwcfg) & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER) 1771 sc->bge_tbi = 1; 1772 1773 /* The SysKonnect SK-9D41 is a 1000baseSX card. */ 1774 if ((pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_SUBSYS) >> 16) == 1775 SK_SUBSYSID_9D41) 1776 sc->bge_tbi = 1; 1777 1778 if (sc->bge_tbi) { 1779 ifmedia_init(&sc->bge_ifmedia, IFM_IMASK, bge_ifmedia_upd, 1780 bge_ifmedia_sts); 1781 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL); 1782 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_1000_SX|IFM_FDX, 1783 0, NULL); 1784 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL); 1785 ifmedia_set(&sc->bge_ifmedia, IFM_ETHER|IFM_AUTO); 1786 } else { 1787 /* 1788 * Do transceiver setup. 1789 */ 1790 ifmedia_init(&sc->bge_mii.mii_media, 0, bge_ifmedia_upd, 1791 bge_ifmedia_sts); 1792 mii_attach(&sc->bge_dev, &sc->bge_mii, 0xffffffff, 1793 MII_PHY_ANY, MII_OFFSET_ANY, 0); 1794 1795 if (LIST_FIRST(&sc->bge_mii.mii_phys) == NULL) { 1796 printf("%s: no PHY found!\n", sc->bge_dev.dv_xname); 1797 ifmedia_add(&sc->bge_mii.mii_media, 1798 IFM_ETHER|IFM_MANUAL, 0, NULL); 1799 ifmedia_set(&sc->bge_mii.mii_media, 1800 IFM_ETHER|IFM_MANUAL); 1801 } else 1802 ifmedia_set(&sc->bge_mii.mii_media, 1803 IFM_ETHER|IFM_AUTO); 1804 } 1805 1806 /* 1807 * Call MI attach routine. 1808 */ 1809 DPRINTFN(5, ("if_attach\n")); 1810 if_attach(ifp); 1811 DPRINTFN(5, ("ether_ifattach\n")); 1812 ether_ifattach(ifp, eaddr); 1813 DPRINTFN(5, ("callout_init\n")); 1814 callout_init(&sc->bge_timeout); 1815 } 1816 1817 void 1818 bge_release_resources(sc) 1819 struct bge_softc *sc; 1820 { 1821 if (sc->bge_vpd_prodname != NULL) 1822 free(sc->bge_vpd_prodname, M_DEVBUF); 1823 1824 if (sc->bge_vpd_readonly != NULL) 1825 free(sc->bge_vpd_readonly, M_DEVBUF); 1826 1827 #ifdef fake 1828 if (sc->bge_intrhand != NULL) 1829 bus_teardown_intr(dev, sc->bge_irq, sc->bge_intrhand); 1830 1831 if (sc->bge_irq != NULL) 1832 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->bge_irq); 1833 1834 if (sc->bge_res != NULL) 1835 bus_release_resource(dev, SYS_RES_MEMORY, 1836 BGE_PCI_BAR0, sc->bge_res); 1837 1838 if (sc->bge_rdata != NULL) 1839 contigfree(sc->bge_rdata, 1840 sizeof(struct bge_ring_data), M_DEVBUF); 1841 #endif 1842 } 1843 1844 void 1845 bge_reset(sc) 1846 struct bge_softc *sc; 1847 { 1848 struct pci_attach_args *pa = &sc->bge_pa; 1849 u_int32_t cachesize, command, pcistate; 1850 int i, val = 0; 1851 1852 /* Save some important PCI state. */ 1853 cachesize = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_CACHESZ); 1854 command = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_CMD); 1855 pcistate = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_PCISTATE); 1856 1857 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_MISC_CTL, 1858 BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR| 1859 BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_PCISTATE_RW); 1860 1861 /* Issue global reset */ 1862 bge_writereg_ind(sc, BGE_MISC_CFG, 1863 BGE_MISCCFG_RESET_CORE_CLOCKS|(65<<1)); 1864 1865 DELAY(1000); 1866 1867 /* Reset some of the PCI state that got zapped by reset */ 1868 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_MISC_CTL, 1869 BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR| 1870 BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_PCISTATE_RW); 1871 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_CMD, command); 1872 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_CACHESZ, cachesize); 1873 bge_writereg_ind(sc, BGE_MISC_CFG, (65 << 1)); 1874 1875 /* Enable memory arbiter. */ 1876 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 1877 1878 /* 1879 * Prevent PXE restart: write a magic number to the 1880 * general communications memory at 0xB50. 1881 */ 1882 bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM, BGE_MAGIC_NUMBER); 1883 1884 /* 1885 * Poll the value location we just wrote until 1886 * we see the 1's complement of the magic number. 1887 * This indicates that the firmware initialization 1888 * is complete. 1889 */ 1890 for (i = 0; i < 750; i++) { 1891 val = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM); 1892 if (val == ~BGE_MAGIC_NUMBER) 1893 break; 1894 DELAY(1000); 1895 } 1896 1897 if (i == BGE_TIMEOUT) { 1898 printf("%s: firmware handshake timed out, val = %x\n", 1899 sc->bge_dev.dv_xname, val); 1900 return; 1901 } 1902 1903 /* 1904 * XXX Wait for the value of the PCISTATE register to 1905 * return to its original pre-reset state. This is a 1906 * fairly good indicator of reset completion. If we don't 1907 * wait for the reset to fully complete, trying to read 1908 * from the device's non-PCI registers may yield garbage 1909 * results. 1910 */ 1911 for (i = 0; i < BGE_TIMEOUT; i++) { 1912 if (pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_PCISTATE) == 1913 pcistate) 1914 break; 1915 DELAY(10); 1916 } 1917 1918 /* Enable memory arbiter. */ 1919 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 1920 1921 /* Fix up byte swapping */ 1922 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS); 1923 1924 CSR_WRITE_4(sc, BGE_MAC_MODE, 0); 1925 1926 DELAY(10000); 1927 } 1928 1929 /* 1930 * Frame reception handling. This is called if there's a frame 1931 * on the receive return list. 1932 * 1933 * Note: we have to be able to handle two possibilities here: 1934 * 1) the frame is from the jumbo recieve ring 1935 * 2) the frame is from the standard receive ring 1936 */ 1937 1938 void 1939 bge_rxeof(sc) 1940 struct bge_softc *sc; 1941 { 1942 struct ifnet *ifp; 1943 int stdcnt = 0, jumbocnt = 0; 1944 int have_tag = 0; 1945 u_int16_t vlan_tag = 0; 1946 bus_dmamap_t dmamap; 1947 bus_addr_t offset, toff; 1948 bus_size_t tlen; 1949 int tosync; 1950 1951 ifp = &sc->ethercom.ec_if; 1952 1953 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 1954 offsetof(struct bge_ring_data, bge_status_block), 1955 sizeof (struct bge_status_block), 1956 BUS_DMASYNC_POSTREAD); 1957 1958 offset = offsetof(struct bge_ring_data, bge_rx_return_ring); 1959 tosync = sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx - 1960 sc->bge_rx_saved_considx; 1961 1962 toff = offset + (sc->bge_rx_saved_considx * sizeof (struct bge_rx_bd)); 1963 1964 if (tosync < 0) { 1965 tlen = (BGE_RETURN_RING_CNT - sc->bge_rx_saved_considx) * 1966 sizeof (struct bge_rx_bd); 1967 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 1968 toff, tlen, BUS_DMASYNC_POSTREAD); 1969 tosync = -tosync; 1970 } 1971 1972 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 1973 offset, tosync * sizeof (struct bge_rx_bd), 1974 BUS_DMASYNC_POSTREAD); 1975 1976 while(sc->bge_rx_saved_considx != 1977 sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx) { 1978 struct bge_rx_bd *cur_rx; 1979 u_int32_t rxidx; 1980 struct mbuf *m = NULL; 1981 1982 cur_rx = &sc->bge_rdata-> 1983 bge_rx_return_ring[sc->bge_rx_saved_considx]; 1984 1985 rxidx = cur_rx->bge_idx; 1986 BGE_INC(sc->bge_rx_saved_considx, BGE_RETURN_RING_CNT); 1987 1988 if (cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) { 1989 have_tag = 1; 1990 vlan_tag = cur_rx->bge_vlan_tag; 1991 } 1992 1993 if (cur_rx->bge_flags & BGE_RXBDFLAG_JUMBO_RING) { 1994 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT); 1995 m = sc->bge_cdata.bge_rx_jumbo_chain[rxidx]; 1996 sc->bge_cdata.bge_rx_jumbo_chain[rxidx] = NULL; 1997 jumbocnt++; 1998 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 1999 ifp->if_ierrors++; 2000 bge_newbuf_jumbo(sc, sc->bge_jumbo, m); 2001 continue; 2002 } 2003 if (bge_newbuf_jumbo(sc, sc->bge_jumbo, 2004 NULL)== ENOBUFS) { 2005 ifp->if_ierrors++; 2006 bge_newbuf_jumbo(sc, sc->bge_jumbo, m); 2007 continue; 2008 } 2009 } else { 2010 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT); 2011 m = sc->bge_cdata.bge_rx_std_chain[rxidx]; 2012 sc->bge_cdata.bge_rx_std_chain[rxidx] = NULL; 2013 stdcnt++; 2014 dmamap = sc->bge_cdata.bge_rx_std_map[rxidx]; 2015 sc->bge_cdata.bge_rx_std_map[rxidx] = 0; 2016 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 2017 ifp->if_ierrors++; 2018 bge_newbuf_std(sc, sc->bge_std, m, dmamap); 2019 continue; 2020 } 2021 if (bge_newbuf_std(sc, sc->bge_std, 2022 NULL, dmamap) == ENOBUFS) { 2023 ifp->if_ierrors++; 2024 bge_newbuf_std(sc, sc->bge_std, m, dmamap); 2025 continue; 2026 } 2027 } 2028 2029 ifp->if_ipackets++; 2030 m->m_pkthdr.len = m->m_len = cur_rx->bge_len; 2031 m->m_pkthdr.rcvif = ifp; 2032 2033 #if NBPFILTER > 0 2034 /* 2035 * Handle BPF listeners. Let the BPF user see the packet. 2036 */ 2037 if (ifp->if_bpf) 2038 bpf_mtap(ifp->if_bpf, m); 2039 #endif 2040 2041 if (sc->bge_asicrev != BGE_ASICREV_BCM5700_B0) { 2042 m->m_pkthdr.csum_flags |= M_CSUM_IPv4; 2043 if ((cur_rx->bge_ip_csum ^ 0xffff) != 0) 2044 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 2045 if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM) { 2046 m->m_pkthdr.csum_data = 2047 cur_rx->bge_tcp_udp_csum; 2048 m->m_pkthdr.csum_flags |= 2049 (M_CSUM_TCPv4|M_CSUM_UDPv4|M_CSUM_DATA); 2050 } 2051 } 2052 2053 /* 2054 * If we received a packet with a vlan tag, pass it 2055 * to vlan_input() instead of ether_input(). 2056 */ 2057 if (have_tag) { 2058 struct mbuf *n; 2059 2060 n = m_aux_add(m, AF_LINK, ETHERTYPE_VLAN); 2061 if (n != NULL) { 2062 *mtod(n, int *) = vlan_tag; 2063 n->m_len = sizeof(int); 2064 have_tag = vlan_tag = 0; 2065 } else { 2066 printf("%s: no mbuf for tag\n", ifp->if_xname); 2067 m_freem(m); 2068 have_tag = vlan_tag = 0; 2069 continue; 2070 } 2071 } 2072 (*ifp->if_input)(ifp, m); 2073 } 2074 2075 CSR_WRITE_4(sc, BGE_MBX_RX_CONS0_LO, sc->bge_rx_saved_considx); 2076 if (stdcnt) 2077 CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std); 2078 if (jumbocnt) 2079 CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo); 2080 } 2081 2082 void 2083 bge_txeof(sc) 2084 struct bge_softc *sc; 2085 { 2086 struct bge_tx_bd *cur_tx = NULL; 2087 struct ifnet *ifp; 2088 struct txdmamap_pool_entry *dma; 2089 bus_addr_t offset, toff; 2090 bus_size_t tlen; 2091 int tosync; 2092 struct mbuf *m; 2093 2094 ifp = &sc->ethercom.ec_if; 2095 2096 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 2097 offsetof(struct bge_ring_data, bge_status_block), 2098 sizeof (struct bge_status_block), 2099 BUS_DMASYNC_POSTREAD); 2100 2101 offset = offsetof(struct bge_ring_data, bge_tx_ring); 2102 tosync = sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx - 2103 sc->bge_tx_saved_considx; 2104 2105 toff = offset + (sc->bge_tx_saved_considx * sizeof (struct bge_tx_bd)); 2106 2107 if (tosync < 0) { 2108 tlen = (BGE_TX_RING_CNT - sc->bge_tx_saved_considx) * 2109 sizeof (struct bge_tx_bd); 2110 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 2111 toff, tlen, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2112 tosync = -tosync; 2113 } 2114 2115 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 2116 offset, tosync * sizeof (struct bge_tx_bd), 2117 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2118 2119 /* 2120 * Go through our tx ring and free mbufs for those 2121 * frames that have been sent. 2122 */ 2123 while (sc->bge_tx_saved_considx != 2124 sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx) { 2125 u_int32_t idx = 0; 2126 2127 idx = sc->bge_tx_saved_considx; 2128 cur_tx = &sc->bge_rdata->bge_tx_ring[idx]; 2129 if (cur_tx->bge_flags & BGE_TXBDFLAG_END) 2130 ifp->if_opackets++; 2131 m = sc->bge_cdata.bge_tx_chain[idx]; 2132 if (m != NULL) { 2133 sc->bge_cdata.bge_tx_chain[idx] = NULL; 2134 dma = sc->txdma[idx]; 2135 bus_dmamap_sync(sc->bge_dmatag, dma->dmamap, 0, 2136 dma->dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 2137 bus_dmamap_unload(sc->bge_dmatag, dma->dmamap); 2138 SLIST_INSERT_HEAD(&sc->txdma_list, dma, link); 2139 sc->txdma[idx] = NULL; 2140 2141 m_freem(m); 2142 } 2143 sc->bge_txcnt--; 2144 BGE_INC(sc->bge_tx_saved_considx, BGE_TX_RING_CNT); 2145 ifp->if_timer = 0; 2146 } 2147 2148 if (cur_tx != NULL) 2149 ifp->if_flags &= ~IFF_OACTIVE; 2150 } 2151 2152 int 2153 bge_intr(xsc) 2154 void *xsc; 2155 { 2156 struct bge_softc *sc; 2157 struct ifnet *ifp; 2158 2159 sc = xsc; 2160 ifp = &sc->ethercom.ec_if; 2161 2162 #ifdef notdef 2163 /* Avoid this for now -- checking this register is expensive. */ 2164 /* Make sure this is really our interrupt. */ 2165 if (!(CSR_READ_4(sc, BGE_MISC_LOCAL_CTL) & BGE_MLC_INTR_STATE)) 2166 return (0); 2167 #endif 2168 /* Ack interrupt and stop others from occuring. */ 2169 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 1); 2170 2171 /* 2172 * Process link state changes. 2173 * Grrr. The link status word in the status block does 2174 * not work correctly on the BCM5700 rev AX and BX chips, 2175 * according to all avaibable information. Hence, we have 2176 * to enable MII interrupts in order to properly obtain 2177 * async link changes. Unfortunately, this also means that 2178 * we have to read the MAC status register to detect link 2179 * changes, thereby adding an additional register access to 2180 * the interrupt handler. 2181 */ 2182 2183 if (BGE_IS_5700_Ax_Bx(sc->bge_asicrev)) { 2184 u_int32_t status; 2185 2186 status = CSR_READ_4(sc, BGE_MAC_STS); 2187 if (status & BGE_MACSTAT_MI_INTERRUPT) { 2188 sc->bge_link = 0; 2189 callout_stop(&sc->bge_timeout); 2190 bge_tick(sc); 2191 /* Clear the interrupt */ 2192 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, 2193 BGE_EVTENB_MI_INTERRUPT); 2194 bge_miibus_readreg(&sc->bge_dev, 1, BRGPHY_MII_ISR); 2195 bge_miibus_writereg(&sc->bge_dev, 1, BRGPHY_MII_IMR, 2196 BRGPHY_INTRS); 2197 } 2198 } else { 2199 if (sc->bge_rdata->bge_status_block.bge_status & 2200 BGE_STATFLAG_LINKSTATE_CHANGED) { 2201 sc->bge_link = 0; 2202 callout_stop(&sc->bge_timeout); 2203 bge_tick(sc); 2204 /* Clear the interrupt */ 2205 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED| 2206 BGE_MACSTAT_CFG_CHANGED); 2207 } 2208 } 2209 2210 if (ifp->if_flags & IFF_RUNNING) { 2211 /* Check RX return ring producer/consumer */ 2212 bge_rxeof(sc); 2213 2214 /* Check TX ring producer/consumer */ 2215 bge_txeof(sc); 2216 } 2217 2218 bge_handle_events(sc); 2219 2220 /* Re-enable interrupts. */ 2221 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 0); 2222 2223 if (ifp->if_flags & IFF_RUNNING && !IFQ_IS_EMPTY(&ifp->if_snd)) 2224 bge_start(ifp); 2225 2226 return (1); 2227 } 2228 2229 void 2230 bge_tick(xsc) 2231 void *xsc; 2232 { 2233 struct bge_softc *sc = xsc; 2234 struct mii_data *mii = &sc->bge_mii; 2235 struct ifmedia *ifm = NULL; 2236 struct ifnet *ifp = &sc->ethercom.ec_if; 2237 int s; 2238 2239 s = splnet(); 2240 2241 bge_stats_update(sc); 2242 callout_reset(&sc->bge_timeout, hz, bge_tick, sc); 2243 if (sc->bge_link) { 2244 splx(s); 2245 return; 2246 } 2247 2248 if (sc->bge_tbi) { 2249 ifm = &sc->bge_ifmedia; 2250 if (CSR_READ_4(sc, BGE_MAC_STS) & 2251 BGE_MACSTAT_TBI_PCS_SYNCHED) { 2252 sc->bge_link++; 2253 CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF); 2254 printf("%s: gigabit link up\n", sc->bge_dev.dv_xname); 2255 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 2256 bge_start(ifp); 2257 } 2258 splx(s); 2259 return; 2260 } 2261 2262 mii_tick(mii); 2263 2264 if (!sc->bge_link && mii->mii_media_status & IFM_ACTIVE && 2265 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 2266 sc->bge_link++; 2267 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T || 2268 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX) 2269 printf("%s: gigabit link up\n", sc->bge_dev.dv_xname); 2270 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 2271 bge_start(ifp); 2272 } 2273 2274 splx(s); 2275 } 2276 2277 void 2278 bge_stats_update(sc) 2279 struct bge_softc *sc; 2280 { 2281 struct ifnet *ifp = &sc->ethercom.ec_if; 2282 bus_size_t stats = BGE_MEMWIN_START + BGE_STATS_BLOCK; 2283 2284 #define READ_STAT(sc, stats, stat) \ 2285 CSR_READ_4(sc, stats + offsetof(struct bge_stats, stat)) 2286 2287 ifp->if_collisions += 2288 (READ_STAT(sc, stats, dot3StatsSingleCollisionFrames.bge_addr_lo) + 2289 READ_STAT(sc, stats, dot3StatsMultipleCollisionFrames.bge_addr_lo) + 2290 READ_STAT(sc, stats, dot3StatsExcessiveCollisions.bge_addr_lo) + 2291 READ_STAT(sc, stats, dot3StatsLateCollisions.bge_addr_lo)) - 2292 ifp->if_collisions; 2293 2294 #undef READ_STAT 2295 2296 #ifdef notdef 2297 ifp->if_collisions += 2298 (sc->bge_rdata->bge_info.bge_stats.dot3StatsSingleCollisionFrames + 2299 sc->bge_rdata->bge_info.bge_stats.dot3StatsMultipleCollisionFrames + 2300 sc->bge_rdata->bge_info.bge_stats.dot3StatsExcessiveCollisions + 2301 sc->bge_rdata->bge_info.bge_stats.dot3StatsLateCollisions) - 2302 ifp->if_collisions; 2303 #endif 2304 } 2305 2306 /* 2307 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data 2308 * pointers to descriptors. 2309 */ 2310 int 2311 bge_encap(sc, m_head, txidx) 2312 struct bge_softc *sc; 2313 struct mbuf *m_head; 2314 u_int32_t *txidx; 2315 { 2316 struct bge_tx_bd *f = NULL; 2317 u_int32_t frag, cur, cnt = 0; 2318 u_int16_t csum_flags = 0; 2319 struct txdmamap_pool_entry *dma; 2320 bus_dmamap_t dmamap; 2321 int i = 0; 2322 struct mbuf *n; 2323 2324 cur = frag = *txidx; 2325 2326 if (m_head->m_pkthdr.csum_flags) { 2327 if (m_head->m_pkthdr.csum_flags & M_CSUM_IPv4) 2328 csum_flags |= BGE_TXBDFLAG_IP_CSUM; 2329 if (m_head->m_pkthdr.csum_flags & (M_CSUM_TCPv4| M_CSUM_UDPv4)) 2330 csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM; 2331 } 2332 2333 dma = SLIST_FIRST(&sc->txdma_list); 2334 if (dma == NULL) 2335 return ENOBUFS; 2336 dmamap = dma->dmamap; 2337 2338 /* 2339 * Start packing the mbufs in this chain into 2340 * the fragment pointers. Stop when we run out 2341 * of fragments or hit the end of the mbuf chain. 2342 */ 2343 if (bus_dmamap_load_mbuf(sc->bge_dmatag, dmamap, m_head, 2344 BUS_DMA_NOWAIT)) 2345 return(ENOBUFS); 2346 2347 for (i = 0; i < dmamap->dm_nsegs; i++) { 2348 f = &sc->bge_rdata->bge_tx_ring[frag]; 2349 if (sc->bge_cdata.bge_tx_chain[frag] != NULL) 2350 break; 2351 bge_set_hostaddr(&f->bge_addr, dmamap->dm_segs[i].ds_addr); 2352 f->bge_len = dmamap->dm_segs[i].ds_len; 2353 f->bge_flags = csum_flags; 2354 2355 n = m_aux_find(m_head, AF_LINK, ETHERTYPE_VLAN); 2356 if (n != NULL) { 2357 f->bge_flags |= BGE_TXBDFLAG_VLAN_TAG; 2358 f->bge_vlan_tag = *mtod(n, int *); 2359 } else { 2360 f->bge_vlan_tag = 0; 2361 } 2362 /* 2363 * Sanity check: avoid coming within 16 descriptors 2364 * of the end of the ring. 2365 */ 2366 if ((BGE_TX_RING_CNT - (sc->bge_txcnt + cnt)) < 16) 2367 return(ENOBUFS); 2368 cur = frag; 2369 BGE_INC(frag, BGE_TX_RING_CNT); 2370 cnt++; 2371 } 2372 2373 if (i < dmamap->dm_nsegs) 2374 return ENOBUFS; 2375 2376 bus_dmamap_sync(sc->bge_dmatag, dmamap, 0, dmamap->dm_mapsize, 2377 BUS_DMASYNC_PREWRITE); 2378 2379 if (frag == sc->bge_tx_saved_considx) 2380 return(ENOBUFS); 2381 2382 sc->bge_rdata->bge_tx_ring[cur].bge_flags |= BGE_TXBDFLAG_END; 2383 sc->bge_cdata.bge_tx_chain[cur] = m_head; 2384 SLIST_REMOVE_HEAD(&sc->txdma_list, link); 2385 sc->txdma[cur] = dma; 2386 sc->bge_txcnt += cnt; 2387 2388 *txidx = frag; 2389 2390 return(0); 2391 } 2392 2393 /* 2394 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 2395 * to the mbuf data regions directly in the transmit descriptors. 2396 */ 2397 void 2398 bge_start(ifp) 2399 struct ifnet *ifp; 2400 { 2401 struct bge_softc *sc; 2402 struct mbuf *m_head = NULL; 2403 u_int32_t prodidx = 0; 2404 int pkts = 0; 2405 2406 sc = ifp->if_softc; 2407 2408 if (!sc->bge_link && ifp->if_snd.ifq_len < 10) 2409 return; 2410 2411 prodidx = CSR_READ_4(sc, BGE_MBX_TX_HOST_PROD0_LO); 2412 2413 while(sc->bge_cdata.bge_tx_chain[prodidx] == NULL) { 2414 IFQ_POLL(&ifp->if_snd, m_head); 2415 if (m_head == NULL) 2416 break; 2417 2418 #if 0 2419 /* 2420 * XXX 2421 * safety overkill. If this is a fragmented packet chain 2422 * with delayed TCP/UDP checksums, then only encapsulate 2423 * it if we have enough descriptors to handle the entire 2424 * chain at once. 2425 * (paranoia -- may not actually be needed) 2426 */ 2427 if (m_head->m_flags & M_FIRSTFRAG && 2428 m_head->m_pkthdr.csum_flags & (CSUM_DELAY_DATA)) { 2429 if ((BGE_TX_RING_CNT - sc->bge_txcnt) < 2430 m_head->m_pkthdr.csum_data + 16) { 2431 ifp->if_flags |= IFF_OACTIVE; 2432 break; 2433 } 2434 } 2435 #endif 2436 2437 /* 2438 * Pack the data into the transmit ring. If we 2439 * don't have room, set the OACTIVE flag and wait 2440 * for the NIC to drain the ring. 2441 */ 2442 if (bge_encap(sc, m_head, &prodidx)) { 2443 ifp->if_flags |= IFF_OACTIVE; 2444 break; 2445 } 2446 2447 /* now we are committed to transmit the packet */ 2448 IFQ_DEQUEUE(&ifp->if_snd, m_head); 2449 pkts++; 2450 2451 #if NBPFILTER > 0 2452 /* 2453 * If there's a BPF listener, bounce a copy of this frame 2454 * to him. 2455 */ 2456 if (ifp->if_bpf) 2457 bpf_mtap(ifp->if_bpf, m_head); 2458 #endif 2459 } 2460 if (pkts == 0) 2461 return; 2462 2463 /* Transmit */ 2464 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); 2465 2466 /* 2467 * Set a timeout in case the chip goes out to lunch. 2468 */ 2469 ifp->if_timer = 5; 2470 } 2471 2472 /* 2473 * If we have a BCM5400 or BCM5401 PHY, we need to properly 2474 * program its internal DSP. Failing to do this can result in 2475 * massive packet loss at 1Gb speeds. 2476 */ 2477 void 2478 bge_phy_hack(sc) 2479 struct bge_softc *sc; 2480 { 2481 struct bge_bcom_hack bhack[] = { 2482 { BRGPHY_MII_AUXCTL, 0x4C20 }, 2483 { BRGPHY_MII_DSP_ADDR_REG, 0x0012 }, 2484 { BRGPHY_MII_DSP_RW_PORT, 0x1804 }, 2485 { BRGPHY_MII_DSP_ADDR_REG, 0x0013 }, 2486 { BRGPHY_MII_DSP_RW_PORT, 0x1204 }, 2487 { BRGPHY_MII_DSP_ADDR_REG, 0x8006 }, 2488 { BRGPHY_MII_DSP_RW_PORT, 0x0132 }, 2489 { BRGPHY_MII_DSP_ADDR_REG, 0x8006 }, 2490 { BRGPHY_MII_DSP_RW_PORT, 0x0232 }, 2491 { BRGPHY_MII_DSP_ADDR_REG, 0x201F }, 2492 { BRGPHY_MII_DSP_RW_PORT, 0x0A20 }, 2493 { 0, 0 } }; 2494 u_int16_t vid, did; 2495 int i; 2496 2497 vid = bge_miibus_readreg(&sc->bge_dev, 1, MII_PHYIDR1); 2498 did = bge_miibus_readreg(&sc->bge_dev, 1, MII_PHYIDR2); 2499 2500 if (MII_OUI(vid, did) == MII_OUI_BROADCOM && 2501 (MII_MODEL(did) == MII_MODEL_BROADCOM_BCM5400 || 2502 MII_MODEL(did) == MII_MODEL_BROADCOM_BCM5401)) { 2503 i = 0; 2504 while (bhack[i].reg) { 2505 bge_miibus_writereg(&sc->bge_dev, 1, bhack[i].reg, 2506 bhack[i].val); 2507 i++; 2508 } 2509 } 2510 } 2511 2512 int 2513 bge_init(ifp) 2514 struct ifnet *ifp; 2515 { 2516 struct bge_softc *sc = ifp->if_softc; 2517 u_int16_t *m; 2518 int s, error; 2519 2520 s = splnet(); 2521 2522 ifp = &sc->ethercom.ec_if; 2523 2524 /* Cancel pending I/O and flush buffers. */ 2525 bge_stop(sc); 2526 bge_reset(sc); 2527 bge_chipinit(sc); 2528 2529 /* 2530 * Init the various state machines, ring 2531 * control blocks and firmware. 2532 */ 2533 error = bge_blockinit(sc); 2534 if (error != 0) { 2535 printf("%s: initialization error %d\n", sc->bge_dev.dv_xname, 2536 error); 2537 splx(s); 2538 return error; 2539 } 2540 2541 ifp = &sc->ethercom.ec_if; 2542 2543 /* Specify MTU. */ 2544 CSR_WRITE_4(sc, BGE_RX_MTU, ifp->if_mtu + 2545 ETHER_HDR_LEN + ETHER_CRC_LEN); 2546 2547 /* Load our MAC address. */ 2548 m = (u_int16_t *)&(LLADDR(ifp->if_sadl)[0]); 2549 CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0])); 2550 CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, (htons(m[1]) << 16) | htons(m[2])); 2551 2552 /* Enable or disable promiscuous mode as needed. */ 2553 if (ifp->if_flags & IFF_PROMISC) { 2554 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 2555 } else { 2556 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 2557 } 2558 2559 /* Program multicast filter. */ 2560 bge_setmulti(sc); 2561 2562 /* Init RX ring. */ 2563 bge_init_rx_ring_std(sc); 2564 2565 /* Init jumbo RX ring. */ 2566 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 2567 bge_init_rx_ring_jumbo(sc); 2568 2569 /* Init our RX return ring index */ 2570 sc->bge_rx_saved_considx = 0; 2571 2572 /* Init TX ring. */ 2573 bge_init_tx_ring(sc); 2574 2575 /* Turn on transmitter */ 2576 BGE_SETBIT(sc, BGE_TX_MODE, BGE_TXMODE_ENABLE); 2577 2578 /* Turn on receiver */ 2579 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE); 2580 2581 /* Tell firmware we're alive. */ 2582 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 2583 2584 /* Enable host interrupts. */ 2585 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA); 2586 BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); 2587 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 0); 2588 2589 bge_ifmedia_upd(ifp); 2590 2591 ifp->if_flags |= IFF_RUNNING; 2592 ifp->if_flags &= ~IFF_OACTIVE; 2593 2594 splx(s); 2595 2596 callout_reset(&sc->bge_timeout, hz, bge_tick, sc); 2597 2598 return 0; 2599 } 2600 2601 /* 2602 * Set media options. 2603 */ 2604 int 2605 bge_ifmedia_upd(ifp) 2606 struct ifnet *ifp; 2607 { 2608 struct bge_softc *sc = ifp->if_softc; 2609 struct mii_data *mii = &sc->bge_mii; 2610 struct ifmedia *ifm = &sc->bge_ifmedia; 2611 2612 /* If this is a 1000baseX NIC, enable the TBI port. */ 2613 if (sc->bge_tbi) { 2614 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 2615 return(EINVAL); 2616 switch(IFM_SUBTYPE(ifm->ifm_media)) { 2617 case IFM_AUTO: 2618 break; 2619 case IFM_1000_SX: 2620 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 2621 BGE_CLRBIT(sc, BGE_MAC_MODE, 2622 BGE_MACMODE_HALF_DUPLEX); 2623 } else { 2624 BGE_SETBIT(sc, BGE_MAC_MODE, 2625 BGE_MACMODE_HALF_DUPLEX); 2626 } 2627 break; 2628 default: 2629 return(EINVAL); 2630 } 2631 return(0); 2632 } 2633 2634 sc->bge_link = 0; 2635 if (mii->mii_instance) { 2636 struct mii_softc *miisc; 2637 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL; 2638 miisc = LIST_NEXT(miisc, mii_list)) 2639 mii_phy_reset(miisc); 2640 } 2641 bge_phy_hack(sc); 2642 mii_mediachg(mii); 2643 2644 return(0); 2645 } 2646 2647 /* 2648 * Report current media status. 2649 */ 2650 void 2651 bge_ifmedia_sts(ifp, ifmr) 2652 struct ifnet *ifp; 2653 struct ifmediareq *ifmr; 2654 { 2655 struct bge_softc *sc = ifp->if_softc; 2656 struct mii_data *mii = &sc->bge_mii; 2657 2658 if (sc->bge_tbi) { 2659 ifmr->ifm_status = IFM_AVALID; 2660 ifmr->ifm_active = IFM_ETHER; 2661 if (CSR_READ_4(sc, BGE_MAC_STS) & 2662 BGE_MACSTAT_TBI_PCS_SYNCHED) 2663 ifmr->ifm_status |= IFM_ACTIVE; 2664 ifmr->ifm_active |= IFM_1000_SX; 2665 if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX) 2666 ifmr->ifm_active |= IFM_HDX; 2667 else 2668 ifmr->ifm_active |= IFM_FDX; 2669 return; 2670 } 2671 2672 mii_pollstat(mii); 2673 ifmr->ifm_active = mii->mii_media_active; 2674 ifmr->ifm_status = mii->mii_media_status; 2675 } 2676 2677 int 2678 bge_ioctl(ifp, command, data) 2679 struct ifnet *ifp; 2680 u_long command; 2681 caddr_t data; 2682 { 2683 struct bge_softc *sc = ifp->if_softc; 2684 struct ifreq *ifr = (struct ifreq *) data; 2685 int s, error = 0; 2686 struct mii_data *mii; 2687 2688 s = splnet(); 2689 2690 switch(command) { 2691 case SIOCSIFFLAGS: 2692 if (ifp->if_flags & IFF_UP) { 2693 /* 2694 * If only the state of the PROMISC flag changed, 2695 * then just use the 'set promisc mode' command 2696 * instead of reinitializing the entire NIC. Doing 2697 * a full re-init means reloading the firmware and 2698 * waiting for it to start up, which may take a 2699 * second or two. 2700 */ 2701 if (ifp->if_flags & IFF_RUNNING && 2702 ifp->if_flags & IFF_PROMISC && 2703 !(sc->bge_if_flags & IFF_PROMISC)) { 2704 BGE_SETBIT(sc, BGE_RX_MODE, 2705 BGE_RXMODE_RX_PROMISC); 2706 } else if (ifp->if_flags & IFF_RUNNING && 2707 !(ifp->if_flags & IFF_PROMISC) && 2708 sc->bge_if_flags & IFF_PROMISC) { 2709 BGE_CLRBIT(sc, BGE_RX_MODE, 2710 BGE_RXMODE_RX_PROMISC); 2711 } else 2712 bge_init(ifp); 2713 } else { 2714 if (ifp->if_flags & IFF_RUNNING) { 2715 bge_stop(sc); 2716 } 2717 } 2718 sc->bge_if_flags = ifp->if_flags; 2719 error = 0; 2720 break; 2721 case SIOCSIFMEDIA: 2722 case SIOCGIFMEDIA: 2723 if (sc->bge_tbi) { 2724 error = ifmedia_ioctl(ifp, ifr, &sc->bge_ifmedia, 2725 command); 2726 } else { 2727 mii = &sc->bge_mii; 2728 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, 2729 command); 2730 } 2731 error = 0; 2732 break; 2733 default: 2734 error = ether_ioctl(ifp, command, data); 2735 if (error == ENETRESET) { 2736 bge_setmulti(sc); 2737 error = 0; 2738 } 2739 break; 2740 } 2741 2742 splx(s); 2743 2744 return(error); 2745 } 2746 2747 void 2748 bge_watchdog(ifp) 2749 struct ifnet *ifp; 2750 { 2751 struct bge_softc *sc; 2752 2753 sc = ifp->if_softc; 2754 2755 printf("%s: watchdog timeout -- resetting\n", sc->bge_dev.dv_xname); 2756 2757 ifp->if_flags &= ~IFF_RUNNING; 2758 bge_init(ifp); 2759 2760 ifp->if_oerrors++; 2761 } 2762 2763 /* 2764 * Stop the adapter and free any mbufs allocated to the 2765 * RX and TX lists. 2766 */ 2767 void 2768 bge_stop(sc) 2769 struct bge_softc *sc; 2770 { 2771 struct ifnet *ifp = &sc->ethercom.ec_if; 2772 2773 callout_stop(&sc->bge_timeout); 2774 2775 /* 2776 * Disable all of the receiver blocks 2777 */ 2778 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE); 2779 BGE_CLRBIT(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 2780 BGE_CLRBIT(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 2781 BGE_CLRBIT(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 2782 BGE_CLRBIT(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE); 2783 BGE_CLRBIT(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 2784 BGE_CLRBIT(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE); 2785 2786 /* 2787 * Disable all of the transmit blocks 2788 */ 2789 BGE_CLRBIT(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 2790 BGE_CLRBIT(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 2791 BGE_CLRBIT(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 2792 BGE_CLRBIT(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE); 2793 BGE_CLRBIT(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE); 2794 BGE_CLRBIT(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 2795 BGE_CLRBIT(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 2796 2797 /* 2798 * Shut down all of the memory managers and related 2799 * state machines. 2800 */ 2801 BGE_CLRBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE); 2802 BGE_CLRBIT(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE); 2803 BGE_CLRBIT(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 2804 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 2805 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 2806 BGE_CLRBIT(sc, BGE_BMAN_MODE, BGE_BMANMODE_ENABLE); 2807 BGE_CLRBIT(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 2808 2809 /* Disable host interrupts. */ 2810 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); 2811 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 1); 2812 2813 /* 2814 * Tell firmware we're shutting down. 2815 */ 2816 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 2817 2818 /* Free the RX lists. */ 2819 bge_free_rx_ring_std(sc); 2820 2821 /* Free jumbo RX list. */ 2822 bge_free_rx_ring_jumbo(sc); 2823 2824 /* Free TX buffers. */ 2825 bge_free_tx_ring(sc); 2826 2827 /* 2828 * Isolate/power down the PHY. 2829 */ 2830 if (!sc->bge_tbi) 2831 mii_down(&sc->bge_mii); 2832 2833 sc->bge_link = 0; 2834 2835 sc->bge_tx_saved_considx = BGE_TXCONS_UNSET; 2836 2837 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2838 } 2839 2840 /* 2841 * Stop all chip I/O so that the kernel's probe routines don't 2842 * get confused by errant DMAs when rebooting. 2843 */ 2844 void 2845 bge_shutdown(xsc) 2846 void *xsc; 2847 { 2848 struct bge_softc *sc = (struct bge_softc *)xsc; 2849 2850 bge_stop(sc); 2851 bge_reset(sc); 2852 } 2853
Indexes created Mon Sep 22 10:09:38 GMT 2025