if_bge.c revision 1.200
1 /* $NetBSD: if_bge.c,v 1.200 2012/02/02 19:43:05 tls Exp $ */ 2 3 /* 4 * Copyright (c) 2001 Wind River Systems 5 * Copyright (c) 1997, 1998, 1999, 2001 6 * Bill Paul <wpaul (at) windriver.com>. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Bill Paul. 19 * 4. Neither the name of the author nor the names of any co-contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 33 * THE POSSIBILITY OF SUCH DAMAGE. 34 * 35 * $FreeBSD: if_bge.c,v 1.13 2002/04/04 06:01:31 wpaul Exp $ 36 */ 37 38 /* 39 * Broadcom BCM570x family gigabit ethernet driver for NetBSD. 40 * 41 * NetBSD version by: 42 * 43 * Frank van der Linden <fvdl (at) wasabisystems.com> 44 * Jason Thorpe <thorpej (at) wasabisystems.com> 45 * Jonathan Stone <jonathan (at) dsg.stanford.edu> 46 * 47 * Originally written for FreeBSD by Bill Paul <wpaul (at) windriver.com> 48 * Senior Engineer, Wind River Systems 49 */ 50 51 /* 52 * The Broadcom BCM5700 is based on technology originally developed by 53 * Alteon Networks as part of the Tigon I and Tigon II gigabit ethernet 54 * MAC chips. The BCM5700, sometimes refered to as the Tigon III, has 55 * two on-board MIPS R4000 CPUs and can have as much as 16MB of external 56 * SSRAM. The BCM5700 supports TCP, UDP and IP checksum offload, jumbo 57 * frames, highly configurable RX filtering, and 16 RX and TX queues 58 * (which, along with RX filter rules, can be used for QOS applications). 59 * Other features, such as TCP segmentation, may be available as part 60 * of value-added firmware updates. Unlike the Tigon I and Tigon II, 61 * firmware images can be stored in hardware and need not be compiled 62 * into the driver. 63 * 64 * The BCM5700 supports the PCI v2.2 and PCI-X v1.0 standards, and will 65 * function in a 32-bit/64-bit 33/66MHz bus, or a 64-bit/133MHz bus. 66 * 67 * The BCM5701 is a single-chip solution incorporating both the BCM5700 68 * MAC and a BCM5401 10/100/1000 PHY. Unlike the BCM5700, the BCM5701 69 * does not support external SSRAM. 70 * 71 * Broadcom also produces a variation of the BCM5700 under the "Altima" 72 * brand name, which is functionally similar but lacks PCI-X support. 73 * 74 * Without external SSRAM, you can only have at most 4 TX rings, 75 * and the use of the mini RX ring is disabled. This seems to imply 76 * that these features are simply not available on the BCM5701. As a 77 * result, this driver does not implement any support for the mini RX 78 * ring. 79 */ 80 81 #include <sys/cdefs.h> 82 __KERNEL_RCSID(0, "$NetBSD: if_bge.c,v 1.200 2012/02/02 19:43:05 tls Exp $"); 83 84 #include "vlan.h" 85 86 #include <sys/param.h> 87 #include <sys/systm.h> 88 #include <sys/callout.h> 89 #include <sys/sockio.h> 90 #include <sys/mbuf.h> 91 #include <sys/malloc.h> 92 #include <sys/kernel.h> 93 #include <sys/device.h> 94 #include <sys/socket.h> 95 #include <sys/sysctl.h> 96 97 #include <net/if.h> 98 #include <net/if_dl.h> 99 #include <net/if_media.h> 100 #include <net/if_ether.h> 101 102 #include <sys/rnd.h> 103 104 #ifdef INET 105 #include <netinet/in.h> 106 #include <netinet/in_systm.h> 107 #include <netinet/in_var.h> 108 #include <netinet/ip.h> 109 #endif 110 111 /* Headers for TCP Segmentation Offload (TSO) */ 112 #include <netinet/in_systm.h> /* n_time for <netinet/ip.h>... */ 113 #include <netinet/in.h> /* ip_{src,dst}, for <netinet/ip.h> */ 114 #include <netinet/ip.h> /* for struct ip */ 115 #include <netinet/tcp.h> /* for struct tcphdr */ 116 117 118 #include <net/bpf.h> 119 120 #include <dev/pci/pcireg.h> 121 #include <dev/pci/pcivar.h> 122 #include <dev/pci/pcidevs.h> 123 124 #include <dev/mii/mii.h> 125 #include <dev/mii/miivar.h> 126 #include <dev/mii/miidevs.h> 127 #include <dev/mii/brgphyreg.h> 128 129 #include <dev/pci/if_bgereg.h> 130 #include <dev/pci/if_bgevar.h> 131 132 #include <prop/proplib.h> 133 134 #define ETHER_MIN_NOPAD (ETHER_MIN_LEN - ETHER_CRC_LEN) /* i.e., 60 */ 135 136 137 /* 138 * Tunable thresholds for rx-side bge interrupt mitigation. 139 */ 140 141 /* 142 * The pairs of values below were obtained from empirical measurement 143 * on bcm5700 rev B2; they ar designed to give roughly 1 receive 144 * interrupt for every N packets received, where N is, approximately, 145 * the second value (rx_max_bds) in each pair. The values are chosen 146 * such that moving from one pair to the succeeding pair was observed 147 * to roughly halve interrupt rate under sustained input packet load. 148 * The values were empirically chosen to avoid overflowing internal 149 * limits on the bcm5700: increasing rx_ticks much beyond 600 150 * results in internal wrapping and higher interrupt rates. 151 * The limit of 46 frames was chosen to match NFS workloads. 152 * 153 * These values also work well on bcm5701, bcm5704C, and (less 154 * tested) bcm5703. On other chipsets, (including the Altima chip 155 * family), the larger values may overflow internal chip limits, 156 * leading to increasing interrupt rates rather than lower interrupt 157 * rates. 158 * 159 * Applications using heavy interrupt mitigation (interrupting every 160 * 32 or 46 frames) in both directions may need to increase the TCP 161 * windowsize to above 131072 bytes (e.g., to 199608 bytes) to sustain 162 * full link bandwidth, due to ACKs and window updates lingering 163 * in the RX queue during the 30-to-40-frame interrupt-mitigation window. 164 */ 165 static const struct bge_load_rx_thresh { 166 int rx_ticks; 167 int rx_max_bds; } 168 bge_rx_threshes[] = { 169 { 16, 1 }, /* rx_max_bds = 1 disables interrupt mitigation */ 170 { 32, 2 }, 171 { 50, 4 }, 172 { 100, 8 }, 173 { 192, 16 }, 174 { 416, 32 }, 175 { 598, 46 } 176 }; 177 #define NBGE_RX_THRESH (sizeof(bge_rx_threshes) / sizeof(bge_rx_threshes[0])) 178 179 /* XXX patchable; should be sysctl'able */ 180 static int bge_auto_thresh = 1; 181 static int bge_rx_thresh_lvl; 182 183 static int bge_rxthresh_nodenum; 184 185 typedef int (*bge_eaddr_fcn_t)(struct bge_softc *, uint8_t[]); 186 187 static int bge_probe(device_t, cfdata_t, void *); 188 static void bge_attach(device_t, device_t, void *); 189 static void bge_release_resources(struct bge_softc *); 190 191 static int bge_get_eaddr_fw(struct bge_softc *, uint8_t[]); 192 static int bge_get_eaddr_mem(struct bge_softc *, uint8_t[]); 193 static int bge_get_eaddr_nvram(struct bge_softc *, uint8_t[]); 194 static int bge_get_eaddr_eeprom(struct bge_softc *, uint8_t[]); 195 static int bge_get_eaddr(struct bge_softc *, uint8_t[]); 196 197 static void bge_txeof(struct bge_softc *); 198 static void bge_rxeof(struct bge_softc *); 199 200 static void bge_asf_driver_up (struct bge_softc *); 201 static void bge_tick(void *); 202 static void bge_stats_update(struct bge_softc *); 203 static void bge_stats_update_regs(struct bge_softc *); 204 static int bge_encap(struct bge_softc *, struct mbuf *, uint32_t *); 205 206 static int bge_intr(void *); 207 static void bge_start(struct ifnet *); 208 static int bge_ifflags_cb(struct ethercom *); 209 static int bge_ioctl(struct ifnet *, u_long, void *); 210 static int bge_init(struct ifnet *); 211 static void bge_stop(struct ifnet *, int); 212 static void bge_watchdog(struct ifnet *); 213 static int bge_ifmedia_upd(struct ifnet *); 214 static void bge_ifmedia_sts(struct ifnet *, struct ifmediareq *); 215 216 static uint8_t bge_nvram_getbyte(struct bge_softc *, int, uint8_t *); 217 static int bge_read_nvram(struct bge_softc *, uint8_t *, int, int); 218 219 static uint8_t bge_eeprom_getbyte(struct bge_softc *, int, uint8_t *); 220 static int bge_read_eeprom(struct bge_softc *, void *, int, int); 221 static void bge_setmulti(struct bge_softc *); 222 223 static void bge_handle_events(struct bge_softc *); 224 static int bge_alloc_jumbo_mem(struct bge_softc *); 225 #if 0 /* XXX */ 226 static void bge_free_jumbo_mem(struct bge_softc *); 227 #endif 228 static void *bge_jalloc(struct bge_softc *); 229 static void bge_jfree(struct mbuf *, void *, size_t, void *); 230 static int bge_newbuf_std(struct bge_softc *, int, struct mbuf *, 231 bus_dmamap_t); 232 static int bge_newbuf_jumbo(struct bge_softc *, int, struct mbuf *); 233 static int bge_init_rx_ring_std(struct bge_softc *); 234 static void bge_free_rx_ring_std(struct bge_softc *); 235 static int bge_init_rx_ring_jumbo(struct bge_softc *); 236 static void bge_free_rx_ring_jumbo(struct bge_softc *); 237 static void bge_free_tx_ring(struct bge_softc *); 238 static int bge_init_tx_ring(struct bge_softc *); 239 240 static int bge_chipinit(struct bge_softc *); 241 static int bge_blockinit(struct bge_softc *); 242 static int bge_setpowerstate(struct bge_softc *, int); 243 static uint32_t bge_readmem_ind(struct bge_softc *, int); 244 static void bge_writemem_ind(struct bge_softc *, int, int); 245 static void bge_writembx(struct bge_softc *, int, int); 246 static void bge_writemem_direct(struct bge_softc *, int, int); 247 static void bge_writereg_ind(struct bge_softc *, int, int); 248 static void bge_set_max_readrq(struct bge_softc *); 249 250 static int bge_miibus_readreg(device_t, int, int); 251 static void bge_miibus_writereg(device_t, int, int, int); 252 static void bge_miibus_statchg(device_t); 253 254 #define BGE_RESET_START 1 255 #define BGE_RESET_STOP 2 256 static void bge_sig_post_reset(struct bge_softc *, int); 257 static void bge_sig_legacy(struct bge_softc *, int); 258 static void bge_sig_pre_reset(struct bge_softc *, int); 259 static void bge_stop_fw(struct bge_softc *); 260 static int bge_reset(struct bge_softc *); 261 static void bge_link_upd(struct bge_softc *); 262 static void sysctl_bge_init(struct bge_softc *); 263 static int sysctl_bge_verify(SYSCTLFN_PROTO); 264 265 #ifdef BGE_DEBUG 266 #define DPRINTF(x) if (bgedebug) printf x 267 #define DPRINTFN(n,x) if (bgedebug >= (n)) printf x 268 #define BGE_TSO_PRINTF(x) do { if (bge_tso_debug) printf x ;} while (0) 269 int bgedebug = 0; 270 int bge_tso_debug = 0; 271 void bge_debug_info(struct bge_softc *); 272 #else 273 #define DPRINTF(x) 274 #define DPRINTFN(n,x) 275 #define BGE_TSO_PRINTF(x) 276 #endif 277 278 #ifdef BGE_EVENT_COUNTERS 279 #define BGE_EVCNT_INCR(ev) (ev).ev_count++ 280 #define BGE_EVCNT_ADD(ev, val) (ev).ev_count += (val) 281 #define BGE_EVCNT_UPD(ev, val) (ev).ev_count = (val) 282 #else 283 #define BGE_EVCNT_INCR(ev) /* nothing */ 284 #define BGE_EVCNT_ADD(ev, val) /* nothing */ 285 #define BGE_EVCNT_UPD(ev, val) /* nothing */ 286 #endif 287 288 static const struct bge_product { 289 pci_vendor_id_t bp_vendor; 290 pci_product_id_t bp_product; 291 const char *bp_name; 292 } bge_products[] = { 293 /* 294 * The BCM5700 documentation seems to indicate that the hardware 295 * still has the Alteon vendor ID burned into it, though it 296 * should always be overridden by the value in the EEPROM. We'll 297 * check for it anyway. 298 */ 299 { PCI_VENDOR_ALTEON, 300 PCI_PRODUCT_ALTEON_BCM5700, 301 "Broadcom BCM5700 Gigabit Ethernet", 302 }, 303 { PCI_VENDOR_ALTEON, 304 PCI_PRODUCT_ALTEON_BCM5701, 305 "Broadcom BCM5701 Gigabit Ethernet", 306 }, 307 { PCI_VENDOR_ALTIMA, 308 PCI_PRODUCT_ALTIMA_AC1000, 309 "Altima AC1000 Gigabit Ethernet", 310 }, 311 { PCI_VENDOR_ALTIMA, 312 PCI_PRODUCT_ALTIMA_AC1001, 313 "Altima AC1001 Gigabit Ethernet", 314 }, 315 { PCI_VENDOR_ALTIMA, 316 PCI_PRODUCT_ALTIMA_AC9100, 317 "Altima AC9100 Gigabit Ethernet", 318 }, 319 { PCI_VENDOR_BROADCOM, 320 PCI_PRODUCT_BROADCOM_BCM5700, 321 "Broadcom BCM5700 Gigabit Ethernet", 322 }, 323 { PCI_VENDOR_BROADCOM, 324 PCI_PRODUCT_BROADCOM_BCM5701, 325 "Broadcom BCM5701 Gigabit Ethernet", 326 }, 327 { PCI_VENDOR_BROADCOM, 328 PCI_PRODUCT_BROADCOM_BCM5702, 329 "Broadcom BCM5702 Gigabit Ethernet", 330 }, 331 { PCI_VENDOR_BROADCOM, 332 PCI_PRODUCT_BROADCOM_BCM5702X, 333 "Broadcom BCM5702X Gigabit Ethernet" }, 334 { PCI_VENDOR_BROADCOM, 335 PCI_PRODUCT_BROADCOM_BCM5703, 336 "Broadcom BCM5703 Gigabit Ethernet", 337 }, 338 { PCI_VENDOR_BROADCOM, 339 PCI_PRODUCT_BROADCOM_BCM5703X, 340 "Broadcom BCM5703X Gigabit Ethernet", 341 }, 342 { PCI_VENDOR_BROADCOM, 343 PCI_PRODUCT_BROADCOM_BCM5703_ALT, 344 "Broadcom BCM5703 Gigabit Ethernet", 345 }, 346 { PCI_VENDOR_BROADCOM, 347 PCI_PRODUCT_BROADCOM_BCM5704C, 348 "Broadcom BCM5704C Dual Gigabit Ethernet", 349 }, 350 { PCI_VENDOR_BROADCOM, 351 PCI_PRODUCT_BROADCOM_BCM5704S, 352 "Broadcom BCM5704S Dual Gigabit Ethernet", 353 }, 354 { PCI_VENDOR_BROADCOM, 355 PCI_PRODUCT_BROADCOM_BCM5705, 356 "Broadcom BCM5705 Gigabit Ethernet", 357 }, 358 { PCI_VENDOR_BROADCOM, 359 PCI_PRODUCT_BROADCOM_BCM5705F, 360 "Broadcom BCM5705F Gigabit Ethernet", 361 }, 362 { PCI_VENDOR_BROADCOM, 363 PCI_PRODUCT_BROADCOM_BCM5705K, 364 "Broadcom BCM5705K Gigabit Ethernet", 365 }, 366 { PCI_VENDOR_BROADCOM, 367 PCI_PRODUCT_BROADCOM_BCM5705M, 368 "Broadcom BCM5705M Gigabit Ethernet", 369 }, 370 { PCI_VENDOR_BROADCOM, 371 PCI_PRODUCT_BROADCOM_BCM5705M_ALT, 372 "Broadcom BCM5705M Gigabit Ethernet", 373 }, 374 { PCI_VENDOR_BROADCOM, 375 PCI_PRODUCT_BROADCOM_BCM5714, 376 "Broadcom BCM5714 Gigabit Ethernet", 377 }, 378 { PCI_VENDOR_BROADCOM, 379 PCI_PRODUCT_BROADCOM_BCM5714S, 380 "Broadcom BCM5714S Gigabit Ethernet", 381 }, 382 { PCI_VENDOR_BROADCOM, 383 PCI_PRODUCT_BROADCOM_BCM5715, 384 "Broadcom BCM5715 Gigabit Ethernet", 385 }, 386 { PCI_VENDOR_BROADCOM, 387 PCI_PRODUCT_BROADCOM_BCM5715S, 388 "Broadcom BCM5715S Gigabit Ethernet", 389 }, 390 { PCI_VENDOR_BROADCOM, 391 PCI_PRODUCT_BROADCOM_BCM5717, 392 "Broadcom BCM5717 Gigabit Ethernet", 393 }, 394 { PCI_VENDOR_BROADCOM, 395 PCI_PRODUCT_BROADCOM_BCM5718, 396 "Broadcom BCM5718 Gigabit Ethernet", 397 }, 398 { PCI_VENDOR_BROADCOM, 399 PCI_PRODUCT_BROADCOM_BCM5720, 400 "Broadcom BCM5720 Gigabit Ethernet", 401 }, 402 { PCI_VENDOR_BROADCOM, 403 PCI_PRODUCT_BROADCOM_BCM5721, 404 "Broadcom BCM5721 Gigabit Ethernet", 405 }, 406 { PCI_VENDOR_BROADCOM, 407 PCI_PRODUCT_BROADCOM_BCM5722, 408 "Broadcom BCM5722 Gigabit Ethernet", 409 }, 410 { PCI_VENDOR_BROADCOM, 411 PCI_PRODUCT_BROADCOM_BCM5723, 412 "Broadcom BCM5723 Gigabit Ethernet", 413 }, 414 { PCI_VENDOR_BROADCOM, 415 PCI_PRODUCT_BROADCOM_BCM5724, 416 "Broadcom BCM5724 Gigabit Ethernet", 417 }, 418 { PCI_VENDOR_BROADCOM, 419 PCI_PRODUCT_BROADCOM_BCM5750, 420 "Broadcom BCM5750 Gigabit Ethernet", 421 }, 422 { PCI_VENDOR_BROADCOM, 423 PCI_PRODUCT_BROADCOM_BCM5750M, 424 "Broadcom BCM5750M Gigabit Ethernet", 425 }, 426 { PCI_VENDOR_BROADCOM, 427 PCI_PRODUCT_BROADCOM_BCM5751, 428 "Broadcom BCM5751 Gigabit Ethernet", 429 }, 430 { PCI_VENDOR_BROADCOM, 431 PCI_PRODUCT_BROADCOM_BCM5751F, 432 "Broadcom BCM5751F Gigabit Ethernet", 433 }, 434 { PCI_VENDOR_BROADCOM, 435 PCI_PRODUCT_BROADCOM_BCM5751M, 436 "Broadcom BCM5751M Gigabit Ethernet", 437 }, 438 { PCI_VENDOR_BROADCOM, 439 PCI_PRODUCT_BROADCOM_BCM5752, 440 "Broadcom BCM5752 Gigabit Ethernet", 441 }, 442 { PCI_VENDOR_BROADCOM, 443 PCI_PRODUCT_BROADCOM_BCM5752M, 444 "Broadcom BCM5752M Gigabit Ethernet", 445 }, 446 { PCI_VENDOR_BROADCOM, 447 PCI_PRODUCT_BROADCOM_BCM5753, 448 "Broadcom BCM5753 Gigabit Ethernet", 449 }, 450 { PCI_VENDOR_BROADCOM, 451 PCI_PRODUCT_BROADCOM_BCM5753F, 452 "Broadcom BCM5753F Gigabit Ethernet", 453 }, 454 { PCI_VENDOR_BROADCOM, 455 PCI_PRODUCT_BROADCOM_BCM5753M, 456 "Broadcom BCM5753M Gigabit Ethernet", 457 }, 458 { PCI_VENDOR_BROADCOM, 459 PCI_PRODUCT_BROADCOM_BCM5754, 460 "Broadcom BCM5754 Gigabit Ethernet", 461 }, 462 { PCI_VENDOR_BROADCOM, 463 PCI_PRODUCT_BROADCOM_BCM5754M, 464 "Broadcom BCM5754M Gigabit Ethernet", 465 }, 466 { PCI_VENDOR_BROADCOM, 467 PCI_PRODUCT_BROADCOM_BCM5755, 468 "Broadcom BCM5755 Gigabit Ethernet", 469 }, 470 { PCI_VENDOR_BROADCOM, 471 PCI_PRODUCT_BROADCOM_BCM5755M, 472 "Broadcom BCM5755M Gigabit Ethernet", 473 }, 474 { PCI_VENDOR_BROADCOM, 475 PCI_PRODUCT_BROADCOM_BCM5756, 476 "Broadcom BCM5756 Gigabit Ethernet", 477 }, 478 { PCI_VENDOR_BROADCOM, 479 PCI_PRODUCT_BROADCOM_BCM5761, 480 "Broadcom BCM5761 Gigabit Ethernet", 481 }, 482 { PCI_VENDOR_BROADCOM, 483 PCI_PRODUCT_BROADCOM_BCM5761E, 484 "Broadcom BCM5761E Gigabit Ethernet", 485 }, 486 { PCI_VENDOR_BROADCOM, 487 PCI_PRODUCT_BROADCOM_BCM5761S, 488 "Broadcom BCM5761S Gigabit Ethernet", 489 }, 490 { PCI_VENDOR_BROADCOM, 491 PCI_PRODUCT_BROADCOM_BCM5761SE, 492 "Broadcom BCM5761SE Gigabit Ethernet", 493 }, 494 { PCI_VENDOR_BROADCOM, 495 PCI_PRODUCT_BROADCOM_BCM5764, 496 "Broadcom BCM5764 Gigabit Ethernet", 497 }, 498 { PCI_VENDOR_BROADCOM, 499 PCI_PRODUCT_BROADCOM_BCM5780, 500 "Broadcom BCM5780 Gigabit Ethernet", 501 }, 502 { PCI_VENDOR_BROADCOM, 503 PCI_PRODUCT_BROADCOM_BCM5780S, 504 "Broadcom BCM5780S Gigabit Ethernet", 505 }, 506 { PCI_VENDOR_BROADCOM, 507 PCI_PRODUCT_BROADCOM_BCM5781, 508 "Broadcom BCM5781 Gigabit Ethernet", 509 }, 510 { PCI_VENDOR_BROADCOM, 511 PCI_PRODUCT_BROADCOM_BCM5782, 512 "Broadcom BCM5782 Gigabit Ethernet", 513 }, 514 { PCI_VENDOR_BROADCOM, 515 PCI_PRODUCT_BROADCOM_BCM5784M, 516 "BCM5784M NetLink 1000baseT Ethernet", 517 }, 518 { PCI_VENDOR_BROADCOM, 519 PCI_PRODUCT_BROADCOM_BCM5786, 520 "Broadcom BCM5786 Gigabit Ethernet", 521 }, 522 { PCI_VENDOR_BROADCOM, 523 PCI_PRODUCT_BROADCOM_BCM5787, 524 "Broadcom BCM5787 Gigabit Ethernet", 525 }, 526 { PCI_VENDOR_BROADCOM, 527 PCI_PRODUCT_BROADCOM_BCM5787M, 528 "Broadcom BCM5787M Gigabit Ethernet", 529 }, 530 { PCI_VENDOR_BROADCOM, 531 PCI_PRODUCT_BROADCOM_BCM5788, 532 "Broadcom BCM5788 Gigabit Ethernet", 533 }, 534 { PCI_VENDOR_BROADCOM, 535 PCI_PRODUCT_BROADCOM_BCM5789, 536 "Broadcom BCM5789 Gigabit Ethernet", 537 }, 538 { PCI_VENDOR_BROADCOM, 539 PCI_PRODUCT_BROADCOM_BCM5901, 540 "Broadcom BCM5901 Fast Ethernet", 541 }, 542 { PCI_VENDOR_BROADCOM, 543 PCI_PRODUCT_BROADCOM_BCM5901A2, 544 "Broadcom BCM5901A2 Fast Ethernet", 545 }, 546 { PCI_VENDOR_BROADCOM, 547 PCI_PRODUCT_BROADCOM_BCM5903M, 548 "Broadcom BCM5903M Fast Ethernet", 549 }, 550 { PCI_VENDOR_BROADCOM, 551 PCI_PRODUCT_BROADCOM_BCM5906, 552 "Broadcom BCM5906 Fast Ethernet", 553 }, 554 { PCI_VENDOR_BROADCOM, 555 PCI_PRODUCT_BROADCOM_BCM5906M, 556 "Broadcom BCM5906M Fast Ethernet", 557 }, 558 { PCI_VENDOR_BROADCOM, 559 PCI_PRODUCT_BROADCOM_BCM57760, 560 "Broadcom BCM57760 Fast Ethernet", 561 }, 562 { PCI_VENDOR_BROADCOM, 563 PCI_PRODUCT_BROADCOM_BCM57761, 564 "Broadcom BCM57761 Fast Ethernet", 565 }, 566 { PCI_VENDOR_BROADCOM, 567 PCI_PRODUCT_BROADCOM_BCM57765, 568 "Broadcom BCM57765 Fast Ethernet", 569 }, 570 { PCI_VENDOR_BROADCOM, 571 PCI_PRODUCT_BROADCOM_BCM57780, 572 "Broadcom BCM57780 Fast Ethernet", 573 }, 574 { PCI_VENDOR_BROADCOM, 575 PCI_PRODUCT_BROADCOM_BCM57781, 576 "Broadcom BCM57781 Fast Ethernet", 577 }, 578 { PCI_VENDOR_BROADCOM, 579 PCI_PRODUCT_BROADCOM_BCM57785, 580 "Broadcom BCM57785 Fast Ethernet", 581 }, 582 { PCI_VENDOR_BROADCOM, 583 PCI_PRODUCT_BROADCOM_BCM57788, 584 "Broadcom BCM57788 Fast Ethernet", 585 }, 586 { PCI_VENDOR_BROADCOM, 587 PCI_PRODUCT_BROADCOM_BCM57790, 588 "Broadcom BCM57790 Fast Ethernet", 589 }, 590 { PCI_VENDOR_BROADCOM, 591 PCI_PRODUCT_BROADCOM_BCM57791, 592 "Broadcom BCM57791 Fast Ethernet", 593 }, 594 { PCI_VENDOR_BROADCOM, 595 PCI_PRODUCT_BROADCOM_BCM57795, 596 "Broadcom BCM57795 Fast Ethernet", 597 }, 598 { PCI_VENDOR_SCHNEIDERKOCH, 599 PCI_PRODUCT_SCHNEIDERKOCH_SK_9DX1, 600 "SysKonnect SK-9Dx1 Gigabit Ethernet", 601 }, 602 { PCI_VENDOR_3COM, 603 PCI_PRODUCT_3COM_3C996, 604 "3Com 3c996 Gigabit Ethernet", 605 }, 606 { PCI_VENDOR_FUJITSU4, 607 PCI_PRODUCT_FUJITSU4_PW008GE4, 608 "Fujitsu PW008GE4 Gigabit Ethernet", 609 }, 610 { PCI_VENDOR_FUJITSU4, 611 PCI_PRODUCT_FUJITSU4_PW008GE5, 612 "Fujitsu PW008GE5 Gigabit Ethernet", 613 }, 614 { PCI_VENDOR_FUJITSU4, 615 PCI_PRODUCT_FUJITSU4_PP250_450_LAN, 616 "Fujitsu Primepower 250/450 Gigabit Ethernet", 617 }, 618 { 0, 619 0, 620 NULL }, 621 }; 622 623 /* 624 * XXX: how to handle variants based on 5750 and derivatives: 625 * 5750 5751, 5721, possibly 5714, 5752, and 5708?, which 626 * in general behave like a 5705, except with additional quirks. 627 * This driver's current handling of the 5721 is wrong; 628 * how we map ASIC revision to "quirks" needs more thought. 629 * (defined here until the thought is done). 630 */ 631 #define BGE_IS_5700_FAMILY(sc) ((sc)->bge_flags & BGE_5700_FAMILY) 632 #define BGE_IS_5714_FAMILY(sc) ((sc)->bge_flags & BGE_5714_FAMILY) 633 #define BGE_IS_5705_PLUS(sc) ((sc)->bge_flags & BGE_5705_PLUS) 634 #define BGE_IS_5750_OR_BEYOND(sc) ((sc)->bge_flags & BGE_5750_PLUS) 635 #define BGE_IS_5755_PLUS(sc) ((sc)->bge_flags & BGE_5755_PLUS) 636 #define BGE_IS_JUMBO_CAPABLE(sc) ((sc)->bge_flags & BGE_JUMBO_CAPABLE) 637 638 static const struct bge_revision { 639 uint32_t br_chipid; 640 const char *br_name; 641 } bge_revisions[] = { 642 { BGE_CHIPID_BCM5700_A0, "BCM5700 A0" }, 643 { BGE_CHIPID_BCM5700_A1, "BCM5700 A1" }, 644 { BGE_CHIPID_BCM5700_B0, "BCM5700 B0" }, 645 { BGE_CHIPID_BCM5700_B1, "BCM5700 B1" }, 646 { BGE_CHIPID_BCM5700_B2, "BCM5700 B2" }, 647 { BGE_CHIPID_BCM5700_B3, "BCM5700 B3" }, 648 /* This is treated like a BCM5700 Bx */ 649 { BGE_CHIPID_BCM5700_ALTIMA, "BCM5700 Altima" }, 650 { BGE_CHIPID_BCM5700_C0, "BCM5700 C0" }, 651 { BGE_CHIPID_BCM5701_A0, "BCM5701 A0" }, 652 { BGE_CHIPID_BCM5701_B0, "BCM5701 B0" }, 653 { BGE_CHIPID_BCM5701_B2, "BCM5701 B2" }, 654 { BGE_CHIPID_BCM5701_B5, "BCM5701 B5" }, 655 { BGE_CHIPID_BCM5703_A0, "BCM5702/5703 A0" }, 656 { BGE_CHIPID_BCM5703_A1, "BCM5702/5703 A1" }, 657 { BGE_CHIPID_BCM5703_A2, "BCM5702/5703 A2" }, 658 { BGE_CHIPID_BCM5703_A3, "BCM5702/5703 A3" }, 659 { BGE_CHIPID_BCM5703_B0, "BCM5702/5703 B0" }, 660 { BGE_CHIPID_BCM5704_A0, "BCM5704 A0" }, 661 { BGE_CHIPID_BCM5704_A1, "BCM5704 A1" }, 662 { BGE_CHIPID_BCM5704_A2, "BCM5704 A2" }, 663 { BGE_CHIPID_BCM5704_A3, "BCM5704 A3" }, 664 { BGE_CHIPID_BCM5704_B0, "BCM5704 B0" }, 665 { BGE_CHIPID_BCM5705_A0, "BCM5705 A0" }, 666 { BGE_CHIPID_BCM5705_A1, "BCM5705 A1" }, 667 { BGE_CHIPID_BCM5705_A2, "BCM5705 A2" }, 668 { BGE_CHIPID_BCM5705_A3, "BCM5705 A3" }, 669 { BGE_CHIPID_BCM5750_A0, "BCM5750 A0" }, 670 { BGE_CHIPID_BCM5750_A1, "BCM5750 A1" }, 671 { BGE_CHIPID_BCM5750_A3, "BCM5750 A3" }, 672 { BGE_CHIPID_BCM5750_B0, "BCM5750 B0" }, 673 { BGE_CHIPID_BCM5750_B1, "BCM5750 B1" }, 674 { BGE_CHIPID_BCM5750_C0, "BCM5750 C0" }, 675 { BGE_CHIPID_BCM5750_C1, "BCM5750 C1" }, 676 { BGE_CHIPID_BCM5750_C2, "BCM5750 C2" }, 677 { BGE_CHIPID_BCM5752_A0, "BCM5752 A0" }, 678 { BGE_CHIPID_BCM5752_A1, "BCM5752 A1" }, 679 { BGE_CHIPID_BCM5752_A2, "BCM5752 A2" }, 680 { BGE_CHIPID_BCM5714_A0, "BCM5714 A0" }, 681 { BGE_CHIPID_BCM5714_B0, "BCM5714 B0" }, 682 { BGE_CHIPID_BCM5714_B3, "BCM5714 B3" }, 683 { BGE_CHIPID_BCM5715_A0, "BCM5715 A0" }, 684 { BGE_CHIPID_BCM5715_A1, "BCM5715 A1" }, 685 { BGE_CHIPID_BCM5715_A3, "BCM5715 A3" }, 686 { BGE_CHIPID_BCM5755_A0, "BCM5755 A0" }, 687 { BGE_CHIPID_BCM5755_A1, "BCM5755 A1" }, 688 { BGE_CHIPID_BCM5755_A2, "BCM5755 A2" }, 689 { BGE_CHIPID_BCM5755_C0, "BCM5755 C0" }, 690 { BGE_CHIPID_BCM5761_A0, "BCM5761 A0" }, 691 { BGE_CHIPID_BCM5761_A1, "BCM5761 A1" }, 692 { BGE_CHIPID_BCM5784_A0, "BCM5784 A0" }, 693 { BGE_CHIPID_BCM5784_A1, "BCM5784 A1" }, 694 /* 5754 and 5787 share the same ASIC ID */ 695 { BGE_CHIPID_BCM5787_A0, "BCM5754/5787 A0" }, 696 { BGE_CHIPID_BCM5787_A1, "BCM5754/5787 A1" }, 697 { BGE_CHIPID_BCM5787_A2, "BCM5754/5787 A2" }, 698 { BGE_CHIPID_BCM5906_A1, "BCM5906 A1" }, 699 { BGE_CHIPID_BCM5906_A2, "BCM5906 A2" }, 700 { BGE_CHIPID_BCM57780_A0, "BCM57780 A0" }, 701 { BGE_CHIPID_BCM57780_A1, "BCM57780 A1" }, 702 703 { 0, NULL } 704 }; 705 706 /* 707 * Some defaults for major revisions, so that newer steppings 708 * that we don't know about have a shot at working. 709 */ 710 static const struct bge_revision bge_majorrevs[] = { 711 { BGE_ASICREV_BCM5700, "unknown BCM5700" }, 712 { BGE_ASICREV_BCM5701, "unknown BCM5701" }, 713 { BGE_ASICREV_BCM5703, "unknown BCM5703" }, 714 { BGE_ASICREV_BCM5704, "unknown BCM5704" }, 715 { BGE_ASICREV_BCM5705, "unknown BCM5705" }, 716 { BGE_ASICREV_BCM5750, "unknown BCM5750" }, 717 { BGE_ASICREV_BCM5714_A0, "unknown BCM5714" }, 718 { BGE_ASICREV_BCM5752, "unknown BCM5752" }, 719 { BGE_ASICREV_BCM5780, "unknown BCM5780" }, 720 { BGE_ASICREV_BCM5714, "unknown BCM5714" }, 721 { BGE_ASICREV_BCM5755, "unknown BCM5755" }, 722 { BGE_ASICREV_BCM5761, "unknown BCM5761" }, 723 { BGE_ASICREV_BCM5784, "unknown BCM5784" }, 724 { BGE_ASICREV_BCM5785, "unknown BCM5785" }, 725 /* 5754 and 5787 share the same ASIC ID */ 726 { BGE_ASICREV_BCM5787, "unknown BCM5754/5787" }, 727 { BGE_ASICREV_BCM5906, "unknown BCM5906" }, 728 { BGE_ASICREV_BCM57780, "unknown BCM57780" }, 729 { BGE_ASICREV_BCM5717, "unknown BCM5717" }, 730 { BGE_ASICREV_BCM57765, "unknown BCM57765" }, 731 732 { 0, NULL } 733 }; 734 735 static int bge_allow_asf = 1; 736 737 CFATTACH_DECL_NEW(bge, sizeof(struct bge_softc), 738 bge_probe, bge_attach, NULL, NULL); 739 740 static uint32_t 741 bge_readmem_ind(struct bge_softc *sc, int off) 742 { 743 pcireg_t val; 744 745 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_BASEADDR, off); 746 val = pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_DATA); 747 return val; 748 } 749 750 static void 751 bge_writemem_ind(struct bge_softc *sc, int off, int val) 752 { 753 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_BASEADDR, off); 754 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_DATA, val); 755 } 756 757 /* 758 * PCI Express only 759 */ 760 static void 761 bge_set_max_readrq(struct bge_softc *sc) 762 { 763 pcireg_t val; 764 765 val = pci_conf_read(sc->sc_pc, sc->sc_pcitag, sc->bge_pciecap 766 + PCI_PCIE_DCSR); 767 if ((val & PCI_PCIE_DCSR_MAX_READ_REQ) != 768 BGE_PCIE_DEVCTL_MAX_READRQ_4096) { 769 aprint_verbose_dev(sc->bge_dev, 770 "adjust device control 0x%04x ", val); 771 val &= ~PCI_PCIE_DCSR_MAX_READ_REQ; 772 val |= BGE_PCIE_DEVCTL_MAX_READRQ_4096; 773 pci_conf_write(sc->sc_pc, sc->sc_pcitag, sc->bge_pciecap 774 + PCI_PCIE_DCSR, val); 775 aprint_verbose("-> 0x%04x\n", val); 776 } 777 } 778 779 #ifdef notdef 780 static uint32_t 781 bge_readreg_ind(struct bge_softc *sc, int off) 782 { 783 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_REG_BASEADDR, off); 784 return (pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_REG_DATA)); 785 } 786 #endif 787 788 static void 789 bge_writereg_ind(struct bge_softc *sc, int off, int val) 790 { 791 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_REG_BASEADDR, off); 792 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_REG_DATA, val); 793 } 794 795 static void 796 bge_writemem_direct(struct bge_softc *sc, int off, int val) 797 { 798 CSR_WRITE_4(sc, off, val); 799 } 800 801 static void 802 bge_writembx(struct bge_softc *sc, int off, int val) 803 { 804 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 805 off += BGE_LPMBX_IRQ0_HI - BGE_MBX_IRQ0_HI; 806 807 CSR_WRITE_4(sc, off, val); 808 } 809 810 static uint8_t 811 bge_nvram_getbyte(struct bge_softc *sc, int addr, uint8_t *dest) 812 { 813 uint32_t access, byte = 0; 814 int i; 815 816 /* Lock. */ 817 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_SET1); 818 for (i = 0; i < 8000; i++) { 819 if (CSR_READ_4(sc, BGE_NVRAM_SWARB) & BGE_NVRAMSWARB_GNT1) 820 break; 821 DELAY(20); 822 } 823 if (i == 8000) 824 return 1; 825 826 /* Enable access. */ 827 access = CSR_READ_4(sc, BGE_NVRAM_ACCESS); 828 CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access | BGE_NVRAMACC_ENABLE); 829 830 CSR_WRITE_4(sc, BGE_NVRAM_ADDR, addr & 0xfffffffc); 831 CSR_WRITE_4(sc, BGE_NVRAM_CMD, BGE_NVRAM_READCMD); 832 for (i = 0; i < BGE_TIMEOUT * 10; i++) { 833 DELAY(10); 834 if (CSR_READ_4(sc, BGE_NVRAM_CMD) & BGE_NVRAMCMD_DONE) { 835 DELAY(10); 836 break; 837 } 838 } 839 840 if (i == BGE_TIMEOUT * 10) { 841 aprint_error_dev(sc->bge_dev, "nvram read timed out\n"); 842 return 1; 843 } 844 845 /* Get result. */ 846 byte = CSR_READ_4(sc, BGE_NVRAM_RDDATA); 847 848 *dest = (bswap32(byte) >> ((addr % 4) * 8)) & 0xFF; 849 850 /* Disable access. */ 851 CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access); 852 853 /* Unlock. */ 854 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_CLR1); 855 CSR_READ_4(sc, BGE_NVRAM_SWARB); 856 857 return 0; 858 } 859 860 /* 861 * Read a sequence of bytes from NVRAM. 862 */ 863 static int 864 bge_read_nvram(struct bge_softc *sc, uint8_t *dest, int off, int cnt) 865 { 866 int err = 0, i; 867 uint8_t byte = 0; 868 869 if (BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5906) 870 return 1; 871 872 for (i = 0; i < cnt; i++) { 873 err = bge_nvram_getbyte(sc, off + i, &byte); 874 if (err) 875 break; 876 *(dest + i) = byte; 877 } 878 879 return (err ? 1 : 0); 880 } 881 882 /* 883 * Read a byte of data stored in the EEPROM at address 'addr.' The 884 * BCM570x supports both the traditional bitbang interface and an 885 * auto access interface for reading the EEPROM. We use the auto 886 * access method. 887 */ 888 static uint8_t 889 bge_eeprom_getbyte(struct bge_softc *sc, int addr, uint8_t *dest) 890 { 891 int i; 892 uint32_t byte = 0; 893 894 /* 895 * Enable use of auto EEPROM access so we can avoid 896 * having to use the bitbang method. 897 */ 898 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM); 899 900 /* Reset the EEPROM, load the clock period. */ 901 CSR_WRITE_4(sc, BGE_EE_ADDR, 902 BGE_EEADDR_RESET | BGE_EEHALFCLK(BGE_HALFCLK_384SCL)); 903 DELAY(20); 904 905 /* Issue the read EEPROM command. */ 906 CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr); 907 908 /* Wait for completion */ 909 for (i = 0; i < BGE_TIMEOUT * 10; i++) { 910 DELAY(10); 911 if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE) 912 break; 913 } 914 915 if (i == BGE_TIMEOUT * 10) { 916 aprint_error_dev(sc->bge_dev, "eeprom read timed out\n"); 917 return 1; 918 } 919 920 /* Get result. */ 921 byte = CSR_READ_4(sc, BGE_EE_DATA); 922 923 *dest = (byte >> ((addr % 4) * 8)) & 0xFF; 924 925 return 0; 926 } 927 928 /* 929 * Read a sequence of bytes from the EEPROM. 930 */ 931 static int 932 bge_read_eeprom(struct bge_softc *sc, void *destv, int off, int cnt) 933 { 934 int err = 0, i; 935 uint8_t byte = 0; 936 char *dest = destv; 937 938 for (i = 0; i < cnt; i++) { 939 err = bge_eeprom_getbyte(sc, off + i, &byte); 940 if (err) 941 break; 942 *(dest + i) = byte; 943 } 944 945 return (err ? 1 : 0); 946 } 947 948 static int 949 bge_miibus_readreg(device_t dev, int phy, int reg) 950 { 951 struct bge_softc *sc = device_private(dev); 952 uint32_t val; 953 uint32_t autopoll; 954 int i; 955 956 /* 957 * Broadcom's own driver always assumes the internal 958 * PHY is at GMII address 1. On some chips, the PHY responds 959 * to accesses at all addresses, which could cause us to 960 * bogusly attach the PHY 32 times at probe type. Always 961 * restricting the lookup to address 1 is simpler than 962 * trying to figure out which chips revisions should be 963 * special-cased. 964 */ 965 if (phy != 1) 966 return 0; 967 968 /* Reading with autopolling on may trigger PCI errors */ 969 autopoll = CSR_READ_4(sc, BGE_MI_MODE); 970 if (autopoll & BGE_MIMODE_AUTOPOLL) { 971 BGE_STS_CLRBIT(sc, BGE_STS_AUTOPOLL); 972 BGE_CLRBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 973 DELAY(40); 974 } 975 976 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_READ | BGE_MICOMM_BUSY | 977 BGE_MIPHY(phy) | BGE_MIREG(reg)); 978 979 for (i = 0; i < BGE_TIMEOUT; i++) { 980 val = CSR_READ_4(sc, BGE_MI_COMM); 981 if (!(val & BGE_MICOMM_BUSY)) 982 break; 983 delay(10); 984 } 985 986 if (i == BGE_TIMEOUT) { 987 aprint_error_dev(sc->bge_dev, "PHY read timed out\n"); 988 val = 0; 989 goto done; 990 } 991 992 val = CSR_READ_4(sc, BGE_MI_COMM); 993 994 done: 995 if (autopoll & BGE_MIMODE_AUTOPOLL) { 996 BGE_STS_SETBIT(sc, BGE_STS_AUTOPOLL); 997 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 998 DELAY(40); 999 } 1000 1001 if (val & BGE_MICOMM_READFAIL) 1002 return 0; 1003 1004 return (val & 0xFFFF); 1005 } 1006 1007 static void 1008 bge_miibus_writereg(device_t dev, int phy, int reg, int val) 1009 { 1010 struct bge_softc *sc = device_private(dev); 1011 uint32_t autopoll; 1012 int i; 1013 1014 if (phy!=1) { 1015 return; 1016 } 1017 1018 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906 && 1019 (reg == BRGPHY_MII_1000CTL || reg == BRGPHY_MII_AUXCTL)) { 1020 return; 1021 } 1022 1023 /* Reading with autopolling on may trigger PCI errors */ 1024 autopoll = CSR_READ_4(sc, BGE_MI_MODE); 1025 if (autopoll & BGE_MIMODE_AUTOPOLL) { 1026 delay(40); 1027 BGE_STS_CLRBIT(sc, BGE_STS_AUTOPOLL); 1028 BGE_CLRBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 1029 delay(10); /* 40 usec is supposed to be adequate */ 1030 } 1031 1032 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_WRITE | BGE_MICOMM_BUSY | 1033 BGE_MIPHY(phy) | BGE_MIREG(reg) | val); 1034 1035 for (i = 0; i < BGE_TIMEOUT; i++) { 1036 delay(10); 1037 if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY)) { 1038 delay(5); 1039 CSR_READ_4(sc, BGE_MI_COMM); 1040 break; 1041 } 1042 } 1043 1044 if (autopoll & BGE_MIMODE_AUTOPOLL) { 1045 BGE_STS_SETBIT(sc, BGE_STS_AUTOPOLL); 1046 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 1047 delay(40); 1048 } 1049 1050 if (i == BGE_TIMEOUT) 1051 aprint_error_dev(sc->bge_dev, "PHY read timed out\n"); 1052 } 1053 1054 static void 1055 bge_miibus_statchg(device_t dev) 1056 { 1057 struct bge_softc *sc = device_private(dev); 1058 struct mii_data *mii = &sc->bge_mii; 1059 1060 /* 1061 * Get flow control negotiation result. 1062 */ 1063 if (IFM_SUBTYPE(mii->mii_media.ifm_cur->ifm_media) == IFM_AUTO && 1064 (mii->mii_media_active & IFM_ETH_FMASK) != sc->bge_flowflags) { 1065 sc->bge_flowflags = mii->mii_media_active & IFM_ETH_FMASK; 1066 mii->mii_media_active &= ~IFM_ETH_FMASK; 1067 } 1068 1069 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_PORTMODE); 1070 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T || 1071 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX) 1072 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_GMII); 1073 else 1074 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_MII); 1075 1076 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) 1077 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX); 1078 else 1079 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX); 1080 1081 /* 1082 * 802.3x flow control 1083 */ 1084 if (sc->bge_flowflags & IFM_ETH_RXPAUSE) 1085 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_FLOWCTL_ENABLE); 1086 else 1087 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_FLOWCTL_ENABLE); 1088 1089 if (sc->bge_flowflags & IFM_ETH_TXPAUSE) 1090 BGE_SETBIT(sc, BGE_TX_MODE, BGE_TXMODE_FLOWCTL_ENABLE); 1091 else 1092 BGE_CLRBIT(sc, BGE_TX_MODE, BGE_TXMODE_FLOWCTL_ENABLE); 1093 } 1094 1095 /* 1096 * Update rx threshold levels to values in a particular slot 1097 * of the interrupt-mitigation table bge_rx_threshes. 1098 */ 1099 static void 1100 bge_set_thresh(struct ifnet *ifp, int lvl) 1101 { 1102 struct bge_softc *sc = ifp->if_softc; 1103 int s; 1104 1105 /* For now, just save the new Rx-intr thresholds and record 1106 * that a threshold update is pending. Updating the hardware 1107 * registers here (even at splhigh()) is observed to 1108 * occasionaly cause glitches where Rx-interrupts are not 1109 * honoured for up to 10 seconds. jonathan (at) NetBSD.org, 2003-04-05 1110 */ 1111 s = splnet(); 1112 sc->bge_rx_coal_ticks = bge_rx_threshes[lvl].rx_ticks; 1113 sc->bge_rx_max_coal_bds = bge_rx_threshes[lvl].rx_max_bds; 1114 sc->bge_pending_rxintr_change = 1; 1115 splx(s); 1116 1117 return; 1118 } 1119 1120 1121 /* 1122 * Update Rx thresholds of all bge devices 1123 */ 1124 static void 1125 bge_update_all_threshes(int lvl) 1126 { 1127 struct ifnet *ifp; 1128 const char * const namebuf = "bge"; 1129 int namelen; 1130 1131 if (lvl < 0) 1132 lvl = 0; 1133 else if (lvl >= NBGE_RX_THRESH) 1134 lvl = NBGE_RX_THRESH - 1; 1135 1136 namelen = strlen(namebuf); 1137 /* 1138 * Now search all the interfaces for this name/number 1139 */ 1140 IFNET_FOREACH(ifp) { 1141 if (strncmp(ifp->if_xname, namebuf, namelen) != 0) 1142 continue; 1143 /* We got a match: update if doing auto-threshold-tuning */ 1144 if (bge_auto_thresh) 1145 bge_set_thresh(ifp, lvl); 1146 } 1147 } 1148 1149 /* 1150 * Handle events that have triggered interrupts. 1151 */ 1152 static void 1153 bge_handle_events(struct bge_softc *sc) 1154 { 1155 1156 return; 1157 } 1158 1159 /* 1160 * Memory management for jumbo frames. 1161 */ 1162 1163 static int 1164 bge_alloc_jumbo_mem(struct bge_softc *sc) 1165 { 1166 char *ptr, *kva; 1167 bus_dma_segment_t seg; 1168 int i, rseg, state, error; 1169 struct bge_jpool_entry *entry; 1170 1171 state = error = 0; 1172 1173 /* Grab a big chunk o' storage. */ 1174 if (bus_dmamem_alloc(sc->bge_dmatag, BGE_JMEM, PAGE_SIZE, 0, 1175 &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 1176 aprint_error_dev(sc->bge_dev, "can't alloc rx buffers\n"); 1177 return ENOBUFS; 1178 } 1179 1180 state = 1; 1181 if (bus_dmamem_map(sc->bge_dmatag, &seg, rseg, BGE_JMEM, (void **)&kva, 1182 BUS_DMA_NOWAIT)) { 1183 aprint_error_dev(sc->bge_dev, 1184 "can't map DMA buffers (%d bytes)\n", (int)BGE_JMEM); 1185 error = ENOBUFS; 1186 goto out; 1187 } 1188 1189 state = 2; 1190 if (bus_dmamap_create(sc->bge_dmatag, BGE_JMEM, 1, BGE_JMEM, 0, 1191 BUS_DMA_NOWAIT, &sc->bge_cdata.bge_rx_jumbo_map)) { 1192 aprint_error_dev(sc->bge_dev, "can't create DMA map\n"); 1193 error = ENOBUFS; 1194 goto out; 1195 } 1196 1197 state = 3; 1198 if (bus_dmamap_load(sc->bge_dmatag, sc->bge_cdata.bge_rx_jumbo_map, 1199 kva, BGE_JMEM, NULL, BUS_DMA_NOWAIT)) { 1200 aprint_error_dev(sc->bge_dev, "can't load DMA map\n"); 1201 error = ENOBUFS; 1202 goto out; 1203 } 1204 1205 state = 4; 1206 sc->bge_cdata.bge_jumbo_buf = (void *)kva; 1207 DPRINTFN(1,("bge_jumbo_buf = %p\n", sc->bge_cdata.bge_jumbo_buf)); 1208 1209 SLIST_INIT(&sc->bge_jfree_listhead); 1210 SLIST_INIT(&sc->bge_jinuse_listhead); 1211 1212 /* 1213 * Now divide it up into 9K pieces and save the addresses 1214 * in an array. 1215 */ 1216 ptr = sc->bge_cdata.bge_jumbo_buf; 1217 for (i = 0; i < BGE_JSLOTS; i++) { 1218 sc->bge_cdata.bge_jslots[i] = ptr; 1219 ptr += BGE_JLEN; 1220 entry = malloc(sizeof(struct bge_jpool_entry), 1221 M_DEVBUF, M_NOWAIT); 1222 if (entry == NULL) { 1223 aprint_error_dev(sc->bge_dev, 1224 "no memory for jumbo buffer queue!\n"); 1225 error = ENOBUFS; 1226 goto out; 1227 } 1228 entry->slot = i; 1229 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, 1230 entry, jpool_entries); 1231 } 1232 out: 1233 if (error != 0) { 1234 switch (state) { 1235 case 4: 1236 bus_dmamap_unload(sc->bge_dmatag, 1237 sc->bge_cdata.bge_rx_jumbo_map); 1238 case 3: 1239 bus_dmamap_destroy(sc->bge_dmatag, 1240 sc->bge_cdata.bge_rx_jumbo_map); 1241 case 2: 1242 bus_dmamem_unmap(sc->bge_dmatag, kva, BGE_JMEM); 1243 case 1: 1244 bus_dmamem_free(sc->bge_dmatag, &seg, rseg); 1245 break; 1246 default: 1247 break; 1248 } 1249 } 1250 1251 return error; 1252 } 1253 1254 /* 1255 * Allocate a jumbo buffer. 1256 */ 1257 static void * 1258 bge_jalloc(struct bge_softc *sc) 1259 { 1260 struct bge_jpool_entry *entry; 1261 1262 entry = SLIST_FIRST(&sc->bge_jfree_listhead); 1263 1264 if (entry == NULL) { 1265 aprint_error_dev(sc->bge_dev, "no free jumbo buffers\n"); 1266 return NULL; 1267 } 1268 1269 SLIST_REMOVE_HEAD(&sc->bge_jfree_listhead, jpool_entries); 1270 SLIST_INSERT_HEAD(&sc->bge_jinuse_listhead, entry, jpool_entries); 1271 return (sc->bge_cdata.bge_jslots[entry->slot]); 1272 } 1273 1274 /* 1275 * Release a jumbo buffer. 1276 */ 1277 static void 1278 bge_jfree(struct mbuf *m, void *buf, size_t size, void *arg) 1279 { 1280 struct bge_jpool_entry *entry; 1281 struct bge_softc *sc; 1282 int i, s; 1283 1284 /* Extract the softc struct pointer. */ 1285 sc = (struct bge_softc *)arg; 1286 1287 if (sc == NULL) 1288 panic("bge_jfree: can't find softc pointer!"); 1289 1290 /* calculate the slot this buffer belongs to */ 1291 1292 i = ((char *)buf 1293 - (char *)sc->bge_cdata.bge_jumbo_buf) / BGE_JLEN; 1294 1295 if ((i < 0) || (i >= BGE_JSLOTS)) 1296 panic("bge_jfree: asked to free buffer that we don't manage!"); 1297 1298 s = splvm(); 1299 entry = SLIST_FIRST(&sc->bge_jinuse_listhead); 1300 if (entry == NULL) 1301 panic("bge_jfree: buffer not in use!"); 1302 entry->slot = i; 1303 SLIST_REMOVE_HEAD(&sc->bge_jinuse_listhead, jpool_entries); 1304 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, entry, jpool_entries); 1305 1306 if (__predict_true(m != NULL)) 1307 pool_cache_put(mb_cache, m); 1308 splx(s); 1309 } 1310 1311 1312 /* 1313 * Initialize a standard receive ring descriptor. 1314 */ 1315 static int 1316 bge_newbuf_std(struct bge_softc *sc, int i, struct mbuf *m, 1317 bus_dmamap_t dmamap) 1318 { 1319 struct mbuf *m_new = NULL; 1320 struct bge_rx_bd *r; 1321 int error; 1322 1323 if (dmamap == NULL) { 1324 error = bus_dmamap_create(sc->bge_dmatag, MCLBYTES, 1, 1325 MCLBYTES, 0, BUS_DMA_NOWAIT, &dmamap); 1326 if (error != 0) 1327 return error; 1328 } 1329 1330 sc->bge_cdata.bge_rx_std_map[i] = dmamap; 1331 1332 if (m == NULL) { 1333 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1334 if (m_new == NULL) 1335 return ENOBUFS; 1336 1337 MCLGET(m_new, M_DONTWAIT); 1338 if (!(m_new->m_flags & M_EXT)) { 1339 m_freem(m_new); 1340 return ENOBUFS; 1341 } 1342 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1343 1344 } else { 1345 m_new = m; 1346 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1347 m_new->m_data = m_new->m_ext.ext_buf; 1348 } 1349 if (!(sc->bge_flags & BGE_RX_ALIGNBUG)) 1350 m_adj(m_new, ETHER_ALIGN); 1351 if (bus_dmamap_load_mbuf(sc->bge_dmatag, dmamap, m_new, 1352 BUS_DMA_READ|BUS_DMA_NOWAIT)) 1353 return ENOBUFS; 1354 bus_dmamap_sync(sc->bge_dmatag, dmamap, 0, dmamap->dm_mapsize, 1355 BUS_DMASYNC_PREREAD); 1356 1357 sc->bge_cdata.bge_rx_std_chain[i] = m_new; 1358 r = &sc->bge_rdata->bge_rx_std_ring[i]; 1359 BGE_HOSTADDR(r->bge_addr, dmamap->dm_segs[0].ds_addr); 1360 r->bge_flags = BGE_RXBDFLAG_END; 1361 r->bge_len = m_new->m_len; 1362 r->bge_idx = i; 1363 1364 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 1365 offsetof(struct bge_ring_data, bge_rx_std_ring) + 1366 i * sizeof (struct bge_rx_bd), 1367 sizeof (struct bge_rx_bd), 1368 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1369 1370 return 0; 1371 } 1372 1373 /* 1374 * Initialize a jumbo receive ring descriptor. This allocates 1375 * a jumbo buffer from the pool managed internally by the driver. 1376 */ 1377 static int 1378 bge_newbuf_jumbo(struct bge_softc *sc, int i, struct mbuf *m) 1379 { 1380 struct mbuf *m_new = NULL; 1381 struct bge_rx_bd *r; 1382 void *buf = NULL; 1383 1384 if (m == NULL) { 1385 1386 /* Allocate the mbuf. */ 1387 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1388 if (m_new == NULL) 1389 return ENOBUFS; 1390 1391 /* Allocate the jumbo buffer */ 1392 buf = bge_jalloc(sc); 1393 if (buf == NULL) { 1394 m_freem(m_new); 1395 aprint_error_dev(sc->bge_dev, 1396 "jumbo allocation failed -- packet dropped!\n"); 1397 return ENOBUFS; 1398 } 1399 1400 /* Attach the buffer to the mbuf. */ 1401 m_new->m_len = m_new->m_pkthdr.len = BGE_JUMBO_FRAMELEN; 1402 MEXTADD(m_new, buf, BGE_JUMBO_FRAMELEN, M_DEVBUF, 1403 bge_jfree, sc); 1404 m_new->m_flags |= M_EXT_RW; 1405 } else { 1406 m_new = m; 1407 buf = m_new->m_data = m_new->m_ext.ext_buf; 1408 m_new->m_ext.ext_size = BGE_JUMBO_FRAMELEN; 1409 } 1410 if (!(sc->bge_flags & BGE_RX_ALIGNBUG)) 1411 m_adj(m_new, ETHER_ALIGN); 1412 bus_dmamap_sync(sc->bge_dmatag, sc->bge_cdata.bge_rx_jumbo_map, 1413 mtod(m_new, char *) - (char *)sc->bge_cdata.bge_jumbo_buf, BGE_JLEN, 1414 BUS_DMASYNC_PREREAD); 1415 /* Set up the descriptor. */ 1416 r = &sc->bge_rdata->bge_rx_jumbo_ring[i]; 1417 sc->bge_cdata.bge_rx_jumbo_chain[i] = m_new; 1418 BGE_HOSTADDR(r->bge_addr, BGE_JUMBO_DMA_ADDR(sc, m_new)); 1419 r->bge_flags = BGE_RXBDFLAG_END|BGE_RXBDFLAG_JUMBO_RING; 1420 r->bge_len = m_new->m_len; 1421 r->bge_idx = i; 1422 1423 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 1424 offsetof(struct bge_ring_data, bge_rx_jumbo_ring) + 1425 i * sizeof (struct bge_rx_bd), 1426 sizeof (struct bge_rx_bd), 1427 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1428 1429 return 0; 1430 } 1431 1432 /* 1433 * The standard receive ring has 512 entries in it. At 2K per mbuf cluster, 1434 * that's 1MB or memory, which is a lot. For now, we fill only the first 1435 * 256 ring entries and hope that our CPU is fast enough to keep up with 1436 * the NIC. 1437 */ 1438 static int 1439 bge_init_rx_ring_std(struct bge_softc *sc) 1440 { 1441 int i; 1442 1443 if (sc->bge_flags & BGE_RXRING_VALID) 1444 return 0; 1445 1446 for (i = 0; i < BGE_SSLOTS; i++) { 1447 if (bge_newbuf_std(sc, i, NULL, 0) == ENOBUFS) 1448 return ENOBUFS; 1449 } 1450 1451 sc->bge_std = i - 1; 1452 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std); 1453 1454 sc->bge_flags |= BGE_RXRING_VALID; 1455 1456 return 0; 1457 } 1458 1459 static void 1460 bge_free_rx_ring_std(struct bge_softc *sc) 1461 { 1462 int i; 1463 1464 if (!(sc->bge_flags & BGE_RXRING_VALID)) 1465 return; 1466 1467 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { 1468 if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) { 1469 m_freem(sc->bge_cdata.bge_rx_std_chain[i]); 1470 sc->bge_cdata.bge_rx_std_chain[i] = NULL; 1471 bus_dmamap_destroy(sc->bge_dmatag, 1472 sc->bge_cdata.bge_rx_std_map[i]); 1473 } 1474 memset((char *)&sc->bge_rdata->bge_rx_std_ring[i], 0, 1475 sizeof(struct bge_rx_bd)); 1476 } 1477 1478 sc->bge_flags &= ~BGE_RXRING_VALID; 1479 } 1480 1481 static int 1482 bge_init_rx_ring_jumbo(struct bge_softc *sc) 1483 { 1484 int i; 1485 volatile struct bge_rcb *rcb; 1486 1487 if (sc->bge_flags & BGE_JUMBO_RXRING_VALID) 1488 return 0; 1489 1490 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 1491 if (bge_newbuf_jumbo(sc, i, NULL) == ENOBUFS) 1492 return ENOBUFS; 1493 }; 1494 1495 sc->bge_jumbo = i - 1; 1496 sc->bge_flags |= BGE_JUMBO_RXRING_VALID; 1497 1498 rcb = &sc->bge_rdata->bge_info.bge_jumbo_rx_rcb; 1499 rcb->bge_maxlen_flags = 0; 1500 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 1501 1502 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo); 1503 1504 return 0; 1505 } 1506 1507 static void 1508 bge_free_rx_ring_jumbo(struct bge_softc *sc) 1509 { 1510 int i; 1511 1512 if (!(sc->bge_flags & BGE_JUMBO_RXRING_VALID)) 1513 return; 1514 1515 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 1516 if (sc->bge_cdata.bge_rx_jumbo_chain[i] != NULL) { 1517 m_freem(sc->bge_cdata.bge_rx_jumbo_chain[i]); 1518 sc->bge_cdata.bge_rx_jumbo_chain[i] = NULL; 1519 } 1520 memset((char *)&sc->bge_rdata->bge_rx_jumbo_ring[i], 0, 1521 sizeof(struct bge_rx_bd)); 1522 } 1523 1524 sc->bge_flags &= ~BGE_JUMBO_RXRING_VALID; 1525 } 1526 1527 static void 1528 bge_free_tx_ring(struct bge_softc *sc) 1529 { 1530 int i, freed; 1531 struct txdmamap_pool_entry *dma; 1532 1533 if (!(sc->bge_flags & BGE_TXRING_VALID)) 1534 return; 1535 1536 freed = 0; 1537 1538 for (i = 0; i < BGE_TX_RING_CNT; i++) { 1539 if (sc->bge_cdata.bge_tx_chain[i] != NULL) { 1540 freed++; 1541 m_freem(sc->bge_cdata.bge_tx_chain[i]); 1542 sc->bge_cdata.bge_tx_chain[i] = NULL; 1543 SLIST_INSERT_HEAD(&sc->txdma_list, sc->txdma[i], 1544 link); 1545 sc->txdma[i] = 0; 1546 } 1547 memset((char *)&sc->bge_rdata->bge_tx_ring[i], 0, 1548 sizeof(struct bge_tx_bd)); 1549 } 1550 1551 while ((dma = SLIST_FIRST(&sc->txdma_list))) { 1552 SLIST_REMOVE_HEAD(&sc->txdma_list, link); 1553 bus_dmamap_destroy(sc->bge_dmatag, dma->dmamap); 1554 free(dma, M_DEVBUF); 1555 } 1556 1557 sc->bge_flags &= ~BGE_TXRING_VALID; 1558 } 1559 1560 static int 1561 bge_init_tx_ring(struct bge_softc *sc) 1562 { 1563 int i; 1564 bus_dmamap_t dmamap; 1565 struct txdmamap_pool_entry *dma; 1566 1567 if (sc->bge_flags & BGE_TXRING_VALID) 1568 return 0; 1569 1570 sc->bge_txcnt = 0; 1571 sc->bge_tx_saved_considx = 0; 1572 1573 /* Initialize transmit producer index for host-memory send ring. */ 1574 sc->bge_tx_prodidx = 0; 1575 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx); 1576 /* 5700 b2 errata */ 1577 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX) 1578 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx); 1579 1580 /* NIC-memory send ring not used; initialize to zero. */ 1581 bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0); 1582 /* 5700 b2 errata */ 1583 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX) 1584 bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0); 1585 1586 SLIST_INIT(&sc->txdma_list); 1587 for (i = 0; i < BGE_RSLOTS; i++) { 1588 if (bus_dmamap_create(sc->bge_dmatag, BGE_TXDMA_MAX, 1589 BGE_NTXSEG, ETHER_MAX_LEN_JUMBO, 0, BUS_DMA_NOWAIT, 1590 &dmamap)) 1591 return ENOBUFS; 1592 if (dmamap == NULL) 1593 panic("dmamap NULL in bge_init_tx_ring"); 1594 dma = malloc(sizeof(*dma), M_DEVBUF, M_NOWAIT); 1595 if (dma == NULL) { 1596 aprint_error_dev(sc->bge_dev, 1597 "can't alloc txdmamap_pool_entry\n"); 1598 bus_dmamap_destroy(sc->bge_dmatag, dmamap); 1599 return ENOMEM; 1600 } 1601 dma->dmamap = dmamap; 1602 SLIST_INSERT_HEAD(&sc->txdma_list, dma, link); 1603 } 1604 1605 sc->bge_flags |= BGE_TXRING_VALID; 1606 1607 return 0; 1608 } 1609 1610 static void 1611 bge_setmulti(struct bge_softc *sc) 1612 { 1613 struct ethercom *ac = &sc->ethercom; 1614 struct ifnet *ifp = &ac->ec_if; 1615 struct ether_multi *enm; 1616 struct ether_multistep step; 1617 uint32_t hashes[4] = { 0, 0, 0, 0 }; 1618 uint32_t h; 1619 int i; 1620 1621 if (ifp->if_flags & IFF_PROMISC) 1622 goto allmulti; 1623 1624 /* Now program new ones. */ 1625 ETHER_FIRST_MULTI(step, ac, enm); 1626 while (enm != NULL) { 1627 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1628 /* 1629 * We must listen to a range of multicast addresses. 1630 * For now, just accept all multicasts, rather than 1631 * trying to set only those filter bits needed to match 1632 * the range. (At this time, the only use of address 1633 * ranges is for IP multicast routing, for which the 1634 * range is big enough to require all bits set.) 1635 */ 1636 goto allmulti; 1637 } 1638 1639 h = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN); 1640 1641 /* Just want the 7 least-significant bits. */ 1642 h &= 0x7f; 1643 1644 hashes[(h & 0x60) >> 5] |= 1 << (h & 0x1F); 1645 ETHER_NEXT_MULTI(step, enm); 1646 } 1647 1648 ifp->if_flags &= ~IFF_ALLMULTI; 1649 goto setit; 1650 1651 allmulti: 1652 ifp->if_flags |= IFF_ALLMULTI; 1653 hashes[0] = hashes[1] = hashes[2] = hashes[3] = 0xffffffff; 1654 1655 setit: 1656 for (i = 0; i < 4; i++) 1657 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]); 1658 } 1659 1660 static void 1661 bge_sig_pre_reset(struct bge_softc *sc, int type) 1662 { 1663 /* 1664 * Some chips don't like this so only do this if ASF is enabled 1665 */ 1666 if (sc->bge_asf_mode) 1667 bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM, BGE_MAGIC_NUMBER); 1668 1669 if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) { 1670 switch (type) { 1671 case BGE_RESET_START: 1672 bge_writemem_ind(sc, BGE_SDI_STATUS, 0x1); /* START */ 1673 break; 1674 case BGE_RESET_STOP: 1675 bge_writemem_ind(sc, BGE_SDI_STATUS, 0x2); /* UNLOAD */ 1676 break; 1677 } 1678 } 1679 } 1680 1681 static void 1682 bge_sig_post_reset(struct bge_softc *sc, int type) 1683 { 1684 1685 if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) { 1686 switch (type) { 1687 case BGE_RESET_START: 1688 bge_writemem_ind(sc, BGE_SDI_STATUS, 0x80000001); 1689 /* START DONE */ 1690 break; 1691 case BGE_RESET_STOP: 1692 bge_writemem_ind(sc, BGE_SDI_STATUS, 0x80000002); 1693 break; 1694 } 1695 } 1696 } 1697 1698 static void 1699 bge_sig_legacy(struct bge_softc *sc, int type) 1700 { 1701 1702 if (sc->bge_asf_mode) { 1703 switch (type) { 1704 case BGE_RESET_START: 1705 bge_writemem_ind(sc, BGE_SDI_STATUS, 0x1); /* START */ 1706 break; 1707 case BGE_RESET_STOP: 1708 bge_writemem_ind(sc, BGE_SDI_STATUS, 0x2); /* UNLOAD */ 1709 break; 1710 } 1711 } 1712 } 1713 1714 static void 1715 bge_stop_fw(struct bge_softc *sc) 1716 { 1717 int i; 1718 1719 if (sc->bge_asf_mode) { 1720 bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM_FW, BGE_FW_PAUSE); 1721 CSR_WRITE_4(sc, BGE_CPU_EVENT, 1722 CSR_READ_4(sc, BGE_CPU_EVENT) | (1 << 14)); 1723 1724 for (i = 0; i < 100; i++) { 1725 if (!(CSR_READ_4(sc, BGE_CPU_EVENT) & (1 << 14))) 1726 break; 1727 DELAY(10); 1728 } 1729 } 1730 } 1731 1732 static int 1733 bge_poll_fw(struct bge_softc *sc) 1734 { 1735 uint32_t val; 1736 int i; 1737 1738 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 1739 for (i = 0; i < BGE_TIMEOUT; i++) { 1740 val = CSR_READ_4(sc, BGE_VCPU_STATUS); 1741 if (val & BGE_VCPU_STATUS_INIT_DONE) 1742 break; 1743 DELAY(100); 1744 } 1745 if (i >= BGE_TIMEOUT) { 1746 aprint_error_dev(sc->bge_dev, "reset timed out\n"); 1747 return -1; 1748 } 1749 } else if ((sc->bge_flags & BGE_NO_EEPROM) == 0) { 1750 /* 1751 * Poll the value location we just wrote until 1752 * we see the 1's complement of the magic number. 1753 * This indicates that the firmware initialization 1754 * is complete. 1755 * XXX 1000ms for Flash and 10000ms for SEEPROM. 1756 */ 1757 for (i = 0; i < BGE_TIMEOUT; i++) { 1758 val = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM); 1759 if (val == ~BGE_MAGIC_NUMBER) 1760 break; 1761 DELAY(10); 1762 } 1763 1764 if (i >= BGE_TIMEOUT) { 1765 aprint_error_dev(sc->bge_dev, 1766 "firmware handshake timed out, val = %x\n", val); 1767 return -1; 1768 } 1769 } 1770 1771 return 0; 1772 } 1773 1774 /* 1775 * Do endian, PCI and DMA initialization. Also check the on-board ROM 1776 * self-test results. 1777 */ 1778 static int 1779 bge_chipinit(struct bge_softc *sc) 1780 { 1781 int i; 1782 uint32_t dma_rw_ctl; 1783 1784 /* Set endianness before we access any non-PCI registers. */ 1785 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MISC_CTL, 1786 BGE_INIT); 1787 1788 /* Set power state to D0. */ 1789 bge_setpowerstate(sc, 0); 1790 1791 /* Clear the MAC control register */ 1792 CSR_WRITE_4(sc, BGE_MAC_MODE, 0); 1793 1794 /* 1795 * Clear the MAC statistics block in the NIC's 1796 * internal memory. 1797 */ 1798 for (i = BGE_STATS_BLOCK; 1799 i < BGE_STATS_BLOCK_END + 1; i += sizeof(uint32_t)) 1800 BGE_MEMWIN_WRITE(sc->sc_pc, sc->sc_pcitag, i, 0); 1801 1802 for (i = BGE_STATUS_BLOCK; 1803 i < BGE_STATUS_BLOCK_END + 1; i += sizeof(uint32_t)) 1804 BGE_MEMWIN_WRITE(sc->sc_pc, sc->sc_pcitag, i, 0); 1805 1806 /* Set up the PCI DMA control register. */ 1807 dma_rw_ctl = BGE_PCI_READ_CMD | BGE_PCI_WRITE_CMD; 1808 if (sc->bge_flags & BGE_PCIE) { 1809 /* Read watermark not used, 128 bytes for write. */ 1810 DPRINTFN(4, ("(%s: PCI-Express DMA setting)\n", 1811 device_xname(sc->bge_dev))); 1812 dma_rw_ctl |= (0x3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT); 1813 } else if (sc->bge_flags & BGE_PCIX) { 1814 DPRINTFN(4, ("(:%s: PCI-X DMA setting)\n", 1815 device_xname(sc->bge_dev))); 1816 /* PCI-X bus */ 1817 if (BGE_IS_5714_FAMILY(sc)) { 1818 /* 256 bytes for read and write. */ 1819 dma_rw_ctl |= (0x02 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) | 1820 (0x02 << BGE_PCIDMARWCTL_WR_WAT_SHIFT); 1821 1822 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5780) 1823 dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL; 1824 else 1825 dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE_LOCAL; 1826 } else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) { 1827 /* 1536 bytes for read, 384 bytes for write. */ 1828 dma_rw_ctl |= 1829 (0x7 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) | 1830 (0x3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT); 1831 } else { 1832 /* 384 bytes for read and write. */ 1833 dma_rw_ctl |= (0x03 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) | 1834 (0x03 << BGE_PCIDMARWCTL_WR_WAT_SHIFT) | 1835 (0x0F); 1836 } 1837 1838 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5703 || 1839 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) { 1840 uint32_t tmp; 1841 1842 /* Set ONEDMA_ATONCE for hardware workaround. */ 1843 tmp = CSR_READ_4(sc, BGE_PCI_CLKCTL) & 0x1f; 1844 if (tmp == 6 || tmp == 7) 1845 dma_rw_ctl |= 1846 BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL; 1847 1848 /* Set PCI-X DMA write workaround. */ 1849 dma_rw_ctl |= BGE_PCIDMARWCTL_ASRT_ALL_BE; 1850 } 1851 } else { 1852 /* Conventional PCI bus: 256 bytes for read and write. */ 1853 DPRINTFN(4, ("(%s: PCI 2.2 DMA setting)\n", 1854 device_xname(sc->bge_dev))); 1855 dma_rw_ctl |= (0x7 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) | 1856 (0x7 << BGE_PCIDMARWCTL_WR_WAT_SHIFT); 1857 if (BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5705 && 1858 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5750) 1859 dma_rw_ctl |= 0x0F; 1860 } 1861 1862 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 1863 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5701) 1864 dma_rw_ctl |= BGE_PCIDMARWCTL_USE_MRM | 1865 BGE_PCIDMARWCTL_ASRT_ALL_BE; 1866 1867 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5703 || 1868 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) 1869 dma_rw_ctl &= ~BGE_PCIDMARWCTL_MINDMA; 1870 1871 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_DMA_RW_CTL, 1872 dma_rw_ctl); 1873 1874 /* 1875 * Set up general mode register. 1876 */ 1877 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS | 1878 BGE_MODECTL_MAC_ATTN_INTR | BGE_MODECTL_HOST_SEND_BDS | 1879 BGE_MODECTL_TX_NO_PHDR_CSUM); 1880 1881 /* 1882 * BCM5701 B5 have a bug causing data corruption when using 1883 * 64-bit DMA reads, which can be terminated early and then 1884 * completed later as 32-bit accesses, in combination with 1885 * certain bridges. 1886 */ 1887 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5701 && 1888 sc->bge_chipid == BGE_CHIPID_BCM5701_B5) 1889 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_FORCE_PCI32); 1890 1891 /* 1892 * Tell the firmware the driver is running 1893 */ 1894 if (sc->bge_asf_mode & ASF_STACKUP) 1895 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 1896 1897 /* 1898 * Disable memory write invalidate. Apparently it is not supported 1899 * properly by these devices. 1900 */ 1901 PCI_CLRBIT(sc->sc_pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG, 1902 PCI_COMMAND_INVALIDATE_ENABLE); 1903 1904 #ifdef __brokenalpha__ 1905 /* 1906 * Must insure that we do not cross an 8K (bytes) boundary 1907 * for DMA reads. Our highest limit is 1K bytes. This is a 1908 * restriction on some ALPHA platforms with early revision 1909 * 21174 PCI chipsets, such as the AlphaPC 164lx 1910 */ 1911 PCI_SETBIT(sc, BGE_PCI_DMA_RW_CTL, BGE_PCI_READ_BNDRY_1024, 4); 1912 #endif 1913 1914 /* Set the timer prescaler (always 66MHz) */ 1915 CSR_WRITE_4(sc, BGE_MISC_CFG, 65 << 1/*BGE_32BITTIME_66MHZ*/); 1916 1917 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 1918 DELAY(40); /* XXX */ 1919 1920 /* Put PHY into ready state */ 1921 BGE_CLRBIT(sc, BGE_MISC_CFG, BGE_MISCCFG_EPHY_IDDQ); 1922 CSR_READ_4(sc, BGE_MISC_CFG); /* Flush */ 1923 DELAY(40); 1924 } 1925 1926 return 0; 1927 } 1928 1929 static int 1930 bge_blockinit(struct bge_softc *sc) 1931 { 1932 volatile struct bge_rcb *rcb; 1933 bus_size_t rcb_addr; 1934 int i; 1935 struct ifnet *ifp = &sc->ethercom.ec_if; 1936 bge_hostaddr taddr; 1937 uint32_t val; 1938 1939 /* 1940 * Initialize the memory window pointer register so that 1941 * we can access the first 32K of internal NIC RAM. This will 1942 * allow us to set up the TX send ring RCBs and the RX return 1943 * ring RCBs, plus other things which live in NIC memory. 1944 */ 1945 1946 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_BASEADDR, 0); 1947 1948 /* Step 33: Configure mbuf memory pool */ 1949 if (BGE_IS_5700_FAMILY(sc)) { 1950 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, 1951 BGE_BUFFPOOL_1); 1952 1953 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) 1954 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000); 1955 else 1956 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000); 1957 1958 /* Configure DMA resource pool */ 1959 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_BASEADDR, 1960 BGE_DMA_DESCRIPTORS); 1961 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LEN, 0x2000); 1962 } 1963 1964 /* Step 35: Configure mbuf pool watermarks */ 1965 #ifdef ORIG_WPAUL_VALUES 1966 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 24); 1967 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 24); 1968 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 48); 1969 #else 1970 1971 /* new broadcom docs strongly recommend these: */ 1972 if (!BGE_IS_5705_PLUS(sc)) { 1973 if (ifp->if_mtu > ETHER_MAX_LEN) { 1974 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x50); 1975 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x20); 1976 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60); 1977 } else { 1978 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 304); 1979 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 152); 1980 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 380); 1981 } 1982 } else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 1983 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0); 1984 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x04); 1985 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x10); 1986 } else { 1987 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0); 1988 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x10); 1989 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60); 1990 } 1991 #endif 1992 1993 /* Step 36: Configure DMA resource watermarks */ 1994 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5); 1995 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10); 1996 1997 /* Step 38: Enable buffer manager */ 1998 CSR_WRITE_4(sc, BGE_BMAN_MODE, 1999 BGE_BMANMODE_ENABLE | BGE_BMANMODE_LOMBUF_ATTN); 2000 2001 /* Step 39: Poll for buffer manager start indication */ 2002 for (i = 0; i < BGE_TIMEOUT * 2; i++) { 2003 if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE) 2004 break; 2005 DELAY(10); 2006 } 2007 2008 if (i == BGE_TIMEOUT * 2) { 2009 aprint_error_dev(sc->bge_dev, 2010 "buffer manager failed to start\n"); 2011 return ENXIO; 2012 } 2013 2014 /* Step 40: Enable flow-through queues */ 2015 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 2016 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 2017 2018 /* Wait until queue initialization is complete */ 2019 for (i = 0; i < BGE_TIMEOUT * 2; i++) { 2020 if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0) 2021 break; 2022 DELAY(10); 2023 } 2024 2025 if (i == BGE_TIMEOUT * 2) { 2026 aprint_error_dev(sc->bge_dev, 2027 "flow-through queue init failed\n"); 2028 return ENXIO; 2029 } 2030 2031 /* Step 41: Initialize the standard RX ring control block */ 2032 rcb = &sc->bge_rdata->bge_info.bge_std_rx_rcb; 2033 BGE_HOSTADDR(rcb->bge_hostaddr, BGE_RING_DMA_ADDR(sc, bge_rx_std_ring)); 2034 if (BGE_IS_5705_PLUS(sc)) 2035 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(512, 0); 2036 else 2037 rcb->bge_maxlen_flags = 2038 BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 0); 2039 rcb->bge_nicaddr = BGE_STD_RX_RINGS; 2040 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcb->bge_hostaddr.bge_addr_hi); 2041 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcb->bge_hostaddr.bge_addr_lo); 2042 CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 2043 CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcb->bge_nicaddr); 2044 2045 /* 2046 * Step 42: Initialize the jumbo RX ring control block 2047 * We set the 'ring disabled' bit in the flags 2048 * field until we're actually ready to start 2049 * using this ring (i.e. once we set the MTU 2050 * high enough to require it). 2051 */ 2052 if (BGE_IS_JUMBO_CAPABLE(sc)) { 2053 rcb = &sc->bge_rdata->bge_info.bge_jumbo_rx_rcb; 2054 BGE_HOSTADDR(rcb->bge_hostaddr, 2055 BGE_RING_DMA_ADDR(sc, bge_rx_jumbo_ring)); 2056 rcb->bge_maxlen_flags = 2057 BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 2058 BGE_RCB_FLAG_RING_DISABLED); 2059 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS; 2060 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI, 2061 rcb->bge_hostaddr.bge_addr_hi); 2062 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO, 2063 rcb->bge_hostaddr.bge_addr_lo); 2064 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, 2065 rcb->bge_maxlen_flags); 2066 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcb->bge_nicaddr); 2067 2068 /* Set up dummy disabled mini ring RCB */ 2069 rcb = &sc->bge_rdata->bge_info.bge_mini_rx_rcb; 2070 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0, 2071 BGE_RCB_FLAG_RING_DISABLED); 2072 CSR_WRITE_4(sc, BGE_RX_MINI_RCB_MAXLEN_FLAGS, 2073 rcb->bge_maxlen_flags); 2074 2075 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 2076 offsetof(struct bge_ring_data, bge_info), 2077 sizeof (struct bge_gib), 2078 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2079 } 2080 2081 /* 2082 * Set the BD ring replenish thresholds. The recommended 2083 * values are 1/8th the number of descriptors allocated to 2084 * each ring. 2085 */ 2086 i = BGE_STD_RX_RING_CNT / 8; 2087 2088 /* 2089 * Use a value of 8 for the following chips to workaround HW errata. 2090 * Some of these chips have been added based on empirical 2091 * evidence (they don't work unless this is done). 2092 */ 2093 if (BGE_IS_5705_PLUS(sc)) 2094 i = 8; 2095 2096 CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, i); 2097 CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH, BGE_JUMBO_RX_RING_CNT / 8); 2098 2099 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5717 || 2100 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57765) { 2101 CSR_WRITE_4(sc, BGE_STD_REPL_LWM, 4); 2102 CSR_WRITE_4(sc, BGE_JUMBO_REPL_LWM, 4); 2103 } 2104 2105 /* 2106 * Disable all unused send rings by setting the 'ring disabled' 2107 * bit in the flags field of all the TX send ring control blocks. 2108 * These are located in NIC memory. 2109 */ 2110 rcb_addr = BGE_MEMWIN_START + BGE_SEND_RING_RCB; 2111 for (i = 0; i < BGE_TX_RINGS_EXTSSRAM_MAX; i++) { 2112 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 2113 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED)); 2114 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 0); 2115 rcb_addr += sizeof(struct bge_rcb); 2116 } 2117 2118 /* Configure TX RCB 0 (we use only the first ring) */ 2119 rcb_addr = BGE_MEMWIN_START + BGE_SEND_RING_RCB; 2120 BGE_HOSTADDR(taddr, BGE_RING_DMA_ADDR(sc, bge_tx_ring)); 2121 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi); 2122 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo); 2123 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 2124 BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT)); 2125 if (BGE_IS_5700_FAMILY(sc)) 2126 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 2127 BGE_RCB_MAXLEN_FLAGS(BGE_TX_RING_CNT, 0)); 2128 2129 /* Disable all unused RX return rings */ 2130 rcb_addr = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB; 2131 for (i = 0; i < BGE_RX_RINGS_MAX; i++) { 2132 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_hi, 0); 2133 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_lo, 0); 2134 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 2135 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 2136 BGE_RCB_FLAG_RING_DISABLED)); 2137 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 0); 2138 bge_writembx(sc, BGE_MBX_RX_CONS0_LO + 2139 (i * (sizeof(uint64_t))), 0); 2140 rcb_addr += sizeof(struct bge_rcb); 2141 } 2142 2143 /* Initialize RX ring indexes */ 2144 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, 0); 2145 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0); 2146 bge_writembx(sc, BGE_MBX_RX_MINI_PROD_LO, 0); 2147 2148 /* 2149 * Set up RX return ring 0 2150 * Note that the NIC address for RX return rings is 0x00000000. 2151 * The return rings live entirely within the host, so the 2152 * nicaddr field in the RCB isn't used. 2153 */ 2154 rcb_addr = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB; 2155 BGE_HOSTADDR(taddr, BGE_RING_DMA_ADDR(sc, bge_rx_return_ring)); 2156 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi); 2157 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo); 2158 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 0x00000000); 2159 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 2160 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 0)); 2161 2162 /* Set random backoff seed for TX */ 2163 CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF, 2164 CLLADDR(ifp->if_sadl)[0] + CLLADDR(ifp->if_sadl)[1] + 2165 CLLADDR(ifp->if_sadl)[2] + CLLADDR(ifp->if_sadl)[3] + 2166 CLLADDR(ifp->if_sadl)[4] + CLLADDR(ifp->if_sadl)[5] + 2167 BGE_TX_BACKOFF_SEED_MASK); 2168 2169 /* Set inter-packet gap */ 2170 CSR_WRITE_4(sc, BGE_TX_LENGTHS, 0x2620); 2171 2172 /* 2173 * Specify which ring to use for packets that don't match 2174 * any RX rules. 2175 */ 2176 CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08); 2177 2178 /* 2179 * Configure number of RX lists. One interrupt distribution 2180 * list, sixteen active lists, one bad frames class. 2181 */ 2182 CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181); 2183 2184 /* Inialize RX list placement stats mask. */ 2185 CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF); 2186 CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1); 2187 2188 /* Disable host coalescing until we get it set up */ 2189 CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000); 2190 2191 /* Poll to make sure it's shut down. */ 2192 for (i = 0; i < BGE_TIMEOUT * 2; i++) { 2193 if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE)) 2194 break; 2195 DELAY(10); 2196 } 2197 2198 if (i == BGE_TIMEOUT * 2) { 2199 aprint_error_dev(sc->bge_dev, 2200 "host coalescing engine failed to idle\n"); 2201 return ENXIO; 2202 } 2203 2204 /* Set up host coalescing defaults */ 2205 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bge_rx_coal_ticks); 2206 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bge_tx_coal_ticks); 2207 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bge_rx_max_coal_bds); 2208 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bge_tx_max_coal_bds); 2209 if (BGE_IS_5700_FAMILY(sc)) { 2210 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT, 0); 2211 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT, 0); 2212 } 2213 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 0); 2214 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 0); 2215 2216 /* Set up address of statistics block */ 2217 if (BGE_IS_5700_FAMILY(sc)) { 2218 BGE_HOSTADDR(taddr, BGE_RING_DMA_ADDR(sc, bge_info.bge_stats)); 2219 CSR_WRITE_4(sc, BGE_HCC_STATS_TICKS, sc->bge_stat_ticks); 2220 CSR_WRITE_4(sc, BGE_HCC_STATS_BASEADDR, BGE_STATS_BLOCK); 2221 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_HI, taddr.bge_addr_hi); 2222 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_LO, taddr.bge_addr_lo); 2223 } 2224 2225 /* Set up address of status block */ 2226 BGE_HOSTADDR(taddr, BGE_RING_DMA_ADDR(sc, bge_status_block)); 2227 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_BASEADDR, BGE_STATUS_BLOCK); 2228 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI, taddr.bge_addr_hi); 2229 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO, taddr.bge_addr_lo); 2230 sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx = 0; 2231 sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx = 0; 2232 2233 /* Turn on host coalescing state machine */ 2234 CSR_WRITE_4(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE); 2235 2236 /* Turn on RX BD completion state machine and enable attentions */ 2237 CSR_WRITE_4(sc, BGE_RBDC_MODE, 2238 BGE_RBDCMODE_ENABLE | BGE_RBDCMODE_ATTN); 2239 2240 /* Turn on RX list placement state machine */ 2241 CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 2242 2243 /* Turn on RX list selector state machine. */ 2244 if (BGE_IS_5700_FAMILY(sc)) 2245 CSR_WRITE_4(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 2246 2247 val = BGE_MACMODE_TXDMA_ENB | BGE_MACMODE_RXDMA_ENB | 2248 BGE_MACMODE_RX_STATS_CLEAR | BGE_MACMODE_TX_STATS_CLEAR | 2249 BGE_MACMODE_RX_STATS_ENB | BGE_MACMODE_TX_STATS_ENB | 2250 BGE_MACMODE_FRMHDR_DMA_ENB; 2251 2252 if (sc->bge_flags & BGE_PHY_FIBER_TBI) 2253 val |= BGE_PORTMODE_TBI; 2254 else if (sc->bge_flags & BGE_PHY_FIBER_MII) 2255 val |= BGE_PORTMODE_GMII; 2256 else 2257 val |= BGE_PORTMODE_MII; 2258 2259 /* Turn on DMA, clear stats */ 2260 CSR_WRITE_4(sc, BGE_MAC_MODE, val); 2261 2262 /* Set misc. local control, enable interrupts on attentions */ 2263 sc->bge_local_ctrl_reg = BGE_MLC_INTR_ONATTN | BGE_MLC_AUTO_EEPROM; 2264 2265 #ifdef notdef 2266 /* Assert GPIO pins for PHY reset */ 2267 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUT0| 2268 BGE_MLC_MISCIO_OUT1|BGE_MLC_MISCIO_OUT2); 2269 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUTEN0| 2270 BGE_MLC_MISCIO_OUTEN1|BGE_MLC_MISCIO_OUTEN2); 2271 #endif 2272 2273 #if defined(not_quite_yet) 2274 /* Linux driver enables enable gpio pin #1 on 5700s */ 2275 if (sc->bge_chipid == BGE_CHIPID_BCM5700) { 2276 sc->bge_local_ctrl_reg |= 2277 (BGE_MLC_MISCIO_OUT1|BGE_MLC_MISCIO_OUTEN1); 2278 } 2279 #endif 2280 CSR_WRITE_4(sc, BGE_MISC_LOCAL_CTL, sc->bge_local_ctrl_reg); 2281 2282 /* Turn on DMA completion state machine */ 2283 if (BGE_IS_5700_FAMILY(sc)) 2284 CSR_WRITE_4(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 2285 2286 /* Turn on write DMA state machine */ 2287 { 2288 uint32_t bge_wdma_mode = 2289 BGE_WDMAMODE_ENABLE|BGE_WDMAMODE_ALL_ATTNS; 2290 2291 /* Enable host coalescing bug fix; see Linux tg3.c */ 2292 if (BGE_IS_5755_PLUS(sc)) 2293 bge_wdma_mode |= BGE_WDMAMODE_STATUS_TAG_FIX; 2294 2295 CSR_WRITE_4(sc, BGE_WDMA_MODE, bge_wdma_mode); 2296 } 2297 2298 /* Turn on read DMA state machine */ 2299 { 2300 uint32_t dma_read_modebits; 2301 2302 dma_read_modebits = 2303 BGE_RDMAMODE_ENABLE | BGE_RDMAMODE_ALL_ATTNS; 2304 2305 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5784 || 2306 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785 || 2307 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57780) 2308 dma_read_modebits |= BGE_RDMAMODE_BD_SBD_CRPT_ATTN | 2309 BGE_RDMAMODE_MBUF_RBD_CRPT_ATTN | 2310 BGE_RDMAMODE_MBUF_SBD_CRPT_ATTN; 2311 2312 if (sc->bge_flags & BGE_PCIE) 2313 dma_read_modebits |= BGE_RDMA_MODE_FIFO_LONG_BURST; 2314 if (sc->bge_flags & BGE_TSO) 2315 dma_read_modebits |= BGE_RDMAMODE_TSO4_ENABLE; 2316 CSR_WRITE_4(sc, BGE_RDMA_MODE, dma_read_modebits); 2317 delay(40); 2318 } 2319 2320 /* Turn on RX data completion state machine */ 2321 CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 2322 2323 /* Turn on RX BD initiator state machine */ 2324 CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 2325 2326 /* Turn on RX data and RX BD initiator state machine */ 2327 CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE); 2328 2329 /* Turn on Mbuf cluster free state machine */ 2330 if (BGE_IS_5700_FAMILY(sc)) 2331 CSR_WRITE_4(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 2332 2333 /* Turn on send BD completion state machine */ 2334 CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 2335 2336 /* Turn on send data completion state machine */ 2337 val = BGE_SDCMODE_ENABLE; 2338 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761) 2339 val |= BGE_SDCMODE_CDELAY; 2340 CSR_WRITE_4(sc, BGE_SDC_MODE, val); 2341 2342 /* Turn on send data initiator state machine */ 2343 if (sc->bge_flags & BGE_TSO) { 2344 /* XXX: magic value from Linux driver */ 2345 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE | 0x08); 2346 } else 2347 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 2348 2349 /* Turn on send BD initiator state machine */ 2350 CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 2351 2352 /* Turn on send BD selector state machine */ 2353 CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 2354 2355 CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF); 2356 CSR_WRITE_4(sc, BGE_SDI_STATS_CTL, 2357 BGE_SDISTATSCTL_ENABLE | BGE_SDISTATSCTL_FASTER); 2358 2359 /* ack/clear link change events */ 2360 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED | 2361 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE | 2362 BGE_MACSTAT_LINK_CHANGED); 2363 CSR_WRITE_4(sc, BGE_MI_STS, 0); 2364 2365 /* Enable PHY auto polling (for MII/GMII only) */ 2366 if (sc->bge_flags & BGE_PHY_FIBER_TBI) { 2367 CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK); 2368 } else { 2369 BGE_STS_SETBIT(sc, BGE_STS_AUTOPOLL); 2370 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL | (10 << 16)); 2371 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700) 2372 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, 2373 BGE_EVTENB_MI_INTERRUPT); 2374 } 2375 2376 /* 2377 * Clear any pending link state attention. 2378 * Otherwise some link state change events may be lost until attention 2379 * is cleared by bge_intr() -> bge_link_upd() sequence. 2380 * It's not necessary on newer BCM chips - perhaps enabling link 2381 * state change attentions implies clearing pending attention. 2382 */ 2383 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED | 2384 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE | 2385 BGE_MACSTAT_LINK_CHANGED); 2386 2387 /* Enable link state change attentions. */ 2388 BGE_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED); 2389 2390 return 0; 2391 } 2392 2393 static const struct bge_revision * 2394 bge_lookup_rev(uint32_t chipid) 2395 { 2396 const struct bge_revision *br; 2397 2398 for (br = bge_revisions; br->br_name != NULL; br++) { 2399 if (br->br_chipid == chipid) 2400 return br; 2401 } 2402 2403 for (br = bge_majorrevs; br->br_name != NULL; br++) { 2404 if (br->br_chipid == BGE_ASICREV(chipid)) 2405 return br; 2406 } 2407 2408 return NULL; 2409 } 2410 2411 static const struct bge_product * 2412 bge_lookup(const struct pci_attach_args *pa) 2413 { 2414 const struct bge_product *bp; 2415 2416 for (bp = bge_products; bp->bp_name != NULL; bp++) { 2417 if (PCI_VENDOR(pa->pa_id) == bp->bp_vendor && 2418 PCI_PRODUCT(pa->pa_id) == bp->bp_product) 2419 return bp; 2420 } 2421 2422 return NULL; 2423 } 2424 2425 static int 2426 bge_setpowerstate(struct bge_softc *sc, int powerlevel) 2427 { 2428 #ifdef NOTYET 2429 uint32_t pm_ctl = 0; 2430 2431 /* XXX FIXME: make sure indirect accesses enabled? */ 2432 pm_ctl = pci_conf_read(sc->bge_dev, BGE_PCI_MISC_CTL, 4); 2433 pm_ctl |= BGE_PCIMISCCTL_INDIRECT_ACCESS; 2434 pci_write_config(sc->bge_dev, BGE_PCI_MISC_CTL, pm_ctl, 4); 2435 2436 /* clear the PME_assert bit and power state bits, enable PME */ 2437 pm_ctl = pci_conf_read(sc->bge_dev, BGE_PCI_PWRMGMT_CMD, 2); 2438 pm_ctl &= ~PCIM_PSTAT_DMASK; 2439 pm_ctl |= (1 << 8); 2440 2441 if (powerlevel == 0) { 2442 pm_ctl |= PCIM_PSTAT_D0; 2443 pci_write_config(sc->bge_dev, BGE_PCI_PWRMGMT_CMD, 2444 pm_ctl, 2); 2445 DELAY(10000); 2446 CSR_WRITE_4(sc, BGE_MISC_LOCAL_CTL, sc->bge_local_ctrl_reg); 2447 DELAY(10000); 2448 2449 #ifdef NOTYET 2450 /* XXX FIXME: write 0x02 to phy aux_Ctrl reg */ 2451 bge_miibus_writereg(sc->bge_dev, 1, 0x18, 0x02); 2452 #endif 2453 DELAY(40); DELAY(40); DELAY(40); 2454 DELAY(10000); /* above not quite adequate on 5700 */ 2455 return 0; 2456 } 2457 2458 2459 /* 2460 * Entering ACPI power states D1-D3 is achieved by wiggling 2461 * GMII gpio pins. Example code assumes all hardware vendors 2462 * followed Broadcom's sample pcb layout. Until we verify that 2463 * for all supported OEM cards, states D1-D3 are unsupported. 2464 */ 2465 aprint_error_dev(sc->bge_dev, 2466 "power state %d unimplemented; check GPIO pins\n", 2467 powerlevel); 2468 #endif 2469 return EOPNOTSUPP; 2470 } 2471 2472 2473 /* 2474 * Probe for a Broadcom chip. Check the PCI vendor and device IDs 2475 * against our list and return its name if we find a match. Note 2476 * that since the Broadcom controller contains VPD support, we 2477 * can get the device name string from the controller itself instead 2478 * of the compiled-in string. This is a little slow, but it guarantees 2479 * we'll always announce the right product name. 2480 */ 2481 static int 2482 bge_probe(device_t parent, cfdata_t match, void *aux) 2483 { 2484 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 2485 2486 if (bge_lookup(pa) != NULL) 2487 return 1; 2488 2489 return 0; 2490 } 2491 2492 static void 2493 bge_attach(device_t parent, device_t self, void *aux) 2494 { 2495 struct bge_softc *sc = device_private(self); 2496 struct pci_attach_args *pa = aux; 2497 prop_dictionary_t dict; 2498 const struct bge_product *bp; 2499 const struct bge_revision *br; 2500 pci_chipset_tag_t pc; 2501 pci_intr_handle_t ih; 2502 const char *intrstr = NULL; 2503 bus_dma_segment_t seg; 2504 int rseg; 2505 uint32_t hwcfg = 0; 2506 uint32_t command; 2507 struct ifnet *ifp; 2508 uint32_t misccfg; 2509 void * kva; 2510 u_char eaddr[ETHER_ADDR_LEN]; 2511 pcireg_t memtype, subid; 2512 bus_addr_t memaddr; 2513 bus_size_t memsize; 2514 uint32_t pm_ctl; 2515 bool no_seeprom; 2516 2517 bp = bge_lookup(pa); 2518 KASSERT(bp != NULL); 2519 2520 sc->sc_pc = pa->pa_pc; 2521 sc->sc_pcitag = pa->pa_tag; 2522 sc->bge_dev = self; 2523 2524 pc = sc->sc_pc; 2525 subid = pci_conf_read(pc, sc->sc_pcitag, PCI_SUBSYS_ID_REG); 2526 2527 aprint_naive(": Ethernet controller\n"); 2528 aprint_normal(": %s\n", bp->bp_name); 2529 2530 /* 2531 * Map control/status registers. 2532 */ 2533 DPRINTFN(5, ("Map control/status regs\n")); 2534 command = pci_conf_read(pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG); 2535 command |= PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_MASTER_ENABLE; 2536 pci_conf_write(pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG, command); 2537 command = pci_conf_read(pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG); 2538 2539 if (!(command & PCI_COMMAND_MEM_ENABLE)) { 2540 aprint_error_dev(sc->bge_dev, 2541 "failed to enable memory mapping!\n"); 2542 return; 2543 } 2544 2545 DPRINTFN(5, ("pci_mem_find\n")); 2546 memtype = pci_mapreg_type(sc->sc_pc, sc->sc_pcitag, BGE_PCI_BAR0); 2547 switch (memtype) { 2548 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 2549 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 2550 if (pci_mapreg_map(pa, BGE_PCI_BAR0, 2551 memtype, 0, &sc->bge_btag, &sc->bge_bhandle, 2552 &memaddr, &memsize) == 0) 2553 break; 2554 default: 2555 aprint_error_dev(sc->bge_dev, "can't find mem space\n"); 2556 return; 2557 } 2558 2559 DPRINTFN(5, ("pci_intr_map\n")); 2560 if (pci_intr_map(pa, &ih)) { 2561 aprint_error_dev(sc->bge_dev, "couldn't map interrupt\n"); 2562 return; 2563 } 2564 2565 DPRINTFN(5, ("pci_intr_string\n")); 2566 intrstr = pci_intr_string(pc, ih); 2567 2568 DPRINTFN(5, ("pci_intr_establish\n")); 2569 sc->bge_intrhand = pci_intr_establish(pc, ih, IPL_NET, bge_intr, sc); 2570 2571 if (sc->bge_intrhand == NULL) { 2572 aprint_error_dev(sc->bge_dev, 2573 "couldn't establish interrupt%s%s\n", 2574 intrstr ? " at " : "", intrstr ? intrstr : ""); 2575 return; 2576 } 2577 aprint_normal_dev(sc->bge_dev, "interrupting at %s\n", intrstr); 2578 2579 /* 2580 * Kludge for 5700 Bx bug: a hardware bug (PCIX byte enable?) 2581 * can clobber the chip's PCI config-space power control registers, 2582 * leaving the card in D3 powersave state. 2583 * We do not have memory-mapped registers in this state, 2584 * so force device into D0 state before starting initialization. 2585 */ 2586 pm_ctl = pci_conf_read(pc, sc->sc_pcitag, BGE_PCI_PWRMGMT_CMD); 2587 pm_ctl &= ~(PCI_PWR_D0|PCI_PWR_D1|PCI_PWR_D2|PCI_PWR_D3); 2588 pm_ctl |= (1 << 8) | PCI_PWR_D0 ; /* D0 state */ 2589 pci_conf_write(pc, sc->sc_pcitag, BGE_PCI_PWRMGMT_CMD, pm_ctl); 2590 DELAY(1000); /* 27 usec is allegedly sufficent */ 2591 2592 /* 2593 * Save ASIC rev. 2594 */ 2595 sc->bge_chipid = 2596 pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_MISC_CTL) 2597 >> BGE_PCIMISCCTL_ASICREV_SHIFT; 2598 2599 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_USE_PRODID_REG) { 2600 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5717 || 2601 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5718 || 2602 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5724) 2603 sc->bge_chipid = pci_conf_read(pc, pa->pa_tag, 2604 BGE_PCI_GEN2_PRODID_ASICREV); 2605 else if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM57761 || 2606 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM57765 || 2607 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM57781 || 2608 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM57785 || 2609 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM57791 || 2610 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM57795) 2611 sc->bge_chipid = pci_conf_read(pc, pa->pa_tag, 2612 BGE_PCI_GEN15_PRODID_ASICREV); 2613 else 2614 sc->bge_chipid = pci_conf_read(pc, pa->pa_tag, 2615 BGE_PCI_PRODID_ASICREV); 2616 } 2617 2618 if ((pci_get_capability(sc->sc_pc, sc->sc_pcitag, PCI_CAP_PCIEXPRESS, 2619 &sc->bge_pciecap, NULL) != 0) 2620 || (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785)) { 2621 /* PCIe */ 2622 sc->bge_flags |= BGE_PCIE; 2623 bge_set_max_readrq(sc); 2624 } else if ((pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_PCISTATE) & 2625 BGE_PCISTATE_PCI_BUSMODE) == 0) { 2626 /* PCI-X */ 2627 sc->bge_flags |= BGE_PCIX; 2628 if (pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_PCIX, 2629 &sc->bge_pcixcap, NULL) == 0) 2630 aprint_error_dev(sc->bge_dev, 2631 "unable to find PCIX capability\n"); 2632 } 2633 2634 /* chipid */ 2635 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 2636 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5701 || 2637 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5703 || 2638 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) 2639 sc->bge_flags |= BGE_5700_FAMILY; 2640 2641 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5714_A0 || 2642 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5780 || 2643 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5714) 2644 sc->bge_flags |= BGE_5714_FAMILY; 2645 2646 /* Intentionally exclude BGE_ASICREV_BCM5906 */ 2647 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5717 || 2648 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5755 || 2649 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761 || 2650 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5784 || 2651 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785 || 2652 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5787 || 2653 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57765 || 2654 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57780) 2655 sc->bge_flags |= BGE_5755_PLUS; 2656 2657 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5750 || 2658 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5752 || 2659 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906 || 2660 BGE_IS_5755_PLUS(sc) || 2661 BGE_IS_5714_FAMILY(sc)) 2662 sc->bge_flags |= BGE_5750_PLUS; 2663 2664 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5705 || 2665 BGE_IS_5750_OR_BEYOND(sc)) 2666 sc->bge_flags |= BGE_5705_PLUS; 2667 2668 /* 2669 * When using the BCM5701 in PCI-X mode, data corruption has 2670 * been observed in the first few bytes of some received packets. 2671 * Aligning the packet buffer in memory eliminates the corruption. 2672 * Unfortunately, this misaligns the packet payloads. On platforms 2673 * which do not support unaligned accesses, we will realign the 2674 * payloads by copying the received packets. 2675 */ 2676 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5701 && 2677 sc->bge_flags & BGE_PCIX) 2678 sc->bge_flags |= BGE_RX_ALIGNBUG; 2679 2680 if (BGE_IS_5700_FAMILY(sc)) 2681 sc->bge_flags |= BGE_JUMBO_CAPABLE; 2682 2683 if ((BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 2684 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5701) && 2685 PCI_VENDOR(subid) == PCI_VENDOR_DELL) 2686 sc->bge_flags |= BGE_NO_3LED; 2687 2688 misccfg = CSR_READ_4(sc, BGE_MISC_CFG); 2689 misccfg &= BGE_MISCCFG_BOARD_ID_MASK; 2690 2691 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5705 && 2692 (misccfg == BGE_MISCCFG_BOARD_ID_5788 || 2693 misccfg == BGE_MISCCFG_BOARD_ID_5788M)) 2694 sc->bge_flags |= BGE_IS_5788; 2695 2696 /* 2697 * Some controllers seem to require a special firmware to use 2698 * TSO. But the firmware is not available to FreeBSD and Linux 2699 * claims that the TSO performed by the firmware is slower than 2700 * hardware based TSO. Moreover the firmware based TSO has one 2701 * known bug which can't handle TSO if ethernet header + IP/TCP 2702 * header is greater than 80 bytes. The workaround for the TSO 2703 * bug exist but it seems it's too expensive than not using 2704 * TSO at all. Some hardwares also have the TSO bug so limit 2705 * the TSO to the controllers that are not affected TSO issues 2706 * (e.g. 5755 or higher). 2707 */ 2708 if (BGE_IS_5755_PLUS(sc)) { 2709 /* 2710 * BCM5754 and BCM5787 shares the same ASIC id so 2711 * explicit device id check is required. 2712 */ 2713 if ((PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_BROADCOM_BCM5754) && 2714 (PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_BROADCOM_BCM5754M)) 2715 sc->bge_flags |= BGE_TSO; 2716 } 2717 2718 if ((BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5703 && 2719 (misccfg == 0x4000 || misccfg == 0x8000)) || 2720 (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5705 && 2721 PCI_VENDOR(pa->pa_id) == PCI_VENDOR_BROADCOM && 2722 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5901 || 2723 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5901A2 || 2724 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5705F)) || 2725 (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_BROADCOM && 2726 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5751F || 2727 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5753F || 2728 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5787F)) || 2729 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM57790 || 2730 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 2731 sc->bge_flags |= BGE_10_100_ONLY; 2732 2733 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 2734 (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5705 && 2735 (sc->bge_chipid != BGE_CHIPID_BCM5705_A0 && 2736 sc->bge_chipid != BGE_CHIPID_BCM5705_A1)) || 2737 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 2738 sc->bge_flags |= BGE_NO_ETH_WIRE_SPEED; 2739 2740 if (sc->bge_chipid == BGE_CHIPID_BCM5701_A0 || 2741 sc->bge_chipid == BGE_CHIPID_BCM5701_B0) 2742 sc->bge_flags |= BGE_PHY_CRC_BUG; 2743 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5703_AX || 2744 BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5704_AX) 2745 sc->bge_flags |= BGE_PHY_ADC_BUG; 2746 if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0) 2747 sc->bge_flags |= BGE_PHY_5704_A0_BUG; 2748 2749 if (BGE_IS_5705_PLUS(sc) && 2750 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5906 && 2751 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5717 && 2752 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5785 && 2753 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM57765 && 2754 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM57780) { 2755 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5755 || 2756 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761 || 2757 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5784 || 2758 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5787) { 2759 if (PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_BROADCOM_BCM5722 && 2760 PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_BROADCOM_BCM5756) 2761 sc->bge_flags |= BGE_PHY_JITTER_BUG; 2762 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5755M) 2763 sc->bge_flags |= BGE_PHY_ADJUST_TRIM; 2764 } else if (BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5906) 2765 sc->bge_flags |= BGE_PHY_BER_BUG; 2766 } 2767 2768 /* 2769 * SEEPROM check. 2770 * First check if firmware knows we do not have SEEPROM. 2771 */ 2772 if (prop_dictionary_get_bool(device_properties(self), 2773 "without-seeprom", &no_seeprom) && no_seeprom) 2774 sc->bge_flags |= BGE_NO_EEPROM; 2775 2776 /* Now check the 'ROM failed' bit on the RX CPU */ 2777 else if (CSR_READ_4(sc, BGE_RXCPU_MODE) & BGE_RXCPUMODE_ROMFAIL) 2778 sc->bge_flags |= BGE_NO_EEPROM; 2779 2780 /* Try to reset the chip. */ 2781 DPRINTFN(5, ("bge_reset\n")); 2782 bge_reset(sc); 2783 2784 sc->bge_asf_mode = 0; 2785 if (bge_allow_asf && (bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_SIG) 2786 == BGE_MAGIC_NUMBER)) { 2787 if (bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_NICCFG) 2788 & BGE_HWCFG_ASF) { 2789 sc->bge_asf_mode |= ASF_ENABLE; 2790 sc->bge_asf_mode |= ASF_STACKUP; 2791 if (BGE_IS_5750_OR_BEYOND(sc)) { 2792 sc->bge_asf_mode |= ASF_NEW_HANDSHAKE; 2793 } 2794 } 2795 } 2796 2797 /* Try to reset the chip again the nice way. */ 2798 bge_stop_fw(sc); 2799 bge_sig_pre_reset(sc, BGE_RESET_STOP); 2800 if (bge_reset(sc)) 2801 aprint_error_dev(sc->bge_dev, "chip reset failed\n"); 2802 2803 bge_sig_legacy(sc, BGE_RESET_STOP); 2804 bge_sig_post_reset(sc, BGE_RESET_STOP); 2805 2806 if (bge_chipinit(sc)) { 2807 aprint_error_dev(sc->bge_dev, "chip initialization failed\n"); 2808 bge_release_resources(sc); 2809 return; 2810 } 2811 2812 /* 2813 * Get station address from the EEPROM 2814 */ 2815 if (bge_get_eaddr(sc, eaddr)) { 2816 aprint_error_dev(sc->bge_dev, 2817 "failed to read station address\n"); 2818 bge_release_resources(sc); 2819 return; 2820 } 2821 2822 br = bge_lookup_rev(sc->bge_chipid); 2823 2824 if (br == NULL) { 2825 aprint_normal_dev(sc->bge_dev, "unknown ASIC (0x%x)", 2826 sc->bge_chipid); 2827 } else { 2828 aprint_normal_dev(sc->bge_dev, "ASIC %s (0x%x)", 2829 br->br_name, sc->bge_chipid); 2830 } 2831 aprint_normal(", Ethernet address %s\n", ether_sprintf(eaddr)); 2832 2833 /* Allocate the general information block and ring buffers. */ 2834 if (pci_dma64_available(pa)) 2835 sc->bge_dmatag = pa->pa_dmat64; 2836 else 2837 sc->bge_dmatag = pa->pa_dmat; 2838 DPRINTFN(5, ("bus_dmamem_alloc\n")); 2839 if (bus_dmamem_alloc(sc->bge_dmatag, sizeof(struct bge_ring_data), 2840 PAGE_SIZE, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 2841 aprint_error_dev(sc->bge_dev, "can't alloc rx buffers\n"); 2842 return; 2843 } 2844 DPRINTFN(5, ("bus_dmamem_map\n")); 2845 if (bus_dmamem_map(sc->bge_dmatag, &seg, rseg, 2846 sizeof(struct bge_ring_data), &kva, 2847 BUS_DMA_NOWAIT)) { 2848 aprint_error_dev(sc->bge_dev, 2849 "can't map DMA buffers (%zu bytes)\n", 2850 sizeof(struct bge_ring_data)); 2851 bus_dmamem_free(sc->bge_dmatag, &seg, rseg); 2852 return; 2853 } 2854 DPRINTFN(5, ("bus_dmamem_create\n")); 2855 if (bus_dmamap_create(sc->bge_dmatag, sizeof(struct bge_ring_data), 1, 2856 sizeof(struct bge_ring_data), 0, 2857 BUS_DMA_NOWAIT, &sc->bge_ring_map)) { 2858 aprint_error_dev(sc->bge_dev, "can't create DMA map\n"); 2859 bus_dmamem_unmap(sc->bge_dmatag, kva, 2860 sizeof(struct bge_ring_data)); 2861 bus_dmamem_free(sc->bge_dmatag, &seg, rseg); 2862 return; 2863 } 2864 DPRINTFN(5, ("bus_dmamem_load\n")); 2865 if (bus_dmamap_load(sc->bge_dmatag, sc->bge_ring_map, kva, 2866 sizeof(struct bge_ring_data), NULL, 2867 BUS_DMA_NOWAIT)) { 2868 bus_dmamap_destroy(sc->bge_dmatag, sc->bge_ring_map); 2869 bus_dmamem_unmap(sc->bge_dmatag, kva, 2870 sizeof(struct bge_ring_data)); 2871 bus_dmamem_free(sc->bge_dmatag, &seg, rseg); 2872 return; 2873 } 2874 2875 DPRINTFN(5, ("bzero\n")); 2876 sc->bge_rdata = (struct bge_ring_data *)kva; 2877 2878 memset(sc->bge_rdata, 0, sizeof(struct bge_ring_data)); 2879 2880 /* Try to allocate memory for jumbo buffers. */ 2881 if (BGE_IS_JUMBO_CAPABLE(sc)) { 2882 if (bge_alloc_jumbo_mem(sc)) { 2883 aprint_error_dev(sc->bge_dev, 2884 "jumbo buffer allocation failed\n"); 2885 } else 2886 sc->ethercom.ec_capabilities |= ETHERCAP_JUMBO_MTU; 2887 } 2888 2889 /* Set default tuneable values. */ 2890 sc->bge_stat_ticks = BGE_TICKS_PER_SEC; 2891 sc->bge_rx_coal_ticks = 150; 2892 sc->bge_rx_max_coal_bds = 64; 2893 #ifdef ORIG_WPAUL_VALUES 2894 sc->bge_tx_coal_ticks = 150; 2895 sc->bge_tx_max_coal_bds = 128; 2896 #else 2897 sc->bge_tx_coal_ticks = 300; 2898 sc->bge_tx_max_coal_bds = 400; 2899 #endif 2900 if (BGE_IS_5705_PLUS(sc)) { 2901 sc->bge_tx_coal_ticks = (12 * 5); 2902 sc->bge_tx_max_coal_bds = (12 * 5); 2903 aprint_verbose_dev(sc->bge_dev, 2904 "setting short Tx thresholds\n"); 2905 } 2906 2907 if (BGE_IS_5705_PLUS(sc)) 2908 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT_5705; 2909 else 2910 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT; 2911 2912 /* Set up ifnet structure */ 2913 ifp = &sc->ethercom.ec_if; 2914 ifp->if_softc = sc; 2915 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 2916 ifp->if_ioctl = bge_ioctl; 2917 ifp->if_stop = bge_stop; 2918 ifp->if_start = bge_start; 2919 ifp->if_init = bge_init; 2920 ifp->if_watchdog = bge_watchdog; 2921 IFQ_SET_MAXLEN(&ifp->if_snd, max(BGE_TX_RING_CNT - 1, IFQ_MAXLEN)); 2922 IFQ_SET_READY(&ifp->if_snd); 2923 DPRINTFN(5, ("strcpy if_xname\n")); 2924 strcpy(ifp->if_xname, device_xname(sc->bge_dev)); 2925 2926 if (sc->bge_chipid != BGE_CHIPID_BCM5700_B0) 2927 sc->ethercom.ec_if.if_capabilities |= 2928 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx; 2929 #if 1 /* XXX TCP/UDP checksum offload breaks with pf(4) */ 2930 sc->ethercom.ec_if.if_capabilities |= 2931 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 2932 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 2933 #endif 2934 sc->ethercom.ec_capabilities |= 2935 ETHERCAP_VLAN_HWTAGGING | ETHERCAP_VLAN_MTU; 2936 2937 if (sc->bge_flags & BGE_TSO) 2938 sc->ethercom.ec_if.if_capabilities |= IFCAP_TSOv4; 2939 2940 /* 2941 * Do MII setup. 2942 */ 2943 DPRINTFN(5, ("mii setup\n")); 2944 sc->bge_mii.mii_ifp = ifp; 2945 sc->bge_mii.mii_readreg = bge_miibus_readreg; 2946 sc->bge_mii.mii_writereg = bge_miibus_writereg; 2947 sc->bge_mii.mii_statchg = bge_miibus_statchg; 2948 2949 /* 2950 * Figure out what sort of media we have by checking the 2951 * hardware config word in the first 32k of NIC internal memory, 2952 * or fall back to the config word in the EEPROM. Note: on some BCM5700 2953 * cards, this value appears to be unset. If that's the 2954 * case, we have to rely on identifying the NIC by its PCI 2955 * subsystem ID, as we do below for the SysKonnect SK-9D41. 2956 */ 2957 if (bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_SIG) == BGE_MAGIC_NUMBER) { 2958 hwcfg = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_NICCFG); 2959 } else if (!(sc->bge_flags & BGE_NO_EEPROM)) { 2960 bge_read_eeprom(sc, (void *)&hwcfg, 2961 BGE_EE_HWCFG_OFFSET, sizeof(hwcfg)); 2962 hwcfg = be32toh(hwcfg); 2963 } 2964 /* The SysKonnect SK-9D41 is a 1000baseSX card. */ 2965 if (PCI_PRODUCT(pa->pa_id) == SK_SUBSYSID_9D41 || 2966 (hwcfg & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER) { 2967 if (BGE_IS_5714_FAMILY(sc)) 2968 sc->bge_flags |= BGE_PHY_FIBER_MII; 2969 else 2970 sc->bge_flags |= BGE_PHY_FIBER_TBI; 2971 } 2972 2973 /* set phyflags and chipid before mii_attach() */ 2974 dict = device_properties(self); 2975 prop_dictionary_set_uint32(dict, "phyflags", sc->bge_flags); 2976 prop_dictionary_set_uint32(dict, "chipid", sc->bge_chipid); 2977 2978 if (sc->bge_flags & BGE_PHY_FIBER_TBI) { 2979 ifmedia_init(&sc->bge_ifmedia, IFM_IMASK, bge_ifmedia_upd, 2980 bge_ifmedia_sts); 2981 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER |IFM_1000_SX, 0, NULL); 2982 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_1000_SX|IFM_FDX, 2983 0, NULL); 2984 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_AUTO, 0, NULL); 2985 ifmedia_set(&sc->bge_ifmedia, IFM_ETHER | IFM_AUTO); 2986 /* Pretend the user requested this setting */ 2987 sc->bge_ifmedia.ifm_media = sc->bge_ifmedia.ifm_cur->ifm_media; 2988 } else { 2989 /* 2990 * Do transceiver setup and tell the firmware the 2991 * driver is down so we can try to get access the 2992 * probe if ASF is running. Retry a couple of times 2993 * if we get a conflict with the ASF firmware accessing 2994 * the PHY. 2995 */ 2996 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 2997 bge_asf_driver_up(sc); 2998 2999 ifmedia_init(&sc->bge_mii.mii_media, 0, bge_ifmedia_upd, 3000 bge_ifmedia_sts); 3001 mii_attach(sc->bge_dev, &sc->bge_mii, 0xffffffff, 3002 MII_PHY_ANY, MII_OFFSET_ANY, 3003 MIIF_FORCEANEG|MIIF_DOPAUSE); 3004 3005 if (LIST_EMPTY(&sc->bge_mii.mii_phys)) { 3006 aprint_error_dev(sc->bge_dev, "no PHY found!\n"); 3007 ifmedia_add(&sc->bge_mii.mii_media, 3008 IFM_ETHER|IFM_MANUAL, 0, NULL); 3009 ifmedia_set(&sc->bge_mii.mii_media, 3010 IFM_ETHER|IFM_MANUAL); 3011 } else 3012 ifmedia_set(&sc->bge_mii.mii_media, 3013 IFM_ETHER|IFM_AUTO); 3014 3015 /* 3016 * Now tell the firmware we are going up after probing the PHY 3017 */ 3018 if (sc->bge_asf_mode & ASF_STACKUP) 3019 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 3020 } 3021 3022 /* 3023 * Call MI attach routine. 3024 */ 3025 DPRINTFN(5, ("if_attach\n")); 3026 if_attach(ifp); 3027 DPRINTFN(5, ("ether_ifattach\n")); 3028 ether_ifattach(ifp, eaddr); 3029 ether_set_ifflags_cb(&sc->ethercom, bge_ifflags_cb); 3030 rnd_attach_source(&sc->rnd_source, device_xname(sc->bge_dev), 3031 RND_TYPE_NET, 0); 3032 #ifdef BGE_EVENT_COUNTERS 3033 /* 3034 * Attach event counters. 3035 */ 3036 evcnt_attach_dynamic(&sc->bge_ev_intr, EVCNT_TYPE_INTR, 3037 NULL, device_xname(sc->bge_dev), "intr"); 3038 evcnt_attach_dynamic(&sc->bge_ev_tx_xoff, EVCNT_TYPE_MISC, 3039 NULL, device_xname(sc->bge_dev), "tx_xoff"); 3040 evcnt_attach_dynamic(&sc->bge_ev_tx_xon, EVCNT_TYPE_MISC, 3041 NULL, device_xname(sc->bge_dev), "tx_xon"); 3042 evcnt_attach_dynamic(&sc->bge_ev_rx_xoff, EVCNT_TYPE_MISC, 3043 NULL, device_xname(sc->bge_dev), "rx_xoff"); 3044 evcnt_attach_dynamic(&sc->bge_ev_rx_xon, EVCNT_TYPE_MISC, 3045 NULL, device_xname(sc->bge_dev), "rx_xon"); 3046 evcnt_attach_dynamic(&sc->bge_ev_rx_macctl, EVCNT_TYPE_MISC, 3047 NULL, device_xname(sc->bge_dev), "rx_macctl"); 3048 evcnt_attach_dynamic(&sc->bge_ev_xoffentered, EVCNT_TYPE_MISC, 3049 NULL, device_xname(sc->bge_dev), "xoffentered"); 3050 #endif /* BGE_EVENT_COUNTERS */ 3051 DPRINTFN(5, ("callout_init\n")); 3052 callout_init(&sc->bge_timeout, 0); 3053 3054 if (pmf_device_register(self, NULL, NULL)) 3055 pmf_class_network_register(self, ifp); 3056 else 3057 aprint_error_dev(self, "couldn't establish power handler\n"); 3058 3059 sysctl_bge_init(sc); 3060 3061 #ifdef BGE_DEBUG 3062 bge_debug_info(sc); 3063 #endif 3064 } 3065 3066 static void 3067 bge_release_resources(struct bge_softc *sc) 3068 { 3069 if (sc->bge_vpd_prodname != NULL) 3070 free(sc->bge_vpd_prodname, M_DEVBUF); 3071 3072 if (sc->bge_vpd_readonly != NULL) 3073 free(sc->bge_vpd_readonly, M_DEVBUF); 3074 } 3075 3076 static int 3077 bge_reset(struct bge_softc *sc) 3078 { 3079 uint32_t cachesize, command, pcistate, marbmode; 3080 #if 0 3081 uint32_t new_pcistate; 3082 #endif 3083 pcireg_t devctl, reg; 3084 int i, val; 3085 void (*write_op)(struct bge_softc *, int, int); 3086 3087 if (BGE_IS_5750_OR_BEYOND(sc) && !BGE_IS_5714_FAMILY(sc) 3088 && (BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5906)) { 3089 if (sc->bge_flags & BGE_PCIE) 3090 write_op = bge_writemem_direct; 3091 else 3092 write_op = bge_writemem_ind; 3093 } else 3094 write_op = bge_writereg_ind; 3095 3096 /* Save some important PCI state. */ 3097 cachesize = pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CACHESZ); 3098 command = pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CMD); 3099 pcistate = pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_PCISTATE); 3100 3101 /* Step 5a: Enable memory arbiter. */ 3102 marbmode = 0; 3103 if (BGE_IS_5714_FAMILY(sc)) 3104 marbmode = CSR_READ_4(sc, BGE_MARB_MODE); 3105 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE | marbmode); 3106 3107 /* Step 5b-5d: */ 3108 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MISC_CTL, 3109 BGE_PCIMISCCTL_INDIRECT_ACCESS | BGE_PCIMISCCTL_MASK_PCI_INTR | 3110 BGE_HIF_SWAP_OPTIONS | BGE_PCIMISCCTL_PCISTATE_RW); 3111 3112 /* XXX ???: Disable fastboot on controllers that support it. */ 3113 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5752 || 3114 BGE_IS_5755_PLUS(sc)) 3115 CSR_WRITE_4(sc, BGE_FASTBOOT_PC, 0); 3116 3117 /* 3118 * Step 6: Write the magic number to SRAM at offset 0xB50. 3119 * When firmware finishes its initialization it will 3120 * write ~BGE_MAGIC_NUMBER to the same location. 3121 */ 3122 bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM, BGE_MAGIC_NUMBER); 3123 3124 /* Step 7: */ 3125 val = BGE_MISCCFG_RESET_CORE_CLOCKS | (65<<1); 3126 /* 3127 * XXX: from FreeBSD/Linux; no documentation 3128 */ 3129 if (sc->bge_flags & BGE_PCIE) { 3130 if (CSR_READ_4(sc, BGE_PCIE_CTL1) == 0x60) 3131 /* PCI Express 1.0 system */ 3132 CSR_WRITE_4(sc, BGE_PCIE_CTL1, 0x20); 3133 if (sc->bge_chipid != BGE_CHIPID_BCM5750_A0) { 3134 /* 3135 * Prevent PCI Express link training 3136 * during global reset. 3137 */ 3138 CSR_WRITE_4(sc, BGE_MISC_CFG, 1 << 29); 3139 val |= (1<<29); 3140 } 3141 } 3142 3143 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 3144 i = CSR_READ_4(sc, BGE_VCPU_STATUS); 3145 CSR_WRITE_4(sc, BGE_VCPU_STATUS, 3146 i | BGE_VCPU_STATUS_DRV_RESET); 3147 i = CSR_READ_4(sc, BGE_VCPU_EXT_CTRL); 3148 CSR_WRITE_4(sc, BGE_VCPU_EXT_CTRL, 3149 i & ~BGE_VCPU_EXT_CTRL_HALT_CPU); 3150 } 3151 3152 /* 3153 * Set GPHY Power Down Override to leave GPHY 3154 * powered up in D0 uninitialized. 3155 */ 3156 if (BGE_IS_5705_PLUS(sc)) 3157 val |= BGE_MISCCFG_KEEP_GPHY_POWER; 3158 3159 /* XXX 5721, 5751 and 5752 */ 3160 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5750) 3161 val |= BGE_MISCCFG_GRC_RESET_DISABLE; 3162 3163 /* Issue global reset */ 3164 write_op(sc, BGE_MISC_CFG, val); 3165 3166 /* Step 8: wait for complete */ 3167 if (sc->bge_flags & BGE_PCIE) 3168 delay(100*1000); /* too big */ 3169 else 3170 delay(100); 3171 3172 /* From Linux: dummy read to flush PCI posted writes */ 3173 reg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CMD); 3174 3175 /* Step 9-10: Reset some of the PCI state that got zapped by reset */ 3176 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MISC_CTL, 3177 BGE_PCIMISCCTL_INDIRECT_ACCESS | BGE_PCIMISCCTL_MASK_PCI_INTR | 3178 BGE_HIF_SWAP_OPTIONS | BGE_PCIMISCCTL_PCISTATE_RW 3179 | BGE_PCIMISCCTL_CLOCKCTL_RW); 3180 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CMD, command); 3181 write_op(sc, BGE_MISC_CFG, (65 << 1)); 3182 3183 /* Step 11: disable PCI-X Relaxed Ordering. */ 3184 if (sc->bge_flags & BGE_PCIX) { 3185 reg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, sc->bge_pcixcap 3186 + PCI_PCIX_CMD); 3187 pci_conf_write(sc->sc_pc, sc->sc_pcitag, sc->bge_pcixcap 3188 + PCI_PCIX_CMD, reg & ~PCI_PCIX_CMD_RELAXED_ORDER); 3189 } 3190 3191 if (sc->bge_flags & BGE_PCIE) { 3192 if (sc->bge_chipid == BGE_CHIPID_BCM5750_A0) { 3193 DELAY(500000); 3194 /* XXX: Magic Numbers */ 3195 reg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 3196 BGE_PCI_UNKNOWN0); 3197 pci_conf_write(sc->sc_pc, sc->sc_pcitag, 3198 BGE_PCI_UNKNOWN0, 3199 reg | (1 << 15)); 3200 } 3201 devctl = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 3202 sc->bge_pciecap + PCI_PCIE_DCSR); 3203 /* Clear enable no snoop and disable relaxed ordering. */ 3204 devctl &= ~(0x0010 | PCI_PCIE_DCSR_ENA_NO_SNOOP); 3205 /* Set PCIE max payload size to 128. */ 3206 devctl &= ~(0x00e0); 3207 /* Clear device status register. Write 1b to clear */ 3208 devctl |= PCI_PCIE_DCSR_URD | PCI_PCIE_DCSR_FED 3209 | PCI_PCIE_DCSR_NFED | PCI_PCIE_DCSR_CED; 3210 pci_conf_write(sc->sc_pc, sc->sc_pcitag, 3211 sc->bge_pciecap + PCI_PCIE_DCSR, devctl); 3212 } 3213 3214 /* Step 12: Enable memory arbiter. */ 3215 marbmode = 0; 3216 if (BGE_IS_5714_FAMILY(sc)) 3217 marbmode = CSR_READ_4(sc, BGE_MARB_MODE); 3218 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE | marbmode); 3219 3220 /* Step 17: Poll until the firmware initialization is complete */ 3221 bge_poll_fw(sc); 3222 3223 /* XXX 5721, 5751 and 5752 */ 3224 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5750) { 3225 /* Step 19: */ 3226 BGE_SETBIT(sc, BGE_TLP_CONTROL_REG, 1 << 29 | 1 << 25); 3227 /* Step 20: */ 3228 BGE_SETBIT(sc, BGE_TLP_CONTROL_REG, BGE_TLP_DATA_FIFO_PROTECT); 3229 } 3230 3231 /* 3232 * Step 18: wirte mac mode 3233 * XXX Write 0x0c for 5703S and 5704S 3234 */ 3235 CSR_WRITE_4(sc, BGE_MAC_MODE, 0); 3236 3237 3238 /* Step 21: 5822 B0 errata */ 3239 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5704_BX) { 3240 pcireg_t msidata; 3241 3242 msidata = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 3243 BGE_PCI_MSI_DATA); 3244 msidata |= ((1 << 13 | 1 << 12 | 1 << 10) << 16); 3245 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MSI_DATA, 3246 msidata); 3247 } 3248 3249 /* Step 23: restore cache line size */ 3250 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CACHESZ, cachesize); 3251 3252 #if 0 3253 /* 3254 * XXX Wait for the value of the PCISTATE register to 3255 * return to its original pre-reset state. This is a 3256 * fairly good indicator of reset completion. If we don't 3257 * wait for the reset to fully complete, trying to read 3258 * from the device's non-PCI registers may yield garbage 3259 * results. 3260 */ 3261 for (i = 0; i < BGE_TIMEOUT; i++) { 3262 new_pcistate = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 3263 BGE_PCI_PCISTATE); 3264 if ((new_pcistate & ~BGE_PCISTATE_RESERVED) == 3265 (pcistate & ~BGE_PCISTATE_RESERVED)) 3266 break; 3267 DELAY(10); 3268 } 3269 if ((new_pcistate & ~BGE_PCISTATE_RESERVED) != 3270 (pcistate & ~BGE_PCISTATE_RESERVED)) { 3271 aprint_error_dev(sc->bge_dev, "pcistate failed to revert\n"); 3272 } 3273 #endif 3274 3275 /* Step 28: Fix up byte swapping */ 3276 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS); 3277 3278 /* Tell the ASF firmware we are up */ 3279 if (sc->bge_asf_mode & ASF_STACKUP) 3280 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 3281 3282 /* 3283 * The 5704 in TBI mode apparently needs some special 3284 * adjustment to insure the SERDES drive level is set 3285 * to 1.2V. 3286 */ 3287 if (sc->bge_flags & BGE_PHY_FIBER_TBI && 3288 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) { 3289 uint32_t serdescfg; 3290 3291 serdescfg = CSR_READ_4(sc, BGE_SERDES_CFG); 3292 serdescfg = (serdescfg & ~0xFFF) | 0x880; 3293 CSR_WRITE_4(sc, BGE_SERDES_CFG, serdescfg); 3294 } 3295 3296 if (sc->bge_flags & BGE_PCIE && 3297 sc->bge_chipid != BGE_CHIPID_BCM5750_A0 && 3298 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5717 && 3299 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5785 && 3300 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM57765) { 3301 uint32_t v; 3302 3303 /* Enable PCI Express bug fix */ 3304 v = CSR_READ_4(sc, 0x7c00); 3305 CSR_WRITE_4(sc, 0x7c00, v | (1<<25)); 3306 } 3307 DELAY(10000); 3308 3309 return 0; 3310 } 3311 3312 /* 3313 * Frame reception handling. This is called if there's a frame 3314 * on the receive return list. 3315 * 3316 * Note: we have to be able to handle two possibilities here: 3317 * 1) the frame is from the jumbo receive ring 3318 * 2) the frame is from the standard receive ring 3319 */ 3320 3321 static void 3322 bge_rxeof(struct bge_softc *sc) 3323 { 3324 struct ifnet *ifp; 3325 uint16_t rx_prod, rx_cons; 3326 int stdcnt = 0, jumbocnt = 0; 3327 bus_dmamap_t dmamap; 3328 bus_addr_t offset, toff; 3329 bus_size_t tlen; 3330 int tosync; 3331 3332 rx_cons = sc->bge_rx_saved_considx; 3333 rx_prod = sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx; 3334 3335 /* Nothing to do */ 3336 if (rx_cons == rx_prod) 3337 return; 3338 3339 ifp = &sc->ethercom.ec_if; 3340 3341 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 3342 offsetof(struct bge_ring_data, bge_status_block), 3343 sizeof (struct bge_status_block), 3344 BUS_DMASYNC_POSTREAD); 3345 3346 offset = offsetof(struct bge_ring_data, bge_rx_return_ring); 3347 tosync = rx_prod - rx_cons; 3348 3349 if (tosync != 0) 3350 rnd_add_uint32(&sc->rnd_source, tosync); 3351 3352 toff = offset + (rx_cons * sizeof (struct bge_rx_bd)); 3353 3354 if (tosync < 0) { 3355 tlen = (sc->bge_return_ring_cnt - rx_cons) * 3356 sizeof (struct bge_rx_bd); 3357 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 3358 toff, tlen, BUS_DMASYNC_POSTREAD); 3359 tosync = -tosync; 3360 } 3361 3362 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 3363 offset, tosync * sizeof (struct bge_rx_bd), 3364 BUS_DMASYNC_POSTREAD); 3365 3366 while (rx_cons != rx_prod) { 3367 struct bge_rx_bd *cur_rx; 3368 uint32_t rxidx; 3369 struct mbuf *m = NULL; 3370 3371 cur_rx = &sc->bge_rdata->bge_rx_return_ring[rx_cons]; 3372 3373 rxidx = cur_rx->bge_idx; 3374 BGE_INC(rx_cons, sc->bge_return_ring_cnt); 3375 3376 if (cur_rx->bge_flags & BGE_RXBDFLAG_JUMBO_RING) { 3377 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT); 3378 m = sc->bge_cdata.bge_rx_jumbo_chain[rxidx]; 3379 sc->bge_cdata.bge_rx_jumbo_chain[rxidx] = NULL; 3380 jumbocnt++; 3381 bus_dmamap_sync(sc->bge_dmatag, 3382 sc->bge_cdata.bge_rx_jumbo_map, 3383 mtod(m, char *) - (char *)sc->bge_cdata.bge_jumbo_buf, 3384 BGE_JLEN, BUS_DMASYNC_POSTREAD); 3385 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 3386 ifp->if_ierrors++; 3387 bge_newbuf_jumbo(sc, sc->bge_jumbo, m); 3388 continue; 3389 } 3390 if (bge_newbuf_jumbo(sc, sc->bge_jumbo, 3391 NULL)== ENOBUFS) { 3392 ifp->if_ierrors++; 3393 bge_newbuf_jumbo(sc, sc->bge_jumbo, m); 3394 continue; 3395 } 3396 } else { 3397 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT); 3398 m = sc->bge_cdata.bge_rx_std_chain[rxidx]; 3399 3400 sc->bge_cdata.bge_rx_std_chain[rxidx] = NULL; 3401 stdcnt++; 3402 dmamap = sc->bge_cdata.bge_rx_std_map[rxidx]; 3403 sc->bge_cdata.bge_rx_std_map[rxidx] = 0; 3404 if (dmamap == NULL) { 3405 ifp->if_ierrors++; 3406 bge_newbuf_std(sc, sc->bge_std, m, dmamap); 3407 continue; 3408 } 3409 bus_dmamap_sync(sc->bge_dmatag, dmamap, 0, 3410 dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 3411 bus_dmamap_unload(sc->bge_dmatag, dmamap); 3412 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 3413 ifp->if_ierrors++; 3414 bge_newbuf_std(sc, sc->bge_std, m, dmamap); 3415 continue; 3416 } 3417 if (bge_newbuf_std(sc, sc->bge_std, 3418 NULL, dmamap) == ENOBUFS) { 3419 ifp->if_ierrors++; 3420 bge_newbuf_std(sc, sc->bge_std, m, dmamap); 3421 continue; 3422 } 3423 } 3424 3425 ifp->if_ipackets++; 3426 #ifndef __NO_STRICT_ALIGNMENT 3427 /* 3428 * XXX: if the 5701 PCIX-Rx-DMA workaround is in effect, 3429 * the Rx buffer has the layer-2 header unaligned. 3430 * If our CPU requires alignment, re-align by copying. 3431 */ 3432 if (sc->bge_flags & BGE_RX_ALIGNBUG) { 3433 memmove(mtod(m, char *) + ETHER_ALIGN, m->m_data, 3434 cur_rx->bge_len); 3435 m->m_data += ETHER_ALIGN; 3436 } 3437 #endif 3438 3439 m->m_pkthdr.len = m->m_len = cur_rx->bge_len - ETHER_CRC_LEN; 3440 m->m_pkthdr.rcvif = ifp; 3441 3442 /* 3443 * Handle BPF listeners. Let the BPF user see the packet. 3444 */ 3445 bpf_mtap(ifp, m); 3446 3447 m->m_pkthdr.csum_flags = M_CSUM_IPv4; 3448 3449 if ((cur_rx->bge_ip_csum ^ 0xffff) != 0) 3450 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 3451 /* 3452 * Rx transport checksum-offload may also 3453 * have bugs with packets which, when transmitted, 3454 * were `runts' requiring padding. 3455 */ 3456 if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM && 3457 (/* (sc->_bge_quirks & BGE_QUIRK_SHORT_CKSUM_BUG) == 0 ||*/ 3458 m->m_pkthdr.len >= ETHER_MIN_NOPAD)) { 3459 m->m_pkthdr.csum_data = 3460 cur_rx->bge_tcp_udp_csum; 3461 m->m_pkthdr.csum_flags |= 3462 (M_CSUM_TCPv4|M_CSUM_UDPv4| 3463 M_CSUM_DATA); 3464 } 3465 3466 /* 3467 * If we received a packet with a vlan tag, pass it 3468 * to vlan_input() instead of ether_input(). 3469 */ 3470 if (cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) { 3471 VLAN_INPUT_TAG(ifp, m, cur_rx->bge_vlan_tag, continue); 3472 } 3473 3474 (*ifp->if_input)(ifp, m); 3475 } 3476 3477 sc->bge_rx_saved_considx = rx_cons; 3478 bge_writembx(sc, BGE_MBX_RX_CONS0_LO, sc->bge_rx_saved_considx); 3479 if (stdcnt) 3480 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std); 3481 if (jumbocnt) 3482 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo); 3483 } 3484 3485 static void 3486 bge_txeof(struct bge_softc *sc) 3487 { 3488 struct bge_tx_bd *cur_tx = NULL; 3489 struct ifnet *ifp; 3490 struct txdmamap_pool_entry *dma; 3491 bus_addr_t offset, toff; 3492 bus_size_t tlen; 3493 int tosync; 3494 struct mbuf *m; 3495 3496 ifp = &sc->ethercom.ec_if; 3497 3498 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 3499 offsetof(struct bge_ring_data, bge_status_block), 3500 sizeof (struct bge_status_block), 3501 BUS_DMASYNC_POSTREAD); 3502 3503 offset = offsetof(struct bge_ring_data, bge_tx_ring); 3504 tosync = sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx - 3505 sc->bge_tx_saved_considx; 3506 3507 if (tosync != 0) 3508 rnd_add_uint32(&sc->rnd_source, tosync); 3509 3510 toff = offset + (sc->bge_tx_saved_considx * sizeof (struct bge_tx_bd)); 3511 3512 if (tosync < 0) { 3513 tlen = (BGE_TX_RING_CNT - sc->bge_tx_saved_considx) * 3514 sizeof (struct bge_tx_bd); 3515 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 3516 toff, tlen, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 3517 tosync = -tosync; 3518 } 3519 3520 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 3521 offset, tosync * sizeof (struct bge_tx_bd), 3522 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 3523 3524 /* 3525 * Go through our tx ring and free mbufs for those 3526 * frames that have been sent. 3527 */ 3528 while (sc->bge_tx_saved_considx != 3529 sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx) { 3530 uint32_t idx = 0; 3531 3532 idx = sc->bge_tx_saved_considx; 3533 cur_tx = &sc->bge_rdata->bge_tx_ring[idx]; 3534 if (cur_tx->bge_flags & BGE_TXBDFLAG_END) 3535 ifp->if_opackets++; 3536 m = sc->bge_cdata.bge_tx_chain[idx]; 3537 if (m != NULL) { 3538 sc->bge_cdata.bge_tx_chain[idx] = NULL; 3539 dma = sc->txdma[idx]; 3540 bus_dmamap_sync(sc->bge_dmatag, dma->dmamap, 0, 3541 dma->dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 3542 bus_dmamap_unload(sc->bge_dmatag, dma->dmamap); 3543 SLIST_INSERT_HEAD(&sc->txdma_list, dma, link); 3544 sc->txdma[idx] = NULL; 3545 3546 m_freem(m); 3547 } 3548 sc->bge_txcnt--; 3549 BGE_INC(sc->bge_tx_saved_considx, BGE_TX_RING_CNT); 3550 ifp->if_timer = 0; 3551 } 3552 3553 if (cur_tx != NULL) 3554 ifp->if_flags &= ~IFF_OACTIVE; 3555 } 3556 3557 static int 3558 bge_intr(void *xsc) 3559 { 3560 struct bge_softc *sc; 3561 struct ifnet *ifp; 3562 uint32_t statusword; 3563 3564 sc = xsc; 3565 ifp = &sc->ethercom.ec_if; 3566 3567 /* It is possible for the interrupt to arrive before 3568 * the status block is updated prior to the interrupt. 3569 * Reading the PCI State register will confirm whether the 3570 * interrupt is ours and will flush the status block. 3571 */ 3572 3573 /* read status word from status block */ 3574 statusword = sc->bge_rdata->bge_status_block.bge_status; 3575 3576 if ((statusword & BGE_STATFLAG_UPDATED) || 3577 (!(CSR_READ_4(sc, BGE_PCI_PCISTATE) & BGE_PCISTATE_INTR_NOT_ACTIVE))) { 3578 /* Ack interrupt and stop others from occuring. */ 3579 bge_writembx(sc, BGE_MBX_IRQ0_LO, 1); 3580 3581 BGE_EVCNT_INCR(sc->bge_ev_intr); 3582 3583 /* clear status word */ 3584 sc->bge_rdata->bge_status_block.bge_status = 0; 3585 3586 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 3587 statusword & BGE_STATFLAG_LINKSTATE_CHANGED || 3588 BGE_STS_BIT(sc, BGE_STS_LINK_EVT)) 3589 bge_link_upd(sc); 3590 3591 if (ifp->if_flags & IFF_RUNNING) { 3592 /* Check RX return ring producer/consumer */ 3593 bge_rxeof(sc); 3594 3595 /* Check TX ring producer/consumer */ 3596 bge_txeof(sc); 3597 } 3598 3599 if (sc->bge_pending_rxintr_change) { 3600 uint32_t rx_ticks = sc->bge_rx_coal_ticks; 3601 uint32_t rx_bds = sc->bge_rx_max_coal_bds; 3602 uint32_t junk; 3603 3604 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, rx_ticks); 3605 DELAY(10); 3606 junk = CSR_READ_4(sc, BGE_HCC_RX_COAL_TICKS); 3607 3608 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, rx_bds); 3609 DELAY(10); 3610 junk = CSR_READ_4(sc, BGE_HCC_RX_MAX_COAL_BDS); 3611 3612 sc->bge_pending_rxintr_change = 0; 3613 } 3614 bge_handle_events(sc); 3615 3616 /* Re-enable interrupts. */ 3617 bge_writembx(sc, BGE_MBX_IRQ0_LO, 0); 3618 3619 if (ifp->if_flags & IFF_RUNNING && !IFQ_IS_EMPTY(&ifp->if_snd)) 3620 bge_start(ifp); 3621 3622 return 1; 3623 } else 3624 return 0; 3625 } 3626 3627 static void 3628 bge_asf_driver_up(struct bge_softc *sc) 3629 { 3630 if (sc->bge_asf_mode & ASF_STACKUP) { 3631 /* Send ASF heartbeat aprox. every 2s */ 3632 if (sc->bge_asf_count) 3633 sc->bge_asf_count --; 3634 else { 3635 sc->bge_asf_count = 2; 3636 bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM_FW, 3637 BGE_FW_DRV_ALIVE); 3638 bge_writemem_ind(sc, BGE_SOFTWARE_GENNCOMM_FW_LEN, 4); 3639 bge_writemem_ind(sc, BGE_SOFTWARE_GENNCOMM_FW_DATA, 3); 3640 CSR_WRITE_4(sc, BGE_CPU_EVENT, 3641 CSR_READ_4(sc, BGE_CPU_EVENT) | (1 << 14)); 3642 } 3643 } 3644 } 3645 3646 static void 3647 bge_tick(void *xsc) 3648 { 3649 struct bge_softc *sc = xsc; 3650 struct mii_data *mii = &sc->bge_mii; 3651 int s; 3652 3653 s = splnet(); 3654 3655 if (BGE_IS_5705_PLUS(sc)) 3656 bge_stats_update_regs(sc); 3657 else 3658 bge_stats_update(sc); 3659 3660 if (sc->bge_flags & BGE_PHY_FIBER_TBI) { 3661 /* 3662 * Since in TBI mode auto-polling can't be used we should poll 3663 * link status manually. Here we register pending link event 3664 * and trigger interrupt. 3665 */ 3666 BGE_STS_SETBIT(sc, BGE_STS_LINK_EVT); 3667 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET); 3668 } else { 3669 /* 3670 * Do not touch PHY if we have link up. This could break 3671 * IPMI/ASF mode or produce extra input errors. 3672 * (extra input errors was reported for bcm5701 & bcm5704). 3673 */ 3674 if (!BGE_STS_BIT(sc, BGE_STS_LINK)) 3675 mii_tick(mii); 3676 } 3677 3678 callout_reset(&sc->bge_timeout, hz, bge_tick, sc); 3679 3680 splx(s); 3681 } 3682 3683 static void 3684 bge_stats_update_regs(struct bge_softc *sc) 3685 { 3686 struct ifnet *ifp = &sc->ethercom.ec_if; 3687 3688 ifp->if_collisions += CSR_READ_4(sc, BGE_MAC_STATS + 3689 offsetof(struct bge_mac_stats_regs, etherStatsCollisions)); 3690 3691 ifp->if_ierrors += CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_DROPS); 3692 ifp->if_ierrors += CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_ERRORS); 3693 ifp->if_ierrors += CSR_READ_4(sc, BGE_RXLP_LOCSTAT_OUT_OF_BDS); 3694 } 3695 3696 static void 3697 bge_stats_update(struct bge_softc *sc) 3698 { 3699 struct ifnet *ifp = &sc->ethercom.ec_if; 3700 bus_size_t stats = BGE_MEMWIN_START + BGE_STATS_BLOCK; 3701 3702 #define READ_STAT(sc, stats, stat) \ 3703 CSR_READ_4(sc, stats + offsetof(struct bge_stats, stat)) 3704 3705 ifp->if_collisions += 3706 (READ_STAT(sc, stats, dot3StatsSingleCollisionFrames.bge_addr_lo) + 3707 READ_STAT(sc, stats, dot3StatsMultipleCollisionFrames.bge_addr_lo) + 3708 READ_STAT(sc, stats, dot3StatsExcessiveCollisions.bge_addr_lo) + 3709 READ_STAT(sc, stats, dot3StatsLateCollisions.bge_addr_lo)) - 3710 ifp->if_collisions; 3711 3712 BGE_EVCNT_UPD(sc->bge_ev_tx_xoff, 3713 READ_STAT(sc, stats, outXoffSent.bge_addr_lo)); 3714 BGE_EVCNT_UPD(sc->bge_ev_tx_xon, 3715 READ_STAT(sc, stats, outXonSent.bge_addr_lo)); 3716 BGE_EVCNT_UPD(sc->bge_ev_rx_xoff, 3717 READ_STAT(sc, stats, 3718 xoffPauseFramesReceived.bge_addr_lo)); 3719 BGE_EVCNT_UPD(sc->bge_ev_rx_xon, 3720 READ_STAT(sc, stats, xonPauseFramesReceived.bge_addr_lo)); 3721 BGE_EVCNT_UPD(sc->bge_ev_rx_macctl, 3722 READ_STAT(sc, stats, 3723 macControlFramesReceived.bge_addr_lo)); 3724 BGE_EVCNT_UPD(sc->bge_ev_xoffentered, 3725 READ_STAT(sc, stats, xoffStateEntered.bge_addr_lo)); 3726 3727 #undef READ_STAT 3728 3729 #ifdef notdef 3730 ifp->if_collisions += 3731 (sc->bge_rdata->bge_info.bge_stats.dot3StatsSingleCollisionFrames + 3732 sc->bge_rdata->bge_info.bge_stats.dot3StatsMultipleCollisionFrames + 3733 sc->bge_rdata->bge_info.bge_stats.dot3StatsExcessiveCollisions + 3734 sc->bge_rdata->bge_info.bge_stats.dot3StatsLateCollisions) - 3735 ifp->if_collisions; 3736 #endif 3737 } 3738 3739 /* 3740 * Pad outbound frame to ETHER_MIN_NOPAD for an unusual reason. 3741 * The bge hardware will pad out Tx runts to ETHER_MIN_NOPAD, 3742 * but when such padded frames employ the bge IP/TCP checksum offload, 3743 * the hardware checksum assist gives incorrect results (possibly 3744 * from incorporating its own padding into the UDP/TCP checksum; who knows). 3745 * If we pad such runts with zeros, the onboard checksum comes out correct. 3746 */ 3747 static inline int 3748 bge_cksum_pad(struct mbuf *pkt) 3749 { 3750 struct mbuf *last = NULL; 3751 int padlen; 3752 3753 padlen = ETHER_MIN_NOPAD - pkt->m_pkthdr.len; 3754 3755 /* if there's only the packet-header and we can pad there, use it. */ 3756 if (pkt->m_pkthdr.len == pkt->m_len && 3757 M_TRAILINGSPACE(pkt) >= padlen) { 3758 last = pkt; 3759 } else { 3760 /* 3761 * Walk packet chain to find last mbuf. We will either 3762 * pad there, or append a new mbuf and pad it 3763 * (thus perhaps avoiding the bcm5700 dma-min bug). 3764 */ 3765 for (last = pkt; last->m_next != NULL; last = last->m_next) { 3766 continue; /* do nothing */ 3767 } 3768 3769 /* `last' now points to last in chain. */ 3770 if (M_TRAILINGSPACE(last) < padlen) { 3771 /* Allocate new empty mbuf, pad it. Compact later. */ 3772 struct mbuf *n; 3773 MGET(n, M_DONTWAIT, MT_DATA); 3774 if (n == NULL) 3775 return ENOBUFS; 3776 n->m_len = 0; 3777 last->m_next = n; 3778 last = n; 3779 } 3780 } 3781 3782 KDASSERT(!M_READONLY(last)); 3783 KDASSERT(M_TRAILINGSPACE(last) >= padlen); 3784 3785 /* Now zero the pad area, to avoid the bge cksum-assist bug */ 3786 memset(mtod(last, char *) + last->m_len, 0, padlen); 3787 last->m_len += padlen; 3788 pkt->m_pkthdr.len += padlen; 3789 return 0; 3790 } 3791 3792 /* 3793 * Compact outbound packets to avoid bug with DMA segments less than 8 bytes. 3794 */ 3795 static inline int 3796 bge_compact_dma_runt(struct mbuf *pkt) 3797 { 3798 struct mbuf *m, *prev; 3799 int totlen, prevlen; 3800 3801 prev = NULL; 3802 totlen = 0; 3803 prevlen = -1; 3804 3805 for (m = pkt; m != NULL; prev = m,m = m->m_next) { 3806 int mlen = m->m_len; 3807 int shortfall = 8 - mlen ; 3808 3809 totlen += mlen; 3810 if (mlen == 0) { 3811 continue; 3812 } 3813 if (mlen >= 8) 3814 continue; 3815 3816 /* If we get here, mbuf data is too small for DMA engine. 3817 * Try to fix by shuffling data to prev or next in chain. 3818 * If that fails, do a compacting deep-copy of the whole chain. 3819 */ 3820 3821 /* Internal frag. If fits in prev, copy it there. */ 3822 if (prev && M_TRAILINGSPACE(prev) >= m->m_len) { 3823 memcpy(prev->m_data + prev->m_len, m->m_data, mlen); 3824 prev->m_len += mlen; 3825 m->m_len = 0; 3826 /* XXX stitch chain */ 3827 prev->m_next = m_free(m); 3828 m = prev; 3829 continue; 3830 } 3831 else if (m->m_next != NULL && 3832 M_TRAILINGSPACE(m) >= shortfall && 3833 m->m_next->m_len >= (8 + shortfall)) { 3834 /* m is writable and have enough data in next, pull up. */ 3835 3836 memcpy(m->m_data + m->m_len, m->m_next->m_data, 3837 shortfall); 3838 m->m_len += shortfall; 3839 m->m_next->m_len -= shortfall; 3840 m->m_next->m_data += shortfall; 3841 } 3842 else if (m->m_next == NULL || 1) { 3843 /* Got a runt at the very end of the packet. 3844 * borrow data from the tail of the preceding mbuf and 3845 * update its length in-place. (The original data is still 3846 * valid, so we can do this even if prev is not writable.) 3847 */ 3848 3849 /* if we'd make prev a runt, just move all of its data. */ 3850 KASSERT(prev != NULL /*, ("runt but null PREV")*/); 3851 KASSERT(prev->m_len >= 8 /*, ("runt prev")*/); 3852 3853 if ((prev->m_len - shortfall) < 8) 3854 shortfall = prev->m_len; 3855 3856 #ifdef notyet /* just do the safe slow thing for now */ 3857 if (!M_READONLY(m)) { 3858 if (M_LEADINGSPACE(m) < shorfall) { 3859 void *m_dat; 3860 m_dat = (m->m_flags & M_PKTHDR) ? 3861 m->m_pktdat : m->dat; 3862 memmove(m_dat, mtod(m, void*), m->m_len); 3863 m->m_data = m_dat; 3864 } 3865 } else 3866 #endif /* just do the safe slow thing */ 3867 { 3868 struct mbuf * n = NULL; 3869 int newprevlen = prev->m_len - shortfall; 3870 3871 MGET(n, M_NOWAIT, MT_DATA); 3872 if (n == NULL) 3873 return ENOBUFS; 3874 KASSERT(m->m_len + shortfall < MLEN 3875 /*, 3876 ("runt %d +prev %d too big\n", m->m_len, shortfall)*/); 3877 3878 /* first copy the data we're stealing from prev */ 3879 memcpy(n->m_data, prev->m_data + newprevlen, 3880 shortfall); 3881 3882 /* update prev->m_len accordingly */ 3883 prev->m_len -= shortfall; 3884 3885 /* copy data from runt m */ 3886 memcpy(n->m_data + shortfall, m->m_data, 3887 m->m_len); 3888 3889 /* n holds what we stole from prev, plus m */ 3890 n->m_len = shortfall + m->m_len; 3891 3892 /* stitch n into chain and free m */ 3893 n->m_next = m->m_next; 3894 prev->m_next = n; 3895 /* KASSERT(m->m_next == NULL); */ 3896 m->m_next = NULL; 3897 m_free(m); 3898 m = n; /* for continuing loop */ 3899 } 3900 } 3901 prevlen = m->m_len; 3902 } 3903 return 0; 3904 } 3905 3906 /* 3907 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data 3908 * pointers to descriptors. 3909 */ 3910 static int 3911 bge_encap(struct bge_softc *sc, struct mbuf *m_head, uint32_t *txidx) 3912 { 3913 struct bge_tx_bd *f = NULL; 3914 uint32_t frag, cur; 3915 uint16_t csum_flags = 0; 3916 uint16_t txbd_tso_flags = 0; 3917 struct txdmamap_pool_entry *dma; 3918 bus_dmamap_t dmamap; 3919 int i = 0; 3920 struct m_tag *mtag; 3921 int use_tso, maxsegsize, error; 3922 3923 cur = frag = *txidx; 3924 3925 if (m_head->m_pkthdr.csum_flags) { 3926 if (m_head->m_pkthdr.csum_flags & M_CSUM_IPv4) 3927 csum_flags |= BGE_TXBDFLAG_IP_CSUM; 3928 if (m_head->m_pkthdr.csum_flags & (M_CSUM_TCPv4|M_CSUM_UDPv4)) 3929 csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM; 3930 } 3931 3932 /* 3933 * If we were asked to do an outboard checksum, and the NIC 3934 * has the bug where it sometimes adds in the Ethernet padding, 3935 * explicitly pad with zeros so the cksum will be correct either way. 3936 * (For now, do this for all chip versions, until newer 3937 * are confirmed to not require the workaround.) 3938 */ 3939 if ((csum_flags & BGE_TXBDFLAG_TCP_UDP_CSUM) == 0 || 3940 #ifdef notyet 3941 (sc->bge_quirks & BGE_QUIRK_SHORT_CKSUM_BUG) == 0 || 3942 #endif 3943 m_head->m_pkthdr.len >= ETHER_MIN_NOPAD) 3944 goto check_dma_bug; 3945 3946 if (bge_cksum_pad(m_head) != 0) 3947 return ENOBUFS; 3948 3949 check_dma_bug: 3950 if (!(BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX)) 3951 goto doit; 3952 3953 /* 3954 * bcm5700 Revision B silicon cannot handle DMA descriptors with 3955 * less than eight bytes. If we encounter a teeny mbuf 3956 * at the end of a chain, we can pad. Otherwise, copy. 3957 */ 3958 if (bge_compact_dma_runt(m_head) != 0) 3959 return ENOBUFS; 3960 3961 doit: 3962 dma = SLIST_FIRST(&sc->txdma_list); 3963 if (dma == NULL) 3964 return ENOBUFS; 3965 dmamap = dma->dmamap; 3966 3967 /* 3968 * Set up any necessary TSO state before we start packing... 3969 */ 3970 use_tso = (m_head->m_pkthdr.csum_flags & M_CSUM_TSOv4) != 0; 3971 if (!use_tso) { 3972 maxsegsize = 0; 3973 } else { /* TSO setup */ 3974 unsigned mss; 3975 struct ether_header *eh; 3976 unsigned ip_tcp_hlen, iptcp_opt_words, tcp_seg_flags, offset; 3977 struct mbuf * m0 = m_head; 3978 struct ip *ip; 3979 struct tcphdr *th; 3980 int iphl, hlen; 3981 3982 /* 3983 * XXX It would be nice if the mbuf pkthdr had offset 3984 * fields for the protocol headers. 3985 */ 3986 3987 eh = mtod(m0, struct ether_header *); 3988 switch (htons(eh->ether_type)) { 3989 case ETHERTYPE_IP: 3990 offset = ETHER_HDR_LEN; 3991 break; 3992 3993 case ETHERTYPE_VLAN: 3994 offset = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 3995 break; 3996 3997 default: 3998 /* 3999 * Don't support this protocol or encapsulation. 4000 */ 4001 return ENOBUFS; 4002 } 4003 4004 /* 4005 * TCP/IP headers are in the first mbuf; we can do 4006 * this the easy way. 4007 */ 4008 iphl = M_CSUM_DATA_IPv4_IPHL(m0->m_pkthdr.csum_data); 4009 hlen = iphl + offset; 4010 if (__predict_false(m0->m_len < 4011 (hlen + sizeof(struct tcphdr)))) { 4012 4013 aprint_debug_dev(sc->bge_dev, 4014 "TSO: hard case m0->m_len == %d < ip/tcp hlen %zd," 4015 "not handled yet\n", 4016 m0->m_len, hlen+ sizeof(struct tcphdr)); 4017 #ifdef NOTYET 4018 /* 4019 * XXX jonathan (at) NetBSD.org: untested. 4020 * how to force this branch to be taken? 4021 */ 4022 BGE_EVCNT_INCR(&sc->sc_ev_txtsopain); 4023 4024 m_copydata(m0, offset, sizeof(ip), &ip); 4025 m_copydata(m0, hlen, sizeof(th), &th); 4026 4027 ip.ip_len = 0; 4028 4029 m_copyback(m0, hlen + offsetof(struct ip, ip_len), 4030 sizeof(ip.ip_len), &ip.ip_len); 4031 4032 th.th_sum = in_cksum_phdr(ip.ip_src.s_addr, 4033 ip.ip_dst.s_addr, htons(IPPROTO_TCP)); 4034 4035 m_copyback(m0, hlen + offsetof(struct tcphdr, th_sum), 4036 sizeof(th.th_sum), &th.th_sum); 4037 4038 hlen += th.th_off << 2; 4039 iptcp_opt_words = hlen; 4040 #else 4041 /* 4042 * if_wm "hard" case not yet supported, can we not 4043 * mandate it out of existence? 4044 */ 4045 (void) ip; (void)th; (void) ip_tcp_hlen; 4046 4047 return ENOBUFS; 4048 #endif 4049 } else { 4050 ip = (struct ip *) (mtod(m0, char *) + offset); 4051 th = (struct tcphdr *) (mtod(m0, char *) + hlen); 4052 ip_tcp_hlen = iphl + (th->th_off << 2); 4053 4054 /* Total IP/TCP options, in 32-bit words */ 4055 iptcp_opt_words = (ip_tcp_hlen 4056 - sizeof(struct tcphdr) 4057 - sizeof(struct ip)) >> 2; 4058 } 4059 if (BGE_IS_5750_OR_BEYOND(sc)) { 4060 th->th_sum = 0; 4061 csum_flags &= ~(BGE_TXBDFLAG_TCP_UDP_CSUM); 4062 } else { 4063 /* 4064 * XXX jonathan (at) NetBSD.org: 5705 untested. 4065 * Requires TSO firmware patch for 5701/5703/5704. 4066 */ 4067 th->th_sum = in_cksum_phdr(ip->ip_src.s_addr, 4068 ip->ip_dst.s_addr, htons(IPPROTO_TCP)); 4069 } 4070 4071 mss = m_head->m_pkthdr.segsz; 4072 txbd_tso_flags |= 4073 BGE_TXBDFLAG_CPU_PRE_DMA | 4074 BGE_TXBDFLAG_CPU_POST_DMA; 4075 4076 /* 4077 * Our NIC TSO-assist assumes TSO has standard, optionless 4078 * IPv4 and TCP headers, which total 40 bytes. By default, 4079 * the NIC copies 40 bytes of IP/TCP header from the 4080 * supplied header into the IP/TCP header portion of 4081 * each post-TSO-segment. If the supplied packet has IP or 4082 * TCP options, we need to tell the NIC to copy those extra 4083 * bytes into each post-TSO header, in addition to the normal 4084 * 40-byte IP/TCP header (and to leave space accordingly). 4085 * Unfortunately, the driver encoding of option length 4086 * varies across different ASIC families. 4087 */ 4088 tcp_seg_flags = 0; 4089 if (iptcp_opt_words) { 4090 if (BGE_IS_5705_PLUS(sc)) { 4091 tcp_seg_flags = 4092 iptcp_opt_words << 11; 4093 } else { 4094 txbd_tso_flags |= 4095 iptcp_opt_words << 12; 4096 } 4097 } 4098 maxsegsize = mss | tcp_seg_flags; 4099 ip->ip_len = htons(mss + ip_tcp_hlen); 4100 4101 } /* TSO setup */ 4102 4103 /* 4104 * Start packing the mbufs in this chain into 4105 * the fragment pointers. Stop when we run out 4106 * of fragments or hit the end of the mbuf chain. 4107 */ 4108 error = bus_dmamap_load_mbuf(sc->bge_dmatag, dmamap, m_head, 4109 BUS_DMA_NOWAIT); 4110 if (error) 4111 return ENOBUFS; 4112 /* 4113 * Sanity check: avoid coming within 16 descriptors 4114 * of the end of the ring. 4115 */ 4116 if (dmamap->dm_nsegs > (BGE_TX_RING_CNT - sc->bge_txcnt - 16)) { 4117 BGE_TSO_PRINTF(("%s: " 4118 " dmamap_load_mbuf too close to ring wrap\n", 4119 device_xname(sc->bge_dev))); 4120 goto fail_unload; 4121 } 4122 4123 mtag = sc->ethercom.ec_nvlans ? 4124 m_tag_find(m_head, PACKET_TAG_VLAN, NULL) : NULL; 4125 4126 4127 /* Iterate over dmap-map fragments. */ 4128 for (i = 0; i < dmamap->dm_nsegs; i++) { 4129 f = &sc->bge_rdata->bge_tx_ring[frag]; 4130 if (sc->bge_cdata.bge_tx_chain[frag] != NULL) 4131 break; 4132 4133 BGE_HOSTADDR(f->bge_addr, dmamap->dm_segs[i].ds_addr); 4134 f->bge_len = dmamap->dm_segs[i].ds_len; 4135 4136 /* 4137 * For 5751 and follow-ons, for TSO we must turn 4138 * off checksum-assist flag in the tx-descr, and 4139 * supply the ASIC-revision-specific encoding 4140 * of TSO flags and segsize. 4141 */ 4142 if (use_tso) { 4143 if (BGE_IS_5750_OR_BEYOND(sc) || i == 0) { 4144 f->bge_rsvd = maxsegsize; 4145 f->bge_flags = csum_flags | txbd_tso_flags; 4146 } else { 4147 f->bge_rsvd = 0; 4148 f->bge_flags = 4149 (csum_flags | txbd_tso_flags) & 0x0fff; 4150 } 4151 } else { 4152 f->bge_rsvd = 0; 4153 f->bge_flags = csum_flags; 4154 } 4155 4156 if (mtag != NULL) { 4157 f->bge_flags |= BGE_TXBDFLAG_VLAN_TAG; 4158 f->bge_vlan_tag = VLAN_TAG_VALUE(mtag); 4159 } else { 4160 f->bge_vlan_tag = 0; 4161 } 4162 cur = frag; 4163 BGE_INC(frag, BGE_TX_RING_CNT); 4164 } 4165 4166 if (i < dmamap->dm_nsegs) { 4167 BGE_TSO_PRINTF(("%s: reached %d < dm_nsegs %d\n", 4168 device_xname(sc->bge_dev), i, dmamap->dm_nsegs)); 4169 goto fail_unload; 4170 } 4171 4172 bus_dmamap_sync(sc->bge_dmatag, dmamap, 0, dmamap->dm_mapsize, 4173 BUS_DMASYNC_PREWRITE); 4174 4175 if (frag == sc->bge_tx_saved_considx) { 4176 BGE_TSO_PRINTF(("%s: frag %d = wrapped id %d?\n", 4177 device_xname(sc->bge_dev), frag, sc->bge_tx_saved_considx)); 4178 4179 goto fail_unload; 4180 } 4181 4182 sc->bge_rdata->bge_tx_ring[cur].bge_flags |= BGE_TXBDFLAG_END; 4183 sc->bge_cdata.bge_tx_chain[cur] = m_head; 4184 SLIST_REMOVE_HEAD(&sc->txdma_list, link); 4185 sc->txdma[cur] = dma; 4186 sc->bge_txcnt += dmamap->dm_nsegs; 4187 4188 *txidx = frag; 4189 4190 return 0; 4191 4192 fail_unload: 4193 bus_dmamap_unload(sc->bge_dmatag, dmamap); 4194 4195 return ENOBUFS; 4196 } 4197 4198 /* 4199 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 4200 * to the mbuf data regions directly in the transmit descriptors. 4201 */ 4202 static void 4203 bge_start(struct ifnet *ifp) 4204 { 4205 struct bge_softc *sc; 4206 struct mbuf *m_head = NULL; 4207 uint32_t prodidx; 4208 int pkts = 0; 4209 4210 sc = ifp->if_softc; 4211 4212 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 4213 return; 4214 4215 prodidx = sc->bge_tx_prodidx; 4216 4217 while (sc->bge_cdata.bge_tx_chain[prodidx] == NULL) { 4218 IFQ_POLL(&ifp->if_snd, m_head); 4219 if (m_head == NULL) 4220 break; 4221 4222 #if 0 4223 /* 4224 * XXX 4225 * safety overkill. If this is a fragmented packet chain 4226 * with delayed TCP/UDP checksums, then only encapsulate 4227 * it if we have enough descriptors to handle the entire 4228 * chain at once. 4229 * (paranoia -- may not actually be needed) 4230 */ 4231 if (m_head->m_flags & M_FIRSTFRAG && 4232 m_head->m_pkthdr.csum_flags & (CSUM_DELAY_DATA)) { 4233 if ((BGE_TX_RING_CNT - sc->bge_txcnt) < 4234 M_CSUM_DATA_IPv4_OFFSET(m_head->m_pkthdr.csum_data) + 16) { 4235 ifp->if_flags |= IFF_OACTIVE; 4236 break; 4237 } 4238 } 4239 #endif 4240 4241 /* 4242 * Pack the data into the transmit ring. If we 4243 * don't have room, set the OACTIVE flag and wait 4244 * for the NIC to drain the ring. 4245 */ 4246 if (bge_encap(sc, m_head, &prodidx)) { 4247 ifp->if_flags |= IFF_OACTIVE; 4248 break; 4249 } 4250 4251 /* now we are committed to transmit the packet */ 4252 IFQ_DEQUEUE(&ifp->if_snd, m_head); 4253 pkts++; 4254 4255 /* 4256 * If there's a BPF listener, bounce a copy of this frame 4257 * to him. 4258 */ 4259 bpf_mtap(ifp, m_head); 4260 } 4261 if (pkts == 0) 4262 return; 4263 4264 /* Transmit */ 4265 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); 4266 /* 5700 b2 errata */ 4267 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX) 4268 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); 4269 4270 sc->bge_tx_prodidx = prodidx; 4271 4272 /* 4273 * Set a timeout in case the chip goes out to lunch. 4274 */ 4275 ifp->if_timer = 5; 4276 } 4277 4278 static int 4279 bge_init(struct ifnet *ifp) 4280 { 4281 struct bge_softc *sc = ifp->if_softc; 4282 const uint16_t *m; 4283 int s, error = 0; 4284 4285 s = splnet(); 4286 4287 ifp = &sc->ethercom.ec_if; 4288 4289 /* Cancel pending I/O and flush buffers. */ 4290 bge_stop(ifp, 0); 4291 4292 bge_stop_fw(sc); 4293 bge_sig_pre_reset(sc, BGE_RESET_START); 4294 bge_reset(sc); 4295 bge_sig_legacy(sc, BGE_RESET_START); 4296 bge_sig_post_reset(sc, BGE_RESET_START); 4297 4298 bge_chipinit(sc); 4299 4300 /* 4301 * Init the various state machines, ring 4302 * control blocks and firmware. 4303 */ 4304 error = bge_blockinit(sc); 4305 if (error != 0) { 4306 aprint_error_dev(sc->bge_dev, "initialization error %d\n", 4307 error); 4308 splx(s); 4309 return error; 4310 } 4311 4312 ifp = &sc->ethercom.ec_if; 4313 4314 /* Specify MTU. */ 4315 CSR_WRITE_4(sc, BGE_RX_MTU, ifp->if_mtu + 4316 ETHER_HDR_LEN + ETHER_CRC_LEN + ETHER_VLAN_ENCAP_LEN); 4317 4318 /* Load our MAC address. */ 4319 m = (const uint16_t *)&(CLLADDR(ifp->if_sadl)[0]); 4320 CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0])); 4321 CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, (htons(m[1]) << 16) | htons(m[2])); 4322 4323 /* Enable or disable promiscuous mode as needed. */ 4324 if (ifp->if_flags & IFF_PROMISC) 4325 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 4326 else 4327 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 4328 4329 /* Program multicast filter. */ 4330 bge_setmulti(sc); 4331 4332 /* Init RX ring. */ 4333 bge_init_rx_ring_std(sc); 4334 4335 /* 4336 * Workaround for a bug in 5705 ASIC rev A0. Poll the NIC's 4337 * memory to insure that the chip has in fact read the first 4338 * entry of the ring. 4339 */ 4340 if (sc->bge_chipid == BGE_CHIPID_BCM5705_A0) { 4341 uint32_t v, i; 4342 for (i = 0; i < 10; i++) { 4343 DELAY(20); 4344 v = bge_readmem_ind(sc, BGE_STD_RX_RINGS + 8); 4345 if (v == (MCLBYTES - ETHER_ALIGN)) 4346 break; 4347 } 4348 if (i == 10) 4349 aprint_error_dev(sc->bge_dev, 4350 "5705 A0 chip failed to load RX ring\n"); 4351 } 4352 4353 /* Init jumbo RX ring. */ 4354 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 4355 bge_init_rx_ring_jumbo(sc); 4356 4357 /* Init our RX return ring index */ 4358 sc->bge_rx_saved_considx = 0; 4359 4360 /* Init TX ring. */ 4361 bge_init_tx_ring(sc); 4362 4363 /* Turn on transmitter */ 4364 BGE_SETBIT(sc, BGE_TX_MODE, BGE_TXMODE_ENABLE); 4365 4366 /* Turn on receiver */ 4367 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE); 4368 4369 CSR_WRITE_4(sc, BGE_MAX_RX_FRAME_LOWAT, 2); 4370 4371 /* Tell firmware we're alive. */ 4372 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 4373 4374 /* Enable host interrupts. */ 4375 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA); 4376 BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); 4377 bge_writembx(sc, BGE_MBX_IRQ0_LO, 0); 4378 4379 if ((error = bge_ifmedia_upd(ifp)) != 0) 4380 goto out; 4381 4382 ifp->if_flags |= IFF_RUNNING; 4383 ifp->if_flags &= ~IFF_OACTIVE; 4384 4385 callout_reset(&sc->bge_timeout, hz, bge_tick, sc); 4386 4387 out: 4388 sc->bge_if_flags = ifp->if_flags; 4389 splx(s); 4390 4391 return error; 4392 } 4393 4394 /* 4395 * Set media options. 4396 */ 4397 static int 4398 bge_ifmedia_upd(struct ifnet *ifp) 4399 { 4400 struct bge_softc *sc = ifp->if_softc; 4401 struct mii_data *mii = &sc->bge_mii; 4402 struct ifmedia *ifm = &sc->bge_ifmedia; 4403 int rc; 4404 4405 /* If this is a 1000baseX NIC, enable the TBI port. */ 4406 if (sc->bge_flags & BGE_PHY_FIBER_TBI) { 4407 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 4408 return EINVAL; 4409 switch (IFM_SUBTYPE(ifm->ifm_media)) { 4410 case IFM_AUTO: 4411 /* 4412 * The BCM5704 ASIC appears to have a special 4413 * mechanism for programming the autoneg 4414 * advertisement registers in TBI mode. 4415 */ 4416 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) { 4417 uint32_t sgdig; 4418 sgdig = CSR_READ_4(sc, BGE_SGDIG_STS); 4419 if (sgdig & BGE_SGDIGSTS_DONE) { 4420 CSR_WRITE_4(sc, BGE_TX_TBI_AUTONEG, 0); 4421 sgdig = CSR_READ_4(sc, BGE_SGDIG_CFG); 4422 sgdig |= BGE_SGDIGCFG_AUTO | 4423 BGE_SGDIGCFG_PAUSE_CAP | 4424 BGE_SGDIGCFG_ASYM_PAUSE; 4425 CSR_WRITE_4(sc, BGE_SGDIG_CFG, 4426 sgdig | BGE_SGDIGCFG_SEND); 4427 DELAY(5); 4428 CSR_WRITE_4(sc, BGE_SGDIG_CFG, sgdig); 4429 } 4430 } 4431 break; 4432 case IFM_1000_SX: 4433 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 4434 BGE_CLRBIT(sc, BGE_MAC_MODE, 4435 BGE_MACMODE_HALF_DUPLEX); 4436 } else { 4437 BGE_SETBIT(sc, BGE_MAC_MODE, 4438 BGE_MACMODE_HALF_DUPLEX); 4439 } 4440 break; 4441 default: 4442 return EINVAL; 4443 } 4444 /* XXX 802.3x flow control for 1000BASE-SX */ 4445 return 0; 4446 } 4447 4448 BGE_STS_SETBIT(sc, BGE_STS_LINK_EVT); 4449 if ((rc = mii_mediachg(mii)) == ENXIO) 4450 return 0; 4451 4452 /* 4453 * Force an interrupt so that we will call bge_link_upd 4454 * if needed and clear any pending link state attention. 4455 * Without this we are not getting any further interrupts 4456 * for link state changes and thus will not UP the link and 4457 * not be able to send in bge_start. The only way to get 4458 * things working was to receive a packet and get a RX intr. 4459 */ 4460 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 4461 sc->bge_flags & BGE_IS_5788) 4462 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET); 4463 else 4464 BGE_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW); 4465 4466 return rc; 4467 } 4468 4469 /* 4470 * Report current media status. 4471 */ 4472 static void 4473 bge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 4474 { 4475 struct bge_softc *sc = ifp->if_softc; 4476 struct mii_data *mii = &sc->bge_mii; 4477 4478 if (sc->bge_flags & BGE_PHY_FIBER_TBI) { 4479 ifmr->ifm_status = IFM_AVALID; 4480 ifmr->ifm_active = IFM_ETHER; 4481 if (CSR_READ_4(sc, BGE_MAC_STS) & 4482 BGE_MACSTAT_TBI_PCS_SYNCHED) 4483 ifmr->ifm_status |= IFM_ACTIVE; 4484 ifmr->ifm_active |= IFM_1000_SX; 4485 if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX) 4486 ifmr->ifm_active |= IFM_HDX; 4487 else 4488 ifmr->ifm_active |= IFM_FDX; 4489 return; 4490 } 4491 4492 mii_pollstat(mii); 4493 ifmr->ifm_status = mii->mii_media_status; 4494 ifmr->ifm_active = (mii->mii_media_active & ~IFM_ETH_FMASK) | 4495 sc->bge_flowflags; 4496 } 4497 4498 static int 4499 bge_ifflags_cb(struct ethercom *ec) 4500 { 4501 struct ifnet *ifp = &ec->ec_if; 4502 struct bge_softc *sc = ifp->if_softc; 4503 int change = ifp->if_flags ^ sc->bge_if_flags; 4504 4505 if ((change & ~(IFF_CANTCHANGE|IFF_DEBUG)) != 0) 4506 return ENETRESET; 4507 else if ((change & (IFF_PROMISC | IFF_ALLMULTI)) == 0) 4508 return 0; 4509 4510 if ((ifp->if_flags & IFF_PROMISC) == 0) 4511 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 4512 else 4513 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 4514 4515 bge_setmulti(sc); 4516 4517 sc->bge_if_flags = ifp->if_flags; 4518 return 0; 4519 } 4520 4521 static int 4522 bge_ioctl(struct ifnet *ifp, u_long command, void *data) 4523 { 4524 struct bge_softc *sc = ifp->if_softc; 4525 struct ifreq *ifr = (struct ifreq *) data; 4526 int s, error = 0; 4527 struct mii_data *mii; 4528 4529 s = splnet(); 4530 4531 switch (command) { 4532 case SIOCSIFMEDIA: 4533 /* XXX Flow control is not supported for 1000BASE-SX */ 4534 if (sc->bge_flags & BGE_PHY_FIBER_TBI) { 4535 ifr->ifr_media &= ~IFM_ETH_FMASK; 4536 sc->bge_flowflags = 0; 4537 } 4538 4539 /* Flow control requires full-duplex mode. */ 4540 if (IFM_SUBTYPE(ifr->ifr_media) == IFM_AUTO || 4541 (ifr->ifr_media & IFM_FDX) == 0) { 4542 ifr->ifr_media &= ~IFM_ETH_FMASK; 4543 } 4544 if (IFM_SUBTYPE(ifr->ifr_media) != IFM_AUTO) { 4545 if ((ifr->ifr_media & IFM_ETH_FMASK) == IFM_FLOW) { 4546 /* We can do both TXPAUSE and RXPAUSE. */ 4547 ifr->ifr_media |= 4548 IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE; 4549 } 4550 sc->bge_flowflags = ifr->ifr_media & IFM_ETH_FMASK; 4551 } 4552 /* FALLTHROUGH */ 4553 case SIOCGIFMEDIA: 4554 if (sc->bge_flags & BGE_PHY_FIBER_TBI) { 4555 error = ifmedia_ioctl(ifp, ifr, &sc->bge_ifmedia, 4556 command); 4557 } else { 4558 mii = &sc->bge_mii; 4559 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, 4560 command); 4561 } 4562 break; 4563 default: 4564 if ((error = ether_ioctl(ifp, command, data)) != ENETRESET) 4565 break; 4566 4567 error = 0; 4568 4569 if (command != SIOCADDMULTI && command != SIOCDELMULTI) 4570 ; 4571 else if (ifp->if_flags & IFF_RUNNING) 4572 bge_setmulti(sc); 4573 break; 4574 } 4575 4576 splx(s); 4577 4578 return error; 4579 } 4580 4581 static void 4582 bge_watchdog(struct ifnet *ifp) 4583 { 4584 struct bge_softc *sc; 4585 4586 sc = ifp->if_softc; 4587 4588 aprint_error_dev(sc->bge_dev, "watchdog timeout -- resetting\n"); 4589 4590 ifp->if_flags &= ~IFF_RUNNING; 4591 bge_init(ifp); 4592 4593 ifp->if_oerrors++; 4594 } 4595 4596 static void 4597 bge_stop_block(struct bge_softc *sc, bus_addr_t reg, uint32_t bit) 4598 { 4599 int i; 4600 4601 BGE_CLRBIT(sc, reg, bit); 4602 4603 for (i = 0; i < 1000; i++) { 4604 if ((CSR_READ_4(sc, reg) & bit) == 0) 4605 return; 4606 delay(100); 4607 } 4608 4609 /* 4610 * Doesn't print only when the register is BGE_SRS_MODE. It occurs 4611 * on some environment (and once after boot?) 4612 */ 4613 if (reg != BGE_SRS_MODE) 4614 aprint_error_dev(sc->bge_dev, 4615 "block failed to stop: reg 0x%lx, bit 0x%08x\n", 4616 (u_long)reg, bit); 4617 } 4618 4619 /* 4620 * Stop the adapter and free any mbufs allocated to the 4621 * RX and TX lists. 4622 */ 4623 static void 4624 bge_stop(struct ifnet *ifp, int disable) 4625 { 4626 struct bge_softc *sc = ifp->if_softc; 4627 4628 callout_stop(&sc->bge_timeout); 4629 4630 /* 4631 * Tell firmware we're shutting down. 4632 */ 4633 bge_stop_fw(sc); 4634 bge_sig_pre_reset(sc, BGE_RESET_STOP); 4635 4636 /* Disable host interrupts. */ 4637 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); 4638 bge_writembx(sc, BGE_MBX_IRQ0_LO, 1); 4639 4640 /* 4641 * Disable all of the receiver blocks 4642 */ 4643 bge_stop_block(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE); 4644 bge_stop_block(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 4645 bge_stop_block(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 4646 if (BGE_IS_5700_FAMILY(sc)) 4647 bge_stop_block(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 4648 bge_stop_block(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE); 4649 bge_stop_block(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 4650 bge_stop_block(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE); 4651 4652 /* 4653 * Disable all of the transmit blocks 4654 */ 4655 bge_stop_block(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 4656 bge_stop_block(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 4657 bge_stop_block(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 4658 bge_stop_block(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE); 4659 bge_stop_block(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE); 4660 if (BGE_IS_5700_FAMILY(sc)) 4661 bge_stop_block(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 4662 bge_stop_block(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 4663 4664 /* 4665 * Shut down all of the memory managers and related 4666 * state machines. 4667 */ 4668 bge_stop_block(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE); 4669 bge_stop_block(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE); 4670 if (BGE_IS_5700_FAMILY(sc)) 4671 bge_stop_block(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 4672 4673 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 4674 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 4675 4676 if (BGE_IS_5700_FAMILY(sc)) { 4677 bge_stop_block(sc, BGE_BMAN_MODE, BGE_BMANMODE_ENABLE); 4678 bge_stop_block(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 4679 } 4680 4681 bge_reset(sc); 4682 bge_sig_legacy(sc, BGE_RESET_STOP); 4683 bge_sig_post_reset(sc, BGE_RESET_STOP); 4684 4685 /* 4686 * Keep the ASF firmware running if up. 4687 */ 4688 if (sc->bge_asf_mode & ASF_STACKUP) 4689 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 4690 else 4691 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 4692 4693 /* Free the RX lists. */ 4694 bge_free_rx_ring_std(sc); 4695 4696 /* Free jumbo RX list. */ 4697 if (BGE_IS_JUMBO_CAPABLE(sc)) 4698 bge_free_rx_ring_jumbo(sc); 4699 4700 /* Free TX buffers. */ 4701 bge_free_tx_ring(sc); 4702 4703 /* 4704 * Isolate/power down the PHY. 4705 */ 4706 if (!(sc->bge_flags & BGE_PHY_FIBER_TBI)) 4707 mii_down(&sc->bge_mii); 4708 4709 sc->bge_tx_saved_considx = BGE_TXCONS_UNSET; 4710 4711 /* Clear MAC's link state (PHY may still have link UP). */ 4712 BGE_STS_CLRBIT(sc, BGE_STS_LINK); 4713 4714 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 4715 } 4716 4717 static void 4718 bge_link_upd(struct bge_softc *sc) 4719 { 4720 struct ifnet *ifp = &sc->ethercom.ec_if; 4721 struct mii_data *mii = &sc->bge_mii; 4722 uint32_t status; 4723 int link; 4724 4725 /* Clear 'pending link event' flag */ 4726 BGE_STS_CLRBIT(sc, BGE_STS_LINK_EVT); 4727 4728 /* 4729 * Process link state changes. 4730 * Grrr. The link status word in the status block does 4731 * not work correctly on the BCM5700 rev AX and BX chips, 4732 * according to all available information. Hence, we have 4733 * to enable MII interrupts in order to properly obtain 4734 * async link changes. Unfortunately, this also means that 4735 * we have to read the MAC status register to detect link 4736 * changes, thereby adding an additional register access to 4737 * the interrupt handler. 4738 */ 4739 4740 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700) { 4741 status = CSR_READ_4(sc, BGE_MAC_STS); 4742 if (status & BGE_MACSTAT_MI_INTERRUPT) { 4743 mii_pollstat(mii); 4744 4745 if (!BGE_STS_BIT(sc, BGE_STS_LINK) && 4746 mii->mii_media_status & IFM_ACTIVE && 4747 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) 4748 BGE_STS_SETBIT(sc, BGE_STS_LINK); 4749 else if (BGE_STS_BIT(sc, BGE_STS_LINK) && 4750 (!(mii->mii_media_status & IFM_ACTIVE) || 4751 IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) 4752 BGE_STS_CLRBIT(sc, BGE_STS_LINK); 4753 4754 /* Clear the interrupt */ 4755 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, 4756 BGE_EVTENB_MI_INTERRUPT); 4757 bge_miibus_readreg(sc->bge_dev, 1, BRGPHY_MII_ISR); 4758 bge_miibus_writereg(sc->bge_dev, 1, BRGPHY_MII_IMR, 4759 BRGPHY_INTRS); 4760 } 4761 return; 4762 } 4763 4764 if (sc->bge_flags & BGE_PHY_FIBER_TBI) { 4765 status = CSR_READ_4(sc, BGE_MAC_STS); 4766 if (status & BGE_MACSTAT_TBI_PCS_SYNCHED) { 4767 if (!BGE_STS_BIT(sc, BGE_STS_LINK)) { 4768 BGE_STS_SETBIT(sc, BGE_STS_LINK); 4769 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) 4770 BGE_CLRBIT(sc, BGE_MAC_MODE, 4771 BGE_MACMODE_TBI_SEND_CFGS); 4772 CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF); 4773 if_link_state_change(ifp, LINK_STATE_UP); 4774 } 4775 } else if (BGE_STS_BIT(sc, BGE_STS_LINK)) { 4776 BGE_STS_CLRBIT(sc, BGE_STS_LINK); 4777 if_link_state_change(ifp, LINK_STATE_DOWN); 4778 } 4779 /* 4780 * Discard link events for MII/GMII cards if MI auto-polling disabled. 4781 * This should not happen since mii callouts are locked now, but 4782 * we keep this check for debug. 4783 */ 4784 } else if (BGE_STS_BIT(sc, BGE_STS_AUTOPOLL)) { 4785 /* 4786 * Some broken BCM chips have BGE_STATFLAG_LINKSTATE_CHANGED 4787 * bit in status word always set. Workaround this bug by 4788 * reading PHY link status directly. 4789 */ 4790 link = (CSR_READ_4(sc, BGE_MI_STS) & BGE_MISTS_LINK)? 4791 BGE_STS_LINK : 0; 4792 4793 if (BGE_STS_BIT(sc, BGE_STS_LINK) != link) { 4794 mii_pollstat(mii); 4795 4796 if (!BGE_STS_BIT(sc, BGE_STS_LINK) && 4797 mii->mii_media_status & IFM_ACTIVE && 4798 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) 4799 BGE_STS_SETBIT(sc, BGE_STS_LINK); 4800 else if (BGE_STS_BIT(sc, BGE_STS_LINK) && 4801 (!(mii->mii_media_status & IFM_ACTIVE) || 4802 IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) 4803 BGE_STS_CLRBIT(sc, BGE_STS_LINK); 4804 } 4805 } 4806 4807 /* Clear the attention */ 4808 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED| 4809 BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE| 4810 BGE_MACSTAT_LINK_CHANGED); 4811 } 4812 4813 static int 4814 sysctl_bge_verify(SYSCTLFN_ARGS) 4815 { 4816 int error, t; 4817 struct sysctlnode node; 4818 4819 node = *rnode; 4820 t = *(int*)rnode->sysctl_data; 4821 node.sysctl_data = &t; 4822 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 4823 if (error || newp == NULL) 4824 return error; 4825 4826 #if 0 4827 DPRINTF2(("%s: t = %d, nodenum = %d, rnodenum = %d\n", __func__, t, 4828 node.sysctl_num, rnode->sysctl_num)); 4829 #endif 4830 4831 if (node.sysctl_num == bge_rxthresh_nodenum) { 4832 if (t < 0 || t >= NBGE_RX_THRESH) 4833 return EINVAL; 4834 bge_update_all_threshes(t); 4835 } else 4836 return EINVAL; 4837 4838 *(int*)rnode->sysctl_data = t; 4839 4840 return 0; 4841 } 4842 4843 /* 4844 * Set up sysctl(3) MIB, hw.bge.*. 4845 */ 4846 static void 4847 sysctl_bge_init(struct bge_softc *sc) 4848 { 4849 int rc, bge_root_num; 4850 const struct sysctlnode *node; 4851 4852 if ((rc = sysctl_createv(&sc->bge_log, 0, NULL, NULL, 4853 CTLFLAG_PERMANENT, CTLTYPE_NODE, "hw", NULL, 4854 NULL, 0, NULL, 0, CTL_HW, CTL_EOL)) != 0) { 4855 goto err; 4856 } 4857 4858 if ((rc = sysctl_createv(&sc->bge_log, 0, NULL, &node, 4859 0, CTLTYPE_NODE, "bge", 4860 SYSCTL_DESCR("BGE interface controls"), 4861 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL)) != 0) { 4862 goto err; 4863 } 4864 4865 bge_root_num = node->sysctl_num; 4866 4867 /* BGE Rx interrupt mitigation level */ 4868 if ((rc = sysctl_createv(&sc->bge_log, 0, NULL, &node, 4869 CTLFLAG_READWRITE, 4870 CTLTYPE_INT, "rx_lvl", 4871 SYSCTL_DESCR("BGE receive interrupt mitigation level"), 4872 sysctl_bge_verify, 0, 4873 &bge_rx_thresh_lvl, 4874 0, CTL_HW, bge_root_num, CTL_CREATE, 4875 CTL_EOL)) != 0) { 4876 goto err; 4877 } 4878 4879 bge_rxthresh_nodenum = node->sysctl_num; 4880 4881 return; 4882 4883 err: 4884 aprint_error("%s: sysctl_createv failed (rc = %d)\n", __func__, rc); 4885 } 4886 4887 #ifdef BGE_DEBUG 4888 void 4889 bge_debug_info(struct bge_softc *sc) 4890 { 4891 4892 printf("Hardware Flags:\n"); 4893 if (BGE_IS_5755_PLUS(sc)) 4894 printf(" - 5755 Plus\n"); 4895 if (BGE_IS_5750_OR_BEYOND(sc)) 4896 printf(" - 5750 Plus\n"); 4897 if (BGE_IS_5705_PLUS(sc)) 4898 printf(" - 5705 Plus\n"); 4899 if (BGE_IS_5714_FAMILY(sc)) 4900 printf(" - 5714 Family\n"); 4901 if (BGE_IS_5700_FAMILY(sc)) 4902 printf(" - 5700 Family\n"); 4903 if (sc->bge_flags & BGE_IS_5788) 4904 printf(" - 5788\n"); 4905 if (sc->bge_flags & BGE_JUMBO_CAPABLE) 4906 printf(" - Supports Jumbo Frames\n"); 4907 if (sc->bge_flags & BGE_NO_EEPROM) 4908 printf(" - No EEPROM\n"); 4909 if (sc->bge_flags & BGE_PCIX) 4910 printf(" - PCI-X Bus\n"); 4911 if (sc->bge_flags & BGE_PCIE) 4912 printf(" - PCI Express Bus\n"); 4913 if (sc->bge_flags & BGE_NO_3LED) 4914 printf(" - No 3 LEDs\n"); 4915 if (sc->bge_flags & BGE_RX_ALIGNBUG) 4916 printf(" - RX Alignment Bug\n"); 4917 if (sc->bge_flags & BGE_TSO) 4918 printf(" - TSO\n"); 4919 } 4920 #endif /* BGE_DEBUG */ 4921 4922 static int 4923 bge_get_eaddr_fw(struct bge_softc *sc, uint8_t ether_addr[]) 4924 { 4925 prop_dictionary_t dict; 4926 prop_data_t ea; 4927 4928 if ((sc->bge_flags & BGE_NO_EEPROM) == 0) 4929 return 1; 4930 4931 dict = device_properties(sc->bge_dev); 4932 ea = prop_dictionary_get(dict, "mac-address"); 4933 if (ea != NULL) { 4934 KASSERT(prop_object_type(ea) == PROP_TYPE_DATA); 4935 KASSERT(prop_data_size(ea) == ETHER_ADDR_LEN); 4936 memcpy(ether_addr, prop_data_data_nocopy(ea), ETHER_ADDR_LEN); 4937 return 0; 4938 } 4939 4940 return 1; 4941 } 4942 4943 static int 4944 bge_get_eaddr_mem(struct bge_softc *sc, uint8_t ether_addr[]) 4945 { 4946 uint32_t mac_addr; 4947 4948 mac_addr = bge_readmem_ind(sc, 0x0c14); 4949 if ((mac_addr >> 16) == 0x484b) { 4950 ether_addr[0] = (uint8_t)(mac_addr >> 8); 4951 ether_addr[1] = (uint8_t)mac_addr; 4952 mac_addr = bge_readmem_ind(sc, 0x0c18); 4953 ether_addr[2] = (uint8_t)(mac_addr >> 24); 4954 ether_addr[3] = (uint8_t)(mac_addr >> 16); 4955 ether_addr[4] = (uint8_t)(mac_addr >> 8); 4956 ether_addr[5] = (uint8_t)mac_addr; 4957 return 0; 4958 } 4959 return 1; 4960 } 4961 4962 static int 4963 bge_get_eaddr_nvram(struct bge_softc *sc, uint8_t ether_addr[]) 4964 { 4965 int mac_offset = BGE_EE_MAC_OFFSET; 4966 4967 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 4968 mac_offset = BGE_EE_MAC_OFFSET_5906; 4969 4970 return (bge_read_nvram(sc, ether_addr, mac_offset + 2, 4971 ETHER_ADDR_LEN)); 4972 } 4973 4974 static int 4975 bge_get_eaddr_eeprom(struct bge_softc *sc, uint8_t ether_addr[]) 4976 { 4977 4978 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 4979 return 1; 4980 4981 return (bge_read_eeprom(sc, ether_addr, BGE_EE_MAC_OFFSET + 2, 4982 ETHER_ADDR_LEN)); 4983 } 4984 4985 static int 4986 bge_get_eaddr(struct bge_softc *sc, uint8_t eaddr[]) 4987 { 4988 static const bge_eaddr_fcn_t bge_eaddr_funcs[] = { 4989 /* NOTE: Order is critical */ 4990 bge_get_eaddr_fw, 4991 bge_get_eaddr_mem, 4992 bge_get_eaddr_nvram, 4993 bge_get_eaddr_eeprom, 4994 NULL 4995 }; 4996 const bge_eaddr_fcn_t *func; 4997 4998 for (func = bge_eaddr_funcs; *func != NULL; ++func) { 4999 if ((*func)(sc, eaddr) == 0) 5000 break; 5001 } 5002 return (*func == NULL ? ENXIO : 0); 5003 } 5004
Indexes created Tue Sep 23 21:09:50 GMT 2025