if_bge.c revision 1.207
1 /* $NetBSD: if_bge.c,v 1.207 2013/02/27 14:19:38 msaitoh Exp $ */ 2 3 /* 4 * Copyright (c) 2001 Wind River Systems 5 * Copyright (c) 1997, 1998, 1999, 2001 6 * Bill Paul <wpaul (at) windriver.com>. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Bill Paul. 19 * 4. Neither the name of the author nor the names of any co-contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 33 * THE POSSIBILITY OF SUCH DAMAGE. 34 * 35 * $FreeBSD: if_bge.c,v 1.13 2002/04/04 06:01:31 wpaul Exp $ 36 */ 37 38 /* 39 * Broadcom BCM570x family gigabit ethernet driver for NetBSD. 40 * 41 * NetBSD version by: 42 * 43 * Frank van der Linden <fvdl (at) wasabisystems.com> 44 * Jason Thorpe <thorpej (at) wasabisystems.com> 45 * Jonathan Stone <jonathan (at) dsg.stanford.edu> 46 * 47 * Originally written for FreeBSD by Bill Paul <wpaul (at) windriver.com> 48 * Senior Engineer, Wind River Systems 49 */ 50 51 /* 52 * The Broadcom BCM5700 is based on technology originally developed by 53 * Alteon Networks as part of the Tigon I and Tigon II gigabit ethernet 54 * MAC chips. The BCM5700, sometimes referred to as the Tigon III, has 55 * two on-board MIPS R4000 CPUs and can have as much as 16MB of external 56 * SSRAM. The BCM5700 supports TCP, UDP and IP checksum offload, jumbo 57 * frames, highly configurable RX filtering, and 16 RX and TX queues 58 * (which, along with RX filter rules, can be used for QOS applications). 59 * Other features, such as TCP segmentation, may be available as part 60 * of value-added firmware updates. Unlike the Tigon I and Tigon II, 61 * firmware images can be stored in hardware and need not be compiled 62 * into the driver. 63 * 64 * The BCM5700 supports the PCI v2.2 and PCI-X v1.0 standards, and will 65 * function in a 32-bit/64-bit 33/66MHz bus, or a 64-bit/133MHz bus. 66 * 67 * The BCM5701 is a single-chip solution incorporating both the BCM5700 68 * MAC and a BCM5401 10/100/1000 PHY. Unlike the BCM5700, the BCM5701 69 * does not support external SSRAM. 70 * 71 * Broadcom also produces a variation of the BCM5700 under the "Altima" 72 * brand name, which is functionally similar but lacks PCI-X support. 73 * 74 * Without external SSRAM, you can only have at most 4 TX rings, 75 * and the use of the mini RX ring is disabled. This seems to imply 76 * that these features are simply not available on the BCM5701. As a 77 * result, this driver does not implement any support for the mini RX 78 * ring. 79 */ 80 81 #include <sys/cdefs.h> 82 __KERNEL_RCSID(0, "$NetBSD: if_bge.c,v 1.207 2013/02/27 14:19:38 msaitoh Exp $"); 83 84 #include "vlan.h" 85 86 #include <sys/param.h> 87 #include <sys/systm.h> 88 #include <sys/callout.h> 89 #include <sys/sockio.h> 90 #include <sys/mbuf.h> 91 #include <sys/malloc.h> 92 #include <sys/kernel.h> 93 #include <sys/device.h> 94 #include <sys/socket.h> 95 #include <sys/sysctl.h> 96 97 #include <net/if.h> 98 #include <net/if_dl.h> 99 #include <net/if_media.h> 100 #include <net/if_ether.h> 101 102 #include <sys/rnd.h> 103 104 #ifdef INET 105 #include <netinet/in.h> 106 #include <netinet/in_systm.h> 107 #include <netinet/in_var.h> 108 #include <netinet/ip.h> 109 #endif 110 111 /* Headers for TCP Segmentation Offload (TSO) */ 112 #include <netinet/in_systm.h> /* n_time for <netinet/ip.h>... */ 113 #include <netinet/in.h> /* ip_{src,dst}, for <netinet/ip.h> */ 114 #include <netinet/ip.h> /* for struct ip */ 115 #include <netinet/tcp.h> /* for struct tcphdr */ 116 117 118 #include <net/bpf.h> 119 120 #include <dev/pci/pcireg.h> 121 #include <dev/pci/pcivar.h> 122 #include <dev/pci/pcidevs.h> 123 124 #include <dev/mii/mii.h> 125 #include <dev/mii/miivar.h> 126 #include <dev/mii/miidevs.h> 127 #include <dev/mii/brgphyreg.h> 128 129 #include <dev/pci/if_bgereg.h> 130 #include <dev/pci/if_bgevar.h> 131 132 #include <prop/proplib.h> 133 134 #define ETHER_MIN_NOPAD (ETHER_MIN_LEN - ETHER_CRC_LEN) /* i.e., 60 */ 135 136 137 /* 138 * Tunable thresholds for rx-side bge interrupt mitigation. 139 */ 140 141 /* 142 * The pairs of values below were obtained from empirical measurement 143 * on bcm5700 rev B2; they ar designed to give roughly 1 receive 144 * interrupt for every N packets received, where N is, approximately, 145 * the second value (rx_max_bds) in each pair. The values are chosen 146 * such that moving from one pair to the succeeding pair was observed 147 * to roughly halve interrupt rate under sustained input packet load. 148 * The values were empirically chosen to avoid overflowing internal 149 * limits on the bcm5700: increasing rx_ticks much beyond 600 150 * results in internal wrapping and higher interrupt rates. 151 * The limit of 46 frames was chosen to match NFS workloads. 152 * 153 * These values also work well on bcm5701, bcm5704C, and (less 154 * tested) bcm5703. On other chipsets, (including the Altima chip 155 * family), the larger values may overflow internal chip limits, 156 * leading to increasing interrupt rates rather than lower interrupt 157 * rates. 158 * 159 * Applications using heavy interrupt mitigation (interrupting every 160 * 32 or 46 frames) in both directions may need to increase the TCP 161 * windowsize to above 131072 bytes (e.g., to 199608 bytes) to sustain 162 * full link bandwidth, due to ACKs and window updates lingering 163 * in the RX queue during the 30-to-40-frame interrupt-mitigation window. 164 */ 165 static const struct bge_load_rx_thresh { 166 int rx_ticks; 167 int rx_max_bds; } 168 bge_rx_threshes[] = { 169 { 16, 1 }, /* rx_max_bds = 1 disables interrupt mitigation */ 170 { 32, 2 }, 171 { 50, 4 }, 172 { 100, 8 }, 173 { 192, 16 }, 174 { 416, 32 }, 175 { 598, 46 } 176 }; 177 #define NBGE_RX_THRESH (sizeof(bge_rx_threshes) / sizeof(bge_rx_threshes[0])) 178 179 /* XXX patchable; should be sysctl'able */ 180 static int bge_auto_thresh = 1; 181 static int bge_rx_thresh_lvl; 182 183 static int bge_rxthresh_nodenum; 184 185 typedef int (*bge_eaddr_fcn_t)(struct bge_softc *, uint8_t[]); 186 187 static int bge_probe(device_t, cfdata_t, void *); 188 static void bge_attach(device_t, device_t, void *); 189 static void bge_release_resources(struct bge_softc *); 190 191 static int bge_get_eaddr_fw(struct bge_softc *, uint8_t[]); 192 static int bge_get_eaddr_mem(struct bge_softc *, uint8_t[]); 193 static int bge_get_eaddr_nvram(struct bge_softc *, uint8_t[]); 194 static int bge_get_eaddr_eeprom(struct bge_softc *, uint8_t[]); 195 static int bge_get_eaddr(struct bge_softc *, uint8_t[]); 196 197 static void bge_txeof(struct bge_softc *); 198 static void bge_rxeof(struct bge_softc *); 199 200 static void bge_asf_driver_up (struct bge_softc *); 201 static void bge_tick(void *); 202 static void bge_stats_update(struct bge_softc *); 203 static void bge_stats_update_regs(struct bge_softc *); 204 static int bge_encap(struct bge_softc *, struct mbuf *, uint32_t *); 205 206 static int bge_intr(void *); 207 static void bge_start(struct ifnet *); 208 static int bge_ifflags_cb(struct ethercom *); 209 static int bge_ioctl(struct ifnet *, u_long, void *); 210 static int bge_init(struct ifnet *); 211 static void bge_stop(struct ifnet *, int); 212 static void bge_watchdog(struct ifnet *); 213 static int bge_ifmedia_upd(struct ifnet *); 214 static void bge_ifmedia_sts(struct ifnet *, struct ifmediareq *); 215 216 static uint8_t bge_nvram_getbyte(struct bge_softc *, int, uint8_t *); 217 static int bge_read_nvram(struct bge_softc *, uint8_t *, int, int); 218 219 static uint8_t bge_eeprom_getbyte(struct bge_softc *, int, uint8_t *); 220 static int bge_read_eeprom(struct bge_softc *, void *, int, int); 221 static void bge_setmulti(struct bge_softc *); 222 223 static void bge_handle_events(struct bge_softc *); 224 static int bge_alloc_jumbo_mem(struct bge_softc *); 225 #if 0 /* XXX */ 226 static void bge_free_jumbo_mem(struct bge_softc *); 227 #endif 228 static void *bge_jalloc(struct bge_softc *); 229 static void bge_jfree(struct mbuf *, void *, size_t, void *); 230 static int bge_newbuf_std(struct bge_softc *, int, struct mbuf *, 231 bus_dmamap_t); 232 static int bge_newbuf_jumbo(struct bge_softc *, int, struct mbuf *); 233 static int bge_init_rx_ring_std(struct bge_softc *); 234 static void bge_free_rx_ring_std(struct bge_softc *); 235 static int bge_init_rx_ring_jumbo(struct bge_softc *); 236 static void bge_free_rx_ring_jumbo(struct bge_softc *); 237 static void bge_free_tx_ring(struct bge_softc *); 238 static int bge_init_tx_ring(struct bge_softc *); 239 240 static int bge_chipinit(struct bge_softc *); 241 static int bge_blockinit(struct bge_softc *); 242 static int bge_setpowerstate(struct bge_softc *, int); 243 static uint32_t bge_readmem_ind(struct bge_softc *, int); 244 static void bge_writemem_ind(struct bge_softc *, int, int); 245 static void bge_writembx(struct bge_softc *, int, int); 246 static void bge_writemem_direct(struct bge_softc *, int, int); 247 static void bge_writereg_ind(struct bge_softc *, int, int); 248 static void bge_set_max_readrq(struct bge_softc *); 249 250 static int bge_miibus_readreg(device_t, int, int); 251 static void bge_miibus_writereg(device_t, int, int, int); 252 static void bge_miibus_statchg(struct ifnet *); 253 254 #define BGE_RESET_START 1 255 #define BGE_RESET_STOP 2 256 static void bge_sig_post_reset(struct bge_softc *, int); 257 static void bge_sig_legacy(struct bge_softc *, int); 258 static void bge_sig_pre_reset(struct bge_softc *, int); 259 static void bge_stop_fw(struct bge_softc *); 260 static int bge_reset(struct bge_softc *); 261 static void bge_link_upd(struct bge_softc *); 262 static void bge_sysctl_init(struct bge_softc *); 263 static int bge_sysctl_verify(SYSCTLFN_PROTO); 264 265 #ifdef BGE_DEBUG 266 #define DPRINTF(x) if (bgedebug) printf x 267 #define DPRINTFN(n,x) if (bgedebug >= (n)) printf x 268 #define BGE_TSO_PRINTF(x) do { if (bge_tso_debug) printf x ;} while (0) 269 int bgedebug = 0; 270 int bge_tso_debug = 0; 271 void bge_debug_info(struct bge_softc *); 272 #else 273 #define DPRINTF(x) 274 #define DPRINTFN(n,x) 275 #define BGE_TSO_PRINTF(x) 276 #endif 277 278 #ifdef BGE_EVENT_COUNTERS 279 #define BGE_EVCNT_INCR(ev) (ev).ev_count++ 280 #define BGE_EVCNT_ADD(ev, val) (ev).ev_count += (val) 281 #define BGE_EVCNT_UPD(ev, val) (ev).ev_count = (val) 282 #else 283 #define BGE_EVCNT_INCR(ev) /* nothing */ 284 #define BGE_EVCNT_ADD(ev, val) /* nothing */ 285 #define BGE_EVCNT_UPD(ev, val) /* nothing */ 286 #endif 287 288 static const struct bge_product { 289 pci_vendor_id_t bp_vendor; 290 pci_product_id_t bp_product; 291 const char *bp_name; 292 } bge_products[] = { 293 /* 294 * The BCM5700 documentation seems to indicate that the hardware 295 * still has the Alteon vendor ID burned into it, though it 296 * should always be overridden by the value in the EEPROM. We'll 297 * check for it anyway. 298 */ 299 { PCI_VENDOR_ALTEON, 300 PCI_PRODUCT_ALTEON_BCM5700, 301 "Broadcom BCM5700 Gigabit Ethernet", 302 }, 303 { PCI_VENDOR_ALTEON, 304 PCI_PRODUCT_ALTEON_BCM5701, 305 "Broadcom BCM5701 Gigabit Ethernet", 306 }, 307 { PCI_VENDOR_ALTIMA, 308 PCI_PRODUCT_ALTIMA_AC1000, 309 "Altima AC1000 Gigabit Ethernet", 310 }, 311 { PCI_VENDOR_ALTIMA, 312 PCI_PRODUCT_ALTIMA_AC1001, 313 "Altima AC1001 Gigabit Ethernet", 314 }, 315 { PCI_VENDOR_ALTIMA, 316 PCI_PRODUCT_ALTIMA_AC9100, 317 "Altima AC9100 Gigabit Ethernet", 318 }, 319 { PCI_VENDOR_BROADCOM, 320 PCI_PRODUCT_BROADCOM_BCM5700, 321 "Broadcom BCM5700 Gigabit Ethernet", 322 }, 323 { PCI_VENDOR_BROADCOM, 324 PCI_PRODUCT_BROADCOM_BCM5701, 325 "Broadcom BCM5701 Gigabit Ethernet", 326 }, 327 { PCI_VENDOR_BROADCOM, 328 PCI_PRODUCT_BROADCOM_BCM5702, 329 "Broadcom BCM5702 Gigabit Ethernet", 330 }, 331 { PCI_VENDOR_BROADCOM, 332 PCI_PRODUCT_BROADCOM_BCM5702X, 333 "Broadcom BCM5702X Gigabit Ethernet" }, 334 { PCI_VENDOR_BROADCOM, 335 PCI_PRODUCT_BROADCOM_BCM5703, 336 "Broadcom BCM5703 Gigabit Ethernet", 337 }, 338 { PCI_VENDOR_BROADCOM, 339 PCI_PRODUCT_BROADCOM_BCM5703X, 340 "Broadcom BCM5703X Gigabit Ethernet", 341 }, 342 { PCI_VENDOR_BROADCOM, 343 PCI_PRODUCT_BROADCOM_BCM5703_ALT, 344 "Broadcom BCM5703 Gigabit Ethernet", 345 }, 346 { PCI_VENDOR_BROADCOM, 347 PCI_PRODUCT_BROADCOM_BCM5704C, 348 "Broadcom BCM5704C Dual Gigabit Ethernet", 349 }, 350 { PCI_VENDOR_BROADCOM, 351 PCI_PRODUCT_BROADCOM_BCM5704S, 352 "Broadcom BCM5704S Dual Gigabit Ethernet", 353 }, 354 { PCI_VENDOR_BROADCOM, 355 PCI_PRODUCT_BROADCOM_BCM5705, 356 "Broadcom BCM5705 Gigabit Ethernet", 357 }, 358 { PCI_VENDOR_BROADCOM, 359 PCI_PRODUCT_BROADCOM_BCM5705F, 360 "Broadcom BCM5705F Gigabit Ethernet", 361 }, 362 { PCI_VENDOR_BROADCOM, 363 PCI_PRODUCT_BROADCOM_BCM5705K, 364 "Broadcom BCM5705K Gigabit Ethernet", 365 }, 366 { PCI_VENDOR_BROADCOM, 367 PCI_PRODUCT_BROADCOM_BCM5705M, 368 "Broadcom BCM5705M Gigabit Ethernet", 369 }, 370 { PCI_VENDOR_BROADCOM, 371 PCI_PRODUCT_BROADCOM_BCM5705M_ALT, 372 "Broadcom BCM5705M Gigabit Ethernet", 373 }, 374 { PCI_VENDOR_BROADCOM, 375 PCI_PRODUCT_BROADCOM_BCM5714, 376 "Broadcom BCM5714 Gigabit Ethernet", 377 }, 378 { PCI_VENDOR_BROADCOM, 379 PCI_PRODUCT_BROADCOM_BCM5714S, 380 "Broadcom BCM5714S Gigabit Ethernet", 381 }, 382 { PCI_VENDOR_BROADCOM, 383 PCI_PRODUCT_BROADCOM_BCM5715, 384 "Broadcom BCM5715 Gigabit Ethernet", 385 }, 386 { PCI_VENDOR_BROADCOM, 387 PCI_PRODUCT_BROADCOM_BCM5715S, 388 "Broadcom BCM5715S Gigabit Ethernet", 389 }, 390 { PCI_VENDOR_BROADCOM, 391 PCI_PRODUCT_BROADCOM_BCM5717, 392 "Broadcom BCM5717 Gigabit Ethernet", 393 }, 394 { PCI_VENDOR_BROADCOM, 395 PCI_PRODUCT_BROADCOM_BCM5718, 396 "Broadcom BCM5718 Gigabit Ethernet", 397 }, 398 { PCI_VENDOR_BROADCOM, 399 PCI_PRODUCT_BROADCOM_BCM5720, 400 "Broadcom BCM5720 Gigabit Ethernet", 401 }, 402 { PCI_VENDOR_BROADCOM, 403 PCI_PRODUCT_BROADCOM_BCM5721, 404 "Broadcom BCM5721 Gigabit Ethernet", 405 }, 406 { PCI_VENDOR_BROADCOM, 407 PCI_PRODUCT_BROADCOM_BCM5722, 408 "Broadcom BCM5722 Gigabit Ethernet", 409 }, 410 { PCI_VENDOR_BROADCOM, 411 PCI_PRODUCT_BROADCOM_BCM5723, 412 "Broadcom BCM5723 Gigabit Ethernet", 413 }, 414 { PCI_VENDOR_BROADCOM, 415 PCI_PRODUCT_BROADCOM_BCM5724, 416 "Broadcom BCM5724 Gigabit Ethernet", 417 }, 418 { PCI_VENDOR_BROADCOM, 419 PCI_PRODUCT_BROADCOM_BCM5750, 420 "Broadcom BCM5750 Gigabit Ethernet", 421 }, 422 { PCI_VENDOR_BROADCOM, 423 PCI_PRODUCT_BROADCOM_BCM5750M, 424 "Broadcom BCM5750M Gigabit Ethernet", 425 }, 426 { PCI_VENDOR_BROADCOM, 427 PCI_PRODUCT_BROADCOM_BCM5751, 428 "Broadcom BCM5751 Gigabit Ethernet", 429 }, 430 { PCI_VENDOR_BROADCOM, 431 PCI_PRODUCT_BROADCOM_BCM5751F, 432 "Broadcom BCM5751F Gigabit Ethernet", 433 }, 434 { PCI_VENDOR_BROADCOM, 435 PCI_PRODUCT_BROADCOM_BCM5751M, 436 "Broadcom BCM5751M Gigabit Ethernet", 437 }, 438 { PCI_VENDOR_BROADCOM, 439 PCI_PRODUCT_BROADCOM_BCM5752, 440 "Broadcom BCM5752 Gigabit Ethernet", 441 }, 442 { PCI_VENDOR_BROADCOM, 443 PCI_PRODUCT_BROADCOM_BCM5752M, 444 "Broadcom BCM5752M Gigabit Ethernet", 445 }, 446 { PCI_VENDOR_BROADCOM, 447 PCI_PRODUCT_BROADCOM_BCM5753, 448 "Broadcom BCM5753 Gigabit Ethernet", 449 }, 450 { PCI_VENDOR_BROADCOM, 451 PCI_PRODUCT_BROADCOM_BCM5753F, 452 "Broadcom BCM5753F Gigabit Ethernet", 453 }, 454 { PCI_VENDOR_BROADCOM, 455 PCI_PRODUCT_BROADCOM_BCM5753M, 456 "Broadcom BCM5753M Gigabit Ethernet", 457 }, 458 { PCI_VENDOR_BROADCOM, 459 PCI_PRODUCT_BROADCOM_BCM5754, 460 "Broadcom BCM5754 Gigabit Ethernet", 461 }, 462 { PCI_VENDOR_BROADCOM, 463 PCI_PRODUCT_BROADCOM_BCM5754M, 464 "Broadcom BCM5754M Gigabit Ethernet", 465 }, 466 { PCI_VENDOR_BROADCOM, 467 PCI_PRODUCT_BROADCOM_BCM5755, 468 "Broadcom BCM5755 Gigabit Ethernet", 469 }, 470 { PCI_VENDOR_BROADCOM, 471 PCI_PRODUCT_BROADCOM_BCM5755M, 472 "Broadcom BCM5755M Gigabit Ethernet", 473 }, 474 { PCI_VENDOR_BROADCOM, 475 PCI_PRODUCT_BROADCOM_BCM5756, 476 "Broadcom BCM5756 Gigabit Ethernet", 477 }, 478 { PCI_VENDOR_BROADCOM, 479 PCI_PRODUCT_BROADCOM_BCM5761, 480 "Broadcom BCM5761 Gigabit Ethernet", 481 }, 482 { PCI_VENDOR_BROADCOM, 483 PCI_PRODUCT_BROADCOM_BCM5761E, 484 "Broadcom BCM5761E Gigabit Ethernet", 485 }, 486 { PCI_VENDOR_BROADCOM, 487 PCI_PRODUCT_BROADCOM_BCM5761S, 488 "Broadcom BCM5761S Gigabit Ethernet", 489 }, 490 { PCI_VENDOR_BROADCOM, 491 PCI_PRODUCT_BROADCOM_BCM5761SE, 492 "Broadcom BCM5761SE Gigabit Ethernet", 493 }, 494 { PCI_VENDOR_BROADCOM, 495 PCI_PRODUCT_BROADCOM_BCM5764, 496 "Broadcom BCM5764 Gigabit Ethernet", 497 }, 498 { PCI_VENDOR_BROADCOM, 499 PCI_PRODUCT_BROADCOM_BCM5780, 500 "Broadcom BCM5780 Gigabit Ethernet", 501 }, 502 { PCI_VENDOR_BROADCOM, 503 PCI_PRODUCT_BROADCOM_BCM5780S, 504 "Broadcom BCM5780S Gigabit Ethernet", 505 }, 506 { PCI_VENDOR_BROADCOM, 507 PCI_PRODUCT_BROADCOM_BCM5781, 508 "Broadcom BCM5781 Gigabit Ethernet", 509 }, 510 { PCI_VENDOR_BROADCOM, 511 PCI_PRODUCT_BROADCOM_BCM5782, 512 "Broadcom BCM5782 Gigabit Ethernet", 513 }, 514 { PCI_VENDOR_BROADCOM, 515 PCI_PRODUCT_BROADCOM_BCM5784M, 516 "BCM5784M NetLink 1000baseT Ethernet", 517 }, 518 { PCI_VENDOR_BROADCOM, 519 PCI_PRODUCT_BROADCOM_BCM5786, 520 "Broadcom BCM5786 Gigabit Ethernet", 521 }, 522 { PCI_VENDOR_BROADCOM, 523 PCI_PRODUCT_BROADCOM_BCM5787, 524 "Broadcom BCM5787 Gigabit Ethernet", 525 }, 526 { PCI_VENDOR_BROADCOM, 527 PCI_PRODUCT_BROADCOM_BCM5787M, 528 "Broadcom BCM5787M Gigabit Ethernet", 529 }, 530 { PCI_VENDOR_BROADCOM, 531 PCI_PRODUCT_BROADCOM_BCM5788, 532 "Broadcom BCM5788 Gigabit Ethernet", 533 }, 534 { PCI_VENDOR_BROADCOM, 535 PCI_PRODUCT_BROADCOM_BCM5789, 536 "Broadcom BCM5789 Gigabit Ethernet", 537 }, 538 { PCI_VENDOR_BROADCOM, 539 PCI_PRODUCT_BROADCOM_BCM5901, 540 "Broadcom BCM5901 Fast Ethernet", 541 }, 542 { PCI_VENDOR_BROADCOM, 543 PCI_PRODUCT_BROADCOM_BCM5901A2, 544 "Broadcom BCM5901A2 Fast Ethernet", 545 }, 546 { PCI_VENDOR_BROADCOM, 547 PCI_PRODUCT_BROADCOM_BCM5903M, 548 "Broadcom BCM5903M Fast Ethernet", 549 }, 550 { PCI_VENDOR_BROADCOM, 551 PCI_PRODUCT_BROADCOM_BCM5906, 552 "Broadcom BCM5906 Fast Ethernet", 553 }, 554 { PCI_VENDOR_BROADCOM, 555 PCI_PRODUCT_BROADCOM_BCM5906M, 556 "Broadcom BCM5906M Fast Ethernet", 557 }, 558 { PCI_VENDOR_BROADCOM, 559 PCI_PRODUCT_BROADCOM_BCM57760, 560 "Broadcom BCM57760 Fast Ethernet", 561 }, 562 { PCI_VENDOR_BROADCOM, 563 PCI_PRODUCT_BROADCOM_BCM57761, 564 "Broadcom BCM57761 Fast Ethernet", 565 }, 566 { PCI_VENDOR_BROADCOM, 567 PCI_PRODUCT_BROADCOM_BCM57762, 568 "Broadcom BCM57762 Gigabit Ethernet", 569 }, 570 { PCI_VENDOR_BROADCOM, 571 PCI_PRODUCT_BROADCOM_BCM57765, 572 "Broadcom BCM57765 Fast Ethernet", 573 }, 574 { PCI_VENDOR_BROADCOM, 575 PCI_PRODUCT_BROADCOM_BCM57780, 576 "Broadcom BCM57780 Fast Ethernet", 577 }, 578 { PCI_VENDOR_BROADCOM, 579 PCI_PRODUCT_BROADCOM_BCM57781, 580 "Broadcom BCM57781 Fast Ethernet", 581 }, 582 { PCI_VENDOR_BROADCOM, 583 PCI_PRODUCT_BROADCOM_BCM57785, 584 "Broadcom BCM57785 Fast Ethernet", 585 }, 586 { PCI_VENDOR_BROADCOM, 587 PCI_PRODUCT_BROADCOM_BCM57788, 588 "Broadcom BCM57788 Fast Ethernet", 589 }, 590 { PCI_VENDOR_BROADCOM, 591 PCI_PRODUCT_BROADCOM_BCM57790, 592 "Broadcom BCM57790 Fast Ethernet", 593 }, 594 { PCI_VENDOR_BROADCOM, 595 PCI_PRODUCT_BROADCOM_BCM57791, 596 "Broadcom BCM57791 Fast Ethernet", 597 }, 598 { PCI_VENDOR_BROADCOM, 599 PCI_PRODUCT_BROADCOM_BCM57795, 600 "Broadcom BCM57795 Fast Ethernet", 601 }, 602 { PCI_VENDOR_SCHNEIDERKOCH, 603 PCI_PRODUCT_SCHNEIDERKOCH_SK_9DX1, 604 "SysKonnect SK-9Dx1 Gigabit Ethernet", 605 }, 606 { PCI_VENDOR_3COM, 607 PCI_PRODUCT_3COM_3C996, 608 "3Com 3c996 Gigabit Ethernet", 609 }, 610 { PCI_VENDOR_FUJITSU4, 611 PCI_PRODUCT_FUJITSU4_PW008GE4, 612 "Fujitsu PW008GE4 Gigabit Ethernet", 613 }, 614 { PCI_VENDOR_FUJITSU4, 615 PCI_PRODUCT_FUJITSU4_PW008GE5, 616 "Fujitsu PW008GE5 Gigabit Ethernet", 617 }, 618 { PCI_VENDOR_FUJITSU4, 619 PCI_PRODUCT_FUJITSU4_PP250_450_LAN, 620 "Fujitsu Primepower 250/450 Gigabit Ethernet", 621 }, 622 { 0, 623 0, 624 NULL }, 625 }; 626 627 #define BGE_IS_5700_FAMILY(sc) ((sc)->bge_flags & BGE_5700_FAMILY) 628 #define BGE_IS_5714_FAMILY(sc) ((sc)->bge_flags & BGE_5714_FAMILY) 629 #define BGE_IS_5705_PLUS(sc) ((sc)->bge_flags & BGE_5705_PLUS) 630 #define BGE_IS_575X_PLUS(sc) ((sc)->bge_flags & BGE_575X_PLUS) 631 #define BGE_IS_5755_PLUS(sc) ((sc)->bge_flags & BGE_5755_PLUS) 632 #define BGE_IS_JUMBO_CAPABLE(sc) ((sc)->bge_flags & BGE_JUMBO_CAPABLE) 633 634 static const struct bge_revision { 635 uint32_t br_chipid; 636 const char *br_name; 637 } bge_revisions[] = { 638 { BGE_CHIPID_BCM5700_A0, "BCM5700 A0" }, 639 { BGE_CHIPID_BCM5700_A1, "BCM5700 A1" }, 640 { BGE_CHIPID_BCM5700_B0, "BCM5700 B0" }, 641 { BGE_CHIPID_BCM5700_B1, "BCM5700 B1" }, 642 { BGE_CHIPID_BCM5700_B2, "BCM5700 B2" }, 643 { BGE_CHIPID_BCM5700_B3, "BCM5700 B3" }, 644 /* This is treated like a BCM5700 Bx */ 645 { BGE_CHIPID_BCM5700_ALTIMA, "BCM5700 Altima" }, 646 { BGE_CHIPID_BCM5700_C0, "BCM5700 C0" }, 647 { BGE_CHIPID_BCM5701_A0, "BCM5701 A0" }, 648 { BGE_CHIPID_BCM5701_B0, "BCM5701 B0" }, 649 { BGE_CHIPID_BCM5701_B2, "BCM5701 B2" }, 650 { BGE_CHIPID_BCM5701_B5, "BCM5701 B5" }, 651 { BGE_CHIPID_BCM5703_A0, "BCM5702/5703 A0" }, 652 { BGE_CHIPID_BCM5703_A1, "BCM5702/5703 A1" }, 653 { BGE_CHIPID_BCM5703_A2, "BCM5702/5703 A2" }, 654 { BGE_CHIPID_BCM5703_A3, "BCM5702/5703 A3" }, 655 { BGE_CHIPID_BCM5703_B0, "BCM5702/5703 B0" }, 656 { BGE_CHIPID_BCM5704_A0, "BCM5704 A0" }, 657 { BGE_CHIPID_BCM5704_A1, "BCM5704 A1" }, 658 { BGE_CHIPID_BCM5704_A2, "BCM5704 A2" }, 659 { BGE_CHIPID_BCM5704_A3, "BCM5704 A3" }, 660 { BGE_CHIPID_BCM5704_B0, "BCM5704 B0" }, 661 { BGE_CHIPID_BCM5705_A0, "BCM5705 A0" }, 662 { BGE_CHIPID_BCM5705_A1, "BCM5705 A1" }, 663 { BGE_CHIPID_BCM5705_A2, "BCM5705 A2" }, 664 { BGE_CHIPID_BCM5705_A3, "BCM5705 A3" }, 665 { BGE_CHIPID_BCM5750_A0, "BCM5750 A0" }, 666 { BGE_CHIPID_BCM5750_A1, "BCM5750 A1" }, 667 { BGE_CHIPID_BCM5750_A3, "BCM5750 A3" }, 668 { BGE_CHIPID_BCM5750_B0, "BCM5750 B0" }, 669 { BGE_CHIPID_BCM5750_B1, "BCM5750 B1" }, 670 { BGE_CHIPID_BCM5750_C0, "BCM5750 C0" }, 671 { BGE_CHIPID_BCM5750_C1, "BCM5750 C1" }, 672 { BGE_CHIPID_BCM5750_C2, "BCM5750 C2" }, 673 { BGE_CHIPID_BCM5752_A0, "BCM5752 A0" }, 674 { BGE_CHIPID_BCM5752_A1, "BCM5752 A1" }, 675 { BGE_CHIPID_BCM5752_A2, "BCM5752 A2" }, 676 { BGE_CHIPID_BCM5714_A0, "BCM5714 A0" }, 677 { BGE_CHIPID_BCM5714_B0, "BCM5714 B0" }, 678 { BGE_CHIPID_BCM5714_B3, "BCM5714 B3" }, 679 { BGE_CHIPID_BCM5715_A0, "BCM5715 A0" }, 680 { BGE_CHIPID_BCM5715_A1, "BCM5715 A1" }, 681 { BGE_CHIPID_BCM5715_A3, "BCM5715 A3" }, 682 { BGE_CHIPID_BCM5755_A0, "BCM5755 A0" }, 683 { BGE_CHIPID_BCM5755_A1, "BCM5755 A1" }, 684 { BGE_CHIPID_BCM5755_A2, "BCM5755 A2" }, 685 { BGE_CHIPID_BCM5755_C0, "BCM5755 C0" }, 686 { BGE_CHIPID_BCM5761_A0, "BCM5761 A0" }, 687 { BGE_CHIPID_BCM5761_A1, "BCM5761 A1" }, 688 { BGE_CHIPID_BCM5784_A0, "BCM5784 A0" }, 689 { BGE_CHIPID_BCM5784_A1, "BCM5784 A1" }, 690 /* 5754 and 5787 share the same ASIC ID */ 691 { BGE_CHIPID_BCM5787_A0, "BCM5754/5787 A0" }, 692 { BGE_CHIPID_BCM5787_A1, "BCM5754/5787 A1" }, 693 { BGE_CHIPID_BCM5787_A2, "BCM5754/5787 A2" }, 694 { BGE_CHIPID_BCM5906_A0, "BCM5906 A0" }, 695 { BGE_CHIPID_BCM5906_A1, "BCM5906 A1" }, 696 { BGE_CHIPID_BCM5906_A2, "BCM5906 A2" }, 697 { BGE_CHIPID_BCM57780_A0, "BCM57780 A0" }, 698 { BGE_CHIPID_BCM57780_A1, "BCM57780 A1" }, 699 700 { 0, NULL } 701 }; 702 703 /* 704 * Some defaults for major revisions, so that newer steppings 705 * that we don't know about have a shot at working. 706 */ 707 static const struct bge_revision bge_majorrevs[] = { 708 { BGE_ASICREV_BCM5700, "unknown BCM5700" }, 709 { BGE_ASICREV_BCM5701, "unknown BCM5701" }, 710 { BGE_ASICREV_BCM5703, "unknown BCM5703" }, 711 { BGE_ASICREV_BCM5704, "unknown BCM5704" }, 712 { BGE_ASICREV_BCM5705, "unknown BCM5705" }, 713 { BGE_ASICREV_BCM5750, "unknown BCM5750" }, 714 { BGE_ASICREV_BCM5714_A0, "unknown BCM5714" }, 715 { BGE_ASICREV_BCM5752, "unknown BCM5752" }, 716 { BGE_ASICREV_BCM5780, "unknown BCM5780" }, 717 { BGE_ASICREV_BCM5714, "unknown BCM5714" }, 718 { BGE_ASICREV_BCM5755, "unknown BCM5755" }, 719 { BGE_ASICREV_BCM5761, "unknown BCM5761" }, 720 { BGE_ASICREV_BCM5784, "unknown BCM5784" }, 721 { BGE_ASICREV_BCM5785, "unknown BCM5785" }, 722 /* 5754 and 5787 share the same ASIC ID */ 723 { BGE_ASICREV_BCM5787, "unknown BCM5754/5787" }, 724 { BGE_ASICREV_BCM5906, "unknown BCM5906" }, 725 { BGE_ASICREV_BCM57780, "unknown BCM57780" }, 726 { BGE_ASICREV_BCM5717, "unknown BCM5717" }, 727 { BGE_ASICREV_BCM57765, "unknown BCM57765" }, 728 { BGE_ASICREV_BCM57766, "unknown BCM57766" }, 729 730 { 0, NULL } 731 }; 732 733 static int bge_allow_asf = 1; 734 735 CFATTACH_DECL_NEW(bge, sizeof(struct bge_softc), 736 bge_probe, bge_attach, NULL, NULL); 737 738 static uint32_t 739 bge_readmem_ind(struct bge_softc *sc, int off) 740 { 741 pcireg_t val; 742 743 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_BASEADDR, off); 744 val = pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_DATA); 745 return val; 746 } 747 748 static void 749 bge_writemem_ind(struct bge_softc *sc, int off, int val) 750 { 751 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_BASEADDR, off); 752 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_DATA, val); 753 } 754 755 /* 756 * PCI Express only 757 */ 758 static void 759 bge_set_max_readrq(struct bge_softc *sc) 760 { 761 pcireg_t val; 762 763 val = pci_conf_read(sc->sc_pc, sc->sc_pcitag, sc->bge_pciecap 764 + PCI_PCIE_DCSR); 765 if ((val & PCI_PCIE_DCSR_MAX_READ_REQ) != 766 BGE_PCIE_DEVCTL_MAX_READRQ_4096) { 767 aprint_verbose_dev(sc->bge_dev, 768 "adjust device control 0x%04x ", val); 769 val &= ~PCI_PCIE_DCSR_MAX_READ_REQ; 770 val |= BGE_PCIE_DEVCTL_MAX_READRQ_4096; 771 pci_conf_write(sc->sc_pc, sc->sc_pcitag, sc->bge_pciecap 772 + PCI_PCIE_DCSR, val); 773 aprint_verbose("-> 0x%04x\n", val); 774 } 775 } 776 777 #ifdef notdef 778 static uint32_t 779 bge_readreg_ind(struct bge_softc *sc, int off) 780 { 781 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_REG_BASEADDR, off); 782 return (pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_REG_DATA)); 783 } 784 #endif 785 786 static void 787 bge_writereg_ind(struct bge_softc *sc, int off, int val) 788 { 789 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_REG_BASEADDR, off); 790 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_REG_DATA, val); 791 } 792 793 static void 794 bge_writemem_direct(struct bge_softc *sc, int off, int val) 795 { 796 CSR_WRITE_4(sc, off, val); 797 } 798 799 static void 800 bge_writembx(struct bge_softc *sc, int off, int val) 801 { 802 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 803 off += BGE_LPMBX_IRQ0_HI - BGE_MBX_IRQ0_HI; 804 805 CSR_WRITE_4(sc, off, val); 806 } 807 808 static uint8_t 809 bge_nvram_getbyte(struct bge_softc *sc, int addr, uint8_t *dest) 810 { 811 uint32_t access, byte = 0; 812 int i; 813 814 /* Lock. */ 815 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_SET1); 816 for (i = 0; i < 8000; i++) { 817 if (CSR_READ_4(sc, BGE_NVRAM_SWARB) & BGE_NVRAMSWARB_GNT1) 818 break; 819 DELAY(20); 820 } 821 if (i == 8000) 822 return 1; 823 824 /* Enable access. */ 825 access = CSR_READ_4(sc, BGE_NVRAM_ACCESS); 826 CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access | BGE_NVRAMACC_ENABLE); 827 828 CSR_WRITE_4(sc, BGE_NVRAM_ADDR, addr & 0xfffffffc); 829 CSR_WRITE_4(sc, BGE_NVRAM_CMD, BGE_NVRAM_READCMD); 830 for (i = 0; i < BGE_TIMEOUT * 10; i++) { 831 DELAY(10); 832 if (CSR_READ_4(sc, BGE_NVRAM_CMD) & BGE_NVRAMCMD_DONE) { 833 DELAY(10); 834 break; 835 } 836 } 837 838 if (i == BGE_TIMEOUT * 10) { 839 aprint_error_dev(sc->bge_dev, "nvram read timed out\n"); 840 return 1; 841 } 842 843 /* Get result. */ 844 byte = CSR_READ_4(sc, BGE_NVRAM_RDDATA); 845 846 *dest = (bswap32(byte) >> ((addr % 4) * 8)) & 0xFF; 847 848 /* Disable access. */ 849 CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access); 850 851 /* Unlock. */ 852 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_CLR1); 853 CSR_READ_4(sc, BGE_NVRAM_SWARB); 854 855 return 0; 856 } 857 858 /* 859 * Read a sequence of bytes from NVRAM. 860 */ 861 static int 862 bge_read_nvram(struct bge_softc *sc, uint8_t *dest, int off, int cnt) 863 { 864 int error = 0, i; 865 uint8_t byte = 0; 866 867 if (BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5906) 868 return 1; 869 870 for (i = 0; i < cnt; i++) { 871 error = bge_nvram_getbyte(sc, off + i, &byte); 872 if (error) 873 break; 874 *(dest + i) = byte; 875 } 876 877 return (error ? 1 : 0); 878 } 879 880 /* 881 * Read a byte of data stored in the EEPROM at address 'addr.' The 882 * BCM570x supports both the traditional bitbang interface and an 883 * auto access interface for reading the EEPROM. We use the auto 884 * access method. 885 */ 886 static uint8_t 887 bge_eeprom_getbyte(struct bge_softc *sc, int addr, uint8_t *dest) 888 { 889 int i; 890 uint32_t byte = 0; 891 892 /* 893 * Enable use of auto EEPROM access so we can avoid 894 * having to use the bitbang method. 895 */ 896 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM); 897 898 /* Reset the EEPROM, load the clock period. */ 899 CSR_WRITE_4(sc, BGE_EE_ADDR, 900 BGE_EEADDR_RESET | BGE_EEHALFCLK(BGE_HALFCLK_384SCL)); 901 DELAY(20); 902 903 /* Issue the read EEPROM command. */ 904 CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr); 905 906 /* Wait for completion */ 907 for (i = 0; i < BGE_TIMEOUT * 10; i++) { 908 DELAY(10); 909 if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE) 910 break; 911 } 912 913 if (i == BGE_TIMEOUT * 10) { 914 aprint_error_dev(sc->bge_dev, "eeprom read timed out\n"); 915 return 1; 916 } 917 918 /* Get result. */ 919 byte = CSR_READ_4(sc, BGE_EE_DATA); 920 921 *dest = (byte >> ((addr % 4) * 8)) & 0xFF; 922 923 return 0; 924 } 925 926 /* 927 * Read a sequence of bytes from the EEPROM. 928 */ 929 static int 930 bge_read_eeprom(struct bge_softc *sc, void *destv, int off, int cnt) 931 { 932 int error = 0, i; 933 uint8_t byte = 0; 934 char *dest = destv; 935 936 for (i = 0; i < cnt; i++) { 937 error = bge_eeprom_getbyte(sc, off + i, &byte); 938 if (error) 939 break; 940 *(dest + i) = byte; 941 } 942 943 return (error ? 1 : 0); 944 } 945 946 static int 947 bge_miibus_readreg(device_t dev, int phy, int reg) 948 { 949 struct bge_softc *sc = device_private(dev); 950 uint32_t val; 951 uint32_t autopoll; 952 int i; 953 954 /* 955 * Broadcom's own driver always assumes the internal 956 * PHY is at GMII address 1. On some chips, the PHY responds 957 * to accesses at all addresses, which could cause us to 958 * bogusly attach the PHY 32 times at probe type. Always 959 * restricting the lookup to address 1 is simpler than 960 * trying to figure out which chips revisions should be 961 * special-cased. 962 */ 963 if (phy != 1) 964 return 0; 965 966 /* Reading with autopolling on may trigger PCI errors */ 967 autopoll = CSR_READ_4(sc, BGE_MI_MODE); 968 if (autopoll & BGE_MIMODE_AUTOPOLL) { 969 BGE_STS_CLRBIT(sc, BGE_STS_AUTOPOLL); 970 BGE_CLRBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 971 DELAY(40); 972 } 973 974 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_READ | BGE_MICOMM_BUSY | 975 BGE_MIPHY(phy) | BGE_MIREG(reg)); 976 977 for (i = 0; i < BGE_TIMEOUT; i++) { 978 val = CSR_READ_4(sc, BGE_MI_COMM); 979 if (!(val & BGE_MICOMM_BUSY)) 980 break; 981 delay(10); 982 } 983 984 if (i == BGE_TIMEOUT) { 985 aprint_error_dev(sc->bge_dev, "PHY read timed out\n"); 986 val = 0; 987 goto done; 988 } 989 990 val = CSR_READ_4(sc, BGE_MI_COMM); 991 992 done: 993 if (autopoll & BGE_MIMODE_AUTOPOLL) { 994 BGE_STS_SETBIT(sc, BGE_STS_AUTOPOLL); 995 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 996 DELAY(40); 997 } 998 999 if (val & BGE_MICOMM_READFAIL) 1000 return 0; 1001 1002 return (val & 0xFFFF); 1003 } 1004 1005 static void 1006 bge_miibus_writereg(device_t dev, int phy, int reg, int val) 1007 { 1008 struct bge_softc *sc = device_private(dev); 1009 uint32_t autopoll; 1010 int i; 1011 1012 if (phy!=1) { 1013 return; 1014 } 1015 1016 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906 && 1017 (reg == BRGPHY_MII_1000CTL || reg == BRGPHY_MII_AUXCTL)) { 1018 return; 1019 } 1020 1021 /* Reading with autopolling on may trigger PCI errors */ 1022 autopoll = CSR_READ_4(sc, BGE_MI_MODE); 1023 if (autopoll & BGE_MIMODE_AUTOPOLL) { 1024 delay(40); 1025 BGE_STS_CLRBIT(sc, BGE_STS_AUTOPOLL); 1026 BGE_CLRBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 1027 delay(10); /* 40 usec is supposed to be adequate */ 1028 } 1029 1030 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_WRITE | BGE_MICOMM_BUSY | 1031 BGE_MIPHY(phy) | BGE_MIREG(reg) | val); 1032 1033 for (i = 0; i < BGE_TIMEOUT; i++) { 1034 delay(10); 1035 if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY)) { 1036 delay(5); 1037 CSR_READ_4(sc, BGE_MI_COMM); 1038 break; 1039 } 1040 } 1041 1042 if (autopoll & BGE_MIMODE_AUTOPOLL) { 1043 BGE_STS_SETBIT(sc, BGE_STS_AUTOPOLL); 1044 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 1045 delay(40); 1046 } 1047 1048 if (i == BGE_TIMEOUT) 1049 aprint_error_dev(sc->bge_dev, "PHY read timed out\n"); 1050 } 1051 1052 static void 1053 bge_miibus_statchg(struct ifnet *ifp) 1054 { 1055 struct bge_softc *sc = ifp->if_softc; 1056 struct mii_data *mii = &sc->bge_mii; 1057 1058 /* 1059 * Get flow control negotiation result. 1060 */ 1061 if (IFM_SUBTYPE(mii->mii_media.ifm_cur->ifm_media) == IFM_AUTO && 1062 (mii->mii_media_active & IFM_ETH_FMASK) != sc->bge_flowflags) { 1063 sc->bge_flowflags = mii->mii_media_active & IFM_ETH_FMASK; 1064 mii->mii_media_active &= ~IFM_ETH_FMASK; 1065 } 1066 1067 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_PORTMODE); 1068 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T || 1069 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX) 1070 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_GMII); 1071 else 1072 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_MII); 1073 1074 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) 1075 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX); 1076 else 1077 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX); 1078 1079 /* 1080 * 802.3x flow control 1081 */ 1082 if (sc->bge_flowflags & IFM_ETH_RXPAUSE) 1083 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_FLOWCTL_ENABLE); 1084 else 1085 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_FLOWCTL_ENABLE); 1086 1087 if (sc->bge_flowflags & IFM_ETH_TXPAUSE) 1088 BGE_SETBIT(sc, BGE_TX_MODE, BGE_TXMODE_FLOWCTL_ENABLE); 1089 else 1090 BGE_CLRBIT(sc, BGE_TX_MODE, BGE_TXMODE_FLOWCTL_ENABLE); 1091 } 1092 1093 /* 1094 * Update rx threshold levels to values in a particular slot 1095 * of the interrupt-mitigation table bge_rx_threshes. 1096 */ 1097 static void 1098 bge_set_thresh(struct ifnet *ifp, int lvl) 1099 { 1100 struct bge_softc *sc = ifp->if_softc; 1101 int s; 1102 1103 /* For now, just save the new Rx-intr thresholds and record 1104 * that a threshold update is pending. Updating the hardware 1105 * registers here (even at splhigh()) is observed to 1106 * occasionaly cause glitches where Rx-interrupts are not 1107 * honoured for up to 10 seconds. jonathan (at) NetBSD.org, 2003-04-05 1108 */ 1109 s = splnet(); 1110 sc->bge_rx_coal_ticks = bge_rx_threshes[lvl].rx_ticks; 1111 sc->bge_rx_max_coal_bds = bge_rx_threshes[lvl].rx_max_bds; 1112 sc->bge_pending_rxintr_change = 1; 1113 splx(s); 1114 1115 return; 1116 } 1117 1118 1119 /* 1120 * Update Rx thresholds of all bge devices 1121 */ 1122 static void 1123 bge_update_all_threshes(int lvl) 1124 { 1125 struct ifnet *ifp; 1126 const char * const namebuf = "bge"; 1127 int namelen; 1128 1129 if (lvl < 0) 1130 lvl = 0; 1131 else if (lvl >= NBGE_RX_THRESH) 1132 lvl = NBGE_RX_THRESH - 1; 1133 1134 namelen = strlen(namebuf); 1135 /* 1136 * Now search all the interfaces for this name/number 1137 */ 1138 IFNET_FOREACH(ifp) { 1139 if (strncmp(ifp->if_xname, namebuf, namelen) != 0) 1140 continue; 1141 /* We got a match: update if doing auto-threshold-tuning */ 1142 if (bge_auto_thresh) 1143 bge_set_thresh(ifp, lvl); 1144 } 1145 } 1146 1147 /* 1148 * Handle events that have triggered interrupts. 1149 */ 1150 static void 1151 bge_handle_events(struct bge_softc *sc) 1152 { 1153 1154 return; 1155 } 1156 1157 /* 1158 * Memory management for jumbo frames. 1159 */ 1160 1161 static int 1162 bge_alloc_jumbo_mem(struct bge_softc *sc) 1163 { 1164 char *ptr, *kva; 1165 bus_dma_segment_t seg; 1166 int i, rseg, state, error; 1167 struct bge_jpool_entry *entry; 1168 1169 state = error = 0; 1170 1171 /* Grab a big chunk o' storage. */ 1172 if (bus_dmamem_alloc(sc->bge_dmatag, BGE_JMEM, PAGE_SIZE, 0, 1173 &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 1174 aprint_error_dev(sc->bge_dev, "can't alloc rx buffers\n"); 1175 return ENOBUFS; 1176 } 1177 1178 state = 1; 1179 if (bus_dmamem_map(sc->bge_dmatag, &seg, rseg, BGE_JMEM, (void **)&kva, 1180 BUS_DMA_NOWAIT)) { 1181 aprint_error_dev(sc->bge_dev, 1182 "can't map DMA buffers (%d bytes)\n", (int)BGE_JMEM); 1183 error = ENOBUFS; 1184 goto out; 1185 } 1186 1187 state = 2; 1188 if (bus_dmamap_create(sc->bge_dmatag, BGE_JMEM, 1, BGE_JMEM, 0, 1189 BUS_DMA_NOWAIT, &sc->bge_cdata.bge_rx_jumbo_map)) { 1190 aprint_error_dev(sc->bge_dev, "can't create DMA map\n"); 1191 error = ENOBUFS; 1192 goto out; 1193 } 1194 1195 state = 3; 1196 if (bus_dmamap_load(sc->bge_dmatag, sc->bge_cdata.bge_rx_jumbo_map, 1197 kva, BGE_JMEM, NULL, BUS_DMA_NOWAIT)) { 1198 aprint_error_dev(sc->bge_dev, "can't load DMA map\n"); 1199 error = ENOBUFS; 1200 goto out; 1201 } 1202 1203 state = 4; 1204 sc->bge_cdata.bge_jumbo_buf = (void *)kva; 1205 DPRINTFN(1,("bge_jumbo_buf = %p\n", sc->bge_cdata.bge_jumbo_buf)); 1206 1207 SLIST_INIT(&sc->bge_jfree_listhead); 1208 SLIST_INIT(&sc->bge_jinuse_listhead); 1209 1210 /* 1211 * Now divide it up into 9K pieces and save the addresses 1212 * in an array. 1213 */ 1214 ptr = sc->bge_cdata.bge_jumbo_buf; 1215 for (i = 0; i < BGE_JSLOTS; i++) { 1216 sc->bge_cdata.bge_jslots[i] = ptr; 1217 ptr += BGE_JLEN; 1218 entry = malloc(sizeof(struct bge_jpool_entry), 1219 M_DEVBUF, M_NOWAIT); 1220 if (entry == NULL) { 1221 aprint_error_dev(sc->bge_dev, 1222 "no memory for jumbo buffer queue!\n"); 1223 error = ENOBUFS; 1224 goto out; 1225 } 1226 entry->slot = i; 1227 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, 1228 entry, jpool_entries); 1229 } 1230 out: 1231 if (error != 0) { 1232 switch (state) { 1233 case 4: 1234 bus_dmamap_unload(sc->bge_dmatag, 1235 sc->bge_cdata.bge_rx_jumbo_map); 1236 case 3: 1237 bus_dmamap_destroy(sc->bge_dmatag, 1238 sc->bge_cdata.bge_rx_jumbo_map); 1239 case 2: 1240 bus_dmamem_unmap(sc->bge_dmatag, kva, BGE_JMEM); 1241 case 1: 1242 bus_dmamem_free(sc->bge_dmatag, &seg, rseg); 1243 break; 1244 default: 1245 break; 1246 } 1247 } 1248 1249 return error; 1250 } 1251 1252 /* 1253 * Allocate a jumbo buffer. 1254 */ 1255 static void * 1256 bge_jalloc(struct bge_softc *sc) 1257 { 1258 struct bge_jpool_entry *entry; 1259 1260 entry = SLIST_FIRST(&sc->bge_jfree_listhead); 1261 1262 if (entry == NULL) { 1263 aprint_error_dev(sc->bge_dev, "no free jumbo buffers\n"); 1264 return NULL; 1265 } 1266 1267 SLIST_REMOVE_HEAD(&sc->bge_jfree_listhead, jpool_entries); 1268 SLIST_INSERT_HEAD(&sc->bge_jinuse_listhead, entry, jpool_entries); 1269 return (sc->bge_cdata.bge_jslots[entry->slot]); 1270 } 1271 1272 /* 1273 * Release a jumbo buffer. 1274 */ 1275 static void 1276 bge_jfree(struct mbuf *m, void *buf, size_t size, void *arg) 1277 { 1278 struct bge_jpool_entry *entry; 1279 struct bge_softc *sc; 1280 int i, s; 1281 1282 /* Extract the softc struct pointer. */ 1283 sc = (struct bge_softc *)arg; 1284 1285 if (sc == NULL) 1286 panic("bge_jfree: can't find softc pointer!"); 1287 1288 /* calculate the slot this buffer belongs to */ 1289 1290 i = ((char *)buf 1291 - (char *)sc->bge_cdata.bge_jumbo_buf) / BGE_JLEN; 1292 1293 if ((i < 0) || (i >= BGE_JSLOTS)) 1294 panic("bge_jfree: asked to free buffer that we don't manage!"); 1295 1296 s = splvm(); 1297 entry = SLIST_FIRST(&sc->bge_jinuse_listhead); 1298 if (entry == NULL) 1299 panic("bge_jfree: buffer not in use!"); 1300 entry->slot = i; 1301 SLIST_REMOVE_HEAD(&sc->bge_jinuse_listhead, jpool_entries); 1302 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, entry, jpool_entries); 1303 1304 if (__predict_true(m != NULL)) 1305 pool_cache_put(mb_cache, m); 1306 splx(s); 1307 } 1308 1309 1310 /* 1311 * Initialize a standard receive ring descriptor. 1312 */ 1313 static int 1314 bge_newbuf_std(struct bge_softc *sc, int i, struct mbuf *m, 1315 bus_dmamap_t dmamap) 1316 { 1317 struct mbuf *m_new = NULL; 1318 struct bge_rx_bd *r; 1319 int error; 1320 1321 if (dmamap == NULL) { 1322 error = bus_dmamap_create(sc->bge_dmatag, MCLBYTES, 1, 1323 MCLBYTES, 0, BUS_DMA_NOWAIT, &dmamap); 1324 if (error != 0) 1325 return error; 1326 } 1327 1328 sc->bge_cdata.bge_rx_std_map[i] = dmamap; 1329 1330 if (m == NULL) { 1331 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1332 if (m_new == NULL) 1333 return ENOBUFS; 1334 1335 MCLGET(m_new, M_DONTWAIT); 1336 if (!(m_new->m_flags & M_EXT)) { 1337 m_freem(m_new); 1338 return ENOBUFS; 1339 } 1340 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1341 1342 } else { 1343 m_new = m; 1344 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1345 m_new->m_data = m_new->m_ext.ext_buf; 1346 } 1347 if (!(sc->bge_flags & BGE_RX_ALIGNBUG)) 1348 m_adj(m_new, ETHER_ALIGN); 1349 if (bus_dmamap_load_mbuf(sc->bge_dmatag, dmamap, m_new, 1350 BUS_DMA_READ|BUS_DMA_NOWAIT)) 1351 return ENOBUFS; 1352 bus_dmamap_sync(sc->bge_dmatag, dmamap, 0, dmamap->dm_mapsize, 1353 BUS_DMASYNC_PREREAD); 1354 1355 sc->bge_cdata.bge_rx_std_chain[i] = m_new; 1356 r = &sc->bge_rdata->bge_rx_std_ring[i]; 1357 BGE_HOSTADDR(r->bge_addr, dmamap->dm_segs[0].ds_addr); 1358 r->bge_flags = BGE_RXBDFLAG_END; 1359 r->bge_len = m_new->m_len; 1360 r->bge_idx = i; 1361 1362 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 1363 offsetof(struct bge_ring_data, bge_rx_std_ring) + 1364 i * sizeof (struct bge_rx_bd), 1365 sizeof (struct bge_rx_bd), 1366 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1367 1368 return 0; 1369 } 1370 1371 /* 1372 * Initialize a jumbo receive ring descriptor. This allocates 1373 * a jumbo buffer from the pool managed internally by the driver. 1374 */ 1375 static int 1376 bge_newbuf_jumbo(struct bge_softc *sc, int i, struct mbuf *m) 1377 { 1378 struct mbuf *m_new = NULL; 1379 struct bge_rx_bd *r; 1380 void *buf = NULL; 1381 1382 if (m == NULL) { 1383 1384 /* Allocate the mbuf. */ 1385 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1386 if (m_new == NULL) 1387 return ENOBUFS; 1388 1389 /* Allocate the jumbo buffer */ 1390 buf = bge_jalloc(sc); 1391 if (buf == NULL) { 1392 m_freem(m_new); 1393 aprint_error_dev(sc->bge_dev, 1394 "jumbo allocation failed -- packet dropped!\n"); 1395 return ENOBUFS; 1396 } 1397 1398 /* Attach the buffer to the mbuf. */ 1399 m_new->m_len = m_new->m_pkthdr.len = BGE_JUMBO_FRAMELEN; 1400 MEXTADD(m_new, buf, BGE_JUMBO_FRAMELEN, M_DEVBUF, 1401 bge_jfree, sc); 1402 m_new->m_flags |= M_EXT_RW; 1403 } else { 1404 m_new = m; 1405 buf = m_new->m_data = m_new->m_ext.ext_buf; 1406 m_new->m_ext.ext_size = BGE_JUMBO_FRAMELEN; 1407 } 1408 if (!(sc->bge_flags & BGE_RX_ALIGNBUG)) 1409 m_adj(m_new, ETHER_ALIGN); 1410 bus_dmamap_sync(sc->bge_dmatag, sc->bge_cdata.bge_rx_jumbo_map, 1411 mtod(m_new, char *) - (char *)sc->bge_cdata.bge_jumbo_buf, BGE_JLEN, 1412 BUS_DMASYNC_PREREAD); 1413 /* Set up the descriptor. */ 1414 r = &sc->bge_rdata->bge_rx_jumbo_ring[i]; 1415 sc->bge_cdata.bge_rx_jumbo_chain[i] = m_new; 1416 BGE_HOSTADDR(r->bge_addr, BGE_JUMBO_DMA_ADDR(sc, m_new)); 1417 r->bge_flags = BGE_RXBDFLAG_END|BGE_RXBDFLAG_JUMBO_RING; 1418 r->bge_len = m_new->m_len; 1419 r->bge_idx = i; 1420 1421 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 1422 offsetof(struct bge_ring_data, bge_rx_jumbo_ring) + 1423 i * sizeof (struct bge_rx_bd), 1424 sizeof (struct bge_rx_bd), 1425 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1426 1427 return 0; 1428 } 1429 1430 /* 1431 * The standard receive ring has 512 entries in it. At 2K per mbuf cluster, 1432 * that's 1MB or memory, which is a lot. For now, we fill only the first 1433 * 256 ring entries and hope that our CPU is fast enough to keep up with 1434 * the NIC. 1435 */ 1436 static int 1437 bge_init_rx_ring_std(struct bge_softc *sc) 1438 { 1439 int i; 1440 1441 if (sc->bge_flags & BGE_RXRING_VALID) 1442 return 0; 1443 1444 for (i = 0; i < BGE_SSLOTS; i++) { 1445 if (bge_newbuf_std(sc, i, NULL, 0) == ENOBUFS) 1446 return ENOBUFS; 1447 } 1448 1449 sc->bge_std = i - 1; 1450 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std); 1451 1452 sc->bge_flags |= BGE_RXRING_VALID; 1453 1454 return 0; 1455 } 1456 1457 static void 1458 bge_free_rx_ring_std(struct bge_softc *sc) 1459 { 1460 int i; 1461 1462 if (!(sc->bge_flags & BGE_RXRING_VALID)) 1463 return; 1464 1465 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { 1466 if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) { 1467 m_freem(sc->bge_cdata.bge_rx_std_chain[i]); 1468 sc->bge_cdata.bge_rx_std_chain[i] = NULL; 1469 bus_dmamap_destroy(sc->bge_dmatag, 1470 sc->bge_cdata.bge_rx_std_map[i]); 1471 } 1472 memset((char *)&sc->bge_rdata->bge_rx_std_ring[i], 0, 1473 sizeof(struct bge_rx_bd)); 1474 } 1475 1476 sc->bge_flags &= ~BGE_RXRING_VALID; 1477 } 1478 1479 static int 1480 bge_init_rx_ring_jumbo(struct bge_softc *sc) 1481 { 1482 int i; 1483 volatile struct bge_rcb *rcb; 1484 1485 if (sc->bge_flags & BGE_JUMBO_RXRING_VALID) 1486 return 0; 1487 1488 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 1489 if (bge_newbuf_jumbo(sc, i, NULL) == ENOBUFS) 1490 return ENOBUFS; 1491 } 1492 1493 sc->bge_jumbo = i - 1; 1494 sc->bge_flags |= BGE_JUMBO_RXRING_VALID; 1495 1496 rcb = &sc->bge_rdata->bge_info.bge_jumbo_rx_rcb; 1497 rcb->bge_maxlen_flags = 0; 1498 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 1499 1500 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo); 1501 1502 return 0; 1503 } 1504 1505 static void 1506 bge_free_rx_ring_jumbo(struct bge_softc *sc) 1507 { 1508 int i; 1509 1510 if (!(sc->bge_flags & BGE_JUMBO_RXRING_VALID)) 1511 return; 1512 1513 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 1514 if (sc->bge_cdata.bge_rx_jumbo_chain[i] != NULL) { 1515 m_freem(sc->bge_cdata.bge_rx_jumbo_chain[i]); 1516 sc->bge_cdata.bge_rx_jumbo_chain[i] = NULL; 1517 } 1518 memset((char *)&sc->bge_rdata->bge_rx_jumbo_ring[i], 0, 1519 sizeof(struct bge_rx_bd)); 1520 } 1521 1522 sc->bge_flags &= ~BGE_JUMBO_RXRING_VALID; 1523 } 1524 1525 static void 1526 bge_free_tx_ring(struct bge_softc *sc) 1527 { 1528 int i; 1529 struct txdmamap_pool_entry *dma; 1530 1531 if (!(sc->bge_flags & BGE_TXRING_VALID)) 1532 return; 1533 1534 for (i = 0; i < BGE_TX_RING_CNT; i++) { 1535 if (sc->bge_cdata.bge_tx_chain[i] != NULL) { 1536 m_freem(sc->bge_cdata.bge_tx_chain[i]); 1537 sc->bge_cdata.bge_tx_chain[i] = NULL; 1538 SLIST_INSERT_HEAD(&sc->txdma_list, sc->txdma[i], 1539 link); 1540 sc->txdma[i] = 0; 1541 } 1542 memset((char *)&sc->bge_rdata->bge_tx_ring[i], 0, 1543 sizeof(struct bge_tx_bd)); 1544 } 1545 1546 while ((dma = SLIST_FIRST(&sc->txdma_list))) { 1547 SLIST_REMOVE_HEAD(&sc->txdma_list, link); 1548 bus_dmamap_destroy(sc->bge_dmatag, dma->dmamap); 1549 free(dma, M_DEVBUF); 1550 } 1551 1552 sc->bge_flags &= ~BGE_TXRING_VALID; 1553 } 1554 1555 static int 1556 bge_init_tx_ring(struct bge_softc *sc) 1557 { 1558 int i; 1559 bus_dmamap_t dmamap; 1560 struct txdmamap_pool_entry *dma; 1561 1562 if (sc->bge_flags & BGE_TXRING_VALID) 1563 return 0; 1564 1565 sc->bge_txcnt = 0; 1566 sc->bge_tx_saved_considx = 0; 1567 1568 /* Initialize transmit producer index for host-memory send ring. */ 1569 sc->bge_tx_prodidx = 0; 1570 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx); 1571 /* 5700 b2 errata */ 1572 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX) 1573 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx); 1574 1575 /* NIC-memory send ring not used; initialize to zero. */ 1576 bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0); 1577 /* 5700 b2 errata */ 1578 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX) 1579 bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0); 1580 1581 SLIST_INIT(&sc->txdma_list); 1582 for (i = 0; i < BGE_RSLOTS; i++) { 1583 if (bus_dmamap_create(sc->bge_dmatag, BGE_TXDMA_MAX, 1584 BGE_NTXSEG, ETHER_MAX_LEN_JUMBO, 0, BUS_DMA_NOWAIT, 1585 &dmamap)) 1586 return ENOBUFS; 1587 if (dmamap == NULL) 1588 panic("dmamap NULL in bge_init_tx_ring"); 1589 dma = malloc(sizeof(*dma), M_DEVBUF, M_NOWAIT); 1590 if (dma == NULL) { 1591 aprint_error_dev(sc->bge_dev, 1592 "can't alloc txdmamap_pool_entry\n"); 1593 bus_dmamap_destroy(sc->bge_dmatag, dmamap); 1594 return ENOMEM; 1595 } 1596 dma->dmamap = dmamap; 1597 SLIST_INSERT_HEAD(&sc->txdma_list, dma, link); 1598 } 1599 1600 sc->bge_flags |= BGE_TXRING_VALID; 1601 1602 return 0; 1603 } 1604 1605 static void 1606 bge_setmulti(struct bge_softc *sc) 1607 { 1608 struct ethercom *ac = &sc->ethercom; 1609 struct ifnet *ifp = &ac->ec_if; 1610 struct ether_multi *enm; 1611 struct ether_multistep step; 1612 uint32_t hashes[4] = { 0, 0, 0, 0 }; 1613 uint32_t h; 1614 int i; 1615 1616 if (ifp->if_flags & IFF_PROMISC) 1617 goto allmulti; 1618 1619 /* Now program new ones. */ 1620 ETHER_FIRST_MULTI(step, ac, enm); 1621 while (enm != NULL) { 1622 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1623 /* 1624 * We must listen to a range of multicast addresses. 1625 * For now, just accept all multicasts, rather than 1626 * trying to set only those filter bits needed to match 1627 * the range. (At this time, the only use of address 1628 * ranges is for IP multicast routing, for which the 1629 * range is big enough to require all bits set.) 1630 */ 1631 goto allmulti; 1632 } 1633 1634 h = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN); 1635 1636 /* Just want the 7 least-significant bits. */ 1637 h &= 0x7f; 1638 1639 hashes[(h & 0x60) >> 5] |= 1 << (h & 0x1F); 1640 ETHER_NEXT_MULTI(step, enm); 1641 } 1642 1643 ifp->if_flags &= ~IFF_ALLMULTI; 1644 goto setit; 1645 1646 allmulti: 1647 ifp->if_flags |= IFF_ALLMULTI; 1648 hashes[0] = hashes[1] = hashes[2] = hashes[3] = 0xffffffff; 1649 1650 setit: 1651 for (i = 0; i < 4; i++) 1652 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]); 1653 } 1654 1655 static void 1656 bge_sig_pre_reset(struct bge_softc *sc, int type) 1657 { 1658 /* 1659 * Some chips don't like this so only do this if ASF is enabled 1660 */ 1661 if (sc->bge_asf_mode) 1662 bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM, BGE_MAGIC_NUMBER); 1663 1664 if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) { 1665 switch (type) { 1666 case BGE_RESET_START: 1667 bge_writemem_ind(sc, BGE_SDI_STATUS, 0x1); /* START */ 1668 break; 1669 case BGE_RESET_STOP: 1670 bge_writemem_ind(sc, BGE_SDI_STATUS, 0x2); /* UNLOAD */ 1671 break; 1672 } 1673 } 1674 } 1675 1676 static void 1677 bge_sig_post_reset(struct bge_softc *sc, int type) 1678 { 1679 1680 if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) { 1681 switch (type) { 1682 case BGE_RESET_START: 1683 bge_writemem_ind(sc, BGE_SDI_STATUS, 0x80000001); 1684 /* START DONE */ 1685 break; 1686 case BGE_RESET_STOP: 1687 bge_writemem_ind(sc, BGE_SDI_STATUS, 0x80000002); 1688 break; 1689 } 1690 } 1691 } 1692 1693 static void 1694 bge_sig_legacy(struct bge_softc *sc, int type) 1695 { 1696 1697 if (sc->bge_asf_mode) { 1698 switch (type) { 1699 case BGE_RESET_START: 1700 bge_writemem_ind(sc, BGE_SDI_STATUS, 0x1); /* START */ 1701 break; 1702 case BGE_RESET_STOP: 1703 bge_writemem_ind(sc, BGE_SDI_STATUS, 0x2); /* UNLOAD */ 1704 break; 1705 } 1706 } 1707 } 1708 1709 static void 1710 bge_stop_fw(struct bge_softc *sc) 1711 { 1712 int i; 1713 1714 if (sc->bge_asf_mode) { 1715 bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM_FW, BGE_FW_PAUSE); 1716 CSR_WRITE_4(sc, BGE_CPU_EVENT, 1717 CSR_READ_4(sc, BGE_CPU_EVENT) | (1 << 14)); 1718 1719 for (i = 0; i < 100; i++) { 1720 if (!(CSR_READ_4(sc, BGE_CPU_EVENT) & (1 << 14))) 1721 break; 1722 DELAY(10); 1723 } 1724 } 1725 } 1726 1727 static int 1728 bge_poll_fw(struct bge_softc *sc) 1729 { 1730 uint32_t val; 1731 int i; 1732 1733 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 1734 for (i = 0; i < BGE_TIMEOUT; i++) { 1735 val = CSR_READ_4(sc, BGE_VCPU_STATUS); 1736 if (val & BGE_VCPU_STATUS_INIT_DONE) 1737 break; 1738 DELAY(100); 1739 } 1740 if (i >= BGE_TIMEOUT) { 1741 aprint_error_dev(sc->bge_dev, "reset timed out\n"); 1742 return -1; 1743 } 1744 } else if ((sc->bge_flags & BGE_NO_EEPROM) == 0) { 1745 /* 1746 * Poll the value location we just wrote until 1747 * we see the 1's complement of the magic number. 1748 * This indicates that the firmware initialization 1749 * is complete. 1750 * XXX 1000ms for Flash and 10000ms for SEEPROM. 1751 */ 1752 for (i = 0; i < BGE_TIMEOUT; i++) { 1753 val = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM); 1754 if (val == ~BGE_MAGIC_NUMBER) 1755 break; 1756 DELAY(10); 1757 } 1758 1759 if (i >= BGE_TIMEOUT) { 1760 aprint_error_dev(sc->bge_dev, 1761 "firmware handshake timed out, val = %x\n", val); 1762 return -1; 1763 } 1764 } 1765 1766 return 0; 1767 } 1768 1769 /* 1770 * Do endian, PCI and DMA initialization. Also check the on-board ROM 1771 * self-test results. 1772 */ 1773 static int 1774 bge_chipinit(struct bge_softc *sc) 1775 { 1776 int i; 1777 uint32_t dma_rw_ctl; 1778 1779 /* Set endianness before we access any non-PCI registers. */ 1780 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MISC_CTL, 1781 BGE_INIT); 1782 1783 /* Set power state to D0. */ 1784 bge_setpowerstate(sc, 0); 1785 1786 /* Clear the MAC control register */ 1787 CSR_WRITE_4(sc, BGE_MAC_MODE, 0); 1788 1789 /* 1790 * Clear the MAC statistics block in the NIC's 1791 * internal memory. 1792 */ 1793 for (i = BGE_STATS_BLOCK; 1794 i < BGE_STATS_BLOCK_END + 1; i += sizeof(uint32_t)) 1795 BGE_MEMWIN_WRITE(sc->sc_pc, sc->sc_pcitag, i, 0); 1796 1797 for (i = BGE_STATUS_BLOCK; 1798 i < BGE_STATUS_BLOCK_END + 1; i += sizeof(uint32_t)) 1799 BGE_MEMWIN_WRITE(sc->sc_pc, sc->sc_pcitag, i, 0); 1800 1801 /* Set up the PCI DMA control register. */ 1802 dma_rw_ctl = BGE_PCI_READ_CMD | BGE_PCI_WRITE_CMD; 1803 if (sc->bge_flags & BGE_PCIE) { 1804 /* Read watermark not used, 128 bytes for write. */ 1805 DPRINTFN(4, ("(%s: PCI-Express DMA setting)\n", 1806 device_xname(sc->bge_dev))); 1807 dma_rw_ctl |= BGE_PCIDMARWCTL_WR_WAT_SHIFT(3); 1808 } else if (sc->bge_flags & BGE_PCIX) { 1809 DPRINTFN(4, ("(:%s: PCI-X DMA setting)\n", 1810 device_xname(sc->bge_dev))); 1811 /* PCI-X bus */ 1812 if (BGE_IS_5714_FAMILY(sc)) { 1813 /* 256 bytes for read and write. */ 1814 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(2) | 1815 BGE_PCIDMARWCTL_WR_WAT_SHIFT(2); 1816 1817 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5780) 1818 dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL; 1819 else 1820 dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE_LOCAL; 1821 } else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) { 1822 /* 1536 bytes for read, 384 bytes for write. */ 1823 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(7) | 1824 BGE_PCIDMARWCTL_WR_WAT_SHIFT(3); 1825 } else { 1826 /* 384 bytes for read and write. */ 1827 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(3) | 1828 BGE_PCIDMARWCTL_WR_WAT_SHIFT(3) | 1829 (0x0F); 1830 } 1831 1832 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5703 || 1833 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) { 1834 uint32_t tmp; 1835 1836 /* Set ONEDMA_ATONCE for hardware workaround. */ 1837 tmp = CSR_READ_4(sc, BGE_PCI_CLKCTL) & 0x1f; 1838 if (tmp == 6 || tmp == 7) 1839 dma_rw_ctl |= 1840 BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL; 1841 1842 /* Set PCI-X DMA write workaround. */ 1843 dma_rw_ctl |= BGE_PCIDMARWCTL_ASRT_ALL_BE; 1844 } 1845 } else { 1846 /* Conventional PCI bus: 256 bytes for read and write. */ 1847 DPRINTFN(4, ("(%s: PCI 2.2 DMA setting)\n", 1848 device_xname(sc->bge_dev))); 1849 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(7) | 1850 BGE_PCIDMARWCTL_WR_WAT_SHIFT(7); 1851 1852 if (BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5705 && 1853 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5750) 1854 dma_rw_ctl |= 0x0F; 1855 } 1856 1857 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 1858 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5701) 1859 dma_rw_ctl |= BGE_PCIDMARWCTL_USE_MRM | 1860 BGE_PCIDMARWCTL_ASRT_ALL_BE; 1861 1862 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5703 || 1863 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) 1864 dma_rw_ctl &= ~BGE_PCIDMARWCTL_MINDMA; 1865 1866 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_DMA_RW_CTL, 1867 dma_rw_ctl); 1868 1869 /* 1870 * Set up general mode register. 1871 */ 1872 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS | 1873 BGE_MODECTL_MAC_ATTN_INTR | BGE_MODECTL_HOST_SEND_BDS | 1874 BGE_MODECTL_TX_NO_PHDR_CSUM); 1875 1876 /* 1877 * BCM5701 B5 have a bug causing data corruption when using 1878 * 64-bit DMA reads, which can be terminated early and then 1879 * completed later as 32-bit accesses, in combination with 1880 * certain bridges. 1881 */ 1882 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5701 && 1883 sc->bge_chipid == BGE_CHIPID_BCM5701_B5) 1884 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_FORCE_PCI32); 1885 1886 /* 1887 * Tell the firmware the driver is running 1888 */ 1889 if (sc->bge_asf_mode & ASF_STACKUP) 1890 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 1891 1892 /* 1893 * Disable memory write invalidate. Apparently it is not supported 1894 * properly by these devices. 1895 */ 1896 PCI_CLRBIT(sc->sc_pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG, 1897 PCI_COMMAND_INVALIDATE_ENABLE); 1898 1899 #ifdef __brokenalpha__ 1900 /* 1901 * Must insure that we do not cross an 8K (bytes) boundary 1902 * for DMA reads. Our highest limit is 1K bytes. This is a 1903 * restriction on some ALPHA platforms with early revision 1904 * 21174 PCI chipsets, such as the AlphaPC 164lx 1905 */ 1906 PCI_SETBIT(sc, BGE_PCI_DMA_RW_CTL, BGE_PCI_READ_BNDRY_1024, 4); 1907 #endif 1908 1909 /* Set the timer prescaler (always 66MHz) */ 1910 CSR_WRITE_4(sc, BGE_MISC_CFG, 65 << 1/*BGE_32BITTIME_66MHZ*/); 1911 1912 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 1913 DELAY(40); /* XXX */ 1914 1915 /* Put PHY into ready state */ 1916 BGE_CLRBIT(sc, BGE_MISC_CFG, BGE_MISCCFG_EPHY_IDDQ); 1917 CSR_READ_4(sc, BGE_MISC_CFG); /* Flush */ 1918 DELAY(40); 1919 } 1920 1921 return 0; 1922 } 1923 1924 static int 1925 bge_blockinit(struct bge_softc *sc) 1926 { 1927 volatile struct bge_rcb *rcb; 1928 bus_size_t rcb_addr; 1929 int i; 1930 struct ifnet *ifp = &sc->ethercom.ec_if; 1931 bge_hostaddr taddr; 1932 uint32_t val; 1933 1934 /* 1935 * Initialize the memory window pointer register so that 1936 * we can access the first 32K of internal NIC RAM. This will 1937 * allow us to set up the TX send ring RCBs and the RX return 1938 * ring RCBs, plus other things which live in NIC memory. 1939 */ 1940 1941 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_BASEADDR, 0); 1942 1943 /* Step 33: Configure mbuf memory pool */ 1944 if (BGE_IS_5700_FAMILY(sc)) { 1945 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, 1946 BGE_BUFFPOOL_1); 1947 1948 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) 1949 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000); 1950 else 1951 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000); 1952 1953 /* Configure DMA resource pool */ 1954 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_BASEADDR, 1955 BGE_DMA_DESCRIPTORS); 1956 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LEN, 0x2000); 1957 } 1958 1959 /* Step 35: Configure mbuf pool watermarks */ 1960 #ifdef ORIG_WPAUL_VALUES 1961 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 24); 1962 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 24); 1963 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 48); 1964 #else 1965 1966 /* new broadcom docs strongly recommend these: */ 1967 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5717 || 1968 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57765 || 1969 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57766) { 1970 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0); 1971 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x2a); 1972 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0xa0); 1973 } else if (BGE_IS_5705_PLUS(sc)) { 1974 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0); 1975 1976 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 1977 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x04); 1978 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x10); 1979 } else { 1980 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x10); 1981 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60); 1982 } 1983 } else if (!BGE_IS_5705_PLUS(sc)) { 1984 if (ifp->if_mtu > ETHER_MAX_LEN) { 1985 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x50); 1986 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x20); 1987 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60); 1988 } else { 1989 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 304); 1990 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 152); 1991 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 380); 1992 } 1993 } else { 1994 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0); 1995 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x10); 1996 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60); 1997 } 1998 #endif 1999 2000 /* Step 36: Configure DMA resource watermarks */ 2001 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5); 2002 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10); 2003 2004 /* Step 38: Enable buffer manager */ 2005 CSR_WRITE_4(sc, BGE_BMAN_MODE, 2006 BGE_BMANMODE_ENABLE | BGE_BMANMODE_LOMBUF_ATTN); 2007 2008 /* Step 39: Poll for buffer manager start indication */ 2009 for (i = 0; i < BGE_TIMEOUT * 2; i++) { 2010 if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE) 2011 break; 2012 DELAY(10); 2013 } 2014 2015 if (i == BGE_TIMEOUT * 2) { 2016 aprint_error_dev(sc->bge_dev, 2017 "buffer manager failed to start\n"); 2018 return ENXIO; 2019 } 2020 2021 /* Step 40: Enable flow-through queues */ 2022 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 2023 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 2024 2025 /* Wait until queue initialization is complete */ 2026 for (i = 0; i < BGE_TIMEOUT * 2; i++) { 2027 if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0) 2028 break; 2029 DELAY(10); 2030 } 2031 2032 if (i == BGE_TIMEOUT * 2) { 2033 aprint_error_dev(sc->bge_dev, 2034 "flow-through queue init failed\n"); 2035 return ENXIO; 2036 } 2037 2038 /* Step 41: Initialize the standard RX ring control block */ 2039 rcb = &sc->bge_rdata->bge_info.bge_std_rx_rcb; 2040 BGE_HOSTADDR(rcb->bge_hostaddr, BGE_RING_DMA_ADDR(sc, bge_rx_std_ring)); 2041 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5717 || 2042 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57765 || 2043 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57766) 2044 rcb->bge_maxlen_flags = 2045 BGE_RCB_MAXLEN_FLAGS(512, BGE_MAX_FRAMELEN << 2); 2046 else if (BGE_IS_5705_PLUS(sc)) 2047 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(512, 0); 2048 else 2049 rcb->bge_maxlen_flags = 2050 BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 0); 2051 rcb->bge_nicaddr = BGE_STD_RX_RINGS; 2052 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcb->bge_hostaddr.bge_addr_hi); 2053 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcb->bge_hostaddr.bge_addr_lo); 2054 CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 2055 CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcb->bge_nicaddr); 2056 2057 /* 2058 * Step 42: Initialize the jumbo RX ring control block 2059 * We set the 'ring disabled' bit in the flags 2060 * field until we're actually ready to start 2061 * using this ring (i.e. once we set the MTU 2062 * high enough to require it). 2063 */ 2064 if (BGE_IS_JUMBO_CAPABLE(sc)) { 2065 rcb = &sc->bge_rdata->bge_info.bge_jumbo_rx_rcb; 2066 BGE_HOSTADDR(rcb->bge_hostaddr, 2067 BGE_RING_DMA_ADDR(sc, bge_rx_jumbo_ring)); 2068 rcb->bge_maxlen_flags = 2069 BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 2070 BGE_RCB_FLAG_RING_DISABLED); 2071 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS; 2072 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI, 2073 rcb->bge_hostaddr.bge_addr_hi); 2074 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO, 2075 rcb->bge_hostaddr.bge_addr_lo); 2076 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, 2077 rcb->bge_maxlen_flags); 2078 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcb->bge_nicaddr); 2079 2080 /* Set up dummy disabled mini ring RCB */ 2081 rcb = &sc->bge_rdata->bge_info.bge_mini_rx_rcb; 2082 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0, 2083 BGE_RCB_FLAG_RING_DISABLED); 2084 CSR_WRITE_4(sc, BGE_RX_MINI_RCB_MAXLEN_FLAGS, 2085 rcb->bge_maxlen_flags); 2086 2087 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 2088 offsetof(struct bge_ring_data, bge_info), 2089 sizeof (struct bge_gib), 2090 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2091 } 2092 2093 /* Choose de-pipeline mode for BCM5906 A0, A1 and A2. */ 2094 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 2095 if (sc->bge_chipid == BGE_CHIPID_BCM5906_A0 || 2096 sc->bge_chipid == BGE_CHIPID_BCM5906_A1 || 2097 sc->bge_chipid == BGE_CHIPID_BCM5906_A2) 2098 CSR_WRITE_4(sc, BGE_ISO_PKT_TX, 2099 (CSR_READ_4(sc, BGE_ISO_PKT_TX) & ~3) | 2); 2100 } 2101 /* 2102 * Set the BD ring replenish thresholds. The recommended 2103 * values are 1/8th the number of descriptors allocated to 2104 * each ring. 2105 */ 2106 i = BGE_STD_RX_RING_CNT / 8; 2107 2108 /* 2109 * Use a value of 8 for the following chips to workaround HW errata. 2110 * Some of these chips have been added based on empirical 2111 * evidence (they don't work unless this is done). 2112 */ 2113 if (BGE_IS_5705_PLUS(sc)) 2114 i = 8; 2115 2116 CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, i); 2117 CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH, BGE_JUMBO_RX_RING_CNT / 8); 2118 2119 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5717 || 2120 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57765 || 2121 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57766) { 2122 CSR_WRITE_4(sc, BGE_STD_REPL_LWM, 4); 2123 CSR_WRITE_4(sc, BGE_JUMBO_REPL_LWM, 4); 2124 } 2125 2126 /* 2127 * Disable all unused send rings by setting the 'ring disabled' 2128 * bit in the flags field of all the TX send ring control blocks. 2129 * These are located in NIC memory. 2130 */ 2131 rcb_addr = BGE_MEMWIN_START + BGE_SEND_RING_RCB; 2132 for (i = 0; i < BGE_TX_RINGS_EXTSSRAM_MAX; i++) { 2133 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 2134 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED)); 2135 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 0); 2136 rcb_addr += sizeof(struct bge_rcb); 2137 } 2138 2139 /* Configure TX RCB 0 (we use only the first ring) */ 2140 rcb_addr = BGE_MEMWIN_START + BGE_SEND_RING_RCB; 2141 BGE_HOSTADDR(taddr, BGE_RING_DMA_ADDR(sc, bge_tx_ring)); 2142 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi); 2143 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo); 2144 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 2145 BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT)); 2146 if (BGE_IS_5700_FAMILY(sc)) 2147 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 2148 BGE_RCB_MAXLEN_FLAGS(BGE_TX_RING_CNT, 0)); 2149 2150 /* Disable all unused RX return rings */ 2151 rcb_addr = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB; 2152 for (i = 0; i < BGE_RX_RINGS_MAX; i++) { 2153 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_hi, 0); 2154 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_lo, 0); 2155 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 2156 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 2157 BGE_RCB_FLAG_RING_DISABLED)); 2158 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 0); 2159 bge_writembx(sc, BGE_MBX_RX_CONS0_LO + 2160 (i * (sizeof(uint64_t))), 0); 2161 rcb_addr += sizeof(struct bge_rcb); 2162 } 2163 2164 /* Initialize RX ring indexes */ 2165 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, 0); 2166 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0); 2167 bge_writembx(sc, BGE_MBX_RX_MINI_PROD_LO, 0); 2168 2169 /* 2170 * Set up RX return ring 0 2171 * Note that the NIC address for RX return rings is 0x00000000. 2172 * The return rings live entirely within the host, so the 2173 * nicaddr field in the RCB isn't used. 2174 */ 2175 rcb_addr = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB; 2176 BGE_HOSTADDR(taddr, BGE_RING_DMA_ADDR(sc, bge_rx_return_ring)); 2177 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi); 2178 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo); 2179 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 0x00000000); 2180 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 2181 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 0)); 2182 2183 /* Set random backoff seed for TX */ 2184 CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF, 2185 CLLADDR(ifp->if_sadl)[0] + CLLADDR(ifp->if_sadl)[1] + 2186 CLLADDR(ifp->if_sadl)[2] + CLLADDR(ifp->if_sadl)[3] + 2187 CLLADDR(ifp->if_sadl)[4] + CLLADDR(ifp->if_sadl)[5] + 2188 BGE_TX_BACKOFF_SEED_MASK); 2189 2190 /* Set inter-packet gap */ 2191 CSR_WRITE_4(sc, BGE_TX_LENGTHS, 0x2620); 2192 2193 /* 2194 * Specify which ring to use for packets that don't match 2195 * any RX rules. 2196 */ 2197 CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08); 2198 2199 /* 2200 * Configure number of RX lists. One interrupt distribution 2201 * list, sixteen active lists, one bad frames class. 2202 */ 2203 CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181); 2204 2205 /* Inialize RX list placement stats mask. */ 2206 CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF); 2207 CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1); 2208 2209 /* Disable host coalescing until we get it set up */ 2210 CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000); 2211 2212 /* Poll to make sure it's shut down. */ 2213 for (i = 0; i < BGE_TIMEOUT * 2; i++) { 2214 if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE)) 2215 break; 2216 DELAY(10); 2217 } 2218 2219 if (i == BGE_TIMEOUT * 2) { 2220 aprint_error_dev(sc->bge_dev, 2221 "host coalescing engine failed to idle\n"); 2222 return ENXIO; 2223 } 2224 2225 /* Set up host coalescing defaults */ 2226 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bge_rx_coal_ticks); 2227 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bge_tx_coal_ticks); 2228 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bge_rx_max_coal_bds); 2229 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bge_tx_max_coal_bds); 2230 if (BGE_IS_5700_FAMILY(sc)) { 2231 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT, 0); 2232 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT, 0); 2233 } 2234 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 0); 2235 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 0); 2236 2237 /* Set up address of statistics block */ 2238 if (BGE_IS_5700_FAMILY(sc)) { 2239 BGE_HOSTADDR(taddr, BGE_RING_DMA_ADDR(sc, bge_info.bge_stats)); 2240 CSR_WRITE_4(sc, BGE_HCC_STATS_TICKS, sc->bge_stat_ticks); 2241 CSR_WRITE_4(sc, BGE_HCC_STATS_BASEADDR, BGE_STATS_BLOCK); 2242 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_HI, taddr.bge_addr_hi); 2243 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_LO, taddr.bge_addr_lo); 2244 } 2245 2246 /* Set up address of status block */ 2247 BGE_HOSTADDR(taddr, BGE_RING_DMA_ADDR(sc, bge_status_block)); 2248 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_BASEADDR, BGE_STATUS_BLOCK); 2249 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI, taddr.bge_addr_hi); 2250 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO, taddr.bge_addr_lo); 2251 sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx = 0; 2252 sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx = 0; 2253 2254 /* Turn on host coalescing state machine */ 2255 CSR_WRITE_4(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE); 2256 2257 /* Turn on RX BD completion state machine and enable attentions */ 2258 CSR_WRITE_4(sc, BGE_RBDC_MODE, 2259 BGE_RBDCMODE_ENABLE | BGE_RBDCMODE_ATTN); 2260 2261 /* Turn on RX list placement state machine */ 2262 CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 2263 2264 /* Turn on RX list selector state machine. */ 2265 if (BGE_IS_5700_FAMILY(sc)) 2266 CSR_WRITE_4(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 2267 2268 val = BGE_MACMODE_TXDMA_ENB | BGE_MACMODE_RXDMA_ENB | 2269 BGE_MACMODE_RX_STATS_CLEAR | BGE_MACMODE_TX_STATS_CLEAR | 2270 BGE_MACMODE_RX_STATS_ENB | BGE_MACMODE_TX_STATS_ENB | 2271 BGE_MACMODE_FRMHDR_DMA_ENB; 2272 2273 if (sc->bge_flags & BGE_PHY_FIBER_TBI) 2274 val |= BGE_PORTMODE_TBI; 2275 else if (sc->bge_flags & BGE_PHY_FIBER_MII) 2276 val |= BGE_PORTMODE_GMII; 2277 else 2278 val |= BGE_PORTMODE_MII; 2279 2280 /* Turn on DMA, clear stats */ 2281 CSR_WRITE_4(sc, BGE_MAC_MODE, val); 2282 2283 /* Set misc. local control, enable interrupts on attentions */ 2284 sc->bge_local_ctrl_reg = BGE_MLC_INTR_ONATTN | BGE_MLC_AUTO_EEPROM; 2285 2286 #ifdef notdef 2287 /* Assert GPIO pins for PHY reset */ 2288 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUT0| 2289 BGE_MLC_MISCIO_OUT1|BGE_MLC_MISCIO_OUT2); 2290 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUTEN0| 2291 BGE_MLC_MISCIO_OUTEN1|BGE_MLC_MISCIO_OUTEN2); 2292 #endif 2293 2294 #if defined(not_quite_yet) 2295 /* Linux driver enables enable gpio pin #1 on 5700s */ 2296 if (sc->bge_chipid == BGE_CHIPID_BCM5700) { 2297 sc->bge_local_ctrl_reg |= 2298 (BGE_MLC_MISCIO_OUT1|BGE_MLC_MISCIO_OUTEN1); 2299 } 2300 #endif 2301 CSR_WRITE_4(sc, BGE_MISC_LOCAL_CTL, sc->bge_local_ctrl_reg); 2302 2303 /* Turn on DMA completion state machine */ 2304 if (BGE_IS_5700_FAMILY(sc)) 2305 CSR_WRITE_4(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 2306 2307 val = BGE_WDMAMODE_ENABLE | BGE_WDMAMODE_ALL_ATTNS; 2308 2309 /* Enable host coalescing bug fix; see Linux tg3.c */ 2310 if (BGE_IS_5755_PLUS(sc)) 2311 val |= BGE_WDMAMODE_STATUS_TAG_FIX; 2312 2313 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785) 2314 val |= BGE_WDMAMODE_BURST_ALL_DATA; 2315 2316 /* Turn on write DMA state machine */ 2317 CSR_WRITE_4(sc, BGE_WDMA_MODE, val); 2318 2319 val = BGE_RDMAMODE_ENABLE | BGE_RDMAMODE_ALL_ATTNS; 2320 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5784 || 2321 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785 || 2322 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57780) 2323 val |= BGE_RDMAMODE_BD_SBD_CRPT_ATTN | 2324 BGE_RDMAMODE_MBUF_RBD_CRPT_ATTN | 2325 BGE_RDMAMODE_MBUF_SBD_CRPT_ATTN; 2326 2327 if (sc->bge_flags & BGE_PCIE) 2328 val |= BGE_RDMAMODE_FIFO_LONG_BURST; 2329 if (sc->bge_flags & BGE_TSO) 2330 val |= BGE_RDMAMODE_TSO4_ENABLE; 2331 2332 /* Turn on read DMA state machine */ 2333 CSR_WRITE_4(sc, BGE_RDMA_MODE, val); 2334 delay(40); 2335 2336 /* Turn on RX data completion state machine */ 2337 CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 2338 2339 /* Turn on RX BD initiator state machine */ 2340 CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 2341 2342 /* Turn on RX data and RX BD initiator state machine */ 2343 CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE); 2344 2345 /* Turn on Mbuf cluster free state machine */ 2346 if (BGE_IS_5700_FAMILY(sc)) 2347 CSR_WRITE_4(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 2348 2349 /* Turn on send BD completion state machine */ 2350 CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 2351 2352 /* Turn on send data completion state machine */ 2353 val = BGE_SDCMODE_ENABLE; 2354 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761) 2355 val |= BGE_SDCMODE_CDELAY; 2356 CSR_WRITE_4(sc, BGE_SDC_MODE, val); 2357 2358 /* Turn on send data initiator state machine */ 2359 if (sc->bge_flags & BGE_TSO) { 2360 /* XXX: magic value from Linux driver */ 2361 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE | 0x08); 2362 } else 2363 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 2364 2365 /* Turn on send BD initiator state machine */ 2366 CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 2367 2368 /* Turn on send BD selector state machine */ 2369 CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 2370 2371 CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF); 2372 CSR_WRITE_4(sc, BGE_SDI_STATS_CTL, 2373 BGE_SDISTATSCTL_ENABLE | BGE_SDISTATSCTL_FASTER); 2374 2375 /* ack/clear link change events */ 2376 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED | 2377 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE | 2378 BGE_MACSTAT_LINK_CHANGED); 2379 CSR_WRITE_4(sc, BGE_MI_STS, 0); 2380 2381 /* Enable PHY auto polling (for MII/GMII only) */ 2382 if (sc->bge_flags & BGE_PHY_FIBER_TBI) { 2383 CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK); 2384 } else { 2385 BGE_STS_SETBIT(sc, BGE_STS_AUTOPOLL); 2386 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL | (10 << 16)); 2387 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700) 2388 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, 2389 BGE_EVTENB_MI_INTERRUPT); 2390 } 2391 2392 /* 2393 * Clear any pending link state attention. 2394 * Otherwise some link state change events may be lost until attention 2395 * is cleared by bge_intr() -> bge_link_upd() sequence. 2396 * It's not necessary on newer BCM chips - perhaps enabling link 2397 * state change attentions implies clearing pending attention. 2398 */ 2399 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED | 2400 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE | 2401 BGE_MACSTAT_LINK_CHANGED); 2402 2403 /* Enable link state change attentions. */ 2404 BGE_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED); 2405 2406 return 0; 2407 } 2408 2409 static const struct bge_revision * 2410 bge_lookup_rev(uint32_t chipid) 2411 { 2412 const struct bge_revision *br; 2413 2414 for (br = bge_revisions; br->br_name != NULL; br++) { 2415 if (br->br_chipid == chipid) 2416 return br; 2417 } 2418 2419 for (br = bge_majorrevs; br->br_name != NULL; br++) { 2420 if (br->br_chipid == BGE_ASICREV(chipid)) 2421 return br; 2422 } 2423 2424 return NULL; 2425 } 2426 2427 static const struct bge_product * 2428 bge_lookup(const struct pci_attach_args *pa) 2429 { 2430 const struct bge_product *bp; 2431 2432 for (bp = bge_products; bp->bp_name != NULL; bp++) { 2433 if (PCI_VENDOR(pa->pa_id) == bp->bp_vendor && 2434 PCI_PRODUCT(pa->pa_id) == bp->bp_product) 2435 return bp; 2436 } 2437 2438 return NULL; 2439 } 2440 2441 static int 2442 bge_setpowerstate(struct bge_softc *sc, int powerlevel) 2443 { 2444 #ifdef NOTYET 2445 uint32_t pm_ctl = 0; 2446 2447 /* XXX FIXME: make sure indirect accesses enabled? */ 2448 pm_ctl = pci_conf_read(sc->bge_dev, BGE_PCI_MISC_CTL, 4); 2449 pm_ctl |= BGE_PCIMISCCTL_INDIRECT_ACCESS; 2450 pci_write_config(sc->bge_dev, BGE_PCI_MISC_CTL, pm_ctl, 4); 2451 2452 /* clear the PME_assert bit and power state bits, enable PME */ 2453 pm_ctl = pci_conf_read(sc->bge_dev, BGE_PCI_PWRMGMT_CMD, 2); 2454 pm_ctl &= ~PCIM_PSTAT_DMASK; 2455 pm_ctl |= (1 << 8); 2456 2457 if (powerlevel == 0) { 2458 pm_ctl |= PCIM_PSTAT_D0; 2459 pci_write_config(sc->bge_dev, BGE_PCI_PWRMGMT_CMD, 2460 pm_ctl, 2); 2461 DELAY(10000); 2462 CSR_WRITE_4(sc, BGE_MISC_LOCAL_CTL, sc->bge_local_ctrl_reg); 2463 DELAY(10000); 2464 2465 #ifdef NOTYET 2466 /* XXX FIXME: write 0x02 to phy aux_Ctrl reg */ 2467 bge_miibus_writereg(sc->bge_dev, 1, 0x18, 0x02); 2468 #endif 2469 DELAY(40); DELAY(40); DELAY(40); 2470 DELAY(10000); /* above not quite adequate on 5700 */ 2471 return 0; 2472 } 2473 2474 2475 /* 2476 * Entering ACPI power states D1-D3 is achieved by wiggling 2477 * GMII gpio pins. Example code assumes all hardware vendors 2478 * followed Broadcom's sample pcb layout. Until we verify that 2479 * for all supported OEM cards, states D1-D3 are unsupported. 2480 */ 2481 aprint_error_dev(sc->bge_dev, 2482 "power state %d unimplemented; check GPIO pins\n", 2483 powerlevel); 2484 #endif 2485 return EOPNOTSUPP; 2486 } 2487 2488 2489 /* 2490 * Probe for a Broadcom chip. Check the PCI vendor and device IDs 2491 * against our list and return its name if we find a match. Note 2492 * that since the Broadcom controller contains VPD support, we 2493 * can get the device name string from the controller itself instead 2494 * of the compiled-in string. This is a little slow, but it guarantees 2495 * we'll always announce the right product name. 2496 */ 2497 static int 2498 bge_probe(device_t parent, cfdata_t match, void *aux) 2499 { 2500 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 2501 2502 if (bge_lookup(pa) != NULL) 2503 return 1; 2504 2505 return 0; 2506 } 2507 2508 static void 2509 bge_attach(device_t parent, device_t self, void *aux) 2510 { 2511 struct bge_softc *sc = device_private(self); 2512 struct pci_attach_args *pa = aux; 2513 prop_dictionary_t dict; 2514 const struct bge_product *bp; 2515 const struct bge_revision *br; 2516 pci_chipset_tag_t pc; 2517 pci_intr_handle_t ih; 2518 const char *intrstr = NULL; 2519 bus_dma_segment_t seg; 2520 int rseg; 2521 uint32_t hwcfg = 0; 2522 uint32_t command; 2523 struct ifnet *ifp; 2524 uint32_t misccfg; 2525 void * kva; 2526 u_char eaddr[ETHER_ADDR_LEN]; 2527 pcireg_t memtype, subid; 2528 bus_addr_t memaddr; 2529 bus_size_t memsize; 2530 uint32_t pm_ctl; 2531 bool no_seeprom; 2532 2533 bp = bge_lookup(pa); 2534 KASSERT(bp != NULL); 2535 2536 sc->sc_pc = pa->pa_pc; 2537 sc->sc_pcitag = pa->pa_tag; 2538 sc->bge_dev = self; 2539 2540 pc = sc->sc_pc; 2541 subid = pci_conf_read(pc, sc->sc_pcitag, PCI_SUBSYS_ID_REG); 2542 2543 aprint_naive(": Ethernet controller\n"); 2544 aprint_normal(": %s\n", bp->bp_name); 2545 2546 /* 2547 * Map control/status registers. 2548 */ 2549 DPRINTFN(5, ("Map control/status regs\n")); 2550 command = pci_conf_read(pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG); 2551 command |= PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_MASTER_ENABLE; 2552 pci_conf_write(pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG, command); 2553 command = pci_conf_read(pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG); 2554 2555 if (!(command & PCI_COMMAND_MEM_ENABLE)) { 2556 aprint_error_dev(sc->bge_dev, 2557 "failed to enable memory mapping!\n"); 2558 return; 2559 } 2560 2561 DPRINTFN(5, ("pci_mem_find\n")); 2562 memtype = pci_mapreg_type(sc->sc_pc, sc->sc_pcitag, BGE_PCI_BAR0); 2563 switch (memtype) { 2564 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 2565 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 2566 if (pci_mapreg_map(pa, BGE_PCI_BAR0, 2567 memtype, 0, &sc->bge_btag, &sc->bge_bhandle, 2568 &memaddr, &memsize) == 0) 2569 break; 2570 default: 2571 aprint_error_dev(sc->bge_dev, "can't find mem space\n"); 2572 return; 2573 } 2574 2575 DPRINTFN(5, ("pci_intr_map\n")); 2576 if (pci_intr_map(pa, &ih)) { 2577 aprint_error_dev(sc->bge_dev, "couldn't map interrupt\n"); 2578 return; 2579 } 2580 2581 DPRINTFN(5, ("pci_intr_string\n")); 2582 intrstr = pci_intr_string(pc, ih); 2583 2584 DPRINTFN(5, ("pci_intr_establish\n")); 2585 sc->bge_intrhand = pci_intr_establish(pc, ih, IPL_NET, bge_intr, sc); 2586 2587 if (sc->bge_intrhand == NULL) { 2588 aprint_error_dev(sc->bge_dev, 2589 "couldn't establish interrupt%s%s\n", 2590 intrstr ? " at " : "", intrstr ? intrstr : ""); 2591 return; 2592 } 2593 aprint_normal_dev(sc->bge_dev, "interrupting at %s\n", intrstr); 2594 2595 /* 2596 * Kludge for 5700 Bx bug: a hardware bug (PCIX byte enable?) 2597 * can clobber the chip's PCI config-space power control registers, 2598 * leaving the card in D3 powersave state. 2599 * We do not have memory-mapped registers in this state, 2600 * so force device into D0 state before starting initialization. 2601 */ 2602 pm_ctl = pci_conf_read(pc, sc->sc_pcitag, BGE_PCI_PWRMGMT_CMD); 2603 pm_ctl &= ~(PCI_PWR_D0|PCI_PWR_D1|PCI_PWR_D2|PCI_PWR_D3); 2604 pm_ctl |= (1 << 8) | PCI_PWR_D0 ; /* D0 state */ 2605 pci_conf_write(pc, sc->sc_pcitag, BGE_PCI_PWRMGMT_CMD, pm_ctl); 2606 DELAY(1000); /* 27 usec is allegedly sufficent */ 2607 2608 /* 2609 * Save ASIC rev. 2610 */ 2611 sc->bge_chipid = 2612 pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_MISC_CTL) 2613 >> BGE_PCIMISCCTL_ASICREV_SHIFT; 2614 2615 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_USE_PRODID_REG) { 2616 switch (PCI_PRODUCT(pa->pa_id)) { 2617 case PCI_PRODUCT_BROADCOM_BCM5717: 2618 case PCI_PRODUCT_BROADCOM_BCM5718: 2619 case PCI_PRODUCT_BROADCOM_BCM5724: /* ??? */ 2620 sc->bge_chipid = pci_conf_read(pc, pa->pa_tag, 2621 BGE_PCI_GEN2_PRODID_ASICREV); 2622 break; 2623 case PCI_PRODUCT_BROADCOM_BCM57761: 2624 case PCI_PRODUCT_BROADCOM_BCM57762: 2625 case PCI_PRODUCT_BROADCOM_BCM57765: 2626 case PCI_PRODUCT_BROADCOM_BCM57781: 2627 case PCI_PRODUCT_BROADCOM_BCM57785: 2628 case PCI_PRODUCT_BROADCOM_BCM57791: 2629 case PCI_PRODUCT_BROADCOM_BCM57795: 2630 sc->bge_chipid = pci_conf_read(pc, pa->pa_tag, 2631 BGE_PCI_GEN15_PRODID_ASICREV); 2632 break; 2633 default: 2634 sc->bge_chipid = pci_conf_read(pc, pa->pa_tag, 2635 BGE_PCI_PRODID_ASICREV); 2636 break; 2637 } 2638 } 2639 2640 if ((pci_get_capability(sc->sc_pc, sc->sc_pcitag, PCI_CAP_PCIEXPRESS, 2641 &sc->bge_pciecap, NULL) != 0) 2642 || (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785)) { 2643 /* PCIe */ 2644 sc->bge_flags |= BGE_PCIE; 2645 bge_set_max_readrq(sc); 2646 } else if ((pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_PCISTATE) & 2647 BGE_PCISTATE_PCI_BUSMODE) == 0) { 2648 /* PCI-X */ 2649 sc->bge_flags |= BGE_PCIX; 2650 if (pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_PCIX, 2651 &sc->bge_pcixcap, NULL) == 0) 2652 aprint_error_dev(sc->bge_dev, 2653 "unable to find PCIX capability\n"); 2654 } 2655 2656 /* chipid */ 2657 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 2658 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5701 || 2659 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5703 || 2660 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) 2661 sc->bge_flags |= BGE_5700_FAMILY; 2662 2663 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5714_A0 || 2664 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5780 || 2665 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5714) 2666 sc->bge_flags |= BGE_5714_FAMILY; 2667 2668 /* Intentionally exclude BGE_ASICREV_BCM5906 */ 2669 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5717 || 2670 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5755 || 2671 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761 || 2672 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5784 || 2673 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785 || 2674 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5787 || 2675 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57765 || 2676 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57766 || 2677 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57780) 2678 sc->bge_flags |= BGE_5755_PLUS; 2679 2680 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5750 || 2681 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5752 || 2682 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906 || 2683 BGE_IS_5755_PLUS(sc) || 2684 BGE_IS_5714_FAMILY(sc)) 2685 sc->bge_flags |= BGE_575X_PLUS; 2686 2687 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5705 || 2688 BGE_IS_575X_PLUS(sc)) 2689 sc->bge_flags |= BGE_5705_PLUS; 2690 2691 /* 2692 * When using the BCM5701 in PCI-X mode, data corruption has 2693 * been observed in the first few bytes of some received packets. 2694 * Aligning the packet buffer in memory eliminates the corruption. 2695 * Unfortunately, this misaligns the packet payloads. On platforms 2696 * which do not support unaligned accesses, we will realign the 2697 * payloads by copying the received packets. 2698 */ 2699 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5701 && 2700 sc->bge_flags & BGE_PCIX) 2701 sc->bge_flags |= BGE_RX_ALIGNBUG; 2702 2703 if (BGE_IS_5700_FAMILY(sc)) 2704 sc->bge_flags |= BGE_JUMBO_CAPABLE; 2705 2706 if ((BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 2707 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5701) && 2708 PCI_VENDOR(subid) == PCI_VENDOR_DELL) 2709 sc->bge_flags |= BGE_NO_3LED; 2710 2711 misccfg = CSR_READ_4(sc, BGE_MISC_CFG); 2712 misccfg &= BGE_MISCCFG_BOARD_ID_MASK; 2713 2714 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5705 && 2715 (misccfg == BGE_MISCCFG_BOARD_ID_5788 || 2716 misccfg == BGE_MISCCFG_BOARD_ID_5788M)) 2717 sc->bge_flags |= BGE_IS_5788; 2718 2719 /* 2720 * Some controllers seem to require a special firmware to use 2721 * TSO. But the firmware is not available to FreeBSD and Linux 2722 * claims that the TSO performed by the firmware is slower than 2723 * hardware based TSO. Moreover the firmware based TSO has one 2724 * known bug which can't handle TSO if ethernet header + IP/TCP 2725 * header is greater than 80 bytes. The workaround for the TSO 2726 * bug exist but it seems it's too expensive than not using 2727 * TSO at all. Some hardwares also have the TSO bug so limit 2728 * the TSO to the controllers that are not affected TSO issues 2729 * (e.g. 5755 or higher). 2730 */ 2731 if (BGE_IS_5755_PLUS(sc)) { 2732 /* 2733 * BCM5754 and BCM5787 shares the same ASIC id so 2734 * explicit device id check is required. 2735 */ 2736 if ((PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_BROADCOM_BCM5754) && 2737 (PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_BROADCOM_BCM5754M)) 2738 sc->bge_flags |= BGE_TSO; 2739 } 2740 2741 if ((BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5703 && 2742 (misccfg == 0x4000 || misccfg == 0x8000)) || 2743 (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5705 && 2744 PCI_VENDOR(pa->pa_id) == PCI_VENDOR_BROADCOM && 2745 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5901 || 2746 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5901A2 || 2747 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5705F)) || 2748 (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_BROADCOM && 2749 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5751F || 2750 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5753F || 2751 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5787F)) || 2752 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM57790 || 2753 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 2754 sc->bge_flags |= BGE_10_100_ONLY; 2755 2756 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 2757 (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5705 && 2758 (sc->bge_chipid != BGE_CHIPID_BCM5705_A0 && 2759 sc->bge_chipid != BGE_CHIPID_BCM5705_A1)) || 2760 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 2761 sc->bge_flags |= BGE_NO_ETH_WIRE_SPEED; 2762 2763 if (sc->bge_chipid == BGE_CHIPID_BCM5701_A0 || 2764 sc->bge_chipid == BGE_CHIPID_BCM5701_B0) 2765 sc->bge_flags |= BGE_PHY_CRC_BUG; 2766 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5703_AX || 2767 BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5704_AX) 2768 sc->bge_flags |= BGE_PHY_ADC_BUG; 2769 if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0) 2770 sc->bge_flags |= BGE_PHY_5704_A0_BUG; 2771 2772 if (BGE_IS_5705_PLUS(sc) && 2773 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5906 && 2774 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5717 && 2775 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5785 && 2776 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM57765 && 2777 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM57766 && 2778 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM57780) { 2779 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5755 || 2780 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761 || 2781 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5784 || 2782 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5787) { 2783 if (PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_BROADCOM_BCM5722 && 2784 PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_BROADCOM_BCM5756) 2785 sc->bge_flags |= BGE_PHY_JITTER_BUG; 2786 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5755M) 2787 sc->bge_flags |= BGE_PHY_ADJUST_TRIM; 2788 } else if (BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5906) 2789 sc->bge_flags |= BGE_PHY_BER_BUG; 2790 } 2791 2792 /* 2793 * SEEPROM check. 2794 * First check if firmware knows we do not have SEEPROM. 2795 */ 2796 if (prop_dictionary_get_bool(device_properties(self), 2797 "without-seeprom", &no_seeprom) && no_seeprom) 2798 sc->bge_flags |= BGE_NO_EEPROM; 2799 2800 /* Now check the 'ROM failed' bit on the RX CPU */ 2801 else if (CSR_READ_4(sc, BGE_RXCPU_MODE) & BGE_RXCPUMODE_ROMFAIL) 2802 sc->bge_flags |= BGE_NO_EEPROM; 2803 2804 /* Try to reset the chip. */ 2805 DPRINTFN(5, ("bge_reset\n")); 2806 bge_reset(sc); 2807 2808 sc->bge_asf_mode = 0; 2809 if (bge_allow_asf && (bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_SIG) 2810 == BGE_MAGIC_NUMBER)) { 2811 if (bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_NICCFG) 2812 & BGE_HWCFG_ASF) { 2813 sc->bge_asf_mode |= ASF_ENABLE; 2814 sc->bge_asf_mode |= ASF_STACKUP; 2815 if (BGE_IS_575X_PLUS(sc)) { 2816 sc->bge_asf_mode |= ASF_NEW_HANDSHAKE; 2817 } 2818 } 2819 } 2820 2821 /* Try to reset the chip again the nice way. */ 2822 bge_stop_fw(sc); 2823 bge_sig_pre_reset(sc, BGE_RESET_STOP); 2824 if (bge_reset(sc)) 2825 aprint_error_dev(sc->bge_dev, "chip reset failed\n"); 2826 2827 bge_sig_legacy(sc, BGE_RESET_STOP); 2828 bge_sig_post_reset(sc, BGE_RESET_STOP); 2829 2830 if (bge_chipinit(sc)) { 2831 aprint_error_dev(sc->bge_dev, "chip initialization failed\n"); 2832 bge_release_resources(sc); 2833 return; 2834 } 2835 2836 /* 2837 * Get station address from the EEPROM. 2838 */ 2839 if (bge_get_eaddr(sc, eaddr)) { 2840 aprint_error_dev(sc->bge_dev, 2841 "failed to read station address\n"); 2842 bge_release_resources(sc); 2843 return; 2844 } 2845 2846 br = bge_lookup_rev(sc->bge_chipid); 2847 2848 if (br == NULL) { 2849 aprint_normal_dev(sc->bge_dev, "unknown ASIC (0x%x)", 2850 sc->bge_chipid); 2851 } else { 2852 aprint_normal_dev(sc->bge_dev, "ASIC %s (0x%x)", 2853 br->br_name, sc->bge_chipid); 2854 } 2855 aprint_normal(", Ethernet address %s\n", ether_sprintf(eaddr)); 2856 2857 /* Allocate the general information block and ring buffers. */ 2858 if (pci_dma64_available(pa)) 2859 sc->bge_dmatag = pa->pa_dmat64; 2860 else 2861 sc->bge_dmatag = pa->pa_dmat; 2862 DPRINTFN(5, ("bus_dmamem_alloc\n")); 2863 if (bus_dmamem_alloc(sc->bge_dmatag, sizeof(struct bge_ring_data), 2864 PAGE_SIZE, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 2865 aprint_error_dev(sc->bge_dev, "can't alloc rx buffers\n"); 2866 return; 2867 } 2868 DPRINTFN(5, ("bus_dmamem_map\n")); 2869 if (bus_dmamem_map(sc->bge_dmatag, &seg, rseg, 2870 sizeof(struct bge_ring_data), &kva, 2871 BUS_DMA_NOWAIT)) { 2872 aprint_error_dev(sc->bge_dev, 2873 "can't map DMA buffers (%zu bytes)\n", 2874 sizeof(struct bge_ring_data)); 2875 bus_dmamem_free(sc->bge_dmatag, &seg, rseg); 2876 return; 2877 } 2878 DPRINTFN(5, ("bus_dmamem_create\n")); 2879 if (bus_dmamap_create(sc->bge_dmatag, sizeof(struct bge_ring_data), 1, 2880 sizeof(struct bge_ring_data), 0, 2881 BUS_DMA_NOWAIT, &sc->bge_ring_map)) { 2882 aprint_error_dev(sc->bge_dev, "can't create DMA map\n"); 2883 bus_dmamem_unmap(sc->bge_dmatag, kva, 2884 sizeof(struct bge_ring_data)); 2885 bus_dmamem_free(sc->bge_dmatag, &seg, rseg); 2886 return; 2887 } 2888 DPRINTFN(5, ("bus_dmamem_load\n")); 2889 if (bus_dmamap_load(sc->bge_dmatag, sc->bge_ring_map, kva, 2890 sizeof(struct bge_ring_data), NULL, 2891 BUS_DMA_NOWAIT)) { 2892 bus_dmamap_destroy(sc->bge_dmatag, sc->bge_ring_map); 2893 bus_dmamem_unmap(sc->bge_dmatag, kva, 2894 sizeof(struct bge_ring_data)); 2895 bus_dmamem_free(sc->bge_dmatag, &seg, rseg); 2896 return; 2897 } 2898 2899 DPRINTFN(5, ("bzero\n")); 2900 sc->bge_rdata = (struct bge_ring_data *)kva; 2901 2902 memset(sc->bge_rdata, 0, sizeof(struct bge_ring_data)); 2903 2904 /* Try to allocate memory for jumbo buffers. */ 2905 if (BGE_IS_JUMBO_CAPABLE(sc)) { 2906 if (bge_alloc_jumbo_mem(sc)) { 2907 aprint_error_dev(sc->bge_dev, 2908 "jumbo buffer allocation failed\n"); 2909 } else 2910 sc->ethercom.ec_capabilities |= ETHERCAP_JUMBO_MTU; 2911 } 2912 2913 /* Set default tuneable values. */ 2914 sc->bge_stat_ticks = BGE_TICKS_PER_SEC; 2915 sc->bge_rx_coal_ticks = 150; 2916 sc->bge_rx_max_coal_bds = 64; 2917 #ifdef ORIG_WPAUL_VALUES 2918 sc->bge_tx_coal_ticks = 150; 2919 sc->bge_tx_max_coal_bds = 128; 2920 #else 2921 sc->bge_tx_coal_ticks = 300; 2922 sc->bge_tx_max_coal_bds = 400; 2923 #endif 2924 if (BGE_IS_5705_PLUS(sc)) { 2925 sc->bge_tx_coal_ticks = (12 * 5); 2926 sc->bge_tx_max_coal_bds = (12 * 5); 2927 aprint_verbose_dev(sc->bge_dev, 2928 "setting short Tx thresholds\n"); 2929 } 2930 2931 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5717 || 2932 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57765 || 2933 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57766) 2934 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT; 2935 else if (BGE_IS_5705_PLUS(sc)) 2936 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT_5705; 2937 else 2938 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT; 2939 2940 /* Set up ifnet structure */ 2941 ifp = &sc->ethercom.ec_if; 2942 ifp->if_softc = sc; 2943 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 2944 ifp->if_ioctl = bge_ioctl; 2945 ifp->if_stop = bge_stop; 2946 ifp->if_start = bge_start; 2947 ifp->if_init = bge_init; 2948 ifp->if_watchdog = bge_watchdog; 2949 IFQ_SET_MAXLEN(&ifp->if_snd, max(BGE_TX_RING_CNT - 1, IFQ_MAXLEN)); 2950 IFQ_SET_READY(&ifp->if_snd); 2951 DPRINTFN(5, ("strcpy if_xname\n")); 2952 strcpy(ifp->if_xname, device_xname(sc->bge_dev)); 2953 2954 if (sc->bge_chipid != BGE_CHIPID_BCM5700_B0) 2955 sc->ethercom.ec_if.if_capabilities |= 2956 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx; 2957 #if 1 /* XXX TCP/UDP checksum offload breaks with pf(4) */ 2958 sc->ethercom.ec_if.if_capabilities |= 2959 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 2960 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 2961 #endif 2962 sc->ethercom.ec_capabilities |= 2963 ETHERCAP_VLAN_HWTAGGING | ETHERCAP_VLAN_MTU; 2964 2965 if (sc->bge_flags & BGE_TSO) 2966 sc->ethercom.ec_if.if_capabilities |= IFCAP_TSOv4; 2967 2968 /* 2969 * Do MII setup. 2970 */ 2971 DPRINTFN(5, ("mii setup\n")); 2972 sc->bge_mii.mii_ifp = ifp; 2973 sc->bge_mii.mii_readreg = bge_miibus_readreg; 2974 sc->bge_mii.mii_writereg = bge_miibus_writereg; 2975 sc->bge_mii.mii_statchg = bge_miibus_statchg; 2976 2977 /* 2978 * Figure out what sort of media we have by checking the hardware 2979 * config word in the first 32k of NIC internal memory, or fall back to 2980 * the config word in the EEPROM. Note: on some BCM5700 cards, 2981 * this value appears to be unset. If that's the case, we have to rely 2982 * on identifying the NIC by its PCI subsystem ID, as we do below for 2983 * the SysKonnect SK-9D41. 2984 */ 2985 if (bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_SIG) == BGE_MAGIC_NUMBER) { 2986 hwcfg = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_NICCFG); 2987 } else if (!(sc->bge_flags & BGE_NO_EEPROM)) { 2988 bge_read_eeprom(sc, (void *)&hwcfg, 2989 BGE_EE_HWCFG_OFFSET, sizeof(hwcfg)); 2990 hwcfg = be32toh(hwcfg); 2991 } 2992 /* The SysKonnect SK-9D41 is a 1000baseSX card. */ 2993 if (PCI_PRODUCT(pa->pa_id) == SK_SUBSYSID_9D41 || 2994 (hwcfg & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER) { 2995 if (BGE_IS_5714_FAMILY(sc)) 2996 sc->bge_flags |= BGE_PHY_FIBER_MII; 2997 else 2998 sc->bge_flags |= BGE_PHY_FIBER_TBI; 2999 } 3000 3001 /* set phyflags and chipid before mii_attach() */ 3002 dict = device_properties(self); 3003 prop_dictionary_set_uint32(dict, "phyflags", sc->bge_flags); 3004 prop_dictionary_set_uint32(dict, "chipid", sc->bge_chipid); 3005 3006 if (sc->bge_flags & BGE_PHY_FIBER_TBI) { 3007 ifmedia_init(&sc->bge_ifmedia, IFM_IMASK, bge_ifmedia_upd, 3008 bge_ifmedia_sts); 3009 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER |IFM_1000_SX, 0, NULL); 3010 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_1000_SX|IFM_FDX, 3011 0, NULL); 3012 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_AUTO, 0, NULL); 3013 ifmedia_set(&sc->bge_ifmedia, IFM_ETHER | IFM_AUTO); 3014 /* Pretend the user requested this setting */ 3015 sc->bge_ifmedia.ifm_media = sc->bge_ifmedia.ifm_cur->ifm_media; 3016 } else { 3017 /* 3018 * Do transceiver setup and tell the firmware the 3019 * driver is down so we can try to get access the 3020 * probe if ASF is running. Retry a couple of times 3021 * if we get a conflict with the ASF firmware accessing 3022 * the PHY. 3023 */ 3024 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 3025 bge_asf_driver_up(sc); 3026 3027 ifmedia_init(&sc->bge_mii.mii_media, 0, bge_ifmedia_upd, 3028 bge_ifmedia_sts); 3029 mii_attach(sc->bge_dev, &sc->bge_mii, 0xffffffff, 3030 MII_PHY_ANY, MII_OFFSET_ANY, 3031 MIIF_FORCEANEG|MIIF_DOPAUSE); 3032 3033 if (LIST_EMPTY(&sc->bge_mii.mii_phys)) { 3034 aprint_error_dev(sc->bge_dev, "no PHY found!\n"); 3035 ifmedia_add(&sc->bge_mii.mii_media, 3036 IFM_ETHER|IFM_MANUAL, 0, NULL); 3037 ifmedia_set(&sc->bge_mii.mii_media, 3038 IFM_ETHER|IFM_MANUAL); 3039 } else 3040 ifmedia_set(&sc->bge_mii.mii_media, 3041 IFM_ETHER|IFM_AUTO); 3042 3043 /* 3044 * Now tell the firmware we are going up after probing the PHY 3045 */ 3046 if (sc->bge_asf_mode & ASF_STACKUP) 3047 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 3048 } 3049 3050 /* 3051 * Call MI attach routine. 3052 */ 3053 DPRINTFN(5, ("if_attach\n")); 3054 if_attach(ifp); 3055 DPRINTFN(5, ("ether_ifattach\n")); 3056 ether_ifattach(ifp, eaddr); 3057 ether_set_ifflags_cb(&sc->ethercom, bge_ifflags_cb); 3058 rnd_attach_source(&sc->rnd_source, device_xname(sc->bge_dev), 3059 RND_TYPE_NET, 0); 3060 #ifdef BGE_EVENT_COUNTERS 3061 /* 3062 * Attach event counters. 3063 */ 3064 evcnt_attach_dynamic(&sc->bge_ev_intr, EVCNT_TYPE_INTR, 3065 NULL, device_xname(sc->bge_dev), "intr"); 3066 evcnt_attach_dynamic(&sc->bge_ev_tx_xoff, EVCNT_TYPE_MISC, 3067 NULL, device_xname(sc->bge_dev), "tx_xoff"); 3068 evcnt_attach_dynamic(&sc->bge_ev_tx_xon, EVCNT_TYPE_MISC, 3069 NULL, device_xname(sc->bge_dev), "tx_xon"); 3070 evcnt_attach_dynamic(&sc->bge_ev_rx_xoff, EVCNT_TYPE_MISC, 3071 NULL, device_xname(sc->bge_dev), "rx_xoff"); 3072 evcnt_attach_dynamic(&sc->bge_ev_rx_xon, EVCNT_TYPE_MISC, 3073 NULL, device_xname(sc->bge_dev), "rx_xon"); 3074 evcnt_attach_dynamic(&sc->bge_ev_rx_macctl, EVCNT_TYPE_MISC, 3075 NULL, device_xname(sc->bge_dev), "rx_macctl"); 3076 evcnt_attach_dynamic(&sc->bge_ev_xoffentered, EVCNT_TYPE_MISC, 3077 NULL, device_xname(sc->bge_dev), "xoffentered"); 3078 #endif /* BGE_EVENT_COUNTERS */ 3079 DPRINTFN(5, ("callout_init\n")); 3080 callout_init(&sc->bge_timeout, 0); 3081 3082 if (pmf_device_register(self, NULL, NULL)) 3083 pmf_class_network_register(self, ifp); 3084 else 3085 aprint_error_dev(self, "couldn't establish power handler\n"); 3086 3087 bge_sysctl_init(sc); 3088 3089 #ifdef BGE_DEBUG 3090 bge_debug_info(sc); 3091 #endif 3092 } 3093 3094 static void 3095 bge_release_resources(struct bge_softc *sc) 3096 { 3097 if (sc->bge_vpd_prodname != NULL) 3098 free(sc->bge_vpd_prodname, M_DEVBUF); 3099 3100 if (sc->bge_vpd_readonly != NULL) 3101 free(sc->bge_vpd_readonly, M_DEVBUF); 3102 } 3103 3104 static int 3105 bge_reset(struct bge_softc *sc) 3106 { 3107 uint32_t cachesize, command, pcistate, marbmode; 3108 #if 0 3109 uint32_t new_pcistate; 3110 #endif 3111 pcireg_t devctl, reg; 3112 int i, val; 3113 void (*write_op)(struct bge_softc *, int, int); 3114 3115 if (BGE_IS_575X_PLUS(sc) && !BGE_IS_5714_FAMILY(sc) 3116 && (BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5906)) { 3117 if (sc->bge_flags & BGE_PCIE) 3118 write_op = bge_writemem_direct; 3119 else 3120 write_op = bge_writemem_ind; 3121 } else 3122 write_op = bge_writereg_ind; 3123 3124 /* Save some important PCI state. */ 3125 cachesize = pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CACHESZ); 3126 command = pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CMD); 3127 pcistate = pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_PCISTATE); 3128 3129 /* Step 5a: Enable memory arbiter. */ 3130 marbmode = 0; 3131 if (BGE_IS_5714_FAMILY(sc)) 3132 marbmode = CSR_READ_4(sc, BGE_MARB_MODE); 3133 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE | marbmode); 3134 3135 /* Step 5b-5d: */ 3136 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MISC_CTL, 3137 BGE_PCIMISCCTL_INDIRECT_ACCESS | BGE_PCIMISCCTL_MASK_PCI_INTR | 3138 BGE_HIF_SWAP_OPTIONS | BGE_PCIMISCCTL_PCISTATE_RW); 3139 3140 /* XXX ???: Disable fastboot on controllers that support it. */ 3141 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5752 || 3142 BGE_IS_5755_PLUS(sc)) 3143 CSR_WRITE_4(sc, BGE_FASTBOOT_PC, 0); 3144 3145 /* 3146 * Step 6: Write the magic number to SRAM at offset 0xB50. 3147 * When firmware finishes its initialization it will 3148 * write ~BGE_MAGIC_NUMBER to the same location. 3149 */ 3150 bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM, BGE_MAGIC_NUMBER); 3151 3152 /* Step 7: */ 3153 val = BGE_MISCCFG_RESET_CORE_CLOCKS | (65<<1); 3154 /* 3155 * XXX: from FreeBSD/Linux; no documentation 3156 */ 3157 if (sc->bge_flags & BGE_PCIE) { 3158 if (CSR_READ_4(sc, BGE_PCIE_CTL1) == 0x60) 3159 /* PCI Express 1.0 system */ 3160 CSR_WRITE_4(sc, BGE_PCIE_CTL1, 0x20); 3161 if (sc->bge_chipid != BGE_CHIPID_BCM5750_A0) { 3162 /* 3163 * Prevent PCI Express link training 3164 * during global reset. 3165 */ 3166 CSR_WRITE_4(sc, BGE_MISC_CFG, 1 << 29); 3167 val |= (1<<29); 3168 } 3169 } 3170 3171 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 3172 i = CSR_READ_4(sc, BGE_VCPU_STATUS); 3173 CSR_WRITE_4(sc, BGE_VCPU_STATUS, 3174 i | BGE_VCPU_STATUS_DRV_RESET); 3175 i = CSR_READ_4(sc, BGE_VCPU_EXT_CTRL); 3176 CSR_WRITE_4(sc, BGE_VCPU_EXT_CTRL, 3177 i & ~BGE_VCPU_EXT_CTRL_HALT_CPU); 3178 } 3179 3180 /* 3181 * Set GPHY Power Down Override to leave GPHY 3182 * powered up in D0 uninitialized. 3183 */ 3184 if (BGE_IS_5705_PLUS(sc)) 3185 val |= BGE_MISCCFG_KEEP_GPHY_POWER; 3186 3187 /* XXX 5721, 5751 and 5752 */ 3188 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5750) 3189 val |= BGE_MISCCFG_GRC_RESET_DISABLE; 3190 3191 /* Issue global reset */ 3192 write_op(sc, BGE_MISC_CFG, val); 3193 3194 /* Step 8: wait for complete */ 3195 if (sc->bge_flags & BGE_PCIE) 3196 delay(100*1000); /* too big */ 3197 else 3198 delay(100); 3199 3200 /* From Linux: dummy read to flush PCI posted writes */ 3201 reg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CMD); 3202 3203 /* Step 9-10: Reset some of the PCI state that got zapped by reset */ 3204 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MISC_CTL, 3205 BGE_PCIMISCCTL_INDIRECT_ACCESS | BGE_PCIMISCCTL_MASK_PCI_INTR | 3206 BGE_HIF_SWAP_OPTIONS | BGE_PCIMISCCTL_PCISTATE_RW 3207 | BGE_PCIMISCCTL_CLOCKCTL_RW); 3208 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CMD, command); 3209 write_op(sc, BGE_MISC_CFG, (65 << 1)); 3210 3211 /* Step 11: disable PCI-X Relaxed Ordering. */ 3212 if (sc->bge_flags & BGE_PCIX) { 3213 reg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, sc->bge_pcixcap 3214 + PCI_PCIX_CMD); 3215 pci_conf_write(sc->sc_pc, sc->sc_pcitag, sc->bge_pcixcap 3216 + PCI_PCIX_CMD, reg & ~PCI_PCIX_CMD_RELAXED_ORDER); 3217 } 3218 3219 if (sc->bge_flags & BGE_PCIE) { 3220 if (sc->bge_chipid == BGE_CHIPID_BCM5750_A0) { 3221 DELAY(500000); 3222 /* XXX: Magic Numbers */ 3223 reg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 3224 BGE_PCI_UNKNOWN0); 3225 pci_conf_write(sc->sc_pc, sc->sc_pcitag, 3226 BGE_PCI_UNKNOWN0, 3227 reg | (1 << 15)); 3228 } 3229 devctl = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 3230 sc->bge_pciecap + PCI_PCIE_DCSR); 3231 /* Clear enable no snoop and disable relaxed ordering. */ 3232 devctl &= ~(0x0010 | PCI_PCIE_DCSR_ENA_NO_SNOOP); 3233 /* Set PCIE max payload size to 128. */ 3234 devctl &= ~(0x00e0); 3235 /* Clear device status register. Write 1b to clear */ 3236 devctl |= PCI_PCIE_DCSR_URD | PCI_PCIE_DCSR_FED 3237 | PCI_PCIE_DCSR_NFED | PCI_PCIE_DCSR_CED; 3238 pci_conf_write(sc->sc_pc, sc->sc_pcitag, 3239 sc->bge_pciecap + PCI_PCIE_DCSR, devctl); 3240 } 3241 3242 /* Step 12: Enable memory arbiter. */ 3243 marbmode = 0; 3244 if (BGE_IS_5714_FAMILY(sc)) 3245 marbmode = CSR_READ_4(sc, BGE_MARB_MODE); 3246 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE | marbmode); 3247 3248 /* Step 17: Poll until the firmware initialization is complete */ 3249 bge_poll_fw(sc); 3250 3251 /* XXX 5721, 5751 and 5752 */ 3252 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5750) { 3253 /* Step 19: */ 3254 BGE_SETBIT(sc, BGE_TLP_CONTROL_REG, 1 << 29 | 1 << 25); 3255 /* Step 20: */ 3256 BGE_SETBIT(sc, BGE_TLP_CONTROL_REG, BGE_TLP_DATA_FIFO_PROTECT); 3257 } 3258 3259 /* 3260 * Step 18: wirte mac mode 3261 * XXX Write 0x0c for 5703S and 5704S 3262 */ 3263 CSR_WRITE_4(sc, BGE_MAC_MODE, 0); 3264 3265 3266 /* Step 21: 5822 B0 errata */ 3267 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5704_BX) { 3268 pcireg_t msidata; 3269 3270 msidata = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 3271 BGE_PCI_MSI_DATA); 3272 msidata |= ((1 << 13 | 1 << 12 | 1 << 10) << 16); 3273 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MSI_DATA, 3274 msidata); 3275 } 3276 3277 /* Step 23: restore cache line size */ 3278 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CACHESZ, cachesize); 3279 3280 #if 0 3281 /* 3282 * XXX Wait for the value of the PCISTATE register to 3283 * return to its original pre-reset state. This is a 3284 * fairly good indicator of reset completion. If we don't 3285 * wait for the reset to fully complete, trying to read 3286 * from the device's non-PCI registers may yield garbage 3287 * results. 3288 */ 3289 for (i = 0; i < BGE_TIMEOUT; i++) { 3290 new_pcistate = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 3291 BGE_PCI_PCISTATE); 3292 if ((new_pcistate & ~BGE_PCISTATE_RESERVED) == 3293 (pcistate & ~BGE_PCISTATE_RESERVED)) 3294 break; 3295 DELAY(10); 3296 } 3297 if ((new_pcistate & ~BGE_PCISTATE_RESERVED) != 3298 (pcistate & ~BGE_PCISTATE_RESERVED)) { 3299 aprint_error_dev(sc->bge_dev, "pcistate failed to revert\n"); 3300 } 3301 #endif 3302 3303 /* Step 28: Fix up byte swapping */ 3304 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS); 3305 3306 /* Tell the ASF firmware we are up */ 3307 if (sc->bge_asf_mode & ASF_STACKUP) 3308 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 3309 3310 /* 3311 * The 5704 in TBI mode apparently needs some special 3312 * adjustment to insure the SERDES drive level is set 3313 * to 1.2V. 3314 */ 3315 if (sc->bge_flags & BGE_PHY_FIBER_TBI && 3316 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) { 3317 uint32_t serdescfg; 3318 3319 serdescfg = CSR_READ_4(sc, BGE_SERDES_CFG); 3320 serdescfg = (serdescfg & ~0xFFF) | 0x880; 3321 CSR_WRITE_4(sc, BGE_SERDES_CFG, serdescfg); 3322 } 3323 3324 if (sc->bge_flags & BGE_PCIE && 3325 sc->bge_chipid != BGE_CHIPID_BCM5750_A0 && 3326 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5717 && 3327 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5785 && 3328 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM57765 && 3329 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM57766) { 3330 uint32_t v; 3331 3332 /* Enable PCI Express bug fix */ 3333 v = CSR_READ_4(sc, 0x7c00); 3334 CSR_WRITE_4(sc, 0x7c00, v | (1<<25)); 3335 } 3336 DELAY(10000); 3337 3338 return 0; 3339 } 3340 3341 /* 3342 * Frame reception handling. This is called if there's a frame 3343 * on the receive return list. 3344 * 3345 * Note: we have to be able to handle two possibilities here: 3346 * 1) the frame is from the jumbo receive ring 3347 * 2) the frame is from the standard receive ring 3348 */ 3349 3350 static void 3351 bge_rxeof(struct bge_softc *sc) 3352 { 3353 struct ifnet *ifp; 3354 uint16_t rx_prod, rx_cons; 3355 int stdcnt = 0, jumbocnt = 0; 3356 bus_dmamap_t dmamap; 3357 bus_addr_t offset, toff; 3358 bus_size_t tlen; 3359 int tosync; 3360 3361 rx_cons = sc->bge_rx_saved_considx; 3362 rx_prod = sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx; 3363 3364 /* Nothing to do */ 3365 if (rx_cons == rx_prod) 3366 return; 3367 3368 ifp = &sc->ethercom.ec_if; 3369 3370 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 3371 offsetof(struct bge_ring_data, bge_status_block), 3372 sizeof (struct bge_status_block), 3373 BUS_DMASYNC_POSTREAD); 3374 3375 offset = offsetof(struct bge_ring_data, bge_rx_return_ring); 3376 tosync = rx_prod - rx_cons; 3377 3378 if (tosync != 0) 3379 rnd_add_uint32(&sc->rnd_source, tosync); 3380 3381 toff = offset + (rx_cons * sizeof (struct bge_rx_bd)); 3382 3383 if (tosync < 0) { 3384 tlen = (sc->bge_return_ring_cnt - rx_cons) * 3385 sizeof (struct bge_rx_bd); 3386 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 3387 toff, tlen, BUS_DMASYNC_POSTREAD); 3388 tosync = -tosync; 3389 } 3390 3391 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 3392 offset, tosync * sizeof (struct bge_rx_bd), 3393 BUS_DMASYNC_POSTREAD); 3394 3395 while (rx_cons != rx_prod) { 3396 struct bge_rx_bd *cur_rx; 3397 uint32_t rxidx; 3398 struct mbuf *m = NULL; 3399 3400 cur_rx = &sc->bge_rdata->bge_rx_return_ring[rx_cons]; 3401 3402 rxidx = cur_rx->bge_idx; 3403 BGE_INC(rx_cons, sc->bge_return_ring_cnt); 3404 3405 if (cur_rx->bge_flags & BGE_RXBDFLAG_JUMBO_RING) { 3406 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT); 3407 m = sc->bge_cdata.bge_rx_jumbo_chain[rxidx]; 3408 sc->bge_cdata.bge_rx_jumbo_chain[rxidx] = NULL; 3409 jumbocnt++; 3410 bus_dmamap_sync(sc->bge_dmatag, 3411 sc->bge_cdata.bge_rx_jumbo_map, 3412 mtod(m, char *) - (char *)sc->bge_cdata.bge_jumbo_buf, 3413 BGE_JLEN, BUS_DMASYNC_POSTREAD); 3414 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 3415 ifp->if_ierrors++; 3416 bge_newbuf_jumbo(sc, sc->bge_jumbo, m); 3417 continue; 3418 } 3419 if (bge_newbuf_jumbo(sc, sc->bge_jumbo, 3420 NULL)== ENOBUFS) { 3421 ifp->if_ierrors++; 3422 bge_newbuf_jumbo(sc, sc->bge_jumbo, m); 3423 continue; 3424 } 3425 } else { 3426 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT); 3427 m = sc->bge_cdata.bge_rx_std_chain[rxidx]; 3428 3429 sc->bge_cdata.bge_rx_std_chain[rxidx] = NULL; 3430 stdcnt++; 3431 dmamap = sc->bge_cdata.bge_rx_std_map[rxidx]; 3432 sc->bge_cdata.bge_rx_std_map[rxidx] = 0; 3433 if (dmamap == NULL) { 3434 ifp->if_ierrors++; 3435 bge_newbuf_std(sc, sc->bge_std, m, dmamap); 3436 continue; 3437 } 3438 bus_dmamap_sync(sc->bge_dmatag, dmamap, 0, 3439 dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 3440 bus_dmamap_unload(sc->bge_dmatag, dmamap); 3441 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 3442 ifp->if_ierrors++; 3443 bge_newbuf_std(sc, sc->bge_std, m, dmamap); 3444 continue; 3445 } 3446 if (bge_newbuf_std(sc, sc->bge_std, 3447 NULL, dmamap) == ENOBUFS) { 3448 ifp->if_ierrors++; 3449 bge_newbuf_std(sc, sc->bge_std, m, dmamap); 3450 continue; 3451 } 3452 } 3453 3454 ifp->if_ipackets++; 3455 #ifndef __NO_STRICT_ALIGNMENT 3456 /* 3457 * XXX: if the 5701 PCIX-Rx-DMA workaround is in effect, 3458 * the Rx buffer has the layer-2 header unaligned. 3459 * If our CPU requires alignment, re-align by copying. 3460 */ 3461 if (sc->bge_flags & BGE_RX_ALIGNBUG) { 3462 memmove(mtod(m, char *) + ETHER_ALIGN, m->m_data, 3463 cur_rx->bge_len); 3464 m->m_data += ETHER_ALIGN; 3465 } 3466 #endif 3467 3468 m->m_pkthdr.len = m->m_len = cur_rx->bge_len - ETHER_CRC_LEN; 3469 m->m_pkthdr.rcvif = ifp; 3470 3471 /* 3472 * Handle BPF listeners. Let the BPF user see the packet. 3473 */ 3474 bpf_mtap(ifp, m); 3475 3476 m->m_pkthdr.csum_flags = M_CSUM_IPv4; 3477 3478 if ((cur_rx->bge_ip_csum ^ 0xffff) != 0) 3479 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 3480 /* 3481 * Rx transport checksum-offload may also 3482 * have bugs with packets which, when transmitted, 3483 * were `runts' requiring padding. 3484 */ 3485 if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM && 3486 (/* (sc->_bge_quirks & BGE_QUIRK_SHORT_CKSUM_BUG) == 0 ||*/ 3487 m->m_pkthdr.len >= ETHER_MIN_NOPAD)) { 3488 m->m_pkthdr.csum_data = 3489 cur_rx->bge_tcp_udp_csum; 3490 m->m_pkthdr.csum_flags |= 3491 (M_CSUM_TCPv4|M_CSUM_UDPv4| 3492 M_CSUM_DATA); 3493 } 3494 3495 /* 3496 * If we received a packet with a vlan tag, pass it 3497 * to vlan_input() instead of ether_input(). 3498 */ 3499 if (cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) { 3500 VLAN_INPUT_TAG(ifp, m, cur_rx->bge_vlan_tag, continue); 3501 } 3502 3503 (*ifp->if_input)(ifp, m); 3504 } 3505 3506 sc->bge_rx_saved_considx = rx_cons; 3507 bge_writembx(sc, BGE_MBX_RX_CONS0_LO, sc->bge_rx_saved_considx); 3508 if (stdcnt) 3509 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std); 3510 if (jumbocnt) 3511 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo); 3512 } 3513 3514 static void 3515 bge_txeof(struct bge_softc *sc) 3516 { 3517 struct bge_tx_bd *cur_tx = NULL; 3518 struct ifnet *ifp; 3519 struct txdmamap_pool_entry *dma; 3520 bus_addr_t offset, toff; 3521 bus_size_t tlen; 3522 int tosync; 3523 struct mbuf *m; 3524 3525 ifp = &sc->ethercom.ec_if; 3526 3527 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 3528 offsetof(struct bge_ring_data, bge_status_block), 3529 sizeof (struct bge_status_block), 3530 BUS_DMASYNC_POSTREAD); 3531 3532 offset = offsetof(struct bge_ring_data, bge_tx_ring); 3533 tosync = sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx - 3534 sc->bge_tx_saved_considx; 3535 3536 if (tosync != 0) 3537 rnd_add_uint32(&sc->rnd_source, tosync); 3538 3539 toff = offset + (sc->bge_tx_saved_considx * sizeof (struct bge_tx_bd)); 3540 3541 if (tosync < 0) { 3542 tlen = (BGE_TX_RING_CNT - sc->bge_tx_saved_considx) * 3543 sizeof (struct bge_tx_bd); 3544 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 3545 toff, tlen, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 3546 tosync = -tosync; 3547 } 3548 3549 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 3550 offset, tosync * sizeof (struct bge_tx_bd), 3551 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 3552 3553 /* 3554 * Go through our tx ring and free mbufs for those 3555 * frames that have been sent. 3556 */ 3557 while (sc->bge_tx_saved_considx != 3558 sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx) { 3559 uint32_t idx = 0; 3560 3561 idx = sc->bge_tx_saved_considx; 3562 cur_tx = &sc->bge_rdata->bge_tx_ring[idx]; 3563 if (cur_tx->bge_flags & BGE_TXBDFLAG_END) 3564 ifp->if_opackets++; 3565 m = sc->bge_cdata.bge_tx_chain[idx]; 3566 if (m != NULL) { 3567 sc->bge_cdata.bge_tx_chain[idx] = NULL; 3568 dma = sc->txdma[idx]; 3569 bus_dmamap_sync(sc->bge_dmatag, dma->dmamap, 0, 3570 dma->dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 3571 bus_dmamap_unload(sc->bge_dmatag, dma->dmamap); 3572 SLIST_INSERT_HEAD(&sc->txdma_list, dma, link); 3573 sc->txdma[idx] = NULL; 3574 3575 m_freem(m); 3576 } 3577 sc->bge_txcnt--; 3578 BGE_INC(sc->bge_tx_saved_considx, BGE_TX_RING_CNT); 3579 ifp->if_timer = 0; 3580 } 3581 3582 if (cur_tx != NULL) 3583 ifp->if_flags &= ~IFF_OACTIVE; 3584 } 3585 3586 static int 3587 bge_intr(void *xsc) 3588 { 3589 struct bge_softc *sc; 3590 struct ifnet *ifp; 3591 uint32_t statusword; 3592 3593 sc = xsc; 3594 ifp = &sc->ethercom.ec_if; 3595 3596 /* It is possible for the interrupt to arrive before 3597 * the status block is updated prior to the interrupt. 3598 * Reading the PCI State register will confirm whether the 3599 * interrupt is ours and will flush the status block. 3600 */ 3601 3602 /* read status word from status block */ 3603 statusword = sc->bge_rdata->bge_status_block.bge_status; 3604 3605 if ((statusword & BGE_STATFLAG_UPDATED) || 3606 (!(CSR_READ_4(sc, BGE_PCI_PCISTATE) & BGE_PCISTATE_INTR_NOT_ACTIVE))) { 3607 /* Ack interrupt and stop others from occuring. */ 3608 bge_writembx(sc, BGE_MBX_IRQ0_LO, 1); 3609 3610 BGE_EVCNT_INCR(sc->bge_ev_intr); 3611 3612 /* clear status word */ 3613 sc->bge_rdata->bge_status_block.bge_status = 0; 3614 3615 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 3616 statusword & BGE_STATFLAG_LINKSTATE_CHANGED || 3617 BGE_STS_BIT(sc, BGE_STS_LINK_EVT)) 3618 bge_link_upd(sc); 3619 3620 if (ifp->if_flags & IFF_RUNNING) { 3621 /* Check RX return ring producer/consumer */ 3622 bge_rxeof(sc); 3623 3624 /* Check TX ring producer/consumer */ 3625 bge_txeof(sc); 3626 } 3627 3628 if (sc->bge_pending_rxintr_change) { 3629 uint32_t rx_ticks = sc->bge_rx_coal_ticks; 3630 uint32_t rx_bds = sc->bge_rx_max_coal_bds; 3631 uint32_t junk; 3632 3633 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, rx_ticks); 3634 DELAY(10); 3635 junk = CSR_READ_4(sc, BGE_HCC_RX_COAL_TICKS); 3636 3637 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, rx_bds); 3638 DELAY(10); 3639 junk = CSR_READ_4(sc, BGE_HCC_RX_MAX_COAL_BDS); 3640 3641 sc->bge_pending_rxintr_change = 0; 3642 } 3643 bge_handle_events(sc); 3644 3645 /* Re-enable interrupts. */ 3646 bge_writembx(sc, BGE_MBX_IRQ0_LO, 0); 3647 3648 if (ifp->if_flags & IFF_RUNNING && !IFQ_IS_EMPTY(&ifp->if_snd)) 3649 bge_start(ifp); 3650 3651 return 1; 3652 } else 3653 return 0; 3654 } 3655 3656 static void 3657 bge_asf_driver_up(struct bge_softc *sc) 3658 { 3659 if (sc->bge_asf_mode & ASF_STACKUP) { 3660 /* Send ASF heartbeat aprox. every 2s */ 3661 if (sc->bge_asf_count) 3662 sc->bge_asf_count --; 3663 else { 3664 sc->bge_asf_count = 2; 3665 bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM_FW, 3666 BGE_FW_DRV_ALIVE); 3667 bge_writemem_ind(sc, BGE_SOFTWARE_GENNCOMM_FW_LEN, 4); 3668 bge_writemem_ind(sc, BGE_SOFTWARE_GENNCOMM_FW_DATA, 3); 3669 CSR_WRITE_4(sc, BGE_CPU_EVENT, 3670 CSR_READ_4(sc, BGE_CPU_EVENT) | (1 << 14)); 3671 } 3672 } 3673 } 3674 3675 static void 3676 bge_tick(void *xsc) 3677 { 3678 struct bge_softc *sc = xsc; 3679 struct mii_data *mii = &sc->bge_mii; 3680 int s; 3681 3682 s = splnet(); 3683 3684 if (BGE_IS_5705_PLUS(sc)) 3685 bge_stats_update_regs(sc); 3686 else 3687 bge_stats_update(sc); 3688 3689 if (sc->bge_flags & BGE_PHY_FIBER_TBI) { 3690 /* 3691 * Since in TBI mode auto-polling can't be used we should poll 3692 * link status manually. Here we register pending link event 3693 * and trigger interrupt. 3694 */ 3695 BGE_STS_SETBIT(sc, BGE_STS_LINK_EVT); 3696 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET); 3697 } else { 3698 /* 3699 * Do not touch PHY if we have link up. This could break 3700 * IPMI/ASF mode or produce extra input errors. 3701 * (extra input errors was reported for bcm5701 & bcm5704). 3702 */ 3703 if (!BGE_STS_BIT(sc, BGE_STS_LINK)) 3704 mii_tick(mii); 3705 } 3706 3707 callout_reset(&sc->bge_timeout, hz, bge_tick, sc); 3708 3709 splx(s); 3710 } 3711 3712 static void 3713 bge_stats_update_regs(struct bge_softc *sc) 3714 { 3715 struct ifnet *ifp = &sc->ethercom.ec_if; 3716 3717 ifp->if_collisions += CSR_READ_4(sc, BGE_MAC_STATS + 3718 offsetof(struct bge_mac_stats_regs, etherStatsCollisions)); 3719 3720 ifp->if_ierrors += CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_DROPS); 3721 ifp->if_ierrors += CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_ERRORS); 3722 ifp->if_ierrors += CSR_READ_4(sc, BGE_RXLP_LOCSTAT_OUT_OF_BDS); 3723 } 3724 3725 static void 3726 bge_stats_update(struct bge_softc *sc) 3727 { 3728 struct ifnet *ifp = &sc->ethercom.ec_if; 3729 bus_size_t stats = BGE_MEMWIN_START + BGE_STATS_BLOCK; 3730 3731 #define READ_STAT(sc, stats, stat) \ 3732 CSR_READ_4(sc, stats + offsetof(struct bge_stats, stat)) 3733 3734 ifp->if_collisions += 3735 (READ_STAT(sc, stats, dot3StatsSingleCollisionFrames.bge_addr_lo) + 3736 READ_STAT(sc, stats, dot3StatsMultipleCollisionFrames.bge_addr_lo) + 3737 READ_STAT(sc, stats, dot3StatsExcessiveCollisions.bge_addr_lo) + 3738 READ_STAT(sc, stats, dot3StatsLateCollisions.bge_addr_lo)) - 3739 ifp->if_collisions; 3740 3741 BGE_EVCNT_UPD(sc->bge_ev_tx_xoff, 3742 READ_STAT(sc, stats, outXoffSent.bge_addr_lo)); 3743 BGE_EVCNT_UPD(sc->bge_ev_tx_xon, 3744 READ_STAT(sc, stats, outXonSent.bge_addr_lo)); 3745 BGE_EVCNT_UPD(sc->bge_ev_rx_xoff, 3746 READ_STAT(sc, stats, 3747 xoffPauseFramesReceived.bge_addr_lo)); 3748 BGE_EVCNT_UPD(sc->bge_ev_rx_xon, 3749 READ_STAT(sc, stats, xonPauseFramesReceived.bge_addr_lo)); 3750 BGE_EVCNT_UPD(sc->bge_ev_rx_macctl, 3751 READ_STAT(sc, stats, 3752 macControlFramesReceived.bge_addr_lo)); 3753 BGE_EVCNT_UPD(sc->bge_ev_xoffentered, 3754 READ_STAT(sc, stats, xoffStateEntered.bge_addr_lo)); 3755 3756 #undef READ_STAT 3757 3758 #ifdef notdef 3759 ifp->if_collisions += 3760 (sc->bge_rdata->bge_info.bge_stats.dot3StatsSingleCollisionFrames + 3761 sc->bge_rdata->bge_info.bge_stats.dot3StatsMultipleCollisionFrames + 3762 sc->bge_rdata->bge_info.bge_stats.dot3StatsExcessiveCollisions + 3763 sc->bge_rdata->bge_info.bge_stats.dot3StatsLateCollisions) - 3764 ifp->if_collisions; 3765 #endif 3766 } 3767 3768 /* 3769 * Pad outbound frame to ETHER_MIN_NOPAD for an unusual reason. 3770 * The bge hardware will pad out Tx runts to ETHER_MIN_NOPAD, 3771 * but when such padded frames employ the bge IP/TCP checksum offload, 3772 * the hardware checksum assist gives incorrect results (possibly 3773 * from incorporating its own padding into the UDP/TCP checksum; who knows). 3774 * If we pad such runts with zeros, the onboard checksum comes out correct. 3775 */ 3776 static inline int 3777 bge_cksum_pad(struct mbuf *pkt) 3778 { 3779 struct mbuf *last = NULL; 3780 int padlen; 3781 3782 padlen = ETHER_MIN_NOPAD - pkt->m_pkthdr.len; 3783 3784 /* if there's only the packet-header and we can pad there, use it. */ 3785 if (pkt->m_pkthdr.len == pkt->m_len && 3786 M_TRAILINGSPACE(pkt) >= padlen) { 3787 last = pkt; 3788 } else { 3789 /* 3790 * Walk packet chain to find last mbuf. We will either 3791 * pad there, or append a new mbuf and pad it 3792 * (thus perhaps avoiding the bcm5700 dma-min bug). 3793 */ 3794 for (last = pkt; last->m_next != NULL; last = last->m_next) { 3795 continue; /* do nothing */ 3796 } 3797 3798 /* `last' now points to last in chain. */ 3799 if (M_TRAILINGSPACE(last) < padlen) { 3800 /* Allocate new empty mbuf, pad it. Compact later. */ 3801 struct mbuf *n; 3802 MGET(n, M_DONTWAIT, MT_DATA); 3803 if (n == NULL) 3804 return ENOBUFS; 3805 n->m_len = 0; 3806 last->m_next = n; 3807 last = n; 3808 } 3809 } 3810 3811 KDASSERT(!M_READONLY(last)); 3812 KDASSERT(M_TRAILINGSPACE(last) >= padlen); 3813 3814 /* Now zero the pad area, to avoid the bge cksum-assist bug */ 3815 memset(mtod(last, char *) + last->m_len, 0, padlen); 3816 last->m_len += padlen; 3817 pkt->m_pkthdr.len += padlen; 3818 return 0; 3819 } 3820 3821 /* 3822 * Compact outbound packets to avoid bug with DMA segments less than 8 bytes. 3823 */ 3824 static inline int 3825 bge_compact_dma_runt(struct mbuf *pkt) 3826 { 3827 struct mbuf *m, *prev; 3828 int totlen, prevlen; 3829 3830 prev = NULL; 3831 totlen = 0; 3832 prevlen = -1; 3833 3834 for (m = pkt; m != NULL; prev = m,m = m->m_next) { 3835 int mlen = m->m_len; 3836 int shortfall = 8 - mlen ; 3837 3838 totlen += mlen; 3839 if (mlen == 0) 3840 continue; 3841 if (mlen >= 8) 3842 continue; 3843 3844 /* If we get here, mbuf data is too small for DMA engine. 3845 * Try to fix by shuffling data to prev or next in chain. 3846 * If that fails, do a compacting deep-copy of the whole chain. 3847 */ 3848 3849 /* Internal frag. If fits in prev, copy it there. */ 3850 if (prev && M_TRAILINGSPACE(prev) >= m->m_len) { 3851 memcpy(prev->m_data + prev->m_len, m->m_data, mlen); 3852 prev->m_len += mlen; 3853 m->m_len = 0; 3854 /* XXX stitch chain */ 3855 prev->m_next = m_free(m); 3856 m = prev; 3857 continue; 3858 } 3859 else if (m->m_next != NULL && 3860 M_TRAILINGSPACE(m) >= shortfall && 3861 m->m_next->m_len >= (8 + shortfall)) { 3862 /* m is writable and have enough data in next, pull up. */ 3863 3864 memcpy(m->m_data + m->m_len, m->m_next->m_data, 3865 shortfall); 3866 m->m_len += shortfall; 3867 m->m_next->m_len -= shortfall; 3868 m->m_next->m_data += shortfall; 3869 } 3870 else if (m->m_next == NULL || 1) { 3871 /* Got a runt at the very end of the packet. 3872 * borrow data from the tail of the preceding mbuf and 3873 * update its length in-place. (The original data is still 3874 * valid, so we can do this even if prev is not writable.) 3875 */ 3876 3877 /* if we'd make prev a runt, just move all of its data. */ 3878 KASSERT(prev != NULL /*, ("runt but null PREV")*/); 3879 KASSERT(prev->m_len >= 8 /*, ("runt prev")*/); 3880 3881 if ((prev->m_len - shortfall) < 8) 3882 shortfall = prev->m_len; 3883 3884 #ifdef notyet /* just do the safe slow thing for now */ 3885 if (!M_READONLY(m)) { 3886 if (M_LEADINGSPACE(m) < shorfall) { 3887 void *m_dat; 3888 m_dat = (m->m_flags & M_PKTHDR) ? 3889 m->m_pktdat : m->dat; 3890 memmove(m_dat, mtod(m, void*), m->m_len); 3891 m->m_data = m_dat; 3892 } 3893 } else 3894 #endif /* just do the safe slow thing */ 3895 { 3896 struct mbuf * n = NULL; 3897 int newprevlen = prev->m_len - shortfall; 3898 3899 MGET(n, M_NOWAIT, MT_DATA); 3900 if (n == NULL) 3901 return ENOBUFS; 3902 KASSERT(m->m_len + shortfall < MLEN 3903 /*, 3904 ("runt %d +prev %d too big\n", m->m_len, shortfall)*/); 3905 3906 /* first copy the data we're stealing from prev */ 3907 memcpy(n->m_data, prev->m_data + newprevlen, 3908 shortfall); 3909 3910 /* update prev->m_len accordingly */ 3911 prev->m_len -= shortfall; 3912 3913 /* copy data from runt m */ 3914 memcpy(n->m_data + shortfall, m->m_data, 3915 m->m_len); 3916 3917 /* n holds what we stole from prev, plus m */ 3918 n->m_len = shortfall + m->m_len; 3919 3920 /* stitch n into chain and free m */ 3921 n->m_next = m->m_next; 3922 prev->m_next = n; 3923 /* KASSERT(m->m_next == NULL); */ 3924 m->m_next = NULL; 3925 m_free(m); 3926 m = n; /* for continuing loop */ 3927 } 3928 } 3929 prevlen = m->m_len; 3930 } 3931 return 0; 3932 } 3933 3934 /* 3935 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data 3936 * pointers to descriptors. 3937 */ 3938 static int 3939 bge_encap(struct bge_softc *sc, struct mbuf *m_head, uint32_t *txidx) 3940 { 3941 struct bge_tx_bd *f = NULL; 3942 uint32_t frag, cur; 3943 uint16_t csum_flags = 0; 3944 uint16_t txbd_tso_flags = 0; 3945 struct txdmamap_pool_entry *dma; 3946 bus_dmamap_t dmamap; 3947 int i = 0; 3948 struct m_tag *mtag; 3949 int use_tso, maxsegsize, error; 3950 3951 cur = frag = *txidx; 3952 3953 if (m_head->m_pkthdr.csum_flags) { 3954 if (m_head->m_pkthdr.csum_flags & M_CSUM_IPv4) 3955 csum_flags |= BGE_TXBDFLAG_IP_CSUM; 3956 if (m_head->m_pkthdr.csum_flags & (M_CSUM_TCPv4|M_CSUM_UDPv4)) 3957 csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM; 3958 } 3959 3960 /* 3961 * If we were asked to do an outboard checksum, and the NIC 3962 * has the bug where it sometimes adds in the Ethernet padding, 3963 * explicitly pad with zeros so the cksum will be correct either way. 3964 * (For now, do this for all chip versions, until newer 3965 * are confirmed to not require the workaround.) 3966 */ 3967 if ((csum_flags & BGE_TXBDFLAG_TCP_UDP_CSUM) == 0 || 3968 #ifdef notyet 3969 (sc->bge_quirks & BGE_QUIRK_SHORT_CKSUM_BUG) == 0 || 3970 #endif 3971 m_head->m_pkthdr.len >= ETHER_MIN_NOPAD) 3972 goto check_dma_bug; 3973 3974 if (bge_cksum_pad(m_head) != 0) 3975 return ENOBUFS; 3976 3977 check_dma_bug: 3978 if (!(BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX)) 3979 goto doit; 3980 3981 /* 3982 * bcm5700 Revision B silicon cannot handle DMA descriptors with 3983 * less than eight bytes. If we encounter a teeny mbuf 3984 * at the end of a chain, we can pad. Otherwise, copy. 3985 */ 3986 if (bge_compact_dma_runt(m_head) != 0) 3987 return ENOBUFS; 3988 3989 doit: 3990 dma = SLIST_FIRST(&sc->txdma_list); 3991 if (dma == NULL) 3992 return ENOBUFS; 3993 dmamap = dma->dmamap; 3994 3995 /* 3996 * Set up any necessary TSO state before we start packing... 3997 */ 3998 use_tso = (m_head->m_pkthdr.csum_flags & M_CSUM_TSOv4) != 0; 3999 if (!use_tso) { 4000 maxsegsize = 0; 4001 } else { /* TSO setup */ 4002 unsigned mss; 4003 struct ether_header *eh; 4004 unsigned ip_tcp_hlen, iptcp_opt_words, tcp_seg_flags, offset; 4005 struct mbuf * m0 = m_head; 4006 struct ip *ip; 4007 struct tcphdr *th; 4008 int iphl, hlen; 4009 4010 /* 4011 * XXX It would be nice if the mbuf pkthdr had offset 4012 * fields for the protocol headers. 4013 */ 4014 4015 eh = mtod(m0, struct ether_header *); 4016 switch (htons(eh->ether_type)) { 4017 case ETHERTYPE_IP: 4018 offset = ETHER_HDR_LEN; 4019 break; 4020 4021 case ETHERTYPE_VLAN: 4022 offset = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 4023 break; 4024 4025 default: 4026 /* 4027 * Don't support this protocol or encapsulation. 4028 */ 4029 return ENOBUFS; 4030 } 4031 4032 /* 4033 * TCP/IP headers are in the first mbuf; we can do 4034 * this the easy way. 4035 */ 4036 iphl = M_CSUM_DATA_IPv4_IPHL(m0->m_pkthdr.csum_data); 4037 hlen = iphl + offset; 4038 if (__predict_false(m0->m_len < 4039 (hlen + sizeof(struct tcphdr)))) { 4040 4041 aprint_debug_dev(sc->bge_dev, 4042 "TSO: hard case m0->m_len == %d < ip/tcp hlen %zd," 4043 "not handled yet\n", 4044 m0->m_len, hlen+ sizeof(struct tcphdr)); 4045 #ifdef NOTYET 4046 /* 4047 * XXX jonathan (at) NetBSD.org: untested. 4048 * how to force this branch to be taken? 4049 */ 4050 BGE_EVCNT_INCR(&sc->sc_ev_txtsopain); 4051 4052 m_copydata(m0, offset, sizeof(ip), &ip); 4053 m_copydata(m0, hlen, sizeof(th), &th); 4054 4055 ip.ip_len = 0; 4056 4057 m_copyback(m0, hlen + offsetof(struct ip, ip_len), 4058 sizeof(ip.ip_len), &ip.ip_len); 4059 4060 th.th_sum = in_cksum_phdr(ip.ip_src.s_addr, 4061 ip.ip_dst.s_addr, htons(IPPROTO_TCP)); 4062 4063 m_copyback(m0, hlen + offsetof(struct tcphdr, th_sum), 4064 sizeof(th.th_sum), &th.th_sum); 4065 4066 hlen += th.th_off << 2; 4067 iptcp_opt_words = hlen; 4068 #else 4069 /* 4070 * if_wm "hard" case not yet supported, can we not 4071 * mandate it out of existence? 4072 */ 4073 (void) ip; (void)th; (void) ip_tcp_hlen; 4074 4075 return ENOBUFS; 4076 #endif 4077 } else { 4078 ip = (struct ip *) (mtod(m0, char *) + offset); 4079 th = (struct tcphdr *) (mtod(m0, char *) + hlen); 4080 ip_tcp_hlen = iphl + (th->th_off << 2); 4081 4082 /* Total IP/TCP options, in 32-bit words */ 4083 iptcp_opt_words = (ip_tcp_hlen 4084 - sizeof(struct tcphdr) 4085 - sizeof(struct ip)) >> 2; 4086 } 4087 if (BGE_IS_575X_PLUS(sc)) { 4088 th->th_sum = 0; 4089 csum_flags &= ~(BGE_TXBDFLAG_TCP_UDP_CSUM); 4090 } else { 4091 /* 4092 * XXX jonathan (at) NetBSD.org: 5705 untested. 4093 * Requires TSO firmware patch for 5701/5703/5704. 4094 */ 4095 th->th_sum = in_cksum_phdr(ip->ip_src.s_addr, 4096 ip->ip_dst.s_addr, htons(IPPROTO_TCP)); 4097 } 4098 4099 mss = m_head->m_pkthdr.segsz; 4100 txbd_tso_flags |= 4101 BGE_TXBDFLAG_CPU_PRE_DMA | 4102 BGE_TXBDFLAG_CPU_POST_DMA; 4103 4104 /* 4105 * Our NIC TSO-assist assumes TSO has standard, optionless 4106 * IPv4 and TCP headers, which total 40 bytes. By default, 4107 * the NIC copies 40 bytes of IP/TCP header from the 4108 * supplied header into the IP/TCP header portion of 4109 * each post-TSO-segment. If the supplied packet has IP or 4110 * TCP options, we need to tell the NIC to copy those extra 4111 * bytes into each post-TSO header, in addition to the normal 4112 * 40-byte IP/TCP header (and to leave space accordingly). 4113 * Unfortunately, the driver encoding of option length 4114 * varies across different ASIC families. 4115 */ 4116 tcp_seg_flags = 0; 4117 if (iptcp_opt_words) { 4118 if (BGE_IS_5705_PLUS(sc)) { 4119 tcp_seg_flags = 4120 iptcp_opt_words << 11; 4121 } else { 4122 txbd_tso_flags |= 4123 iptcp_opt_words << 12; 4124 } 4125 } 4126 maxsegsize = mss | tcp_seg_flags; 4127 ip->ip_len = htons(mss + ip_tcp_hlen); 4128 4129 } /* TSO setup */ 4130 4131 /* 4132 * Start packing the mbufs in this chain into 4133 * the fragment pointers. Stop when we run out 4134 * of fragments or hit the end of the mbuf chain. 4135 */ 4136 error = bus_dmamap_load_mbuf(sc->bge_dmatag, dmamap, m_head, 4137 BUS_DMA_NOWAIT); 4138 if (error) 4139 return ENOBUFS; 4140 /* 4141 * Sanity check: avoid coming within 16 descriptors 4142 * of the end of the ring. 4143 */ 4144 if (dmamap->dm_nsegs > (BGE_TX_RING_CNT - sc->bge_txcnt - 16)) { 4145 BGE_TSO_PRINTF(("%s: " 4146 " dmamap_load_mbuf too close to ring wrap\n", 4147 device_xname(sc->bge_dev))); 4148 goto fail_unload; 4149 } 4150 4151 mtag = sc->ethercom.ec_nvlans ? 4152 m_tag_find(m_head, PACKET_TAG_VLAN, NULL) : NULL; 4153 4154 4155 /* Iterate over dmap-map fragments. */ 4156 for (i = 0; i < dmamap->dm_nsegs; i++) { 4157 f = &sc->bge_rdata->bge_tx_ring[frag]; 4158 if (sc->bge_cdata.bge_tx_chain[frag] != NULL) 4159 break; 4160 4161 BGE_HOSTADDR(f->bge_addr, dmamap->dm_segs[i].ds_addr); 4162 f->bge_len = dmamap->dm_segs[i].ds_len; 4163 4164 /* 4165 * For 5751 and follow-ons, for TSO we must turn 4166 * off checksum-assist flag in the tx-descr, and 4167 * supply the ASIC-revision-specific encoding 4168 * of TSO flags and segsize. 4169 */ 4170 if (use_tso) { 4171 if (BGE_IS_575X_PLUS(sc) || i == 0) { 4172 f->bge_rsvd = maxsegsize; 4173 f->bge_flags = csum_flags | txbd_tso_flags; 4174 } else { 4175 f->bge_rsvd = 0; 4176 f->bge_flags = 4177 (csum_flags | txbd_tso_flags) & 0x0fff; 4178 } 4179 } else { 4180 f->bge_rsvd = 0; 4181 f->bge_flags = csum_flags; 4182 } 4183 4184 if (mtag != NULL) { 4185 f->bge_flags |= BGE_TXBDFLAG_VLAN_TAG; 4186 f->bge_vlan_tag = VLAN_TAG_VALUE(mtag); 4187 } else { 4188 f->bge_vlan_tag = 0; 4189 } 4190 cur = frag; 4191 BGE_INC(frag, BGE_TX_RING_CNT); 4192 } 4193 4194 if (i < dmamap->dm_nsegs) { 4195 BGE_TSO_PRINTF(("%s: reached %d < dm_nsegs %d\n", 4196 device_xname(sc->bge_dev), i, dmamap->dm_nsegs)); 4197 goto fail_unload; 4198 } 4199 4200 bus_dmamap_sync(sc->bge_dmatag, dmamap, 0, dmamap->dm_mapsize, 4201 BUS_DMASYNC_PREWRITE); 4202 4203 if (frag == sc->bge_tx_saved_considx) { 4204 BGE_TSO_PRINTF(("%s: frag %d = wrapped id %d?\n", 4205 device_xname(sc->bge_dev), frag, sc->bge_tx_saved_considx)); 4206 4207 goto fail_unload; 4208 } 4209 4210 sc->bge_rdata->bge_tx_ring[cur].bge_flags |= BGE_TXBDFLAG_END; 4211 sc->bge_cdata.bge_tx_chain[cur] = m_head; 4212 SLIST_REMOVE_HEAD(&sc->txdma_list, link); 4213 sc->txdma[cur] = dma; 4214 sc->bge_txcnt += dmamap->dm_nsegs; 4215 4216 *txidx = frag; 4217 4218 return 0; 4219 4220 fail_unload: 4221 bus_dmamap_unload(sc->bge_dmatag, dmamap); 4222 4223 return ENOBUFS; 4224 } 4225 4226 /* 4227 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 4228 * to the mbuf data regions directly in the transmit descriptors. 4229 */ 4230 static void 4231 bge_start(struct ifnet *ifp) 4232 { 4233 struct bge_softc *sc; 4234 struct mbuf *m_head = NULL; 4235 uint32_t prodidx; 4236 int pkts = 0; 4237 4238 sc = ifp->if_softc; 4239 4240 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 4241 return; 4242 4243 prodidx = sc->bge_tx_prodidx; 4244 4245 while (sc->bge_cdata.bge_tx_chain[prodidx] == NULL) { 4246 IFQ_POLL(&ifp->if_snd, m_head); 4247 if (m_head == NULL) 4248 break; 4249 4250 #if 0 4251 /* 4252 * XXX 4253 * safety overkill. If this is a fragmented packet chain 4254 * with delayed TCP/UDP checksums, then only encapsulate 4255 * it if we have enough descriptors to handle the entire 4256 * chain at once. 4257 * (paranoia -- may not actually be needed) 4258 */ 4259 if (m_head->m_flags & M_FIRSTFRAG && 4260 m_head->m_pkthdr.csum_flags & (CSUM_DELAY_DATA)) { 4261 if ((BGE_TX_RING_CNT - sc->bge_txcnt) < 4262 M_CSUM_DATA_IPv4_OFFSET(m_head->m_pkthdr.csum_data) + 16) { 4263 ifp->if_flags |= IFF_OACTIVE; 4264 break; 4265 } 4266 } 4267 #endif 4268 4269 /* 4270 * Pack the data into the transmit ring. If we 4271 * don't have room, set the OACTIVE flag and wait 4272 * for the NIC to drain the ring. 4273 */ 4274 if (bge_encap(sc, m_head, &prodidx)) { 4275 ifp->if_flags |= IFF_OACTIVE; 4276 break; 4277 } 4278 4279 /* now we are committed to transmit the packet */ 4280 IFQ_DEQUEUE(&ifp->if_snd, m_head); 4281 pkts++; 4282 4283 /* 4284 * If there's a BPF listener, bounce a copy of this frame 4285 * to him. 4286 */ 4287 bpf_mtap(ifp, m_head); 4288 } 4289 if (pkts == 0) 4290 return; 4291 4292 /* Transmit */ 4293 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); 4294 /* 5700 b2 errata */ 4295 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX) 4296 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); 4297 4298 sc->bge_tx_prodidx = prodidx; 4299 4300 /* 4301 * Set a timeout in case the chip goes out to lunch. 4302 */ 4303 ifp->if_timer = 5; 4304 } 4305 4306 static int 4307 bge_init(struct ifnet *ifp) 4308 { 4309 struct bge_softc *sc = ifp->if_softc; 4310 const uint16_t *m; 4311 uint32_t mode; 4312 int s, error = 0; 4313 4314 s = splnet(); 4315 4316 ifp = &sc->ethercom.ec_if; 4317 4318 /* Cancel pending I/O and flush buffers. */ 4319 bge_stop(ifp, 0); 4320 4321 bge_stop_fw(sc); 4322 bge_sig_pre_reset(sc, BGE_RESET_START); 4323 bge_reset(sc); 4324 bge_sig_legacy(sc, BGE_RESET_START); 4325 bge_sig_post_reset(sc, BGE_RESET_START); 4326 4327 bge_chipinit(sc); 4328 4329 /* 4330 * Init the various state machines, ring 4331 * control blocks and firmware. 4332 */ 4333 error = bge_blockinit(sc); 4334 if (error != 0) { 4335 aprint_error_dev(sc->bge_dev, "initialization error %d\n", 4336 error); 4337 splx(s); 4338 return error; 4339 } 4340 4341 ifp = &sc->ethercom.ec_if; 4342 4343 /* Specify MTU. */ 4344 CSR_WRITE_4(sc, BGE_RX_MTU, ifp->if_mtu + 4345 ETHER_HDR_LEN + ETHER_CRC_LEN + ETHER_VLAN_ENCAP_LEN); 4346 4347 /* Load our MAC address. */ 4348 m = (const uint16_t *)&(CLLADDR(ifp->if_sadl)[0]); 4349 CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0])); 4350 CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, (htons(m[1]) << 16) | htons(m[2])); 4351 4352 /* Enable or disable promiscuous mode as needed. */ 4353 if (ifp->if_flags & IFF_PROMISC) 4354 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 4355 else 4356 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 4357 4358 /* Program multicast filter. */ 4359 bge_setmulti(sc); 4360 4361 /* Init RX ring. */ 4362 bge_init_rx_ring_std(sc); 4363 4364 /* 4365 * Workaround for a bug in 5705 ASIC rev A0. Poll the NIC's 4366 * memory to insure that the chip has in fact read the first 4367 * entry of the ring. 4368 */ 4369 if (sc->bge_chipid == BGE_CHIPID_BCM5705_A0) { 4370 uint32_t v, i; 4371 for (i = 0; i < 10; i++) { 4372 DELAY(20); 4373 v = bge_readmem_ind(sc, BGE_STD_RX_RINGS + 8); 4374 if (v == (MCLBYTES - ETHER_ALIGN)) 4375 break; 4376 } 4377 if (i == 10) 4378 aprint_error_dev(sc->bge_dev, 4379 "5705 A0 chip failed to load RX ring\n"); 4380 } 4381 4382 /* Init jumbo RX ring. */ 4383 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 4384 bge_init_rx_ring_jumbo(sc); 4385 4386 /* Init our RX return ring index */ 4387 sc->bge_rx_saved_considx = 0; 4388 4389 /* Init TX ring. */ 4390 bge_init_tx_ring(sc); 4391 4392 /* Enable TX MAC state machine lockup fix. */ 4393 mode = CSR_READ_4(sc, BGE_TX_MODE); 4394 if (BGE_IS_5755_PLUS(sc) || 4395 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 4396 mode |= BGE_TXMODE_MBUF_LOCKUP_FIX; 4397 4398 /* Turn on transmitter */ 4399 CSR_WRITE_4(sc, BGE_TX_MODE, mode | BGE_TXMODE_ENABLE); 4400 DELAY(100); 4401 4402 /* Turn on receiver */ 4403 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE); 4404 DELAY(10); 4405 4406 CSR_WRITE_4(sc, BGE_MAX_RX_FRAME_LOWAT, 2); 4407 4408 /* Tell firmware we're alive. */ 4409 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 4410 4411 /* Enable host interrupts. */ 4412 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA); 4413 BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); 4414 bge_writembx(sc, BGE_MBX_IRQ0_LO, 0); 4415 4416 if ((error = bge_ifmedia_upd(ifp)) != 0) 4417 goto out; 4418 4419 ifp->if_flags |= IFF_RUNNING; 4420 ifp->if_flags &= ~IFF_OACTIVE; 4421 4422 callout_reset(&sc->bge_timeout, hz, bge_tick, sc); 4423 4424 out: 4425 sc->bge_if_flags = ifp->if_flags; 4426 splx(s); 4427 4428 return error; 4429 } 4430 4431 /* 4432 * Set media options. 4433 */ 4434 static int 4435 bge_ifmedia_upd(struct ifnet *ifp) 4436 { 4437 struct bge_softc *sc = ifp->if_softc; 4438 struct mii_data *mii = &sc->bge_mii; 4439 struct ifmedia *ifm = &sc->bge_ifmedia; 4440 int rc; 4441 4442 /* If this is a 1000baseX NIC, enable the TBI port. */ 4443 if (sc->bge_flags & BGE_PHY_FIBER_TBI) { 4444 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 4445 return EINVAL; 4446 switch (IFM_SUBTYPE(ifm->ifm_media)) { 4447 case IFM_AUTO: 4448 /* 4449 * The BCM5704 ASIC appears to have a special 4450 * mechanism for programming the autoneg 4451 * advertisement registers in TBI mode. 4452 */ 4453 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) { 4454 uint32_t sgdig; 4455 sgdig = CSR_READ_4(sc, BGE_SGDIG_STS); 4456 if (sgdig & BGE_SGDIGSTS_DONE) { 4457 CSR_WRITE_4(sc, BGE_TX_TBI_AUTONEG, 0); 4458 sgdig = CSR_READ_4(sc, BGE_SGDIG_CFG); 4459 sgdig |= BGE_SGDIGCFG_AUTO | 4460 BGE_SGDIGCFG_PAUSE_CAP | 4461 BGE_SGDIGCFG_ASYM_PAUSE; 4462 CSR_WRITE_4(sc, BGE_SGDIG_CFG, 4463 sgdig | BGE_SGDIGCFG_SEND); 4464 DELAY(5); 4465 CSR_WRITE_4(sc, BGE_SGDIG_CFG, sgdig); 4466 } 4467 } 4468 break; 4469 case IFM_1000_SX: 4470 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 4471 BGE_CLRBIT(sc, BGE_MAC_MODE, 4472 BGE_MACMODE_HALF_DUPLEX); 4473 } else { 4474 BGE_SETBIT(sc, BGE_MAC_MODE, 4475 BGE_MACMODE_HALF_DUPLEX); 4476 } 4477 break; 4478 default: 4479 return EINVAL; 4480 } 4481 /* XXX 802.3x flow control for 1000BASE-SX */ 4482 return 0; 4483 } 4484 4485 BGE_STS_SETBIT(sc, BGE_STS_LINK_EVT); 4486 if ((rc = mii_mediachg(mii)) == ENXIO) 4487 return 0; 4488 4489 /* 4490 * Force an interrupt so that we will call bge_link_upd 4491 * if needed and clear any pending link state attention. 4492 * Without this we are not getting any further interrupts 4493 * for link state changes and thus will not UP the link and 4494 * not be able to send in bge_start. The only way to get 4495 * things working was to receive a packet and get a RX intr. 4496 */ 4497 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 4498 sc->bge_flags & BGE_IS_5788) 4499 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET); 4500 else 4501 BGE_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW); 4502 4503 return rc; 4504 } 4505 4506 /* 4507 * Report current media status. 4508 */ 4509 static void 4510 bge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 4511 { 4512 struct bge_softc *sc = ifp->if_softc; 4513 struct mii_data *mii = &sc->bge_mii; 4514 4515 if (sc->bge_flags & BGE_PHY_FIBER_TBI) { 4516 ifmr->ifm_status = IFM_AVALID; 4517 ifmr->ifm_active = IFM_ETHER; 4518 if (CSR_READ_4(sc, BGE_MAC_STS) & 4519 BGE_MACSTAT_TBI_PCS_SYNCHED) 4520 ifmr->ifm_status |= IFM_ACTIVE; 4521 ifmr->ifm_active |= IFM_1000_SX; 4522 if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX) 4523 ifmr->ifm_active |= IFM_HDX; 4524 else 4525 ifmr->ifm_active |= IFM_FDX; 4526 return; 4527 } 4528 4529 mii_pollstat(mii); 4530 ifmr->ifm_status = mii->mii_media_status; 4531 ifmr->ifm_active = (mii->mii_media_active & ~IFM_ETH_FMASK) | 4532 sc->bge_flowflags; 4533 } 4534 4535 static int 4536 bge_ifflags_cb(struct ethercom *ec) 4537 { 4538 struct ifnet *ifp = &ec->ec_if; 4539 struct bge_softc *sc = ifp->if_softc; 4540 int change = ifp->if_flags ^ sc->bge_if_flags; 4541 4542 if ((change & ~(IFF_CANTCHANGE|IFF_DEBUG)) != 0) 4543 return ENETRESET; 4544 else if ((change & (IFF_PROMISC | IFF_ALLMULTI)) == 0) 4545 return 0; 4546 4547 if ((ifp->if_flags & IFF_PROMISC) == 0) 4548 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 4549 else 4550 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 4551 4552 bge_setmulti(sc); 4553 4554 sc->bge_if_flags = ifp->if_flags; 4555 return 0; 4556 } 4557 4558 static int 4559 bge_ioctl(struct ifnet *ifp, u_long command, void *data) 4560 { 4561 struct bge_softc *sc = ifp->if_softc; 4562 struct ifreq *ifr = (struct ifreq *) data; 4563 int s, error = 0; 4564 struct mii_data *mii; 4565 4566 s = splnet(); 4567 4568 switch (command) { 4569 case SIOCSIFMEDIA: 4570 /* XXX Flow control is not supported for 1000BASE-SX */ 4571 if (sc->bge_flags & BGE_PHY_FIBER_TBI) { 4572 ifr->ifr_media &= ~IFM_ETH_FMASK; 4573 sc->bge_flowflags = 0; 4574 } 4575 4576 /* Flow control requires full-duplex mode. */ 4577 if (IFM_SUBTYPE(ifr->ifr_media) == IFM_AUTO || 4578 (ifr->ifr_media & IFM_FDX) == 0) { 4579 ifr->ifr_media &= ~IFM_ETH_FMASK; 4580 } 4581 if (IFM_SUBTYPE(ifr->ifr_media) != IFM_AUTO) { 4582 if ((ifr->ifr_media & IFM_ETH_FMASK) == IFM_FLOW) { 4583 /* We can do both TXPAUSE and RXPAUSE. */ 4584 ifr->ifr_media |= 4585 IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE; 4586 } 4587 sc->bge_flowflags = ifr->ifr_media & IFM_ETH_FMASK; 4588 } 4589 /* FALLTHROUGH */ 4590 case SIOCGIFMEDIA: 4591 if (sc->bge_flags & BGE_PHY_FIBER_TBI) { 4592 error = ifmedia_ioctl(ifp, ifr, &sc->bge_ifmedia, 4593 command); 4594 } else { 4595 mii = &sc->bge_mii; 4596 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, 4597 command); 4598 } 4599 break; 4600 default: 4601 if ((error = ether_ioctl(ifp, command, data)) != ENETRESET) 4602 break; 4603 4604 error = 0; 4605 4606 if (command != SIOCADDMULTI && command != SIOCDELMULTI) 4607 ; 4608 else if (ifp->if_flags & IFF_RUNNING) 4609 bge_setmulti(sc); 4610 break; 4611 } 4612 4613 splx(s); 4614 4615 return error; 4616 } 4617 4618 static void 4619 bge_watchdog(struct ifnet *ifp) 4620 { 4621 struct bge_softc *sc; 4622 4623 sc = ifp->if_softc; 4624 4625 aprint_error_dev(sc->bge_dev, "watchdog timeout -- resetting\n"); 4626 4627 ifp->if_flags &= ~IFF_RUNNING; 4628 bge_init(ifp); 4629 4630 ifp->if_oerrors++; 4631 } 4632 4633 static void 4634 bge_stop_block(struct bge_softc *sc, bus_addr_t reg, uint32_t bit) 4635 { 4636 int i; 4637 4638 BGE_CLRBIT(sc, reg, bit); 4639 4640 for (i = 0; i < 1000; i++) { 4641 if ((CSR_READ_4(sc, reg) & bit) == 0) 4642 return; 4643 delay(100); 4644 } 4645 4646 /* 4647 * Doesn't print only when the register is BGE_SRS_MODE. It occurs 4648 * on some environment (and once after boot?) 4649 */ 4650 if (reg != BGE_SRS_MODE) 4651 aprint_error_dev(sc->bge_dev, 4652 "block failed to stop: reg 0x%lx, bit 0x%08x\n", 4653 (u_long)reg, bit); 4654 } 4655 4656 /* 4657 * Stop the adapter and free any mbufs allocated to the 4658 * RX and TX lists. 4659 */ 4660 static void 4661 bge_stop(struct ifnet *ifp, int disable) 4662 { 4663 struct bge_softc *sc = ifp->if_softc; 4664 4665 callout_stop(&sc->bge_timeout); 4666 4667 /* 4668 * Tell firmware we're shutting down. 4669 */ 4670 bge_stop_fw(sc); 4671 bge_sig_pre_reset(sc, BGE_RESET_STOP); 4672 4673 /* Disable host interrupts. */ 4674 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); 4675 bge_writembx(sc, BGE_MBX_IRQ0_LO, 1); 4676 4677 /* 4678 * Disable all of the receiver blocks 4679 */ 4680 bge_stop_block(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE); 4681 bge_stop_block(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 4682 bge_stop_block(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 4683 if (BGE_IS_5700_FAMILY(sc)) 4684 bge_stop_block(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 4685 bge_stop_block(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE); 4686 bge_stop_block(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 4687 bge_stop_block(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE); 4688 4689 /* 4690 * Disable all of the transmit blocks 4691 */ 4692 bge_stop_block(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 4693 bge_stop_block(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 4694 bge_stop_block(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 4695 bge_stop_block(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE); 4696 bge_stop_block(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE); 4697 if (BGE_IS_5700_FAMILY(sc)) 4698 bge_stop_block(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 4699 bge_stop_block(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 4700 4701 /* 4702 * Shut down all of the memory managers and related 4703 * state machines. 4704 */ 4705 bge_stop_block(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE); 4706 bge_stop_block(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE); 4707 if (BGE_IS_5700_FAMILY(sc)) 4708 bge_stop_block(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 4709 4710 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 4711 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 4712 4713 if (BGE_IS_5700_FAMILY(sc)) { 4714 bge_stop_block(sc, BGE_BMAN_MODE, BGE_BMANMODE_ENABLE); 4715 bge_stop_block(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 4716 } 4717 4718 bge_reset(sc); 4719 bge_sig_legacy(sc, BGE_RESET_STOP); 4720 bge_sig_post_reset(sc, BGE_RESET_STOP); 4721 4722 /* 4723 * Keep the ASF firmware running if up. 4724 */ 4725 if (sc->bge_asf_mode & ASF_STACKUP) 4726 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 4727 else 4728 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 4729 4730 /* Free the RX lists. */ 4731 bge_free_rx_ring_std(sc); 4732 4733 /* Free jumbo RX list. */ 4734 if (BGE_IS_JUMBO_CAPABLE(sc)) 4735 bge_free_rx_ring_jumbo(sc); 4736 4737 /* Free TX buffers. */ 4738 bge_free_tx_ring(sc); 4739 4740 /* 4741 * Isolate/power down the PHY. 4742 */ 4743 if (!(sc->bge_flags & BGE_PHY_FIBER_TBI)) 4744 mii_down(&sc->bge_mii); 4745 4746 sc->bge_tx_saved_considx = BGE_TXCONS_UNSET; 4747 4748 /* Clear MAC's link state (PHY may still have link UP). */ 4749 BGE_STS_CLRBIT(sc, BGE_STS_LINK); 4750 4751 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 4752 } 4753 4754 static void 4755 bge_link_upd(struct bge_softc *sc) 4756 { 4757 struct ifnet *ifp = &sc->ethercom.ec_if; 4758 struct mii_data *mii = &sc->bge_mii; 4759 uint32_t status; 4760 int link; 4761 4762 /* Clear 'pending link event' flag */ 4763 BGE_STS_CLRBIT(sc, BGE_STS_LINK_EVT); 4764 4765 /* 4766 * Process link state changes. 4767 * Grrr. The link status word in the status block does 4768 * not work correctly on the BCM5700 rev AX and BX chips, 4769 * according to all available information. Hence, we have 4770 * to enable MII interrupts in order to properly obtain 4771 * async link changes. Unfortunately, this also means that 4772 * we have to read the MAC status register to detect link 4773 * changes, thereby adding an additional register access to 4774 * the interrupt handler. 4775 */ 4776 4777 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700) { 4778 status = CSR_READ_4(sc, BGE_MAC_STS); 4779 if (status & BGE_MACSTAT_MI_INTERRUPT) { 4780 mii_pollstat(mii); 4781 4782 if (!BGE_STS_BIT(sc, BGE_STS_LINK) && 4783 mii->mii_media_status & IFM_ACTIVE && 4784 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) 4785 BGE_STS_SETBIT(sc, BGE_STS_LINK); 4786 else if (BGE_STS_BIT(sc, BGE_STS_LINK) && 4787 (!(mii->mii_media_status & IFM_ACTIVE) || 4788 IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) 4789 BGE_STS_CLRBIT(sc, BGE_STS_LINK); 4790 4791 /* Clear the interrupt */ 4792 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, 4793 BGE_EVTENB_MI_INTERRUPT); 4794 bge_miibus_readreg(sc->bge_dev, 1, BRGPHY_MII_ISR); 4795 bge_miibus_writereg(sc->bge_dev, 1, BRGPHY_MII_IMR, 4796 BRGPHY_INTRS); 4797 } 4798 return; 4799 } 4800 4801 if (sc->bge_flags & BGE_PHY_FIBER_TBI) { 4802 status = CSR_READ_4(sc, BGE_MAC_STS); 4803 if (status & BGE_MACSTAT_TBI_PCS_SYNCHED) { 4804 if (!BGE_STS_BIT(sc, BGE_STS_LINK)) { 4805 BGE_STS_SETBIT(sc, BGE_STS_LINK); 4806 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) 4807 BGE_CLRBIT(sc, BGE_MAC_MODE, 4808 BGE_MACMODE_TBI_SEND_CFGS); 4809 CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF); 4810 if_link_state_change(ifp, LINK_STATE_UP); 4811 } 4812 } else if (BGE_STS_BIT(sc, BGE_STS_LINK)) { 4813 BGE_STS_CLRBIT(sc, BGE_STS_LINK); 4814 if_link_state_change(ifp, LINK_STATE_DOWN); 4815 } 4816 /* 4817 * Discard link events for MII/GMII cards if MI auto-polling disabled. 4818 * This should not happen since mii callouts are locked now, but 4819 * we keep this check for debug. 4820 */ 4821 } else if (BGE_STS_BIT(sc, BGE_STS_AUTOPOLL)) { 4822 /* 4823 * Some broken BCM chips have BGE_STATFLAG_LINKSTATE_CHANGED 4824 * bit in status word always set. Workaround this bug by 4825 * reading PHY link status directly. 4826 */ 4827 link = (CSR_READ_4(sc, BGE_MI_STS) & BGE_MISTS_LINK)? 4828 BGE_STS_LINK : 0; 4829 4830 if (BGE_STS_BIT(sc, BGE_STS_LINK) != link) { 4831 mii_pollstat(mii); 4832 4833 if (!BGE_STS_BIT(sc, BGE_STS_LINK) && 4834 mii->mii_media_status & IFM_ACTIVE && 4835 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) 4836 BGE_STS_SETBIT(sc, BGE_STS_LINK); 4837 else if (BGE_STS_BIT(sc, BGE_STS_LINK) && 4838 (!(mii->mii_media_status & IFM_ACTIVE) || 4839 IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) 4840 BGE_STS_CLRBIT(sc, BGE_STS_LINK); 4841 } 4842 } 4843 4844 /* Clear the attention */ 4845 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED| 4846 BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE| 4847 BGE_MACSTAT_LINK_CHANGED); 4848 } 4849 4850 static int 4851 bge_sysctl_verify(SYSCTLFN_ARGS) 4852 { 4853 int error, t; 4854 struct sysctlnode node; 4855 4856 node = *rnode; 4857 t = *(int*)rnode->sysctl_data; 4858 node.sysctl_data = &t; 4859 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 4860 if (error || newp == NULL) 4861 return error; 4862 4863 #if 0 4864 DPRINTF2(("%s: t = %d, nodenum = %d, rnodenum = %d\n", __func__, t, 4865 node.sysctl_num, rnode->sysctl_num)); 4866 #endif 4867 4868 if (node.sysctl_num == bge_rxthresh_nodenum) { 4869 if (t < 0 || t >= NBGE_RX_THRESH) 4870 return EINVAL; 4871 bge_update_all_threshes(t); 4872 } else 4873 return EINVAL; 4874 4875 *(int*)rnode->sysctl_data = t; 4876 4877 return 0; 4878 } 4879 4880 /* 4881 * Set up sysctl(3) MIB, hw.bge.*. 4882 */ 4883 static void 4884 bge_sysctl_init(struct bge_softc *sc) 4885 { 4886 int rc, bge_root_num; 4887 const struct sysctlnode *node; 4888 4889 if ((rc = sysctl_createv(&sc->bge_log, 0, NULL, NULL, 4890 CTLFLAG_PERMANENT, CTLTYPE_NODE, "hw", NULL, 4891 NULL, 0, NULL, 0, CTL_HW, CTL_EOL)) != 0) { 4892 goto out; 4893 } 4894 4895 if ((rc = sysctl_createv(&sc->bge_log, 0, NULL, &node, 4896 0, CTLTYPE_NODE, "bge", 4897 SYSCTL_DESCR("BGE interface controls"), 4898 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL)) != 0) { 4899 goto out; 4900 } 4901 4902 bge_root_num = node->sysctl_num; 4903 4904 /* BGE Rx interrupt mitigation level */ 4905 if ((rc = sysctl_createv(&sc->bge_log, 0, NULL, &node, 4906 CTLFLAG_READWRITE, 4907 CTLTYPE_INT, "rx_lvl", 4908 SYSCTL_DESCR("BGE receive interrupt mitigation level"), 4909 bge_sysctl_verify, 0, 4910 &bge_rx_thresh_lvl, 4911 0, CTL_HW, bge_root_num, CTL_CREATE, 4912 CTL_EOL)) != 0) { 4913 goto out; 4914 } 4915 4916 bge_rxthresh_nodenum = node->sysctl_num; 4917 4918 return; 4919 4920 out: 4921 aprint_error("%s: sysctl_createv failed (rc = %d)\n", __func__, rc); 4922 } 4923 4924 #ifdef BGE_DEBUG 4925 void 4926 bge_debug_info(struct bge_softc *sc) 4927 { 4928 4929 printf("Hardware Flags:\n"); 4930 if (BGE_IS_5755_PLUS(sc)) 4931 printf(" - 5755 Plus\n"); 4932 if (BGE_IS_575X_PLUS(sc)) 4933 printf(" - 575X Plus\n"); 4934 if (BGE_IS_5705_PLUS(sc)) 4935 printf(" - 5705 Plus\n"); 4936 if (BGE_IS_5714_FAMILY(sc)) 4937 printf(" - 5714 Family\n"); 4938 if (BGE_IS_5700_FAMILY(sc)) 4939 printf(" - 5700 Family\n"); 4940 if (sc->bge_flags & BGE_IS_5788) 4941 printf(" - 5788\n"); 4942 if (sc->bge_flags & BGE_JUMBO_CAPABLE) 4943 printf(" - Supports Jumbo Frames\n"); 4944 if (sc->bge_flags & BGE_NO_EEPROM) 4945 printf(" - No EEPROM\n"); 4946 if (sc->bge_flags & BGE_PCIX) 4947 printf(" - PCI-X Bus\n"); 4948 if (sc->bge_flags & BGE_PCIE) 4949 printf(" - PCI Express Bus\n"); 4950 if (sc->bge_flags & BGE_NO_3LED) 4951 printf(" - No 3 LEDs\n"); 4952 if (sc->bge_flags & BGE_RX_ALIGNBUG) 4953 printf(" - RX Alignment Bug\n"); 4954 if (sc->bge_flags & BGE_TSO) 4955 printf(" - TSO\n"); 4956 } 4957 #endif /* BGE_DEBUG */ 4958 4959 static int 4960 bge_get_eaddr_fw(struct bge_softc *sc, uint8_t ether_addr[]) 4961 { 4962 prop_dictionary_t dict; 4963 prop_data_t ea; 4964 4965 if ((sc->bge_flags & BGE_NO_EEPROM) == 0) 4966 return 1; 4967 4968 dict = device_properties(sc->bge_dev); 4969 ea = prop_dictionary_get(dict, "mac-address"); 4970 if (ea != NULL) { 4971 KASSERT(prop_object_type(ea) == PROP_TYPE_DATA); 4972 KASSERT(prop_data_size(ea) == ETHER_ADDR_LEN); 4973 memcpy(ether_addr, prop_data_data_nocopy(ea), ETHER_ADDR_LEN); 4974 return 0; 4975 } 4976 4977 return 1; 4978 } 4979 4980 static int 4981 bge_get_eaddr_mem(struct bge_softc *sc, uint8_t ether_addr[]) 4982 { 4983 uint32_t mac_addr; 4984 4985 mac_addr = bge_readmem_ind(sc, BGE_SRAM_MAC_ADDR_HIGH_MB); 4986 if ((mac_addr >> 16) == 0x484b) { 4987 ether_addr[0] = (uint8_t)(mac_addr >> 8); 4988 ether_addr[1] = (uint8_t)mac_addr; 4989 mac_addr = bge_readmem_ind(sc, BGE_SRAM_MAC_ADDR_LOW_MB); 4990 ether_addr[2] = (uint8_t)(mac_addr >> 24); 4991 ether_addr[3] = (uint8_t)(mac_addr >> 16); 4992 ether_addr[4] = (uint8_t)(mac_addr >> 8); 4993 ether_addr[5] = (uint8_t)mac_addr; 4994 return 0; 4995 } 4996 return 1; 4997 } 4998 4999 static int 5000 bge_get_eaddr_nvram(struct bge_softc *sc, uint8_t ether_addr[]) 5001 { 5002 int mac_offset = BGE_EE_MAC_OFFSET; 5003 5004 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 5005 mac_offset = BGE_EE_MAC_OFFSET_5906; 5006 5007 return (bge_read_nvram(sc, ether_addr, mac_offset + 2, 5008 ETHER_ADDR_LEN)); 5009 } 5010 5011 static int 5012 bge_get_eaddr_eeprom(struct bge_softc *sc, uint8_t ether_addr[]) 5013 { 5014 5015 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 5016 return 1; 5017 5018 return (bge_read_eeprom(sc, ether_addr, BGE_EE_MAC_OFFSET + 2, 5019 ETHER_ADDR_LEN)); 5020 } 5021 5022 static int 5023 bge_get_eaddr(struct bge_softc *sc, uint8_t eaddr[]) 5024 { 5025 static const bge_eaddr_fcn_t bge_eaddr_funcs[] = { 5026 /* NOTE: Order is critical */ 5027 bge_get_eaddr_fw, 5028 bge_get_eaddr_mem, 5029 bge_get_eaddr_nvram, 5030 bge_get_eaddr_eeprom, 5031 NULL 5032 }; 5033 const bge_eaddr_fcn_t *func; 5034 5035 for (func = bge_eaddr_funcs; *func != NULL; ++func) { 5036 if ((*func)(sc, eaddr) == 0) 5037 break; 5038 } 5039 return (*func == NULL ? ENXIO : 0); 5040 } 5041
Indexes created Tue Sep 23 13:09:54 GMT 2025