if_bge.c revision 1.21
1 /* $NetBSD: if_bge.c,v 1.21 2002/09/30 20:37:25 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 2001 Wind River Systems 5 * Copyright (c) 1997, 1998, 1999, 2001 6 * Bill Paul <wpaul (at) windriver.com>. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Bill Paul. 19 * 4. Neither the name of the author nor the names of any co-contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 33 * THE POSSIBILITY OF SUCH DAMAGE. 34 * 35 * $FreeBSD: if_bge.c,v 1.13 2002/04/04 06:01:31 wpaul Exp $ 36 */ 37 38 /* 39 * Broadcom BCM570x family gigabit ethernet driver for NetBSD. 40 * 41 * NetBSD version by: 42 * 43 * Frank van der Linden <fvdl (at) wasabisystems.com> 44 * Jason Thorpe <thorpej (at) wasabisystems.com> 45 * 46 * Originally written for FreeBSD by Bill Paul <wpaul (at) windriver.com> 47 * Senior Engineer, Wind River Systems 48 */ 49 50 /* 51 * The Broadcom BCM5700 is based on technology originally developed by 52 * Alteon Networks as part of the Tigon I and Tigon II gigabit ethernet 53 * MAC chips. The BCM5700, sometimes refered to as the Tigon III, has 54 * two on-board MIPS R4000 CPUs and can have as much as 16MB of external 55 * SSRAM. The BCM5700 supports TCP, UDP and IP checksum offload, jumbo 56 * frames, highly configurable RX filtering, and 16 RX and TX queues 57 * (which, along with RX filter rules, can be used for QOS applications). 58 * Other features, such as TCP segmentation, may be available as part 59 * of value-added firmware updates. Unlike the Tigon I and Tigon II, 60 * firmware images can be stored in hardware and need not be compiled 61 * into the driver. 62 * 63 * The BCM5700 supports the PCI v2.2 and PCI-X v1.0 standards, and will 64 * function in a 32-bit/64-bit 33/66Mhz bus, or a 64-bit/133Mhz bus. 65 * 66 * The BCM5701 is a single-chip solution incorporating both the BCM5700 67 * MAC and a BCM5401 10/100/1000 PHY. Unlike the BCM5700, the BCM5700 68 * does not support external SSRAM. 69 * 70 * Broadcom also produces a variation of the BCM5700 under the "Altima" 71 * brand name, which is functionally similar but lacks PCI-X support. 72 * 73 * Without external SSRAM, you can only have at most 4 TX rings, 74 * and the use of the mini RX ring is disabled. This seems to imply 75 * that these features are simply not available on the BCM5701. As a 76 * result, this driver does not implement any support for the mini RX 77 * ring. 78 */ 79 80 #include "bpfilter.h" 81 #include "vlan.h" 82 83 #include <sys/param.h> 84 #include <sys/systm.h> 85 #include <sys/callout.h> 86 #include <sys/sockio.h> 87 #include <sys/mbuf.h> 88 #include <sys/malloc.h> 89 #include <sys/kernel.h> 90 #include <sys/device.h> 91 #include <sys/socket.h> 92 93 #include <net/if.h> 94 #include <net/if_dl.h> 95 #include <net/if_media.h> 96 #include <net/if_ether.h> 97 98 #ifdef INET 99 #include <netinet/in.h> 100 #include <netinet/in_systm.h> 101 #include <netinet/in_var.h> 102 #include <netinet/ip.h> 103 #endif 104 105 #if NBPFILTER > 0 106 #include <net/bpf.h> 107 #endif 108 109 #include <dev/pci/pcireg.h> 110 #include <dev/pci/pcivar.h> 111 #include <dev/pci/pcidevs.h> 112 113 #include <dev/mii/mii.h> 114 #include <dev/mii/miivar.h> 115 #include <dev/mii/miidevs.h> 116 #include <dev/mii/brgphyreg.h> 117 118 #include <dev/pci/if_bgereg.h> 119 120 #include <uvm/uvm_extern.h> 121 122 int bge_probe(struct device *, struct cfdata *, void *); 123 void bge_attach(struct device *, struct device *, void *); 124 void bge_release_resources(struct bge_softc *); 125 void bge_txeof(struct bge_softc *); 126 void bge_rxeof(struct bge_softc *); 127 128 void bge_tick(void *); 129 void bge_stats_update(struct bge_softc *); 130 int bge_encap(struct bge_softc *, struct mbuf *, u_int32_t *); 131 132 int bge_intr(void *); 133 void bge_start(struct ifnet *); 134 int bge_ioctl(struct ifnet *, u_long, caddr_t); 135 int bge_init(struct ifnet *); 136 void bge_stop(struct bge_softc *); 137 void bge_watchdog(struct ifnet *); 138 void bge_shutdown(void *); 139 int bge_ifmedia_upd(struct ifnet *); 140 void bge_ifmedia_sts(struct ifnet *, struct ifmediareq *); 141 142 u_int8_t bge_eeprom_getbyte(struct bge_softc *, int, u_int8_t *); 143 int bge_read_eeprom(struct bge_softc *, caddr_t, int, int); 144 145 void bge_setmulti(struct bge_softc *); 146 147 void bge_handle_events(struct bge_softc *); 148 int bge_alloc_jumbo_mem(struct bge_softc *); 149 void bge_free_jumbo_mem(struct bge_softc *); 150 void *bge_jalloc(struct bge_softc *); 151 void bge_jfree(struct mbuf *, caddr_t, u_int, void *); 152 int bge_newbuf_std(struct bge_softc *, int, struct mbuf *, bus_dmamap_t); 153 int bge_newbuf_jumbo(struct bge_softc *, int, struct mbuf *); 154 int bge_init_rx_ring_std(struct bge_softc *); 155 void bge_free_rx_ring_std(struct bge_softc *); 156 int bge_init_rx_ring_jumbo(struct bge_softc *); 157 void bge_free_rx_ring_jumbo(struct bge_softc *); 158 void bge_free_tx_ring(struct bge_softc *); 159 int bge_init_tx_ring(struct bge_softc *); 160 161 int bge_chipinit(struct bge_softc *); 162 int bge_blockinit(struct bge_softc *); 163 164 #ifdef notdef 165 u_int8_t bge_vpd_readbyte(struct bge_softc *, int); 166 void bge_vpd_read_res(struct bge_softc *, struct vpd_res *, int); 167 void bge_vpd_read(struct bge_softc *); 168 #endif 169 170 u_int32_t bge_readmem_ind(struct bge_softc *, int); 171 void bge_writemem_ind(struct bge_softc *, int, int); 172 #ifdef notdef 173 u_int32_t bge_readreg_ind(struct bge_softc *, int); 174 #endif 175 void bge_writereg_ind(struct bge_softc *, int, int); 176 177 int bge_miibus_readreg(struct device *, int, int); 178 void bge_miibus_writereg(struct device *, int, int, int); 179 void bge_miibus_statchg(struct device *); 180 181 void bge_reset(struct bge_softc *); 182 183 void bge_dump_status(struct bge_softc *); 184 void bge_dump_rxbd(struct bge_rx_bd *); 185 186 #define BGE_DEBUG 187 #ifdef BGE_DEBUG 188 #define DPRINTF(x) if (bgedebug) printf x 189 #define DPRINTFN(n,x) if (bgedebug >= (n)) printf x 190 int bgedebug = 0; 191 #else 192 #define DPRINTF(x) 193 #define DPRINTFN(n,x) 194 #endif 195 196 /* Various chip quirks. */ 197 #define BGE_QUIRK_LINK_STATE_BROKEN 0x00000001 198 #define BGE_QUIRK_CSUM_BROKEN 0x00000002 199 200 CFATTACH_DECL(bge, sizeof(struct bge_softc), 201 bge_probe, bge_attach, NULL, NULL) 202 203 u_int32_t 204 bge_readmem_ind(sc, off) 205 struct bge_softc *sc; 206 int off; 207 { 208 struct pci_attach_args *pa = &(sc->bge_pa); 209 pcireg_t val; 210 211 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_MEMWIN_BASEADDR, off); 212 val = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_MEMWIN_DATA); 213 return val; 214 } 215 216 void 217 bge_writemem_ind(sc, off, val) 218 struct bge_softc *sc; 219 int off, val; 220 { 221 struct pci_attach_args *pa = &(sc->bge_pa); 222 223 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_MEMWIN_BASEADDR, off); 224 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_MEMWIN_DATA, val); 225 } 226 227 #ifdef notdef 228 u_int32_t 229 bge_readreg_ind(sc, off) 230 struct bge_softc *sc; 231 int off; 232 { 233 struct pci_attach_args *pa = &(sc->bge_pa); 234 235 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_REG_BASEADDR, off); 236 return(pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_REG_DATA)); 237 } 238 #endif 239 240 void 241 bge_writereg_ind(sc, off, val) 242 struct bge_softc *sc; 243 int off, val; 244 { 245 struct pci_attach_args *pa = &(sc->bge_pa); 246 247 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_REG_BASEADDR, off); 248 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_REG_DATA, val); 249 } 250 251 #ifdef notdef 252 u_int8_t 253 bge_vpd_readbyte(sc, addr) 254 struct bge_softc *sc; 255 int addr; 256 { 257 int i; 258 u_int32_t val; 259 struct pci_attach_args *pa = &(sc->bge_pa); 260 261 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_VPD_ADDR, addr); 262 for (i = 0; i < BGE_TIMEOUT * 10; i++) { 263 DELAY(10); 264 if (pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_VPD_ADDR) & 265 BGE_VPD_FLAG) 266 break; 267 } 268 269 if (i == BGE_TIMEOUT) { 270 printf("%s: VPD read timed out\n", sc->bge_dev.dv_xname); 271 return(0); 272 } 273 274 val = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_VPD_DATA); 275 276 return((val >> ((addr % 4) * 8)) & 0xFF); 277 } 278 279 void 280 bge_vpd_read_res(sc, res, addr) 281 struct bge_softc *sc; 282 struct vpd_res *res; 283 int addr; 284 { 285 int i; 286 u_int8_t *ptr; 287 288 ptr = (u_int8_t *)res; 289 for (i = 0; i < sizeof(struct vpd_res); i++) 290 ptr[i] = bge_vpd_readbyte(sc, i + addr); 291 } 292 293 void 294 bge_vpd_read(sc) 295 struct bge_softc *sc; 296 { 297 int pos = 0, i; 298 struct vpd_res res; 299 300 if (sc->bge_vpd_prodname != NULL) 301 free(sc->bge_vpd_prodname, M_DEVBUF); 302 if (sc->bge_vpd_readonly != NULL) 303 free(sc->bge_vpd_readonly, M_DEVBUF); 304 sc->bge_vpd_prodname = NULL; 305 sc->bge_vpd_readonly = NULL; 306 307 bge_vpd_read_res(sc, &res, pos); 308 309 if (res.vr_id != VPD_RES_ID) { 310 printf("%s: bad VPD resource id: expected %x got %x\n", 311 sc->bge_dev.dv_xname, VPD_RES_ID, res.vr_id); 312 return; 313 } 314 315 pos += sizeof(res); 316 sc->bge_vpd_prodname = malloc(res.vr_len + 1, M_DEVBUF, M_NOWAIT); 317 if (sc->bge_vpd_prodname == NULL) 318 panic("bge_vpd_read"); 319 for (i = 0; i < res.vr_len; i++) 320 sc->bge_vpd_prodname[i] = bge_vpd_readbyte(sc, i + pos); 321 sc->bge_vpd_prodname[i] = '\0'; 322 pos += i; 323 324 bge_vpd_read_res(sc, &res, pos); 325 326 if (res.vr_id != VPD_RES_READ) { 327 printf("%s: bad VPD resource id: expected %x got %x\n", 328 sc->bge_dev.dv_xname, VPD_RES_READ, res.vr_id); 329 return; 330 } 331 332 pos += sizeof(res); 333 sc->bge_vpd_readonly = malloc(res.vr_len, M_DEVBUF, M_NOWAIT); 334 if (sc->bge_vpd_readonly == NULL) 335 panic("bge_vpd_read"); 336 for (i = 0; i < res.vr_len + 1; i++) 337 sc->bge_vpd_readonly[i] = bge_vpd_readbyte(sc, i + pos); 338 } 339 #endif 340 341 /* 342 * Read a byte of data stored in the EEPROM at address 'addr.' The 343 * BCM570x supports both the traditional bitbang interface and an 344 * auto access interface for reading the EEPROM. We use the auto 345 * access method. 346 */ 347 u_int8_t 348 bge_eeprom_getbyte(sc, addr, dest) 349 struct bge_softc *sc; 350 int addr; 351 u_int8_t *dest; 352 { 353 int i; 354 u_int32_t byte = 0; 355 356 /* 357 * Enable use of auto EEPROM access so we can avoid 358 * having to use the bitbang method. 359 */ 360 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM); 361 362 /* Reset the EEPROM, load the clock period. */ 363 CSR_WRITE_4(sc, BGE_EE_ADDR, 364 BGE_EEADDR_RESET|BGE_EEHALFCLK(BGE_HALFCLK_384SCL)); 365 DELAY(20); 366 367 /* Issue the read EEPROM command. */ 368 CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr); 369 370 /* Wait for completion */ 371 for(i = 0; i < BGE_TIMEOUT * 10; i++) { 372 DELAY(10); 373 if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE) 374 break; 375 } 376 377 if (i == BGE_TIMEOUT) { 378 printf("%s: eeprom read timed out\n", sc->bge_dev.dv_xname); 379 return(0); 380 } 381 382 /* Get result. */ 383 byte = CSR_READ_4(sc, BGE_EE_DATA); 384 385 *dest = (byte >> ((addr % 4) * 8)) & 0xFF; 386 387 return(0); 388 } 389 390 /* 391 * Read a sequence of bytes from the EEPROM. 392 */ 393 int 394 bge_read_eeprom(sc, dest, off, cnt) 395 struct bge_softc *sc; 396 caddr_t dest; 397 int off; 398 int cnt; 399 { 400 int err = 0, i; 401 u_int8_t byte = 0; 402 403 for (i = 0; i < cnt; i++) { 404 err = bge_eeprom_getbyte(sc, off + i, &byte); 405 if (err) 406 break; 407 *(dest + i) = byte; 408 } 409 410 return(err ? 1 : 0); 411 } 412 413 int 414 bge_miibus_readreg(dev, phy, reg) 415 struct device *dev; 416 int phy, reg; 417 { 418 struct bge_softc *sc = (struct bge_softc *)dev; 419 struct ifnet *ifp; 420 u_int32_t val; 421 int i; 422 423 ifp = &sc->ethercom.ec_if; 424 425 if (sc->bge_asicrev == BGE_ASICREV_BCM5701_B5 && phy != 1) 426 return(0); 427 428 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_READ|BGE_MICOMM_BUSY| 429 BGE_MIPHY(phy)|BGE_MIREG(reg)); 430 431 for (i = 0; i < BGE_TIMEOUT; i++) { 432 val = CSR_READ_4(sc, BGE_MI_COMM); 433 if (!(val & BGE_MICOMM_BUSY)) 434 break; 435 delay(10); 436 } 437 438 if (i == BGE_TIMEOUT) { 439 printf("%s: PHY read timed out\n", sc->bge_dev.dv_xname); 440 return(0); 441 } 442 443 val = CSR_READ_4(sc, BGE_MI_COMM); 444 445 if (val & BGE_MICOMM_READFAIL) 446 return(0); 447 448 return(val & 0xFFFF); 449 } 450 451 void 452 bge_miibus_writereg(dev, phy, reg, val) 453 struct device *dev; 454 int phy, reg, val; 455 { 456 struct bge_softc *sc = (struct bge_softc *)dev; 457 int i; 458 459 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_WRITE|BGE_MICOMM_BUSY| 460 BGE_MIPHY(phy)|BGE_MIREG(reg)|val); 461 462 for (i = 0; i < BGE_TIMEOUT; i++) { 463 if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY)) 464 break; 465 delay(10); 466 } 467 468 if (i == BGE_TIMEOUT) { 469 printf("%s: PHY read timed out\n", sc->bge_dev.dv_xname); 470 } 471 } 472 473 void 474 bge_miibus_statchg(dev) 475 struct device *dev; 476 { 477 struct bge_softc *sc = (struct bge_softc *)dev; 478 struct mii_data *mii = &sc->bge_mii; 479 480 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_PORTMODE); 481 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) { 482 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_GMII); 483 } else { 484 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_MII); 485 } 486 487 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 488 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX); 489 } else { 490 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX); 491 } 492 } 493 494 /* 495 * Handle events that have triggered interrupts. 496 */ 497 void 498 bge_handle_events(sc) 499 struct bge_softc *sc; 500 { 501 502 return; 503 } 504 505 /* 506 * Memory management for jumbo frames. 507 */ 508 509 int 510 bge_alloc_jumbo_mem(sc) 511 struct bge_softc *sc; 512 { 513 caddr_t ptr, kva; 514 bus_dma_segment_t seg; 515 int i, rseg, state, error; 516 struct bge_jpool_entry *entry; 517 518 state = error = 0; 519 520 /* Grab a big chunk o' storage. */ 521 if (bus_dmamem_alloc(sc->bge_dmatag, BGE_JMEM, PAGE_SIZE, 0, 522 &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 523 printf("%s: can't alloc rx buffers\n", sc->bge_dev.dv_xname); 524 return ENOBUFS; 525 } 526 527 state = 1; 528 if (bus_dmamem_map(sc->bge_dmatag, &seg, rseg, BGE_JMEM, &kva, 529 BUS_DMA_NOWAIT)) { 530 printf("%s: can't map dma buffers (%d bytes)\n", 531 sc->bge_dev.dv_xname, (int)BGE_JMEM); 532 error = ENOBUFS; 533 goto out; 534 } 535 536 state = 2; 537 if (bus_dmamap_create(sc->bge_dmatag, BGE_JMEM, 1, BGE_JMEM, 0, 538 BUS_DMA_NOWAIT, &sc->bge_cdata.bge_rx_jumbo_map)) { 539 printf("%s: can't create dma map\n", sc->bge_dev.dv_xname); 540 error = ENOBUFS; 541 goto out; 542 } 543 544 state = 3; 545 if (bus_dmamap_load(sc->bge_dmatag, sc->bge_cdata.bge_rx_jumbo_map, 546 kva, BGE_JMEM, NULL, BUS_DMA_NOWAIT)) { 547 printf("%s: can't load dma map\n", sc->bge_dev.dv_xname); 548 error = ENOBUFS; 549 goto out; 550 } 551 552 state = 4; 553 sc->bge_cdata.bge_jumbo_buf = (caddr_t)kva; 554 DPRINTFN(1,("bge_jumbo_buf = 0x%p\n", sc->bge_cdata.bge_jumbo_buf)); 555 556 SLIST_INIT(&sc->bge_jfree_listhead); 557 SLIST_INIT(&sc->bge_jinuse_listhead); 558 559 /* 560 * Now divide it up into 9K pieces and save the addresses 561 * in an array. 562 */ 563 ptr = sc->bge_cdata.bge_jumbo_buf; 564 for (i = 0; i < BGE_JSLOTS; i++) { 565 sc->bge_cdata.bge_jslots[i] = ptr; 566 ptr += BGE_JLEN; 567 entry = malloc(sizeof(struct bge_jpool_entry), 568 M_DEVBUF, M_NOWAIT); 569 if (entry == NULL) { 570 printf("%s: no memory for jumbo buffer queue!\n", 571 sc->bge_dev.dv_xname); 572 error = ENOBUFS; 573 goto out; 574 } 575 entry->slot = i; 576 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, 577 entry, jpool_entries); 578 } 579 out: 580 if (error != 0) { 581 switch (state) { 582 case 4: 583 bus_dmamap_unload(sc->bge_dmatag, 584 sc->bge_cdata.bge_rx_jumbo_map); 585 case 3: 586 bus_dmamap_destroy(sc->bge_dmatag, 587 sc->bge_cdata.bge_rx_jumbo_map); 588 case 2: 589 bus_dmamem_unmap(sc->bge_dmatag, kva, BGE_JMEM); 590 case 1: 591 bus_dmamem_free(sc->bge_dmatag, &seg, rseg); 592 break; 593 default: 594 break; 595 } 596 } 597 598 return error; 599 } 600 601 /* 602 * Allocate a jumbo buffer. 603 */ 604 void * 605 bge_jalloc(sc) 606 struct bge_softc *sc; 607 { 608 struct bge_jpool_entry *entry; 609 610 entry = SLIST_FIRST(&sc->bge_jfree_listhead); 611 612 if (entry == NULL) { 613 printf("%s: no free jumbo buffers\n", sc->bge_dev.dv_xname); 614 return(NULL); 615 } 616 617 SLIST_REMOVE_HEAD(&sc->bge_jfree_listhead, jpool_entries); 618 SLIST_INSERT_HEAD(&sc->bge_jinuse_listhead, entry, jpool_entries); 619 return(sc->bge_cdata.bge_jslots[entry->slot]); 620 } 621 622 /* 623 * Release a jumbo buffer. 624 */ 625 void 626 bge_jfree(m, buf, size, arg) 627 struct mbuf *m; 628 caddr_t buf; 629 u_int size; 630 void *arg; 631 { 632 struct bge_jpool_entry *entry; 633 struct bge_softc *sc; 634 int i, s; 635 636 /* Extract the softc struct pointer. */ 637 sc = (struct bge_softc *)arg; 638 639 if (sc == NULL) 640 panic("bge_jfree: can't find softc pointer!"); 641 642 /* calculate the slot this buffer belongs to */ 643 644 i = ((caddr_t)buf 645 - (caddr_t)sc->bge_cdata.bge_jumbo_buf) / BGE_JLEN; 646 647 if ((i < 0) || (i >= BGE_JSLOTS)) 648 panic("bge_jfree: asked to free buffer that we don't manage!"); 649 650 s = splvm(); 651 entry = SLIST_FIRST(&sc->bge_jinuse_listhead); 652 if (entry == NULL) 653 panic("bge_jfree: buffer not in use!"); 654 entry->slot = i; 655 SLIST_REMOVE_HEAD(&sc->bge_jinuse_listhead, jpool_entries); 656 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, entry, jpool_entries); 657 658 if (__predict_true(m != NULL)) 659 pool_cache_put(&mbpool_cache, m); 660 splx(s); 661 } 662 663 664 /* 665 * Intialize a standard receive ring descriptor. 666 */ 667 int 668 bge_newbuf_std(sc, i, m, dmamap) 669 struct bge_softc *sc; 670 int i; 671 struct mbuf *m; 672 bus_dmamap_t dmamap; 673 { 674 struct mbuf *m_new = NULL; 675 struct bge_rx_bd *r; 676 int error; 677 678 if (dmamap == NULL) { 679 error = bus_dmamap_create(sc->bge_dmatag, MCLBYTES, 1, 680 MCLBYTES, 0, BUS_DMA_NOWAIT, &dmamap); 681 if (error != 0) 682 return error; 683 } 684 685 sc->bge_cdata.bge_rx_std_map[i] = dmamap; 686 687 if (m == NULL) { 688 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 689 if (m_new == NULL) { 690 return(ENOBUFS); 691 } 692 693 MCLGET(m_new, M_DONTWAIT); 694 if (!(m_new->m_flags & M_EXT)) { 695 m_freem(m_new); 696 return(ENOBUFS); 697 } 698 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 699 m_adj(m_new, ETHER_ALIGN); 700 701 if (bus_dmamap_load_mbuf(sc->bge_dmatag, dmamap, m_new, 702 BUS_DMA_READ|BUS_DMA_NOWAIT)) 703 return(ENOBUFS); 704 } else { 705 m_new = m; 706 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 707 m_new->m_data = m_new->m_ext.ext_buf; 708 m_adj(m_new, ETHER_ALIGN); 709 } 710 711 sc->bge_cdata.bge_rx_std_chain[i] = m_new; 712 r = &sc->bge_rdata->bge_rx_std_ring[i]; 713 bge_set_hostaddr(&r->bge_addr, 714 dmamap->dm_segs[0].ds_addr); 715 r->bge_flags = BGE_RXBDFLAG_END; 716 r->bge_len = m_new->m_len; 717 r->bge_idx = i; 718 719 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 720 offsetof(struct bge_ring_data, bge_rx_std_ring) + 721 i * sizeof (struct bge_rx_bd), 722 sizeof (struct bge_rx_bd), 723 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 724 725 return(0); 726 } 727 728 /* 729 * Initialize a jumbo receive ring descriptor. This allocates 730 * a jumbo buffer from the pool managed internally by the driver. 731 */ 732 int 733 bge_newbuf_jumbo(sc, i, m) 734 struct bge_softc *sc; 735 int i; 736 struct mbuf *m; 737 { 738 struct mbuf *m_new = NULL; 739 struct bge_rx_bd *r; 740 741 if (m == NULL) { 742 caddr_t *buf = NULL; 743 744 /* Allocate the mbuf. */ 745 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 746 if (m_new == NULL) { 747 return(ENOBUFS); 748 } 749 750 /* Allocate the jumbo buffer */ 751 buf = bge_jalloc(sc); 752 if (buf == NULL) { 753 m_freem(m_new); 754 printf("%s: jumbo allocation failed " 755 "-- packet dropped!\n", sc->bge_dev.dv_xname); 756 return(ENOBUFS); 757 } 758 759 /* Attach the buffer to the mbuf. */ 760 m_new->m_len = m_new->m_pkthdr.len = BGE_JUMBO_FRAMELEN; 761 MEXTADD(m_new, buf, BGE_JUMBO_FRAMELEN, M_DEVBUF, 762 bge_jfree, sc); 763 } else { 764 m_new = m; 765 m_new->m_data = m_new->m_ext.ext_buf; 766 m_new->m_ext.ext_size = BGE_JUMBO_FRAMELEN; 767 } 768 769 m_adj(m_new, ETHER_ALIGN); 770 /* Set up the descriptor. */ 771 r = &sc->bge_rdata->bge_rx_jumbo_ring[i]; 772 sc->bge_cdata.bge_rx_jumbo_chain[i] = m_new; 773 bge_set_hostaddr(&r->bge_addr, BGE_JUMBO_DMA_ADDR(sc, m_new)); 774 r->bge_flags = BGE_RXBDFLAG_END|BGE_RXBDFLAG_JUMBO_RING; 775 r->bge_len = m_new->m_len; 776 r->bge_idx = i; 777 778 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 779 offsetof(struct bge_ring_data, bge_rx_jumbo_ring) + 780 i * sizeof (struct bge_rx_bd), 781 sizeof (struct bge_rx_bd), 782 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 783 784 return(0); 785 } 786 787 /* 788 * The standard receive ring has 512 entries in it. At 2K per mbuf cluster, 789 * that's 1MB or memory, which is a lot. For now, we fill only the first 790 * 256 ring entries and hope that our CPU is fast enough to keep up with 791 * the NIC. 792 */ 793 int 794 bge_init_rx_ring_std(sc) 795 struct bge_softc *sc; 796 { 797 int i; 798 799 if (sc->bge_flags & BGE_RXRING_VALID) 800 return 0; 801 802 for (i = 0; i < BGE_SSLOTS; i++) { 803 if (bge_newbuf_std(sc, i, NULL, 0) == ENOBUFS) 804 return(ENOBUFS); 805 } 806 807 sc->bge_std = i - 1; 808 CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std); 809 810 sc->bge_flags |= BGE_RXRING_VALID; 811 812 return(0); 813 } 814 815 void 816 bge_free_rx_ring_std(sc) 817 struct bge_softc *sc; 818 { 819 int i; 820 821 if (!(sc->bge_flags & BGE_RXRING_VALID)) 822 return; 823 824 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { 825 if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) { 826 m_freem(sc->bge_cdata.bge_rx_std_chain[i]); 827 sc->bge_cdata.bge_rx_std_chain[i] = NULL; 828 bus_dmamap_destroy(sc->bge_dmatag, 829 sc->bge_cdata.bge_rx_std_map[i]); 830 } 831 memset((char *)&sc->bge_rdata->bge_rx_std_ring[i], 0, 832 sizeof(struct bge_rx_bd)); 833 } 834 835 sc->bge_flags &= ~BGE_RXRING_VALID; 836 } 837 838 int 839 bge_init_rx_ring_jumbo(sc) 840 struct bge_softc *sc; 841 { 842 int i; 843 struct bge_rcb *rcb; 844 struct bge_rcb_opaque *rcbo; 845 846 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 847 if (bge_newbuf_jumbo(sc, i, NULL) == ENOBUFS) 848 return(ENOBUFS); 849 }; 850 851 sc->bge_jumbo = i - 1; 852 853 rcb = &sc->bge_rdata->bge_info.bge_jumbo_rx_rcb; 854 rcbo = (struct bge_rcb_opaque *)rcb; 855 rcb->bge_flags = 0; 856 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcbo->bge_reg2); 857 858 CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo); 859 860 return(0); 861 } 862 863 void 864 bge_free_rx_ring_jumbo(sc) 865 struct bge_softc *sc; 866 { 867 int i; 868 869 if (!(sc->bge_flags & BGE_JUMBO_RXRING_VALID)) 870 return; 871 872 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 873 if (sc->bge_cdata.bge_rx_jumbo_chain[i] != NULL) { 874 m_freem(sc->bge_cdata.bge_rx_jumbo_chain[i]); 875 sc->bge_cdata.bge_rx_jumbo_chain[i] = NULL; 876 } 877 memset((char *)&sc->bge_rdata->bge_rx_jumbo_ring[i], 0, 878 sizeof(struct bge_rx_bd)); 879 } 880 881 sc->bge_flags &= ~BGE_JUMBO_RXRING_VALID; 882 } 883 884 void 885 bge_free_tx_ring(sc) 886 struct bge_softc *sc; 887 { 888 int i, freed; 889 struct txdmamap_pool_entry *dma; 890 891 if (!(sc->bge_flags & BGE_TXRING_VALID)) 892 return; 893 894 freed = 0; 895 896 for (i = 0; i < BGE_TX_RING_CNT; i++) { 897 if (sc->bge_cdata.bge_tx_chain[i] != NULL) { 898 freed++; 899 m_freem(sc->bge_cdata.bge_tx_chain[i]); 900 sc->bge_cdata.bge_tx_chain[i] = NULL; 901 SLIST_INSERT_HEAD(&sc->txdma_list, sc->txdma[i], 902 link); 903 sc->txdma[i] = 0; 904 } 905 memset((char *)&sc->bge_rdata->bge_tx_ring[i], 0, 906 sizeof(struct bge_tx_bd)); 907 } 908 909 while ((dma = SLIST_FIRST(&sc->txdma_list))) { 910 SLIST_REMOVE_HEAD(&sc->txdma_list, link); 911 bus_dmamap_destroy(sc->bge_dmatag, dma->dmamap); 912 free(dma, M_DEVBUF); 913 } 914 915 sc->bge_flags &= ~BGE_TXRING_VALID; 916 } 917 918 int 919 bge_init_tx_ring(sc) 920 struct bge_softc *sc; 921 { 922 int i; 923 bus_dmamap_t dmamap; 924 struct txdmamap_pool_entry *dma; 925 926 if (sc->bge_flags & BGE_TXRING_VALID) 927 return 0; 928 929 sc->bge_txcnt = 0; 930 sc->bge_tx_saved_considx = 0; 931 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, 0); 932 CSR_WRITE_4(sc, BGE_MBX_TX_NIC_PROD0_LO, 0); 933 934 SLIST_INIT(&sc->txdma_list); 935 for (i = 0; i < BGE_RSLOTS; i++) { 936 if (bus_dmamap_create(sc->bge_dmatag, ETHER_MAX_LEN_JUMBO, 937 BGE_NTXSEG, ETHER_MAX_LEN_JUMBO, 0, BUS_DMA_NOWAIT, 938 &dmamap)) 939 return(ENOBUFS); 940 if (dmamap == NULL) 941 panic("dmamap NULL in bge_init_tx_ring"); 942 dma = malloc(sizeof(*dma), M_DEVBUF, M_NOWAIT); 943 if (dma == NULL) { 944 printf("%s: can't alloc txdmamap_pool_entry\n", 945 sc->bge_dev.dv_xname); 946 bus_dmamap_destroy(sc->bge_dmatag, dmamap); 947 return (ENOMEM); 948 } 949 dma->dmamap = dmamap; 950 SLIST_INSERT_HEAD(&sc->txdma_list, dma, link); 951 } 952 953 sc->bge_flags |= BGE_TXRING_VALID; 954 955 return(0); 956 } 957 958 void 959 bge_setmulti(sc) 960 struct bge_softc *sc; 961 { 962 struct ethercom *ac = &sc->ethercom; 963 struct ifnet *ifp = &ac->ec_if; 964 struct ether_multi *enm; 965 struct ether_multistep step; 966 u_int32_t hashes[4] = { 0, 0, 0, 0 }; 967 u_int32_t h; 968 int i; 969 970 if (ifp->if_flags & IFF_PROMISC) 971 goto allmulti; 972 973 /* Now program new ones. */ 974 ETHER_FIRST_MULTI(step, ac, enm); 975 while (enm != NULL) { 976 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 977 /* 978 * We must listen to a range of multicast addresses. 979 * For now, just accept all multicasts, rather than 980 * trying to set only those filter bits needed to match 981 * the range. (At this time, the only use of address 982 * ranges is for IP multicast routing, for which the 983 * range is big enough to require all bits set.) 984 */ 985 goto allmulti; 986 } 987 988 h = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN); 989 990 /* Just want the 7 least-significant bits. */ 991 h &= 0x7f; 992 993 hashes[(h & 0x60) >> 5] |= 1 << (h & 0x1F); 994 ETHER_NEXT_MULTI(step, enm); 995 } 996 997 ifp->if_flags &= ~IFF_ALLMULTI; 998 goto setit; 999 1000 allmulti: 1001 ifp->if_flags |= IFF_ALLMULTI; 1002 hashes[0] = hashes[1] = hashes[2] = hashes[3] = 0xffffffff; 1003 1004 setit: 1005 for (i = 0; i < 4; i++) 1006 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]); 1007 } 1008 1009 int bge_swapbits[] = { 1010 0, 1011 BGE_MODECTL_BYTESWAP_DATA, 1012 BGE_MODECTL_WORDSWAP_DATA, 1013 BGE_MODECTL_BYTESWAP_NONFRAME, 1014 BGE_MODECTL_WORDSWAP_NONFRAME, 1015 1016 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA, 1017 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_BYTESWAP_NONFRAME, 1018 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_NONFRAME, 1019 1020 BGE_MODECTL_WORDSWAP_DATA|BGE_MODECTL_BYTESWAP_NONFRAME, 1021 BGE_MODECTL_WORDSWAP_DATA|BGE_MODECTL_WORDSWAP_NONFRAME, 1022 1023 BGE_MODECTL_BYTESWAP_NONFRAME|BGE_MODECTL_WORDSWAP_NONFRAME, 1024 1025 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA| 1026 BGE_MODECTL_BYTESWAP_NONFRAME, 1027 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA| 1028 BGE_MODECTL_WORDSWAP_NONFRAME, 1029 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_BYTESWAP_NONFRAME| 1030 BGE_MODECTL_WORDSWAP_NONFRAME, 1031 BGE_MODECTL_WORDSWAP_DATA|BGE_MODECTL_BYTESWAP_NONFRAME| 1032 BGE_MODECTL_WORDSWAP_NONFRAME, 1033 1034 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA| 1035 BGE_MODECTL_BYTESWAP_NONFRAME|BGE_MODECTL_WORDSWAP_NONFRAME, 1036 }; 1037 1038 int bge_swapindex = 0; 1039 1040 /* 1041 * Do endian, PCI and DMA initialization. Also check the on-board ROM 1042 * self-test results. 1043 */ 1044 int 1045 bge_chipinit(sc) 1046 struct bge_softc *sc; 1047 { 1048 u_int32_t cachesize; 1049 int i; 1050 struct pci_attach_args *pa = &(sc->bge_pa); 1051 1052 1053 /* Set endianness before we access any non-PCI registers. */ 1054 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_MISC_CTL, 1055 BGE_INIT); 1056 1057 /* 1058 * Check the 'ROM failed' bit on the RX CPU to see if 1059 * self-tests passed. 1060 */ 1061 if (CSR_READ_4(sc, BGE_RXCPU_MODE) & BGE_RXCPUMODE_ROMFAIL) { 1062 printf("%s: RX CPU self-diagnostics failed!\n", 1063 sc->bge_dev.dv_xname); 1064 return(ENODEV); 1065 } 1066 1067 /* Clear the MAC control register */ 1068 CSR_WRITE_4(sc, BGE_MAC_MODE, 0); 1069 1070 /* 1071 * Clear the MAC statistics block in the NIC's 1072 * internal memory. 1073 */ 1074 for (i = BGE_STATS_BLOCK; 1075 i < BGE_STATS_BLOCK_END + 1; i += sizeof(u_int32_t)) 1076 BGE_MEMWIN_WRITE(pa->pa_pc, pa->pa_tag, i, 0); 1077 1078 for (i = BGE_STATUS_BLOCK; 1079 i < BGE_STATUS_BLOCK_END + 1; i += sizeof(u_int32_t)) 1080 BGE_MEMWIN_WRITE(pa->pa_pc, pa->pa_tag, i, 0); 1081 1082 /* Set up the PCI DMA control register. */ 1083 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_DMA_RW_CTL, 1084 BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD|0x0F); 1085 1086 /* 1087 * Set up general mode register. 1088 */ 1089 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS| 1090 BGE_MODECTL_MAC_ATTN_INTR|BGE_MODECTL_HOST_SEND_BDS| 1091 BGE_MODECTL_NO_RX_CRC|BGE_MODECTL_TX_NO_PHDR_CSUM| 1092 BGE_MODECTL_RX_NO_PHDR_CSUM); 1093 1094 /* Get cache line size. */ 1095 cachesize = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_CACHESZ); 1096 1097 /* 1098 * Avoid violating PCI spec on certain chip revs. 1099 */ 1100 if (pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_CMD) & 1101 PCIM_CMD_MWIEN) { 1102 switch(cachesize) { 1103 case 1: 1104 PCI_SETBIT(pa->pa_pc, pa->pa_tag, BGE_PCI_DMA_RW_CTL, 1105 BGE_PCI_WRITE_BNDRY_16BYTES); 1106 break; 1107 case 2: 1108 PCI_SETBIT(pa->pa_pc, pa->pa_tag, BGE_PCI_DMA_RW_CTL, 1109 BGE_PCI_WRITE_BNDRY_32BYTES); 1110 break; 1111 case 4: 1112 PCI_SETBIT(pa->pa_pc, pa->pa_tag, BGE_PCI_DMA_RW_CTL, 1113 BGE_PCI_WRITE_BNDRY_64BYTES); 1114 break; 1115 case 8: 1116 PCI_SETBIT(pa->pa_pc, pa->pa_tag, BGE_PCI_DMA_RW_CTL, 1117 BGE_PCI_WRITE_BNDRY_128BYTES); 1118 break; 1119 case 16: 1120 PCI_SETBIT(pa->pa_pc, pa->pa_tag, BGE_PCI_DMA_RW_CTL, 1121 BGE_PCI_WRITE_BNDRY_256BYTES); 1122 break; 1123 case 32: 1124 PCI_SETBIT(pa->pa_pc, pa->pa_tag, BGE_PCI_DMA_RW_CTL, 1125 BGE_PCI_WRITE_BNDRY_512BYTES); 1126 break; 1127 case 64: 1128 PCI_SETBIT(pa->pa_pc, pa->pa_tag, BGE_PCI_DMA_RW_CTL, 1129 BGE_PCI_WRITE_BNDRY_1024BYTES); 1130 break; 1131 default: 1132 /* Disable PCI memory write and invalidate. */ 1133 #if 0 1134 if (bootverbose) 1135 printf("%s: cache line size %d not " 1136 "supported; disabling PCI MWI\n", 1137 sc->bge_dev.dv_xname, cachesize); 1138 #endif 1139 PCI_CLRBIT(pa->pa_pc, pa->pa_tag, BGE_PCI_CMD, 1140 PCIM_CMD_MWIEN); 1141 break; 1142 } 1143 } 1144 1145 #ifdef __brokenalpha__ 1146 /* 1147 * Must insure that we do not cross an 8K (bytes) boundary 1148 * for DMA reads. Our highest limit is 1K bytes. This is a 1149 * restriction on some ALPHA platforms with early revision 1150 * 21174 PCI chipsets, such as the AlphaPC 164lx 1151 */ 1152 PCI_SETBIT(sc, BGE_PCI_DMA_RW_CTL, BGE_PCI_READ_BNDRY_1024, 4); 1153 #endif 1154 1155 /* Set the timer prescaler (always 66Mhz) */ 1156 CSR_WRITE_4(sc, BGE_MISC_CFG, 65 << 1/*BGE_32BITTIME_66MHZ*/); 1157 1158 return(0); 1159 } 1160 1161 int 1162 bge_blockinit(sc) 1163 struct bge_softc *sc; 1164 { 1165 struct bge_rcb *rcb; 1166 struct bge_rcb_opaque *rcbo; 1167 bus_size_t rcb_addr; 1168 int i; 1169 struct ifnet *ifp = &sc->ethercom.ec_if; 1170 bge_hostaddr taddr; 1171 1172 /* 1173 * Initialize the memory window pointer register so that 1174 * we can access the first 32K of internal NIC RAM. This will 1175 * allow us to set up the TX send ring RCBs and the RX return 1176 * ring RCBs, plus other things which live in NIC memory. 1177 */ 1178 1179 pci_conf_write(sc->bge_pa.pa_pc, sc->bge_pa.pa_tag, 1180 BGE_PCI_MEMWIN_BASEADDR, 0); 1181 1182 /* Configure mbuf memory pool */ 1183 if (sc->bge_extram) { 1184 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, BGE_EXT_SSRAM); 1185 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000); 1186 } else { 1187 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, BGE_BUFFPOOL_1); 1188 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000); 1189 } 1190 1191 /* Configure DMA resource pool */ 1192 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_BASEADDR, BGE_DMA_DESCRIPTORS); 1193 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LEN, 0x2000); 1194 1195 /* Configure mbuf pool watermarks */ 1196 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 24); 1197 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 24); 1198 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 48); 1199 1200 /* Configure DMA resource watermarks */ 1201 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5); 1202 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10); 1203 1204 /* Enable buffer manager */ 1205 CSR_WRITE_4(sc, BGE_BMAN_MODE, 1206 BGE_BMANMODE_ENABLE|BGE_BMANMODE_LOMBUF_ATTN); 1207 1208 /* Poll for buffer manager start indication */ 1209 for (i = 0; i < BGE_TIMEOUT; i++) { 1210 if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE) 1211 break; 1212 DELAY(10); 1213 } 1214 1215 if (i == BGE_TIMEOUT) { 1216 printf("%s: buffer manager failed to start\n", 1217 sc->bge_dev.dv_xname); 1218 return(ENXIO); 1219 } 1220 1221 /* Enable flow-through queues */ 1222 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 1223 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 1224 1225 /* Wait until queue initialization is complete */ 1226 for (i = 0; i < BGE_TIMEOUT; i++) { 1227 if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0) 1228 break; 1229 DELAY(10); 1230 } 1231 1232 if (i == BGE_TIMEOUT) { 1233 printf("%s: flow-through queue init failed\n", 1234 sc->bge_dev.dv_xname); 1235 return(ENXIO); 1236 } 1237 1238 /* Initialize the standard RX ring control block */ 1239 rcb = &sc->bge_rdata->bge_info.bge_std_rx_rcb; 1240 bge_set_hostaddr(&rcb->bge_hostaddr, 1241 BGE_RING_DMA_ADDR(sc, bge_rx_std_ring)); 1242 rcb->bge_max_len = BGE_MAX_FRAMELEN; 1243 if (sc->bge_extram) 1244 rcb->bge_nicaddr = BGE_EXT_STD_RX_RINGS; 1245 else 1246 rcb->bge_nicaddr = BGE_STD_RX_RINGS; 1247 rcb->bge_flags = 0; 1248 rcbo = (struct bge_rcb_opaque *)rcb; 1249 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcbo->bge_reg0); 1250 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcbo->bge_reg1); 1251 CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcbo->bge_reg2); 1252 CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcbo->bge_reg3); 1253 1254 /* 1255 * Initialize the jumbo RX ring control block 1256 * We set the 'ring disabled' bit in the flags 1257 * field until we're actually ready to start 1258 * using this ring (i.e. once we set the MTU 1259 * high enough to require it). 1260 */ 1261 rcb = &sc->bge_rdata->bge_info.bge_jumbo_rx_rcb; 1262 bge_set_hostaddr(&rcb->bge_hostaddr, 1263 BGE_RING_DMA_ADDR(sc, bge_rx_jumbo_ring)); 1264 rcb->bge_max_len = BGE_MAX_FRAMELEN; 1265 if (sc->bge_extram) 1266 rcb->bge_nicaddr = BGE_EXT_JUMBO_RX_RINGS; 1267 else 1268 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS; 1269 rcb->bge_flags = BGE_RCB_FLAG_RING_DISABLED; 1270 1271 rcbo = (struct bge_rcb_opaque *)rcb; 1272 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI, rcbo->bge_reg0); 1273 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO, rcbo->bge_reg1); 1274 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcbo->bge_reg2); 1275 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcbo->bge_reg3); 1276 1277 /* Set up dummy disabled mini ring RCB */ 1278 rcb = &sc->bge_rdata->bge_info.bge_mini_rx_rcb; 1279 rcb->bge_flags = BGE_RCB_FLAG_RING_DISABLED; 1280 rcbo = (struct bge_rcb_opaque *)rcb; 1281 CSR_WRITE_4(sc, BGE_RX_MINI_RCB_MAXLEN_FLAGS, rcbo->bge_reg2); 1282 1283 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 1284 offsetof(struct bge_ring_data, bge_info), sizeof (struct bge_gib), 1285 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1286 1287 /* 1288 * Set the BD ring replentish thresholds. The recommended 1289 * values are 1/8th the number of descriptors allocated to 1290 * each ring. 1291 */ 1292 CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, BGE_STD_RX_RING_CNT/8); 1293 CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH, BGE_JUMBO_RX_RING_CNT/8); 1294 1295 /* 1296 * Disable all unused send rings by setting the 'ring disabled' 1297 * bit in the flags field of all the TX send ring control blocks. 1298 * These are located in NIC memory. 1299 */ 1300 rcb_addr = BGE_MEMWIN_START + BGE_SEND_RING_RCB; 1301 for (i = 0; i < BGE_TX_RINGS_EXTSSRAM_MAX; i++) { 1302 RCB_WRITE_2(sc, rcb_addr, bge_flags, 1303 BGE_RCB_FLAG_RING_DISABLED); 1304 RCB_WRITE_2(sc, rcb_addr, bge_max_len, 0); 1305 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 0); 1306 rcb_addr += sizeof(struct bge_rcb); 1307 } 1308 1309 /* Configure TX RCB 0 (we use only the first ring) */ 1310 rcb_addr = BGE_MEMWIN_START + BGE_SEND_RING_RCB; 1311 bge_set_hostaddr(&taddr, BGE_RING_DMA_ADDR(sc, bge_tx_ring)); 1312 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi); 1313 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo); 1314 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 1315 BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT)); 1316 RCB_WRITE_2(sc, rcb_addr, bge_max_len, BGE_TX_RING_CNT); 1317 RCB_WRITE_2(sc, rcb_addr, bge_flags, 0); 1318 1319 /* Disable all unused RX return rings */ 1320 rcb_addr = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB; 1321 for (i = 0; i < BGE_RX_RINGS_MAX; i++) { 1322 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_hi, 0); 1323 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_lo, 0); 1324 RCB_WRITE_2(sc, rcb_addr, bge_flags, 1325 BGE_RCB_FLAG_RING_DISABLED); 1326 RCB_WRITE_2(sc, rcb_addr, bge_max_len, BGE_RETURN_RING_CNT); 1327 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 0); 1328 CSR_WRITE_4(sc, BGE_MBX_RX_CONS0_LO + 1329 (i * (sizeof(u_int64_t))), 0); 1330 rcb_addr += sizeof(struct bge_rcb); 1331 } 1332 1333 /* Initialize RX ring indexes */ 1334 CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, 0); 1335 CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0); 1336 CSR_WRITE_4(sc, BGE_MBX_RX_MINI_PROD_LO, 0); 1337 1338 /* 1339 * Set up RX return ring 0 1340 * Note that the NIC address for RX return rings is 0x00000000. 1341 * The return rings live entirely within the host, so the 1342 * nicaddr field in the RCB isn't used. 1343 */ 1344 rcb_addr = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB; 1345 bge_set_hostaddr(&taddr, BGE_RING_DMA_ADDR(sc, bge_rx_return_ring)); 1346 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi); 1347 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo); 1348 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 0x00000000); 1349 RCB_WRITE_2(sc, rcb_addr, bge_max_len, BGE_RETURN_RING_CNT); 1350 RCB_WRITE_2(sc, rcb_addr, bge_flags, 0); 1351 1352 /* Set random backoff seed for TX */ 1353 CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF, 1354 LLADDR(ifp->if_sadl)[0] + LLADDR(ifp->if_sadl)[1] + 1355 LLADDR(ifp->if_sadl)[2] + LLADDR(ifp->if_sadl)[3] + 1356 LLADDR(ifp->if_sadl)[4] + LLADDR(ifp->if_sadl)[5] + 1357 BGE_TX_BACKOFF_SEED_MASK); 1358 1359 /* Set inter-packet gap */ 1360 CSR_WRITE_4(sc, BGE_TX_LENGTHS, 0x2620); 1361 1362 /* 1363 * Specify which ring to use for packets that don't match 1364 * any RX rules. 1365 */ 1366 CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08); 1367 1368 /* 1369 * Configure number of RX lists. One interrupt distribution 1370 * list, sixteen active lists, one bad frames class. 1371 */ 1372 CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181); 1373 1374 /* Inialize RX list placement stats mask. */ 1375 CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF); 1376 CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1); 1377 1378 /* Disable host coalescing until we get it set up */ 1379 CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000); 1380 1381 /* Poll to make sure it's shut down. */ 1382 for (i = 0; i < BGE_TIMEOUT; i++) { 1383 if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE)) 1384 break; 1385 DELAY(10); 1386 } 1387 1388 if (i == BGE_TIMEOUT) { 1389 printf("%s: host coalescing engine failed to idle\n", 1390 sc->bge_dev.dv_xname); 1391 return(ENXIO); 1392 } 1393 1394 /* Set up host coalescing defaults */ 1395 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bge_rx_coal_ticks); 1396 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bge_tx_coal_ticks); 1397 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bge_rx_max_coal_bds); 1398 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bge_tx_max_coal_bds); 1399 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT, 0); 1400 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT, 0); 1401 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 0); 1402 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 0); 1403 CSR_WRITE_4(sc, BGE_HCC_STATS_TICKS, sc->bge_stat_ticks); 1404 1405 /* Set up address of statistics block */ 1406 bge_set_hostaddr(&taddr, BGE_RING_DMA_ADDR(sc, bge_info.bge_stats)); 1407 CSR_WRITE_4(sc, BGE_HCC_STATS_BASEADDR, BGE_STATS_BLOCK); 1408 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_HI, taddr.bge_addr_hi); 1409 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_LO, taddr.bge_addr_lo); 1410 1411 /* Set up address of status block */ 1412 bge_set_hostaddr(&taddr, BGE_RING_DMA_ADDR(sc, bge_status_block)); 1413 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_BASEADDR, BGE_STATUS_BLOCK); 1414 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI, taddr.bge_addr_hi); 1415 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO, taddr.bge_addr_lo); 1416 sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx = 0; 1417 sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx = 0; 1418 1419 /* Turn on host coalescing state machine */ 1420 CSR_WRITE_4(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE); 1421 1422 /* Turn on RX BD completion state machine and enable attentions */ 1423 CSR_WRITE_4(sc, BGE_RBDC_MODE, 1424 BGE_RBDCMODE_ENABLE|BGE_RBDCMODE_ATTN); 1425 1426 /* Turn on RX list placement state machine */ 1427 CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 1428 1429 /* Turn on RX list selector state machine. */ 1430 CSR_WRITE_4(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 1431 1432 /* Turn on DMA, clear stats */ 1433 CSR_WRITE_4(sc, BGE_MAC_MODE, BGE_MACMODE_TXDMA_ENB| 1434 BGE_MACMODE_RXDMA_ENB|BGE_MACMODE_RX_STATS_CLEAR| 1435 BGE_MACMODE_TX_STATS_CLEAR|BGE_MACMODE_RX_STATS_ENB| 1436 BGE_MACMODE_TX_STATS_ENB|BGE_MACMODE_FRMHDR_DMA_ENB| 1437 (sc->bge_tbi ? BGE_PORTMODE_TBI : BGE_PORTMODE_MII)); 1438 1439 /* Set misc. local control, enable interrupts on attentions */ 1440 CSR_WRITE_4(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_ONATTN); 1441 1442 #ifdef notdef 1443 /* Assert GPIO pins for PHY reset */ 1444 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUT0| 1445 BGE_MLC_MISCIO_OUT1|BGE_MLC_MISCIO_OUT2); 1446 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUTEN0| 1447 BGE_MLC_MISCIO_OUTEN1|BGE_MLC_MISCIO_OUTEN2); 1448 #endif 1449 1450 /* Turn on DMA completion state machine */ 1451 CSR_WRITE_4(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 1452 1453 /* Turn on write DMA state machine */ 1454 CSR_WRITE_4(sc, BGE_WDMA_MODE, 1455 BGE_WDMAMODE_ENABLE|BGE_WDMAMODE_ALL_ATTNS); 1456 1457 /* Turn on read DMA state machine */ 1458 CSR_WRITE_4(sc, BGE_RDMA_MODE, 1459 BGE_RDMAMODE_ENABLE|BGE_RDMAMODE_ALL_ATTNS); 1460 1461 /* Turn on RX data completion state machine */ 1462 CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 1463 1464 /* Turn on RX BD initiator state machine */ 1465 CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 1466 1467 /* Turn on RX data and RX BD initiator state machine */ 1468 CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE); 1469 1470 /* Turn on Mbuf cluster free state machine */ 1471 CSR_WRITE_4(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 1472 1473 /* Turn on send BD completion state machine */ 1474 CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 1475 1476 /* Turn on send data completion state machine */ 1477 CSR_WRITE_4(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE); 1478 1479 /* Turn on send data initiator state machine */ 1480 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 1481 1482 /* Turn on send BD initiator state machine */ 1483 CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 1484 1485 /* Turn on send BD selector state machine */ 1486 CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 1487 1488 CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF); 1489 CSR_WRITE_4(sc, BGE_SDI_STATS_CTL, 1490 BGE_SDISTATSCTL_ENABLE|BGE_SDISTATSCTL_FASTER); 1491 1492 /* init LED register */ 1493 CSR_WRITE_4(sc, BGE_MAC_LED_CTL, 0x00000000); 1494 1495 /* ack/clear link change events */ 1496 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED| 1497 BGE_MACSTAT_CFG_CHANGED); 1498 CSR_WRITE_4(sc, BGE_MI_STS, 0); 1499 1500 /* Enable PHY auto polling (for MII/GMII only) */ 1501 if (sc->bge_tbi) { 1502 CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK); 1503 } else { 1504 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL|10<<16); 1505 if (sc->bge_quirks & BGE_QUIRK_LINK_STATE_BROKEN) 1506 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, 1507 BGE_EVTENB_MI_INTERRUPT); 1508 } 1509 1510 /* Enable link state change attentions. */ 1511 BGE_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED); 1512 1513 return(0); 1514 } 1515 1516 static const struct bge_revision { 1517 uint32_t br_asicrev; 1518 uint32_t br_quirks; 1519 const char *br_name; 1520 } bge_revisions[] = { 1521 { BGE_ASICREV_BCM5700_A0, 1522 BGE_QUIRK_LINK_STATE_BROKEN, 1523 "BCM5700 A0" }, 1524 1525 { BGE_ASICREV_BCM5700_A1, 1526 BGE_QUIRK_LINK_STATE_BROKEN, 1527 "BCM5700 A1" }, 1528 1529 { BGE_ASICREV_BCM5700_B0, 1530 BGE_QUIRK_LINK_STATE_BROKEN|BGE_QUIRK_CSUM_BROKEN, 1531 "BCM5700 B0" }, 1532 1533 { BGE_ASICREV_BCM5700_B1, 1534 BGE_QUIRK_LINK_STATE_BROKEN, 1535 "BCM5700 B1" }, 1536 1537 { BGE_ASICREV_BCM5700_B2, 1538 BGE_QUIRK_LINK_STATE_BROKEN, 1539 "BCM5700 B2" }, 1540 1541 /* This is treated like a BCM5700 Bx */ 1542 { BGE_ASICREV_BCM5700_ALTIMA, 1543 BGE_QUIRK_LINK_STATE_BROKEN, 1544 "BCM5700 Altima" }, 1545 1546 { BGE_ASICREV_BCM5700_C0, 1547 0, 1548 "BCM5700 C0" }, 1549 1550 { BGE_ASICREV_BCM5701_A0, 1551 0, 1552 "BCM5701 A0" }, 1553 1554 { BGE_ASICREV_BCM5701_B0, 1555 0, 1556 "BCM5701 B0" }, 1557 1558 { BGE_ASICREV_BCM5701_B2, 1559 0, 1560 "BCM5701 B2" }, 1561 1562 { BGE_ASICREV_BCM5701_B5, 1563 0, 1564 "BCM5701 B5" }, 1565 1566 { BGE_ASICREV_BCM5703_A0, 1567 0, 1568 "BCM5703 A0" }, 1569 1570 { BGE_ASICREV_BCM5703_A1, 1571 0, 1572 "BCM5703 A1" }, 1573 1574 { BGE_ASICREV_BCM5703_A2, 1575 0, 1576 "BCM5703 A2" }, 1577 1578 { 0, 0, NULL } 1579 }; 1580 1581 static const struct bge_revision * 1582 bge_lookup_rev(uint32_t asicrev) 1583 { 1584 const struct bge_revision *br; 1585 1586 for (br = bge_revisions; br->br_name != NULL; br++) { 1587 if (br->br_asicrev == asicrev) 1588 return (br); 1589 } 1590 1591 return (NULL); 1592 } 1593 1594 static const struct bge_product { 1595 pci_vendor_id_t bp_vendor; 1596 pci_product_id_t bp_product; 1597 const char *bp_name; 1598 } bge_products[] = { 1599 /* 1600 * The BCM5700 documentation seems to indicate that the hardware 1601 * still has the Alteon vendor ID burned into it, though it 1602 * should always be overridden by the value in the EEPROM. We'll 1603 * check for it anyway. 1604 */ 1605 { PCI_VENDOR_ALTEON, 1606 PCI_PRODUCT_ALTEON_BCM5700, 1607 "Broadcom BCM5700 Gigabit Ethernet" }, 1608 { PCI_VENDOR_ALTEON, 1609 PCI_PRODUCT_ALTEON_BCM5701, 1610 "Broadcom BCM5701 Gigabit Ethernet" }, 1611 1612 { PCI_VENDOR_ALTIMA, 1613 PCI_PRODUCT_ALTIMA_AC1000, 1614 "Altima AC1000 Gigabit Ethernet" }, 1615 { PCI_VENDOR_ALTIMA, 1616 PCI_PRODUCT_ALTIMA_AC1001, 1617 "Altima AC1001 Gigabit Ethernet" }, 1618 { PCI_VENDOR_ALTIMA, 1619 PCI_PRODUCT_ALTIMA_AC9100, 1620 "Altima AC9100 Gigabit Ethernet" }, 1621 1622 { PCI_VENDOR_BROADCOM, 1623 PCI_PRODUCT_BROADCOM_BCM5700, 1624 "Broadcom BCM5700 Gigabit Ethernet" }, 1625 { PCI_VENDOR_BROADCOM, 1626 PCI_PRODUCT_BROADCOM_BCM5701, 1627 "Broadcom BCM5700 Gigabit Ethernet" }, 1628 1629 { PCI_VENDOR_SCHNEIDERKOCH, 1630 PCI_PRODUCT_SCHNEIDERKOCH_SK_9DX1, 1631 "SysKonnect SK-9Dx1 Gigabit Ethernet" }, 1632 1633 { PCI_VENDOR_3COM, 1634 PCI_PRODUCT_3COM_3C996, 1635 "3Com 3c996 Gigabit Ethernet" }, 1636 1637 { 0, 1638 0, 1639 NULL }, 1640 }; 1641 1642 static const struct bge_product * 1643 bge_lookup(const struct pci_attach_args *pa) 1644 { 1645 const struct bge_product *bp; 1646 1647 for (bp = bge_products; bp->bp_name != NULL; bp++) { 1648 if (PCI_VENDOR(pa->pa_id) == bp->bp_vendor && 1649 PCI_PRODUCT(pa->pa_id) == bp->bp_product) 1650 return (bp); 1651 } 1652 1653 return (NULL); 1654 } 1655 1656 /* 1657 * Probe for a Broadcom chip. Check the PCI vendor and device IDs 1658 * against our list and return its name if we find a match. Note 1659 * that since the Broadcom controller contains VPD support, we 1660 * can get the device name string from the controller itself instead 1661 * of the compiled-in string. This is a little slow, but it guarantees 1662 * we'll always announce the right product name. 1663 */ 1664 int 1665 bge_probe(parent, match, aux) 1666 struct device *parent; 1667 struct cfdata *match; 1668 void *aux; 1669 { 1670 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 1671 1672 if (bge_lookup(pa) != NULL) 1673 return (1); 1674 1675 return (0); 1676 } 1677 1678 void 1679 bge_attach(parent, self, aux) 1680 struct device *parent, *self; 1681 void *aux; 1682 { 1683 struct bge_softc *sc = (struct bge_softc *)self; 1684 struct pci_attach_args *pa = aux; 1685 const struct bge_product *bp; 1686 const struct bge_revision *br; 1687 pci_chipset_tag_t pc = pa->pa_pc; 1688 pci_intr_handle_t ih; 1689 const char *intrstr = NULL; 1690 bus_dma_segment_t seg; 1691 int rseg; 1692 u_int32_t hwcfg = 0; 1693 u_int32_t command; 1694 struct ifnet *ifp; 1695 int unit; 1696 caddr_t kva; 1697 u_char eaddr[ETHER_ADDR_LEN]; 1698 pcireg_t memtype; 1699 bus_addr_t memaddr; 1700 bus_size_t memsize; 1701 1702 bp = bge_lookup(pa); 1703 KASSERT(bp != NULL); 1704 1705 sc->bge_pa = *pa; 1706 1707 printf(": %s\n", bp->bp_name); 1708 1709 /* 1710 * Map control/status registers. 1711 */ 1712 DPRINTFN(5, ("Map control/status regs\n")); 1713 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 1714 command |= PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_MASTER_ENABLE; 1715 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, command); 1716 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 1717 1718 if (!(command & PCI_COMMAND_MEM_ENABLE)) { 1719 printf("%s: failed to enable memory mapping!\n", 1720 sc->bge_dev.dv_xname); 1721 return; 1722 } 1723 1724 DPRINTFN(5, ("pci_mem_find\n")); 1725 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, BGE_PCI_BAR0); 1726 switch (memtype) { 1727 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 1728 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 1729 if (pci_mapreg_map(pa, BGE_PCI_BAR0, 1730 memtype, 0, &sc->bge_btag, &sc->bge_bhandle, 1731 &memaddr, &memsize) == 0) 1732 break; 1733 default: 1734 printf("%s: can't find mem space\n", 1735 sc->bge_dev.dv_xname); 1736 return; 1737 } 1738 1739 DPRINTFN(5, ("pci_intr_map\n")); 1740 if (pci_intr_map(pa, &ih)) { 1741 printf("%s: couldn't map interrupt\n", 1742 sc->bge_dev.dv_xname); 1743 return; 1744 } 1745 1746 DPRINTFN(5, ("pci_intr_string\n")); 1747 intrstr = pci_intr_string(pc, ih); 1748 1749 DPRINTFN(5, ("pci_intr_establish\n")); 1750 sc->bge_intrhand = pci_intr_establish(pc, ih, IPL_NET, bge_intr, sc); 1751 1752 if (sc->bge_intrhand == NULL) { 1753 printf("%s: couldn't establish interrupt", 1754 sc->bge_dev.dv_xname); 1755 if (intrstr != NULL) 1756 printf(" at %s", intrstr); 1757 printf("\n"); 1758 return; 1759 } 1760 printf("%s: interrupting at %s\n", sc->bge_dev.dv_xname, intrstr); 1761 1762 /* Try to reset the chip. */ 1763 DPRINTFN(5, ("bge_reset\n")); 1764 bge_reset(sc); 1765 1766 if (bge_chipinit(sc)) { 1767 printf("%s: chip initializatino failed\n", 1768 sc->bge_dev.dv_xname); 1769 bge_release_resources(sc); 1770 return; 1771 } 1772 1773 /* 1774 * Get station address from the EEPROM. 1775 */ 1776 if (bge_read_eeprom(sc, (caddr_t)eaddr, 1777 BGE_EE_MAC_OFFSET + 2, ETHER_ADDR_LEN)) { 1778 printf("bge%d: failed to read station address\n", unit); 1779 bge_release_resources(sc); 1780 return; 1781 } 1782 1783 /* 1784 * Save ASIC rev. Look up any quirks associated with this 1785 * ASIC. 1786 */ 1787 sc->bge_asicrev = 1788 pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_MISC_CTL) & 1789 BGE_PCIMISCCTL_ASICREV; 1790 br = bge_lookup_rev(sc->bge_asicrev); 1791 1792 printf("%s: ", sc->bge_dev.dv_xname); 1793 if (br == NULL) { 1794 printf("unknown ASIC 0x%08x", sc->bge_asicrev); 1795 sc->bge_quirks = 0; 1796 } else { 1797 printf("ASIC %s", br->br_name); 1798 sc->bge_quirks = br->br_quirks; 1799 } 1800 printf(", Ethernet address %s\n", ether_sprintf(eaddr)); 1801 1802 /* Allocate the general information block and ring buffers. */ 1803 sc->bge_dmatag = pa->pa_dmat; 1804 DPRINTFN(5, ("bus_dmamem_alloc\n")); 1805 if (bus_dmamem_alloc(sc->bge_dmatag, sizeof(struct bge_ring_data), 1806 PAGE_SIZE, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 1807 printf("%s: can't alloc rx buffers\n", sc->bge_dev.dv_xname); 1808 return; 1809 } 1810 DPRINTFN(5, ("bus_dmamem_map\n")); 1811 if (bus_dmamem_map(sc->bge_dmatag, &seg, rseg, 1812 sizeof(struct bge_ring_data), &kva, 1813 BUS_DMA_NOWAIT)) { 1814 printf("%s: can't map dma buffers (%d bytes)\n", 1815 sc->bge_dev.dv_xname, (int)sizeof(struct bge_ring_data)); 1816 bus_dmamem_free(sc->bge_dmatag, &seg, rseg); 1817 return; 1818 } 1819 DPRINTFN(5, ("bus_dmamem_create\n")); 1820 if (bus_dmamap_create(sc->bge_dmatag, sizeof(struct bge_ring_data), 1, 1821 sizeof(struct bge_ring_data), 0, 1822 BUS_DMA_NOWAIT, &sc->bge_ring_map)) { 1823 printf("%s: can't create dma map\n", sc->bge_dev.dv_xname); 1824 bus_dmamem_unmap(sc->bge_dmatag, kva, 1825 sizeof(struct bge_ring_data)); 1826 bus_dmamem_free(sc->bge_dmatag, &seg, rseg); 1827 return; 1828 } 1829 DPRINTFN(5, ("bus_dmamem_load\n")); 1830 if (bus_dmamap_load(sc->bge_dmatag, sc->bge_ring_map, kva, 1831 sizeof(struct bge_ring_data), NULL, 1832 BUS_DMA_NOWAIT)) { 1833 bus_dmamap_destroy(sc->bge_dmatag, sc->bge_ring_map); 1834 bus_dmamem_unmap(sc->bge_dmatag, kva, 1835 sizeof(struct bge_ring_data)); 1836 bus_dmamem_free(sc->bge_dmatag, &seg, rseg); 1837 return; 1838 } 1839 1840 DPRINTFN(5, ("bzero\n")); 1841 sc->bge_rdata = (struct bge_ring_data *)kva; 1842 1843 memset(sc->bge_rdata, 0, sizeof(struct bge_ring_data)); 1844 1845 /* Try to allocate memory for jumbo buffers. */ 1846 if (bge_alloc_jumbo_mem(sc)) { 1847 printf("%s: jumbo buffer allocation failed\n", 1848 sc->bge_dev.dv_xname); 1849 } else 1850 sc->ethercom.ec_capabilities |= ETHERCAP_JUMBO_MTU; 1851 1852 /* Set default tuneable values. */ 1853 sc->bge_stat_ticks = BGE_TICKS_PER_SEC; 1854 sc->bge_rx_coal_ticks = 150; 1855 sc->bge_tx_coal_ticks = 150; 1856 sc->bge_rx_max_coal_bds = 64; 1857 sc->bge_tx_max_coal_bds = 128; 1858 1859 /* Set up ifnet structure */ 1860 ifp = &sc->ethercom.ec_if; 1861 ifp->if_softc = sc; 1862 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1863 ifp->if_ioctl = bge_ioctl; 1864 ifp->if_start = bge_start; 1865 ifp->if_init = bge_init; 1866 ifp->if_watchdog = bge_watchdog; 1867 IFQ_SET_MAXLEN(&ifp->if_snd, BGE_TX_RING_CNT - 1); 1868 IFQ_SET_READY(&ifp->if_snd); 1869 DPRINTFN(5, ("bcopy\n")); 1870 strcpy(ifp->if_xname, sc->bge_dev.dv_xname); 1871 1872 if ((sc->bge_quirks & BGE_QUIRK_CSUM_BROKEN) == 0) 1873 sc->ethercom.ec_if.if_capabilities |= 1874 IFCAP_CSUM_IPv4 | IFCAP_CSUM_TCPv4 | IFCAP_CSUM_UDPv4; 1875 sc->ethercom.ec_capabilities |= 1876 ETHERCAP_VLAN_HWTAGGING | ETHERCAP_VLAN_MTU; 1877 1878 /* 1879 * Do MII setup. 1880 */ 1881 DPRINTFN(5, ("mii setup\n")); 1882 sc->bge_mii.mii_ifp = ifp; 1883 sc->bge_mii.mii_readreg = bge_miibus_readreg; 1884 sc->bge_mii.mii_writereg = bge_miibus_writereg; 1885 sc->bge_mii.mii_statchg = bge_miibus_statchg; 1886 1887 /* 1888 * Figure out what sort of media we have by checking the 1889 * hardware config word in the EEPROM. Note: on some BCM5700 1890 * cards, this value appears to be unset. If that's the 1891 * case, we have to rely on identifying the NIC by its PCI 1892 * subsystem ID, as we do below for the SysKonnect SK-9D41. 1893 */ 1894 bge_read_eeprom(sc, (caddr_t)&hwcfg, 1895 BGE_EE_HWCFG_OFFSET, sizeof(hwcfg)); 1896 if ((be32toh(hwcfg) & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER) 1897 sc->bge_tbi = 1; 1898 1899 /* The SysKonnect SK-9D41 is a 1000baseSX card. */ 1900 if ((pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_SUBSYS) >> 16) == 1901 SK_SUBSYSID_9D41) 1902 sc->bge_tbi = 1; 1903 1904 if (sc->bge_tbi) { 1905 ifmedia_init(&sc->bge_ifmedia, IFM_IMASK, bge_ifmedia_upd, 1906 bge_ifmedia_sts); 1907 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL); 1908 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_1000_SX|IFM_FDX, 1909 0, NULL); 1910 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL); 1911 ifmedia_set(&sc->bge_ifmedia, IFM_ETHER|IFM_AUTO); 1912 } else { 1913 /* 1914 * Do transceiver setup. 1915 */ 1916 ifmedia_init(&sc->bge_mii.mii_media, 0, bge_ifmedia_upd, 1917 bge_ifmedia_sts); 1918 mii_attach(&sc->bge_dev, &sc->bge_mii, 0xffffffff, 1919 MII_PHY_ANY, MII_OFFSET_ANY, 0); 1920 1921 if (LIST_FIRST(&sc->bge_mii.mii_phys) == NULL) { 1922 printf("%s: no PHY found!\n", sc->bge_dev.dv_xname); 1923 ifmedia_add(&sc->bge_mii.mii_media, 1924 IFM_ETHER|IFM_MANUAL, 0, NULL); 1925 ifmedia_set(&sc->bge_mii.mii_media, 1926 IFM_ETHER|IFM_MANUAL); 1927 } else 1928 ifmedia_set(&sc->bge_mii.mii_media, 1929 IFM_ETHER|IFM_AUTO); 1930 } 1931 1932 /* 1933 * Call MI attach routine. 1934 */ 1935 DPRINTFN(5, ("if_attach\n")); 1936 if_attach(ifp); 1937 DPRINTFN(5, ("ether_ifattach\n")); 1938 ether_ifattach(ifp, eaddr); 1939 DPRINTFN(5, ("callout_init\n")); 1940 callout_init(&sc->bge_timeout); 1941 } 1942 1943 void 1944 bge_release_resources(sc) 1945 struct bge_softc *sc; 1946 { 1947 if (sc->bge_vpd_prodname != NULL) 1948 free(sc->bge_vpd_prodname, M_DEVBUF); 1949 1950 if (sc->bge_vpd_readonly != NULL) 1951 free(sc->bge_vpd_readonly, M_DEVBUF); 1952 } 1953 1954 void 1955 bge_reset(sc) 1956 struct bge_softc *sc; 1957 { 1958 struct pci_attach_args *pa = &sc->bge_pa; 1959 u_int32_t cachesize, command, pcistate; 1960 int i, val = 0; 1961 1962 /* Save some important PCI state. */ 1963 cachesize = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_CACHESZ); 1964 command = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_CMD); 1965 pcistate = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_PCISTATE); 1966 1967 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_MISC_CTL, 1968 BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR| 1969 BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_PCISTATE_RW); 1970 1971 /* Issue global reset */ 1972 bge_writereg_ind(sc, BGE_MISC_CFG, 1973 BGE_MISCCFG_RESET_CORE_CLOCKS|(65<<1)); 1974 1975 DELAY(1000); 1976 1977 /* Reset some of the PCI state that got zapped by reset */ 1978 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_MISC_CTL, 1979 BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR| 1980 BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_PCISTATE_RW); 1981 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_CMD, command); 1982 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_CACHESZ, cachesize); 1983 bge_writereg_ind(sc, BGE_MISC_CFG, (65 << 1)); 1984 1985 /* Enable memory arbiter. */ 1986 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 1987 1988 /* 1989 * Prevent PXE restart: write a magic number to the 1990 * general communications memory at 0xB50. 1991 */ 1992 bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM, BGE_MAGIC_NUMBER); 1993 1994 /* 1995 * Poll the value location we just wrote until 1996 * we see the 1's complement of the magic number. 1997 * This indicates that the firmware initialization 1998 * is complete. 1999 */ 2000 for (i = 0; i < 750; i++) { 2001 val = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM); 2002 if (val == ~BGE_MAGIC_NUMBER) 2003 break; 2004 DELAY(1000); 2005 } 2006 2007 if (i == 750) { 2008 printf("%s: firmware handshake timed out, val = %x\n", 2009 sc->bge_dev.dv_xname, val); 2010 return; 2011 } 2012 2013 /* 2014 * XXX Wait for the value of the PCISTATE register to 2015 * return to its original pre-reset state. This is a 2016 * fairly good indicator of reset completion. If we don't 2017 * wait for the reset to fully complete, trying to read 2018 * from the device's non-PCI registers may yield garbage 2019 * results. 2020 */ 2021 for (i = 0; i < BGE_TIMEOUT; i++) { 2022 if (pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_PCISTATE) == 2023 pcistate) 2024 break; 2025 DELAY(10); 2026 } 2027 2028 /* Enable memory arbiter. */ 2029 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 2030 2031 /* Fix up byte swapping */ 2032 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS); 2033 2034 CSR_WRITE_4(sc, BGE_MAC_MODE, 0); 2035 2036 DELAY(10000); 2037 } 2038 2039 /* 2040 * Frame reception handling. This is called if there's a frame 2041 * on the receive return list. 2042 * 2043 * Note: we have to be able to handle two possibilities here: 2044 * 1) the frame is from the jumbo recieve ring 2045 * 2) the frame is from the standard receive ring 2046 */ 2047 2048 void 2049 bge_rxeof(sc) 2050 struct bge_softc *sc; 2051 { 2052 struct ifnet *ifp; 2053 int stdcnt = 0, jumbocnt = 0; 2054 int have_tag = 0; 2055 u_int16_t vlan_tag = 0; 2056 bus_dmamap_t dmamap; 2057 bus_addr_t offset, toff; 2058 bus_size_t tlen; 2059 int tosync; 2060 2061 ifp = &sc->ethercom.ec_if; 2062 2063 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 2064 offsetof(struct bge_ring_data, bge_status_block), 2065 sizeof (struct bge_status_block), 2066 BUS_DMASYNC_POSTREAD); 2067 2068 offset = offsetof(struct bge_ring_data, bge_rx_return_ring); 2069 tosync = sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx - 2070 sc->bge_rx_saved_considx; 2071 2072 toff = offset + (sc->bge_rx_saved_considx * sizeof (struct bge_rx_bd)); 2073 2074 if (tosync < 0) { 2075 tlen = (BGE_RETURN_RING_CNT - sc->bge_rx_saved_considx) * 2076 sizeof (struct bge_rx_bd); 2077 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 2078 toff, tlen, BUS_DMASYNC_POSTREAD); 2079 tosync = -tosync; 2080 } 2081 2082 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 2083 offset, tosync * sizeof (struct bge_rx_bd), 2084 BUS_DMASYNC_POSTREAD); 2085 2086 while(sc->bge_rx_saved_considx != 2087 sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx) { 2088 struct bge_rx_bd *cur_rx; 2089 u_int32_t rxidx; 2090 struct mbuf *m = NULL; 2091 2092 cur_rx = &sc->bge_rdata-> 2093 bge_rx_return_ring[sc->bge_rx_saved_considx]; 2094 2095 rxidx = cur_rx->bge_idx; 2096 BGE_INC(sc->bge_rx_saved_considx, BGE_RETURN_RING_CNT); 2097 2098 if (cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) { 2099 have_tag = 1; 2100 vlan_tag = cur_rx->bge_vlan_tag; 2101 } 2102 2103 if (cur_rx->bge_flags & BGE_RXBDFLAG_JUMBO_RING) { 2104 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT); 2105 m = sc->bge_cdata.bge_rx_jumbo_chain[rxidx]; 2106 sc->bge_cdata.bge_rx_jumbo_chain[rxidx] = NULL; 2107 jumbocnt++; 2108 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 2109 ifp->if_ierrors++; 2110 bge_newbuf_jumbo(sc, sc->bge_jumbo, m); 2111 continue; 2112 } 2113 if (bge_newbuf_jumbo(sc, sc->bge_jumbo, 2114 NULL)== ENOBUFS) { 2115 ifp->if_ierrors++; 2116 bge_newbuf_jumbo(sc, sc->bge_jumbo, m); 2117 continue; 2118 } 2119 } else { 2120 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT); 2121 m = sc->bge_cdata.bge_rx_std_chain[rxidx]; 2122 sc->bge_cdata.bge_rx_std_chain[rxidx] = NULL; 2123 stdcnt++; 2124 dmamap = sc->bge_cdata.bge_rx_std_map[rxidx]; 2125 sc->bge_cdata.bge_rx_std_map[rxidx] = 0; 2126 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 2127 ifp->if_ierrors++; 2128 bge_newbuf_std(sc, sc->bge_std, m, dmamap); 2129 continue; 2130 } 2131 if (bge_newbuf_std(sc, sc->bge_std, 2132 NULL, dmamap) == ENOBUFS) { 2133 ifp->if_ierrors++; 2134 bge_newbuf_std(sc, sc->bge_std, m, dmamap); 2135 continue; 2136 } 2137 } 2138 2139 ifp->if_ipackets++; 2140 m->m_pkthdr.len = m->m_len = cur_rx->bge_len; 2141 m->m_pkthdr.rcvif = ifp; 2142 2143 #if NBPFILTER > 0 2144 /* 2145 * Handle BPF listeners. Let the BPF user see the packet. 2146 */ 2147 if (ifp->if_bpf) 2148 bpf_mtap(ifp->if_bpf, m); 2149 #endif 2150 2151 if ((sc->bge_quirks & BGE_QUIRK_CSUM_BROKEN) == 0) { 2152 m->m_pkthdr.csum_flags |= M_CSUM_IPv4; 2153 if ((cur_rx->bge_ip_csum ^ 0xffff) != 0) 2154 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 2155 #if 0 /* XXX appears to be broken */ 2156 if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM) { 2157 m->m_pkthdr.csum_data = 2158 cur_rx->bge_tcp_udp_csum; 2159 m->m_pkthdr.csum_flags |= 2160 (M_CSUM_TCPv4|M_CSUM_UDPv4|M_CSUM_DATA); 2161 } 2162 #endif 2163 } 2164 2165 /* 2166 * If we received a packet with a vlan tag, pass it 2167 * to vlan_input() instead of ether_input(). 2168 */ 2169 if (have_tag) { 2170 struct mbuf *n; 2171 2172 n = m_aux_add(m, AF_LINK, ETHERTYPE_VLAN); 2173 if (n != NULL) { 2174 *mtod(n, int *) = vlan_tag; 2175 n->m_len = sizeof(int); 2176 have_tag = vlan_tag = 0; 2177 } else { 2178 printf("%s: no mbuf for tag\n", ifp->if_xname); 2179 m_freem(m); 2180 have_tag = vlan_tag = 0; 2181 continue; 2182 } 2183 } 2184 (*ifp->if_input)(ifp, m); 2185 } 2186 2187 CSR_WRITE_4(sc, BGE_MBX_RX_CONS0_LO, sc->bge_rx_saved_considx); 2188 if (stdcnt) 2189 CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std); 2190 if (jumbocnt) 2191 CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo); 2192 } 2193 2194 void 2195 bge_txeof(sc) 2196 struct bge_softc *sc; 2197 { 2198 struct bge_tx_bd *cur_tx = NULL; 2199 struct ifnet *ifp; 2200 struct txdmamap_pool_entry *dma; 2201 bus_addr_t offset, toff; 2202 bus_size_t tlen; 2203 int tosync; 2204 struct mbuf *m; 2205 2206 ifp = &sc->ethercom.ec_if; 2207 2208 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 2209 offsetof(struct bge_ring_data, bge_status_block), 2210 sizeof (struct bge_status_block), 2211 BUS_DMASYNC_POSTREAD); 2212 2213 offset = offsetof(struct bge_ring_data, bge_tx_ring); 2214 tosync = sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx - 2215 sc->bge_tx_saved_considx; 2216 2217 toff = offset + (sc->bge_tx_saved_considx * sizeof (struct bge_tx_bd)); 2218 2219 if (tosync < 0) { 2220 tlen = (BGE_TX_RING_CNT - sc->bge_tx_saved_considx) * 2221 sizeof (struct bge_tx_bd); 2222 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 2223 toff, tlen, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2224 tosync = -tosync; 2225 } 2226 2227 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 2228 offset, tosync * sizeof (struct bge_tx_bd), 2229 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2230 2231 /* 2232 * Go through our tx ring and free mbufs for those 2233 * frames that have been sent. 2234 */ 2235 while (sc->bge_tx_saved_considx != 2236 sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx) { 2237 u_int32_t idx = 0; 2238 2239 idx = sc->bge_tx_saved_considx; 2240 cur_tx = &sc->bge_rdata->bge_tx_ring[idx]; 2241 if (cur_tx->bge_flags & BGE_TXBDFLAG_END) 2242 ifp->if_opackets++; 2243 m = sc->bge_cdata.bge_tx_chain[idx]; 2244 if (m != NULL) { 2245 sc->bge_cdata.bge_tx_chain[idx] = NULL; 2246 dma = sc->txdma[idx]; 2247 bus_dmamap_sync(sc->bge_dmatag, dma->dmamap, 0, 2248 dma->dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 2249 bus_dmamap_unload(sc->bge_dmatag, dma->dmamap); 2250 SLIST_INSERT_HEAD(&sc->txdma_list, dma, link); 2251 sc->txdma[idx] = NULL; 2252 2253 m_freem(m); 2254 } 2255 sc->bge_txcnt--; 2256 BGE_INC(sc->bge_tx_saved_considx, BGE_TX_RING_CNT); 2257 ifp->if_timer = 0; 2258 } 2259 2260 if (cur_tx != NULL) 2261 ifp->if_flags &= ~IFF_OACTIVE; 2262 } 2263 2264 int 2265 bge_intr(xsc) 2266 void *xsc; 2267 { 2268 struct bge_softc *sc; 2269 struct ifnet *ifp; 2270 2271 sc = xsc; 2272 ifp = &sc->ethercom.ec_if; 2273 2274 #ifdef notdef 2275 /* Avoid this for now -- checking this register is expensive. */ 2276 /* Make sure this is really our interrupt. */ 2277 if (!(CSR_READ_4(sc, BGE_MISC_LOCAL_CTL) & BGE_MLC_INTR_STATE)) 2278 return (0); 2279 #endif 2280 /* Ack interrupt and stop others from occuring. */ 2281 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 1); 2282 2283 /* 2284 * Process link state changes. 2285 * Grrr. The link status word in the status block does 2286 * not work correctly on the BCM5700 rev AX and BX chips, 2287 * according to all avaibable information. Hence, we have 2288 * to enable MII interrupts in order to properly obtain 2289 * async link changes. Unfortunately, this also means that 2290 * we have to read the MAC status register to detect link 2291 * changes, thereby adding an additional register access to 2292 * the interrupt handler. 2293 */ 2294 2295 if (sc->bge_quirks & BGE_QUIRK_LINK_STATE_BROKEN) { 2296 u_int32_t status; 2297 2298 status = CSR_READ_4(sc, BGE_MAC_STS); 2299 if (status & BGE_MACSTAT_MI_INTERRUPT) { 2300 sc->bge_link = 0; 2301 callout_stop(&sc->bge_timeout); 2302 bge_tick(sc); 2303 /* Clear the interrupt */ 2304 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, 2305 BGE_EVTENB_MI_INTERRUPT); 2306 bge_miibus_readreg(&sc->bge_dev, 1, BRGPHY_MII_ISR); 2307 bge_miibus_writereg(&sc->bge_dev, 1, BRGPHY_MII_IMR, 2308 BRGPHY_INTRS); 2309 } 2310 } else { 2311 if (sc->bge_rdata->bge_status_block.bge_status & 2312 BGE_STATFLAG_LINKSTATE_CHANGED) { 2313 sc->bge_link = 0; 2314 callout_stop(&sc->bge_timeout); 2315 bge_tick(sc); 2316 /* Clear the interrupt */ 2317 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED| 2318 BGE_MACSTAT_CFG_CHANGED); 2319 } 2320 } 2321 2322 if (ifp->if_flags & IFF_RUNNING) { 2323 /* Check RX return ring producer/consumer */ 2324 bge_rxeof(sc); 2325 2326 /* Check TX ring producer/consumer */ 2327 bge_txeof(sc); 2328 } 2329 2330 bge_handle_events(sc); 2331 2332 /* Re-enable interrupts. */ 2333 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 0); 2334 2335 if (ifp->if_flags & IFF_RUNNING && !IFQ_IS_EMPTY(&ifp->if_snd)) 2336 bge_start(ifp); 2337 2338 return (1); 2339 } 2340 2341 void 2342 bge_tick(xsc) 2343 void *xsc; 2344 { 2345 struct bge_softc *sc = xsc; 2346 struct mii_data *mii = &sc->bge_mii; 2347 struct ifmedia *ifm = NULL; 2348 struct ifnet *ifp = &sc->ethercom.ec_if; 2349 int s; 2350 2351 s = splnet(); 2352 2353 bge_stats_update(sc); 2354 callout_reset(&sc->bge_timeout, hz, bge_tick, sc); 2355 if (sc->bge_link) { 2356 splx(s); 2357 return; 2358 } 2359 2360 if (sc->bge_tbi) { 2361 ifm = &sc->bge_ifmedia; 2362 if (CSR_READ_4(sc, BGE_MAC_STS) & 2363 BGE_MACSTAT_TBI_PCS_SYNCHED) { 2364 sc->bge_link++; 2365 CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF); 2366 printf("%s: gigabit link up\n", sc->bge_dev.dv_xname); 2367 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 2368 bge_start(ifp); 2369 } 2370 splx(s); 2371 return; 2372 } 2373 2374 mii_tick(mii); 2375 2376 if (!sc->bge_link && mii->mii_media_status & IFM_ACTIVE && 2377 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 2378 sc->bge_link++; 2379 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T || 2380 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX) 2381 printf("%s: gigabit link up\n", sc->bge_dev.dv_xname); 2382 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 2383 bge_start(ifp); 2384 } 2385 2386 splx(s); 2387 } 2388 2389 void 2390 bge_stats_update(sc) 2391 struct bge_softc *sc; 2392 { 2393 struct ifnet *ifp = &sc->ethercom.ec_if; 2394 bus_size_t stats = BGE_MEMWIN_START + BGE_STATS_BLOCK; 2395 2396 #define READ_STAT(sc, stats, stat) \ 2397 CSR_READ_4(sc, stats + offsetof(struct bge_stats, stat)) 2398 2399 ifp->if_collisions += 2400 (READ_STAT(sc, stats, dot3StatsSingleCollisionFrames.bge_addr_lo) + 2401 READ_STAT(sc, stats, dot3StatsMultipleCollisionFrames.bge_addr_lo) + 2402 READ_STAT(sc, stats, dot3StatsExcessiveCollisions.bge_addr_lo) + 2403 READ_STAT(sc, stats, dot3StatsLateCollisions.bge_addr_lo)) - 2404 ifp->if_collisions; 2405 2406 #undef READ_STAT 2407 2408 #ifdef notdef 2409 ifp->if_collisions += 2410 (sc->bge_rdata->bge_info.bge_stats.dot3StatsSingleCollisionFrames + 2411 sc->bge_rdata->bge_info.bge_stats.dot3StatsMultipleCollisionFrames + 2412 sc->bge_rdata->bge_info.bge_stats.dot3StatsExcessiveCollisions + 2413 sc->bge_rdata->bge_info.bge_stats.dot3StatsLateCollisions) - 2414 ifp->if_collisions; 2415 #endif 2416 } 2417 2418 /* 2419 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data 2420 * pointers to descriptors. 2421 */ 2422 int 2423 bge_encap(sc, m_head, txidx) 2424 struct bge_softc *sc; 2425 struct mbuf *m_head; 2426 u_int32_t *txidx; 2427 { 2428 struct bge_tx_bd *f = NULL; 2429 u_int32_t frag, cur, cnt = 0; 2430 u_int16_t csum_flags = 0; 2431 struct txdmamap_pool_entry *dma; 2432 bus_dmamap_t dmamap; 2433 int i = 0; 2434 struct mbuf *n; 2435 2436 cur = frag = *txidx; 2437 2438 if (m_head->m_pkthdr.csum_flags) { 2439 if (m_head->m_pkthdr.csum_flags & M_CSUM_IPv4) 2440 csum_flags |= BGE_TXBDFLAG_IP_CSUM; 2441 if (m_head->m_pkthdr.csum_flags & (M_CSUM_TCPv4|M_CSUM_UDPv4)) 2442 csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM; 2443 } 2444 2445 dma = SLIST_FIRST(&sc->txdma_list); 2446 if (dma == NULL) 2447 return ENOBUFS; 2448 dmamap = dma->dmamap; 2449 2450 /* 2451 * Start packing the mbufs in this chain into 2452 * the fragment pointers. Stop when we run out 2453 * of fragments or hit the end of the mbuf chain. 2454 */ 2455 if (bus_dmamap_load_mbuf(sc->bge_dmatag, dmamap, m_head, 2456 BUS_DMA_NOWAIT)) 2457 return(ENOBUFS); 2458 2459 n = sc->ethercom.ec_nvlans ? 2460 m_aux_find(m_head, AF_LINK, ETHERTYPE_VLAN) : NULL; 2461 2462 for (i = 0; i < dmamap->dm_nsegs; i++) { 2463 f = &sc->bge_rdata->bge_tx_ring[frag]; 2464 if (sc->bge_cdata.bge_tx_chain[frag] != NULL) 2465 break; 2466 bge_set_hostaddr(&f->bge_addr, dmamap->dm_segs[i].ds_addr); 2467 f->bge_len = dmamap->dm_segs[i].ds_len; 2468 f->bge_flags = csum_flags; 2469 2470 if (n != NULL) { 2471 f->bge_flags |= BGE_TXBDFLAG_VLAN_TAG; 2472 f->bge_vlan_tag = *mtod(n, int *); 2473 } else { 2474 f->bge_vlan_tag = 0; 2475 } 2476 /* 2477 * Sanity check: avoid coming within 16 descriptors 2478 * of the end of the ring. 2479 */ 2480 if ((BGE_TX_RING_CNT - (sc->bge_txcnt + cnt)) < 16) 2481 return(ENOBUFS); 2482 cur = frag; 2483 BGE_INC(frag, BGE_TX_RING_CNT); 2484 cnt++; 2485 } 2486 2487 if (i < dmamap->dm_nsegs) 2488 return ENOBUFS; 2489 2490 bus_dmamap_sync(sc->bge_dmatag, dmamap, 0, dmamap->dm_mapsize, 2491 BUS_DMASYNC_PREWRITE); 2492 2493 if (frag == sc->bge_tx_saved_considx) 2494 return(ENOBUFS); 2495 2496 sc->bge_rdata->bge_tx_ring[cur].bge_flags |= BGE_TXBDFLAG_END; 2497 sc->bge_cdata.bge_tx_chain[cur] = m_head; 2498 SLIST_REMOVE_HEAD(&sc->txdma_list, link); 2499 sc->txdma[cur] = dma; 2500 sc->bge_txcnt += cnt; 2501 2502 *txidx = frag; 2503 2504 return(0); 2505 } 2506 2507 /* 2508 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 2509 * to the mbuf data regions directly in the transmit descriptors. 2510 */ 2511 void 2512 bge_start(ifp) 2513 struct ifnet *ifp; 2514 { 2515 struct bge_softc *sc; 2516 struct mbuf *m_head = NULL; 2517 u_int32_t prodidx = 0; 2518 int pkts = 0; 2519 2520 sc = ifp->if_softc; 2521 2522 if (!sc->bge_link && ifp->if_snd.ifq_len < 10) 2523 return; 2524 2525 prodidx = CSR_READ_4(sc, BGE_MBX_TX_HOST_PROD0_LO); 2526 2527 while(sc->bge_cdata.bge_tx_chain[prodidx] == NULL) { 2528 IFQ_POLL(&ifp->if_snd, m_head); 2529 if (m_head == NULL) 2530 break; 2531 2532 #if 0 2533 /* 2534 * XXX 2535 * safety overkill. If this is a fragmented packet chain 2536 * with delayed TCP/UDP checksums, then only encapsulate 2537 * it if we have enough descriptors to handle the entire 2538 * chain at once. 2539 * (paranoia -- may not actually be needed) 2540 */ 2541 if (m_head->m_flags & M_FIRSTFRAG && 2542 m_head->m_pkthdr.csum_flags & (CSUM_DELAY_DATA)) { 2543 if ((BGE_TX_RING_CNT - sc->bge_txcnt) < 2544 m_head->m_pkthdr.csum_data + 16) { 2545 ifp->if_flags |= IFF_OACTIVE; 2546 break; 2547 } 2548 } 2549 #endif 2550 2551 /* 2552 * Pack the data into the transmit ring. If we 2553 * don't have room, set the OACTIVE flag and wait 2554 * for the NIC to drain the ring. 2555 */ 2556 if (bge_encap(sc, m_head, &prodidx)) { 2557 ifp->if_flags |= IFF_OACTIVE; 2558 break; 2559 } 2560 2561 /* now we are committed to transmit the packet */ 2562 IFQ_DEQUEUE(&ifp->if_snd, m_head); 2563 pkts++; 2564 2565 #if NBPFILTER > 0 2566 /* 2567 * If there's a BPF listener, bounce a copy of this frame 2568 * to him. 2569 */ 2570 if (ifp->if_bpf) 2571 bpf_mtap(ifp->if_bpf, m_head); 2572 #endif 2573 } 2574 if (pkts == 0) 2575 return; 2576 2577 /* Transmit */ 2578 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); 2579 2580 /* 2581 * Set a timeout in case the chip goes out to lunch. 2582 */ 2583 ifp->if_timer = 5; 2584 } 2585 2586 int 2587 bge_init(ifp) 2588 struct ifnet *ifp; 2589 { 2590 struct bge_softc *sc = ifp->if_softc; 2591 u_int16_t *m; 2592 int s, error; 2593 2594 s = splnet(); 2595 2596 ifp = &sc->ethercom.ec_if; 2597 2598 /* Cancel pending I/O and flush buffers. */ 2599 bge_stop(sc); 2600 bge_reset(sc); 2601 bge_chipinit(sc); 2602 2603 /* 2604 * Init the various state machines, ring 2605 * control blocks and firmware. 2606 */ 2607 error = bge_blockinit(sc); 2608 if (error != 0) { 2609 printf("%s: initialization error %d\n", sc->bge_dev.dv_xname, 2610 error); 2611 splx(s); 2612 return error; 2613 } 2614 2615 ifp = &sc->ethercom.ec_if; 2616 2617 /* Specify MTU. */ 2618 CSR_WRITE_4(sc, BGE_RX_MTU, ifp->if_mtu + 2619 ETHER_HDR_LEN + ETHER_CRC_LEN); 2620 2621 /* Load our MAC address. */ 2622 m = (u_int16_t *)&(LLADDR(ifp->if_sadl)[0]); 2623 CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0])); 2624 CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, (htons(m[1]) << 16) | htons(m[2])); 2625 2626 /* Enable or disable promiscuous mode as needed. */ 2627 if (ifp->if_flags & IFF_PROMISC) { 2628 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 2629 } else { 2630 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 2631 } 2632 2633 /* Program multicast filter. */ 2634 bge_setmulti(sc); 2635 2636 /* Init RX ring. */ 2637 bge_init_rx_ring_std(sc); 2638 2639 /* Init jumbo RX ring. */ 2640 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 2641 bge_init_rx_ring_jumbo(sc); 2642 2643 /* Init our RX return ring index */ 2644 sc->bge_rx_saved_considx = 0; 2645 2646 /* Init TX ring. */ 2647 bge_init_tx_ring(sc); 2648 2649 /* Turn on transmitter */ 2650 BGE_SETBIT(sc, BGE_TX_MODE, BGE_TXMODE_ENABLE); 2651 2652 /* Turn on receiver */ 2653 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE); 2654 2655 /* Tell firmware we're alive. */ 2656 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 2657 2658 /* Enable host interrupts. */ 2659 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA); 2660 BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); 2661 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 0); 2662 2663 bge_ifmedia_upd(ifp); 2664 2665 ifp->if_flags |= IFF_RUNNING; 2666 ifp->if_flags &= ~IFF_OACTIVE; 2667 2668 splx(s); 2669 2670 callout_reset(&sc->bge_timeout, hz, bge_tick, sc); 2671 2672 return 0; 2673 } 2674 2675 /* 2676 * Set media options. 2677 */ 2678 int 2679 bge_ifmedia_upd(ifp) 2680 struct ifnet *ifp; 2681 { 2682 struct bge_softc *sc = ifp->if_softc; 2683 struct mii_data *mii = &sc->bge_mii; 2684 struct ifmedia *ifm = &sc->bge_ifmedia; 2685 2686 /* If this is a 1000baseX NIC, enable the TBI port. */ 2687 if (sc->bge_tbi) { 2688 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 2689 return(EINVAL); 2690 switch(IFM_SUBTYPE(ifm->ifm_media)) { 2691 case IFM_AUTO: 2692 break; 2693 case IFM_1000_SX: 2694 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 2695 BGE_CLRBIT(sc, BGE_MAC_MODE, 2696 BGE_MACMODE_HALF_DUPLEX); 2697 } else { 2698 BGE_SETBIT(sc, BGE_MAC_MODE, 2699 BGE_MACMODE_HALF_DUPLEX); 2700 } 2701 break; 2702 default: 2703 return(EINVAL); 2704 } 2705 return(0); 2706 } 2707 2708 sc->bge_link = 0; 2709 mii_mediachg(mii); 2710 2711 return(0); 2712 } 2713 2714 /* 2715 * Report current media status. 2716 */ 2717 void 2718 bge_ifmedia_sts(ifp, ifmr) 2719 struct ifnet *ifp; 2720 struct ifmediareq *ifmr; 2721 { 2722 struct bge_softc *sc = ifp->if_softc; 2723 struct mii_data *mii = &sc->bge_mii; 2724 2725 if (sc->bge_tbi) { 2726 ifmr->ifm_status = IFM_AVALID; 2727 ifmr->ifm_active = IFM_ETHER; 2728 if (CSR_READ_4(sc, BGE_MAC_STS) & 2729 BGE_MACSTAT_TBI_PCS_SYNCHED) 2730 ifmr->ifm_status |= IFM_ACTIVE; 2731 ifmr->ifm_active |= IFM_1000_SX; 2732 if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX) 2733 ifmr->ifm_active |= IFM_HDX; 2734 else 2735 ifmr->ifm_active |= IFM_FDX; 2736 return; 2737 } 2738 2739 mii_pollstat(mii); 2740 ifmr->ifm_active = mii->mii_media_active; 2741 ifmr->ifm_status = mii->mii_media_status; 2742 } 2743 2744 int 2745 bge_ioctl(ifp, command, data) 2746 struct ifnet *ifp; 2747 u_long command; 2748 caddr_t data; 2749 { 2750 struct bge_softc *sc = ifp->if_softc; 2751 struct ifreq *ifr = (struct ifreq *) data; 2752 int s, error = 0; 2753 struct mii_data *mii; 2754 2755 s = splnet(); 2756 2757 switch(command) { 2758 case SIOCSIFFLAGS: 2759 if (ifp->if_flags & IFF_UP) { 2760 /* 2761 * If only the state of the PROMISC flag changed, 2762 * then just use the 'set promisc mode' command 2763 * instead of reinitializing the entire NIC. Doing 2764 * a full re-init means reloading the firmware and 2765 * waiting for it to start up, which may take a 2766 * second or two. 2767 */ 2768 if (ifp->if_flags & IFF_RUNNING && 2769 ifp->if_flags & IFF_PROMISC && 2770 !(sc->bge_if_flags & IFF_PROMISC)) { 2771 BGE_SETBIT(sc, BGE_RX_MODE, 2772 BGE_RXMODE_RX_PROMISC); 2773 } else if (ifp->if_flags & IFF_RUNNING && 2774 !(ifp->if_flags & IFF_PROMISC) && 2775 sc->bge_if_flags & IFF_PROMISC) { 2776 BGE_CLRBIT(sc, BGE_RX_MODE, 2777 BGE_RXMODE_RX_PROMISC); 2778 } else 2779 bge_init(ifp); 2780 } else { 2781 if (ifp->if_flags & IFF_RUNNING) { 2782 bge_stop(sc); 2783 } 2784 } 2785 sc->bge_if_flags = ifp->if_flags; 2786 error = 0; 2787 break; 2788 case SIOCSIFMEDIA: 2789 case SIOCGIFMEDIA: 2790 if (sc->bge_tbi) { 2791 error = ifmedia_ioctl(ifp, ifr, &sc->bge_ifmedia, 2792 command); 2793 } else { 2794 mii = &sc->bge_mii; 2795 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, 2796 command); 2797 } 2798 error = 0; 2799 break; 2800 default: 2801 error = ether_ioctl(ifp, command, data); 2802 if (error == ENETRESET) { 2803 bge_setmulti(sc); 2804 error = 0; 2805 } 2806 break; 2807 } 2808 2809 splx(s); 2810 2811 return(error); 2812 } 2813 2814 void 2815 bge_watchdog(ifp) 2816 struct ifnet *ifp; 2817 { 2818 struct bge_softc *sc; 2819 2820 sc = ifp->if_softc; 2821 2822 printf("%s: watchdog timeout -- resetting\n", sc->bge_dev.dv_xname); 2823 2824 ifp->if_flags &= ~IFF_RUNNING; 2825 bge_init(ifp); 2826 2827 ifp->if_oerrors++; 2828 } 2829 2830 static void 2831 bge_stop_block(struct bge_softc *sc, bus_addr_t reg, uint32_t bit) 2832 { 2833 int i; 2834 2835 BGE_CLRBIT(sc, reg, bit); 2836 2837 for (i = 0; i < BGE_TIMEOUT; i++) { 2838 if ((CSR_READ_4(sc, reg) & bit) == 0) 2839 return; 2840 delay(100); 2841 } 2842 2843 printf("%s: block failed to stop: reg 0x%lx, bit 0x%08x\n", 2844 sc->bge_dev.dv_xname, (u_long) reg, bit); 2845 } 2846 2847 /* 2848 * Stop the adapter and free any mbufs allocated to the 2849 * RX and TX lists. 2850 */ 2851 void 2852 bge_stop(sc) 2853 struct bge_softc *sc; 2854 { 2855 struct ifnet *ifp = &sc->ethercom.ec_if; 2856 2857 callout_stop(&sc->bge_timeout); 2858 2859 /* 2860 * Disable all of the receiver blocks 2861 */ 2862 bge_stop_block(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE); 2863 bge_stop_block(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 2864 bge_stop_block(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 2865 bge_stop_block(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 2866 bge_stop_block(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE); 2867 bge_stop_block(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 2868 bge_stop_block(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE); 2869 2870 /* 2871 * Disable all of the transmit blocks 2872 */ 2873 bge_stop_block(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 2874 bge_stop_block(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 2875 bge_stop_block(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 2876 bge_stop_block(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE); 2877 bge_stop_block(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE); 2878 bge_stop_block(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 2879 bge_stop_block(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 2880 2881 /* 2882 * Shut down all of the memory managers and related 2883 * state machines. 2884 */ 2885 bge_stop_block(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE); 2886 bge_stop_block(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE); 2887 bge_stop_block(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 2888 2889 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 2890 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 2891 2892 bge_stop_block(sc, BGE_BMAN_MODE, BGE_BMANMODE_ENABLE); 2893 bge_stop_block(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 2894 2895 /* Disable host interrupts. */ 2896 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); 2897 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 1); 2898 2899 /* 2900 * Tell firmware we're shutting down. 2901 */ 2902 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 2903 2904 /* Free the RX lists. */ 2905 bge_free_rx_ring_std(sc); 2906 2907 /* Free jumbo RX list. */ 2908 bge_free_rx_ring_jumbo(sc); 2909 2910 /* Free TX buffers. */ 2911 bge_free_tx_ring(sc); 2912 2913 /* 2914 * Isolate/power down the PHY. 2915 */ 2916 if (!sc->bge_tbi) 2917 mii_down(&sc->bge_mii); 2918 2919 sc->bge_link = 0; 2920 2921 sc->bge_tx_saved_considx = BGE_TXCONS_UNSET; 2922 2923 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2924 } 2925 2926 /* 2927 * Stop all chip I/O so that the kernel's probe routines don't 2928 * get confused by errant DMAs when rebooting. 2929 */ 2930 void 2931 bge_shutdown(xsc) 2932 void *xsc; 2933 { 2934 struct bge_softc *sc = (struct bge_softc *)xsc; 2935 2936 bge_stop(sc); 2937 bge_reset(sc); 2938 } 2939
Indexes created Tue Sep 23 07:09:52 GMT 2025