if_bge.c revision 1.210
1 /* $NetBSD: if_bge.c,v 1.210 2013/03/07 04:42:09 msaitoh Exp $ */ 2 3 /* 4 * Copyright (c) 2001 Wind River Systems 5 * Copyright (c) 1997, 1998, 1999, 2001 6 * Bill Paul <wpaul (at) windriver.com>. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Bill Paul. 19 * 4. Neither the name of the author nor the names of any co-contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 33 * THE POSSIBILITY OF SUCH DAMAGE. 34 * 35 * $FreeBSD: if_bge.c,v 1.13 2002/04/04 06:01:31 wpaul Exp $ 36 */ 37 38 /* 39 * Broadcom BCM570x family gigabit ethernet driver for NetBSD. 40 * 41 * NetBSD version by: 42 * 43 * Frank van der Linden <fvdl (at) wasabisystems.com> 44 * Jason Thorpe <thorpej (at) wasabisystems.com> 45 * Jonathan Stone <jonathan (at) dsg.stanford.edu> 46 * 47 * Originally written for FreeBSD by Bill Paul <wpaul (at) windriver.com> 48 * Senior Engineer, Wind River Systems 49 */ 50 51 /* 52 * The Broadcom BCM5700 is based on technology originally developed by 53 * Alteon Networks as part of the Tigon I and Tigon II gigabit ethernet 54 * MAC chips. The BCM5700, sometimes referred to as the Tigon III, has 55 * two on-board MIPS R4000 CPUs and can have as much as 16MB of external 56 * SSRAM. The BCM5700 supports TCP, UDP and IP checksum offload, jumbo 57 * frames, highly configurable RX filtering, and 16 RX and TX queues 58 * (which, along with RX filter rules, can be used for QOS applications). 59 * Other features, such as TCP segmentation, may be available as part 60 * of value-added firmware updates. Unlike the Tigon I and Tigon II, 61 * firmware images can be stored in hardware and need not be compiled 62 * into the driver. 63 * 64 * The BCM5700 supports the PCI v2.2 and PCI-X v1.0 standards, and will 65 * function in a 32-bit/64-bit 33/66MHz bus, or a 64-bit/133MHz bus. 66 * 67 * The BCM5701 is a single-chip solution incorporating both the BCM5700 68 * MAC and a BCM5401 10/100/1000 PHY. Unlike the BCM5700, the BCM5701 69 * does not support external SSRAM. 70 * 71 * Broadcom also produces a variation of the BCM5700 under the "Altima" 72 * brand name, which is functionally similar but lacks PCI-X support. 73 * 74 * Without external SSRAM, you can only have at most 4 TX rings, 75 * and the use of the mini RX ring is disabled. This seems to imply 76 * that these features are simply not available on the BCM5701. As a 77 * result, this driver does not implement any support for the mini RX 78 * ring. 79 */ 80 81 #include <sys/cdefs.h> 82 __KERNEL_RCSID(0, "$NetBSD: if_bge.c,v 1.210 2013/03/07 04:42:09 msaitoh Exp $"); 83 84 #include "vlan.h" 85 86 #include <sys/param.h> 87 #include <sys/systm.h> 88 #include <sys/callout.h> 89 #include <sys/sockio.h> 90 #include <sys/mbuf.h> 91 #include <sys/malloc.h> 92 #include <sys/kernel.h> 93 #include <sys/device.h> 94 #include <sys/socket.h> 95 #include <sys/sysctl.h> 96 97 #include <net/if.h> 98 #include <net/if_dl.h> 99 #include <net/if_media.h> 100 #include <net/if_ether.h> 101 102 #include <sys/rnd.h> 103 104 #ifdef INET 105 #include <netinet/in.h> 106 #include <netinet/in_systm.h> 107 #include <netinet/in_var.h> 108 #include <netinet/ip.h> 109 #endif 110 111 /* Headers for TCP Segmentation Offload (TSO) */ 112 #include <netinet/in_systm.h> /* n_time for <netinet/ip.h>... */ 113 #include <netinet/in.h> /* ip_{src,dst}, for <netinet/ip.h> */ 114 #include <netinet/ip.h> /* for struct ip */ 115 #include <netinet/tcp.h> /* for struct tcphdr */ 116 117 118 #include <net/bpf.h> 119 120 #include <dev/pci/pcireg.h> 121 #include <dev/pci/pcivar.h> 122 #include <dev/pci/pcidevs.h> 123 124 #include <dev/mii/mii.h> 125 #include <dev/mii/miivar.h> 126 #include <dev/mii/miidevs.h> 127 #include <dev/mii/brgphyreg.h> 128 129 #include <dev/pci/if_bgereg.h> 130 #include <dev/pci/if_bgevar.h> 131 132 #include <prop/proplib.h> 133 134 #define ETHER_MIN_NOPAD (ETHER_MIN_LEN - ETHER_CRC_LEN) /* i.e., 60 */ 135 136 137 /* 138 * Tunable thresholds for rx-side bge interrupt mitigation. 139 */ 140 141 /* 142 * The pairs of values below were obtained from empirical measurement 143 * on bcm5700 rev B2; they ar designed to give roughly 1 receive 144 * interrupt for every N packets received, where N is, approximately, 145 * the second value (rx_max_bds) in each pair. The values are chosen 146 * such that moving from one pair to the succeeding pair was observed 147 * to roughly halve interrupt rate under sustained input packet load. 148 * The values were empirically chosen to avoid overflowing internal 149 * limits on the bcm5700: increasing rx_ticks much beyond 600 150 * results in internal wrapping and higher interrupt rates. 151 * The limit of 46 frames was chosen to match NFS workloads. 152 * 153 * These values also work well on bcm5701, bcm5704C, and (less 154 * tested) bcm5703. On other chipsets, (including the Altima chip 155 * family), the larger values may overflow internal chip limits, 156 * leading to increasing interrupt rates rather than lower interrupt 157 * rates. 158 * 159 * Applications using heavy interrupt mitigation (interrupting every 160 * 32 or 46 frames) in both directions may need to increase the TCP 161 * windowsize to above 131072 bytes (e.g., to 199608 bytes) to sustain 162 * full link bandwidth, due to ACKs and window updates lingering 163 * in the RX queue during the 30-to-40-frame interrupt-mitigation window. 164 */ 165 static const struct bge_load_rx_thresh { 166 int rx_ticks; 167 int rx_max_bds; } 168 bge_rx_threshes[] = { 169 { 16, 1 }, /* rx_max_bds = 1 disables interrupt mitigation */ 170 { 32, 2 }, 171 { 50, 4 }, 172 { 100, 8 }, 173 { 192, 16 }, 174 { 416, 32 }, 175 { 598, 46 } 176 }; 177 #define NBGE_RX_THRESH (sizeof(bge_rx_threshes) / sizeof(bge_rx_threshes[0])) 178 179 /* XXX patchable; should be sysctl'able */ 180 static int bge_auto_thresh = 1; 181 static int bge_rx_thresh_lvl; 182 183 static int bge_rxthresh_nodenum; 184 185 typedef int (*bge_eaddr_fcn_t)(struct bge_softc *, uint8_t[]); 186 187 static int bge_probe(device_t, cfdata_t, void *); 188 static void bge_attach(device_t, device_t, void *); 189 static void bge_release_resources(struct bge_softc *); 190 191 static int bge_get_eaddr_fw(struct bge_softc *, uint8_t[]); 192 static int bge_get_eaddr_mem(struct bge_softc *, uint8_t[]); 193 static int bge_get_eaddr_nvram(struct bge_softc *, uint8_t[]); 194 static int bge_get_eaddr_eeprom(struct bge_softc *, uint8_t[]); 195 static int bge_get_eaddr(struct bge_softc *, uint8_t[]); 196 197 static void bge_txeof(struct bge_softc *); 198 static void bge_rxeof(struct bge_softc *); 199 200 static void bge_asf_driver_up (struct bge_softc *); 201 static void bge_tick(void *); 202 static void bge_stats_update(struct bge_softc *); 203 static void bge_stats_update_regs(struct bge_softc *); 204 static int bge_encap(struct bge_softc *, struct mbuf *, uint32_t *); 205 206 static int bge_intr(void *); 207 static void bge_start(struct ifnet *); 208 static int bge_ifflags_cb(struct ethercom *); 209 static int bge_ioctl(struct ifnet *, u_long, void *); 210 static int bge_init(struct ifnet *); 211 static void bge_stop(struct ifnet *, int); 212 static void bge_watchdog(struct ifnet *); 213 static int bge_ifmedia_upd(struct ifnet *); 214 static void bge_ifmedia_sts(struct ifnet *, struct ifmediareq *); 215 216 static uint8_t bge_nvram_getbyte(struct bge_softc *, int, uint8_t *); 217 static int bge_read_nvram(struct bge_softc *, uint8_t *, int, int); 218 219 static uint8_t bge_eeprom_getbyte(struct bge_softc *, int, uint8_t *); 220 static int bge_read_eeprom(struct bge_softc *, void *, int, int); 221 static void bge_setmulti(struct bge_softc *); 222 223 static void bge_handle_events(struct bge_softc *); 224 static int bge_alloc_jumbo_mem(struct bge_softc *); 225 #if 0 /* XXX */ 226 static void bge_free_jumbo_mem(struct bge_softc *); 227 #endif 228 static void *bge_jalloc(struct bge_softc *); 229 static void bge_jfree(struct mbuf *, void *, size_t, void *); 230 static int bge_newbuf_std(struct bge_softc *, int, struct mbuf *, 231 bus_dmamap_t); 232 static int bge_newbuf_jumbo(struct bge_softc *, int, struct mbuf *); 233 static int bge_init_rx_ring_std(struct bge_softc *); 234 static void bge_free_rx_ring_std(struct bge_softc *); 235 static int bge_init_rx_ring_jumbo(struct bge_softc *); 236 static void bge_free_rx_ring_jumbo(struct bge_softc *); 237 static void bge_free_tx_ring(struct bge_softc *); 238 static int bge_init_tx_ring(struct bge_softc *); 239 240 static int bge_chipinit(struct bge_softc *); 241 static int bge_blockinit(struct bge_softc *); 242 static int bge_setpowerstate(struct bge_softc *, int); 243 static uint32_t bge_readmem_ind(struct bge_softc *, int); 244 static void bge_writemem_ind(struct bge_softc *, int, int); 245 static void bge_writembx(struct bge_softc *, int, int); 246 static void bge_writemem_direct(struct bge_softc *, int, int); 247 static void bge_writereg_ind(struct bge_softc *, int, int); 248 static void bge_set_max_readrq(struct bge_softc *); 249 250 static int bge_miibus_readreg(device_t, int, int); 251 static void bge_miibus_writereg(device_t, int, int, int); 252 static void bge_miibus_statchg(struct ifnet *); 253 254 #define BGE_RESET_START 1 255 #define BGE_RESET_STOP 2 256 static void bge_sig_post_reset(struct bge_softc *, int); 257 static void bge_sig_legacy(struct bge_softc *, int); 258 static void bge_sig_pre_reset(struct bge_softc *, int); 259 static void bge_stop_fw(struct bge_softc *); 260 static int bge_reset(struct bge_softc *); 261 static void bge_link_upd(struct bge_softc *); 262 static void bge_sysctl_init(struct bge_softc *); 263 static int bge_sysctl_verify(SYSCTLFN_PROTO); 264 265 #ifdef BGE_DEBUG 266 #define DPRINTF(x) if (bgedebug) printf x 267 #define DPRINTFN(n,x) if (bgedebug >= (n)) printf x 268 #define BGE_TSO_PRINTF(x) do { if (bge_tso_debug) printf x ;} while (0) 269 int bgedebug = 0; 270 int bge_tso_debug = 0; 271 void bge_debug_info(struct bge_softc *); 272 #else 273 #define DPRINTF(x) 274 #define DPRINTFN(n,x) 275 #define BGE_TSO_PRINTF(x) 276 #endif 277 278 #ifdef BGE_EVENT_COUNTERS 279 #define BGE_EVCNT_INCR(ev) (ev).ev_count++ 280 #define BGE_EVCNT_ADD(ev, val) (ev).ev_count += (val) 281 #define BGE_EVCNT_UPD(ev, val) (ev).ev_count = (val) 282 #else 283 #define BGE_EVCNT_INCR(ev) /* nothing */ 284 #define BGE_EVCNT_ADD(ev, val) /* nothing */ 285 #define BGE_EVCNT_UPD(ev, val) /* nothing */ 286 #endif 287 288 static const struct bge_product { 289 pci_vendor_id_t bp_vendor; 290 pci_product_id_t bp_product; 291 const char *bp_name; 292 } bge_products[] = { 293 /* 294 * The BCM5700 documentation seems to indicate that the hardware 295 * still has the Alteon vendor ID burned into it, though it 296 * should always be overridden by the value in the EEPROM. We'll 297 * check for it anyway. 298 */ 299 { PCI_VENDOR_ALTEON, 300 PCI_PRODUCT_ALTEON_BCM5700, 301 "Broadcom BCM5700 Gigabit Ethernet", 302 }, 303 { PCI_VENDOR_ALTEON, 304 PCI_PRODUCT_ALTEON_BCM5701, 305 "Broadcom BCM5701 Gigabit Ethernet", 306 }, 307 { PCI_VENDOR_ALTIMA, 308 PCI_PRODUCT_ALTIMA_AC1000, 309 "Altima AC1000 Gigabit Ethernet", 310 }, 311 { PCI_VENDOR_ALTIMA, 312 PCI_PRODUCT_ALTIMA_AC1001, 313 "Altima AC1001 Gigabit Ethernet", 314 }, 315 { PCI_VENDOR_ALTIMA, 316 PCI_PRODUCT_ALTIMA_AC1003, 317 "Altima AC1003 Gigabit Ethernet", 318 }, 319 { PCI_VENDOR_ALTIMA, 320 PCI_PRODUCT_ALTIMA_AC9100, 321 "Altima AC9100 Gigabit Ethernet", 322 }, 323 { PCI_VENDOR_APPLE, 324 PCI_PRODUCT_APPLE_BCM5701, 325 "APPLE BCM5701 Gigabit Ethernet", 326 }, 327 { PCI_VENDOR_BROADCOM, 328 PCI_PRODUCT_BROADCOM_BCM5700, 329 "Broadcom BCM5700 Gigabit Ethernet", 330 }, 331 { PCI_VENDOR_BROADCOM, 332 PCI_PRODUCT_BROADCOM_BCM5701, 333 "Broadcom BCM5701 Gigabit Ethernet", 334 }, 335 { PCI_VENDOR_BROADCOM, 336 PCI_PRODUCT_BROADCOM_BCM5702, 337 "Broadcom BCM5702 Gigabit Ethernet", 338 }, 339 { PCI_VENDOR_BROADCOM, 340 PCI_PRODUCT_BROADCOM_BCM5702X, 341 "Broadcom BCM5702X Gigabit Ethernet" }, 342 { PCI_VENDOR_BROADCOM, 343 PCI_PRODUCT_BROADCOM_BCM5703, 344 "Broadcom BCM5703 Gigabit Ethernet", 345 }, 346 { PCI_VENDOR_BROADCOM, 347 PCI_PRODUCT_BROADCOM_BCM5703X, 348 "Broadcom BCM5703X Gigabit Ethernet", 349 }, 350 { PCI_VENDOR_BROADCOM, 351 PCI_PRODUCT_BROADCOM_BCM5703_ALT, 352 "Broadcom BCM5703 Gigabit Ethernet", 353 }, 354 { PCI_VENDOR_BROADCOM, 355 PCI_PRODUCT_BROADCOM_BCM5704C, 356 "Broadcom BCM5704C Dual Gigabit Ethernet", 357 }, 358 { PCI_VENDOR_BROADCOM, 359 PCI_PRODUCT_BROADCOM_BCM5704S, 360 "Broadcom BCM5704S Dual Gigabit Ethernet", 361 }, 362 { PCI_VENDOR_BROADCOM, 363 PCI_PRODUCT_BROADCOM_BCM5705, 364 "Broadcom BCM5705 Gigabit Ethernet", 365 }, 366 { PCI_VENDOR_BROADCOM, 367 PCI_PRODUCT_BROADCOM_BCM5705F, 368 "Broadcom BCM5705F Gigabit Ethernet", 369 }, 370 { PCI_VENDOR_BROADCOM, 371 PCI_PRODUCT_BROADCOM_BCM5705K, 372 "Broadcom BCM5705K Gigabit Ethernet", 373 }, 374 { PCI_VENDOR_BROADCOM, 375 PCI_PRODUCT_BROADCOM_BCM5705M, 376 "Broadcom BCM5705M Gigabit Ethernet", 377 }, 378 { PCI_VENDOR_BROADCOM, 379 PCI_PRODUCT_BROADCOM_BCM5705M_ALT, 380 "Broadcom BCM5705M Gigabit Ethernet", 381 }, 382 { PCI_VENDOR_BROADCOM, 383 PCI_PRODUCT_BROADCOM_BCM5714, 384 "Broadcom BCM5714 Gigabit Ethernet", 385 }, 386 { PCI_VENDOR_BROADCOM, 387 PCI_PRODUCT_BROADCOM_BCM5714S, 388 "Broadcom BCM5714S Gigabit Ethernet", 389 }, 390 { PCI_VENDOR_BROADCOM, 391 PCI_PRODUCT_BROADCOM_BCM5715, 392 "Broadcom BCM5715 Gigabit Ethernet", 393 }, 394 { PCI_VENDOR_BROADCOM, 395 PCI_PRODUCT_BROADCOM_BCM5715S, 396 "Broadcom BCM5715S Gigabit Ethernet", 397 }, 398 { PCI_VENDOR_BROADCOM, 399 PCI_PRODUCT_BROADCOM_BCM5717, 400 "Broadcom BCM5717 Gigabit Ethernet", 401 }, 402 { PCI_VENDOR_BROADCOM, 403 PCI_PRODUCT_BROADCOM_BCM5718, 404 "Broadcom BCM5718 Gigabit Ethernet", 405 }, 406 { PCI_VENDOR_BROADCOM, 407 PCI_PRODUCT_BROADCOM_BCM5720, 408 "Broadcom BCM5720 Gigabit Ethernet", 409 }, 410 { PCI_VENDOR_BROADCOM, 411 PCI_PRODUCT_BROADCOM_BCM5721, 412 "Broadcom BCM5721 Gigabit Ethernet", 413 }, 414 { PCI_VENDOR_BROADCOM, 415 PCI_PRODUCT_BROADCOM_BCM5722, 416 "Broadcom BCM5722 Gigabit Ethernet", 417 }, 418 { PCI_VENDOR_BROADCOM, 419 PCI_PRODUCT_BROADCOM_BCM5723, 420 "Broadcom BCM5723 Gigabit Ethernet", 421 }, 422 { PCI_VENDOR_BROADCOM, 423 PCI_PRODUCT_BROADCOM_BCM5724, 424 "Broadcom BCM5724 Gigabit Ethernet", 425 }, 426 { PCI_VENDOR_BROADCOM, 427 PCI_PRODUCT_BROADCOM_BCM5750, 428 "Broadcom BCM5750 Gigabit Ethernet", 429 }, 430 { PCI_VENDOR_BROADCOM, 431 PCI_PRODUCT_BROADCOM_BCM5750M, 432 "Broadcom BCM5750M Gigabit Ethernet", 433 }, 434 { PCI_VENDOR_BROADCOM, 435 PCI_PRODUCT_BROADCOM_BCM5751, 436 "Broadcom BCM5751 Gigabit Ethernet", 437 }, 438 { PCI_VENDOR_BROADCOM, 439 PCI_PRODUCT_BROADCOM_BCM5751F, 440 "Broadcom BCM5751F Gigabit Ethernet", 441 }, 442 { PCI_VENDOR_BROADCOM, 443 PCI_PRODUCT_BROADCOM_BCM5751M, 444 "Broadcom BCM5751M Gigabit Ethernet", 445 }, 446 { PCI_VENDOR_BROADCOM, 447 PCI_PRODUCT_BROADCOM_BCM5752, 448 "Broadcom BCM5752 Gigabit Ethernet", 449 }, 450 { PCI_VENDOR_BROADCOM, 451 PCI_PRODUCT_BROADCOM_BCM5752M, 452 "Broadcom BCM5752M Gigabit Ethernet", 453 }, 454 { PCI_VENDOR_BROADCOM, 455 PCI_PRODUCT_BROADCOM_BCM5753, 456 "Broadcom BCM5753 Gigabit Ethernet", 457 }, 458 { PCI_VENDOR_BROADCOM, 459 PCI_PRODUCT_BROADCOM_BCM5753F, 460 "Broadcom BCM5753F Gigabit Ethernet", 461 }, 462 { PCI_VENDOR_BROADCOM, 463 PCI_PRODUCT_BROADCOM_BCM5753M, 464 "Broadcom BCM5753M Gigabit Ethernet", 465 }, 466 { PCI_VENDOR_BROADCOM, 467 PCI_PRODUCT_BROADCOM_BCM5754, 468 "Broadcom BCM5754 Gigabit Ethernet", 469 }, 470 { PCI_VENDOR_BROADCOM, 471 PCI_PRODUCT_BROADCOM_BCM5754M, 472 "Broadcom BCM5754M Gigabit Ethernet", 473 }, 474 { PCI_VENDOR_BROADCOM, 475 PCI_PRODUCT_BROADCOM_BCM5755, 476 "Broadcom BCM5755 Gigabit Ethernet", 477 }, 478 { PCI_VENDOR_BROADCOM, 479 PCI_PRODUCT_BROADCOM_BCM5755M, 480 "Broadcom BCM5755M Gigabit Ethernet", 481 }, 482 { PCI_VENDOR_BROADCOM, 483 PCI_PRODUCT_BROADCOM_BCM5756, 484 "Broadcom BCM5756 Gigabit Ethernet", 485 }, 486 { PCI_VENDOR_BROADCOM, 487 PCI_PRODUCT_BROADCOM_BCM5761, 488 "Broadcom BCM5761 Gigabit Ethernet", 489 }, 490 { PCI_VENDOR_BROADCOM, 491 PCI_PRODUCT_BROADCOM_BCM5761E, 492 "Broadcom BCM5761E Gigabit Ethernet", 493 }, 494 { PCI_VENDOR_BROADCOM, 495 PCI_PRODUCT_BROADCOM_BCM5761S, 496 "Broadcom BCM5761S Gigabit Ethernet", 497 }, 498 { PCI_VENDOR_BROADCOM, 499 PCI_PRODUCT_BROADCOM_BCM5761SE, 500 "Broadcom BCM5761SE Gigabit Ethernet", 501 }, 502 { PCI_VENDOR_BROADCOM, 503 PCI_PRODUCT_BROADCOM_BCM5764, 504 "Broadcom BCM5764 Gigabit Ethernet", 505 }, 506 { PCI_VENDOR_BROADCOM, 507 PCI_PRODUCT_BROADCOM_BCM5780, 508 "Broadcom BCM5780 Gigabit Ethernet", 509 }, 510 { PCI_VENDOR_BROADCOM, 511 PCI_PRODUCT_BROADCOM_BCM5780S, 512 "Broadcom BCM5780S Gigabit Ethernet", 513 }, 514 { PCI_VENDOR_BROADCOM, 515 PCI_PRODUCT_BROADCOM_BCM5781, 516 "Broadcom BCM5781 Gigabit Ethernet", 517 }, 518 { PCI_VENDOR_BROADCOM, 519 PCI_PRODUCT_BROADCOM_BCM5782, 520 "Broadcom BCM5782 Gigabit Ethernet", 521 }, 522 { PCI_VENDOR_BROADCOM, 523 PCI_PRODUCT_BROADCOM_BCM5784M, 524 "BCM5784M NetLink 1000baseT Ethernet", 525 }, 526 { PCI_VENDOR_BROADCOM, 527 PCI_PRODUCT_BROADCOM_BCM5785F, 528 "BCM5785F NetLink 10/100 Ethernet", 529 }, 530 { PCI_VENDOR_BROADCOM, 531 PCI_PRODUCT_BROADCOM_BCM5785G, 532 "BCM5785G NetLink 1000baseT Ethernet", 533 }, 534 { PCI_VENDOR_BROADCOM, 535 PCI_PRODUCT_BROADCOM_BCM5786, 536 "Broadcom BCM5786 Gigabit Ethernet", 537 }, 538 { PCI_VENDOR_BROADCOM, 539 PCI_PRODUCT_BROADCOM_BCM5787, 540 "Broadcom BCM5787 Gigabit Ethernet", 541 }, 542 { PCI_VENDOR_BROADCOM, 543 PCI_PRODUCT_BROADCOM_BCM5787F, 544 "Broadcom BCM5787F 10/100 Ethernet", 545 }, 546 { PCI_VENDOR_BROADCOM, 547 PCI_PRODUCT_BROADCOM_BCM5787M, 548 "Broadcom BCM5787M Gigabit Ethernet", 549 }, 550 { PCI_VENDOR_BROADCOM, 551 PCI_PRODUCT_BROADCOM_BCM5788, 552 "Broadcom BCM5788 Gigabit Ethernet", 553 }, 554 { PCI_VENDOR_BROADCOM, 555 PCI_PRODUCT_BROADCOM_BCM5789, 556 "Broadcom BCM5789 Gigabit Ethernet", 557 }, 558 { PCI_VENDOR_BROADCOM, 559 PCI_PRODUCT_BROADCOM_BCM5901, 560 "Broadcom BCM5901 Fast Ethernet", 561 }, 562 { PCI_VENDOR_BROADCOM, 563 PCI_PRODUCT_BROADCOM_BCM5901A2, 564 "Broadcom BCM5901A2 Fast Ethernet", 565 }, 566 { PCI_VENDOR_BROADCOM, 567 PCI_PRODUCT_BROADCOM_BCM5903M, 568 "Broadcom BCM5903M Fast Ethernet", 569 }, 570 { PCI_VENDOR_BROADCOM, 571 PCI_PRODUCT_BROADCOM_BCM5906, 572 "Broadcom BCM5906 Fast Ethernet", 573 }, 574 { PCI_VENDOR_BROADCOM, 575 PCI_PRODUCT_BROADCOM_BCM5906M, 576 "Broadcom BCM5906M Fast Ethernet", 577 }, 578 { PCI_VENDOR_BROADCOM, 579 PCI_PRODUCT_BROADCOM_BCM57760, 580 "Broadcom BCM57760 Fast Ethernet", 581 }, 582 { PCI_VENDOR_BROADCOM, 583 PCI_PRODUCT_BROADCOM_BCM57761, 584 "Broadcom BCM57761 Fast Ethernet", 585 }, 586 { PCI_VENDOR_BROADCOM, 587 PCI_PRODUCT_BROADCOM_BCM57762, 588 "Broadcom BCM57762 Gigabit Ethernet", 589 }, 590 { PCI_VENDOR_BROADCOM, 591 PCI_PRODUCT_BROADCOM_BCM57765, 592 "Broadcom BCM57765 Fast Ethernet", 593 }, 594 { PCI_VENDOR_BROADCOM, 595 PCI_PRODUCT_BROADCOM_BCM57780, 596 "Broadcom BCM57780 Fast Ethernet", 597 }, 598 { PCI_VENDOR_BROADCOM, 599 PCI_PRODUCT_BROADCOM_BCM57781, 600 "Broadcom BCM57781 Fast Ethernet", 601 }, 602 { PCI_VENDOR_BROADCOM, 603 PCI_PRODUCT_BROADCOM_BCM57785, 604 "Broadcom BCM57785 Fast Ethernet", 605 }, 606 { PCI_VENDOR_BROADCOM, 607 PCI_PRODUCT_BROADCOM_BCM57788, 608 "Broadcom BCM57788 Fast Ethernet", 609 }, 610 { PCI_VENDOR_BROADCOM, 611 PCI_PRODUCT_BROADCOM_BCM57790, 612 "Broadcom BCM57790 Fast Ethernet", 613 }, 614 { PCI_VENDOR_BROADCOM, 615 PCI_PRODUCT_BROADCOM_BCM57791, 616 "Broadcom BCM57791 Fast Ethernet", 617 }, 618 { PCI_VENDOR_BROADCOM, 619 PCI_PRODUCT_BROADCOM_BCM57795, 620 "Broadcom BCM57795 Fast Ethernet", 621 }, 622 { PCI_VENDOR_SCHNEIDERKOCH, 623 PCI_PRODUCT_SCHNEIDERKOCH_SK_9DX1, 624 "SysKonnect SK-9Dx1 Gigabit Ethernet", 625 }, 626 { PCI_VENDOR_3COM, 627 PCI_PRODUCT_3COM_3C996, 628 "3Com 3c996 Gigabit Ethernet", 629 }, 630 { PCI_VENDOR_FUJITSU4, 631 PCI_PRODUCT_FUJITSU4_PW008GE4, 632 "Fujitsu PW008GE4 Gigabit Ethernet", 633 }, 634 { PCI_VENDOR_FUJITSU4, 635 PCI_PRODUCT_FUJITSU4_PW008GE5, 636 "Fujitsu PW008GE5 Gigabit Ethernet", 637 }, 638 { PCI_VENDOR_FUJITSU4, 639 PCI_PRODUCT_FUJITSU4_PP250_450_LAN, 640 "Fujitsu Primepower 250/450 Gigabit Ethernet", 641 }, 642 { 0, 643 0, 644 NULL }, 645 }; 646 647 #define BGE_IS_5700_FAMILY(sc) ((sc)->bge_flags & BGE_5700_FAMILY) 648 #define BGE_IS_5714_FAMILY(sc) ((sc)->bge_flags & BGE_5714_FAMILY) 649 #define BGE_IS_5705_PLUS(sc) ((sc)->bge_flags & BGE_5705_PLUS) 650 #define BGE_IS_575X_PLUS(sc) ((sc)->bge_flags & BGE_575X_PLUS) 651 #define BGE_IS_5755_PLUS(sc) ((sc)->bge_flags & BGE_5755_PLUS) 652 #define BGE_IS_JUMBO_CAPABLE(sc) ((sc)->bge_flags & BGE_JUMBO_CAPABLE) 653 654 static const struct bge_revision { 655 uint32_t br_chipid; 656 const char *br_name; 657 } bge_revisions[] = { 658 { BGE_CHIPID_BCM5700_A0, "BCM5700 A0" }, 659 { BGE_CHIPID_BCM5700_A1, "BCM5700 A1" }, 660 { BGE_CHIPID_BCM5700_B0, "BCM5700 B0" }, 661 { BGE_CHIPID_BCM5700_B1, "BCM5700 B1" }, 662 { BGE_CHIPID_BCM5700_B2, "BCM5700 B2" }, 663 { BGE_CHIPID_BCM5700_B3, "BCM5700 B3" }, 664 /* This is treated like a BCM5700 Bx */ 665 { BGE_CHIPID_BCM5700_ALTIMA, "BCM5700 Altima" }, 666 { BGE_CHIPID_BCM5700_C0, "BCM5700 C0" }, 667 { BGE_CHIPID_BCM5701_A0, "BCM5701 A0" }, 668 { BGE_CHIPID_BCM5701_B0, "BCM5701 B0" }, 669 { BGE_CHIPID_BCM5701_B2, "BCM5701 B2" }, 670 { BGE_CHIPID_BCM5701_B5, "BCM5701 B5" }, 671 { BGE_CHIPID_BCM5703_A0, "BCM5702/5703 A0" }, 672 { BGE_CHIPID_BCM5703_A1, "BCM5702/5703 A1" }, 673 { BGE_CHIPID_BCM5703_A2, "BCM5702/5703 A2" }, 674 { BGE_CHIPID_BCM5703_A3, "BCM5702/5703 A3" }, 675 { BGE_CHIPID_BCM5703_B0, "BCM5702/5703 B0" }, 676 { BGE_CHIPID_BCM5704_A0, "BCM5704 A0" }, 677 { BGE_CHIPID_BCM5704_A1, "BCM5704 A1" }, 678 { BGE_CHIPID_BCM5704_A2, "BCM5704 A2" }, 679 { BGE_CHIPID_BCM5704_A3, "BCM5704 A3" }, 680 { BGE_CHIPID_BCM5704_B0, "BCM5704 B0" }, 681 { BGE_CHIPID_BCM5705_A0, "BCM5705 A0" }, 682 { BGE_CHIPID_BCM5705_A1, "BCM5705 A1" }, 683 { BGE_CHIPID_BCM5705_A2, "BCM5705 A2" }, 684 { BGE_CHIPID_BCM5705_A3, "BCM5705 A3" }, 685 { BGE_CHIPID_BCM5750_A0, "BCM5750 A0" }, 686 { BGE_CHIPID_BCM5750_A1, "BCM5750 A1" }, 687 { BGE_CHIPID_BCM5750_A3, "BCM5750 A3" }, 688 { BGE_CHIPID_BCM5750_B0, "BCM5750 B0" }, 689 { BGE_CHIPID_BCM5750_B1, "BCM5750 B1" }, 690 { BGE_CHIPID_BCM5750_C0, "BCM5750 C0" }, 691 { BGE_CHIPID_BCM5750_C1, "BCM5750 C1" }, 692 { BGE_CHIPID_BCM5750_C2, "BCM5750 C2" }, 693 { BGE_CHIPID_BCM5752_A0, "BCM5752 A0" }, 694 { BGE_CHIPID_BCM5752_A1, "BCM5752 A1" }, 695 { BGE_CHIPID_BCM5752_A2, "BCM5752 A2" }, 696 { BGE_CHIPID_BCM5714_A0, "BCM5714 A0" }, 697 { BGE_CHIPID_BCM5714_B0, "BCM5714 B0" }, 698 { BGE_CHIPID_BCM5714_B3, "BCM5714 B3" }, 699 { BGE_CHIPID_BCM5715_A0, "BCM5715 A0" }, 700 { BGE_CHIPID_BCM5715_A1, "BCM5715 A1" }, 701 { BGE_CHIPID_BCM5715_A3, "BCM5715 A3" }, 702 { BGE_CHIPID_BCM5755_A0, "BCM5755 A0" }, 703 { BGE_CHIPID_BCM5755_A1, "BCM5755 A1" }, 704 { BGE_CHIPID_BCM5755_A2, "BCM5755 A2" }, 705 { BGE_CHIPID_BCM5755_C0, "BCM5755 C0" }, 706 { BGE_CHIPID_BCM5761_A0, "BCM5761 A0" }, 707 { BGE_CHIPID_BCM5761_A1, "BCM5761 A1" }, 708 { BGE_CHIPID_BCM5784_A0, "BCM5784 A0" }, 709 { BGE_CHIPID_BCM5784_A1, "BCM5784 A1" }, 710 /* 5754 and 5787 share the same ASIC ID */ 711 { BGE_CHIPID_BCM5787_A0, "BCM5754/5787 A0" }, 712 { BGE_CHIPID_BCM5787_A1, "BCM5754/5787 A1" }, 713 { BGE_CHIPID_BCM5787_A2, "BCM5754/5787 A2" }, 714 { BGE_CHIPID_BCM5906_A0, "BCM5906 A0" }, 715 { BGE_CHIPID_BCM5906_A1, "BCM5906 A1" }, 716 { BGE_CHIPID_BCM5906_A2, "BCM5906 A2" }, 717 { BGE_CHIPID_BCM57780_A0, "BCM57780 A0" }, 718 { BGE_CHIPID_BCM57780_A1, "BCM57780 A1" }, 719 720 { 0, NULL } 721 }; 722 723 /* 724 * Some defaults for major revisions, so that newer steppings 725 * that we don't know about have a shot at working. 726 */ 727 static const struct bge_revision bge_majorrevs[] = { 728 { BGE_ASICREV_BCM5700, "unknown BCM5700" }, 729 { BGE_ASICREV_BCM5701, "unknown BCM5701" }, 730 { BGE_ASICREV_BCM5703, "unknown BCM5703" }, 731 { BGE_ASICREV_BCM5704, "unknown BCM5704" }, 732 { BGE_ASICREV_BCM5705, "unknown BCM5705" }, 733 { BGE_ASICREV_BCM5750, "unknown BCM5750" }, 734 { BGE_ASICREV_BCM5714_A0, "unknown BCM5714" }, 735 { BGE_ASICREV_BCM5752, "unknown BCM5752" }, 736 { BGE_ASICREV_BCM5780, "unknown BCM5780" }, 737 { BGE_ASICREV_BCM5714, "unknown BCM5714" }, 738 { BGE_ASICREV_BCM5755, "unknown BCM5755" }, 739 { BGE_ASICREV_BCM5761, "unknown BCM5761" }, 740 { BGE_ASICREV_BCM5784, "unknown BCM5784" }, 741 { BGE_ASICREV_BCM5785, "unknown BCM5785" }, 742 /* 5754 and 5787 share the same ASIC ID */ 743 { BGE_ASICREV_BCM5787, "unknown BCM5754/5787" }, 744 { BGE_ASICREV_BCM5906, "unknown BCM5906" }, 745 { BGE_ASICREV_BCM57780, "unknown BCM57780" }, 746 { BGE_ASICREV_BCM5717, "unknown BCM5717" }, 747 { BGE_ASICREV_BCM57765, "unknown BCM57765" }, 748 { BGE_ASICREV_BCM57766, "unknown BCM57766" }, 749 750 { 0, NULL } 751 }; 752 753 static int bge_allow_asf = 1; 754 755 CFATTACH_DECL_NEW(bge, sizeof(struct bge_softc), 756 bge_probe, bge_attach, NULL, NULL); 757 758 static uint32_t 759 bge_readmem_ind(struct bge_softc *sc, int off) 760 { 761 pcireg_t val; 762 763 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_BASEADDR, off); 764 val = pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_DATA); 765 return val; 766 } 767 768 static void 769 bge_writemem_ind(struct bge_softc *sc, int off, int val) 770 { 771 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_BASEADDR, off); 772 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_DATA, val); 773 } 774 775 /* 776 * PCI Express only 777 */ 778 static void 779 bge_set_max_readrq(struct bge_softc *sc) 780 { 781 pcireg_t val; 782 783 val = pci_conf_read(sc->sc_pc, sc->sc_pcitag, sc->bge_pciecap 784 + PCI_PCIE_DCSR); 785 if ((val & PCI_PCIE_DCSR_MAX_READ_REQ) != 786 BGE_PCIE_DEVCTL_MAX_READRQ_4096) { 787 aprint_verbose_dev(sc->bge_dev, 788 "adjust device control 0x%04x ", val); 789 val &= ~PCI_PCIE_DCSR_MAX_READ_REQ; 790 val |= BGE_PCIE_DEVCTL_MAX_READRQ_4096; 791 pci_conf_write(sc->sc_pc, sc->sc_pcitag, sc->bge_pciecap 792 + PCI_PCIE_DCSR, val); 793 aprint_verbose("-> 0x%04x\n", val); 794 } 795 } 796 797 #ifdef notdef 798 static uint32_t 799 bge_readreg_ind(struct bge_softc *sc, int off) 800 { 801 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_REG_BASEADDR, off); 802 return (pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_REG_DATA)); 803 } 804 #endif 805 806 static void 807 bge_writereg_ind(struct bge_softc *sc, int off, int val) 808 { 809 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_REG_BASEADDR, off); 810 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_REG_DATA, val); 811 } 812 813 static void 814 bge_writemem_direct(struct bge_softc *sc, int off, int val) 815 { 816 CSR_WRITE_4(sc, off, val); 817 } 818 819 static void 820 bge_writembx(struct bge_softc *sc, int off, int val) 821 { 822 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 823 off += BGE_LPMBX_IRQ0_HI - BGE_MBX_IRQ0_HI; 824 825 CSR_WRITE_4(sc, off, val); 826 } 827 828 static uint8_t 829 bge_nvram_getbyte(struct bge_softc *sc, int addr, uint8_t *dest) 830 { 831 uint32_t access, byte = 0; 832 int i; 833 834 /* Lock. */ 835 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_SET1); 836 for (i = 0; i < 8000; i++) { 837 if (CSR_READ_4(sc, BGE_NVRAM_SWARB) & BGE_NVRAMSWARB_GNT1) 838 break; 839 DELAY(20); 840 } 841 if (i == 8000) 842 return 1; 843 844 /* Enable access. */ 845 access = CSR_READ_4(sc, BGE_NVRAM_ACCESS); 846 CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access | BGE_NVRAMACC_ENABLE); 847 848 CSR_WRITE_4(sc, BGE_NVRAM_ADDR, addr & 0xfffffffc); 849 CSR_WRITE_4(sc, BGE_NVRAM_CMD, BGE_NVRAM_READCMD); 850 for (i = 0; i < BGE_TIMEOUT * 10; i++) { 851 DELAY(10); 852 if (CSR_READ_4(sc, BGE_NVRAM_CMD) & BGE_NVRAMCMD_DONE) { 853 DELAY(10); 854 break; 855 } 856 } 857 858 if (i == BGE_TIMEOUT * 10) { 859 aprint_error_dev(sc->bge_dev, "nvram read timed out\n"); 860 return 1; 861 } 862 863 /* Get result. */ 864 byte = CSR_READ_4(sc, BGE_NVRAM_RDDATA); 865 866 *dest = (bswap32(byte) >> ((addr % 4) * 8)) & 0xFF; 867 868 /* Disable access. */ 869 CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access); 870 871 /* Unlock. */ 872 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_CLR1); 873 CSR_READ_4(sc, BGE_NVRAM_SWARB); 874 875 return 0; 876 } 877 878 /* 879 * Read a sequence of bytes from NVRAM. 880 */ 881 static int 882 bge_read_nvram(struct bge_softc *sc, uint8_t *dest, int off, int cnt) 883 { 884 int error = 0, i; 885 uint8_t byte = 0; 886 887 if (BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5906) 888 return 1; 889 890 for (i = 0; i < cnt; i++) { 891 error = bge_nvram_getbyte(sc, off + i, &byte); 892 if (error) 893 break; 894 *(dest + i) = byte; 895 } 896 897 return (error ? 1 : 0); 898 } 899 900 /* 901 * Read a byte of data stored in the EEPROM at address 'addr.' The 902 * BCM570x supports both the traditional bitbang interface and an 903 * auto access interface for reading the EEPROM. We use the auto 904 * access method. 905 */ 906 static uint8_t 907 bge_eeprom_getbyte(struct bge_softc *sc, int addr, uint8_t *dest) 908 { 909 int i; 910 uint32_t byte = 0; 911 912 /* 913 * Enable use of auto EEPROM access so we can avoid 914 * having to use the bitbang method. 915 */ 916 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM); 917 918 /* Reset the EEPROM, load the clock period. */ 919 CSR_WRITE_4(sc, BGE_EE_ADDR, 920 BGE_EEADDR_RESET | BGE_EEHALFCLK(BGE_HALFCLK_384SCL)); 921 DELAY(20); 922 923 /* Issue the read EEPROM command. */ 924 CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr); 925 926 /* Wait for completion */ 927 for (i = 0; i < BGE_TIMEOUT * 10; i++) { 928 DELAY(10); 929 if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE) 930 break; 931 } 932 933 if (i == BGE_TIMEOUT * 10) { 934 aprint_error_dev(sc->bge_dev, "eeprom read timed out\n"); 935 return 1; 936 } 937 938 /* Get result. */ 939 byte = CSR_READ_4(sc, BGE_EE_DATA); 940 941 *dest = (byte >> ((addr % 4) * 8)) & 0xFF; 942 943 return 0; 944 } 945 946 /* 947 * Read a sequence of bytes from the EEPROM. 948 */ 949 static int 950 bge_read_eeprom(struct bge_softc *sc, void *destv, int off, int cnt) 951 { 952 int error = 0, i; 953 uint8_t byte = 0; 954 char *dest = destv; 955 956 for (i = 0; i < cnt; i++) { 957 error = bge_eeprom_getbyte(sc, off + i, &byte); 958 if (error) 959 break; 960 *(dest + i) = byte; 961 } 962 963 return (error ? 1 : 0); 964 } 965 966 static int 967 bge_miibus_readreg(device_t dev, int phy, int reg) 968 { 969 struct bge_softc *sc = device_private(dev); 970 uint32_t val; 971 uint32_t autopoll; 972 int i; 973 974 /* 975 * Broadcom's own driver always assumes the internal 976 * PHY is at GMII address 1. On some chips, the PHY responds 977 * to accesses at all addresses, which could cause us to 978 * bogusly attach the PHY 32 times at probe type. Always 979 * restricting the lookup to address 1 is simpler than 980 * trying to figure out which chips revisions should be 981 * special-cased. 982 */ 983 if (phy != 1) 984 return 0; 985 986 /* Reading with autopolling on may trigger PCI errors */ 987 autopoll = CSR_READ_4(sc, BGE_MI_MODE); 988 if (autopoll & BGE_MIMODE_AUTOPOLL) { 989 BGE_STS_CLRBIT(sc, BGE_STS_AUTOPOLL); 990 BGE_CLRBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 991 DELAY(40); 992 } 993 994 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_READ | BGE_MICOMM_BUSY | 995 BGE_MIPHY(phy) | BGE_MIREG(reg)); 996 997 for (i = 0; i < BGE_TIMEOUT; i++) { 998 val = CSR_READ_4(sc, BGE_MI_COMM); 999 if (!(val & BGE_MICOMM_BUSY)) 1000 break; 1001 delay(10); 1002 } 1003 1004 if (i == BGE_TIMEOUT) { 1005 aprint_error_dev(sc->bge_dev, "PHY read timed out\n"); 1006 val = 0; 1007 goto done; 1008 } 1009 1010 val = CSR_READ_4(sc, BGE_MI_COMM); 1011 1012 done: 1013 if (autopoll & BGE_MIMODE_AUTOPOLL) { 1014 BGE_STS_SETBIT(sc, BGE_STS_AUTOPOLL); 1015 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 1016 DELAY(40); 1017 } 1018 1019 if (val & BGE_MICOMM_READFAIL) 1020 return 0; 1021 1022 return (val & 0xFFFF); 1023 } 1024 1025 static void 1026 bge_miibus_writereg(device_t dev, int phy, int reg, int val) 1027 { 1028 struct bge_softc *sc = device_private(dev); 1029 uint32_t autopoll; 1030 int i; 1031 1032 if (phy!=1) { 1033 return; 1034 } 1035 1036 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906 && 1037 (reg == BRGPHY_MII_1000CTL || reg == BRGPHY_MII_AUXCTL)) 1038 return; 1039 1040 /* Reading with autopolling on may trigger PCI errors */ 1041 autopoll = CSR_READ_4(sc, BGE_MI_MODE); 1042 if (autopoll & BGE_MIMODE_AUTOPOLL) { 1043 delay(40); 1044 BGE_STS_CLRBIT(sc, BGE_STS_AUTOPOLL); 1045 BGE_CLRBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 1046 delay(10); /* 40 usec is supposed to be adequate */ 1047 } 1048 1049 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_WRITE | BGE_MICOMM_BUSY | 1050 BGE_MIPHY(phy) | BGE_MIREG(reg) | val); 1051 1052 for (i = 0; i < BGE_TIMEOUT; i++) { 1053 delay(10); 1054 if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY)) { 1055 delay(5); 1056 CSR_READ_4(sc, BGE_MI_COMM); 1057 break; 1058 } 1059 } 1060 1061 if (autopoll & BGE_MIMODE_AUTOPOLL) { 1062 BGE_STS_SETBIT(sc, BGE_STS_AUTOPOLL); 1063 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 1064 delay(40); 1065 } 1066 1067 if (i == BGE_TIMEOUT) 1068 aprint_error_dev(sc->bge_dev, "PHY read timed out\n"); 1069 } 1070 1071 static void 1072 bge_miibus_statchg(struct ifnet *ifp) 1073 { 1074 struct bge_softc *sc = ifp->if_softc; 1075 struct mii_data *mii = &sc->bge_mii; 1076 1077 /* 1078 * Get flow control negotiation result. 1079 */ 1080 if (IFM_SUBTYPE(mii->mii_media.ifm_cur->ifm_media) == IFM_AUTO && 1081 (mii->mii_media_active & IFM_ETH_FMASK) != sc->bge_flowflags) { 1082 sc->bge_flowflags = mii->mii_media_active & IFM_ETH_FMASK; 1083 mii->mii_media_active &= ~IFM_ETH_FMASK; 1084 } 1085 1086 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_PORTMODE); 1087 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T || 1088 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX) 1089 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_GMII); 1090 else 1091 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_MII); 1092 1093 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) 1094 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX); 1095 else 1096 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX); 1097 1098 /* 1099 * 802.3x flow control 1100 */ 1101 if (sc->bge_flowflags & IFM_ETH_RXPAUSE) 1102 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_FLOWCTL_ENABLE); 1103 else 1104 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_FLOWCTL_ENABLE); 1105 1106 if (sc->bge_flowflags & IFM_ETH_TXPAUSE) 1107 BGE_SETBIT(sc, BGE_TX_MODE, BGE_TXMODE_FLOWCTL_ENABLE); 1108 else 1109 BGE_CLRBIT(sc, BGE_TX_MODE, BGE_TXMODE_FLOWCTL_ENABLE); 1110 } 1111 1112 /* 1113 * Update rx threshold levels to values in a particular slot 1114 * of the interrupt-mitigation table bge_rx_threshes. 1115 */ 1116 static void 1117 bge_set_thresh(struct ifnet *ifp, int lvl) 1118 { 1119 struct bge_softc *sc = ifp->if_softc; 1120 int s; 1121 1122 /* For now, just save the new Rx-intr thresholds and record 1123 * that a threshold update is pending. Updating the hardware 1124 * registers here (even at splhigh()) is observed to 1125 * occasionaly cause glitches where Rx-interrupts are not 1126 * honoured for up to 10 seconds. jonathan (at) NetBSD.org, 2003-04-05 1127 */ 1128 s = splnet(); 1129 sc->bge_rx_coal_ticks = bge_rx_threshes[lvl].rx_ticks; 1130 sc->bge_rx_max_coal_bds = bge_rx_threshes[lvl].rx_max_bds; 1131 sc->bge_pending_rxintr_change = 1; 1132 splx(s); 1133 } 1134 1135 1136 /* 1137 * Update Rx thresholds of all bge devices 1138 */ 1139 static void 1140 bge_update_all_threshes(int lvl) 1141 { 1142 struct ifnet *ifp; 1143 const char * const namebuf = "bge"; 1144 int namelen; 1145 1146 if (lvl < 0) 1147 lvl = 0; 1148 else if (lvl >= NBGE_RX_THRESH) 1149 lvl = NBGE_RX_THRESH - 1; 1150 1151 namelen = strlen(namebuf); 1152 /* 1153 * Now search all the interfaces for this name/number 1154 */ 1155 IFNET_FOREACH(ifp) { 1156 if (strncmp(ifp->if_xname, namebuf, namelen) != 0) 1157 continue; 1158 /* We got a match: update if doing auto-threshold-tuning */ 1159 if (bge_auto_thresh) 1160 bge_set_thresh(ifp, lvl); 1161 } 1162 } 1163 1164 /* 1165 * Handle events that have triggered interrupts. 1166 */ 1167 static void 1168 bge_handle_events(struct bge_softc *sc) 1169 { 1170 1171 return; 1172 } 1173 1174 /* 1175 * Memory management for jumbo frames. 1176 */ 1177 1178 static int 1179 bge_alloc_jumbo_mem(struct bge_softc *sc) 1180 { 1181 char *ptr, *kva; 1182 bus_dma_segment_t seg; 1183 int i, rseg, state, error; 1184 struct bge_jpool_entry *entry; 1185 1186 state = error = 0; 1187 1188 /* Grab a big chunk o' storage. */ 1189 if (bus_dmamem_alloc(sc->bge_dmatag, BGE_JMEM, PAGE_SIZE, 0, 1190 &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 1191 aprint_error_dev(sc->bge_dev, "can't alloc rx buffers\n"); 1192 return ENOBUFS; 1193 } 1194 1195 state = 1; 1196 if (bus_dmamem_map(sc->bge_dmatag, &seg, rseg, BGE_JMEM, (void **)&kva, 1197 BUS_DMA_NOWAIT)) { 1198 aprint_error_dev(sc->bge_dev, 1199 "can't map DMA buffers (%d bytes)\n", (int)BGE_JMEM); 1200 error = ENOBUFS; 1201 goto out; 1202 } 1203 1204 state = 2; 1205 if (bus_dmamap_create(sc->bge_dmatag, BGE_JMEM, 1, BGE_JMEM, 0, 1206 BUS_DMA_NOWAIT, &sc->bge_cdata.bge_rx_jumbo_map)) { 1207 aprint_error_dev(sc->bge_dev, "can't create DMA map\n"); 1208 error = ENOBUFS; 1209 goto out; 1210 } 1211 1212 state = 3; 1213 if (bus_dmamap_load(sc->bge_dmatag, sc->bge_cdata.bge_rx_jumbo_map, 1214 kva, BGE_JMEM, NULL, BUS_DMA_NOWAIT)) { 1215 aprint_error_dev(sc->bge_dev, "can't load DMA map\n"); 1216 error = ENOBUFS; 1217 goto out; 1218 } 1219 1220 state = 4; 1221 sc->bge_cdata.bge_jumbo_buf = (void *)kva; 1222 DPRINTFN(1,("bge_jumbo_buf = %p\n", sc->bge_cdata.bge_jumbo_buf)); 1223 1224 SLIST_INIT(&sc->bge_jfree_listhead); 1225 SLIST_INIT(&sc->bge_jinuse_listhead); 1226 1227 /* 1228 * Now divide it up into 9K pieces and save the addresses 1229 * in an array. 1230 */ 1231 ptr = sc->bge_cdata.bge_jumbo_buf; 1232 for (i = 0; i < BGE_JSLOTS; i++) { 1233 sc->bge_cdata.bge_jslots[i] = ptr; 1234 ptr += BGE_JLEN; 1235 entry = malloc(sizeof(struct bge_jpool_entry), 1236 M_DEVBUF, M_NOWAIT); 1237 if (entry == NULL) { 1238 aprint_error_dev(sc->bge_dev, 1239 "no memory for jumbo buffer queue!\n"); 1240 error = ENOBUFS; 1241 goto out; 1242 } 1243 entry->slot = i; 1244 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, 1245 entry, jpool_entries); 1246 } 1247 out: 1248 if (error != 0) { 1249 switch (state) { 1250 case 4: 1251 bus_dmamap_unload(sc->bge_dmatag, 1252 sc->bge_cdata.bge_rx_jumbo_map); 1253 case 3: 1254 bus_dmamap_destroy(sc->bge_dmatag, 1255 sc->bge_cdata.bge_rx_jumbo_map); 1256 case 2: 1257 bus_dmamem_unmap(sc->bge_dmatag, kva, BGE_JMEM); 1258 case 1: 1259 bus_dmamem_free(sc->bge_dmatag, &seg, rseg); 1260 break; 1261 default: 1262 break; 1263 } 1264 } 1265 1266 return error; 1267 } 1268 1269 /* 1270 * Allocate a jumbo buffer. 1271 */ 1272 static void * 1273 bge_jalloc(struct bge_softc *sc) 1274 { 1275 struct bge_jpool_entry *entry; 1276 1277 entry = SLIST_FIRST(&sc->bge_jfree_listhead); 1278 1279 if (entry == NULL) { 1280 aprint_error_dev(sc->bge_dev, "no free jumbo buffers\n"); 1281 return NULL; 1282 } 1283 1284 SLIST_REMOVE_HEAD(&sc->bge_jfree_listhead, jpool_entries); 1285 SLIST_INSERT_HEAD(&sc->bge_jinuse_listhead, entry, jpool_entries); 1286 return (sc->bge_cdata.bge_jslots[entry->slot]); 1287 } 1288 1289 /* 1290 * Release a jumbo buffer. 1291 */ 1292 static void 1293 bge_jfree(struct mbuf *m, void *buf, size_t size, void *arg) 1294 { 1295 struct bge_jpool_entry *entry; 1296 struct bge_softc *sc; 1297 int i, s; 1298 1299 /* Extract the softc struct pointer. */ 1300 sc = (struct bge_softc *)arg; 1301 1302 if (sc == NULL) 1303 panic("bge_jfree: can't find softc pointer!"); 1304 1305 /* calculate the slot this buffer belongs to */ 1306 1307 i = ((char *)buf 1308 - (char *)sc->bge_cdata.bge_jumbo_buf) / BGE_JLEN; 1309 1310 if ((i < 0) || (i >= BGE_JSLOTS)) 1311 panic("bge_jfree: asked to free buffer that we don't manage!"); 1312 1313 s = splvm(); 1314 entry = SLIST_FIRST(&sc->bge_jinuse_listhead); 1315 if (entry == NULL) 1316 panic("bge_jfree: buffer not in use!"); 1317 entry->slot = i; 1318 SLIST_REMOVE_HEAD(&sc->bge_jinuse_listhead, jpool_entries); 1319 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, entry, jpool_entries); 1320 1321 if (__predict_true(m != NULL)) 1322 pool_cache_put(mb_cache, m); 1323 splx(s); 1324 } 1325 1326 1327 /* 1328 * Initialize a standard receive ring descriptor. 1329 */ 1330 static int 1331 bge_newbuf_std(struct bge_softc *sc, int i, struct mbuf *m, 1332 bus_dmamap_t dmamap) 1333 { 1334 struct mbuf *m_new = NULL; 1335 struct bge_rx_bd *r; 1336 int error; 1337 1338 if (dmamap == NULL) { 1339 error = bus_dmamap_create(sc->bge_dmatag, MCLBYTES, 1, 1340 MCLBYTES, 0, BUS_DMA_NOWAIT, &dmamap); 1341 if (error != 0) 1342 return error; 1343 } 1344 1345 sc->bge_cdata.bge_rx_std_map[i] = dmamap; 1346 1347 if (m == NULL) { 1348 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1349 if (m_new == NULL) 1350 return ENOBUFS; 1351 1352 MCLGET(m_new, M_DONTWAIT); 1353 if (!(m_new->m_flags & M_EXT)) { 1354 m_freem(m_new); 1355 return ENOBUFS; 1356 } 1357 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1358 1359 } else { 1360 m_new = m; 1361 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1362 m_new->m_data = m_new->m_ext.ext_buf; 1363 } 1364 if (!(sc->bge_flags & BGE_RX_ALIGNBUG)) 1365 m_adj(m_new, ETHER_ALIGN); 1366 if (bus_dmamap_load_mbuf(sc->bge_dmatag, dmamap, m_new, 1367 BUS_DMA_READ|BUS_DMA_NOWAIT)) 1368 return ENOBUFS; 1369 bus_dmamap_sync(sc->bge_dmatag, dmamap, 0, dmamap->dm_mapsize, 1370 BUS_DMASYNC_PREREAD); 1371 1372 sc->bge_cdata.bge_rx_std_chain[i] = m_new; 1373 r = &sc->bge_rdata->bge_rx_std_ring[i]; 1374 BGE_HOSTADDR(r->bge_addr, dmamap->dm_segs[0].ds_addr); 1375 r->bge_flags = BGE_RXBDFLAG_END; 1376 r->bge_len = m_new->m_len; 1377 r->bge_idx = i; 1378 1379 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 1380 offsetof(struct bge_ring_data, bge_rx_std_ring) + 1381 i * sizeof (struct bge_rx_bd), 1382 sizeof (struct bge_rx_bd), 1383 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1384 1385 return 0; 1386 } 1387 1388 /* 1389 * Initialize a jumbo receive ring descriptor. This allocates 1390 * a jumbo buffer from the pool managed internally by the driver. 1391 */ 1392 static int 1393 bge_newbuf_jumbo(struct bge_softc *sc, int i, struct mbuf *m) 1394 { 1395 struct mbuf *m_new = NULL; 1396 struct bge_rx_bd *r; 1397 void *buf = NULL; 1398 1399 if (m == NULL) { 1400 1401 /* Allocate the mbuf. */ 1402 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1403 if (m_new == NULL) 1404 return ENOBUFS; 1405 1406 /* Allocate the jumbo buffer */ 1407 buf = bge_jalloc(sc); 1408 if (buf == NULL) { 1409 m_freem(m_new); 1410 aprint_error_dev(sc->bge_dev, 1411 "jumbo allocation failed -- packet dropped!\n"); 1412 return ENOBUFS; 1413 } 1414 1415 /* Attach the buffer to the mbuf. */ 1416 m_new->m_len = m_new->m_pkthdr.len = BGE_JUMBO_FRAMELEN; 1417 MEXTADD(m_new, buf, BGE_JUMBO_FRAMELEN, M_DEVBUF, 1418 bge_jfree, sc); 1419 m_new->m_flags |= M_EXT_RW; 1420 } else { 1421 m_new = m; 1422 buf = m_new->m_data = m_new->m_ext.ext_buf; 1423 m_new->m_ext.ext_size = BGE_JUMBO_FRAMELEN; 1424 } 1425 if (!(sc->bge_flags & BGE_RX_ALIGNBUG)) 1426 m_adj(m_new, ETHER_ALIGN); 1427 bus_dmamap_sync(sc->bge_dmatag, sc->bge_cdata.bge_rx_jumbo_map, 1428 mtod(m_new, char *) - (char *)sc->bge_cdata.bge_jumbo_buf, BGE_JLEN, 1429 BUS_DMASYNC_PREREAD); 1430 /* Set up the descriptor. */ 1431 r = &sc->bge_rdata->bge_rx_jumbo_ring[i]; 1432 sc->bge_cdata.bge_rx_jumbo_chain[i] = m_new; 1433 BGE_HOSTADDR(r->bge_addr, BGE_JUMBO_DMA_ADDR(sc, m_new)); 1434 r->bge_flags = BGE_RXBDFLAG_END|BGE_RXBDFLAG_JUMBO_RING; 1435 r->bge_len = m_new->m_len; 1436 r->bge_idx = i; 1437 1438 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 1439 offsetof(struct bge_ring_data, bge_rx_jumbo_ring) + 1440 i * sizeof (struct bge_rx_bd), 1441 sizeof (struct bge_rx_bd), 1442 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1443 1444 return 0; 1445 } 1446 1447 /* 1448 * The standard receive ring has 512 entries in it. At 2K per mbuf cluster, 1449 * that's 1MB or memory, which is a lot. For now, we fill only the first 1450 * 256 ring entries and hope that our CPU is fast enough to keep up with 1451 * the NIC. 1452 */ 1453 static int 1454 bge_init_rx_ring_std(struct bge_softc *sc) 1455 { 1456 int i; 1457 1458 if (sc->bge_flags & BGE_RXRING_VALID) 1459 return 0; 1460 1461 for (i = 0; i < BGE_SSLOTS; i++) { 1462 if (bge_newbuf_std(sc, i, NULL, 0) == ENOBUFS) 1463 return ENOBUFS; 1464 } 1465 1466 sc->bge_std = i - 1; 1467 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std); 1468 1469 sc->bge_flags |= BGE_RXRING_VALID; 1470 1471 return 0; 1472 } 1473 1474 static void 1475 bge_free_rx_ring_std(struct bge_softc *sc) 1476 { 1477 int i; 1478 1479 if (!(sc->bge_flags & BGE_RXRING_VALID)) 1480 return; 1481 1482 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { 1483 if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) { 1484 m_freem(sc->bge_cdata.bge_rx_std_chain[i]); 1485 sc->bge_cdata.bge_rx_std_chain[i] = NULL; 1486 bus_dmamap_destroy(sc->bge_dmatag, 1487 sc->bge_cdata.bge_rx_std_map[i]); 1488 } 1489 memset((char *)&sc->bge_rdata->bge_rx_std_ring[i], 0, 1490 sizeof(struct bge_rx_bd)); 1491 } 1492 1493 sc->bge_flags &= ~BGE_RXRING_VALID; 1494 } 1495 1496 static int 1497 bge_init_rx_ring_jumbo(struct bge_softc *sc) 1498 { 1499 int i; 1500 volatile struct bge_rcb *rcb; 1501 1502 if (sc->bge_flags & BGE_JUMBO_RXRING_VALID) 1503 return 0; 1504 1505 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 1506 if (bge_newbuf_jumbo(sc, i, NULL) == ENOBUFS) 1507 return ENOBUFS; 1508 } 1509 1510 sc->bge_jumbo = i - 1; 1511 sc->bge_flags |= BGE_JUMBO_RXRING_VALID; 1512 1513 rcb = &sc->bge_rdata->bge_info.bge_jumbo_rx_rcb; 1514 rcb->bge_maxlen_flags = 0; 1515 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 1516 1517 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo); 1518 1519 return 0; 1520 } 1521 1522 static void 1523 bge_free_rx_ring_jumbo(struct bge_softc *sc) 1524 { 1525 int i; 1526 1527 if (!(sc->bge_flags & BGE_JUMBO_RXRING_VALID)) 1528 return; 1529 1530 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 1531 if (sc->bge_cdata.bge_rx_jumbo_chain[i] != NULL) { 1532 m_freem(sc->bge_cdata.bge_rx_jumbo_chain[i]); 1533 sc->bge_cdata.bge_rx_jumbo_chain[i] = NULL; 1534 } 1535 memset((char *)&sc->bge_rdata->bge_rx_jumbo_ring[i], 0, 1536 sizeof(struct bge_rx_bd)); 1537 } 1538 1539 sc->bge_flags &= ~BGE_JUMBO_RXRING_VALID; 1540 } 1541 1542 static void 1543 bge_free_tx_ring(struct bge_softc *sc) 1544 { 1545 int i; 1546 struct txdmamap_pool_entry *dma; 1547 1548 if (!(sc->bge_flags & BGE_TXRING_VALID)) 1549 return; 1550 1551 for (i = 0; i < BGE_TX_RING_CNT; i++) { 1552 if (sc->bge_cdata.bge_tx_chain[i] != NULL) { 1553 m_freem(sc->bge_cdata.bge_tx_chain[i]); 1554 sc->bge_cdata.bge_tx_chain[i] = NULL; 1555 SLIST_INSERT_HEAD(&sc->txdma_list, sc->txdma[i], 1556 link); 1557 sc->txdma[i] = 0; 1558 } 1559 memset((char *)&sc->bge_rdata->bge_tx_ring[i], 0, 1560 sizeof(struct bge_tx_bd)); 1561 } 1562 1563 while ((dma = SLIST_FIRST(&sc->txdma_list))) { 1564 SLIST_REMOVE_HEAD(&sc->txdma_list, link); 1565 bus_dmamap_destroy(sc->bge_dmatag, dma->dmamap); 1566 free(dma, M_DEVBUF); 1567 } 1568 1569 sc->bge_flags &= ~BGE_TXRING_VALID; 1570 } 1571 1572 static int 1573 bge_init_tx_ring(struct bge_softc *sc) 1574 { 1575 int i; 1576 bus_dmamap_t dmamap; 1577 struct txdmamap_pool_entry *dma; 1578 1579 if (sc->bge_flags & BGE_TXRING_VALID) 1580 return 0; 1581 1582 sc->bge_txcnt = 0; 1583 sc->bge_tx_saved_considx = 0; 1584 1585 /* Initialize transmit producer index for host-memory send ring. */ 1586 sc->bge_tx_prodidx = 0; 1587 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx); 1588 /* 5700 b2 errata */ 1589 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX) 1590 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx); 1591 1592 /* NIC-memory send ring not used; initialize to zero. */ 1593 bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0); 1594 /* 5700 b2 errata */ 1595 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX) 1596 bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0); 1597 1598 SLIST_INIT(&sc->txdma_list); 1599 for (i = 0; i < BGE_RSLOTS; i++) { 1600 if (bus_dmamap_create(sc->bge_dmatag, BGE_TXDMA_MAX, 1601 BGE_NTXSEG, ETHER_MAX_LEN_JUMBO, 0, BUS_DMA_NOWAIT, 1602 &dmamap)) 1603 return ENOBUFS; 1604 if (dmamap == NULL) 1605 panic("dmamap NULL in bge_init_tx_ring"); 1606 dma = malloc(sizeof(*dma), M_DEVBUF, M_NOWAIT); 1607 if (dma == NULL) { 1608 aprint_error_dev(sc->bge_dev, 1609 "can't alloc txdmamap_pool_entry\n"); 1610 bus_dmamap_destroy(sc->bge_dmatag, dmamap); 1611 return ENOMEM; 1612 } 1613 dma->dmamap = dmamap; 1614 SLIST_INSERT_HEAD(&sc->txdma_list, dma, link); 1615 } 1616 1617 sc->bge_flags |= BGE_TXRING_VALID; 1618 1619 return 0; 1620 } 1621 1622 static void 1623 bge_setmulti(struct bge_softc *sc) 1624 { 1625 struct ethercom *ac = &sc->ethercom; 1626 struct ifnet *ifp = &ac->ec_if; 1627 struct ether_multi *enm; 1628 struct ether_multistep step; 1629 uint32_t hashes[4] = { 0, 0, 0, 0 }; 1630 uint32_t h; 1631 int i; 1632 1633 if (ifp->if_flags & IFF_PROMISC) 1634 goto allmulti; 1635 1636 /* Now program new ones. */ 1637 ETHER_FIRST_MULTI(step, ac, enm); 1638 while (enm != NULL) { 1639 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1640 /* 1641 * We must listen to a range of multicast addresses. 1642 * For now, just accept all multicasts, rather than 1643 * trying to set only those filter bits needed to match 1644 * the range. (At this time, the only use of address 1645 * ranges is for IP multicast routing, for which the 1646 * range is big enough to require all bits set.) 1647 */ 1648 goto allmulti; 1649 } 1650 1651 h = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN); 1652 1653 /* Just want the 7 least-significant bits. */ 1654 h &= 0x7f; 1655 1656 hashes[(h & 0x60) >> 5] |= 1 << (h & 0x1F); 1657 ETHER_NEXT_MULTI(step, enm); 1658 } 1659 1660 ifp->if_flags &= ~IFF_ALLMULTI; 1661 goto setit; 1662 1663 allmulti: 1664 ifp->if_flags |= IFF_ALLMULTI; 1665 hashes[0] = hashes[1] = hashes[2] = hashes[3] = 0xffffffff; 1666 1667 setit: 1668 for (i = 0; i < 4; i++) 1669 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]); 1670 } 1671 1672 static void 1673 bge_sig_pre_reset(struct bge_softc *sc, int type) 1674 { 1675 1676 /* 1677 * Some chips don't like this so only do this if ASF is enabled 1678 */ 1679 if (sc->bge_asf_mode) 1680 bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM, BGE_MAGIC_NUMBER); 1681 1682 if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) { 1683 switch (type) { 1684 case BGE_RESET_START: 1685 bge_writemem_ind(sc, BGE_SDI_STATUS, 0x1); /* START */ 1686 break; 1687 case BGE_RESET_STOP: 1688 bge_writemem_ind(sc, BGE_SDI_STATUS, 0x2); /* UNLOAD */ 1689 break; 1690 } 1691 } 1692 } 1693 1694 static void 1695 bge_sig_post_reset(struct bge_softc *sc, int type) 1696 { 1697 1698 if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) { 1699 switch (type) { 1700 case BGE_RESET_START: 1701 bge_writemem_ind(sc, BGE_SDI_STATUS, 0x80000001); 1702 /* START DONE */ 1703 break; 1704 case BGE_RESET_STOP: 1705 bge_writemem_ind(sc, BGE_SDI_STATUS, 0x80000002); 1706 break; 1707 } 1708 } 1709 } 1710 1711 static void 1712 bge_sig_legacy(struct bge_softc *sc, int type) 1713 { 1714 1715 if (sc->bge_asf_mode) { 1716 switch (type) { 1717 case BGE_RESET_START: 1718 bge_writemem_ind(sc, BGE_SDI_STATUS, 0x1); /* START */ 1719 break; 1720 case BGE_RESET_STOP: 1721 bge_writemem_ind(sc, BGE_SDI_STATUS, 0x2); /* UNLOAD */ 1722 break; 1723 } 1724 } 1725 } 1726 1727 static void 1728 bge_stop_fw(struct bge_softc *sc) 1729 { 1730 int i; 1731 1732 if (sc->bge_asf_mode) { 1733 bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM_FW, BGE_FW_PAUSE); 1734 CSR_WRITE_4(sc, BGE_CPU_EVENT, 1735 CSR_READ_4(sc, BGE_CPU_EVENT) | (1 << 14)); 1736 1737 for (i = 0; i < 100; i++) { 1738 if (!(CSR_READ_4(sc, BGE_CPU_EVENT) & (1 << 14))) 1739 break; 1740 DELAY(10); 1741 } 1742 } 1743 } 1744 1745 static int 1746 bge_poll_fw(struct bge_softc *sc) 1747 { 1748 uint32_t val; 1749 int i; 1750 1751 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 1752 for (i = 0; i < BGE_TIMEOUT; i++) { 1753 val = CSR_READ_4(sc, BGE_VCPU_STATUS); 1754 if (val & BGE_VCPU_STATUS_INIT_DONE) 1755 break; 1756 DELAY(100); 1757 } 1758 if (i >= BGE_TIMEOUT) { 1759 aprint_error_dev(sc->bge_dev, "reset timed out\n"); 1760 return -1; 1761 } 1762 } else if ((sc->bge_flags & BGE_NO_EEPROM) == 0) { 1763 /* 1764 * Poll the value location we just wrote until 1765 * we see the 1's complement of the magic number. 1766 * This indicates that the firmware initialization 1767 * is complete. 1768 * XXX 1000ms for Flash and 10000ms for SEEPROM. 1769 */ 1770 for (i = 0; i < BGE_TIMEOUT; i++) { 1771 val = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM); 1772 if (val == ~BGE_MAGIC_NUMBER) 1773 break; 1774 DELAY(10); 1775 } 1776 1777 if (i >= BGE_TIMEOUT) { 1778 aprint_error_dev(sc->bge_dev, 1779 "firmware handshake timed out, val = %x\n", val); 1780 return -1; 1781 } 1782 } 1783 1784 return 0; 1785 } 1786 1787 /* 1788 * Do endian, PCI and DMA initialization. Also check the on-board ROM 1789 * self-test results. 1790 */ 1791 static int 1792 bge_chipinit(struct bge_softc *sc) 1793 { 1794 int i; 1795 uint32_t dma_rw_ctl; 1796 1797 /* Set endianness before we access any non-PCI registers. */ 1798 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MISC_CTL, 1799 BGE_INIT); 1800 1801 /* Set power state to D0. */ 1802 bge_setpowerstate(sc, 0); 1803 1804 /* Clear the MAC control register */ 1805 CSR_WRITE_4(sc, BGE_MAC_MODE, 0); 1806 1807 /* 1808 * Clear the MAC statistics block in the NIC's 1809 * internal memory. 1810 */ 1811 for (i = BGE_STATS_BLOCK; 1812 i < BGE_STATS_BLOCK_END + 1; i += sizeof(uint32_t)) 1813 BGE_MEMWIN_WRITE(sc->sc_pc, sc->sc_pcitag, i, 0); 1814 1815 for (i = BGE_STATUS_BLOCK; 1816 i < BGE_STATUS_BLOCK_END + 1; i += sizeof(uint32_t)) 1817 BGE_MEMWIN_WRITE(sc->sc_pc, sc->sc_pcitag, i, 0); 1818 1819 /* Set up the PCI DMA control register. */ 1820 dma_rw_ctl = BGE_PCI_READ_CMD | BGE_PCI_WRITE_CMD; 1821 if (sc->bge_flags & BGE_PCIE) { 1822 /* Read watermark not used, 128 bytes for write. */ 1823 DPRINTFN(4, ("(%s: PCI-Express DMA setting)\n", 1824 device_xname(sc->bge_dev))); 1825 dma_rw_ctl |= BGE_PCIDMARWCTL_WR_WAT_SHIFT(3); 1826 } else if (sc->bge_flags & BGE_PCIX) { 1827 DPRINTFN(4, ("(:%s: PCI-X DMA setting)\n", 1828 device_xname(sc->bge_dev))); 1829 /* PCI-X bus */ 1830 if (BGE_IS_5714_FAMILY(sc)) { 1831 /* 256 bytes for read and write. */ 1832 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(2) | 1833 BGE_PCIDMARWCTL_WR_WAT_SHIFT(2); 1834 1835 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5780) 1836 dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL; 1837 else 1838 dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE_LOCAL; 1839 } else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) { 1840 /* 1536 bytes for read, 384 bytes for write. */ 1841 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(7) | 1842 BGE_PCIDMARWCTL_WR_WAT_SHIFT(3); 1843 } else { 1844 /* 384 bytes for read and write. */ 1845 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(3) | 1846 BGE_PCIDMARWCTL_WR_WAT_SHIFT(3) | 1847 (0x0F); 1848 } 1849 1850 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5703 || 1851 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) { 1852 uint32_t tmp; 1853 1854 /* Set ONEDMA_ATONCE for hardware workaround. */ 1855 tmp = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 1856 BGE_PCI_CLKCTL) & 0x1f; 1857 if (tmp == 6 || tmp == 7) 1858 dma_rw_ctl |= 1859 BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL; 1860 1861 /* Set PCI-X DMA write workaround. */ 1862 dma_rw_ctl |= BGE_PCIDMARWCTL_ASRT_ALL_BE; 1863 } 1864 } else { 1865 /* Conventional PCI bus: 256 bytes for read and write. */ 1866 DPRINTFN(4, ("(%s: PCI 2.2 DMA setting)\n", 1867 device_xname(sc->bge_dev))); 1868 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(7) | 1869 BGE_PCIDMARWCTL_WR_WAT_SHIFT(7); 1870 1871 if (BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5705 && 1872 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5750) 1873 dma_rw_ctl |= 0x0F; 1874 } 1875 1876 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 1877 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5701) 1878 dma_rw_ctl |= BGE_PCIDMARWCTL_USE_MRM | 1879 BGE_PCIDMARWCTL_ASRT_ALL_BE; 1880 1881 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5703 || 1882 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) 1883 dma_rw_ctl &= ~BGE_PCIDMARWCTL_MINDMA; 1884 1885 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_DMA_RW_CTL, 1886 dma_rw_ctl); 1887 1888 /* 1889 * Set up general mode register. 1890 */ 1891 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS | 1892 BGE_MODECTL_MAC_ATTN_INTR | BGE_MODECTL_HOST_SEND_BDS | 1893 BGE_MODECTL_TX_NO_PHDR_CSUM); 1894 1895 /* 1896 * BCM5701 B5 have a bug causing data corruption when using 1897 * 64-bit DMA reads, which can be terminated early and then 1898 * completed later as 32-bit accesses, in combination with 1899 * certain bridges. 1900 */ 1901 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5701 && 1902 sc->bge_chipid == BGE_CHIPID_BCM5701_B5) 1903 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_FORCE_PCI32); 1904 1905 /* 1906 * Tell the firmware the driver is running 1907 */ 1908 if (sc->bge_asf_mode & ASF_STACKUP) 1909 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 1910 1911 /* 1912 * Disable memory write invalidate. Apparently it is not supported 1913 * properly by these devices. 1914 */ 1915 PCI_CLRBIT(sc->sc_pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG, 1916 PCI_COMMAND_INVALIDATE_ENABLE); 1917 1918 #ifdef __brokenalpha__ 1919 /* 1920 * Must insure that we do not cross an 8K (bytes) boundary 1921 * for DMA reads. Our highest limit is 1K bytes. This is a 1922 * restriction on some ALPHA platforms with early revision 1923 * 21174 PCI chipsets, such as the AlphaPC 164lx 1924 */ 1925 PCI_SETBIT(sc, BGE_PCI_DMA_RW_CTL, BGE_PCI_READ_BNDRY_1024, 4); 1926 #endif 1927 1928 /* Set the timer prescaler (always 66MHz) */ 1929 CSR_WRITE_4(sc, BGE_MISC_CFG, 65 << 1/*BGE_32BITTIME_66MHZ*/); 1930 1931 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 1932 DELAY(40); /* XXX */ 1933 1934 /* Put PHY into ready state */ 1935 BGE_CLRBIT(sc, BGE_MISC_CFG, BGE_MISCCFG_EPHY_IDDQ); 1936 CSR_READ_4(sc, BGE_MISC_CFG); /* Flush */ 1937 DELAY(40); 1938 } 1939 1940 return 0; 1941 } 1942 1943 static int 1944 bge_blockinit(struct bge_softc *sc) 1945 { 1946 volatile struct bge_rcb *rcb; 1947 bus_size_t rcb_addr; 1948 int i; 1949 struct ifnet *ifp = &sc->ethercom.ec_if; 1950 bge_hostaddr taddr; 1951 uint32_t val; 1952 1953 /* 1954 * Initialize the memory window pointer register so that 1955 * we can access the first 32K of internal NIC RAM. This will 1956 * allow us to set up the TX send ring RCBs and the RX return 1957 * ring RCBs, plus other things which live in NIC memory. 1958 */ 1959 1960 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_BASEADDR, 0); 1961 1962 /* Step 33: Configure mbuf memory pool */ 1963 if (BGE_IS_5700_FAMILY(sc)) { 1964 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, 1965 BGE_BUFFPOOL_1); 1966 1967 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) 1968 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000); 1969 else 1970 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000); 1971 1972 /* Configure DMA resource pool */ 1973 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_BASEADDR, 1974 BGE_DMA_DESCRIPTORS); 1975 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LEN, 0x2000); 1976 } 1977 1978 /* Step 35: Configure mbuf pool watermarks */ 1979 #ifdef ORIG_WPAUL_VALUES 1980 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 24); 1981 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 24); 1982 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 48); 1983 #else 1984 1985 /* new broadcom docs strongly recommend these: */ 1986 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5717 || 1987 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57765 || 1988 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57766) { 1989 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0); 1990 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x2a); 1991 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0xa0); 1992 } else if (BGE_IS_5705_PLUS(sc)) { 1993 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0); 1994 1995 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 1996 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x04); 1997 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x10); 1998 } else { 1999 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x10); 2000 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60); 2001 } 2002 } else if (!BGE_IS_5705_PLUS(sc)) { 2003 if (ifp->if_mtu > ETHER_MAX_LEN) { 2004 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x50); 2005 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x20); 2006 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60); 2007 } else { 2008 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 304); 2009 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 152); 2010 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 380); 2011 } 2012 } else { 2013 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0); 2014 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x10); 2015 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60); 2016 } 2017 #endif 2018 2019 /* Step 36: Configure DMA resource watermarks */ 2020 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5); 2021 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10); 2022 2023 /* Step 38: Enable buffer manager */ 2024 CSR_WRITE_4(sc, BGE_BMAN_MODE, 2025 BGE_BMANMODE_ENABLE | BGE_BMANMODE_LOMBUF_ATTN); 2026 2027 /* Step 39: Poll for buffer manager start indication */ 2028 for (i = 0; i < BGE_TIMEOUT * 2; i++) { 2029 if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE) 2030 break; 2031 DELAY(10); 2032 } 2033 2034 if (i == BGE_TIMEOUT * 2) { 2035 aprint_error_dev(sc->bge_dev, 2036 "buffer manager failed to start\n"); 2037 return ENXIO; 2038 } 2039 2040 /* Step 40: Enable flow-through queues */ 2041 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 2042 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 2043 2044 /* Wait until queue initialization is complete */ 2045 for (i = 0; i < BGE_TIMEOUT * 2; i++) { 2046 if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0) 2047 break; 2048 DELAY(10); 2049 } 2050 2051 if (i == BGE_TIMEOUT * 2) { 2052 aprint_error_dev(sc->bge_dev, 2053 "flow-through queue init failed\n"); 2054 return ENXIO; 2055 } 2056 2057 /* Step 41: Initialize the standard RX ring control block */ 2058 rcb = &sc->bge_rdata->bge_info.bge_std_rx_rcb; 2059 BGE_HOSTADDR(rcb->bge_hostaddr, BGE_RING_DMA_ADDR(sc, bge_rx_std_ring)); 2060 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5717 || 2061 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57765 || 2062 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57766) 2063 rcb->bge_maxlen_flags = 2064 BGE_RCB_MAXLEN_FLAGS(512, BGE_MAX_FRAMELEN << 2); 2065 else if (BGE_IS_5705_PLUS(sc)) 2066 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(512, 0); 2067 else 2068 rcb->bge_maxlen_flags = 2069 BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 0); 2070 rcb->bge_nicaddr = BGE_STD_RX_RINGS; 2071 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcb->bge_hostaddr.bge_addr_hi); 2072 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcb->bge_hostaddr.bge_addr_lo); 2073 CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 2074 CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcb->bge_nicaddr); 2075 2076 /* 2077 * Step 42: Initialize the jumbo RX ring control block 2078 * We set the 'ring disabled' bit in the flags 2079 * field until we're actually ready to start 2080 * using this ring (i.e. once we set the MTU 2081 * high enough to require it). 2082 */ 2083 if (BGE_IS_JUMBO_CAPABLE(sc)) { 2084 rcb = &sc->bge_rdata->bge_info.bge_jumbo_rx_rcb; 2085 BGE_HOSTADDR(rcb->bge_hostaddr, 2086 BGE_RING_DMA_ADDR(sc, bge_rx_jumbo_ring)); 2087 rcb->bge_maxlen_flags = 2088 BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 2089 BGE_RCB_FLAG_RING_DISABLED); 2090 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS; 2091 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI, 2092 rcb->bge_hostaddr.bge_addr_hi); 2093 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO, 2094 rcb->bge_hostaddr.bge_addr_lo); 2095 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, 2096 rcb->bge_maxlen_flags); 2097 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcb->bge_nicaddr); 2098 2099 /* Set up dummy disabled mini ring RCB */ 2100 rcb = &sc->bge_rdata->bge_info.bge_mini_rx_rcb; 2101 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0, 2102 BGE_RCB_FLAG_RING_DISABLED); 2103 CSR_WRITE_4(sc, BGE_RX_MINI_RCB_MAXLEN_FLAGS, 2104 rcb->bge_maxlen_flags); 2105 2106 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 2107 offsetof(struct bge_ring_data, bge_info), 2108 sizeof (struct bge_gib), 2109 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2110 } 2111 2112 /* Choose de-pipeline mode for BCM5906 A0, A1 and A2. */ 2113 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 2114 if (sc->bge_chipid == BGE_CHIPID_BCM5906_A0 || 2115 sc->bge_chipid == BGE_CHIPID_BCM5906_A1 || 2116 sc->bge_chipid == BGE_CHIPID_BCM5906_A2) 2117 CSR_WRITE_4(sc, BGE_ISO_PKT_TX, 2118 (CSR_READ_4(sc, BGE_ISO_PKT_TX) & ~3) | 2); 2119 } 2120 /* 2121 * Set the BD ring replenish thresholds. The recommended 2122 * values are 1/8th the number of descriptors allocated to 2123 * each ring. 2124 */ 2125 i = BGE_STD_RX_RING_CNT / 8; 2126 2127 /* 2128 * Use a value of 8 for the following chips to workaround HW errata. 2129 * Some of these chips have been added based on empirical 2130 * evidence (they don't work unless this is done). 2131 */ 2132 if (BGE_IS_5705_PLUS(sc)) 2133 i = 8; 2134 2135 CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, i); 2136 CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH, BGE_JUMBO_RX_RING_CNT / 8); 2137 2138 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5717 || 2139 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57765 || 2140 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57766) { 2141 CSR_WRITE_4(sc, BGE_STD_REPL_LWM, 4); 2142 CSR_WRITE_4(sc, BGE_JUMBO_REPL_LWM, 4); 2143 } 2144 2145 /* 2146 * Disable all unused send rings by setting the 'ring disabled' 2147 * bit in the flags field of all the TX send ring control blocks. 2148 * These are located in NIC memory. 2149 */ 2150 rcb_addr = BGE_MEMWIN_START + BGE_SEND_RING_RCB; 2151 for (i = 0; i < BGE_TX_RINGS_EXTSSRAM_MAX; i++) { 2152 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 2153 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED)); 2154 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 0); 2155 rcb_addr += sizeof(struct bge_rcb); 2156 } 2157 2158 /* Configure TX RCB 0 (we use only the first ring) */ 2159 rcb_addr = BGE_MEMWIN_START + BGE_SEND_RING_RCB; 2160 BGE_HOSTADDR(taddr, BGE_RING_DMA_ADDR(sc, bge_tx_ring)); 2161 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi); 2162 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo); 2163 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 2164 BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT)); 2165 if (BGE_IS_5700_FAMILY(sc)) 2166 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 2167 BGE_RCB_MAXLEN_FLAGS(BGE_TX_RING_CNT, 0)); 2168 2169 /* Disable all unused RX return rings */ 2170 rcb_addr = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB; 2171 for (i = 0; i < BGE_RX_RINGS_MAX; i++) { 2172 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_hi, 0); 2173 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_lo, 0); 2174 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 2175 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 2176 BGE_RCB_FLAG_RING_DISABLED)); 2177 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 0); 2178 bge_writembx(sc, BGE_MBX_RX_CONS0_LO + 2179 (i * (sizeof(uint64_t))), 0); 2180 rcb_addr += sizeof(struct bge_rcb); 2181 } 2182 2183 /* Initialize RX ring indexes */ 2184 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, 0); 2185 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0); 2186 bge_writembx(sc, BGE_MBX_RX_MINI_PROD_LO, 0); 2187 2188 /* 2189 * Set up RX return ring 0 2190 * Note that the NIC address for RX return rings is 0x00000000. 2191 * The return rings live entirely within the host, so the 2192 * nicaddr field in the RCB isn't used. 2193 */ 2194 rcb_addr = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB; 2195 BGE_HOSTADDR(taddr, BGE_RING_DMA_ADDR(sc, bge_rx_return_ring)); 2196 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi); 2197 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo); 2198 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 0x00000000); 2199 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 2200 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 0)); 2201 2202 /* Set random backoff seed for TX */ 2203 CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF, 2204 CLLADDR(ifp->if_sadl)[0] + CLLADDR(ifp->if_sadl)[1] + 2205 CLLADDR(ifp->if_sadl)[2] + CLLADDR(ifp->if_sadl)[3] + 2206 CLLADDR(ifp->if_sadl)[4] + CLLADDR(ifp->if_sadl)[5] + 2207 BGE_TX_BACKOFF_SEED_MASK); 2208 2209 /* Set inter-packet gap */ 2210 CSR_WRITE_4(sc, BGE_TX_LENGTHS, 0x2620); 2211 2212 /* 2213 * Specify which ring to use for packets that don't match 2214 * any RX rules. 2215 */ 2216 CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08); 2217 2218 /* 2219 * Configure number of RX lists. One interrupt distribution 2220 * list, sixteen active lists, one bad frames class. 2221 */ 2222 CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181); 2223 2224 /* Inialize RX list placement stats mask. */ 2225 CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF); 2226 CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1); 2227 2228 /* Disable host coalescing until we get it set up */ 2229 CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000); 2230 2231 /* Poll to make sure it's shut down. */ 2232 for (i = 0; i < BGE_TIMEOUT * 2; i++) { 2233 if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE)) 2234 break; 2235 DELAY(10); 2236 } 2237 2238 if (i == BGE_TIMEOUT * 2) { 2239 aprint_error_dev(sc->bge_dev, 2240 "host coalescing engine failed to idle\n"); 2241 return ENXIO; 2242 } 2243 2244 /* Set up host coalescing defaults */ 2245 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bge_rx_coal_ticks); 2246 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bge_tx_coal_ticks); 2247 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bge_rx_max_coal_bds); 2248 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bge_tx_max_coal_bds); 2249 if (BGE_IS_5700_FAMILY(sc)) { 2250 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT, 0); 2251 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT, 0); 2252 } 2253 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 0); 2254 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 0); 2255 2256 /* Set up address of statistics block */ 2257 if (BGE_IS_5700_FAMILY(sc)) { 2258 BGE_HOSTADDR(taddr, BGE_RING_DMA_ADDR(sc, bge_info.bge_stats)); 2259 CSR_WRITE_4(sc, BGE_HCC_STATS_TICKS, sc->bge_stat_ticks); 2260 CSR_WRITE_4(sc, BGE_HCC_STATS_BASEADDR, BGE_STATS_BLOCK); 2261 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_HI, taddr.bge_addr_hi); 2262 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_LO, taddr.bge_addr_lo); 2263 } 2264 2265 /* Set up address of status block */ 2266 BGE_HOSTADDR(taddr, BGE_RING_DMA_ADDR(sc, bge_status_block)); 2267 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_BASEADDR, BGE_STATUS_BLOCK); 2268 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI, taddr.bge_addr_hi); 2269 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO, taddr.bge_addr_lo); 2270 sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx = 0; 2271 sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx = 0; 2272 2273 /* Turn on host coalescing state machine */ 2274 CSR_WRITE_4(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE); 2275 2276 /* Turn on RX BD completion state machine and enable attentions */ 2277 CSR_WRITE_4(sc, BGE_RBDC_MODE, 2278 BGE_RBDCMODE_ENABLE | BGE_RBDCMODE_ATTN); 2279 2280 /* Turn on RX list placement state machine */ 2281 CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 2282 2283 /* Turn on RX list selector state machine. */ 2284 if (BGE_IS_5700_FAMILY(sc)) 2285 CSR_WRITE_4(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 2286 2287 val = BGE_MACMODE_TXDMA_ENB | BGE_MACMODE_RXDMA_ENB | 2288 BGE_MACMODE_RX_STATS_CLEAR | BGE_MACMODE_TX_STATS_CLEAR | 2289 BGE_MACMODE_RX_STATS_ENB | BGE_MACMODE_TX_STATS_ENB | 2290 BGE_MACMODE_FRMHDR_DMA_ENB; 2291 2292 if (sc->bge_flags & BGE_PHY_FIBER_TBI) 2293 val |= BGE_PORTMODE_TBI; 2294 else if (sc->bge_flags & BGE_PHY_FIBER_MII) 2295 val |= BGE_PORTMODE_GMII; 2296 else 2297 val |= BGE_PORTMODE_MII; 2298 2299 /* Turn on DMA, clear stats */ 2300 CSR_WRITE_4(sc, BGE_MAC_MODE, val); 2301 2302 /* Set misc. local control, enable interrupts on attentions */ 2303 sc->bge_local_ctrl_reg = BGE_MLC_INTR_ONATTN | BGE_MLC_AUTO_EEPROM; 2304 2305 #ifdef notdef 2306 /* Assert GPIO pins for PHY reset */ 2307 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUT0| 2308 BGE_MLC_MISCIO_OUT1|BGE_MLC_MISCIO_OUT2); 2309 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUTEN0| 2310 BGE_MLC_MISCIO_OUTEN1|BGE_MLC_MISCIO_OUTEN2); 2311 #endif 2312 2313 #if defined(not_quite_yet) 2314 /* Linux driver enables enable gpio pin #1 on 5700s */ 2315 if (sc->bge_chipid == BGE_CHIPID_BCM5700) { 2316 sc->bge_local_ctrl_reg |= 2317 (BGE_MLC_MISCIO_OUT1|BGE_MLC_MISCIO_OUTEN1); 2318 } 2319 #endif 2320 CSR_WRITE_4(sc, BGE_MISC_LOCAL_CTL, sc->bge_local_ctrl_reg); 2321 2322 /* Turn on DMA completion state machine */ 2323 if (BGE_IS_5700_FAMILY(sc)) 2324 CSR_WRITE_4(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 2325 2326 val = BGE_WDMAMODE_ENABLE | BGE_WDMAMODE_ALL_ATTNS; 2327 2328 /* Enable host coalescing bug fix */ 2329 if (BGE_IS_5755_PLUS(sc)) 2330 val |= BGE_WDMAMODE_STATUS_TAG_FIX; 2331 2332 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785) 2333 val |= BGE_WDMAMODE_BURST_ALL_DATA; 2334 2335 /* Turn on write DMA state machine */ 2336 CSR_WRITE_4(sc, BGE_WDMA_MODE, val); 2337 2338 val = BGE_RDMAMODE_ENABLE | BGE_RDMAMODE_ALL_ATTNS; 2339 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5784 || 2340 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785 || 2341 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57780) 2342 val |= BGE_RDMAMODE_BD_SBD_CRPT_ATTN | 2343 BGE_RDMAMODE_MBUF_RBD_CRPT_ATTN | 2344 BGE_RDMAMODE_MBUF_SBD_CRPT_ATTN; 2345 2346 if (sc->bge_flags & BGE_PCIE) 2347 val |= BGE_RDMAMODE_FIFO_LONG_BURST; 2348 if (sc->bge_flags & BGE_TSO) 2349 val |= BGE_RDMAMODE_TSO4_ENABLE; 2350 2351 /* Turn on read DMA state machine */ 2352 CSR_WRITE_4(sc, BGE_RDMA_MODE, val); 2353 delay(40); 2354 2355 /* Turn on RX data completion state machine */ 2356 CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 2357 2358 /* Turn on RX BD initiator state machine */ 2359 CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 2360 2361 /* Turn on RX data and RX BD initiator state machine */ 2362 CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE); 2363 2364 /* Turn on Mbuf cluster free state machine */ 2365 if (BGE_IS_5700_FAMILY(sc)) 2366 CSR_WRITE_4(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 2367 2368 /* Turn on send BD completion state machine */ 2369 CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 2370 2371 /* Turn on send data completion state machine */ 2372 val = BGE_SDCMODE_ENABLE; 2373 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761) 2374 val |= BGE_SDCMODE_CDELAY; 2375 CSR_WRITE_4(sc, BGE_SDC_MODE, val); 2376 2377 /* Turn on send data initiator state machine */ 2378 if (sc->bge_flags & BGE_TSO) { 2379 /* XXX: magic value from Linux driver */ 2380 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE | 0x08); 2381 } else 2382 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 2383 2384 /* Turn on send BD initiator state machine */ 2385 CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 2386 2387 /* Turn on send BD selector state machine */ 2388 CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 2389 2390 CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF); 2391 CSR_WRITE_4(sc, BGE_SDI_STATS_CTL, 2392 BGE_SDISTATSCTL_ENABLE | BGE_SDISTATSCTL_FASTER); 2393 2394 /* ack/clear link change events */ 2395 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED | 2396 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE | 2397 BGE_MACSTAT_LINK_CHANGED); 2398 CSR_WRITE_4(sc, BGE_MI_STS, 0); 2399 2400 /* Enable PHY auto polling (for MII/GMII only) */ 2401 if (sc->bge_flags & BGE_PHY_FIBER_TBI) { 2402 CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK); 2403 } else { 2404 BGE_STS_SETBIT(sc, BGE_STS_AUTOPOLL); 2405 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL | (10 << 16)); 2406 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700) 2407 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, 2408 BGE_EVTENB_MI_INTERRUPT); 2409 } 2410 2411 /* 2412 * Clear any pending link state attention. 2413 * Otherwise some link state change events may be lost until attention 2414 * is cleared by bge_intr() -> bge_link_upd() sequence. 2415 * It's not necessary on newer BCM chips - perhaps enabling link 2416 * state change attentions implies clearing pending attention. 2417 */ 2418 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED | 2419 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE | 2420 BGE_MACSTAT_LINK_CHANGED); 2421 2422 /* Enable link state change attentions. */ 2423 BGE_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED); 2424 2425 return 0; 2426 } 2427 2428 static const struct bge_revision * 2429 bge_lookup_rev(uint32_t chipid) 2430 { 2431 const struct bge_revision *br; 2432 2433 for (br = bge_revisions; br->br_name != NULL; br++) { 2434 if (br->br_chipid == chipid) 2435 return br; 2436 } 2437 2438 for (br = bge_majorrevs; br->br_name != NULL; br++) { 2439 if (br->br_chipid == BGE_ASICREV(chipid)) 2440 return br; 2441 } 2442 2443 return NULL; 2444 } 2445 2446 static const struct bge_product * 2447 bge_lookup(const struct pci_attach_args *pa) 2448 { 2449 const struct bge_product *bp; 2450 2451 for (bp = bge_products; bp->bp_name != NULL; bp++) { 2452 if (PCI_VENDOR(pa->pa_id) == bp->bp_vendor && 2453 PCI_PRODUCT(pa->pa_id) == bp->bp_product) 2454 return bp; 2455 } 2456 2457 return NULL; 2458 } 2459 2460 static int 2461 bge_setpowerstate(struct bge_softc *sc, int powerlevel) 2462 { 2463 #ifdef NOTYET 2464 uint32_t pm_ctl = 0; 2465 2466 /* XXX FIXME: make sure indirect accesses enabled? */ 2467 pm_ctl = pci_conf_read(sc->bge_dev, BGE_PCI_MISC_CTL, 4); 2468 pm_ctl |= BGE_PCIMISCCTL_INDIRECT_ACCESS; 2469 pci_write_config(sc->bge_dev, BGE_PCI_MISC_CTL, pm_ctl, 4); 2470 2471 /* clear the PME_assert bit and power state bits, enable PME */ 2472 pm_ctl = pci_conf_read(sc->bge_dev, BGE_PCI_PWRMGMT_CMD, 2); 2473 pm_ctl &= ~PCIM_PSTAT_DMASK; 2474 pm_ctl |= (1 << 8); 2475 2476 if (powerlevel == 0) { 2477 pm_ctl |= PCIM_PSTAT_D0; 2478 pci_write_config(sc->bge_dev, BGE_PCI_PWRMGMT_CMD, 2479 pm_ctl, 2); 2480 DELAY(10000); 2481 CSR_WRITE_4(sc, BGE_MISC_LOCAL_CTL, sc->bge_local_ctrl_reg); 2482 DELAY(10000); 2483 2484 #ifdef NOTYET 2485 /* XXX FIXME: write 0x02 to phy aux_Ctrl reg */ 2486 bge_miibus_writereg(sc->bge_dev, 1, 0x18, 0x02); 2487 #endif 2488 DELAY(40); DELAY(40); DELAY(40); 2489 DELAY(10000); /* above not quite adequate on 5700 */ 2490 return 0; 2491 } 2492 2493 2494 /* 2495 * Entering ACPI power states D1-D3 is achieved by wiggling 2496 * GMII gpio pins. Example code assumes all hardware vendors 2497 * followed Broadcom's sample pcb layout. Until we verify that 2498 * for all supported OEM cards, states D1-D3 are unsupported. 2499 */ 2500 aprint_error_dev(sc->bge_dev, 2501 "power state %d unimplemented; check GPIO pins\n", 2502 powerlevel); 2503 #endif 2504 return EOPNOTSUPP; 2505 } 2506 2507 2508 /* 2509 * Probe for a Broadcom chip. Check the PCI vendor and device IDs 2510 * against our list and return its name if we find a match. Note 2511 * that since the Broadcom controller contains VPD support, we 2512 * can get the device name string from the controller itself instead 2513 * of the compiled-in string. This is a little slow, but it guarantees 2514 * we'll always announce the right product name. 2515 */ 2516 static int 2517 bge_probe(device_t parent, cfdata_t match, void *aux) 2518 { 2519 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 2520 2521 if (bge_lookup(pa) != NULL) 2522 return 1; 2523 2524 return 0; 2525 } 2526 2527 static void 2528 bge_attach(device_t parent, device_t self, void *aux) 2529 { 2530 struct bge_softc *sc = device_private(self); 2531 struct pci_attach_args *pa = aux; 2532 prop_dictionary_t dict; 2533 const struct bge_product *bp; 2534 const struct bge_revision *br; 2535 pci_chipset_tag_t pc; 2536 pci_intr_handle_t ih; 2537 const char *intrstr = NULL; 2538 bus_dma_segment_t seg; 2539 int rseg; 2540 uint32_t hwcfg = 0; 2541 uint32_t command; 2542 struct ifnet *ifp; 2543 uint32_t misccfg; 2544 void * kva; 2545 u_char eaddr[ETHER_ADDR_LEN]; 2546 pcireg_t memtype, subid; 2547 bus_addr_t memaddr; 2548 bus_size_t memsize; 2549 uint32_t pm_ctl; 2550 bool no_seeprom; 2551 2552 bp = bge_lookup(pa); 2553 KASSERT(bp != NULL); 2554 2555 sc->sc_pc = pa->pa_pc; 2556 sc->sc_pcitag = pa->pa_tag; 2557 sc->bge_dev = self; 2558 2559 pc = sc->sc_pc; 2560 subid = pci_conf_read(pc, sc->sc_pcitag, PCI_SUBSYS_ID_REG); 2561 2562 aprint_naive(": Ethernet controller\n"); 2563 aprint_normal(": %s\n", bp->bp_name); 2564 2565 /* 2566 * Map control/status registers. 2567 */ 2568 DPRINTFN(5, ("Map control/status regs\n")); 2569 command = pci_conf_read(pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG); 2570 command |= PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_MASTER_ENABLE; 2571 pci_conf_write(pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG, command); 2572 command = pci_conf_read(pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG); 2573 2574 if (!(command & PCI_COMMAND_MEM_ENABLE)) { 2575 aprint_error_dev(sc->bge_dev, 2576 "failed to enable memory mapping!\n"); 2577 return; 2578 } 2579 2580 DPRINTFN(5, ("pci_mem_find\n")); 2581 memtype = pci_mapreg_type(sc->sc_pc, sc->sc_pcitag, BGE_PCI_BAR0); 2582 switch (memtype) { 2583 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 2584 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 2585 if (pci_mapreg_map(pa, BGE_PCI_BAR0, 2586 memtype, 0, &sc->bge_btag, &sc->bge_bhandle, 2587 &memaddr, &memsize) == 0) 2588 break; 2589 default: 2590 aprint_error_dev(sc->bge_dev, "can't find mem space\n"); 2591 return; 2592 } 2593 2594 DPRINTFN(5, ("pci_intr_map\n")); 2595 if (pci_intr_map(pa, &ih)) { 2596 aprint_error_dev(sc->bge_dev, "couldn't map interrupt\n"); 2597 return; 2598 } 2599 2600 DPRINTFN(5, ("pci_intr_string\n")); 2601 intrstr = pci_intr_string(pc, ih); 2602 2603 DPRINTFN(5, ("pci_intr_establish\n")); 2604 sc->bge_intrhand = pci_intr_establish(pc, ih, IPL_NET, bge_intr, sc); 2605 2606 if (sc->bge_intrhand == NULL) { 2607 aprint_error_dev(sc->bge_dev, 2608 "couldn't establish interrupt%s%s\n", 2609 intrstr ? " at " : "", intrstr ? intrstr : ""); 2610 return; 2611 } 2612 aprint_normal_dev(sc->bge_dev, "interrupting at %s\n", intrstr); 2613 2614 /* 2615 * Kludge for 5700 Bx bug: a hardware bug (PCIX byte enable?) 2616 * can clobber the chip's PCI config-space power control registers, 2617 * leaving the card in D3 powersave state. 2618 * We do not have memory-mapped registers in this state, 2619 * so force device into D0 state before starting initialization. 2620 */ 2621 pm_ctl = pci_conf_read(pc, sc->sc_pcitag, BGE_PCI_PWRMGMT_CMD); 2622 pm_ctl &= ~(PCI_PWR_D0|PCI_PWR_D1|PCI_PWR_D2|PCI_PWR_D3); 2623 pm_ctl |= (1 << 8) | PCI_PWR_D0 ; /* D0 state */ 2624 pci_conf_write(pc, sc->sc_pcitag, BGE_PCI_PWRMGMT_CMD, pm_ctl); 2625 DELAY(1000); /* 27 usec is allegedly sufficent */ 2626 2627 /* 2628 * Save ASIC rev. 2629 */ 2630 sc->bge_chipid = 2631 pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_MISC_CTL) 2632 >> BGE_PCIMISCCTL_ASICREV_SHIFT; 2633 2634 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_USE_PRODID_REG) { 2635 switch (PCI_PRODUCT(pa->pa_id)) { 2636 case PCI_PRODUCT_BROADCOM_BCM5717: 2637 case PCI_PRODUCT_BROADCOM_BCM5718: 2638 case PCI_PRODUCT_BROADCOM_BCM5724: /* ??? */ 2639 sc->bge_chipid = pci_conf_read(pc, pa->pa_tag, 2640 BGE_PCI_GEN2_PRODID_ASICREV); 2641 break; 2642 case PCI_PRODUCT_BROADCOM_BCM57761: 2643 case PCI_PRODUCT_BROADCOM_BCM57762: 2644 case PCI_PRODUCT_BROADCOM_BCM57765: 2645 case PCI_PRODUCT_BROADCOM_BCM57781: 2646 case PCI_PRODUCT_BROADCOM_BCM57785: 2647 case PCI_PRODUCT_BROADCOM_BCM57791: 2648 case PCI_PRODUCT_BROADCOM_BCM57795: 2649 sc->bge_chipid = pci_conf_read(pc, pa->pa_tag, 2650 BGE_PCI_GEN15_PRODID_ASICREV); 2651 break; 2652 default: 2653 sc->bge_chipid = pci_conf_read(pc, pa->pa_tag, 2654 BGE_PCI_PRODID_ASICREV); 2655 break; 2656 } 2657 } 2658 2659 if ((pci_get_capability(sc->sc_pc, sc->sc_pcitag, PCI_CAP_PCIEXPRESS, 2660 &sc->bge_pciecap, NULL) != 0) 2661 || (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785)) { 2662 /* PCIe */ 2663 sc->bge_flags |= BGE_PCIE; 2664 bge_set_max_readrq(sc); 2665 } else if ((pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_PCISTATE) & 2666 BGE_PCISTATE_PCI_BUSMODE) == 0) { 2667 /* PCI-X */ 2668 sc->bge_flags |= BGE_PCIX; 2669 if (pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_PCIX, 2670 &sc->bge_pcixcap, NULL) == 0) 2671 aprint_error_dev(sc->bge_dev, 2672 "unable to find PCIX capability\n"); 2673 } 2674 2675 /* chipid */ 2676 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 2677 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5701 || 2678 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5703 || 2679 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) 2680 sc->bge_flags |= BGE_5700_FAMILY; 2681 2682 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5714_A0 || 2683 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5780 || 2684 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5714) 2685 sc->bge_flags |= BGE_5714_FAMILY; 2686 2687 /* Intentionally exclude BGE_ASICREV_BCM5906 */ 2688 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5717 || 2689 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5755 || 2690 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761 || 2691 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5784 || 2692 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785 || 2693 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5787 || 2694 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57765 || 2695 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57766 || 2696 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57780) 2697 sc->bge_flags |= BGE_5755_PLUS; 2698 2699 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5750 || 2700 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5752 || 2701 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906 || 2702 BGE_IS_5755_PLUS(sc) || 2703 BGE_IS_5714_FAMILY(sc)) 2704 sc->bge_flags |= BGE_575X_PLUS; 2705 2706 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5705 || 2707 BGE_IS_575X_PLUS(sc)) 2708 sc->bge_flags |= BGE_5705_PLUS; 2709 2710 /* 2711 * When using the BCM5701 in PCI-X mode, data corruption has 2712 * been observed in the first few bytes of some received packets. 2713 * Aligning the packet buffer in memory eliminates the corruption. 2714 * Unfortunately, this misaligns the packet payloads. On platforms 2715 * which do not support unaligned accesses, we will realign the 2716 * payloads by copying the received packets. 2717 */ 2718 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5701 && 2719 sc->bge_flags & BGE_PCIX) 2720 sc->bge_flags |= BGE_RX_ALIGNBUG; 2721 2722 if (BGE_IS_5700_FAMILY(sc)) 2723 sc->bge_flags |= BGE_JUMBO_CAPABLE; 2724 2725 if ((BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 2726 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5701) && 2727 PCI_VENDOR(subid) == PCI_VENDOR_DELL) 2728 sc->bge_flags |= BGE_NO_3LED; 2729 2730 misccfg = CSR_READ_4(sc, BGE_MISC_CFG); 2731 misccfg &= BGE_MISCCFG_BOARD_ID_MASK; 2732 2733 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5705 && 2734 (misccfg == BGE_MISCCFG_BOARD_ID_5788 || 2735 misccfg == BGE_MISCCFG_BOARD_ID_5788M)) 2736 sc->bge_flags |= BGE_IS_5788; 2737 2738 /* 2739 * Some controllers seem to require a special firmware to use 2740 * TSO. But the firmware is not available to FreeBSD and Linux 2741 * claims that the TSO performed by the firmware is slower than 2742 * hardware based TSO. Moreover the firmware based TSO has one 2743 * known bug which can't handle TSO if ethernet header + IP/TCP 2744 * header is greater than 80 bytes. The workaround for the TSO 2745 * bug exist but it seems it's too expensive than not using 2746 * TSO at all. Some hardwares also have the TSO bug so limit 2747 * the TSO to the controllers that are not affected TSO issues 2748 * (e.g. 5755 or higher). 2749 */ 2750 if (BGE_IS_5755_PLUS(sc)) { 2751 /* 2752 * BCM5754 and BCM5787 shares the same ASIC id so 2753 * explicit device id check is required. 2754 */ 2755 if ((PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_BROADCOM_BCM5754) && 2756 (PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_BROADCOM_BCM5754M)) 2757 sc->bge_flags |= BGE_TSO; 2758 } 2759 2760 if ((BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5703 && 2761 (misccfg == 0x4000 || misccfg == 0x8000)) || 2762 (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5705 && 2763 PCI_VENDOR(pa->pa_id) == PCI_VENDOR_BROADCOM && 2764 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5901 || 2765 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5901A2 || 2766 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5705F)) || 2767 (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_BROADCOM && 2768 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5751F || 2769 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5753F || 2770 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5787F)) || 2771 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM57790 || 2772 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 2773 sc->bge_flags |= BGE_10_100_ONLY; 2774 2775 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 2776 (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5705 && 2777 (sc->bge_chipid != BGE_CHIPID_BCM5705_A0 && 2778 sc->bge_chipid != BGE_CHIPID_BCM5705_A1)) || 2779 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 2780 sc->bge_flags |= BGE_NO_ETH_WIRE_SPEED; 2781 2782 if (sc->bge_chipid == BGE_CHIPID_BCM5701_A0 || 2783 sc->bge_chipid == BGE_CHIPID_BCM5701_B0) 2784 sc->bge_flags |= BGE_PHY_CRC_BUG; 2785 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5703_AX || 2786 BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5704_AX) 2787 sc->bge_flags |= BGE_PHY_ADC_BUG; 2788 if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0) 2789 sc->bge_flags |= BGE_PHY_5704_A0_BUG; 2790 2791 if (BGE_IS_5705_PLUS(sc) && 2792 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5906 && 2793 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5717 && 2794 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5785 && 2795 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM57765 && 2796 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM57766 && 2797 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM57780) { 2798 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5755 || 2799 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761 || 2800 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5784 || 2801 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5787) { 2802 if (PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_BROADCOM_BCM5722 && 2803 PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_BROADCOM_BCM5756) 2804 sc->bge_flags |= BGE_PHY_JITTER_BUG; 2805 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5755M) 2806 sc->bge_flags |= BGE_PHY_ADJUST_TRIM; 2807 } else if (BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5906) 2808 sc->bge_flags |= BGE_PHY_BER_BUG; 2809 } 2810 2811 /* 2812 * SEEPROM check. 2813 * First check if firmware knows we do not have SEEPROM. 2814 */ 2815 if (prop_dictionary_get_bool(device_properties(self), 2816 "without-seeprom", &no_seeprom) && no_seeprom) 2817 sc->bge_flags |= BGE_NO_EEPROM; 2818 2819 /* Now check the 'ROM failed' bit on the RX CPU */ 2820 else if (CSR_READ_4(sc, BGE_RXCPU_MODE) & BGE_RXCPUMODE_ROMFAIL) 2821 sc->bge_flags |= BGE_NO_EEPROM; 2822 2823 /* Try to reset the chip. */ 2824 DPRINTFN(5, ("bge_reset\n")); 2825 bge_reset(sc); 2826 2827 sc->bge_asf_mode = 0; 2828 if (bge_allow_asf && (bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_SIG) 2829 == BGE_MAGIC_NUMBER)) { 2830 if (bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_NICCFG) 2831 & BGE_HWCFG_ASF) { 2832 sc->bge_asf_mode |= ASF_ENABLE; 2833 sc->bge_asf_mode |= ASF_STACKUP; 2834 if (BGE_IS_575X_PLUS(sc)) { 2835 sc->bge_asf_mode |= ASF_NEW_HANDSHAKE; 2836 } 2837 } 2838 } 2839 2840 /* Try to reset the chip again the nice way. */ 2841 bge_stop_fw(sc); 2842 bge_sig_pre_reset(sc, BGE_RESET_STOP); 2843 if (bge_reset(sc)) 2844 aprint_error_dev(sc->bge_dev, "chip reset failed\n"); 2845 2846 bge_sig_legacy(sc, BGE_RESET_STOP); 2847 bge_sig_post_reset(sc, BGE_RESET_STOP); 2848 2849 if (bge_chipinit(sc)) { 2850 aprint_error_dev(sc->bge_dev, "chip initialization failed\n"); 2851 bge_release_resources(sc); 2852 return; 2853 } 2854 2855 /* 2856 * Get station address from the EEPROM. 2857 */ 2858 if (bge_get_eaddr(sc, eaddr)) { 2859 aprint_error_dev(sc->bge_dev, 2860 "failed to read station address\n"); 2861 bge_release_resources(sc); 2862 return; 2863 } 2864 2865 br = bge_lookup_rev(sc->bge_chipid); 2866 2867 if (br == NULL) { 2868 aprint_normal_dev(sc->bge_dev, "unknown ASIC (0x%x)", 2869 sc->bge_chipid); 2870 } else { 2871 aprint_normal_dev(sc->bge_dev, "ASIC %s (0x%x)", 2872 br->br_name, sc->bge_chipid); 2873 } 2874 aprint_normal(", Ethernet address %s\n", ether_sprintf(eaddr)); 2875 2876 /* Allocate the general information block and ring buffers. */ 2877 if (pci_dma64_available(pa)) 2878 sc->bge_dmatag = pa->pa_dmat64; 2879 else 2880 sc->bge_dmatag = pa->pa_dmat; 2881 DPRINTFN(5, ("bus_dmamem_alloc\n")); 2882 if (bus_dmamem_alloc(sc->bge_dmatag, sizeof(struct bge_ring_data), 2883 PAGE_SIZE, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 2884 aprint_error_dev(sc->bge_dev, "can't alloc rx buffers\n"); 2885 return; 2886 } 2887 DPRINTFN(5, ("bus_dmamem_map\n")); 2888 if (bus_dmamem_map(sc->bge_dmatag, &seg, rseg, 2889 sizeof(struct bge_ring_data), &kva, 2890 BUS_DMA_NOWAIT)) { 2891 aprint_error_dev(sc->bge_dev, 2892 "can't map DMA buffers (%zu bytes)\n", 2893 sizeof(struct bge_ring_data)); 2894 bus_dmamem_free(sc->bge_dmatag, &seg, rseg); 2895 return; 2896 } 2897 DPRINTFN(5, ("bus_dmamem_create\n")); 2898 if (bus_dmamap_create(sc->bge_dmatag, sizeof(struct bge_ring_data), 1, 2899 sizeof(struct bge_ring_data), 0, 2900 BUS_DMA_NOWAIT, &sc->bge_ring_map)) { 2901 aprint_error_dev(sc->bge_dev, "can't create DMA map\n"); 2902 bus_dmamem_unmap(sc->bge_dmatag, kva, 2903 sizeof(struct bge_ring_data)); 2904 bus_dmamem_free(sc->bge_dmatag, &seg, rseg); 2905 return; 2906 } 2907 DPRINTFN(5, ("bus_dmamem_load\n")); 2908 if (bus_dmamap_load(sc->bge_dmatag, sc->bge_ring_map, kva, 2909 sizeof(struct bge_ring_data), NULL, 2910 BUS_DMA_NOWAIT)) { 2911 bus_dmamap_destroy(sc->bge_dmatag, sc->bge_ring_map); 2912 bus_dmamem_unmap(sc->bge_dmatag, kva, 2913 sizeof(struct bge_ring_data)); 2914 bus_dmamem_free(sc->bge_dmatag, &seg, rseg); 2915 return; 2916 } 2917 2918 DPRINTFN(5, ("bzero\n")); 2919 sc->bge_rdata = (struct bge_ring_data *)kva; 2920 2921 memset(sc->bge_rdata, 0, sizeof(struct bge_ring_data)); 2922 2923 /* Try to allocate memory for jumbo buffers. */ 2924 if (BGE_IS_JUMBO_CAPABLE(sc)) { 2925 if (bge_alloc_jumbo_mem(sc)) { 2926 aprint_error_dev(sc->bge_dev, 2927 "jumbo buffer allocation failed\n"); 2928 } else 2929 sc->ethercom.ec_capabilities |= ETHERCAP_JUMBO_MTU; 2930 } 2931 2932 /* Set default tuneable values. */ 2933 sc->bge_stat_ticks = BGE_TICKS_PER_SEC; 2934 sc->bge_rx_coal_ticks = 150; 2935 sc->bge_rx_max_coal_bds = 64; 2936 #ifdef ORIG_WPAUL_VALUES 2937 sc->bge_tx_coal_ticks = 150; 2938 sc->bge_tx_max_coal_bds = 128; 2939 #else 2940 sc->bge_tx_coal_ticks = 300; 2941 sc->bge_tx_max_coal_bds = 400; 2942 #endif 2943 if (BGE_IS_5705_PLUS(sc)) { 2944 sc->bge_tx_coal_ticks = (12 * 5); 2945 sc->bge_tx_max_coal_bds = (12 * 5); 2946 aprint_verbose_dev(sc->bge_dev, 2947 "setting short Tx thresholds\n"); 2948 } 2949 2950 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5717 || 2951 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57765 || 2952 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57766) 2953 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT; 2954 else if (BGE_IS_5705_PLUS(sc)) 2955 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT_5705; 2956 else 2957 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT; 2958 2959 /* Set up ifnet structure */ 2960 ifp = &sc->ethercom.ec_if; 2961 ifp->if_softc = sc; 2962 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 2963 ifp->if_ioctl = bge_ioctl; 2964 ifp->if_stop = bge_stop; 2965 ifp->if_start = bge_start; 2966 ifp->if_init = bge_init; 2967 ifp->if_watchdog = bge_watchdog; 2968 IFQ_SET_MAXLEN(&ifp->if_snd, max(BGE_TX_RING_CNT - 1, IFQ_MAXLEN)); 2969 IFQ_SET_READY(&ifp->if_snd); 2970 DPRINTFN(5, ("strcpy if_xname\n")); 2971 strcpy(ifp->if_xname, device_xname(sc->bge_dev)); 2972 2973 if (sc->bge_chipid != BGE_CHIPID_BCM5700_B0) 2974 sc->ethercom.ec_if.if_capabilities |= 2975 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx; 2976 #if 1 /* XXX TCP/UDP checksum offload breaks with pf(4) */ 2977 sc->ethercom.ec_if.if_capabilities |= 2978 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 2979 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 2980 #endif 2981 sc->ethercom.ec_capabilities |= 2982 ETHERCAP_VLAN_HWTAGGING | ETHERCAP_VLAN_MTU; 2983 2984 if (sc->bge_flags & BGE_TSO) 2985 sc->ethercom.ec_if.if_capabilities |= IFCAP_TSOv4; 2986 2987 /* 2988 * Do MII setup. 2989 */ 2990 DPRINTFN(5, ("mii setup\n")); 2991 sc->bge_mii.mii_ifp = ifp; 2992 sc->bge_mii.mii_readreg = bge_miibus_readreg; 2993 sc->bge_mii.mii_writereg = bge_miibus_writereg; 2994 sc->bge_mii.mii_statchg = bge_miibus_statchg; 2995 2996 /* 2997 * Figure out what sort of media we have by checking the hardware 2998 * config word in the first 32k of NIC internal memory, or fall back to 2999 * the config word in the EEPROM. Note: on some BCM5700 cards, 3000 * this value appears to be unset. If that's the case, we have to rely 3001 * on identifying the NIC by its PCI subsystem ID, as we do below for 3002 * the SysKonnect SK-9D41. 3003 */ 3004 if (bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_SIG) == BGE_MAGIC_NUMBER) { 3005 hwcfg = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_NICCFG); 3006 } else if (!(sc->bge_flags & BGE_NO_EEPROM)) { 3007 bge_read_eeprom(sc, (void *)&hwcfg, 3008 BGE_EE_HWCFG_OFFSET, sizeof(hwcfg)); 3009 hwcfg = be32toh(hwcfg); 3010 } 3011 /* The SysKonnect SK-9D41 is a 1000baseSX card. */ 3012 if (PCI_PRODUCT(pa->pa_id) == SK_SUBSYSID_9D41 || 3013 (hwcfg & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER) { 3014 if (BGE_IS_5714_FAMILY(sc)) 3015 sc->bge_flags |= BGE_PHY_FIBER_MII; 3016 else 3017 sc->bge_flags |= BGE_PHY_FIBER_TBI; 3018 } 3019 3020 /* set phyflags and chipid before mii_attach() */ 3021 dict = device_properties(self); 3022 prop_dictionary_set_uint32(dict, "phyflags", sc->bge_flags); 3023 prop_dictionary_set_uint32(dict, "chipid", sc->bge_chipid); 3024 3025 if (sc->bge_flags & BGE_PHY_FIBER_TBI) { 3026 ifmedia_init(&sc->bge_ifmedia, IFM_IMASK, bge_ifmedia_upd, 3027 bge_ifmedia_sts); 3028 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER |IFM_1000_SX, 0, NULL); 3029 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_1000_SX|IFM_FDX, 3030 0, NULL); 3031 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_AUTO, 0, NULL); 3032 ifmedia_set(&sc->bge_ifmedia, IFM_ETHER | IFM_AUTO); 3033 /* Pretend the user requested this setting */ 3034 sc->bge_ifmedia.ifm_media = sc->bge_ifmedia.ifm_cur->ifm_media; 3035 } else { 3036 /* 3037 * Do transceiver setup and tell the firmware the 3038 * driver is down so we can try to get access the 3039 * probe if ASF is running. Retry a couple of times 3040 * if we get a conflict with the ASF firmware accessing 3041 * the PHY. 3042 */ 3043 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 3044 bge_asf_driver_up(sc); 3045 3046 ifmedia_init(&sc->bge_mii.mii_media, 0, bge_ifmedia_upd, 3047 bge_ifmedia_sts); 3048 mii_attach(sc->bge_dev, &sc->bge_mii, 0xffffffff, 3049 MII_PHY_ANY, MII_OFFSET_ANY, 3050 MIIF_FORCEANEG|MIIF_DOPAUSE); 3051 3052 if (LIST_EMPTY(&sc->bge_mii.mii_phys)) { 3053 aprint_error_dev(sc->bge_dev, "no PHY found!\n"); 3054 ifmedia_add(&sc->bge_mii.mii_media, 3055 IFM_ETHER|IFM_MANUAL, 0, NULL); 3056 ifmedia_set(&sc->bge_mii.mii_media, 3057 IFM_ETHER|IFM_MANUAL); 3058 } else 3059 ifmedia_set(&sc->bge_mii.mii_media, 3060 IFM_ETHER|IFM_AUTO); 3061 3062 /* 3063 * Now tell the firmware we are going up after probing the PHY 3064 */ 3065 if (sc->bge_asf_mode & ASF_STACKUP) 3066 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 3067 } 3068 3069 /* 3070 * Call MI attach routine. 3071 */ 3072 DPRINTFN(5, ("if_attach\n")); 3073 if_attach(ifp); 3074 DPRINTFN(5, ("ether_ifattach\n")); 3075 ether_ifattach(ifp, eaddr); 3076 ether_set_ifflags_cb(&sc->ethercom, bge_ifflags_cb); 3077 rnd_attach_source(&sc->rnd_source, device_xname(sc->bge_dev), 3078 RND_TYPE_NET, 0); 3079 #ifdef BGE_EVENT_COUNTERS 3080 /* 3081 * Attach event counters. 3082 */ 3083 evcnt_attach_dynamic(&sc->bge_ev_intr, EVCNT_TYPE_INTR, 3084 NULL, device_xname(sc->bge_dev), "intr"); 3085 evcnt_attach_dynamic(&sc->bge_ev_tx_xoff, EVCNT_TYPE_MISC, 3086 NULL, device_xname(sc->bge_dev), "tx_xoff"); 3087 evcnt_attach_dynamic(&sc->bge_ev_tx_xon, EVCNT_TYPE_MISC, 3088 NULL, device_xname(sc->bge_dev), "tx_xon"); 3089 evcnt_attach_dynamic(&sc->bge_ev_rx_xoff, EVCNT_TYPE_MISC, 3090 NULL, device_xname(sc->bge_dev), "rx_xoff"); 3091 evcnt_attach_dynamic(&sc->bge_ev_rx_xon, EVCNT_TYPE_MISC, 3092 NULL, device_xname(sc->bge_dev), "rx_xon"); 3093 evcnt_attach_dynamic(&sc->bge_ev_rx_macctl, EVCNT_TYPE_MISC, 3094 NULL, device_xname(sc->bge_dev), "rx_macctl"); 3095 evcnt_attach_dynamic(&sc->bge_ev_xoffentered, EVCNT_TYPE_MISC, 3096 NULL, device_xname(sc->bge_dev), "xoffentered"); 3097 #endif /* BGE_EVENT_COUNTERS */ 3098 DPRINTFN(5, ("callout_init\n")); 3099 callout_init(&sc->bge_timeout, 0); 3100 3101 if (pmf_device_register(self, NULL, NULL)) 3102 pmf_class_network_register(self, ifp); 3103 else 3104 aprint_error_dev(self, "couldn't establish power handler\n"); 3105 3106 bge_sysctl_init(sc); 3107 3108 #ifdef BGE_DEBUG 3109 bge_debug_info(sc); 3110 #endif 3111 } 3112 3113 static void 3114 bge_release_resources(struct bge_softc *sc) 3115 { 3116 if (sc->bge_vpd_prodname != NULL) 3117 free(sc->bge_vpd_prodname, M_DEVBUF); 3118 3119 if (sc->bge_vpd_readonly != NULL) 3120 free(sc->bge_vpd_readonly, M_DEVBUF); 3121 } 3122 3123 static int 3124 bge_reset(struct bge_softc *sc) 3125 { 3126 uint32_t cachesize, command, pcistate, marbmode; 3127 #if 0 3128 uint32_t new_pcistate; 3129 #endif 3130 pcireg_t devctl, reg; 3131 int i, val; 3132 void (*write_op)(struct bge_softc *, int, int); 3133 3134 if (BGE_IS_575X_PLUS(sc) && !BGE_IS_5714_FAMILY(sc) 3135 && (BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5906)) { 3136 if (sc->bge_flags & BGE_PCIE) 3137 write_op = bge_writemem_direct; 3138 else 3139 write_op = bge_writemem_ind; 3140 } else 3141 write_op = bge_writereg_ind; 3142 3143 /* Save some important PCI state. */ 3144 cachesize = pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CACHESZ); 3145 command = pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CMD); 3146 pcistate = pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_PCISTATE); 3147 3148 /* Step 5a: Enable memory arbiter. */ 3149 marbmode = 0; 3150 if (BGE_IS_5714_FAMILY(sc)) 3151 marbmode = CSR_READ_4(sc, BGE_MARB_MODE); 3152 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE | marbmode); 3153 3154 /* Step 5b-5d: */ 3155 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MISC_CTL, 3156 BGE_PCIMISCCTL_INDIRECT_ACCESS | BGE_PCIMISCCTL_MASK_PCI_INTR | 3157 BGE_HIF_SWAP_OPTIONS | BGE_PCIMISCCTL_PCISTATE_RW); 3158 3159 /* XXX ???: Disable fastboot on controllers that support it. */ 3160 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5752 || 3161 BGE_IS_5755_PLUS(sc)) 3162 CSR_WRITE_4(sc, BGE_FASTBOOT_PC, 0); 3163 3164 /* 3165 * Step 6: Write the magic number to SRAM at offset 0xB50. 3166 * When firmware finishes its initialization it will 3167 * write ~BGE_MAGIC_NUMBER to the same location. 3168 */ 3169 bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM, BGE_MAGIC_NUMBER); 3170 3171 /* Step 7: */ 3172 val = BGE_MISCCFG_RESET_CORE_CLOCKS | (65<<1); 3173 /* 3174 * XXX: from FreeBSD/Linux; no documentation 3175 */ 3176 if (sc->bge_flags & BGE_PCIE) { 3177 if (CSR_READ_4(sc, BGE_PCIE_CTL1) == 0x60) 3178 /* PCI Express 1.0 system */ 3179 CSR_WRITE_4(sc, BGE_PCIE_CTL1, 0x20); 3180 if (sc->bge_chipid != BGE_CHIPID_BCM5750_A0) { 3181 /* 3182 * Prevent PCI Express link training 3183 * during global reset. 3184 */ 3185 CSR_WRITE_4(sc, BGE_MISC_CFG, 1 << 29); 3186 val |= (1<<29); 3187 } 3188 } 3189 3190 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 3191 i = CSR_READ_4(sc, BGE_VCPU_STATUS); 3192 CSR_WRITE_4(sc, BGE_VCPU_STATUS, 3193 i | BGE_VCPU_STATUS_DRV_RESET); 3194 i = CSR_READ_4(sc, BGE_VCPU_EXT_CTRL); 3195 CSR_WRITE_4(sc, BGE_VCPU_EXT_CTRL, 3196 i & ~BGE_VCPU_EXT_CTRL_HALT_CPU); 3197 } 3198 3199 /* 3200 * Set GPHY Power Down Override to leave GPHY 3201 * powered up in D0 uninitialized. 3202 */ 3203 if (BGE_IS_5705_PLUS(sc)) 3204 val |= BGE_MISCCFG_KEEP_GPHY_POWER; 3205 3206 /* XXX 5721, 5751 and 5752 */ 3207 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5750) 3208 val |= BGE_MISCCFG_GRC_RESET_DISABLE; 3209 3210 /* Issue global reset */ 3211 write_op(sc, BGE_MISC_CFG, val); 3212 3213 /* Step 8: wait for complete */ 3214 if (sc->bge_flags & BGE_PCIE) 3215 delay(100*1000); /* too big */ 3216 else 3217 delay(100); 3218 3219 /* From Linux: dummy read to flush PCI posted writes */ 3220 reg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CMD); 3221 3222 /* Step 9-10: Reset some of the PCI state that got zapped by reset */ 3223 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MISC_CTL, 3224 BGE_PCIMISCCTL_INDIRECT_ACCESS | BGE_PCIMISCCTL_MASK_PCI_INTR | 3225 BGE_HIF_SWAP_OPTIONS | BGE_PCIMISCCTL_PCISTATE_RW 3226 | BGE_PCIMISCCTL_CLOCKCTL_RW); 3227 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CMD, command); 3228 write_op(sc, BGE_MISC_CFG, (65 << 1)); 3229 3230 /* Step 11: disable PCI-X Relaxed Ordering. */ 3231 if (sc->bge_flags & BGE_PCIX) { 3232 reg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, sc->bge_pcixcap 3233 + PCI_PCIX_CMD); 3234 pci_conf_write(sc->sc_pc, sc->sc_pcitag, sc->bge_pcixcap 3235 + PCI_PCIX_CMD, reg & ~PCI_PCIX_CMD_RELAXED_ORDER); 3236 } 3237 3238 if (sc->bge_flags & BGE_PCIE) { 3239 if (sc->bge_chipid == BGE_CHIPID_BCM5750_A0) { 3240 DELAY(500000); 3241 /* XXX: Magic Numbers */ 3242 reg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 3243 BGE_PCI_UNKNOWN0); 3244 pci_conf_write(sc->sc_pc, sc->sc_pcitag, 3245 BGE_PCI_UNKNOWN0, 3246 reg | (1 << 15)); 3247 } 3248 devctl = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 3249 sc->bge_pciecap + PCI_PCIE_DCSR); 3250 /* Clear enable no snoop and disable relaxed ordering. */ 3251 devctl &= ~(PCI_PCIE_DCSR_ENA_RELAX_ORD | 3252 PCI_PCIE_DCSR_ENA_NO_SNOOP); 3253 /* Set PCIE max payload size to 128. */ 3254 devctl &= ~(0x00e0); 3255 /* Clear device status register. Write 1b to clear */ 3256 devctl |= PCI_PCIE_DCSR_URD | PCI_PCIE_DCSR_FED 3257 | PCI_PCIE_DCSR_NFED | PCI_PCIE_DCSR_CED; 3258 pci_conf_write(sc->sc_pc, sc->sc_pcitag, 3259 sc->bge_pciecap + PCI_PCIE_DCSR, devctl); 3260 } 3261 3262 /* Step 12: Enable memory arbiter. */ 3263 marbmode = 0; 3264 if (BGE_IS_5714_FAMILY(sc)) 3265 marbmode = CSR_READ_4(sc, BGE_MARB_MODE); 3266 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE | marbmode); 3267 3268 /* Step 17: Poll until the firmware initialization is complete */ 3269 bge_poll_fw(sc); 3270 3271 /* XXX 5721, 5751 and 5752 */ 3272 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5750) { 3273 /* Step 19: */ 3274 BGE_SETBIT(sc, BGE_TLP_CONTROL_REG, 1 << 29 | 1 << 25); 3275 /* Step 20: */ 3276 BGE_SETBIT(sc, BGE_TLP_CONTROL_REG, BGE_TLP_DATA_FIFO_PROTECT); 3277 } 3278 3279 /* 3280 * Step 18: wirte mac mode 3281 * XXX Write 0x0c for 5703S and 5704S 3282 */ 3283 CSR_WRITE_4(sc, BGE_MAC_MODE, 0); 3284 3285 3286 /* Step 21: 5822 B0 errata */ 3287 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5704_BX) { 3288 pcireg_t msidata; 3289 3290 msidata = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 3291 BGE_PCI_MSI_DATA); 3292 msidata |= ((1 << 13 | 1 << 12 | 1 << 10) << 16); 3293 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MSI_DATA, 3294 msidata); 3295 } 3296 3297 /* Step 23: restore cache line size */ 3298 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CACHESZ, cachesize); 3299 3300 #if 0 3301 /* 3302 * XXX Wait for the value of the PCISTATE register to 3303 * return to its original pre-reset state. This is a 3304 * fairly good indicator of reset completion. If we don't 3305 * wait for the reset to fully complete, trying to read 3306 * from the device's non-PCI registers may yield garbage 3307 * results. 3308 */ 3309 for (i = 0; i < BGE_TIMEOUT; i++) { 3310 new_pcistate = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 3311 BGE_PCI_PCISTATE); 3312 if ((new_pcistate & ~BGE_PCISTATE_RESERVED) == 3313 (pcistate & ~BGE_PCISTATE_RESERVED)) 3314 break; 3315 DELAY(10); 3316 } 3317 if ((new_pcistate & ~BGE_PCISTATE_RESERVED) != 3318 (pcistate & ~BGE_PCISTATE_RESERVED)) { 3319 aprint_error_dev(sc->bge_dev, "pcistate failed to revert\n"); 3320 } 3321 #endif 3322 3323 /* Step 28: Fix up byte swapping */ 3324 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS); 3325 3326 /* Tell the ASF firmware we are up */ 3327 if (sc->bge_asf_mode & ASF_STACKUP) 3328 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 3329 3330 /* 3331 * The 5704 in TBI mode apparently needs some special 3332 * adjustment to insure the SERDES drive level is set 3333 * to 1.2V. 3334 */ 3335 if (sc->bge_flags & BGE_PHY_FIBER_TBI && 3336 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) { 3337 uint32_t serdescfg; 3338 3339 serdescfg = CSR_READ_4(sc, BGE_SERDES_CFG); 3340 serdescfg = (serdescfg & ~0xFFF) | 0x880; 3341 CSR_WRITE_4(sc, BGE_SERDES_CFG, serdescfg); 3342 } 3343 3344 if (sc->bge_flags & BGE_PCIE && 3345 sc->bge_chipid != BGE_CHIPID_BCM5750_A0 && 3346 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5717 && 3347 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5785 && 3348 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM57765 && 3349 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM57766) { 3350 uint32_t v; 3351 3352 /* Enable PCI Express bug fix */ 3353 v = CSR_READ_4(sc, 0x7c00); 3354 CSR_WRITE_4(sc, 0x7c00, v | (1<<25)); 3355 } 3356 DELAY(10000); 3357 3358 return 0; 3359 } 3360 3361 /* 3362 * Frame reception handling. This is called if there's a frame 3363 * on the receive return list. 3364 * 3365 * Note: we have to be able to handle two possibilities here: 3366 * 1) the frame is from the jumbo receive ring 3367 * 2) the frame is from the standard receive ring 3368 */ 3369 3370 static void 3371 bge_rxeof(struct bge_softc *sc) 3372 { 3373 struct ifnet *ifp; 3374 uint16_t rx_prod, rx_cons; 3375 int stdcnt = 0, jumbocnt = 0; 3376 bus_dmamap_t dmamap; 3377 bus_addr_t offset, toff; 3378 bus_size_t tlen; 3379 int tosync; 3380 3381 rx_cons = sc->bge_rx_saved_considx; 3382 rx_prod = sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx; 3383 3384 /* Nothing to do */ 3385 if (rx_cons == rx_prod) 3386 return; 3387 3388 ifp = &sc->ethercom.ec_if; 3389 3390 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 3391 offsetof(struct bge_ring_data, bge_status_block), 3392 sizeof (struct bge_status_block), 3393 BUS_DMASYNC_POSTREAD); 3394 3395 offset = offsetof(struct bge_ring_data, bge_rx_return_ring); 3396 tosync = rx_prod - rx_cons; 3397 3398 if (tosync != 0) 3399 rnd_add_uint32(&sc->rnd_source, tosync); 3400 3401 toff = offset + (rx_cons * sizeof (struct bge_rx_bd)); 3402 3403 if (tosync < 0) { 3404 tlen = (sc->bge_return_ring_cnt - rx_cons) * 3405 sizeof (struct bge_rx_bd); 3406 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 3407 toff, tlen, BUS_DMASYNC_POSTREAD); 3408 tosync = -tosync; 3409 } 3410 3411 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 3412 offset, tosync * sizeof (struct bge_rx_bd), 3413 BUS_DMASYNC_POSTREAD); 3414 3415 while (rx_cons != rx_prod) { 3416 struct bge_rx_bd *cur_rx; 3417 uint32_t rxidx; 3418 struct mbuf *m = NULL; 3419 3420 cur_rx = &sc->bge_rdata->bge_rx_return_ring[rx_cons]; 3421 3422 rxidx = cur_rx->bge_idx; 3423 BGE_INC(rx_cons, sc->bge_return_ring_cnt); 3424 3425 if (cur_rx->bge_flags & BGE_RXBDFLAG_JUMBO_RING) { 3426 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT); 3427 m = sc->bge_cdata.bge_rx_jumbo_chain[rxidx]; 3428 sc->bge_cdata.bge_rx_jumbo_chain[rxidx] = NULL; 3429 jumbocnt++; 3430 bus_dmamap_sync(sc->bge_dmatag, 3431 sc->bge_cdata.bge_rx_jumbo_map, 3432 mtod(m, char *) - (char *)sc->bge_cdata.bge_jumbo_buf, 3433 BGE_JLEN, BUS_DMASYNC_POSTREAD); 3434 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 3435 ifp->if_ierrors++; 3436 bge_newbuf_jumbo(sc, sc->bge_jumbo, m); 3437 continue; 3438 } 3439 if (bge_newbuf_jumbo(sc, sc->bge_jumbo, 3440 NULL)== ENOBUFS) { 3441 ifp->if_ierrors++; 3442 bge_newbuf_jumbo(sc, sc->bge_jumbo, m); 3443 continue; 3444 } 3445 } else { 3446 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT); 3447 m = sc->bge_cdata.bge_rx_std_chain[rxidx]; 3448 3449 sc->bge_cdata.bge_rx_std_chain[rxidx] = NULL; 3450 stdcnt++; 3451 dmamap = sc->bge_cdata.bge_rx_std_map[rxidx]; 3452 sc->bge_cdata.bge_rx_std_map[rxidx] = 0; 3453 if (dmamap == NULL) { 3454 ifp->if_ierrors++; 3455 bge_newbuf_std(sc, sc->bge_std, m, dmamap); 3456 continue; 3457 } 3458 bus_dmamap_sync(sc->bge_dmatag, dmamap, 0, 3459 dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 3460 bus_dmamap_unload(sc->bge_dmatag, dmamap); 3461 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 3462 ifp->if_ierrors++; 3463 bge_newbuf_std(sc, sc->bge_std, m, dmamap); 3464 continue; 3465 } 3466 if (bge_newbuf_std(sc, sc->bge_std, 3467 NULL, dmamap) == ENOBUFS) { 3468 ifp->if_ierrors++; 3469 bge_newbuf_std(sc, sc->bge_std, m, dmamap); 3470 continue; 3471 } 3472 } 3473 3474 ifp->if_ipackets++; 3475 #ifndef __NO_STRICT_ALIGNMENT 3476 /* 3477 * XXX: if the 5701 PCIX-Rx-DMA workaround is in effect, 3478 * the Rx buffer has the layer-2 header unaligned. 3479 * If our CPU requires alignment, re-align by copying. 3480 */ 3481 if (sc->bge_flags & BGE_RX_ALIGNBUG) { 3482 memmove(mtod(m, char *) + ETHER_ALIGN, m->m_data, 3483 cur_rx->bge_len); 3484 m->m_data += ETHER_ALIGN; 3485 } 3486 #endif 3487 3488 m->m_pkthdr.len = m->m_len = cur_rx->bge_len - ETHER_CRC_LEN; 3489 m->m_pkthdr.rcvif = ifp; 3490 3491 /* 3492 * Handle BPF listeners. Let the BPF user see the packet. 3493 */ 3494 bpf_mtap(ifp, m); 3495 3496 m->m_pkthdr.csum_flags = M_CSUM_IPv4; 3497 3498 if ((cur_rx->bge_ip_csum ^ 0xffff) != 0) 3499 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 3500 /* 3501 * Rx transport checksum-offload may also 3502 * have bugs with packets which, when transmitted, 3503 * were `runts' requiring padding. 3504 */ 3505 if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM && 3506 (/* (sc->_bge_quirks & BGE_QUIRK_SHORT_CKSUM_BUG) == 0 ||*/ 3507 m->m_pkthdr.len >= ETHER_MIN_NOPAD)) { 3508 m->m_pkthdr.csum_data = 3509 cur_rx->bge_tcp_udp_csum; 3510 m->m_pkthdr.csum_flags |= 3511 (M_CSUM_TCPv4|M_CSUM_UDPv4| 3512 M_CSUM_DATA); 3513 } 3514 3515 /* 3516 * If we received a packet with a vlan tag, pass it 3517 * to vlan_input() instead of ether_input(). 3518 */ 3519 if (cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) { 3520 VLAN_INPUT_TAG(ifp, m, cur_rx->bge_vlan_tag, continue); 3521 } 3522 3523 (*ifp->if_input)(ifp, m); 3524 } 3525 3526 sc->bge_rx_saved_considx = rx_cons; 3527 bge_writembx(sc, BGE_MBX_RX_CONS0_LO, sc->bge_rx_saved_considx); 3528 if (stdcnt) 3529 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std); 3530 if (jumbocnt) 3531 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo); 3532 } 3533 3534 static void 3535 bge_txeof(struct bge_softc *sc) 3536 { 3537 struct bge_tx_bd *cur_tx = NULL; 3538 struct ifnet *ifp; 3539 struct txdmamap_pool_entry *dma; 3540 bus_addr_t offset, toff; 3541 bus_size_t tlen; 3542 int tosync; 3543 struct mbuf *m; 3544 3545 ifp = &sc->ethercom.ec_if; 3546 3547 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 3548 offsetof(struct bge_ring_data, bge_status_block), 3549 sizeof (struct bge_status_block), 3550 BUS_DMASYNC_POSTREAD); 3551 3552 offset = offsetof(struct bge_ring_data, bge_tx_ring); 3553 tosync = sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx - 3554 sc->bge_tx_saved_considx; 3555 3556 if (tosync != 0) 3557 rnd_add_uint32(&sc->rnd_source, tosync); 3558 3559 toff = offset + (sc->bge_tx_saved_considx * sizeof (struct bge_tx_bd)); 3560 3561 if (tosync < 0) { 3562 tlen = (BGE_TX_RING_CNT - sc->bge_tx_saved_considx) * 3563 sizeof (struct bge_tx_bd); 3564 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 3565 toff, tlen, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 3566 tosync = -tosync; 3567 } 3568 3569 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 3570 offset, tosync * sizeof (struct bge_tx_bd), 3571 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 3572 3573 /* 3574 * Go through our tx ring and free mbufs for those 3575 * frames that have been sent. 3576 */ 3577 while (sc->bge_tx_saved_considx != 3578 sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx) { 3579 uint32_t idx = 0; 3580 3581 idx = sc->bge_tx_saved_considx; 3582 cur_tx = &sc->bge_rdata->bge_tx_ring[idx]; 3583 if (cur_tx->bge_flags & BGE_TXBDFLAG_END) 3584 ifp->if_opackets++; 3585 m = sc->bge_cdata.bge_tx_chain[idx]; 3586 if (m != NULL) { 3587 sc->bge_cdata.bge_tx_chain[idx] = NULL; 3588 dma = sc->txdma[idx]; 3589 bus_dmamap_sync(sc->bge_dmatag, dma->dmamap, 0, 3590 dma->dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 3591 bus_dmamap_unload(sc->bge_dmatag, dma->dmamap); 3592 SLIST_INSERT_HEAD(&sc->txdma_list, dma, link); 3593 sc->txdma[idx] = NULL; 3594 3595 m_freem(m); 3596 } 3597 sc->bge_txcnt--; 3598 BGE_INC(sc->bge_tx_saved_considx, BGE_TX_RING_CNT); 3599 ifp->if_timer = 0; 3600 } 3601 3602 if (cur_tx != NULL) 3603 ifp->if_flags &= ~IFF_OACTIVE; 3604 } 3605 3606 static int 3607 bge_intr(void *xsc) 3608 { 3609 struct bge_softc *sc; 3610 struct ifnet *ifp; 3611 uint32_t statusword; 3612 3613 sc = xsc; 3614 ifp = &sc->ethercom.ec_if; 3615 3616 /* It is possible for the interrupt to arrive before 3617 * the status block is updated prior to the interrupt. 3618 * Reading the PCI State register will confirm whether the 3619 * interrupt is ours and will flush the status block. 3620 */ 3621 3622 /* read status word from status block */ 3623 statusword = sc->bge_rdata->bge_status_block.bge_status; 3624 3625 if ((statusword & BGE_STATFLAG_UPDATED) || 3626 (!(pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_PCISTATE) & 3627 BGE_PCISTATE_INTR_NOT_ACTIVE))) { 3628 /* Ack interrupt and stop others from occuring. */ 3629 bge_writembx(sc, BGE_MBX_IRQ0_LO, 1); 3630 3631 BGE_EVCNT_INCR(sc->bge_ev_intr); 3632 3633 /* clear status word */ 3634 sc->bge_rdata->bge_status_block.bge_status = 0; 3635 3636 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 3637 statusword & BGE_STATFLAG_LINKSTATE_CHANGED || 3638 BGE_STS_BIT(sc, BGE_STS_LINK_EVT)) 3639 bge_link_upd(sc); 3640 3641 if (ifp->if_flags & IFF_RUNNING) { 3642 /* Check RX return ring producer/consumer */ 3643 bge_rxeof(sc); 3644 3645 /* Check TX ring producer/consumer */ 3646 bge_txeof(sc); 3647 } 3648 3649 if (sc->bge_pending_rxintr_change) { 3650 uint32_t rx_ticks = sc->bge_rx_coal_ticks; 3651 uint32_t rx_bds = sc->bge_rx_max_coal_bds; 3652 uint32_t junk; 3653 3654 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, rx_ticks); 3655 DELAY(10); 3656 junk = CSR_READ_4(sc, BGE_HCC_RX_COAL_TICKS); 3657 3658 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, rx_bds); 3659 DELAY(10); 3660 junk = CSR_READ_4(sc, BGE_HCC_RX_MAX_COAL_BDS); 3661 3662 sc->bge_pending_rxintr_change = 0; 3663 } 3664 bge_handle_events(sc); 3665 3666 /* Re-enable interrupts. */ 3667 bge_writembx(sc, BGE_MBX_IRQ0_LO, 0); 3668 3669 if (ifp->if_flags & IFF_RUNNING && !IFQ_IS_EMPTY(&ifp->if_snd)) 3670 bge_start(ifp); 3671 3672 return 1; 3673 } else 3674 return 0; 3675 } 3676 3677 static void 3678 bge_asf_driver_up(struct bge_softc *sc) 3679 { 3680 if (sc->bge_asf_mode & ASF_STACKUP) { 3681 /* Send ASF heartbeat aprox. every 2s */ 3682 if (sc->bge_asf_count) 3683 sc->bge_asf_count --; 3684 else { 3685 sc->bge_asf_count = 2; 3686 bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM_FW, 3687 BGE_FW_DRV_ALIVE); 3688 bge_writemem_ind(sc, BGE_SOFTWARE_GENNCOMM_FW_LEN, 4); 3689 bge_writemem_ind(sc, BGE_SOFTWARE_GENNCOMM_FW_DATA, 3); 3690 CSR_WRITE_4(sc, BGE_CPU_EVENT, 3691 CSR_READ_4(sc, BGE_CPU_EVENT) | (1 << 14)); 3692 } 3693 } 3694 } 3695 3696 static void 3697 bge_tick(void *xsc) 3698 { 3699 struct bge_softc *sc = xsc; 3700 struct mii_data *mii = &sc->bge_mii; 3701 int s; 3702 3703 s = splnet(); 3704 3705 if (BGE_IS_5705_PLUS(sc)) 3706 bge_stats_update_regs(sc); 3707 else 3708 bge_stats_update(sc); 3709 3710 if (sc->bge_flags & BGE_PHY_FIBER_TBI) { 3711 /* 3712 * Since in TBI mode auto-polling can't be used we should poll 3713 * link status manually. Here we register pending link event 3714 * and trigger interrupt. 3715 */ 3716 BGE_STS_SETBIT(sc, BGE_STS_LINK_EVT); 3717 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET); 3718 } else { 3719 /* 3720 * Do not touch PHY if we have link up. This could break 3721 * IPMI/ASF mode or produce extra input errors. 3722 * (extra input errors was reported for bcm5701 & bcm5704). 3723 */ 3724 if (!BGE_STS_BIT(sc, BGE_STS_LINK)) 3725 mii_tick(mii); 3726 } 3727 3728 callout_reset(&sc->bge_timeout, hz, bge_tick, sc); 3729 3730 splx(s); 3731 } 3732 3733 static void 3734 bge_stats_update_regs(struct bge_softc *sc) 3735 { 3736 struct ifnet *ifp = &sc->ethercom.ec_if; 3737 3738 ifp->if_collisions += CSR_READ_4(sc, BGE_MAC_STATS + 3739 offsetof(struct bge_mac_stats_regs, etherStatsCollisions)); 3740 3741 ifp->if_ierrors += CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_DROPS); 3742 ifp->if_ierrors += CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_ERRORS); 3743 ifp->if_ierrors += CSR_READ_4(sc, BGE_RXLP_LOCSTAT_OUT_OF_BDS); 3744 } 3745 3746 static void 3747 bge_stats_update(struct bge_softc *sc) 3748 { 3749 struct ifnet *ifp = &sc->ethercom.ec_if; 3750 bus_size_t stats = BGE_MEMWIN_START + BGE_STATS_BLOCK; 3751 3752 #define READ_STAT(sc, stats, stat) \ 3753 CSR_READ_4(sc, stats + offsetof(struct bge_stats, stat)) 3754 3755 ifp->if_collisions += 3756 (READ_STAT(sc, stats, dot3StatsSingleCollisionFrames.bge_addr_lo) + 3757 READ_STAT(sc, stats, dot3StatsMultipleCollisionFrames.bge_addr_lo) + 3758 READ_STAT(sc, stats, dot3StatsExcessiveCollisions.bge_addr_lo) + 3759 READ_STAT(sc, stats, dot3StatsLateCollisions.bge_addr_lo)) - 3760 ifp->if_collisions; 3761 3762 BGE_EVCNT_UPD(sc->bge_ev_tx_xoff, 3763 READ_STAT(sc, stats, outXoffSent.bge_addr_lo)); 3764 BGE_EVCNT_UPD(sc->bge_ev_tx_xon, 3765 READ_STAT(sc, stats, outXonSent.bge_addr_lo)); 3766 BGE_EVCNT_UPD(sc->bge_ev_rx_xoff, 3767 READ_STAT(sc, stats, 3768 xoffPauseFramesReceived.bge_addr_lo)); 3769 BGE_EVCNT_UPD(sc->bge_ev_rx_xon, 3770 READ_STAT(sc, stats, xonPauseFramesReceived.bge_addr_lo)); 3771 BGE_EVCNT_UPD(sc->bge_ev_rx_macctl, 3772 READ_STAT(sc, stats, 3773 macControlFramesReceived.bge_addr_lo)); 3774 BGE_EVCNT_UPD(sc->bge_ev_xoffentered, 3775 READ_STAT(sc, stats, xoffStateEntered.bge_addr_lo)); 3776 3777 #undef READ_STAT 3778 3779 #ifdef notdef 3780 ifp->if_collisions += 3781 (sc->bge_rdata->bge_info.bge_stats.dot3StatsSingleCollisionFrames + 3782 sc->bge_rdata->bge_info.bge_stats.dot3StatsMultipleCollisionFrames + 3783 sc->bge_rdata->bge_info.bge_stats.dot3StatsExcessiveCollisions + 3784 sc->bge_rdata->bge_info.bge_stats.dot3StatsLateCollisions) - 3785 ifp->if_collisions; 3786 #endif 3787 } 3788 3789 /* 3790 * Pad outbound frame to ETHER_MIN_NOPAD for an unusual reason. 3791 * The bge hardware will pad out Tx runts to ETHER_MIN_NOPAD, 3792 * but when such padded frames employ the bge IP/TCP checksum offload, 3793 * the hardware checksum assist gives incorrect results (possibly 3794 * from incorporating its own padding into the UDP/TCP checksum; who knows). 3795 * If we pad such runts with zeros, the onboard checksum comes out correct. 3796 */ 3797 static inline int 3798 bge_cksum_pad(struct mbuf *pkt) 3799 { 3800 struct mbuf *last = NULL; 3801 int padlen; 3802 3803 padlen = ETHER_MIN_NOPAD - pkt->m_pkthdr.len; 3804 3805 /* if there's only the packet-header and we can pad there, use it. */ 3806 if (pkt->m_pkthdr.len == pkt->m_len && 3807 M_TRAILINGSPACE(pkt) >= padlen) { 3808 last = pkt; 3809 } else { 3810 /* 3811 * Walk packet chain to find last mbuf. We will either 3812 * pad there, or append a new mbuf and pad it 3813 * (thus perhaps avoiding the bcm5700 dma-min bug). 3814 */ 3815 for (last = pkt; last->m_next != NULL; last = last->m_next) { 3816 continue; /* do nothing */ 3817 } 3818 3819 /* `last' now points to last in chain. */ 3820 if (M_TRAILINGSPACE(last) < padlen) { 3821 /* Allocate new empty mbuf, pad it. Compact later. */ 3822 struct mbuf *n; 3823 MGET(n, M_DONTWAIT, MT_DATA); 3824 if (n == NULL) 3825 return ENOBUFS; 3826 n->m_len = 0; 3827 last->m_next = n; 3828 last = n; 3829 } 3830 } 3831 3832 KDASSERT(!M_READONLY(last)); 3833 KDASSERT(M_TRAILINGSPACE(last) >= padlen); 3834 3835 /* Now zero the pad area, to avoid the bge cksum-assist bug */ 3836 memset(mtod(last, char *) + last->m_len, 0, padlen); 3837 last->m_len += padlen; 3838 pkt->m_pkthdr.len += padlen; 3839 return 0; 3840 } 3841 3842 /* 3843 * Compact outbound packets to avoid bug with DMA segments less than 8 bytes. 3844 */ 3845 static inline int 3846 bge_compact_dma_runt(struct mbuf *pkt) 3847 { 3848 struct mbuf *m, *prev; 3849 int totlen, prevlen; 3850 3851 prev = NULL; 3852 totlen = 0; 3853 prevlen = -1; 3854 3855 for (m = pkt; m != NULL; prev = m,m = m->m_next) { 3856 int mlen = m->m_len; 3857 int shortfall = 8 - mlen ; 3858 3859 totlen += mlen; 3860 if (mlen == 0) 3861 continue; 3862 if (mlen >= 8) 3863 continue; 3864 3865 /* If we get here, mbuf data is too small for DMA engine. 3866 * Try to fix by shuffling data to prev or next in chain. 3867 * If that fails, do a compacting deep-copy of the whole chain. 3868 */ 3869 3870 /* Internal frag. If fits in prev, copy it there. */ 3871 if (prev && M_TRAILINGSPACE(prev) >= m->m_len) { 3872 memcpy(prev->m_data + prev->m_len, m->m_data, mlen); 3873 prev->m_len += mlen; 3874 m->m_len = 0; 3875 /* XXX stitch chain */ 3876 prev->m_next = m_free(m); 3877 m = prev; 3878 continue; 3879 } 3880 else if (m->m_next != NULL && 3881 M_TRAILINGSPACE(m) >= shortfall && 3882 m->m_next->m_len >= (8 + shortfall)) { 3883 /* m is writable and have enough data in next, pull up. */ 3884 3885 memcpy(m->m_data + m->m_len, m->m_next->m_data, 3886 shortfall); 3887 m->m_len += shortfall; 3888 m->m_next->m_len -= shortfall; 3889 m->m_next->m_data += shortfall; 3890 } 3891 else if (m->m_next == NULL || 1) { 3892 /* Got a runt at the very end of the packet. 3893 * borrow data from the tail of the preceding mbuf and 3894 * update its length in-place. (The original data is still 3895 * valid, so we can do this even if prev is not writable.) 3896 */ 3897 3898 /* if we'd make prev a runt, just move all of its data. */ 3899 KASSERT(prev != NULL /*, ("runt but null PREV")*/); 3900 KASSERT(prev->m_len >= 8 /*, ("runt prev")*/); 3901 3902 if ((prev->m_len - shortfall) < 8) 3903 shortfall = prev->m_len; 3904 3905 #ifdef notyet /* just do the safe slow thing for now */ 3906 if (!M_READONLY(m)) { 3907 if (M_LEADINGSPACE(m) < shorfall) { 3908 void *m_dat; 3909 m_dat = (m->m_flags & M_PKTHDR) ? 3910 m->m_pktdat : m->dat; 3911 memmove(m_dat, mtod(m, void*), m->m_len); 3912 m->m_data = m_dat; 3913 } 3914 } else 3915 #endif /* just do the safe slow thing */ 3916 { 3917 struct mbuf * n = NULL; 3918 int newprevlen = prev->m_len - shortfall; 3919 3920 MGET(n, M_NOWAIT, MT_DATA); 3921 if (n == NULL) 3922 return ENOBUFS; 3923 KASSERT(m->m_len + shortfall < MLEN 3924 /*, 3925 ("runt %d +prev %d too big\n", m->m_len, shortfall)*/); 3926 3927 /* first copy the data we're stealing from prev */ 3928 memcpy(n->m_data, prev->m_data + newprevlen, 3929 shortfall); 3930 3931 /* update prev->m_len accordingly */ 3932 prev->m_len -= shortfall; 3933 3934 /* copy data from runt m */ 3935 memcpy(n->m_data + shortfall, m->m_data, 3936 m->m_len); 3937 3938 /* n holds what we stole from prev, plus m */ 3939 n->m_len = shortfall + m->m_len; 3940 3941 /* stitch n into chain and free m */ 3942 n->m_next = m->m_next; 3943 prev->m_next = n; 3944 /* KASSERT(m->m_next == NULL); */ 3945 m->m_next = NULL; 3946 m_free(m); 3947 m = n; /* for continuing loop */ 3948 } 3949 } 3950 prevlen = m->m_len; 3951 } 3952 return 0; 3953 } 3954 3955 /* 3956 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data 3957 * pointers to descriptors. 3958 */ 3959 static int 3960 bge_encap(struct bge_softc *sc, struct mbuf *m_head, uint32_t *txidx) 3961 { 3962 struct bge_tx_bd *f = NULL; 3963 uint32_t frag, cur; 3964 uint16_t csum_flags = 0; 3965 uint16_t txbd_tso_flags = 0; 3966 struct txdmamap_pool_entry *dma; 3967 bus_dmamap_t dmamap; 3968 int i = 0; 3969 struct m_tag *mtag; 3970 int use_tso, maxsegsize, error; 3971 3972 cur = frag = *txidx; 3973 3974 if (m_head->m_pkthdr.csum_flags) { 3975 if (m_head->m_pkthdr.csum_flags & M_CSUM_IPv4) 3976 csum_flags |= BGE_TXBDFLAG_IP_CSUM; 3977 if (m_head->m_pkthdr.csum_flags & (M_CSUM_TCPv4|M_CSUM_UDPv4)) 3978 csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM; 3979 } 3980 3981 /* 3982 * If we were asked to do an outboard checksum, and the NIC 3983 * has the bug where it sometimes adds in the Ethernet padding, 3984 * explicitly pad with zeros so the cksum will be correct either way. 3985 * (For now, do this for all chip versions, until newer 3986 * are confirmed to not require the workaround.) 3987 */ 3988 if ((csum_flags & BGE_TXBDFLAG_TCP_UDP_CSUM) == 0 || 3989 #ifdef notyet 3990 (sc->bge_quirks & BGE_QUIRK_SHORT_CKSUM_BUG) == 0 || 3991 #endif 3992 m_head->m_pkthdr.len >= ETHER_MIN_NOPAD) 3993 goto check_dma_bug; 3994 3995 if (bge_cksum_pad(m_head) != 0) 3996 return ENOBUFS; 3997 3998 check_dma_bug: 3999 if (!(BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX)) 4000 goto doit; 4001 4002 /* 4003 * bcm5700 Revision B silicon cannot handle DMA descriptors with 4004 * less than eight bytes. If we encounter a teeny mbuf 4005 * at the end of a chain, we can pad. Otherwise, copy. 4006 */ 4007 if (bge_compact_dma_runt(m_head) != 0) 4008 return ENOBUFS; 4009 4010 doit: 4011 dma = SLIST_FIRST(&sc->txdma_list); 4012 if (dma == NULL) 4013 return ENOBUFS; 4014 dmamap = dma->dmamap; 4015 4016 /* 4017 * Set up any necessary TSO state before we start packing... 4018 */ 4019 use_tso = (m_head->m_pkthdr.csum_flags & M_CSUM_TSOv4) != 0; 4020 if (!use_tso) { 4021 maxsegsize = 0; 4022 } else { /* TSO setup */ 4023 unsigned mss; 4024 struct ether_header *eh; 4025 unsigned ip_tcp_hlen, iptcp_opt_words, tcp_seg_flags, offset; 4026 struct mbuf * m0 = m_head; 4027 struct ip *ip; 4028 struct tcphdr *th; 4029 int iphl, hlen; 4030 4031 /* 4032 * XXX It would be nice if the mbuf pkthdr had offset 4033 * fields for the protocol headers. 4034 */ 4035 4036 eh = mtod(m0, struct ether_header *); 4037 switch (htons(eh->ether_type)) { 4038 case ETHERTYPE_IP: 4039 offset = ETHER_HDR_LEN; 4040 break; 4041 4042 case ETHERTYPE_VLAN: 4043 offset = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 4044 break; 4045 4046 default: 4047 /* 4048 * Don't support this protocol or encapsulation. 4049 */ 4050 return ENOBUFS; 4051 } 4052 4053 /* 4054 * TCP/IP headers are in the first mbuf; we can do 4055 * this the easy way. 4056 */ 4057 iphl = M_CSUM_DATA_IPv4_IPHL(m0->m_pkthdr.csum_data); 4058 hlen = iphl + offset; 4059 if (__predict_false(m0->m_len < 4060 (hlen + sizeof(struct tcphdr)))) { 4061 4062 aprint_debug_dev(sc->bge_dev, 4063 "TSO: hard case m0->m_len == %d < ip/tcp hlen %zd," 4064 "not handled yet\n", 4065 m0->m_len, hlen+ sizeof(struct tcphdr)); 4066 #ifdef NOTYET 4067 /* 4068 * XXX jonathan (at) NetBSD.org: untested. 4069 * how to force this branch to be taken? 4070 */ 4071 BGE_EVCNT_INCR(&sc->sc_ev_txtsopain); 4072 4073 m_copydata(m0, offset, sizeof(ip), &ip); 4074 m_copydata(m0, hlen, sizeof(th), &th); 4075 4076 ip.ip_len = 0; 4077 4078 m_copyback(m0, hlen + offsetof(struct ip, ip_len), 4079 sizeof(ip.ip_len), &ip.ip_len); 4080 4081 th.th_sum = in_cksum_phdr(ip.ip_src.s_addr, 4082 ip.ip_dst.s_addr, htons(IPPROTO_TCP)); 4083 4084 m_copyback(m0, hlen + offsetof(struct tcphdr, th_sum), 4085 sizeof(th.th_sum), &th.th_sum); 4086 4087 hlen += th.th_off << 2; 4088 iptcp_opt_words = hlen; 4089 #else 4090 /* 4091 * if_wm "hard" case not yet supported, can we not 4092 * mandate it out of existence? 4093 */ 4094 (void) ip; (void)th; (void) ip_tcp_hlen; 4095 4096 return ENOBUFS; 4097 #endif 4098 } else { 4099 ip = (struct ip *) (mtod(m0, char *) + offset); 4100 th = (struct tcphdr *) (mtod(m0, char *) + hlen); 4101 ip_tcp_hlen = iphl + (th->th_off << 2); 4102 4103 /* Total IP/TCP options, in 32-bit words */ 4104 iptcp_opt_words = (ip_tcp_hlen 4105 - sizeof(struct tcphdr) 4106 - sizeof(struct ip)) >> 2; 4107 } 4108 if (BGE_IS_575X_PLUS(sc)) { 4109 th->th_sum = 0; 4110 csum_flags &= ~(BGE_TXBDFLAG_TCP_UDP_CSUM); 4111 } else { 4112 /* 4113 * XXX jonathan (at) NetBSD.org: 5705 untested. 4114 * Requires TSO firmware patch for 5701/5703/5704. 4115 */ 4116 th->th_sum = in_cksum_phdr(ip->ip_src.s_addr, 4117 ip->ip_dst.s_addr, htons(IPPROTO_TCP)); 4118 } 4119 4120 mss = m_head->m_pkthdr.segsz; 4121 txbd_tso_flags |= 4122 BGE_TXBDFLAG_CPU_PRE_DMA | 4123 BGE_TXBDFLAG_CPU_POST_DMA; 4124 4125 /* 4126 * Our NIC TSO-assist assumes TSO has standard, optionless 4127 * IPv4 and TCP headers, which total 40 bytes. By default, 4128 * the NIC copies 40 bytes of IP/TCP header from the 4129 * supplied header into the IP/TCP header portion of 4130 * each post-TSO-segment. If the supplied packet has IP or 4131 * TCP options, we need to tell the NIC to copy those extra 4132 * bytes into each post-TSO header, in addition to the normal 4133 * 40-byte IP/TCP header (and to leave space accordingly). 4134 * Unfortunately, the driver encoding of option length 4135 * varies across different ASIC families. 4136 */ 4137 tcp_seg_flags = 0; 4138 if (iptcp_opt_words) { 4139 if (BGE_IS_5705_PLUS(sc)) { 4140 tcp_seg_flags = 4141 iptcp_opt_words << 11; 4142 } else { 4143 txbd_tso_flags |= 4144 iptcp_opt_words << 12; 4145 } 4146 } 4147 maxsegsize = mss | tcp_seg_flags; 4148 ip->ip_len = htons(mss + ip_tcp_hlen); 4149 4150 } /* TSO setup */ 4151 4152 /* 4153 * Start packing the mbufs in this chain into 4154 * the fragment pointers. Stop when we run out 4155 * of fragments or hit the end of the mbuf chain. 4156 */ 4157 error = bus_dmamap_load_mbuf(sc->bge_dmatag, dmamap, m_head, 4158 BUS_DMA_NOWAIT); 4159 if (error) 4160 return ENOBUFS; 4161 /* 4162 * Sanity check: avoid coming within 16 descriptors 4163 * of the end of the ring. 4164 */ 4165 if (dmamap->dm_nsegs > (BGE_TX_RING_CNT - sc->bge_txcnt - 16)) { 4166 BGE_TSO_PRINTF(("%s: " 4167 " dmamap_load_mbuf too close to ring wrap\n", 4168 device_xname(sc->bge_dev))); 4169 goto fail_unload; 4170 } 4171 4172 mtag = sc->ethercom.ec_nvlans ? 4173 m_tag_find(m_head, PACKET_TAG_VLAN, NULL) : NULL; 4174 4175 4176 /* Iterate over dmap-map fragments. */ 4177 for (i = 0; i < dmamap->dm_nsegs; i++) { 4178 f = &sc->bge_rdata->bge_tx_ring[frag]; 4179 if (sc->bge_cdata.bge_tx_chain[frag] != NULL) 4180 break; 4181 4182 BGE_HOSTADDR(f->bge_addr, dmamap->dm_segs[i].ds_addr); 4183 f->bge_len = dmamap->dm_segs[i].ds_len; 4184 4185 /* 4186 * For 5751 and follow-ons, for TSO we must turn 4187 * off checksum-assist flag in the tx-descr, and 4188 * supply the ASIC-revision-specific encoding 4189 * of TSO flags and segsize. 4190 */ 4191 if (use_tso) { 4192 if (BGE_IS_575X_PLUS(sc) || i == 0) { 4193 f->bge_rsvd = maxsegsize; 4194 f->bge_flags = csum_flags | txbd_tso_flags; 4195 } else { 4196 f->bge_rsvd = 0; 4197 f->bge_flags = 4198 (csum_flags | txbd_tso_flags) & 0x0fff; 4199 } 4200 } else { 4201 f->bge_rsvd = 0; 4202 f->bge_flags = csum_flags; 4203 } 4204 4205 if (mtag != NULL) { 4206 f->bge_flags |= BGE_TXBDFLAG_VLAN_TAG; 4207 f->bge_vlan_tag = VLAN_TAG_VALUE(mtag); 4208 } else { 4209 f->bge_vlan_tag = 0; 4210 } 4211 cur = frag; 4212 BGE_INC(frag, BGE_TX_RING_CNT); 4213 } 4214 4215 if (i < dmamap->dm_nsegs) { 4216 BGE_TSO_PRINTF(("%s: reached %d < dm_nsegs %d\n", 4217 device_xname(sc->bge_dev), i, dmamap->dm_nsegs)); 4218 goto fail_unload; 4219 } 4220 4221 bus_dmamap_sync(sc->bge_dmatag, dmamap, 0, dmamap->dm_mapsize, 4222 BUS_DMASYNC_PREWRITE); 4223 4224 if (frag == sc->bge_tx_saved_considx) { 4225 BGE_TSO_PRINTF(("%s: frag %d = wrapped id %d?\n", 4226 device_xname(sc->bge_dev), frag, sc->bge_tx_saved_considx)); 4227 4228 goto fail_unload; 4229 } 4230 4231 sc->bge_rdata->bge_tx_ring[cur].bge_flags |= BGE_TXBDFLAG_END; 4232 sc->bge_cdata.bge_tx_chain[cur] = m_head; 4233 SLIST_REMOVE_HEAD(&sc->txdma_list, link); 4234 sc->txdma[cur] = dma; 4235 sc->bge_txcnt += dmamap->dm_nsegs; 4236 4237 *txidx = frag; 4238 4239 return 0; 4240 4241 fail_unload: 4242 bus_dmamap_unload(sc->bge_dmatag, dmamap); 4243 4244 return ENOBUFS; 4245 } 4246 4247 /* 4248 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 4249 * to the mbuf data regions directly in the transmit descriptors. 4250 */ 4251 static void 4252 bge_start(struct ifnet *ifp) 4253 { 4254 struct bge_softc *sc; 4255 struct mbuf *m_head = NULL; 4256 uint32_t prodidx; 4257 int pkts = 0; 4258 4259 sc = ifp->if_softc; 4260 4261 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 4262 return; 4263 4264 prodidx = sc->bge_tx_prodidx; 4265 4266 while (sc->bge_cdata.bge_tx_chain[prodidx] == NULL) { 4267 IFQ_POLL(&ifp->if_snd, m_head); 4268 if (m_head == NULL) 4269 break; 4270 4271 #if 0 4272 /* 4273 * XXX 4274 * safety overkill. If this is a fragmented packet chain 4275 * with delayed TCP/UDP checksums, then only encapsulate 4276 * it if we have enough descriptors to handle the entire 4277 * chain at once. 4278 * (paranoia -- may not actually be needed) 4279 */ 4280 if (m_head->m_flags & M_FIRSTFRAG && 4281 m_head->m_pkthdr.csum_flags & (CSUM_DELAY_DATA)) { 4282 if ((BGE_TX_RING_CNT - sc->bge_txcnt) < 4283 M_CSUM_DATA_IPv4_OFFSET(m_head->m_pkthdr.csum_data) + 16) { 4284 ifp->if_flags |= IFF_OACTIVE; 4285 break; 4286 } 4287 } 4288 #endif 4289 4290 /* 4291 * Pack the data into the transmit ring. If we 4292 * don't have room, set the OACTIVE flag and wait 4293 * for the NIC to drain the ring. 4294 */ 4295 if (bge_encap(sc, m_head, &prodidx)) { 4296 ifp->if_flags |= IFF_OACTIVE; 4297 break; 4298 } 4299 4300 /* now we are committed to transmit the packet */ 4301 IFQ_DEQUEUE(&ifp->if_snd, m_head); 4302 pkts++; 4303 4304 /* 4305 * If there's a BPF listener, bounce a copy of this frame 4306 * to him. 4307 */ 4308 bpf_mtap(ifp, m_head); 4309 } 4310 if (pkts == 0) 4311 return; 4312 4313 /* Transmit */ 4314 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); 4315 /* 5700 b2 errata */ 4316 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX) 4317 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); 4318 4319 sc->bge_tx_prodidx = prodidx; 4320 4321 /* 4322 * Set a timeout in case the chip goes out to lunch. 4323 */ 4324 ifp->if_timer = 5; 4325 } 4326 4327 static int 4328 bge_init(struct ifnet *ifp) 4329 { 4330 struct bge_softc *sc = ifp->if_softc; 4331 const uint16_t *m; 4332 uint32_t mode; 4333 int s, error = 0; 4334 4335 s = splnet(); 4336 4337 ifp = &sc->ethercom.ec_if; 4338 4339 /* Cancel pending I/O and flush buffers. */ 4340 bge_stop(ifp, 0); 4341 4342 bge_stop_fw(sc); 4343 bge_sig_pre_reset(sc, BGE_RESET_START); 4344 bge_reset(sc); 4345 bge_sig_legacy(sc, BGE_RESET_START); 4346 bge_sig_post_reset(sc, BGE_RESET_START); 4347 4348 bge_chipinit(sc); 4349 4350 /* 4351 * Init the various state machines, ring 4352 * control blocks and firmware. 4353 */ 4354 error = bge_blockinit(sc); 4355 if (error != 0) { 4356 aprint_error_dev(sc->bge_dev, "initialization error %d\n", 4357 error); 4358 splx(s); 4359 return error; 4360 } 4361 4362 ifp = &sc->ethercom.ec_if; 4363 4364 /* Specify MTU. */ 4365 CSR_WRITE_4(sc, BGE_RX_MTU, ifp->if_mtu + 4366 ETHER_HDR_LEN + ETHER_CRC_LEN + ETHER_VLAN_ENCAP_LEN); 4367 4368 /* Load our MAC address. */ 4369 m = (const uint16_t *)&(CLLADDR(ifp->if_sadl)[0]); 4370 CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0])); 4371 CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, (htons(m[1]) << 16) | htons(m[2])); 4372 4373 /* Enable or disable promiscuous mode as needed. */ 4374 if (ifp->if_flags & IFF_PROMISC) 4375 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 4376 else 4377 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 4378 4379 /* Program multicast filter. */ 4380 bge_setmulti(sc); 4381 4382 /* Init RX ring. */ 4383 bge_init_rx_ring_std(sc); 4384 4385 /* 4386 * Workaround for a bug in 5705 ASIC rev A0. Poll the NIC's 4387 * memory to insure that the chip has in fact read the first 4388 * entry of the ring. 4389 */ 4390 if (sc->bge_chipid == BGE_CHIPID_BCM5705_A0) { 4391 uint32_t v, i; 4392 for (i = 0; i < 10; i++) { 4393 DELAY(20); 4394 v = bge_readmem_ind(sc, BGE_STD_RX_RINGS + 8); 4395 if (v == (MCLBYTES - ETHER_ALIGN)) 4396 break; 4397 } 4398 if (i == 10) 4399 aprint_error_dev(sc->bge_dev, 4400 "5705 A0 chip failed to load RX ring\n"); 4401 } 4402 4403 /* Init jumbo RX ring. */ 4404 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 4405 bge_init_rx_ring_jumbo(sc); 4406 4407 /* Init our RX return ring index */ 4408 sc->bge_rx_saved_considx = 0; 4409 4410 /* Init TX ring. */ 4411 bge_init_tx_ring(sc); 4412 4413 /* Enable TX MAC state machine lockup fix. */ 4414 mode = CSR_READ_4(sc, BGE_TX_MODE); 4415 if (BGE_IS_5755_PLUS(sc) || 4416 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 4417 mode |= BGE_TXMODE_MBUF_LOCKUP_FIX; 4418 4419 /* Turn on transmitter */ 4420 CSR_WRITE_4(sc, BGE_TX_MODE, mode | BGE_TXMODE_ENABLE); 4421 DELAY(100); 4422 4423 /* Turn on receiver */ 4424 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE); 4425 DELAY(10); 4426 4427 CSR_WRITE_4(sc, BGE_MAX_RX_FRAME_LOWAT, 2); 4428 4429 /* Tell firmware we're alive. */ 4430 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 4431 4432 /* Enable host interrupts. */ 4433 PCI_SETBIT(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MISC_CTL, 4434 BGE_PCIMISCCTL_CLEAR_INTA); 4435 PCI_CLRBIT(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MISC_CTL, 4436 BGE_PCIMISCCTL_MASK_PCI_INTR); 4437 bge_writembx(sc, BGE_MBX_IRQ0_LO, 0); 4438 4439 if ((error = bge_ifmedia_upd(ifp)) != 0) 4440 goto out; 4441 4442 ifp->if_flags |= IFF_RUNNING; 4443 ifp->if_flags &= ~IFF_OACTIVE; 4444 4445 callout_reset(&sc->bge_timeout, hz, bge_tick, sc); 4446 4447 out: 4448 sc->bge_if_flags = ifp->if_flags; 4449 splx(s); 4450 4451 return error; 4452 } 4453 4454 /* 4455 * Set media options. 4456 */ 4457 static int 4458 bge_ifmedia_upd(struct ifnet *ifp) 4459 { 4460 struct bge_softc *sc = ifp->if_softc; 4461 struct mii_data *mii = &sc->bge_mii; 4462 struct ifmedia *ifm = &sc->bge_ifmedia; 4463 int rc; 4464 4465 /* If this is a 1000baseX NIC, enable the TBI port. */ 4466 if (sc->bge_flags & BGE_PHY_FIBER_TBI) { 4467 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 4468 return EINVAL; 4469 switch (IFM_SUBTYPE(ifm->ifm_media)) { 4470 case IFM_AUTO: 4471 /* 4472 * The BCM5704 ASIC appears to have a special 4473 * mechanism for programming the autoneg 4474 * advertisement registers in TBI mode. 4475 */ 4476 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) { 4477 uint32_t sgdig; 4478 sgdig = CSR_READ_4(sc, BGE_SGDIG_STS); 4479 if (sgdig & BGE_SGDIGSTS_DONE) { 4480 CSR_WRITE_4(sc, BGE_TX_TBI_AUTONEG, 0); 4481 sgdig = CSR_READ_4(sc, BGE_SGDIG_CFG); 4482 sgdig |= BGE_SGDIGCFG_AUTO | 4483 BGE_SGDIGCFG_PAUSE_CAP | 4484 BGE_SGDIGCFG_ASYM_PAUSE; 4485 CSR_WRITE_4(sc, BGE_SGDIG_CFG, 4486 sgdig | BGE_SGDIGCFG_SEND); 4487 DELAY(5); 4488 CSR_WRITE_4(sc, BGE_SGDIG_CFG, sgdig); 4489 } 4490 } 4491 break; 4492 case IFM_1000_SX: 4493 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 4494 BGE_CLRBIT(sc, BGE_MAC_MODE, 4495 BGE_MACMODE_HALF_DUPLEX); 4496 } else { 4497 BGE_SETBIT(sc, BGE_MAC_MODE, 4498 BGE_MACMODE_HALF_DUPLEX); 4499 } 4500 break; 4501 default: 4502 return EINVAL; 4503 } 4504 /* XXX 802.3x flow control for 1000BASE-SX */ 4505 return 0; 4506 } 4507 4508 BGE_STS_SETBIT(sc, BGE_STS_LINK_EVT); 4509 if ((rc = mii_mediachg(mii)) == ENXIO) 4510 return 0; 4511 4512 /* 4513 * Force an interrupt so that we will call bge_link_upd 4514 * if needed and clear any pending link state attention. 4515 * Without this we are not getting any further interrupts 4516 * for link state changes and thus will not UP the link and 4517 * not be able to send in bge_start. The only way to get 4518 * things working was to receive a packet and get a RX intr. 4519 */ 4520 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 4521 sc->bge_flags & BGE_IS_5788) 4522 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET); 4523 else 4524 BGE_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW); 4525 4526 return rc; 4527 } 4528 4529 /* 4530 * Report current media status. 4531 */ 4532 static void 4533 bge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 4534 { 4535 struct bge_softc *sc = ifp->if_softc; 4536 struct mii_data *mii = &sc->bge_mii; 4537 4538 if (sc->bge_flags & BGE_PHY_FIBER_TBI) { 4539 ifmr->ifm_status = IFM_AVALID; 4540 ifmr->ifm_active = IFM_ETHER; 4541 if (CSR_READ_4(sc, BGE_MAC_STS) & 4542 BGE_MACSTAT_TBI_PCS_SYNCHED) 4543 ifmr->ifm_status |= IFM_ACTIVE; 4544 ifmr->ifm_active |= IFM_1000_SX; 4545 if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX) 4546 ifmr->ifm_active |= IFM_HDX; 4547 else 4548 ifmr->ifm_active |= IFM_FDX; 4549 return; 4550 } 4551 4552 mii_pollstat(mii); 4553 ifmr->ifm_status = mii->mii_media_status; 4554 ifmr->ifm_active = (mii->mii_media_active & ~IFM_ETH_FMASK) | 4555 sc->bge_flowflags; 4556 } 4557 4558 static int 4559 bge_ifflags_cb(struct ethercom *ec) 4560 { 4561 struct ifnet *ifp = &ec->ec_if; 4562 struct bge_softc *sc = ifp->if_softc; 4563 int change = ifp->if_flags ^ sc->bge_if_flags; 4564 4565 if ((change & ~(IFF_CANTCHANGE|IFF_DEBUG)) != 0) 4566 return ENETRESET; 4567 else if ((change & (IFF_PROMISC | IFF_ALLMULTI)) == 0) 4568 return 0; 4569 4570 if ((ifp->if_flags & IFF_PROMISC) == 0) 4571 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 4572 else 4573 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 4574 4575 bge_setmulti(sc); 4576 4577 sc->bge_if_flags = ifp->if_flags; 4578 return 0; 4579 } 4580 4581 static int 4582 bge_ioctl(struct ifnet *ifp, u_long command, void *data) 4583 { 4584 struct bge_softc *sc = ifp->if_softc; 4585 struct ifreq *ifr = (struct ifreq *) data; 4586 int s, error = 0; 4587 struct mii_data *mii; 4588 4589 s = splnet(); 4590 4591 switch (command) { 4592 case SIOCSIFMEDIA: 4593 /* XXX Flow control is not supported for 1000BASE-SX */ 4594 if (sc->bge_flags & BGE_PHY_FIBER_TBI) { 4595 ifr->ifr_media &= ~IFM_ETH_FMASK; 4596 sc->bge_flowflags = 0; 4597 } 4598 4599 /* Flow control requires full-duplex mode. */ 4600 if (IFM_SUBTYPE(ifr->ifr_media) == IFM_AUTO || 4601 (ifr->ifr_media & IFM_FDX) == 0) { 4602 ifr->ifr_media &= ~IFM_ETH_FMASK; 4603 } 4604 if (IFM_SUBTYPE(ifr->ifr_media) != IFM_AUTO) { 4605 if ((ifr->ifr_media & IFM_ETH_FMASK) == IFM_FLOW) { 4606 /* We can do both TXPAUSE and RXPAUSE. */ 4607 ifr->ifr_media |= 4608 IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE; 4609 } 4610 sc->bge_flowflags = ifr->ifr_media & IFM_ETH_FMASK; 4611 } 4612 /* FALLTHROUGH */ 4613 case SIOCGIFMEDIA: 4614 if (sc->bge_flags & BGE_PHY_FIBER_TBI) { 4615 error = ifmedia_ioctl(ifp, ifr, &sc->bge_ifmedia, 4616 command); 4617 } else { 4618 mii = &sc->bge_mii; 4619 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, 4620 command); 4621 } 4622 break; 4623 default: 4624 if ((error = ether_ioctl(ifp, command, data)) != ENETRESET) 4625 break; 4626 4627 error = 0; 4628 4629 if (command != SIOCADDMULTI && command != SIOCDELMULTI) 4630 ; 4631 else if (ifp->if_flags & IFF_RUNNING) 4632 bge_setmulti(sc); 4633 break; 4634 } 4635 4636 splx(s); 4637 4638 return error; 4639 } 4640 4641 static void 4642 bge_watchdog(struct ifnet *ifp) 4643 { 4644 struct bge_softc *sc; 4645 4646 sc = ifp->if_softc; 4647 4648 aprint_error_dev(sc->bge_dev, "watchdog timeout -- resetting\n"); 4649 4650 ifp->if_flags &= ~IFF_RUNNING; 4651 bge_init(ifp); 4652 4653 ifp->if_oerrors++; 4654 } 4655 4656 static void 4657 bge_stop_block(struct bge_softc *sc, bus_addr_t reg, uint32_t bit) 4658 { 4659 int i; 4660 4661 BGE_CLRBIT(sc, reg, bit); 4662 4663 for (i = 0; i < 1000; i++) { 4664 if ((CSR_READ_4(sc, reg) & bit) == 0) 4665 return; 4666 delay(100); 4667 } 4668 4669 /* 4670 * Doesn't print only when the register is BGE_SRS_MODE. It occurs 4671 * on some environment (and once after boot?) 4672 */ 4673 if (reg != BGE_SRS_MODE) 4674 aprint_error_dev(sc->bge_dev, 4675 "block failed to stop: reg 0x%lx, bit 0x%08x\n", 4676 (u_long)reg, bit); 4677 } 4678 4679 /* 4680 * Stop the adapter and free any mbufs allocated to the 4681 * RX and TX lists. 4682 */ 4683 static void 4684 bge_stop(struct ifnet *ifp, int disable) 4685 { 4686 struct bge_softc *sc = ifp->if_softc; 4687 4688 callout_stop(&sc->bge_timeout); 4689 4690 /* 4691 * Tell firmware we're shutting down. 4692 */ 4693 bge_stop_fw(sc); 4694 bge_sig_pre_reset(sc, BGE_RESET_STOP); 4695 4696 /* Disable host interrupts. */ 4697 PCI_SETBIT(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MISC_CTL, 4698 BGE_PCIMISCCTL_MASK_PCI_INTR); 4699 bge_writembx(sc, BGE_MBX_IRQ0_LO, 1); 4700 4701 /* 4702 * Disable all of the receiver blocks. 4703 */ 4704 bge_stop_block(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE); 4705 bge_stop_block(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 4706 bge_stop_block(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 4707 if (BGE_IS_5700_FAMILY(sc)) 4708 bge_stop_block(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 4709 bge_stop_block(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE); 4710 bge_stop_block(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 4711 bge_stop_block(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE); 4712 4713 /* 4714 * Disable all of the transmit blocks. 4715 */ 4716 bge_stop_block(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 4717 bge_stop_block(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 4718 bge_stop_block(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 4719 bge_stop_block(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE); 4720 bge_stop_block(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE); 4721 if (BGE_IS_5700_FAMILY(sc)) 4722 bge_stop_block(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 4723 bge_stop_block(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 4724 4725 /* 4726 * Shut down all of the memory managers and related 4727 * state machines. 4728 */ 4729 bge_stop_block(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE); 4730 bge_stop_block(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE); 4731 if (BGE_IS_5700_FAMILY(sc)) 4732 bge_stop_block(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 4733 4734 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 4735 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 4736 4737 if (BGE_IS_5700_FAMILY(sc)) { 4738 bge_stop_block(sc, BGE_BMAN_MODE, BGE_BMANMODE_ENABLE); 4739 bge_stop_block(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 4740 } 4741 4742 bge_reset(sc); 4743 bge_sig_legacy(sc, BGE_RESET_STOP); 4744 bge_sig_post_reset(sc, BGE_RESET_STOP); 4745 4746 /* 4747 * Keep the ASF firmware running if up. 4748 */ 4749 if (sc->bge_asf_mode & ASF_STACKUP) 4750 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 4751 else 4752 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 4753 4754 /* Free the RX lists. */ 4755 bge_free_rx_ring_std(sc); 4756 4757 /* Free jumbo RX list. */ 4758 if (BGE_IS_JUMBO_CAPABLE(sc)) 4759 bge_free_rx_ring_jumbo(sc); 4760 4761 /* Free TX buffers. */ 4762 bge_free_tx_ring(sc); 4763 4764 /* 4765 * Isolate/power down the PHY. 4766 */ 4767 if (!(sc->bge_flags & BGE_PHY_FIBER_TBI)) 4768 mii_down(&sc->bge_mii); 4769 4770 sc->bge_tx_saved_considx = BGE_TXCONS_UNSET; 4771 4772 /* Clear MAC's link state (PHY may still have link UP). */ 4773 BGE_STS_CLRBIT(sc, BGE_STS_LINK); 4774 4775 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 4776 } 4777 4778 static void 4779 bge_link_upd(struct bge_softc *sc) 4780 { 4781 struct ifnet *ifp = &sc->ethercom.ec_if; 4782 struct mii_data *mii = &sc->bge_mii; 4783 uint32_t status; 4784 int link; 4785 4786 /* Clear 'pending link event' flag */ 4787 BGE_STS_CLRBIT(sc, BGE_STS_LINK_EVT); 4788 4789 /* 4790 * Process link state changes. 4791 * Grrr. The link status word in the status block does 4792 * not work correctly on the BCM5700 rev AX and BX chips, 4793 * according to all available information. Hence, we have 4794 * to enable MII interrupts in order to properly obtain 4795 * async link changes. Unfortunately, this also means that 4796 * we have to read the MAC status register to detect link 4797 * changes, thereby adding an additional register access to 4798 * the interrupt handler. 4799 */ 4800 4801 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700) { 4802 status = CSR_READ_4(sc, BGE_MAC_STS); 4803 if (status & BGE_MACSTAT_MI_INTERRUPT) { 4804 mii_pollstat(mii); 4805 4806 if (!BGE_STS_BIT(sc, BGE_STS_LINK) && 4807 mii->mii_media_status & IFM_ACTIVE && 4808 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) 4809 BGE_STS_SETBIT(sc, BGE_STS_LINK); 4810 else if (BGE_STS_BIT(sc, BGE_STS_LINK) && 4811 (!(mii->mii_media_status & IFM_ACTIVE) || 4812 IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) 4813 BGE_STS_CLRBIT(sc, BGE_STS_LINK); 4814 4815 /* Clear the interrupt */ 4816 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, 4817 BGE_EVTENB_MI_INTERRUPT); 4818 bge_miibus_readreg(sc->bge_dev, 1, BRGPHY_MII_ISR); 4819 bge_miibus_writereg(sc->bge_dev, 1, BRGPHY_MII_IMR, 4820 BRGPHY_INTRS); 4821 } 4822 return; 4823 } 4824 4825 if (sc->bge_flags & BGE_PHY_FIBER_TBI) { 4826 status = CSR_READ_4(sc, BGE_MAC_STS); 4827 if (status & BGE_MACSTAT_TBI_PCS_SYNCHED) { 4828 if (!BGE_STS_BIT(sc, BGE_STS_LINK)) { 4829 BGE_STS_SETBIT(sc, BGE_STS_LINK); 4830 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) 4831 BGE_CLRBIT(sc, BGE_MAC_MODE, 4832 BGE_MACMODE_TBI_SEND_CFGS); 4833 CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF); 4834 if_link_state_change(ifp, LINK_STATE_UP); 4835 } 4836 } else if (BGE_STS_BIT(sc, BGE_STS_LINK)) { 4837 BGE_STS_CLRBIT(sc, BGE_STS_LINK); 4838 if_link_state_change(ifp, LINK_STATE_DOWN); 4839 } 4840 /* 4841 * Discard link events for MII/GMII cards if MI auto-polling disabled. 4842 * This should not happen since mii callouts are locked now, but 4843 * we keep this check for debug. 4844 */ 4845 } else if (BGE_STS_BIT(sc, BGE_STS_AUTOPOLL)) { 4846 /* 4847 * Some broken BCM chips have BGE_STATFLAG_LINKSTATE_CHANGED 4848 * bit in status word always set. Workaround this bug by 4849 * reading PHY link status directly. 4850 */ 4851 link = (CSR_READ_4(sc, BGE_MI_STS) & BGE_MISTS_LINK)? 4852 BGE_STS_LINK : 0; 4853 4854 if (BGE_STS_BIT(sc, BGE_STS_LINK) != link) { 4855 mii_pollstat(mii); 4856 4857 if (!BGE_STS_BIT(sc, BGE_STS_LINK) && 4858 mii->mii_media_status & IFM_ACTIVE && 4859 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) 4860 BGE_STS_SETBIT(sc, BGE_STS_LINK); 4861 else if (BGE_STS_BIT(sc, BGE_STS_LINK) && 4862 (!(mii->mii_media_status & IFM_ACTIVE) || 4863 IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) 4864 BGE_STS_CLRBIT(sc, BGE_STS_LINK); 4865 } 4866 } 4867 4868 /* Clear the attention */ 4869 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED| 4870 BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE| 4871 BGE_MACSTAT_LINK_CHANGED); 4872 } 4873 4874 static int 4875 bge_sysctl_verify(SYSCTLFN_ARGS) 4876 { 4877 int error, t; 4878 struct sysctlnode node; 4879 4880 node = *rnode; 4881 t = *(int*)rnode->sysctl_data; 4882 node.sysctl_data = &t; 4883 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 4884 if (error || newp == NULL) 4885 return error; 4886 4887 #if 0 4888 DPRINTF2(("%s: t = %d, nodenum = %d, rnodenum = %d\n", __func__, t, 4889 node.sysctl_num, rnode->sysctl_num)); 4890 #endif 4891 4892 if (node.sysctl_num == bge_rxthresh_nodenum) { 4893 if (t < 0 || t >= NBGE_RX_THRESH) 4894 return EINVAL; 4895 bge_update_all_threshes(t); 4896 } else 4897 return EINVAL; 4898 4899 *(int*)rnode->sysctl_data = t; 4900 4901 return 0; 4902 } 4903 4904 /* 4905 * Set up sysctl(3) MIB, hw.bge.*. 4906 */ 4907 static void 4908 bge_sysctl_init(struct bge_softc *sc) 4909 { 4910 int rc, bge_root_num; 4911 const struct sysctlnode *node; 4912 4913 if ((rc = sysctl_createv(&sc->bge_log, 0, NULL, NULL, 4914 CTLFLAG_PERMANENT, CTLTYPE_NODE, "hw", NULL, 4915 NULL, 0, NULL, 0, CTL_HW, CTL_EOL)) != 0) { 4916 goto out; 4917 } 4918 4919 if ((rc = sysctl_createv(&sc->bge_log, 0, NULL, &node, 4920 0, CTLTYPE_NODE, "bge", 4921 SYSCTL_DESCR("BGE interface controls"), 4922 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL)) != 0) { 4923 goto out; 4924 } 4925 4926 bge_root_num = node->sysctl_num; 4927 4928 /* BGE Rx interrupt mitigation level */ 4929 if ((rc = sysctl_createv(&sc->bge_log, 0, NULL, &node, 4930 CTLFLAG_READWRITE, 4931 CTLTYPE_INT, "rx_lvl", 4932 SYSCTL_DESCR("BGE receive interrupt mitigation level"), 4933 bge_sysctl_verify, 0, 4934 &bge_rx_thresh_lvl, 4935 0, CTL_HW, bge_root_num, CTL_CREATE, 4936 CTL_EOL)) != 0) { 4937 goto out; 4938 } 4939 4940 bge_rxthresh_nodenum = node->sysctl_num; 4941 4942 return; 4943 4944 out: 4945 aprint_error("%s: sysctl_createv failed (rc = %d)\n", __func__, rc); 4946 } 4947 4948 #ifdef BGE_DEBUG 4949 void 4950 bge_debug_info(struct bge_softc *sc) 4951 { 4952 4953 printf("Hardware Flags:\n"); 4954 if (BGE_IS_5755_PLUS(sc)) 4955 printf(" - 5755 Plus\n"); 4956 if (BGE_IS_575X_PLUS(sc)) 4957 printf(" - 575X Plus\n"); 4958 if (BGE_IS_5705_PLUS(sc)) 4959 printf(" - 5705 Plus\n"); 4960 if (BGE_IS_5714_FAMILY(sc)) 4961 printf(" - 5714 Family\n"); 4962 if (BGE_IS_5700_FAMILY(sc)) 4963 printf(" - 5700 Family\n"); 4964 if (sc->bge_flags & BGE_IS_5788) 4965 printf(" - 5788\n"); 4966 if (sc->bge_flags & BGE_JUMBO_CAPABLE) 4967 printf(" - Supports Jumbo Frames\n"); 4968 if (sc->bge_flags & BGE_NO_EEPROM) 4969 printf(" - No EEPROM\n"); 4970 if (sc->bge_flags & BGE_PCIX) 4971 printf(" - PCI-X Bus\n"); 4972 if (sc->bge_flags & BGE_PCIE) 4973 printf(" - PCI Express Bus\n"); 4974 if (sc->bge_flags & BGE_NO_3LED) 4975 printf(" - No 3 LEDs\n"); 4976 if (sc->bge_flags & BGE_RX_ALIGNBUG) 4977 printf(" - RX Alignment Bug\n"); 4978 if (sc->bge_flags & BGE_TSO) 4979 printf(" - TSO\n"); 4980 } 4981 #endif /* BGE_DEBUG */ 4982 4983 static int 4984 bge_get_eaddr_fw(struct bge_softc *sc, uint8_t ether_addr[]) 4985 { 4986 prop_dictionary_t dict; 4987 prop_data_t ea; 4988 4989 if ((sc->bge_flags & BGE_NO_EEPROM) == 0) 4990 return 1; 4991 4992 dict = device_properties(sc->bge_dev); 4993 ea = prop_dictionary_get(dict, "mac-address"); 4994 if (ea != NULL) { 4995 KASSERT(prop_object_type(ea) == PROP_TYPE_DATA); 4996 KASSERT(prop_data_size(ea) == ETHER_ADDR_LEN); 4997 memcpy(ether_addr, prop_data_data_nocopy(ea), ETHER_ADDR_LEN); 4998 return 0; 4999 } 5000 5001 return 1; 5002 } 5003 5004 static int 5005 bge_get_eaddr_mem(struct bge_softc *sc, uint8_t ether_addr[]) 5006 { 5007 uint32_t mac_addr; 5008 5009 mac_addr = bge_readmem_ind(sc, BGE_SRAM_MAC_ADDR_HIGH_MB); 5010 if ((mac_addr >> 16) == 0x484b) { 5011 ether_addr[0] = (uint8_t)(mac_addr >> 8); 5012 ether_addr[1] = (uint8_t)mac_addr; 5013 mac_addr = bge_readmem_ind(sc, BGE_SRAM_MAC_ADDR_LOW_MB); 5014 ether_addr[2] = (uint8_t)(mac_addr >> 24); 5015 ether_addr[3] = (uint8_t)(mac_addr >> 16); 5016 ether_addr[4] = (uint8_t)(mac_addr >> 8); 5017 ether_addr[5] = (uint8_t)mac_addr; 5018 return 0; 5019 } 5020 return 1; 5021 } 5022 5023 static int 5024 bge_get_eaddr_nvram(struct bge_softc *sc, uint8_t ether_addr[]) 5025 { 5026 int mac_offset = BGE_EE_MAC_OFFSET; 5027 5028 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 5029 mac_offset = BGE_EE_MAC_OFFSET_5906; 5030 5031 return (bge_read_nvram(sc, ether_addr, mac_offset + 2, 5032 ETHER_ADDR_LEN)); 5033 } 5034 5035 static int 5036 bge_get_eaddr_eeprom(struct bge_softc *sc, uint8_t ether_addr[]) 5037 { 5038 5039 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 5040 return 1; 5041 5042 return (bge_read_eeprom(sc, ether_addr, BGE_EE_MAC_OFFSET + 2, 5043 ETHER_ADDR_LEN)); 5044 } 5045 5046 static int 5047 bge_get_eaddr(struct bge_softc *sc, uint8_t eaddr[]) 5048 { 5049 static const bge_eaddr_fcn_t bge_eaddr_funcs[] = { 5050 /* NOTE: Order is critical */ 5051 bge_get_eaddr_fw, 5052 bge_get_eaddr_mem, 5053 bge_get_eaddr_nvram, 5054 bge_get_eaddr_eeprom, 5055 NULL 5056 }; 5057 const bge_eaddr_fcn_t *func; 5058 5059 for (func = bge_eaddr_funcs; *func != NULL; ++func) { 5060 if ((*func)(sc, eaddr) == 0) 5061 break; 5062 } 5063 return (*func == NULL ? ENXIO : 0); 5064 } 5065
Indexes created Wed Sep 24 05:09:52 GMT 2025