if_bge.c revision 1.213
1 /* $NetBSD: if_bge.c,v 1.213 2013/03/07 10:57:01 msaitoh Exp $ */ 2 3 /* 4 * Copyright (c) 2001 Wind River Systems 5 * Copyright (c) 1997, 1998, 1999, 2001 6 * Bill Paul <wpaul (at) windriver.com>. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Bill Paul. 19 * 4. Neither the name of the author nor the names of any co-contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 33 * THE POSSIBILITY OF SUCH DAMAGE. 34 * 35 * $FreeBSD: if_bge.c,v 1.13 2002/04/04 06:01:31 wpaul Exp $ 36 */ 37 38 /* 39 * Broadcom BCM570x family gigabit ethernet driver for NetBSD. 40 * 41 * NetBSD version by: 42 * 43 * Frank van der Linden <fvdl (at) wasabisystems.com> 44 * Jason Thorpe <thorpej (at) wasabisystems.com> 45 * Jonathan Stone <jonathan (at) dsg.stanford.edu> 46 * 47 * Originally written for FreeBSD by Bill Paul <wpaul (at) windriver.com> 48 * Senior Engineer, Wind River Systems 49 */ 50 51 /* 52 * The Broadcom BCM5700 is based on technology originally developed by 53 * Alteon Networks as part of the Tigon I and Tigon II gigabit ethernet 54 * MAC chips. The BCM5700, sometimes referred to as the Tigon III, has 55 * two on-board MIPS R4000 CPUs and can have as much as 16MB of external 56 * SSRAM. The BCM5700 supports TCP, UDP and IP checksum offload, jumbo 57 * frames, highly configurable RX filtering, and 16 RX and TX queues 58 * (which, along with RX filter rules, can be used for QOS applications). 59 * Other features, such as TCP segmentation, may be available as part 60 * of value-added firmware updates. Unlike the Tigon I and Tigon II, 61 * firmware images can be stored in hardware and need not be compiled 62 * into the driver. 63 * 64 * The BCM5700 supports the PCI v2.2 and PCI-X v1.0 standards, and will 65 * function in a 32-bit/64-bit 33/66MHz bus, or a 64-bit/133MHz bus. 66 * 67 * The BCM5701 is a single-chip solution incorporating both the BCM5700 68 * MAC and a BCM5401 10/100/1000 PHY. Unlike the BCM5700, the BCM5701 69 * does not support external SSRAM. 70 * 71 * Broadcom also produces a variation of the BCM5700 under the "Altima" 72 * brand name, which is functionally similar but lacks PCI-X support. 73 * 74 * Without external SSRAM, you can only have at most 4 TX rings, 75 * and the use of the mini RX ring is disabled. This seems to imply 76 * that these features are simply not available on the BCM5701. As a 77 * result, this driver does not implement any support for the mini RX 78 * ring. 79 */ 80 81 #include <sys/cdefs.h> 82 __KERNEL_RCSID(0, "$NetBSD: if_bge.c,v 1.213 2013/03/07 10:57:01 msaitoh Exp $"); 83 84 #include "vlan.h" 85 86 #include <sys/param.h> 87 #include <sys/systm.h> 88 #include <sys/callout.h> 89 #include <sys/sockio.h> 90 #include <sys/mbuf.h> 91 #include <sys/malloc.h> 92 #include <sys/kernel.h> 93 #include <sys/device.h> 94 #include <sys/socket.h> 95 #include <sys/sysctl.h> 96 97 #include <net/if.h> 98 #include <net/if_dl.h> 99 #include <net/if_media.h> 100 #include <net/if_ether.h> 101 102 #include <sys/rnd.h> 103 104 #ifdef INET 105 #include <netinet/in.h> 106 #include <netinet/in_systm.h> 107 #include <netinet/in_var.h> 108 #include <netinet/ip.h> 109 #endif 110 111 /* Headers for TCP Segmentation Offload (TSO) */ 112 #include <netinet/in_systm.h> /* n_time for <netinet/ip.h>... */ 113 #include <netinet/in.h> /* ip_{src,dst}, for <netinet/ip.h> */ 114 #include <netinet/ip.h> /* for struct ip */ 115 #include <netinet/tcp.h> /* for struct tcphdr */ 116 117 118 #include <net/bpf.h> 119 120 #include <dev/pci/pcireg.h> 121 #include <dev/pci/pcivar.h> 122 #include <dev/pci/pcidevs.h> 123 124 #include <dev/mii/mii.h> 125 #include <dev/mii/miivar.h> 126 #include <dev/mii/miidevs.h> 127 #include <dev/mii/brgphyreg.h> 128 129 #include <dev/pci/if_bgereg.h> 130 #include <dev/pci/if_bgevar.h> 131 132 #include <prop/proplib.h> 133 134 #define ETHER_MIN_NOPAD (ETHER_MIN_LEN - ETHER_CRC_LEN) /* i.e., 60 */ 135 136 137 /* 138 * Tunable thresholds for rx-side bge interrupt mitigation. 139 */ 140 141 /* 142 * The pairs of values below were obtained from empirical measurement 143 * on bcm5700 rev B2; they ar designed to give roughly 1 receive 144 * interrupt for every N packets received, where N is, approximately, 145 * the second value (rx_max_bds) in each pair. The values are chosen 146 * such that moving from one pair to the succeeding pair was observed 147 * to roughly halve interrupt rate under sustained input packet load. 148 * The values were empirically chosen to avoid overflowing internal 149 * limits on the bcm5700: increasing rx_ticks much beyond 600 150 * results in internal wrapping and higher interrupt rates. 151 * The limit of 46 frames was chosen to match NFS workloads. 152 * 153 * These values also work well on bcm5701, bcm5704C, and (less 154 * tested) bcm5703. On other chipsets, (including the Altima chip 155 * family), the larger values may overflow internal chip limits, 156 * leading to increasing interrupt rates rather than lower interrupt 157 * rates. 158 * 159 * Applications using heavy interrupt mitigation (interrupting every 160 * 32 or 46 frames) in both directions may need to increase the TCP 161 * windowsize to above 131072 bytes (e.g., to 199608 bytes) to sustain 162 * full link bandwidth, due to ACKs and window updates lingering 163 * in the RX queue during the 30-to-40-frame interrupt-mitigation window. 164 */ 165 static const struct bge_load_rx_thresh { 166 int rx_ticks; 167 int rx_max_bds; } 168 bge_rx_threshes[] = { 169 { 16, 1 }, /* rx_max_bds = 1 disables interrupt mitigation */ 170 { 32, 2 }, 171 { 50, 4 }, 172 { 100, 8 }, 173 { 192, 16 }, 174 { 416, 32 }, 175 { 598, 46 } 176 }; 177 #define NBGE_RX_THRESH (sizeof(bge_rx_threshes) / sizeof(bge_rx_threshes[0])) 178 179 /* XXX patchable; should be sysctl'able */ 180 static int bge_auto_thresh = 1; 181 static int bge_rx_thresh_lvl; 182 183 static int bge_rxthresh_nodenum; 184 185 typedef int (*bge_eaddr_fcn_t)(struct bge_softc *, uint8_t[]); 186 187 static int bge_probe(device_t, cfdata_t, void *); 188 static void bge_attach(device_t, device_t, void *); 189 static void bge_release_resources(struct bge_softc *); 190 191 static int bge_get_eaddr_fw(struct bge_softc *, uint8_t[]); 192 static int bge_get_eaddr_mem(struct bge_softc *, uint8_t[]); 193 static int bge_get_eaddr_nvram(struct bge_softc *, uint8_t[]); 194 static int bge_get_eaddr_eeprom(struct bge_softc *, uint8_t[]); 195 static int bge_get_eaddr(struct bge_softc *, uint8_t[]); 196 197 static void bge_txeof(struct bge_softc *); 198 static void bge_rxeof(struct bge_softc *); 199 200 static void bge_asf_driver_up (struct bge_softc *); 201 static void bge_tick(void *); 202 static void bge_stats_update(struct bge_softc *); 203 static void bge_stats_update_regs(struct bge_softc *); 204 static int bge_encap(struct bge_softc *, struct mbuf *, uint32_t *); 205 206 static int bge_intr(void *); 207 static void bge_start(struct ifnet *); 208 static int bge_ifflags_cb(struct ethercom *); 209 static int bge_ioctl(struct ifnet *, u_long, void *); 210 static int bge_init(struct ifnet *); 211 static void bge_stop(struct ifnet *, int); 212 static void bge_watchdog(struct ifnet *); 213 static int bge_ifmedia_upd(struct ifnet *); 214 static void bge_ifmedia_sts(struct ifnet *, struct ifmediareq *); 215 216 static uint8_t bge_nvram_getbyte(struct bge_softc *, int, uint8_t *); 217 static int bge_read_nvram(struct bge_softc *, uint8_t *, int, int); 218 219 static uint8_t bge_eeprom_getbyte(struct bge_softc *, int, uint8_t *); 220 static int bge_read_eeprom(struct bge_softc *, void *, int, int); 221 static void bge_setmulti(struct bge_softc *); 222 223 static void bge_handle_events(struct bge_softc *); 224 static int bge_alloc_jumbo_mem(struct bge_softc *); 225 #if 0 /* XXX */ 226 static void bge_free_jumbo_mem(struct bge_softc *); 227 #endif 228 static void *bge_jalloc(struct bge_softc *); 229 static void bge_jfree(struct mbuf *, void *, size_t, void *); 230 static int bge_newbuf_std(struct bge_softc *, int, struct mbuf *, 231 bus_dmamap_t); 232 static int bge_newbuf_jumbo(struct bge_softc *, int, struct mbuf *); 233 static int bge_init_rx_ring_std(struct bge_softc *); 234 static void bge_free_rx_ring_std(struct bge_softc *); 235 static int bge_init_rx_ring_jumbo(struct bge_softc *); 236 static void bge_free_rx_ring_jumbo(struct bge_softc *); 237 static void bge_free_tx_ring(struct bge_softc *); 238 static int bge_init_tx_ring(struct bge_softc *); 239 240 static int bge_chipinit(struct bge_softc *); 241 static int bge_blockinit(struct bge_softc *); 242 static int bge_setpowerstate(struct bge_softc *, int); 243 static uint32_t bge_readmem_ind(struct bge_softc *, int); 244 static void bge_writemem_ind(struct bge_softc *, int, int); 245 static void bge_writembx(struct bge_softc *, int, int); 246 static void bge_writembx_flush(struct bge_softc *, int, int); 247 static void bge_writemem_direct(struct bge_softc *, int, int); 248 static void bge_writereg_ind(struct bge_softc *, int, int); 249 static void bge_set_max_readrq(struct bge_softc *); 250 251 static int bge_miibus_readreg(device_t, int, int); 252 static void bge_miibus_writereg(device_t, int, int, int); 253 static void bge_miibus_statchg(struct ifnet *); 254 255 #define BGE_RESET_START 1 256 #define BGE_RESET_STOP 2 257 static void bge_sig_post_reset(struct bge_softc *, int); 258 static void bge_sig_legacy(struct bge_softc *, int); 259 static void bge_sig_pre_reset(struct bge_softc *, int); 260 static void bge_stop_fw(struct bge_softc *); 261 static int bge_reset(struct bge_softc *); 262 static void bge_link_upd(struct bge_softc *); 263 static void bge_sysctl_init(struct bge_softc *); 264 static int bge_sysctl_verify(SYSCTLFN_PROTO); 265 266 #ifdef BGE_DEBUG 267 #define DPRINTF(x) if (bgedebug) printf x 268 #define DPRINTFN(n,x) if (bgedebug >= (n)) printf x 269 #define BGE_TSO_PRINTF(x) do { if (bge_tso_debug) printf x ;} while (0) 270 int bgedebug = 0; 271 int bge_tso_debug = 0; 272 void bge_debug_info(struct bge_softc *); 273 #else 274 #define DPRINTF(x) 275 #define DPRINTFN(n,x) 276 #define BGE_TSO_PRINTF(x) 277 #endif 278 279 #ifdef BGE_EVENT_COUNTERS 280 #define BGE_EVCNT_INCR(ev) (ev).ev_count++ 281 #define BGE_EVCNT_ADD(ev, val) (ev).ev_count += (val) 282 #define BGE_EVCNT_UPD(ev, val) (ev).ev_count = (val) 283 #else 284 #define BGE_EVCNT_INCR(ev) /* nothing */ 285 #define BGE_EVCNT_ADD(ev, val) /* nothing */ 286 #define BGE_EVCNT_UPD(ev, val) /* nothing */ 287 #endif 288 289 static const struct bge_product { 290 pci_vendor_id_t bp_vendor; 291 pci_product_id_t bp_product; 292 const char *bp_name; 293 } bge_products[] = { 294 /* 295 * The BCM5700 documentation seems to indicate that the hardware 296 * still has the Alteon vendor ID burned into it, though it 297 * should always be overridden by the value in the EEPROM. We'll 298 * check for it anyway. 299 */ 300 { PCI_VENDOR_ALTEON, 301 PCI_PRODUCT_ALTEON_BCM5700, 302 "Broadcom BCM5700 Gigabit Ethernet", 303 }, 304 { PCI_VENDOR_ALTEON, 305 PCI_PRODUCT_ALTEON_BCM5701, 306 "Broadcom BCM5701 Gigabit Ethernet", 307 }, 308 { PCI_VENDOR_ALTIMA, 309 PCI_PRODUCT_ALTIMA_AC1000, 310 "Altima AC1000 Gigabit Ethernet", 311 }, 312 { PCI_VENDOR_ALTIMA, 313 PCI_PRODUCT_ALTIMA_AC1001, 314 "Altima AC1001 Gigabit Ethernet", 315 }, 316 { PCI_VENDOR_ALTIMA, 317 PCI_PRODUCT_ALTIMA_AC1003, 318 "Altima AC1003 Gigabit Ethernet", 319 }, 320 { PCI_VENDOR_ALTIMA, 321 PCI_PRODUCT_ALTIMA_AC9100, 322 "Altima AC9100 Gigabit Ethernet", 323 }, 324 { PCI_VENDOR_APPLE, 325 PCI_PRODUCT_APPLE_BCM5701, 326 "APPLE BCM5701 Gigabit Ethernet", 327 }, 328 { PCI_VENDOR_BROADCOM, 329 PCI_PRODUCT_BROADCOM_BCM5700, 330 "Broadcom BCM5700 Gigabit Ethernet", 331 }, 332 { PCI_VENDOR_BROADCOM, 333 PCI_PRODUCT_BROADCOM_BCM5701, 334 "Broadcom BCM5701 Gigabit Ethernet", 335 }, 336 { PCI_VENDOR_BROADCOM, 337 PCI_PRODUCT_BROADCOM_BCM5702, 338 "Broadcom BCM5702 Gigabit Ethernet", 339 }, 340 { PCI_VENDOR_BROADCOM, 341 PCI_PRODUCT_BROADCOM_BCM5702X, 342 "Broadcom BCM5702X Gigabit Ethernet" }, 343 { PCI_VENDOR_BROADCOM, 344 PCI_PRODUCT_BROADCOM_BCM5703, 345 "Broadcom BCM5703 Gigabit Ethernet", 346 }, 347 { PCI_VENDOR_BROADCOM, 348 PCI_PRODUCT_BROADCOM_BCM5703X, 349 "Broadcom BCM5703X Gigabit Ethernet", 350 }, 351 { PCI_VENDOR_BROADCOM, 352 PCI_PRODUCT_BROADCOM_BCM5703_ALT, 353 "Broadcom BCM5703 Gigabit Ethernet", 354 }, 355 { PCI_VENDOR_BROADCOM, 356 PCI_PRODUCT_BROADCOM_BCM5704C, 357 "Broadcom BCM5704C Dual Gigabit Ethernet", 358 }, 359 { PCI_VENDOR_BROADCOM, 360 PCI_PRODUCT_BROADCOM_BCM5704S, 361 "Broadcom BCM5704S Dual Gigabit Ethernet", 362 }, 363 { PCI_VENDOR_BROADCOM, 364 PCI_PRODUCT_BROADCOM_BCM5705, 365 "Broadcom BCM5705 Gigabit Ethernet", 366 }, 367 { PCI_VENDOR_BROADCOM, 368 PCI_PRODUCT_BROADCOM_BCM5705F, 369 "Broadcom BCM5705F Gigabit Ethernet", 370 }, 371 { PCI_VENDOR_BROADCOM, 372 PCI_PRODUCT_BROADCOM_BCM5705K, 373 "Broadcom BCM5705K Gigabit Ethernet", 374 }, 375 { PCI_VENDOR_BROADCOM, 376 PCI_PRODUCT_BROADCOM_BCM5705M, 377 "Broadcom BCM5705M Gigabit Ethernet", 378 }, 379 { PCI_VENDOR_BROADCOM, 380 PCI_PRODUCT_BROADCOM_BCM5705M_ALT, 381 "Broadcom BCM5705M Gigabit Ethernet", 382 }, 383 { PCI_VENDOR_BROADCOM, 384 PCI_PRODUCT_BROADCOM_BCM5714, 385 "Broadcom BCM5714 Gigabit Ethernet", 386 }, 387 { PCI_VENDOR_BROADCOM, 388 PCI_PRODUCT_BROADCOM_BCM5714S, 389 "Broadcom BCM5714S Gigabit Ethernet", 390 }, 391 { PCI_VENDOR_BROADCOM, 392 PCI_PRODUCT_BROADCOM_BCM5715, 393 "Broadcom BCM5715 Gigabit Ethernet", 394 }, 395 { PCI_VENDOR_BROADCOM, 396 PCI_PRODUCT_BROADCOM_BCM5715S, 397 "Broadcom BCM5715S Gigabit Ethernet", 398 }, 399 { PCI_VENDOR_BROADCOM, 400 PCI_PRODUCT_BROADCOM_BCM5717, 401 "Broadcom BCM5717 Gigabit Ethernet", 402 }, 403 { PCI_VENDOR_BROADCOM, 404 PCI_PRODUCT_BROADCOM_BCM5718, 405 "Broadcom BCM5718 Gigabit Ethernet", 406 }, 407 #if 0 408 { PCI_VENDOR_BROADCOM, 409 PCI_PRODUCT_BROADCOM_BCM5720, 410 "Broadcom BCM5720 Gigabit Ethernet", 411 }, 412 #endif 413 { PCI_VENDOR_BROADCOM, 414 PCI_PRODUCT_BROADCOM_BCM5721, 415 "Broadcom BCM5721 Gigabit Ethernet", 416 }, 417 { PCI_VENDOR_BROADCOM, 418 PCI_PRODUCT_BROADCOM_BCM5722, 419 "Broadcom BCM5722 Gigabit Ethernet", 420 }, 421 { PCI_VENDOR_BROADCOM, 422 PCI_PRODUCT_BROADCOM_BCM5723, 423 "Broadcom BCM5723 Gigabit Ethernet", 424 }, 425 { PCI_VENDOR_BROADCOM, 426 PCI_PRODUCT_BROADCOM_BCM5724, 427 "Broadcom BCM5724 Gigabit Ethernet", 428 }, 429 { PCI_VENDOR_BROADCOM, 430 PCI_PRODUCT_BROADCOM_BCM5750, 431 "Broadcom BCM5750 Gigabit Ethernet", 432 }, 433 { PCI_VENDOR_BROADCOM, 434 PCI_PRODUCT_BROADCOM_BCM5750M, 435 "Broadcom BCM5750M Gigabit Ethernet", 436 }, 437 { PCI_VENDOR_BROADCOM, 438 PCI_PRODUCT_BROADCOM_BCM5751, 439 "Broadcom BCM5751 Gigabit Ethernet", 440 }, 441 { PCI_VENDOR_BROADCOM, 442 PCI_PRODUCT_BROADCOM_BCM5751F, 443 "Broadcom BCM5751F Gigabit Ethernet", 444 }, 445 { PCI_VENDOR_BROADCOM, 446 PCI_PRODUCT_BROADCOM_BCM5751M, 447 "Broadcom BCM5751M Gigabit Ethernet", 448 }, 449 { PCI_VENDOR_BROADCOM, 450 PCI_PRODUCT_BROADCOM_BCM5752, 451 "Broadcom BCM5752 Gigabit Ethernet", 452 }, 453 { PCI_VENDOR_BROADCOM, 454 PCI_PRODUCT_BROADCOM_BCM5752M, 455 "Broadcom BCM5752M Gigabit Ethernet", 456 }, 457 { PCI_VENDOR_BROADCOM, 458 PCI_PRODUCT_BROADCOM_BCM5753, 459 "Broadcom BCM5753 Gigabit Ethernet", 460 }, 461 { PCI_VENDOR_BROADCOM, 462 PCI_PRODUCT_BROADCOM_BCM5753F, 463 "Broadcom BCM5753F Gigabit Ethernet", 464 }, 465 { PCI_VENDOR_BROADCOM, 466 PCI_PRODUCT_BROADCOM_BCM5753M, 467 "Broadcom BCM5753M Gigabit Ethernet", 468 }, 469 { PCI_VENDOR_BROADCOM, 470 PCI_PRODUCT_BROADCOM_BCM5754, 471 "Broadcom BCM5754 Gigabit Ethernet", 472 }, 473 { PCI_VENDOR_BROADCOM, 474 PCI_PRODUCT_BROADCOM_BCM5754M, 475 "Broadcom BCM5754M Gigabit Ethernet", 476 }, 477 { PCI_VENDOR_BROADCOM, 478 PCI_PRODUCT_BROADCOM_BCM5755, 479 "Broadcom BCM5755 Gigabit Ethernet", 480 }, 481 { PCI_VENDOR_BROADCOM, 482 PCI_PRODUCT_BROADCOM_BCM5755M, 483 "Broadcom BCM5755M Gigabit Ethernet", 484 }, 485 { PCI_VENDOR_BROADCOM, 486 PCI_PRODUCT_BROADCOM_BCM5756, 487 "Broadcom BCM5756 Gigabit Ethernet", 488 }, 489 { PCI_VENDOR_BROADCOM, 490 PCI_PRODUCT_BROADCOM_BCM5761, 491 "Broadcom BCM5761 Gigabit Ethernet", 492 }, 493 { PCI_VENDOR_BROADCOM, 494 PCI_PRODUCT_BROADCOM_BCM5761E, 495 "Broadcom BCM5761E Gigabit Ethernet", 496 }, 497 { PCI_VENDOR_BROADCOM, 498 PCI_PRODUCT_BROADCOM_BCM5761S, 499 "Broadcom BCM5761S Gigabit Ethernet", 500 }, 501 { PCI_VENDOR_BROADCOM, 502 PCI_PRODUCT_BROADCOM_BCM5761SE, 503 "Broadcom BCM5761SE Gigabit Ethernet", 504 }, 505 { PCI_VENDOR_BROADCOM, 506 PCI_PRODUCT_BROADCOM_BCM5764, 507 "Broadcom BCM5764 Gigabit Ethernet", 508 }, 509 { PCI_VENDOR_BROADCOM, 510 PCI_PRODUCT_BROADCOM_BCM5780, 511 "Broadcom BCM5780 Gigabit Ethernet", 512 }, 513 { PCI_VENDOR_BROADCOM, 514 PCI_PRODUCT_BROADCOM_BCM5780S, 515 "Broadcom BCM5780S Gigabit Ethernet", 516 }, 517 { PCI_VENDOR_BROADCOM, 518 PCI_PRODUCT_BROADCOM_BCM5781, 519 "Broadcom BCM5781 Gigabit Ethernet", 520 }, 521 { PCI_VENDOR_BROADCOM, 522 PCI_PRODUCT_BROADCOM_BCM5782, 523 "Broadcom BCM5782 Gigabit Ethernet", 524 }, 525 { PCI_VENDOR_BROADCOM, 526 PCI_PRODUCT_BROADCOM_BCM5784M, 527 "BCM5784M NetLink 1000baseT Ethernet", 528 }, 529 { PCI_VENDOR_BROADCOM, 530 PCI_PRODUCT_BROADCOM_BCM5785F, 531 "BCM5785F NetLink 10/100 Ethernet", 532 }, 533 { PCI_VENDOR_BROADCOM, 534 PCI_PRODUCT_BROADCOM_BCM5785G, 535 "BCM5785G NetLink 1000baseT Ethernet", 536 }, 537 { PCI_VENDOR_BROADCOM, 538 PCI_PRODUCT_BROADCOM_BCM5786, 539 "Broadcom BCM5786 Gigabit Ethernet", 540 }, 541 { PCI_VENDOR_BROADCOM, 542 PCI_PRODUCT_BROADCOM_BCM5787, 543 "Broadcom BCM5787 Gigabit Ethernet", 544 }, 545 { PCI_VENDOR_BROADCOM, 546 PCI_PRODUCT_BROADCOM_BCM5787F, 547 "Broadcom BCM5787F 10/100 Ethernet", 548 }, 549 { PCI_VENDOR_BROADCOM, 550 PCI_PRODUCT_BROADCOM_BCM5787M, 551 "Broadcom BCM5787M Gigabit Ethernet", 552 }, 553 { PCI_VENDOR_BROADCOM, 554 PCI_PRODUCT_BROADCOM_BCM5788, 555 "Broadcom BCM5788 Gigabit Ethernet", 556 }, 557 { PCI_VENDOR_BROADCOM, 558 PCI_PRODUCT_BROADCOM_BCM5789, 559 "Broadcom BCM5789 Gigabit Ethernet", 560 }, 561 { PCI_VENDOR_BROADCOM, 562 PCI_PRODUCT_BROADCOM_BCM5901, 563 "Broadcom BCM5901 Fast Ethernet", 564 }, 565 { PCI_VENDOR_BROADCOM, 566 PCI_PRODUCT_BROADCOM_BCM5901A2, 567 "Broadcom BCM5901A2 Fast Ethernet", 568 }, 569 { PCI_VENDOR_BROADCOM, 570 PCI_PRODUCT_BROADCOM_BCM5903M, 571 "Broadcom BCM5903M Fast Ethernet", 572 }, 573 { PCI_VENDOR_BROADCOM, 574 PCI_PRODUCT_BROADCOM_BCM5906, 575 "Broadcom BCM5906 Fast Ethernet", 576 }, 577 { PCI_VENDOR_BROADCOM, 578 PCI_PRODUCT_BROADCOM_BCM5906M, 579 "Broadcom BCM5906M Fast Ethernet", 580 }, 581 { PCI_VENDOR_BROADCOM, 582 PCI_PRODUCT_BROADCOM_BCM57760, 583 "Broadcom BCM57760 Fast Ethernet", 584 }, 585 { PCI_VENDOR_BROADCOM, 586 PCI_PRODUCT_BROADCOM_BCM57761, 587 "Broadcom BCM57761 Fast Ethernet", 588 }, 589 { PCI_VENDOR_BROADCOM, 590 PCI_PRODUCT_BROADCOM_BCM57762, 591 "Broadcom BCM57762 Gigabit Ethernet", 592 }, 593 { PCI_VENDOR_BROADCOM, 594 PCI_PRODUCT_BROADCOM_BCM57765, 595 "Broadcom BCM57765 Fast Ethernet", 596 }, 597 { PCI_VENDOR_BROADCOM, 598 PCI_PRODUCT_BROADCOM_BCM57780, 599 "Broadcom BCM57780 Fast Ethernet", 600 }, 601 { PCI_VENDOR_BROADCOM, 602 PCI_PRODUCT_BROADCOM_BCM57781, 603 "Broadcom BCM57781 Fast Ethernet", 604 }, 605 { PCI_VENDOR_BROADCOM, 606 PCI_PRODUCT_BROADCOM_BCM57785, 607 "Broadcom BCM57785 Fast Ethernet", 608 }, 609 { PCI_VENDOR_BROADCOM, 610 PCI_PRODUCT_BROADCOM_BCM57788, 611 "Broadcom BCM57788 Fast Ethernet", 612 }, 613 { PCI_VENDOR_BROADCOM, 614 PCI_PRODUCT_BROADCOM_BCM57790, 615 "Broadcom BCM57790 Fast Ethernet", 616 }, 617 { PCI_VENDOR_BROADCOM, 618 PCI_PRODUCT_BROADCOM_BCM57791, 619 "Broadcom BCM57791 Fast Ethernet", 620 }, 621 { PCI_VENDOR_BROADCOM, 622 PCI_PRODUCT_BROADCOM_BCM57795, 623 "Broadcom BCM57795 Fast Ethernet", 624 }, 625 { PCI_VENDOR_SCHNEIDERKOCH, 626 PCI_PRODUCT_SCHNEIDERKOCH_SK_9DX1, 627 "SysKonnect SK-9Dx1 Gigabit Ethernet", 628 }, 629 { PCI_VENDOR_3COM, 630 PCI_PRODUCT_3COM_3C996, 631 "3Com 3c996 Gigabit Ethernet", 632 }, 633 { PCI_VENDOR_FUJITSU4, 634 PCI_PRODUCT_FUJITSU4_PW008GE4, 635 "Fujitsu PW008GE4 Gigabit Ethernet", 636 }, 637 { PCI_VENDOR_FUJITSU4, 638 PCI_PRODUCT_FUJITSU4_PW008GE5, 639 "Fujitsu PW008GE5 Gigabit Ethernet", 640 }, 641 { PCI_VENDOR_FUJITSU4, 642 PCI_PRODUCT_FUJITSU4_PP250_450_LAN, 643 "Fujitsu Primepower 250/450 Gigabit Ethernet", 644 }, 645 { 0, 646 0, 647 NULL }, 648 }; 649 650 #define BGE_IS_5700_FAMILY(sc) ((sc)->bge_flags & BGE_5700_FAMILY) 651 #define BGE_IS_5714_FAMILY(sc) ((sc)->bge_flags & BGE_5714_FAMILY) 652 #define BGE_IS_5705_PLUS(sc) ((sc)->bge_flags & BGE_5705_PLUS) 653 #define BGE_IS_575X_PLUS(sc) ((sc)->bge_flags & BGE_575X_PLUS) 654 #define BGE_IS_5755_PLUS(sc) ((sc)->bge_flags & BGE_5755_PLUS) 655 #define BGE_IS_JUMBO_CAPABLE(sc) ((sc)->bge_flags & BGE_JUMBO_CAPABLE) 656 657 static const struct bge_revision { 658 uint32_t br_chipid; 659 const char *br_name; 660 } bge_revisions[] = { 661 { BGE_CHIPID_BCM5700_A0, "BCM5700 A0" }, 662 { BGE_CHIPID_BCM5700_A1, "BCM5700 A1" }, 663 { BGE_CHIPID_BCM5700_B0, "BCM5700 B0" }, 664 { BGE_CHIPID_BCM5700_B1, "BCM5700 B1" }, 665 { BGE_CHIPID_BCM5700_B2, "BCM5700 B2" }, 666 { BGE_CHIPID_BCM5700_B3, "BCM5700 B3" }, 667 /* This is treated like a BCM5700 Bx */ 668 { BGE_CHIPID_BCM5700_ALTIMA, "BCM5700 Altima" }, 669 { BGE_CHIPID_BCM5700_C0, "BCM5700 C0" }, 670 { BGE_CHIPID_BCM5701_A0, "BCM5701 A0" }, 671 { BGE_CHIPID_BCM5701_B0, "BCM5701 B0" }, 672 { BGE_CHIPID_BCM5701_B2, "BCM5701 B2" }, 673 { BGE_CHIPID_BCM5701_B5, "BCM5701 B5" }, 674 { BGE_CHIPID_BCM5703_A0, "BCM5702/5703 A0" }, 675 { BGE_CHIPID_BCM5703_A1, "BCM5702/5703 A1" }, 676 { BGE_CHIPID_BCM5703_A2, "BCM5702/5703 A2" }, 677 { BGE_CHIPID_BCM5703_A3, "BCM5702/5703 A3" }, 678 { BGE_CHIPID_BCM5703_B0, "BCM5702/5703 B0" }, 679 { BGE_CHIPID_BCM5704_A0, "BCM5704 A0" }, 680 { BGE_CHIPID_BCM5704_A1, "BCM5704 A1" }, 681 { BGE_CHIPID_BCM5704_A2, "BCM5704 A2" }, 682 { BGE_CHIPID_BCM5704_A3, "BCM5704 A3" }, 683 { BGE_CHIPID_BCM5704_B0, "BCM5704 B0" }, 684 { BGE_CHIPID_BCM5705_A0, "BCM5705 A0" }, 685 { BGE_CHIPID_BCM5705_A1, "BCM5705 A1" }, 686 { BGE_CHIPID_BCM5705_A2, "BCM5705 A2" }, 687 { BGE_CHIPID_BCM5705_A3, "BCM5705 A3" }, 688 { BGE_CHIPID_BCM5750_A0, "BCM5750 A0" }, 689 { BGE_CHIPID_BCM5750_A1, "BCM5750 A1" }, 690 { BGE_CHIPID_BCM5750_A3, "BCM5750 A3" }, 691 { BGE_CHIPID_BCM5750_B0, "BCM5750 B0" }, 692 { BGE_CHIPID_BCM5750_B1, "BCM5750 B1" }, 693 { BGE_CHIPID_BCM5750_C0, "BCM5750 C0" }, 694 { BGE_CHIPID_BCM5750_C1, "BCM5750 C1" }, 695 { BGE_CHIPID_BCM5750_C2, "BCM5750 C2" }, 696 { BGE_CHIPID_BCM5752_A0, "BCM5752 A0" }, 697 { BGE_CHIPID_BCM5752_A1, "BCM5752 A1" }, 698 { BGE_CHIPID_BCM5752_A2, "BCM5752 A2" }, 699 { BGE_CHIPID_BCM5714_A0, "BCM5714 A0" }, 700 { BGE_CHIPID_BCM5714_B0, "BCM5714 B0" }, 701 { BGE_CHIPID_BCM5714_B3, "BCM5714 B3" }, 702 { BGE_CHIPID_BCM5715_A0, "BCM5715 A0" }, 703 { BGE_CHIPID_BCM5715_A1, "BCM5715 A1" }, 704 { BGE_CHIPID_BCM5715_A3, "BCM5715 A3" }, 705 { BGE_CHIPID_BCM5755_A0, "BCM5755 A0" }, 706 { BGE_CHIPID_BCM5755_A1, "BCM5755 A1" }, 707 { BGE_CHIPID_BCM5755_A2, "BCM5755 A2" }, 708 { BGE_CHIPID_BCM5755_C0, "BCM5755 C0" }, 709 { BGE_CHIPID_BCM5761_A0, "BCM5761 A0" }, 710 { BGE_CHIPID_BCM5761_A1, "BCM5761 A1" }, 711 { BGE_CHIPID_BCM5784_A0, "BCM5784 A0" }, 712 { BGE_CHIPID_BCM5784_A1, "BCM5784 A1" }, 713 /* 5754 and 5787 share the same ASIC ID */ 714 { BGE_CHIPID_BCM5787_A0, "BCM5754/5787 A0" }, 715 { BGE_CHIPID_BCM5787_A1, "BCM5754/5787 A1" }, 716 { BGE_CHIPID_BCM5787_A2, "BCM5754/5787 A2" }, 717 { BGE_CHIPID_BCM5906_A0, "BCM5906 A0" }, 718 { BGE_CHIPID_BCM5906_A1, "BCM5906 A1" }, 719 { BGE_CHIPID_BCM5906_A2, "BCM5906 A2" }, 720 { BGE_CHIPID_BCM57780_A0, "BCM57780 A0" }, 721 { BGE_CHIPID_BCM57780_A1, "BCM57780 A1" }, 722 723 { 0, NULL } 724 }; 725 726 /* 727 * Some defaults for major revisions, so that newer steppings 728 * that we don't know about have a shot at working. 729 */ 730 static const struct bge_revision bge_majorrevs[] = { 731 { BGE_ASICREV_BCM5700, "unknown BCM5700" }, 732 { BGE_ASICREV_BCM5701, "unknown BCM5701" }, 733 { BGE_ASICREV_BCM5703, "unknown BCM5703" }, 734 { BGE_ASICREV_BCM5704, "unknown BCM5704" }, 735 { BGE_ASICREV_BCM5705, "unknown BCM5705" }, 736 { BGE_ASICREV_BCM5750, "unknown BCM5750" }, 737 { BGE_ASICREV_BCM5714_A0, "unknown BCM5714" }, 738 { BGE_ASICREV_BCM5752, "unknown BCM5752" }, 739 { BGE_ASICREV_BCM5780, "unknown BCM5780" }, 740 { BGE_ASICREV_BCM5714, "unknown BCM5714" }, 741 { BGE_ASICREV_BCM5755, "unknown BCM5755" }, 742 { BGE_ASICREV_BCM5761, "unknown BCM5761" }, 743 { BGE_ASICREV_BCM5784, "unknown BCM5784" }, 744 { BGE_ASICREV_BCM5785, "unknown BCM5785" }, 745 /* 5754 and 5787 share the same ASIC ID */ 746 { BGE_ASICREV_BCM5787, "unknown BCM5754/5787" }, 747 { BGE_ASICREV_BCM5906, "unknown BCM5906" }, 748 { BGE_ASICREV_BCM57780, "unknown BCM57780" }, 749 { BGE_ASICREV_BCM5717, "unknown BCM5717" }, 750 { BGE_ASICREV_BCM57765, "unknown BCM57765" }, 751 { BGE_ASICREV_BCM57766, "unknown BCM57766" }, 752 753 { 0, NULL } 754 }; 755 756 static int bge_allow_asf = 1; 757 758 CFATTACH_DECL_NEW(bge, sizeof(struct bge_softc), 759 bge_probe, bge_attach, NULL, NULL); 760 761 static uint32_t 762 bge_readmem_ind(struct bge_softc *sc, int off) 763 { 764 pcireg_t val; 765 766 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_BASEADDR, off); 767 val = pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_DATA); 768 return val; 769 } 770 771 static void 772 bge_writemem_ind(struct bge_softc *sc, int off, int val) 773 { 774 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_BASEADDR, off); 775 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_DATA, val); 776 } 777 778 /* 779 * PCI Express only 780 */ 781 static void 782 bge_set_max_readrq(struct bge_softc *sc) 783 { 784 pcireg_t val; 785 786 val = pci_conf_read(sc->sc_pc, sc->sc_pcitag, sc->bge_pciecap 787 + PCI_PCIE_DCSR); 788 if ((val & PCI_PCIE_DCSR_MAX_READ_REQ) != 789 BGE_PCIE_DEVCTL_MAX_READRQ_4096) { 790 aprint_verbose_dev(sc->bge_dev, 791 "adjust device control 0x%04x ", val); 792 val &= ~PCI_PCIE_DCSR_MAX_READ_REQ; 793 val |= BGE_PCIE_DEVCTL_MAX_READRQ_4096; 794 pci_conf_write(sc->sc_pc, sc->sc_pcitag, sc->bge_pciecap 795 + PCI_PCIE_DCSR, val); 796 aprint_verbose("-> 0x%04x\n", val); 797 } 798 } 799 800 #ifdef notdef 801 static uint32_t 802 bge_readreg_ind(struct bge_softc *sc, int off) 803 { 804 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_REG_BASEADDR, off); 805 return (pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_REG_DATA)); 806 } 807 #endif 808 809 static void 810 bge_writereg_ind(struct bge_softc *sc, int off, int val) 811 { 812 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_REG_BASEADDR, off); 813 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_REG_DATA, val); 814 } 815 816 static void 817 bge_writemem_direct(struct bge_softc *sc, int off, int val) 818 { 819 CSR_WRITE_4(sc, off, val); 820 } 821 822 static void 823 bge_writembx(struct bge_softc *sc, int off, int val) 824 { 825 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 826 off += BGE_LPMBX_IRQ0_HI - BGE_MBX_IRQ0_HI; 827 828 CSR_WRITE_4(sc, off, val); 829 } 830 831 static void 832 bge_writembx_flush(struct bge_softc *sc, int off, int val) 833 { 834 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 835 off += BGE_LPMBX_IRQ0_HI - BGE_MBX_IRQ0_HI; 836 837 CSR_WRITE_4_FLUSH(sc, off, val); 838 } 839 840 static uint8_t 841 bge_nvram_getbyte(struct bge_softc *sc, int addr, uint8_t *dest) 842 { 843 uint32_t access, byte = 0; 844 int i; 845 846 /* Lock. */ 847 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_SET1); 848 for (i = 0; i < 8000; i++) { 849 if (CSR_READ_4(sc, BGE_NVRAM_SWARB) & BGE_NVRAMSWARB_GNT1) 850 break; 851 DELAY(20); 852 } 853 if (i == 8000) 854 return 1; 855 856 /* Enable access. */ 857 access = CSR_READ_4(sc, BGE_NVRAM_ACCESS); 858 CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access | BGE_NVRAMACC_ENABLE); 859 860 CSR_WRITE_4(sc, BGE_NVRAM_ADDR, addr & 0xfffffffc); 861 CSR_WRITE_4(sc, BGE_NVRAM_CMD, BGE_NVRAM_READCMD); 862 for (i = 0; i < BGE_TIMEOUT * 10; i++) { 863 DELAY(10); 864 if (CSR_READ_4(sc, BGE_NVRAM_CMD) & BGE_NVRAMCMD_DONE) { 865 DELAY(10); 866 break; 867 } 868 } 869 870 if (i == BGE_TIMEOUT * 10) { 871 aprint_error_dev(sc->bge_dev, "nvram read timed out\n"); 872 return 1; 873 } 874 875 /* Get result. */ 876 byte = CSR_READ_4(sc, BGE_NVRAM_RDDATA); 877 878 *dest = (bswap32(byte) >> ((addr % 4) * 8)) & 0xFF; 879 880 /* Disable access. */ 881 CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access); 882 883 /* Unlock. */ 884 CSR_WRITE_4_FLUSH(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_CLR1); 885 886 return 0; 887 } 888 889 /* 890 * Read a sequence of bytes from NVRAM. 891 */ 892 static int 893 bge_read_nvram(struct bge_softc *sc, uint8_t *dest, int off, int cnt) 894 { 895 int error = 0, i; 896 uint8_t byte = 0; 897 898 if (BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5906) 899 return 1; 900 901 for (i = 0; i < cnt; i++) { 902 error = bge_nvram_getbyte(sc, off + i, &byte); 903 if (error) 904 break; 905 *(dest + i) = byte; 906 } 907 908 return (error ? 1 : 0); 909 } 910 911 /* 912 * Read a byte of data stored in the EEPROM at address 'addr.' The 913 * BCM570x supports both the traditional bitbang interface and an 914 * auto access interface for reading the EEPROM. We use the auto 915 * access method. 916 */ 917 static uint8_t 918 bge_eeprom_getbyte(struct bge_softc *sc, int addr, uint8_t *dest) 919 { 920 int i; 921 uint32_t byte = 0; 922 923 /* 924 * Enable use of auto EEPROM access so we can avoid 925 * having to use the bitbang method. 926 */ 927 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM); 928 929 /* Reset the EEPROM, load the clock period. */ 930 CSR_WRITE_4(sc, BGE_EE_ADDR, 931 BGE_EEADDR_RESET | BGE_EEHALFCLK(BGE_HALFCLK_384SCL)); 932 DELAY(20); 933 934 /* Issue the read EEPROM command. */ 935 CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr); 936 937 /* Wait for completion */ 938 for (i = 0; i < BGE_TIMEOUT * 10; i++) { 939 DELAY(10); 940 if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE) 941 break; 942 } 943 944 if (i == BGE_TIMEOUT * 10) { 945 aprint_error_dev(sc->bge_dev, "eeprom read timed out\n"); 946 return 1; 947 } 948 949 /* Get result. */ 950 byte = CSR_READ_4(sc, BGE_EE_DATA); 951 952 *dest = (byte >> ((addr % 4) * 8)) & 0xFF; 953 954 return 0; 955 } 956 957 /* 958 * Read a sequence of bytes from the EEPROM. 959 */ 960 static int 961 bge_read_eeprom(struct bge_softc *sc, void *destv, int off, int cnt) 962 { 963 int error = 0, i; 964 uint8_t byte = 0; 965 char *dest = destv; 966 967 for (i = 0; i < cnt; i++) { 968 error = bge_eeprom_getbyte(sc, off + i, &byte); 969 if (error) 970 break; 971 *(dest + i) = byte; 972 } 973 974 return (error ? 1 : 0); 975 } 976 977 static int 978 bge_miibus_readreg(device_t dev, int phy, int reg) 979 { 980 struct bge_softc *sc = device_private(dev); 981 uint32_t val; 982 uint32_t autopoll; 983 int i; 984 985 /* 986 * Broadcom's own driver always assumes the internal 987 * PHY is at GMII address 1. On some chips, the PHY responds 988 * to accesses at all addresses, which could cause us to 989 * bogusly attach the PHY 32 times at probe type. Always 990 * restricting the lookup to address 1 is simpler than 991 * trying to figure out which chips revisions should be 992 * special-cased. 993 */ 994 if (phy != 1) 995 return 0; 996 997 /* Reading with autopolling on may trigger PCI errors */ 998 autopoll = CSR_READ_4(sc, BGE_MI_MODE); 999 if (autopoll & BGE_MIMODE_AUTOPOLL) { 1000 BGE_STS_CLRBIT(sc, BGE_STS_AUTOPOLL); 1001 BGE_CLRBIT_FLUSH(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 1002 DELAY(40); 1003 } 1004 1005 CSR_WRITE_4_FLUSH(sc, BGE_MI_COMM, BGE_MICMD_READ | BGE_MICOMM_BUSY | 1006 BGE_MIPHY(phy) | BGE_MIREG(reg)); 1007 1008 for (i = 0; i < BGE_TIMEOUT; i++) { 1009 val = CSR_READ_4(sc, BGE_MI_COMM); 1010 if (!(val & BGE_MICOMM_BUSY)) 1011 break; 1012 delay(10); 1013 } 1014 1015 if (i == BGE_TIMEOUT) { 1016 aprint_error_dev(sc->bge_dev, "PHY read timed out\n"); 1017 val = 0; 1018 goto done; 1019 } 1020 1021 val = CSR_READ_4(sc, BGE_MI_COMM); 1022 1023 done: 1024 if (autopoll & BGE_MIMODE_AUTOPOLL) { 1025 BGE_STS_SETBIT(sc, BGE_STS_AUTOPOLL); 1026 BGE_SETBIT_FLUSH(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 1027 DELAY(40); 1028 } 1029 1030 if (val & BGE_MICOMM_READFAIL) 1031 return 0; 1032 1033 return (val & 0xFFFF); 1034 } 1035 1036 static void 1037 bge_miibus_writereg(device_t dev, int phy, int reg, int val) 1038 { 1039 struct bge_softc *sc = device_private(dev); 1040 uint32_t autopoll; 1041 int i; 1042 1043 if (phy!=1) { 1044 return; 1045 } 1046 1047 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906 && 1048 (reg == BRGPHY_MII_1000CTL || reg == BRGPHY_MII_AUXCTL)) 1049 return; 1050 1051 /* Reading with autopolling on may trigger PCI errors */ 1052 autopoll = CSR_READ_4(sc, BGE_MI_MODE); 1053 if (autopoll & BGE_MIMODE_AUTOPOLL) { 1054 delay(40); 1055 BGE_STS_CLRBIT(sc, BGE_STS_AUTOPOLL); 1056 BGE_CLRBIT_FLUSH(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 1057 delay(10); /* 40 usec is supposed to be adequate */ 1058 } 1059 1060 CSR_WRITE_4_FLUSH(sc, BGE_MI_COMM, BGE_MICMD_WRITE | BGE_MICOMM_BUSY | 1061 BGE_MIPHY(phy) | BGE_MIREG(reg) | val); 1062 1063 for (i = 0; i < BGE_TIMEOUT; i++) { 1064 delay(10); 1065 if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY)) { 1066 delay(5); 1067 CSR_READ_4(sc, BGE_MI_COMM); 1068 break; 1069 } 1070 } 1071 1072 if (autopoll & BGE_MIMODE_AUTOPOLL) { 1073 BGE_STS_SETBIT(sc, BGE_STS_AUTOPOLL); 1074 BGE_SETBIT_FLUSH(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 1075 delay(40); 1076 } 1077 1078 if (i == BGE_TIMEOUT) 1079 aprint_error_dev(sc->bge_dev, "PHY read timed out\n"); 1080 } 1081 1082 static void 1083 bge_miibus_statchg(struct ifnet *ifp) 1084 { 1085 struct bge_softc *sc = ifp->if_softc; 1086 struct mii_data *mii = &sc->bge_mii; 1087 1088 /* 1089 * Get flow control negotiation result. 1090 */ 1091 if (IFM_SUBTYPE(mii->mii_media.ifm_cur->ifm_media) == IFM_AUTO && 1092 (mii->mii_media_active & IFM_ETH_FMASK) != sc->bge_flowflags) { 1093 sc->bge_flowflags = mii->mii_media_active & IFM_ETH_FMASK; 1094 mii->mii_media_active &= ~IFM_ETH_FMASK; 1095 } 1096 1097 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_PORTMODE); 1098 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T || 1099 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX) 1100 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_GMII); 1101 else 1102 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_MII); 1103 1104 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) 1105 BGE_CLRBIT_FLUSH(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX); 1106 else 1107 BGE_SETBIT_FLUSH(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX); 1108 DELAY(40); 1109 1110 /* 1111 * 802.3x flow control 1112 */ 1113 if (sc->bge_flowflags & IFM_ETH_RXPAUSE) 1114 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_FLOWCTL_ENABLE); 1115 else 1116 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_FLOWCTL_ENABLE); 1117 1118 if (sc->bge_flowflags & IFM_ETH_TXPAUSE) 1119 BGE_SETBIT(sc, BGE_TX_MODE, BGE_TXMODE_FLOWCTL_ENABLE); 1120 else 1121 BGE_CLRBIT(sc, BGE_TX_MODE, BGE_TXMODE_FLOWCTL_ENABLE); 1122 } 1123 1124 /* 1125 * Update rx threshold levels to values in a particular slot 1126 * of the interrupt-mitigation table bge_rx_threshes. 1127 */ 1128 static void 1129 bge_set_thresh(struct ifnet *ifp, int lvl) 1130 { 1131 struct bge_softc *sc = ifp->if_softc; 1132 int s; 1133 1134 /* For now, just save the new Rx-intr thresholds and record 1135 * that a threshold update is pending. Updating the hardware 1136 * registers here (even at splhigh()) is observed to 1137 * occasionaly cause glitches where Rx-interrupts are not 1138 * honoured for up to 10 seconds. jonathan (at) NetBSD.org, 2003-04-05 1139 */ 1140 s = splnet(); 1141 sc->bge_rx_coal_ticks = bge_rx_threshes[lvl].rx_ticks; 1142 sc->bge_rx_max_coal_bds = bge_rx_threshes[lvl].rx_max_bds; 1143 sc->bge_pending_rxintr_change = 1; 1144 splx(s); 1145 } 1146 1147 1148 /* 1149 * Update Rx thresholds of all bge devices 1150 */ 1151 static void 1152 bge_update_all_threshes(int lvl) 1153 { 1154 struct ifnet *ifp; 1155 const char * const namebuf = "bge"; 1156 int namelen; 1157 1158 if (lvl < 0) 1159 lvl = 0; 1160 else if (lvl >= NBGE_RX_THRESH) 1161 lvl = NBGE_RX_THRESH - 1; 1162 1163 namelen = strlen(namebuf); 1164 /* 1165 * Now search all the interfaces for this name/number 1166 */ 1167 IFNET_FOREACH(ifp) { 1168 if (strncmp(ifp->if_xname, namebuf, namelen) != 0) 1169 continue; 1170 /* We got a match: update if doing auto-threshold-tuning */ 1171 if (bge_auto_thresh) 1172 bge_set_thresh(ifp, lvl); 1173 } 1174 } 1175 1176 /* 1177 * Handle events that have triggered interrupts. 1178 */ 1179 static void 1180 bge_handle_events(struct bge_softc *sc) 1181 { 1182 1183 return; 1184 } 1185 1186 /* 1187 * Memory management for jumbo frames. 1188 */ 1189 1190 static int 1191 bge_alloc_jumbo_mem(struct bge_softc *sc) 1192 { 1193 char *ptr, *kva; 1194 bus_dma_segment_t seg; 1195 int i, rseg, state, error; 1196 struct bge_jpool_entry *entry; 1197 1198 state = error = 0; 1199 1200 /* Grab a big chunk o' storage. */ 1201 if (bus_dmamem_alloc(sc->bge_dmatag, BGE_JMEM, PAGE_SIZE, 0, 1202 &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 1203 aprint_error_dev(sc->bge_dev, "can't alloc rx buffers\n"); 1204 return ENOBUFS; 1205 } 1206 1207 state = 1; 1208 if (bus_dmamem_map(sc->bge_dmatag, &seg, rseg, BGE_JMEM, (void **)&kva, 1209 BUS_DMA_NOWAIT)) { 1210 aprint_error_dev(sc->bge_dev, 1211 "can't map DMA buffers (%d bytes)\n", (int)BGE_JMEM); 1212 error = ENOBUFS; 1213 goto out; 1214 } 1215 1216 state = 2; 1217 if (bus_dmamap_create(sc->bge_dmatag, BGE_JMEM, 1, BGE_JMEM, 0, 1218 BUS_DMA_NOWAIT, &sc->bge_cdata.bge_rx_jumbo_map)) { 1219 aprint_error_dev(sc->bge_dev, "can't create DMA map\n"); 1220 error = ENOBUFS; 1221 goto out; 1222 } 1223 1224 state = 3; 1225 if (bus_dmamap_load(sc->bge_dmatag, sc->bge_cdata.bge_rx_jumbo_map, 1226 kva, BGE_JMEM, NULL, BUS_DMA_NOWAIT)) { 1227 aprint_error_dev(sc->bge_dev, "can't load DMA map\n"); 1228 error = ENOBUFS; 1229 goto out; 1230 } 1231 1232 state = 4; 1233 sc->bge_cdata.bge_jumbo_buf = (void *)kva; 1234 DPRINTFN(1,("bge_jumbo_buf = %p\n", sc->bge_cdata.bge_jumbo_buf)); 1235 1236 SLIST_INIT(&sc->bge_jfree_listhead); 1237 SLIST_INIT(&sc->bge_jinuse_listhead); 1238 1239 /* 1240 * Now divide it up into 9K pieces and save the addresses 1241 * in an array. 1242 */ 1243 ptr = sc->bge_cdata.bge_jumbo_buf; 1244 for (i = 0; i < BGE_JSLOTS; i++) { 1245 sc->bge_cdata.bge_jslots[i] = ptr; 1246 ptr += BGE_JLEN; 1247 entry = malloc(sizeof(struct bge_jpool_entry), 1248 M_DEVBUF, M_NOWAIT); 1249 if (entry == NULL) { 1250 aprint_error_dev(sc->bge_dev, 1251 "no memory for jumbo buffer queue!\n"); 1252 error = ENOBUFS; 1253 goto out; 1254 } 1255 entry->slot = i; 1256 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, 1257 entry, jpool_entries); 1258 } 1259 out: 1260 if (error != 0) { 1261 switch (state) { 1262 case 4: 1263 bus_dmamap_unload(sc->bge_dmatag, 1264 sc->bge_cdata.bge_rx_jumbo_map); 1265 case 3: 1266 bus_dmamap_destroy(sc->bge_dmatag, 1267 sc->bge_cdata.bge_rx_jumbo_map); 1268 case 2: 1269 bus_dmamem_unmap(sc->bge_dmatag, kva, BGE_JMEM); 1270 case 1: 1271 bus_dmamem_free(sc->bge_dmatag, &seg, rseg); 1272 break; 1273 default: 1274 break; 1275 } 1276 } 1277 1278 return error; 1279 } 1280 1281 /* 1282 * Allocate a jumbo buffer. 1283 */ 1284 static void * 1285 bge_jalloc(struct bge_softc *sc) 1286 { 1287 struct bge_jpool_entry *entry; 1288 1289 entry = SLIST_FIRST(&sc->bge_jfree_listhead); 1290 1291 if (entry == NULL) { 1292 aprint_error_dev(sc->bge_dev, "no free jumbo buffers\n"); 1293 return NULL; 1294 } 1295 1296 SLIST_REMOVE_HEAD(&sc->bge_jfree_listhead, jpool_entries); 1297 SLIST_INSERT_HEAD(&sc->bge_jinuse_listhead, entry, jpool_entries); 1298 return (sc->bge_cdata.bge_jslots[entry->slot]); 1299 } 1300 1301 /* 1302 * Release a jumbo buffer. 1303 */ 1304 static void 1305 bge_jfree(struct mbuf *m, void *buf, size_t size, void *arg) 1306 { 1307 struct bge_jpool_entry *entry; 1308 struct bge_softc *sc; 1309 int i, s; 1310 1311 /* Extract the softc struct pointer. */ 1312 sc = (struct bge_softc *)arg; 1313 1314 if (sc == NULL) 1315 panic("bge_jfree: can't find softc pointer!"); 1316 1317 /* calculate the slot this buffer belongs to */ 1318 1319 i = ((char *)buf 1320 - (char *)sc->bge_cdata.bge_jumbo_buf) / BGE_JLEN; 1321 1322 if ((i < 0) || (i >= BGE_JSLOTS)) 1323 panic("bge_jfree: asked to free buffer that we don't manage!"); 1324 1325 s = splvm(); 1326 entry = SLIST_FIRST(&sc->bge_jinuse_listhead); 1327 if (entry == NULL) 1328 panic("bge_jfree: buffer not in use!"); 1329 entry->slot = i; 1330 SLIST_REMOVE_HEAD(&sc->bge_jinuse_listhead, jpool_entries); 1331 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, entry, jpool_entries); 1332 1333 if (__predict_true(m != NULL)) 1334 pool_cache_put(mb_cache, m); 1335 splx(s); 1336 } 1337 1338 1339 /* 1340 * Initialize a standard receive ring descriptor. 1341 */ 1342 static int 1343 bge_newbuf_std(struct bge_softc *sc, int i, struct mbuf *m, 1344 bus_dmamap_t dmamap) 1345 { 1346 struct mbuf *m_new = NULL; 1347 struct bge_rx_bd *r; 1348 int error; 1349 1350 if (dmamap == NULL) { 1351 error = bus_dmamap_create(sc->bge_dmatag, MCLBYTES, 1, 1352 MCLBYTES, 0, BUS_DMA_NOWAIT, &dmamap); 1353 if (error != 0) 1354 return error; 1355 } 1356 1357 sc->bge_cdata.bge_rx_std_map[i] = dmamap; 1358 1359 if (m == NULL) { 1360 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1361 if (m_new == NULL) 1362 return ENOBUFS; 1363 1364 MCLGET(m_new, M_DONTWAIT); 1365 if (!(m_new->m_flags & M_EXT)) { 1366 m_freem(m_new); 1367 return ENOBUFS; 1368 } 1369 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1370 1371 } else { 1372 m_new = m; 1373 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1374 m_new->m_data = m_new->m_ext.ext_buf; 1375 } 1376 if (!(sc->bge_flags & BGE_RX_ALIGNBUG)) 1377 m_adj(m_new, ETHER_ALIGN); 1378 if (bus_dmamap_load_mbuf(sc->bge_dmatag, dmamap, m_new, 1379 BUS_DMA_READ|BUS_DMA_NOWAIT)) 1380 return ENOBUFS; 1381 bus_dmamap_sync(sc->bge_dmatag, dmamap, 0, dmamap->dm_mapsize, 1382 BUS_DMASYNC_PREREAD); 1383 1384 sc->bge_cdata.bge_rx_std_chain[i] = m_new; 1385 r = &sc->bge_rdata->bge_rx_std_ring[i]; 1386 BGE_HOSTADDR(r->bge_addr, dmamap->dm_segs[0].ds_addr); 1387 r->bge_flags = BGE_RXBDFLAG_END; 1388 r->bge_len = m_new->m_len; 1389 r->bge_idx = i; 1390 1391 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 1392 offsetof(struct bge_ring_data, bge_rx_std_ring) + 1393 i * sizeof (struct bge_rx_bd), 1394 sizeof (struct bge_rx_bd), 1395 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1396 1397 return 0; 1398 } 1399 1400 /* 1401 * Initialize a jumbo receive ring descriptor. This allocates 1402 * a jumbo buffer from the pool managed internally by the driver. 1403 */ 1404 static int 1405 bge_newbuf_jumbo(struct bge_softc *sc, int i, struct mbuf *m) 1406 { 1407 struct mbuf *m_new = NULL; 1408 struct bge_rx_bd *r; 1409 void *buf = NULL; 1410 1411 if (m == NULL) { 1412 1413 /* Allocate the mbuf. */ 1414 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1415 if (m_new == NULL) 1416 return ENOBUFS; 1417 1418 /* Allocate the jumbo buffer */ 1419 buf = bge_jalloc(sc); 1420 if (buf == NULL) { 1421 m_freem(m_new); 1422 aprint_error_dev(sc->bge_dev, 1423 "jumbo allocation failed -- packet dropped!\n"); 1424 return ENOBUFS; 1425 } 1426 1427 /* Attach the buffer to the mbuf. */ 1428 m_new->m_len = m_new->m_pkthdr.len = BGE_JUMBO_FRAMELEN; 1429 MEXTADD(m_new, buf, BGE_JUMBO_FRAMELEN, M_DEVBUF, 1430 bge_jfree, sc); 1431 m_new->m_flags |= M_EXT_RW; 1432 } else { 1433 m_new = m; 1434 buf = m_new->m_data = m_new->m_ext.ext_buf; 1435 m_new->m_ext.ext_size = BGE_JUMBO_FRAMELEN; 1436 } 1437 if (!(sc->bge_flags & BGE_RX_ALIGNBUG)) 1438 m_adj(m_new, ETHER_ALIGN); 1439 bus_dmamap_sync(sc->bge_dmatag, sc->bge_cdata.bge_rx_jumbo_map, 1440 mtod(m_new, char *) - (char *)sc->bge_cdata.bge_jumbo_buf, BGE_JLEN, 1441 BUS_DMASYNC_PREREAD); 1442 /* Set up the descriptor. */ 1443 r = &sc->bge_rdata->bge_rx_jumbo_ring[i]; 1444 sc->bge_cdata.bge_rx_jumbo_chain[i] = m_new; 1445 BGE_HOSTADDR(r->bge_addr, BGE_JUMBO_DMA_ADDR(sc, m_new)); 1446 r->bge_flags = BGE_RXBDFLAG_END|BGE_RXBDFLAG_JUMBO_RING; 1447 r->bge_len = m_new->m_len; 1448 r->bge_idx = i; 1449 1450 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 1451 offsetof(struct bge_ring_data, bge_rx_jumbo_ring) + 1452 i * sizeof (struct bge_rx_bd), 1453 sizeof (struct bge_rx_bd), 1454 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1455 1456 return 0; 1457 } 1458 1459 /* 1460 * The standard receive ring has 512 entries in it. At 2K per mbuf cluster, 1461 * that's 1MB or memory, which is a lot. For now, we fill only the first 1462 * 256 ring entries and hope that our CPU is fast enough to keep up with 1463 * the NIC. 1464 */ 1465 static int 1466 bge_init_rx_ring_std(struct bge_softc *sc) 1467 { 1468 int i; 1469 1470 if (sc->bge_flags & BGE_RXRING_VALID) 1471 return 0; 1472 1473 for (i = 0; i < BGE_SSLOTS; i++) { 1474 if (bge_newbuf_std(sc, i, NULL, 0) == ENOBUFS) 1475 return ENOBUFS; 1476 } 1477 1478 sc->bge_std = i - 1; 1479 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std); 1480 1481 sc->bge_flags |= BGE_RXRING_VALID; 1482 1483 return 0; 1484 } 1485 1486 static void 1487 bge_free_rx_ring_std(struct bge_softc *sc) 1488 { 1489 int i; 1490 1491 if (!(sc->bge_flags & BGE_RXRING_VALID)) 1492 return; 1493 1494 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { 1495 if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) { 1496 m_freem(sc->bge_cdata.bge_rx_std_chain[i]); 1497 sc->bge_cdata.bge_rx_std_chain[i] = NULL; 1498 bus_dmamap_destroy(sc->bge_dmatag, 1499 sc->bge_cdata.bge_rx_std_map[i]); 1500 } 1501 memset((char *)&sc->bge_rdata->bge_rx_std_ring[i], 0, 1502 sizeof(struct bge_rx_bd)); 1503 } 1504 1505 sc->bge_flags &= ~BGE_RXRING_VALID; 1506 } 1507 1508 static int 1509 bge_init_rx_ring_jumbo(struct bge_softc *sc) 1510 { 1511 int i; 1512 volatile struct bge_rcb *rcb; 1513 1514 if (sc->bge_flags & BGE_JUMBO_RXRING_VALID) 1515 return 0; 1516 1517 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 1518 if (bge_newbuf_jumbo(sc, i, NULL) == ENOBUFS) 1519 return ENOBUFS; 1520 } 1521 1522 sc->bge_jumbo = i - 1; 1523 sc->bge_flags |= BGE_JUMBO_RXRING_VALID; 1524 1525 rcb = &sc->bge_rdata->bge_info.bge_jumbo_rx_rcb; 1526 rcb->bge_maxlen_flags = 0; 1527 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 1528 1529 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo); 1530 1531 return 0; 1532 } 1533 1534 static void 1535 bge_free_rx_ring_jumbo(struct bge_softc *sc) 1536 { 1537 int i; 1538 1539 if (!(sc->bge_flags & BGE_JUMBO_RXRING_VALID)) 1540 return; 1541 1542 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 1543 if (sc->bge_cdata.bge_rx_jumbo_chain[i] != NULL) { 1544 m_freem(sc->bge_cdata.bge_rx_jumbo_chain[i]); 1545 sc->bge_cdata.bge_rx_jumbo_chain[i] = NULL; 1546 } 1547 memset((char *)&sc->bge_rdata->bge_rx_jumbo_ring[i], 0, 1548 sizeof(struct bge_rx_bd)); 1549 } 1550 1551 sc->bge_flags &= ~BGE_JUMBO_RXRING_VALID; 1552 } 1553 1554 static void 1555 bge_free_tx_ring(struct bge_softc *sc) 1556 { 1557 int i; 1558 struct txdmamap_pool_entry *dma; 1559 1560 if (!(sc->bge_flags & BGE_TXRING_VALID)) 1561 return; 1562 1563 for (i = 0; i < BGE_TX_RING_CNT; i++) { 1564 if (sc->bge_cdata.bge_tx_chain[i] != NULL) { 1565 m_freem(sc->bge_cdata.bge_tx_chain[i]); 1566 sc->bge_cdata.bge_tx_chain[i] = NULL; 1567 SLIST_INSERT_HEAD(&sc->txdma_list, sc->txdma[i], 1568 link); 1569 sc->txdma[i] = 0; 1570 } 1571 memset((char *)&sc->bge_rdata->bge_tx_ring[i], 0, 1572 sizeof(struct bge_tx_bd)); 1573 } 1574 1575 while ((dma = SLIST_FIRST(&sc->txdma_list))) { 1576 SLIST_REMOVE_HEAD(&sc->txdma_list, link); 1577 bus_dmamap_destroy(sc->bge_dmatag, dma->dmamap); 1578 free(dma, M_DEVBUF); 1579 } 1580 1581 sc->bge_flags &= ~BGE_TXRING_VALID; 1582 } 1583 1584 static int 1585 bge_init_tx_ring(struct bge_softc *sc) 1586 { 1587 int i; 1588 bus_dmamap_t dmamap; 1589 struct txdmamap_pool_entry *dma; 1590 1591 if (sc->bge_flags & BGE_TXRING_VALID) 1592 return 0; 1593 1594 sc->bge_txcnt = 0; 1595 sc->bge_tx_saved_considx = 0; 1596 1597 /* Initialize transmit producer index for host-memory send ring. */ 1598 sc->bge_tx_prodidx = 0; 1599 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx); 1600 /* 5700 b2 errata */ 1601 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX) 1602 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx); 1603 1604 /* NIC-memory send ring not used; initialize to zero. */ 1605 bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0); 1606 /* 5700 b2 errata */ 1607 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX) 1608 bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0); 1609 1610 SLIST_INIT(&sc->txdma_list); 1611 for (i = 0; i < BGE_RSLOTS; i++) { 1612 if (bus_dmamap_create(sc->bge_dmatag, BGE_TXDMA_MAX, 1613 BGE_NTXSEG, ETHER_MAX_LEN_JUMBO, 0, BUS_DMA_NOWAIT, 1614 &dmamap)) 1615 return ENOBUFS; 1616 if (dmamap == NULL) 1617 panic("dmamap NULL in bge_init_tx_ring"); 1618 dma = malloc(sizeof(*dma), M_DEVBUF, M_NOWAIT); 1619 if (dma == NULL) { 1620 aprint_error_dev(sc->bge_dev, 1621 "can't alloc txdmamap_pool_entry\n"); 1622 bus_dmamap_destroy(sc->bge_dmatag, dmamap); 1623 return ENOMEM; 1624 } 1625 dma->dmamap = dmamap; 1626 SLIST_INSERT_HEAD(&sc->txdma_list, dma, link); 1627 } 1628 1629 sc->bge_flags |= BGE_TXRING_VALID; 1630 1631 return 0; 1632 } 1633 1634 static void 1635 bge_setmulti(struct bge_softc *sc) 1636 { 1637 struct ethercom *ac = &sc->ethercom; 1638 struct ifnet *ifp = &ac->ec_if; 1639 struct ether_multi *enm; 1640 struct ether_multistep step; 1641 uint32_t hashes[4] = { 0, 0, 0, 0 }; 1642 uint32_t h; 1643 int i; 1644 1645 if (ifp->if_flags & IFF_PROMISC) 1646 goto allmulti; 1647 1648 /* Now program new ones. */ 1649 ETHER_FIRST_MULTI(step, ac, enm); 1650 while (enm != NULL) { 1651 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1652 /* 1653 * We must listen to a range of multicast addresses. 1654 * For now, just accept all multicasts, rather than 1655 * trying to set only those filter bits needed to match 1656 * the range. (At this time, the only use of address 1657 * ranges is for IP multicast routing, for which the 1658 * range is big enough to require all bits set.) 1659 */ 1660 goto allmulti; 1661 } 1662 1663 h = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN); 1664 1665 /* Just want the 7 least-significant bits. */ 1666 h &= 0x7f; 1667 1668 hashes[(h & 0x60) >> 5] |= 1 << (h & 0x1F); 1669 ETHER_NEXT_MULTI(step, enm); 1670 } 1671 1672 ifp->if_flags &= ~IFF_ALLMULTI; 1673 goto setit; 1674 1675 allmulti: 1676 ifp->if_flags |= IFF_ALLMULTI; 1677 hashes[0] = hashes[1] = hashes[2] = hashes[3] = 0xffffffff; 1678 1679 setit: 1680 for (i = 0; i < 4; i++) 1681 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]); 1682 } 1683 1684 static void 1685 bge_sig_pre_reset(struct bge_softc *sc, int type) 1686 { 1687 1688 /* 1689 * Some chips don't like this so only do this if ASF is enabled 1690 */ 1691 if (sc->bge_asf_mode) 1692 bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM, BGE_MAGIC_NUMBER); 1693 1694 if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) { 1695 switch (type) { 1696 case BGE_RESET_START: 1697 bge_writemem_ind(sc, BGE_SDI_STATUS, 0x1); /* START */ 1698 break; 1699 case BGE_RESET_STOP: 1700 bge_writemem_ind(sc, BGE_SDI_STATUS, 0x2); /* UNLOAD */ 1701 break; 1702 } 1703 } 1704 } 1705 1706 static void 1707 bge_sig_post_reset(struct bge_softc *sc, int type) 1708 { 1709 1710 if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) { 1711 switch (type) { 1712 case BGE_RESET_START: 1713 bge_writemem_ind(sc, BGE_SDI_STATUS, 0x80000001); 1714 /* START DONE */ 1715 break; 1716 case BGE_RESET_STOP: 1717 bge_writemem_ind(sc, BGE_SDI_STATUS, 0x80000002); 1718 break; 1719 } 1720 } 1721 } 1722 1723 static void 1724 bge_sig_legacy(struct bge_softc *sc, int type) 1725 { 1726 1727 if (sc->bge_asf_mode) { 1728 switch (type) { 1729 case BGE_RESET_START: 1730 bge_writemem_ind(sc, BGE_SDI_STATUS, 0x1); /* START */ 1731 break; 1732 case BGE_RESET_STOP: 1733 bge_writemem_ind(sc, BGE_SDI_STATUS, 0x2); /* UNLOAD */ 1734 break; 1735 } 1736 } 1737 } 1738 1739 static void 1740 bge_stop_fw(struct bge_softc *sc) 1741 { 1742 int i; 1743 1744 if (sc->bge_asf_mode) { 1745 bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM_FW, BGE_FW_PAUSE); 1746 CSR_WRITE_4_FLUSH(sc, BGE_CPU_EVENT, 1747 CSR_READ_4(sc, BGE_CPU_EVENT) | (1 << 14)); 1748 1749 for (i = 0; i < 100; i++) { 1750 if (!(CSR_READ_4(sc, BGE_CPU_EVENT) & (1 << 14))) 1751 break; 1752 DELAY(10); 1753 } 1754 } 1755 } 1756 1757 static int 1758 bge_poll_fw(struct bge_softc *sc) 1759 { 1760 uint32_t val; 1761 int i; 1762 1763 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 1764 for (i = 0; i < BGE_TIMEOUT; i++) { 1765 val = CSR_READ_4(sc, BGE_VCPU_STATUS); 1766 if (val & BGE_VCPU_STATUS_INIT_DONE) 1767 break; 1768 DELAY(100); 1769 } 1770 if (i >= BGE_TIMEOUT) { 1771 aprint_error_dev(sc->bge_dev, "reset timed out\n"); 1772 return -1; 1773 } 1774 } else if ((sc->bge_flags & BGE_NO_EEPROM) == 0) { 1775 /* 1776 * Poll the value location we just wrote until 1777 * we see the 1's complement of the magic number. 1778 * This indicates that the firmware initialization 1779 * is complete. 1780 * XXX 1000ms for Flash and 10000ms for SEEPROM. 1781 */ 1782 for (i = 0; i < BGE_TIMEOUT; i++) { 1783 val = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM); 1784 if (val == ~BGE_MAGIC_NUMBER) 1785 break; 1786 DELAY(10); 1787 } 1788 1789 if (i >= BGE_TIMEOUT) { 1790 aprint_error_dev(sc->bge_dev, 1791 "firmware handshake timed out, val = %x\n", val); 1792 return -1; 1793 } 1794 } 1795 1796 return 0; 1797 } 1798 1799 /* 1800 * Do endian, PCI and DMA initialization. Also check the on-board ROM 1801 * self-test results. 1802 */ 1803 static int 1804 bge_chipinit(struct bge_softc *sc) 1805 { 1806 int i; 1807 uint32_t dma_rw_ctl; 1808 1809 /* Set endianness before we access any non-PCI registers. */ 1810 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MISC_CTL, 1811 BGE_INIT); 1812 1813 /* Set power state to D0. */ 1814 bge_setpowerstate(sc, 0); 1815 1816 /* Clear the MAC control register */ 1817 CSR_WRITE_4(sc, BGE_MAC_MODE, 0); 1818 1819 /* 1820 * Clear the MAC statistics block in the NIC's 1821 * internal memory. 1822 */ 1823 for (i = BGE_STATS_BLOCK; 1824 i < BGE_STATS_BLOCK_END + 1; i += sizeof(uint32_t)) 1825 BGE_MEMWIN_WRITE(sc->sc_pc, sc->sc_pcitag, i, 0); 1826 1827 for (i = BGE_STATUS_BLOCK; 1828 i < BGE_STATUS_BLOCK_END + 1; i += sizeof(uint32_t)) 1829 BGE_MEMWIN_WRITE(sc->sc_pc, sc->sc_pcitag, i, 0); 1830 1831 /* Set up the PCI DMA control register. */ 1832 dma_rw_ctl = BGE_PCI_READ_CMD | BGE_PCI_WRITE_CMD; 1833 if (sc->bge_flags & BGE_PCIE) { 1834 /* Read watermark not used, 128 bytes for write. */ 1835 DPRINTFN(4, ("(%s: PCI-Express DMA setting)\n", 1836 device_xname(sc->bge_dev))); 1837 dma_rw_ctl |= BGE_PCIDMARWCTL_WR_WAT_SHIFT(3); 1838 } else if (sc->bge_flags & BGE_PCIX) { 1839 DPRINTFN(4, ("(:%s: PCI-X DMA setting)\n", 1840 device_xname(sc->bge_dev))); 1841 /* PCI-X bus */ 1842 if (BGE_IS_5714_FAMILY(sc)) { 1843 /* 256 bytes for read and write. */ 1844 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(2) | 1845 BGE_PCIDMARWCTL_WR_WAT_SHIFT(2); 1846 1847 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5780) 1848 dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL; 1849 else 1850 dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE_LOCAL; 1851 } else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) { 1852 /* 1536 bytes for read, 384 bytes for write. */ 1853 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(7) | 1854 BGE_PCIDMARWCTL_WR_WAT_SHIFT(3); 1855 } else { 1856 /* 384 bytes for read and write. */ 1857 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(3) | 1858 BGE_PCIDMARWCTL_WR_WAT_SHIFT(3) | 1859 (0x0F); 1860 } 1861 1862 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5703 || 1863 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) { 1864 uint32_t tmp; 1865 1866 /* Set ONEDMA_ATONCE for hardware workaround. */ 1867 tmp = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 1868 BGE_PCI_CLKCTL) & 0x1f; 1869 if (tmp == 6 || tmp == 7) 1870 dma_rw_ctl |= 1871 BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL; 1872 1873 /* Set PCI-X DMA write workaround. */ 1874 dma_rw_ctl |= BGE_PCIDMARWCTL_ASRT_ALL_BE; 1875 } 1876 } else { 1877 /* Conventional PCI bus: 256 bytes for read and write. */ 1878 DPRINTFN(4, ("(%s: PCI 2.2 DMA setting)\n", 1879 device_xname(sc->bge_dev))); 1880 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(7) | 1881 BGE_PCIDMARWCTL_WR_WAT_SHIFT(7); 1882 1883 if (BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5705 && 1884 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5750) 1885 dma_rw_ctl |= 0x0F; 1886 } 1887 1888 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 1889 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5701) 1890 dma_rw_ctl |= BGE_PCIDMARWCTL_USE_MRM | 1891 BGE_PCIDMARWCTL_ASRT_ALL_BE; 1892 1893 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5703 || 1894 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) 1895 dma_rw_ctl &= ~BGE_PCIDMARWCTL_MINDMA; 1896 1897 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_DMA_RW_CTL, 1898 dma_rw_ctl); 1899 1900 /* 1901 * Set up general mode register. 1902 */ 1903 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS | 1904 BGE_MODECTL_MAC_ATTN_INTR | BGE_MODECTL_HOST_SEND_BDS | 1905 BGE_MODECTL_TX_NO_PHDR_CSUM); 1906 1907 /* 1908 * BCM5701 B5 have a bug causing data corruption when using 1909 * 64-bit DMA reads, which can be terminated early and then 1910 * completed later as 32-bit accesses, in combination with 1911 * certain bridges. 1912 */ 1913 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5701 && 1914 sc->bge_chipid == BGE_CHIPID_BCM5701_B5) 1915 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_FORCE_PCI32); 1916 1917 /* 1918 * Tell the firmware the driver is running 1919 */ 1920 if (sc->bge_asf_mode & ASF_STACKUP) 1921 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 1922 1923 /* 1924 * Disable memory write invalidate. Apparently it is not supported 1925 * properly by these devices. 1926 */ 1927 PCI_CLRBIT(sc->sc_pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG, 1928 PCI_COMMAND_INVALIDATE_ENABLE); 1929 1930 #ifdef __brokenalpha__ 1931 /* 1932 * Must insure that we do not cross an 8K (bytes) boundary 1933 * for DMA reads. Our highest limit is 1K bytes. This is a 1934 * restriction on some ALPHA platforms with early revision 1935 * 21174 PCI chipsets, such as the AlphaPC 164lx 1936 */ 1937 PCI_SETBIT(sc, BGE_PCI_DMA_RW_CTL, BGE_PCI_READ_BNDRY_1024, 4); 1938 #endif 1939 1940 /* Set the timer prescaler (always 66MHz) */ 1941 CSR_WRITE_4(sc, BGE_MISC_CFG, 65 << 1/*BGE_32BITTIME_66MHZ*/); 1942 1943 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 1944 DELAY(40); /* XXX */ 1945 1946 /* Put PHY into ready state */ 1947 BGE_CLRBIT_FLUSH(sc, BGE_MISC_CFG, BGE_MISCCFG_EPHY_IDDQ); 1948 DELAY(40); 1949 } 1950 1951 return 0; 1952 } 1953 1954 static int 1955 bge_blockinit(struct bge_softc *sc) 1956 { 1957 volatile struct bge_rcb *rcb; 1958 bus_size_t rcb_addr; 1959 int i; 1960 struct ifnet *ifp = &sc->ethercom.ec_if; 1961 bge_hostaddr taddr; 1962 uint32_t val; 1963 1964 /* 1965 * Initialize the memory window pointer register so that 1966 * we can access the first 32K of internal NIC RAM. This will 1967 * allow us to set up the TX send ring RCBs and the RX return 1968 * ring RCBs, plus other things which live in NIC memory. 1969 */ 1970 1971 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_BASEADDR, 0); 1972 1973 /* Step 33: Configure mbuf memory pool */ 1974 if (BGE_IS_5700_FAMILY(sc)) { 1975 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, 1976 BGE_BUFFPOOL_1); 1977 1978 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) 1979 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000); 1980 else 1981 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000); 1982 1983 /* Configure DMA resource pool */ 1984 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_BASEADDR, 1985 BGE_DMA_DESCRIPTORS); 1986 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LEN, 0x2000); 1987 } 1988 1989 /* Step 35: Configure mbuf pool watermarks */ 1990 #ifdef ORIG_WPAUL_VALUES 1991 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 24); 1992 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 24); 1993 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 48); 1994 #else 1995 1996 /* new broadcom docs strongly recommend these: */ 1997 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5717 || 1998 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57765 || 1999 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57766) { 2000 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0); 2001 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x2a); 2002 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0xa0); 2003 } else if (BGE_IS_5705_PLUS(sc)) { 2004 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0); 2005 2006 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 2007 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x04); 2008 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x10); 2009 } else { 2010 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x10); 2011 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60); 2012 } 2013 } else if (!BGE_IS_5705_PLUS(sc)) { 2014 if (ifp->if_mtu > ETHER_MAX_LEN) { 2015 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x50); 2016 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x20); 2017 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60); 2018 } else { 2019 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 304); 2020 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 152); 2021 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 380); 2022 } 2023 } else { 2024 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0); 2025 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x10); 2026 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60); 2027 } 2028 #endif 2029 2030 /* Step 36: Configure DMA resource watermarks */ 2031 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5); 2032 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10); 2033 2034 /* Step 38: Enable buffer manager */ 2035 CSR_WRITE_4(sc, BGE_BMAN_MODE, 2036 BGE_BMANMODE_ENABLE | BGE_BMANMODE_LOMBUF_ATTN); 2037 2038 /* Step 39: Poll for buffer manager start indication */ 2039 for (i = 0; i < BGE_TIMEOUT * 2; i++) { 2040 if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE) 2041 break; 2042 DELAY(10); 2043 } 2044 2045 if (i == BGE_TIMEOUT * 2) { 2046 aprint_error_dev(sc->bge_dev, 2047 "buffer manager failed to start\n"); 2048 return ENXIO; 2049 } 2050 2051 /* Step 40: Enable flow-through queues */ 2052 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 2053 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 2054 2055 /* Wait until queue initialization is complete */ 2056 for (i = 0; i < BGE_TIMEOUT * 2; i++) { 2057 if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0) 2058 break; 2059 DELAY(10); 2060 } 2061 2062 if (i == BGE_TIMEOUT * 2) { 2063 aprint_error_dev(sc->bge_dev, 2064 "flow-through queue init failed\n"); 2065 return ENXIO; 2066 } 2067 2068 /* Step 41: Initialize the standard RX ring control block */ 2069 rcb = &sc->bge_rdata->bge_info.bge_std_rx_rcb; 2070 BGE_HOSTADDR(rcb->bge_hostaddr, BGE_RING_DMA_ADDR(sc, bge_rx_std_ring)); 2071 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5717 || 2072 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57765 || 2073 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57766) 2074 rcb->bge_maxlen_flags = 2075 BGE_RCB_MAXLEN_FLAGS(512, BGE_MAX_FRAMELEN << 2); 2076 else if (BGE_IS_5705_PLUS(sc)) 2077 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(512, 0); 2078 else 2079 rcb->bge_maxlen_flags = 2080 BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 0); 2081 rcb->bge_nicaddr = BGE_STD_RX_RINGS; 2082 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcb->bge_hostaddr.bge_addr_hi); 2083 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcb->bge_hostaddr.bge_addr_lo); 2084 CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 2085 CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcb->bge_nicaddr); 2086 2087 /* 2088 * Step 42: Initialize the jumbo RX ring control block 2089 * We set the 'ring disabled' bit in the flags 2090 * field until we're actually ready to start 2091 * using this ring (i.e. once we set the MTU 2092 * high enough to require it). 2093 */ 2094 if (BGE_IS_JUMBO_CAPABLE(sc)) { 2095 rcb = &sc->bge_rdata->bge_info.bge_jumbo_rx_rcb; 2096 BGE_HOSTADDR(rcb->bge_hostaddr, 2097 BGE_RING_DMA_ADDR(sc, bge_rx_jumbo_ring)); 2098 rcb->bge_maxlen_flags = 2099 BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 2100 BGE_RCB_FLAG_RING_DISABLED); 2101 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS; 2102 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI, 2103 rcb->bge_hostaddr.bge_addr_hi); 2104 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO, 2105 rcb->bge_hostaddr.bge_addr_lo); 2106 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, 2107 rcb->bge_maxlen_flags); 2108 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcb->bge_nicaddr); 2109 2110 /* Set up dummy disabled mini ring RCB */ 2111 rcb = &sc->bge_rdata->bge_info.bge_mini_rx_rcb; 2112 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0, 2113 BGE_RCB_FLAG_RING_DISABLED); 2114 CSR_WRITE_4(sc, BGE_RX_MINI_RCB_MAXLEN_FLAGS, 2115 rcb->bge_maxlen_flags); 2116 2117 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 2118 offsetof(struct bge_ring_data, bge_info), 2119 sizeof (struct bge_gib), 2120 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2121 } 2122 2123 /* Choose de-pipeline mode for BCM5906 A0, A1 and A2. */ 2124 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 2125 if (sc->bge_chipid == BGE_CHIPID_BCM5906_A0 || 2126 sc->bge_chipid == BGE_CHIPID_BCM5906_A1 || 2127 sc->bge_chipid == BGE_CHIPID_BCM5906_A2) 2128 CSR_WRITE_4(sc, BGE_ISO_PKT_TX, 2129 (CSR_READ_4(sc, BGE_ISO_PKT_TX) & ~3) | 2); 2130 } 2131 /* 2132 * Set the BD ring replenish thresholds. The recommended 2133 * values are 1/8th the number of descriptors allocated to 2134 * each ring. 2135 */ 2136 i = BGE_STD_RX_RING_CNT / 8; 2137 2138 /* 2139 * Use a value of 8 for the following chips to workaround HW errata. 2140 * Some of these chips have been added based on empirical 2141 * evidence (they don't work unless this is done). 2142 */ 2143 if (BGE_IS_5705_PLUS(sc)) 2144 i = 8; 2145 2146 CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, i); 2147 CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH, BGE_JUMBO_RX_RING_CNT / 8); 2148 2149 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5717 || 2150 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57765 || 2151 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57766) { 2152 CSR_WRITE_4(sc, BGE_STD_REPL_LWM, 4); 2153 CSR_WRITE_4(sc, BGE_JUMBO_REPL_LWM, 4); 2154 } 2155 2156 /* 2157 * Disable all unused send rings by setting the 'ring disabled' 2158 * bit in the flags field of all the TX send ring control blocks. 2159 * These are located in NIC memory. 2160 */ 2161 rcb_addr = BGE_MEMWIN_START + BGE_SEND_RING_RCB; 2162 for (i = 0; i < BGE_TX_RINGS_EXTSSRAM_MAX; i++) { 2163 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 2164 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED)); 2165 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 0); 2166 rcb_addr += sizeof(struct bge_rcb); 2167 } 2168 2169 /* Configure TX RCB 0 (we use only the first ring) */ 2170 rcb_addr = BGE_MEMWIN_START + BGE_SEND_RING_RCB; 2171 BGE_HOSTADDR(taddr, BGE_RING_DMA_ADDR(sc, bge_tx_ring)); 2172 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi); 2173 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo); 2174 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 2175 BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT)); 2176 if (BGE_IS_5700_FAMILY(sc)) 2177 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 2178 BGE_RCB_MAXLEN_FLAGS(BGE_TX_RING_CNT, 0)); 2179 2180 /* Disable all unused RX return rings */ 2181 rcb_addr = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB; 2182 for (i = 0; i < BGE_RX_RINGS_MAX; i++) { 2183 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_hi, 0); 2184 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_lo, 0); 2185 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 2186 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 2187 BGE_RCB_FLAG_RING_DISABLED)); 2188 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 0); 2189 bge_writembx(sc, BGE_MBX_RX_CONS0_LO + 2190 (i * (sizeof(uint64_t))), 0); 2191 rcb_addr += sizeof(struct bge_rcb); 2192 } 2193 2194 /* Initialize RX ring indexes */ 2195 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, 0); 2196 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0); 2197 bge_writembx(sc, BGE_MBX_RX_MINI_PROD_LO, 0); 2198 2199 /* 2200 * Set up RX return ring 0 2201 * Note that the NIC address for RX return rings is 0x00000000. 2202 * The return rings live entirely within the host, so the 2203 * nicaddr field in the RCB isn't used. 2204 */ 2205 rcb_addr = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB; 2206 BGE_HOSTADDR(taddr, BGE_RING_DMA_ADDR(sc, bge_rx_return_ring)); 2207 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi); 2208 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo); 2209 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 0x00000000); 2210 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 2211 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 0)); 2212 2213 /* Set random backoff seed for TX */ 2214 CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF, 2215 CLLADDR(ifp->if_sadl)[0] + CLLADDR(ifp->if_sadl)[1] + 2216 CLLADDR(ifp->if_sadl)[2] + CLLADDR(ifp->if_sadl)[3] + 2217 CLLADDR(ifp->if_sadl)[4] + CLLADDR(ifp->if_sadl)[5] + 2218 BGE_TX_BACKOFF_SEED_MASK); 2219 2220 /* Set inter-packet gap */ 2221 CSR_WRITE_4(sc, BGE_TX_LENGTHS, 0x2620); 2222 2223 /* 2224 * Specify which ring to use for packets that don't match 2225 * any RX rules. 2226 */ 2227 CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08); 2228 2229 /* 2230 * Configure number of RX lists. One interrupt distribution 2231 * list, sixteen active lists, one bad frames class. 2232 */ 2233 CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181); 2234 2235 /* Inialize RX list placement stats mask. */ 2236 CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF); 2237 CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1); 2238 2239 /* Disable host coalescing until we get it set up */ 2240 CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000); 2241 2242 /* Poll to make sure it's shut down. */ 2243 for (i = 0; i < BGE_TIMEOUT * 2; i++) { 2244 if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE)) 2245 break; 2246 DELAY(10); 2247 } 2248 2249 if (i == BGE_TIMEOUT * 2) { 2250 aprint_error_dev(sc->bge_dev, 2251 "host coalescing engine failed to idle\n"); 2252 return ENXIO; 2253 } 2254 2255 /* Set up host coalescing defaults */ 2256 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bge_rx_coal_ticks); 2257 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bge_tx_coal_ticks); 2258 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bge_rx_max_coal_bds); 2259 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bge_tx_max_coal_bds); 2260 if (BGE_IS_5700_FAMILY(sc)) { 2261 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT, 0); 2262 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT, 0); 2263 } 2264 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 0); 2265 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 0); 2266 2267 /* Set up address of statistics block */ 2268 if (BGE_IS_5700_FAMILY(sc)) { 2269 BGE_HOSTADDR(taddr, BGE_RING_DMA_ADDR(sc, bge_info.bge_stats)); 2270 CSR_WRITE_4(sc, BGE_HCC_STATS_TICKS, sc->bge_stat_ticks); 2271 CSR_WRITE_4(sc, BGE_HCC_STATS_BASEADDR, BGE_STATS_BLOCK); 2272 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_HI, taddr.bge_addr_hi); 2273 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_LO, taddr.bge_addr_lo); 2274 } 2275 2276 /* Set up address of status block */ 2277 BGE_HOSTADDR(taddr, BGE_RING_DMA_ADDR(sc, bge_status_block)); 2278 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_BASEADDR, BGE_STATUS_BLOCK); 2279 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI, taddr.bge_addr_hi); 2280 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO, taddr.bge_addr_lo); 2281 sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx = 0; 2282 sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx = 0; 2283 2284 /* Turn on host coalescing state machine */ 2285 CSR_WRITE_4(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE); 2286 2287 /* Turn on RX BD completion state machine and enable attentions */ 2288 CSR_WRITE_4(sc, BGE_RBDC_MODE, 2289 BGE_RBDCMODE_ENABLE | BGE_RBDCMODE_ATTN); 2290 2291 /* Turn on RX list placement state machine */ 2292 CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 2293 2294 /* Turn on RX list selector state machine. */ 2295 if (BGE_IS_5700_FAMILY(sc)) 2296 CSR_WRITE_4(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 2297 2298 val = BGE_MACMODE_TXDMA_ENB | BGE_MACMODE_RXDMA_ENB | 2299 BGE_MACMODE_RX_STATS_CLEAR | BGE_MACMODE_TX_STATS_CLEAR | 2300 BGE_MACMODE_RX_STATS_ENB | BGE_MACMODE_TX_STATS_ENB | 2301 BGE_MACMODE_FRMHDR_DMA_ENB; 2302 2303 if (sc->bge_flags & BGE_PHY_FIBER_TBI) 2304 val |= BGE_PORTMODE_TBI; 2305 else if (sc->bge_flags & BGE_PHY_FIBER_MII) 2306 val |= BGE_PORTMODE_GMII; 2307 else 2308 val |= BGE_PORTMODE_MII; 2309 2310 /* Turn on DMA, clear stats */ 2311 CSR_WRITE_4_FLUSH(sc, BGE_MAC_MODE, val); 2312 DELAY(40); 2313 2314 /* Set misc. local control, enable interrupts on attentions */ 2315 sc->bge_local_ctrl_reg = BGE_MLC_INTR_ONATTN | BGE_MLC_AUTO_EEPROM; 2316 2317 #ifdef notdef 2318 /* Assert GPIO pins for PHY reset */ 2319 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUT0| 2320 BGE_MLC_MISCIO_OUT1|BGE_MLC_MISCIO_OUT2); 2321 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUTEN0| 2322 BGE_MLC_MISCIO_OUTEN1|BGE_MLC_MISCIO_OUTEN2); 2323 #endif 2324 2325 #if defined(not_quite_yet) 2326 /* Linux driver enables enable gpio pin #1 on 5700s */ 2327 if (sc->bge_chipid == BGE_CHIPID_BCM5700) { 2328 sc->bge_local_ctrl_reg |= 2329 (BGE_MLC_MISCIO_OUT1|BGE_MLC_MISCIO_OUTEN1); 2330 } 2331 #endif 2332 CSR_WRITE_4(sc, BGE_MISC_LOCAL_CTL, sc->bge_local_ctrl_reg); 2333 2334 /* Turn on DMA completion state machine */ 2335 if (BGE_IS_5700_FAMILY(sc)) 2336 CSR_WRITE_4(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 2337 2338 val = BGE_WDMAMODE_ENABLE | BGE_WDMAMODE_ALL_ATTNS; 2339 2340 /* Enable host coalescing bug fix */ 2341 if (BGE_IS_5755_PLUS(sc)) 2342 val |= BGE_WDMAMODE_STATUS_TAG_FIX; 2343 2344 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785) 2345 val |= BGE_WDMAMODE_BURST_ALL_DATA; 2346 2347 /* Turn on write DMA state machine */ 2348 CSR_WRITE_4_FLUSH(sc, BGE_WDMA_MODE, val); 2349 DELAY(40); 2350 2351 val = BGE_RDMAMODE_ENABLE | BGE_RDMAMODE_ALL_ATTNS; 2352 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5784 || 2353 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785 || 2354 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57780) 2355 val |= BGE_RDMAMODE_BD_SBD_CRPT_ATTN | 2356 BGE_RDMAMODE_MBUF_RBD_CRPT_ATTN | 2357 BGE_RDMAMODE_MBUF_SBD_CRPT_ATTN; 2358 2359 if (sc->bge_flags & BGE_PCIE) 2360 val |= BGE_RDMAMODE_FIFO_LONG_BURST; 2361 if (sc->bge_flags & BGE_TSO) 2362 val |= BGE_RDMAMODE_TSO4_ENABLE; 2363 2364 /* Turn on read DMA state machine */ 2365 CSR_WRITE_4_FLUSH(sc, BGE_RDMA_MODE, val); 2366 delay(40); 2367 2368 /* Turn on RX data completion state machine */ 2369 CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 2370 2371 /* Turn on RX BD initiator state machine */ 2372 CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 2373 2374 /* Turn on RX data and RX BD initiator state machine */ 2375 CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE); 2376 2377 /* Turn on Mbuf cluster free state machine */ 2378 if (BGE_IS_5700_FAMILY(sc)) 2379 CSR_WRITE_4(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 2380 2381 /* Turn on send BD completion state machine */ 2382 CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 2383 2384 /* Turn on send data completion state machine */ 2385 val = BGE_SDCMODE_ENABLE; 2386 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761) 2387 val |= BGE_SDCMODE_CDELAY; 2388 CSR_WRITE_4(sc, BGE_SDC_MODE, val); 2389 2390 /* Turn on send data initiator state machine */ 2391 if (sc->bge_flags & BGE_TSO) { 2392 /* XXX: magic value from Linux driver */ 2393 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE | 0x08); 2394 } else 2395 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 2396 2397 /* Turn on send BD initiator state machine */ 2398 CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 2399 2400 /* Turn on send BD selector state machine */ 2401 CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 2402 2403 CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF); 2404 CSR_WRITE_4(sc, BGE_SDI_STATS_CTL, 2405 BGE_SDISTATSCTL_ENABLE | BGE_SDISTATSCTL_FASTER); 2406 2407 /* ack/clear link change events */ 2408 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED | 2409 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE | 2410 BGE_MACSTAT_LINK_CHANGED); 2411 CSR_WRITE_4(sc, BGE_MI_STS, 0); 2412 2413 /* Enable PHY auto polling (for MII/GMII only) */ 2414 if (sc->bge_flags & BGE_PHY_FIBER_TBI) { 2415 CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK); 2416 } else { 2417 BGE_STS_SETBIT(sc, BGE_STS_AUTOPOLL); 2418 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL | (10 << 16)); 2419 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700) 2420 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, 2421 BGE_EVTENB_MI_INTERRUPT); 2422 } 2423 2424 /* 2425 * Clear any pending link state attention. 2426 * Otherwise some link state change events may be lost until attention 2427 * is cleared by bge_intr() -> bge_link_upd() sequence. 2428 * It's not necessary on newer BCM chips - perhaps enabling link 2429 * state change attentions implies clearing pending attention. 2430 */ 2431 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED | 2432 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE | 2433 BGE_MACSTAT_LINK_CHANGED); 2434 2435 /* Enable link state change attentions. */ 2436 BGE_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED); 2437 2438 return 0; 2439 } 2440 2441 static const struct bge_revision * 2442 bge_lookup_rev(uint32_t chipid) 2443 { 2444 const struct bge_revision *br; 2445 2446 for (br = bge_revisions; br->br_name != NULL; br++) { 2447 if (br->br_chipid == chipid) 2448 return br; 2449 } 2450 2451 for (br = bge_majorrevs; br->br_name != NULL; br++) { 2452 if (br->br_chipid == BGE_ASICREV(chipid)) 2453 return br; 2454 } 2455 2456 return NULL; 2457 } 2458 2459 static const struct bge_product * 2460 bge_lookup(const struct pci_attach_args *pa) 2461 { 2462 const struct bge_product *bp; 2463 2464 for (bp = bge_products; bp->bp_name != NULL; bp++) { 2465 if (PCI_VENDOR(pa->pa_id) == bp->bp_vendor && 2466 PCI_PRODUCT(pa->pa_id) == bp->bp_product) 2467 return bp; 2468 } 2469 2470 return NULL; 2471 } 2472 2473 static int 2474 bge_setpowerstate(struct bge_softc *sc, int powerlevel) 2475 { 2476 #ifdef NOTYET 2477 uint32_t pm_ctl = 0; 2478 2479 /* XXX FIXME: make sure indirect accesses enabled? */ 2480 pm_ctl = pci_conf_read(sc->bge_dev, BGE_PCI_MISC_CTL, 4); 2481 pm_ctl |= BGE_PCIMISCCTL_INDIRECT_ACCESS; 2482 pci_write_config(sc->bge_dev, BGE_PCI_MISC_CTL, pm_ctl, 4); 2483 2484 /* clear the PME_assert bit and power state bits, enable PME */ 2485 pm_ctl = pci_conf_read(sc->bge_dev, BGE_PCI_PWRMGMT_CMD, 2); 2486 pm_ctl &= ~PCIM_PSTAT_DMASK; 2487 pm_ctl |= (1 << 8); 2488 2489 if (powerlevel == 0) { 2490 pm_ctl |= PCIM_PSTAT_D0; 2491 pci_write_config(sc->bge_dev, BGE_PCI_PWRMGMT_CMD, 2492 pm_ctl, 2); 2493 DELAY(10000); 2494 CSR_WRITE_4(sc, BGE_MISC_LOCAL_CTL, sc->bge_local_ctrl_reg); 2495 DELAY(10000); 2496 2497 #ifdef NOTYET 2498 /* XXX FIXME: write 0x02 to phy aux_Ctrl reg */ 2499 bge_miibus_writereg(sc->bge_dev, 1, 0x18, 0x02); 2500 #endif 2501 DELAY(40); DELAY(40); DELAY(40); 2502 DELAY(10000); /* above not quite adequate on 5700 */ 2503 return 0; 2504 } 2505 2506 2507 /* 2508 * Entering ACPI power states D1-D3 is achieved by wiggling 2509 * GMII gpio pins. Example code assumes all hardware vendors 2510 * followed Broadcom's sample pcb layout. Until we verify that 2511 * for all supported OEM cards, states D1-D3 are unsupported. 2512 */ 2513 aprint_error_dev(sc->bge_dev, 2514 "power state %d unimplemented; check GPIO pins\n", 2515 powerlevel); 2516 #endif 2517 return EOPNOTSUPP; 2518 } 2519 2520 2521 /* 2522 * Probe for a Broadcom chip. Check the PCI vendor and device IDs 2523 * against our list and return its name if we find a match. Note 2524 * that since the Broadcom controller contains VPD support, we 2525 * can get the device name string from the controller itself instead 2526 * of the compiled-in string. This is a little slow, but it guarantees 2527 * we'll always announce the right product name. 2528 */ 2529 static int 2530 bge_probe(device_t parent, cfdata_t match, void *aux) 2531 { 2532 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 2533 2534 if (bge_lookup(pa) != NULL) 2535 return 1; 2536 2537 return 0; 2538 } 2539 2540 static void 2541 bge_attach(device_t parent, device_t self, void *aux) 2542 { 2543 struct bge_softc *sc = device_private(self); 2544 struct pci_attach_args *pa = aux; 2545 prop_dictionary_t dict; 2546 const struct bge_product *bp; 2547 const struct bge_revision *br; 2548 pci_chipset_tag_t pc; 2549 pci_intr_handle_t ih; 2550 const char *intrstr = NULL; 2551 bus_dma_segment_t seg; 2552 int rseg; 2553 uint32_t hwcfg = 0; 2554 uint32_t command; 2555 struct ifnet *ifp; 2556 uint32_t misccfg; 2557 void * kva; 2558 u_char eaddr[ETHER_ADDR_LEN]; 2559 pcireg_t memtype, subid; 2560 bus_addr_t memaddr; 2561 bus_size_t memsize; 2562 uint32_t pm_ctl; 2563 bool no_seeprom; 2564 2565 bp = bge_lookup(pa); 2566 KASSERT(bp != NULL); 2567 2568 sc->sc_pc = pa->pa_pc; 2569 sc->sc_pcitag = pa->pa_tag; 2570 sc->bge_dev = self; 2571 2572 pc = sc->sc_pc; 2573 subid = pci_conf_read(pc, sc->sc_pcitag, PCI_SUBSYS_ID_REG); 2574 2575 aprint_naive(": Ethernet controller\n"); 2576 aprint_normal(": %s\n", bp->bp_name); 2577 2578 /* 2579 * Map control/status registers. 2580 */ 2581 DPRINTFN(5, ("Map control/status regs\n")); 2582 command = pci_conf_read(pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG); 2583 command |= PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_MASTER_ENABLE; 2584 pci_conf_write(pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG, command); 2585 command = pci_conf_read(pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG); 2586 2587 if (!(command & PCI_COMMAND_MEM_ENABLE)) { 2588 aprint_error_dev(sc->bge_dev, 2589 "failed to enable memory mapping!\n"); 2590 return; 2591 } 2592 2593 DPRINTFN(5, ("pci_mem_find\n")); 2594 memtype = pci_mapreg_type(sc->sc_pc, sc->sc_pcitag, BGE_PCI_BAR0); 2595 switch (memtype) { 2596 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 2597 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 2598 if (pci_mapreg_map(pa, BGE_PCI_BAR0, 2599 memtype, 0, &sc->bge_btag, &sc->bge_bhandle, 2600 &memaddr, &memsize) == 0) 2601 break; 2602 default: 2603 aprint_error_dev(sc->bge_dev, "can't find mem space\n"); 2604 return; 2605 } 2606 2607 DPRINTFN(5, ("pci_intr_map\n")); 2608 if (pci_intr_map(pa, &ih)) { 2609 aprint_error_dev(sc->bge_dev, "couldn't map interrupt\n"); 2610 return; 2611 } 2612 2613 DPRINTFN(5, ("pci_intr_string\n")); 2614 intrstr = pci_intr_string(pc, ih); 2615 2616 DPRINTFN(5, ("pci_intr_establish\n")); 2617 sc->bge_intrhand = pci_intr_establish(pc, ih, IPL_NET, bge_intr, sc); 2618 2619 if (sc->bge_intrhand == NULL) { 2620 aprint_error_dev(sc->bge_dev, 2621 "couldn't establish interrupt%s%s\n", 2622 intrstr ? " at " : "", intrstr ? intrstr : ""); 2623 return; 2624 } 2625 aprint_normal_dev(sc->bge_dev, "interrupting at %s\n", intrstr); 2626 2627 /* 2628 * Kludge for 5700 Bx bug: a hardware bug (PCIX byte enable?) 2629 * can clobber the chip's PCI config-space power control registers, 2630 * leaving the card in D3 powersave state. 2631 * We do not have memory-mapped registers in this state, 2632 * so force device into D0 state before starting initialization. 2633 */ 2634 pm_ctl = pci_conf_read(pc, sc->sc_pcitag, BGE_PCI_PWRMGMT_CMD); 2635 pm_ctl &= ~(PCI_PWR_D0|PCI_PWR_D1|PCI_PWR_D2|PCI_PWR_D3); 2636 pm_ctl |= (1 << 8) | PCI_PWR_D0 ; /* D0 state */ 2637 pci_conf_write(pc, sc->sc_pcitag, BGE_PCI_PWRMGMT_CMD, pm_ctl); 2638 DELAY(1000); /* 27 usec is allegedly sufficent */ 2639 2640 /* 2641 * Save ASIC rev. 2642 */ 2643 sc->bge_chipid = 2644 pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_MISC_CTL) 2645 >> BGE_PCIMISCCTL_ASICREV_SHIFT; 2646 2647 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_USE_PRODID_REG) { 2648 switch (PCI_PRODUCT(pa->pa_id)) { 2649 case PCI_PRODUCT_BROADCOM_BCM5717: 2650 case PCI_PRODUCT_BROADCOM_BCM5718: 2651 case PCI_PRODUCT_BROADCOM_BCM5724: /* ??? */ 2652 sc->bge_chipid = pci_conf_read(pc, pa->pa_tag, 2653 BGE_PCI_GEN2_PRODID_ASICREV); 2654 break; 2655 case PCI_PRODUCT_BROADCOM_BCM57761: 2656 case PCI_PRODUCT_BROADCOM_BCM57762: 2657 case PCI_PRODUCT_BROADCOM_BCM57765: 2658 case PCI_PRODUCT_BROADCOM_BCM57781: 2659 case PCI_PRODUCT_BROADCOM_BCM57785: 2660 case PCI_PRODUCT_BROADCOM_BCM57791: 2661 case PCI_PRODUCT_BROADCOM_BCM57795: 2662 sc->bge_chipid = pci_conf_read(pc, pa->pa_tag, 2663 BGE_PCI_GEN15_PRODID_ASICREV); 2664 break; 2665 default: 2666 sc->bge_chipid = pci_conf_read(pc, pa->pa_tag, 2667 BGE_PCI_PRODID_ASICREV); 2668 break; 2669 } 2670 } 2671 2672 if ((pci_get_capability(sc->sc_pc, sc->sc_pcitag, PCI_CAP_PCIEXPRESS, 2673 &sc->bge_pciecap, NULL) != 0) 2674 || (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785)) { 2675 /* PCIe */ 2676 sc->bge_flags |= BGE_PCIE; 2677 bge_set_max_readrq(sc); 2678 } else if ((pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_PCISTATE) & 2679 BGE_PCISTATE_PCI_BUSMODE) == 0) { 2680 /* PCI-X */ 2681 sc->bge_flags |= BGE_PCIX; 2682 if (pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_PCIX, 2683 &sc->bge_pcixcap, NULL) == 0) 2684 aprint_error_dev(sc->bge_dev, 2685 "unable to find PCIX capability\n"); 2686 } 2687 2688 /* chipid */ 2689 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 2690 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5701 || 2691 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5703 || 2692 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) 2693 sc->bge_flags |= BGE_5700_FAMILY; 2694 2695 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5714_A0 || 2696 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5780 || 2697 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5714) 2698 sc->bge_flags |= BGE_5714_FAMILY; 2699 2700 /* Intentionally exclude BGE_ASICREV_BCM5906 */ 2701 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5717 || 2702 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5755 || 2703 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761 || 2704 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5784 || 2705 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785 || 2706 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5787 || 2707 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57765 || 2708 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57766 || 2709 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57780) 2710 sc->bge_flags |= BGE_5755_PLUS; 2711 2712 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5750 || 2713 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5752 || 2714 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906 || 2715 BGE_IS_5755_PLUS(sc) || 2716 BGE_IS_5714_FAMILY(sc)) 2717 sc->bge_flags |= BGE_575X_PLUS; 2718 2719 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5705 || 2720 BGE_IS_575X_PLUS(sc)) 2721 sc->bge_flags |= BGE_5705_PLUS; 2722 2723 /* 2724 * When using the BCM5701 in PCI-X mode, data corruption has 2725 * been observed in the first few bytes of some received packets. 2726 * Aligning the packet buffer in memory eliminates the corruption. 2727 * Unfortunately, this misaligns the packet payloads. On platforms 2728 * which do not support unaligned accesses, we will realign the 2729 * payloads by copying the received packets. 2730 */ 2731 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5701 && 2732 sc->bge_flags & BGE_PCIX) 2733 sc->bge_flags |= BGE_RX_ALIGNBUG; 2734 2735 if (BGE_IS_5700_FAMILY(sc)) 2736 sc->bge_flags |= BGE_JUMBO_CAPABLE; 2737 2738 if ((BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 2739 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5701) && 2740 PCI_VENDOR(subid) == PCI_VENDOR_DELL) 2741 sc->bge_flags |= BGE_NO_3LED; 2742 2743 misccfg = CSR_READ_4(sc, BGE_MISC_CFG); 2744 misccfg &= BGE_MISCCFG_BOARD_ID_MASK; 2745 2746 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5705 && 2747 (misccfg == BGE_MISCCFG_BOARD_ID_5788 || 2748 misccfg == BGE_MISCCFG_BOARD_ID_5788M)) 2749 sc->bge_flags |= BGE_IS_5788; 2750 2751 /* 2752 * Some controllers seem to require a special firmware to use 2753 * TSO. But the firmware is not available to FreeBSD and Linux 2754 * claims that the TSO performed by the firmware is slower than 2755 * hardware based TSO. Moreover the firmware based TSO has one 2756 * known bug which can't handle TSO if ethernet header + IP/TCP 2757 * header is greater than 80 bytes. The workaround for the TSO 2758 * bug exist but it seems it's too expensive than not using 2759 * TSO at all. Some hardwares also have the TSO bug so limit 2760 * the TSO to the controllers that are not affected TSO issues 2761 * (e.g. 5755 or higher). 2762 */ 2763 if (BGE_IS_5755_PLUS(sc)) { 2764 /* 2765 * BCM5754 and BCM5787 shares the same ASIC id so 2766 * explicit device id check is required. 2767 */ 2768 if ((PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_BROADCOM_BCM5754) && 2769 (PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_BROADCOM_BCM5754M)) 2770 sc->bge_flags |= BGE_TSO; 2771 } 2772 2773 if ((BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5703 && 2774 (misccfg == 0x4000 || misccfg == 0x8000)) || 2775 (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5705 && 2776 PCI_VENDOR(pa->pa_id) == PCI_VENDOR_BROADCOM && 2777 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5901 || 2778 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5901A2 || 2779 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5705F)) || 2780 (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_BROADCOM && 2781 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5751F || 2782 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5753F || 2783 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5787F)) || 2784 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM57790 || 2785 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 2786 sc->bge_flags |= BGE_10_100_ONLY; 2787 2788 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 2789 (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5705 && 2790 (sc->bge_chipid != BGE_CHIPID_BCM5705_A0 && 2791 sc->bge_chipid != BGE_CHIPID_BCM5705_A1)) || 2792 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 2793 sc->bge_flags |= BGE_NO_ETH_WIRE_SPEED; 2794 2795 if (sc->bge_chipid == BGE_CHIPID_BCM5701_A0 || 2796 sc->bge_chipid == BGE_CHIPID_BCM5701_B0) 2797 sc->bge_flags |= BGE_PHY_CRC_BUG; 2798 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5703_AX || 2799 BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5704_AX) 2800 sc->bge_flags |= BGE_PHY_ADC_BUG; 2801 if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0) 2802 sc->bge_flags |= BGE_PHY_5704_A0_BUG; 2803 2804 if (BGE_IS_5705_PLUS(sc) && 2805 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5906 && 2806 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5717 && 2807 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5785 && 2808 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM57765 && 2809 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM57766 && 2810 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM57780) { 2811 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5755 || 2812 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761 || 2813 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5784 || 2814 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5787) { 2815 if (PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_BROADCOM_BCM5722 && 2816 PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_BROADCOM_BCM5756) 2817 sc->bge_flags |= BGE_PHY_JITTER_BUG; 2818 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5755M) 2819 sc->bge_flags |= BGE_PHY_ADJUST_TRIM; 2820 } else if (BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5906) 2821 sc->bge_flags |= BGE_PHY_BER_BUG; 2822 } 2823 2824 /* 2825 * SEEPROM check. 2826 * First check if firmware knows we do not have SEEPROM. 2827 */ 2828 if (prop_dictionary_get_bool(device_properties(self), 2829 "without-seeprom", &no_seeprom) && no_seeprom) 2830 sc->bge_flags |= BGE_NO_EEPROM; 2831 2832 /* Now check the 'ROM failed' bit on the RX CPU */ 2833 else if (CSR_READ_4(sc, BGE_RXCPU_MODE) & BGE_RXCPUMODE_ROMFAIL) 2834 sc->bge_flags |= BGE_NO_EEPROM; 2835 2836 /* Try to reset the chip. */ 2837 DPRINTFN(5, ("bge_reset\n")); 2838 bge_reset(sc); 2839 2840 sc->bge_asf_mode = 0; 2841 if (bge_allow_asf && (bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_SIG) 2842 == BGE_MAGIC_NUMBER)) { 2843 if (bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_NICCFG) 2844 & BGE_HWCFG_ASF) { 2845 sc->bge_asf_mode |= ASF_ENABLE; 2846 sc->bge_asf_mode |= ASF_STACKUP; 2847 if (BGE_IS_575X_PLUS(sc)) { 2848 sc->bge_asf_mode |= ASF_NEW_HANDSHAKE; 2849 } 2850 } 2851 } 2852 2853 /* Try to reset the chip again the nice way. */ 2854 bge_stop_fw(sc); 2855 bge_sig_pre_reset(sc, BGE_RESET_STOP); 2856 if (bge_reset(sc)) 2857 aprint_error_dev(sc->bge_dev, "chip reset failed\n"); 2858 2859 bge_sig_legacy(sc, BGE_RESET_STOP); 2860 bge_sig_post_reset(sc, BGE_RESET_STOP); 2861 2862 if (bge_chipinit(sc)) { 2863 aprint_error_dev(sc->bge_dev, "chip initialization failed\n"); 2864 bge_release_resources(sc); 2865 return; 2866 } 2867 2868 /* 2869 * Get station address from the EEPROM. 2870 */ 2871 if (bge_get_eaddr(sc, eaddr)) { 2872 aprint_error_dev(sc->bge_dev, 2873 "failed to read station address\n"); 2874 bge_release_resources(sc); 2875 return; 2876 } 2877 2878 br = bge_lookup_rev(sc->bge_chipid); 2879 2880 if (br == NULL) { 2881 aprint_normal_dev(sc->bge_dev, "unknown ASIC (0x%x)", 2882 sc->bge_chipid); 2883 } else { 2884 aprint_normal_dev(sc->bge_dev, "ASIC %s (0x%x)", 2885 br->br_name, sc->bge_chipid); 2886 } 2887 aprint_normal(", Ethernet address %s\n", ether_sprintf(eaddr)); 2888 2889 /* Allocate the general information block and ring buffers. */ 2890 if (pci_dma64_available(pa)) 2891 sc->bge_dmatag = pa->pa_dmat64; 2892 else 2893 sc->bge_dmatag = pa->pa_dmat; 2894 DPRINTFN(5, ("bus_dmamem_alloc\n")); 2895 if (bus_dmamem_alloc(sc->bge_dmatag, sizeof(struct bge_ring_data), 2896 PAGE_SIZE, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 2897 aprint_error_dev(sc->bge_dev, "can't alloc rx buffers\n"); 2898 return; 2899 } 2900 DPRINTFN(5, ("bus_dmamem_map\n")); 2901 if (bus_dmamem_map(sc->bge_dmatag, &seg, rseg, 2902 sizeof(struct bge_ring_data), &kva, 2903 BUS_DMA_NOWAIT)) { 2904 aprint_error_dev(sc->bge_dev, 2905 "can't map DMA buffers (%zu bytes)\n", 2906 sizeof(struct bge_ring_data)); 2907 bus_dmamem_free(sc->bge_dmatag, &seg, rseg); 2908 return; 2909 } 2910 DPRINTFN(5, ("bus_dmamem_create\n")); 2911 if (bus_dmamap_create(sc->bge_dmatag, sizeof(struct bge_ring_data), 1, 2912 sizeof(struct bge_ring_data), 0, 2913 BUS_DMA_NOWAIT, &sc->bge_ring_map)) { 2914 aprint_error_dev(sc->bge_dev, "can't create DMA map\n"); 2915 bus_dmamem_unmap(sc->bge_dmatag, kva, 2916 sizeof(struct bge_ring_data)); 2917 bus_dmamem_free(sc->bge_dmatag, &seg, rseg); 2918 return; 2919 } 2920 DPRINTFN(5, ("bus_dmamem_load\n")); 2921 if (bus_dmamap_load(sc->bge_dmatag, sc->bge_ring_map, kva, 2922 sizeof(struct bge_ring_data), NULL, 2923 BUS_DMA_NOWAIT)) { 2924 bus_dmamap_destroy(sc->bge_dmatag, sc->bge_ring_map); 2925 bus_dmamem_unmap(sc->bge_dmatag, kva, 2926 sizeof(struct bge_ring_data)); 2927 bus_dmamem_free(sc->bge_dmatag, &seg, rseg); 2928 return; 2929 } 2930 2931 DPRINTFN(5, ("bzero\n")); 2932 sc->bge_rdata = (struct bge_ring_data *)kva; 2933 2934 memset(sc->bge_rdata, 0, sizeof(struct bge_ring_data)); 2935 2936 /* Try to allocate memory for jumbo buffers. */ 2937 if (BGE_IS_JUMBO_CAPABLE(sc)) { 2938 if (bge_alloc_jumbo_mem(sc)) { 2939 aprint_error_dev(sc->bge_dev, 2940 "jumbo buffer allocation failed\n"); 2941 } else 2942 sc->ethercom.ec_capabilities |= ETHERCAP_JUMBO_MTU; 2943 } 2944 2945 /* Set default tuneable values. */ 2946 sc->bge_stat_ticks = BGE_TICKS_PER_SEC; 2947 sc->bge_rx_coal_ticks = 150; 2948 sc->bge_rx_max_coal_bds = 64; 2949 #ifdef ORIG_WPAUL_VALUES 2950 sc->bge_tx_coal_ticks = 150; 2951 sc->bge_tx_max_coal_bds = 128; 2952 #else 2953 sc->bge_tx_coal_ticks = 300; 2954 sc->bge_tx_max_coal_bds = 400; 2955 #endif 2956 if (BGE_IS_5705_PLUS(sc)) { 2957 sc->bge_tx_coal_ticks = (12 * 5); 2958 sc->bge_tx_max_coal_bds = (12 * 5); 2959 aprint_verbose_dev(sc->bge_dev, 2960 "setting short Tx thresholds\n"); 2961 } 2962 2963 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5717 || 2964 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57765 || 2965 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57766) 2966 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT; 2967 else if (BGE_IS_5705_PLUS(sc)) 2968 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT_5705; 2969 else 2970 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT; 2971 2972 /* Set up ifnet structure */ 2973 ifp = &sc->ethercom.ec_if; 2974 ifp->if_softc = sc; 2975 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 2976 ifp->if_ioctl = bge_ioctl; 2977 ifp->if_stop = bge_stop; 2978 ifp->if_start = bge_start; 2979 ifp->if_init = bge_init; 2980 ifp->if_watchdog = bge_watchdog; 2981 IFQ_SET_MAXLEN(&ifp->if_snd, max(BGE_TX_RING_CNT - 1, IFQ_MAXLEN)); 2982 IFQ_SET_READY(&ifp->if_snd); 2983 DPRINTFN(5, ("strcpy if_xname\n")); 2984 strcpy(ifp->if_xname, device_xname(sc->bge_dev)); 2985 2986 if (sc->bge_chipid != BGE_CHIPID_BCM5700_B0) 2987 sc->ethercom.ec_if.if_capabilities |= 2988 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx; 2989 #if 1 /* XXX TCP/UDP checksum offload breaks with pf(4) */ 2990 sc->ethercom.ec_if.if_capabilities |= 2991 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 2992 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 2993 #endif 2994 sc->ethercom.ec_capabilities |= 2995 ETHERCAP_VLAN_HWTAGGING | ETHERCAP_VLAN_MTU; 2996 2997 if (sc->bge_flags & BGE_TSO) 2998 sc->ethercom.ec_if.if_capabilities |= IFCAP_TSOv4; 2999 3000 /* 3001 * Do MII setup. 3002 */ 3003 DPRINTFN(5, ("mii setup\n")); 3004 sc->bge_mii.mii_ifp = ifp; 3005 sc->bge_mii.mii_readreg = bge_miibus_readreg; 3006 sc->bge_mii.mii_writereg = bge_miibus_writereg; 3007 sc->bge_mii.mii_statchg = bge_miibus_statchg; 3008 3009 /* 3010 * Figure out what sort of media we have by checking the hardware 3011 * config word in the first 32k of NIC internal memory, or fall back to 3012 * the config word in the EEPROM. Note: on some BCM5700 cards, 3013 * this value appears to be unset. If that's the case, we have to rely 3014 * on identifying the NIC by its PCI subsystem ID, as we do below for 3015 * the SysKonnect SK-9D41. 3016 */ 3017 if (bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_SIG) == BGE_MAGIC_NUMBER) { 3018 hwcfg = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_NICCFG); 3019 } else if (!(sc->bge_flags & BGE_NO_EEPROM)) { 3020 bge_read_eeprom(sc, (void *)&hwcfg, 3021 BGE_EE_HWCFG_OFFSET, sizeof(hwcfg)); 3022 hwcfg = be32toh(hwcfg); 3023 } 3024 /* The SysKonnect SK-9D41 is a 1000baseSX card. */ 3025 if (PCI_PRODUCT(pa->pa_id) == SK_SUBSYSID_9D41 || 3026 (hwcfg & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER) { 3027 if (BGE_IS_5714_FAMILY(sc)) 3028 sc->bge_flags |= BGE_PHY_FIBER_MII; 3029 else 3030 sc->bge_flags |= BGE_PHY_FIBER_TBI; 3031 } 3032 3033 /* set phyflags and chipid before mii_attach() */ 3034 dict = device_properties(self); 3035 prop_dictionary_set_uint32(dict, "phyflags", sc->bge_flags); 3036 prop_dictionary_set_uint32(dict, "chipid", sc->bge_chipid); 3037 3038 if (sc->bge_flags & BGE_PHY_FIBER_TBI) { 3039 ifmedia_init(&sc->bge_ifmedia, IFM_IMASK, bge_ifmedia_upd, 3040 bge_ifmedia_sts); 3041 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER |IFM_1000_SX, 0, NULL); 3042 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_1000_SX|IFM_FDX, 3043 0, NULL); 3044 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_AUTO, 0, NULL); 3045 ifmedia_set(&sc->bge_ifmedia, IFM_ETHER | IFM_AUTO); 3046 /* Pretend the user requested this setting */ 3047 sc->bge_ifmedia.ifm_media = sc->bge_ifmedia.ifm_cur->ifm_media; 3048 } else { 3049 /* 3050 * Do transceiver setup and tell the firmware the 3051 * driver is down so we can try to get access the 3052 * probe if ASF is running. Retry a couple of times 3053 * if we get a conflict with the ASF firmware accessing 3054 * the PHY. 3055 */ 3056 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 3057 bge_asf_driver_up(sc); 3058 3059 ifmedia_init(&sc->bge_mii.mii_media, 0, bge_ifmedia_upd, 3060 bge_ifmedia_sts); 3061 mii_attach(sc->bge_dev, &sc->bge_mii, 0xffffffff, 3062 MII_PHY_ANY, MII_OFFSET_ANY, 3063 MIIF_FORCEANEG|MIIF_DOPAUSE); 3064 3065 if (LIST_EMPTY(&sc->bge_mii.mii_phys)) { 3066 aprint_error_dev(sc->bge_dev, "no PHY found!\n"); 3067 ifmedia_add(&sc->bge_mii.mii_media, 3068 IFM_ETHER|IFM_MANUAL, 0, NULL); 3069 ifmedia_set(&sc->bge_mii.mii_media, 3070 IFM_ETHER|IFM_MANUAL); 3071 } else 3072 ifmedia_set(&sc->bge_mii.mii_media, 3073 IFM_ETHER|IFM_AUTO); 3074 3075 /* 3076 * Now tell the firmware we are going up after probing the PHY 3077 */ 3078 if (sc->bge_asf_mode & ASF_STACKUP) 3079 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 3080 } 3081 3082 /* 3083 * Call MI attach routine. 3084 */ 3085 DPRINTFN(5, ("if_attach\n")); 3086 if_attach(ifp); 3087 DPRINTFN(5, ("ether_ifattach\n")); 3088 ether_ifattach(ifp, eaddr); 3089 ether_set_ifflags_cb(&sc->ethercom, bge_ifflags_cb); 3090 rnd_attach_source(&sc->rnd_source, device_xname(sc->bge_dev), 3091 RND_TYPE_NET, 0); 3092 #ifdef BGE_EVENT_COUNTERS 3093 /* 3094 * Attach event counters. 3095 */ 3096 evcnt_attach_dynamic(&sc->bge_ev_intr, EVCNT_TYPE_INTR, 3097 NULL, device_xname(sc->bge_dev), "intr"); 3098 evcnt_attach_dynamic(&sc->bge_ev_tx_xoff, EVCNT_TYPE_MISC, 3099 NULL, device_xname(sc->bge_dev), "tx_xoff"); 3100 evcnt_attach_dynamic(&sc->bge_ev_tx_xon, EVCNT_TYPE_MISC, 3101 NULL, device_xname(sc->bge_dev), "tx_xon"); 3102 evcnt_attach_dynamic(&sc->bge_ev_rx_xoff, EVCNT_TYPE_MISC, 3103 NULL, device_xname(sc->bge_dev), "rx_xoff"); 3104 evcnt_attach_dynamic(&sc->bge_ev_rx_xon, EVCNT_TYPE_MISC, 3105 NULL, device_xname(sc->bge_dev), "rx_xon"); 3106 evcnt_attach_dynamic(&sc->bge_ev_rx_macctl, EVCNT_TYPE_MISC, 3107 NULL, device_xname(sc->bge_dev), "rx_macctl"); 3108 evcnt_attach_dynamic(&sc->bge_ev_xoffentered, EVCNT_TYPE_MISC, 3109 NULL, device_xname(sc->bge_dev), "xoffentered"); 3110 #endif /* BGE_EVENT_COUNTERS */ 3111 DPRINTFN(5, ("callout_init\n")); 3112 callout_init(&sc->bge_timeout, 0); 3113 3114 if (pmf_device_register(self, NULL, NULL)) 3115 pmf_class_network_register(self, ifp); 3116 else 3117 aprint_error_dev(self, "couldn't establish power handler\n"); 3118 3119 bge_sysctl_init(sc); 3120 3121 #ifdef BGE_DEBUG 3122 bge_debug_info(sc); 3123 #endif 3124 } 3125 3126 static void 3127 bge_release_resources(struct bge_softc *sc) 3128 { 3129 if (sc->bge_vpd_prodname != NULL) 3130 free(sc->bge_vpd_prodname, M_DEVBUF); 3131 3132 if (sc->bge_vpd_readonly != NULL) 3133 free(sc->bge_vpd_readonly, M_DEVBUF); 3134 } 3135 3136 static int 3137 bge_reset(struct bge_softc *sc) 3138 { 3139 uint32_t cachesize, command, pcistate, marbmode; 3140 #if 0 3141 uint32_t new_pcistate; 3142 #endif 3143 pcireg_t devctl, reg; 3144 int i, val; 3145 void (*write_op)(struct bge_softc *, int, int); 3146 3147 if (BGE_IS_575X_PLUS(sc) && !BGE_IS_5714_FAMILY(sc) 3148 && (BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5906)) { 3149 if (sc->bge_flags & BGE_PCIE) 3150 write_op = bge_writemem_direct; 3151 else 3152 write_op = bge_writemem_ind; 3153 } else 3154 write_op = bge_writereg_ind; 3155 3156 /* Save some important PCI state. */ 3157 cachesize = pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CACHESZ); 3158 command = pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CMD); 3159 pcistate = pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_PCISTATE); 3160 3161 /* Step 5a: Enable memory arbiter. */ 3162 marbmode = 0; 3163 if (BGE_IS_5714_FAMILY(sc)) 3164 marbmode = CSR_READ_4(sc, BGE_MARB_MODE); 3165 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE | marbmode); 3166 3167 /* Step 5b-5d: */ 3168 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MISC_CTL, 3169 BGE_PCIMISCCTL_INDIRECT_ACCESS | BGE_PCIMISCCTL_MASK_PCI_INTR | 3170 BGE_HIF_SWAP_OPTIONS | BGE_PCIMISCCTL_PCISTATE_RW); 3171 3172 /* XXX ???: Disable fastboot on controllers that support it. */ 3173 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5752 || 3174 BGE_IS_5755_PLUS(sc)) 3175 CSR_WRITE_4(sc, BGE_FASTBOOT_PC, 0); 3176 3177 /* 3178 * Step 6: Write the magic number to SRAM at offset 0xB50. 3179 * When firmware finishes its initialization it will 3180 * write ~BGE_MAGIC_NUMBER to the same location. 3181 */ 3182 bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM, BGE_MAGIC_NUMBER); 3183 3184 /* Step 7: */ 3185 val = BGE_MISCCFG_RESET_CORE_CLOCKS | (65<<1); 3186 /* 3187 * XXX: from FreeBSD/Linux; no documentation 3188 */ 3189 if (sc->bge_flags & BGE_PCIE) { 3190 if (CSR_READ_4(sc, BGE_PCIE_CTL1) == 0x60) 3191 /* PCI Express 1.0 system */ 3192 CSR_WRITE_4(sc, BGE_PCIE_CTL1, 0x20); 3193 if (sc->bge_chipid != BGE_CHIPID_BCM5750_A0) { 3194 /* 3195 * Prevent PCI Express link training 3196 * during global reset. 3197 */ 3198 CSR_WRITE_4(sc, BGE_MISC_CFG, 1 << 29); 3199 val |= (1<<29); 3200 } 3201 } 3202 3203 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 3204 i = CSR_READ_4(sc, BGE_VCPU_STATUS); 3205 CSR_WRITE_4(sc, BGE_VCPU_STATUS, 3206 i | BGE_VCPU_STATUS_DRV_RESET); 3207 i = CSR_READ_4(sc, BGE_VCPU_EXT_CTRL); 3208 CSR_WRITE_4(sc, BGE_VCPU_EXT_CTRL, 3209 i & ~BGE_VCPU_EXT_CTRL_HALT_CPU); 3210 } 3211 3212 /* 3213 * Set GPHY Power Down Override to leave GPHY 3214 * powered up in D0 uninitialized. 3215 */ 3216 if (BGE_IS_5705_PLUS(sc)) 3217 val |= BGE_MISCCFG_KEEP_GPHY_POWER; 3218 3219 /* XXX 5721, 5751 and 5752 */ 3220 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5750) 3221 val |= BGE_MISCCFG_GRC_RESET_DISABLE; 3222 3223 /* Issue global reset */ 3224 write_op(sc, BGE_MISC_CFG, val); 3225 3226 /* Step 8: wait for complete */ 3227 if (sc->bge_flags & BGE_PCIE) 3228 delay(100*1000); /* too big */ 3229 else 3230 delay(100); 3231 3232 /* From Linux: dummy read to flush PCI posted writes */ 3233 reg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CMD); 3234 3235 /* Step 9-10: Reset some of the PCI state that got zapped by reset */ 3236 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MISC_CTL, 3237 BGE_PCIMISCCTL_INDIRECT_ACCESS | BGE_PCIMISCCTL_MASK_PCI_INTR | 3238 BGE_HIF_SWAP_OPTIONS | BGE_PCIMISCCTL_PCISTATE_RW 3239 | BGE_PCIMISCCTL_CLOCKCTL_RW); 3240 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CMD, command); 3241 write_op(sc, BGE_MISC_CFG, (65 << 1)); 3242 3243 /* Step 11: disable PCI-X Relaxed Ordering. */ 3244 if (sc->bge_flags & BGE_PCIX) { 3245 reg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, sc->bge_pcixcap 3246 + PCI_PCIX_CMD); 3247 pci_conf_write(sc->sc_pc, sc->sc_pcitag, sc->bge_pcixcap 3248 + PCI_PCIX_CMD, reg & ~PCI_PCIX_CMD_RELAXED_ORDER); 3249 } 3250 3251 if (sc->bge_flags & BGE_PCIE) { 3252 if (sc->bge_chipid == BGE_CHIPID_BCM5750_A0) { 3253 DELAY(500000); 3254 /* XXX: Magic Numbers */ 3255 reg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 3256 BGE_PCI_UNKNOWN0); 3257 pci_conf_write(sc->sc_pc, sc->sc_pcitag, 3258 BGE_PCI_UNKNOWN0, 3259 reg | (1 << 15)); 3260 } 3261 devctl = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 3262 sc->bge_pciecap + PCI_PCIE_DCSR); 3263 /* Clear enable no snoop and disable relaxed ordering. */ 3264 devctl &= ~(PCI_PCIE_DCSR_ENA_RELAX_ORD | 3265 PCI_PCIE_DCSR_ENA_NO_SNOOP); 3266 /* Set PCIE max payload size to 128. */ 3267 devctl &= ~(0x00e0); 3268 /* Clear device status register. Write 1b to clear */ 3269 devctl |= PCI_PCIE_DCSR_URD | PCI_PCIE_DCSR_FED 3270 | PCI_PCIE_DCSR_NFED | PCI_PCIE_DCSR_CED; 3271 pci_conf_write(sc->sc_pc, sc->sc_pcitag, 3272 sc->bge_pciecap + PCI_PCIE_DCSR, devctl); 3273 } 3274 3275 /* Step 12: Enable memory arbiter. */ 3276 marbmode = 0; 3277 if (BGE_IS_5714_FAMILY(sc)) 3278 marbmode = CSR_READ_4(sc, BGE_MARB_MODE); 3279 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE | marbmode); 3280 3281 /* Step 17: Poll until the firmware initialization is complete */ 3282 bge_poll_fw(sc); 3283 3284 /* XXX 5721, 5751 and 5752 */ 3285 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5750) { 3286 /* Step 19: */ 3287 BGE_SETBIT(sc, BGE_TLP_CONTROL_REG, 1 << 29 | 1 << 25); 3288 /* Step 20: */ 3289 BGE_SETBIT(sc, BGE_TLP_CONTROL_REG, BGE_TLP_DATA_FIFO_PROTECT); 3290 } 3291 3292 /* 3293 * Step 18: wirte mac mode 3294 * XXX Write 0x0c for 5703S and 5704S 3295 */ 3296 CSR_WRITE_4_FLUSH(sc, BGE_MAC_MODE, 0); 3297 DELAY(40); 3298 3299 3300 /* Step 21: 5822 B0 errata */ 3301 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5704_BX) { 3302 pcireg_t msidata; 3303 3304 msidata = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 3305 BGE_PCI_MSI_DATA); 3306 msidata |= ((1 << 13 | 1 << 12 | 1 << 10) << 16); 3307 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MSI_DATA, 3308 msidata); 3309 } 3310 3311 /* Step 23: restore cache line size */ 3312 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CACHESZ, cachesize); 3313 3314 #if 0 3315 /* 3316 * XXX Wait for the value of the PCISTATE register to 3317 * return to its original pre-reset state. This is a 3318 * fairly good indicator of reset completion. If we don't 3319 * wait for the reset to fully complete, trying to read 3320 * from the device's non-PCI registers may yield garbage 3321 * results. 3322 */ 3323 for (i = 0; i < BGE_TIMEOUT; i++) { 3324 new_pcistate = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 3325 BGE_PCI_PCISTATE); 3326 if ((new_pcistate & ~BGE_PCISTATE_RESERVED) == 3327 (pcistate & ~BGE_PCISTATE_RESERVED)) 3328 break; 3329 DELAY(10); 3330 } 3331 if ((new_pcistate & ~BGE_PCISTATE_RESERVED) != 3332 (pcistate & ~BGE_PCISTATE_RESERVED)) { 3333 aprint_error_dev(sc->bge_dev, "pcistate failed to revert\n"); 3334 } 3335 #endif 3336 3337 /* Step 28: Fix up byte swapping */ 3338 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS); 3339 3340 /* Tell the ASF firmware we are up */ 3341 if (sc->bge_asf_mode & ASF_STACKUP) 3342 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 3343 3344 /* 3345 * The 5704 in TBI mode apparently needs some special 3346 * adjustment to insure the SERDES drive level is set 3347 * to 1.2V. 3348 */ 3349 if (sc->bge_flags & BGE_PHY_FIBER_TBI && 3350 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) { 3351 uint32_t serdescfg; 3352 3353 serdescfg = CSR_READ_4(sc, BGE_SERDES_CFG); 3354 serdescfg = (serdescfg & ~0xFFF) | 0x880; 3355 CSR_WRITE_4(sc, BGE_SERDES_CFG, serdescfg); 3356 } 3357 3358 if (sc->bge_flags & BGE_PCIE && 3359 sc->bge_chipid != BGE_CHIPID_BCM5750_A0 && 3360 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5717 && 3361 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5785 && 3362 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM57765 && 3363 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM57766) { 3364 uint32_t v; 3365 3366 /* Enable PCI Express bug fix */ 3367 v = CSR_READ_4(sc, 0x7c00); 3368 CSR_WRITE_4(sc, 0x7c00, v | (1<<25)); 3369 } 3370 DELAY(10000); 3371 3372 return 0; 3373 } 3374 3375 /* 3376 * Frame reception handling. This is called if there's a frame 3377 * on the receive return list. 3378 * 3379 * Note: we have to be able to handle two possibilities here: 3380 * 1) the frame is from the jumbo receive ring 3381 * 2) the frame is from the standard receive ring 3382 */ 3383 3384 static void 3385 bge_rxeof(struct bge_softc *sc) 3386 { 3387 struct ifnet *ifp; 3388 uint16_t rx_prod, rx_cons; 3389 int stdcnt = 0, jumbocnt = 0; 3390 bus_dmamap_t dmamap; 3391 bus_addr_t offset, toff; 3392 bus_size_t tlen; 3393 int tosync; 3394 3395 rx_cons = sc->bge_rx_saved_considx; 3396 rx_prod = sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx; 3397 3398 /* Nothing to do */ 3399 if (rx_cons == rx_prod) 3400 return; 3401 3402 ifp = &sc->ethercom.ec_if; 3403 3404 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 3405 offsetof(struct bge_ring_data, bge_status_block), 3406 sizeof (struct bge_status_block), 3407 BUS_DMASYNC_POSTREAD); 3408 3409 offset = offsetof(struct bge_ring_data, bge_rx_return_ring); 3410 tosync = rx_prod - rx_cons; 3411 3412 if (tosync != 0) 3413 rnd_add_uint32(&sc->rnd_source, tosync); 3414 3415 toff = offset + (rx_cons * sizeof (struct bge_rx_bd)); 3416 3417 if (tosync < 0) { 3418 tlen = (sc->bge_return_ring_cnt - rx_cons) * 3419 sizeof (struct bge_rx_bd); 3420 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 3421 toff, tlen, BUS_DMASYNC_POSTREAD); 3422 tosync = -tosync; 3423 } 3424 3425 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 3426 offset, tosync * sizeof (struct bge_rx_bd), 3427 BUS_DMASYNC_POSTREAD); 3428 3429 while (rx_cons != rx_prod) { 3430 struct bge_rx_bd *cur_rx; 3431 uint32_t rxidx; 3432 struct mbuf *m = NULL; 3433 3434 cur_rx = &sc->bge_rdata->bge_rx_return_ring[rx_cons]; 3435 3436 rxidx = cur_rx->bge_idx; 3437 BGE_INC(rx_cons, sc->bge_return_ring_cnt); 3438 3439 if (cur_rx->bge_flags & BGE_RXBDFLAG_JUMBO_RING) { 3440 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT); 3441 m = sc->bge_cdata.bge_rx_jumbo_chain[rxidx]; 3442 sc->bge_cdata.bge_rx_jumbo_chain[rxidx] = NULL; 3443 jumbocnt++; 3444 bus_dmamap_sync(sc->bge_dmatag, 3445 sc->bge_cdata.bge_rx_jumbo_map, 3446 mtod(m, char *) - (char *)sc->bge_cdata.bge_jumbo_buf, 3447 BGE_JLEN, BUS_DMASYNC_POSTREAD); 3448 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 3449 ifp->if_ierrors++; 3450 bge_newbuf_jumbo(sc, sc->bge_jumbo, m); 3451 continue; 3452 } 3453 if (bge_newbuf_jumbo(sc, sc->bge_jumbo, 3454 NULL)== ENOBUFS) { 3455 ifp->if_ierrors++; 3456 bge_newbuf_jumbo(sc, sc->bge_jumbo, m); 3457 continue; 3458 } 3459 } else { 3460 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT); 3461 m = sc->bge_cdata.bge_rx_std_chain[rxidx]; 3462 3463 sc->bge_cdata.bge_rx_std_chain[rxidx] = NULL; 3464 stdcnt++; 3465 dmamap = sc->bge_cdata.bge_rx_std_map[rxidx]; 3466 sc->bge_cdata.bge_rx_std_map[rxidx] = 0; 3467 if (dmamap == NULL) { 3468 ifp->if_ierrors++; 3469 bge_newbuf_std(sc, sc->bge_std, m, dmamap); 3470 continue; 3471 } 3472 bus_dmamap_sync(sc->bge_dmatag, dmamap, 0, 3473 dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 3474 bus_dmamap_unload(sc->bge_dmatag, dmamap); 3475 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 3476 ifp->if_ierrors++; 3477 bge_newbuf_std(sc, sc->bge_std, m, dmamap); 3478 continue; 3479 } 3480 if (bge_newbuf_std(sc, sc->bge_std, 3481 NULL, dmamap) == ENOBUFS) { 3482 ifp->if_ierrors++; 3483 bge_newbuf_std(sc, sc->bge_std, m, dmamap); 3484 continue; 3485 } 3486 } 3487 3488 ifp->if_ipackets++; 3489 #ifndef __NO_STRICT_ALIGNMENT 3490 /* 3491 * XXX: if the 5701 PCIX-Rx-DMA workaround is in effect, 3492 * the Rx buffer has the layer-2 header unaligned. 3493 * If our CPU requires alignment, re-align by copying. 3494 */ 3495 if (sc->bge_flags & BGE_RX_ALIGNBUG) { 3496 memmove(mtod(m, char *) + ETHER_ALIGN, m->m_data, 3497 cur_rx->bge_len); 3498 m->m_data += ETHER_ALIGN; 3499 } 3500 #endif 3501 3502 m->m_pkthdr.len = m->m_len = cur_rx->bge_len - ETHER_CRC_LEN; 3503 m->m_pkthdr.rcvif = ifp; 3504 3505 /* 3506 * Handle BPF listeners. Let the BPF user see the packet. 3507 */ 3508 bpf_mtap(ifp, m); 3509 3510 m->m_pkthdr.csum_flags = M_CSUM_IPv4; 3511 3512 if ((cur_rx->bge_ip_csum ^ 0xffff) != 0) 3513 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 3514 /* 3515 * Rx transport checksum-offload may also 3516 * have bugs with packets which, when transmitted, 3517 * were `runts' requiring padding. 3518 */ 3519 if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM && 3520 (/* (sc->_bge_quirks & BGE_QUIRK_SHORT_CKSUM_BUG) == 0 ||*/ 3521 m->m_pkthdr.len >= ETHER_MIN_NOPAD)) { 3522 m->m_pkthdr.csum_data = 3523 cur_rx->bge_tcp_udp_csum; 3524 m->m_pkthdr.csum_flags |= 3525 (M_CSUM_TCPv4|M_CSUM_UDPv4| 3526 M_CSUM_DATA); 3527 } 3528 3529 /* 3530 * If we received a packet with a vlan tag, pass it 3531 * to vlan_input() instead of ether_input(). 3532 */ 3533 if (cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) { 3534 VLAN_INPUT_TAG(ifp, m, cur_rx->bge_vlan_tag, continue); 3535 } 3536 3537 (*ifp->if_input)(ifp, m); 3538 } 3539 3540 sc->bge_rx_saved_considx = rx_cons; 3541 bge_writembx(sc, BGE_MBX_RX_CONS0_LO, sc->bge_rx_saved_considx); 3542 if (stdcnt) 3543 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std); 3544 if (jumbocnt) 3545 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo); 3546 } 3547 3548 static void 3549 bge_txeof(struct bge_softc *sc) 3550 { 3551 struct bge_tx_bd *cur_tx = NULL; 3552 struct ifnet *ifp; 3553 struct txdmamap_pool_entry *dma; 3554 bus_addr_t offset, toff; 3555 bus_size_t tlen; 3556 int tosync; 3557 struct mbuf *m; 3558 3559 ifp = &sc->ethercom.ec_if; 3560 3561 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 3562 offsetof(struct bge_ring_data, bge_status_block), 3563 sizeof (struct bge_status_block), 3564 BUS_DMASYNC_POSTREAD); 3565 3566 offset = offsetof(struct bge_ring_data, bge_tx_ring); 3567 tosync = sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx - 3568 sc->bge_tx_saved_considx; 3569 3570 if (tosync != 0) 3571 rnd_add_uint32(&sc->rnd_source, tosync); 3572 3573 toff = offset + (sc->bge_tx_saved_considx * sizeof (struct bge_tx_bd)); 3574 3575 if (tosync < 0) { 3576 tlen = (BGE_TX_RING_CNT - sc->bge_tx_saved_considx) * 3577 sizeof (struct bge_tx_bd); 3578 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 3579 toff, tlen, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 3580 tosync = -tosync; 3581 } 3582 3583 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 3584 offset, tosync * sizeof (struct bge_tx_bd), 3585 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 3586 3587 /* 3588 * Go through our tx ring and free mbufs for those 3589 * frames that have been sent. 3590 */ 3591 while (sc->bge_tx_saved_considx != 3592 sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx) { 3593 uint32_t idx = 0; 3594 3595 idx = sc->bge_tx_saved_considx; 3596 cur_tx = &sc->bge_rdata->bge_tx_ring[idx]; 3597 if (cur_tx->bge_flags & BGE_TXBDFLAG_END) 3598 ifp->if_opackets++; 3599 m = sc->bge_cdata.bge_tx_chain[idx]; 3600 if (m != NULL) { 3601 sc->bge_cdata.bge_tx_chain[idx] = NULL; 3602 dma = sc->txdma[idx]; 3603 bus_dmamap_sync(sc->bge_dmatag, dma->dmamap, 0, 3604 dma->dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 3605 bus_dmamap_unload(sc->bge_dmatag, dma->dmamap); 3606 SLIST_INSERT_HEAD(&sc->txdma_list, dma, link); 3607 sc->txdma[idx] = NULL; 3608 3609 m_freem(m); 3610 } 3611 sc->bge_txcnt--; 3612 BGE_INC(sc->bge_tx_saved_considx, BGE_TX_RING_CNT); 3613 ifp->if_timer = 0; 3614 } 3615 3616 if (cur_tx != NULL) 3617 ifp->if_flags &= ~IFF_OACTIVE; 3618 } 3619 3620 static int 3621 bge_intr(void *xsc) 3622 { 3623 struct bge_softc *sc; 3624 struct ifnet *ifp; 3625 uint32_t statusword; 3626 3627 sc = xsc; 3628 ifp = &sc->ethercom.ec_if; 3629 3630 /* It is possible for the interrupt to arrive before 3631 * the status block is updated prior to the interrupt. 3632 * Reading the PCI State register will confirm whether the 3633 * interrupt is ours and will flush the status block. 3634 */ 3635 3636 /* read status word from status block */ 3637 statusword = sc->bge_rdata->bge_status_block.bge_status; 3638 3639 if ((statusword & BGE_STATFLAG_UPDATED) || 3640 (!(pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_PCISTATE) & 3641 BGE_PCISTATE_INTR_NOT_ACTIVE))) { 3642 /* Ack interrupt and stop others from occuring. */ 3643 bge_writembx_flush(sc, BGE_MBX_IRQ0_LO, 1); 3644 3645 BGE_EVCNT_INCR(sc->bge_ev_intr); 3646 3647 /* clear status word */ 3648 sc->bge_rdata->bge_status_block.bge_status = 0; 3649 3650 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 3651 statusword & BGE_STATFLAG_LINKSTATE_CHANGED || 3652 BGE_STS_BIT(sc, BGE_STS_LINK_EVT)) 3653 bge_link_upd(sc); 3654 3655 if (ifp->if_flags & IFF_RUNNING) { 3656 /* Check RX return ring producer/consumer */ 3657 bge_rxeof(sc); 3658 3659 /* Check TX ring producer/consumer */ 3660 bge_txeof(sc); 3661 } 3662 3663 if (sc->bge_pending_rxintr_change) { 3664 uint32_t rx_ticks = sc->bge_rx_coal_ticks; 3665 uint32_t rx_bds = sc->bge_rx_max_coal_bds; 3666 uint32_t junk; 3667 3668 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, rx_ticks); 3669 DELAY(10); 3670 junk = CSR_READ_4(sc, BGE_HCC_RX_COAL_TICKS); 3671 3672 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, rx_bds); 3673 DELAY(10); 3674 junk = CSR_READ_4(sc, BGE_HCC_RX_MAX_COAL_BDS); 3675 3676 sc->bge_pending_rxintr_change = 0; 3677 } 3678 bge_handle_events(sc); 3679 3680 /* Re-enable interrupts. */ 3681 bge_writembx_flush(sc, BGE_MBX_IRQ0_LO, 0); 3682 3683 if (ifp->if_flags & IFF_RUNNING && !IFQ_IS_EMPTY(&ifp->if_snd)) 3684 bge_start(ifp); 3685 3686 return 1; 3687 } else 3688 return 0; 3689 } 3690 3691 static void 3692 bge_asf_driver_up(struct bge_softc *sc) 3693 { 3694 if (sc->bge_asf_mode & ASF_STACKUP) { 3695 /* Send ASF heartbeat aprox. every 2s */ 3696 if (sc->bge_asf_count) 3697 sc->bge_asf_count --; 3698 else { 3699 sc->bge_asf_count = 2; 3700 bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM_FW, 3701 BGE_FW_DRV_ALIVE); 3702 bge_writemem_ind(sc, BGE_SOFTWARE_GENNCOMM_FW_LEN, 4); 3703 bge_writemem_ind(sc, BGE_SOFTWARE_GENNCOMM_FW_DATA, 3); 3704 CSR_WRITE_4_FLUSH(sc, BGE_CPU_EVENT, 3705 CSR_READ_4(sc, BGE_CPU_EVENT) | (1 << 14)); 3706 } 3707 } 3708 } 3709 3710 static void 3711 bge_tick(void *xsc) 3712 { 3713 struct bge_softc *sc = xsc; 3714 struct mii_data *mii = &sc->bge_mii; 3715 int s; 3716 3717 s = splnet(); 3718 3719 if (BGE_IS_5705_PLUS(sc)) 3720 bge_stats_update_regs(sc); 3721 else 3722 bge_stats_update(sc); 3723 3724 if (sc->bge_flags & BGE_PHY_FIBER_TBI) { 3725 /* 3726 * Since in TBI mode auto-polling can't be used we should poll 3727 * link status manually. Here we register pending link event 3728 * and trigger interrupt. 3729 */ 3730 BGE_STS_SETBIT(sc, BGE_STS_LINK_EVT); 3731 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET); 3732 } else { 3733 /* 3734 * Do not touch PHY if we have link up. This could break 3735 * IPMI/ASF mode or produce extra input errors. 3736 * (extra input errors was reported for bcm5701 & bcm5704). 3737 */ 3738 if (!BGE_STS_BIT(sc, BGE_STS_LINK)) 3739 mii_tick(mii); 3740 } 3741 3742 callout_reset(&sc->bge_timeout, hz, bge_tick, sc); 3743 3744 splx(s); 3745 } 3746 3747 static void 3748 bge_stats_update_regs(struct bge_softc *sc) 3749 { 3750 struct ifnet *ifp = &sc->ethercom.ec_if; 3751 3752 ifp->if_collisions += CSR_READ_4(sc, BGE_MAC_STATS + 3753 offsetof(struct bge_mac_stats_regs, etherStatsCollisions)); 3754 3755 ifp->if_ierrors += CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_DROPS); 3756 ifp->if_ierrors += CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_ERRORS); 3757 ifp->if_ierrors += CSR_READ_4(sc, BGE_RXLP_LOCSTAT_OUT_OF_BDS); 3758 } 3759 3760 static void 3761 bge_stats_update(struct bge_softc *sc) 3762 { 3763 struct ifnet *ifp = &sc->ethercom.ec_if; 3764 bus_size_t stats = BGE_MEMWIN_START + BGE_STATS_BLOCK; 3765 3766 #define READ_STAT(sc, stats, stat) \ 3767 CSR_READ_4(sc, stats + offsetof(struct bge_stats, stat)) 3768 3769 ifp->if_collisions += 3770 (READ_STAT(sc, stats, dot3StatsSingleCollisionFrames.bge_addr_lo) + 3771 READ_STAT(sc, stats, dot3StatsMultipleCollisionFrames.bge_addr_lo) + 3772 READ_STAT(sc, stats, dot3StatsExcessiveCollisions.bge_addr_lo) + 3773 READ_STAT(sc, stats, dot3StatsLateCollisions.bge_addr_lo)) - 3774 ifp->if_collisions; 3775 3776 BGE_EVCNT_UPD(sc->bge_ev_tx_xoff, 3777 READ_STAT(sc, stats, outXoffSent.bge_addr_lo)); 3778 BGE_EVCNT_UPD(sc->bge_ev_tx_xon, 3779 READ_STAT(sc, stats, outXonSent.bge_addr_lo)); 3780 BGE_EVCNT_UPD(sc->bge_ev_rx_xoff, 3781 READ_STAT(sc, stats, 3782 xoffPauseFramesReceived.bge_addr_lo)); 3783 BGE_EVCNT_UPD(sc->bge_ev_rx_xon, 3784 READ_STAT(sc, stats, xonPauseFramesReceived.bge_addr_lo)); 3785 BGE_EVCNT_UPD(sc->bge_ev_rx_macctl, 3786 READ_STAT(sc, stats, 3787 macControlFramesReceived.bge_addr_lo)); 3788 BGE_EVCNT_UPD(sc->bge_ev_xoffentered, 3789 READ_STAT(sc, stats, xoffStateEntered.bge_addr_lo)); 3790 3791 #undef READ_STAT 3792 3793 #ifdef notdef 3794 ifp->if_collisions += 3795 (sc->bge_rdata->bge_info.bge_stats.dot3StatsSingleCollisionFrames + 3796 sc->bge_rdata->bge_info.bge_stats.dot3StatsMultipleCollisionFrames + 3797 sc->bge_rdata->bge_info.bge_stats.dot3StatsExcessiveCollisions + 3798 sc->bge_rdata->bge_info.bge_stats.dot3StatsLateCollisions) - 3799 ifp->if_collisions; 3800 #endif 3801 } 3802 3803 /* 3804 * Pad outbound frame to ETHER_MIN_NOPAD for an unusual reason. 3805 * The bge hardware will pad out Tx runts to ETHER_MIN_NOPAD, 3806 * but when such padded frames employ the bge IP/TCP checksum offload, 3807 * the hardware checksum assist gives incorrect results (possibly 3808 * from incorporating its own padding into the UDP/TCP checksum; who knows). 3809 * If we pad such runts with zeros, the onboard checksum comes out correct. 3810 */ 3811 static inline int 3812 bge_cksum_pad(struct mbuf *pkt) 3813 { 3814 struct mbuf *last = NULL; 3815 int padlen; 3816 3817 padlen = ETHER_MIN_NOPAD - pkt->m_pkthdr.len; 3818 3819 /* if there's only the packet-header and we can pad there, use it. */ 3820 if (pkt->m_pkthdr.len == pkt->m_len && 3821 M_TRAILINGSPACE(pkt) >= padlen) { 3822 last = pkt; 3823 } else { 3824 /* 3825 * Walk packet chain to find last mbuf. We will either 3826 * pad there, or append a new mbuf and pad it 3827 * (thus perhaps avoiding the bcm5700 dma-min bug). 3828 */ 3829 for (last = pkt; last->m_next != NULL; last = last->m_next) { 3830 continue; /* do nothing */ 3831 } 3832 3833 /* `last' now points to last in chain. */ 3834 if (M_TRAILINGSPACE(last) < padlen) { 3835 /* Allocate new empty mbuf, pad it. Compact later. */ 3836 struct mbuf *n; 3837 MGET(n, M_DONTWAIT, MT_DATA); 3838 if (n == NULL) 3839 return ENOBUFS; 3840 n->m_len = 0; 3841 last->m_next = n; 3842 last = n; 3843 } 3844 } 3845 3846 KDASSERT(!M_READONLY(last)); 3847 KDASSERT(M_TRAILINGSPACE(last) >= padlen); 3848 3849 /* Now zero the pad area, to avoid the bge cksum-assist bug */ 3850 memset(mtod(last, char *) + last->m_len, 0, padlen); 3851 last->m_len += padlen; 3852 pkt->m_pkthdr.len += padlen; 3853 return 0; 3854 } 3855 3856 /* 3857 * Compact outbound packets to avoid bug with DMA segments less than 8 bytes. 3858 */ 3859 static inline int 3860 bge_compact_dma_runt(struct mbuf *pkt) 3861 { 3862 struct mbuf *m, *prev; 3863 int totlen, prevlen; 3864 3865 prev = NULL; 3866 totlen = 0; 3867 prevlen = -1; 3868 3869 for (m = pkt; m != NULL; prev = m,m = m->m_next) { 3870 int mlen = m->m_len; 3871 int shortfall = 8 - mlen ; 3872 3873 totlen += mlen; 3874 if (mlen == 0) 3875 continue; 3876 if (mlen >= 8) 3877 continue; 3878 3879 /* If we get here, mbuf data is too small for DMA engine. 3880 * Try to fix by shuffling data to prev or next in chain. 3881 * If that fails, do a compacting deep-copy of the whole chain. 3882 */ 3883 3884 /* Internal frag. If fits in prev, copy it there. */ 3885 if (prev && M_TRAILINGSPACE(prev) >= m->m_len) { 3886 memcpy(prev->m_data + prev->m_len, m->m_data, mlen); 3887 prev->m_len += mlen; 3888 m->m_len = 0; 3889 /* XXX stitch chain */ 3890 prev->m_next = m_free(m); 3891 m = prev; 3892 continue; 3893 } 3894 else if (m->m_next != NULL && 3895 M_TRAILINGSPACE(m) >= shortfall && 3896 m->m_next->m_len >= (8 + shortfall)) { 3897 /* m is writable and have enough data in next, pull up. */ 3898 3899 memcpy(m->m_data + m->m_len, m->m_next->m_data, 3900 shortfall); 3901 m->m_len += shortfall; 3902 m->m_next->m_len -= shortfall; 3903 m->m_next->m_data += shortfall; 3904 } 3905 else if (m->m_next == NULL || 1) { 3906 /* Got a runt at the very end of the packet. 3907 * borrow data from the tail of the preceding mbuf and 3908 * update its length in-place. (The original data is still 3909 * valid, so we can do this even if prev is not writable.) 3910 */ 3911 3912 /* if we'd make prev a runt, just move all of its data. */ 3913 KASSERT(prev != NULL /*, ("runt but null PREV")*/); 3914 KASSERT(prev->m_len >= 8 /*, ("runt prev")*/); 3915 3916 if ((prev->m_len - shortfall) < 8) 3917 shortfall = prev->m_len; 3918 3919 #ifdef notyet /* just do the safe slow thing for now */ 3920 if (!M_READONLY(m)) { 3921 if (M_LEADINGSPACE(m) < shorfall) { 3922 void *m_dat; 3923 m_dat = (m->m_flags & M_PKTHDR) ? 3924 m->m_pktdat : m->dat; 3925 memmove(m_dat, mtod(m, void*), m->m_len); 3926 m->m_data = m_dat; 3927 } 3928 } else 3929 #endif /* just do the safe slow thing */ 3930 { 3931 struct mbuf * n = NULL; 3932 int newprevlen = prev->m_len - shortfall; 3933 3934 MGET(n, M_NOWAIT, MT_DATA); 3935 if (n == NULL) 3936 return ENOBUFS; 3937 KASSERT(m->m_len + shortfall < MLEN 3938 /*, 3939 ("runt %d +prev %d too big\n", m->m_len, shortfall)*/); 3940 3941 /* first copy the data we're stealing from prev */ 3942 memcpy(n->m_data, prev->m_data + newprevlen, 3943 shortfall); 3944 3945 /* update prev->m_len accordingly */ 3946 prev->m_len -= shortfall; 3947 3948 /* copy data from runt m */ 3949 memcpy(n->m_data + shortfall, m->m_data, 3950 m->m_len); 3951 3952 /* n holds what we stole from prev, plus m */ 3953 n->m_len = shortfall + m->m_len; 3954 3955 /* stitch n into chain and free m */ 3956 n->m_next = m->m_next; 3957 prev->m_next = n; 3958 /* KASSERT(m->m_next == NULL); */ 3959 m->m_next = NULL; 3960 m_free(m); 3961 m = n; /* for continuing loop */ 3962 } 3963 } 3964 prevlen = m->m_len; 3965 } 3966 return 0; 3967 } 3968 3969 /* 3970 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data 3971 * pointers to descriptors. 3972 */ 3973 static int 3974 bge_encap(struct bge_softc *sc, struct mbuf *m_head, uint32_t *txidx) 3975 { 3976 struct bge_tx_bd *f = NULL; 3977 uint32_t frag, cur; 3978 uint16_t csum_flags = 0; 3979 uint16_t txbd_tso_flags = 0; 3980 struct txdmamap_pool_entry *dma; 3981 bus_dmamap_t dmamap; 3982 int i = 0; 3983 struct m_tag *mtag; 3984 int use_tso, maxsegsize, error; 3985 3986 cur = frag = *txidx; 3987 3988 if (m_head->m_pkthdr.csum_flags) { 3989 if (m_head->m_pkthdr.csum_flags & M_CSUM_IPv4) 3990 csum_flags |= BGE_TXBDFLAG_IP_CSUM; 3991 if (m_head->m_pkthdr.csum_flags & (M_CSUM_TCPv4|M_CSUM_UDPv4)) 3992 csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM; 3993 } 3994 3995 /* 3996 * If we were asked to do an outboard checksum, and the NIC 3997 * has the bug where it sometimes adds in the Ethernet padding, 3998 * explicitly pad with zeros so the cksum will be correct either way. 3999 * (For now, do this for all chip versions, until newer 4000 * are confirmed to not require the workaround.) 4001 */ 4002 if ((csum_flags & BGE_TXBDFLAG_TCP_UDP_CSUM) == 0 || 4003 #ifdef notyet 4004 (sc->bge_quirks & BGE_QUIRK_SHORT_CKSUM_BUG) == 0 || 4005 #endif 4006 m_head->m_pkthdr.len >= ETHER_MIN_NOPAD) 4007 goto check_dma_bug; 4008 4009 if (bge_cksum_pad(m_head) != 0) 4010 return ENOBUFS; 4011 4012 check_dma_bug: 4013 if (!(BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX)) 4014 goto doit; 4015 4016 /* 4017 * bcm5700 Revision B silicon cannot handle DMA descriptors with 4018 * less than eight bytes. If we encounter a teeny mbuf 4019 * at the end of a chain, we can pad. Otherwise, copy. 4020 */ 4021 if (bge_compact_dma_runt(m_head) != 0) 4022 return ENOBUFS; 4023 4024 doit: 4025 dma = SLIST_FIRST(&sc->txdma_list); 4026 if (dma == NULL) 4027 return ENOBUFS; 4028 dmamap = dma->dmamap; 4029 4030 /* 4031 * Set up any necessary TSO state before we start packing... 4032 */ 4033 use_tso = (m_head->m_pkthdr.csum_flags & M_CSUM_TSOv4) != 0; 4034 if (!use_tso) { 4035 maxsegsize = 0; 4036 } else { /* TSO setup */ 4037 unsigned mss; 4038 struct ether_header *eh; 4039 unsigned ip_tcp_hlen, iptcp_opt_words, tcp_seg_flags, offset; 4040 struct mbuf * m0 = m_head; 4041 struct ip *ip; 4042 struct tcphdr *th; 4043 int iphl, hlen; 4044 4045 /* 4046 * XXX It would be nice if the mbuf pkthdr had offset 4047 * fields for the protocol headers. 4048 */ 4049 4050 eh = mtod(m0, struct ether_header *); 4051 switch (htons(eh->ether_type)) { 4052 case ETHERTYPE_IP: 4053 offset = ETHER_HDR_LEN; 4054 break; 4055 4056 case ETHERTYPE_VLAN: 4057 offset = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 4058 break; 4059 4060 default: 4061 /* 4062 * Don't support this protocol or encapsulation. 4063 */ 4064 return ENOBUFS; 4065 } 4066 4067 /* 4068 * TCP/IP headers are in the first mbuf; we can do 4069 * this the easy way. 4070 */ 4071 iphl = M_CSUM_DATA_IPv4_IPHL(m0->m_pkthdr.csum_data); 4072 hlen = iphl + offset; 4073 if (__predict_false(m0->m_len < 4074 (hlen + sizeof(struct tcphdr)))) { 4075 4076 aprint_debug_dev(sc->bge_dev, 4077 "TSO: hard case m0->m_len == %d < ip/tcp hlen %zd," 4078 "not handled yet\n", 4079 m0->m_len, hlen+ sizeof(struct tcphdr)); 4080 #ifdef NOTYET 4081 /* 4082 * XXX jonathan (at) NetBSD.org: untested. 4083 * how to force this branch to be taken? 4084 */ 4085 BGE_EVCNT_INCR(&sc->sc_ev_txtsopain); 4086 4087 m_copydata(m0, offset, sizeof(ip), &ip); 4088 m_copydata(m0, hlen, sizeof(th), &th); 4089 4090 ip.ip_len = 0; 4091 4092 m_copyback(m0, hlen + offsetof(struct ip, ip_len), 4093 sizeof(ip.ip_len), &ip.ip_len); 4094 4095 th.th_sum = in_cksum_phdr(ip.ip_src.s_addr, 4096 ip.ip_dst.s_addr, htons(IPPROTO_TCP)); 4097 4098 m_copyback(m0, hlen + offsetof(struct tcphdr, th_sum), 4099 sizeof(th.th_sum), &th.th_sum); 4100 4101 hlen += th.th_off << 2; 4102 iptcp_opt_words = hlen; 4103 #else 4104 /* 4105 * if_wm "hard" case not yet supported, can we not 4106 * mandate it out of existence? 4107 */ 4108 (void) ip; (void)th; (void) ip_tcp_hlen; 4109 4110 return ENOBUFS; 4111 #endif 4112 } else { 4113 ip = (struct ip *) (mtod(m0, char *) + offset); 4114 th = (struct tcphdr *) (mtod(m0, char *) + hlen); 4115 ip_tcp_hlen = iphl + (th->th_off << 2); 4116 4117 /* Total IP/TCP options, in 32-bit words */ 4118 iptcp_opt_words = (ip_tcp_hlen 4119 - sizeof(struct tcphdr) 4120 - sizeof(struct ip)) >> 2; 4121 } 4122 if (BGE_IS_575X_PLUS(sc)) { 4123 th->th_sum = 0; 4124 csum_flags &= ~(BGE_TXBDFLAG_TCP_UDP_CSUM); 4125 } else { 4126 /* 4127 * XXX jonathan (at) NetBSD.org: 5705 untested. 4128 * Requires TSO firmware patch for 5701/5703/5704. 4129 */ 4130 th->th_sum = in_cksum_phdr(ip->ip_src.s_addr, 4131 ip->ip_dst.s_addr, htons(IPPROTO_TCP)); 4132 } 4133 4134 mss = m_head->m_pkthdr.segsz; 4135 txbd_tso_flags |= 4136 BGE_TXBDFLAG_CPU_PRE_DMA | 4137 BGE_TXBDFLAG_CPU_POST_DMA; 4138 4139 /* 4140 * Our NIC TSO-assist assumes TSO has standard, optionless 4141 * IPv4 and TCP headers, which total 40 bytes. By default, 4142 * the NIC copies 40 bytes of IP/TCP header from the 4143 * supplied header into the IP/TCP header portion of 4144 * each post-TSO-segment. If the supplied packet has IP or 4145 * TCP options, we need to tell the NIC to copy those extra 4146 * bytes into each post-TSO header, in addition to the normal 4147 * 40-byte IP/TCP header (and to leave space accordingly). 4148 * Unfortunately, the driver encoding of option length 4149 * varies across different ASIC families. 4150 */ 4151 tcp_seg_flags = 0; 4152 if (iptcp_opt_words) { 4153 if (BGE_IS_5705_PLUS(sc)) { 4154 tcp_seg_flags = 4155 iptcp_opt_words << 11; 4156 } else { 4157 txbd_tso_flags |= 4158 iptcp_opt_words << 12; 4159 } 4160 } 4161 maxsegsize = mss | tcp_seg_flags; 4162 ip->ip_len = htons(mss + ip_tcp_hlen); 4163 4164 } /* TSO setup */ 4165 4166 /* 4167 * Start packing the mbufs in this chain into 4168 * the fragment pointers. Stop when we run out 4169 * of fragments or hit the end of the mbuf chain. 4170 */ 4171 error = bus_dmamap_load_mbuf(sc->bge_dmatag, dmamap, m_head, 4172 BUS_DMA_NOWAIT); 4173 if (error) 4174 return ENOBUFS; 4175 /* 4176 * Sanity check: avoid coming within 16 descriptors 4177 * of the end of the ring. 4178 */ 4179 if (dmamap->dm_nsegs > (BGE_TX_RING_CNT - sc->bge_txcnt - 16)) { 4180 BGE_TSO_PRINTF(("%s: " 4181 " dmamap_load_mbuf too close to ring wrap\n", 4182 device_xname(sc->bge_dev))); 4183 goto fail_unload; 4184 } 4185 4186 mtag = sc->ethercom.ec_nvlans ? 4187 m_tag_find(m_head, PACKET_TAG_VLAN, NULL) : NULL; 4188 4189 4190 /* Iterate over dmap-map fragments. */ 4191 for (i = 0; i < dmamap->dm_nsegs; i++) { 4192 f = &sc->bge_rdata->bge_tx_ring[frag]; 4193 if (sc->bge_cdata.bge_tx_chain[frag] != NULL) 4194 break; 4195 4196 BGE_HOSTADDR(f->bge_addr, dmamap->dm_segs[i].ds_addr); 4197 f->bge_len = dmamap->dm_segs[i].ds_len; 4198 4199 /* 4200 * For 5751 and follow-ons, for TSO we must turn 4201 * off checksum-assist flag in the tx-descr, and 4202 * supply the ASIC-revision-specific encoding 4203 * of TSO flags and segsize. 4204 */ 4205 if (use_tso) { 4206 if (BGE_IS_575X_PLUS(sc) || i == 0) { 4207 f->bge_rsvd = maxsegsize; 4208 f->bge_flags = csum_flags | txbd_tso_flags; 4209 } else { 4210 f->bge_rsvd = 0; 4211 f->bge_flags = 4212 (csum_flags | txbd_tso_flags) & 0x0fff; 4213 } 4214 } else { 4215 f->bge_rsvd = 0; 4216 f->bge_flags = csum_flags; 4217 } 4218 4219 if (mtag != NULL) { 4220 f->bge_flags |= BGE_TXBDFLAG_VLAN_TAG; 4221 f->bge_vlan_tag = VLAN_TAG_VALUE(mtag); 4222 } else { 4223 f->bge_vlan_tag = 0; 4224 } 4225 cur = frag; 4226 BGE_INC(frag, BGE_TX_RING_CNT); 4227 } 4228 4229 if (i < dmamap->dm_nsegs) { 4230 BGE_TSO_PRINTF(("%s: reached %d < dm_nsegs %d\n", 4231 device_xname(sc->bge_dev), i, dmamap->dm_nsegs)); 4232 goto fail_unload; 4233 } 4234 4235 bus_dmamap_sync(sc->bge_dmatag, dmamap, 0, dmamap->dm_mapsize, 4236 BUS_DMASYNC_PREWRITE); 4237 4238 if (frag == sc->bge_tx_saved_considx) { 4239 BGE_TSO_PRINTF(("%s: frag %d = wrapped id %d?\n", 4240 device_xname(sc->bge_dev), frag, sc->bge_tx_saved_considx)); 4241 4242 goto fail_unload; 4243 } 4244 4245 sc->bge_rdata->bge_tx_ring[cur].bge_flags |= BGE_TXBDFLAG_END; 4246 sc->bge_cdata.bge_tx_chain[cur] = m_head; 4247 SLIST_REMOVE_HEAD(&sc->txdma_list, link); 4248 sc->txdma[cur] = dma; 4249 sc->bge_txcnt += dmamap->dm_nsegs; 4250 4251 *txidx = frag; 4252 4253 return 0; 4254 4255 fail_unload: 4256 bus_dmamap_unload(sc->bge_dmatag, dmamap); 4257 4258 return ENOBUFS; 4259 } 4260 4261 /* 4262 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 4263 * to the mbuf data regions directly in the transmit descriptors. 4264 */ 4265 static void 4266 bge_start(struct ifnet *ifp) 4267 { 4268 struct bge_softc *sc; 4269 struct mbuf *m_head = NULL; 4270 uint32_t prodidx; 4271 int pkts = 0; 4272 4273 sc = ifp->if_softc; 4274 4275 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 4276 return; 4277 4278 prodidx = sc->bge_tx_prodidx; 4279 4280 while (sc->bge_cdata.bge_tx_chain[prodidx] == NULL) { 4281 IFQ_POLL(&ifp->if_snd, m_head); 4282 if (m_head == NULL) 4283 break; 4284 4285 #if 0 4286 /* 4287 * XXX 4288 * safety overkill. If this is a fragmented packet chain 4289 * with delayed TCP/UDP checksums, then only encapsulate 4290 * it if we have enough descriptors to handle the entire 4291 * chain at once. 4292 * (paranoia -- may not actually be needed) 4293 */ 4294 if (m_head->m_flags & M_FIRSTFRAG && 4295 m_head->m_pkthdr.csum_flags & (CSUM_DELAY_DATA)) { 4296 if ((BGE_TX_RING_CNT - sc->bge_txcnt) < 4297 M_CSUM_DATA_IPv4_OFFSET(m_head->m_pkthdr.csum_data) + 16) { 4298 ifp->if_flags |= IFF_OACTIVE; 4299 break; 4300 } 4301 } 4302 #endif 4303 4304 /* 4305 * Pack the data into the transmit ring. If we 4306 * don't have room, set the OACTIVE flag and wait 4307 * for the NIC to drain the ring. 4308 */ 4309 if (bge_encap(sc, m_head, &prodidx)) { 4310 ifp->if_flags |= IFF_OACTIVE; 4311 break; 4312 } 4313 4314 /* now we are committed to transmit the packet */ 4315 IFQ_DEQUEUE(&ifp->if_snd, m_head); 4316 pkts++; 4317 4318 /* 4319 * If there's a BPF listener, bounce a copy of this frame 4320 * to him. 4321 */ 4322 bpf_mtap(ifp, m_head); 4323 } 4324 if (pkts == 0) 4325 return; 4326 4327 /* Transmit */ 4328 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); 4329 /* 5700 b2 errata */ 4330 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX) 4331 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); 4332 4333 sc->bge_tx_prodidx = prodidx; 4334 4335 /* 4336 * Set a timeout in case the chip goes out to lunch. 4337 */ 4338 ifp->if_timer = 5; 4339 } 4340 4341 static int 4342 bge_init(struct ifnet *ifp) 4343 { 4344 struct bge_softc *sc = ifp->if_softc; 4345 const uint16_t *m; 4346 uint32_t mode; 4347 int s, error = 0; 4348 4349 s = splnet(); 4350 4351 ifp = &sc->ethercom.ec_if; 4352 4353 /* Cancel pending I/O and flush buffers. */ 4354 bge_stop(ifp, 0); 4355 4356 bge_stop_fw(sc); 4357 bge_sig_pre_reset(sc, BGE_RESET_START); 4358 bge_reset(sc); 4359 bge_sig_legacy(sc, BGE_RESET_START); 4360 bge_sig_post_reset(sc, BGE_RESET_START); 4361 4362 bge_chipinit(sc); 4363 4364 /* 4365 * Init the various state machines, ring 4366 * control blocks and firmware. 4367 */ 4368 error = bge_blockinit(sc); 4369 if (error != 0) { 4370 aprint_error_dev(sc->bge_dev, "initialization error %d\n", 4371 error); 4372 splx(s); 4373 return error; 4374 } 4375 4376 ifp = &sc->ethercom.ec_if; 4377 4378 /* Specify MTU. */ 4379 CSR_WRITE_4(sc, BGE_RX_MTU, ifp->if_mtu + 4380 ETHER_HDR_LEN + ETHER_CRC_LEN + ETHER_VLAN_ENCAP_LEN); 4381 4382 /* Load our MAC address. */ 4383 m = (const uint16_t *)&(CLLADDR(ifp->if_sadl)[0]); 4384 CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0])); 4385 CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, (htons(m[1]) << 16) | htons(m[2])); 4386 4387 /* Enable or disable promiscuous mode as needed. */ 4388 if (ifp->if_flags & IFF_PROMISC) 4389 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 4390 else 4391 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 4392 4393 /* Program multicast filter. */ 4394 bge_setmulti(sc); 4395 4396 /* Init RX ring. */ 4397 bge_init_rx_ring_std(sc); 4398 4399 /* 4400 * Workaround for a bug in 5705 ASIC rev A0. Poll the NIC's 4401 * memory to insure that the chip has in fact read the first 4402 * entry of the ring. 4403 */ 4404 if (sc->bge_chipid == BGE_CHIPID_BCM5705_A0) { 4405 uint32_t v, i; 4406 for (i = 0; i < 10; i++) { 4407 DELAY(20); 4408 v = bge_readmem_ind(sc, BGE_STD_RX_RINGS + 8); 4409 if (v == (MCLBYTES - ETHER_ALIGN)) 4410 break; 4411 } 4412 if (i == 10) 4413 aprint_error_dev(sc->bge_dev, 4414 "5705 A0 chip failed to load RX ring\n"); 4415 } 4416 4417 /* Init jumbo RX ring. */ 4418 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 4419 bge_init_rx_ring_jumbo(sc); 4420 4421 /* Init our RX return ring index */ 4422 sc->bge_rx_saved_considx = 0; 4423 4424 /* Init TX ring. */ 4425 bge_init_tx_ring(sc); 4426 4427 /* Enable TX MAC state machine lockup fix. */ 4428 mode = CSR_READ_4(sc, BGE_TX_MODE); 4429 if (BGE_IS_5755_PLUS(sc) || 4430 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 4431 mode |= BGE_TXMODE_MBUF_LOCKUP_FIX; 4432 4433 /* Turn on transmitter */ 4434 CSR_WRITE_4_FLUSH(sc, BGE_TX_MODE, mode | BGE_TXMODE_ENABLE); 4435 DELAY(100); 4436 4437 /* Turn on receiver */ 4438 BGE_SETBIT_FLUSH(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE); 4439 DELAY(10); 4440 4441 CSR_WRITE_4(sc, BGE_MAX_RX_FRAME_LOWAT, 2); 4442 4443 /* Tell firmware we're alive. */ 4444 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 4445 4446 /* Enable host interrupts. */ 4447 PCI_SETBIT(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MISC_CTL, 4448 BGE_PCIMISCCTL_CLEAR_INTA); 4449 PCI_CLRBIT(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MISC_CTL, 4450 BGE_PCIMISCCTL_MASK_PCI_INTR); 4451 bge_writembx_flush(sc, BGE_MBX_IRQ0_LO, 0); 4452 4453 if ((error = bge_ifmedia_upd(ifp)) != 0) 4454 goto out; 4455 4456 ifp->if_flags |= IFF_RUNNING; 4457 ifp->if_flags &= ~IFF_OACTIVE; 4458 4459 callout_reset(&sc->bge_timeout, hz, bge_tick, sc); 4460 4461 out: 4462 sc->bge_if_flags = ifp->if_flags; 4463 splx(s); 4464 4465 return error; 4466 } 4467 4468 /* 4469 * Set media options. 4470 */ 4471 static int 4472 bge_ifmedia_upd(struct ifnet *ifp) 4473 { 4474 struct bge_softc *sc = ifp->if_softc; 4475 struct mii_data *mii = &sc->bge_mii; 4476 struct ifmedia *ifm = &sc->bge_ifmedia; 4477 int rc; 4478 4479 /* If this is a 1000baseX NIC, enable the TBI port. */ 4480 if (sc->bge_flags & BGE_PHY_FIBER_TBI) { 4481 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 4482 return EINVAL; 4483 switch (IFM_SUBTYPE(ifm->ifm_media)) { 4484 case IFM_AUTO: 4485 /* 4486 * The BCM5704 ASIC appears to have a special 4487 * mechanism for programming the autoneg 4488 * advertisement registers in TBI mode. 4489 */ 4490 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) { 4491 uint32_t sgdig; 4492 sgdig = CSR_READ_4(sc, BGE_SGDIG_STS); 4493 if (sgdig & BGE_SGDIGSTS_DONE) { 4494 CSR_WRITE_4(sc, BGE_TX_TBI_AUTONEG, 0); 4495 sgdig = CSR_READ_4(sc, BGE_SGDIG_CFG); 4496 sgdig |= BGE_SGDIGCFG_AUTO | 4497 BGE_SGDIGCFG_PAUSE_CAP | 4498 BGE_SGDIGCFG_ASYM_PAUSE; 4499 CSR_WRITE_4_FLUSH(sc, BGE_SGDIG_CFG, 4500 sgdig | BGE_SGDIGCFG_SEND); 4501 DELAY(5); 4502 CSR_WRITE_4_FLUSH(sc, BGE_SGDIG_CFG, 4503 sgdig); 4504 } 4505 } 4506 break; 4507 case IFM_1000_SX: 4508 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 4509 BGE_CLRBIT(sc, BGE_MAC_MODE, 4510 BGE_MACMODE_HALF_DUPLEX); 4511 } else { 4512 BGE_SETBIT(sc, BGE_MAC_MODE, 4513 BGE_MACMODE_HALF_DUPLEX); 4514 } 4515 break; 4516 default: 4517 return EINVAL; 4518 } 4519 /* XXX 802.3x flow control for 1000BASE-SX */ 4520 return 0; 4521 } 4522 4523 BGE_STS_SETBIT(sc, BGE_STS_LINK_EVT); 4524 if ((rc = mii_mediachg(mii)) == ENXIO) 4525 return 0; 4526 4527 /* 4528 * Force an interrupt so that we will call bge_link_upd 4529 * if needed and clear any pending link state attention. 4530 * Without this we are not getting any further interrupts 4531 * for link state changes and thus will not UP the link and 4532 * not be able to send in bge_start. The only way to get 4533 * things working was to receive a packet and get a RX intr. 4534 */ 4535 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 4536 sc->bge_flags & BGE_IS_5788) 4537 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET); 4538 else 4539 BGE_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW); 4540 4541 return rc; 4542 } 4543 4544 /* 4545 * Report current media status. 4546 */ 4547 static void 4548 bge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 4549 { 4550 struct bge_softc *sc = ifp->if_softc; 4551 struct mii_data *mii = &sc->bge_mii; 4552 4553 if (sc->bge_flags & BGE_PHY_FIBER_TBI) { 4554 ifmr->ifm_status = IFM_AVALID; 4555 ifmr->ifm_active = IFM_ETHER; 4556 if (CSR_READ_4(sc, BGE_MAC_STS) & 4557 BGE_MACSTAT_TBI_PCS_SYNCHED) 4558 ifmr->ifm_status |= IFM_ACTIVE; 4559 ifmr->ifm_active |= IFM_1000_SX; 4560 if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX) 4561 ifmr->ifm_active |= IFM_HDX; 4562 else 4563 ifmr->ifm_active |= IFM_FDX; 4564 return; 4565 } 4566 4567 mii_pollstat(mii); 4568 ifmr->ifm_status = mii->mii_media_status; 4569 ifmr->ifm_active = (mii->mii_media_active & ~IFM_ETH_FMASK) | 4570 sc->bge_flowflags; 4571 } 4572 4573 static int 4574 bge_ifflags_cb(struct ethercom *ec) 4575 { 4576 struct ifnet *ifp = &ec->ec_if; 4577 struct bge_softc *sc = ifp->if_softc; 4578 int change = ifp->if_flags ^ sc->bge_if_flags; 4579 4580 if ((change & ~(IFF_CANTCHANGE|IFF_DEBUG)) != 0) 4581 return ENETRESET; 4582 else if ((change & (IFF_PROMISC | IFF_ALLMULTI)) == 0) 4583 return 0; 4584 4585 if ((ifp->if_flags & IFF_PROMISC) == 0) 4586 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 4587 else 4588 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 4589 4590 bge_setmulti(sc); 4591 4592 sc->bge_if_flags = ifp->if_flags; 4593 return 0; 4594 } 4595 4596 static int 4597 bge_ioctl(struct ifnet *ifp, u_long command, void *data) 4598 { 4599 struct bge_softc *sc = ifp->if_softc; 4600 struct ifreq *ifr = (struct ifreq *) data; 4601 int s, error = 0; 4602 struct mii_data *mii; 4603 4604 s = splnet(); 4605 4606 switch (command) { 4607 case SIOCSIFMEDIA: 4608 /* XXX Flow control is not supported for 1000BASE-SX */ 4609 if (sc->bge_flags & BGE_PHY_FIBER_TBI) { 4610 ifr->ifr_media &= ~IFM_ETH_FMASK; 4611 sc->bge_flowflags = 0; 4612 } 4613 4614 /* Flow control requires full-duplex mode. */ 4615 if (IFM_SUBTYPE(ifr->ifr_media) == IFM_AUTO || 4616 (ifr->ifr_media & IFM_FDX) == 0) { 4617 ifr->ifr_media &= ~IFM_ETH_FMASK; 4618 } 4619 if (IFM_SUBTYPE(ifr->ifr_media) != IFM_AUTO) { 4620 if ((ifr->ifr_media & IFM_ETH_FMASK) == IFM_FLOW) { 4621 /* We can do both TXPAUSE and RXPAUSE. */ 4622 ifr->ifr_media |= 4623 IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE; 4624 } 4625 sc->bge_flowflags = ifr->ifr_media & IFM_ETH_FMASK; 4626 } 4627 /* FALLTHROUGH */ 4628 case SIOCGIFMEDIA: 4629 if (sc->bge_flags & BGE_PHY_FIBER_TBI) { 4630 error = ifmedia_ioctl(ifp, ifr, &sc->bge_ifmedia, 4631 command); 4632 } else { 4633 mii = &sc->bge_mii; 4634 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, 4635 command); 4636 } 4637 break; 4638 default: 4639 if ((error = ether_ioctl(ifp, command, data)) != ENETRESET) 4640 break; 4641 4642 error = 0; 4643 4644 if (command != SIOCADDMULTI && command != SIOCDELMULTI) 4645 ; 4646 else if (ifp->if_flags & IFF_RUNNING) 4647 bge_setmulti(sc); 4648 break; 4649 } 4650 4651 splx(s); 4652 4653 return error; 4654 } 4655 4656 static void 4657 bge_watchdog(struct ifnet *ifp) 4658 { 4659 struct bge_softc *sc; 4660 4661 sc = ifp->if_softc; 4662 4663 aprint_error_dev(sc->bge_dev, "watchdog timeout -- resetting\n"); 4664 4665 ifp->if_flags &= ~IFF_RUNNING; 4666 bge_init(ifp); 4667 4668 ifp->if_oerrors++; 4669 } 4670 4671 static void 4672 bge_stop_block(struct bge_softc *sc, bus_addr_t reg, uint32_t bit) 4673 { 4674 int i; 4675 4676 BGE_CLRBIT_FLUSH(sc, reg, bit); 4677 4678 for (i = 0; i < 1000; i++) { 4679 if ((CSR_READ_4(sc, reg) & bit) == 0) 4680 return; 4681 delay(100); 4682 } 4683 4684 /* 4685 * Doesn't print only when the register is BGE_SRS_MODE. It occurs 4686 * on some environment (and once after boot?) 4687 */ 4688 if (reg != BGE_SRS_MODE) 4689 aprint_error_dev(sc->bge_dev, 4690 "block failed to stop: reg 0x%lx, bit 0x%08x\n", 4691 (u_long)reg, bit); 4692 } 4693 4694 /* 4695 * Stop the adapter and free any mbufs allocated to the 4696 * RX and TX lists. 4697 */ 4698 static void 4699 bge_stop(struct ifnet *ifp, int disable) 4700 { 4701 struct bge_softc *sc = ifp->if_softc; 4702 4703 callout_stop(&sc->bge_timeout); 4704 4705 /* 4706 * Tell firmware we're shutting down. 4707 */ 4708 bge_stop_fw(sc); 4709 bge_sig_pre_reset(sc, BGE_RESET_STOP); 4710 4711 /* Disable host interrupts. */ 4712 PCI_SETBIT(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MISC_CTL, 4713 BGE_PCIMISCCTL_MASK_PCI_INTR); 4714 bge_writembx_flush(sc, BGE_MBX_IRQ0_LO, 1); 4715 4716 /* 4717 * Disable all of the receiver blocks. 4718 */ 4719 bge_stop_block(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE); 4720 bge_stop_block(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 4721 bge_stop_block(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 4722 if (BGE_IS_5700_FAMILY(sc)) 4723 bge_stop_block(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 4724 bge_stop_block(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE); 4725 bge_stop_block(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 4726 bge_stop_block(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE); 4727 4728 /* 4729 * Disable all of the transmit blocks. 4730 */ 4731 bge_stop_block(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 4732 bge_stop_block(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 4733 bge_stop_block(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 4734 bge_stop_block(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE); 4735 bge_stop_block(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE); 4736 if (BGE_IS_5700_FAMILY(sc)) 4737 bge_stop_block(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 4738 bge_stop_block(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 4739 4740 /* 4741 * Shut down all of the memory managers and related 4742 * state machines. 4743 */ 4744 bge_stop_block(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE); 4745 bge_stop_block(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE); 4746 if (BGE_IS_5700_FAMILY(sc)) 4747 bge_stop_block(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 4748 4749 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 4750 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 4751 4752 if (BGE_IS_5700_FAMILY(sc)) { 4753 bge_stop_block(sc, BGE_BMAN_MODE, BGE_BMANMODE_ENABLE); 4754 bge_stop_block(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 4755 } 4756 4757 bge_reset(sc); 4758 bge_sig_legacy(sc, BGE_RESET_STOP); 4759 bge_sig_post_reset(sc, BGE_RESET_STOP); 4760 4761 /* 4762 * Keep the ASF firmware running if up. 4763 */ 4764 if (sc->bge_asf_mode & ASF_STACKUP) 4765 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 4766 else 4767 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 4768 4769 /* Free the RX lists. */ 4770 bge_free_rx_ring_std(sc); 4771 4772 /* Free jumbo RX list. */ 4773 if (BGE_IS_JUMBO_CAPABLE(sc)) 4774 bge_free_rx_ring_jumbo(sc); 4775 4776 /* Free TX buffers. */ 4777 bge_free_tx_ring(sc); 4778 4779 /* 4780 * Isolate/power down the PHY. 4781 */ 4782 if (!(sc->bge_flags & BGE_PHY_FIBER_TBI)) 4783 mii_down(&sc->bge_mii); 4784 4785 sc->bge_tx_saved_considx = BGE_TXCONS_UNSET; 4786 4787 /* Clear MAC's link state (PHY may still have link UP). */ 4788 BGE_STS_CLRBIT(sc, BGE_STS_LINK); 4789 4790 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 4791 } 4792 4793 static void 4794 bge_link_upd(struct bge_softc *sc) 4795 { 4796 struct ifnet *ifp = &sc->ethercom.ec_if; 4797 struct mii_data *mii = &sc->bge_mii; 4798 uint32_t status; 4799 int link; 4800 4801 /* Clear 'pending link event' flag */ 4802 BGE_STS_CLRBIT(sc, BGE_STS_LINK_EVT); 4803 4804 /* 4805 * Process link state changes. 4806 * Grrr. The link status word in the status block does 4807 * not work correctly on the BCM5700 rev AX and BX chips, 4808 * according to all available information. Hence, we have 4809 * to enable MII interrupts in order to properly obtain 4810 * async link changes. Unfortunately, this also means that 4811 * we have to read the MAC status register to detect link 4812 * changes, thereby adding an additional register access to 4813 * the interrupt handler. 4814 */ 4815 4816 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700) { 4817 status = CSR_READ_4(sc, BGE_MAC_STS); 4818 if (status & BGE_MACSTAT_MI_INTERRUPT) { 4819 mii_pollstat(mii); 4820 4821 if (!BGE_STS_BIT(sc, BGE_STS_LINK) && 4822 mii->mii_media_status & IFM_ACTIVE && 4823 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) 4824 BGE_STS_SETBIT(sc, BGE_STS_LINK); 4825 else if (BGE_STS_BIT(sc, BGE_STS_LINK) && 4826 (!(mii->mii_media_status & IFM_ACTIVE) || 4827 IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) 4828 BGE_STS_CLRBIT(sc, BGE_STS_LINK); 4829 4830 /* Clear the interrupt */ 4831 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, 4832 BGE_EVTENB_MI_INTERRUPT); 4833 bge_miibus_readreg(sc->bge_dev, 1, BRGPHY_MII_ISR); 4834 bge_miibus_writereg(sc->bge_dev, 1, BRGPHY_MII_IMR, 4835 BRGPHY_INTRS); 4836 } 4837 return; 4838 } 4839 4840 if (sc->bge_flags & BGE_PHY_FIBER_TBI) { 4841 status = CSR_READ_4(sc, BGE_MAC_STS); 4842 if (status & BGE_MACSTAT_TBI_PCS_SYNCHED) { 4843 if (!BGE_STS_BIT(sc, BGE_STS_LINK)) { 4844 BGE_STS_SETBIT(sc, BGE_STS_LINK); 4845 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) 4846 BGE_CLRBIT(sc, BGE_MAC_MODE, 4847 BGE_MACMODE_TBI_SEND_CFGS); 4848 CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF); 4849 if_link_state_change(ifp, LINK_STATE_UP); 4850 } 4851 } else if (BGE_STS_BIT(sc, BGE_STS_LINK)) { 4852 BGE_STS_CLRBIT(sc, BGE_STS_LINK); 4853 if_link_state_change(ifp, LINK_STATE_DOWN); 4854 } 4855 /* 4856 * Discard link events for MII/GMII cards if MI auto-polling disabled. 4857 * This should not happen since mii callouts are locked now, but 4858 * we keep this check for debug. 4859 */ 4860 } else if (BGE_STS_BIT(sc, BGE_STS_AUTOPOLL)) { 4861 /* 4862 * Some broken BCM chips have BGE_STATFLAG_LINKSTATE_CHANGED 4863 * bit in status word always set. Workaround this bug by 4864 * reading PHY link status directly. 4865 */ 4866 link = (CSR_READ_4(sc, BGE_MI_STS) & BGE_MISTS_LINK)? 4867 BGE_STS_LINK : 0; 4868 4869 if (BGE_STS_BIT(sc, BGE_STS_LINK) != link) { 4870 mii_pollstat(mii); 4871 4872 if (!BGE_STS_BIT(sc, BGE_STS_LINK) && 4873 mii->mii_media_status & IFM_ACTIVE && 4874 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) 4875 BGE_STS_SETBIT(sc, BGE_STS_LINK); 4876 else if (BGE_STS_BIT(sc, BGE_STS_LINK) && 4877 (!(mii->mii_media_status & IFM_ACTIVE) || 4878 IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) 4879 BGE_STS_CLRBIT(sc, BGE_STS_LINK); 4880 } 4881 } 4882 4883 /* Clear the attention */ 4884 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED| 4885 BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE| 4886 BGE_MACSTAT_LINK_CHANGED); 4887 } 4888 4889 static int 4890 bge_sysctl_verify(SYSCTLFN_ARGS) 4891 { 4892 int error, t; 4893 struct sysctlnode node; 4894 4895 node = *rnode; 4896 t = *(int*)rnode->sysctl_data; 4897 node.sysctl_data = &t; 4898 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 4899 if (error || newp == NULL) 4900 return error; 4901 4902 #if 0 4903 DPRINTF2(("%s: t = %d, nodenum = %d, rnodenum = %d\n", __func__, t, 4904 node.sysctl_num, rnode->sysctl_num)); 4905 #endif 4906 4907 if (node.sysctl_num == bge_rxthresh_nodenum) { 4908 if (t < 0 || t >= NBGE_RX_THRESH) 4909 return EINVAL; 4910 bge_update_all_threshes(t); 4911 } else 4912 return EINVAL; 4913 4914 *(int*)rnode->sysctl_data = t; 4915 4916 return 0; 4917 } 4918 4919 /* 4920 * Set up sysctl(3) MIB, hw.bge.*. 4921 */ 4922 static void 4923 bge_sysctl_init(struct bge_softc *sc) 4924 { 4925 int rc, bge_root_num; 4926 const struct sysctlnode *node; 4927 4928 if ((rc = sysctl_createv(&sc->bge_log, 0, NULL, NULL, 4929 CTLFLAG_PERMANENT, CTLTYPE_NODE, "hw", NULL, 4930 NULL, 0, NULL, 0, CTL_HW, CTL_EOL)) != 0) { 4931 goto out; 4932 } 4933 4934 if ((rc = sysctl_createv(&sc->bge_log, 0, NULL, &node, 4935 0, CTLTYPE_NODE, "bge", 4936 SYSCTL_DESCR("BGE interface controls"), 4937 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL)) != 0) { 4938 goto out; 4939 } 4940 4941 bge_root_num = node->sysctl_num; 4942 4943 /* BGE Rx interrupt mitigation level */ 4944 if ((rc = sysctl_createv(&sc->bge_log, 0, NULL, &node, 4945 CTLFLAG_READWRITE, 4946 CTLTYPE_INT, "rx_lvl", 4947 SYSCTL_DESCR("BGE receive interrupt mitigation level"), 4948 bge_sysctl_verify, 0, 4949 &bge_rx_thresh_lvl, 4950 0, CTL_HW, bge_root_num, CTL_CREATE, 4951 CTL_EOL)) != 0) { 4952 goto out; 4953 } 4954 4955 bge_rxthresh_nodenum = node->sysctl_num; 4956 4957 return; 4958 4959 out: 4960 aprint_error("%s: sysctl_createv failed (rc = %d)\n", __func__, rc); 4961 } 4962 4963 #ifdef BGE_DEBUG 4964 void 4965 bge_debug_info(struct bge_softc *sc) 4966 { 4967 4968 printf("Hardware Flags:\n"); 4969 if (BGE_IS_5755_PLUS(sc)) 4970 printf(" - 5755 Plus\n"); 4971 if (BGE_IS_575X_PLUS(sc)) 4972 printf(" - 575X Plus\n"); 4973 if (BGE_IS_5705_PLUS(sc)) 4974 printf(" - 5705 Plus\n"); 4975 if (BGE_IS_5714_FAMILY(sc)) 4976 printf(" - 5714 Family\n"); 4977 if (BGE_IS_5700_FAMILY(sc)) 4978 printf(" - 5700 Family\n"); 4979 if (sc->bge_flags & BGE_IS_5788) 4980 printf(" - 5788\n"); 4981 if (sc->bge_flags & BGE_JUMBO_CAPABLE) 4982 printf(" - Supports Jumbo Frames\n"); 4983 if (sc->bge_flags & BGE_NO_EEPROM) 4984 printf(" - No EEPROM\n"); 4985 if (sc->bge_flags & BGE_PCIX) 4986 printf(" - PCI-X Bus\n"); 4987 if (sc->bge_flags & BGE_PCIE) 4988 printf(" - PCI Express Bus\n"); 4989 if (sc->bge_flags & BGE_NO_3LED) 4990 printf(" - No 3 LEDs\n"); 4991 if (sc->bge_flags & BGE_RX_ALIGNBUG) 4992 printf(" - RX Alignment Bug\n"); 4993 if (sc->bge_flags & BGE_TSO) 4994 printf(" - TSO\n"); 4995 } 4996 #endif /* BGE_DEBUG */ 4997 4998 static int 4999 bge_get_eaddr_fw(struct bge_softc *sc, uint8_t ether_addr[]) 5000 { 5001 prop_dictionary_t dict; 5002 prop_data_t ea; 5003 5004 if ((sc->bge_flags & BGE_NO_EEPROM) == 0) 5005 return 1; 5006 5007 dict = device_properties(sc->bge_dev); 5008 ea = prop_dictionary_get(dict, "mac-address"); 5009 if (ea != NULL) { 5010 KASSERT(prop_object_type(ea) == PROP_TYPE_DATA); 5011 KASSERT(prop_data_size(ea) == ETHER_ADDR_LEN); 5012 memcpy(ether_addr, prop_data_data_nocopy(ea), ETHER_ADDR_LEN); 5013 return 0; 5014 } 5015 5016 return 1; 5017 } 5018 5019 static int 5020 bge_get_eaddr_mem(struct bge_softc *sc, uint8_t ether_addr[]) 5021 { 5022 uint32_t mac_addr; 5023 5024 mac_addr = bge_readmem_ind(sc, BGE_SRAM_MAC_ADDR_HIGH_MB); 5025 if ((mac_addr >> 16) == 0x484b) { 5026 ether_addr[0] = (uint8_t)(mac_addr >> 8); 5027 ether_addr[1] = (uint8_t)mac_addr; 5028 mac_addr = bge_readmem_ind(sc, BGE_SRAM_MAC_ADDR_LOW_MB); 5029 ether_addr[2] = (uint8_t)(mac_addr >> 24); 5030 ether_addr[3] = (uint8_t)(mac_addr >> 16); 5031 ether_addr[4] = (uint8_t)(mac_addr >> 8); 5032 ether_addr[5] = (uint8_t)mac_addr; 5033 return 0; 5034 } 5035 return 1; 5036 } 5037 5038 static int 5039 bge_get_eaddr_nvram(struct bge_softc *sc, uint8_t ether_addr[]) 5040 { 5041 int mac_offset = BGE_EE_MAC_OFFSET; 5042 5043 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 5044 mac_offset = BGE_EE_MAC_OFFSET_5906; 5045 5046 return (bge_read_nvram(sc, ether_addr, mac_offset + 2, 5047 ETHER_ADDR_LEN)); 5048 } 5049 5050 static int 5051 bge_get_eaddr_eeprom(struct bge_softc *sc, uint8_t ether_addr[]) 5052 { 5053 5054 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 5055 return 1; 5056 5057 return (bge_read_eeprom(sc, ether_addr, BGE_EE_MAC_OFFSET + 2, 5058 ETHER_ADDR_LEN)); 5059 } 5060 5061 static int 5062 bge_get_eaddr(struct bge_softc *sc, uint8_t eaddr[]) 5063 { 5064 static const bge_eaddr_fcn_t bge_eaddr_funcs[] = { 5065 /* NOTE: Order is critical */ 5066 bge_get_eaddr_fw, 5067 bge_get_eaddr_mem, 5068 bge_get_eaddr_nvram, 5069 bge_get_eaddr_eeprom, 5070 NULL 5071 }; 5072 const bge_eaddr_fcn_t *func; 5073 5074 for (func = bge_eaddr_funcs; *func != NULL; ++func) { 5075 if ((*func)(sc, eaddr) == 0) 5076 break; 5077 } 5078 return (*func == NULL ? ENXIO : 0); 5079 } 5080
Indexes created Tue Sep 23 02:09:52 GMT 2025