if_bge.c revision 1.214
1 /* $NetBSD: if_bge.c,v 1.214 2013/03/13 09:44:20 msaitoh Exp $ */ 2 3 /* 4 * Copyright (c) 2001 Wind River Systems 5 * Copyright (c) 1997, 1998, 1999, 2001 6 * Bill Paul <wpaul (at) windriver.com>. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Bill Paul. 19 * 4. Neither the name of the author nor the names of any co-contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 33 * THE POSSIBILITY OF SUCH DAMAGE. 34 * 35 * $FreeBSD: if_bge.c,v 1.13 2002/04/04 06:01:31 wpaul Exp $ 36 */ 37 38 /* 39 * Broadcom BCM570x family gigabit ethernet driver for NetBSD. 40 * 41 * NetBSD version by: 42 * 43 * Frank van der Linden <fvdl (at) wasabisystems.com> 44 * Jason Thorpe <thorpej (at) wasabisystems.com> 45 * Jonathan Stone <jonathan (at) dsg.stanford.edu> 46 * 47 * Originally written for FreeBSD by Bill Paul <wpaul (at) windriver.com> 48 * Senior Engineer, Wind River Systems 49 */ 50 51 /* 52 * The Broadcom BCM5700 is based on technology originally developed by 53 * Alteon Networks as part of the Tigon I and Tigon II gigabit ethernet 54 * MAC chips. The BCM5700, sometimes referred to as the Tigon III, has 55 * two on-board MIPS R4000 CPUs and can have as much as 16MB of external 56 * SSRAM. The BCM5700 supports TCP, UDP and IP checksum offload, jumbo 57 * frames, highly configurable RX filtering, and 16 RX and TX queues 58 * (which, along with RX filter rules, can be used for QOS applications). 59 * Other features, such as TCP segmentation, may be available as part 60 * of value-added firmware updates. Unlike the Tigon I and Tigon II, 61 * firmware images can be stored in hardware and need not be compiled 62 * into the driver. 63 * 64 * The BCM5700 supports the PCI v2.2 and PCI-X v1.0 standards, and will 65 * function in a 32-bit/64-bit 33/66MHz bus, or a 64-bit/133MHz bus. 66 * 67 * The BCM5701 is a single-chip solution incorporating both the BCM5700 68 * MAC and a BCM5401 10/100/1000 PHY. Unlike the BCM5700, the BCM5701 69 * does not support external SSRAM. 70 * 71 * Broadcom also produces a variation of the BCM5700 under the "Altima" 72 * brand name, which is functionally similar but lacks PCI-X support. 73 * 74 * Without external SSRAM, you can only have at most 4 TX rings, 75 * and the use of the mini RX ring is disabled. This seems to imply 76 * that these features are simply not available on the BCM5701. As a 77 * result, this driver does not implement any support for the mini RX 78 * ring. 79 */ 80 81 #include <sys/cdefs.h> 82 __KERNEL_RCSID(0, "$NetBSD: if_bge.c,v 1.214 2013/03/13 09:44:20 msaitoh Exp $"); 83 84 #include "vlan.h" 85 86 #include <sys/param.h> 87 #include <sys/systm.h> 88 #include <sys/callout.h> 89 #include <sys/sockio.h> 90 #include <sys/mbuf.h> 91 #include <sys/malloc.h> 92 #include <sys/kernel.h> 93 #include <sys/device.h> 94 #include <sys/socket.h> 95 #include <sys/sysctl.h> 96 97 #include <net/if.h> 98 #include <net/if_dl.h> 99 #include <net/if_media.h> 100 #include <net/if_ether.h> 101 102 #include <sys/rnd.h> 103 104 #ifdef INET 105 #include <netinet/in.h> 106 #include <netinet/in_systm.h> 107 #include <netinet/in_var.h> 108 #include <netinet/ip.h> 109 #endif 110 111 /* Headers for TCP Segmentation Offload (TSO) */ 112 #include <netinet/in_systm.h> /* n_time for <netinet/ip.h>... */ 113 #include <netinet/in.h> /* ip_{src,dst}, for <netinet/ip.h> */ 114 #include <netinet/ip.h> /* for struct ip */ 115 #include <netinet/tcp.h> /* for struct tcphdr */ 116 117 118 #include <net/bpf.h> 119 120 #include <dev/pci/pcireg.h> 121 #include <dev/pci/pcivar.h> 122 #include <dev/pci/pcidevs.h> 123 124 #include <dev/mii/mii.h> 125 #include <dev/mii/miivar.h> 126 #include <dev/mii/miidevs.h> 127 #include <dev/mii/brgphyreg.h> 128 129 #include <dev/pci/if_bgereg.h> 130 #include <dev/pci/if_bgevar.h> 131 132 #include <prop/proplib.h> 133 134 #define ETHER_MIN_NOPAD (ETHER_MIN_LEN - ETHER_CRC_LEN) /* i.e., 60 */ 135 136 137 /* 138 * Tunable thresholds for rx-side bge interrupt mitigation. 139 */ 140 141 /* 142 * The pairs of values below were obtained from empirical measurement 143 * on bcm5700 rev B2; they ar designed to give roughly 1 receive 144 * interrupt for every N packets received, where N is, approximately, 145 * the second value (rx_max_bds) in each pair. The values are chosen 146 * such that moving from one pair to the succeeding pair was observed 147 * to roughly halve interrupt rate under sustained input packet load. 148 * The values were empirically chosen to avoid overflowing internal 149 * limits on the bcm5700: increasing rx_ticks much beyond 600 150 * results in internal wrapping and higher interrupt rates. 151 * The limit of 46 frames was chosen to match NFS workloads. 152 * 153 * These values also work well on bcm5701, bcm5704C, and (less 154 * tested) bcm5703. On other chipsets, (including the Altima chip 155 * family), the larger values may overflow internal chip limits, 156 * leading to increasing interrupt rates rather than lower interrupt 157 * rates. 158 * 159 * Applications using heavy interrupt mitigation (interrupting every 160 * 32 or 46 frames) in both directions may need to increase the TCP 161 * windowsize to above 131072 bytes (e.g., to 199608 bytes) to sustain 162 * full link bandwidth, due to ACKs and window updates lingering 163 * in the RX queue during the 30-to-40-frame interrupt-mitigation window. 164 */ 165 static const struct bge_load_rx_thresh { 166 int rx_ticks; 167 int rx_max_bds; } 168 bge_rx_threshes[] = { 169 { 16, 1 }, /* rx_max_bds = 1 disables interrupt mitigation */ 170 { 32, 2 }, 171 { 50, 4 }, 172 { 100, 8 }, 173 { 192, 16 }, 174 { 416, 32 }, 175 { 598, 46 } 176 }; 177 #define NBGE_RX_THRESH (sizeof(bge_rx_threshes) / sizeof(bge_rx_threshes[0])) 178 179 /* XXX patchable; should be sysctl'able */ 180 static int bge_auto_thresh = 1; 181 static int bge_rx_thresh_lvl; 182 183 static int bge_rxthresh_nodenum; 184 185 typedef int (*bge_eaddr_fcn_t)(struct bge_softc *, uint8_t[]); 186 187 static int bge_probe(device_t, cfdata_t, void *); 188 static void bge_attach(device_t, device_t, void *); 189 static void bge_release_resources(struct bge_softc *); 190 191 static int bge_get_eaddr_fw(struct bge_softc *, uint8_t[]); 192 static int bge_get_eaddr_mem(struct bge_softc *, uint8_t[]); 193 static int bge_get_eaddr_nvram(struct bge_softc *, uint8_t[]); 194 static int bge_get_eaddr_eeprom(struct bge_softc *, uint8_t[]); 195 static int bge_get_eaddr(struct bge_softc *, uint8_t[]); 196 197 static void bge_txeof(struct bge_softc *); 198 static void bge_rxeof(struct bge_softc *); 199 200 static void bge_asf_driver_up (struct bge_softc *); 201 static void bge_tick(void *); 202 static void bge_stats_update(struct bge_softc *); 203 static void bge_stats_update_regs(struct bge_softc *); 204 static int bge_encap(struct bge_softc *, struct mbuf *, uint32_t *); 205 206 static int bge_intr(void *); 207 static void bge_start(struct ifnet *); 208 static int bge_ifflags_cb(struct ethercom *); 209 static int bge_ioctl(struct ifnet *, u_long, void *); 210 static int bge_init(struct ifnet *); 211 static void bge_stop(struct ifnet *, int); 212 static void bge_watchdog(struct ifnet *); 213 static int bge_ifmedia_upd(struct ifnet *); 214 static void bge_ifmedia_sts(struct ifnet *, struct ifmediareq *); 215 216 static uint8_t bge_nvram_getbyte(struct bge_softc *, int, uint8_t *); 217 static int bge_read_nvram(struct bge_softc *, uint8_t *, int, int); 218 219 static uint8_t bge_eeprom_getbyte(struct bge_softc *, int, uint8_t *); 220 static int bge_read_eeprom(struct bge_softc *, void *, int, int); 221 static void bge_setmulti(struct bge_softc *); 222 223 static void bge_handle_events(struct bge_softc *); 224 static int bge_alloc_jumbo_mem(struct bge_softc *); 225 #if 0 /* XXX */ 226 static void bge_free_jumbo_mem(struct bge_softc *); 227 #endif 228 static void *bge_jalloc(struct bge_softc *); 229 static void bge_jfree(struct mbuf *, void *, size_t, void *); 230 static int bge_newbuf_std(struct bge_softc *, int, struct mbuf *, 231 bus_dmamap_t); 232 static int bge_newbuf_jumbo(struct bge_softc *, int, struct mbuf *); 233 static int bge_init_rx_ring_std(struct bge_softc *); 234 static void bge_free_rx_ring_std(struct bge_softc *); 235 static int bge_init_rx_ring_jumbo(struct bge_softc *); 236 static void bge_free_rx_ring_jumbo(struct bge_softc *); 237 static void bge_free_tx_ring(struct bge_softc *); 238 static int bge_init_tx_ring(struct bge_softc *); 239 240 static int bge_chipinit(struct bge_softc *); 241 static int bge_blockinit(struct bge_softc *); 242 static int bge_setpowerstate(struct bge_softc *, int); 243 static uint32_t bge_readmem_ind(struct bge_softc *, int); 244 static void bge_writemem_ind(struct bge_softc *, int, int); 245 static void bge_writembx(struct bge_softc *, int, int); 246 static void bge_writembx_flush(struct bge_softc *, int, int); 247 static void bge_writemem_direct(struct bge_softc *, int, int); 248 static void bge_writereg_ind(struct bge_softc *, int, int); 249 static void bge_set_max_readrq(struct bge_softc *); 250 251 static int bge_miibus_readreg(device_t, int, int); 252 static void bge_miibus_writereg(device_t, int, int, int); 253 static void bge_miibus_statchg(struct ifnet *); 254 255 #define BGE_RESET_START 1 256 #define BGE_RESET_STOP 2 257 static void bge_sig_post_reset(struct bge_softc *, int); 258 static void bge_sig_legacy(struct bge_softc *, int); 259 static void bge_sig_pre_reset(struct bge_softc *, int); 260 static void bge_stop_fw(struct bge_softc *); 261 static int bge_reset(struct bge_softc *); 262 static void bge_link_upd(struct bge_softc *); 263 static void bge_sysctl_init(struct bge_softc *); 264 static int bge_sysctl_verify(SYSCTLFN_PROTO); 265 266 #ifdef BGE_DEBUG 267 #define DPRINTF(x) if (bgedebug) printf x 268 #define DPRINTFN(n,x) if (bgedebug >= (n)) printf x 269 #define BGE_TSO_PRINTF(x) do { if (bge_tso_debug) printf x ;} while (0) 270 int bgedebug = 0; 271 int bge_tso_debug = 0; 272 void bge_debug_info(struct bge_softc *); 273 #else 274 #define DPRINTF(x) 275 #define DPRINTFN(n,x) 276 #define BGE_TSO_PRINTF(x) 277 #endif 278 279 #ifdef BGE_EVENT_COUNTERS 280 #define BGE_EVCNT_INCR(ev) (ev).ev_count++ 281 #define BGE_EVCNT_ADD(ev, val) (ev).ev_count += (val) 282 #define BGE_EVCNT_UPD(ev, val) (ev).ev_count = (val) 283 #else 284 #define BGE_EVCNT_INCR(ev) /* nothing */ 285 #define BGE_EVCNT_ADD(ev, val) /* nothing */ 286 #define BGE_EVCNT_UPD(ev, val) /* nothing */ 287 #endif 288 289 static const struct bge_product { 290 pci_vendor_id_t bp_vendor; 291 pci_product_id_t bp_product; 292 const char *bp_name; 293 } bge_products[] = { 294 /* 295 * The BCM5700 documentation seems to indicate that the hardware 296 * still has the Alteon vendor ID burned into it, though it 297 * should always be overridden by the value in the EEPROM. We'll 298 * check for it anyway. 299 */ 300 { PCI_VENDOR_ALTEON, 301 PCI_PRODUCT_ALTEON_BCM5700, 302 "Broadcom BCM5700 Gigabit Ethernet", 303 }, 304 { PCI_VENDOR_ALTEON, 305 PCI_PRODUCT_ALTEON_BCM5701, 306 "Broadcom BCM5701 Gigabit Ethernet", 307 }, 308 { PCI_VENDOR_ALTIMA, 309 PCI_PRODUCT_ALTIMA_AC1000, 310 "Altima AC1000 Gigabit Ethernet", 311 }, 312 { PCI_VENDOR_ALTIMA, 313 PCI_PRODUCT_ALTIMA_AC1001, 314 "Altima AC1001 Gigabit Ethernet", 315 }, 316 { PCI_VENDOR_ALTIMA, 317 PCI_PRODUCT_ALTIMA_AC1003, 318 "Altima AC1003 Gigabit Ethernet", 319 }, 320 { PCI_VENDOR_ALTIMA, 321 PCI_PRODUCT_ALTIMA_AC9100, 322 "Altima AC9100 Gigabit Ethernet", 323 }, 324 { PCI_VENDOR_APPLE, 325 PCI_PRODUCT_APPLE_BCM5701, 326 "APPLE BCM5701 Gigabit Ethernet", 327 }, 328 { PCI_VENDOR_BROADCOM, 329 PCI_PRODUCT_BROADCOM_BCM5700, 330 "Broadcom BCM5700 Gigabit Ethernet", 331 }, 332 { PCI_VENDOR_BROADCOM, 333 PCI_PRODUCT_BROADCOM_BCM5701, 334 "Broadcom BCM5701 Gigabit Ethernet", 335 }, 336 { PCI_VENDOR_BROADCOM, 337 PCI_PRODUCT_BROADCOM_BCM5702, 338 "Broadcom BCM5702 Gigabit Ethernet", 339 }, 340 { PCI_VENDOR_BROADCOM, 341 PCI_PRODUCT_BROADCOM_BCM5702X, 342 "Broadcom BCM5702X Gigabit Ethernet" }, 343 { PCI_VENDOR_BROADCOM, 344 PCI_PRODUCT_BROADCOM_BCM5703, 345 "Broadcom BCM5703 Gigabit Ethernet", 346 }, 347 { PCI_VENDOR_BROADCOM, 348 PCI_PRODUCT_BROADCOM_BCM5703X, 349 "Broadcom BCM5703X Gigabit Ethernet", 350 }, 351 { PCI_VENDOR_BROADCOM, 352 PCI_PRODUCT_BROADCOM_BCM5703_ALT, 353 "Broadcom BCM5703 Gigabit Ethernet", 354 }, 355 { PCI_VENDOR_BROADCOM, 356 PCI_PRODUCT_BROADCOM_BCM5704C, 357 "Broadcom BCM5704C Dual Gigabit Ethernet", 358 }, 359 { PCI_VENDOR_BROADCOM, 360 PCI_PRODUCT_BROADCOM_BCM5704S, 361 "Broadcom BCM5704S Dual Gigabit Ethernet", 362 }, 363 { PCI_VENDOR_BROADCOM, 364 PCI_PRODUCT_BROADCOM_BCM5705, 365 "Broadcom BCM5705 Gigabit Ethernet", 366 }, 367 { PCI_VENDOR_BROADCOM, 368 PCI_PRODUCT_BROADCOM_BCM5705F, 369 "Broadcom BCM5705F Gigabit Ethernet", 370 }, 371 { PCI_VENDOR_BROADCOM, 372 PCI_PRODUCT_BROADCOM_BCM5705K, 373 "Broadcom BCM5705K Gigabit Ethernet", 374 }, 375 { PCI_VENDOR_BROADCOM, 376 PCI_PRODUCT_BROADCOM_BCM5705M, 377 "Broadcom BCM5705M Gigabit Ethernet", 378 }, 379 { PCI_VENDOR_BROADCOM, 380 PCI_PRODUCT_BROADCOM_BCM5705M_ALT, 381 "Broadcom BCM5705M Gigabit Ethernet", 382 }, 383 { PCI_VENDOR_BROADCOM, 384 PCI_PRODUCT_BROADCOM_BCM5714, 385 "Broadcom BCM5714 Gigabit Ethernet", 386 }, 387 { PCI_VENDOR_BROADCOM, 388 PCI_PRODUCT_BROADCOM_BCM5714S, 389 "Broadcom BCM5714S Gigabit Ethernet", 390 }, 391 { PCI_VENDOR_BROADCOM, 392 PCI_PRODUCT_BROADCOM_BCM5715, 393 "Broadcom BCM5715 Gigabit Ethernet", 394 }, 395 { PCI_VENDOR_BROADCOM, 396 PCI_PRODUCT_BROADCOM_BCM5715S, 397 "Broadcom BCM5715S Gigabit Ethernet", 398 }, 399 { PCI_VENDOR_BROADCOM, 400 PCI_PRODUCT_BROADCOM_BCM5717, 401 "Broadcom BCM5717 Gigabit Ethernet", 402 }, 403 { PCI_VENDOR_BROADCOM, 404 PCI_PRODUCT_BROADCOM_BCM5718, 405 "Broadcom BCM5718 Gigabit Ethernet", 406 }, 407 #if 0 408 { PCI_VENDOR_BROADCOM, 409 PCI_PRODUCT_BROADCOM_BCM5720, 410 "Broadcom BCM5720 Gigabit Ethernet", 411 }, 412 #endif 413 { PCI_VENDOR_BROADCOM, 414 PCI_PRODUCT_BROADCOM_BCM5721, 415 "Broadcom BCM5721 Gigabit Ethernet", 416 }, 417 { PCI_VENDOR_BROADCOM, 418 PCI_PRODUCT_BROADCOM_BCM5722, 419 "Broadcom BCM5722 Gigabit Ethernet", 420 }, 421 { PCI_VENDOR_BROADCOM, 422 PCI_PRODUCT_BROADCOM_BCM5723, 423 "Broadcom BCM5723 Gigabit Ethernet", 424 }, 425 { PCI_VENDOR_BROADCOM, 426 PCI_PRODUCT_BROADCOM_BCM5724, 427 "Broadcom BCM5724 Gigabit Ethernet", 428 }, 429 { PCI_VENDOR_BROADCOM, 430 PCI_PRODUCT_BROADCOM_BCM5750, 431 "Broadcom BCM5750 Gigabit Ethernet", 432 }, 433 { PCI_VENDOR_BROADCOM, 434 PCI_PRODUCT_BROADCOM_BCM5750M, 435 "Broadcom BCM5750M Gigabit Ethernet", 436 }, 437 { PCI_VENDOR_BROADCOM, 438 PCI_PRODUCT_BROADCOM_BCM5751, 439 "Broadcom BCM5751 Gigabit Ethernet", 440 }, 441 { PCI_VENDOR_BROADCOM, 442 PCI_PRODUCT_BROADCOM_BCM5751F, 443 "Broadcom BCM5751F Gigabit Ethernet", 444 }, 445 { PCI_VENDOR_BROADCOM, 446 PCI_PRODUCT_BROADCOM_BCM5751M, 447 "Broadcom BCM5751M Gigabit Ethernet", 448 }, 449 { PCI_VENDOR_BROADCOM, 450 PCI_PRODUCT_BROADCOM_BCM5752, 451 "Broadcom BCM5752 Gigabit Ethernet", 452 }, 453 { PCI_VENDOR_BROADCOM, 454 PCI_PRODUCT_BROADCOM_BCM5752M, 455 "Broadcom BCM5752M Gigabit Ethernet", 456 }, 457 { PCI_VENDOR_BROADCOM, 458 PCI_PRODUCT_BROADCOM_BCM5753, 459 "Broadcom BCM5753 Gigabit Ethernet", 460 }, 461 { PCI_VENDOR_BROADCOM, 462 PCI_PRODUCT_BROADCOM_BCM5753F, 463 "Broadcom BCM5753F Gigabit Ethernet", 464 }, 465 { PCI_VENDOR_BROADCOM, 466 PCI_PRODUCT_BROADCOM_BCM5753M, 467 "Broadcom BCM5753M Gigabit Ethernet", 468 }, 469 { PCI_VENDOR_BROADCOM, 470 PCI_PRODUCT_BROADCOM_BCM5754, 471 "Broadcom BCM5754 Gigabit Ethernet", 472 }, 473 { PCI_VENDOR_BROADCOM, 474 PCI_PRODUCT_BROADCOM_BCM5754M, 475 "Broadcom BCM5754M Gigabit Ethernet", 476 }, 477 { PCI_VENDOR_BROADCOM, 478 PCI_PRODUCT_BROADCOM_BCM5755, 479 "Broadcom BCM5755 Gigabit Ethernet", 480 }, 481 { PCI_VENDOR_BROADCOM, 482 PCI_PRODUCT_BROADCOM_BCM5755M, 483 "Broadcom BCM5755M Gigabit Ethernet", 484 }, 485 { PCI_VENDOR_BROADCOM, 486 PCI_PRODUCT_BROADCOM_BCM5756, 487 "Broadcom BCM5756 Gigabit Ethernet", 488 }, 489 { PCI_VENDOR_BROADCOM, 490 PCI_PRODUCT_BROADCOM_BCM5761, 491 "Broadcom BCM5761 Gigabit Ethernet", 492 }, 493 { PCI_VENDOR_BROADCOM, 494 PCI_PRODUCT_BROADCOM_BCM5761E, 495 "Broadcom BCM5761E Gigabit Ethernet", 496 }, 497 { PCI_VENDOR_BROADCOM, 498 PCI_PRODUCT_BROADCOM_BCM5761S, 499 "Broadcom BCM5761S Gigabit Ethernet", 500 }, 501 { PCI_VENDOR_BROADCOM, 502 PCI_PRODUCT_BROADCOM_BCM5761SE, 503 "Broadcom BCM5761SE Gigabit Ethernet", 504 }, 505 { PCI_VENDOR_BROADCOM, 506 PCI_PRODUCT_BROADCOM_BCM5764, 507 "Broadcom BCM5764 Gigabit Ethernet", 508 }, 509 { PCI_VENDOR_BROADCOM, 510 PCI_PRODUCT_BROADCOM_BCM5780, 511 "Broadcom BCM5780 Gigabit Ethernet", 512 }, 513 { PCI_VENDOR_BROADCOM, 514 PCI_PRODUCT_BROADCOM_BCM5780S, 515 "Broadcom BCM5780S Gigabit Ethernet", 516 }, 517 { PCI_VENDOR_BROADCOM, 518 PCI_PRODUCT_BROADCOM_BCM5781, 519 "Broadcom BCM5781 Gigabit Ethernet", 520 }, 521 { PCI_VENDOR_BROADCOM, 522 PCI_PRODUCT_BROADCOM_BCM5782, 523 "Broadcom BCM5782 Gigabit Ethernet", 524 }, 525 { PCI_VENDOR_BROADCOM, 526 PCI_PRODUCT_BROADCOM_BCM5784M, 527 "BCM5784M NetLink 1000baseT Ethernet", 528 }, 529 { PCI_VENDOR_BROADCOM, 530 PCI_PRODUCT_BROADCOM_BCM5785F, 531 "BCM5785F NetLink 10/100 Ethernet", 532 }, 533 { PCI_VENDOR_BROADCOM, 534 PCI_PRODUCT_BROADCOM_BCM5785G, 535 "BCM5785G NetLink 1000baseT Ethernet", 536 }, 537 { PCI_VENDOR_BROADCOM, 538 PCI_PRODUCT_BROADCOM_BCM5786, 539 "Broadcom BCM5786 Gigabit Ethernet", 540 }, 541 { PCI_VENDOR_BROADCOM, 542 PCI_PRODUCT_BROADCOM_BCM5787, 543 "Broadcom BCM5787 Gigabit Ethernet", 544 }, 545 { PCI_VENDOR_BROADCOM, 546 PCI_PRODUCT_BROADCOM_BCM5787F, 547 "Broadcom BCM5787F 10/100 Ethernet", 548 }, 549 { PCI_VENDOR_BROADCOM, 550 PCI_PRODUCT_BROADCOM_BCM5787M, 551 "Broadcom BCM5787M Gigabit Ethernet", 552 }, 553 { PCI_VENDOR_BROADCOM, 554 PCI_PRODUCT_BROADCOM_BCM5788, 555 "Broadcom BCM5788 Gigabit Ethernet", 556 }, 557 { PCI_VENDOR_BROADCOM, 558 PCI_PRODUCT_BROADCOM_BCM5789, 559 "Broadcom BCM5789 Gigabit Ethernet", 560 }, 561 { PCI_VENDOR_BROADCOM, 562 PCI_PRODUCT_BROADCOM_BCM5901, 563 "Broadcom BCM5901 Fast Ethernet", 564 }, 565 { PCI_VENDOR_BROADCOM, 566 PCI_PRODUCT_BROADCOM_BCM5901A2, 567 "Broadcom BCM5901A2 Fast Ethernet", 568 }, 569 { PCI_VENDOR_BROADCOM, 570 PCI_PRODUCT_BROADCOM_BCM5903M, 571 "Broadcom BCM5903M Fast Ethernet", 572 }, 573 { PCI_VENDOR_BROADCOM, 574 PCI_PRODUCT_BROADCOM_BCM5906, 575 "Broadcom BCM5906 Fast Ethernet", 576 }, 577 { PCI_VENDOR_BROADCOM, 578 PCI_PRODUCT_BROADCOM_BCM5906M, 579 "Broadcom BCM5906M Fast Ethernet", 580 }, 581 { PCI_VENDOR_BROADCOM, 582 PCI_PRODUCT_BROADCOM_BCM57760, 583 "Broadcom BCM57760 Fast Ethernet", 584 }, 585 { PCI_VENDOR_BROADCOM, 586 PCI_PRODUCT_BROADCOM_BCM57761, 587 "Broadcom BCM57761 Fast Ethernet", 588 }, 589 { PCI_VENDOR_BROADCOM, 590 PCI_PRODUCT_BROADCOM_BCM57762, 591 "Broadcom BCM57762 Gigabit Ethernet", 592 }, 593 { PCI_VENDOR_BROADCOM, 594 PCI_PRODUCT_BROADCOM_BCM57765, 595 "Broadcom BCM57765 Fast Ethernet", 596 }, 597 { PCI_VENDOR_BROADCOM, 598 PCI_PRODUCT_BROADCOM_BCM57780, 599 "Broadcom BCM57780 Fast Ethernet", 600 }, 601 { PCI_VENDOR_BROADCOM, 602 PCI_PRODUCT_BROADCOM_BCM57781, 603 "Broadcom BCM57781 Fast Ethernet", 604 }, 605 { PCI_VENDOR_BROADCOM, 606 PCI_PRODUCT_BROADCOM_BCM57785, 607 "Broadcom BCM57785 Fast Ethernet", 608 }, 609 { PCI_VENDOR_BROADCOM, 610 PCI_PRODUCT_BROADCOM_BCM57788, 611 "Broadcom BCM57788 Fast Ethernet", 612 }, 613 { PCI_VENDOR_BROADCOM, 614 PCI_PRODUCT_BROADCOM_BCM57790, 615 "Broadcom BCM57790 Fast Ethernet", 616 }, 617 { PCI_VENDOR_BROADCOM, 618 PCI_PRODUCT_BROADCOM_BCM57791, 619 "Broadcom BCM57791 Fast Ethernet", 620 }, 621 { PCI_VENDOR_BROADCOM, 622 PCI_PRODUCT_BROADCOM_BCM57795, 623 "Broadcom BCM57795 Fast Ethernet", 624 }, 625 { PCI_VENDOR_SCHNEIDERKOCH, 626 PCI_PRODUCT_SCHNEIDERKOCH_SK_9DX1, 627 "SysKonnect SK-9Dx1 Gigabit Ethernet", 628 }, 629 { PCI_VENDOR_3COM, 630 PCI_PRODUCT_3COM_3C996, 631 "3Com 3c996 Gigabit Ethernet", 632 }, 633 { PCI_VENDOR_FUJITSU4, 634 PCI_PRODUCT_FUJITSU4_PW008GE4, 635 "Fujitsu PW008GE4 Gigabit Ethernet", 636 }, 637 { PCI_VENDOR_FUJITSU4, 638 PCI_PRODUCT_FUJITSU4_PW008GE5, 639 "Fujitsu PW008GE5 Gigabit Ethernet", 640 }, 641 { PCI_VENDOR_FUJITSU4, 642 PCI_PRODUCT_FUJITSU4_PP250_450_LAN, 643 "Fujitsu Primepower 250/450 Gigabit Ethernet", 644 }, 645 { 0, 646 0, 647 NULL }, 648 }; 649 650 #define BGE_IS_5700_FAMILY(sc) ((sc)->bge_flags & BGE_5700_FAMILY) 651 #define BGE_IS_5714_FAMILY(sc) ((sc)->bge_flags & BGE_5714_FAMILY) 652 #define BGE_IS_5705_PLUS(sc) ((sc)->bge_flags & BGE_5705_PLUS) 653 #define BGE_IS_575X_PLUS(sc) ((sc)->bge_flags & BGE_575X_PLUS) 654 #define BGE_IS_5755_PLUS(sc) ((sc)->bge_flags & BGE_5755_PLUS) 655 #define BGE_IS_5717_PLUS(sc) ((sc)->bge_flags & BGE_5717_PLUS) 656 #define BGE_IS_57765_PLUS(sc) ((sc)->bge_flags & BGE_57765_PLUS) 657 #define BGE_IS_JUMBO_CAPABLE(sc) ((sc)->bge_flags & BGE_JUMBO_CAPABLE) 658 659 static const struct bge_revision { 660 uint32_t br_chipid; 661 const char *br_name; 662 } bge_revisions[] = { 663 { BGE_CHIPID_BCM5700_A0, "BCM5700 A0" }, 664 { BGE_CHIPID_BCM5700_A1, "BCM5700 A1" }, 665 { BGE_CHIPID_BCM5700_B0, "BCM5700 B0" }, 666 { BGE_CHIPID_BCM5700_B1, "BCM5700 B1" }, 667 { BGE_CHIPID_BCM5700_B2, "BCM5700 B2" }, 668 { BGE_CHIPID_BCM5700_B3, "BCM5700 B3" }, 669 /* This is treated like a BCM5700 Bx */ 670 { BGE_CHIPID_BCM5700_ALTIMA, "BCM5700 Altima" }, 671 { BGE_CHIPID_BCM5700_C0, "BCM5700 C0" }, 672 { BGE_CHIPID_BCM5701_A0, "BCM5701 A0" }, 673 { BGE_CHIPID_BCM5701_B0, "BCM5701 B0" }, 674 { BGE_CHIPID_BCM5701_B2, "BCM5701 B2" }, 675 { BGE_CHIPID_BCM5701_B5, "BCM5701 B5" }, 676 { BGE_CHIPID_BCM5703_A0, "BCM5702/5703 A0" }, 677 { BGE_CHIPID_BCM5703_A1, "BCM5702/5703 A1" }, 678 { BGE_CHIPID_BCM5703_A2, "BCM5702/5703 A2" }, 679 { BGE_CHIPID_BCM5703_A3, "BCM5702/5703 A3" }, 680 { BGE_CHIPID_BCM5703_B0, "BCM5702/5703 B0" }, 681 { BGE_CHIPID_BCM5704_A0, "BCM5704 A0" }, 682 { BGE_CHIPID_BCM5704_A1, "BCM5704 A1" }, 683 { BGE_CHIPID_BCM5704_A2, "BCM5704 A2" }, 684 { BGE_CHIPID_BCM5704_A3, "BCM5704 A3" }, 685 { BGE_CHIPID_BCM5704_B0, "BCM5704 B0" }, 686 { BGE_CHIPID_BCM5705_A0, "BCM5705 A0" }, 687 { BGE_CHIPID_BCM5705_A1, "BCM5705 A1" }, 688 { BGE_CHIPID_BCM5705_A2, "BCM5705 A2" }, 689 { BGE_CHIPID_BCM5705_A3, "BCM5705 A3" }, 690 { BGE_CHIPID_BCM5750_A0, "BCM5750 A0" }, 691 { BGE_CHIPID_BCM5750_A1, "BCM5750 A1" }, 692 { BGE_CHIPID_BCM5750_A3, "BCM5750 A3" }, 693 { BGE_CHIPID_BCM5750_B0, "BCM5750 B0" }, 694 { BGE_CHIPID_BCM5750_B1, "BCM5750 B1" }, 695 { BGE_CHIPID_BCM5750_C0, "BCM5750 C0" }, 696 { BGE_CHIPID_BCM5750_C1, "BCM5750 C1" }, 697 { BGE_CHIPID_BCM5750_C2, "BCM5750 C2" }, 698 { BGE_CHIPID_BCM5752_A0, "BCM5752 A0" }, 699 { BGE_CHIPID_BCM5752_A1, "BCM5752 A1" }, 700 { BGE_CHIPID_BCM5752_A2, "BCM5752 A2" }, 701 { BGE_CHIPID_BCM5714_A0, "BCM5714 A0" }, 702 { BGE_CHIPID_BCM5714_B0, "BCM5714 B0" }, 703 { BGE_CHIPID_BCM5714_B3, "BCM5714 B3" }, 704 { BGE_CHIPID_BCM5715_A0, "BCM5715 A0" }, 705 { BGE_CHIPID_BCM5715_A1, "BCM5715 A1" }, 706 { BGE_CHIPID_BCM5715_A3, "BCM5715 A3" }, 707 { BGE_CHIPID_BCM5755_A0, "BCM5755 A0" }, 708 { BGE_CHIPID_BCM5755_A1, "BCM5755 A1" }, 709 { BGE_CHIPID_BCM5755_A2, "BCM5755 A2" }, 710 { BGE_CHIPID_BCM5755_C0, "BCM5755 C0" }, 711 { BGE_CHIPID_BCM5761_A0, "BCM5761 A0" }, 712 { BGE_CHIPID_BCM5761_A1, "BCM5761 A1" }, 713 { BGE_CHIPID_BCM5784_A0, "BCM5784 A0" }, 714 { BGE_CHIPID_BCM5784_A1, "BCM5784 A1" }, 715 /* 5754 and 5787 share the same ASIC ID */ 716 { BGE_CHIPID_BCM5787_A0, "BCM5754/5787 A0" }, 717 { BGE_CHIPID_BCM5787_A1, "BCM5754/5787 A1" }, 718 { BGE_CHIPID_BCM5787_A2, "BCM5754/5787 A2" }, 719 { BGE_CHIPID_BCM5906_A0, "BCM5906 A0" }, 720 { BGE_CHIPID_BCM5906_A1, "BCM5906 A1" }, 721 { BGE_CHIPID_BCM5906_A2, "BCM5906 A2" }, 722 { BGE_CHIPID_BCM57765_A0, "BCM57765 A0" }, 723 { BGE_CHIPID_BCM57765_B0, "BCM57765 B0" }, 724 { BGE_CHIPID_BCM57780_A0, "BCM57780 A0" }, 725 { BGE_CHIPID_BCM57780_A1, "BCM57780 A1" }, 726 727 { 0, NULL } 728 }; 729 730 /* 731 * Some defaults for major revisions, so that newer steppings 732 * that we don't know about have a shot at working. 733 */ 734 static const struct bge_revision bge_majorrevs[] = { 735 { BGE_ASICREV_BCM5700, "unknown BCM5700" }, 736 { BGE_ASICREV_BCM5701, "unknown BCM5701" }, 737 { BGE_ASICREV_BCM5703, "unknown BCM5703" }, 738 { BGE_ASICREV_BCM5704, "unknown BCM5704" }, 739 { BGE_ASICREV_BCM5705, "unknown BCM5705" }, 740 { BGE_ASICREV_BCM5750, "unknown BCM5750" }, 741 { BGE_ASICREV_BCM5714_A0, "unknown BCM5714" }, 742 { BGE_ASICREV_BCM5752, "unknown BCM5752" }, 743 { BGE_ASICREV_BCM5780, "unknown BCM5780" }, 744 { BGE_ASICREV_BCM5714, "unknown BCM5714" }, 745 { BGE_ASICREV_BCM5755, "unknown BCM5755" }, 746 { BGE_ASICREV_BCM5761, "unknown BCM5761" }, 747 { BGE_ASICREV_BCM5784, "unknown BCM5784" }, 748 { BGE_ASICREV_BCM5785, "unknown BCM5785" }, 749 /* 5754 and 5787 share the same ASIC ID */ 750 { BGE_ASICREV_BCM5787, "unknown BCM5754/5787" }, 751 { BGE_ASICREV_BCM5906, "unknown BCM5906" }, 752 { BGE_ASICREV_BCM57780, "unknown BCM57780" }, 753 { BGE_ASICREV_BCM5717, "unknown BCM5717" }, 754 { BGE_ASICREV_BCM57765, "unknown BCM57765" }, 755 { BGE_ASICREV_BCM57766, "unknown BCM57766" }, 756 757 { 0, NULL } 758 }; 759 760 static int bge_allow_asf = 1; 761 762 CFATTACH_DECL_NEW(bge, sizeof(struct bge_softc), 763 bge_probe, bge_attach, NULL, NULL); 764 765 static uint32_t 766 bge_readmem_ind(struct bge_softc *sc, int off) 767 { 768 pcireg_t val; 769 770 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_BASEADDR, off); 771 val = pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_DATA); 772 return val; 773 } 774 775 static void 776 bge_writemem_ind(struct bge_softc *sc, int off, int val) 777 { 778 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_BASEADDR, off); 779 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_DATA, val); 780 } 781 782 /* 783 * PCI Express only 784 */ 785 static void 786 bge_set_max_readrq(struct bge_softc *sc) 787 { 788 pcireg_t val; 789 790 val = pci_conf_read(sc->sc_pc, sc->sc_pcitag, sc->bge_pciecap 791 + PCI_PCIE_DCSR); 792 if ((val & PCI_PCIE_DCSR_MAX_READ_REQ) != 793 BGE_PCIE_DEVCTL_MAX_READRQ_4096) { 794 aprint_verbose_dev(sc->bge_dev, 795 "adjust device control 0x%04x ", val); 796 val &= ~PCI_PCIE_DCSR_MAX_READ_REQ; 797 val |= BGE_PCIE_DEVCTL_MAX_READRQ_4096; 798 pci_conf_write(sc->sc_pc, sc->sc_pcitag, sc->bge_pciecap 799 + PCI_PCIE_DCSR, val); 800 aprint_verbose("-> 0x%04x\n", val); 801 } 802 } 803 804 #ifdef notdef 805 static uint32_t 806 bge_readreg_ind(struct bge_softc *sc, int off) 807 { 808 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_REG_BASEADDR, off); 809 return (pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_REG_DATA)); 810 } 811 #endif 812 813 static void 814 bge_writereg_ind(struct bge_softc *sc, int off, int val) 815 { 816 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_REG_BASEADDR, off); 817 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_REG_DATA, val); 818 } 819 820 static void 821 bge_writemem_direct(struct bge_softc *sc, int off, int val) 822 { 823 CSR_WRITE_4(sc, off, val); 824 } 825 826 static void 827 bge_writembx(struct bge_softc *sc, int off, int val) 828 { 829 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 830 off += BGE_LPMBX_IRQ0_HI - BGE_MBX_IRQ0_HI; 831 832 CSR_WRITE_4(sc, off, val); 833 } 834 835 static void 836 bge_writembx_flush(struct bge_softc *sc, int off, int val) 837 { 838 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 839 off += BGE_LPMBX_IRQ0_HI - BGE_MBX_IRQ0_HI; 840 841 CSR_WRITE_4_FLUSH(sc, off, val); 842 } 843 844 static uint8_t 845 bge_nvram_getbyte(struct bge_softc *sc, int addr, uint8_t *dest) 846 { 847 uint32_t access, byte = 0; 848 int i; 849 850 /* Lock. */ 851 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_SET1); 852 for (i = 0; i < 8000; i++) { 853 if (CSR_READ_4(sc, BGE_NVRAM_SWARB) & BGE_NVRAMSWARB_GNT1) 854 break; 855 DELAY(20); 856 } 857 if (i == 8000) 858 return 1; 859 860 /* Enable access. */ 861 access = CSR_READ_4(sc, BGE_NVRAM_ACCESS); 862 CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access | BGE_NVRAMACC_ENABLE); 863 864 CSR_WRITE_4(sc, BGE_NVRAM_ADDR, addr & 0xfffffffc); 865 CSR_WRITE_4(sc, BGE_NVRAM_CMD, BGE_NVRAM_READCMD); 866 for (i = 0; i < BGE_TIMEOUT * 10; i++) { 867 DELAY(10); 868 if (CSR_READ_4(sc, BGE_NVRAM_CMD) & BGE_NVRAMCMD_DONE) { 869 DELAY(10); 870 break; 871 } 872 } 873 874 if (i == BGE_TIMEOUT * 10) { 875 aprint_error_dev(sc->bge_dev, "nvram read timed out\n"); 876 return 1; 877 } 878 879 /* Get result. */ 880 byte = CSR_READ_4(sc, BGE_NVRAM_RDDATA); 881 882 *dest = (bswap32(byte) >> ((addr % 4) * 8)) & 0xFF; 883 884 /* Disable access. */ 885 CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access); 886 887 /* Unlock. */ 888 CSR_WRITE_4_FLUSH(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_CLR1); 889 890 return 0; 891 } 892 893 /* 894 * Read a sequence of bytes from NVRAM. 895 */ 896 static int 897 bge_read_nvram(struct bge_softc *sc, uint8_t *dest, int off, int cnt) 898 { 899 int error = 0, i; 900 uint8_t byte = 0; 901 902 if (BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5906) 903 return 1; 904 905 for (i = 0; i < cnt; i++) { 906 error = bge_nvram_getbyte(sc, off + i, &byte); 907 if (error) 908 break; 909 *(dest + i) = byte; 910 } 911 912 return (error ? 1 : 0); 913 } 914 915 /* 916 * Read a byte of data stored in the EEPROM at address 'addr.' The 917 * BCM570x supports both the traditional bitbang interface and an 918 * auto access interface for reading the EEPROM. We use the auto 919 * access method. 920 */ 921 static uint8_t 922 bge_eeprom_getbyte(struct bge_softc *sc, int addr, uint8_t *dest) 923 { 924 int i; 925 uint32_t byte = 0; 926 927 /* 928 * Enable use of auto EEPROM access so we can avoid 929 * having to use the bitbang method. 930 */ 931 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM); 932 933 /* Reset the EEPROM, load the clock period. */ 934 CSR_WRITE_4(sc, BGE_EE_ADDR, 935 BGE_EEADDR_RESET | BGE_EEHALFCLK(BGE_HALFCLK_384SCL)); 936 DELAY(20); 937 938 /* Issue the read EEPROM command. */ 939 CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr); 940 941 /* Wait for completion */ 942 for (i = 0; i < BGE_TIMEOUT * 10; i++) { 943 DELAY(10); 944 if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE) 945 break; 946 } 947 948 if (i == BGE_TIMEOUT * 10) { 949 aprint_error_dev(sc->bge_dev, "eeprom read timed out\n"); 950 return 1; 951 } 952 953 /* Get result. */ 954 byte = CSR_READ_4(sc, BGE_EE_DATA); 955 956 *dest = (byte >> ((addr % 4) * 8)) & 0xFF; 957 958 return 0; 959 } 960 961 /* 962 * Read a sequence of bytes from the EEPROM. 963 */ 964 static int 965 bge_read_eeprom(struct bge_softc *sc, void *destv, int off, int cnt) 966 { 967 int error = 0, i; 968 uint8_t byte = 0; 969 char *dest = destv; 970 971 for (i = 0; i < cnt; i++) { 972 error = bge_eeprom_getbyte(sc, off + i, &byte); 973 if (error) 974 break; 975 *(dest + i) = byte; 976 } 977 978 return (error ? 1 : 0); 979 } 980 981 static int 982 bge_miibus_readreg(device_t dev, int phy, int reg) 983 { 984 struct bge_softc *sc = device_private(dev); 985 uint32_t val; 986 uint32_t autopoll; 987 int i; 988 989 /* 990 * Broadcom's own driver always assumes the internal 991 * PHY is at GMII address 1. On some chips, the PHY responds 992 * to accesses at all addresses, which could cause us to 993 * bogusly attach the PHY 32 times at probe type. Always 994 * restricting the lookup to address 1 is simpler than 995 * trying to figure out which chips revisions should be 996 * special-cased. 997 */ 998 if (phy != 1) 999 return 0; 1000 1001 /* Reading with autopolling on may trigger PCI errors */ 1002 autopoll = CSR_READ_4(sc, BGE_MI_MODE); 1003 if (autopoll & BGE_MIMODE_AUTOPOLL) { 1004 BGE_STS_CLRBIT(sc, BGE_STS_AUTOPOLL); 1005 BGE_CLRBIT_FLUSH(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 1006 DELAY(40); 1007 } 1008 1009 CSR_WRITE_4_FLUSH(sc, BGE_MI_COMM, BGE_MICMD_READ | BGE_MICOMM_BUSY | 1010 BGE_MIPHY(phy) | BGE_MIREG(reg)); 1011 1012 for (i = 0; i < BGE_TIMEOUT; i++) { 1013 val = CSR_READ_4(sc, BGE_MI_COMM); 1014 if (!(val & BGE_MICOMM_BUSY)) 1015 break; 1016 delay(10); 1017 } 1018 1019 if (i == BGE_TIMEOUT) { 1020 aprint_error_dev(sc->bge_dev, "PHY read timed out\n"); 1021 val = 0; 1022 goto done; 1023 } 1024 1025 val = CSR_READ_4(sc, BGE_MI_COMM); 1026 1027 done: 1028 if (autopoll & BGE_MIMODE_AUTOPOLL) { 1029 BGE_STS_SETBIT(sc, BGE_STS_AUTOPOLL); 1030 BGE_SETBIT_FLUSH(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 1031 DELAY(40); 1032 } 1033 1034 if (val & BGE_MICOMM_READFAIL) 1035 return 0; 1036 1037 return (val & 0xFFFF); 1038 } 1039 1040 static void 1041 bge_miibus_writereg(device_t dev, int phy, int reg, int val) 1042 { 1043 struct bge_softc *sc = device_private(dev); 1044 uint32_t autopoll; 1045 int i; 1046 1047 if (phy!=1) { 1048 return; 1049 } 1050 1051 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906 && 1052 (reg == BRGPHY_MII_1000CTL || reg == BRGPHY_MII_AUXCTL)) 1053 return; 1054 1055 /* Reading with autopolling on may trigger PCI errors */ 1056 autopoll = CSR_READ_4(sc, BGE_MI_MODE); 1057 if (autopoll & BGE_MIMODE_AUTOPOLL) { 1058 delay(40); 1059 BGE_STS_CLRBIT(sc, BGE_STS_AUTOPOLL); 1060 BGE_CLRBIT_FLUSH(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 1061 delay(10); /* 40 usec is supposed to be adequate */ 1062 } 1063 1064 CSR_WRITE_4_FLUSH(sc, BGE_MI_COMM, BGE_MICMD_WRITE | BGE_MICOMM_BUSY | 1065 BGE_MIPHY(phy) | BGE_MIREG(reg) | val); 1066 1067 for (i = 0; i < BGE_TIMEOUT; i++) { 1068 delay(10); 1069 if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY)) { 1070 delay(5); 1071 CSR_READ_4(sc, BGE_MI_COMM); 1072 break; 1073 } 1074 } 1075 1076 if (autopoll & BGE_MIMODE_AUTOPOLL) { 1077 BGE_STS_SETBIT(sc, BGE_STS_AUTOPOLL); 1078 BGE_SETBIT_FLUSH(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 1079 delay(40); 1080 } 1081 1082 if (i == BGE_TIMEOUT) 1083 aprint_error_dev(sc->bge_dev, "PHY read timed out\n"); 1084 } 1085 1086 static void 1087 bge_miibus_statchg(struct ifnet *ifp) 1088 { 1089 struct bge_softc *sc = ifp->if_softc; 1090 struct mii_data *mii = &sc->bge_mii; 1091 1092 /* 1093 * Get flow control negotiation result. 1094 */ 1095 if (IFM_SUBTYPE(mii->mii_media.ifm_cur->ifm_media) == IFM_AUTO && 1096 (mii->mii_media_active & IFM_ETH_FMASK) != sc->bge_flowflags) { 1097 sc->bge_flowflags = mii->mii_media_active & IFM_ETH_FMASK; 1098 mii->mii_media_active &= ~IFM_ETH_FMASK; 1099 } 1100 1101 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_PORTMODE); 1102 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T || 1103 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX) 1104 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_GMII); 1105 else 1106 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_MII); 1107 1108 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) 1109 BGE_CLRBIT_FLUSH(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX); 1110 else 1111 BGE_SETBIT_FLUSH(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX); 1112 DELAY(40); 1113 1114 /* 1115 * 802.3x flow control 1116 */ 1117 if (sc->bge_flowflags & IFM_ETH_RXPAUSE) 1118 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_FLOWCTL_ENABLE); 1119 else 1120 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_FLOWCTL_ENABLE); 1121 1122 if (sc->bge_flowflags & IFM_ETH_TXPAUSE) 1123 BGE_SETBIT(sc, BGE_TX_MODE, BGE_TXMODE_FLOWCTL_ENABLE); 1124 else 1125 BGE_CLRBIT(sc, BGE_TX_MODE, BGE_TXMODE_FLOWCTL_ENABLE); 1126 } 1127 1128 /* 1129 * Update rx threshold levels to values in a particular slot 1130 * of the interrupt-mitigation table bge_rx_threshes. 1131 */ 1132 static void 1133 bge_set_thresh(struct ifnet *ifp, int lvl) 1134 { 1135 struct bge_softc *sc = ifp->if_softc; 1136 int s; 1137 1138 /* For now, just save the new Rx-intr thresholds and record 1139 * that a threshold update is pending. Updating the hardware 1140 * registers here (even at splhigh()) is observed to 1141 * occasionaly cause glitches where Rx-interrupts are not 1142 * honoured for up to 10 seconds. jonathan (at) NetBSD.org, 2003-04-05 1143 */ 1144 s = splnet(); 1145 sc->bge_rx_coal_ticks = bge_rx_threshes[lvl].rx_ticks; 1146 sc->bge_rx_max_coal_bds = bge_rx_threshes[lvl].rx_max_bds; 1147 sc->bge_pending_rxintr_change = 1; 1148 splx(s); 1149 } 1150 1151 1152 /* 1153 * Update Rx thresholds of all bge devices 1154 */ 1155 static void 1156 bge_update_all_threshes(int lvl) 1157 { 1158 struct ifnet *ifp; 1159 const char * const namebuf = "bge"; 1160 int namelen; 1161 1162 if (lvl < 0) 1163 lvl = 0; 1164 else if (lvl >= NBGE_RX_THRESH) 1165 lvl = NBGE_RX_THRESH - 1; 1166 1167 namelen = strlen(namebuf); 1168 /* 1169 * Now search all the interfaces for this name/number 1170 */ 1171 IFNET_FOREACH(ifp) { 1172 if (strncmp(ifp->if_xname, namebuf, namelen) != 0) 1173 continue; 1174 /* We got a match: update if doing auto-threshold-tuning */ 1175 if (bge_auto_thresh) 1176 bge_set_thresh(ifp, lvl); 1177 } 1178 } 1179 1180 /* 1181 * Handle events that have triggered interrupts. 1182 */ 1183 static void 1184 bge_handle_events(struct bge_softc *sc) 1185 { 1186 1187 return; 1188 } 1189 1190 /* 1191 * Memory management for jumbo frames. 1192 */ 1193 1194 static int 1195 bge_alloc_jumbo_mem(struct bge_softc *sc) 1196 { 1197 char *ptr, *kva; 1198 bus_dma_segment_t seg; 1199 int i, rseg, state, error; 1200 struct bge_jpool_entry *entry; 1201 1202 state = error = 0; 1203 1204 /* Grab a big chunk o' storage. */ 1205 if (bus_dmamem_alloc(sc->bge_dmatag, BGE_JMEM, PAGE_SIZE, 0, 1206 &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 1207 aprint_error_dev(sc->bge_dev, "can't alloc rx buffers\n"); 1208 return ENOBUFS; 1209 } 1210 1211 state = 1; 1212 if (bus_dmamem_map(sc->bge_dmatag, &seg, rseg, BGE_JMEM, (void **)&kva, 1213 BUS_DMA_NOWAIT)) { 1214 aprint_error_dev(sc->bge_dev, 1215 "can't map DMA buffers (%d bytes)\n", (int)BGE_JMEM); 1216 error = ENOBUFS; 1217 goto out; 1218 } 1219 1220 state = 2; 1221 if (bus_dmamap_create(sc->bge_dmatag, BGE_JMEM, 1, BGE_JMEM, 0, 1222 BUS_DMA_NOWAIT, &sc->bge_cdata.bge_rx_jumbo_map)) { 1223 aprint_error_dev(sc->bge_dev, "can't create DMA map\n"); 1224 error = ENOBUFS; 1225 goto out; 1226 } 1227 1228 state = 3; 1229 if (bus_dmamap_load(sc->bge_dmatag, sc->bge_cdata.bge_rx_jumbo_map, 1230 kva, BGE_JMEM, NULL, BUS_DMA_NOWAIT)) { 1231 aprint_error_dev(sc->bge_dev, "can't load DMA map\n"); 1232 error = ENOBUFS; 1233 goto out; 1234 } 1235 1236 state = 4; 1237 sc->bge_cdata.bge_jumbo_buf = (void *)kva; 1238 DPRINTFN(1,("bge_jumbo_buf = %p\n", sc->bge_cdata.bge_jumbo_buf)); 1239 1240 SLIST_INIT(&sc->bge_jfree_listhead); 1241 SLIST_INIT(&sc->bge_jinuse_listhead); 1242 1243 /* 1244 * Now divide it up into 9K pieces and save the addresses 1245 * in an array. 1246 */ 1247 ptr = sc->bge_cdata.bge_jumbo_buf; 1248 for (i = 0; i < BGE_JSLOTS; i++) { 1249 sc->bge_cdata.bge_jslots[i] = ptr; 1250 ptr += BGE_JLEN; 1251 entry = malloc(sizeof(struct bge_jpool_entry), 1252 M_DEVBUF, M_NOWAIT); 1253 if (entry == NULL) { 1254 aprint_error_dev(sc->bge_dev, 1255 "no memory for jumbo buffer queue!\n"); 1256 error = ENOBUFS; 1257 goto out; 1258 } 1259 entry->slot = i; 1260 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, 1261 entry, jpool_entries); 1262 } 1263 out: 1264 if (error != 0) { 1265 switch (state) { 1266 case 4: 1267 bus_dmamap_unload(sc->bge_dmatag, 1268 sc->bge_cdata.bge_rx_jumbo_map); 1269 case 3: 1270 bus_dmamap_destroy(sc->bge_dmatag, 1271 sc->bge_cdata.bge_rx_jumbo_map); 1272 case 2: 1273 bus_dmamem_unmap(sc->bge_dmatag, kva, BGE_JMEM); 1274 case 1: 1275 bus_dmamem_free(sc->bge_dmatag, &seg, rseg); 1276 break; 1277 default: 1278 break; 1279 } 1280 } 1281 1282 return error; 1283 } 1284 1285 /* 1286 * Allocate a jumbo buffer. 1287 */ 1288 static void * 1289 bge_jalloc(struct bge_softc *sc) 1290 { 1291 struct bge_jpool_entry *entry; 1292 1293 entry = SLIST_FIRST(&sc->bge_jfree_listhead); 1294 1295 if (entry == NULL) { 1296 aprint_error_dev(sc->bge_dev, "no free jumbo buffers\n"); 1297 return NULL; 1298 } 1299 1300 SLIST_REMOVE_HEAD(&sc->bge_jfree_listhead, jpool_entries); 1301 SLIST_INSERT_HEAD(&sc->bge_jinuse_listhead, entry, jpool_entries); 1302 return (sc->bge_cdata.bge_jslots[entry->slot]); 1303 } 1304 1305 /* 1306 * Release a jumbo buffer. 1307 */ 1308 static void 1309 bge_jfree(struct mbuf *m, void *buf, size_t size, void *arg) 1310 { 1311 struct bge_jpool_entry *entry; 1312 struct bge_softc *sc; 1313 int i, s; 1314 1315 /* Extract the softc struct pointer. */ 1316 sc = (struct bge_softc *)arg; 1317 1318 if (sc == NULL) 1319 panic("bge_jfree: can't find softc pointer!"); 1320 1321 /* calculate the slot this buffer belongs to */ 1322 1323 i = ((char *)buf 1324 - (char *)sc->bge_cdata.bge_jumbo_buf) / BGE_JLEN; 1325 1326 if ((i < 0) || (i >= BGE_JSLOTS)) 1327 panic("bge_jfree: asked to free buffer that we don't manage!"); 1328 1329 s = splvm(); 1330 entry = SLIST_FIRST(&sc->bge_jinuse_listhead); 1331 if (entry == NULL) 1332 panic("bge_jfree: buffer not in use!"); 1333 entry->slot = i; 1334 SLIST_REMOVE_HEAD(&sc->bge_jinuse_listhead, jpool_entries); 1335 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, entry, jpool_entries); 1336 1337 if (__predict_true(m != NULL)) 1338 pool_cache_put(mb_cache, m); 1339 splx(s); 1340 } 1341 1342 1343 /* 1344 * Initialize a standard receive ring descriptor. 1345 */ 1346 static int 1347 bge_newbuf_std(struct bge_softc *sc, int i, struct mbuf *m, 1348 bus_dmamap_t dmamap) 1349 { 1350 struct mbuf *m_new = NULL; 1351 struct bge_rx_bd *r; 1352 int error; 1353 1354 if (dmamap == NULL) { 1355 error = bus_dmamap_create(sc->bge_dmatag, MCLBYTES, 1, 1356 MCLBYTES, 0, BUS_DMA_NOWAIT, &dmamap); 1357 if (error != 0) 1358 return error; 1359 } 1360 1361 sc->bge_cdata.bge_rx_std_map[i] = dmamap; 1362 1363 if (m == NULL) { 1364 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1365 if (m_new == NULL) 1366 return ENOBUFS; 1367 1368 MCLGET(m_new, M_DONTWAIT); 1369 if (!(m_new->m_flags & M_EXT)) { 1370 m_freem(m_new); 1371 return ENOBUFS; 1372 } 1373 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1374 1375 } else { 1376 m_new = m; 1377 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1378 m_new->m_data = m_new->m_ext.ext_buf; 1379 } 1380 if (!(sc->bge_flags & BGE_RX_ALIGNBUG)) 1381 m_adj(m_new, ETHER_ALIGN); 1382 if (bus_dmamap_load_mbuf(sc->bge_dmatag, dmamap, m_new, 1383 BUS_DMA_READ|BUS_DMA_NOWAIT)) 1384 return ENOBUFS; 1385 bus_dmamap_sync(sc->bge_dmatag, dmamap, 0, dmamap->dm_mapsize, 1386 BUS_DMASYNC_PREREAD); 1387 1388 sc->bge_cdata.bge_rx_std_chain[i] = m_new; 1389 r = &sc->bge_rdata->bge_rx_std_ring[i]; 1390 BGE_HOSTADDR(r->bge_addr, dmamap->dm_segs[0].ds_addr); 1391 r->bge_flags = BGE_RXBDFLAG_END; 1392 r->bge_len = m_new->m_len; 1393 r->bge_idx = i; 1394 1395 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 1396 offsetof(struct bge_ring_data, bge_rx_std_ring) + 1397 i * sizeof (struct bge_rx_bd), 1398 sizeof (struct bge_rx_bd), 1399 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1400 1401 return 0; 1402 } 1403 1404 /* 1405 * Initialize a jumbo receive ring descriptor. This allocates 1406 * a jumbo buffer from the pool managed internally by the driver. 1407 */ 1408 static int 1409 bge_newbuf_jumbo(struct bge_softc *sc, int i, struct mbuf *m) 1410 { 1411 struct mbuf *m_new = NULL; 1412 struct bge_rx_bd *r; 1413 void *buf = NULL; 1414 1415 if (m == NULL) { 1416 1417 /* Allocate the mbuf. */ 1418 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1419 if (m_new == NULL) 1420 return ENOBUFS; 1421 1422 /* Allocate the jumbo buffer */ 1423 buf = bge_jalloc(sc); 1424 if (buf == NULL) { 1425 m_freem(m_new); 1426 aprint_error_dev(sc->bge_dev, 1427 "jumbo allocation failed -- packet dropped!\n"); 1428 return ENOBUFS; 1429 } 1430 1431 /* Attach the buffer to the mbuf. */ 1432 m_new->m_len = m_new->m_pkthdr.len = BGE_JUMBO_FRAMELEN; 1433 MEXTADD(m_new, buf, BGE_JUMBO_FRAMELEN, M_DEVBUF, 1434 bge_jfree, sc); 1435 m_new->m_flags |= M_EXT_RW; 1436 } else { 1437 m_new = m; 1438 buf = m_new->m_data = m_new->m_ext.ext_buf; 1439 m_new->m_ext.ext_size = BGE_JUMBO_FRAMELEN; 1440 } 1441 if (!(sc->bge_flags & BGE_RX_ALIGNBUG)) 1442 m_adj(m_new, ETHER_ALIGN); 1443 bus_dmamap_sync(sc->bge_dmatag, sc->bge_cdata.bge_rx_jumbo_map, 1444 mtod(m_new, char *) - (char *)sc->bge_cdata.bge_jumbo_buf, BGE_JLEN, 1445 BUS_DMASYNC_PREREAD); 1446 /* Set up the descriptor. */ 1447 r = &sc->bge_rdata->bge_rx_jumbo_ring[i]; 1448 sc->bge_cdata.bge_rx_jumbo_chain[i] = m_new; 1449 BGE_HOSTADDR(r->bge_addr, BGE_JUMBO_DMA_ADDR(sc, m_new)); 1450 r->bge_flags = BGE_RXBDFLAG_END|BGE_RXBDFLAG_JUMBO_RING; 1451 r->bge_len = m_new->m_len; 1452 r->bge_idx = i; 1453 1454 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 1455 offsetof(struct bge_ring_data, bge_rx_jumbo_ring) + 1456 i * sizeof (struct bge_rx_bd), 1457 sizeof (struct bge_rx_bd), 1458 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1459 1460 return 0; 1461 } 1462 1463 /* 1464 * The standard receive ring has 512 entries in it. At 2K per mbuf cluster, 1465 * that's 1MB or memory, which is a lot. For now, we fill only the first 1466 * 256 ring entries and hope that our CPU is fast enough to keep up with 1467 * the NIC. 1468 */ 1469 static int 1470 bge_init_rx_ring_std(struct bge_softc *sc) 1471 { 1472 int i; 1473 1474 if (sc->bge_flags & BGE_RXRING_VALID) 1475 return 0; 1476 1477 for (i = 0; i < BGE_SSLOTS; i++) { 1478 if (bge_newbuf_std(sc, i, NULL, 0) == ENOBUFS) 1479 return ENOBUFS; 1480 } 1481 1482 sc->bge_std = i - 1; 1483 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std); 1484 1485 sc->bge_flags |= BGE_RXRING_VALID; 1486 1487 return 0; 1488 } 1489 1490 static void 1491 bge_free_rx_ring_std(struct bge_softc *sc) 1492 { 1493 int i; 1494 1495 if (!(sc->bge_flags & BGE_RXRING_VALID)) 1496 return; 1497 1498 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { 1499 if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) { 1500 m_freem(sc->bge_cdata.bge_rx_std_chain[i]); 1501 sc->bge_cdata.bge_rx_std_chain[i] = NULL; 1502 bus_dmamap_destroy(sc->bge_dmatag, 1503 sc->bge_cdata.bge_rx_std_map[i]); 1504 } 1505 memset((char *)&sc->bge_rdata->bge_rx_std_ring[i], 0, 1506 sizeof(struct bge_rx_bd)); 1507 } 1508 1509 sc->bge_flags &= ~BGE_RXRING_VALID; 1510 } 1511 1512 static int 1513 bge_init_rx_ring_jumbo(struct bge_softc *sc) 1514 { 1515 int i; 1516 volatile struct bge_rcb *rcb; 1517 1518 if (sc->bge_flags & BGE_JUMBO_RXRING_VALID) 1519 return 0; 1520 1521 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 1522 if (bge_newbuf_jumbo(sc, i, NULL) == ENOBUFS) 1523 return ENOBUFS; 1524 } 1525 1526 sc->bge_jumbo = i - 1; 1527 sc->bge_flags |= BGE_JUMBO_RXRING_VALID; 1528 1529 rcb = &sc->bge_rdata->bge_info.bge_jumbo_rx_rcb; 1530 rcb->bge_maxlen_flags = 0; 1531 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 1532 1533 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo); 1534 1535 return 0; 1536 } 1537 1538 static void 1539 bge_free_rx_ring_jumbo(struct bge_softc *sc) 1540 { 1541 int i; 1542 1543 if (!(sc->bge_flags & BGE_JUMBO_RXRING_VALID)) 1544 return; 1545 1546 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 1547 if (sc->bge_cdata.bge_rx_jumbo_chain[i] != NULL) { 1548 m_freem(sc->bge_cdata.bge_rx_jumbo_chain[i]); 1549 sc->bge_cdata.bge_rx_jumbo_chain[i] = NULL; 1550 } 1551 memset((char *)&sc->bge_rdata->bge_rx_jumbo_ring[i], 0, 1552 sizeof(struct bge_rx_bd)); 1553 } 1554 1555 sc->bge_flags &= ~BGE_JUMBO_RXRING_VALID; 1556 } 1557 1558 static void 1559 bge_free_tx_ring(struct bge_softc *sc) 1560 { 1561 int i; 1562 struct txdmamap_pool_entry *dma; 1563 1564 if (!(sc->bge_flags & BGE_TXRING_VALID)) 1565 return; 1566 1567 for (i = 0; i < BGE_TX_RING_CNT; i++) { 1568 if (sc->bge_cdata.bge_tx_chain[i] != NULL) { 1569 m_freem(sc->bge_cdata.bge_tx_chain[i]); 1570 sc->bge_cdata.bge_tx_chain[i] = NULL; 1571 SLIST_INSERT_HEAD(&sc->txdma_list, sc->txdma[i], 1572 link); 1573 sc->txdma[i] = 0; 1574 } 1575 memset((char *)&sc->bge_rdata->bge_tx_ring[i], 0, 1576 sizeof(struct bge_tx_bd)); 1577 } 1578 1579 while ((dma = SLIST_FIRST(&sc->txdma_list))) { 1580 SLIST_REMOVE_HEAD(&sc->txdma_list, link); 1581 bus_dmamap_destroy(sc->bge_dmatag, dma->dmamap); 1582 free(dma, M_DEVBUF); 1583 } 1584 1585 sc->bge_flags &= ~BGE_TXRING_VALID; 1586 } 1587 1588 static int 1589 bge_init_tx_ring(struct bge_softc *sc) 1590 { 1591 int i; 1592 bus_dmamap_t dmamap; 1593 struct txdmamap_pool_entry *dma; 1594 1595 if (sc->bge_flags & BGE_TXRING_VALID) 1596 return 0; 1597 1598 sc->bge_txcnt = 0; 1599 sc->bge_tx_saved_considx = 0; 1600 1601 /* Initialize transmit producer index for host-memory send ring. */ 1602 sc->bge_tx_prodidx = 0; 1603 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx); 1604 /* 5700 b2 errata */ 1605 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX) 1606 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx); 1607 1608 /* NIC-memory send ring not used; initialize to zero. */ 1609 bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0); 1610 /* 5700 b2 errata */ 1611 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX) 1612 bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0); 1613 1614 SLIST_INIT(&sc->txdma_list); 1615 for (i = 0; i < BGE_RSLOTS; i++) { 1616 if (bus_dmamap_create(sc->bge_dmatag, BGE_TXDMA_MAX, 1617 BGE_NTXSEG, ETHER_MAX_LEN_JUMBO, 0, BUS_DMA_NOWAIT, 1618 &dmamap)) 1619 return ENOBUFS; 1620 if (dmamap == NULL) 1621 panic("dmamap NULL in bge_init_tx_ring"); 1622 dma = malloc(sizeof(*dma), M_DEVBUF, M_NOWAIT); 1623 if (dma == NULL) { 1624 aprint_error_dev(sc->bge_dev, 1625 "can't alloc txdmamap_pool_entry\n"); 1626 bus_dmamap_destroy(sc->bge_dmatag, dmamap); 1627 return ENOMEM; 1628 } 1629 dma->dmamap = dmamap; 1630 SLIST_INSERT_HEAD(&sc->txdma_list, dma, link); 1631 } 1632 1633 sc->bge_flags |= BGE_TXRING_VALID; 1634 1635 return 0; 1636 } 1637 1638 static void 1639 bge_setmulti(struct bge_softc *sc) 1640 { 1641 struct ethercom *ac = &sc->ethercom; 1642 struct ifnet *ifp = &ac->ec_if; 1643 struct ether_multi *enm; 1644 struct ether_multistep step; 1645 uint32_t hashes[4] = { 0, 0, 0, 0 }; 1646 uint32_t h; 1647 int i; 1648 1649 if (ifp->if_flags & IFF_PROMISC) 1650 goto allmulti; 1651 1652 /* Now program new ones. */ 1653 ETHER_FIRST_MULTI(step, ac, enm); 1654 while (enm != NULL) { 1655 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1656 /* 1657 * We must listen to a range of multicast addresses. 1658 * For now, just accept all multicasts, rather than 1659 * trying to set only those filter bits needed to match 1660 * the range. (At this time, the only use of address 1661 * ranges is for IP multicast routing, for which the 1662 * range is big enough to require all bits set.) 1663 */ 1664 goto allmulti; 1665 } 1666 1667 h = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN); 1668 1669 /* Just want the 7 least-significant bits. */ 1670 h &= 0x7f; 1671 1672 hashes[(h & 0x60) >> 5] |= 1 << (h & 0x1F); 1673 ETHER_NEXT_MULTI(step, enm); 1674 } 1675 1676 ifp->if_flags &= ~IFF_ALLMULTI; 1677 goto setit; 1678 1679 allmulti: 1680 ifp->if_flags |= IFF_ALLMULTI; 1681 hashes[0] = hashes[1] = hashes[2] = hashes[3] = 0xffffffff; 1682 1683 setit: 1684 for (i = 0; i < 4; i++) 1685 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]); 1686 } 1687 1688 static void 1689 bge_sig_pre_reset(struct bge_softc *sc, int type) 1690 { 1691 1692 /* 1693 * Some chips don't like this so only do this if ASF is enabled 1694 */ 1695 if (sc->bge_asf_mode) 1696 bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM, BGE_MAGIC_NUMBER); 1697 1698 if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) { 1699 switch (type) { 1700 case BGE_RESET_START: 1701 bge_writemem_ind(sc, BGE_SDI_STATUS, 0x1); /* START */ 1702 break; 1703 case BGE_RESET_STOP: 1704 bge_writemem_ind(sc, BGE_SDI_STATUS, 0x2); /* UNLOAD */ 1705 break; 1706 } 1707 } 1708 } 1709 1710 static void 1711 bge_sig_post_reset(struct bge_softc *sc, int type) 1712 { 1713 1714 if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) { 1715 switch (type) { 1716 case BGE_RESET_START: 1717 bge_writemem_ind(sc, BGE_SDI_STATUS, 0x80000001); 1718 /* START DONE */ 1719 break; 1720 case BGE_RESET_STOP: 1721 bge_writemem_ind(sc, BGE_SDI_STATUS, 0x80000002); 1722 break; 1723 } 1724 } 1725 } 1726 1727 static void 1728 bge_sig_legacy(struct bge_softc *sc, int type) 1729 { 1730 1731 if (sc->bge_asf_mode) { 1732 switch (type) { 1733 case BGE_RESET_START: 1734 bge_writemem_ind(sc, BGE_SDI_STATUS, 0x1); /* START */ 1735 break; 1736 case BGE_RESET_STOP: 1737 bge_writemem_ind(sc, BGE_SDI_STATUS, 0x2); /* UNLOAD */ 1738 break; 1739 } 1740 } 1741 } 1742 1743 static void 1744 bge_stop_fw(struct bge_softc *sc) 1745 { 1746 int i; 1747 1748 if (sc->bge_asf_mode) { 1749 bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM_FW, BGE_FW_PAUSE); 1750 CSR_WRITE_4_FLUSH(sc, BGE_CPU_EVENT, 1751 CSR_READ_4(sc, BGE_CPU_EVENT) | (1 << 14)); 1752 1753 for (i = 0; i < 100; i++) { 1754 if (!(CSR_READ_4(sc, BGE_CPU_EVENT) & (1 << 14))) 1755 break; 1756 DELAY(10); 1757 } 1758 } 1759 } 1760 1761 static int 1762 bge_poll_fw(struct bge_softc *sc) 1763 { 1764 uint32_t val; 1765 int i; 1766 1767 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 1768 for (i = 0; i < BGE_TIMEOUT; i++) { 1769 val = CSR_READ_4(sc, BGE_VCPU_STATUS); 1770 if (val & BGE_VCPU_STATUS_INIT_DONE) 1771 break; 1772 DELAY(100); 1773 } 1774 if (i >= BGE_TIMEOUT) { 1775 aprint_error_dev(sc->bge_dev, "reset timed out\n"); 1776 return -1; 1777 } 1778 } else if ((sc->bge_flags & BGE_NO_EEPROM) == 0) { 1779 /* 1780 * Poll the value location we just wrote until 1781 * we see the 1's complement of the magic number. 1782 * This indicates that the firmware initialization 1783 * is complete. 1784 * XXX 1000ms for Flash and 10000ms for SEEPROM. 1785 */ 1786 for (i = 0; i < BGE_TIMEOUT; i++) { 1787 val = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM); 1788 if (val == ~BGE_MAGIC_NUMBER) 1789 break; 1790 DELAY(10); 1791 } 1792 1793 if (i >= BGE_TIMEOUT) { 1794 aprint_error_dev(sc->bge_dev, 1795 "firmware handshake timed out, val = %x\n", val); 1796 return -1; 1797 } 1798 } 1799 1800 if (sc->bge_chipid == BGE_CHIPID_BCM57765_A0) { 1801 /* tg3 says we have to wait extra time */ 1802 delay(10 * 1000); 1803 } 1804 1805 return 0; 1806 } 1807 1808 /* 1809 * Do endian, PCI and DMA initialization. Also check the on-board ROM 1810 * self-test results. 1811 */ 1812 static int 1813 bge_chipinit(struct bge_softc *sc) 1814 { 1815 uint32_t dma_rw_ctl, mode_ctl, reg; 1816 int i; 1817 1818 /* Set endianness before we access any non-PCI registers. */ 1819 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MISC_CTL, 1820 BGE_INIT); 1821 1822 /* Set power state to D0. */ 1823 bge_setpowerstate(sc, 0); 1824 1825 /* Clear the MAC control register */ 1826 CSR_WRITE_4(sc, BGE_MAC_MODE, 0); 1827 1828 /* 1829 * Clear the MAC statistics block in the NIC's 1830 * internal memory. 1831 */ 1832 for (i = BGE_STATS_BLOCK; 1833 i < BGE_STATS_BLOCK_END + 1; i += sizeof(uint32_t)) 1834 BGE_MEMWIN_WRITE(sc->sc_pc, sc->sc_pcitag, i, 0); 1835 1836 for (i = BGE_STATUS_BLOCK; 1837 i < BGE_STATUS_BLOCK_END + 1; i += sizeof(uint32_t)) 1838 BGE_MEMWIN_WRITE(sc->sc_pc, sc->sc_pcitag, i, 0); 1839 1840 /* 5717 workaround from tg3 */ 1841 if (sc->bge_chipid == BGE_CHIPID_BCM5717_A0) { 1842 /* Save */ 1843 mode_ctl = CSR_READ_4(sc, BGE_MODE_CTL); 1844 1845 /* Temporary modify MODE_CTL to control TLP */ 1846 reg = mode_ctl & ~BGE_MODECTL_PCIE_TLPADDRMASK; 1847 CSR_WRITE_4(sc, BGE_MODE_CTL, reg | BGE_MODECTL_PCIE_TLPADDR1); 1848 1849 /* Control TLP */ 1850 reg = CSR_READ_4(sc, BGE_TLP_CONTROL_REG + 1851 BGE_TLP_PHYCTL1); 1852 CSR_WRITE_4(sc, BGE_TLP_CONTROL_REG + BGE_TLP_PHYCTL1, 1853 reg | BGE_TLP_PHYCTL1_EN_L1PLLPD); 1854 1855 /* Restore */ 1856 CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl); 1857 } 1858 1859 /* XXX Should we use 57765_FAMILY? */ 1860 if (BGE_IS_57765_PLUS(sc)) { 1861 if (sc->bge_chipid == BGE_CHIPID_BCM57765_A0) { 1862 /* Save */ 1863 mode_ctl = CSR_READ_4(sc, BGE_MODE_CTL); 1864 1865 /* Temporary modify MODE_CTL to control TLP */ 1866 reg = mode_ctl & ~BGE_MODECTL_PCIE_TLPADDRMASK; 1867 CSR_WRITE_4(sc, BGE_MODE_CTL, 1868 reg | BGE_MODECTL_PCIE_TLPADDR1); 1869 1870 /* Control TLP */ 1871 reg = CSR_READ_4(sc, BGE_TLP_CONTROL_REG + 1872 BGE_TLP_PHYCTL5); 1873 CSR_WRITE_4(sc, BGE_TLP_CONTROL_REG + BGE_TLP_PHYCTL5, 1874 reg | BGE_TLP_PHYCTL5_DIS_L2CLKREQ); 1875 1876 /* Restore */ 1877 CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl); 1878 } 1879 if (BGE_CHIPREV(sc->bge_chipid) != BGE_CHIPREV_57765_AX) { 1880 reg = CSR_READ_4(sc, BGE_CPMU_PADRNG_CTL); 1881 CSR_WRITE_4(sc, BGE_CPMU_PADRNG_CTL, 1882 reg | BGE_CPMU_PADRNG_CTL_RDIV2); 1883 1884 /* Save */ 1885 mode_ctl = CSR_READ_4(sc, BGE_MODE_CTL); 1886 1887 /* Temporary modify MODE_CTL to control TLP */ 1888 reg = mode_ctl & ~BGE_MODECTL_PCIE_TLPADDRMASK; 1889 CSR_WRITE_4(sc, BGE_MODE_CTL, 1890 reg | BGE_MODECTL_PCIE_TLPADDR0); 1891 1892 /* Control TLP */ 1893 reg = CSR_READ_4(sc, BGE_TLP_CONTROL_REG + 1894 BGE_TLP_FTSMAX); 1895 reg &= ~BGE_TLP_FTSMAX_MSK; 1896 CSR_WRITE_4(sc, BGE_TLP_CONTROL_REG + BGE_TLP_FTSMAX, 1897 reg | BGE_TLP_FTSMAX_VAL); 1898 1899 /* Restore */ 1900 CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl); 1901 } 1902 1903 reg = CSR_READ_4(sc, BGE_CPMU_LSPD_10MB_CLK); 1904 reg &= ~BGE_CPMU_LSPD_10MB_MACCLK_MASK; 1905 reg |= BGE_CPMU_LSPD_10MB_MACCLK_6_25; 1906 CSR_WRITE_4(sc, BGE_CPMU_LSPD_10MB_CLK, reg); 1907 } 1908 1909 /* Set up the PCI DMA control register. */ 1910 dma_rw_ctl = BGE_PCI_READ_CMD | BGE_PCI_WRITE_CMD; 1911 if (sc->bge_flags & BGE_PCIE) { 1912 /* Read watermark not used, 128 bytes for write. */ 1913 DPRINTFN(4, ("(%s: PCI-Express DMA setting)\n", 1914 device_xname(sc->bge_dev))); 1915 dma_rw_ctl |= BGE_PCIDMARWCTL_WR_WAT_SHIFT(3); 1916 } else if (sc->bge_flags & BGE_PCIX) { 1917 DPRINTFN(4, ("(:%s: PCI-X DMA setting)\n", 1918 device_xname(sc->bge_dev))); 1919 /* PCI-X bus */ 1920 if (BGE_IS_5714_FAMILY(sc)) { 1921 /* 256 bytes for read and write. */ 1922 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(2) | 1923 BGE_PCIDMARWCTL_WR_WAT_SHIFT(2); 1924 1925 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5780) 1926 dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL; 1927 else 1928 dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE_LOCAL; 1929 } else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) { 1930 /* 1536 bytes for read, 384 bytes for write. */ 1931 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(7) | 1932 BGE_PCIDMARWCTL_WR_WAT_SHIFT(3); 1933 } else { 1934 /* 384 bytes for read and write. */ 1935 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(3) | 1936 BGE_PCIDMARWCTL_WR_WAT_SHIFT(3) | 1937 (0x0F); 1938 } 1939 1940 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5703 || 1941 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) { 1942 uint32_t tmp; 1943 1944 /* Set ONEDMA_ATONCE for hardware workaround. */ 1945 tmp = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 1946 BGE_PCI_CLKCTL) & 0x1f; 1947 if (tmp == 6 || tmp == 7) 1948 dma_rw_ctl |= 1949 BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL; 1950 1951 /* Set PCI-X DMA write workaround. */ 1952 dma_rw_ctl |= BGE_PCIDMARWCTL_ASRT_ALL_BE; 1953 } 1954 } else { 1955 /* Conventional PCI bus: 256 bytes for read and write. */ 1956 DPRINTFN(4, ("(%s: PCI 2.2 DMA setting)\n", 1957 device_xname(sc->bge_dev))); 1958 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(7) | 1959 BGE_PCIDMARWCTL_WR_WAT_SHIFT(7); 1960 1961 if (BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5705 && 1962 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5750) 1963 dma_rw_ctl |= 0x0F; 1964 } 1965 1966 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 1967 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5701) 1968 dma_rw_ctl |= BGE_PCIDMARWCTL_USE_MRM | 1969 BGE_PCIDMARWCTL_ASRT_ALL_BE; 1970 1971 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5703 || 1972 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) 1973 dma_rw_ctl &= ~BGE_PCIDMARWCTL_MINDMA; 1974 1975 if (BGE_IS_5717_PLUS(sc)) { 1976 dma_rw_ctl &= ~BGE_PCIDMARWCTL_DIS_CACHE_ALIGNMENT; 1977 if (sc->bge_chipid == BGE_CHIPID_BCM57765_A0) 1978 dma_rw_ctl &= ~BGE_PCIDMARWCTL_CRDRDR_RDMA_MRRS_MSK; 1979 1980 /* 1981 * Enable HW workaround for controllers that misinterpret 1982 * a status tag update and leave interrupts permanently 1983 * disabled. 1984 */ 1985 if (BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5717 && 1986 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM57765) 1987 dma_rw_ctl |= BGE_PCIDMARWCTL_TAGGED_STATUS_WA; 1988 } 1989 1990 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_DMA_RW_CTL, 1991 dma_rw_ctl); 1992 1993 /* 1994 * Set up general mode register. 1995 */ 1996 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS | 1997 BGE_MODECTL_MAC_ATTN_INTR | BGE_MODECTL_HOST_SEND_BDS | 1998 BGE_MODECTL_TX_NO_PHDR_CSUM); 1999 2000 /* 2001 * BCM5701 B5 have a bug causing data corruption when using 2002 * 64-bit DMA reads, which can be terminated early and then 2003 * completed later as 32-bit accesses, in combination with 2004 * certain bridges. 2005 */ 2006 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5701 && 2007 sc->bge_chipid == BGE_CHIPID_BCM5701_B5) 2008 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_FORCE_PCI32); 2009 2010 /* 2011 * Tell the firmware the driver is running 2012 */ 2013 if (sc->bge_asf_mode & ASF_STACKUP) 2014 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 2015 2016 /* 2017 * Disable memory write invalidate. Apparently it is not supported 2018 * properly by these devices. 2019 */ 2020 PCI_CLRBIT(sc->sc_pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG, 2021 PCI_COMMAND_INVALIDATE_ENABLE); 2022 2023 #ifdef __brokenalpha__ 2024 /* 2025 * Must insure that we do not cross an 8K (bytes) boundary 2026 * for DMA reads. Our highest limit is 1K bytes. This is a 2027 * restriction on some ALPHA platforms with early revision 2028 * 21174 PCI chipsets, such as the AlphaPC 164lx 2029 */ 2030 PCI_SETBIT(sc, BGE_PCI_DMA_RW_CTL, BGE_PCI_READ_BNDRY_1024, 4); 2031 #endif 2032 2033 /* Set the timer prescaler (always 66MHz) */ 2034 CSR_WRITE_4(sc, BGE_MISC_CFG, 65 << 1/*BGE_32BITTIME_66MHZ*/); 2035 2036 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 2037 DELAY(40); /* XXX */ 2038 2039 /* Put PHY into ready state */ 2040 BGE_CLRBIT_FLUSH(sc, BGE_MISC_CFG, BGE_MISCCFG_EPHY_IDDQ); 2041 DELAY(40); 2042 } 2043 2044 return 0; 2045 } 2046 2047 static int 2048 bge_blockinit(struct bge_softc *sc) 2049 { 2050 volatile struct bge_rcb *rcb; 2051 bus_size_t rcb_addr; 2052 int i; 2053 struct ifnet *ifp = &sc->ethercom.ec_if; 2054 bge_hostaddr taddr; 2055 uint32_t val; 2056 2057 /* 2058 * Initialize the memory window pointer register so that 2059 * we can access the first 32K of internal NIC RAM. This will 2060 * allow us to set up the TX send ring RCBs and the RX return 2061 * ring RCBs, plus other things which live in NIC memory. 2062 */ 2063 2064 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_BASEADDR, 0); 2065 2066 /* Step 33: Configure mbuf memory pool */ 2067 if (BGE_IS_5700_FAMILY(sc)) { 2068 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, 2069 BGE_BUFFPOOL_1); 2070 2071 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) 2072 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000); 2073 else 2074 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000); 2075 2076 /* Configure DMA resource pool */ 2077 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_BASEADDR, 2078 BGE_DMA_DESCRIPTORS); 2079 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LEN, 0x2000); 2080 } 2081 2082 /* Step 35: Configure mbuf pool watermarks */ 2083 #ifdef ORIG_WPAUL_VALUES 2084 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 24); 2085 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 24); 2086 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 48); 2087 #else 2088 2089 /* new broadcom docs strongly recommend these: */ 2090 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5717 || 2091 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57765 || 2092 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57766) { 2093 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0); 2094 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x2a); 2095 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0xa0); 2096 } else if (BGE_IS_5705_PLUS(sc)) { 2097 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0); 2098 2099 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 2100 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x04); 2101 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x10); 2102 } else { 2103 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x10); 2104 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60); 2105 } 2106 } else if (!BGE_IS_5705_PLUS(sc)) { 2107 if (ifp->if_mtu > ETHER_MAX_LEN) { 2108 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x50); 2109 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x20); 2110 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60); 2111 } else { 2112 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 304); 2113 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 152); 2114 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 380); 2115 } 2116 } else { 2117 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0); 2118 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x10); 2119 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60); 2120 } 2121 #endif 2122 2123 /* Step 36: Configure DMA resource watermarks */ 2124 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5); 2125 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10); 2126 2127 /* Step 38: Enable buffer manager */ 2128 CSR_WRITE_4(sc, BGE_BMAN_MODE, 2129 BGE_BMANMODE_ENABLE | BGE_BMANMODE_LOMBUF_ATTN); 2130 2131 /* Step 39: Poll for buffer manager start indication */ 2132 for (i = 0; i < BGE_TIMEOUT * 2; i++) { 2133 if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE) 2134 break; 2135 DELAY(10); 2136 } 2137 2138 if (i == BGE_TIMEOUT * 2) { 2139 aprint_error_dev(sc->bge_dev, 2140 "buffer manager failed to start\n"); 2141 return ENXIO; 2142 } 2143 2144 /* Step 40: Enable flow-through queues */ 2145 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 2146 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 2147 2148 /* Wait until queue initialization is complete */ 2149 for (i = 0; i < BGE_TIMEOUT * 2; i++) { 2150 if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0) 2151 break; 2152 DELAY(10); 2153 } 2154 2155 if (i == BGE_TIMEOUT * 2) { 2156 aprint_error_dev(sc->bge_dev, 2157 "flow-through queue init failed\n"); 2158 return ENXIO; 2159 } 2160 2161 /* Step 41: Initialize the standard RX ring control block */ 2162 rcb = &sc->bge_rdata->bge_info.bge_std_rx_rcb; 2163 BGE_HOSTADDR(rcb->bge_hostaddr, BGE_RING_DMA_ADDR(sc, bge_rx_std_ring)); 2164 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5717 || 2165 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57765 || 2166 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57766) 2167 rcb->bge_maxlen_flags = 2168 BGE_RCB_MAXLEN_FLAGS(512, BGE_MAX_FRAMELEN << 2); 2169 else if (BGE_IS_5705_PLUS(sc)) 2170 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(512, 0); 2171 else 2172 rcb->bge_maxlen_flags = 2173 BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 0); 2174 rcb->bge_nicaddr = BGE_STD_RX_RINGS; 2175 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcb->bge_hostaddr.bge_addr_hi); 2176 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcb->bge_hostaddr.bge_addr_lo); 2177 CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 2178 CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcb->bge_nicaddr); 2179 2180 /* 2181 * Step 42: Initialize the jumbo RX ring control block 2182 * We set the 'ring disabled' bit in the flags 2183 * field until we're actually ready to start 2184 * using this ring (i.e. once we set the MTU 2185 * high enough to require it). 2186 */ 2187 if (BGE_IS_JUMBO_CAPABLE(sc)) { 2188 rcb = &sc->bge_rdata->bge_info.bge_jumbo_rx_rcb; 2189 BGE_HOSTADDR(rcb->bge_hostaddr, 2190 BGE_RING_DMA_ADDR(sc, bge_rx_jumbo_ring)); 2191 rcb->bge_maxlen_flags = 2192 BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 2193 BGE_RCB_FLAG_RING_DISABLED); 2194 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS; 2195 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI, 2196 rcb->bge_hostaddr.bge_addr_hi); 2197 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO, 2198 rcb->bge_hostaddr.bge_addr_lo); 2199 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, 2200 rcb->bge_maxlen_flags); 2201 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcb->bge_nicaddr); 2202 2203 /* Set up dummy disabled mini ring RCB */ 2204 rcb = &sc->bge_rdata->bge_info.bge_mini_rx_rcb; 2205 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0, 2206 BGE_RCB_FLAG_RING_DISABLED); 2207 CSR_WRITE_4(sc, BGE_RX_MINI_RCB_MAXLEN_FLAGS, 2208 rcb->bge_maxlen_flags); 2209 2210 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 2211 offsetof(struct bge_ring_data, bge_info), 2212 sizeof (struct bge_gib), 2213 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2214 } 2215 2216 /* Choose de-pipeline mode for BCM5906 A0, A1 and A2. */ 2217 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 2218 if (sc->bge_chipid == BGE_CHIPID_BCM5906_A0 || 2219 sc->bge_chipid == BGE_CHIPID_BCM5906_A1 || 2220 sc->bge_chipid == BGE_CHIPID_BCM5906_A2) 2221 CSR_WRITE_4(sc, BGE_ISO_PKT_TX, 2222 (CSR_READ_4(sc, BGE_ISO_PKT_TX) & ~3) | 2); 2223 } 2224 /* 2225 * Set the BD ring replenish thresholds. The recommended 2226 * values are 1/8th the number of descriptors allocated to 2227 * each ring. 2228 */ 2229 i = BGE_STD_RX_RING_CNT / 8; 2230 2231 /* 2232 * Use a value of 8 for the following chips to workaround HW errata. 2233 * Some of these chips have been added based on empirical 2234 * evidence (they don't work unless this is done). 2235 */ 2236 if (BGE_IS_5705_PLUS(sc)) 2237 i = 8; 2238 2239 CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, i); 2240 CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH, BGE_JUMBO_RX_RING_CNT / 8); 2241 2242 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5717 || 2243 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57765 || 2244 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57766) { 2245 CSR_WRITE_4(sc, BGE_STD_REPL_LWM, 4); 2246 CSR_WRITE_4(sc, BGE_JUMBO_REPL_LWM, 4); 2247 } 2248 2249 /* 2250 * Disable all unused send rings by setting the 'ring disabled' 2251 * bit in the flags field of all the TX send ring control blocks. 2252 * These are located in NIC memory. 2253 */ 2254 rcb_addr = BGE_MEMWIN_START + BGE_SEND_RING_RCB; 2255 for (i = 0; i < BGE_TX_RINGS_EXTSSRAM_MAX; i++) { 2256 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 2257 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED)); 2258 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 0); 2259 rcb_addr += sizeof(struct bge_rcb); 2260 } 2261 2262 /* Configure TX RCB 0 (we use only the first ring) */ 2263 rcb_addr = BGE_MEMWIN_START + BGE_SEND_RING_RCB; 2264 BGE_HOSTADDR(taddr, BGE_RING_DMA_ADDR(sc, bge_tx_ring)); 2265 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi); 2266 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo); 2267 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 2268 BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT)); 2269 if (BGE_IS_5700_FAMILY(sc)) 2270 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 2271 BGE_RCB_MAXLEN_FLAGS(BGE_TX_RING_CNT, 0)); 2272 2273 /* Disable all unused RX return rings */ 2274 rcb_addr = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB; 2275 for (i = 0; i < BGE_RX_RINGS_MAX; i++) { 2276 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_hi, 0); 2277 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_lo, 0); 2278 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 2279 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 2280 BGE_RCB_FLAG_RING_DISABLED)); 2281 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 0); 2282 bge_writembx(sc, BGE_MBX_RX_CONS0_LO + 2283 (i * (sizeof(uint64_t))), 0); 2284 rcb_addr += sizeof(struct bge_rcb); 2285 } 2286 2287 /* Initialize RX ring indexes */ 2288 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, 0); 2289 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0); 2290 bge_writembx(sc, BGE_MBX_RX_MINI_PROD_LO, 0); 2291 2292 /* 2293 * Set up RX return ring 0 2294 * Note that the NIC address for RX return rings is 0x00000000. 2295 * The return rings live entirely within the host, so the 2296 * nicaddr field in the RCB isn't used. 2297 */ 2298 rcb_addr = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB; 2299 BGE_HOSTADDR(taddr, BGE_RING_DMA_ADDR(sc, bge_rx_return_ring)); 2300 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi); 2301 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo); 2302 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 0x00000000); 2303 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 2304 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 0)); 2305 2306 /* Set random backoff seed for TX */ 2307 CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF, 2308 CLLADDR(ifp->if_sadl)[0] + CLLADDR(ifp->if_sadl)[1] + 2309 CLLADDR(ifp->if_sadl)[2] + CLLADDR(ifp->if_sadl)[3] + 2310 CLLADDR(ifp->if_sadl)[4] + CLLADDR(ifp->if_sadl)[5] + 2311 BGE_TX_BACKOFF_SEED_MASK); 2312 2313 /* Set inter-packet gap */ 2314 CSR_WRITE_4(sc, BGE_TX_LENGTHS, 0x2620); 2315 2316 /* 2317 * Specify which ring to use for packets that don't match 2318 * any RX rules. 2319 */ 2320 CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08); 2321 2322 /* 2323 * Configure number of RX lists. One interrupt distribution 2324 * list, sixteen active lists, one bad frames class. 2325 */ 2326 CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181); 2327 2328 /* Inialize RX list placement stats mask. */ 2329 CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF); 2330 CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1); 2331 2332 /* Disable host coalescing until we get it set up */ 2333 CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000); 2334 2335 /* Poll to make sure it's shut down. */ 2336 for (i = 0; i < BGE_TIMEOUT * 2; i++) { 2337 if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE)) 2338 break; 2339 DELAY(10); 2340 } 2341 2342 if (i == BGE_TIMEOUT * 2) { 2343 aprint_error_dev(sc->bge_dev, 2344 "host coalescing engine failed to idle\n"); 2345 return ENXIO; 2346 } 2347 2348 /* Set up host coalescing defaults */ 2349 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bge_rx_coal_ticks); 2350 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bge_tx_coal_ticks); 2351 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bge_rx_max_coal_bds); 2352 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bge_tx_max_coal_bds); 2353 if (BGE_IS_5700_FAMILY(sc)) { 2354 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT, 0); 2355 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT, 0); 2356 } 2357 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 0); 2358 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 0); 2359 2360 /* Set up address of statistics block */ 2361 if (BGE_IS_5700_FAMILY(sc)) { 2362 BGE_HOSTADDR(taddr, BGE_RING_DMA_ADDR(sc, bge_info.bge_stats)); 2363 CSR_WRITE_4(sc, BGE_HCC_STATS_TICKS, sc->bge_stat_ticks); 2364 CSR_WRITE_4(sc, BGE_HCC_STATS_BASEADDR, BGE_STATS_BLOCK); 2365 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_HI, taddr.bge_addr_hi); 2366 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_LO, taddr.bge_addr_lo); 2367 } 2368 2369 /* Set up address of status block */ 2370 BGE_HOSTADDR(taddr, BGE_RING_DMA_ADDR(sc, bge_status_block)); 2371 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_BASEADDR, BGE_STATUS_BLOCK); 2372 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI, taddr.bge_addr_hi); 2373 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO, taddr.bge_addr_lo); 2374 sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx = 0; 2375 sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx = 0; 2376 2377 /* Turn on host coalescing state machine */ 2378 CSR_WRITE_4(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE); 2379 2380 /* Turn on RX BD completion state machine and enable attentions */ 2381 CSR_WRITE_4(sc, BGE_RBDC_MODE, 2382 BGE_RBDCMODE_ENABLE | BGE_RBDCMODE_ATTN); 2383 2384 /* Turn on RX list placement state machine */ 2385 CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 2386 2387 /* Turn on RX list selector state machine. */ 2388 if (BGE_IS_5700_FAMILY(sc)) 2389 CSR_WRITE_4(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 2390 2391 val = BGE_MACMODE_TXDMA_ENB | BGE_MACMODE_RXDMA_ENB | 2392 BGE_MACMODE_RX_STATS_CLEAR | BGE_MACMODE_TX_STATS_CLEAR | 2393 BGE_MACMODE_RX_STATS_ENB | BGE_MACMODE_TX_STATS_ENB | 2394 BGE_MACMODE_FRMHDR_DMA_ENB; 2395 2396 if (sc->bge_flags & BGE_PHY_FIBER_TBI) 2397 val |= BGE_PORTMODE_TBI; 2398 else if (sc->bge_flags & BGE_PHY_FIBER_MII) 2399 val |= BGE_PORTMODE_GMII; 2400 else 2401 val |= BGE_PORTMODE_MII; 2402 2403 /* Turn on DMA, clear stats */ 2404 CSR_WRITE_4_FLUSH(sc, BGE_MAC_MODE, val); 2405 DELAY(40); 2406 2407 /* Set misc. local control, enable interrupts on attentions */ 2408 sc->bge_local_ctrl_reg = BGE_MLC_INTR_ONATTN | BGE_MLC_AUTO_EEPROM; 2409 2410 #ifdef notdef 2411 /* Assert GPIO pins for PHY reset */ 2412 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUT0| 2413 BGE_MLC_MISCIO_OUT1|BGE_MLC_MISCIO_OUT2); 2414 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUTEN0| 2415 BGE_MLC_MISCIO_OUTEN1|BGE_MLC_MISCIO_OUTEN2); 2416 #endif 2417 2418 #if defined(not_quite_yet) 2419 /* Linux driver enables enable gpio pin #1 on 5700s */ 2420 if (sc->bge_chipid == BGE_CHIPID_BCM5700) { 2421 sc->bge_local_ctrl_reg |= 2422 (BGE_MLC_MISCIO_OUT1|BGE_MLC_MISCIO_OUTEN1); 2423 } 2424 #endif 2425 CSR_WRITE_4(sc, BGE_MISC_LOCAL_CTL, sc->bge_local_ctrl_reg); 2426 2427 /* Turn on DMA completion state machine */ 2428 if (BGE_IS_5700_FAMILY(sc)) 2429 CSR_WRITE_4(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 2430 2431 val = BGE_WDMAMODE_ENABLE | BGE_WDMAMODE_ALL_ATTNS; 2432 2433 /* Enable host coalescing bug fix */ 2434 if (BGE_IS_5755_PLUS(sc)) 2435 val |= BGE_WDMAMODE_STATUS_TAG_FIX; 2436 2437 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785) 2438 val |= BGE_WDMAMODE_BURST_ALL_DATA; 2439 2440 /* Turn on write DMA state machine */ 2441 CSR_WRITE_4_FLUSH(sc, BGE_WDMA_MODE, val); 2442 DELAY(40); 2443 2444 val = BGE_RDMAMODE_ENABLE | BGE_RDMAMODE_ALL_ATTNS; 2445 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5784 || 2446 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785 || 2447 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57780) 2448 val |= BGE_RDMAMODE_BD_SBD_CRPT_ATTN | 2449 BGE_RDMAMODE_MBUF_RBD_CRPT_ATTN | 2450 BGE_RDMAMODE_MBUF_SBD_CRPT_ATTN; 2451 2452 if (sc->bge_flags & BGE_PCIE) 2453 val |= BGE_RDMAMODE_FIFO_LONG_BURST; 2454 if (sc->bge_flags & BGE_TSO) 2455 val |= BGE_RDMAMODE_TSO4_ENABLE; 2456 2457 /* Turn on read DMA state machine */ 2458 CSR_WRITE_4_FLUSH(sc, BGE_RDMA_MODE, val); 2459 delay(40); 2460 2461 /* Turn on RX data completion state machine */ 2462 CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 2463 2464 /* Turn on RX BD initiator state machine */ 2465 CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 2466 2467 /* Turn on RX data and RX BD initiator state machine */ 2468 CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE); 2469 2470 /* Turn on Mbuf cluster free state machine */ 2471 if (BGE_IS_5700_FAMILY(sc)) 2472 CSR_WRITE_4(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 2473 2474 /* Turn on send BD completion state machine */ 2475 CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 2476 2477 /* Turn on send data completion state machine */ 2478 val = BGE_SDCMODE_ENABLE; 2479 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761) 2480 val |= BGE_SDCMODE_CDELAY; 2481 CSR_WRITE_4(sc, BGE_SDC_MODE, val); 2482 2483 /* Turn on send data initiator state machine */ 2484 if (sc->bge_flags & BGE_TSO) { 2485 /* XXX: magic value from Linux driver */ 2486 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE | 0x08); 2487 } else 2488 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 2489 2490 /* Turn on send BD initiator state machine */ 2491 CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 2492 2493 /* Turn on send BD selector state machine */ 2494 CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 2495 2496 CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF); 2497 CSR_WRITE_4(sc, BGE_SDI_STATS_CTL, 2498 BGE_SDISTATSCTL_ENABLE | BGE_SDISTATSCTL_FASTER); 2499 2500 /* ack/clear link change events */ 2501 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED | 2502 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE | 2503 BGE_MACSTAT_LINK_CHANGED); 2504 CSR_WRITE_4(sc, BGE_MI_STS, 0); 2505 2506 /* Enable PHY auto polling (for MII/GMII only) */ 2507 if (sc->bge_flags & BGE_PHY_FIBER_TBI) { 2508 CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK); 2509 } else { 2510 BGE_STS_SETBIT(sc, BGE_STS_AUTOPOLL); 2511 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL | (10 << 16)); 2512 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700) 2513 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, 2514 BGE_EVTENB_MI_INTERRUPT); 2515 } 2516 2517 /* 2518 * Clear any pending link state attention. 2519 * Otherwise some link state change events may be lost until attention 2520 * is cleared by bge_intr() -> bge_link_upd() sequence. 2521 * It's not necessary on newer BCM chips - perhaps enabling link 2522 * state change attentions implies clearing pending attention. 2523 */ 2524 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED | 2525 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE | 2526 BGE_MACSTAT_LINK_CHANGED); 2527 2528 /* Enable link state change attentions. */ 2529 BGE_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED); 2530 2531 return 0; 2532 } 2533 2534 static const struct bge_revision * 2535 bge_lookup_rev(uint32_t chipid) 2536 { 2537 const struct bge_revision *br; 2538 2539 for (br = bge_revisions; br->br_name != NULL; br++) { 2540 if (br->br_chipid == chipid) 2541 return br; 2542 } 2543 2544 for (br = bge_majorrevs; br->br_name != NULL; br++) { 2545 if (br->br_chipid == BGE_ASICREV(chipid)) 2546 return br; 2547 } 2548 2549 return NULL; 2550 } 2551 2552 static const struct bge_product * 2553 bge_lookup(const struct pci_attach_args *pa) 2554 { 2555 const struct bge_product *bp; 2556 2557 for (bp = bge_products; bp->bp_name != NULL; bp++) { 2558 if (PCI_VENDOR(pa->pa_id) == bp->bp_vendor && 2559 PCI_PRODUCT(pa->pa_id) == bp->bp_product) 2560 return bp; 2561 } 2562 2563 return NULL; 2564 } 2565 2566 static int 2567 bge_setpowerstate(struct bge_softc *sc, int powerlevel) 2568 { 2569 #ifdef NOTYET 2570 uint32_t pm_ctl = 0; 2571 2572 /* XXX FIXME: make sure indirect accesses enabled? */ 2573 pm_ctl = pci_conf_read(sc->bge_dev, BGE_PCI_MISC_CTL, 4); 2574 pm_ctl |= BGE_PCIMISCCTL_INDIRECT_ACCESS; 2575 pci_write_config(sc->bge_dev, BGE_PCI_MISC_CTL, pm_ctl, 4); 2576 2577 /* clear the PME_assert bit and power state bits, enable PME */ 2578 pm_ctl = pci_conf_read(sc->bge_dev, BGE_PCI_PWRMGMT_CMD, 2); 2579 pm_ctl &= ~PCIM_PSTAT_DMASK; 2580 pm_ctl |= (1 << 8); 2581 2582 if (powerlevel == 0) { 2583 pm_ctl |= PCIM_PSTAT_D0; 2584 pci_write_config(sc->bge_dev, BGE_PCI_PWRMGMT_CMD, 2585 pm_ctl, 2); 2586 DELAY(10000); 2587 CSR_WRITE_4(sc, BGE_MISC_LOCAL_CTL, sc->bge_local_ctrl_reg); 2588 DELAY(10000); 2589 2590 #ifdef NOTYET 2591 /* XXX FIXME: write 0x02 to phy aux_Ctrl reg */ 2592 bge_miibus_writereg(sc->bge_dev, 1, 0x18, 0x02); 2593 #endif 2594 DELAY(40); DELAY(40); DELAY(40); 2595 DELAY(10000); /* above not quite adequate on 5700 */ 2596 return 0; 2597 } 2598 2599 2600 /* 2601 * Entering ACPI power states D1-D3 is achieved by wiggling 2602 * GMII gpio pins. Example code assumes all hardware vendors 2603 * followed Broadcom's sample pcb layout. Until we verify that 2604 * for all supported OEM cards, states D1-D3 are unsupported. 2605 */ 2606 aprint_error_dev(sc->bge_dev, 2607 "power state %d unimplemented; check GPIO pins\n", 2608 powerlevel); 2609 #endif 2610 return EOPNOTSUPP; 2611 } 2612 2613 2614 /* 2615 * Probe for a Broadcom chip. Check the PCI vendor and device IDs 2616 * against our list and return its name if we find a match. Note 2617 * that since the Broadcom controller contains VPD support, we 2618 * can get the device name string from the controller itself instead 2619 * of the compiled-in string. This is a little slow, but it guarantees 2620 * we'll always announce the right product name. 2621 */ 2622 static int 2623 bge_probe(device_t parent, cfdata_t match, void *aux) 2624 { 2625 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 2626 2627 if (bge_lookup(pa) != NULL) 2628 return 1; 2629 2630 return 0; 2631 } 2632 2633 static void 2634 bge_attach(device_t parent, device_t self, void *aux) 2635 { 2636 struct bge_softc *sc = device_private(self); 2637 struct pci_attach_args *pa = aux; 2638 prop_dictionary_t dict; 2639 const struct bge_product *bp; 2640 const struct bge_revision *br; 2641 pci_chipset_tag_t pc; 2642 pci_intr_handle_t ih; 2643 const char *intrstr = NULL; 2644 bus_dma_segment_t seg; 2645 int rseg; 2646 uint32_t hwcfg = 0; 2647 uint32_t command; 2648 struct ifnet *ifp; 2649 uint32_t misccfg; 2650 void * kva; 2651 u_char eaddr[ETHER_ADDR_LEN]; 2652 pcireg_t memtype, subid; 2653 bus_addr_t memaddr; 2654 bus_size_t memsize; 2655 uint32_t pm_ctl; 2656 bool no_seeprom; 2657 2658 bp = bge_lookup(pa); 2659 KASSERT(bp != NULL); 2660 2661 sc->sc_pc = pa->pa_pc; 2662 sc->sc_pcitag = pa->pa_tag; 2663 sc->bge_dev = self; 2664 2665 pc = sc->sc_pc; 2666 subid = pci_conf_read(pc, sc->sc_pcitag, PCI_SUBSYS_ID_REG); 2667 2668 aprint_naive(": Ethernet controller\n"); 2669 aprint_normal(": %s\n", bp->bp_name); 2670 2671 /* 2672 * Map control/status registers. 2673 */ 2674 DPRINTFN(5, ("Map control/status regs\n")); 2675 command = pci_conf_read(pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG); 2676 command |= PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_MASTER_ENABLE; 2677 pci_conf_write(pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG, command); 2678 command = pci_conf_read(pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG); 2679 2680 if (!(command & PCI_COMMAND_MEM_ENABLE)) { 2681 aprint_error_dev(sc->bge_dev, 2682 "failed to enable memory mapping!\n"); 2683 return; 2684 } 2685 2686 DPRINTFN(5, ("pci_mem_find\n")); 2687 memtype = pci_mapreg_type(sc->sc_pc, sc->sc_pcitag, BGE_PCI_BAR0); 2688 switch (memtype) { 2689 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 2690 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 2691 if (pci_mapreg_map(pa, BGE_PCI_BAR0, 2692 memtype, 0, &sc->bge_btag, &sc->bge_bhandle, 2693 &memaddr, &memsize) == 0) 2694 break; 2695 default: 2696 aprint_error_dev(sc->bge_dev, "can't find mem space\n"); 2697 return; 2698 } 2699 2700 DPRINTFN(5, ("pci_intr_map\n")); 2701 if (pci_intr_map(pa, &ih)) { 2702 aprint_error_dev(sc->bge_dev, "couldn't map interrupt\n"); 2703 return; 2704 } 2705 2706 DPRINTFN(5, ("pci_intr_string\n")); 2707 intrstr = pci_intr_string(pc, ih); 2708 2709 DPRINTFN(5, ("pci_intr_establish\n")); 2710 sc->bge_intrhand = pci_intr_establish(pc, ih, IPL_NET, bge_intr, sc); 2711 2712 if (sc->bge_intrhand == NULL) { 2713 aprint_error_dev(sc->bge_dev, 2714 "couldn't establish interrupt%s%s\n", 2715 intrstr ? " at " : "", intrstr ? intrstr : ""); 2716 return; 2717 } 2718 aprint_normal_dev(sc->bge_dev, "interrupting at %s\n", intrstr); 2719 2720 /* 2721 * Kludge for 5700 Bx bug: a hardware bug (PCIX byte enable?) 2722 * can clobber the chip's PCI config-space power control registers, 2723 * leaving the card in D3 powersave state. 2724 * We do not have memory-mapped registers in this state, 2725 * so force device into D0 state before starting initialization. 2726 */ 2727 pm_ctl = pci_conf_read(pc, sc->sc_pcitag, BGE_PCI_PWRMGMT_CMD); 2728 pm_ctl &= ~(PCI_PWR_D0|PCI_PWR_D1|PCI_PWR_D2|PCI_PWR_D3); 2729 pm_ctl |= (1 << 8) | PCI_PWR_D0 ; /* D0 state */ 2730 pci_conf_write(pc, sc->sc_pcitag, BGE_PCI_PWRMGMT_CMD, pm_ctl); 2731 DELAY(1000); /* 27 usec is allegedly sufficent */ 2732 2733 /* 2734 * Save ASIC rev. 2735 */ 2736 sc->bge_chipid = 2737 pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_MISC_CTL) 2738 >> BGE_PCIMISCCTL_ASICREV_SHIFT; 2739 2740 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_USE_PRODID_REG) { 2741 switch (PCI_PRODUCT(pa->pa_id)) { 2742 case PCI_PRODUCT_BROADCOM_BCM5717: 2743 case PCI_PRODUCT_BROADCOM_BCM5718: 2744 case PCI_PRODUCT_BROADCOM_BCM5724: /* ??? */ 2745 sc->bge_chipid = pci_conf_read(pc, pa->pa_tag, 2746 BGE_PCI_GEN2_PRODID_ASICREV); 2747 break; 2748 case PCI_PRODUCT_BROADCOM_BCM57761: 2749 case PCI_PRODUCT_BROADCOM_BCM57762: 2750 case PCI_PRODUCT_BROADCOM_BCM57765: 2751 case PCI_PRODUCT_BROADCOM_BCM57781: 2752 case PCI_PRODUCT_BROADCOM_BCM57785: 2753 case PCI_PRODUCT_BROADCOM_BCM57791: 2754 case PCI_PRODUCT_BROADCOM_BCM57795: 2755 sc->bge_chipid = pci_conf_read(pc, pa->pa_tag, 2756 BGE_PCI_GEN15_PRODID_ASICREV); 2757 break; 2758 default: 2759 sc->bge_chipid = pci_conf_read(pc, pa->pa_tag, 2760 BGE_PCI_PRODID_ASICREV); 2761 break; 2762 } 2763 } 2764 2765 if ((pci_get_capability(sc->sc_pc, sc->sc_pcitag, PCI_CAP_PCIEXPRESS, 2766 &sc->bge_pciecap, NULL) != 0) 2767 || (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785)) { 2768 /* PCIe */ 2769 sc->bge_flags |= BGE_PCIE; 2770 bge_set_max_readrq(sc); 2771 } else if ((pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_PCISTATE) & 2772 BGE_PCISTATE_PCI_BUSMODE) == 0) { 2773 /* PCI-X */ 2774 sc->bge_flags |= BGE_PCIX; 2775 if (pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_PCIX, 2776 &sc->bge_pcixcap, NULL) == 0) 2777 aprint_error_dev(sc->bge_dev, 2778 "unable to find PCIX capability\n"); 2779 } 2780 2781 /* chipid */ 2782 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 2783 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5701 || 2784 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5703 || 2785 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) 2786 sc->bge_flags |= BGE_5700_FAMILY; 2787 2788 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5714_A0 || 2789 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5780 || 2790 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5714) 2791 sc->bge_flags |= BGE_5714_FAMILY; 2792 2793 /* Intentionally exclude BGE_ASICREV_BCM5906 */ 2794 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5717 || 2795 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5755 || 2796 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761 || 2797 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5784 || 2798 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785 || 2799 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5787 || 2800 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57765 || 2801 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57766 || 2802 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57780) 2803 sc->bge_flags |= BGE_5755_PLUS; 2804 2805 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5750 || 2806 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5752 || 2807 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906 || 2808 BGE_IS_5755_PLUS(sc) || 2809 BGE_IS_5714_FAMILY(sc)) 2810 sc->bge_flags |= BGE_575X_PLUS; 2811 2812 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5705 || 2813 BGE_IS_575X_PLUS(sc)) 2814 sc->bge_flags |= BGE_5705_PLUS; 2815 2816 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57765 || 2817 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57766) 2818 sc->bge_flags |= BGE_57765_PLUS; 2819 2820 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5717 || 2821 BGE_IS_57765_PLUS(sc)) 2822 sc->bge_flags |= BGE_5717_PLUS; 2823 /* 2824 * When using the BCM5701 in PCI-X mode, data corruption has 2825 * been observed in the first few bytes of some received packets. 2826 * Aligning the packet buffer in memory eliminates the corruption. 2827 * Unfortunately, this misaligns the packet payloads. On platforms 2828 * which do not support unaligned accesses, we will realign the 2829 * payloads by copying the received packets. 2830 */ 2831 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5701 && 2832 sc->bge_flags & BGE_PCIX) 2833 sc->bge_flags |= BGE_RX_ALIGNBUG; 2834 2835 if (BGE_IS_5700_FAMILY(sc)) 2836 sc->bge_flags |= BGE_JUMBO_CAPABLE; 2837 2838 if ((BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 2839 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5701) && 2840 PCI_VENDOR(subid) == PCI_VENDOR_DELL) 2841 sc->bge_flags |= BGE_NO_3LED; 2842 2843 misccfg = CSR_READ_4(sc, BGE_MISC_CFG); 2844 misccfg &= BGE_MISCCFG_BOARD_ID_MASK; 2845 2846 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5705 && 2847 (misccfg == BGE_MISCCFG_BOARD_ID_5788 || 2848 misccfg == BGE_MISCCFG_BOARD_ID_5788M)) 2849 sc->bge_flags |= BGE_IS_5788; 2850 2851 /* 2852 * Some controllers seem to require a special firmware to use 2853 * TSO. But the firmware is not available to FreeBSD and Linux 2854 * claims that the TSO performed by the firmware is slower than 2855 * hardware based TSO. Moreover the firmware based TSO has one 2856 * known bug which can't handle TSO if ethernet header + IP/TCP 2857 * header is greater than 80 bytes. The workaround for the TSO 2858 * bug exist but it seems it's too expensive than not using 2859 * TSO at all. Some hardwares also have the TSO bug so limit 2860 * the TSO to the controllers that are not affected TSO issues 2861 * (e.g. 5755 or higher). 2862 */ 2863 if (BGE_IS_5755_PLUS(sc)) { 2864 /* 2865 * BCM5754 and BCM5787 shares the same ASIC id so 2866 * explicit device id check is required. 2867 */ 2868 if ((PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_BROADCOM_BCM5754) && 2869 (PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_BROADCOM_BCM5754M)) 2870 sc->bge_flags |= BGE_TSO; 2871 } 2872 2873 if ((BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5703 && 2874 (misccfg == 0x4000 || misccfg == 0x8000)) || 2875 (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5705 && 2876 PCI_VENDOR(pa->pa_id) == PCI_VENDOR_BROADCOM && 2877 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5901 || 2878 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5901A2 || 2879 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5705F)) || 2880 (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_BROADCOM && 2881 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5751F || 2882 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5753F || 2883 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5787F)) || 2884 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM57790 || 2885 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 2886 sc->bge_flags |= BGE_10_100_ONLY; 2887 2888 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 2889 (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5705 && 2890 (sc->bge_chipid != BGE_CHIPID_BCM5705_A0 && 2891 sc->bge_chipid != BGE_CHIPID_BCM5705_A1)) || 2892 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 2893 sc->bge_flags |= BGE_NO_ETH_WIRE_SPEED; 2894 2895 if (sc->bge_chipid == BGE_CHIPID_BCM5701_A0 || 2896 sc->bge_chipid == BGE_CHIPID_BCM5701_B0) 2897 sc->bge_flags |= BGE_PHY_CRC_BUG; 2898 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5703_AX || 2899 BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5704_AX) 2900 sc->bge_flags |= BGE_PHY_ADC_BUG; 2901 if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0) 2902 sc->bge_flags |= BGE_PHY_5704_A0_BUG; 2903 2904 if (BGE_IS_5705_PLUS(sc) && 2905 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5906 && 2906 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5717 && 2907 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5785 && 2908 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM57765 && 2909 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM57766 && 2910 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM57780) { 2911 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5755 || 2912 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761 || 2913 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5784 || 2914 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5787) { 2915 if (PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_BROADCOM_BCM5722 && 2916 PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_BROADCOM_BCM5756) 2917 sc->bge_flags |= BGE_PHY_JITTER_BUG; 2918 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5755M) 2919 sc->bge_flags |= BGE_PHY_ADJUST_TRIM; 2920 } else if (BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5906) 2921 sc->bge_flags |= BGE_PHY_BER_BUG; 2922 } 2923 2924 /* 2925 * SEEPROM check. 2926 * First check if firmware knows we do not have SEEPROM. 2927 */ 2928 if (prop_dictionary_get_bool(device_properties(self), 2929 "without-seeprom", &no_seeprom) && no_seeprom) 2930 sc->bge_flags |= BGE_NO_EEPROM; 2931 2932 /* Now check the 'ROM failed' bit on the RX CPU */ 2933 else if (CSR_READ_4(sc, BGE_RXCPU_MODE) & BGE_RXCPUMODE_ROMFAIL) 2934 sc->bge_flags |= BGE_NO_EEPROM; 2935 2936 /* Identify the chips that use an CPMU. */ 2937 if (BGE_IS_5717_PLUS(sc) || 2938 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5784 || 2939 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761 || 2940 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785 || 2941 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57780) 2942 sc->bge_flags |= BGE_CPMU_PRESENT; 2943 2944 /* Try to reset the chip. */ 2945 DPRINTFN(5, ("bge_reset\n")); 2946 bge_reset(sc); 2947 2948 sc->bge_asf_mode = 0; 2949 if (bge_allow_asf && (bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_SIG) 2950 == BGE_MAGIC_NUMBER)) { 2951 if (bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_NICCFG) 2952 & BGE_HWCFG_ASF) { 2953 sc->bge_asf_mode |= ASF_ENABLE; 2954 sc->bge_asf_mode |= ASF_STACKUP; 2955 if (BGE_IS_575X_PLUS(sc)) { 2956 sc->bge_asf_mode |= ASF_NEW_HANDSHAKE; 2957 } 2958 } 2959 } 2960 2961 /* Try to reset the chip again the nice way. */ 2962 bge_stop_fw(sc); 2963 bge_sig_pre_reset(sc, BGE_RESET_STOP); 2964 if (bge_reset(sc)) 2965 aprint_error_dev(sc->bge_dev, "chip reset failed\n"); 2966 2967 bge_sig_legacy(sc, BGE_RESET_STOP); 2968 bge_sig_post_reset(sc, BGE_RESET_STOP); 2969 2970 if (bge_chipinit(sc)) { 2971 aprint_error_dev(sc->bge_dev, "chip initialization failed\n"); 2972 bge_release_resources(sc); 2973 return; 2974 } 2975 2976 /* 2977 * Get station address from the EEPROM. 2978 */ 2979 if (bge_get_eaddr(sc, eaddr)) { 2980 aprint_error_dev(sc->bge_dev, 2981 "failed to read station address\n"); 2982 bge_release_resources(sc); 2983 return; 2984 } 2985 2986 br = bge_lookup_rev(sc->bge_chipid); 2987 2988 if (br == NULL) { 2989 aprint_normal_dev(sc->bge_dev, "unknown ASIC (0x%x)", 2990 sc->bge_chipid); 2991 } else { 2992 aprint_normal_dev(sc->bge_dev, "ASIC %s (0x%x)", 2993 br->br_name, sc->bge_chipid); 2994 } 2995 aprint_normal(", Ethernet address %s\n", ether_sprintf(eaddr)); 2996 2997 /* Allocate the general information block and ring buffers. */ 2998 if (pci_dma64_available(pa)) 2999 sc->bge_dmatag = pa->pa_dmat64; 3000 else 3001 sc->bge_dmatag = pa->pa_dmat; 3002 DPRINTFN(5, ("bus_dmamem_alloc\n")); 3003 if (bus_dmamem_alloc(sc->bge_dmatag, sizeof(struct bge_ring_data), 3004 PAGE_SIZE, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 3005 aprint_error_dev(sc->bge_dev, "can't alloc rx buffers\n"); 3006 return; 3007 } 3008 DPRINTFN(5, ("bus_dmamem_map\n")); 3009 if (bus_dmamem_map(sc->bge_dmatag, &seg, rseg, 3010 sizeof(struct bge_ring_data), &kva, 3011 BUS_DMA_NOWAIT)) { 3012 aprint_error_dev(sc->bge_dev, 3013 "can't map DMA buffers (%zu bytes)\n", 3014 sizeof(struct bge_ring_data)); 3015 bus_dmamem_free(sc->bge_dmatag, &seg, rseg); 3016 return; 3017 } 3018 DPRINTFN(5, ("bus_dmamem_create\n")); 3019 if (bus_dmamap_create(sc->bge_dmatag, sizeof(struct bge_ring_data), 1, 3020 sizeof(struct bge_ring_data), 0, 3021 BUS_DMA_NOWAIT, &sc->bge_ring_map)) { 3022 aprint_error_dev(sc->bge_dev, "can't create DMA map\n"); 3023 bus_dmamem_unmap(sc->bge_dmatag, kva, 3024 sizeof(struct bge_ring_data)); 3025 bus_dmamem_free(sc->bge_dmatag, &seg, rseg); 3026 return; 3027 } 3028 DPRINTFN(5, ("bus_dmamem_load\n")); 3029 if (bus_dmamap_load(sc->bge_dmatag, sc->bge_ring_map, kva, 3030 sizeof(struct bge_ring_data), NULL, 3031 BUS_DMA_NOWAIT)) { 3032 bus_dmamap_destroy(sc->bge_dmatag, sc->bge_ring_map); 3033 bus_dmamem_unmap(sc->bge_dmatag, kva, 3034 sizeof(struct bge_ring_data)); 3035 bus_dmamem_free(sc->bge_dmatag, &seg, rseg); 3036 return; 3037 } 3038 3039 DPRINTFN(5, ("bzero\n")); 3040 sc->bge_rdata = (struct bge_ring_data *)kva; 3041 3042 memset(sc->bge_rdata, 0, sizeof(struct bge_ring_data)); 3043 3044 /* Try to allocate memory for jumbo buffers. */ 3045 if (BGE_IS_JUMBO_CAPABLE(sc)) { 3046 if (bge_alloc_jumbo_mem(sc)) { 3047 aprint_error_dev(sc->bge_dev, 3048 "jumbo buffer allocation failed\n"); 3049 } else 3050 sc->ethercom.ec_capabilities |= ETHERCAP_JUMBO_MTU; 3051 } 3052 3053 /* Set default tuneable values. */ 3054 sc->bge_stat_ticks = BGE_TICKS_PER_SEC; 3055 sc->bge_rx_coal_ticks = 150; 3056 sc->bge_rx_max_coal_bds = 64; 3057 #ifdef ORIG_WPAUL_VALUES 3058 sc->bge_tx_coal_ticks = 150; 3059 sc->bge_tx_max_coal_bds = 128; 3060 #else 3061 sc->bge_tx_coal_ticks = 300; 3062 sc->bge_tx_max_coal_bds = 400; 3063 #endif 3064 if (BGE_IS_5705_PLUS(sc)) { 3065 sc->bge_tx_coal_ticks = (12 * 5); 3066 sc->bge_tx_max_coal_bds = (12 * 5); 3067 aprint_verbose_dev(sc->bge_dev, 3068 "setting short Tx thresholds\n"); 3069 } 3070 3071 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5717 || 3072 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57765 || 3073 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57766) 3074 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT; 3075 else if (BGE_IS_5705_PLUS(sc)) 3076 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT_5705; 3077 else 3078 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT; 3079 3080 /* Set up ifnet structure */ 3081 ifp = &sc->ethercom.ec_if; 3082 ifp->if_softc = sc; 3083 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 3084 ifp->if_ioctl = bge_ioctl; 3085 ifp->if_stop = bge_stop; 3086 ifp->if_start = bge_start; 3087 ifp->if_init = bge_init; 3088 ifp->if_watchdog = bge_watchdog; 3089 IFQ_SET_MAXLEN(&ifp->if_snd, max(BGE_TX_RING_CNT - 1, IFQ_MAXLEN)); 3090 IFQ_SET_READY(&ifp->if_snd); 3091 DPRINTFN(5, ("strcpy if_xname\n")); 3092 strcpy(ifp->if_xname, device_xname(sc->bge_dev)); 3093 3094 if (sc->bge_chipid != BGE_CHIPID_BCM5700_B0) 3095 sc->ethercom.ec_if.if_capabilities |= 3096 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx; 3097 #if 1 /* XXX TCP/UDP checksum offload breaks with pf(4) */ 3098 sc->ethercom.ec_if.if_capabilities |= 3099 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 3100 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 3101 #endif 3102 sc->ethercom.ec_capabilities |= 3103 ETHERCAP_VLAN_HWTAGGING | ETHERCAP_VLAN_MTU; 3104 3105 if (sc->bge_flags & BGE_TSO) 3106 sc->ethercom.ec_if.if_capabilities |= IFCAP_TSOv4; 3107 3108 /* 3109 * Do MII setup. 3110 */ 3111 DPRINTFN(5, ("mii setup\n")); 3112 sc->bge_mii.mii_ifp = ifp; 3113 sc->bge_mii.mii_readreg = bge_miibus_readreg; 3114 sc->bge_mii.mii_writereg = bge_miibus_writereg; 3115 sc->bge_mii.mii_statchg = bge_miibus_statchg; 3116 3117 /* 3118 * Figure out what sort of media we have by checking the hardware 3119 * config word in the first 32k of NIC internal memory, or fall back to 3120 * the config word in the EEPROM. Note: on some BCM5700 cards, 3121 * this value appears to be unset. If that's the case, we have to rely 3122 * on identifying the NIC by its PCI subsystem ID, as we do below for 3123 * the SysKonnect SK-9D41. 3124 */ 3125 if (bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_SIG) == BGE_MAGIC_NUMBER) { 3126 hwcfg = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_NICCFG); 3127 } else if (!(sc->bge_flags & BGE_NO_EEPROM)) { 3128 bge_read_eeprom(sc, (void *)&hwcfg, 3129 BGE_EE_HWCFG_OFFSET, sizeof(hwcfg)); 3130 hwcfg = be32toh(hwcfg); 3131 } 3132 /* The SysKonnect SK-9D41 is a 1000baseSX card. */ 3133 if (PCI_PRODUCT(pa->pa_id) == SK_SUBSYSID_9D41 || 3134 (hwcfg & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER) { 3135 if (BGE_IS_5714_FAMILY(sc)) 3136 sc->bge_flags |= BGE_PHY_FIBER_MII; 3137 else 3138 sc->bge_flags |= BGE_PHY_FIBER_TBI; 3139 } 3140 3141 /* set phyflags and chipid before mii_attach() */ 3142 dict = device_properties(self); 3143 prop_dictionary_set_uint32(dict, "phyflags", sc->bge_flags); 3144 prop_dictionary_set_uint32(dict, "chipid", sc->bge_chipid); 3145 3146 if (sc->bge_flags & BGE_PHY_FIBER_TBI) { 3147 ifmedia_init(&sc->bge_ifmedia, IFM_IMASK, bge_ifmedia_upd, 3148 bge_ifmedia_sts); 3149 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER |IFM_1000_SX, 0, NULL); 3150 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_1000_SX|IFM_FDX, 3151 0, NULL); 3152 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_AUTO, 0, NULL); 3153 ifmedia_set(&sc->bge_ifmedia, IFM_ETHER | IFM_AUTO); 3154 /* Pretend the user requested this setting */ 3155 sc->bge_ifmedia.ifm_media = sc->bge_ifmedia.ifm_cur->ifm_media; 3156 } else { 3157 /* 3158 * Do transceiver setup and tell the firmware the 3159 * driver is down so we can try to get access the 3160 * probe if ASF is running. Retry a couple of times 3161 * if we get a conflict with the ASF firmware accessing 3162 * the PHY. 3163 */ 3164 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 3165 bge_asf_driver_up(sc); 3166 3167 ifmedia_init(&sc->bge_mii.mii_media, 0, bge_ifmedia_upd, 3168 bge_ifmedia_sts); 3169 mii_attach(sc->bge_dev, &sc->bge_mii, 0xffffffff, 3170 MII_PHY_ANY, MII_OFFSET_ANY, 3171 MIIF_FORCEANEG|MIIF_DOPAUSE); 3172 3173 if (LIST_EMPTY(&sc->bge_mii.mii_phys)) { 3174 aprint_error_dev(sc->bge_dev, "no PHY found!\n"); 3175 ifmedia_add(&sc->bge_mii.mii_media, 3176 IFM_ETHER|IFM_MANUAL, 0, NULL); 3177 ifmedia_set(&sc->bge_mii.mii_media, 3178 IFM_ETHER|IFM_MANUAL); 3179 } else 3180 ifmedia_set(&sc->bge_mii.mii_media, 3181 IFM_ETHER|IFM_AUTO); 3182 3183 /* 3184 * Now tell the firmware we are going up after probing the PHY 3185 */ 3186 if (sc->bge_asf_mode & ASF_STACKUP) 3187 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 3188 } 3189 3190 /* 3191 * Call MI attach routine. 3192 */ 3193 DPRINTFN(5, ("if_attach\n")); 3194 if_attach(ifp); 3195 DPRINTFN(5, ("ether_ifattach\n")); 3196 ether_ifattach(ifp, eaddr); 3197 ether_set_ifflags_cb(&sc->ethercom, bge_ifflags_cb); 3198 rnd_attach_source(&sc->rnd_source, device_xname(sc->bge_dev), 3199 RND_TYPE_NET, 0); 3200 #ifdef BGE_EVENT_COUNTERS 3201 /* 3202 * Attach event counters. 3203 */ 3204 evcnt_attach_dynamic(&sc->bge_ev_intr, EVCNT_TYPE_INTR, 3205 NULL, device_xname(sc->bge_dev), "intr"); 3206 evcnt_attach_dynamic(&sc->bge_ev_tx_xoff, EVCNT_TYPE_MISC, 3207 NULL, device_xname(sc->bge_dev), "tx_xoff"); 3208 evcnt_attach_dynamic(&sc->bge_ev_tx_xon, EVCNT_TYPE_MISC, 3209 NULL, device_xname(sc->bge_dev), "tx_xon"); 3210 evcnt_attach_dynamic(&sc->bge_ev_rx_xoff, EVCNT_TYPE_MISC, 3211 NULL, device_xname(sc->bge_dev), "rx_xoff"); 3212 evcnt_attach_dynamic(&sc->bge_ev_rx_xon, EVCNT_TYPE_MISC, 3213 NULL, device_xname(sc->bge_dev), "rx_xon"); 3214 evcnt_attach_dynamic(&sc->bge_ev_rx_macctl, EVCNT_TYPE_MISC, 3215 NULL, device_xname(sc->bge_dev), "rx_macctl"); 3216 evcnt_attach_dynamic(&sc->bge_ev_xoffentered, EVCNT_TYPE_MISC, 3217 NULL, device_xname(sc->bge_dev), "xoffentered"); 3218 #endif /* BGE_EVENT_COUNTERS */ 3219 DPRINTFN(5, ("callout_init\n")); 3220 callout_init(&sc->bge_timeout, 0); 3221 3222 if (pmf_device_register(self, NULL, NULL)) 3223 pmf_class_network_register(self, ifp); 3224 else 3225 aprint_error_dev(self, "couldn't establish power handler\n"); 3226 3227 bge_sysctl_init(sc); 3228 3229 #ifdef BGE_DEBUG 3230 bge_debug_info(sc); 3231 #endif 3232 } 3233 3234 static void 3235 bge_release_resources(struct bge_softc *sc) 3236 { 3237 if (sc->bge_vpd_prodname != NULL) 3238 free(sc->bge_vpd_prodname, M_DEVBUF); 3239 3240 if (sc->bge_vpd_readonly != NULL) 3241 free(sc->bge_vpd_readonly, M_DEVBUF); 3242 } 3243 3244 static int 3245 bge_reset(struct bge_softc *sc) 3246 { 3247 uint32_t cachesize, command, pcistate, marbmode; 3248 #if 0 3249 uint32_t new_pcistate; 3250 #endif 3251 pcireg_t devctl, reg; 3252 int i, val; 3253 void (*write_op)(struct bge_softc *, int, int); 3254 3255 if (BGE_IS_575X_PLUS(sc) && !BGE_IS_5714_FAMILY(sc) 3256 && (BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5906)) { 3257 if (sc->bge_flags & BGE_PCIE) 3258 write_op = bge_writemem_direct; 3259 else 3260 write_op = bge_writemem_ind; 3261 } else 3262 write_op = bge_writereg_ind; 3263 3264 /* Save some important PCI state. */ 3265 cachesize = pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CACHESZ); 3266 command = pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CMD); 3267 pcistate = pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_PCISTATE); 3268 3269 /* Step 5a: Enable memory arbiter. */ 3270 marbmode = 0; 3271 if (BGE_IS_5714_FAMILY(sc)) 3272 marbmode = CSR_READ_4(sc, BGE_MARB_MODE); 3273 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE | marbmode); 3274 3275 /* Step 5b-5d: */ 3276 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MISC_CTL, 3277 BGE_PCIMISCCTL_INDIRECT_ACCESS | BGE_PCIMISCCTL_MASK_PCI_INTR | 3278 BGE_HIF_SWAP_OPTIONS | BGE_PCIMISCCTL_PCISTATE_RW); 3279 3280 /* XXX ???: Disable fastboot on controllers that support it. */ 3281 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5752 || 3282 BGE_IS_5755_PLUS(sc)) 3283 CSR_WRITE_4(sc, BGE_FASTBOOT_PC, 0); 3284 3285 /* 3286 * Step 6: Write the magic number to SRAM at offset 0xB50. 3287 * When firmware finishes its initialization it will 3288 * write ~BGE_MAGIC_NUMBER to the same location. 3289 */ 3290 bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM, BGE_MAGIC_NUMBER); 3291 3292 /* Step 7: */ 3293 val = BGE_MISCCFG_RESET_CORE_CLOCKS | (65<<1); 3294 /* 3295 * XXX: from FreeBSD/Linux; no documentation 3296 */ 3297 if (sc->bge_flags & BGE_PCIE) { 3298 if (BGE_ASICREV(sc->bge_chipid != BGE_ASICREV_BCM5785) && 3299 !BGE_IS_57765_PLUS(sc) && 3300 (CSR_READ_4(sc, BGE_PCIE_CTL1) == 3301 (BGE_PHY_PCIE_LTASS_MODE | BGE_PHY_PCIE_SCRAM_MODE))) { 3302 /* PCI Express 1.0 system */ 3303 CSR_WRITE_4(sc, BGE_PHY_TEST_CTRL_REG, 3304 BGE_PHY_PCIE_SCRAM_MODE); 3305 } 3306 if (sc->bge_chipid != BGE_CHIPID_BCM5750_A0) { 3307 /* 3308 * Prevent PCI Express link training 3309 * during global reset. 3310 */ 3311 CSR_WRITE_4(sc, BGE_MISC_CFG, 1 << 29); 3312 val |= (1<<29); 3313 } 3314 } 3315 3316 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 3317 i = CSR_READ_4(sc, BGE_VCPU_STATUS); 3318 CSR_WRITE_4(sc, BGE_VCPU_STATUS, 3319 i | BGE_VCPU_STATUS_DRV_RESET); 3320 i = CSR_READ_4(sc, BGE_VCPU_EXT_CTRL); 3321 CSR_WRITE_4(sc, BGE_VCPU_EXT_CTRL, 3322 i & ~BGE_VCPU_EXT_CTRL_HALT_CPU); 3323 } 3324 3325 /* 3326 * Set GPHY Power Down Override to leave GPHY 3327 * powered up in D0 uninitialized. 3328 */ 3329 if (BGE_IS_5705_PLUS(sc)) 3330 val |= BGE_MISCCFG_KEEP_GPHY_POWER; 3331 3332 /* XXX 5721, 5751 and 5752 */ 3333 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5750) 3334 val |= BGE_MISCCFG_GRC_RESET_DISABLE; 3335 3336 /* Issue global reset */ 3337 write_op(sc, BGE_MISC_CFG, val); 3338 3339 /* Step 8: wait for complete */ 3340 if (sc->bge_flags & BGE_PCIE) 3341 delay(100*1000); /* too big */ 3342 else 3343 delay(100); 3344 3345 /* From Linux: dummy read to flush PCI posted writes */ 3346 reg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CMD); 3347 3348 /* Step 9-10: Reset some of the PCI state that got zapped by reset */ 3349 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MISC_CTL, 3350 BGE_PCIMISCCTL_INDIRECT_ACCESS | BGE_PCIMISCCTL_MASK_PCI_INTR | 3351 BGE_HIF_SWAP_OPTIONS | BGE_PCIMISCCTL_PCISTATE_RW 3352 | BGE_PCIMISCCTL_CLOCKCTL_RW); 3353 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CMD, command); 3354 write_op(sc, BGE_MISC_CFG, (65 << 1)); 3355 3356 /* Step 11: disable PCI-X Relaxed Ordering. */ 3357 if (sc->bge_flags & BGE_PCIX) { 3358 reg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, sc->bge_pcixcap 3359 + PCI_PCIX_CMD); 3360 pci_conf_write(sc->sc_pc, sc->sc_pcitag, sc->bge_pcixcap 3361 + PCI_PCIX_CMD, reg & ~PCI_PCIX_CMD_RELAXED_ORDER); 3362 } 3363 3364 if (sc->bge_flags & BGE_PCIE) { 3365 if (sc->bge_chipid == BGE_CHIPID_BCM5750_A0) { 3366 DELAY(500000); 3367 /* XXX: Magic Numbers */ 3368 reg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 3369 BGE_PCI_UNKNOWN0); 3370 pci_conf_write(sc->sc_pc, sc->sc_pcitag, 3371 BGE_PCI_UNKNOWN0, 3372 reg | (1 << 15)); 3373 } 3374 devctl = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 3375 sc->bge_pciecap + PCI_PCIE_DCSR); 3376 /* Clear enable no snoop and disable relaxed ordering. */ 3377 devctl &= ~(PCI_PCIE_DCSR_ENA_RELAX_ORD | 3378 PCI_PCIE_DCSR_ENA_NO_SNOOP); 3379 /* Set PCIE max payload size to 128. */ 3380 devctl &= ~(0x00e0); 3381 /* Clear device status register. Write 1b to clear */ 3382 devctl |= PCI_PCIE_DCSR_URD | PCI_PCIE_DCSR_FED 3383 | PCI_PCIE_DCSR_NFED | PCI_PCIE_DCSR_CED; 3384 pci_conf_write(sc->sc_pc, sc->sc_pcitag, 3385 sc->bge_pciecap + PCI_PCIE_DCSR, devctl); 3386 } 3387 3388 /* Step 12: Enable memory arbiter. */ 3389 marbmode = 0; 3390 if (BGE_IS_5714_FAMILY(sc)) 3391 marbmode = CSR_READ_4(sc, BGE_MARB_MODE); 3392 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE | marbmode); 3393 3394 /* Step 17: Poll until the firmware initialization is complete */ 3395 bge_poll_fw(sc); 3396 3397 /* XXX 5721, 5751 and 5752 */ 3398 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5750) { 3399 /* Step 19: */ 3400 BGE_SETBIT(sc, BGE_TLP_CONTROL_REG, 1 << 29 | 1 << 25); 3401 /* Step 20: */ 3402 BGE_SETBIT(sc, BGE_TLP_CONTROL_REG, BGE_TLP_DATA_FIFO_PROTECT); 3403 } 3404 3405 /* 3406 * Step 18: wirte mac mode 3407 * XXX Write 0x0c for 5703S and 5704S 3408 */ 3409 CSR_WRITE_4_FLUSH(sc, BGE_MAC_MODE, 0); 3410 DELAY(40); 3411 3412 3413 /* Step 21: 5822 B0 errata */ 3414 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5704_BX) { 3415 pcireg_t msidata; 3416 3417 msidata = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 3418 BGE_PCI_MSI_DATA); 3419 msidata |= ((1 << 13 | 1 << 12 | 1 << 10) << 16); 3420 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MSI_DATA, 3421 msidata); 3422 } 3423 3424 /* Step 23: restore cache line size */ 3425 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CACHESZ, cachesize); 3426 3427 #if 0 3428 /* 3429 * XXX Wait for the value of the PCISTATE register to 3430 * return to its original pre-reset state. This is a 3431 * fairly good indicator of reset completion. If we don't 3432 * wait for the reset to fully complete, trying to read 3433 * from the device's non-PCI registers may yield garbage 3434 * results. 3435 */ 3436 for (i = 0; i < BGE_TIMEOUT; i++) { 3437 new_pcistate = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 3438 BGE_PCI_PCISTATE); 3439 if ((new_pcistate & ~BGE_PCISTATE_RESERVED) == 3440 (pcistate & ~BGE_PCISTATE_RESERVED)) 3441 break; 3442 DELAY(10); 3443 } 3444 if ((new_pcistate & ~BGE_PCISTATE_RESERVED) != 3445 (pcistate & ~BGE_PCISTATE_RESERVED)) { 3446 aprint_error_dev(sc->bge_dev, "pcistate failed to revert\n"); 3447 } 3448 #endif 3449 3450 /* Step 28: Fix up byte swapping */ 3451 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS); 3452 3453 /* Tell the ASF firmware we are up */ 3454 if (sc->bge_asf_mode & ASF_STACKUP) 3455 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 3456 3457 /* 3458 * The 5704 in TBI mode apparently needs some special 3459 * adjustment to insure the SERDES drive level is set 3460 * to 1.2V. 3461 */ 3462 if (sc->bge_flags & BGE_PHY_FIBER_TBI && 3463 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) { 3464 uint32_t serdescfg; 3465 3466 serdescfg = CSR_READ_4(sc, BGE_SERDES_CFG); 3467 serdescfg = (serdescfg & ~0xFFF) | 0x880; 3468 CSR_WRITE_4(sc, BGE_SERDES_CFG, serdescfg); 3469 } 3470 3471 if (sc->bge_flags & BGE_PCIE && 3472 !BGE_IS_57765_PLUS(sc) && 3473 sc->bge_chipid != BGE_CHIPID_BCM5750_A0 && 3474 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5785) { 3475 uint32_t v; 3476 3477 /* Enable PCI Express bug fix */ 3478 v = CSR_READ_4(sc, 0x7c00); 3479 CSR_WRITE_4(sc, 0x7c00, v | (1<<25)); 3480 } 3481 DELAY(10000); 3482 3483 return 0; 3484 } 3485 3486 /* 3487 * Frame reception handling. This is called if there's a frame 3488 * on the receive return list. 3489 * 3490 * Note: we have to be able to handle two possibilities here: 3491 * 1) the frame is from the jumbo receive ring 3492 * 2) the frame is from the standard receive ring 3493 */ 3494 3495 static void 3496 bge_rxeof(struct bge_softc *sc) 3497 { 3498 struct ifnet *ifp; 3499 uint16_t rx_prod, rx_cons; 3500 int stdcnt = 0, jumbocnt = 0; 3501 bus_dmamap_t dmamap; 3502 bus_addr_t offset, toff; 3503 bus_size_t tlen; 3504 int tosync; 3505 3506 rx_cons = sc->bge_rx_saved_considx; 3507 rx_prod = sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx; 3508 3509 /* Nothing to do */ 3510 if (rx_cons == rx_prod) 3511 return; 3512 3513 ifp = &sc->ethercom.ec_if; 3514 3515 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 3516 offsetof(struct bge_ring_data, bge_status_block), 3517 sizeof (struct bge_status_block), 3518 BUS_DMASYNC_POSTREAD); 3519 3520 offset = offsetof(struct bge_ring_data, bge_rx_return_ring); 3521 tosync = rx_prod - rx_cons; 3522 3523 if (tosync != 0) 3524 rnd_add_uint32(&sc->rnd_source, tosync); 3525 3526 toff = offset + (rx_cons * sizeof (struct bge_rx_bd)); 3527 3528 if (tosync < 0) { 3529 tlen = (sc->bge_return_ring_cnt - rx_cons) * 3530 sizeof (struct bge_rx_bd); 3531 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 3532 toff, tlen, BUS_DMASYNC_POSTREAD); 3533 tosync = -tosync; 3534 } 3535 3536 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 3537 offset, tosync * sizeof (struct bge_rx_bd), 3538 BUS_DMASYNC_POSTREAD); 3539 3540 while (rx_cons != rx_prod) { 3541 struct bge_rx_bd *cur_rx; 3542 uint32_t rxidx; 3543 struct mbuf *m = NULL; 3544 3545 cur_rx = &sc->bge_rdata->bge_rx_return_ring[rx_cons]; 3546 3547 rxidx = cur_rx->bge_idx; 3548 BGE_INC(rx_cons, sc->bge_return_ring_cnt); 3549 3550 if (cur_rx->bge_flags & BGE_RXBDFLAG_JUMBO_RING) { 3551 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT); 3552 m = sc->bge_cdata.bge_rx_jumbo_chain[rxidx]; 3553 sc->bge_cdata.bge_rx_jumbo_chain[rxidx] = NULL; 3554 jumbocnt++; 3555 bus_dmamap_sync(sc->bge_dmatag, 3556 sc->bge_cdata.bge_rx_jumbo_map, 3557 mtod(m, char *) - (char *)sc->bge_cdata.bge_jumbo_buf, 3558 BGE_JLEN, BUS_DMASYNC_POSTREAD); 3559 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 3560 ifp->if_ierrors++; 3561 bge_newbuf_jumbo(sc, sc->bge_jumbo, m); 3562 continue; 3563 } 3564 if (bge_newbuf_jumbo(sc, sc->bge_jumbo, 3565 NULL)== ENOBUFS) { 3566 ifp->if_ierrors++; 3567 bge_newbuf_jumbo(sc, sc->bge_jumbo, m); 3568 continue; 3569 } 3570 } else { 3571 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT); 3572 m = sc->bge_cdata.bge_rx_std_chain[rxidx]; 3573 3574 sc->bge_cdata.bge_rx_std_chain[rxidx] = NULL; 3575 stdcnt++; 3576 dmamap = sc->bge_cdata.bge_rx_std_map[rxidx]; 3577 sc->bge_cdata.bge_rx_std_map[rxidx] = 0; 3578 if (dmamap == NULL) { 3579 ifp->if_ierrors++; 3580 bge_newbuf_std(sc, sc->bge_std, m, dmamap); 3581 continue; 3582 } 3583 bus_dmamap_sync(sc->bge_dmatag, dmamap, 0, 3584 dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 3585 bus_dmamap_unload(sc->bge_dmatag, dmamap); 3586 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 3587 ifp->if_ierrors++; 3588 bge_newbuf_std(sc, sc->bge_std, m, dmamap); 3589 continue; 3590 } 3591 if (bge_newbuf_std(sc, sc->bge_std, 3592 NULL, dmamap) == ENOBUFS) { 3593 ifp->if_ierrors++; 3594 bge_newbuf_std(sc, sc->bge_std, m, dmamap); 3595 continue; 3596 } 3597 } 3598 3599 ifp->if_ipackets++; 3600 #ifndef __NO_STRICT_ALIGNMENT 3601 /* 3602 * XXX: if the 5701 PCIX-Rx-DMA workaround is in effect, 3603 * the Rx buffer has the layer-2 header unaligned. 3604 * If our CPU requires alignment, re-align by copying. 3605 */ 3606 if (sc->bge_flags & BGE_RX_ALIGNBUG) { 3607 memmove(mtod(m, char *) + ETHER_ALIGN, m->m_data, 3608 cur_rx->bge_len); 3609 m->m_data += ETHER_ALIGN; 3610 } 3611 #endif 3612 3613 m->m_pkthdr.len = m->m_len = cur_rx->bge_len - ETHER_CRC_LEN; 3614 m->m_pkthdr.rcvif = ifp; 3615 3616 /* 3617 * Handle BPF listeners. Let the BPF user see the packet. 3618 */ 3619 bpf_mtap(ifp, m); 3620 3621 m->m_pkthdr.csum_flags = M_CSUM_IPv4; 3622 3623 if ((cur_rx->bge_ip_csum ^ 0xffff) != 0) 3624 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 3625 /* 3626 * Rx transport checksum-offload may also 3627 * have bugs with packets which, when transmitted, 3628 * were `runts' requiring padding. 3629 */ 3630 if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM && 3631 (/* (sc->_bge_quirks & BGE_QUIRK_SHORT_CKSUM_BUG) == 0 ||*/ 3632 m->m_pkthdr.len >= ETHER_MIN_NOPAD)) { 3633 m->m_pkthdr.csum_data = 3634 cur_rx->bge_tcp_udp_csum; 3635 m->m_pkthdr.csum_flags |= 3636 (M_CSUM_TCPv4|M_CSUM_UDPv4| 3637 M_CSUM_DATA); 3638 } 3639 3640 /* 3641 * If we received a packet with a vlan tag, pass it 3642 * to vlan_input() instead of ether_input(). 3643 */ 3644 if (cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) { 3645 VLAN_INPUT_TAG(ifp, m, cur_rx->bge_vlan_tag, continue); 3646 } 3647 3648 (*ifp->if_input)(ifp, m); 3649 } 3650 3651 sc->bge_rx_saved_considx = rx_cons; 3652 bge_writembx(sc, BGE_MBX_RX_CONS0_LO, sc->bge_rx_saved_considx); 3653 if (stdcnt) 3654 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std); 3655 if (jumbocnt) 3656 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo); 3657 } 3658 3659 static void 3660 bge_txeof(struct bge_softc *sc) 3661 { 3662 struct bge_tx_bd *cur_tx = NULL; 3663 struct ifnet *ifp; 3664 struct txdmamap_pool_entry *dma; 3665 bus_addr_t offset, toff; 3666 bus_size_t tlen; 3667 int tosync; 3668 struct mbuf *m; 3669 3670 ifp = &sc->ethercom.ec_if; 3671 3672 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 3673 offsetof(struct bge_ring_data, bge_status_block), 3674 sizeof (struct bge_status_block), 3675 BUS_DMASYNC_POSTREAD); 3676 3677 offset = offsetof(struct bge_ring_data, bge_tx_ring); 3678 tosync = sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx - 3679 sc->bge_tx_saved_considx; 3680 3681 if (tosync != 0) 3682 rnd_add_uint32(&sc->rnd_source, tosync); 3683 3684 toff = offset + (sc->bge_tx_saved_considx * sizeof (struct bge_tx_bd)); 3685 3686 if (tosync < 0) { 3687 tlen = (BGE_TX_RING_CNT - sc->bge_tx_saved_considx) * 3688 sizeof (struct bge_tx_bd); 3689 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 3690 toff, tlen, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 3691 tosync = -tosync; 3692 } 3693 3694 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 3695 offset, tosync * sizeof (struct bge_tx_bd), 3696 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 3697 3698 /* 3699 * Go through our tx ring and free mbufs for those 3700 * frames that have been sent. 3701 */ 3702 while (sc->bge_tx_saved_considx != 3703 sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx) { 3704 uint32_t idx = 0; 3705 3706 idx = sc->bge_tx_saved_considx; 3707 cur_tx = &sc->bge_rdata->bge_tx_ring[idx]; 3708 if (cur_tx->bge_flags & BGE_TXBDFLAG_END) 3709 ifp->if_opackets++; 3710 m = sc->bge_cdata.bge_tx_chain[idx]; 3711 if (m != NULL) { 3712 sc->bge_cdata.bge_tx_chain[idx] = NULL; 3713 dma = sc->txdma[idx]; 3714 bus_dmamap_sync(sc->bge_dmatag, dma->dmamap, 0, 3715 dma->dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 3716 bus_dmamap_unload(sc->bge_dmatag, dma->dmamap); 3717 SLIST_INSERT_HEAD(&sc->txdma_list, dma, link); 3718 sc->txdma[idx] = NULL; 3719 3720 m_freem(m); 3721 } 3722 sc->bge_txcnt--; 3723 BGE_INC(sc->bge_tx_saved_considx, BGE_TX_RING_CNT); 3724 ifp->if_timer = 0; 3725 } 3726 3727 if (cur_tx != NULL) 3728 ifp->if_flags &= ~IFF_OACTIVE; 3729 } 3730 3731 static int 3732 bge_intr(void *xsc) 3733 { 3734 struct bge_softc *sc; 3735 struct ifnet *ifp; 3736 uint32_t statusword; 3737 3738 sc = xsc; 3739 ifp = &sc->ethercom.ec_if; 3740 3741 /* It is possible for the interrupt to arrive before 3742 * the status block is updated prior to the interrupt. 3743 * Reading the PCI State register will confirm whether the 3744 * interrupt is ours and will flush the status block. 3745 */ 3746 3747 /* read status word from status block */ 3748 statusword = sc->bge_rdata->bge_status_block.bge_status; 3749 3750 if ((statusword & BGE_STATFLAG_UPDATED) || 3751 (!(pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_PCISTATE) & 3752 BGE_PCISTATE_INTR_NOT_ACTIVE))) { 3753 /* Ack interrupt and stop others from occuring. */ 3754 bge_writembx_flush(sc, BGE_MBX_IRQ0_LO, 1); 3755 3756 BGE_EVCNT_INCR(sc->bge_ev_intr); 3757 3758 /* clear status word */ 3759 sc->bge_rdata->bge_status_block.bge_status = 0; 3760 3761 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 3762 statusword & BGE_STATFLAG_LINKSTATE_CHANGED || 3763 BGE_STS_BIT(sc, BGE_STS_LINK_EVT)) 3764 bge_link_upd(sc); 3765 3766 if (ifp->if_flags & IFF_RUNNING) { 3767 /* Check RX return ring producer/consumer */ 3768 bge_rxeof(sc); 3769 3770 /* Check TX ring producer/consumer */ 3771 bge_txeof(sc); 3772 } 3773 3774 if (sc->bge_pending_rxintr_change) { 3775 uint32_t rx_ticks = sc->bge_rx_coal_ticks; 3776 uint32_t rx_bds = sc->bge_rx_max_coal_bds; 3777 uint32_t junk; 3778 3779 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, rx_ticks); 3780 DELAY(10); 3781 junk = CSR_READ_4(sc, BGE_HCC_RX_COAL_TICKS); 3782 3783 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, rx_bds); 3784 DELAY(10); 3785 junk = CSR_READ_4(sc, BGE_HCC_RX_MAX_COAL_BDS); 3786 3787 sc->bge_pending_rxintr_change = 0; 3788 } 3789 bge_handle_events(sc); 3790 3791 /* Re-enable interrupts. */ 3792 bge_writembx_flush(sc, BGE_MBX_IRQ0_LO, 0); 3793 3794 if (ifp->if_flags & IFF_RUNNING && !IFQ_IS_EMPTY(&ifp->if_snd)) 3795 bge_start(ifp); 3796 3797 return 1; 3798 } else 3799 return 0; 3800 } 3801 3802 static void 3803 bge_asf_driver_up(struct bge_softc *sc) 3804 { 3805 if (sc->bge_asf_mode & ASF_STACKUP) { 3806 /* Send ASF heartbeat aprox. every 2s */ 3807 if (sc->bge_asf_count) 3808 sc->bge_asf_count --; 3809 else { 3810 sc->bge_asf_count = 2; 3811 bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM_FW, 3812 BGE_FW_DRV_ALIVE); 3813 bge_writemem_ind(sc, BGE_SOFTWARE_GENNCOMM_FW_LEN, 4); 3814 bge_writemem_ind(sc, BGE_SOFTWARE_GENNCOMM_FW_DATA, 3); 3815 CSR_WRITE_4_FLUSH(sc, BGE_CPU_EVENT, 3816 CSR_READ_4(sc, BGE_CPU_EVENT) | (1 << 14)); 3817 } 3818 } 3819 } 3820 3821 static void 3822 bge_tick(void *xsc) 3823 { 3824 struct bge_softc *sc = xsc; 3825 struct mii_data *mii = &sc->bge_mii; 3826 int s; 3827 3828 s = splnet(); 3829 3830 if (BGE_IS_5705_PLUS(sc)) 3831 bge_stats_update_regs(sc); 3832 else 3833 bge_stats_update(sc); 3834 3835 if (sc->bge_flags & BGE_PHY_FIBER_TBI) { 3836 /* 3837 * Since in TBI mode auto-polling can't be used we should poll 3838 * link status manually. Here we register pending link event 3839 * and trigger interrupt. 3840 */ 3841 BGE_STS_SETBIT(sc, BGE_STS_LINK_EVT); 3842 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET); 3843 } else { 3844 /* 3845 * Do not touch PHY if we have link up. This could break 3846 * IPMI/ASF mode or produce extra input errors. 3847 * (extra input errors was reported for bcm5701 & bcm5704). 3848 */ 3849 if (!BGE_STS_BIT(sc, BGE_STS_LINK)) 3850 mii_tick(mii); 3851 } 3852 3853 callout_reset(&sc->bge_timeout, hz, bge_tick, sc); 3854 3855 splx(s); 3856 } 3857 3858 static void 3859 bge_stats_update_regs(struct bge_softc *sc) 3860 { 3861 struct ifnet *ifp = &sc->ethercom.ec_if; 3862 3863 ifp->if_collisions += CSR_READ_4(sc, BGE_MAC_STATS + 3864 offsetof(struct bge_mac_stats_regs, etherStatsCollisions)); 3865 3866 ifp->if_ierrors += CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_DROPS); 3867 ifp->if_ierrors += CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_ERRORS); 3868 ifp->if_ierrors += CSR_READ_4(sc, BGE_RXLP_LOCSTAT_OUT_OF_BDS); 3869 } 3870 3871 static void 3872 bge_stats_update(struct bge_softc *sc) 3873 { 3874 struct ifnet *ifp = &sc->ethercom.ec_if; 3875 bus_size_t stats = BGE_MEMWIN_START + BGE_STATS_BLOCK; 3876 3877 #define READ_STAT(sc, stats, stat) \ 3878 CSR_READ_4(sc, stats + offsetof(struct bge_stats, stat)) 3879 3880 ifp->if_collisions += 3881 (READ_STAT(sc, stats, dot3StatsSingleCollisionFrames.bge_addr_lo) + 3882 READ_STAT(sc, stats, dot3StatsMultipleCollisionFrames.bge_addr_lo) + 3883 READ_STAT(sc, stats, dot3StatsExcessiveCollisions.bge_addr_lo) + 3884 READ_STAT(sc, stats, dot3StatsLateCollisions.bge_addr_lo)) - 3885 ifp->if_collisions; 3886 3887 BGE_EVCNT_UPD(sc->bge_ev_tx_xoff, 3888 READ_STAT(sc, stats, outXoffSent.bge_addr_lo)); 3889 BGE_EVCNT_UPD(sc->bge_ev_tx_xon, 3890 READ_STAT(sc, stats, outXonSent.bge_addr_lo)); 3891 BGE_EVCNT_UPD(sc->bge_ev_rx_xoff, 3892 READ_STAT(sc, stats, 3893 xoffPauseFramesReceived.bge_addr_lo)); 3894 BGE_EVCNT_UPD(sc->bge_ev_rx_xon, 3895 READ_STAT(sc, stats, xonPauseFramesReceived.bge_addr_lo)); 3896 BGE_EVCNT_UPD(sc->bge_ev_rx_macctl, 3897 READ_STAT(sc, stats, 3898 macControlFramesReceived.bge_addr_lo)); 3899 BGE_EVCNT_UPD(sc->bge_ev_xoffentered, 3900 READ_STAT(sc, stats, xoffStateEntered.bge_addr_lo)); 3901 3902 #undef READ_STAT 3903 3904 #ifdef notdef 3905 ifp->if_collisions += 3906 (sc->bge_rdata->bge_info.bge_stats.dot3StatsSingleCollisionFrames + 3907 sc->bge_rdata->bge_info.bge_stats.dot3StatsMultipleCollisionFrames + 3908 sc->bge_rdata->bge_info.bge_stats.dot3StatsExcessiveCollisions + 3909 sc->bge_rdata->bge_info.bge_stats.dot3StatsLateCollisions) - 3910 ifp->if_collisions; 3911 #endif 3912 } 3913 3914 /* 3915 * Pad outbound frame to ETHER_MIN_NOPAD for an unusual reason. 3916 * The bge hardware will pad out Tx runts to ETHER_MIN_NOPAD, 3917 * but when such padded frames employ the bge IP/TCP checksum offload, 3918 * the hardware checksum assist gives incorrect results (possibly 3919 * from incorporating its own padding into the UDP/TCP checksum; who knows). 3920 * If we pad such runts with zeros, the onboard checksum comes out correct. 3921 */ 3922 static inline int 3923 bge_cksum_pad(struct mbuf *pkt) 3924 { 3925 struct mbuf *last = NULL; 3926 int padlen; 3927 3928 padlen = ETHER_MIN_NOPAD - pkt->m_pkthdr.len; 3929 3930 /* if there's only the packet-header and we can pad there, use it. */ 3931 if (pkt->m_pkthdr.len == pkt->m_len && 3932 M_TRAILINGSPACE(pkt) >= padlen) { 3933 last = pkt; 3934 } else { 3935 /* 3936 * Walk packet chain to find last mbuf. We will either 3937 * pad there, or append a new mbuf and pad it 3938 * (thus perhaps avoiding the bcm5700 dma-min bug). 3939 */ 3940 for (last = pkt; last->m_next != NULL; last = last->m_next) { 3941 continue; /* do nothing */ 3942 } 3943 3944 /* `last' now points to last in chain. */ 3945 if (M_TRAILINGSPACE(last) < padlen) { 3946 /* Allocate new empty mbuf, pad it. Compact later. */ 3947 struct mbuf *n; 3948 MGET(n, M_DONTWAIT, MT_DATA); 3949 if (n == NULL) 3950 return ENOBUFS; 3951 n->m_len = 0; 3952 last->m_next = n; 3953 last = n; 3954 } 3955 } 3956 3957 KDASSERT(!M_READONLY(last)); 3958 KDASSERT(M_TRAILINGSPACE(last) >= padlen); 3959 3960 /* Now zero the pad area, to avoid the bge cksum-assist bug */ 3961 memset(mtod(last, char *) + last->m_len, 0, padlen); 3962 last->m_len += padlen; 3963 pkt->m_pkthdr.len += padlen; 3964 return 0; 3965 } 3966 3967 /* 3968 * Compact outbound packets to avoid bug with DMA segments less than 8 bytes. 3969 */ 3970 static inline int 3971 bge_compact_dma_runt(struct mbuf *pkt) 3972 { 3973 struct mbuf *m, *prev; 3974 int totlen, prevlen; 3975 3976 prev = NULL; 3977 totlen = 0; 3978 prevlen = -1; 3979 3980 for (m = pkt; m != NULL; prev = m,m = m->m_next) { 3981 int mlen = m->m_len; 3982 int shortfall = 8 - mlen ; 3983 3984 totlen += mlen; 3985 if (mlen == 0) 3986 continue; 3987 if (mlen >= 8) 3988 continue; 3989 3990 /* If we get here, mbuf data is too small for DMA engine. 3991 * Try to fix by shuffling data to prev or next in chain. 3992 * If that fails, do a compacting deep-copy of the whole chain. 3993 */ 3994 3995 /* Internal frag. If fits in prev, copy it there. */ 3996 if (prev && M_TRAILINGSPACE(prev) >= m->m_len) { 3997 memcpy(prev->m_data + prev->m_len, m->m_data, mlen); 3998 prev->m_len += mlen; 3999 m->m_len = 0; 4000 /* XXX stitch chain */ 4001 prev->m_next = m_free(m); 4002 m = prev; 4003 continue; 4004 } 4005 else if (m->m_next != NULL && 4006 M_TRAILINGSPACE(m) >= shortfall && 4007 m->m_next->m_len >= (8 + shortfall)) { 4008 /* m is writable and have enough data in next, pull up. */ 4009 4010 memcpy(m->m_data + m->m_len, m->m_next->m_data, 4011 shortfall); 4012 m->m_len += shortfall; 4013 m->m_next->m_len -= shortfall; 4014 m->m_next->m_data += shortfall; 4015 } 4016 else if (m->m_next == NULL || 1) { 4017 /* Got a runt at the very end of the packet. 4018 * borrow data from the tail of the preceding mbuf and 4019 * update its length in-place. (The original data is still 4020 * valid, so we can do this even if prev is not writable.) 4021 */ 4022 4023 /* if we'd make prev a runt, just move all of its data. */ 4024 KASSERT(prev != NULL /*, ("runt but null PREV")*/); 4025 KASSERT(prev->m_len >= 8 /*, ("runt prev")*/); 4026 4027 if ((prev->m_len - shortfall) < 8) 4028 shortfall = prev->m_len; 4029 4030 #ifdef notyet /* just do the safe slow thing for now */ 4031 if (!M_READONLY(m)) { 4032 if (M_LEADINGSPACE(m) < shorfall) { 4033 void *m_dat; 4034 m_dat = (m->m_flags & M_PKTHDR) ? 4035 m->m_pktdat : m->dat; 4036 memmove(m_dat, mtod(m, void*), m->m_len); 4037 m->m_data = m_dat; 4038 } 4039 } else 4040 #endif /* just do the safe slow thing */ 4041 { 4042 struct mbuf * n = NULL; 4043 int newprevlen = prev->m_len - shortfall; 4044 4045 MGET(n, M_NOWAIT, MT_DATA); 4046 if (n == NULL) 4047 return ENOBUFS; 4048 KASSERT(m->m_len + shortfall < MLEN 4049 /*, 4050 ("runt %d +prev %d too big\n", m->m_len, shortfall)*/); 4051 4052 /* first copy the data we're stealing from prev */ 4053 memcpy(n->m_data, prev->m_data + newprevlen, 4054 shortfall); 4055 4056 /* update prev->m_len accordingly */ 4057 prev->m_len -= shortfall; 4058 4059 /* copy data from runt m */ 4060 memcpy(n->m_data + shortfall, m->m_data, 4061 m->m_len); 4062 4063 /* n holds what we stole from prev, plus m */ 4064 n->m_len = shortfall + m->m_len; 4065 4066 /* stitch n into chain and free m */ 4067 n->m_next = m->m_next; 4068 prev->m_next = n; 4069 /* KASSERT(m->m_next == NULL); */ 4070 m->m_next = NULL; 4071 m_free(m); 4072 m = n; /* for continuing loop */ 4073 } 4074 } 4075 prevlen = m->m_len; 4076 } 4077 return 0; 4078 } 4079 4080 /* 4081 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data 4082 * pointers to descriptors. 4083 */ 4084 static int 4085 bge_encap(struct bge_softc *sc, struct mbuf *m_head, uint32_t *txidx) 4086 { 4087 struct bge_tx_bd *f = NULL; 4088 uint32_t frag, cur; 4089 uint16_t csum_flags = 0; 4090 uint16_t txbd_tso_flags = 0; 4091 struct txdmamap_pool_entry *dma; 4092 bus_dmamap_t dmamap; 4093 int i = 0; 4094 struct m_tag *mtag; 4095 int use_tso, maxsegsize, error; 4096 4097 cur = frag = *txidx; 4098 4099 if (m_head->m_pkthdr.csum_flags) { 4100 if (m_head->m_pkthdr.csum_flags & M_CSUM_IPv4) 4101 csum_flags |= BGE_TXBDFLAG_IP_CSUM; 4102 if (m_head->m_pkthdr.csum_flags & (M_CSUM_TCPv4|M_CSUM_UDPv4)) 4103 csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM; 4104 } 4105 4106 /* 4107 * If we were asked to do an outboard checksum, and the NIC 4108 * has the bug where it sometimes adds in the Ethernet padding, 4109 * explicitly pad with zeros so the cksum will be correct either way. 4110 * (For now, do this for all chip versions, until newer 4111 * are confirmed to not require the workaround.) 4112 */ 4113 if ((csum_flags & BGE_TXBDFLAG_TCP_UDP_CSUM) == 0 || 4114 #ifdef notyet 4115 (sc->bge_quirks & BGE_QUIRK_SHORT_CKSUM_BUG) == 0 || 4116 #endif 4117 m_head->m_pkthdr.len >= ETHER_MIN_NOPAD) 4118 goto check_dma_bug; 4119 4120 if (bge_cksum_pad(m_head) != 0) 4121 return ENOBUFS; 4122 4123 check_dma_bug: 4124 if (!(BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX)) 4125 goto doit; 4126 4127 /* 4128 * bcm5700 Revision B silicon cannot handle DMA descriptors with 4129 * less than eight bytes. If we encounter a teeny mbuf 4130 * at the end of a chain, we can pad. Otherwise, copy. 4131 */ 4132 if (bge_compact_dma_runt(m_head) != 0) 4133 return ENOBUFS; 4134 4135 doit: 4136 dma = SLIST_FIRST(&sc->txdma_list); 4137 if (dma == NULL) 4138 return ENOBUFS; 4139 dmamap = dma->dmamap; 4140 4141 /* 4142 * Set up any necessary TSO state before we start packing... 4143 */ 4144 use_tso = (m_head->m_pkthdr.csum_flags & M_CSUM_TSOv4) != 0; 4145 if (!use_tso) { 4146 maxsegsize = 0; 4147 } else { /* TSO setup */ 4148 unsigned mss; 4149 struct ether_header *eh; 4150 unsigned ip_tcp_hlen, iptcp_opt_words, tcp_seg_flags, offset; 4151 struct mbuf * m0 = m_head; 4152 struct ip *ip; 4153 struct tcphdr *th; 4154 int iphl, hlen; 4155 4156 /* 4157 * XXX It would be nice if the mbuf pkthdr had offset 4158 * fields for the protocol headers. 4159 */ 4160 4161 eh = mtod(m0, struct ether_header *); 4162 switch (htons(eh->ether_type)) { 4163 case ETHERTYPE_IP: 4164 offset = ETHER_HDR_LEN; 4165 break; 4166 4167 case ETHERTYPE_VLAN: 4168 offset = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 4169 break; 4170 4171 default: 4172 /* 4173 * Don't support this protocol or encapsulation. 4174 */ 4175 return ENOBUFS; 4176 } 4177 4178 /* 4179 * TCP/IP headers are in the first mbuf; we can do 4180 * this the easy way. 4181 */ 4182 iphl = M_CSUM_DATA_IPv4_IPHL(m0->m_pkthdr.csum_data); 4183 hlen = iphl + offset; 4184 if (__predict_false(m0->m_len < 4185 (hlen + sizeof(struct tcphdr)))) { 4186 4187 aprint_debug_dev(sc->bge_dev, 4188 "TSO: hard case m0->m_len == %d < ip/tcp hlen %zd," 4189 "not handled yet\n", 4190 m0->m_len, hlen+ sizeof(struct tcphdr)); 4191 #ifdef NOTYET 4192 /* 4193 * XXX jonathan (at) NetBSD.org: untested. 4194 * how to force this branch to be taken? 4195 */ 4196 BGE_EVCNT_INCR(&sc->sc_ev_txtsopain); 4197 4198 m_copydata(m0, offset, sizeof(ip), &ip); 4199 m_copydata(m0, hlen, sizeof(th), &th); 4200 4201 ip.ip_len = 0; 4202 4203 m_copyback(m0, hlen + offsetof(struct ip, ip_len), 4204 sizeof(ip.ip_len), &ip.ip_len); 4205 4206 th.th_sum = in_cksum_phdr(ip.ip_src.s_addr, 4207 ip.ip_dst.s_addr, htons(IPPROTO_TCP)); 4208 4209 m_copyback(m0, hlen + offsetof(struct tcphdr, th_sum), 4210 sizeof(th.th_sum), &th.th_sum); 4211 4212 hlen += th.th_off << 2; 4213 iptcp_opt_words = hlen; 4214 #else 4215 /* 4216 * if_wm "hard" case not yet supported, can we not 4217 * mandate it out of existence? 4218 */ 4219 (void) ip; (void)th; (void) ip_tcp_hlen; 4220 4221 return ENOBUFS; 4222 #endif 4223 } else { 4224 ip = (struct ip *) (mtod(m0, char *) + offset); 4225 th = (struct tcphdr *) (mtod(m0, char *) + hlen); 4226 ip_tcp_hlen = iphl + (th->th_off << 2); 4227 4228 /* Total IP/TCP options, in 32-bit words */ 4229 iptcp_opt_words = (ip_tcp_hlen 4230 - sizeof(struct tcphdr) 4231 - sizeof(struct ip)) >> 2; 4232 } 4233 if (BGE_IS_575X_PLUS(sc)) { 4234 th->th_sum = 0; 4235 csum_flags &= ~(BGE_TXBDFLAG_TCP_UDP_CSUM); 4236 } else { 4237 /* 4238 * XXX jonathan (at) NetBSD.org: 5705 untested. 4239 * Requires TSO firmware patch for 5701/5703/5704. 4240 */ 4241 th->th_sum = in_cksum_phdr(ip->ip_src.s_addr, 4242 ip->ip_dst.s_addr, htons(IPPROTO_TCP)); 4243 } 4244 4245 mss = m_head->m_pkthdr.segsz; 4246 txbd_tso_flags |= 4247 BGE_TXBDFLAG_CPU_PRE_DMA | 4248 BGE_TXBDFLAG_CPU_POST_DMA; 4249 4250 /* 4251 * Our NIC TSO-assist assumes TSO has standard, optionless 4252 * IPv4 and TCP headers, which total 40 bytes. By default, 4253 * the NIC copies 40 bytes of IP/TCP header from the 4254 * supplied header into the IP/TCP header portion of 4255 * each post-TSO-segment. If the supplied packet has IP or 4256 * TCP options, we need to tell the NIC to copy those extra 4257 * bytes into each post-TSO header, in addition to the normal 4258 * 40-byte IP/TCP header (and to leave space accordingly). 4259 * Unfortunately, the driver encoding of option length 4260 * varies across different ASIC families. 4261 */ 4262 tcp_seg_flags = 0; 4263 if (iptcp_opt_words) { 4264 if (BGE_IS_5705_PLUS(sc)) { 4265 tcp_seg_flags = 4266 iptcp_opt_words << 11; 4267 } else { 4268 txbd_tso_flags |= 4269 iptcp_opt_words << 12; 4270 } 4271 } 4272 maxsegsize = mss | tcp_seg_flags; 4273 ip->ip_len = htons(mss + ip_tcp_hlen); 4274 4275 } /* TSO setup */ 4276 4277 /* 4278 * Start packing the mbufs in this chain into 4279 * the fragment pointers. Stop when we run out 4280 * of fragments or hit the end of the mbuf chain. 4281 */ 4282 error = bus_dmamap_load_mbuf(sc->bge_dmatag, dmamap, m_head, 4283 BUS_DMA_NOWAIT); 4284 if (error) 4285 return ENOBUFS; 4286 /* 4287 * Sanity check: avoid coming within 16 descriptors 4288 * of the end of the ring. 4289 */ 4290 if (dmamap->dm_nsegs > (BGE_TX_RING_CNT - sc->bge_txcnt - 16)) { 4291 BGE_TSO_PRINTF(("%s: " 4292 " dmamap_load_mbuf too close to ring wrap\n", 4293 device_xname(sc->bge_dev))); 4294 goto fail_unload; 4295 } 4296 4297 mtag = sc->ethercom.ec_nvlans ? 4298 m_tag_find(m_head, PACKET_TAG_VLAN, NULL) : NULL; 4299 4300 4301 /* Iterate over dmap-map fragments. */ 4302 for (i = 0; i < dmamap->dm_nsegs; i++) { 4303 f = &sc->bge_rdata->bge_tx_ring[frag]; 4304 if (sc->bge_cdata.bge_tx_chain[frag] != NULL) 4305 break; 4306 4307 BGE_HOSTADDR(f->bge_addr, dmamap->dm_segs[i].ds_addr); 4308 f->bge_len = dmamap->dm_segs[i].ds_len; 4309 4310 /* 4311 * For 5751 and follow-ons, for TSO we must turn 4312 * off checksum-assist flag in the tx-descr, and 4313 * supply the ASIC-revision-specific encoding 4314 * of TSO flags and segsize. 4315 */ 4316 if (use_tso) { 4317 if (BGE_IS_575X_PLUS(sc) || i == 0) { 4318 f->bge_rsvd = maxsegsize; 4319 f->bge_flags = csum_flags | txbd_tso_flags; 4320 } else { 4321 f->bge_rsvd = 0; 4322 f->bge_flags = 4323 (csum_flags | txbd_tso_flags) & 0x0fff; 4324 } 4325 } else { 4326 f->bge_rsvd = 0; 4327 f->bge_flags = csum_flags; 4328 } 4329 4330 if (mtag != NULL) { 4331 f->bge_flags |= BGE_TXBDFLAG_VLAN_TAG; 4332 f->bge_vlan_tag = VLAN_TAG_VALUE(mtag); 4333 } else { 4334 f->bge_vlan_tag = 0; 4335 } 4336 cur = frag; 4337 BGE_INC(frag, BGE_TX_RING_CNT); 4338 } 4339 4340 if (i < dmamap->dm_nsegs) { 4341 BGE_TSO_PRINTF(("%s: reached %d < dm_nsegs %d\n", 4342 device_xname(sc->bge_dev), i, dmamap->dm_nsegs)); 4343 goto fail_unload; 4344 } 4345 4346 bus_dmamap_sync(sc->bge_dmatag, dmamap, 0, dmamap->dm_mapsize, 4347 BUS_DMASYNC_PREWRITE); 4348 4349 if (frag == sc->bge_tx_saved_considx) { 4350 BGE_TSO_PRINTF(("%s: frag %d = wrapped id %d?\n", 4351 device_xname(sc->bge_dev), frag, sc->bge_tx_saved_considx)); 4352 4353 goto fail_unload; 4354 } 4355 4356 sc->bge_rdata->bge_tx_ring[cur].bge_flags |= BGE_TXBDFLAG_END; 4357 sc->bge_cdata.bge_tx_chain[cur] = m_head; 4358 SLIST_REMOVE_HEAD(&sc->txdma_list, link); 4359 sc->txdma[cur] = dma; 4360 sc->bge_txcnt += dmamap->dm_nsegs; 4361 4362 *txidx = frag; 4363 4364 return 0; 4365 4366 fail_unload: 4367 bus_dmamap_unload(sc->bge_dmatag, dmamap); 4368 4369 return ENOBUFS; 4370 } 4371 4372 /* 4373 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 4374 * to the mbuf data regions directly in the transmit descriptors. 4375 */ 4376 static void 4377 bge_start(struct ifnet *ifp) 4378 { 4379 struct bge_softc *sc; 4380 struct mbuf *m_head = NULL; 4381 uint32_t prodidx; 4382 int pkts = 0; 4383 4384 sc = ifp->if_softc; 4385 4386 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 4387 return; 4388 4389 prodidx = sc->bge_tx_prodidx; 4390 4391 while (sc->bge_cdata.bge_tx_chain[prodidx] == NULL) { 4392 IFQ_POLL(&ifp->if_snd, m_head); 4393 if (m_head == NULL) 4394 break; 4395 4396 #if 0 4397 /* 4398 * XXX 4399 * safety overkill. If this is a fragmented packet chain 4400 * with delayed TCP/UDP checksums, then only encapsulate 4401 * it if we have enough descriptors to handle the entire 4402 * chain at once. 4403 * (paranoia -- may not actually be needed) 4404 */ 4405 if (m_head->m_flags & M_FIRSTFRAG && 4406 m_head->m_pkthdr.csum_flags & (CSUM_DELAY_DATA)) { 4407 if ((BGE_TX_RING_CNT - sc->bge_txcnt) < 4408 M_CSUM_DATA_IPv4_OFFSET(m_head->m_pkthdr.csum_data) + 16) { 4409 ifp->if_flags |= IFF_OACTIVE; 4410 break; 4411 } 4412 } 4413 #endif 4414 4415 /* 4416 * Pack the data into the transmit ring. If we 4417 * don't have room, set the OACTIVE flag and wait 4418 * for the NIC to drain the ring. 4419 */ 4420 if (bge_encap(sc, m_head, &prodidx)) { 4421 ifp->if_flags |= IFF_OACTIVE; 4422 break; 4423 } 4424 4425 /* now we are committed to transmit the packet */ 4426 IFQ_DEQUEUE(&ifp->if_snd, m_head); 4427 pkts++; 4428 4429 /* 4430 * If there's a BPF listener, bounce a copy of this frame 4431 * to him. 4432 */ 4433 bpf_mtap(ifp, m_head); 4434 } 4435 if (pkts == 0) 4436 return; 4437 4438 /* Transmit */ 4439 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); 4440 /* 5700 b2 errata */ 4441 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX) 4442 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); 4443 4444 sc->bge_tx_prodidx = prodidx; 4445 4446 /* 4447 * Set a timeout in case the chip goes out to lunch. 4448 */ 4449 ifp->if_timer = 5; 4450 } 4451 4452 static int 4453 bge_init(struct ifnet *ifp) 4454 { 4455 struct bge_softc *sc = ifp->if_softc; 4456 const uint16_t *m; 4457 uint32_t mode; 4458 int s, error = 0; 4459 4460 s = splnet(); 4461 4462 ifp = &sc->ethercom.ec_if; 4463 4464 /* Cancel pending I/O and flush buffers. */ 4465 bge_stop(ifp, 0); 4466 4467 bge_stop_fw(sc); 4468 bge_sig_pre_reset(sc, BGE_RESET_START); 4469 bge_reset(sc); 4470 bge_sig_legacy(sc, BGE_RESET_START); 4471 bge_sig_post_reset(sc, BGE_RESET_START); 4472 4473 bge_chipinit(sc); 4474 4475 /* 4476 * Init the various state machines, ring 4477 * control blocks and firmware. 4478 */ 4479 error = bge_blockinit(sc); 4480 if (error != 0) { 4481 aprint_error_dev(sc->bge_dev, "initialization error %d\n", 4482 error); 4483 splx(s); 4484 return error; 4485 } 4486 4487 ifp = &sc->ethercom.ec_if; 4488 4489 /* Specify MTU. */ 4490 CSR_WRITE_4(sc, BGE_RX_MTU, ifp->if_mtu + 4491 ETHER_HDR_LEN + ETHER_CRC_LEN + ETHER_VLAN_ENCAP_LEN); 4492 4493 /* Load our MAC address. */ 4494 m = (const uint16_t *)&(CLLADDR(ifp->if_sadl)[0]); 4495 CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0])); 4496 CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, (htons(m[1]) << 16) | htons(m[2])); 4497 4498 /* Enable or disable promiscuous mode as needed. */ 4499 if (ifp->if_flags & IFF_PROMISC) 4500 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 4501 else 4502 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 4503 4504 /* Program multicast filter. */ 4505 bge_setmulti(sc); 4506 4507 /* Init RX ring. */ 4508 bge_init_rx_ring_std(sc); 4509 4510 /* 4511 * Workaround for a bug in 5705 ASIC rev A0. Poll the NIC's 4512 * memory to insure that the chip has in fact read the first 4513 * entry of the ring. 4514 */ 4515 if (sc->bge_chipid == BGE_CHIPID_BCM5705_A0) { 4516 uint32_t v, i; 4517 for (i = 0; i < 10; i++) { 4518 DELAY(20); 4519 v = bge_readmem_ind(sc, BGE_STD_RX_RINGS + 8); 4520 if (v == (MCLBYTES - ETHER_ALIGN)) 4521 break; 4522 } 4523 if (i == 10) 4524 aprint_error_dev(sc->bge_dev, 4525 "5705 A0 chip failed to load RX ring\n"); 4526 } 4527 4528 /* Init jumbo RX ring. */ 4529 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 4530 bge_init_rx_ring_jumbo(sc); 4531 4532 /* Init our RX return ring index */ 4533 sc->bge_rx_saved_considx = 0; 4534 4535 /* Init TX ring. */ 4536 bge_init_tx_ring(sc); 4537 4538 /* Enable TX MAC state machine lockup fix. */ 4539 mode = CSR_READ_4(sc, BGE_TX_MODE); 4540 if (BGE_IS_5755_PLUS(sc) || 4541 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 4542 mode |= BGE_TXMODE_MBUF_LOCKUP_FIX; 4543 4544 /* Turn on transmitter */ 4545 CSR_WRITE_4_FLUSH(sc, BGE_TX_MODE, mode | BGE_TXMODE_ENABLE); 4546 DELAY(100); 4547 4548 /* Turn on receiver */ 4549 BGE_SETBIT_FLUSH(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE); 4550 DELAY(10); 4551 4552 CSR_WRITE_4(sc, BGE_MAX_RX_FRAME_LOWAT, 2); 4553 4554 /* Tell firmware we're alive. */ 4555 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 4556 4557 /* Enable host interrupts. */ 4558 PCI_SETBIT(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MISC_CTL, 4559 BGE_PCIMISCCTL_CLEAR_INTA); 4560 PCI_CLRBIT(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MISC_CTL, 4561 BGE_PCIMISCCTL_MASK_PCI_INTR); 4562 bge_writembx_flush(sc, BGE_MBX_IRQ0_LO, 0); 4563 4564 if ((error = bge_ifmedia_upd(ifp)) != 0) 4565 goto out; 4566 4567 ifp->if_flags |= IFF_RUNNING; 4568 ifp->if_flags &= ~IFF_OACTIVE; 4569 4570 callout_reset(&sc->bge_timeout, hz, bge_tick, sc); 4571 4572 out: 4573 sc->bge_if_flags = ifp->if_flags; 4574 splx(s); 4575 4576 return error; 4577 } 4578 4579 /* 4580 * Set media options. 4581 */ 4582 static int 4583 bge_ifmedia_upd(struct ifnet *ifp) 4584 { 4585 struct bge_softc *sc = ifp->if_softc; 4586 struct mii_data *mii = &sc->bge_mii; 4587 struct ifmedia *ifm = &sc->bge_ifmedia; 4588 int rc; 4589 4590 /* If this is a 1000baseX NIC, enable the TBI port. */ 4591 if (sc->bge_flags & BGE_PHY_FIBER_TBI) { 4592 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 4593 return EINVAL; 4594 switch (IFM_SUBTYPE(ifm->ifm_media)) { 4595 case IFM_AUTO: 4596 /* 4597 * The BCM5704 ASIC appears to have a special 4598 * mechanism for programming the autoneg 4599 * advertisement registers in TBI mode. 4600 */ 4601 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) { 4602 uint32_t sgdig; 4603 sgdig = CSR_READ_4(sc, BGE_SGDIG_STS); 4604 if (sgdig & BGE_SGDIGSTS_DONE) { 4605 CSR_WRITE_4(sc, BGE_TX_TBI_AUTONEG, 0); 4606 sgdig = CSR_READ_4(sc, BGE_SGDIG_CFG); 4607 sgdig |= BGE_SGDIGCFG_AUTO | 4608 BGE_SGDIGCFG_PAUSE_CAP | 4609 BGE_SGDIGCFG_ASYM_PAUSE; 4610 CSR_WRITE_4_FLUSH(sc, BGE_SGDIG_CFG, 4611 sgdig | BGE_SGDIGCFG_SEND); 4612 DELAY(5); 4613 CSR_WRITE_4_FLUSH(sc, BGE_SGDIG_CFG, 4614 sgdig); 4615 } 4616 } 4617 break; 4618 case IFM_1000_SX: 4619 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 4620 BGE_CLRBIT(sc, BGE_MAC_MODE, 4621 BGE_MACMODE_HALF_DUPLEX); 4622 } else { 4623 BGE_SETBIT(sc, BGE_MAC_MODE, 4624 BGE_MACMODE_HALF_DUPLEX); 4625 } 4626 break; 4627 default: 4628 return EINVAL; 4629 } 4630 /* XXX 802.3x flow control for 1000BASE-SX */ 4631 return 0; 4632 } 4633 4634 BGE_STS_SETBIT(sc, BGE_STS_LINK_EVT); 4635 if ((rc = mii_mediachg(mii)) == ENXIO) 4636 return 0; 4637 4638 /* 4639 * Force an interrupt so that we will call bge_link_upd 4640 * if needed and clear any pending link state attention. 4641 * Without this we are not getting any further interrupts 4642 * for link state changes and thus will not UP the link and 4643 * not be able to send in bge_start. The only way to get 4644 * things working was to receive a packet and get a RX intr. 4645 */ 4646 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 4647 sc->bge_flags & BGE_IS_5788) 4648 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET); 4649 else 4650 BGE_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW); 4651 4652 return rc; 4653 } 4654 4655 /* 4656 * Report current media status. 4657 */ 4658 static void 4659 bge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 4660 { 4661 struct bge_softc *sc = ifp->if_softc; 4662 struct mii_data *mii = &sc->bge_mii; 4663 4664 if (sc->bge_flags & BGE_PHY_FIBER_TBI) { 4665 ifmr->ifm_status = IFM_AVALID; 4666 ifmr->ifm_active = IFM_ETHER; 4667 if (CSR_READ_4(sc, BGE_MAC_STS) & 4668 BGE_MACSTAT_TBI_PCS_SYNCHED) 4669 ifmr->ifm_status |= IFM_ACTIVE; 4670 ifmr->ifm_active |= IFM_1000_SX; 4671 if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX) 4672 ifmr->ifm_active |= IFM_HDX; 4673 else 4674 ifmr->ifm_active |= IFM_FDX; 4675 return; 4676 } 4677 4678 mii_pollstat(mii); 4679 ifmr->ifm_status = mii->mii_media_status; 4680 ifmr->ifm_active = (mii->mii_media_active & ~IFM_ETH_FMASK) | 4681 sc->bge_flowflags; 4682 } 4683 4684 static int 4685 bge_ifflags_cb(struct ethercom *ec) 4686 { 4687 struct ifnet *ifp = &ec->ec_if; 4688 struct bge_softc *sc = ifp->if_softc; 4689 int change = ifp->if_flags ^ sc->bge_if_flags; 4690 4691 if ((change & ~(IFF_CANTCHANGE|IFF_DEBUG)) != 0) 4692 return ENETRESET; 4693 else if ((change & (IFF_PROMISC | IFF_ALLMULTI)) == 0) 4694 return 0; 4695 4696 if ((ifp->if_flags & IFF_PROMISC) == 0) 4697 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 4698 else 4699 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 4700 4701 bge_setmulti(sc); 4702 4703 sc->bge_if_flags = ifp->if_flags; 4704 return 0; 4705 } 4706 4707 static int 4708 bge_ioctl(struct ifnet *ifp, u_long command, void *data) 4709 { 4710 struct bge_softc *sc = ifp->if_softc; 4711 struct ifreq *ifr = (struct ifreq *) data; 4712 int s, error = 0; 4713 struct mii_data *mii; 4714 4715 s = splnet(); 4716 4717 switch (command) { 4718 case SIOCSIFMEDIA: 4719 /* XXX Flow control is not supported for 1000BASE-SX */ 4720 if (sc->bge_flags & BGE_PHY_FIBER_TBI) { 4721 ifr->ifr_media &= ~IFM_ETH_FMASK; 4722 sc->bge_flowflags = 0; 4723 } 4724 4725 /* Flow control requires full-duplex mode. */ 4726 if (IFM_SUBTYPE(ifr->ifr_media) == IFM_AUTO || 4727 (ifr->ifr_media & IFM_FDX) == 0) { 4728 ifr->ifr_media &= ~IFM_ETH_FMASK; 4729 } 4730 if (IFM_SUBTYPE(ifr->ifr_media) != IFM_AUTO) { 4731 if ((ifr->ifr_media & IFM_ETH_FMASK) == IFM_FLOW) { 4732 /* We can do both TXPAUSE and RXPAUSE. */ 4733 ifr->ifr_media |= 4734 IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE; 4735 } 4736 sc->bge_flowflags = ifr->ifr_media & IFM_ETH_FMASK; 4737 } 4738 /* FALLTHROUGH */ 4739 case SIOCGIFMEDIA: 4740 if (sc->bge_flags & BGE_PHY_FIBER_TBI) { 4741 error = ifmedia_ioctl(ifp, ifr, &sc->bge_ifmedia, 4742 command); 4743 } else { 4744 mii = &sc->bge_mii; 4745 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, 4746 command); 4747 } 4748 break; 4749 default: 4750 if ((error = ether_ioctl(ifp, command, data)) != ENETRESET) 4751 break; 4752 4753 error = 0; 4754 4755 if (command != SIOCADDMULTI && command != SIOCDELMULTI) 4756 ; 4757 else if (ifp->if_flags & IFF_RUNNING) 4758 bge_setmulti(sc); 4759 break; 4760 } 4761 4762 splx(s); 4763 4764 return error; 4765 } 4766 4767 static void 4768 bge_watchdog(struct ifnet *ifp) 4769 { 4770 struct bge_softc *sc; 4771 4772 sc = ifp->if_softc; 4773 4774 aprint_error_dev(sc->bge_dev, "watchdog timeout -- resetting\n"); 4775 4776 ifp->if_flags &= ~IFF_RUNNING; 4777 bge_init(ifp); 4778 4779 ifp->if_oerrors++; 4780 } 4781 4782 static void 4783 bge_stop_block(struct bge_softc *sc, bus_addr_t reg, uint32_t bit) 4784 { 4785 int i; 4786 4787 BGE_CLRBIT_FLUSH(sc, reg, bit); 4788 4789 for (i = 0; i < 1000; i++) { 4790 if ((CSR_READ_4(sc, reg) & bit) == 0) 4791 return; 4792 delay(100); 4793 } 4794 4795 /* 4796 * Doesn't print only when the register is BGE_SRS_MODE. It occurs 4797 * on some environment (and once after boot?) 4798 */ 4799 if (reg != BGE_SRS_MODE) 4800 aprint_error_dev(sc->bge_dev, 4801 "block failed to stop: reg 0x%lx, bit 0x%08x\n", 4802 (u_long)reg, bit); 4803 } 4804 4805 /* 4806 * Stop the adapter and free any mbufs allocated to the 4807 * RX and TX lists. 4808 */ 4809 static void 4810 bge_stop(struct ifnet *ifp, int disable) 4811 { 4812 struct bge_softc *sc = ifp->if_softc; 4813 4814 callout_stop(&sc->bge_timeout); 4815 4816 /* 4817 * Tell firmware we're shutting down. 4818 */ 4819 bge_stop_fw(sc); 4820 bge_sig_pre_reset(sc, BGE_RESET_STOP); 4821 4822 /* Disable host interrupts. */ 4823 PCI_SETBIT(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MISC_CTL, 4824 BGE_PCIMISCCTL_MASK_PCI_INTR); 4825 bge_writembx_flush(sc, BGE_MBX_IRQ0_LO, 1); 4826 4827 /* 4828 * Disable all of the receiver blocks. 4829 */ 4830 bge_stop_block(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE); 4831 bge_stop_block(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 4832 bge_stop_block(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 4833 if (BGE_IS_5700_FAMILY(sc)) 4834 bge_stop_block(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 4835 bge_stop_block(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE); 4836 bge_stop_block(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 4837 bge_stop_block(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE); 4838 4839 /* 4840 * Disable all of the transmit blocks. 4841 */ 4842 bge_stop_block(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 4843 bge_stop_block(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 4844 bge_stop_block(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 4845 bge_stop_block(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE); 4846 bge_stop_block(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE); 4847 if (BGE_IS_5700_FAMILY(sc)) 4848 bge_stop_block(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 4849 bge_stop_block(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 4850 4851 /* 4852 * Shut down all of the memory managers and related 4853 * state machines. 4854 */ 4855 bge_stop_block(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE); 4856 bge_stop_block(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE); 4857 if (BGE_IS_5700_FAMILY(sc)) 4858 bge_stop_block(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 4859 4860 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 4861 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 4862 4863 if (BGE_IS_5700_FAMILY(sc)) { 4864 bge_stop_block(sc, BGE_BMAN_MODE, BGE_BMANMODE_ENABLE); 4865 bge_stop_block(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 4866 } 4867 4868 bge_reset(sc); 4869 bge_sig_legacy(sc, BGE_RESET_STOP); 4870 bge_sig_post_reset(sc, BGE_RESET_STOP); 4871 4872 /* 4873 * Keep the ASF firmware running if up. 4874 */ 4875 if (sc->bge_asf_mode & ASF_STACKUP) 4876 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 4877 else 4878 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 4879 4880 /* Free the RX lists. */ 4881 bge_free_rx_ring_std(sc); 4882 4883 /* Free jumbo RX list. */ 4884 if (BGE_IS_JUMBO_CAPABLE(sc)) 4885 bge_free_rx_ring_jumbo(sc); 4886 4887 /* Free TX buffers. */ 4888 bge_free_tx_ring(sc); 4889 4890 /* 4891 * Isolate/power down the PHY. 4892 */ 4893 if (!(sc->bge_flags & BGE_PHY_FIBER_TBI)) 4894 mii_down(&sc->bge_mii); 4895 4896 sc->bge_tx_saved_considx = BGE_TXCONS_UNSET; 4897 4898 /* Clear MAC's link state (PHY may still have link UP). */ 4899 BGE_STS_CLRBIT(sc, BGE_STS_LINK); 4900 4901 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 4902 } 4903 4904 static void 4905 bge_link_upd(struct bge_softc *sc) 4906 { 4907 struct ifnet *ifp = &sc->ethercom.ec_if; 4908 struct mii_data *mii = &sc->bge_mii; 4909 uint32_t status; 4910 int link; 4911 4912 /* Clear 'pending link event' flag */ 4913 BGE_STS_CLRBIT(sc, BGE_STS_LINK_EVT); 4914 4915 /* 4916 * Process link state changes. 4917 * Grrr. The link status word in the status block does 4918 * not work correctly on the BCM5700 rev AX and BX chips, 4919 * according to all available information. Hence, we have 4920 * to enable MII interrupts in order to properly obtain 4921 * async link changes. Unfortunately, this also means that 4922 * we have to read the MAC status register to detect link 4923 * changes, thereby adding an additional register access to 4924 * the interrupt handler. 4925 */ 4926 4927 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700) { 4928 status = CSR_READ_4(sc, BGE_MAC_STS); 4929 if (status & BGE_MACSTAT_MI_INTERRUPT) { 4930 mii_pollstat(mii); 4931 4932 if (!BGE_STS_BIT(sc, BGE_STS_LINK) && 4933 mii->mii_media_status & IFM_ACTIVE && 4934 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) 4935 BGE_STS_SETBIT(sc, BGE_STS_LINK); 4936 else if (BGE_STS_BIT(sc, BGE_STS_LINK) && 4937 (!(mii->mii_media_status & IFM_ACTIVE) || 4938 IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) 4939 BGE_STS_CLRBIT(sc, BGE_STS_LINK); 4940 4941 /* Clear the interrupt */ 4942 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, 4943 BGE_EVTENB_MI_INTERRUPT); 4944 bge_miibus_readreg(sc->bge_dev, 1, BRGPHY_MII_ISR); 4945 bge_miibus_writereg(sc->bge_dev, 1, BRGPHY_MII_IMR, 4946 BRGPHY_INTRS); 4947 } 4948 return; 4949 } 4950 4951 if (sc->bge_flags & BGE_PHY_FIBER_TBI) { 4952 status = CSR_READ_4(sc, BGE_MAC_STS); 4953 if (status & BGE_MACSTAT_TBI_PCS_SYNCHED) { 4954 if (!BGE_STS_BIT(sc, BGE_STS_LINK)) { 4955 BGE_STS_SETBIT(sc, BGE_STS_LINK); 4956 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) 4957 BGE_CLRBIT(sc, BGE_MAC_MODE, 4958 BGE_MACMODE_TBI_SEND_CFGS); 4959 CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF); 4960 if_link_state_change(ifp, LINK_STATE_UP); 4961 } 4962 } else if (BGE_STS_BIT(sc, BGE_STS_LINK)) { 4963 BGE_STS_CLRBIT(sc, BGE_STS_LINK); 4964 if_link_state_change(ifp, LINK_STATE_DOWN); 4965 } 4966 /* 4967 * Discard link events for MII/GMII cards if MI auto-polling disabled. 4968 * This should not happen since mii callouts are locked now, but 4969 * we keep this check for debug. 4970 */ 4971 } else if (BGE_STS_BIT(sc, BGE_STS_AUTOPOLL)) { 4972 /* 4973 * Some broken BCM chips have BGE_STATFLAG_LINKSTATE_CHANGED 4974 * bit in status word always set. Workaround this bug by 4975 * reading PHY link status directly. 4976 */ 4977 link = (CSR_READ_4(sc, BGE_MI_STS) & BGE_MISTS_LINK)? 4978 BGE_STS_LINK : 0; 4979 4980 if (BGE_STS_BIT(sc, BGE_STS_LINK) != link) { 4981 mii_pollstat(mii); 4982 4983 if (!BGE_STS_BIT(sc, BGE_STS_LINK) && 4984 mii->mii_media_status & IFM_ACTIVE && 4985 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) 4986 BGE_STS_SETBIT(sc, BGE_STS_LINK); 4987 else if (BGE_STS_BIT(sc, BGE_STS_LINK) && 4988 (!(mii->mii_media_status & IFM_ACTIVE) || 4989 IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) 4990 BGE_STS_CLRBIT(sc, BGE_STS_LINK); 4991 } 4992 } 4993 4994 /* Clear the attention */ 4995 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED| 4996 BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE| 4997 BGE_MACSTAT_LINK_CHANGED); 4998 } 4999 5000 static int 5001 bge_sysctl_verify(SYSCTLFN_ARGS) 5002 { 5003 int error, t; 5004 struct sysctlnode node; 5005 5006 node = *rnode; 5007 t = *(int*)rnode->sysctl_data; 5008 node.sysctl_data = &t; 5009 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 5010 if (error || newp == NULL) 5011 return error; 5012 5013 #if 0 5014 DPRINTF2(("%s: t = %d, nodenum = %d, rnodenum = %d\n", __func__, t, 5015 node.sysctl_num, rnode->sysctl_num)); 5016 #endif 5017 5018 if (node.sysctl_num == bge_rxthresh_nodenum) { 5019 if (t < 0 || t >= NBGE_RX_THRESH) 5020 return EINVAL; 5021 bge_update_all_threshes(t); 5022 } else 5023 return EINVAL; 5024 5025 *(int*)rnode->sysctl_data = t; 5026 5027 return 0; 5028 } 5029 5030 /* 5031 * Set up sysctl(3) MIB, hw.bge.*. 5032 */ 5033 static void 5034 bge_sysctl_init(struct bge_softc *sc) 5035 { 5036 int rc, bge_root_num; 5037 const struct sysctlnode *node; 5038 5039 if ((rc = sysctl_createv(&sc->bge_log, 0, NULL, NULL, 5040 CTLFLAG_PERMANENT, CTLTYPE_NODE, "hw", NULL, 5041 NULL, 0, NULL, 0, CTL_HW, CTL_EOL)) != 0) { 5042 goto out; 5043 } 5044 5045 if ((rc = sysctl_createv(&sc->bge_log, 0, NULL, &node, 5046 0, CTLTYPE_NODE, "bge", 5047 SYSCTL_DESCR("BGE interface controls"), 5048 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL)) != 0) { 5049 goto out; 5050 } 5051 5052 bge_root_num = node->sysctl_num; 5053 5054 /* BGE Rx interrupt mitigation level */ 5055 if ((rc = sysctl_createv(&sc->bge_log, 0, NULL, &node, 5056 CTLFLAG_READWRITE, 5057 CTLTYPE_INT, "rx_lvl", 5058 SYSCTL_DESCR("BGE receive interrupt mitigation level"), 5059 bge_sysctl_verify, 0, 5060 &bge_rx_thresh_lvl, 5061 0, CTL_HW, bge_root_num, CTL_CREATE, 5062 CTL_EOL)) != 0) { 5063 goto out; 5064 } 5065 5066 bge_rxthresh_nodenum = node->sysctl_num; 5067 5068 return; 5069 5070 out: 5071 aprint_error("%s: sysctl_createv failed (rc = %d)\n", __func__, rc); 5072 } 5073 5074 #ifdef BGE_DEBUG 5075 void 5076 bge_debug_info(struct bge_softc *sc) 5077 { 5078 5079 printf("Hardware Flags:\n"); 5080 if (BGE_IS_57765_PLUS(sc)) 5081 printf(" - 57765 Plus\n"); 5082 if (BGE_IS_5717_PLUS(sc)) 5083 printf(" - 5717 Plus\n"); 5084 if (BGE_IS_5755_PLUS(sc)) 5085 printf(" - 5755 Plus\n"); 5086 if (BGE_IS_575X_PLUS(sc)) 5087 printf(" - 575X Plus\n"); 5088 if (BGE_IS_5705_PLUS(sc)) 5089 printf(" - 5705 Plus\n"); 5090 if (BGE_IS_5714_FAMILY(sc)) 5091 printf(" - 5714 Family\n"); 5092 if (BGE_IS_5700_FAMILY(sc)) 5093 printf(" - 5700 Family\n"); 5094 if (sc->bge_flags & BGE_IS_5788) 5095 printf(" - 5788\n"); 5096 if (sc->bge_flags & BGE_JUMBO_CAPABLE) 5097 printf(" - Supports Jumbo Frames\n"); 5098 if (sc->bge_flags & BGE_NO_EEPROM) 5099 printf(" - No EEPROM\n"); 5100 if (sc->bge_flags & BGE_PCIX) 5101 printf(" - PCI-X Bus\n"); 5102 if (sc->bge_flags & BGE_PCIE) 5103 printf(" - PCI Express Bus\n"); 5104 if (sc->bge_flags & BGE_NO_3LED) 5105 printf(" - No 3 LEDs\n"); 5106 if (sc->bge_flags & BGE_RX_ALIGNBUG) 5107 printf(" - RX Alignment Bug\n"); 5108 if (sc->bge_flags & BGE_CPMU_PRESENT) 5109 printf(" - CPMU\n"); 5110 if (sc->bge_flags & BGE_TSO) 5111 printf(" - TSO\n"); 5112 } 5113 #endif /* BGE_DEBUG */ 5114 5115 static int 5116 bge_get_eaddr_fw(struct bge_softc *sc, uint8_t ether_addr[]) 5117 { 5118 prop_dictionary_t dict; 5119 prop_data_t ea; 5120 5121 if ((sc->bge_flags & BGE_NO_EEPROM) == 0) 5122 return 1; 5123 5124 dict = device_properties(sc->bge_dev); 5125 ea = prop_dictionary_get(dict, "mac-address"); 5126 if (ea != NULL) { 5127 KASSERT(prop_object_type(ea) == PROP_TYPE_DATA); 5128 KASSERT(prop_data_size(ea) == ETHER_ADDR_LEN); 5129 memcpy(ether_addr, prop_data_data_nocopy(ea), ETHER_ADDR_LEN); 5130 return 0; 5131 } 5132 5133 return 1; 5134 } 5135 5136 static int 5137 bge_get_eaddr_mem(struct bge_softc *sc, uint8_t ether_addr[]) 5138 { 5139 uint32_t mac_addr; 5140 5141 mac_addr = bge_readmem_ind(sc, BGE_SRAM_MAC_ADDR_HIGH_MB); 5142 if ((mac_addr >> 16) == 0x484b) { 5143 ether_addr[0] = (uint8_t)(mac_addr >> 8); 5144 ether_addr[1] = (uint8_t)mac_addr; 5145 mac_addr = bge_readmem_ind(sc, BGE_SRAM_MAC_ADDR_LOW_MB); 5146 ether_addr[2] = (uint8_t)(mac_addr >> 24); 5147 ether_addr[3] = (uint8_t)(mac_addr >> 16); 5148 ether_addr[4] = (uint8_t)(mac_addr >> 8); 5149 ether_addr[5] = (uint8_t)mac_addr; 5150 return 0; 5151 } 5152 return 1; 5153 } 5154 5155 static int 5156 bge_get_eaddr_nvram(struct bge_softc *sc, uint8_t ether_addr[]) 5157 { 5158 int mac_offset = BGE_EE_MAC_OFFSET; 5159 5160 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 5161 mac_offset = BGE_EE_MAC_OFFSET_5906; 5162 5163 return (bge_read_nvram(sc, ether_addr, mac_offset + 2, 5164 ETHER_ADDR_LEN)); 5165 } 5166 5167 static int 5168 bge_get_eaddr_eeprom(struct bge_softc *sc, uint8_t ether_addr[]) 5169 { 5170 5171 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 5172 return 1; 5173 5174 return (bge_read_eeprom(sc, ether_addr, BGE_EE_MAC_OFFSET + 2, 5175 ETHER_ADDR_LEN)); 5176 } 5177 5178 static int 5179 bge_get_eaddr(struct bge_softc *sc, uint8_t eaddr[]) 5180 { 5181 static const bge_eaddr_fcn_t bge_eaddr_funcs[] = { 5182 /* NOTE: Order is critical */ 5183 bge_get_eaddr_fw, 5184 bge_get_eaddr_mem, 5185 bge_get_eaddr_nvram, 5186 bge_get_eaddr_eeprom, 5187 NULL 5188 }; 5189 const bge_eaddr_fcn_t *func; 5190 5191 for (func = bge_eaddr_funcs; *func != NULL; ++func) { 5192 if ((*func)(sc, eaddr) == 0) 5193 break; 5194 } 5195 return (*func == NULL ? ENXIO : 0); 5196 } 5197
Indexes created Thu Sep 25 16:09:42 GMT 2025