if_bge.c revision 1.217
1 /* $NetBSD: if_bge.c,v 1.217 2013/03/17 18:46:10 msaitoh Exp $ */ 2 3 /* 4 * Copyright (c) 2001 Wind River Systems 5 * Copyright (c) 1997, 1998, 1999, 2001 6 * Bill Paul <wpaul (at) windriver.com>. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Bill Paul. 19 * 4. Neither the name of the author nor the names of any co-contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 33 * THE POSSIBILITY OF SUCH DAMAGE. 34 * 35 * $FreeBSD: if_bge.c,v 1.13 2002/04/04 06:01:31 wpaul Exp $ 36 */ 37 38 /* 39 * Broadcom BCM570x family gigabit ethernet driver for NetBSD. 40 * 41 * NetBSD version by: 42 * 43 * Frank van der Linden <fvdl (at) wasabisystems.com> 44 * Jason Thorpe <thorpej (at) wasabisystems.com> 45 * Jonathan Stone <jonathan (at) dsg.stanford.edu> 46 * 47 * Originally written for FreeBSD by Bill Paul <wpaul (at) windriver.com> 48 * Senior Engineer, Wind River Systems 49 */ 50 51 /* 52 * The Broadcom BCM5700 is based on technology originally developed by 53 * Alteon Networks as part of the Tigon I and Tigon II gigabit ethernet 54 * MAC chips. The BCM5700, sometimes referred to as the Tigon III, has 55 * two on-board MIPS R4000 CPUs and can have as much as 16MB of external 56 * SSRAM. The BCM5700 supports TCP, UDP and IP checksum offload, jumbo 57 * frames, highly configurable RX filtering, and 16 RX and TX queues 58 * (which, along with RX filter rules, can be used for QOS applications). 59 * Other features, such as TCP segmentation, may be available as part 60 * of value-added firmware updates. Unlike the Tigon I and Tigon II, 61 * firmware images can be stored in hardware and need not be compiled 62 * into the driver. 63 * 64 * The BCM5700 supports the PCI v2.2 and PCI-X v1.0 standards, and will 65 * function in a 32-bit/64-bit 33/66MHz bus, or a 64-bit/133MHz bus. 66 * 67 * The BCM5701 is a single-chip solution incorporating both the BCM5700 68 * MAC and a BCM5401 10/100/1000 PHY. Unlike the BCM5700, the BCM5701 69 * does not support external SSRAM. 70 * 71 * Broadcom also produces a variation of the BCM5700 under the "Altima" 72 * brand name, which is functionally similar but lacks PCI-X support. 73 * 74 * Without external SSRAM, you can only have at most 4 TX rings, 75 * and the use of the mini RX ring is disabled. This seems to imply 76 * that these features are simply not available on the BCM5701. As a 77 * result, this driver does not implement any support for the mini RX 78 * ring. 79 */ 80 81 #include <sys/cdefs.h> 82 __KERNEL_RCSID(0, "$NetBSD: if_bge.c,v 1.217 2013/03/17 18:46:10 msaitoh Exp $"); 83 84 #include "vlan.h" 85 86 #include <sys/param.h> 87 #include <sys/systm.h> 88 #include <sys/callout.h> 89 #include <sys/sockio.h> 90 #include <sys/mbuf.h> 91 #include <sys/malloc.h> 92 #include <sys/kernel.h> 93 #include <sys/device.h> 94 #include <sys/socket.h> 95 #include <sys/sysctl.h> 96 97 #include <net/if.h> 98 #include <net/if_dl.h> 99 #include <net/if_media.h> 100 #include <net/if_ether.h> 101 102 #include <sys/rnd.h> 103 104 #ifdef INET 105 #include <netinet/in.h> 106 #include <netinet/in_systm.h> 107 #include <netinet/in_var.h> 108 #include <netinet/ip.h> 109 #endif 110 111 /* Headers for TCP Segmentation Offload (TSO) */ 112 #include <netinet/in_systm.h> /* n_time for <netinet/ip.h>... */ 113 #include <netinet/in.h> /* ip_{src,dst}, for <netinet/ip.h> */ 114 #include <netinet/ip.h> /* for struct ip */ 115 #include <netinet/tcp.h> /* for struct tcphdr */ 116 117 118 #include <net/bpf.h> 119 120 #include <dev/pci/pcireg.h> 121 #include <dev/pci/pcivar.h> 122 #include <dev/pci/pcidevs.h> 123 124 #include <dev/mii/mii.h> 125 #include <dev/mii/miivar.h> 126 #include <dev/mii/miidevs.h> 127 #include <dev/mii/brgphyreg.h> 128 129 #include <dev/pci/if_bgereg.h> 130 #include <dev/pci/if_bgevar.h> 131 132 #include <prop/proplib.h> 133 134 #define ETHER_MIN_NOPAD (ETHER_MIN_LEN - ETHER_CRC_LEN) /* i.e., 60 */ 135 136 137 /* 138 * Tunable thresholds for rx-side bge interrupt mitigation. 139 */ 140 141 /* 142 * The pairs of values below were obtained from empirical measurement 143 * on bcm5700 rev B2; they ar designed to give roughly 1 receive 144 * interrupt for every N packets received, where N is, approximately, 145 * the second value (rx_max_bds) in each pair. The values are chosen 146 * such that moving from one pair to the succeeding pair was observed 147 * to roughly halve interrupt rate under sustained input packet load. 148 * The values were empirically chosen to avoid overflowing internal 149 * limits on the bcm5700: increasing rx_ticks much beyond 600 150 * results in internal wrapping and higher interrupt rates. 151 * The limit of 46 frames was chosen to match NFS workloads. 152 * 153 * These values also work well on bcm5701, bcm5704C, and (less 154 * tested) bcm5703. On other chipsets, (including the Altima chip 155 * family), the larger values may overflow internal chip limits, 156 * leading to increasing interrupt rates rather than lower interrupt 157 * rates. 158 * 159 * Applications using heavy interrupt mitigation (interrupting every 160 * 32 or 46 frames) in both directions may need to increase the TCP 161 * windowsize to above 131072 bytes (e.g., to 199608 bytes) to sustain 162 * full link bandwidth, due to ACKs and window updates lingering 163 * in the RX queue during the 30-to-40-frame interrupt-mitigation window. 164 */ 165 static const struct bge_load_rx_thresh { 166 int rx_ticks; 167 int rx_max_bds; } 168 bge_rx_threshes[] = { 169 { 16, 1 }, /* rx_max_bds = 1 disables interrupt mitigation */ 170 { 32, 2 }, 171 { 50, 4 }, 172 { 100, 8 }, 173 { 192, 16 }, 174 { 416, 32 }, 175 { 598, 46 } 176 }; 177 #define NBGE_RX_THRESH (sizeof(bge_rx_threshes) / sizeof(bge_rx_threshes[0])) 178 179 /* XXX patchable; should be sysctl'able */ 180 static int bge_auto_thresh = 1; 181 static int bge_rx_thresh_lvl; 182 183 static int bge_rxthresh_nodenum; 184 185 typedef int (*bge_eaddr_fcn_t)(struct bge_softc *, uint8_t[]); 186 187 static uint32_t bge_chipid(const struct pci_attach_args *pa); 188 static int bge_probe(device_t, cfdata_t, void *); 189 static void bge_attach(device_t, device_t, void *); 190 static void bge_release_resources(struct bge_softc *); 191 192 static int bge_get_eaddr_fw(struct bge_softc *, uint8_t[]); 193 static int bge_get_eaddr_mem(struct bge_softc *, uint8_t[]); 194 static int bge_get_eaddr_nvram(struct bge_softc *, uint8_t[]); 195 static int bge_get_eaddr_eeprom(struct bge_softc *, uint8_t[]); 196 static int bge_get_eaddr(struct bge_softc *, uint8_t[]); 197 198 static void bge_txeof(struct bge_softc *); 199 static void bge_rxeof(struct bge_softc *); 200 201 static void bge_asf_driver_up (struct bge_softc *); 202 static void bge_tick(void *); 203 static void bge_stats_update(struct bge_softc *); 204 static void bge_stats_update_regs(struct bge_softc *); 205 static int bge_encap(struct bge_softc *, struct mbuf *, uint32_t *); 206 207 static int bge_intr(void *); 208 static void bge_start(struct ifnet *); 209 static int bge_ifflags_cb(struct ethercom *); 210 static int bge_ioctl(struct ifnet *, u_long, void *); 211 static int bge_init(struct ifnet *); 212 static void bge_stop(struct ifnet *, int); 213 static void bge_watchdog(struct ifnet *); 214 static int bge_ifmedia_upd(struct ifnet *); 215 static void bge_ifmedia_sts(struct ifnet *, struct ifmediareq *); 216 217 static uint8_t bge_nvram_getbyte(struct bge_softc *, int, uint8_t *); 218 static int bge_read_nvram(struct bge_softc *, uint8_t *, int, int); 219 220 static uint8_t bge_eeprom_getbyte(struct bge_softc *, int, uint8_t *); 221 static int bge_read_eeprom(struct bge_softc *, void *, int, int); 222 static void bge_setmulti(struct bge_softc *); 223 224 static void bge_handle_events(struct bge_softc *); 225 static int bge_alloc_jumbo_mem(struct bge_softc *); 226 #if 0 /* XXX */ 227 static void bge_free_jumbo_mem(struct bge_softc *); 228 #endif 229 static void *bge_jalloc(struct bge_softc *); 230 static void bge_jfree(struct mbuf *, void *, size_t, void *); 231 static int bge_newbuf_std(struct bge_softc *, int, struct mbuf *, 232 bus_dmamap_t); 233 static int bge_newbuf_jumbo(struct bge_softc *, int, struct mbuf *); 234 static int bge_init_rx_ring_std(struct bge_softc *); 235 static void bge_free_rx_ring_std(struct bge_softc *); 236 static int bge_init_rx_ring_jumbo(struct bge_softc *); 237 static void bge_free_rx_ring_jumbo(struct bge_softc *); 238 static void bge_free_tx_ring(struct bge_softc *); 239 static int bge_init_tx_ring(struct bge_softc *); 240 241 static int bge_chipinit(struct bge_softc *); 242 static int bge_blockinit(struct bge_softc *); 243 static int bge_phy_addr(struct bge_softc *); 244 static uint32_t bge_readmem_ind(struct bge_softc *, int); 245 static void bge_writemem_ind(struct bge_softc *, int, int); 246 static void bge_writembx(struct bge_softc *, int, int); 247 static void bge_writembx_flush(struct bge_softc *, int, int); 248 static void bge_writemem_direct(struct bge_softc *, int, int); 249 static void bge_writereg_ind(struct bge_softc *, int, int); 250 static void bge_set_max_readrq(struct bge_softc *); 251 252 static int bge_miibus_readreg(device_t, int, int); 253 static void bge_miibus_writereg(device_t, int, int, int); 254 static void bge_miibus_statchg(struct ifnet *); 255 256 #define BGE_RESET_SHUTDOWN 0 257 #define BGE_RESET_START 1 258 #define BGE_RESET_SUSPEND 2 259 static void bge_sig_post_reset(struct bge_softc *, int); 260 static void bge_sig_legacy(struct bge_softc *, int); 261 static void bge_sig_pre_reset(struct bge_softc *, int); 262 static void bge_wait_for_event_ack(struct bge_softc *); 263 static void bge_stop_fw(struct bge_softc *); 264 static int bge_reset(struct bge_softc *); 265 static void bge_link_upd(struct bge_softc *); 266 static void bge_sysctl_init(struct bge_softc *); 267 static int bge_sysctl_verify(SYSCTLFN_PROTO); 268 269 static void bge_ape_lock_init(struct bge_softc *); 270 static void bge_ape_read_fw_ver(struct bge_softc *); 271 static int bge_ape_lock(struct bge_softc *, int); 272 static void bge_ape_unlock(struct bge_softc *, int); 273 static void bge_ape_send_event(struct bge_softc *, uint32_t); 274 static void bge_ape_driver_state_change(struct bge_softc *, int); 275 276 #ifdef BGE_DEBUG 277 #define DPRINTF(x) if (bgedebug) printf x 278 #define DPRINTFN(n,x) if (bgedebug >= (n)) printf x 279 #define BGE_TSO_PRINTF(x) do { if (bge_tso_debug) printf x ;} while (0) 280 int bgedebug = 0; 281 int bge_tso_debug = 0; 282 void bge_debug_info(struct bge_softc *); 283 #else 284 #define DPRINTF(x) 285 #define DPRINTFN(n,x) 286 #define BGE_TSO_PRINTF(x) 287 #endif 288 289 #ifdef BGE_EVENT_COUNTERS 290 #define BGE_EVCNT_INCR(ev) (ev).ev_count++ 291 #define BGE_EVCNT_ADD(ev, val) (ev).ev_count += (val) 292 #define BGE_EVCNT_UPD(ev, val) (ev).ev_count = (val) 293 #else 294 #define BGE_EVCNT_INCR(ev) /* nothing */ 295 #define BGE_EVCNT_ADD(ev, val) /* nothing */ 296 #define BGE_EVCNT_UPD(ev, val) /* nothing */ 297 #endif 298 299 static const struct bge_product { 300 pci_vendor_id_t bp_vendor; 301 pci_product_id_t bp_product; 302 const char *bp_name; 303 } bge_products[] = { 304 /* 305 * The BCM5700 documentation seems to indicate that the hardware 306 * still has the Alteon vendor ID burned into it, though it 307 * should always be overridden by the value in the EEPROM. We'll 308 * check for it anyway. 309 */ 310 { PCI_VENDOR_ALTEON, 311 PCI_PRODUCT_ALTEON_BCM5700, 312 "Broadcom BCM5700 Gigabit Ethernet", 313 }, 314 { PCI_VENDOR_ALTEON, 315 PCI_PRODUCT_ALTEON_BCM5701, 316 "Broadcom BCM5701 Gigabit Ethernet", 317 }, 318 { PCI_VENDOR_ALTIMA, 319 PCI_PRODUCT_ALTIMA_AC1000, 320 "Altima AC1000 Gigabit Ethernet", 321 }, 322 { PCI_VENDOR_ALTIMA, 323 PCI_PRODUCT_ALTIMA_AC1001, 324 "Altima AC1001 Gigabit Ethernet", 325 }, 326 { PCI_VENDOR_ALTIMA, 327 PCI_PRODUCT_ALTIMA_AC1003, 328 "Altima AC1003 Gigabit Ethernet", 329 }, 330 { PCI_VENDOR_ALTIMA, 331 PCI_PRODUCT_ALTIMA_AC9100, 332 "Altima AC9100 Gigabit Ethernet", 333 }, 334 { PCI_VENDOR_APPLE, 335 PCI_PRODUCT_APPLE_BCM5701, 336 "APPLE BCM5701 Gigabit Ethernet", 337 }, 338 { PCI_VENDOR_BROADCOM, 339 PCI_PRODUCT_BROADCOM_BCM5700, 340 "Broadcom BCM5700 Gigabit Ethernet", 341 }, 342 { PCI_VENDOR_BROADCOM, 343 PCI_PRODUCT_BROADCOM_BCM5701, 344 "Broadcom BCM5701 Gigabit Ethernet", 345 }, 346 { PCI_VENDOR_BROADCOM, 347 PCI_PRODUCT_BROADCOM_BCM5702, 348 "Broadcom BCM5702 Gigabit Ethernet", 349 }, 350 { PCI_VENDOR_BROADCOM, 351 PCI_PRODUCT_BROADCOM_BCM5702X, 352 "Broadcom BCM5702X Gigabit Ethernet" }, 353 { PCI_VENDOR_BROADCOM, 354 PCI_PRODUCT_BROADCOM_BCM5703, 355 "Broadcom BCM5703 Gigabit Ethernet", 356 }, 357 { PCI_VENDOR_BROADCOM, 358 PCI_PRODUCT_BROADCOM_BCM5703X, 359 "Broadcom BCM5703X Gigabit Ethernet", 360 }, 361 { PCI_VENDOR_BROADCOM, 362 PCI_PRODUCT_BROADCOM_BCM5703_ALT, 363 "Broadcom BCM5703 Gigabit Ethernet", 364 }, 365 { PCI_VENDOR_BROADCOM, 366 PCI_PRODUCT_BROADCOM_BCM5704C, 367 "Broadcom BCM5704C Dual Gigabit Ethernet", 368 }, 369 { PCI_VENDOR_BROADCOM, 370 PCI_PRODUCT_BROADCOM_BCM5704S, 371 "Broadcom BCM5704S Dual Gigabit Ethernet", 372 }, 373 { PCI_VENDOR_BROADCOM, 374 PCI_PRODUCT_BROADCOM_BCM5705, 375 "Broadcom BCM5705 Gigabit Ethernet", 376 }, 377 { PCI_VENDOR_BROADCOM, 378 PCI_PRODUCT_BROADCOM_BCM5705F, 379 "Broadcom BCM5705F Gigabit Ethernet", 380 }, 381 { PCI_VENDOR_BROADCOM, 382 PCI_PRODUCT_BROADCOM_BCM5705K, 383 "Broadcom BCM5705K Gigabit Ethernet", 384 }, 385 { PCI_VENDOR_BROADCOM, 386 PCI_PRODUCT_BROADCOM_BCM5705M, 387 "Broadcom BCM5705M Gigabit Ethernet", 388 }, 389 { PCI_VENDOR_BROADCOM, 390 PCI_PRODUCT_BROADCOM_BCM5705M_ALT, 391 "Broadcom BCM5705M Gigabit Ethernet", 392 }, 393 { PCI_VENDOR_BROADCOM, 394 PCI_PRODUCT_BROADCOM_BCM5714, 395 "Broadcom BCM5714 Gigabit Ethernet", 396 }, 397 { PCI_VENDOR_BROADCOM, 398 PCI_PRODUCT_BROADCOM_BCM5714S, 399 "Broadcom BCM5714S Gigabit Ethernet", 400 }, 401 { PCI_VENDOR_BROADCOM, 402 PCI_PRODUCT_BROADCOM_BCM5715, 403 "Broadcom BCM5715 Gigabit Ethernet", 404 }, 405 { PCI_VENDOR_BROADCOM, 406 PCI_PRODUCT_BROADCOM_BCM5715S, 407 "Broadcom BCM5715S Gigabit Ethernet", 408 }, 409 { PCI_VENDOR_BROADCOM, 410 PCI_PRODUCT_BROADCOM_BCM5717, 411 "Broadcom BCM5717 Gigabit Ethernet", 412 }, 413 { PCI_VENDOR_BROADCOM, 414 PCI_PRODUCT_BROADCOM_BCM5718, 415 "Broadcom BCM5718 Gigabit Ethernet", 416 }, 417 { PCI_VENDOR_BROADCOM, 418 PCI_PRODUCT_BROADCOM_BCM5719, 419 "Broadcom BCM5719 Gigabit Ethernet", 420 }, 421 { PCI_VENDOR_BROADCOM, 422 PCI_PRODUCT_BROADCOM_BCM5720, 423 "Broadcom BCM5720 Gigabit Ethernet", 424 }, 425 { PCI_VENDOR_BROADCOM, 426 PCI_PRODUCT_BROADCOM_BCM5721, 427 "Broadcom BCM5721 Gigabit Ethernet", 428 }, 429 { PCI_VENDOR_BROADCOM, 430 PCI_PRODUCT_BROADCOM_BCM5722, 431 "Broadcom BCM5722 Gigabit Ethernet", 432 }, 433 { PCI_VENDOR_BROADCOM, 434 PCI_PRODUCT_BROADCOM_BCM5723, 435 "Broadcom BCM5723 Gigabit Ethernet", 436 }, 437 { PCI_VENDOR_BROADCOM, 438 PCI_PRODUCT_BROADCOM_BCM5724, 439 "Broadcom BCM5724 Gigabit Ethernet", 440 }, 441 { PCI_VENDOR_BROADCOM, 442 PCI_PRODUCT_BROADCOM_BCM5750, 443 "Broadcom BCM5750 Gigabit Ethernet", 444 }, 445 { PCI_VENDOR_BROADCOM, 446 PCI_PRODUCT_BROADCOM_BCM5750M, 447 "Broadcom BCM5750M Gigabit Ethernet", 448 }, 449 { PCI_VENDOR_BROADCOM, 450 PCI_PRODUCT_BROADCOM_BCM5751, 451 "Broadcom BCM5751 Gigabit Ethernet", 452 }, 453 { PCI_VENDOR_BROADCOM, 454 PCI_PRODUCT_BROADCOM_BCM5751F, 455 "Broadcom BCM5751F Gigabit Ethernet", 456 }, 457 { PCI_VENDOR_BROADCOM, 458 PCI_PRODUCT_BROADCOM_BCM5751M, 459 "Broadcom BCM5751M Gigabit Ethernet", 460 }, 461 { PCI_VENDOR_BROADCOM, 462 PCI_PRODUCT_BROADCOM_BCM5752, 463 "Broadcom BCM5752 Gigabit Ethernet", 464 }, 465 { PCI_VENDOR_BROADCOM, 466 PCI_PRODUCT_BROADCOM_BCM5752M, 467 "Broadcom BCM5752M Gigabit Ethernet", 468 }, 469 { PCI_VENDOR_BROADCOM, 470 PCI_PRODUCT_BROADCOM_BCM5753, 471 "Broadcom BCM5753 Gigabit Ethernet", 472 }, 473 { PCI_VENDOR_BROADCOM, 474 PCI_PRODUCT_BROADCOM_BCM5753F, 475 "Broadcom BCM5753F Gigabit Ethernet", 476 }, 477 { PCI_VENDOR_BROADCOM, 478 PCI_PRODUCT_BROADCOM_BCM5753M, 479 "Broadcom BCM5753M Gigabit Ethernet", 480 }, 481 { PCI_VENDOR_BROADCOM, 482 PCI_PRODUCT_BROADCOM_BCM5754, 483 "Broadcom BCM5754 Gigabit Ethernet", 484 }, 485 { PCI_VENDOR_BROADCOM, 486 PCI_PRODUCT_BROADCOM_BCM5754M, 487 "Broadcom BCM5754M Gigabit Ethernet", 488 }, 489 { PCI_VENDOR_BROADCOM, 490 PCI_PRODUCT_BROADCOM_BCM5755, 491 "Broadcom BCM5755 Gigabit Ethernet", 492 }, 493 { PCI_VENDOR_BROADCOM, 494 PCI_PRODUCT_BROADCOM_BCM5755M, 495 "Broadcom BCM5755M Gigabit Ethernet", 496 }, 497 { PCI_VENDOR_BROADCOM, 498 PCI_PRODUCT_BROADCOM_BCM5756, 499 "Broadcom BCM5756 Gigabit Ethernet", 500 }, 501 { PCI_VENDOR_BROADCOM, 502 PCI_PRODUCT_BROADCOM_BCM5761, 503 "Broadcom BCM5761 Gigabit Ethernet", 504 }, 505 { PCI_VENDOR_BROADCOM, 506 PCI_PRODUCT_BROADCOM_BCM5761E, 507 "Broadcom BCM5761E Gigabit Ethernet", 508 }, 509 { PCI_VENDOR_BROADCOM, 510 PCI_PRODUCT_BROADCOM_BCM5761S, 511 "Broadcom BCM5761S Gigabit Ethernet", 512 }, 513 { PCI_VENDOR_BROADCOM, 514 PCI_PRODUCT_BROADCOM_BCM5761SE, 515 "Broadcom BCM5761SE Gigabit Ethernet", 516 }, 517 { PCI_VENDOR_BROADCOM, 518 PCI_PRODUCT_BROADCOM_BCM5764, 519 "Broadcom BCM5764 Gigabit Ethernet", 520 }, 521 { PCI_VENDOR_BROADCOM, 522 PCI_PRODUCT_BROADCOM_BCM5780, 523 "Broadcom BCM5780 Gigabit Ethernet", 524 }, 525 { PCI_VENDOR_BROADCOM, 526 PCI_PRODUCT_BROADCOM_BCM5780S, 527 "Broadcom BCM5780S Gigabit Ethernet", 528 }, 529 { PCI_VENDOR_BROADCOM, 530 PCI_PRODUCT_BROADCOM_BCM5781, 531 "Broadcom BCM5781 Gigabit Ethernet", 532 }, 533 { PCI_VENDOR_BROADCOM, 534 PCI_PRODUCT_BROADCOM_BCM5782, 535 "Broadcom BCM5782 Gigabit Ethernet", 536 }, 537 { PCI_VENDOR_BROADCOM, 538 PCI_PRODUCT_BROADCOM_BCM5784M, 539 "BCM5784M NetLink 1000baseT Ethernet", 540 }, 541 { PCI_VENDOR_BROADCOM, 542 PCI_PRODUCT_BROADCOM_BCM5785F, 543 "BCM5785F NetLink 10/100 Ethernet", 544 }, 545 { PCI_VENDOR_BROADCOM, 546 PCI_PRODUCT_BROADCOM_BCM5785G, 547 "BCM5785G NetLink 1000baseT Ethernet", 548 }, 549 { PCI_VENDOR_BROADCOM, 550 PCI_PRODUCT_BROADCOM_BCM5786, 551 "Broadcom BCM5786 Gigabit Ethernet", 552 }, 553 { PCI_VENDOR_BROADCOM, 554 PCI_PRODUCT_BROADCOM_BCM5787, 555 "Broadcom BCM5787 Gigabit Ethernet", 556 }, 557 { PCI_VENDOR_BROADCOM, 558 PCI_PRODUCT_BROADCOM_BCM5787F, 559 "Broadcom BCM5787F 10/100 Ethernet", 560 }, 561 { PCI_VENDOR_BROADCOM, 562 PCI_PRODUCT_BROADCOM_BCM5787M, 563 "Broadcom BCM5787M Gigabit Ethernet", 564 }, 565 { PCI_VENDOR_BROADCOM, 566 PCI_PRODUCT_BROADCOM_BCM5788, 567 "Broadcom BCM5788 Gigabit Ethernet", 568 }, 569 { PCI_VENDOR_BROADCOM, 570 PCI_PRODUCT_BROADCOM_BCM5789, 571 "Broadcom BCM5789 Gigabit Ethernet", 572 }, 573 { PCI_VENDOR_BROADCOM, 574 PCI_PRODUCT_BROADCOM_BCM5901, 575 "Broadcom BCM5901 Fast Ethernet", 576 }, 577 { PCI_VENDOR_BROADCOM, 578 PCI_PRODUCT_BROADCOM_BCM5901A2, 579 "Broadcom BCM5901A2 Fast Ethernet", 580 }, 581 { PCI_VENDOR_BROADCOM, 582 PCI_PRODUCT_BROADCOM_BCM5903M, 583 "Broadcom BCM5903M Fast Ethernet", 584 }, 585 { PCI_VENDOR_BROADCOM, 586 PCI_PRODUCT_BROADCOM_BCM5906, 587 "Broadcom BCM5906 Fast Ethernet", 588 }, 589 { PCI_VENDOR_BROADCOM, 590 PCI_PRODUCT_BROADCOM_BCM5906M, 591 "Broadcom BCM5906M Fast Ethernet", 592 }, 593 { PCI_VENDOR_BROADCOM, 594 PCI_PRODUCT_BROADCOM_BCM57760, 595 "Broadcom BCM57760 Fast Ethernet", 596 }, 597 { PCI_VENDOR_BROADCOM, 598 PCI_PRODUCT_BROADCOM_BCM57761, 599 "Broadcom BCM57761 Fast Ethernet", 600 }, 601 { PCI_VENDOR_BROADCOM, 602 PCI_PRODUCT_BROADCOM_BCM57762, 603 "Broadcom BCM57762 Gigabit Ethernet", 604 }, 605 { PCI_VENDOR_BROADCOM, 606 PCI_PRODUCT_BROADCOM_BCM57765, 607 "Broadcom BCM57765 Fast Ethernet", 608 }, 609 { PCI_VENDOR_BROADCOM, 610 PCI_PRODUCT_BROADCOM_BCM57766, 611 "Broadcom BCM57766 Fast Ethernet", 612 }, 613 { PCI_VENDOR_BROADCOM, 614 PCI_PRODUCT_BROADCOM_BCM57780, 615 "Broadcom BCM57780 Fast Ethernet", 616 }, 617 { PCI_VENDOR_BROADCOM, 618 PCI_PRODUCT_BROADCOM_BCM57781, 619 "Broadcom BCM57781 Fast Ethernet", 620 }, 621 { PCI_VENDOR_BROADCOM, 622 PCI_PRODUCT_BROADCOM_BCM57782, 623 "Broadcom BCM57782 Fast Ethernet", 624 }, 625 { PCI_VENDOR_BROADCOM, 626 PCI_PRODUCT_BROADCOM_BCM57785, 627 "Broadcom BCM57785 Fast Ethernet", 628 }, 629 { PCI_VENDOR_BROADCOM, 630 PCI_PRODUCT_BROADCOM_BCM57786, 631 "Broadcom BCM57786 Fast Ethernet", 632 }, 633 { PCI_VENDOR_BROADCOM, 634 PCI_PRODUCT_BROADCOM_BCM57788, 635 "Broadcom BCM57788 Fast Ethernet", 636 }, 637 { PCI_VENDOR_BROADCOM, 638 PCI_PRODUCT_BROADCOM_BCM57790, 639 "Broadcom BCM57790 Fast Ethernet", 640 }, 641 { PCI_VENDOR_BROADCOM, 642 PCI_PRODUCT_BROADCOM_BCM57791, 643 "Broadcom BCM57791 Fast Ethernet", 644 }, 645 { PCI_VENDOR_BROADCOM, 646 PCI_PRODUCT_BROADCOM_BCM57795, 647 "Broadcom BCM57795 Fast Ethernet", 648 }, 649 { PCI_VENDOR_SCHNEIDERKOCH, 650 PCI_PRODUCT_SCHNEIDERKOCH_SK_9DX1, 651 "SysKonnect SK-9Dx1 Gigabit Ethernet", 652 }, 653 { PCI_VENDOR_3COM, 654 PCI_PRODUCT_3COM_3C996, 655 "3Com 3c996 Gigabit Ethernet", 656 }, 657 { PCI_VENDOR_FUJITSU4, 658 PCI_PRODUCT_FUJITSU4_PW008GE4, 659 "Fujitsu PW008GE4 Gigabit Ethernet", 660 }, 661 { PCI_VENDOR_FUJITSU4, 662 PCI_PRODUCT_FUJITSU4_PW008GE5, 663 "Fujitsu PW008GE5 Gigabit Ethernet", 664 }, 665 { PCI_VENDOR_FUJITSU4, 666 PCI_PRODUCT_FUJITSU4_PP250_450_LAN, 667 "Fujitsu Primepower 250/450 Gigabit Ethernet", 668 }, 669 { 0, 670 0, 671 NULL }, 672 }; 673 674 #define BGE_IS_JUMBO_CAPABLE(sc) ((sc)->bge_flags & BGE_JUMBO_CAPABLE) 675 #define BGE_IS_5700_FAMILY(sc) ((sc)->bge_flags & BGE_5700_FAMILY) 676 #define BGE_IS_5705_PLUS(sc) ((sc)->bge_flags & BGE_5705_PLUS) 677 #define BGE_IS_5714_FAMILY(sc) ((sc)->bge_flags & BGE_5714_FAMILY) 678 #define BGE_IS_575X_PLUS(sc) ((sc)->bge_flags & BGE_575X_PLUS) 679 #define BGE_IS_5755_PLUS(sc) ((sc)->bge_flags & BGE_5755_PLUS) 680 #define BGE_IS_5717_PLUS(sc) ((sc)->bge_flags & BGE_5717_PLUS) 681 #define BGE_IS_57765_PLUS(sc) ((sc)->bge_flags & BGE_57765_PLUS) 682 683 static const struct bge_revision { 684 uint32_t br_chipid; 685 const char *br_name; 686 } bge_revisions[] = { 687 { BGE_CHIPID_BCM5700_A0, "BCM5700 A0" }, 688 { BGE_CHIPID_BCM5700_A1, "BCM5700 A1" }, 689 { BGE_CHIPID_BCM5700_B0, "BCM5700 B0" }, 690 { BGE_CHIPID_BCM5700_B1, "BCM5700 B1" }, 691 { BGE_CHIPID_BCM5700_B2, "BCM5700 B2" }, 692 { BGE_CHIPID_BCM5700_B3, "BCM5700 B3" }, 693 { BGE_CHIPID_BCM5700_ALTIMA, "BCM5700 Altima" }, 694 { BGE_CHIPID_BCM5700_C0, "BCM5700 C0" }, 695 { BGE_CHIPID_BCM5701_A0, "BCM5701 A0" }, 696 { BGE_CHIPID_BCM5701_B0, "BCM5701 B0" }, 697 { BGE_CHIPID_BCM5701_B2, "BCM5701 B2" }, 698 { BGE_CHIPID_BCM5701_B5, "BCM5701 B5" }, 699 { BGE_CHIPID_BCM5703_A0, "BCM5702/5703 A0" }, 700 { BGE_CHIPID_BCM5703_A1, "BCM5702/5703 A1" }, 701 { BGE_CHIPID_BCM5703_A2, "BCM5702/5703 A2" }, 702 { BGE_CHIPID_BCM5703_A3, "BCM5702/5703 A3" }, 703 { BGE_CHIPID_BCM5703_B0, "BCM5702/5703 B0" }, 704 { BGE_CHIPID_BCM5704_A0, "BCM5704 A0" }, 705 { BGE_CHIPID_BCM5704_A1, "BCM5704 A1" }, 706 { BGE_CHIPID_BCM5704_A2, "BCM5704 A2" }, 707 { BGE_CHIPID_BCM5704_A3, "BCM5704 A3" }, 708 { BGE_CHIPID_BCM5704_B0, "BCM5704 B0" }, 709 { BGE_CHIPID_BCM5705_A0, "BCM5705 A0" }, 710 { BGE_CHIPID_BCM5705_A1, "BCM5705 A1" }, 711 { BGE_CHIPID_BCM5705_A2, "BCM5705 A2" }, 712 { BGE_CHIPID_BCM5705_A3, "BCM5705 A3" }, 713 { BGE_CHIPID_BCM5750_A0, "BCM5750 A0" }, 714 { BGE_CHIPID_BCM5750_A1, "BCM5750 A1" }, 715 { BGE_CHIPID_BCM5750_A3, "BCM5750 A3" }, 716 { BGE_CHIPID_BCM5750_B0, "BCM5750 B0" }, 717 { BGE_CHIPID_BCM5750_B1, "BCM5750 B1" }, 718 { BGE_CHIPID_BCM5750_C0, "BCM5750 C0" }, 719 { BGE_CHIPID_BCM5750_C1, "BCM5750 C1" }, 720 { BGE_CHIPID_BCM5750_C2, "BCM5750 C2" }, 721 { BGE_CHIPID_BCM5752_A0, "BCM5752 A0" }, 722 { BGE_CHIPID_BCM5752_A1, "BCM5752 A1" }, 723 { BGE_CHIPID_BCM5752_A2, "BCM5752 A2" }, 724 { BGE_CHIPID_BCM5714_A0, "BCM5714 A0" }, 725 { BGE_CHIPID_BCM5714_B0, "BCM5714 B0" }, 726 { BGE_CHIPID_BCM5714_B3, "BCM5714 B3" }, 727 { BGE_CHIPID_BCM5715_A0, "BCM5715 A0" }, 728 { BGE_CHIPID_BCM5715_A1, "BCM5715 A1" }, 729 { BGE_CHIPID_BCM5715_A3, "BCM5715 A3" }, 730 { BGE_CHIPID_BCM5717_A0, "BCM5717 A0" }, 731 { BGE_CHIPID_BCM5717_B0, "BCM5717 B0" }, 732 { BGE_CHIPID_BCM5719_A0, "BCM5719 A0" }, 733 { BGE_CHIPID_BCM5720_A0, "BCM5720 A0" }, 734 { BGE_CHIPID_BCM5755_A0, "BCM5755 A0" }, 735 { BGE_CHIPID_BCM5755_A1, "BCM5755 A1" }, 736 { BGE_CHIPID_BCM5755_A2, "BCM5755 A2" }, 737 { BGE_CHIPID_BCM5755_C0, "BCM5755 C0" }, 738 { BGE_CHIPID_BCM5761_A0, "BCM5761 A0" }, 739 { BGE_CHIPID_BCM5761_A1, "BCM5761 A1" }, 740 { BGE_CHIPID_BCM5784_A0, "BCM5784 A0" }, 741 { BGE_CHIPID_BCM5784_A1, "BCM5784 A1" }, 742 /* 5754 and 5787 share the same ASIC ID */ 743 { BGE_CHIPID_BCM5787_A0, "BCM5754/5787 A0" }, 744 { BGE_CHIPID_BCM5787_A1, "BCM5754/5787 A1" }, 745 { BGE_CHIPID_BCM5787_A2, "BCM5754/5787 A2" }, 746 { BGE_CHIPID_BCM5906_A0, "BCM5906 A0" }, 747 { BGE_CHIPID_BCM5906_A1, "BCM5906 A1" }, 748 { BGE_CHIPID_BCM5906_A2, "BCM5906 A2" }, 749 { BGE_CHIPID_BCM57765_A0, "BCM57765 A0" }, 750 { BGE_CHIPID_BCM57765_B0, "BCM57765 B0" }, 751 { BGE_CHIPID_BCM57780_A0, "BCM57780 A0" }, 752 { BGE_CHIPID_BCM57780_A1, "BCM57780 A1" }, 753 754 { 0, NULL } 755 }; 756 757 /* 758 * Some defaults for major revisions, so that newer steppings 759 * that we don't know about have a shot at working. 760 */ 761 static const struct bge_revision bge_majorrevs[] = { 762 { BGE_ASICREV_BCM5700, "unknown BCM5700" }, 763 { BGE_ASICREV_BCM5701, "unknown BCM5701" }, 764 { BGE_ASICREV_BCM5703, "unknown BCM5703" }, 765 { BGE_ASICREV_BCM5704, "unknown BCM5704" }, 766 { BGE_ASICREV_BCM5705, "unknown BCM5705" }, 767 { BGE_ASICREV_BCM5750, "unknown BCM5750" }, 768 { BGE_ASICREV_BCM5714, "unknown BCM5714" }, 769 { BGE_ASICREV_BCM5714_A0, "unknown BCM5714" }, 770 { BGE_ASICREV_BCM5752, "unknown BCM5752" }, 771 { BGE_ASICREV_BCM5780, "unknown BCM5780" }, 772 { BGE_ASICREV_BCM5755, "unknown BCM5755" }, 773 { BGE_ASICREV_BCM5761, "unknown BCM5761" }, 774 { BGE_ASICREV_BCM5784, "unknown BCM5784" }, 775 { BGE_ASICREV_BCM5785, "unknown BCM5785" }, 776 /* 5754 and 5787 share the same ASIC ID */ 777 { BGE_ASICREV_BCM5787, "unknown BCM5754/5787" }, 778 { BGE_ASICREV_BCM5906, "unknown BCM5906" }, 779 { BGE_ASICREV_BCM57765, "unknown BCM57765" }, 780 { BGE_ASICREV_BCM57766, "unknown BCM57766" }, 781 { BGE_ASICREV_BCM57780, "unknown BCM57780" }, 782 { BGE_ASICREV_BCM5717, "unknown BCM5717" }, 783 { BGE_ASICREV_BCM5719, "unknown BCM5719" }, 784 { BGE_ASICREV_BCM5720, "unknown BCM5720" }, 785 786 { 0, NULL } 787 }; 788 789 static int bge_allow_asf = 1; 790 791 CFATTACH_DECL_NEW(bge, sizeof(struct bge_softc), 792 bge_probe, bge_attach, NULL, NULL); 793 794 static uint32_t 795 bge_readmem_ind(struct bge_softc *sc, int off) 796 { 797 pcireg_t val; 798 799 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906 && 800 off >= BGE_STATS_BLOCK && off < BGE_SEND_RING_1_TO_4) 801 return 0; 802 803 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_BASEADDR, off); 804 val = pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_DATA); 805 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_BASEADDR, 0); 806 return val; 807 } 808 809 static void 810 bge_writemem_ind(struct bge_softc *sc, int off, int val) 811 { 812 813 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_BASEADDR, off); 814 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_DATA, val); 815 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_BASEADDR, 0); 816 } 817 818 /* 819 * PCI Express only 820 */ 821 static void 822 bge_set_max_readrq(struct bge_softc *sc) 823 { 824 pcireg_t val; 825 826 val = pci_conf_read(sc->sc_pc, sc->sc_pcitag, sc->bge_pciecap 827 + PCI_PCIE_DCSR); 828 val &= ~PCI_PCIE_DCSR_MAX_READ_REQ; 829 switch (sc->bge_expmrq) { 830 case 2048: 831 val |= BGE_PCIE_DEVCTL_MAX_READRQ_2048; 832 break; 833 case 4096: 834 val |= BGE_PCIE_DEVCTL_MAX_READRQ_4096; 835 break; 836 default: 837 panic("incorrect expmrq value(%d)", sc->bge_expmrq); 838 break; 839 } 840 pci_conf_write(sc->sc_pc, sc->sc_pcitag, sc->bge_pciecap 841 + PCI_PCIE_DCSR, val); 842 } 843 844 #ifdef notdef 845 static uint32_t 846 bge_readreg_ind(struct bge_softc *sc, int off) 847 { 848 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_REG_BASEADDR, off); 849 return (pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_REG_DATA)); 850 } 851 #endif 852 853 static void 854 bge_writereg_ind(struct bge_softc *sc, int off, int val) 855 { 856 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_REG_BASEADDR, off); 857 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_REG_DATA, val); 858 } 859 860 static void 861 bge_writemem_direct(struct bge_softc *sc, int off, int val) 862 { 863 CSR_WRITE_4(sc, off, val); 864 } 865 866 static void 867 bge_writembx(struct bge_softc *sc, int off, int val) 868 { 869 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 870 off += BGE_LPMBX_IRQ0_HI - BGE_MBX_IRQ0_HI; 871 872 CSR_WRITE_4(sc, off, val); 873 } 874 875 static void 876 bge_writembx_flush(struct bge_softc *sc, int off, int val) 877 { 878 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 879 off += BGE_LPMBX_IRQ0_HI - BGE_MBX_IRQ0_HI; 880 881 CSR_WRITE_4_FLUSH(sc, off, val); 882 } 883 884 /* 885 * Clear all stale locks and select the lock for this driver instance. 886 */ 887 void 888 bge_ape_lock_init(struct bge_softc *sc) 889 { 890 struct pci_attach_args *pa = &(sc->bge_pa); 891 uint32_t bit, regbase; 892 int i; 893 894 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761) 895 regbase = BGE_APE_LOCK_GRANT; 896 else 897 regbase = BGE_APE_PER_LOCK_GRANT; 898 899 /* Clear any stale locks. */ 900 for (i = BGE_APE_LOCK_PHY0; i <= BGE_APE_LOCK_GPIO; i++) { 901 switch (i) { 902 case BGE_APE_LOCK_PHY0: 903 case BGE_APE_LOCK_PHY1: 904 case BGE_APE_LOCK_PHY2: 905 case BGE_APE_LOCK_PHY3: 906 bit = BGE_APE_LOCK_GRANT_DRIVER0; 907 break; 908 default: 909 if (pa->pa_function != 0) 910 bit = BGE_APE_LOCK_GRANT_DRIVER0; 911 else 912 bit = (1 << pa->pa_function); 913 } 914 APE_WRITE_4(sc, regbase + 4 * i, bit); 915 } 916 917 /* Select the PHY lock based on the device's function number. */ 918 switch (pa->pa_function) { 919 case 0: 920 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY0; 921 break; 922 case 1: 923 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY1; 924 break; 925 case 2: 926 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY2; 927 break; 928 case 3: 929 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY3; 930 break; 931 default: 932 printf("%s: PHY lock not supported on function\n", 933 device_xname(sc->bge_dev)); 934 break; 935 } 936 } 937 938 /* 939 * Check for APE firmware, set flags, and print version info. 940 */ 941 void 942 bge_ape_read_fw_ver(struct bge_softc *sc) 943 { 944 const char *fwtype; 945 uint32_t apedata, features; 946 947 /* Check for a valid APE signature in shared memory. */ 948 apedata = APE_READ_4(sc, BGE_APE_SEG_SIG); 949 if (apedata != BGE_APE_SEG_SIG_MAGIC) { 950 sc->bge_mfw_flags &= ~ BGE_MFW_ON_APE; 951 return; 952 } 953 954 /* Check if APE firmware is running. */ 955 apedata = APE_READ_4(sc, BGE_APE_FW_STATUS); 956 if ((apedata & BGE_APE_FW_STATUS_READY) == 0) { 957 printf("%s: APE signature found but FW status not ready! " 958 "0x%08x\n", device_xname(sc->bge_dev), apedata); 959 return; 960 } 961 962 sc->bge_mfw_flags |= BGE_MFW_ON_APE; 963 964 /* Fetch the APE firwmare type and version. */ 965 apedata = APE_READ_4(sc, BGE_APE_FW_VERSION); 966 features = APE_READ_4(sc, BGE_APE_FW_FEATURES); 967 if ((features & BGE_APE_FW_FEATURE_NCSI) != 0) { 968 sc->bge_mfw_flags |= BGE_MFW_TYPE_NCSI; 969 fwtype = "NCSI"; 970 } else if ((features & BGE_APE_FW_FEATURE_DASH) != 0) { 971 sc->bge_mfw_flags |= BGE_MFW_TYPE_DASH; 972 fwtype = "DASH"; 973 } else 974 fwtype = "UNKN"; 975 976 /* Print the APE firmware version. */ 977 printf(", APE firmware %s %d.%d.%d.%d", fwtype, 978 (apedata & BGE_APE_FW_VERSION_MAJMSK) >> BGE_APE_FW_VERSION_MAJSFT, 979 (apedata & BGE_APE_FW_VERSION_MINMSK) >> BGE_APE_FW_VERSION_MINSFT, 980 (apedata & BGE_APE_FW_VERSION_REVMSK) >> BGE_APE_FW_VERSION_REVSFT, 981 (apedata & BGE_APE_FW_VERSION_BLDMSK)); 982 } 983 984 int 985 bge_ape_lock(struct bge_softc *sc, int locknum) 986 { 987 struct pci_attach_args *pa = &(sc->bge_pa); 988 uint32_t bit, gnt, req, status; 989 int i, off; 990 991 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0) 992 return (0); 993 994 /* Lock request/grant registers have different bases. */ 995 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761) { 996 req = BGE_APE_LOCK_REQ; 997 gnt = BGE_APE_LOCK_GRANT; 998 } else { 999 req = BGE_APE_PER_LOCK_REQ; 1000 gnt = BGE_APE_PER_LOCK_GRANT; 1001 } 1002 1003 off = 4 * locknum; 1004 1005 switch (locknum) { 1006 case BGE_APE_LOCK_GPIO: 1007 /* Lock required when using GPIO. */ 1008 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761) 1009 return (0); 1010 if (pa->pa_function == 0) 1011 bit = BGE_APE_LOCK_REQ_DRIVER0; 1012 else 1013 bit = (1 << pa->pa_function); 1014 break; 1015 case BGE_APE_LOCK_GRC: 1016 /* Lock required to reset the device. */ 1017 if (pa->pa_function == 0) 1018 bit = BGE_APE_LOCK_REQ_DRIVER0; 1019 else 1020 bit = (1 << pa->pa_function); 1021 break; 1022 case BGE_APE_LOCK_MEM: 1023 /* Lock required when accessing certain APE memory. */ 1024 if (pa->pa_function == 0) 1025 bit = BGE_APE_LOCK_REQ_DRIVER0; 1026 else 1027 bit = (1 << pa->pa_function); 1028 break; 1029 case BGE_APE_LOCK_PHY0: 1030 case BGE_APE_LOCK_PHY1: 1031 case BGE_APE_LOCK_PHY2: 1032 case BGE_APE_LOCK_PHY3: 1033 /* Lock required when accessing PHYs. */ 1034 bit = BGE_APE_LOCK_REQ_DRIVER0; 1035 break; 1036 default: 1037 return (EINVAL); 1038 } 1039 1040 /* Request a lock. */ 1041 APE_WRITE_4_FLUSH(sc, req + off, bit); 1042 1043 /* Wait up to 1 second to acquire lock. */ 1044 for (i = 0; i < 20000; i++) { 1045 status = APE_READ_4(sc, gnt + off); 1046 if (status == bit) 1047 break; 1048 DELAY(50); 1049 } 1050 1051 /* Handle any errors. */ 1052 if (status != bit) { 1053 printf("%s: APE lock %d request failed! " 1054 "request = 0x%04x[0x%04x], status = 0x%04x[0x%04x]\n", 1055 device_xname(sc->bge_dev), 1056 locknum, req + off, bit & 0xFFFF, gnt + off, 1057 status & 0xFFFF); 1058 /* Revoke the lock request. */ 1059 APE_WRITE_4(sc, gnt + off, bit); 1060 return (EBUSY); 1061 } 1062 1063 return (0); 1064 } 1065 1066 void 1067 bge_ape_unlock(struct bge_softc *sc, int locknum) 1068 { 1069 struct pci_attach_args *pa = &(sc->bge_pa); 1070 uint32_t bit, gnt; 1071 int off; 1072 1073 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0) 1074 return; 1075 1076 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761) 1077 gnt = BGE_APE_LOCK_GRANT; 1078 else 1079 gnt = BGE_APE_PER_LOCK_GRANT; 1080 1081 off = 4 * locknum; 1082 1083 switch (locknum) { 1084 case BGE_APE_LOCK_GPIO: 1085 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761) 1086 return; 1087 if (pa->pa_function == 0) 1088 bit = BGE_APE_LOCK_GRANT_DRIVER0; 1089 else 1090 bit = (1 << pa->pa_function); 1091 break; 1092 case BGE_APE_LOCK_GRC: 1093 if (pa->pa_function == 0) 1094 bit = BGE_APE_LOCK_GRANT_DRIVER0; 1095 else 1096 bit = (1 << pa->pa_function); 1097 break; 1098 case BGE_APE_LOCK_MEM: 1099 if (pa->pa_function == 0) 1100 bit = BGE_APE_LOCK_GRANT_DRIVER0; 1101 else 1102 bit = (1 << pa->pa_function); 1103 break; 1104 case BGE_APE_LOCK_PHY0: 1105 case BGE_APE_LOCK_PHY1: 1106 case BGE_APE_LOCK_PHY2: 1107 case BGE_APE_LOCK_PHY3: 1108 bit = BGE_APE_LOCK_GRANT_DRIVER0; 1109 break; 1110 default: 1111 return; 1112 } 1113 1114 /* Write and flush for consecutive bge_ape_lock() */ 1115 APE_WRITE_4_FLUSH(sc, gnt + off, bit); 1116 } 1117 1118 /* 1119 * Send an event to the APE firmware. 1120 */ 1121 void 1122 bge_ape_send_event(struct bge_softc *sc, uint32_t event) 1123 { 1124 uint32_t apedata; 1125 int i; 1126 1127 /* NCSI does not support APE events. */ 1128 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0) 1129 return; 1130 1131 /* Wait up to 1ms for APE to service previous event. */ 1132 for (i = 10; i > 0; i--) { 1133 if (bge_ape_lock(sc, BGE_APE_LOCK_MEM) != 0) 1134 break; 1135 apedata = APE_READ_4(sc, BGE_APE_EVENT_STATUS); 1136 if ((apedata & BGE_APE_EVENT_STATUS_EVENT_PENDING) == 0) { 1137 APE_WRITE_4(sc, BGE_APE_EVENT_STATUS, event | 1138 BGE_APE_EVENT_STATUS_EVENT_PENDING); 1139 bge_ape_unlock(sc, BGE_APE_LOCK_MEM); 1140 APE_WRITE_4(sc, BGE_APE_EVENT, BGE_APE_EVENT_1); 1141 break; 1142 } 1143 bge_ape_unlock(sc, BGE_APE_LOCK_MEM); 1144 DELAY(100); 1145 } 1146 if (i == 0) { 1147 printf("%s: APE event 0x%08x send timed out\n", 1148 device_xname(sc->bge_dev), event); 1149 } 1150 } 1151 1152 void 1153 bge_ape_driver_state_change(struct bge_softc *sc, int kind) 1154 { 1155 uint32_t apedata, event; 1156 1157 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0) 1158 return; 1159 1160 switch (kind) { 1161 case BGE_RESET_START: 1162 /* If this is the first load, clear the load counter. */ 1163 apedata = APE_READ_4(sc, BGE_APE_HOST_SEG_SIG); 1164 if (apedata != BGE_APE_HOST_SEG_SIG_MAGIC) 1165 APE_WRITE_4(sc, BGE_APE_HOST_INIT_COUNT, 0); 1166 else { 1167 apedata = APE_READ_4(sc, BGE_APE_HOST_INIT_COUNT); 1168 APE_WRITE_4(sc, BGE_APE_HOST_INIT_COUNT, ++apedata); 1169 } 1170 APE_WRITE_4(sc, BGE_APE_HOST_SEG_SIG, 1171 BGE_APE_HOST_SEG_SIG_MAGIC); 1172 APE_WRITE_4(sc, BGE_APE_HOST_SEG_LEN, 1173 BGE_APE_HOST_SEG_LEN_MAGIC); 1174 1175 /* Add some version info if bge(4) supports it. */ 1176 APE_WRITE_4(sc, BGE_APE_HOST_DRIVER_ID, 1177 BGE_APE_HOST_DRIVER_ID_MAGIC(1, 0)); 1178 APE_WRITE_4(sc, BGE_APE_HOST_BEHAVIOR, 1179 BGE_APE_HOST_BEHAV_NO_PHYLOCK); 1180 APE_WRITE_4(sc, BGE_APE_HOST_HEARTBEAT_INT_MS, 1181 BGE_APE_HOST_HEARTBEAT_INT_DISABLE); 1182 APE_WRITE_4(sc, BGE_APE_HOST_DRVR_STATE, 1183 BGE_APE_HOST_DRVR_STATE_START); 1184 event = BGE_APE_EVENT_STATUS_STATE_START; 1185 break; 1186 case BGE_RESET_SHUTDOWN: 1187 APE_WRITE_4(sc, BGE_APE_HOST_DRVR_STATE, 1188 BGE_APE_HOST_DRVR_STATE_UNLOAD); 1189 event = BGE_APE_EVENT_STATUS_STATE_UNLOAD; 1190 break; 1191 case BGE_RESET_SUSPEND: 1192 event = BGE_APE_EVENT_STATUS_STATE_SUSPEND; 1193 break; 1194 default: 1195 return; 1196 } 1197 1198 bge_ape_send_event(sc, event | BGE_APE_EVENT_STATUS_DRIVER_EVNT | 1199 BGE_APE_EVENT_STATUS_STATE_CHNGE); 1200 } 1201 1202 static uint8_t 1203 bge_nvram_getbyte(struct bge_softc *sc, int addr, uint8_t *dest) 1204 { 1205 uint32_t access, byte = 0; 1206 int i; 1207 1208 /* Lock. */ 1209 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_SET1); 1210 for (i = 0; i < 8000; i++) { 1211 if (CSR_READ_4(sc, BGE_NVRAM_SWARB) & BGE_NVRAMSWARB_GNT1) 1212 break; 1213 DELAY(20); 1214 } 1215 if (i == 8000) 1216 return 1; 1217 1218 /* Enable access. */ 1219 access = CSR_READ_4(sc, BGE_NVRAM_ACCESS); 1220 CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access | BGE_NVRAMACC_ENABLE); 1221 1222 CSR_WRITE_4(sc, BGE_NVRAM_ADDR, addr & 0xfffffffc); 1223 CSR_WRITE_4(sc, BGE_NVRAM_CMD, BGE_NVRAM_READCMD); 1224 for (i = 0; i < BGE_TIMEOUT * 10; i++) { 1225 DELAY(10); 1226 if (CSR_READ_4(sc, BGE_NVRAM_CMD) & BGE_NVRAMCMD_DONE) { 1227 DELAY(10); 1228 break; 1229 } 1230 } 1231 1232 if (i == BGE_TIMEOUT * 10) { 1233 aprint_error_dev(sc->bge_dev, "nvram read timed out\n"); 1234 return 1; 1235 } 1236 1237 /* Get result. */ 1238 byte = CSR_READ_4(sc, BGE_NVRAM_RDDATA); 1239 1240 *dest = (bswap32(byte) >> ((addr % 4) * 8)) & 0xFF; 1241 1242 /* Disable access. */ 1243 CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access); 1244 1245 /* Unlock. */ 1246 CSR_WRITE_4_FLUSH(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_CLR1); 1247 1248 return 0; 1249 } 1250 1251 /* 1252 * Read a sequence of bytes from NVRAM. 1253 */ 1254 static int 1255 bge_read_nvram(struct bge_softc *sc, uint8_t *dest, int off, int cnt) 1256 { 1257 int error = 0, i; 1258 uint8_t byte = 0; 1259 1260 if (BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5906) 1261 return 1; 1262 1263 for (i = 0; i < cnt; i++) { 1264 error = bge_nvram_getbyte(sc, off + i, &byte); 1265 if (error) 1266 break; 1267 *(dest + i) = byte; 1268 } 1269 1270 return (error ? 1 : 0); 1271 } 1272 1273 /* 1274 * Read a byte of data stored in the EEPROM at address 'addr.' The 1275 * BCM570x supports both the traditional bitbang interface and an 1276 * auto access interface for reading the EEPROM. We use the auto 1277 * access method. 1278 */ 1279 static uint8_t 1280 bge_eeprom_getbyte(struct bge_softc *sc, int addr, uint8_t *dest) 1281 { 1282 int i; 1283 uint32_t byte = 0; 1284 1285 /* 1286 * Enable use of auto EEPROM access so we can avoid 1287 * having to use the bitbang method. 1288 */ 1289 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM); 1290 1291 /* Reset the EEPROM, load the clock period. */ 1292 CSR_WRITE_4(sc, BGE_EE_ADDR, 1293 BGE_EEADDR_RESET | BGE_EEHALFCLK(BGE_HALFCLK_384SCL)); 1294 DELAY(20); 1295 1296 /* Issue the read EEPROM command. */ 1297 CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr); 1298 1299 /* Wait for completion */ 1300 for (i = 0; i < BGE_TIMEOUT * 10; i++) { 1301 DELAY(10); 1302 if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE) 1303 break; 1304 } 1305 1306 if (i == BGE_TIMEOUT * 10) { 1307 aprint_error_dev(sc->bge_dev, "eeprom read timed out\n"); 1308 return 1; 1309 } 1310 1311 /* Get result. */ 1312 byte = CSR_READ_4(sc, BGE_EE_DATA); 1313 1314 *dest = (byte >> ((addr % 4) * 8)) & 0xFF; 1315 1316 return 0; 1317 } 1318 1319 /* 1320 * Read a sequence of bytes from the EEPROM. 1321 */ 1322 static int 1323 bge_read_eeprom(struct bge_softc *sc, void *destv, int off, int cnt) 1324 { 1325 int error = 0, i; 1326 uint8_t byte = 0; 1327 char *dest = destv; 1328 1329 for (i = 0; i < cnt; i++) { 1330 error = bge_eeprom_getbyte(sc, off + i, &byte); 1331 if (error) 1332 break; 1333 *(dest + i) = byte; 1334 } 1335 1336 return (error ? 1 : 0); 1337 } 1338 1339 static int 1340 bge_miibus_readreg(device_t dev, int phy, int reg) 1341 { 1342 struct bge_softc *sc = device_private(dev); 1343 uint32_t val; 1344 uint32_t autopoll; 1345 int i; 1346 1347 if (bge_ape_lock(sc, sc->bge_phy_ape_lock) != 0) 1348 return 0; 1349 1350 /* Reading with autopolling on may trigger PCI errors */ 1351 autopoll = CSR_READ_4(sc, BGE_MI_MODE); 1352 if (autopoll & BGE_MIMODE_AUTOPOLL) { 1353 BGE_STS_CLRBIT(sc, BGE_STS_AUTOPOLL); 1354 BGE_CLRBIT_FLUSH(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 1355 DELAY(80); 1356 } 1357 1358 CSR_WRITE_4_FLUSH(sc, BGE_MI_COMM, BGE_MICMD_READ | BGE_MICOMM_BUSY | 1359 BGE_MIPHY(phy) | BGE_MIREG(reg)); 1360 1361 for (i = 0; i < BGE_TIMEOUT; i++) { 1362 delay(10); 1363 val = CSR_READ_4(sc, BGE_MI_COMM); 1364 if (!(val & BGE_MICOMM_BUSY)) { 1365 DELAY(5); 1366 val = CSR_READ_4(sc, BGE_MI_COMM); 1367 break; 1368 } 1369 } 1370 1371 if (i == BGE_TIMEOUT) { 1372 aprint_error_dev(sc->bge_dev, "PHY read timed out\n"); 1373 val = 0; 1374 goto done; 1375 } 1376 1377 done: 1378 if (autopoll & BGE_MIMODE_AUTOPOLL) { 1379 BGE_STS_SETBIT(sc, BGE_STS_AUTOPOLL); 1380 BGE_SETBIT_FLUSH(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 1381 DELAY(80); 1382 } 1383 1384 bge_ape_unlock(sc, sc->bge_phy_ape_lock); 1385 1386 if (val & BGE_MICOMM_READFAIL) 1387 return 0; 1388 1389 return (val & 0xFFFF); 1390 } 1391 1392 static void 1393 bge_miibus_writereg(device_t dev, int phy, int reg, int val) 1394 { 1395 struct bge_softc *sc = device_private(dev); 1396 uint32_t autopoll; 1397 int i; 1398 1399 if (bge_ape_lock(sc, sc->bge_phy_ape_lock) != 0) 1400 return; 1401 1402 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906 && 1403 (reg == BRGPHY_MII_1000CTL || reg == BRGPHY_MII_AUXCTL)) 1404 return; 1405 1406 /* Reading with autopolling on may trigger PCI errors */ 1407 autopoll = CSR_READ_4(sc, BGE_MI_MODE); 1408 if (autopoll & BGE_MIMODE_AUTOPOLL) { 1409 BGE_STS_CLRBIT(sc, BGE_STS_AUTOPOLL); 1410 BGE_CLRBIT_FLUSH(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 1411 DELAY(80); 1412 } 1413 1414 CSR_WRITE_4_FLUSH(sc, BGE_MI_COMM, BGE_MICMD_WRITE | BGE_MICOMM_BUSY | 1415 BGE_MIPHY(phy) | BGE_MIREG(reg) | val); 1416 1417 for (i = 0; i < BGE_TIMEOUT; i++) { 1418 delay(10); 1419 if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY)) { 1420 delay(5); 1421 CSR_READ_4(sc, BGE_MI_COMM); 1422 break; 1423 } 1424 } 1425 1426 if (autopoll & BGE_MIMODE_AUTOPOLL) { 1427 BGE_STS_SETBIT(sc, BGE_STS_AUTOPOLL); 1428 BGE_SETBIT_FLUSH(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 1429 delay(80); 1430 } 1431 1432 bge_ape_unlock(sc, sc->bge_phy_ape_lock); 1433 1434 if (i == BGE_TIMEOUT) 1435 aprint_error_dev(sc->bge_dev, "PHY read timed out\n"); 1436 } 1437 1438 static void 1439 bge_miibus_statchg(struct ifnet *ifp) 1440 { 1441 struct bge_softc *sc = ifp->if_softc; 1442 struct mii_data *mii = &sc->bge_mii; 1443 uint32_t mac_mode, rx_mode, tx_mode; 1444 1445 /* 1446 * Get flow control negotiation result. 1447 */ 1448 if (IFM_SUBTYPE(mii->mii_media.ifm_cur->ifm_media) == IFM_AUTO && 1449 (mii->mii_media_active & IFM_ETH_FMASK) != sc->bge_flowflags) { 1450 sc->bge_flowflags = mii->mii_media_active & IFM_ETH_FMASK; 1451 mii->mii_media_active &= ~IFM_ETH_FMASK; 1452 } 1453 1454 /* Set the port mode (MII/GMII) to match the link speed. */ 1455 mac_mode = CSR_READ_4(sc, BGE_MAC_MODE) & 1456 ~(BGE_MACMODE_PORTMODE | BGE_MACMODE_HALF_DUPLEX); 1457 tx_mode = CSR_READ_4(sc, BGE_TX_MODE); 1458 rx_mode = CSR_READ_4(sc, BGE_RX_MODE); 1459 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T || 1460 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX) 1461 mac_mode |= BGE_PORTMODE_GMII; 1462 else 1463 mac_mode |= BGE_PORTMODE_MII; 1464 1465 tx_mode &= ~BGE_TXMODE_FLOWCTL_ENABLE; 1466 rx_mode &= ~BGE_RXMODE_FLOWCTL_ENABLE; 1467 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 1468 if (sc->bge_flowflags & IFM_ETH_TXPAUSE) 1469 tx_mode |= BGE_TXMODE_FLOWCTL_ENABLE; 1470 if (sc->bge_flowflags & IFM_ETH_RXPAUSE) 1471 rx_mode |= BGE_RXMODE_FLOWCTL_ENABLE; 1472 } else 1473 mac_mode |= BGE_MACMODE_HALF_DUPLEX; 1474 1475 CSR_WRITE_4_FLUSH(sc, BGE_MAC_MODE, mac_mode); 1476 DELAY(40); 1477 CSR_WRITE_4(sc, BGE_TX_MODE, tx_mode); 1478 CSR_WRITE_4(sc, BGE_RX_MODE, rx_mode); 1479 } 1480 1481 /* 1482 * Update rx threshold levels to values in a particular slot 1483 * of the interrupt-mitigation table bge_rx_threshes. 1484 */ 1485 static void 1486 bge_set_thresh(struct ifnet *ifp, int lvl) 1487 { 1488 struct bge_softc *sc = ifp->if_softc; 1489 int s; 1490 1491 /* For now, just save the new Rx-intr thresholds and record 1492 * that a threshold update is pending. Updating the hardware 1493 * registers here (even at splhigh()) is observed to 1494 * occasionaly cause glitches where Rx-interrupts are not 1495 * honoured for up to 10 seconds. jonathan (at) NetBSD.org, 2003-04-05 1496 */ 1497 s = splnet(); 1498 sc->bge_rx_coal_ticks = bge_rx_threshes[lvl].rx_ticks; 1499 sc->bge_rx_max_coal_bds = bge_rx_threshes[lvl].rx_max_bds; 1500 sc->bge_pending_rxintr_change = 1; 1501 splx(s); 1502 } 1503 1504 1505 /* 1506 * Update Rx thresholds of all bge devices 1507 */ 1508 static void 1509 bge_update_all_threshes(int lvl) 1510 { 1511 struct ifnet *ifp; 1512 const char * const namebuf = "bge"; 1513 int namelen; 1514 1515 if (lvl < 0) 1516 lvl = 0; 1517 else if (lvl >= NBGE_RX_THRESH) 1518 lvl = NBGE_RX_THRESH - 1; 1519 1520 namelen = strlen(namebuf); 1521 /* 1522 * Now search all the interfaces for this name/number 1523 */ 1524 IFNET_FOREACH(ifp) { 1525 if (strncmp(ifp->if_xname, namebuf, namelen) != 0) 1526 continue; 1527 /* We got a match: update if doing auto-threshold-tuning */ 1528 if (bge_auto_thresh) 1529 bge_set_thresh(ifp, lvl); 1530 } 1531 } 1532 1533 /* 1534 * Handle events that have triggered interrupts. 1535 */ 1536 static void 1537 bge_handle_events(struct bge_softc *sc) 1538 { 1539 1540 return; 1541 } 1542 1543 /* 1544 * Memory management for jumbo frames. 1545 */ 1546 1547 static int 1548 bge_alloc_jumbo_mem(struct bge_softc *sc) 1549 { 1550 char *ptr, *kva; 1551 bus_dma_segment_t seg; 1552 int i, rseg, state, error; 1553 struct bge_jpool_entry *entry; 1554 1555 state = error = 0; 1556 1557 /* Grab a big chunk o' storage. */ 1558 if (bus_dmamem_alloc(sc->bge_dmatag, BGE_JMEM, PAGE_SIZE, 0, 1559 &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 1560 aprint_error_dev(sc->bge_dev, "can't alloc rx buffers\n"); 1561 return ENOBUFS; 1562 } 1563 1564 state = 1; 1565 if (bus_dmamem_map(sc->bge_dmatag, &seg, rseg, BGE_JMEM, (void **)&kva, 1566 BUS_DMA_NOWAIT)) { 1567 aprint_error_dev(sc->bge_dev, 1568 "can't map DMA buffers (%d bytes)\n", (int)BGE_JMEM); 1569 error = ENOBUFS; 1570 goto out; 1571 } 1572 1573 state = 2; 1574 if (bus_dmamap_create(sc->bge_dmatag, BGE_JMEM, 1, BGE_JMEM, 0, 1575 BUS_DMA_NOWAIT, &sc->bge_cdata.bge_rx_jumbo_map)) { 1576 aprint_error_dev(sc->bge_dev, "can't create DMA map\n"); 1577 error = ENOBUFS; 1578 goto out; 1579 } 1580 1581 state = 3; 1582 if (bus_dmamap_load(sc->bge_dmatag, sc->bge_cdata.bge_rx_jumbo_map, 1583 kva, BGE_JMEM, NULL, BUS_DMA_NOWAIT)) { 1584 aprint_error_dev(sc->bge_dev, "can't load DMA map\n"); 1585 error = ENOBUFS; 1586 goto out; 1587 } 1588 1589 state = 4; 1590 sc->bge_cdata.bge_jumbo_buf = (void *)kva; 1591 DPRINTFN(1,("bge_jumbo_buf = %p\n", sc->bge_cdata.bge_jumbo_buf)); 1592 1593 SLIST_INIT(&sc->bge_jfree_listhead); 1594 SLIST_INIT(&sc->bge_jinuse_listhead); 1595 1596 /* 1597 * Now divide it up into 9K pieces and save the addresses 1598 * in an array. 1599 */ 1600 ptr = sc->bge_cdata.bge_jumbo_buf; 1601 for (i = 0; i < BGE_JSLOTS; i++) { 1602 sc->bge_cdata.bge_jslots[i] = ptr; 1603 ptr += BGE_JLEN; 1604 entry = malloc(sizeof(struct bge_jpool_entry), 1605 M_DEVBUF, M_NOWAIT); 1606 if (entry == NULL) { 1607 aprint_error_dev(sc->bge_dev, 1608 "no memory for jumbo buffer queue!\n"); 1609 error = ENOBUFS; 1610 goto out; 1611 } 1612 entry->slot = i; 1613 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, 1614 entry, jpool_entries); 1615 } 1616 out: 1617 if (error != 0) { 1618 switch (state) { 1619 case 4: 1620 bus_dmamap_unload(sc->bge_dmatag, 1621 sc->bge_cdata.bge_rx_jumbo_map); 1622 case 3: 1623 bus_dmamap_destroy(sc->bge_dmatag, 1624 sc->bge_cdata.bge_rx_jumbo_map); 1625 case 2: 1626 bus_dmamem_unmap(sc->bge_dmatag, kva, BGE_JMEM); 1627 case 1: 1628 bus_dmamem_free(sc->bge_dmatag, &seg, rseg); 1629 break; 1630 default: 1631 break; 1632 } 1633 } 1634 1635 return error; 1636 } 1637 1638 /* 1639 * Allocate a jumbo buffer. 1640 */ 1641 static void * 1642 bge_jalloc(struct bge_softc *sc) 1643 { 1644 struct bge_jpool_entry *entry; 1645 1646 entry = SLIST_FIRST(&sc->bge_jfree_listhead); 1647 1648 if (entry == NULL) { 1649 aprint_error_dev(sc->bge_dev, "no free jumbo buffers\n"); 1650 return NULL; 1651 } 1652 1653 SLIST_REMOVE_HEAD(&sc->bge_jfree_listhead, jpool_entries); 1654 SLIST_INSERT_HEAD(&sc->bge_jinuse_listhead, entry, jpool_entries); 1655 return (sc->bge_cdata.bge_jslots[entry->slot]); 1656 } 1657 1658 /* 1659 * Release a jumbo buffer. 1660 */ 1661 static void 1662 bge_jfree(struct mbuf *m, void *buf, size_t size, void *arg) 1663 { 1664 struct bge_jpool_entry *entry; 1665 struct bge_softc *sc; 1666 int i, s; 1667 1668 /* Extract the softc struct pointer. */ 1669 sc = (struct bge_softc *)arg; 1670 1671 if (sc == NULL) 1672 panic("bge_jfree: can't find softc pointer!"); 1673 1674 /* calculate the slot this buffer belongs to */ 1675 1676 i = ((char *)buf 1677 - (char *)sc->bge_cdata.bge_jumbo_buf) / BGE_JLEN; 1678 1679 if ((i < 0) || (i >= BGE_JSLOTS)) 1680 panic("bge_jfree: asked to free buffer that we don't manage!"); 1681 1682 s = splvm(); 1683 entry = SLIST_FIRST(&sc->bge_jinuse_listhead); 1684 if (entry == NULL) 1685 panic("bge_jfree: buffer not in use!"); 1686 entry->slot = i; 1687 SLIST_REMOVE_HEAD(&sc->bge_jinuse_listhead, jpool_entries); 1688 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, entry, jpool_entries); 1689 1690 if (__predict_true(m != NULL)) 1691 pool_cache_put(mb_cache, m); 1692 splx(s); 1693 } 1694 1695 1696 /* 1697 * Initialize a standard receive ring descriptor. 1698 */ 1699 static int 1700 bge_newbuf_std(struct bge_softc *sc, int i, struct mbuf *m, 1701 bus_dmamap_t dmamap) 1702 { 1703 struct mbuf *m_new = NULL; 1704 struct bge_rx_bd *r; 1705 int error; 1706 1707 if (dmamap == NULL) { 1708 error = bus_dmamap_create(sc->bge_dmatag, MCLBYTES, 1, 1709 MCLBYTES, 0, BUS_DMA_NOWAIT, &dmamap); 1710 if (error != 0) 1711 return error; 1712 } 1713 1714 sc->bge_cdata.bge_rx_std_map[i] = dmamap; 1715 1716 if (m == NULL) { 1717 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1718 if (m_new == NULL) 1719 return ENOBUFS; 1720 1721 MCLGET(m_new, M_DONTWAIT); 1722 if (!(m_new->m_flags & M_EXT)) { 1723 m_freem(m_new); 1724 return ENOBUFS; 1725 } 1726 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1727 1728 } else { 1729 m_new = m; 1730 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1731 m_new->m_data = m_new->m_ext.ext_buf; 1732 } 1733 if (!(sc->bge_flags & BGE_RX_ALIGNBUG)) 1734 m_adj(m_new, ETHER_ALIGN); 1735 if (bus_dmamap_load_mbuf(sc->bge_dmatag, dmamap, m_new, 1736 BUS_DMA_READ|BUS_DMA_NOWAIT)) 1737 return ENOBUFS; 1738 bus_dmamap_sync(sc->bge_dmatag, dmamap, 0, dmamap->dm_mapsize, 1739 BUS_DMASYNC_PREREAD); 1740 1741 sc->bge_cdata.bge_rx_std_chain[i] = m_new; 1742 r = &sc->bge_rdata->bge_rx_std_ring[i]; 1743 BGE_HOSTADDR(r->bge_addr, dmamap->dm_segs[0].ds_addr); 1744 r->bge_flags = BGE_RXBDFLAG_END; 1745 r->bge_len = m_new->m_len; 1746 r->bge_idx = i; 1747 1748 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 1749 offsetof(struct bge_ring_data, bge_rx_std_ring) + 1750 i * sizeof (struct bge_rx_bd), 1751 sizeof (struct bge_rx_bd), 1752 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1753 1754 return 0; 1755 } 1756 1757 /* 1758 * Initialize a jumbo receive ring descriptor. This allocates 1759 * a jumbo buffer from the pool managed internally by the driver. 1760 */ 1761 static int 1762 bge_newbuf_jumbo(struct bge_softc *sc, int i, struct mbuf *m) 1763 { 1764 struct mbuf *m_new = NULL; 1765 struct bge_rx_bd *r; 1766 void *buf = NULL; 1767 1768 if (m == NULL) { 1769 1770 /* Allocate the mbuf. */ 1771 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1772 if (m_new == NULL) 1773 return ENOBUFS; 1774 1775 /* Allocate the jumbo buffer */ 1776 buf = bge_jalloc(sc); 1777 if (buf == NULL) { 1778 m_freem(m_new); 1779 aprint_error_dev(sc->bge_dev, 1780 "jumbo allocation failed -- packet dropped!\n"); 1781 return ENOBUFS; 1782 } 1783 1784 /* Attach the buffer to the mbuf. */ 1785 m_new->m_len = m_new->m_pkthdr.len = BGE_JUMBO_FRAMELEN; 1786 MEXTADD(m_new, buf, BGE_JUMBO_FRAMELEN, M_DEVBUF, 1787 bge_jfree, sc); 1788 m_new->m_flags |= M_EXT_RW; 1789 } else { 1790 m_new = m; 1791 buf = m_new->m_data = m_new->m_ext.ext_buf; 1792 m_new->m_ext.ext_size = BGE_JUMBO_FRAMELEN; 1793 } 1794 if (!(sc->bge_flags & BGE_RX_ALIGNBUG)) 1795 m_adj(m_new, ETHER_ALIGN); 1796 bus_dmamap_sync(sc->bge_dmatag, sc->bge_cdata.bge_rx_jumbo_map, 1797 mtod(m_new, char *) - (char *)sc->bge_cdata.bge_jumbo_buf, BGE_JLEN, 1798 BUS_DMASYNC_PREREAD); 1799 /* Set up the descriptor. */ 1800 r = &sc->bge_rdata->bge_rx_jumbo_ring[i]; 1801 sc->bge_cdata.bge_rx_jumbo_chain[i] = m_new; 1802 BGE_HOSTADDR(r->bge_addr, BGE_JUMBO_DMA_ADDR(sc, m_new)); 1803 r->bge_flags = BGE_RXBDFLAG_END|BGE_RXBDFLAG_JUMBO_RING; 1804 r->bge_len = m_new->m_len; 1805 r->bge_idx = i; 1806 1807 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 1808 offsetof(struct bge_ring_data, bge_rx_jumbo_ring) + 1809 i * sizeof (struct bge_rx_bd), 1810 sizeof (struct bge_rx_bd), 1811 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1812 1813 return 0; 1814 } 1815 1816 /* 1817 * The standard receive ring has 512 entries in it. At 2K per mbuf cluster, 1818 * that's 1MB or memory, which is a lot. For now, we fill only the first 1819 * 256 ring entries and hope that our CPU is fast enough to keep up with 1820 * the NIC. 1821 */ 1822 static int 1823 bge_init_rx_ring_std(struct bge_softc *sc) 1824 { 1825 int i; 1826 1827 if (sc->bge_flags & BGE_RXRING_VALID) 1828 return 0; 1829 1830 for (i = 0; i < BGE_SSLOTS; i++) { 1831 if (bge_newbuf_std(sc, i, NULL, 0) == ENOBUFS) 1832 return ENOBUFS; 1833 } 1834 1835 sc->bge_std = i - 1; 1836 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std); 1837 1838 sc->bge_flags |= BGE_RXRING_VALID; 1839 1840 return 0; 1841 } 1842 1843 static void 1844 bge_free_rx_ring_std(struct bge_softc *sc) 1845 { 1846 int i; 1847 1848 if (!(sc->bge_flags & BGE_RXRING_VALID)) 1849 return; 1850 1851 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { 1852 if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) { 1853 m_freem(sc->bge_cdata.bge_rx_std_chain[i]); 1854 sc->bge_cdata.bge_rx_std_chain[i] = NULL; 1855 bus_dmamap_destroy(sc->bge_dmatag, 1856 sc->bge_cdata.bge_rx_std_map[i]); 1857 } 1858 memset((char *)&sc->bge_rdata->bge_rx_std_ring[i], 0, 1859 sizeof(struct bge_rx_bd)); 1860 } 1861 1862 sc->bge_flags &= ~BGE_RXRING_VALID; 1863 } 1864 1865 static int 1866 bge_init_rx_ring_jumbo(struct bge_softc *sc) 1867 { 1868 int i; 1869 volatile struct bge_rcb *rcb; 1870 1871 if (sc->bge_flags & BGE_JUMBO_RXRING_VALID) 1872 return 0; 1873 1874 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 1875 if (bge_newbuf_jumbo(sc, i, NULL) == ENOBUFS) 1876 return ENOBUFS; 1877 } 1878 1879 sc->bge_jumbo = i - 1; 1880 sc->bge_flags |= BGE_JUMBO_RXRING_VALID; 1881 1882 rcb = &sc->bge_rdata->bge_info.bge_jumbo_rx_rcb; 1883 rcb->bge_maxlen_flags = 0; 1884 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 1885 1886 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo); 1887 1888 return 0; 1889 } 1890 1891 static void 1892 bge_free_rx_ring_jumbo(struct bge_softc *sc) 1893 { 1894 int i; 1895 1896 if (!(sc->bge_flags & BGE_JUMBO_RXRING_VALID)) 1897 return; 1898 1899 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 1900 if (sc->bge_cdata.bge_rx_jumbo_chain[i] != NULL) { 1901 m_freem(sc->bge_cdata.bge_rx_jumbo_chain[i]); 1902 sc->bge_cdata.bge_rx_jumbo_chain[i] = NULL; 1903 } 1904 memset((char *)&sc->bge_rdata->bge_rx_jumbo_ring[i], 0, 1905 sizeof(struct bge_rx_bd)); 1906 } 1907 1908 sc->bge_flags &= ~BGE_JUMBO_RXRING_VALID; 1909 } 1910 1911 static void 1912 bge_free_tx_ring(struct bge_softc *sc) 1913 { 1914 int i; 1915 struct txdmamap_pool_entry *dma; 1916 1917 if (!(sc->bge_flags & BGE_TXRING_VALID)) 1918 return; 1919 1920 for (i = 0; i < BGE_TX_RING_CNT; i++) { 1921 if (sc->bge_cdata.bge_tx_chain[i] != NULL) { 1922 m_freem(sc->bge_cdata.bge_tx_chain[i]); 1923 sc->bge_cdata.bge_tx_chain[i] = NULL; 1924 SLIST_INSERT_HEAD(&sc->txdma_list, sc->txdma[i], 1925 link); 1926 sc->txdma[i] = 0; 1927 } 1928 memset((char *)&sc->bge_rdata->bge_tx_ring[i], 0, 1929 sizeof(struct bge_tx_bd)); 1930 } 1931 1932 while ((dma = SLIST_FIRST(&sc->txdma_list))) { 1933 SLIST_REMOVE_HEAD(&sc->txdma_list, link); 1934 bus_dmamap_destroy(sc->bge_dmatag, dma->dmamap); 1935 free(dma, M_DEVBUF); 1936 } 1937 1938 sc->bge_flags &= ~BGE_TXRING_VALID; 1939 } 1940 1941 static int 1942 bge_init_tx_ring(struct bge_softc *sc) 1943 { 1944 int i; 1945 bus_dmamap_t dmamap; 1946 struct txdmamap_pool_entry *dma; 1947 1948 if (sc->bge_flags & BGE_TXRING_VALID) 1949 return 0; 1950 1951 sc->bge_txcnt = 0; 1952 sc->bge_tx_saved_considx = 0; 1953 1954 /* Initialize transmit producer index for host-memory send ring. */ 1955 sc->bge_tx_prodidx = 0; 1956 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx); 1957 /* 5700 b2 errata */ 1958 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX) 1959 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx); 1960 1961 /* NIC-memory send ring not used; initialize to zero. */ 1962 bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0); 1963 /* 5700 b2 errata */ 1964 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX) 1965 bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0); 1966 1967 SLIST_INIT(&sc->txdma_list); 1968 for (i = 0; i < BGE_RSLOTS; i++) { 1969 if (bus_dmamap_create(sc->bge_dmatag, BGE_TXDMA_MAX, 1970 BGE_NTXSEG, ETHER_MAX_LEN_JUMBO, 0, BUS_DMA_NOWAIT, 1971 &dmamap)) 1972 return ENOBUFS; 1973 if (dmamap == NULL) 1974 panic("dmamap NULL in bge_init_tx_ring"); 1975 dma = malloc(sizeof(*dma), M_DEVBUF, M_NOWAIT); 1976 if (dma == NULL) { 1977 aprint_error_dev(sc->bge_dev, 1978 "can't alloc txdmamap_pool_entry\n"); 1979 bus_dmamap_destroy(sc->bge_dmatag, dmamap); 1980 return ENOMEM; 1981 } 1982 dma->dmamap = dmamap; 1983 SLIST_INSERT_HEAD(&sc->txdma_list, dma, link); 1984 } 1985 1986 sc->bge_flags |= BGE_TXRING_VALID; 1987 1988 return 0; 1989 } 1990 1991 static void 1992 bge_setmulti(struct bge_softc *sc) 1993 { 1994 struct ethercom *ac = &sc->ethercom; 1995 struct ifnet *ifp = &ac->ec_if; 1996 struct ether_multi *enm; 1997 struct ether_multistep step; 1998 uint32_t hashes[4] = { 0, 0, 0, 0 }; 1999 uint32_t h; 2000 int i; 2001 2002 if (ifp->if_flags & IFF_PROMISC) 2003 goto allmulti; 2004 2005 /* Now program new ones. */ 2006 ETHER_FIRST_MULTI(step, ac, enm); 2007 while (enm != NULL) { 2008 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 2009 /* 2010 * We must listen to a range of multicast addresses. 2011 * For now, just accept all multicasts, rather than 2012 * trying to set only those filter bits needed to match 2013 * the range. (At this time, the only use of address 2014 * ranges is for IP multicast routing, for which the 2015 * range is big enough to require all bits set.) 2016 */ 2017 goto allmulti; 2018 } 2019 2020 h = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN); 2021 2022 /* Just want the 7 least-significant bits. */ 2023 h &= 0x7f; 2024 2025 hashes[(h & 0x60) >> 5] |= 1 << (h & 0x1F); 2026 ETHER_NEXT_MULTI(step, enm); 2027 } 2028 2029 ifp->if_flags &= ~IFF_ALLMULTI; 2030 goto setit; 2031 2032 allmulti: 2033 ifp->if_flags |= IFF_ALLMULTI; 2034 hashes[0] = hashes[1] = hashes[2] = hashes[3] = 0xffffffff; 2035 2036 setit: 2037 for (i = 0; i < 4; i++) 2038 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]); 2039 } 2040 2041 static void 2042 bge_sig_pre_reset(struct bge_softc *sc, int type) 2043 { 2044 2045 /* 2046 * Some chips don't like this so only do this if ASF is enabled 2047 */ 2048 if (sc->bge_asf_mode) 2049 bge_writemem_ind(sc, BGE_SRAM_FW_MB, BGE_SRAM_FW_MB_MAGIC); 2050 2051 if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) { 2052 switch (type) { 2053 case BGE_RESET_START: 2054 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 2055 BGE_FW_DRV_STATE_START); 2056 break; 2057 case BGE_RESET_SHUTDOWN: 2058 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 2059 BGE_FW_DRV_STATE_UNLOAD); 2060 break; 2061 case BGE_RESET_SUSPEND: 2062 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 2063 BGE_FW_DRV_STATE_SUSPEND); 2064 break; 2065 } 2066 } 2067 2068 if (type == BGE_RESET_START || type == BGE_RESET_SUSPEND) 2069 bge_ape_driver_state_change(sc, type); 2070 } 2071 2072 static void 2073 bge_sig_post_reset(struct bge_softc *sc, int type) 2074 { 2075 2076 if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) { 2077 switch (type) { 2078 case BGE_RESET_START: 2079 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 2080 BGE_FW_DRV_STATE_START_DONE); 2081 /* START DONE */ 2082 break; 2083 case BGE_RESET_SHUTDOWN: 2084 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 2085 BGE_FW_DRV_STATE_UNLOAD_DONE); 2086 break; 2087 } 2088 } 2089 2090 if (type == BGE_RESET_SHUTDOWN) 2091 bge_ape_driver_state_change(sc, type); 2092 } 2093 2094 static void 2095 bge_sig_legacy(struct bge_softc *sc, int type) 2096 { 2097 2098 if (sc->bge_asf_mode) { 2099 switch (type) { 2100 case BGE_RESET_START: 2101 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 2102 BGE_FW_DRV_STATE_START); 2103 break; 2104 case BGE_RESET_SHUTDOWN: 2105 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 2106 BGE_FW_DRV_STATE_UNLOAD); 2107 break; 2108 } 2109 } 2110 } 2111 2112 static void 2113 bge_wait_for_event_ack(struct bge_softc *sc) 2114 { 2115 int i; 2116 2117 /* wait up to 2500usec */ 2118 for (i = 0; i < 250; i++) { 2119 if (!(CSR_READ_4(sc, BGE_RX_CPU_EVENT) & 2120 BGE_RX_CPU_DRV_EVENT)) 2121 break; 2122 DELAY(10); 2123 } 2124 } 2125 2126 static void 2127 bge_stop_fw(struct bge_softc *sc) 2128 { 2129 2130 if (sc->bge_asf_mode) { 2131 bge_wait_for_event_ack(sc); 2132 2133 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_MB, BGE_FW_CMD_PAUSE); 2134 CSR_WRITE_4_FLUSH(sc, BGE_RX_CPU_EVENT, 2135 CSR_READ_4(sc, BGE_RX_CPU_EVENT) | BGE_RX_CPU_DRV_EVENT); 2136 2137 bge_wait_for_event_ack(sc); 2138 } 2139 } 2140 2141 static int 2142 bge_poll_fw(struct bge_softc *sc) 2143 { 2144 uint32_t val; 2145 int i; 2146 2147 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 2148 for (i = 0; i < BGE_TIMEOUT; i++) { 2149 val = CSR_READ_4(sc, BGE_VCPU_STATUS); 2150 if (val & BGE_VCPU_STATUS_INIT_DONE) 2151 break; 2152 DELAY(100); 2153 } 2154 if (i >= BGE_TIMEOUT) { 2155 aprint_error_dev(sc->bge_dev, "reset timed out\n"); 2156 return -1; 2157 } 2158 } else if ((sc->bge_flags & BGE_NO_EEPROM) == 0) { 2159 /* 2160 * Poll the value location we just wrote until 2161 * we see the 1's complement of the magic number. 2162 * This indicates that the firmware initialization 2163 * is complete. 2164 * XXX 1000ms for Flash and 10000ms for SEEPROM. 2165 */ 2166 for (i = 0; i < BGE_TIMEOUT; i++) { 2167 val = bge_readmem_ind(sc, BGE_SRAM_FW_MB); 2168 if (val == ~BGE_SRAM_FW_MB_MAGIC) 2169 break; 2170 DELAY(10); 2171 } 2172 2173 if (i >= BGE_TIMEOUT) { 2174 aprint_error_dev(sc->bge_dev, 2175 "firmware handshake timed out, val = %x\n", val); 2176 return -1; 2177 } 2178 } 2179 2180 if (sc->bge_chipid == BGE_CHIPID_BCM57765_A0) { 2181 /* tg3 says we have to wait extra time */ 2182 delay(10 * 1000); 2183 } 2184 2185 return 0; 2186 } 2187 2188 int 2189 bge_phy_addr(struct bge_softc *sc) 2190 { 2191 struct pci_attach_args *pa = &(sc->bge_pa); 2192 int phy_addr = 1; 2193 2194 /* 2195 * PHY address mapping for various devices. 2196 * 2197 * | F0 Cu | F0 Sr | F1 Cu | F1 Sr | 2198 * ---------+-------+-------+-------+-------+ 2199 * BCM57XX | 1 | X | X | X | 2200 * BCM5704 | 1 | X | 1 | X | 2201 * BCM5717 | 1 | 8 | 2 | 9 | 2202 * BCM5719 | 1 | 8 | 2 | 9 | 2203 * BCM5720 | 1 | 8 | 2 | 9 | 2204 * 2205 * | F2 Cu | F2 Sr | F3 Cu | F3 Sr | 2206 * ---------+-------+-------+-------+-------+ 2207 * BCM57XX | X | X | X | X | 2208 * BCM5704 | X | X | X | X | 2209 * BCM5717 | X | X | X | X | 2210 * BCM5719 | 3 | 10 | 4 | 11 | 2211 * BCM5720 | X | X | X | X | 2212 * 2213 * Other addresses may respond but they are not 2214 * IEEE compliant PHYs and should be ignored. 2215 */ 2216 switch (BGE_ASICREV(sc->bge_chipid)) { 2217 case BGE_ASICREV_BCM5717: 2218 case BGE_ASICREV_BCM5719: 2219 case BGE_ASICREV_BCM5720: 2220 phy_addr = pa->pa_function; 2221 if (sc->bge_chipid == BGE_CHIPID_BCM5717_A0) { 2222 phy_addr += (CSR_READ_4(sc, BGE_SGDIG_STS) & 2223 BGE_SGDIGSTS_IS_SERDES) ? 8 : 1; 2224 } else { 2225 phy_addr += (CSR_READ_4(sc, BGE_CPMU_PHY_STRAP) & 2226 BGE_CPMU_PHY_STRAP_IS_SERDES) ? 8 : 1; 2227 } 2228 } 2229 2230 return phy_addr; 2231 } 2232 2233 /* 2234 * Do endian, PCI and DMA initialization. Also check the on-board ROM 2235 * self-test results. 2236 */ 2237 static int 2238 bge_chipinit(struct bge_softc *sc) 2239 { 2240 uint32_t dma_rw_ctl, mode_ctl, reg; 2241 int i; 2242 2243 /* Set endianness before we access any non-PCI registers. */ 2244 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MISC_CTL, 2245 BGE_INIT); 2246 2247 /* 2248 * Clear the MAC statistics block in the NIC's 2249 * internal memory. 2250 */ 2251 for (i = BGE_STATS_BLOCK; 2252 i < BGE_STATS_BLOCK_END + 1; i += sizeof(uint32_t)) 2253 BGE_MEMWIN_WRITE(sc->sc_pc, sc->sc_pcitag, i, 0); 2254 2255 for (i = BGE_STATUS_BLOCK; 2256 i < BGE_STATUS_BLOCK_END + 1; i += sizeof(uint32_t)) 2257 BGE_MEMWIN_WRITE(sc->sc_pc, sc->sc_pcitag, i, 0); 2258 2259 /* 5717 workaround from tg3 */ 2260 if (sc->bge_chipid == BGE_CHIPID_BCM5717_A0) { 2261 /* Save */ 2262 mode_ctl = CSR_READ_4(sc, BGE_MODE_CTL); 2263 2264 /* Temporary modify MODE_CTL to control TLP */ 2265 reg = mode_ctl & ~BGE_MODECTL_PCIE_TLPADDRMASK; 2266 CSR_WRITE_4(sc, BGE_MODE_CTL, reg | BGE_MODECTL_PCIE_TLPADDR1); 2267 2268 /* Control TLP */ 2269 reg = CSR_READ_4(sc, BGE_TLP_CONTROL_REG + 2270 BGE_TLP_PHYCTL1); 2271 CSR_WRITE_4(sc, BGE_TLP_CONTROL_REG + BGE_TLP_PHYCTL1, 2272 reg | BGE_TLP_PHYCTL1_EN_L1PLLPD); 2273 2274 /* Restore */ 2275 CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl); 2276 } 2277 2278 /* XXX Should we use 57765_FAMILY? */ 2279 if (BGE_IS_57765_PLUS(sc)) { 2280 if (sc->bge_chipid == BGE_CHIPID_BCM57765_A0) { 2281 /* Save */ 2282 mode_ctl = CSR_READ_4(sc, BGE_MODE_CTL); 2283 2284 /* Temporary modify MODE_CTL to control TLP */ 2285 reg = mode_ctl & ~BGE_MODECTL_PCIE_TLPADDRMASK; 2286 CSR_WRITE_4(sc, BGE_MODE_CTL, 2287 reg | BGE_MODECTL_PCIE_TLPADDR1); 2288 2289 /* Control TLP */ 2290 reg = CSR_READ_4(sc, BGE_TLP_CONTROL_REG + 2291 BGE_TLP_PHYCTL5); 2292 CSR_WRITE_4(sc, BGE_TLP_CONTROL_REG + BGE_TLP_PHYCTL5, 2293 reg | BGE_TLP_PHYCTL5_DIS_L2CLKREQ); 2294 2295 /* Restore */ 2296 CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl); 2297 } 2298 if (BGE_CHIPREV(sc->bge_chipid) != BGE_CHIPREV_57765_AX) { 2299 reg = CSR_READ_4(sc, BGE_CPMU_PADRNG_CTL); 2300 CSR_WRITE_4(sc, BGE_CPMU_PADRNG_CTL, 2301 reg | BGE_CPMU_PADRNG_CTL_RDIV2); 2302 2303 /* Save */ 2304 mode_ctl = CSR_READ_4(sc, BGE_MODE_CTL); 2305 2306 /* Temporary modify MODE_CTL to control TLP */ 2307 reg = mode_ctl & ~BGE_MODECTL_PCIE_TLPADDRMASK; 2308 CSR_WRITE_4(sc, BGE_MODE_CTL, 2309 reg | BGE_MODECTL_PCIE_TLPADDR0); 2310 2311 /* Control TLP */ 2312 reg = CSR_READ_4(sc, BGE_TLP_CONTROL_REG + 2313 BGE_TLP_FTSMAX); 2314 reg &= ~BGE_TLP_FTSMAX_MSK; 2315 CSR_WRITE_4(sc, BGE_TLP_CONTROL_REG + BGE_TLP_FTSMAX, 2316 reg | BGE_TLP_FTSMAX_VAL); 2317 2318 /* Restore */ 2319 CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl); 2320 } 2321 2322 reg = CSR_READ_4(sc, BGE_CPMU_LSPD_10MB_CLK); 2323 reg &= ~BGE_CPMU_LSPD_10MB_MACCLK_MASK; 2324 reg |= BGE_CPMU_LSPD_10MB_MACCLK_6_25; 2325 CSR_WRITE_4(sc, BGE_CPMU_LSPD_10MB_CLK, reg); 2326 } 2327 2328 /* Set up the PCI DMA control register. */ 2329 dma_rw_ctl = BGE_PCI_READ_CMD | BGE_PCI_WRITE_CMD; 2330 if (sc->bge_flags & BGE_PCIE) { 2331 /* Read watermark not used, 128 bytes for write. */ 2332 DPRINTFN(4, ("(%s: PCI-Express DMA setting)\n", 2333 device_xname(sc->bge_dev))); 2334 dma_rw_ctl |= BGE_PCIDMARWCTL_WR_WAT_SHIFT(3); 2335 } else if (sc->bge_flags & BGE_PCIX) { 2336 DPRINTFN(4, ("(:%s: PCI-X DMA setting)\n", 2337 device_xname(sc->bge_dev))); 2338 /* PCI-X bus */ 2339 if (BGE_IS_5714_FAMILY(sc)) { 2340 /* 256 bytes for read and write. */ 2341 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(2) | 2342 BGE_PCIDMARWCTL_WR_WAT_SHIFT(2); 2343 2344 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5780) 2345 dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL; 2346 else 2347 dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE_LOCAL; 2348 } else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) { 2349 /* 1536 bytes for read, 384 bytes for write. */ 2350 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(7) | 2351 BGE_PCIDMARWCTL_WR_WAT_SHIFT(3); 2352 } else { 2353 /* 384 bytes for read and write. */ 2354 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(3) | 2355 BGE_PCIDMARWCTL_WR_WAT_SHIFT(3) | 2356 (0x0F); 2357 } 2358 2359 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5703 || 2360 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) { 2361 uint32_t tmp; 2362 2363 /* Set ONEDMA_ATONCE for hardware workaround. */ 2364 tmp = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 2365 BGE_PCI_CLKCTL) & 0x1f; 2366 if (tmp == 6 || tmp == 7) 2367 dma_rw_ctl |= 2368 BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL; 2369 2370 /* Set PCI-X DMA write workaround. */ 2371 dma_rw_ctl |= BGE_PCIDMARWCTL_ASRT_ALL_BE; 2372 } 2373 } else { 2374 /* Conventional PCI bus: 256 bytes for read and write. */ 2375 DPRINTFN(4, ("(%s: PCI 2.2 DMA setting)\n", 2376 device_xname(sc->bge_dev))); 2377 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(7) | 2378 BGE_PCIDMARWCTL_WR_WAT_SHIFT(7); 2379 2380 if (BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5705 && 2381 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5750) 2382 dma_rw_ctl |= 0x0F; 2383 } 2384 2385 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 2386 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5701) 2387 dma_rw_ctl |= BGE_PCIDMARWCTL_USE_MRM | 2388 BGE_PCIDMARWCTL_ASRT_ALL_BE; 2389 2390 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5703 || 2391 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) 2392 dma_rw_ctl &= ~BGE_PCIDMARWCTL_MINDMA; 2393 2394 if (BGE_IS_5717_PLUS(sc)) { 2395 dma_rw_ctl &= ~BGE_PCIDMARWCTL_DIS_CACHE_ALIGNMENT; 2396 if (sc->bge_chipid == BGE_CHIPID_BCM57765_A0) 2397 dma_rw_ctl &= ~BGE_PCIDMARWCTL_CRDRDR_RDMA_MRRS_MSK; 2398 2399 /* 2400 * Enable HW workaround for controllers that misinterpret 2401 * a status tag update and leave interrupts permanently 2402 * disabled. 2403 */ 2404 if (BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5717 && 2405 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM57765) 2406 dma_rw_ctl |= BGE_PCIDMARWCTL_TAGGED_STATUS_WA; 2407 } 2408 2409 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_DMA_RW_CTL, 2410 dma_rw_ctl); 2411 2412 /* 2413 * Set up general mode register. 2414 */ 2415 mode_ctl = BGE_DMA_SWAP_OPTIONS; 2416 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) { 2417 /* Retain Host-2-BMC settings written by APE firmware. */ 2418 mode_ctl |= CSR_READ_4(sc, BGE_MODE_CTL) & 2419 (BGE_MODECTL_BYTESWAP_B2HRX_DATA | 2420 BGE_MODECTL_WORDSWAP_B2HRX_DATA | 2421 BGE_MODECTL_B2HRX_ENABLE | BGE_MODECTL_HTX2B_ENABLE); 2422 } 2423 mode_ctl |= BGE_MODECTL_MAC_ATTN_INTR | BGE_MODECTL_HOST_SEND_BDS | 2424 BGE_MODECTL_TX_NO_PHDR_CSUM; 2425 2426 /* 2427 * BCM5701 B5 have a bug causing data corruption when using 2428 * 64-bit DMA reads, which can be terminated early and then 2429 * completed later as 32-bit accesses, in combination with 2430 * certain bridges. 2431 */ 2432 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5701 && 2433 sc->bge_chipid == BGE_CHIPID_BCM5701_B5) 2434 mode_ctl |= BGE_MODECTL_FORCE_PCI32; 2435 2436 /* 2437 * Tell the firmware the driver is running 2438 */ 2439 if (sc->bge_asf_mode & ASF_STACKUP) 2440 mode_ctl |= BGE_MODECTL_STACKUP; 2441 2442 CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl); 2443 2444 /* 2445 * Disable memory write invalidate. Apparently it is not supported 2446 * properly by these devices. 2447 */ 2448 PCI_CLRBIT(sc->sc_pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG, 2449 PCI_COMMAND_INVALIDATE_ENABLE); 2450 2451 #ifdef __brokenalpha__ 2452 /* 2453 * Must insure that we do not cross an 8K (bytes) boundary 2454 * for DMA reads. Our highest limit is 1K bytes. This is a 2455 * restriction on some ALPHA platforms with early revision 2456 * 21174 PCI chipsets, such as the AlphaPC 164lx 2457 */ 2458 PCI_SETBIT(sc, BGE_PCI_DMA_RW_CTL, BGE_PCI_READ_BNDRY_1024, 4); 2459 #endif 2460 2461 /* Set the timer prescaler (always 66MHz) */ 2462 CSR_WRITE_4(sc, BGE_MISC_CFG, BGE_32BITTIME_66MHZ); 2463 2464 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 2465 DELAY(40); /* XXX */ 2466 2467 /* Put PHY into ready state */ 2468 BGE_CLRBIT_FLUSH(sc, BGE_MISC_CFG, BGE_MISCCFG_EPHY_IDDQ); 2469 DELAY(40); 2470 } 2471 2472 return 0; 2473 } 2474 2475 static int 2476 bge_blockinit(struct bge_softc *sc) 2477 { 2478 volatile struct bge_rcb *rcb; 2479 bus_size_t rcb_addr; 2480 int i; 2481 struct ifnet *ifp = &sc->ethercom.ec_if; 2482 bge_hostaddr taddr; 2483 uint32_t dmactl, val; 2484 2485 /* 2486 * Initialize the memory window pointer register so that 2487 * we can access the first 32K of internal NIC RAM. This will 2488 * allow us to set up the TX send ring RCBs and the RX return 2489 * ring RCBs, plus other things which live in NIC memory. 2490 */ 2491 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_BASEADDR, 0); 2492 2493 /* Step 33: Configure mbuf memory pool */ 2494 if (!BGE_IS_5705_PLUS(sc)) { 2495 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, 2496 BGE_BUFFPOOL_1); 2497 2498 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) 2499 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000); 2500 else 2501 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000); 2502 2503 /* Configure DMA resource pool */ 2504 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_BASEADDR, 2505 BGE_DMA_DESCRIPTORS); 2506 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LEN, 0x2000); 2507 } 2508 2509 /* Step 35: Configure mbuf pool watermarks */ 2510 #ifdef ORIG_WPAUL_VALUES 2511 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 24); 2512 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 24); 2513 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 48); 2514 #else 2515 2516 /* new broadcom docs strongly recommend these: */ 2517 if (BGE_IS_5717_PLUS(sc)) { 2518 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0); 2519 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x2a); 2520 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0xa0); 2521 } else if (BGE_IS_5705_PLUS(sc)) { 2522 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0); 2523 2524 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 2525 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x04); 2526 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x10); 2527 } else { 2528 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x10); 2529 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60); 2530 } 2531 } else if (!BGE_IS_5705_PLUS(sc)) { 2532 if (ifp->if_mtu > ETHER_MAX_LEN) { 2533 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x50); 2534 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x20); 2535 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60); 2536 } else { 2537 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 304); 2538 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 152); 2539 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 380); 2540 } 2541 } else { 2542 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0); 2543 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x10); 2544 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60); 2545 } 2546 #endif 2547 2548 /* Step 36: Configure DMA resource watermarks */ 2549 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5); 2550 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10); 2551 2552 /* Step 38: Enable buffer manager */ 2553 val = BGE_BMANMODE_ENABLE | BGE_BMANMODE_ATTN; 2554 /* 2555 * Change the arbitration algorithm of TXMBUF read request to 2556 * round-robin instead of priority based for BCM5719. When 2557 * TXFIFO is almost empty, RDMA will hold its request until 2558 * TXFIFO is not almost empty. 2559 */ 2560 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719) 2561 val |= BGE_BMANMODE_NO_TX_UNDERRUN; 2562 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5717 || 2563 sc->bge_chipid == BGE_CHIPID_BCM5719_A0 || 2564 sc->bge_chipid == BGE_CHIPID_BCM5720_A0) 2565 val |= BGE_BMANMODE_LOMBUF_ATTN; 2566 CSR_WRITE_4(sc, BGE_BMAN_MODE, val); 2567 2568 /* Step 39: Poll for buffer manager start indication */ 2569 for (i = 0; i < BGE_TIMEOUT * 2; i++) { 2570 DELAY(10); 2571 if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE) 2572 break; 2573 } 2574 2575 if (i == BGE_TIMEOUT * 2) { 2576 aprint_error_dev(sc->bge_dev, 2577 "buffer manager failed to start\n"); 2578 return ENXIO; 2579 } 2580 2581 /* Step 40: Enable flow-through queues */ 2582 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 2583 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 2584 2585 /* Wait until queue initialization is complete */ 2586 for (i = 0; i < BGE_TIMEOUT * 2; i++) { 2587 if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0) 2588 break; 2589 DELAY(10); 2590 } 2591 2592 if (i == BGE_TIMEOUT * 2) { 2593 aprint_error_dev(sc->bge_dev, 2594 "flow-through queue init failed\n"); 2595 return ENXIO; 2596 } 2597 2598 /* Step 41: Initialize the standard RX ring control block */ 2599 rcb = &sc->bge_rdata->bge_info.bge_std_rx_rcb; 2600 BGE_HOSTADDR(rcb->bge_hostaddr, BGE_RING_DMA_ADDR(sc, bge_rx_std_ring)); 2601 if (BGE_IS_5717_PLUS(sc)) 2602 rcb->bge_maxlen_flags = 2603 BGE_RCB_MAXLEN_FLAGS(512, BGE_MAX_FRAMELEN << 2); 2604 else if (BGE_IS_5705_PLUS(sc)) 2605 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(512, 0); 2606 else 2607 rcb->bge_maxlen_flags = 2608 BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 0); 2609 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5717 || 2610 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719 || 2611 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) 2612 rcb->bge_nicaddr = BGE_STD_RX_RINGS_5717; 2613 else 2614 rcb->bge_nicaddr = BGE_STD_RX_RINGS; 2615 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcb->bge_hostaddr.bge_addr_hi); 2616 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcb->bge_hostaddr.bge_addr_lo); 2617 CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 2618 CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcb->bge_nicaddr); 2619 2620 /* 2621 * Step 42: Initialize the jumbo RX ring control block 2622 * We set the 'ring disabled' bit in the flags 2623 * field until we're actually ready to start 2624 * using this ring (i.e. once we set the MTU 2625 * high enough to require it). 2626 */ 2627 if (BGE_IS_JUMBO_CAPABLE(sc)) { 2628 rcb = &sc->bge_rdata->bge_info.bge_jumbo_rx_rcb; 2629 BGE_HOSTADDR(rcb->bge_hostaddr, 2630 BGE_RING_DMA_ADDR(sc, bge_rx_jumbo_ring)); 2631 rcb->bge_maxlen_flags = 2632 BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 2633 BGE_RCB_FLAG_RING_DISABLED); 2634 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5717 || 2635 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719 || 2636 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) 2637 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS_5717; 2638 else 2639 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS; 2640 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI, 2641 rcb->bge_hostaddr.bge_addr_hi); 2642 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO, 2643 rcb->bge_hostaddr.bge_addr_lo); 2644 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, 2645 rcb->bge_maxlen_flags); 2646 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcb->bge_nicaddr); 2647 /* Reset the jumbo receive producer ring producer index. */ 2648 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0); 2649 } 2650 2651 /* Disable the mini receive producer ring RCB. */ 2652 if (BGE_IS_5700_FAMILY(sc)) { 2653 /* Set up dummy disabled mini ring RCB */ 2654 rcb = &sc->bge_rdata->bge_info.bge_mini_rx_rcb; 2655 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0, 2656 BGE_RCB_FLAG_RING_DISABLED); 2657 CSR_WRITE_4(sc, BGE_RX_MINI_RCB_MAXLEN_FLAGS, 2658 rcb->bge_maxlen_flags); 2659 /* Reset the mini receive producer ring producer index. */ 2660 bge_writembx(sc, BGE_MBX_RX_MINI_PROD_LO, 0); 2661 2662 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 2663 offsetof(struct bge_ring_data, bge_info), 2664 sizeof (struct bge_gib), 2665 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2666 } 2667 2668 /* Choose de-pipeline mode for BCM5906 A0, A1 and A2. */ 2669 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 2670 if (sc->bge_chipid == BGE_CHIPID_BCM5906_A0 || 2671 sc->bge_chipid == BGE_CHIPID_BCM5906_A1 || 2672 sc->bge_chipid == BGE_CHIPID_BCM5906_A2) 2673 CSR_WRITE_4(sc, BGE_ISO_PKT_TX, 2674 (CSR_READ_4(sc, BGE_ISO_PKT_TX) & ~3) | 2); 2675 } 2676 /* 2677 * Set the BD ring replenish thresholds. The recommended 2678 * values are 1/8th the number of descriptors allocated to 2679 * each ring. 2680 */ 2681 i = BGE_STD_RX_RING_CNT / 8; 2682 2683 /* 2684 * Use a value of 8 for the following chips to workaround HW errata. 2685 * Some of these chips have been added based on empirical 2686 * evidence (they don't work unless this is done). 2687 */ 2688 if (BGE_IS_5705_PLUS(sc)) 2689 i = 8; 2690 2691 CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, i); 2692 CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH, BGE_JUMBO_RX_RING_CNT / 8); 2693 2694 if (BGE_IS_5717_PLUS(sc)) { 2695 CSR_WRITE_4(sc, BGE_STD_REPL_LWM, 4); 2696 CSR_WRITE_4(sc, BGE_JUMBO_REPL_LWM, 4); 2697 } 2698 2699 /* 2700 * Disable all unused send rings by setting the 'ring disabled' 2701 * bit in the flags field of all the TX send ring control blocks. 2702 * These are located in NIC memory. 2703 */ 2704 rcb_addr = BGE_MEMWIN_START + BGE_SEND_RING_RCB; 2705 for (i = 0; i < BGE_TX_RINGS_EXTSSRAM_MAX; i++) { 2706 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 2707 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED)); 2708 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 0); 2709 rcb_addr += sizeof(struct bge_rcb); 2710 } 2711 2712 /* Configure TX RCB 0 (we use only the first ring) */ 2713 rcb_addr = BGE_MEMWIN_START + BGE_SEND_RING_RCB; 2714 BGE_HOSTADDR(taddr, BGE_RING_DMA_ADDR(sc, bge_tx_ring)); 2715 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi); 2716 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo); 2717 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5717 || 2718 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719 || 2719 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) 2720 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, BGE_SEND_RING_5717); 2721 else 2722 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 2723 BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT)); 2724 if (BGE_IS_5700_FAMILY(sc)) 2725 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 2726 BGE_RCB_MAXLEN_FLAGS(BGE_TX_RING_CNT, 0)); 2727 2728 /* Disable all unused RX return rings */ 2729 rcb_addr = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB; 2730 for (i = 0; i < BGE_RX_RINGS_MAX; i++) { 2731 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_hi, 0); 2732 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_lo, 0); 2733 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 2734 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 2735 BGE_RCB_FLAG_RING_DISABLED)); 2736 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 0); 2737 bge_writembx(sc, BGE_MBX_RX_CONS0_LO + 2738 (i * (sizeof(uint64_t))), 0); 2739 rcb_addr += sizeof(struct bge_rcb); 2740 } 2741 2742 /* 2743 * Set up RX return ring 0 2744 * Note that the NIC address for RX return rings is 0x00000000. 2745 * The return rings live entirely within the host, so the 2746 * nicaddr field in the RCB isn't used. 2747 */ 2748 rcb_addr = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB; 2749 BGE_HOSTADDR(taddr, BGE_RING_DMA_ADDR(sc, bge_rx_return_ring)); 2750 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi); 2751 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo); 2752 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 0x00000000); 2753 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 2754 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 0)); 2755 2756 /* Set random backoff seed for TX */ 2757 CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF, 2758 CLLADDR(ifp->if_sadl)[0] + CLLADDR(ifp->if_sadl)[1] + 2759 CLLADDR(ifp->if_sadl)[2] + CLLADDR(ifp->if_sadl)[3] + 2760 CLLADDR(ifp->if_sadl)[4] + CLLADDR(ifp->if_sadl)[5] + 2761 BGE_TX_BACKOFF_SEED_MASK); 2762 2763 /* Set inter-packet gap */ 2764 val = 0x2620; 2765 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) 2766 val |= CSR_READ_4(sc, BGE_TX_LENGTHS) & 2767 (BGE_TXLEN_JMB_FRM_LEN_MSK | BGE_TXLEN_CNT_DN_VAL_MSK); 2768 CSR_WRITE_4(sc, BGE_TX_LENGTHS, val); 2769 2770 /* 2771 * Specify which ring to use for packets that don't match 2772 * any RX rules. 2773 */ 2774 CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08); 2775 2776 /* 2777 * Configure number of RX lists. One interrupt distribution 2778 * list, sixteen active lists, one bad frames class. 2779 */ 2780 CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181); 2781 2782 /* Inialize RX list placement stats mask. */ 2783 CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF); 2784 CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1); 2785 2786 /* Disable host coalescing until we get it set up */ 2787 CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000); 2788 2789 /* Poll to make sure it's shut down. */ 2790 for (i = 0; i < BGE_TIMEOUT * 2; i++) { 2791 DELAY(10); 2792 if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE)) 2793 break; 2794 } 2795 2796 if (i == BGE_TIMEOUT * 2) { 2797 aprint_error_dev(sc->bge_dev, 2798 "host coalescing engine failed to idle\n"); 2799 return ENXIO; 2800 } 2801 2802 /* Set up host coalescing defaults */ 2803 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bge_rx_coal_ticks); 2804 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bge_tx_coal_ticks); 2805 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bge_rx_max_coal_bds); 2806 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bge_tx_max_coal_bds); 2807 if (!(BGE_IS_5705_PLUS(sc))) { 2808 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT, 0); 2809 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT, 0); 2810 } 2811 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 0); 2812 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 0); 2813 2814 /* Set up address of statistics block */ 2815 if (BGE_IS_5700_FAMILY(sc)) { 2816 BGE_HOSTADDR(taddr, BGE_RING_DMA_ADDR(sc, bge_info.bge_stats)); 2817 CSR_WRITE_4(sc, BGE_HCC_STATS_TICKS, sc->bge_stat_ticks); 2818 CSR_WRITE_4(sc, BGE_HCC_STATS_BASEADDR, BGE_STATS_BLOCK); 2819 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_HI, taddr.bge_addr_hi); 2820 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_LO, taddr.bge_addr_lo); 2821 } 2822 2823 /* Set up address of status block */ 2824 BGE_HOSTADDR(taddr, BGE_RING_DMA_ADDR(sc, bge_status_block)); 2825 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_BASEADDR, BGE_STATUS_BLOCK); 2826 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI, taddr.bge_addr_hi); 2827 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO, taddr.bge_addr_lo); 2828 sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx = 0; 2829 sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx = 0; 2830 2831 /* Set up status block size. */ 2832 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 && 2833 sc->bge_chipid != BGE_CHIPID_BCM5700_C0) { 2834 val = BGE_STATBLKSZ_FULL; 2835 bzero(&sc->bge_rdata->bge_status_block, BGE_STATUS_BLK_SZ); 2836 } else { 2837 val = BGE_STATBLKSZ_32BYTE; 2838 bzero(&sc->bge_rdata->bge_status_block, 32); 2839 } 2840 2841 /* Turn on host coalescing state machine */ 2842 CSR_WRITE_4(sc, BGE_HCC_MODE, val | BGE_HCCMODE_ENABLE); 2843 2844 /* Turn on RX BD completion state machine and enable attentions */ 2845 CSR_WRITE_4(sc, BGE_RBDC_MODE, 2846 BGE_RBDCMODE_ENABLE | BGE_RBDCMODE_ATTN); 2847 2848 /* Turn on RX list placement state machine */ 2849 CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 2850 2851 /* Turn on RX list selector state machine. */ 2852 if (!(BGE_IS_5705_PLUS(sc))) 2853 CSR_WRITE_4(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 2854 2855 val = BGE_MACMODE_TXDMA_ENB | BGE_MACMODE_RXDMA_ENB | 2856 BGE_MACMODE_RX_STATS_CLEAR | BGE_MACMODE_TX_STATS_CLEAR | 2857 BGE_MACMODE_RX_STATS_ENB | BGE_MACMODE_TX_STATS_ENB | 2858 BGE_MACMODE_FRMHDR_DMA_ENB; 2859 2860 if (sc->bge_flags & BGE_PHY_FIBER_TBI) 2861 val |= BGE_PORTMODE_TBI; 2862 else if (sc->bge_flags & BGE_PHY_FIBER_MII) 2863 val |= BGE_PORTMODE_GMII; 2864 else 2865 val |= BGE_PORTMODE_MII; 2866 2867 /* Allow APE to send/receive frames. */ 2868 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) != 0) 2869 val |= BGE_MACMODE_APE_RX_EN | BGE_MACMODE_APE_TX_EN; 2870 2871 /* Turn on DMA, clear stats */ 2872 CSR_WRITE_4_FLUSH(sc, BGE_MAC_MODE, val); 2873 DELAY(40); 2874 2875 /* Set misc. local control, enable interrupts on attentions */ 2876 sc->bge_local_ctrl_reg = BGE_MLC_INTR_ONATTN | BGE_MLC_AUTO_EEPROM; 2877 2878 #ifdef notdef 2879 /* Assert GPIO pins for PHY reset */ 2880 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUT0| 2881 BGE_MLC_MISCIO_OUT1|BGE_MLC_MISCIO_OUT2); 2882 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUTEN0| 2883 BGE_MLC_MISCIO_OUTEN1|BGE_MLC_MISCIO_OUTEN2); 2884 #endif 2885 2886 #if defined(not_quite_yet) 2887 /* Linux driver enables enable gpio pin #1 on 5700s */ 2888 if (sc->bge_chipid == BGE_CHIPID_BCM5700) { 2889 sc->bge_local_ctrl_reg |= 2890 (BGE_MLC_MISCIO_OUT1|BGE_MLC_MISCIO_OUTEN1); 2891 } 2892 #endif 2893 CSR_WRITE_4(sc, BGE_MISC_LOCAL_CTL, sc->bge_local_ctrl_reg); 2894 2895 /* Turn on DMA completion state machine */ 2896 if (!(BGE_IS_5705_PLUS(sc))) 2897 CSR_WRITE_4(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 2898 2899 val = BGE_WDMAMODE_ENABLE | BGE_WDMAMODE_ALL_ATTNS; 2900 2901 /* Enable host coalescing bug fix. */ 2902 if (BGE_IS_5755_PLUS(sc)) 2903 val |= BGE_WDMAMODE_STATUS_TAG_FIX; 2904 2905 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785) 2906 val |= BGE_WDMAMODE_BURST_ALL_DATA; 2907 2908 /* Turn on write DMA state machine */ 2909 CSR_WRITE_4_FLUSH(sc, BGE_WDMA_MODE, val); 2910 DELAY(40); 2911 2912 val = BGE_RDMAMODE_ENABLE | BGE_RDMAMODE_ALL_ATTNS; 2913 2914 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5717) 2915 val |= BGE_RDMAMODE_MULT_DMA_RD_DIS; 2916 2917 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5784 || 2918 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785 || 2919 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57780) 2920 val |= BGE_RDMAMODE_BD_SBD_CRPT_ATTN | 2921 BGE_RDMAMODE_MBUF_RBD_CRPT_ATTN | 2922 BGE_RDMAMODE_MBUF_SBD_CRPT_ATTN; 2923 2924 if (sc->bge_flags & BGE_PCIE) 2925 val |= BGE_RDMAMODE_FIFO_LONG_BURST; 2926 if (sc->bge_flags & BGE_TSO) 2927 val |= BGE_RDMAMODE_TSO4_ENABLE; 2928 2929 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) { 2930 val |= CSR_READ_4(sc, BGE_RDMA_MODE) & 2931 BGE_RDMAMODE_H2BNC_VLAN_DET; 2932 /* 2933 * Allow multiple outstanding read requests from 2934 * non-LSO read DMA engine. 2935 */ 2936 val &= ~BGE_RDMAMODE_MULT_DMA_RD_DIS; 2937 } 2938 2939 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761 || 2940 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5784 || 2941 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785 || 2942 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57780 || 2943 BGE_IS_5717_PLUS(sc)) { /* XXX 57765? */ 2944 dmactl = CSR_READ_4(sc, BGE_RDMA_RSRVCTRL); 2945 /* 2946 * Adjust tx margin to prevent TX data corruption and 2947 * fix internal FIFO overflow. 2948 */ 2949 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719 || 2950 sc->bge_chipid == BGE_CHIPID_BCM5719_A0) { 2951 dmactl &= ~(BGE_RDMA_RSRVCTRL_FIFO_LWM_MASK | 2952 BGE_RDMA_RSRVCTRL_FIFO_HWM_MASK | 2953 BGE_RDMA_RSRVCTRL_TXMRGN_MASK); 2954 dmactl |= BGE_RDMA_RSRVCTRL_FIFO_LWM_1_5K | 2955 BGE_RDMA_RSRVCTRL_FIFO_HWM_1_5K | 2956 BGE_RDMA_RSRVCTRL_TXMRGN_320B; 2957 } 2958 /* 2959 * Enable fix for read DMA FIFO overruns. 2960 * The fix is to limit the number of RX BDs 2961 * the hardware would fetch at a fime. 2962 */ 2963 CSR_WRITE_4(sc, BGE_RDMA_RSRVCTRL, dmactl | 2964 BGE_RDMA_RSRVCTRL_FIFO_OFLW_FIX); 2965 } 2966 2967 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719) { 2968 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL, 2969 CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL) | 2970 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_4K | 2971 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K); 2972 } else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) { 2973 /* 2974 * Allow 4KB burst length reads for non-LSO frames. 2975 * Enable 512B burst length reads for buffer descriptors. 2976 */ 2977 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL, 2978 CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL) | 2979 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_512 | 2980 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K); 2981 } 2982 2983 /* Turn on read DMA state machine */ 2984 CSR_WRITE_4_FLUSH(sc, BGE_RDMA_MODE, val); 2985 delay(40); 2986 2987 /* Turn on RX data completion state machine */ 2988 CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 2989 2990 /* Turn on RX BD initiator state machine */ 2991 CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 2992 2993 /* Turn on RX data and RX BD initiator state machine */ 2994 CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE); 2995 2996 /* Turn on Mbuf cluster free state machine */ 2997 if (!BGE_IS_5705_PLUS(sc)) 2998 CSR_WRITE_4(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 2999 3000 /* Turn on send BD completion state machine */ 3001 CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 3002 3003 /* Turn on send data completion state machine */ 3004 val = BGE_SDCMODE_ENABLE; 3005 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761) 3006 val |= BGE_SDCMODE_CDELAY; 3007 CSR_WRITE_4(sc, BGE_SDC_MODE, val); 3008 3009 /* Turn on send data initiator state machine */ 3010 if (sc->bge_flags & BGE_TSO) { 3011 /* XXX: magic value from Linux driver */ 3012 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE | 0x08); 3013 } else 3014 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 3015 3016 /* Turn on send BD initiator state machine */ 3017 CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 3018 3019 /* Turn on send BD selector state machine */ 3020 CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 3021 3022 CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF); 3023 CSR_WRITE_4(sc, BGE_SDI_STATS_CTL, 3024 BGE_SDISTATSCTL_ENABLE | BGE_SDISTATSCTL_FASTER); 3025 3026 /* ack/clear link change events */ 3027 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED | 3028 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE | 3029 BGE_MACSTAT_LINK_CHANGED); 3030 CSR_WRITE_4(sc, BGE_MI_STS, 0); 3031 3032 /* 3033 * Enable attention when the link has changed state for 3034 * devices that use auto polling. 3035 */ 3036 if (sc->bge_flags & BGE_PHY_FIBER_TBI) { 3037 CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK); 3038 } else { 3039 BGE_STS_SETBIT(sc, BGE_STS_AUTOPOLL); 3040 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL | (10 << 16)); 3041 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700) 3042 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, 3043 BGE_EVTENB_MI_INTERRUPT); 3044 } 3045 3046 /* 3047 * Clear any pending link state attention. 3048 * Otherwise some link state change events may be lost until attention 3049 * is cleared by bge_intr() -> bge_link_upd() sequence. 3050 * It's not necessary on newer BCM chips - perhaps enabling link 3051 * state change attentions implies clearing pending attention. 3052 */ 3053 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED | 3054 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE | 3055 BGE_MACSTAT_LINK_CHANGED); 3056 3057 /* Enable link state change attentions. */ 3058 BGE_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED); 3059 3060 return 0; 3061 } 3062 3063 static const struct bge_revision * 3064 bge_lookup_rev(uint32_t chipid) 3065 { 3066 const struct bge_revision *br; 3067 3068 for (br = bge_revisions; br->br_name != NULL; br++) { 3069 if (br->br_chipid == chipid) 3070 return br; 3071 } 3072 3073 for (br = bge_majorrevs; br->br_name != NULL; br++) { 3074 if (br->br_chipid == BGE_ASICREV(chipid)) 3075 return br; 3076 } 3077 3078 return NULL; 3079 } 3080 3081 static const struct bge_product * 3082 bge_lookup(const struct pci_attach_args *pa) 3083 { 3084 const struct bge_product *bp; 3085 3086 for (bp = bge_products; bp->bp_name != NULL; bp++) { 3087 if (PCI_VENDOR(pa->pa_id) == bp->bp_vendor && 3088 PCI_PRODUCT(pa->pa_id) == bp->bp_product) 3089 return bp; 3090 } 3091 3092 return NULL; 3093 } 3094 3095 static uint32_t 3096 bge_chipid(const struct pci_attach_args *pa) 3097 { 3098 uint32_t id; 3099 3100 id = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_MISC_CTL) 3101 >> BGE_PCIMISCCTL_ASICREV_SHIFT; 3102 3103 if (BGE_ASICREV(id) == BGE_ASICREV_USE_PRODID_REG) { 3104 switch (PCI_PRODUCT(pa->pa_id)) { 3105 case PCI_PRODUCT_BROADCOM_BCM5717: 3106 case PCI_PRODUCT_BROADCOM_BCM5718: 3107 case PCI_PRODUCT_BROADCOM_BCM5719: 3108 case PCI_PRODUCT_BROADCOM_BCM5720: 3109 case PCI_PRODUCT_BROADCOM_BCM5724: /* ??? */ 3110 id = pci_conf_read(pa->pa_pc, pa->pa_tag, 3111 BGE_PCI_GEN2_PRODID_ASICREV); 3112 break; 3113 case PCI_PRODUCT_BROADCOM_BCM57761: 3114 case PCI_PRODUCT_BROADCOM_BCM57762: 3115 case PCI_PRODUCT_BROADCOM_BCM57765: 3116 case PCI_PRODUCT_BROADCOM_BCM57766: 3117 case PCI_PRODUCT_BROADCOM_BCM57781: 3118 case PCI_PRODUCT_BROADCOM_BCM57785: 3119 case PCI_PRODUCT_BROADCOM_BCM57791: 3120 case PCI_PRODUCT_BROADCOM_BCM57795: 3121 id = pci_conf_read(pa->pa_pc, pa->pa_tag, 3122 BGE_PCI_GEN15_PRODID_ASICREV); 3123 break; 3124 default: 3125 id = pci_conf_read(pa->pa_pc, pa->pa_tag, 3126 BGE_PCI_PRODID_ASICREV); 3127 break; 3128 } 3129 } 3130 3131 return id; 3132 } 3133 3134 /* 3135 * Probe for a Broadcom chip. Check the PCI vendor and device IDs 3136 * against our list and return its name if we find a match. Note 3137 * that since the Broadcom controller contains VPD support, we 3138 * can get the device name string from the controller itself instead 3139 * of the compiled-in string. This is a little slow, but it guarantees 3140 * we'll always announce the right product name. 3141 */ 3142 static int 3143 bge_probe(device_t parent, cfdata_t match, void *aux) 3144 { 3145 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 3146 3147 if (bge_lookup(pa) != NULL) 3148 return 1; 3149 3150 return 0; 3151 } 3152 3153 static void 3154 bge_attach(device_t parent, device_t self, void *aux) 3155 { 3156 struct bge_softc *sc = device_private(self); 3157 struct pci_attach_args *pa = aux; 3158 prop_dictionary_t dict; 3159 const struct bge_product *bp; 3160 const struct bge_revision *br; 3161 pci_chipset_tag_t pc; 3162 pci_intr_handle_t ih; 3163 const char *intrstr = NULL; 3164 bus_dma_segment_t seg; 3165 int rseg; 3166 uint32_t hwcfg = 0; 3167 uint32_t command; 3168 struct ifnet *ifp; 3169 uint32_t misccfg; 3170 void * kva; 3171 u_char eaddr[ETHER_ADDR_LEN]; 3172 pcireg_t memtype, subid, reg; 3173 bus_addr_t memaddr; 3174 bus_size_t memsize, apesize; 3175 uint32_t pm_ctl; 3176 bool no_seeprom; 3177 3178 bp = bge_lookup(pa); 3179 KASSERT(bp != NULL); 3180 3181 sc->sc_pc = pa->pa_pc; 3182 sc->sc_pcitag = pa->pa_tag; 3183 sc->bge_dev = self; 3184 3185 sc->bge_pa = *pa; 3186 pc = sc->sc_pc; 3187 subid = pci_conf_read(pc, sc->sc_pcitag, PCI_SUBSYS_ID_REG); 3188 3189 aprint_naive(": Ethernet controller\n"); 3190 aprint_normal(": %s\n", bp->bp_name); 3191 3192 /* 3193 * Map control/status registers. 3194 */ 3195 DPRINTFN(5, ("Map control/status regs\n")); 3196 command = pci_conf_read(pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG); 3197 command |= PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_MASTER_ENABLE; 3198 pci_conf_write(pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG, command); 3199 command = pci_conf_read(pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG); 3200 3201 if (!(command & PCI_COMMAND_MEM_ENABLE)) { 3202 aprint_error_dev(sc->bge_dev, 3203 "failed to enable memory mapping!\n"); 3204 return; 3205 } 3206 3207 DPRINTFN(5, ("pci_mem_find\n")); 3208 memtype = pci_mapreg_type(sc->sc_pc, sc->sc_pcitag, BGE_PCI_BAR0); 3209 switch (memtype) { 3210 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 3211 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 3212 if (pci_mapreg_map(pa, BGE_PCI_BAR0, 3213 memtype, 0, &sc->bge_btag, &sc->bge_bhandle, 3214 &memaddr, &memsize) == 0) 3215 break; 3216 default: 3217 aprint_error_dev(sc->bge_dev, "can't find mem space\n"); 3218 return; 3219 } 3220 3221 DPRINTFN(5, ("pci_intr_map\n")); 3222 if (pci_intr_map(pa, &ih)) { 3223 aprint_error_dev(sc->bge_dev, "couldn't map interrupt\n"); 3224 return; 3225 } 3226 3227 DPRINTFN(5, ("pci_intr_string\n")); 3228 intrstr = pci_intr_string(pc, ih); 3229 3230 DPRINTFN(5, ("pci_intr_establish\n")); 3231 sc->bge_intrhand = pci_intr_establish(pc, ih, IPL_NET, bge_intr, sc); 3232 3233 if (sc->bge_intrhand == NULL) { 3234 aprint_error_dev(sc->bge_dev, 3235 "couldn't establish interrupt%s%s\n", 3236 intrstr ? " at " : "", intrstr ? intrstr : ""); 3237 return; 3238 } 3239 aprint_normal_dev(sc->bge_dev, "interrupting at %s\n", intrstr); 3240 3241 /* Save various chip information. */ 3242 sc->bge_chipid = bge_chipid(pa); 3243 sc->bge_phy_addr = bge_phy_addr(sc); 3244 3245 if ((pci_get_capability(sc->sc_pc, sc->sc_pcitag, PCI_CAP_PCIEXPRESS, 3246 &sc->bge_pciecap, NULL) != 0) 3247 || (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785)) { 3248 /* PCIe */ 3249 sc->bge_flags |= BGE_PCIE; 3250 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719 || 3251 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) 3252 sc->bge_expmrq = 2048; 3253 else 3254 sc->bge_expmrq = 4096; 3255 bge_set_max_readrq(sc); 3256 } else if ((pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_PCISTATE) & 3257 BGE_PCISTATE_PCI_BUSMODE) == 0) { 3258 /* PCI-X */ 3259 sc->bge_flags |= BGE_PCIX; 3260 if (pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_PCIX, 3261 &sc->bge_pcixcap, NULL) == 0) 3262 aprint_error_dev(sc->bge_dev, 3263 "unable to find PCIX capability\n"); 3264 } 3265 3266 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX) { 3267 /* 3268 * Kludge for 5700 Bx bug: a hardware bug (PCIX byte enable?) 3269 * can clobber the chip's PCI config-space power control 3270 * registers, leaving the card in D3 powersave state. We do 3271 * not have memory-mapped registers in this state, so force 3272 * device into D0 state before starting initialization. 3273 */ 3274 pm_ctl = pci_conf_read(pc, sc->sc_pcitag, BGE_PCI_PWRMGMT_CMD); 3275 pm_ctl &= ~(PCI_PWR_D0|PCI_PWR_D1|PCI_PWR_D2|PCI_PWR_D3); 3276 pm_ctl |= (1 << 8) | PCI_PWR_D0 ; /* D0 state */ 3277 pci_conf_write(pc, sc->sc_pcitag, BGE_PCI_PWRMGMT_CMD, pm_ctl); 3278 DELAY(1000); /* 27 usec is allegedly sufficent */ 3279 } 3280 3281 /* Save chipset family. */ 3282 switch (BGE_ASICREV(sc->bge_chipid)) { 3283 case BGE_ASICREV_BCM57765: 3284 case BGE_ASICREV_BCM57766: 3285 sc->bge_flags |= BGE_57765_PLUS; 3286 /* FALLTHROUGH */ 3287 case BGE_ASICREV_BCM5717: 3288 case BGE_ASICREV_BCM5719: 3289 case BGE_ASICREV_BCM5720: 3290 sc->bge_flags |= BGE_5717_PLUS | BGE_5755_PLUS | BGE_575X_PLUS | 3291 BGE_5705_PLUS; 3292 break; 3293 case BGE_ASICREV_BCM5755: 3294 case BGE_ASICREV_BCM5761: 3295 case BGE_ASICREV_BCM5784: 3296 case BGE_ASICREV_BCM5785: 3297 case BGE_ASICREV_BCM5787: 3298 case BGE_ASICREV_BCM57780: 3299 sc->bge_flags |= BGE_5755_PLUS | BGE_575X_PLUS | BGE_5705_PLUS; 3300 break; 3301 case BGE_ASICREV_BCM5700: 3302 case BGE_ASICREV_BCM5701: 3303 case BGE_ASICREV_BCM5703: 3304 case BGE_ASICREV_BCM5704: 3305 sc->bge_flags |= BGE_5700_FAMILY | BGE_JUMBO_CAPABLE; 3306 break; 3307 case BGE_ASICREV_BCM5714_A0: 3308 case BGE_ASICREV_BCM5780: 3309 case BGE_ASICREV_BCM5714: 3310 sc->bge_flags |= BGE_5714_FAMILY; 3311 /* FALLTHROUGH */ 3312 case BGE_ASICREV_BCM5750: 3313 case BGE_ASICREV_BCM5752: 3314 case BGE_ASICREV_BCM5906: 3315 sc->bge_flags |= BGE_575X_PLUS; 3316 /* FALLTHROUGH */ 3317 case BGE_ASICREV_BCM5705: 3318 sc->bge_flags |= BGE_5705_PLUS; 3319 break; 3320 } 3321 3322 /* Identify chips with APE processor. */ 3323 switch (BGE_ASICREV(sc->bge_chipid)) { 3324 case BGE_ASICREV_BCM5717: 3325 case BGE_ASICREV_BCM5719: 3326 case BGE_ASICREV_BCM5720: 3327 case BGE_ASICREV_BCM5761: 3328 sc->bge_flags |= BGE_APE; 3329 break; 3330 } 3331 3332 /* Chips with APE need BAR2 access for APE registers/memory. */ 3333 if ((sc->bge_flags & BGE_APE) != 0) { 3334 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, BGE_PCI_BAR2); 3335 if (pci_mapreg_map(pa, BGE_PCI_BAR2, memtype, 0, 3336 &sc->bge_apetag, &sc->bge_apehandle, NULL, &apesize)) { 3337 aprint_error_dev(sc->bge_dev, 3338 "couldn't map BAR2 memory\n"); 3339 return; 3340 } 3341 3342 /* Enable APE register/memory access by host driver. */ 3343 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_PCISTATE); 3344 reg |= BGE_PCISTATE_ALLOW_APE_CTLSPC_WR | 3345 BGE_PCISTATE_ALLOW_APE_SHMEM_WR | 3346 BGE_PCISTATE_ALLOW_APE_PSPACE_WR; 3347 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_PCISTATE, reg); 3348 3349 bge_ape_lock_init(sc); 3350 bge_ape_read_fw_ver(sc); 3351 } 3352 3353 /* Identify the chips that use an CPMU. */ 3354 if (BGE_IS_5717_PLUS(sc) || 3355 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5784 || 3356 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761 || 3357 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785 || 3358 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57780) 3359 sc->bge_flags |= BGE_CPMU_PRESENT; 3360 3361 if ((sc->bge_flags & BGE_CPMU_PRESENT) != 0) 3362 CSR_WRITE_4(sc, BGE_MI_MODE, BGE_MIMODE_500KHZ_CONST); 3363 else 3364 CSR_WRITE_4(sc, BGE_MI_MODE, BGE_MIMODE_BASE); 3365 3366 /* 3367 * When using the BCM5701 in PCI-X mode, data corruption has 3368 * been observed in the first few bytes of some received packets. 3369 * Aligning the packet buffer in memory eliminates the corruption. 3370 * Unfortunately, this misaligns the packet payloads. On platforms 3371 * which do not support unaligned accesses, we will realign the 3372 * payloads by copying the received packets. 3373 */ 3374 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5701 && 3375 sc->bge_flags & BGE_PCIX) 3376 sc->bge_flags |= BGE_RX_ALIGNBUG; 3377 3378 if (BGE_IS_5700_FAMILY(sc)) 3379 sc->bge_flags |= BGE_JUMBO_CAPABLE; 3380 3381 if ((BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 3382 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5701) && 3383 PCI_VENDOR(subid) == PCI_VENDOR_DELL) 3384 sc->bge_flags |= BGE_NO_3LED; 3385 3386 misccfg = CSR_READ_4(sc, BGE_MISC_CFG); 3387 misccfg &= BGE_MISCCFG_BOARD_ID_MASK; 3388 3389 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5705 && 3390 (misccfg == BGE_MISCCFG_BOARD_ID_5788 || 3391 misccfg == BGE_MISCCFG_BOARD_ID_5788M)) 3392 sc->bge_flags |= BGE_IS_5788; 3393 3394 /* 3395 * Some controllers seem to require a special firmware to use 3396 * TSO. But the firmware is not available to FreeBSD and Linux 3397 * claims that the TSO performed by the firmware is slower than 3398 * hardware based TSO. Moreover the firmware based TSO has one 3399 * known bug which can't handle TSO if ethernet header + IP/TCP 3400 * header is greater than 80 bytes. The workaround for the TSO 3401 * bug exist but it seems it's too expensive than not using 3402 * TSO at all. Some hardwares also have the TSO bug so limit 3403 * the TSO to the controllers that are not affected TSO issues 3404 * (e.g. 5755 or higher). 3405 */ 3406 if (BGE_IS_5755_PLUS(sc)) { 3407 /* 3408 * BCM5754 and BCM5787 shares the same ASIC id so 3409 * explicit device id check is required. 3410 */ 3411 if ((PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_BROADCOM_BCM5754) && 3412 (PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_BROADCOM_BCM5754M)) 3413 sc->bge_flags |= BGE_TSO; 3414 } 3415 3416 if ((BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5703 && 3417 (misccfg == 0x4000 || misccfg == 0x8000)) || 3418 (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5705 && 3419 PCI_VENDOR(pa->pa_id) == PCI_VENDOR_BROADCOM && 3420 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5901 || 3421 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5901A2 || 3422 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5705F)) || 3423 (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_BROADCOM && 3424 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5751F || 3425 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5753F || 3426 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5787F)) || 3427 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM57790 || 3428 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM57791 || 3429 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM57795 || 3430 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 3431 sc->bge_flags |= BGE_10_100_ONLY; 3432 3433 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 3434 (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5705 && 3435 (sc->bge_chipid != BGE_CHIPID_BCM5705_A0 && 3436 sc->bge_chipid != BGE_CHIPID_BCM5705_A1)) || 3437 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 3438 sc->bge_flags |= BGE_NO_ETH_WIRE_SPEED; 3439 3440 if (sc->bge_chipid == BGE_CHIPID_BCM5701_A0 || 3441 sc->bge_chipid == BGE_CHIPID_BCM5701_B0) 3442 sc->bge_flags |= BGE_PHY_CRC_BUG; 3443 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5703_AX || 3444 BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5704_AX) 3445 sc->bge_flags |= BGE_PHY_ADC_BUG; 3446 if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0) 3447 sc->bge_flags |= BGE_PHY_5704_A0_BUG; 3448 3449 if (BGE_IS_5705_PLUS(sc) && 3450 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5906 && 3451 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5785 && 3452 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM57780 && 3453 !BGE_IS_5717_PLUS(sc)) { 3454 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5755 || 3455 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761 || 3456 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5784 || 3457 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5787) { 3458 if (PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_BROADCOM_BCM5722 && 3459 PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_BROADCOM_BCM5756) 3460 sc->bge_flags |= BGE_PHY_JITTER_BUG; 3461 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5755M) 3462 sc->bge_flags |= BGE_PHY_ADJUST_TRIM; 3463 } else 3464 sc->bge_flags |= BGE_PHY_BER_BUG; 3465 } 3466 3467 /* 3468 * SEEPROM check. 3469 * First check if firmware knows we do not have SEEPROM. 3470 */ 3471 if (prop_dictionary_get_bool(device_properties(self), 3472 "without-seeprom", &no_seeprom) && no_seeprom) 3473 sc->bge_flags |= BGE_NO_EEPROM; 3474 3475 /* Now check the 'ROM failed' bit on the RX CPU */ 3476 else if (CSR_READ_4(sc, BGE_RXCPU_MODE) & BGE_RXCPUMODE_ROMFAIL) 3477 sc->bge_flags |= BGE_NO_EEPROM; 3478 3479 sc->bge_asf_mode = 0; 3480 /* No ASF if APE present. */ 3481 if ((sc->bge_flags & BGE_APE) == 0) { 3482 if (bge_allow_asf && (bge_readmem_ind(sc, BGE_SRAM_DATA_SIG) == 3483 BGE_SRAM_DATA_SIG_MAGIC)) { 3484 if (bge_readmem_ind(sc, BGE_SRAM_DATA_CFG) & 3485 BGE_HWCFG_ASF) { 3486 sc->bge_asf_mode |= ASF_ENABLE; 3487 sc->bge_asf_mode |= ASF_STACKUP; 3488 if (BGE_IS_575X_PLUS(sc)) 3489 sc->bge_asf_mode |= ASF_NEW_HANDSHAKE; 3490 } 3491 } 3492 } 3493 3494 bge_stop_fw(sc); 3495 bge_sig_pre_reset(sc, BGE_RESET_START); 3496 if (bge_reset(sc)) 3497 aprint_error_dev(sc->bge_dev, "chip reset failed\n"); 3498 3499 bge_sig_legacy(sc, BGE_RESET_START); 3500 bge_sig_post_reset(sc, BGE_RESET_START); 3501 3502 if (bge_chipinit(sc)) { 3503 aprint_error_dev(sc->bge_dev, "chip initialization failed\n"); 3504 bge_release_resources(sc); 3505 return; 3506 } 3507 3508 /* 3509 * Get station address from the EEPROM. 3510 */ 3511 if (bge_get_eaddr(sc, eaddr)) { 3512 aprint_error_dev(sc->bge_dev, 3513 "failed to read station address\n"); 3514 bge_release_resources(sc); 3515 return; 3516 } 3517 3518 br = bge_lookup_rev(sc->bge_chipid); 3519 3520 if (br == NULL) { 3521 aprint_normal_dev(sc->bge_dev, "unknown ASIC (0x%x)", 3522 sc->bge_chipid); 3523 } else { 3524 aprint_normal_dev(sc->bge_dev, "ASIC %s (0x%x)", 3525 br->br_name, sc->bge_chipid); 3526 } 3527 aprint_normal(", Ethernet address %s\n", ether_sprintf(eaddr)); 3528 3529 /* Allocate the general information block and ring buffers. */ 3530 if (pci_dma64_available(pa)) 3531 sc->bge_dmatag = pa->pa_dmat64; 3532 else 3533 sc->bge_dmatag = pa->pa_dmat; 3534 DPRINTFN(5, ("bus_dmamem_alloc\n")); 3535 if (bus_dmamem_alloc(sc->bge_dmatag, sizeof(struct bge_ring_data), 3536 PAGE_SIZE, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 3537 aprint_error_dev(sc->bge_dev, "can't alloc rx buffers\n"); 3538 return; 3539 } 3540 DPRINTFN(5, ("bus_dmamem_map\n")); 3541 if (bus_dmamem_map(sc->bge_dmatag, &seg, rseg, 3542 sizeof(struct bge_ring_data), &kva, 3543 BUS_DMA_NOWAIT)) { 3544 aprint_error_dev(sc->bge_dev, 3545 "can't map DMA buffers (%zu bytes)\n", 3546 sizeof(struct bge_ring_data)); 3547 bus_dmamem_free(sc->bge_dmatag, &seg, rseg); 3548 return; 3549 } 3550 DPRINTFN(5, ("bus_dmamem_create\n")); 3551 if (bus_dmamap_create(sc->bge_dmatag, sizeof(struct bge_ring_data), 1, 3552 sizeof(struct bge_ring_data), 0, 3553 BUS_DMA_NOWAIT, &sc->bge_ring_map)) { 3554 aprint_error_dev(sc->bge_dev, "can't create DMA map\n"); 3555 bus_dmamem_unmap(sc->bge_dmatag, kva, 3556 sizeof(struct bge_ring_data)); 3557 bus_dmamem_free(sc->bge_dmatag, &seg, rseg); 3558 return; 3559 } 3560 DPRINTFN(5, ("bus_dmamem_load\n")); 3561 if (bus_dmamap_load(sc->bge_dmatag, sc->bge_ring_map, kva, 3562 sizeof(struct bge_ring_data), NULL, 3563 BUS_DMA_NOWAIT)) { 3564 bus_dmamap_destroy(sc->bge_dmatag, sc->bge_ring_map); 3565 bus_dmamem_unmap(sc->bge_dmatag, kva, 3566 sizeof(struct bge_ring_data)); 3567 bus_dmamem_free(sc->bge_dmatag, &seg, rseg); 3568 return; 3569 } 3570 3571 DPRINTFN(5, ("bzero\n")); 3572 sc->bge_rdata = (struct bge_ring_data *)kva; 3573 3574 memset(sc->bge_rdata, 0, sizeof(struct bge_ring_data)); 3575 3576 /* Try to allocate memory for jumbo buffers. */ 3577 if (BGE_IS_JUMBO_CAPABLE(sc)) { 3578 if (bge_alloc_jumbo_mem(sc)) { 3579 aprint_error_dev(sc->bge_dev, 3580 "jumbo buffer allocation failed\n"); 3581 } else 3582 sc->ethercom.ec_capabilities |= ETHERCAP_JUMBO_MTU; 3583 } 3584 3585 /* Set default tuneable values. */ 3586 sc->bge_stat_ticks = BGE_TICKS_PER_SEC; 3587 sc->bge_rx_coal_ticks = 150; 3588 sc->bge_rx_max_coal_bds = 64; 3589 #ifdef ORIG_WPAUL_VALUES 3590 sc->bge_tx_coal_ticks = 150; 3591 sc->bge_tx_max_coal_bds = 128; 3592 #else 3593 sc->bge_tx_coal_ticks = 300; 3594 sc->bge_tx_max_coal_bds = 400; 3595 #endif 3596 if (BGE_IS_5705_PLUS(sc)) { 3597 sc->bge_tx_coal_ticks = (12 * 5); 3598 sc->bge_tx_max_coal_bds = (12 * 5); 3599 aprint_verbose_dev(sc->bge_dev, 3600 "setting short Tx thresholds\n"); 3601 } 3602 3603 if (BGE_IS_5717_PLUS(sc)) 3604 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT; 3605 else if (BGE_IS_5705_PLUS(sc)) 3606 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT_5705; 3607 else 3608 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT; 3609 3610 /* Set up ifnet structure */ 3611 ifp = &sc->ethercom.ec_if; 3612 ifp->if_softc = sc; 3613 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 3614 ifp->if_ioctl = bge_ioctl; 3615 ifp->if_stop = bge_stop; 3616 ifp->if_start = bge_start; 3617 ifp->if_init = bge_init; 3618 ifp->if_watchdog = bge_watchdog; 3619 IFQ_SET_MAXLEN(&ifp->if_snd, max(BGE_TX_RING_CNT - 1, IFQ_MAXLEN)); 3620 IFQ_SET_READY(&ifp->if_snd); 3621 DPRINTFN(5, ("strcpy if_xname\n")); 3622 strcpy(ifp->if_xname, device_xname(sc->bge_dev)); 3623 3624 if (sc->bge_chipid != BGE_CHIPID_BCM5700_B0) 3625 sc->ethercom.ec_if.if_capabilities |= 3626 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx; 3627 #if 1 /* XXX TCP/UDP checksum offload breaks with pf(4) */ 3628 sc->ethercom.ec_if.if_capabilities |= 3629 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 3630 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 3631 #endif 3632 sc->ethercom.ec_capabilities |= 3633 ETHERCAP_VLAN_HWTAGGING | ETHERCAP_VLAN_MTU; 3634 3635 if (sc->bge_flags & BGE_TSO) 3636 sc->ethercom.ec_if.if_capabilities |= IFCAP_TSOv4; 3637 3638 /* 3639 * Do MII setup. 3640 */ 3641 DPRINTFN(5, ("mii setup\n")); 3642 sc->bge_mii.mii_ifp = ifp; 3643 sc->bge_mii.mii_readreg = bge_miibus_readreg; 3644 sc->bge_mii.mii_writereg = bge_miibus_writereg; 3645 sc->bge_mii.mii_statchg = bge_miibus_statchg; 3646 3647 /* 3648 * Figure out what sort of media we have by checking the hardware 3649 * config word in the first 32k of NIC internal memory, or fall back to 3650 * the config word in the EEPROM. Note: on some BCM5700 cards, 3651 * this value appears to be unset. If that's the case, we have to rely 3652 * on identifying the NIC by its PCI subsystem ID, as we do below for 3653 * the SysKonnect SK-9D41. 3654 */ 3655 if (bge_readmem_ind(sc, BGE_SRAM_DATA_SIG) == BGE_SRAM_DATA_SIG_MAGIC) { 3656 hwcfg = bge_readmem_ind(sc, BGE_SRAM_DATA_CFG); 3657 } else if (!(sc->bge_flags & BGE_NO_EEPROM)) { 3658 bge_read_eeprom(sc, (void *)&hwcfg, 3659 BGE_EE_HWCFG_OFFSET, sizeof(hwcfg)); 3660 hwcfg = be32toh(hwcfg); 3661 } 3662 /* The SysKonnect SK-9D41 is a 1000baseSX card. */ 3663 if (PCI_PRODUCT(pa->pa_id) == SK_SUBSYSID_9D41 || 3664 (hwcfg & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER) { 3665 if (BGE_IS_5714_FAMILY(sc)) 3666 sc->bge_flags |= BGE_PHY_FIBER_MII; 3667 else 3668 sc->bge_flags |= BGE_PHY_FIBER_TBI; 3669 } 3670 3671 /* set phyflags and chipid before mii_attach() */ 3672 dict = device_properties(self); 3673 prop_dictionary_set_uint32(dict, "phyflags", sc->bge_flags); 3674 prop_dictionary_set_uint32(dict, "chipid", sc->bge_chipid); 3675 3676 if (sc->bge_flags & BGE_PHY_FIBER_TBI) { 3677 ifmedia_init(&sc->bge_ifmedia, IFM_IMASK, bge_ifmedia_upd, 3678 bge_ifmedia_sts); 3679 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER |IFM_1000_SX, 0, NULL); 3680 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_1000_SX|IFM_FDX, 3681 0, NULL); 3682 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_AUTO, 0, NULL); 3683 ifmedia_set(&sc->bge_ifmedia, IFM_ETHER | IFM_AUTO); 3684 /* Pretend the user requested this setting */ 3685 sc->bge_ifmedia.ifm_media = sc->bge_ifmedia.ifm_cur->ifm_media; 3686 } else { 3687 /* 3688 * Do transceiver setup and tell the firmware the 3689 * driver is down so we can try to get access the 3690 * probe if ASF is running. Retry a couple of times 3691 * if we get a conflict with the ASF firmware accessing 3692 * the PHY. 3693 */ 3694 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 3695 bge_asf_driver_up(sc); 3696 3697 ifmedia_init(&sc->bge_mii.mii_media, 0, bge_ifmedia_upd, 3698 bge_ifmedia_sts); 3699 mii_attach(sc->bge_dev, &sc->bge_mii, 0xffffffff, 3700 sc->bge_phy_addr, MII_OFFSET_ANY, 3701 MIIF_DOPAUSE); 3702 3703 if (LIST_EMPTY(&sc->bge_mii.mii_phys)) { 3704 aprint_error_dev(sc->bge_dev, "no PHY found!\n"); 3705 ifmedia_add(&sc->bge_mii.mii_media, 3706 IFM_ETHER|IFM_MANUAL, 0, NULL); 3707 ifmedia_set(&sc->bge_mii.mii_media, 3708 IFM_ETHER|IFM_MANUAL); 3709 } else 3710 ifmedia_set(&sc->bge_mii.mii_media, 3711 IFM_ETHER|IFM_AUTO); 3712 3713 /* 3714 * Now tell the firmware we are going up after probing the PHY 3715 */ 3716 if (sc->bge_asf_mode & ASF_STACKUP) 3717 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 3718 } 3719 3720 /* 3721 * Call MI attach routine. 3722 */ 3723 DPRINTFN(5, ("if_attach\n")); 3724 if_attach(ifp); 3725 DPRINTFN(5, ("ether_ifattach\n")); 3726 ether_ifattach(ifp, eaddr); 3727 ether_set_ifflags_cb(&sc->ethercom, bge_ifflags_cb); 3728 rnd_attach_source(&sc->rnd_source, device_xname(sc->bge_dev), 3729 RND_TYPE_NET, 0); 3730 #ifdef BGE_EVENT_COUNTERS 3731 /* 3732 * Attach event counters. 3733 */ 3734 evcnt_attach_dynamic(&sc->bge_ev_intr, EVCNT_TYPE_INTR, 3735 NULL, device_xname(sc->bge_dev), "intr"); 3736 evcnt_attach_dynamic(&sc->bge_ev_tx_xoff, EVCNT_TYPE_MISC, 3737 NULL, device_xname(sc->bge_dev), "tx_xoff"); 3738 evcnt_attach_dynamic(&sc->bge_ev_tx_xon, EVCNT_TYPE_MISC, 3739 NULL, device_xname(sc->bge_dev), "tx_xon"); 3740 evcnt_attach_dynamic(&sc->bge_ev_rx_xoff, EVCNT_TYPE_MISC, 3741 NULL, device_xname(sc->bge_dev), "rx_xoff"); 3742 evcnt_attach_dynamic(&sc->bge_ev_rx_xon, EVCNT_TYPE_MISC, 3743 NULL, device_xname(sc->bge_dev), "rx_xon"); 3744 evcnt_attach_dynamic(&sc->bge_ev_rx_macctl, EVCNT_TYPE_MISC, 3745 NULL, device_xname(sc->bge_dev), "rx_macctl"); 3746 evcnt_attach_dynamic(&sc->bge_ev_xoffentered, EVCNT_TYPE_MISC, 3747 NULL, device_xname(sc->bge_dev), "xoffentered"); 3748 #endif /* BGE_EVENT_COUNTERS */ 3749 DPRINTFN(5, ("callout_init\n")); 3750 callout_init(&sc->bge_timeout, 0); 3751 3752 if (pmf_device_register(self, NULL, NULL)) 3753 pmf_class_network_register(self, ifp); 3754 else 3755 aprint_error_dev(self, "couldn't establish power handler\n"); 3756 3757 bge_sysctl_init(sc); 3758 3759 #ifdef BGE_DEBUG 3760 bge_debug_info(sc); 3761 #endif 3762 } 3763 3764 static void 3765 bge_release_resources(struct bge_softc *sc) 3766 { 3767 if (sc->bge_vpd_prodname != NULL) 3768 free(sc->bge_vpd_prodname, M_DEVBUF); 3769 3770 if (sc->bge_vpd_readonly != NULL) 3771 free(sc->bge_vpd_readonly, M_DEVBUF); 3772 } 3773 3774 static int 3775 bge_reset(struct bge_softc *sc) 3776 { 3777 uint32_t cachesize, command; 3778 uint32_t reset, mac_mode, mac_mode_mask; 3779 pcireg_t devctl, reg; 3780 int i, val; 3781 void (*write_op)(struct bge_softc *, int, int); 3782 3783 mac_mode_mask = BGE_MACMODE_HALF_DUPLEX | BGE_MACMODE_PORTMODE; 3784 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) != 0) 3785 mac_mode_mask |= BGE_MACMODE_APE_RX_EN | BGE_MACMODE_APE_TX_EN; 3786 mac_mode = CSR_READ_4(sc, BGE_MAC_MODE) & mac_mode_mask; 3787 3788 if (BGE_IS_575X_PLUS(sc) && !BGE_IS_5714_FAMILY(sc) && 3789 (BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5906)) { 3790 if (sc->bge_flags & BGE_PCIE) 3791 write_op = bge_writemem_direct; 3792 else 3793 write_op = bge_writemem_ind; 3794 } else 3795 write_op = bge_writereg_ind; 3796 3797 if (BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5700 && 3798 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5701) { 3799 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_SET1); 3800 for (i = 0; i < 8000; i++) { 3801 if (CSR_READ_4(sc, BGE_NVRAM_SWARB) & 3802 BGE_NVRAMSWARB_GNT1) 3803 break; 3804 DELAY(20); 3805 } 3806 if (i == 8000) { 3807 printf("%s: NVRAM lock timedout!\n", 3808 device_xname(sc->bge_dev)); 3809 } 3810 } 3811 /* Take APE lock when performing reset. */ 3812 bge_ape_lock(sc, BGE_APE_LOCK_GRC); 3813 3814 /* Save some important PCI state. */ 3815 cachesize = pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CACHESZ); 3816 command = pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CMD); 3817 3818 /* Step 5b-5d: */ 3819 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MISC_CTL, 3820 BGE_PCIMISCCTL_INDIRECT_ACCESS | BGE_PCIMISCCTL_MASK_PCI_INTR | 3821 BGE_HIF_SWAP_OPTIONS | BGE_PCIMISCCTL_PCISTATE_RW); 3822 3823 /* XXX ???: Disable fastboot on controllers that support it. */ 3824 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5752 || 3825 BGE_IS_5755_PLUS(sc)) 3826 CSR_WRITE_4(sc, BGE_FASTBOOT_PC, 0); 3827 3828 /* 3829 * Step 6: Write the magic number to SRAM at offset 0xB50. 3830 * When firmware finishes its initialization it will 3831 * write ~BGE_MAGIC_NUMBER to the same location. 3832 */ 3833 bge_writemem_ind(sc, BGE_SRAM_FW_MB, BGE_SRAM_FW_MB_MAGIC); 3834 3835 /* Step 7: */ 3836 reset = BGE_MISCCFG_RESET_CORE_CLOCKS | BGE_32BITTIME_66MHZ; 3837 /* 3838 * XXX: from FreeBSD/Linux; no documentation 3839 */ 3840 if (sc->bge_flags & BGE_PCIE) { 3841 if (BGE_ASICREV(sc->bge_chipid != BGE_ASICREV_BCM5785) && 3842 !BGE_IS_57765_PLUS(sc) && 3843 (CSR_READ_4(sc, BGE_PHY_TEST_CTRL_REG) == 3844 (BGE_PHY_PCIE_LTASS_MODE | BGE_PHY_PCIE_SCRAM_MODE))) { 3845 /* PCI Express 1.0 system */ 3846 CSR_WRITE_4(sc, BGE_PHY_TEST_CTRL_REG, 3847 BGE_PHY_PCIE_SCRAM_MODE); 3848 } 3849 if (sc->bge_chipid != BGE_CHIPID_BCM5750_A0) { 3850 /* 3851 * Prevent PCI Express link training 3852 * during global reset. 3853 */ 3854 CSR_WRITE_4(sc, BGE_MISC_CFG, 1 << 29); 3855 reset |= (1<<29); 3856 } 3857 } 3858 3859 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 3860 i = CSR_READ_4(sc, BGE_VCPU_STATUS); 3861 CSR_WRITE_4(sc, BGE_VCPU_STATUS, 3862 i | BGE_VCPU_STATUS_DRV_RESET); 3863 i = CSR_READ_4(sc, BGE_VCPU_EXT_CTRL); 3864 CSR_WRITE_4(sc, BGE_VCPU_EXT_CTRL, 3865 i & ~BGE_VCPU_EXT_CTRL_HALT_CPU); 3866 } 3867 3868 /* 3869 * Set GPHY Power Down Override to leave GPHY 3870 * powered up in D0 uninitialized. 3871 */ 3872 if (BGE_IS_5705_PLUS(sc) && 3873 (sc->bge_flags & BGE_CPMU_PRESENT) == 0) 3874 reset |= BGE_MISCCFG_GPHY_PD_OVERRIDE; 3875 3876 /* XXX 5721, 5751 and 5752 */ 3877 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5750) 3878 reset |= BGE_MISCCFG_GRC_RESET_DISABLE; 3879 3880 /* Issue global reset */ 3881 write_op(sc, BGE_MISC_CFG, reset); 3882 3883 /* Step 8: wait for complete */ 3884 if (sc->bge_flags & BGE_PCIE) 3885 delay(100*1000); /* too big */ 3886 else 3887 delay(1000); 3888 3889 if (sc->bge_flags & BGE_PCIE) { 3890 if (sc->bge_chipid == BGE_CHIPID_BCM5750_A0) { 3891 DELAY(500000); 3892 /* XXX: Magic Numbers */ 3893 reg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 3894 BGE_PCI_UNKNOWN0); 3895 pci_conf_write(sc->sc_pc, sc->sc_pcitag, 3896 BGE_PCI_UNKNOWN0, 3897 reg | (1 << 15)); 3898 } 3899 devctl = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 3900 sc->bge_pciecap + PCI_PCIE_DCSR); 3901 /* Clear enable no snoop and disable relaxed ordering. */ 3902 devctl &= ~(PCI_PCIE_DCSR_ENA_RELAX_ORD | 3903 PCI_PCIE_DCSR_ENA_NO_SNOOP); 3904 3905 /* Set PCIE max payload size to 128 for older PCIe devices */ 3906 if ((sc->bge_flags & BGE_CPMU_PRESENT) == 0) 3907 devctl &= ~(0x00e0); 3908 /* Clear device status register. Write 1b to clear */ 3909 devctl |= PCI_PCIE_DCSR_URD | PCI_PCIE_DCSR_FED 3910 | PCI_PCIE_DCSR_NFED | PCI_PCIE_DCSR_CED; 3911 pci_conf_write(sc->sc_pc, sc->sc_pcitag, 3912 sc->bge_pciecap + PCI_PCIE_DCSR, devctl); 3913 bge_set_max_readrq(sc); 3914 } 3915 3916 /* From Linux: dummy read to flush PCI posted writes */ 3917 reg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CMD); 3918 3919 /* Step 9-10: Reset some of the PCI state that got zapped by reset */ 3920 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MISC_CTL, 3921 BGE_PCIMISCCTL_INDIRECT_ACCESS | BGE_PCIMISCCTL_MASK_PCI_INTR | 3922 BGE_HIF_SWAP_OPTIONS | BGE_PCIMISCCTL_PCISTATE_RW); 3923 val = BGE_PCISTATE_ROM_ENABLE | BGE_PCISTATE_ROM_RETRY_ENABLE; 3924 if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0 && 3925 (sc->bge_flags & BGE_PCIX) != 0) 3926 val |= BGE_PCISTATE_RETRY_SAME_DMA; 3927 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) != 0) 3928 val |= BGE_PCISTATE_ALLOW_APE_CTLSPC_WR | 3929 BGE_PCISTATE_ALLOW_APE_SHMEM_WR | 3930 BGE_PCISTATE_ALLOW_APE_PSPACE_WR; 3931 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_PCISTATE, val); 3932 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CACHESZ, cachesize); 3933 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CMD, command); 3934 3935 /* Step 11: disable PCI-X Relaxed Ordering. */ 3936 if (sc->bge_flags & BGE_PCIX) { 3937 reg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, sc->bge_pcixcap 3938 + PCI_PCIX_CMD); 3939 pci_conf_write(sc->sc_pc, sc->sc_pcitag, sc->bge_pcixcap 3940 + PCI_PCIX_CMD, reg & ~PCI_PCIX_CMD_RELAXED_ORDER); 3941 } 3942 3943 /* Step 12: Enable memory arbiter. */ 3944 if (BGE_IS_5714_FAMILY(sc)) { 3945 val = CSR_READ_4(sc, BGE_MARB_MODE); 3946 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE | val); 3947 } else 3948 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 3949 3950 /* XXX 5721, 5751 and 5752 */ 3951 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5750) { 3952 /* Step 19: */ 3953 BGE_SETBIT(sc, BGE_TLP_CONTROL_REG, 1 << 29 | 1 << 25); 3954 /* Step 20: */ 3955 BGE_SETBIT(sc, BGE_TLP_CONTROL_REG, BGE_TLP_DATA_FIFO_PROTECT); 3956 } 3957 3958 /* Step 28: Fix up byte swapping */ 3959 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS); 3960 3961 /* Step 21: 5822 B0 errata */ 3962 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5704_BX) { 3963 pcireg_t msidata; 3964 3965 msidata = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 3966 BGE_PCI_MSI_DATA); 3967 msidata |= ((1 << 13 | 1 << 12 | 1 << 10) << 16); 3968 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MSI_DATA, 3969 msidata); 3970 } 3971 3972 /* 3973 * Step 18: wirte mac mode 3974 * XXX Write 0x0c for 5703S and 5704S 3975 */ 3976 val = CSR_READ_4(sc, BGE_MAC_MODE); 3977 val = (val & ~mac_mode_mask) | mac_mode; 3978 CSR_WRITE_4_FLUSH(sc, BGE_MAC_MODE, val); 3979 DELAY(40); 3980 3981 bge_ape_unlock(sc, BGE_APE_LOCK_GRC); 3982 3983 /* Step 17: Poll until the firmware initialization is complete */ 3984 bge_poll_fw(sc); 3985 3986 /* 3987 * The 5704 in TBI mode apparently needs some special 3988 * adjustment to insure the SERDES drive level is set 3989 * to 1.2V. 3990 */ 3991 if (sc->bge_flags & BGE_PHY_FIBER_TBI && 3992 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) { 3993 uint32_t serdescfg; 3994 3995 serdescfg = CSR_READ_4(sc, BGE_SERDES_CFG); 3996 serdescfg = (serdescfg & ~0xFFF) | 0x880; 3997 CSR_WRITE_4(sc, BGE_SERDES_CFG, serdescfg); 3998 } 3999 4000 if (sc->bge_flags & BGE_PCIE && 4001 !BGE_IS_57765_PLUS(sc) && 4002 sc->bge_chipid != BGE_CHIPID_BCM5750_A0 && 4003 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5785) { 4004 uint32_t v; 4005 4006 /* Enable PCI Express bug fix */ 4007 v = CSR_READ_4(sc, BGE_TLP_CONTROL_REG); 4008 CSR_WRITE_4(sc, BGE_TLP_CONTROL_REG, 4009 v | BGE_TLP_DATA_FIFO_PROTECT); 4010 } 4011 4012 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) 4013 BGE_CLRBIT(sc, BGE_CPMU_CLCK_ORIDE, 4014 CPMU_CLCK_ORIDE_MAC_ORIDE_EN); 4015 4016 return 0; 4017 } 4018 4019 /* 4020 * Frame reception handling. This is called if there's a frame 4021 * on the receive return list. 4022 * 4023 * Note: we have to be able to handle two possibilities here: 4024 * 1) the frame is from the jumbo receive ring 4025 * 2) the frame is from the standard receive ring 4026 */ 4027 4028 static void 4029 bge_rxeof(struct bge_softc *sc) 4030 { 4031 struct ifnet *ifp; 4032 uint16_t rx_prod, rx_cons; 4033 int stdcnt = 0, jumbocnt = 0; 4034 bus_dmamap_t dmamap; 4035 bus_addr_t offset, toff; 4036 bus_size_t tlen; 4037 int tosync; 4038 4039 rx_cons = sc->bge_rx_saved_considx; 4040 rx_prod = sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx; 4041 4042 /* Nothing to do */ 4043 if (rx_cons == rx_prod) 4044 return; 4045 4046 ifp = &sc->ethercom.ec_if; 4047 4048 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 4049 offsetof(struct bge_ring_data, bge_status_block), 4050 sizeof (struct bge_status_block), 4051 BUS_DMASYNC_POSTREAD); 4052 4053 offset = offsetof(struct bge_ring_data, bge_rx_return_ring); 4054 tosync = rx_prod - rx_cons; 4055 4056 if (tosync != 0) 4057 rnd_add_uint32(&sc->rnd_source, tosync); 4058 4059 toff = offset + (rx_cons * sizeof (struct bge_rx_bd)); 4060 4061 if (tosync < 0) { 4062 tlen = (sc->bge_return_ring_cnt - rx_cons) * 4063 sizeof (struct bge_rx_bd); 4064 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 4065 toff, tlen, BUS_DMASYNC_POSTREAD); 4066 tosync = -tosync; 4067 } 4068 4069 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 4070 offset, tosync * sizeof (struct bge_rx_bd), 4071 BUS_DMASYNC_POSTREAD); 4072 4073 while (rx_cons != rx_prod) { 4074 struct bge_rx_bd *cur_rx; 4075 uint32_t rxidx; 4076 struct mbuf *m = NULL; 4077 4078 cur_rx = &sc->bge_rdata->bge_rx_return_ring[rx_cons]; 4079 4080 rxidx = cur_rx->bge_idx; 4081 BGE_INC(rx_cons, sc->bge_return_ring_cnt); 4082 4083 if (cur_rx->bge_flags & BGE_RXBDFLAG_JUMBO_RING) { 4084 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT); 4085 m = sc->bge_cdata.bge_rx_jumbo_chain[rxidx]; 4086 sc->bge_cdata.bge_rx_jumbo_chain[rxidx] = NULL; 4087 jumbocnt++; 4088 bus_dmamap_sync(sc->bge_dmatag, 4089 sc->bge_cdata.bge_rx_jumbo_map, 4090 mtod(m, char *) - (char *)sc->bge_cdata.bge_jumbo_buf, 4091 BGE_JLEN, BUS_DMASYNC_POSTREAD); 4092 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 4093 ifp->if_ierrors++; 4094 bge_newbuf_jumbo(sc, sc->bge_jumbo, m); 4095 continue; 4096 } 4097 if (bge_newbuf_jumbo(sc, sc->bge_jumbo, 4098 NULL)== ENOBUFS) { 4099 ifp->if_ierrors++; 4100 bge_newbuf_jumbo(sc, sc->bge_jumbo, m); 4101 continue; 4102 } 4103 } else { 4104 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT); 4105 m = sc->bge_cdata.bge_rx_std_chain[rxidx]; 4106 4107 sc->bge_cdata.bge_rx_std_chain[rxidx] = NULL; 4108 stdcnt++; 4109 dmamap = sc->bge_cdata.bge_rx_std_map[rxidx]; 4110 sc->bge_cdata.bge_rx_std_map[rxidx] = 0; 4111 if (dmamap == NULL) { 4112 ifp->if_ierrors++; 4113 bge_newbuf_std(sc, sc->bge_std, m, dmamap); 4114 continue; 4115 } 4116 bus_dmamap_sync(sc->bge_dmatag, dmamap, 0, 4117 dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 4118 bus_dmamap_unload(sc->bge_dmatag, dmamap); 4119 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 4120 ifp->if_ierrors++; 4121 bge_newbuf_std(sc, sc->bge_std, m, dmamap); 4122 continue; 4123 } 4124 if (bge_newbuf_std(sc, sc->bge_std, 4125 NULL, dmamap) == ENOBUFS) { 4126 ifp->if_ierrors++; 4127 bge_newbuf_std(sc, sc->bge_std, m, dmamap); 4128 continue; 4129 } 4130 } 4131 4132 ifp->if_ipackets++; 4133 #ifndef __NO_STRICT_ALIGNMENT 4134 /* 4135 * XXX: if the 5701 PCIX-Rx-DMA workaround is in effect, 4136 * the Rx buffer has the layer-2 header unaligned. 4137 * If our CPU requires alignment, re-align by copying. 4138 */ 4139 if (sc->bge_flags & BGE_RX_ALIGNBUG) { 4140 memmove(mtod(m, char *) + ETHER_ALIGN, m->m_data, 4141 cur_rx->bge_len); 4142 m->m_data += ETHER_ALIGN; 4143 } 4144 #endif 4145 4146 m->m_pkthdr.len = m->m_len = cur_rx->bge_len - ETHER_CRC_LEN; 4147 m->m_pkthdr.rcvif = ifp; 4148 4149 /* 4150 * Handle BPF listeners. Let the BPF user see the packet. 4151 */ 4152 bpf_mtap(ifp, m); 4153 4154 m->m_pkthdr.csum_flags = M_CSUM_IPv4; 4155 4156 if (BGE_IS_5717_PLUS(sc)) { 4157 if ((cur_rx->bge_error_flag & 4158 BGE_RXERRFLAG_IP_CSUM_NOK) != 0) 4159 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 4160 } else { 4161 if ((cur_rx->bge_ip_csum ^ 0xffff) != 0) 4162 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 4163 } 4164 /* 4165 * Rx transport checksum-offload may also 4166 * have bugs with packets which, when transmitted, 4167 * were `runts' requiring padding. 4168 */ 4169 if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM && 4170 (/* (sc->_bge_quirks & BGE_QUIRK_SHORT_CKSUM_BUG) == 0 ||*/ 4171 m->m_pkthdr.len >= ETHER_MIN_NOPAD)) { 4172 m->m_pkthdr.csum_data = 4173 cur_rx->bge_tcp_udp_csum; 4174 m->m_pkthdr.csum_flags |= 4175 (M_CSUM_TCPv4|M_CSUM_UDPv4| 4176 M_CSUM_DATA); 4177 } 4178 4179 /* 4180 * If we received a packet with a vlan tag, pass it 4181 * to vlan_input() instead of ether_input(). 4182 */ 4183 if (cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) { 4184 VLAN_INPUT_TAG(ifp, m, cur_rx->bge_vlan_tag, continue); 4185 } 4186 4187 (*ifp->if_input)(ifp, m); 4188 } 4189 4190 sc->bge_rx_saved_considx = rx_cons; 4191 bge_writembx(sc, BGE_MBX_RX_CONS0_LO, sc->bge_rx_saved_considx); 4192 if (stdcnt) 4193 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std); 4194 if (jumbocnt) 4195 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo); 4196 } 4197 4198 static void 4199 bge_txeof(struct bge_softc *sc) 4200 { 4201 struct bge_tx_bd *cur_tx = NULL; 4202 struct ifnet *ifp; 4203 struct txdmamap_pool_entry *dma; 4204 bus_addr_t offset, toff; 4205 bus_size_t tlen; 4206 int tosync; 4207 struct mbuf *m; 4208 4209 ifp = &sc->ethercom.ec_if; 4210 4211 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 4212 offsetof(struct bge_ring_data, bge_status_block), 4213 sizeof (struct bge_status_block), 4214 BUS_DMASYNC_POSTREAD); 4215 4216 offset = offsetof(struct bge_ring_data, bge_tx_ring); 4217 tosync = sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx - 4218 sc->bge_tx_saved_considx; 4219 4220 if (tosync != 0) 4221 rnd_add_uint32(&sc->rnd_source, tosync); 4222 4223 toff = offset + (sc->bge_tx_saved_considx * sizeof (struct bge_tx_bd)); 4224 4225 if (tosync < 0) { 4226 tlen = (BGE_TX_RING_CNT - sc->bge_tx_saved_considx) * 4227 sizeof (struct bge_tx_bd); 4228 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 4229 toff, tlen, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 4230 tosync = -tosync; 4231 } 4232 4233 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 4234 offset, tosync * sizeof (struct bge_tx_bd), 4235 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 4236 4237 /* 4238 * Go through our tx ring and free mbufs for those 4239 * frames that have been sent. 4240 */ 4241 while (sc->bge_tx_saved_considx != 4242 sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx) { 4243 uint32_t idx = 0; 4244 4245 idx = sc->bge_tx_saved_considx; 4246 cur_tx = &sc->bge_rdata->bge_tx_ring[idx]; 4247 if (cur_tx->bge_flags & BGE_TXBDFLAG_END) 4248 ifp->if_opackets++; 4249 m = sc->bge_cdata.bge_tx_chain[idx]; 4250 if (m != NULL) { 4251 sc->bge_cdata.bge_tx_chain[idx] = NULL; 4252 dma = sc->txdma[idx]; 4253 bus_dmamap_sync(sc->bge_dmatag, dma->dmamap, 0, 4254 dma->dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 4255 bus_dmamap_unload(sc->bge_dmatag, dma->dmamap); 4256 SLIST_INSERT_HEAD(&sc->txdma_list, dma, link); 4257 sc->txdma[idx] = NULL; 4258 4259 m_freem(m); 4260 } 4261 sc->bge_txcnt--; 4262 BGE_INC(sc->bge_tx_saved_considx, BGE_TX_RING_CNT); 4263 ifp->if_timer = 0; 4264 } 4265 4266 if (cur_tx != NULL) 4267 ifp->if_flags &= ~IFF_OACTIVE; 4268 } 4269 4270 static int 4271 bge_intr(void *xsc) 4272 { 4273 struct bge_softc *sc; 4274 struct ifnet *ifp; 4275 uint32_t statusword; 4276 4277 sc = xsc; 4278 ifp = &sc->ethercom.ec_if; 4279 4280 /* It is possible for the interrupt to arrive before 4281 * the status block is updated prior to the interrupt. 4282 * Reading the PCI State register will confirm whether the 4283 * interrupt is ours and will flush the status block. 4284 */ 4285 4286 /* read status word from status block */ 4287 statusword = sc->bge_rdata->bge_status_block.bge_status; 4288 4289 if ((statusword & BGE_STATFLAG_UPDATED) || 4290 (!(pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_PCISTATE) & 4291 BGE_PCISTATE_INTR_NOT_ACTIVE))) { 4292 /* Ack interrupt and stop others from occuring. */ 4293 bge_writembx_flush(sc, BGE_MBX_IRQ0_LO, 1); 4294 4295 BGE_EVCNT_INCR(sc->bge_ev_intr); 4296 4297 /* clear status word */ 4298 sc->bge_rdata->bge_status_block.bge_status = 0; 4299 4300 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 4301 statusword & BGE_STATFLAG_LINKSTATE_CHANGED || 4302 BGE_STS_BIT(sc, BGE_STS_LINK_EVT)) 4303 bge_link_upd(sc); 4304 4305 if (ifp->if_flags & IFF_RUNNING) { 4306 /* Check RX return ring producer/consumer */ 4307 bge_rxeof(sc); 4308 4309 /* Check TX ring producer/consumer */ 4310 bge_txeof(sc); 4311 } 4312 4313 if (sc->bge_pending_rxintr_change) { 4314 uint32_t rx_ticks = sc->bge_rx_coal_ticks; 4315 uint32_t rx_bds = sc->bge_rx_max_coal_bds; 4316 uint32_t junk; 4317 4318 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, rx_ticks); 4319 DELAY(10); 4320 junk = CSR_READ_4(sc, BGE_HCC_RX_COAL_TICKS); 4321 4322 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, rx_bds); 4323 DELAY(10); 4324 junk = CSR_READ_4(sc, BGE_HCC_RX_MAX_COAL_BDS); 4325 4326 sc->bge_pending_rxintr_change = 0; 4327 } 4328 bge_handle_events(sc); 4329 4330 /* Re-enable interrupts. */ 4331 bge_writembx_flush(sc, BGE_MBX_IRQ0_LO, 0); 4332 4333 if (ifp->if_flags & IFF_RUNNING && !IFQ_IS_EMPTY(&ifp->if_snd)) 4334 bge_start(ifp); 4335 4336 return 1; 4337 } else 4338 return 0; 4339 } 4340 4341 static void 4342 bge_asf_driver_up(struct bge_softc *sc) 4343 { 4344 if (sc->bge_asf_mode & ASF_STACKUP) { 4345 /* Send ASF heartbeat aprox. every 2s */ 4346 if (sc->bge_asf_count) 4347 sc->bge_asf_count --; 4348 else { 4349 sc->bge_asf_count = 2; 4350 4351 bge_wait_for_event_ack(sc); 4352 4353 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_MB, 4354 BGE_FW_CMD_DRV_ALIVE); 4355 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_LEN_MB, 4); 4356 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_DATA_MB, 4357 BGE_FW_HB_TIMEOUT_SEC); 4358 CSR_WRITE_4_FLUSH(sc, BGE_RX_CPU_EVENT, 4359 CSR_READ_4(sc, BGE_RX_CPU_EVENT) | 4360 BGE_RX_CPU_DRV_EVENT); 4361 } 4362 } 4363 } 4364 4365 static void 4366 bge_tick(void *xsc) 4367 { 4368 struct bge_softc *sc = xsc; 4369 struct mii_data *mii = &sc->bge_mii; 4370 int s; 4371 4372 s = splnet(); 4373 4374 if (BGE_IS_5705_PLUS(sc)) 4375 bge_stats_update_regs(sc); 4376 else 4377 bge_stats_update(sc); 4378 4379 if (sc->bge_flags & BGE_PHY_FIBER_TBI) { 4380 /* 4381 * Since in TBI mode auto-polling can't be used we should poll 4382 * link status manually. Here we register pending link event 4383 * and trigger interrupt. 4384 */ 4385 BGE_STS_SETBIT(sc, BGE_STS_LINK_EVT); 4386 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET); 4387 } else { 4388 /* 4389 * Do not touch PHY if we have link up. This could break 4390 * IPMI/ASF mode or produce extra input errors. 4391 * (extra input errors was reported for bcm5701 & bcm5704). 4392 */ 4393 if (!BGE_STS_BIT(sc, BGE_STS_LINK)) 4394 mii_tick(mii); 4395 } 4396 4397 bge_asf_driver_up(sc); 4398 4399 callout_reset(&sc->bge_timeout, hz, bge_tick, sc); 4400 4401 splx(s); 4402 } 4403 4404 static void 4405 bge_stats_update_regs(struct bge_softc *sc) 4406 { 4407 struct ifnet *ifp = &sc->ethercom.ec_if; 4408 4409 ifp->if_collisions += CSR_READ_4(sc, BGE_MAC_STATS + 4410 offsetof(struct bge_mac_stats_regs, etherStatsCollisions)); 4411 4412 ifp->if_ierrors += CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_DROPS); 4413 ifp->if_ierrors += CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_ERRORS); 4414 ifp->if_ierrors += CSR_READ_4(sc, BGE_RXLP_LOCSTAT_OUT_OF_BDS); 4415 } 4416 4417 static void 4418 bge_stats_update(struct bge_softc *sc) 4419 { 4420 struct ifnet *ifp = &sc->ethercom.ec_if; 4421 bus_size_t stats = BGE_MEMWIN_START + BGE_STATS_BLOCK; 4422 4423 #define READ_STAT(sc, stats, stat) \ 4424 CSR_READ_4(sc, stats + offsetof(struct bge_stats, stat)) 4425 4426 ifp->if_collisions += 4427 (READ_STAT(sc, stats, dot3StatsSingleCollisionFrames.bge_addr_lo) + 4428 READ_STAT(sc, stats, dot3StatsMultipleCollisionFrames.bge_addr_lo) + 4429 READ_STAT(sc, stats, dot3StatsExcessiveCollisions.bge_addr_lo) + 4430 READ_STAT(sc, stats, dot3StatsLateCollisions.bge_addr_lo)) - 4431 ifp->if_collisions; 4432 4433 BGE_EVCNT_UPD(sc->bge_ev_tx_xoff, 4434 READ_STAT(sc, stats, outXoffSent.bge_addr_lo)); 4435 BGE_EVCNT_UPD(sc->bge_ev_tx_xon, 4436 READ_STAT(sc, stats, outXonSent.bge_addr_lo)); 4437 BGE_EVCNT_UPD(sc->bge_ev_rx_xoff, 4438 READ_STAT(sc, stats, 4439 xoffPauseFramesReceived.bge_addr_lo)); 4440 BGE_EVCNT_UPD(sc->bge_ev_rx_xon, 4441 READ_STAT(sc, stats, xonPauseFramesReceived.bge_addr_lo)); 4442 BGE_EVCNT_UPD(sc->bge_ev_rx_macctl, 4443 READ_STAT(sc, stats, 4444 macControlFramesReceived.bge_addr_lo)); 4445 BGE_EVCNT_UPD(sc->bge_ev_xoffentered, 4446 READ_STAT(sc, stats, xoffStateEntered.bge_addr_lo)); 4447 4448 #undef READ_STAT 4449 4450 #ifdef notdef 4451 ifp->if_collisions += 4452 (sc->bge_rdata->bge_info.bge_stats.dot3StatsSingleCollisionFrames + 4453 sc->bge_rdata->bge_info.bge_stats.dot3StatsMultipleCollisionFrames + 4454 sc->bge_rdata->bge_info.bge_stats.dot3StatsExcessiveCollisions + 4455 sc->bge_rdata->bge_info.bge_stats.dot3StatsLateCollisions) - 4456 ifp->if_collisions; 4457 #endif 4458 } 4459 4460 /* 4461 * Pad outbound frame to ETHER_MIN_NOPAD for an unusual reason. 4462 * The bge hardware will pad out Tx runts to ETHER_MIN_NOPAD, 4463 * but when such padded frames employ the bge IP/TCP checksum offload, 4464 * the hardware checksum assist gives incorrect results (possibly 4465 * from incorporating its own padding into the UDP/TCP checksum; who knows). 4466 * If we pad such runts with zeros, the onboard checksum comes out correct. 4467 */ 4468 static inline int 4469 bge_cksum_pad(struct mbuf *pkt) 4470 { 4471 struct mbuf *last = NULL; 4472 int padlen; 4473 4474 padlen = ETHER_MIN_NOPAD - pkt->m_pkthdr.len; 4475 4476 /* if there's only the packet-header and we can pad there, use it. */ 4477 if (pkt->m_pkthdr.len == pkt->m_len && 4478 M_TRAILINGSPACE(pkt) >= padlen) { 4479 last = pkt; 4480 } else { 4481 /* 4482 * Walk packet chain to find last mbuf. We will either 4483 * pad there, or append a new mbuf and pad it 4484 * (thus perhaps avoiding the bcm5700 dma-min bug). 4485 */ 4486 for (last = pkt; last->m_next != NULL; last = last->m_next) { 4487 continue; /* do nothing */ 4488 } 4489 4490 /* `last' now points to last in chain. */ 4491 if (M_TRAILINGSPACE(last) < padlen) { 4492 /* Allocate new empty mbuf, pad it. Compact later. */ 4493 struct mbuf *n; 4494 MGET(n, M_DONTWAIT, MT_DATA); 4495 if (n == NULL) 4496 return ENOBUFS; 4497 n->m_len = 0; 4498 last->m_next = n; 4499 last = n; 4500 } 4501 } 4502 4503 KDASSERT(!M_READONLY(last)); 4504 KDASSERT(M_TRAILINGSPACE(last) >= padlen); 4505 4506 /* Now zero the pad area, to avoid the bge cksum-assist bug */ 4507 memset(mtod(last, char *) + last->m_len, 0, padlen); 4508 last->m_len += padlen; 4509 pkt->m_pkthdr.len += padlen; 4510 return 0; 4511 } 4512 4513 /* 4514 * Compact outbound packets to avoid bug with DMA segments less than 8 bytes. 4515 */ 4516 static inline int 4517 bge_compact_dma_runt(struct mbuf *pkt) 4518 { 4519 struct mbuf *m, *prev; 4520 int totlen, prevlen; 4521 4522 prev = NULL; 4523 totlen = 0; 4524 prevlen = -1; 4525 4526 for (m = pkt; m != NULL; prev = m,m = m->m_next) { 4527 int mlen = m->m_len; 4528 int shortfall = 8 - mlen ; 4529 4530 totlen += mlen; 4531 if (mlen == 0) 4532 continue; 4533 if (mlen >= 8) 4534 continue; 4535 4536 /* If we get here, mbuf data is too small for DMA engine. 4537 * Try to fix by shuffling data to prev or next in chain. 4538 * If that fails, do a compacting deep-copy of the whole chain. 4539 */ 4540 4541 /* Internal frag. If fits in prev, copy it there. */ 4542 if (prev && M_TRAILINGSPACE(prev) >= m->m_len) { 4543 memcpy(prev->m_data + prev->m_len, m->m_data, mlen); 4544 prev->m_len += mlen; 4545 m->m_len = 0; 4546 /* XXX stitch chain */ 4547 prev->m_next = m_free(m); 4548 m = prev; 4549 continue; 4550 } 4551 else if (m->m_next != NULL && 4552 M_TRAILINGSPACE(m) >= shortfall && 4553 m->m_next->m_len >= (8 + shortfall)) { 4554 /* m is writable and have enough data in next, pull up. */ 4555 4556 memcpy(m->m_data + m->m_len, m->m_next->m_data, 4557 shortfall); 4558 m->m_len += shortfall; 4559 m->m_next->m_len -= shortfall; 4560 m->m_next->m_data += shortfall; 4561 } 4562 else if (m->m_next == NULL || 1) { 4563 /* Got a runt at the very end of the packet. 4564 * borrow data from the tail of the preceding mbuf and 4565 * update its length in-place. (The original data is still 4566 * valid, so we can do this even if prev is not writable.) 4567 */ 4568 4569 /* if we'd make prev a runt, just move all of its data. */ 4570 KASSERT(prev != NULL /*, ("runt but null PREV")*/); 4571 KASSERT(prev->m_len >= 8 /*, ("runt prev")*/); 4572 4573 if ((prev->m_len - shortfall) < 8) 4574 shortfall = prev->m_len; 4575 4576 #ifdef notyet /* just do the safe slow thing for now */ 4577 if (!M_READONLY(m)) { 4578 if (M_LEADINGSPACE(m) < shorfall) { 4579 void *m_dat; 4580 m_dat = (m->m_flags & M_PKTHDR) ? 4581 m->m_pktdat : m->dat; 4582 memmove(m_dat, mtod(m, void*), m->m_len); 4583 m->m_data = m_dat; 4584 } 4585 } else 4586 #endif /* just do the safe slow thing */ 4587 { 4588 struct mbuf * n = NULL; 4589 int newprevlen = prev->m_len - shortfall; 4590 4591 MGET(n, M_NOWAIT, MT_DATA); 4592 if (n == NULL) 4593 return ENOBUFS; 4594 KASSERT(m->m_len + shortfall < MLEN 4595 /*, 4596 ("runt %d +prev %d too big\n", m->m_len, shortfall)*/); 4597 4598 /* first copy the data we're stealing from prev */ 4599 memcpy(n->m_data, prev->m_data + newprevlen, 4600 shortfall); 4601 4602 /* update prev->m_len accordingly */ 4603 prev->m_len -= shortfall; 4604 4605 /* copy data from runt m */ 4606 memcpy(n->m_data + shortfall, m->m_data, 4607 m->m_len); 4608 4609 /* n holds what we stole from prev, plus m */ 4610 n->m_len = shortfall + m->m_len; 4611 4612 /* stitch n into chain and free m */ 4613 n->m_next = m->m_next; 4614 prev->m_next = n; 4615 /* KASSERT(m->m_next == NULL); */ 4616 m->m_next = NULL; 4617 m_free(m); 4618 m = n; /* for continuing loop */ 4619 } 4620 } 4621 prevlen = m->m_len; 4622 } 4623 return 0; 4624 } 4625 4626 /* 4627 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data 4628 * pointers to descriptors. 4629 */ 4630 static int 4631 bge_encap(struct bge_softc *sc, struct mbuf *m_head, uint32_t *txidx) 4632 { 4633 struct bge_tx_bd *f = NULL; 4634 uint32_t frag, cur; 4635 uint16_t csum_flags = 0; 4636 uint16_t txbd_tso_flags = 0; 4637 struct txdmamap_pool_entry *dma; 4638 bus_dmamap_t dmamap; 4639 int i = 0; 4640 struct m_tag *mtag; 4641 int use_tso, maxsegsize, error; 4642 4643 cur = frag = *txidx; 4644 4645 if (m_head->m_pkthdr.csum_flags) { 4646 if (m_head->m_pkthdr.csum_flags & M_CSUM_IPv4) 4647 csum_flags |= BGE_TXBDFLAG_IP_CSUM; 4648 if (m_head->m_pkthdr.csum_flags & (M_CSUM_TCPv4|M_CSUM_UDPv4)) 4649 csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM; 4650 } 4651 4652 /* 4653 * If we were asked to do an outboard checksum, and the NIC 4654 * has the bug where it sometimes adds in the Ethernet padding, 4655 * explicitly pad with zeros so the cksum will be correct either way. 4656 * (For now, do this for all chip versions, until newer 4657 * are confirmed to not require the workaround.) 4658 */ 4659 if ((csum_flags & BGE_TXBDFLAG_TCP_UDP_CSUM) == 0 || 4660 #ifdef notyet 4661 (sc->bge_quirks & BGE_QUIRK_SHORT_CKSUM_BUG) == 0 || 4662 #endif 4663 m_head->m_pkthdr.len >= ETHER_MIN_NOPAD) 4664 goto check_dma_bug; 4665 4666 if (bge_cksum_pad(m_head) != 0) 4667 return ENOBUFS; 4668 4669 check_dma_bug: 4670 if (!(BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX)) 4671 goto doit; 4672 4673 /* 4674 * bcm5700 Revision B silicon cannot handle DMA descriptors with 4675 * less than eight bytes. If we encounter a teeny mbuf 4676 * at the end of a chain, we can pad. Otherwise, copy. 4677 */ 4678 if (bge_compact_dma_runt(m_head) != 0) 4679 return ENOBUFS; 4680 4681 doit: 4682 dma = SLIST_FIRST(&sc->txdma_list); 4683 if (dma == NULL) 4684 return ENOBUFS; 4685 dmamap = dma->dmamap; 4686 4687 /* 4688 * Set up any necessary TSO state before we start packing... 4689 */ 4690 use_tso = (m_head->m_pkthdr.csum_flags & M_CSUM_TSOv4) != 0; 4691 if (!use_tso) { 4692 maxsegsize = 0; 4693 } else { /* TSO setup */ 4694 unsigned mss; 4695 struct ether_header *eh; 4696 unsigned ip_tcp_hlen, iptcp_opt_words, tcp_seg_flags, offset; 4697 struct mbuf * m0 = m_head; 4698 struct ip *ip; 4699 struct tcphdr *th; 4700 int iphl, hlen; 4701 4702 /* 4703 * XXX It would be nice if the mbuf pkthdr had offset 4704 * fields for the protocol headers. 4705 */ 4706 4707 eh = mtod(m0, struct ether_header *); 4708 switch (htons(eh->ether_type)) { 4709 case ETHERTYPE_IP: 4710 offset = ETHER_HDR_LEN; 4711 break; 4712 4713 case ETHERTYPE_VLAN: 4714 offset = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 4715 break; 4716 4717 default: 4718 /* 4719 * Don't support this protocol or encapsulation. 4720 */ 4721 return ENOBUFS; 4722 } 4723 4724 /* 4725 * TCP/IP headers are in the first mbuf; we can do 4726 * this the easy way. 4727 */ 4728 iphl = M_CSUM_DATA_IPv4_IPHL(m0->m_pkthdr.csum_data); 4729 hlen = iphl + offset; 4730 if (__predict_false(m0->m_len < 4731 (hlen + sizeof(struct tcphdr)))) { 4732 4733 aprint_debug_dev(sc->bge_dev, 4734 "TSO: hard case m0->m_len == %d < ip/tcp hlen %zd," 4735 "not handled yet\n", 4736 m0->m_len, hlen+ sizeof(struct tcphdr)); 4737 #ifdef NOTYET 4738 /* 4739 * XXX jonathan (at) NetBSD.org: untested. 4740 * how to force this branch to be taken? 4741 */ 4742 BGE_EVCNT_INCR(&sc->sc_ev_txtsopain); 4743 4744 m_copydata(m0, offset, sizeof(ip), &ip); 4745 m_copydata(m0, hlen, sizeof(th), &th); 4746 4747 ip.ip_len = 0; 4748 4749 m_copyback(m0, hlen + offsetof(struct ip, ip_len), 4750 sizeof(ip.ip_len), &ip.ip_len); 4751 4752 th.th_sum = in_cksum_phdr(ip.ip_src.s_addr, 4753 ip.ip_dst.s_addr, htons(IPPROTO_TCP)); 4754 4755 m_copyback(m0, hlen + offsetof(struct tcphdr, th_sum), 4756 sizeof(th.th_sum), &th.th_sum); 4757 4758 hlen += th.th_off << 2; 4759 iptcp_opt_words = hlen; 4760 #else 4761 /* 4762 * if_wm "hard" case not yet supported, can we not 4763 * mandate it out of existence? 4764 */ 4765 (void) ip; (void)th; (void) ip_tcp_hlen; 4766 4767 return ENOBUFS; 4768 #endif 4769 } else { 4770 ip = (struct ip *) (mtod(m0, char *) + offset); 4771 th = (struct tcphdr *) (mtod(m0, char *) + hlen); 4772 ip_tcp_hlen = iphl + (th->th_off << 2); 4773 4774 /* Total IP/TCP options, in 32-bit words */ 4775 iptcp_opt_words = (ip_tcp_hlen 4776 - sizeof(struct tcphdr) 4777 - sizeof(struct ip)) >> 2; 4778 } 4779 if (BGE_IS_575X_PLUS(sc)) { 4780 th->th_sum = 0; 4781 csum_flags &= ~(BGE_TXBDFLAG_TCP_UDP_CSUM); 4782 } else { 4783 /* 4784 * XXX jonathan (at) NetBSD.org: 5705 untested. 4785 * Requires TSO firmware patch for 5701/5703/5704. 4786 */ 4787 th->th_sum = in_cksum_phdr(ip->ip_src.s_addr, 4788 ip->ip_dst.s_addr, htons(IPPROTO_TCP)); 4789 } 4790 4791 mss = m_head->m_pkthdr.segsz; 4792 txbd_tso_flags |= 4793 BGE_TXBDFLAG_CPU_PRE_DMA | 4794 BGE_TXBDFLAG_CPU_POST_DMA; 4795 4796 /* 4797 * Our NIC TSO-assist assumes TSO has standard, optionless 4798 * IPv4 and TCP headers, which total 40 bytes. By default, 4799 * the NIC copies 40 bytes of IP/TCP header from the 4800 * supplied header into the IP/TCP header portion of 4801 * each post-TSO-segment. If the supplied packet has IP or 4802 * TCP options, we need to tell the NIC to copy those extra 4803 * bytes into each post-TSO header, in addition to the normal 4804 * 40-byte IP/TCP header (and to leave space accordingly). 4805 * Unfortunately, the driver encoding of option length 4806 * varies across different ASIC families. 4807 */ 4808 tcp_seg_flags = 0; 4809 if (iptcp_opt_words) { 4810 if (BGE_IS_5705_PLUS(sc)) { 4811 tcp_seg_flags = 4812 iptcp_opt_words << 11; 4813 } else { 4814 txbd_tso_flags |= 4815 iptcp_opt_words << 12; 4816 } 4817 } 4818 maxsegsize = mss | tcp_seg_flags; 4819 ip->ip_len = htons(mss + ip_tcp_hlen); 4820 4821 } /* TSO setup */ 4822 4823 /* 4824 * Start packing the mbufs in this chain into 4825 * the fragment pointers. Stop when we run out 4826 * of fragments or hit the end of the mbuf chain. 4827 */ 4828 error = bus_dmamap_load_mbuf(sc->bge_dmatag, dmamap, m_head, 4829 BUS_DMA_NOWAIT); 4830 if (error) 4831 return ENOBUFS; 4832 /* 4833 * Sanity check: avoid coming within 16 descriptors 4834 * of the end of the ring. 4835 */ 4836 if (dmamap->dm_nsegs > (BGE_TX_RING_CNT - sc->bge_txcnt - 16)) { 4837 BGE_TSO_PRINTF(("%s: " 4838 " dmamap_load_mbuf too close to ring wrap\n", 4839 device_xname(sc->bge_dev))); 4840 goto fail_unload; 4841 } 4842 4843 mtag = sc->ethercom.ec_nvlans ? 4844 m_tag_find(m_head, PACKET_TAG_VLAN, NULL) : NULL; 4845 4846 4847 /* Iterate over dmap-map fragments. */ 4848 for (i = 0; i < dmamap->dm_nsegs; i++) { 4849 f = &sc->bge_rdata->bge_tx_ring[frag]; 4850 if (sc->bge_cdata.bge_tx_chain[frag] != NULL) 4851 break; 4852 4853 BGE_HOSTADDR(f->bge_addr, dmamap->dm_segs[i].ds_addr); 4854 f->bge_len = dmamap->dm_segs[i].ds_len; 4855 4856 /* 4857 * For 5751 and follow-ons, for TSO we must turn 4858 * off checksum-assist flag in the tx-descr, and 4859 * supply the ASIC-revision-specific encoding 4860 * of TSO flags and segsize. 4861 */ 4862 if (use_tso) { 4863 if (BGE_IS_575X_PLUS(sc) || i == 0) { 4864 f->bge_rsvd = maxsegsize; 4865 f->bge_flags = csum_flags | txbd_tso_flags; 4866 } else { 4867 f->bge_rsvd = 0; 4868 f->bge_flags = 4869 (csum_flags | txbd_tso_flags) & 0x0fff; 4870 } 4871 } else { 4872 f->bge_rsvd = 0; 4873 f->bge_flags = csum_flags; 4874 } 4875 4876 if (mtag != NULL) { 4877 f->bge_flags |= BGE_TXBDFLAG_VLAN_TAG; 4878 f->bge_vlan_tag = VLAN_TAG_VALUE(mtag); 4879 } else { 4880 f->bge_vlan_tag = 0; 4881 } 4882 cur = frag; 4883 BGE_INC(frag, BGE_TX_RING_CNT); 4884 } 4885 4886 if (i < dmamap->dm_nsegs) { 4887 BGE_TSO_PRINTF(("%s: reached %d < dm_nsegs %d\n", 4888 device_xname(sc->bge_dev), i, dmamap->dm_nsegs)); 4889 goto fail_unload; 4890 } 4891 4892 bus_dmamap_sync(sc->bge_dmatag, dmamap, 0, dmamap->dm_mapsize, 4893 BUS_DMASYNC_PREWRITE); 4894 4895 if (frag == sc->bge_tx_saved_considx) { 4896 BGE_TSO_PRINTF(("%s: frag %d = wrapped id %d?\n", 4897 device_xname(sc->bge_dev), frag, sc->bge_tx_saved_considx)); 4898 4899 goto fail_unload; 4900 } 4901 4902 sc->bge_rdata->bge_tx_ring[cur].bge_flags |= BGE_TXBDFLAG_END; 4903 sc->bge_cdata.bge_tx_chain[cur] = m_head; 4904 SLIST_REMOVE_HEAD(&sc->txdma_list, link); 4905 sc->txdma[cur] = dma; 4906 sc->bge_txcnt += dmamap->dm_nsegs; 4907 4908 *txidx = frag; 4909 4910 return 0; 4911 4912 fail_unload: 4913 bus_dmamap_unload(sc->bge_dmatag, dmamap); 4914 4915 return ENOBUFS; 4916 } 4917 4918 /* 4919 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 4920 * to the mbuf data regions directly in the transmit descriptors. 4921 */ 4922 static void 4923 bge_start(struct ifnet *ifp) 4924 { 4925 struct bge_softc *sc; 4926 struct mbuf *m_head = NULL; 4927 uint32_t prodidx; 4928 int pkts = 0; 4929 4930 sc = ifp->if_softc; 4931 4932 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 4933 return; 4934 4935 prodidx = sc->bge_tx_prodidx; 4936 4937 while (sc->bge_cdata.bge_tx_chain[prodidx] == NULL) { 4938 IFQ_POLL(&ifp->if_snd, m_head); 4939 if (m_head == NULL) 4940 break; 4941 4942 #if 0 4943 /* 4944 * XXX 4945 * safety overkill. If this is a fragmented packet chain 4946 * with delayed TCP/UDP checksums, then only encapsulate 4947 * it if we have enough descriptors to handle the entire 4948 * chain at once. 4949 * (paranoia -- may not actually be needed) 4950 */ 4951 if (m_head->m_flags & M_FIRSTFRAG && 4952 m_head->m_pkthdr.csum_flags & (CSUM_DELAY_DATA)) { 4953 if ((BGE_TX_RING_CNT - sc->bge_txcnt) < 4954 M_CSUM_DATA_IPv4_OFFSET(m_head->m_pkthdr.csum_data) + 16) { 4955 ifp->if_flags |= IFF_OACTIVE; 4956 break; 4957 } 4958 } 4959 #endif 4960 4961 /* 4962 * Pack the data into the transmit ring. If we 4963 * don't have room, set the OACTIVE flag and wait 4964 * for the NIC to drain the ring. 4965 */ 4966 if (bge_encap(sc, m_head, &prodidx)) { 4967 ifp->if_flags |= IFF_OACTIVE; 4968 break; 4969 } 4970 4971 /* now we are committed to transmit the packet */ 4972 IFQ_DEQUEUE(&ifp->if_snd, m_head); 4973 pkts++; 4974 4975 /* 4976 * If there's a BPF listener, bounce a copy of this frame 4977 * to him. 4978 */ 4979 bpf_mtap(ifp, m_head); 4980 } 4981 if (pkts == 0) 4982 return; 4983 4984 /* Transmit */ 4985 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); 4986 /* 5700 b2 errata */ 4987 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX) 4988 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); 4989 4990 sc->bge_tx_prodidx = prodidx; 4991 4992 /* 4993 * Set a timeout in case the chip goes out to lunch. 4994 */ 4995 ifp->if_timer = 5; 4996 } 4997 4998 static int 4999 bge_init(struct ifnet *ifp) 5000 { 5001 struct bge_softc *sc = ifp->if_softc; 5002 const uint16_t *m; 5003 uint32_t mode; 5004 int s, error = 0; 5005 5006 s = splnet(); 5007 5008 ifp = &sc->ethercom.ec_if; 5009 5010 /* Cancel pending I/O and flush buffers. */ 5011 bge_stop(ifp, 0); 5012 5013 bge_stop_fw(sc); 5014 bge_sig_pre_reset(sc, BGE_RESET_START); 5015 bge_reset(sc); 5016 bge_sig_legacy(sc, BGE_RESET_START); 5017 bge_sig_post_reset(sc, BGE_RESET_START); 5018 5019 bge_chipinit(sc); 5020 5021 /* 5022 * Init the various state machines, ring 5023 * control blocks and firmware. 5024 */ 5025 error = bge_blockinit(sc); 5026 if (error != 0) { 5027 aprint_error_dev(sc->bge_dev, "initialization error %d\n", 5028 error); 5029 splx(s); 5030 return error; 5031 } 5032 5033 ifp = &sc->ethercom.ec_if; 5034 5035 /* Specify MTU. */ 5036 CSR_WRITE_4(sc, BGE_RX_MTU, ifp->if_mtu + 5037 ETHER_HDR_LEN + ETHER_CRC_LEN + ETHER_VLAN_ENCAP_LEN); 5038 5039 /* Load our MAC address. */ 5040 m = (const uint16_t *)&(CLLADDR(ifp->if_sadl)[0]); 5041 CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0])); 5042 CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, (htons(m[1]) << 16) | htons(m[2])); 5043 5044 /* Enable or disable promiscuous mode as needed. */ 5045 if (ifp->if_flags & IFF_PROMISC) 5046 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 5047 else 5048 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 5049 5050 /* Program multicast filter. */ 5051 bge_setmulti(sc); 5052 5053 /* Init RX ring. */ 5054 bge_init_rx_ring_std(sc); 5055 5056 /* 5057 * Workaround for a bug in 5705 ASIC rev A0. Poll the NIC's 5058 * memory to insure that the chip has in fact read the first 5059 * entry of the ring. 5060 */ 5061 if (sc->bge_chipid == BGE_CHIPID_BCM5705_A0) { 5062 uint32_t v, i; 5063 for (i = 0; i < 10; i++) { 5064 DELAY(20); 5065 v = bge_readmem_ind(sc, BGE_STD_RX_RINGS + 8); 5066 if (v == (MCLBYTES - ETHER_ALIGN)) 5067 break; 5068 } 5069 if (i == 10) 5070 aprint_error_dev(sc->bge_dev, 5071 "5705 A0 chip failed to load RX ring\n"); 5072 } 5073 5074 /* Init jumbo RX ring. */ 5075 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 5076 bge_init_rx_ring_jumbo(sc); 5077 5078 /* Init our RX return ring index */ 5079 sc->bge_rx_saved_considx = 0; 5080 5081 /* Init TX ring. */ 5082 bge_init_tx_ring(sc); 5083 5084 /* Enable TX MAC state machine lockup fix. */ 5085 mode = CSR_READ_4(sc, BGE_TX_MODE); 5086 if (BGE_IS_5755_PLUS(sc) || 5087 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 5088 mode |= BGE_TXMODE_MBUF_LOCKUP_FIX; 5089 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) { 5090 mode &= ~(BGE_TXMODE_JMB_FRM_LEN | BGE_TXMODE_CNT_DN_MODE); 5091 mode |= CSR_READ_4(sc, BGE_TX_MODE) & 5092 (BGE_TXMODE_JMB_FRM_LEN | BGE_TXMODE_CNT_DN_MODE); 5093 } 5094 5095 /* Turn on transmitter */ 5096 CSR_WRITE_4_FLUSH(sc, BGE_TX_MODE, mode | BGE_TXMODE_ENABLE); 5097 DELAY(100); 5098 5099 /* Turn on receiver */ 5100 mode = CSR_READ_4(sc, BGE_RX_MODE); 5101 if (BGE_IS_5755_PLUS(sc)) 5102 mode |= BGE_RXMODE_IPV6_ENABLE; 5103 CSR_WRITE_4_FLUSH(sc, BGE_RX_MODE, mode | BGE_RXMODE_ENABLE); 5104 DELAY(10); 5105 5106 CSR_WRITE_4(sc, BGE_MAX_RX_FRAME_LOWAT, 2); 5107 5108 /* Tell firmware we're alive. */ 5109 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 5110 5111 /* Enable host interrupts. */ 5112 PCI_SETBIT(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MISC_CTL, 5113 BGE_PCIMISCCTL_CLEAR_INTA); 5114 PCI_CLRBIT(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MISC_CTL, 5115 BGE_PCIMISCCTL_MASK_PCI_INTR); 5116 bge_writembx_flush(sc, BGE_MBX_IRQ0_LO, 0); 5117 5118 if ((error = bge_ifmedia_upd(ifp)) != 0) 5119 goto out; 5120 5121 ifp->if_flags |= IFF_RUNNING; 5122 ifp->if_flags &= ~IFF_OACTIVE; 5123 5124 callout_reset(&sc->bge_timeout, hz, bge_tick, sc); 5125 5126 out: 5127 sc->bge_if_flags = ifp->if_flags; 5128 splx(s); 5129 5130 return error; 5131 } 5132 5133 /* 5134 * Set media options. 5135 */ 5136 static int 5137 bge_ifmedia_upd(struct ifnet *ifp) 5138 { 5139 struct bge_softc *sc = ifp->if_softc; 5140 struct mii_data *mii = &sc->bge_mii; 5141 struct ifmedia *ifm = &sc->bge_ifmedia; 5142 int rc; 5143 5144 /* If this is a 1000baseX NIC, enable the TBI port. */ 5145 if (sc->bge_flags & BGE_PHY_FIBER_TBI) { 5146 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 5147 return EINVAL; 5148 switch (IFM_SUBTYPE(ifm->ifm_media)) { 5149 case IFM_AUTO: 5150 /* 5151 * The BCM5704 ASIC appears to have a special 5152 * mechanism for programming the autoneg 5153 * advertisement registers in TBI mode. 5154 */ 5155 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) { 5156 uint32_t sgdig; 5157 sgdig = CSR_READ_4(sc, BGE_SGDIG_STS); 5158 if (sgdig & BGE_SGDIGSTS_DONE) { 5159 CSR_WRITE_4(sc, BGE_TX_TBI_AUTONEG, 0); 5160 sgdig = CSR_READ_4(sc, BGE_SGDIG_CFG); 5161 sgdig |= BGE_SGDIGCFG_AUTO | 5162 BGE_SGDIGCFG_PAUSE_CAP | 5163 BGE_SGDIGCFG_ASYM_PAUSE; 5164 CSR_WRITE_4_FLUSH(sc, BGE_SGDIG_CFG, 5165 sgdig | BGE_SGDIGCFG_SEND); 5166 DELAY(5); 5167 CSR_WRITE_4_FLUSH(sc, BGE_SGDIG_CFG, 5168 sgdig); 5169 } 5170 } 5171 break; 5172 case IFM_1000_SX: 5173 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 5174 BGE_CLRBIT(sc, BGE_MAC_MODE, 5175 BGE_MACMODE_HALF_DUPLEX); 5176 } else { 5177 BGE_SETBIT(sc, BGE_MAC_MODE, 5178 BGE_MACMODE_HALF_DUPLEX); 5179 } 5180 DELAY(40); 5181 break; 5182 default: 5183 return EINVAL; 5184 } 5185 /* XXX 802.3x flow control for 1000BASE-SX */ 5186 return 0; 5187 } 5188 5189 BGE_STS_SETBIT(sc, BGE_STS_LINK_EVT); 5190 if ((rc = mii_mediachg(mii)) == ENXIO) 5191 return 0; 5192 5193 /* 5194 * Force an interrupt so that we will call bge_link_upd 5195 * if needed and clear any pending link state attention. 5196 * Without this we are not getting any further interrupts 5197 * for link state changes and thus will not UP the link and 5198 * not be able to send in bge_start. The only way to get 5199 * things working was to receive a packet and get a RX intr. 5200 */ 5201 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 5202 sc->bge_flags & BGE_IS_5788) 5203 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET); 5204 else 5205 BGE_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW); 5206 5207 return rc; 5208 } 5209 5210 /* 5211 * Report current media status. 5212 */ 5213 static void 5214 bge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 5215 { 5216 struct bge_softc *sc = ifp->if_softc; 5217 struct mii_data *mii = &sc->bge_mii; 5218 5219 if (sc->bge_flags & BGE_PHY_FIBER_TBI) { 5220 ifmr->ifm_status = IFM_AVALID; 5221 ifmr->ifm_active = IFM_ETHER; 5222 if (CSR_READ_4(sc, BGE_MAC_STS) & 5223 BGE_MACSTAT_TBI_PCS_SYNCHED) 5224 ifmr->ifm_status |= IFM_ACTIVE; 5225 ifmr->ifm_active |= IFM_1000_SX; 5226 if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX) 5227 ifmr->ifm_active |= IFM_HDX; 5228 else 5229 ifmr->ifm_active |= IFM_FDX; 5230 return; 5231 } 5232 5233 mii_pollstat(mii); 5234 ifmr->ifm_status = mii->mii_media_status; 5235 ifmr->ifm_active = (mii->mii_media_active & ~IFM_ETH_FMASK) | 5236 sc->bge_flowflags; 5237 } 5238 5239 static int 5240 bge_ifflags_cb(struct ethercom *ec) 5241 { 5242 struct ifnet *ifp = &ec->ec_if; 5243 struct bge_softc *sc = ifp->if_softc; 5244 int change = ifp->if_flags ^ sc->bge_if_flags; 5245 5246 if ((change & ~(IFF_CANTCHANGE|IFF_DEBUG)) != 0) 5247 return ENETRESET; 5248 else if ((change & (IFF_PROMISC | IFF_ALLMULTI)) == 0) 5249 return 0; 5250 5251 if ((ifp->if_flags & IFF_PROMISC) == 0) 5252 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 5253 else 5254 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 5255 5256 bge_setmulti(sc); 5257 5258 sc->bge_if_flags = ifp->if_flags; 5259 return 0; 5260 } 5261 5262 static int 5263 bge_ioctl(struct ifnet *ifp, u_long command, void *data) 5264 { 5265 struct bge_softc *sc = ifp->if_softc; 5266 struct ifreq *ifr = (struct ifreq *) data; 5267 int s, error = 0; 5268 struct mii_data *mii; 5269 5270 s = splnet(); 5271 5272 switch (command) { 5273 case SIOCSIFMEDIA: 5274 /* XXX Flow control is not supported for 1000BASE-SX */ 5275 if (sc->bge_flags & BGE_PHY_FIBER_TBI) { 5276 ifr->ifr_media &= ~IFM_ETH_FMASK; 5277 sc->bge_flowflags = 0; 5278 } 5279 5280 /* Flow control requires full-duplex mode. */ 5281 if (IFM_SUBTYPE(ifr->ifr_media) == IFM_AUTO || 5282 (ifr->ifr_media & IFM_FDX) == 0) { 5283 ifr->ifr_media &= ~IFM_ETH_FMASK; 5284 } 5285 if (IFM_SUBTYPE(ifr->ifr_media) != IFM_AUTO) { 5286 if ((ifr->ifr_media & IFM_ETH_FMASK) == IFM_FLOW) { 5287 /* We can do both TXPAUSE and RXPAUSE. */ 5288 ifr->ifr_media |= 5289 IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE; 5290 } 5291 sc->bge_flowflags = ifr->ifr_media & IFM_ETH_FMASK; 5292 } 5293 /* FALLTHROUGH */ 5294 case SIOCGIFMEDIA: 5295 if (sc->bge_flags & BGE_PHY_FIBER_TBI) { 5296 error = ifmedia_ioctl(ifp, ifr, &sc->bge_ifmedia, 5297 command); 5298 } else { 5299 mii = &sc->bge_mii; 5300 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, 5301 command); 5302 } 5303 break; 5304 default: 5305 if ((error = ether_ioctl(ifp, command, data)) != ENETRESET) 5306 break; 5307 5308 error = 0; 5309 5310 if (command != SIOCADDMULTI && command != SIOCDELMULTI) 5311 ; 5312 else if (ifp->if_flags & IFF_RUNNING) 5313 bge_setmulti(sc); 5314 break; 5315 } 5316 5317 splx(s); 5318 5319 return error; 5320 } 5321 5322 static void 5323 bge_watchdog(struct ifnet *ifp) 5324 { 5325 struct bge_softc *sc; 5326 5327 sc = ifp->if_softc; 5328 5329 aprint_error_dev(sc->bge_dev, "watchdog timeout -- resetting\n"); 5330 5331 ifp->if_flags &= ~IFF_RUNNING; 5332 bge_init(ifp); 5333 5334 ifp->if_oerrors++; 5335 } 5336 5337 static void 5338 bge_stop_block(struct bge_softc *sc, bus_addr_t reg, uint32_t bit) 5339 { 5340 int i; 5341 5342 BGE_CLRBIT_FLUSH(sc, reg, bit); 5343 5344 for (i = 0; i < 1000; i++) { 5345 delay(100); 5346 if ((CSR_READ_4(sc, reg) & bit) == 0) 5347 return; 5348 } 5349 5350 /* 5351 * Doesn't print only when the register is BGE_SRS_MODE. It occurs 5352 * on some environment (and once after boot?) 5353 */ 5354 if (reg != BGE_SRS_MODE) 5355 aprint_error_dev(sc->bge_dev, 5356 "block failed to stop: reg 0x%lx, bit 0x%08x\n", 5357 (u_long)reg, bit); 5358 } 5359 5360 /* 5361 * Stop the adapter and free any mbufs allocated to the 5362 * RX and TX lists. 5363 */ 5364 static void 5365 bge_stop(struct ifnet *ifp, int disable) 5366 { 5367 struct bge_softc *sc = ifp->if_softc; 5368 5369 callout_stop(&sc->bge_timeout); 5370 5371 /* Disable host interrupts. */ 5372 PCI_SETBIT(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MISC_CTL, 5373 BGE_PCIMISCCTL_MASK_PCI_INTR); 5374 bge_writembx_flush(sc, BGE_MBX_IRQ0_LO, 1); 5375 5376 /* 5377 * Tell firmware we're shutting down. 5378 */ 5379 bge_stop_fw(sc); 5380 bge_sig_pre_reset(sc, BGE_RESET_SHUTDOWN); 5381 5382 /* 5383 * Disable all of the receiver blocks. 5384 */ 5385 bge_stop_block(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE); 5386 bge_stop_block(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 5387 bge_stop_block(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 5388 if (BGE_IS_5700_FAMILY(sc)) 5389 bge_stop_block(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 5390 bge_stop_block(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE); 5391 bge_stop_block(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 5392 bge_stop_block(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE); 5393 5394 /* 5395 * Disable all of the transmit blocks. 5396 */ 5397 bge_stop_block(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 5398 bge_stop_block(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 5399 bge_stop_block(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 5400 bge_stop_block(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE); 5401 bge_stop_block(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE); 5402 if (BGE_IS_5700_FAMILY(sc)) 5403 bge_stop_block(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 5404 bge_stop_block(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 5405 5406 BGE_CLRBIT_FLUSH(sc, BGE_MAC_MODE, BGE_MACMODE_TXDMA_ENB); 5407 delay(40); 5408 5409 bge_stop_block(sc, BGE_TX_MODE, BGE_TXMODE_ENABLE); 5410 5411 /* 5412 * Shut down all of the memory managers and related 5413 * state machines. 5414 */ 5415 bge_stop_block(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE); 5416 bge_stop_block(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE); 5417 if (BGE_IS_5700_FAMILY(sc)) 5418 bge_stop_block(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 5419 5420 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 5421 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 5422 5423 if (BGE_IS_5700_FAMILY(sc)) { 5424 bge_stop_block(sc, BGE_BMAN_MODE, BGE_BMANMODE_ENABLE); 5425 bge_stop_block(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 5426 } 5427 5428 bge_reset(sc); 5429 bge_sig_legacy(sc, BGE_RESET_SHUTDOWN); 5430 bge_sig_post_reset(sc, BGE_RESET_SHUTDOWN); 5431 5432 /* 5433 * Keep the ASF firmware running if up. 5434 */ 5435 if (sc->bge_asf_mode & ASF_STACKUP) 5436 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 5437 else 5438 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 5439 5440 /* Free the RX lists. */ 5441 bge_free_rx_ring_std(sc); 5442 5443 /* Free jumbo RX list. */ 5444 if (BGE_IS_JUMBO_CAPABLE(sc)) 5445 bge_free_rx_ring_jumbo(sc); 5446 5447 /* Free TX buffers. */ 5448 bge_free_tx_ring(sc); 5449 5450 /* 5451 * Isolate/power down the PHY. 5452 */ 5453 if (!(sc->bge_flags & BGE_PHY_FIBER_TBI)) 5454 mii_down(&sc->bge_mii); 5455 5456 sc->bge_tx_saved_considx = BGE_TXCONS_UNSET; 5457 5458 /* Clear MAC's link state (PHY may still have link UP). */ 5459 BGE_STS_CLRBIT(sc, BGE_STS_LINK); 5460 5461 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 5462 } 5463 5464 static void 5465 bge_link_upd(struct bge_softc *sc) 5466 { 5467 struct ifnet *ifp = &sc->ethercom.ec_if; 5468 struct mii_data *mii = &sc->bge_mii; 5469 uint32_t status; 5470 int link; 5471 5472 /* Clear 'pending link event' flag */ 5473 BGE_STS_CLRBIT(sc, BGE_STS_LINK_EVT); 5474 5475 /* 5476 * Process link state changes. 5477 * Grrr. The link status word in the status block does 5478 * not work correctly on the BCM5700 rev AX and BX chips, 5479 * according to all available information. Hence, we have 5480 * to enable MII interrupts in order to properly obtain 5481 * async link changes. Unfortunately, this also means that 5482 * we have to read the MAC status register to detect link 5483 * changes, thereby adding an additional register access to 5484 * the interrupt handler. 5485 */ 5486 5487 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700) { 5488 status = CSR_READ_4(sc, BGE_MAC_STS); 5489 if (status & BGE_MACSTAT_MI_INTERRUPT) { 5490 mii_pollstat(mii); 5491 5492 if (!BGE_STS_BIT(sc, BGE_STS_LINK) && 5493 mii->mii_media_status & IFM_ACTIVE && 5494 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) 5495 BGE_STS_SETBIT(sc, BGE_STS_LINK); 5496 else if (BGE_STS_BIT(sc, BGE_STS_LINK) && 5497 (!(mii->mii_media_status & IFM_ACTIVE) || 5498 IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) 5499 BGE_STS_CLRBIT(sc, BGE_STS_LINK); 5500 5501 /* Clear the interrupt */ 5502 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, 5503 BGE_EVTENB_MI_INTERRUPT); 5504 bge_miibus_readreg(sc->bge_dev, sc->bge_phy_addr, 5505 BRGPHY_MII_ISR); 5506 bge_miibus_writereg(sc->bge_dev, sc->bge_phy_addr, 5507 BRGPHY_MII_IMR, BRGPHY_INTRS); 5508 } 5509 return; 5510 } 5511 5512 if (sc->bge_flags & BGE_PHY_FIBER_TBI) { 5513 status = CSR_READ_4(sc, BGE_MAC_STS); 5514 if (status & BGE_MACSTAT_TBI_PCS_SYNCHED) { 5515 if (!BGE_STS_BIT(sc, BGE_STS_LINK)) { 5516 BGE_STS_SETBIT(sc, BGE_STS_LINK); 5517 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) 5518 BGE_CLRBIT(sc, BGE_MAC_MODE, 5519 BGE_MACMODE_TBI_SEND_CFGS); 5520 CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF); 5521 if_link_state_change(ifp, LINK_STATE_UP); 5522 } 5523 } else if (BGE_STS_BIT(sc, BGE_STS_LINK)) { 5524 BGE_STS_CLRBIT(sc, BGE_STS_LINK); 5525 if_link_state_change(ifp, LINK_STATE_DOWN); 5526 } 5527 /* 5528 * Discard link events for MII/GMII cards if MI auto-polling disabled. 5529 * This should not happen since mii callouts are locked now, but 5530 * we keep this check for debug. 5531 */ 5532 } else if (BGE_STS_BIT(sc, BGE_STS_AUTOPOLL)) { 5533 /* 5534 * Some broken BCM chips have BGE_STATFLAG_LINKSTATE_CHANGED 5535 * bit in status word always set. Workaround this bug by 5536 * reading PHY link status directly. 5537 */ 5538 link = (CSR_READ_4(sc, BGE_MI_STS) & BGE_MISTS_LINK)? 5539 BGE_STS_LINK : 0; 5540 5541 if (BGE_STS_BIT(sc, BGE_STS_LINK) != link) { 5542 mii_pollstat(mii); 5543 5544 if (!BGE_STS_BIT(sc, BGE_STS_LINK) && 5545 mii->mii_media_status & IFM_ACTIVE && 5546 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) 5547 BGE_STS_SETBIT(sc, BGE_STS_LINK); 5548 else if (BGE_STS_BIT(sc, BGE_STS_LINK) && 5549 (!(mii->mii_media_status & IFM_ACTIVE) || 5550 IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) 5551 BGE_STS_CLRBIT(sc, BGE_STS_LINK); 5552 } 5553 } 5554 5555 /* Clear the attention */ 5556 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED| 5557 BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE| 5558 BGE_MACSTAT_LINK_CHANGED); 5559 } 5560 5561 static int 5562 bge_sysctl_verify(SYSCTLFN_ARGS) 5563 { 5564 int error, t; 5565 struct sysctlnode node; 5566 5567 node = *rnode; 5568 t = *(int*)rnode->sysctl_data; 5569 node.sysctl_data = &t; 5570 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 5571 if (error || newp == NULL) 5572 return error; 5573 5574 #if 0 5575 DPRINTF2(("%s: t = %d, nodenum = %d, rnodenum = %d\n", __func__, t, 5576 node.sysctl_num, rnode->sysctl_num)); 5577 #endif 5578 5579 if (node.sysctl_num == bge_rxthresh_nodenum) { 5580 if (t < 0 || t >= NBGE_RX_THRESH) 5581 return EINVAL; 5582 bge_update_all_threshes(t); 5583 } else 5584 return EINVAL; 5585 5586 *(int*)rnode->sysctl_data = t; 5587 5588 return 0; 5589 } 5590 5591 /* 5592 * Set up sysctl(3) MIB, hw.bge.*. 5593 */ 5594 static void 5595 bge_sysctl_init(struct bge_softc *sc) 5596 { 5597 int rc, bge_root_num; 5598 const struct sysctlnode *node; 5599 5600 if ((rc = sysctl_createv(&sc->bge_log, 0, NULL, NULL, 5601 CTLFLAG_PERMANENT, CTLTYPE_NODE, "hw", NULL, 5602 NULL, 0, NULL, 0, CTL_HW, CTL_EOL)) != 0) { 5603 goto out; 5604 } 5605 5606 if ((rc = sysctl_createv(&sc->bge_log, 0, NULL, &node, 5607 0, CTLTYPE_NODE, "bge", 5608 SYSCTL_DESCR("BGE interface controls"), 5609 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL)) != 0) { 5610 goto out; 5611 } 5612 5613 bge_root_num = node->sysctl_num; 5614 5615 /* BGE Rx interrupt mitigation level */ 5616 if ((rc = sysctl_createv(&sc->bge_log, 0, NULL, &node, 5617 CTLFLAG_READWRITE, 5618 CTLTYPE_INT, "rx_lvl", 5619 SYSCTL_DESCR("BGE receive interrupt mitigation level"), 5620 bge_sysctl_verify, 0, 5621 &bge_rx_thresh_lvl, 5622 0, CTL_HW, bge_root_num, CTL_CREATE, 5623 CTL_EOL)) != 0) { 5624 goto out; 5625 } 5626 5627 bge_rxthresh_nodenum = node->sysctl_num; 5628 5629 return; 5630 5631 out: 5632 aprint_error("%s: sysctl_createv failed (rc = %d)\n", __func__, rc); 5633 } 5634 5635 #ifdef BGE_DEBUG 5636 void 5637 bge_debug_info(struct bge_softc *sc) 5638 { 5639 5640 printf("Hardware Flags:\n"); 5641 if (BGE_IS_57765_PLUS(sc)) 5642 printf(" - 57765 Plus\n"); 5643 if (BGE_IS_5717_PLUS(sc)) 5644 printf(" - 5717 Plus\n"); 5645 if (BGE_IS_5755_PLUS(sc)) 5646 printf(" - 5755 Plus\n"); 5647 if (BGE_IS_575X_PLUS(sc)) 5648 printf(" - 575X Plus\n"); 5649 if (BGE_IS_5705_PLUS(sc)) 5650 printf(" - 5705 Plus\n"); 5651 if (BGE_IS_5714_FAMILY(sc)) 5652 printf(" - 5714 Family\n"); 5653 if (BGE_IS_5700_FAMILY(sc)) 5654 printf(" - 5700 Family\n"); 5655 if (sc->bge_flags & BGE_IS_5788) 5656 printf(" - 5788\n"); 5657 if (sc->bge_flags & BGE_JUMBO_CAPABLE) 5658 printf(" - Supports Jumbo Frames\n"); 5659 if (sc->bge_flags & BGE_NO_EEPROM) 5660 printf(" - No EEPROM\n"); 5661 if (sc->bge_flags & BGE_PCIX) 5662 printf(" - PCI-X Bus\n"); 5663 if (sc->bge_flags & BGE_PCIE) 5664 printf(" - PCI Express Bus\n"); 5665 if (sc->bge_flags & BGE_NO_3LED) 5666 printf(" - No 3 LEDs\n"); 5667 if (sc->bge_flags & BGE_RX_ALIGNBUG) 5668 printf(" - RX Alignment Bug\n"); 5669 if (sc->bge_flags & BGE_APE) 5670 printf(" - APE\n"); 5671 if (sc->bge_flags & BGE_CPMU_PRESENT) 5672 printf(" - CPMU\n"); 5673 if (sc->bge_flags & BGE_TSO) 5674 printf(" - TSO\n"); 5675 } 5676 #endif /* BGE_DEBUG */ 5677 5678 static int 5679 bge_get_eaddr_fw(struct bge_softc *sc, uint8_t ether_addr[]) 5680 { 5681 prop_dictionary_t dict; 5682 prop_data_t ea; 5683 5684 if ((sc->bge_flags & BGE_NO_EEPROM) == 0) 5685 return 1; 5686 5687 dict = device_properties(sc->bge_dev); 5688 ea = prop_dictionary_get(dict, "mac-address"); 5689 if (ea != NULL) { 5690 KASSERT(prop_object_type(ea) == PROP_TYPE_DATA); 5691 KASSERT(prop_data_size(ea) == ETHER_ADDR_LEN); 5692 memcpy(ether_addr, prop_data_data_nocopy(ea), ETHER_ADDR_LEN); 5693 return 0; 5694 } 5695 5696 return 1; 5697 } 5698 5699 static int 5700 bge_get_eaddr_mem(struct bge_softc *sc, uint8_t ether_addr[]) 5701 { 5702 uint32_t mac_addr; 5703 5704 mac_addr = bge_readmem_ind(sc, BGE_SRAM_MAC_ADDR_HIGH_MB); 5705 if ((mac_addr >> 16) == 0x484b) { 5706 ether_addr[0] = (uint8_t)(mac_addr >> 8); 5707 ether_addr[1] = (uint8_t)mac_addr; 5708 mac_addr = bge_readmem_ind(sc, BGE_SRAM_MAC_ADDR_LOW_MB); 5709 ether_addr[2] = (uint8_t)(mac_addr >> 24); 5710 ether_addr[3] = (uint8_t)(mac_addr >> 16); 5711 ether_addr[4] = (uint8_t)(mac_addr >> 8); 5712 ether_addr[5] = (uint8_t)mac_addr; 5713 return 0; 5714 } 5715 return 1; 5716 } 5717 5718 static int 5719 bge_get_eaddr_nvram(struct bge_softc *sc, uint8_t ether_addr[]) 5720 { 5721 int mac_offset = BGE_EE_MAC_OFFSET; 5722 5723 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 5724 mac_offset = BGE_EE_MAC_OFFSET_5906; 5725 5726 return (bge_read_nvram(sc, ether_addr, mac_offset + 2, 5727 ETHER_ADDR_LEN)); 5728 } 5729 5730 static int 5731 bge_get_eaddr_eeprom(struct bge_softc *sc, uint8_t ether_addr[]) 5732 { 5733 5734 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 5735 return 1; 5736 5737 return (bge_read_eeprom(sc, ether_addr, BGE_EE_MAC_OFFSET + 2, 5738 ETHER_ADDR_LEN)); 5739 } 5740 5741 static int 5742 bge_get_eaddr(struct bge_softc *sc, uint8_t eaddr[]) 5743 { 5744 static const bge_eaddr_fcn_t bge_eaddr_funcs[] = { 5745 /* NOTE: Order is critical */ 5746 bge_get_eaddr_fw, 5747 bge_get_eaddr_mem, 5748 bge_get_eaddr_nvram, 5749 bge_get_eaddr_eeprom, 5750 NULL 5751 }; 5752 const bge_eaddr_fcn_t *func; 5753 5754 for (func = bge_eaddr_funcs; *func != NULL; ++func) { 5755 if ((*func)(sc, eaddr) == 0) 5756 break; 5757 } 5758 return (*func == NULL ? ENXIO : 0); 5759 } 5760
Indexes created Thu Sep 25 02:09:54 GMT 2025