if_bge.c revision 1.218
1 /* $NetBSD: if_bge.c,v 1.218 2013/03/19 02:56:16 msaitoh Exp $ */ 2 3 /* 4 * Copyright (c) 2001 Wind River Systems 5 * Copyright (c) 1997, 1998, 1999, 2001 6 * Bill Paul <wpaul (at) windriver.com>. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Bill Paul. 19 * 4. Neither the name of the author nor the names of any co-contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 33 * THE POSSIBILITY OF SUCH DAMAGE. 34 * 35 * $FreeBSD: if_bge.c,v 1.13 2002/04/04 06:01:31 wpaul Exp $ 36 */ 37 38 /* 39 * Broadcom BCM570x family gigabit ethernet driver for NetBSD. 40 * 41 * NetBSD version by: 42 * 43 * Frank van der Linden <fvdl (at) wasabisystems.com> 44 * Jason Thorpe <thorpej (at) wasabisystems.com> 45 * Jonathan Stone <jonathan (at) dsg.stanford.edu> 46 * 47 * Originally written for FreeBSD by Bill Paul <wpaul (at) windriver.com> 48 * Senior Engineer, Wind River Systems 49 */ 50 51 /* 52 * The Broadcom BCM5700 is based on technology originally developed by 53 * Alteon Networks as part of the Tigon I and Tigon II gigabit ethernet 54 * MAC chips. The BCM5700, sometimes referred to as the Tigon III, has 55 * two on-board MIPS R4000 CPUs and can have as much as 16MB of external 56 * SSRAM. The BCM5700 supports TCP, UDP and IP checksum offload, jumbo 57 * frames, highly configurable RX filtering, and 16 RX and TX queues 58 * (which, along with RX filter rules, can be used for QOS applications). 59 * Other features, such as TCP segmentation, may be available as part 60 * of value-added firmware updates. Unlike the Tigon I and Tigon II, 61 * firmware images can be stored in hardware and need not be compiled 62 * into the driver. 63 * 64 * The BCM5700 supports the PCI v2.2 and PCI-X v1.0 standards, and will 65 * function in a 32-bit/64-bit 33/66MHz bus, or a 64-bit/133MHz bus. 66 * 67 * The BCM5701 is a single-chip solution incorporating both the BCM5700 68 * MAC and a BCM5401 10/100/1000 PHY. Unlike the BCM5700, the BCM5701 69 * does not support external SSRAM. 70 * 71 * Broadcom also produces a variation of the BCM5700 under the "Altima" 72 * brand name, which is functionally similar but lacks PCI-X support. 73 * 74 * Without external SSRAM, you can only have at most 4 TX rings, 75 * and the use of the mini RX ring is disabled. This seems to imply 76 * that these features are simply not available on the BCM5701. As a 77 * result, this driver does not implement any support for the mini RX 78 * ring. 79 */ 80 81 #include <sys/cdefs.h> 82 __KERNEL_RCSID(0, "$NetBSD: if_bge.c,v 1.218 2013/03/19 02:56:16 msaitoh Exp $"); 83 84 #include "vlan.h" 85 86 #include <sys/param.h> 87 #include <sys/systm.h> 88 #include <sys/callout.h> 89 #include <sys/sockio.h> 90 #include <sys/mbuf.h> 91 #include <sys/malloc.h> 92 #include <sys/kernel.h> 93 #include <sys/device.h> 94 #include <sys/socket.h> 95 #include <sys/sysctl.h> 96 97 #include <net/if.h> 98 #include <net/if_dl.h> 99 #include <net/if_media.h> 100 #include <net/if_ether.h> 101 102 #include <sys/rnd.h> 103 104 #ifdef INET 105 #include <netinet/in.h> 106 #include <netinet/in_systm.h> 107 #include <netinet/in_var.h> 108 #include <netinet/ip.h> 109 #endif 110 111 /* Headers for TCP Segmentation Offload (TSO) */ 112 #include <netinet/in_systm.h> /* n_time for <netinet/ip.h>... */ 113 #include <netinet/in.h> /* ip_{src,dst}, for <netinet/ip.h> */ 114 #include <netinet/ip.h> /* for struct ip */ 115 #include <netinet/tcp.h> /* for struct tcphdr */ 116 117 118 #include <net/bpf.h> 119 120 #include <dev/pci/pcireg.h> 121 #include <dev/pci/pcivar.h> 122 #include <dev/pci/pcidevs.h> 123 124 #include <dev/mii/mii.h> 125 #include <dev/mii/miivar.h> 126 #include <dev/mii/miidevs.h> 127 #include <dev/mii/brgphyreg.h> 128 129 #include <dev/pci/if_bgereg.h> 130 #include <dev/pci/if_bgevar.h> 131 132 #include <prop/proplib.h> 133 134 #define ETHER_MIN_NOPAD (ETHER_MIN_LEN - ETHER_CRC_LEN) /* i.e., 60 */ 135 136 137 /* 138 * Tunable thresholds for rx-side bge interrupt mitigation. 139 */ 140 141 /* 142 * The pairs of values below were obtained from empirical measurement 143 * on bcm5700 rev B2; they ar designed to give roughly 1 receive 144 * interrupt for every N packets received, where N is, approximately, 145 * the second value (rx_max_bds) in each pair. The values are chosen 146 * such that moving from one pair to the succeeding pair was observed 147 * to roughly halve interrupt rate under sustained input packet load. 148 * The values were empirically chosen to avoid overflowing internal 149 * limits on the bcm5700: increasing rx_ticks much beyond 600 150 * results in internal wrapping and higher interrupt rates. 151 * The limit of 46 frames was chosen to match NFS workloads. 152 * 153 * These values also work well on bcm5701, bcm5704C, and (less 154 * tested) bcm5703. On other chipsets, (including the Altima chip 155 * family), the larger values may overflow internal chip limits, 156 * leading to increasing interrupt rates rather than lower interrupt 157 * rates. 158 * 159 * Applications using heavy interrupt mitigation (interrupting every 160 * 32 or 46 frames) in both directions may need to increase the TCP 161 * windowsize to above 131072 bytes (e.g., to 199608 bytes) to sustain 162 * full link bandwidth, due to ACKs and window updates lingering 163 * in the RX queue during the 30-to-40-frame interrupt-mitigation window. 164 */ 165 static const struct bge_load_rx_thresh { 166 int rx_ticks; 167 int rx_max_bds; } 168 bge_rx_threshes[] = { 169 { 16, 1 }, /* rx_max_bds = 1 disables interrupt mitigation */ 170 { 32, 2 }, 171 { 50, 4 }, 172 { 100, 8 }, 173 { 192, 16 }, 174 { 416, 32 }, 175 { 598, 46 } 176 }; 177 #define NBGE_RX_THRESH (sizeof(bge_rx_threshes) / sizeof(bge_rx_threshes[0])) 178 179 /* XXX patchable; should be sysctl'able */ 180 static int bge_auto_thresh = 1; 181 static int bge_rx_thresh_lvl; 182 183 static int bge_rxthresh_nodenum; 184 185 typedef int (*bge_eaddr_fcn_t)(struct bge_softc *, uint8_t[]); 186 187 static uint32_t bge_chipid(const struct pci_attach_args *pa); 188 static int bge_probe(device_t, cfdata_t, void *); 189 static void bge_attach(device_t, device_t, void *); 190 static void bge_release_resources(struct bge_softc *); 191 192 static int bge_get_eaddr_fw(struct bge_softc *, uint8_t[]); 193 static int bge_get_eaddr_mem(struct bge_softc *, uint8_t[]); 194 static int bge_get_eaddr_nvram(struct bge_softc *, uint8_t[]); 195 static int bge_get_eaddr_eeprom(struct bge_softc *, uint8_t[]); 196 static int bge_get_eaddr(struct bge_softc *, uint8_t[]); 197 198 static void bge_txeof(struct bge_softc *); 199 static void bge_rxeof(struct bge_softc *); 200 201 static void bge_asf_driver_up (struct bge_softc *); 202 static void bge_tick(void *); 203 static void bge_stats_update(struct bge_softc *); 204 static void bge_stats_update_regs(struct bge_softc *); 205 static int bge_encap(struct bge_softc *, struct mbuf *, uint32_t *); 206 207 static int bge_intr(void *); 208 static void bge_start(struct ifnet *); 209 static int bge_ifflags_cb(struct ethercom *); 210 static int bge_ioctl(struct ifnet *, u_long, void *); 211 static int bge_init(struct ifnet *); 212 static void bge_stop(struct ifnet *, int); 213 static void bge_watchdog(struct ifnet *); 214 static int bge_ifmedia_upd(struct ifnet *); 215 static void bge_ifmedia_sts(struct ifnet *, struct ifmediareq *); 216 217 static uint8_t bge_nvram_getbyte(struct bge_softc *, int, uint8_t *); 218 static int bge_read_nvram(struct bge_softc *, uint8_t *, int, int); 219 220 static uint8_t bge_eeprom_getbyte(struct bge_softc *, int, uint8_t *); 221 static int bge_read_eeprom(struct bge_softc *, void *, int, int); 222 static void bge_setmulti(struct bge_softc *); 223 224 static void bge_handle_events(struct bge_softc *); 225 static int bge_alloc_jumbo_mem(struct bge_softc *); 226 #if 0 /* XXX */ 227 static void bge_free_jumbo_mem(struct bge_softc *); 228 #endif 229 static void *bge_jalloc(struct bge_softc *); 230 static void bge_jfree(struct mbuf *, void *, size_t, void *); 231 static int bge_newbuf_std(struct bge_softc *, int, struct mbuf *, 232 bus_dmamap_t); 233 static int bge_newbuf_jumbo(struct bge_softc *, int, struct mbuf *); 234 static int bge_init_rx_ring_std(struct bge_softc *); 235 static void bge_free_rx_ring_std(struct bge_softc *); 236 static int bge_init_rx_ring_jumbo(struct bge_softc *); 237 static void bge_free_rx_ring_jumbo(struct bge_softc *); 238 static void bge_free_tx_ring(struct bge_softc *); 239 static int bge_init_tx_ring(struct bge_softc *); 240 241 static int bge_chipinit(struct bge_softc *); 242 static int bge_blockinit(struct bge_softc *); 243 static int bge_phy_addr(struct bge_softc *); 244 static uint32_t bge_readmem_ind(struct bge_softc *, int); 245 static void bge_writemem_ind(struct bge_softc *, int, int); 246 static void bge_writembx(struct bge_softc *, int, int); 247 static void bge_writembx_flush(struct bge_softc *, int, int); 248 static void bge_writemem_direct(struct bge_softc *, int, int); 249 static void bge_writereg_ind(struct bge_softc *, int, int); 250 static void bge_set_max_readrq(struct bge_softc *); 251 252 static int bge_miibus_readreg(device_t, int, int); 253 static void bge_miibus_writereg(device_t, int, int, int); 254 static void bge_miibus_statchg(struct ifnet *); 255 256 #define BGE_RESET_SHUTDOWN 0 257 #define BGE_RESET_START 1 258 #define BGE_RESET_SUSPEND 2 259 static void bge_sig_post_reset(struct bge_softc *, int); 260 static void bge_sig_legacy(struct bge_softc *, int); 261 static void bge_sig_pre_reset(struct bge_softc *, int); 262 static void bge_wait_for_event_ack(struct bge_softc *); 263 static void bge_stop_fw(struct bge_softc *); 264 static int bge_reset(struct bge_softc *); 265 static void bge_link_upd(struct bge_softc *); 266 static void bge_sysctl_init(struct bge_softc *); 267 static int bge_sysctl_verify(SYSCTLFN_PROTO); 268 269 static void bge_ape_lock_init(struct bge_softc *); 270 static void bge_ape_read_fw_ver(struct bge_softc *); 271 static int bge_ape_lock(struct bge_softc *, int); 272 static void bge_ape_unlock(struct bge_softc *, int); 273 static void bge_ape_send_event(struct bge_softc *, uint32_t); 274 static void bge_ape_driver_state_change(struct bge_softc *, int); 275 276 #ifdef BGE_DEBUG 277 #define DPRINTF(x) if (bgedebug) printf x 278 #define DPRINTFN(n,x) if (bgedebug >= (n)) printf x 279 #define BGE_TSO_PRINTF(x) do { if (bge_tso_debug) printf x ;} while (0) 280 int bgedebug = 0; 281 int bge_tso_debug = 0; 282 void bge_debug_info(struct bge_softc *); 283 #else 284 #define DPRINTF(x) 285 #define DPRINTFN(n,x) 286 #define BGE_TSO_PRINTF(x) 287 #endif 288 289 #ifdef BGE_EVENT_COUNTERS 290 #define BGE_EVCNT_INCR(ev) (ev).ev_count++ 291 #define BGE_EVCNT_ADD(ev, val) (ev).ev_count += (val) 292 #define BGE_EVCNT_UPD(ev, val) (ev).ev_count = (val) 293 #else 294 #define BGE_EVCNT_INCR(ev) /* nothing */ 295 #define BGE_EVCNT_ADD(ev, val) /* nothing */ 296 #define BGE_EVCNT_UPD(ev, val) /* nothing */ 297 #endif 298 299 static const struct bge_product { 300 pci_vendor_id_t bp_vendor; 301 pci_product_id_t bp_product; 302 const char *bp_name; 303 } bge_products[] = { 304 /* 305 * The BCM5700 documentation seems to indicate that the hardware 306 * still has the Alteon vendor ID burned into it, though it 307 * should always be overridden by the value in the EEPROM. We'll 308 * check for it anyway. 309 */ 310 { PCI_VENDOR_ALTEON, 311 PCI_PRODUCT_ALTEON_BCM5700, 312 "Broadcom BCM5700 Gigabit Ethernet", 313 }, 314 { PCI_VENDOR_ALTEON, 315 PCI_PRODUCT_ALTEON_BCM5701, 316 "Broadcom BCM5701 Gigabit Ethernet", 317 }, 318 { PCI_VENDOR_ALTIMA, 319 PCI_PRODUCT_ALTIMA_AC1000, 320 "Altima AC1000 Gigabit Ethernet", 321 }, 322 { PCI_VENDOR_ALTIMA, 323 PCI_PRODUCT_ALTIMA_AC1001, 324 "Altima AC1001 Gigabit Ethernet", 325 }, 326 { PCI_VENDOR_ALTIMA, 327 PCI_PRODUCT_ALTIMA_AC1003, 328 "Altima AC1003 Gigabit Ethernet", 329 }, 330 { PCI_VENDOR_ALTIMA, 331 PCI_PRODUCT_ALTIMA_AC9100, 332 "Altima AC9100 Gigabit Ethernet", 333 }, 334 { PCI_VENDOR_APPLE, 335 PCI_PRODUCT_APPLE_BCM5701, 336 "APPLE BCM5701 Gigabit Ethernet", 337 }, 338 { PCI_VENDOR_BROADCOM, 339 PCI_PRODUCT_BROADCOM_BCM5700, 340 "Broadcom BCM5700 Gigabit Ethernet", 341 }, 342 { PCI_VENDOR_BROADCOM, 343 PCI_PRODUCT_BROADCOM_BCM5701, 344 "Broadcom BCM5701 Gigabit Ethernet", 345 }, 346 { PCI_VENDOR_BROADCOM, 347 PCI_PRODUCT_BROADCOM_BCM5702, 348 "Broadcom BCM5702 Gigabit Ethernet", 349 }, 350 { PCI_VENDOR_BROADCOM, 351 PCI_PRODUCT_BROADCOM_BCM5702X, 352 "Broadcom BCM5702X Gigabit Ethernet" }, 353 { PCI_VENDOR_BROADCOM, 354 PCI_PRODUCT_BROADCOM_BCM5703, 355 "Broadcom BCM5703 Gigabit Ethernet", 356 }, 357 { PCI_VENDOR_BROADCOM, 358 PCI_PRODUCT_BROADCOM_BCM5703X, 359 "Broadcom BCM5703X Gigabit Ethernet", 360 }, 361 { PCI_VENDOR_BROADCOM, 362 PCI_PRODUCT_BROADCOM_BCM5703_ALT, 363 "Broadcom BCM5703 Gigabit Ethernet", 364 }, 365 { PCI_VENDOR_BROADCOM, 366 PCI_PRODUCT_BROADCOM_BCM5704C, 367 "Broadcom BCM5704C Dual Gigabit Ethernet", 368 }, 369 { PCI_VENDOR_BROADCOM, 370 PCI_PRODUCT_BROADCOM_BCM5704S, 371 "Broadcom BCM5704S Dual Gigabit Ethernet", 372 }, 373 { PCI_VENDOR_BROADCOM, 374 PCI_PRODUCT_BROADCOM_BCM5705, 375 "Broadcom BCM5705 Gigabit Ethernet", 376 }, 377 { PCI_VENDOR_BROADCOM, 378 PCI_PRODUCT_BROADCOM_BCM5705F, 379 "Broadcom BCM5705F Gigabit Ethernet", 380 }, 381 { PCI_VENDOR_BROADCOM, 382 PCI_PRODUCT_BROADCOM_BCM5705K, 383 "Broadcom BCM5705K Gigabit Ethernet", 384 }, 385 { PCI_VENDOR_BROADCOM, 386 PCI_PRODUCT_BROADCOM_BCM5705M, 387 "Broadcom BCM5705M Gigabit Ethernet", 388 }, 389 { PCI_VENDOR_BROADCOM, 390 PCI_PRODUCT_BROADCOM_BCM5705M_ALT, 391 "Broadcom BCM5705M Gigabit Ethernet", 392 }, 393 { PCI_VENDOR_BROADCOM, 394 PCI_PRODUCT_BROADCOM_BCM5714, 395 "Broadcom BCM5714 Gigabit Ethernet", 396 }, 397 { PCI_VENDOR_BROADCOM, 398 PCI_PRODUCT_BROADCOM_BCM5714S, 399 "Broadcom BCM5714S Gigabit Ethernet", 400 }, 401 { PCI_VENDOR_BROADCOM, 402 PCI_PRODUCT_BROADCOM_BCM5715, 403 "Broadcom BCM5715 Gigabit Ethernet", 404 }, 405 { PCI_VENDOR_BROADCOM, 406 PCI_PRODUCT_BROADCOM_BCM5715S, 407 "Broadcom BCM5715S Gigabit Ethernet", 408 }, 409 { PCI_VENDOR_BROADCOM, 410 PCI_PRODUCT_BROADCOM_BCM5717, 411 "Broadcom BCM5717 Gigabit Ethernet", 412 }, 413 { PCI_VENDOR_BROADCOM, 414 PCI_PRODUCT_BROADCOM_BCM5718, 415 "Broadcom BCM5718 Gigabit Ethernet", 416 }, 417 { PCI_VENDOR_BROADCOM, 418 PCI_PRODUCT_BROADCOM_BCM5719, 419 "Broadcom BCM5719 Gigabit Ethernet", 420 }, 421 { PCI_VENDOR_BROADCOM, 422 PCI_PRODUCT_BROADCOM_BCM5720, 423 "Broadcom BCM5720 Gigabit Ethernet", 424 }, 425 { PCI_VENDOR_BROADCOM, 426 PCI_PRODUCT_BROADCOM_BCM5721, 427 "Broadcom BCM5721 Gigabit Ethernet", 428 }, 429 { PCI_VENDOR_BROADCOM, 430 PCI_PRODUCT_BROADCOM_BCM5722, 431 "Broadcom BCM5722 Gigabit Ethernet", 432 }, 433 { PCI_VENDOR_BROADCOM, 434 PCI_PRODUCT_BROADCOM_BCM5723, 435 "Broadcom BCM5723 Gigabit Ethernet", 436 }, 437 { PCI_VENDOR_BROADCOM, 438 PCI_PRODUCT_BROADCOM_BCM5724, 439 "Broadcom BCM5724 Gigabit Ethernet", 440 }, 441 { PCI_VENDOR_BROADCOM, 442 PCI_PRODUCT_BROADCOM_BCM5750, 443 "Broadcom BCM5750 Gigabit Ethernet", 444 }, 445 { PCI_VENDOR_BROADCOM, 446 PCI_PRODUCT_BROADCOM_BCM5750M, 447 "Broadcom BCM5750M Gigabit Ethernet", 448 }, 449 { PCI_VENDOR_BROADCOM, 450 PCI_PRODUCT_BROADCOM_BCM5751, 451 "Broadcom BCM5751 Gigabit Ethernet", 452 }, 453 { PCI_VENDOR_BROADCOM, 454 PCI_PRODUCT_BROADCOM_BCM5751F, 455 "Broadcom BCM5751F Gigabit Ethernet", 456 }, 457 { PCI_VENDOR_BROADCOM, 458 PCI_PRODUCT_BROADCOM_BCM5751M, 459 "Broadcom BCM5751M Gigabit Ethernet", 460 }, 461 { PCI_VENDOR_BROADCOM, 462 PCI_PRODUCT_BROADCOM_BCM5752, 463 "Broadcom BCM5752 Gigabit Ethernet", 464 }, 465 { PCI_VENDOR_BROADCOM, 466 PCI_PRODUCT_BROADCOM_BCM5752M, 467 "Broadcom BCM5752M Gigabit Ethernet", 468 }, 469 { PCI_VENDOR_BROADCOM, 470 PCI_PRODUCT_BROADCOM_BCM5753, 471 "Broadcom BCM5753 Gigabit Ethernet", 472 }, 473 { PCI_VENDOR_BROADCOM, 474 PCI_PRODUCT_BROADCOM_BCM5753F, 475 "Broadcom BCM5753F Gigabit Ethernet", 476 }, 477 { PCI_VENDOR_BROADCOM, 478 PCI_PRODUCT_BROADCOM_BCM5753M, 479 "Broadcom BCM5753M Gigabit Ethernet", 480 }, 481 { PCI_VENDOR_BROADCOM, 482 PCI_PRODUCT_BROADCOM_BCM5754, 483 "Broadcom BCM5754 Gigabit Ethernet", 484 }, 485 { PCI_VENDOR_BROADCOM, 486 PCI_PRODUCT_BROADCOM_BCM5754M, 487 "Broadcom BCM5754M Gigabit Ethernet", 488 }, 489 { PCI_VENDOR_BROADCOM, 490 PCI_PRODUCT_BROADCOM_BCM5755, 491 "Broadcom BCM5755 Gigabit Ethernet", 492 }, 493 { PCI_VENDOR_BROADCOM, 494 PCI_PRODUCT_BROADCOM_BCM5755M, 495 "Broadcom BCM5755M Gigabit Ethernet", 496 }, 497 { PCI_VENDOR_BROADCOM, 498 PCI_PRODUCT_BROADCOM_BCM5756, 499 "Broadcom BCM5756 Gigabit Ethernet", 500 }, 501 { PCI_VENDOR_BROADCOM, 502 PCI_PRODUCT_BROADCOM_BCM5761, 503 "Broadcom BCM5761 Gigabit Ethernet", 504 }, 505 { PCI_VENDOR_BROADCOM, 506 PCI_PRODUCT_BROADCOM_BCM5761E, 507 "Broadcom BCM5761E Gigabit Ethernet", 508 }, 509 { PCI_VENDOR_BROADCOM, 510 PCI_PRODUCT_BROADCOM_BCM5761S, 511 "Broadcom BCM5761S Gigabit Ethernet", 512 }, 513 { PCI_VENDOR_BROADCOM, 514 PCI_PRODUCT_BROADCOM_BCM5761SE, 515 "Broadcom BCM5761SE Gigabit Ethernet", 516 }, 517 { PCI_VENDOR_BROADCOM, 518 PCI_PRODUCT_BROADCOM_BCM5764, 519 "Broadcom BCM5764 Gigabit Ethernet", 520 }, 521 { PCI_VENDOR_BROADCOM, 522 PCI_PRODUCT_BROADCOM_BCM5780, 523 "Broadcom BCM5780 Gigabit Ethernet", 524 }, 525 { PCI_VENDOR_BROADCOM, 526 PCI_PRODUCT_BROADCOM_BCM5780S, 527 "Broadcom BCM5780S Gigabit Ethernet", 528 }, 529 { PCI_VENDOR_BROADCOM, 530 PCI_PRODUCT_BROADCOM_BCM5781, 531 "Broadcom BCM5781 Gigabit Ethernet", 532 }, 533 { PCI_VENDOR_BROADCOM, 534 PCI_PRODUCT_BROADCOM_BCM5782, 535 "Broadcom BCM5782 Gigabit Ethernet", 536 }, 537 { PCI_VENDOR_BROADCOM, 538 PCI_PRODUCT_BROADCOM_BCM5784M, 539 "BCM5784M NetLink 1000baseT Ethernet", 540 }, 541 { PCI_VENDOR_BROADCOM, 542 PCI_PRODUCT_BROADCOM_BCM5785F, 543 "BCM5785F NetLink 10/100 Ethernet", 544 }, 545 { PCI_VENDOR_BROADCOM, 546 PCI_PRODUCT_BROADCOM_BCM5785G, 547 "BCM5785G NetLink 1000baseT Ethernet", 548 }, 549 { PCI_VENDOR_BROADCOM, 550 PCI_PRODUCT_BROADCOM_BCM5786, 551 "Broadcom BCM5786 Gigabit Ethernet", 552 }, 553 { PCI_VENDOR_BROADCOM, 554 PCI_PRODUCT_BROADCOM_BCM5787, 555 "Broadcom BCM5787 Gigabit Ethernet", 556 }, 557 { PCI_VENDOR_BROADCOM, 558 PCI_PRODUCT_BROADCOM_BCM5787F, 559 "Broadcom BCM5787F 10/100 Ethernet", 560 }, 561 { PCI_VENDOR_BROADCOM, 562 PCI_PRODUCT_BROADCOM_BCM5787M, 563 "Broadcom BCM5787M Gigabit Ethernet", 564 }, 565 { PCI_VENDOR_BROADCOM, 566 PCI_PRODUCT_BROADCOM_BCM5788, 567 "Broadcom BCM5788 Gigabit Ethernet", 568 }, 569 { PCI_VENDOR_BROADCOM, 570 PCI_PRODUCT_BROADCOM_BCM5789, 571 "Broadcom BCM5789 Gigabit Ethernet", 572 }, 573 { PCI_VENDOR_BROADCOM, 574 PCI_PRODUCT_BROADCOM_BCM5901, 575 "Broadcom BCM5901 Fast Ethernet", 576 }, 577 { PCI_VENDOR_BROADCOM, 578 PCI_PRODUCT_BROADCOM_BCM5901A2, 579 "Broadcom BCM5901A2 Fast Ethernet", 580 }, 581 { PCI_VENDOR_BROADCOM, 582 PCI_PRODUCT_BROADCOM_BCM5903M, 583 "Broadcom BCM5903M Fast Ethernet", 584 }, 585 { PCI_VENDOR_BROADCOM, 586 PCI_PRODUCT_BROADCOM_BCM5906, 587 "Broadcom BCM5906 Fast Ethernet", 588 }, 589 { PCI_VENDOR_BROADCOM, 590 PCI_PRODUCT_BROADCOM_BCM5906M, 591 "Broadcom BCM5906M Fast Ethernet", 592 }, 593 { PCI_VENDOR_BROADCOM, 594 PCI_PRODUCT_BROADCOM_BCM57760, 595 "Broadcom BCM57760 Fast Ethernet", 596 }, 597 { PCI_VENDOR_BROADCOM, 598 PCI_PRODUCT_BROADCOM_BCM57761, 599 "Broadcom BCM57761 Fast Ethernet", 600 }, 601 { PCI_VENDOR_BROADCOM, 602 PCI_PRODUCT_BROADCOM_BCM57762, 603 "Broadcom BCM57762 Gigabit Ethernet", 604 }, 605 { PCI_VENDOR_BROADCOM, 606 PCI_PRODUCT_BROADCOM_BCM57765, 607 "Broadcom BCM57765 Fast Ethernet", 608 }, 609 { PCI_VENDOR_BROADCOM, 610 PCI_PRODUCT_BROADCOM_BCM57766, 611 "Broadcom BCM57766 Fast Ethernet", 612 }, 613 { PCI_VENDOR_BROADCOM, 614 PCI_PRODUCT_BROADCOM_BCM57780, 615 "Broadcom BCM57780 Fast Ethernet", 616 }, 617 { PCI_VENDOR_BROADCOM, 618 PCI_PRODUCT_BROADCOM_BCM57781, 619 "Broadcom BCM57781 Fast Ethernet", 620 }, 621 { PCI_VENDOR_BROADCOM, 622 PCI_PRODUCT_BROADCOM_BCM57782, 623 "Broadcom BCM57782 Fast Ethernet", 624 }, 625 { PCI_VENDOR_BROADCOM, 626 PCI_PRODUCT_BROADCOM_BCM57785, 627 "Broadcom BCM57785 Fast Ethernet", 628 }, 629 { PCI_VENDOR_BROADCOM, 630 PCI_PRODUCT_BROADCOM_BCM57786, 631 "Broadcom BCM57786 Fast Ethernet", 632 }, 633 { PCI_VENDOR_BROADCOM, 634 PCI_PRODUCT_BROADCOM_BCM57788, 635 "Broadcom BCM57788 Fast Ethernet", 636 }, 637 { PCI_VENDOR_BROADCOM, 638 PCI_PRODUCT_BROADCOM_BCM57790, 639 "Broadcom BCM57790 Fast Ethernet", 640 }, 641 { PCI_VENDOR_BROADCOM, 642 PCI_PRODUCT_BROADCOM_BCM57791, 643 "Broadcom BCM57791 Fast Ethernet", 644 }, 645 { PCI_VENDOR_BROADCOM, 646 PCI_PRODUCT_BROADCOM_BCM57795, 647 "Broadcom BCM57795 Fast Ethernet", 648 }, 649 { PCI_VENDOR_SCHNEIDERKOCH, 650 PCI_PRODUCT_SCHNEIDERKOCH_SK_9DX1, 651 "SysKonnect SK-9Dx1 Gigabit Ethernet", 652 }, 653 { PCI_VENDOR_3COM, 654 PCI_PRODUCT_3COM_3C996, 655 "3Com 3c996 Gigabit Ethernet", 656 }, 657 { PCI_VENDOR_FUJITSU4, 658 PCI_PRODUCT_FUJITSU4_PW008GE4, 659 "Fujitsu PW008GE4 Gigabit Ethernet", 660 }, 661 { PCI_VENDOR_FUJITSU4, 662 PCI_PRODUCT_FUJITSU4_PW008GE5, 663 "Fujitsu PW008GE5 Gigabit Ethernet", 664 }, 665 { PCI_VENDOR_FUJITSU4, 666 PCI_PRODUCT_FUJITSU4_PP250_450_LAN, 667 "Fujitsu Primepower 250/450 Gigabit Ethernet", 668 }, 669 { 0, 670 0, 671 NULL }, 672 }; 673 674 #define BGE_IS_JUMBO_CAPABLE(sc) ((sc)->bge_flags & BGE_JUMBO_CAPABLE) 675 #define BGE_IS_5700_FAMILY(sc) ((sc)->bge_flags & BGE_5700_FAMILY) 676 #define BGE_IS_5705_PLUS(sc) ((sc)->bge_flags & BGE_5705_PLUS) 677 #define BGE_IS_5714_FAMILY(sc) ((sc)->bge_flags & BGE_5714_FAMILY) 678 #define BGE_IS_575X_PLUS(sc) ((sc)->bge_flags & BGE_575X_PLUS) 679 #define BGE_IS_5755_PLUS(sc) ((sc)->bge_flags & BGE_5755_PLUS) 680 #define BGE_IS_5717_PLUS(sc) ((sc)->bge_flags & BGE_5717_PLUS) 681 #define BGE_IS_57765_PLUS(sc) ((sc)->bge_flags & BGE_57765_PLUS) 682 683 static const struct bge_revision { 684 uint32_t br_chipid; 685 const char *br_name; 686 } bge_revisions[] = { 687 { BGE_CHIPID_BCM5700_A0, "BCM5700 A0" }, 688 { BGE_CHIPID_BCM5700_A1, "BCM5700 A1" }, 689 { BGE_CHIPID_BCM5700_B0, "BCM5700 B0" }, 690 { BGE_CHIPID_BCM5700_B1, "BCM5700 B1" }, 691 { BGE_CHIPID_BCM5700_B2, "BCM5700 B2" }, 692 { BGE_CHIPID_BCM5700_B3, "BCM5700 B3" }, 693 { BGE_CHIPID_BCM5700_ALTIMA, "BCM5700 Altima" }, 694 { BGE_CHIPID_BCM5700_C0, "BCM5700 C0" }, 695 { BGE_CHIPID_BCM5701_A0, "BCM5701 A0" }, 696 { BGE_CHIPID_BCM5701_B0, "BCM5701 B0" }, 697 { BGE_CHIPID_BCM5701_B2, "BCM5701 B2" }, 698 { BGE_CHIPID_BCM5701_B5, "BCM5701 B5" }, 699 { BGE_CHIPID_BCM5703_A0, "BCM5702/5703 A0" }, 700 { BGE_CHIPID_BCM5703_A1, "BCM5702/5703 A1" }, 701 { BGE_CHIPID_BCM5703_A2, "BCM5702/5703 A2" }, 702 { BGE_CHIPID_BCM5703_A3, "BCM5702/5703 A3" }, 703 { BGE_CHIPID_BCM5703_B0, "BCM5702/5703 B0" }, 704 { BGE_CHIPID_BCM5704_A0, "BCM5704 A0" }, 705 { BGE_CHIPID_BCM5704_A1, "BCM5704 A1" }, 706 { BGE_CHIPID_BCM5704_A2, "BCM5704 A2" }, 707 { BGE_CHIPID_BCM5704_A3, "BCM5704 A3" }, 708 { BGE_CHIPID_BCM5704_B0, "BCM5704 B0" }, 709 { BGE_CHIPID_BCM5705_A0, "BCM5705 A0" }, 710 { BGE_CHIPID_BCM5705_A1, "BCM5705 A1" }, 711 { BGE_CHIPID_BCM5705_A2, "BCM5705 A2" }, 712 { BGE_CHIPID_BCM5705_A3, "BCM5705 A3" }, 713 { BGE_CHIPID_BCM5750_A0, "BCM5750 A0" }, 714 { BGE_CHIPID_BCM5750_A1, "BCM5750 A1" }, 715 { BGE_CHIPID_BCM5750_A3, "BCM5750 A3" }, 716 { BGE_CHIPID_BCM5750_B0, "BCM5750 B0" }, 717 { BGE_CHIPID_BCM5750_B1, "BCM5750 B1" }, 718 { BGE_CHIPID_BCM5750_C0, "BCM5750 C0" }, 719 { BGE_CHIPID_BCM5750_C1, "BCM5750 C1" }, 720 { BGE_CHIPID_BCM5750_C2, "BCM5750 C2" }, 721 { BGE_CHIPID_BCM5752_A0, "BCM5752 A0" }, 722 { BGE_CHIPID_BCM5752_A1, "BCM5752 A1" }, 723 { BGE_CHIPID_BCM5752_A2, "BCM5752 A2" }, 724 { BGE_CHIPID_BCM5714_A0, "BCM5714 A0" }, 725 { BGE_CHIPID_BCM5714_B0, "BCM5714 B0" }, 726 { BGE_CHIPID_BCM5714_B3, "BCM5714 B3" }, 727 { BGE_CHIPID_BCM5715_A0, "BCM5715 A0" }, 728 { BGE_CHIPID_BCM5715_A1, "BCM5715 A1" }, 729 { BGE_CHIPID_BCM5715_A3, "BCM5715 A3" }, 730 { BGE_CHIPID_BCM5717_A0, "BCM5717 A0" }, 731 { BGE_CHIPID_BCM5717_B0, "BCM5717 B0" }, 732 { BGE_CHIPID_BCM5719_A0, "BCM5719 A0" }, 733 { BGE_CHIPID_BCM5720_A0, "BCM5720 A0" }, 734 { BGE_CHIPID_BCM5755_A0, "BCM5755 A0" }, 735 { BGE_CHIPID_BCM5755_A1, "BCM5755 A1" }, 736 { BGE_CHIPID_BCM5755_A2, "BCM5755 A2" }, 737 { BGE_CHIPID_BCM5755_C0, "BCM5755 C0" }, 738 { BGE_CHIPID_BCM5761_A0, "BCM5761 A0" }, 739 { BGE_CHIPID_BCM5761_A1, "BCM5761 A1" }, 740 { BGE_CHIPID_BCM5784_A0, "BCM5784 A0" }, 741 { BGE_CHIPID_BCM5784_A1, "BCM5784 A1" }, 742 /* 5754 and 5787 share the same ASIC ID */ 743 { BGE_CHIPID_BCM5787_A0, "BCM5754/5787 A0" }, 744 { BGE_CHIPID_BCM5787_A1, "BCM5754/5787 A1" }, 745 { BGE_CHIPID_BCM5787_A2, "BCM5754/5787 A2" }, 746 { BGE_CHIPID_BCM5906_A0, "BCM5906 A0" }, 747 { BGE_CHIPID_BCM5906_A1, "BCM5906 A1" }, 748 { BGE_CHIPID_BCM5906_A2, "BCM5906 A2" }, 749 { BGE_CHIPID_BCM57765_A0, "BCM57765 A0" }, 750 { BGE_CHIPID_BCM57765_B0, "BCM57765 B0" }, 751 { BGE_CHIPID_BCM57780_A0, "BCM57780 A0" }, 752 { BGE_CHIPID_BCM57780_A1, "BCM57780 A1" }, 753 754 { 0, NULL } 755 }; 756 757 /* 758 * Some defaults for major revisions, so that newer steppings 759 * that we don't know about have a shot at working. 760 */ 761 static const struct bge_revision bge_majorrevs[] = { 762 { BGE_ASICREV_BCM5700, "unknown BCM5700" }, 763 { BGE_ASICREV_BCM5701, "unknown BCM5701" }, 764 { BGE_ASICREV_BCM5703, "unknown BCM5703" }, 765 { BGE_ASICREV_BCM5704, "unknown BCM5704" }, 766 { BGE_ASICREV_BCM5705, "unknown BCM5705" }, 767 { BGE_ASICREV_BCM5750, "unknown BCM5750" }, 768 { BGE_ASICREV_BCM5714, "unknown BCM5714" }, 769 { BGE_ASICREV_BCM5714_A0, "unknown BCM5714" }, 770 { BGE_ASICREV_BCM5752, "unknown BCM5752" }, 771 { BGE_ASICREV_BCM5780, "unknown BCM5780" }, 772 { BGE_ASICREV_BCM5755, "unknown BCM5755" }, 773 { BGE_ASICREV_BCM5761, "unknown BCM5761" }, 774 { BGE_ASICREV_BCM5784, "unknown BCM5784" }, 775 { BGE_ASICREV_BCM5785, "unknown BCM5785" }, 776 /* 5754 and 5787 share the same ASIC ID */ 777 { BGE_ASICREV_BCM5787, "unknown BCM5754/5787" }, 778 { BGE_ASICREV_BCM5906, "unknown BCM5906" }, 779 { BGE_ASICREV_BCM57765, "unknown BCM57765" }, 780 { BGE_ASICREV_BCM57766, "unknown BCM57766" }, 781 { BGE_ASICREV_BCM57780, "unknown BCM57780" }, 782 { BGE_ASICREV_BCM5717, "unknown BCM5717" }, 783 { BGE_ASICREV_BCM5719, "unknown BCM5719" }, 784 { BGE_ASICREV_BCM5720, "unknown BCM5720" }, 785 786 { 0, NULL } 787 }; 788 789 static int bge_allow_asf = 1; 790 791 CFATTACH_DECL_NEW(bge, sizeof(struct bge_softc), 792 bge_probe, bge_attach, NULL, NULL); 793 794 static uint32_t 795 bge_readmem_ind(struct bge_softc *sc, int off) 796 { 797 pcireg_t val; 798 799 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906 && 800 off >= BGE_STATS_BLOCK && off < BGE_SEND_RING_1_TO_4) 801 return 0; 802 803 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_BASEADDR, off); 804 val = pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_DATA); 805 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_BASEADDR, 0); 806 return val; 807 } 808 809 static void 810 bge_writemem_ind(struct bge_softc *sc, int off, int val) 811 { 812 813 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_BASEADDR, off); 814 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_DATA, val); 815 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_BASEADDR, 0); 816 } 817 818 /* 819 * PCI Express only 820 */ 821 static void 822 bge_set_max_readrq(struct bge_softc *sc) 823 { 824 pcireg_t val; 825 826 val = pci_conf_read(sc->sc_pc, sc->sc_pcitag, sc->bge_pciecap 827 + PCI_PCIE_DCSR); 828 val &= ~PCI_PCIE_DCSR_MAX_READ_REQ; 829 switch (sc->bge_expmrq) { 830 case 2048: 831 val |= BGE_PCIE_DEVCTL_MAX_READRQ_2048; 832 break; 833 case 4096: 834 val |= BGE_PCIE_DEVCTL_MAX_READRQ_4096; 835 break; 836 default: 837 panic("incorrect expmrq value(%d)", sc->bge_expmrq); 838 break; 839 } 840 pci_conf_write(sc->sc_pc, sc->sc_pcitag, sc->bge_pciecap 841 + PCI_PCIE_DCSR, val); 842 } 843 844 #ifdef notdef 845 static uint32_t 846 bge_readreg_ind(struct bge_softc *sc, int off) 847 { 848 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_REG_BASEADDR, off); 849 return (pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_REG_DATA)); 850 } 851 #endif 852 853 static void 854 bge_writereg_ind(struct bge_softc *sc, int off, int val) 855 { 856 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_REG_BASEADDR, off); 857 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_REG_DATA, val); 858 } 859 860 static void 861 bge_writemem_direct(struct bge_softc *sc, int off, int val) 862 { 863 CSR_WRITE_4(sc, off, val); 864 } 865 866 static void 867 bge_writembx(struct bge_softc *sc, int off, int val) 868 { 869 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 870 off += BGE_LPMBX_IRQ0_HI - BGE_MBX_IRQ0_HI; 871 872 CSR_WRITE_4(sc, off, val); 873 } 874 875 static void 876 bge_writembx_flush(struct bge_softc *sc, int off, int val) 877 { 878 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 879 off += BGE_LPMBX_IRQ0_HI - BGE_MBX_IRQ0_HI; 880 881 CSR_WRITE_4_FLUSH(sc, off, val); 882 } 883 884 /* 885 * Clear all stale locks and select the lock for this driver instance. 886 */ 887 void 888 bge_ape_lock_init(struct bge_softc *sc) 889 { 890 struct pci_attach_args *pa = &(sc->bge_pa); 891 uint32_t bit, regbase; 892 int i; 893 894 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761) 895 regbase = BGE_APE_LOCK_GRANT; 896 else 897 regbase = BGE_APE_PER_LOCK_GRANT; 898 899 /* Clear any stale locks. */ 900 for (i = BGE_APE_LOCK_PHY0; i <= BGE_APE_LOCK_GPIO; i++) { 901 switch (i) { 902 case BGE_APE_LOCK_PHY0: 903 case BGE_APE_LOCK_PHY1: 904 case BGE_APE_LOCK_PHY2: 905 case BGE_APE_LOCK_PHY3: 906 bit = BGE_APE_LOCK_GRANT_DRIVER0; 907 break; 908 default: 909 if (pa->pa_function != 0) 910 bit = BGE_APE_LOCK_GRANT_DRIVER0; 911 else 912 bit = (1 << pa->pa_function); 913 } 914 APE_WRITE_4(sc, regbase + 4 * i, bit); 915 } 916 917 /* Select the PHY lock based on the device's function number. */ 918 switch (pa->pa_function) { 919 case 0: 920 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY0; 921 break; 922 case 1: 923 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY1; 924 break; 925 case 2: 926 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY2; 927 break; 928 case 3: 929 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY3; 930 break; 931 default: 932 printf("%s: PHY lock not supported on function\n", 933 device_xname(sc->bge_dev)); 934 break; 935 } 936 } 937 938 /* 939 * Check for APE firmware, set flags, and print version info. 940 */ 941 void 942 bge_ape_read_fw_ver(struct bge_softc *sc) 943 { 944 const char *fwtype; 945 uint32_t apedata, features; 946 947 /* Check for a valid APE signature in shared memory. */ 948 apedata = APE_READ_4(sc, BGE_APE_SEG_SIG); 949 if (apedata != BGE_APE_SEG_SIG_MAGIC) { 950 sc->bge_mfw_flags &= ~ BGE_MFW_ON_APE; 951 return; 952 } 953 954 /* Check if APE firmware is running. */ 955 apedata = APE_READ_4(sc, BGE_APE_FW_STATUS); 956 if ((apedata & BGE_APE_FW_STATUS_READY) == 0) { 957 printf("%s: APE signature found but FW status not ready! " 958 "0x%08x\n", device_xname(sc->bge_dev), apedata); 959 return; 960 } 961 962 sc->bge_mfw_flags |= BGE_MFW_ON_APE; 963 964 /* Fetch the APE firwmare type and version. */ 965 apedata = APE_READ_4(sc, BGE_APE_FW_VERSION); 966 features = APE_READ_4(sc, BGE_APE_FW_FEATURES); 967 if ((features & BGE_APE_FW_FEATURE_NCSI) != 0) { 968 sc->bge_mfw_flags |= BGE_MFW_TYPE_NCSI; 969 fwtype = "NCSI"; 970 } else if ((features & BGE_APE_FW_FEATURE_DASH) != 0) { 971 sc->bge_mfw_flags |= BGE_MFW_TYPE_DASH; 972 fwtype = "DASH"; 973 } else 974 fwtype = "UNKN"; 975 976 /* Print the APE firmware version. */ 977 printf(", APE firmware %s %d.%d.%d.%d", fwtype, 978 (apedata & BGE_APE_FW_VERSION_MAJMSK) >> BGE_APE_FW_VERSION_MAJSFT, 979 (apedata & BGE_APE_FW_VERSION_MINMSK) >> BGE_APE_FW_VERSION_MINSFT, 980 (apedata & BGE_APE_FW_VERSION_REVMSK) >> BGE_APE_FW_VERSION_REVSFT, 981 (apedata & BGE_APE_FW_VERSION_BLDMSK)); 982 } 983 984 int 985 bge_ape_lock(struct bge_softc *sc, int locknum) 986 { 987 struct pci_attach_args *pa = &(sc->bge_pa); 988 uint32_t bit, gnt, req, status; 989 int i, off; 990 991 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0) 992 return (0); 993 994 /* Lock request/grant registers have different bases. */ 995 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761) { 996 req = BGE_APE_LOCK_REQ; 997 gnt = BGE_APE_LOCK_GRANT; 998 } else { 999 req = BGE_APE_PER_LOCK_REQ; 1000 gnt = BGE_APE_PER_LOCK_GRANT; 1001 } 1002 1003 off = 4 * locknum; 1004 1005 switch (locknum) { 1006 case BGE_APE_LOCK_GPIO: 1007 /* Lock required when using GPIO. */ 1008 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761) 1009 return (0); 1010 if (pa->pa_function == 0) 1011 bit = BGE_APE_LOCK_REQ_DRIVER0; 1012 else 1013 bit = (1 << pa->pa_function); 1014 break; 1015 case BGE_APE_LOCK_GRC: 1016 /* Lock required to reset the device. */ 1017 if (pa->pa_function == 0) 1018 bit = BGE_APE_LOCK_REQ_DRIVER0; 1019 else 1020 bit = (1 << pa->pa_function); 1021 break; 1022 case BGE_APE_LOCK_MEM: 1023 /* Lock required when accessing certain APE memory. */ 1024 if (pa->pa_function == 0) 1025 bit = BGE_APE_LOCK_REQ_DRIVER0; 1026 else 1027 bit = (1 << pa->pa_function); 1028 break; 1029 case BGE_APE_LOCK_PHY0: 1030 case BGE_APE_LOCK_PHY1: 1031 case BGE_APE_LOCK_PHY2: 1032 case BGE_APE_LOCK_PHY3: 1033 /* Lock required when accessing PHYs. */ 1034 bit = BGE_APE_LOCK_REQ_DRIVER0; 1035 break; 1036 default: 1037 return (EINVAL); 1038 } 1039 1040 /* Request a lock. */ 1041 APE_WRITE_4_FLUSH(sc, req + off, bit); 1042 1043 /* Wait up to 1 second to acquire lock. */ 1044 for (i = 0; i < 20000; i++) { 1045 status = APE_READ_4(sc, gnt + off); 1046 if (status == bit) 1047 break; 1048 DELAY(50); 1049 } 1050 1051 /* Handle any errors. */ 1052 if (status != bit) { 1053 printf("%s: APE lock %d request failed! " 1054 "request = 0x%04x[0x%04x], status = 0x%04x[0x%04x]\n", 1055 device_xname(sc->bge_dev), 1056 locknum, req + off, bit & 0xFFFF, gnt + off, 1057 status & 0xFFFF); 1058 /* Revoke the lock request. */ 1059 APE_WRITE_4(sc, gnt + off, bit); 1060 return (EBUSY); 1061 } 1062 1063 return (0); 1064 } 1065 1066 void 1067 bge_ape_unlock(struct bge_softc *sc, int locknum) 1068 { 1069 struct pci_attach_args *pa = &(sc->bge_pa); 1070 uint32_t bit, gnt; 1071 int off; 1072 1073 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0) 1074 return; 1075 1076 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761) 1077 gnt = BGE_APE_LOCK_GRANT; 1078 else 1079 gnt = BGE_APE_PER_LOCK_GRANT; 1080 1081 off = 4 * locknum; 1082 1083 switch (locknum) { 1084 case BGE_APE_LOCK_GPIO: 1085 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761) 1086 return; 1087 if (pa->pa_function == 0) 1088 bit = BGE_APE_LOCK_GRANT_DRIVER0; 1089 else 1090 bit = (1 << pa->pa_function); 1091 break; 1092 case BGE_APE_LOCK_GRC: 1093 if (pa->pa_function == 0) 1094 bit = BGE_APE_LOCK_GRANT_DRIVER0; 1095 else 1096 bit = (1 << pa->pa_function); 1097 break; 1098 case BGE_APE_LOCK_MEM: 1099 if (pa->pa_function == 0) 1100 bit = BGE_APE_LOCK_GRANT_DRIVER0; 1101 else 1102 bit = (1 << pa->pa_function); 1103 break; 1104 case BGE_APE_LOCK_PHY0: 1105 case BGE_APE_LOCK_PHY1: 1106 case BGE_APE_LOCK_PHY2: 1107 case BGE_APE_LOCK_PHY3: 1108 bit = BGE_APE_LOCK_GRANT_DRIVER0; 1109 break; 1110 default: 1111 return; 1112 } 1113 1114 /* Write and flush for consecutive bge_ape_lock() */ 1115 APE_WRITE_4_FLUSH(sc, gnt + off, bit); 1116 } 1117 1118 /* 1119 * Send an event to the APE firmware. 1120 */ 1121 void 1122 bge_ape_send_event(struct bge_softc *sc, uint32_t event) 1123 { 1124 uint32_t apedata; 1125 int i; 1126 1127 /* NCSI does not support APE events. */ 1128 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0) 1129 return; 1130 1131 /* Wait up to 1ms for APE to service previous event. */ 1132 for (i = 10; i > 0; i--) { 1133 if (bge_ape_lock(sc, BGE_APE_LOCK_MEM) != 0) 1134 break; 1135 apedata = APE_READ_4(sc, BGE_APE_EVENT_STATUS); 1136 if ((apedata & BGE_APE_EVENT_STATUS_EVENT_PENDING) == 0) { 1137 APE_WRITE_4(sc, BGE_APE_EVENT_STATUS, event | 1138 BGE_APE_EVENT_STATUS_EVENT_PENDING); 1139 bge_ape_unlock(sc, BGE_APE_LOCK_MEM); 1140 APE_WRITE_4(sc, BGE_APE_EVENT, BGE_APE_EVENT_1); 1141 break; 1142 } 1143 bge_ape_unlock(sc, BGE_APE_LOCK_MEM); 1144 DELAY(100); 1145 } 1146 if (i == 0) { 1147 printf("%s: APE event 0x%08x send timed out\n", 1148 device_xname(sc->bge_dev), event); 1149 } 1150 } 1151 1152 void 1153 bge_ape_driver_state_change(struct bge_softc *sc, int kind) 1154 { 1155 uint32_t apedata, event; 1156 1157 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0) 1158 return; 1159 1160 switch (kind) { 1161 case BGE_RESET_START: 1162 /* If this is the first load, clear the load counter. */ 1163 apedata = APE_READ_4(sc, BGE_APE_HOST_SEG_SIG); 1164 if (apedata != BGE_APE_HOST_SEG_SIG_MAGIC) 1165 APE_WRITE_4(sc, BGE_APE_HOST_INIT_COUNT, 0); 1166 else { 1167 apedata = APE_READ_4(sc, BGE_APE_HOST_INIT_COUNT); 1168 APE_WRITE_4(sc, BGE_APE_HOST_INIT_COUNT, ++apedata); 1169 } 1170 APE_WRITE_4(sc, BGE_APE_HOST_SEG_SIG, 1171 BGE_APE_HOST_SEG_SIG_MAGIC); 1172 APE_WRITE_4(sc, BGE_APE_HOST_SEG_LEN, 1173 BGE_APE_HOST_SEG_LEN_MAGIC); 1174 1175 /* Add some version info if bge(4) supports it. */ 1176 APE_WRITE_4(sc, BGE_APE_HOST_DRIVER_ID, 1177 BGE_APE_HOST_DRIVER_ID_MAGIC(1, 0)); 1178 APE_WRITE_4(sc, BGE_APE_HOST_BEHAVIOR, 1179 BGE_APE_HOST_BEHAV_NO_PHYLOCK); 1180 APE_WRITE_4(sc, BGE_APE_HOST_HEARTBEAT_INT_MS, 1181 BGE_APE_HOST_HEARTBEAT_INT_DISABLE); 1182 APE_WRITE_4(sc, BGE_APE_HOST_DRVR_STATE, 1183 BGE_APE_HOST_DRVR_STATE_START); 1184 event = BGE_APE_EVENT_STATUS_STATE_START; 1185 break; 1186 case BGE_RESET_SHUTDOWN: 1187 APE_WRITE_4(sc, BGE_APE_HOST_DRVR_STATE, 1188 BGE_APE_HOST_DRVR_STATE_UNLOAD); 1189 event = BGE_APE_EVENT_STATUS_STATE_UNLOAD; 1190 break; 1191 case BGE_RESET_SUSPEND: 1192 event = BGE_APE_EVENT_STATUS_STATE_SUSPEND; 1193 break; 1194 default: 1195 return; 1196 } 1197 1198 bge_ape_send_event(sc, event | BGE_APE_EVENT_STATUS_DRIVER_EVNT | 1199 BGE_APE_EVENT_STATUS_STATE_CHNGE); 1200 } 1201 1202 static uint8_t 1203 bge_nvram_getbyte(struct bge_softc *sc, int addr, uint8_t *dest) 1204 { 1205 uint32_t access, byte = 0; 1206 int i; 1207 1208 /* Lock. */ 1209 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_SET1); 1210 for (i = 0; i < 8000; i++) { 1211 if (CSR_READ_4(sc, BGE_NVRAM_SWARB) & BGE_NVRAMSWARB_GNT1) 1212 break; 1213 DELAY(20); 1214 } 1215 if (i == 8000) 1216 return 1; 1217 1218 /* Enable access. */ 1219 access = CSR_READ_4(sc, BGE_NVRAM_ACCESS); 1220 CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access | BGE_NVRAMACC_ENABLE); 1221 1222 CSR_WRITE_4(sc, BGE_NVRAM_ADDR, addr & 0xfffffffc); 1223 CSR_WRITE_4(sc, BGE_NVRAM_CMD, BGE_NVRAM_READCMD); 1224 for (i = 0; i < BGE_TIMEOUT * 10; i++) { 1225 DELAY(10); 1226 if (CSR_READ_4(sc, BGE_NVRAM_CMD) & BGE_NVRAMCMD_DONE) { 1227 DELAY(10); 1228 break; 1229 } 1230 } 1231 1232 if (i == BGE_TIMEOUT * 10) { 1233 aprint_error_dev(sc->bge_dev, "nvram read timed out\n"); 1234 return 1; 1235 } 1236 1237 /* Get result. */ 1238 byte = CSR_READ_4(sc, BGE_NVRAM_RDDATA); 1239 1240 *dest = (bswap32(byte) >> ((addr % 4) * 8)) & 0xFF; 1241 1242 /* Disable access. */ 1243 CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access); 1244 1245 /* Unlock. */ 1246 CSR_WRITE_4_FLUSH(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_CLR1); 1247 1248 return 0; 1249 } 1250 1251 /* 1252 * Read a sequence of bytes from NVRAM. 1253 */ 1254 static int 1255 bge_read_nvram(struct bge_softc *sc, uint8_t *dest, int off, int cnt) 1256 { 1257 int error = 0, i; 1258 uint8_t byte = 0; 1259 1260 if (BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5906) 1261 return 1; 1262 1263 for (i = 0; i < cnt; i++) { 1264 error = bge_nvram_getbyte(sc, off + i, &byte); 1265 if (error) 1266 break; 1267 *(dest + i) = byte; 1268 } 1269 1270 return (error ? 1 : 0); 1271 } 1272 1273 /* 1274 * Read a byte of data stored in the EEPROM at address 'addr.' The 1275 * BCM570x supports both the traditional bitbang interface and an 1276 * auto access interface for reading the EEPROM. We use the auto 1277 * access method. 1278 */ 1279 static uint8_t 1280 bge_eeprom_getbyte(struct bge_softc *sc, int addr, uint8_t *dest) 1281 { 1282 int i; 1283 uint32_t byte = 0; 1284 1285 /* 1286 * Enable use of auto EEPROM access so we can avoid 1287 * having to use the bitbang method. 1288 */ 1289 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM); 1290 1291 /* Reset the EEPROM, load the clock period. */ 1292 CSR_WRITE_4(sc, BGE_EE_ADDR, 1293 BGE_EEADDR_RESET | BGE_EEHALFCLK(BGE_HALFCLK_384SCL)); 1294 DELAY(20); 1295 1296 /* Issue the read EEPROM command. */ 1297 CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr); 1298 1299 /* Wait for completion */ 1300 for (i = 0; i < BGE_TIMEOUT * 10; i++) { 1301 DELAY(10); 1302 if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE) 1303 break; 1304 } 1305 1306 if (i == BGE_TIMEOUT * 10) { 1307 aprint_error_dev(sc->bge_dev, "eeprom read timed out\n"); 1308 return 1; 1309 } 1310 1311 /* Get result. */ 1312 byte = CSR_READ_4(sc, BGE_EE_DATA); 1313 1314 *dest = (byte >> ((addr % 4) * 8)) & 0xFF; 1315 1316 return 0; 1317 } 1318 1319 /* 1320 * Read a sequence of bytes from the EEPROM. 1321 */ 1322 static int 1323 bge_read_eeprom(struct bge_softc *sc, void *destv, int off, int cnt) 1324 { 1325 int error = 0, i; 1326 uint8_t byte = 0; 1327 char *dest = destv; 1328 1329 for (i = 0; i < cnt; i++) { 1330 error = bge_eeprom_getbyte(sc, off + i, &byte); 1331 if (error) 1332 break; 1333 *(dest + i) = byte; 1334 } 1335 1336 return (error ? 1 : 0); 1337 } 1338 1339 static int 1340 bge_miibus_readreg(device_t dev, int phy, int reg) 1341 { 1342 struct bge_softc *sc = device_private(dev); 1343 uint32_t val; 1344 uint32_t autopoll; 1345 int i; 1346 1347 if (bge_ape_lock(sc, sc->bge_phy_ape_lock) != 0) 1348 return 0; 1349 1350 /* Reading with autopolling on may trigger PCI errors */ 1351 autopoll = CSR_READ_4(sc, BGE_MI_MODE); 1352 if (autopoll & BGE_MIMODE_AUTOPOLL) { 1353 BGE_STS_CLRBIT(sc, BGE_STS_AUTOPOLL); 1354 BGE_CLRBIT_FLUSH(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 1355 DELAY(80); 1356 } 1357 1358 CSR_WRITE_4_FLUSH(sc, BGE_MI_COMM, BGE_MICMD_READ | BGE_MICOMM_BUSY | 1359 BGE_MIPHY(phy) | BGE_MIREG(reg)); 1360 1361 for (i = 0; i < BGE_TIMEOUT; i++) { 1362 delay(10); 1363 val = CSR_READ_4(sc, BGE_MI_COMM); 1364 if (!(val & BGE_MICOMM_BUSY)) { 1365 DELAY(5); 1366 val = CSR_READ_4(sc, BGE_MI_COMM); 1367 break; 1368 } 1369 } 1370 1371 if (i == BGE_TIMEOUT) { 1372 aprint_error_dev(sc->bge_dev, "PHY read timed out\n"); 1373 val = 0; 1374 goto done; 1375 } 1376 1377 done: 1378 if (autopoll & BGE_MIMODE_AUTOPOLL) { 1379 BGE_STS_SETBIT(sc, BGE_STS_AUTOPOLL); 1380 BGE_SETBIT_FLUSH(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 1381 DELAY(80); 1382 } 1383 1384 bge_ape_unlock(sc, sc->bge_phy_ape_lock); 1385 1386 if (val & BGE_MICOMM_READFAIL) 1387 return 0; 1388 1389 return (val & 0xFFFF); 1390 } 1391 1392 static void 1393 bge_miibus_writereg(device_t dev, int phy, int reg, int val) 1394 { 1395 struct bge_softc *sc = device_private(dev); 1396 uint32_t autopoll; 1397 int i; 1398 1399 if (bge_ape_lock(sc, sc->bge_phy_ape_lock) != 0) 1400 return; 1401 1402 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906 && 1403 (reg == BRGPHY_MII_1000CTL || reg == BRGPHY_MII_AUXCTL)) 1404 return; 1405 1406 /* Reading with autopolling on may trigger PCI errors */ 1407 autopoll = CSR_READ_4(sc, BGE_MI_MODE); 1408 if (autopoll & BGE_MIMODE_AUTOPOLL) { 1409 BGE_STS_CLRBIT(sc, BGE_STS_AUTOPOLL); 1410 BGE_CLRBIT_FLUSH(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 1411 DELAY(80); 1412 } 1413 1414 CSR_WRITE_4_FLUSH(sc, BGE_MI_COMM, BGE_MICMD_WRITE | BGE_MICOMM_BUSY | 1415 BGE_MIPHY(phy) | BGE_MIREG(reg) | val); 1416 1417 for (i = 0; i < BGE_TIMEOUT; i++) { 1418 delay(10); 1419 if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY)) { 1420 delay(5); 1421 CSR_READ_4(sc, BGE_MI_COMM); 1422 break; 1423 } 1424 } 1425 1426 if (autopoll & BGE_MIMODE_AUTOPOLL) { 1427 BGE_STS_SETBIT(sc, BGE_STS_AUTOPOLL); 1428 BGE_SETBIT_FLUSH(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 1429 delay(80); 1430 } 1431 1432 bge_ape_unlock(sc, sc->bge_phy_ape_lock); 1433 1434 if (i == BGE_TIMEOUT) 1435 aprint_error_dev(sc->bge_dev, "PHY read timed out\n"); 1436 } 1437 1438 static void 1439 bge_miibus_statchg(struct ifnet *ifp) 1440 { 1441 struct bge_softc *sc = ifp->if_softc; 1442 struct mii_data *mii = &sc->bge_mii; 1443 uint32_t mac_mode, rx_mode, tx_mode; 1444 1445 /* 1446 * Get flow control negotiation result. 1447 */ 1448 if (IFM_SUBTYPE(mii->mii_media.ifm_cur->ifm_media) == IFM_AUTO && 1449 (mii->mii_media_active & IFM_ETH_FMASK) != sc->bge_flowflags) { 1450 sc->bge_flowflags = mii->mii_media_active & IFM_ETH_FMASK; 1451 mii->mii_media_active &= ~IFM_ETH_FMASK; 1452 } 1453 1454 /* Set the port mode (MII/GMII) to match the link speed. */ 1455 mac_mode = CSR_READ_4(sc, BGE_MAC_MODE) & 1456 ~(BGE_MACMODE_PORTMODE | BGE_MACMODE_HALF_DUPLEX); 1457 tx_mode = CSR_READ_4(sc, BGE_TX_MODE); 1458 rx_mode = CSR_READ_4(sc, BGE_RX_MODE); 1459 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T || 1460 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX) 1461 mac_mode |= BGE_PORTMODE_GMII; 1462 else 1463 mac_mode |= BGE_PORTMODE_MII; 1464 1465 tx_mode &= ~BGE_TXMODE_FLOWCTL_ENABLE; 1466 rx_mode &= ~BGE_RXMODE_FLOWCTL_ENABLE; 1467 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 1468 if (sc->bge_flowflags & IFM_ETH_TXPAUSE) 1469 tx_mode |= BGE_TXMODE_FLOWCTL_ENABLE; 1470 if (sc->bge_flowflags & IFM_ETH_RXPAUSE) 1471 rx_mode |= BGE_RXMODE_FLOWCTL_ENABLE; 1472 } else 1473 mac_mode |= BGE_MACMODE_HALF_DUPLEX; 1474 1475 CSR_WRITE_4_FLUSH(sc, BGE_MAC_MODE, mac_mode); 1476 DELAY(40); 1477 CSR_WRITE_4(sc, BGE_TX_MODE, tx_mode); 1478 CSR_WRITE_4(sc, BGE_RX_MODE, rx_mode); 1479 } 1480 1481 /* 1482 * Update rx threshold levels to values in a particular slot 1483 * of the interrupt-mitigation table bge_rx_threshes. 1484 */ 1485 static void 1486 bge_set_thresh(struct ifnet *ifp, int lvl) 1487 { 1488 struct bge_softc *sc = ifp->if_softc; 1489 int s; 1490 1491 /* For now, just save the new Rx-intr thresholds and record 1492 * that a threshold update is pending. Updating the hardware 1493 * registers here (even at splhigh()) is observed to 1494 * occasionaly cause glitches where Rx-interrupts are not 1495 * honoured for up to 10 seconds. jonathan (at) NetBSD.org, 2003-04-05 1496 */ 1497 s = splnet(); 1498 sc->bge_rx_coal_ticks = bge_rx_threshes[lvl].rx_ticks; 1499 sc->bge_rx_max_coal_bds = bge_rx_threshes[lvl].rx_max_bds; 1500 sc->bge_pending_rxintr_change = 1; 1501 splx(s); 1502 } 1503 1504 1505 /* 1506 * Update Rx thresholds of all bge devices 1507 */ 1508 static void 1509 bge_update_all_threshes(int lvl) 1510 { 1511 struct ifnet *ifp; 1512 const char * const namebuf = "bge"; 1513 int namelen; 1514 1515 if (lvl < 0) 1516 lvl = 0; 1517 else if (lvl >= NBGE_RX_THRESH) 1518 lvl = NBGE_RX_THRESH - 1; 1519 1520 namelen = strlen(namebuf); 1521 /* 1522 * Now search all the interfaces for this name/number 1523 */ 1524 IFNET_FOREACH(ifp) { 1525 if (strncmp(ifp->if_xname, namebuf, namelen) != 0) 1526 continue; 1527 /* We got a match: update if doing auto-threshold-tuning */ 1528 if (bge_auto_thresh) 1529 bge_set_thresh(ifp, lvl); 1530 } 1531 } 1532 1533 /* 1534 * Handle events that have triggered interrupts. 1535 */ 1536 static void 1537 bge_handle_events(struct bge_softc *sc) 1538 { 1539 1540 return; 1541 } 1542 1543 /* 1544 * Memory management for jumbo frames. 1545 */ 1546 1547 static int 1548 bge_alloc_jumbo_mem(struct bge_softc *sc) 1549 { 1550 char *ptr, *kva; 1551 bus_dma_segment_t seg; 1552 int i, rseg, state, error; 1553 struct bge_jpool_entry *entry; 1554 1555 state = error = 0; 1556 1557 /* Grab a big chunk o' storage. */ 1558 if (bus_dmamem_alloc(sc->bge_dmatag, BGE_JMEM, PAGE_SIZE, 0, 1559 &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 1560 aprint_error_dev(sc->bge_dev, "can't alloc rx buffers\n"); 1561 return ENOBUFS; 1562 } 1563 1564 state = 1; 1565 if (bus_dmamem_map(sc->bge_dmatag, &seg, rseg, BGE_JMEM, (void **)&kva, 1566 BUS_DMA_NOWAIT)) { 1567 aprint_error_dev(sc->bge_dev, 1568 "can't map DMA buffers (%d bytes)\n", (int)BGE_JMEM); 1569 error = ENOBUFS; 1570 goto out; 1571 } 1572 1573 state = 2; 1574 if (bus_dmamap_create(sc->bge_dmatag, BGE_JMEM, 1, BGE_JMEM, 0, 1575 BUS_DMA_NOWAIT, &sc->bge_cdata.bge_rx_jumbo_map)) { 1576 aprint_error_dev(sc->bge_dev, "can't create DMA map\n"); 1577 error = ENOBUFS; 1578 goto out; 1579 } 1580 1581 state = 3; 1582 if (bus_dmamap_load(sc->bge_dmatag, sc->bge_cdata.bge_rx_jumbo_map, 1583 kva, BGE_JMEM, NULL, BUS_DMA_NOWAIT)) { 1584 aprint_error_dev(sc->bge_dev, "can't load DMA map\n"); 1585 error = ENOBUFS; 1586 goto out; 1587 } 1588 1589 state = 4; 1590 sc->bge_cdata.bge_jumbo_buf = (void *)kva; 1591 DPRINTFN(1,("bge_jumbo_buf = %p\n", sc->bge_cdata.bge_jumbo_buf)); 1592 1593 SLIST_INIT(&sc->bge_jfree_listhead); 1594 SLIST_INIT(&sc->bge_jinuse_listhead); 1595 1596 /* 1597 * Now divide it up into 9K pieces and save the addresses 1598 * in an array. 1599 */ 1600 ptr = sc->bge_cdata.bge_jumbo_buf; 1601 for (i = 0; i < BGE_JSLOTS; i++) { 1602 sc->bge_cdata.bge_jslots[i] = ptr; 1603 ptr += BGE_JLEN; 1604 entry = malloc(sizeof(struct bge_jpool_entry), 1605 M_DEVBUF, M_NOWAIT); 1606 if (entry == NULL) { 1607 aprint_error_dev(sc->bge_dev, 1608 "no memory for jumbo buffer queue!\n"); 1609 error = ENOBUFS; 1610 goto out; 1611 } 1612 entry->slot = i; 1613 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, 1614 entry, jpool_entries); 1615 } 1616 out: 1617 if (error != 0) { 1618 switch (state) { 1619 case 4: 1620 bus_dmamap_unload(sc->bge_dmatag, 1621 sc->bge_cdata.bge_rx_jumbo_map); 1622 case 3: 1623 bus_dmamap_destroy(sc->bge_dmatag, 1624 sc->bge_cdata.bge_rx_jumbo_map); 1625 case 2: 1626 bus_dmamem_unmap(sc->bge_dmatag, kva, BGE_JMEM); 1627 case 1: 1628 bus_dmamem_free(sc->bge_dmatag, &seg, rseg); 1629 break; 1630 default: 1631 break; 1632 } 1633 } 1634 1635 return error; 1636 } 1637 1638 /* 1639 * Allocate a jumbo buffer. 1640 */ 1641 static void * 1642 bge_jalloc(struct bge_softc *sc) 1643 { 1644 struct bge_jpool_entry *entry; 1645 1646 entry = SLIST_FIRST(&sc->bge_jfree_listhead); 1647 1648 if (entry == NULL) { 1649 aprint_error_dev(sc->bge_dev, "no free jumbo buffers\n"); 1650 return NULL; 1651 } 1652 1653 SLIST_REMOVE_HEAD(&sc->bge_jfree_listhead, jpool_entries); 1654 SLIST_INSERT_HEAD(&sc->bge_jinuse_listhead, entry, jpool_entries); 1655 return (sc->bge_cdata.bge_jslots[entry->slot]); 1656 } 1657 1658 /* 1659 * Release a jumbo buffer. 1660 */ 1661 static void 1662 bge_jfree(struct mbuf *m, void *buf, size_t size, void *arg) 1663 { 1664 struct bge_jpool_entry *entry; 1665 struct bge_softc *sc; 1666 int i, s; 1667 1668 /* Extract the softc struct pointer. */ 1669 sc = (struct bge_softc *)arg; 1670 1671 if (sc == NULL) 1672 panic("bge_jfree: can't find softc pointer!"); 1673 1674 /* calculate the slot this buffer belongs to */ 1675 1676 i = ((char *)buf 1677 - (char *)sc->bge_cdata.bge_jumbo_buf) / BGE_JLEN; 1678 1679 if ((i < 0) || (i >= BGE_JSLOTS)) 1680 panic("bge_jfree: asked to free buffer that we don't manage!"); 1681 1682 s = splvm(); 1683 entry = SLIST_FIRST(&sc->bge_jinuse_listhead); 1684 if (entry == NULL) 1685 panic("bge_jfree: buffer not in use!"); 1686 entry->slot = i; 1687 SLIST_REMOVE_HEAD(&sc->bge_jinuse_listhead, jpool_entries); 1688 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, entry, jpool_entries); 1689 1690 if (__predict_true(m != NULL)) 1691 pool_cache_put(mb_cache, m); 1692 splx(s); 1693 } 1694 1695 1696 /* 1697 * Initialize a standard receive ring descriptor. 1698 */ 1699 static int 1700 bge_newbuf_std(struct bge_softc *sc, int i, struct mbuf *m, 1701 bus_dmamap_t dmamap) 1702 { 1703 struct mbuf *m_new = NULL; 1704 struct bge_rx_bd *r; 1705 int error; 1706 1707 if (dmamap == NULL) { 1708 error = bus_dmamap_create(sc->bge_dmatag, MCLBYTES, 1, 1709 MCLBYTES, 0, BUS_DMA_NOWAIT, &dmamap); 1710 if (error != 0) 1711 return error; 1712 } 1713 1714 sc->bge_cdata.bge_rx_std_map[i] = dmamap; 1715 1716 if (m == NULL) { 1717 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1718 if (m_new == NULL) 1719 return ENOBUFS; 1720 1721 MCLGET(m_new, M_DONTWAIT); 1722 if (!(m_new->m_flags & M_EXT)) { 1723 m_freem(m_new); 1724 return ENOBUFS; 1725 } 1726 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1727 1728 } else { 1729 m_new = m; 1730 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1731 m_new->m_data = m_new->m_ext.ext_buf; 1732 } 1733 if (!(sc->bge_flags & BGE_RX_ALIGNBUG)) 1734 m_adj(m_new, ETHER_ALIGN); 1735 if (bus_dmamap_load_mbuf(sc->bge_dmatag, dmamap, m_new, 1736 BUS_DMA_READ|BUS_DMA_NOWAIT)) 1737 return ENOBUFS; 1738 bus_dmamap_sync(sc->bge_dmatag, dmamap, 0, dmamap->dm_mapsize, 1739 BUS_DMASYNC_PREREAD); 1740 1741 sc->bge_cdata.bge_rx_std_chain[i] = m_new; 1742 r = &sc->bge_rdata->bge_rx_std_ring[i]; 1743 BGE_HOSTADDR(r->bge_addr, dmamap->dm_segs[0].ds_addr); 1744 r->bge_flags = BGE_RXBDFLAG_END; 1745 r->bge_len = m_new->m_len; 1746 r->bge_idx = i; 1747 1748 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 1749 offsetof(struct bge_ring_data, bge_rx_std_ring) + 1750 i * sizeof (struct bge_rx_bd), 1751 sizeof (struct bge_rx_bd), 1752 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1753 1754 return 0; 1755 } 1756 1757 /* 1758 * Initialize a jumbo receive ring descriptor. This allocates 1759 * a jumbo buffer from the pool managed internally by the driver. 1760 */ 1761 static int 1762 bge_newbuf_jumbo(struct bge_softc *sc, int i, struct mbuf *m) 1763 { 1764 struct mbuf *m_new = NULL; 1765 struct bge_rx_bd *r; 1766 void *buf = NULL; 1767 1768 if (m == NULL) { 1769 1770 /* Allocate the mbuf. */ 1771 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1772 if (m_new == NULL) 1773 return ENOBUFS; 1774 1775 /* Allocate the jumbo buffer */ 1776 buf = bge_jalloc(sc); 1777 if (buf == NULL) { 1778 m_freem(m_new); 1779 aprint_error_dev(sc->bge_dev, 1780 "jumbo allocation failed -- packet dropped!\n"); 1781 return ENOBUFS; 1782 } 1783 1784 /* Attach the buffer to the mbuf. */ 1785 m_new->m_len = m_new->m_pkthdr.len = BGE_JUMBO_FRAMELEN; 1786 MEXTADD(m_new, buf, BGE_JUMBO_FRAMELEN, M_DEVBUF, 1787 bge_jfree, sc); 1788 m_new->m_flags |= M_EXT_RW; 1789 } else { 1790 m_new = m; 1791 buf = m_new->m_data = m_new->m_ext.ext_buf; 1792 m_new->m_ext.ext_size = BGE_JUMBO_FRAMELEN; 1793 } 1794 if (!(sc->bge_flags & BGE_RX_ALIGNBUG)) 1795 m_adj(m_new, ETHER_ALIGN); 1796 bus_dmamap_sync(sc->bge_dmatag, sc->bge_cdata.bge_rx_jumbo_map, 1797 mtod(m_new, char *) - (char *)sc->bge_cdata.bge_jumbo_buf, BGE_JLEN, 1798 BUS_DMASYNC_PREREAD); 1799 /* Set up the descriptor. */ 1800 r = &sc->bge_rdata->bge_rx_jumbo_ring[i]; 1801 sc->bge_cdata.bge_rx_jumbo_chain[i] = m_new; 1802 BGE_HOSTADDR(r->bge_addr, BGE_JUMBO_DMA_ADDR(sc, m_new)); 1803 r->bge_flags = BGE_RXBDFLAG_END|BGE_RXBDFLAG_JUMBO_RING; 1804 r->bge_len = m_new->m_len; 1805 r->bge_idx = i; 1806 1807 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 1808 offsetof(struct bge_ring_data, bge_rx_jumbo_ring) + 1809 i * sizeof (struct bge_rx_bd), 1810 sizeof (struct bge_rx_bd), 1811 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1812 1813 return 0; 1814 } 1815 1816 /* 1817 * The standard receive ring has 512 entries in it. At 2K per mbuf cluster, 1818 * that's 1MB or memory, which is a lot. For now, we fill only the first 1819 * 256 ring entries and hope that our CPU is fast enough to keep up with 1820 * the NIC. 1821 */ 1822 static int 1823 bge_init_rx_ring_std(struct bge_softc *sc) 1824 { 1825 int i; 1826 1827 if (sc->bge_flags & BGE_RXRING_VALID) 1828 return 0; 1829 1830 for (i = 0; i < BGE_SSLOTS; i++) { 1831 if (bge_newbuf_std(sc, i, NULL, 0) == ENOBUFS) 1832 return ENOBUFS; 1833 } 1834 1835 sc->bge_std = i - 1; 1836 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std); 1837 1838 sc->bge_flags |= BGE_RXRING_VALID; 1839 1840 return 0; 1841 } 1842 1843 static void 1844 bge_free_rx_ring_std(struct bge_softc *sc) 1845 { 1846 int i; 1847 1848 if (!(sc->bge_flags & BGE_RXRING_VALID)) 1849 return; 1850 1851 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { 1852 if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) { 1853 m_freem(sc->bge_cdata.bge_rx_std_chain[i]); 1854 sc->bge_cdata.bge_rx_std_chain[i] = NULL; 1855 bus_dmamap_destroy(sc->bge_dmatag, 1856 sc->bge_cdata.bge_rx_std_map[i]); 1857 } 1858 memset((char *)&sc->bge_rdata->bge_rx_std_ring[i], 0, 1859 sizeof(struct bge_rx_bd)); 1860 } 1861 1862 sc->bge_flags &= ~BGE_RXRING_VALID; 1863 } 1864 1865 static int 1866 bge_init_rx_ring_jumbo(struct bge_softc *sc) 1867 { 1868 int i; 1869 volatile struct bge_rcb *rcb; 1870 1871 if (sc->bge_flags & BGE_JUMBO_RXRING_VALID) 1872 return 0; 1873 1874 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 1875 if (bge_newbuf_jumbo(sc, i, NULL) == ENOBUFS) 1876 return ENOBUFS; 1877 } 1878 1879 sc->bge_jumbo = i - 1; 1880 sc->bge_flags |= BGE_JUMBO_RXRING_VALID; 1881 1882 rcb = &sc->bge_rdata->bge_info.bge_jumbo_rx_rcb; 1883 rcb->bge_maxlen_flags = 0; 1884 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 1885 1886 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo); 1887 1888 return 0; 1889 } 1890 1891 static void 1892 bge_free_rx_ring_jumbo(struct bge_softc *sc) 1893 { 1894 int i; 1895 1896 if (!(sc->bge_flags & BGE_JUMBO_RXRING_VALID)) 1897 return; 1898 1899 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 1900 if (sc->bge_cdata.bge_rx_jumbo_chain[i] != NULL) { 1901 m_freem(sc->bge_cdata.bge_rx_jumbo_chain[i]); 1902 sc->bge_cdata.bge_rx_jumbo_chain[i] = NULL; 1903 } 1904 memset((char *)&sc->bge_rdata->bge_rx_jumbo_ring[i], 0, 1905 sizeof(struct bge_rx_bd)); 1906 } 1907 1908 sc->bge_flags &= ~BGE_JUMBO_RXRING_VALID; 1909 } 1910 1911 static void 1912 bge_free_tx_ring(struct bge_softc *sc) 1913 { 1914 int i; 1915 struct txdmamap_pool_entry *dma; 1916 1917 if (!(sc->bge_flags & BGE_TXRING_VALID)) 1918 return; 1919 1920 for (i = 0; i < BGE_TX_RING_CNT; i++) { 1921 if (sc->bge_cdata.bge_tx_chain[i] != NULL) { 1922 m_freem(sc->bge_cdata.bge_tx_chain[i]); 1923 sc->bge_cdata.bge_tx_chain[i] = NULL; 1924 SLIST_INSERT_HEAD(&sc->txdma_list, sc->txdma[i], 1925 link); 1926 sc->txdma[i] = 0; 1927 } 1928 memset((char *)&sc->bge_rdata->bge_tx_ring[i], 0, 1929 sizeof(struct bge_tx_bd)); 1930 } 1931 1932 while ((dma = SLIST_FIRST(&sc->txdma_list))) { 1933 SLIST_REMOVE_HEAD(&sc->txdma_list, link); 1934 bus_dmamap_destroy(sc->bge_dmatag, dma->dmamap); 1935 free(dma, M_DEVBUF); 1936 } 1937 1938 sc->bge_flags &= ~BGE_TXRING_VALID; 1939 } 1940 1941 static int 1942 bge_init_tx_ring(struct bge_softc *sc) 1943 { 1944 int i; 1945 bus_dmamap_t dmamap; 1946 struct txdmamap_pool_entry *dma; 1947 1948 if (sc->bge_flags & BGE_TXRING_VALID) 1949 return 0; 1950 1951 sc->bge_txcnt = 0; 1952 sc->bge_tx_saved_considx = 0; 1953 1954 /* Initialize transmit producer index for host-memory send ring. */ 1955 sc->bge_tx_prodidx = 0; 1956 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx); 1957 /* 5700 b2 errata */ 1958 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX) 1959 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx); 1960 1961 /* NIC-memory send ring not used; initialize to zero. */ 1962 bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0); 1963 /* 5700 b2 errata */ 1964 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX) 1965 bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0); 1966 1967 SLIST_INIT(&sc->txdma_list); 1968 for (i = 0; i < BGE_RSLOTS; i++) { 1969 if (bus_dmamap_create(sc->bge_dmatag, BGE_TXDMA_MAX, 1970 BGE_NTXSEG, ETHER_MAX_LEN_JUMBO, 0, BUS_DMA_NOWAIT, 1971 &dmamap)) 1972 return ENOBUFS; 1973 if (dmamap == NULL) 1974 panic("dmamap NULL in bge_init_tx_ring"); 1975 dma = malloc(sizeof(*dma), M_DEVBUF, M_NOWAIT); 1976 if (dma == NULL) { 1977 aprint_error_dev(sc->bge_dev, 1978 "can't alloc txdmamap_pool_entry\n"); 1979 bus_dmamap_destroy(sc->bge_dmatag, dmamap); 1980 return ENOMEM; 1981 } 1982 dma->dmamap = dmamap; 1983 SLIST_INSERT_HEAD(&sc->txdma_list, dma, link); 1984 } 1985 1986 sc->bge_flags |= BGE_TXRING_VALID; 1987 1988 return 0; 1989 } 1990 1991 static void 1992 bge_setmulti(struct bge_softc *sc) 1993 { 1994 struct ethercom *ac = &sc->ethercom; 1995 struct ifnet *ifp = &ac->ec_if; 1996 struct ether_multi *enm; 1997 struct ether_multistep step; 1998 uint32_t hashes[4] = { 0, 0, 0, 0 }; 1999 uint32_t h; 2000 int i; 2001 2002 if (ifp->if_flags & IFF_PROMISC) 2003 goto allmulti; 2004 2005 /* Now program new ones. */ 2006 ETHER_FIRST_MULTI(step, ac, enm); 2007 while (enm != NULL) { 2008 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 2009 /* 2010 * We must listen to a range of multicast addresses. 2011 * For now, just accept all multicasts, rather than 2012 * trying to set only those filter bits needed to match 2013 * the range. (At this time, the only use of address 2014 * ranges is for IP multicast routing, for which the 2015 * range is big enough to require all bits set.) 2016 */ 2017 goto allmulti; 2018 } 2019 2020 h = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN); 2021 2022 /* Just want the 7 least-significant bits. */ 2023 h &= 0x7f; 2024 2025 hashes[(h & 0x60) >> 5] |= 1 << (h & 0x1F); 2026 ETHER_NEXT_MULTI(step, enm); 2027 } 2028 2029 ifp->if_flags &= ~IFF_ALLMULTI; 2030 goto setit; 2031 2032 allmulti: 2033 ifp->if_flags |= IFF_ALLMULTI; 2034 hashes[0] = hashes[1] = hashes[2] = hashes[3] = 0xffffffff; 2035 2036 setit: 2037 for (i = 0; i < 4; i++) 2038 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]); 2039 } 2040 2041 static void 2042 bge_sig_pre_reset(struct bge_softc *sc, int type) 2043 { 2044 2045 /* 2046 * Some chips don't like this so only do this if ASF is enabled 2047 */ 2048 if (sc->bge_asf_mode) 2049 bge_writemem_ind(sc, BGE_SRAM_FW_MB, BGE_SRAM_FW_MB_MAGIC); 2050 2051 if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) { 2052 switch (type) { 2053 case BGE_RESET_START: 2054 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 2055 BGE_FW_DRV_STATE_START); 2056 break; 2057 case BGE_RESET_SHUTDOWN: 2058 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 2059 BGE_FW_DRV_STATE_UNLOAD); 2060 break; 2061 case BGE_RESET_SUSPEND: 2062 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 2063 BGE_FW_DRV_STATE_SUSPEND); 2064 break; 2065 } 2066 } 2067 2068 if (type == BGE_RESET_START || type == BGE_RESET_SUSPEND) 2069 bge_ape_driver_state_change(sc, type); 2070 } 2071 2072 static void 2073 bge_sig_post_reset(struct bge_softc *sc, int type) 2074 { 2075 2076 if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) { 2077 switch (type) { 2078 case BGE_RESET_START: 2079 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 2080 BGE_FW_DRV_STATE_START_DONE); 2081 /* START DONE */ 2082 break; 2083 case BGE_RESET_SHUTDOWN: 2084 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 2085 BGE_FW_DRV_STATE_UNLOAD_DONE); 2086 break; 2087 } 2088 } 2089 2090 if (type == BGE_RESET_SHUTDOWN) 2091 bge_ape_driver_state_change(sc, type); 2092 } 2093 2094 static void 2095 bge_sig_legacy(struct bge_softc *sc, int type) 2096 { 2097 2098 if (sc->bge_asf_mode) { 2099 switch (type) { 2100 case BGE_RESET_START: 2101 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 2102 BGE_FW_DRV_STATE_START); 2103 break; 2104 case BGE_RESET_SHUTDOWN: 2105 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 2106 BGE_FW_DRV_STATE_UNLOAD); 2107 break; 2108 } 2109 } 2110 } 2111 2112 static void 2113 bge_wait_for_event_ack(struct bge_softc *sc) 2114 { 2115 int i; 2116 2117 /* wait up to 2500usec */ 2118 for (i = 0; i < 250; i++) { 2119 if (!(CSR_READ_4(sc, BGE_RX_CPU_EVENT) & 2120 BGE_RX_CPU_DRV_EVENT)) 2121 break; 2122 DELAY(10); 2123 } 2124 } 2125 2126 static void 2127 bge_stop_fw(struct bge_softc *sc) 2128 { 2129 2130 if (sc->bge_asf_mode) { 2131 bge_wait_for_event_ack(sc); 2132 2133 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_MB, BGE_FW_CMD_PAUSE); 2134 CSR_WRITE_4_FLUSH(sc, BGE_RX_CPU_EVENT, 2135 CSR_READ_4(sc, BGE_RX_CPU_EVENT) | BGE_RX_CPU_DRV_EVENT); 2136 2137 bge_wait_for_event_ack(sc); 2138 } 2139 } 2140 2141 static int 2142 bge_poll_fw(struct bge_softc *sc) 2143 { 2144 uint32_t val; 2145 int i; 2146 2147 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 2148 for (i = 0; i < BGE_TIMEOUT; i++) { 2149 val = CSR_READ_4(sc, BGE_VCPU_STATUS); 2150 if (val & BGE_VCPU_STATUS_INIT_DONE) 2151 break; 2152 DELAY(100); 2153 } 2154 if (i >= BGE_TIMEOUT) { 2155 aprint_error_dev(sc->bge_dev, "reset timed out\n"); 2156 return -1; 2157 } 2158 } else if ((sc->bge_flags & BGE_NO_EEPROM) == 0) { 2159 /* 2160 * Poll the value location we just wrote until 2161 * we see the 1's complement of the magic number. 2162 * This indicates that the firmware initialization 2163 * is complete. 2164 * XXX 1000ms for Flash and 10000ms for SEEPROM. 2165 */ 2166 for (i = 0; i < BGE_TIMEOUT; i++) { 2167 val = bge_readmem_ind(sc, BGE_SRAM_FW_MB); 2168 if (val == ~BGE_SRAM_FW_MB_MAGIC) 2169 break; 2170 DELAY(10); 2171 } 2172 2173 if (i >= BGE_TIMEOUT) { 2174 aprint_error_dev(sc->bge_dev, 2175 "firmware handshake timed out, val = %x\n", val); 2176 return -1; 2177 } 2178 } 2179 2180 if (sc->bge_chipid == BGE_CHIPID_BCM57765_A0) { 2181 /* tg3 says we have to wait extra time */ 2182 delay(10 * 1000); 2183 } 2184 2185 return 0; 2186 } 2187 2188 int 2189 bge_phy_addr(struct bge_softc *sc) 2190 { 2191 struct pci_attach_args *pa = &(sc->bge_pa); 2192 int phy_addr = 1; 2193 2194 /* 2195 * PHY address mapping for various devices. 2196 * 2197 * | F0 Cu | F0 Sr | F1 Cu | F1 Sr | 2198 * ---------+-------+-------+-------+-------+ 2199 * BCM57XX | 1 | X | X | X | 2200 * BCM5704 | 1 | X | 1 | X | 2201 * BCM5717 | 1 | 8 | 2 | 9 | 2202 * BCM5719 | 1 | 8 | 2 | 9 | 2203 * BCM5720 | 1 | 8 | 2 | 9 | 2204 * 2205 * | F2 Cu | F2 Sr | F3 Cu | F3 Sr | 2206 * ---------+-------+-------+-------+-------+ 2207 * BCM57XX | X | X | X | X | 2208 * BCM5704 | X | X | X | X | 2209 * BCM5717 | X | X | X | X | 2210 * BCM5719 | 3 | 10 | 4 | 11 | 2211 * BCM5720 | X | X | X | X | 2212 * 2213 * Other addresses may respond but they are not 2214 * IEEE compliant PHYs and should be ignored. 2215 */ 2216 switch (BGE_ASICREV(sc->bge_chipid)) { 2217 case BGE_ASICREV_BCM5717: 2218 case BGE_ASICREV_BCM5719: 2219 case BGE_ASICREV_BCM5720: 2220 phy_addr = pa->pa_function; 2221 if (sc->bge_chipid == BGE_CHIPID_BCM5717_A0) { 2222 phy_addr += (CSR_READ_4(sc, BGE_SGDIG_STS) & 2223 BGE_SGDIGSTS_IS_SERDES) ? 8 : 1; 2224 } else { 2225 phy_addr += (CSR_READ_4(sc, BGE_CPMU_PHY_STRAP) & 2226 BGE_CPMU_PHY_STRAP_IS_SERDES) ? 8 : 1; 2227 } 2228 } 2229 2230 return phy_addr; 2231 } 2232 2233 /* 2234 * Do endian, PCI and DMA initialization. Also check the on-board ROM 2235 * self-test results. 2236 */ 2237 static int 2238 bge_chipinit(struct bge_softc *sc) 2239 { 2240 uint32_t dma_rw_ctl, mode_ctl, reg; 2241 int i; 2242 2243 /* Set endianness before we access any non-PCI registers. */ 2244 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MISC_CTL, 2245 BGE_INIT); 2246 2247 /* 2248 * Clear the MAC statistics block in the NIC's 2249 * internal memory. 2250 */ 2251 for (i = BGE_STATS_BLOCK; 2252 i < BGE_STATS_BLOCK_END + 1; i += sizeof(uint32_t)) 2253 BGE_MEMWIN_WRITE(sc->sc_pc, sc->sc_pcitag, i, 0); 2254 2255 for (i = BGE_STATUS_BLOCK; 2256 i < BGE_STATUS_BLOCK_END + 1; i += sizeof(uint32_t)) 2257 BGE_MEMWIN_WRITE(sc->sc_pc, sc->sc_pcitag, i, 0); 2258 2259 /* 5717 workaround from tg3 */ 2260 if (sc->bge_chipid == BGE_CHIPID_BCM5717_A0) { 2261 /* Save */ 2262 mode_ctl = CSR_READ_4(sc, BGE_MODE_CTL); 2263 2264 /* Temporary modify MODE_CTL to control TLP */ 2265 reg = mode_ctl & ~BGE_MODECTL_PCIE_TLPADDRMASK; 2266 CSR_WRITE_4(sc, BGE_MODE_CTL, reg | BGE_MODECTL_PCIE_TLPADDR1); 2267 2268 /* Control TLP */ 2269 reg = CSR_READ_4(sc, BGE_TLP_CONTROL_REG + 2270 BGE_TLP_PHYCTL1); 2271 CSR_WRITE_4(sc, BGE_TLP_CONTROL_REG + BGE_TLP_PHYCTL1, 2272 reg | BGE_TLP_PHYCTL1_EN_L1PLLPD); 2273 2274 /* Restore */ 2275 CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl); 2276 } 2277 2278 /* XXX Should we use 57765_FAMILY? */ 2279 if (BGE_IS_57765_PLUS(sc)) { 2280 if (sc->bge_chipid == BGE_CHIPID_BCM57765_A0) { 2281 /* Save */ 2282 mode_ctl = CSR_READ_4(sc, BGE_MODE_CTL); 2283 2284 /* Temporary modify MODE_CTL to control TLP */ 2285 reg = mode_ctl & ~BGE_MODECTL_PCIE_TLPADDRMASK; 2286 CSR_WRITE_4(sc, BGE_MODE_CTL, 2287 reg | BGE_MODECTL_PCIE_TLPADDR1); 2288 2289 /* Control TLP */ 2290 reg = CSR_READ_4(sc, BGE_TLP_CONTROL_REG + 2291 BGE_TLP_PHYCTL5); 2292 CSR_WRITE_4(sc, BGE_TLP_CONTROL_REG + BGE_TLP_PHYCTL5, 2293 reg | BGE_TLP_PHYCTL5_DIS_L2CLKREQ); 2294 2295 /* Restore */ 2296 CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl); 2297 } 2298 if (BGE_CHIPREV(sc->bge_chipid) != BGE_CHIPREV_57765_AX) { 2299 reg = CSR_READ_4(sc, BGE_CPMU_PADRNG_CTL); 2300 CSR_WRITE_4(sc, BGE_CPMU_PADRNG_CTL, 2301 reg | BGE_CPMU_PADRNG_CTL_RDIV2); 2302 2303 /* Save */ 2304 mode_ctl = CSR_READ_4(sc, BGE_MODE_CTL); 2305 2306 /* Temporary modify MODE_CTL to control TLP */ 2307 reg = mode_ctl & ~BGE_MODECTL_PCIE_TLPADDRMASK; 2308 CSR_WRITE_4(sc, BGE_MODE_CTL, 2309 reg | BGE_MODECTL_PCIE_TLPADDR0); 2310 2311 /* Control TLP */ 2312 reg = CSR_READ_4(sc, BGE_TLP_CONTROL_REG + 2313 BGE_TLP_FTSMAX); 2314 reg &= ~BGE_TLP_FTSMAX_MSK; 2315 CSR_WRITE_4(sc, BGE_TLP_CONTROL_REG + BGE_TLP_FTSMAX, 2316 reg | BGE_TLP_FTSMAX_VAL); 2317 2318 /* Restore */ 2319 CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl); 2320 } 2321 2322 reg = CSR_READ_4(sc, BGE_CPMU_LSPD_10MB_CLK); 2323 reg &= ~BGE_CPMU_LSPD_10MB_MACCLK_MASK; 2324 reg |= BGE_CPMU_LSPD_10MB_MACCLK_6_25; 2325 CSR_WRITE_4(sc, BGE_CPMU_LSPD_10MB_CLK, reg); 2326 } 2327 2328 /* Set up the PCI DMA control register. */ 2329 dma_rw_ctl = BGE_PCI_READ_CMD | BGE_PCI_WRITE_CMD; 2330 if (sc->bge_flags & BGE_PCIE) { 2331 /* Read watermark not used, 128 bytes for write. */ 2332 DPRINTFN(4, ("(%s: PCI-Express DMA setting)\n", 2333 device_xname(sc->bge_dev))); 2334 dma_rw_ctl |= BGE_PCIDMARWCTL_WR_WAT_SHIFT(3); 2335 } else if (sc->bge_flags & BGE_PCIX) { 2336 DPRINTFN(4, ("(:%s: PCI-X DMA setting)\n", 2337 device_xname(sc->bge_dev))); 2338 /* PCI-X bus */ 2339 if (BGE_IS_5714_FAMILY(sc)) { 2340 /* 256 bytes for read and write. */ 2341 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(2) | 2342 BGE_PCIDMARWCTL_WR_WAT_SHIFT(2); 2343 2344 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5780) 2345 dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL; 2346 else 2347 dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE_LOCAL; 2348 } else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) { 2349 /* 1536 bytes for read, 384 bytes for write. */ 2350 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(7) | 2351 BGE_PCIDMARWCTL_WR_WAT_SHIFT(3); 2352 } else { 2353 /* 384 bytes for read and write. */ 2354 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(3) | 2355 BGE_PCIDMARWCTL_WR_WAT_SHIFT(3) | 2356 (0x0F); 2357 } 2358 2359 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5703 || 2360 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) { 2361 uint32_t tmp; 2362 2363 /* Set ONEDMA_ATONCE for hardware workaround. */ 2364 tmp = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 2365 BGE_PCI_CLKCTL) & 0x1f; 2366 if (tmp == 6 || tmp == 7) 2367 dma_rw_ctl |= 2368 BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL; 2369 2370 /* Set PCI-X DMA write workaround. */ 2371 dma_rw_ctl |= BGE_PCIDMARWCTL_ASRT_ALL_BE; 2372 } 2373 } else { 2374 /* Conventional PCI bus: 256 bytes for read and write. */ 2375 DPRINTFN(4, ("(%s: PCI 2.2 DMA setting)\n", 2376 device_xname(sc->bge_dev))); 2377 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(7) | 2378 BGE_PCIDMARWCTL_WR_WAT_SHIFT(7); 2379 2380 if (BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5705 && 2381 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5750) 2382 dma_rw_ctl |= 0x0F; 2383 } 2384 2385 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 2386 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5701) 2387 dma_rw_ctl |= BGE_PCIDMARWCTL_USE_MRM | 2388 BGE_PCIDMARWCTL_ASRT_ALL_BE; 2389 2390 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5703 || 2391 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) 2392 dma_rw_ctl &= ~BGE_PCIDMARWCTL_MINDMA; 2393 2394 if (BGE_IS_5717_PLUS(sc)) { 2395 dma_rw_ctl &= ~BGE_PCIDMARWCTL_DIS_CACHE_ALIGNMENT; 2396 if (sc->bge_chipid == BGE_CHIPID_BCM57765_A0) 2397 dma_rw_ctl &= ~BGE_PCIDMARWCTL_CRDRDR_RDMA_MRRS_MSK; 2398 2399 /* 2400 * Enable HW workaround for controllers that misinterpret 2401 * a status tag update and leave interrupts permanently 2402 * disabled. 2403 */ 2404 if (BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5717 && 2405 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM57765) 2406 dma_rw_ctl |= BGE_PCIDMARWCTL_TAGGED_STATUS_WA; 2407 } 2408 2409 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_DMA_RW_CTL, 2410 dma_rw_ctl); 2411 2412 /* 2413 * Set up general mode register. 2414 */ 2415 mode_ctl = BGE_DMA_SWAP_OPTIONS; 2416 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) { 2417 /* Retain Host-2-BMC settings written by APE firmware. */ 2418 mode_ctl |= CSR_READ_4(sc, BGE_MODE_CTL) & 2419 (BGE_MODECTL_BYTESWAP_B2HRX_DATA | 2420 BGE_MODECTL_WORDSWAP_B2HRX_DATA | 2421 BGE_MODECTL_B2HRX_ENABLE | BGE_MODECTL_HTX2B_ENABLE); 2422 } 2423 mode_ctl |= BGE_MODECTL_MAC_ATTN_INTR | BGE_MODECTL_HOST_SEND_BDS | 2424 BGE_MODECTL_TX_NO_PHDR_CSUM; 2425 2426 /* 2427 * BCM5701 B5 have a bug causing data corruption when using 2428 * 64-bit DMA reads, which can be terminated early and then 2429 * completed later as 32-bit accesses, in combination with 2430 * certain bridges. 2431 */ 2432 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5701 && 2433 sc->bge_chipid == BGE_CHIPID_BCM5701_B5) 2434 mode_ctl |= BGE_MODECTL_FORCE_PCI32; 2435 2436 /* 2437 * Tell the firmware the driver is running 2438 */ 2439 if (sc->bge_asf_mode & ASF_STACKUP) 2440 mode_ctl |= BGE_MODECTL_STACKUP; 2441 2442 CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl); 2443 2444 /* 2445 * Disable memory write invalidate. Apparently it is not supported 2446 * properly by these devices. 2447 */ 2448 PCI_CLRBIT(sc->sc_pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG, 2449 PCI_COMMAND_INVALIDATE_ENABLE); 2450 2451 #ifdef __brokenalpha__ 2452 /* 2453 * Must insure that we do not cross an 8K (bytes) boundary 2454 * for DMA reads. Our highest limit is 1K bytes. This is a 2455 * restriction on some ALPHA platforms with early revision 2456 * 21174 PCI chipsets, such as the AlphaPC 164lx 2457 */ 2458 PCI_SETBIT(sc, BGE_PCI_DMA_RW_CTL, BGE_PCI_READ_BNDRY_1024, 4); 2459 #endif 2460 2461 /* Set the timer prescaler (always 66MHz) */ 2462 CSR_WRITE_4(sc, BGE_MISC_CFG, BGE_32BITTIME_66MHZ); 2463 2464 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 2465 DELAY(40); /* XXX */ 2466 2467 /* Put PHY into ready state */ 2468 BGE_CLRBIT_FLUSH(sc, BGE_MISC_CFG, BGE_MISCCFG_EPHY_IDDQ); 2469 DELAY(40); 2470 } 2471 2472 return 0; 2473 } 2474 2475 static int 2476 bge_blockinit(struct bge_softc *sc) 2477 { 2478 volatile struct bge_rcb *rcb; 2479 bus_size_t rcb_addr; 2480 int i; 2481 struct ifnet *ifp = &sc->ethercom.ec_if; 2482 bge_hostaddr taddr; 2483 uint32_t dmactl, val; 2484 2485 /* 2486 * Initialize the memory window pointer register so that 2487 * we can access the first 32K of internal NIC RAM. This will 2488 * allow us to set up the TX send ring RCBs and the RX return 2489 * ring RCBs, plus other things which live in NIC memory. 2490 */ 2491 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_BASEADDR, 0); 2492 2493 /* Step 33: Configure mbuf memory pool */ 2494 if (!BGE_IS_5705_PLUS(sc)) { 2495 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, 2496 BGE_BUFFPOOL_1); 2497 2498 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) 2499 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000); 2500 else 2501 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000); 2502 2503 /* Configure DMA resource pool */ 2504 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_BASEADDR, 2505 BGE_DMA_DESCRIPTORS); 2506 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LEN, 0x2000); 2507 } 2508 2509 /* Step 35: Configure mbuf pool watermarks */ 2510 #ifdef ORIG_WPAUL_VALUES 2511 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 24); 2512 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 24); 2513 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 48); 2514 #else 2515 2516 /* new broadcom docs strongly recommend these: */ 2517 if (BGE_IS_5717_PLUS(sc)) { 2518 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0); 2519 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x2a); 2520 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0xa0); 2521 } else if (BGE_IS_5705_PLUS(sc)) { 2522 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0); 2523 2524 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 2525 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x04); 2526 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x10); 2527 } else { 2528 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x10); 2529 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60); 2530 } 2531 } else { 2532 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x50); 2533 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x20); 2534 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60); 2535 } 2536 #endif 2537 2538 /* Step 36: Configure DMA resource watermarks */ 2539 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5); 2540 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10); 2541 2542 /* Step 38: Enable buffer manager */ 2543 val = BGE_BMANMODE_ENABLE | BGE_BMANMODE_ATTN; 2544 /* 2545 * Change the arbitration algorithm of TXMBUF read request to 2546 * round-robin instead of priority based for BCM5719. When 2547 * TXFIFO is almost empty, RDMA will hold its request until 2548 * TXFIFO is not almost empty. 2549 */ 2550 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719) 2551 val |= BGE_BMANMODE_NO_TX_UNDERRUN; 2552 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5717 || 2553 sc->bge_chipid == BGE_CHIPID_BCM5719_A0 || 2554 sc->bge_chipid == BGE_CHIPID_BCM5720_A0) 2555 val |= BGE_BMANMODE_LOMBUF_ATTN; 2556 CSR_WRITE_4(sc, BGE_BMAN_MODE, val); 2557 2558 /* Step 39: Poll for buffer manager start indication */ 2559 for (i = 0; i < BGE_TIMEOUT * 2; i++) { 2560 DELAY(10); 2561 if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE) 2562 break; 2563 } 2564 2565 if (i == BGE_TIMEOUT * 2) { 2566 aprint_error_dev(sc->bge_dev, 2567 "buffer manager failed to start\n"); 2568 return ENXIO; 2569 } 2570 2571 /* Step 40: Enable flow-through queues */ 2572 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 2573 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 2574 2575 /* Wait until queue initialization is complete */ 2576 for (i = 0; i < BGE_TIMEOUT * 2; i++) { 2577 if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0) 2578 break; 2579 DELAY(10); 2580 } 2581 2582 if (i == BGE_TIMEOUT * 2) { 2583 aprint_error_dev(sc->bge_dev, 2584 "flow-through queue init failed\n"); 2585 return ENXIO; 2586 } 2587 2588 /* Step 41: Initialize the standard RX ring control block */ 2589 rcb = &sc->bge_rdata->bge_info.bge_std_rx_rcb; 2590 BGE_HOSTADDR(rcb->bge_hostaddr, BGE_RING_DMA_ADDR(sc, bge_rx_std_ring)); 2591 if (BGE_IS_5717_PLUS(sc)) 2592 rcb->bge_maxlen_flags = 2593 BGE_RCB_MAXLEN_FLAGS(512, BGE_MAX_FRAMELEN << 2); 2594 else if (BGE_IS_5705_PLUS(sc)) 2595 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(512, 0); 2596 else 2597 rcb->bge_maxlen_flags = 2598 BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 0); 2599 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5717 || 2600 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719 || 2601 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) 2602 rcb->bge_nicaddr = BGE_STD_RX_RINGS_5717; 2603 else 2604 rcb->bge_nicaddr = BGE_STD_RX_RINGS; 2605 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcb->bge_hostaddr.bge_addr_hi); 2606 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcb->bge_hostaddr.bge_addr_lo); 2607 CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 2608 CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcb->bge_nicaddr); 2609 2610 /* 2611 * Step 42: Initialize the jumbo RX ring control block 2612 * We set the 'ring disabled' bit in the flags 2613 * field until we're actually ready to start 2614 * using this ring (i.e. once we set the MTU 2615 * high enough to require it). 2616 */ 2617 if (BGE_IS_JUMBO_CAPABLE(sc)) { 2618 rcb = &sc->bge_rdata->bge_info.bge_jumbo_rx_rcb; 2619 BGE_HOSTADDR(rcb->bge_hostaddr, 2620 BGE_RING_DMA_ADDR(sc, bge_rx_jumbo_ring)); 2621 rcb->bge_maxlen_flags = 2622 BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 2623 BGE_RCB_FLAG_RING_DISABLED); 2624 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5717 || 2625 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719 || 2626 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) 2627 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS_5717; 2628 else 2629 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS; 2630 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI, 2631 rcb->bge_hostaddr.bge_addr_hi); 2632 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO, 2633 rcb->bge_hostaddr.bge_addr_lo); 2634 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, 2635 rcb->bge_maxlen_flags); 2636 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcb->bge_nicaddr); 2637 /* Reset the jumbo receive producer ring producer index. */ 2638 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0); 2639 } 2640 2641 /* Disable the mini receive producer ring RCB. */ 2642 if (BGE_IS_5700_FAMILY(sc)) { 2643 /* Set up dummy disabled mini ring RCB */ 2644 rcb = &sc->bge_rdata->bge_info.bge_mini_rx_rcb; 2645 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0, 2646 BGE_RCB_FLAG_RING_DISABLED); 2647 CSR_WRITE_4(sc, BGE_RX_MINI_RCB_MAXLEN_FLAGS, 2648 rcb->bge_maxlen_flags); 2649 /* Reset the mini receive producer ring producer index. */ 2650 bge_writembx(sc, BGE_MBX_RX_MINI_PROD_LO, 0); 2651 2652 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 2653 offsetof(struct bge_ring_data, bge_info), 2654 sizeof (struct bge_gib), 2655 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2656 } 2657 2658 /* Choose de-pipeline mode for BCM5906 A0, A1 and A2. */ 2659 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 2660 if (sc->bge_chipid == BGE_CHIPID_BCM5906_A0 || 2661 sc->bge_chipid == BGE_CHIPID_BCM5906_A1 || 2662 sc->bge_chipid == BGE_CHIPID_BCM5906_A2) 2663 CSR_WRITE_4(sc, BGE_ISO_PKT_TX, 2664 (CSR_READ_4(sc, BGE_ISO_PKT_TX) & ~3) | 2); 2665 } 2666 /* 2667 * Set the BD ring replenish thresholds. The recommended 2668 * values are 1/8th the number of descriptors allocated to 2669 * each ring. 2670 */ 2671 i = BGE_STD_RX_RING_CNT / 8; 2672 2673 /* 2674 * Use a value of 8 for the following chips to workaround HW errata. 2675 * Some of these chips have been added based on empirical 2676 * evidence (they don't work unless this is done). 2677 */ 2678 if (BGE_IS_5705_PLUS(sc)) 2679 i = 8; 2680 2681 CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, i); 2682 CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH, BGE_JUMBO_RX_RING_CNT / 8); 2683 2684 if (BGE_IS_5717_PLUS(sc)) { 2685 CSR_WRITE_4(sc, BGE_STD_REPL_LWM, 4); 2686 CSR_WRITE_4(sc, BGE_JUMBO_REPL_LWM, 4); 2687 } 2688 2689 /* 2690 * Disable all unused send rings by setting the 'ring disabled' 2691 * bit in the flags field of all the TX send ring control blocks. 2692 * These are located in NIC memory. 2693 */ 2694 rcb_addr = BGE_MEMWIN_START + BGE_SEND_RING_RCB; 2695 for (i = 0; i < BGE_TX_RINGS_EXTSSRAM_MAX; i++) { 2696 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 2697 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED)); 2698 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 0); 2699 rcb_addr += sizeof(struct bge_rcb); 2700 } 2701 2702 /* Configure TX RCB 0 (we use only the first ring) */ 2703 rcb_addr = BGE_MEMWIN_START + BGE_SEND_RING_RCB; 2704 BGE_HOSTADDR(taddr, BGE_RING_DMA_ADDR(sc, bge_tx_ring)); 2705 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi); 2706 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo); 2707 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5717 || 2708 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719 || 2709 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) 2710 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, BGE_SEND_RING_5717); 2711 else 2712 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 2713 BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT)); 2714 if (BGE_IS_5700_FAMILY(sc)) 2715 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 2716 BGE_RCB_MAXLEN_FLAGS(BGE_TX_RING_CNT, 0)); 2717 2718 /* Disable all unused RX return rings */ 2719 rcb_addr = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB; 2720 for (i = 0; i < BGE_RX_RINGS_MAX; i++) { 2721 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_hi, 0); 2722 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_lo, 0); 2723 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 2724 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 2725 BGE_RCB_FLAG_RING_DISABLED)); 2726 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 0); 2727 bge_writembx(sc, BGE_MBX_RX_CONS0_LO + 2728 (i * (sizeof(uint64_t))), 0); 2729 rcb_addr += sizeof(struct bge_rcb); 2730 } 2731 2732 /* 2733 * Set up RX return ring 0 2734 * Note that the NIC address for RX return rings is 0x00000000. 2735 * The return rings live entirely within the host, so the 2736 * nicaddr field in the RCB isn't used. 2737 */ 2738 rcb_addr = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB; 2739 BGE_HOSTADDR(taddr, BGE_RING_DMA_ADDR(sc, bge_rx_return_ring)); 2740 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi); 2741 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo); 2742 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 0x00000000); 2743 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 2744 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 0)); 2745 2746 /* Set random backoff seed for TX */ 2747 CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF, 2748 CLLADDR(ifp->if_sadl)[0] + CLLADDR(ifp->if_sadl)[1] + 2749 CLLADDR(ifp->if_sadl)[2] + CLLADDR(ifp->if_sadl)[3] + 2750 CLLADDR(ifp->if_sadl)[4] + CLLADDR(ifp->if_sadl)[5] + 2751 BGE_TX_BACKOFF_SEED_MASK); 2752 2753 /* Set inter-packet gap */ 2754 val = 0x2620; 2755 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) 2756 val |= CSR_READ_4(sc, BGE_TX_LENGTHS) & 2757 (BGE_TXLEN_JMB_FRM_LEN_MSK | BGE_TXLEN_CNT_DN_VAL_MSK); 2758 CSR_WRITE_4(sc, BGE_TX_LENGTHS, val); 2759 2760 /* 2761 * Specify which ring to use for packets that don't match 2762 * any RX rules. 2763 */ 2764 CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08); 2765 2766 /* 2767 * Configure number of RX lists. One interrupt distribution 2768 * list, sixteen active lists, one bad frames class. 2769 */ 2770 CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181); 2771 2772 /* Inialize RX list placement stats mask. */ 2773 CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF); 2774 CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1); 2775 2776 /* Disable host coalescing until we get it set up */ 2777 CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000); 2778 2779 /* Poll to make sure it's shut down. */ 2780 for (i = 0; i < BGE_TIMEOUT * 2; i++) { 2781 DELAY(10); 2782 if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE)) 2783 break; 2784 } 2785 2786 if (i == BGE_TIMEOUT * 2) { 2787 aprint_error_dev(sc->bge_dev, 2788 "host coalescing engine failed to idle\n"); 2789 return ENXIO; 2790 } 2791 2792 /* Set up host coalescing defaults */ 2793 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bge_rx_coal_ticks); 2794 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bge_tx_coal_ticks); 2795 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bge_rx_max_coal_bds); 2796 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bge_tx_max_coal_bds); 2797 if (!(BGE_IS_5705_PLUS(sc))) { 2798 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT, 0); 2799 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT, 0); 2800 } 2801 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 0); 2802 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 0); 2803 2804 /* Set up address of statistics block */ 2805 if (BGE_IS_5700_FAMILY(sc)) { 2806 BGE_HOSTADDR(taddr, BGE_RING_DMA_ADDR(sc, bge_info.bge_stats)); 2807 CSR_WRITE_4(sc, BGE_HCC_STATS_TICKS, sc->bge_stat_ticks); 2808 CSR_WRITE_4(sc, BGE_HCC_STATS_BASEADDR, BGE_STATS_BLOCK); 2809 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_HI, taddr.bge_addr_hi); 2810 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_LO, taddr.bge_addr_lo); 2811 } 2812 2813 /* Set up address of status block */ 2814 BGE_HOSTADDR(taddr, BGE_RING_DMA_ADDR(sc, bge_status_block)); 2815 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_BASEADDR, BGE_STATUS_BLOCK); 2816 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI, taddr.bge_addr_hi); 2817 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO, taddr.bge_addr_lo); 2818 sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx = 0; 2819 sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx = 0; 2820 2821 /* Set up status block size. */ 2822 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 && 2823 sc->bge_chipid != BGE_CHIPID_BCM5700_C0) { 2824 val = BGE_STATBLKSZ_FULL; 2825 bzero(&sc->bge_rdata->bge_status_block, BGE_STATUS_BLK_SZ); 2826 } else { 2827 val = BGE_STATBLKSZ_32BYTE; 2828 bzero(&sc->bge_rdata->bge_status_block, 32); 2829 } 2830 2831 /* Turn on host coalescing state machine */ 2832 CSR_WRITE_4(sc, BGE_HCC_MODE, val | BGE_HCCMODE_ENABLE); 2833 2834 /* Turn on RX BD completion state machine and enable attentions */ 2835 CSR_WRITE_4(sc, BGE_RBDC_MODE, 2836 BGE_RBDCMODE_ENABLE | BGE_RBDCMODE_ATTN); 2837 2838 /* Turn on RX list placement state machine */ 2839 CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 2840 2841 /* Turn on RX list selector state machine. */ 2842 if (!(BGE_IS_5705_PLUS(sc))) 2843 CSR_WRITE_4(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 2844 2845 val = BGE_MACMODE_TXDMA_ENB | BGE_MACMODE_RXDMA_ENB | 2846 BGE_MACMODE_RX_STATS_CLEAR | BGE_MACMODE_TX_STATS_CLEAR | 2847 BGE_MACMODE_RX_STATS_ENB | BGE_MACMODE_TX_STATS_ENB | 2848 BGE_MACMODE_FRMHDR_DMA_ENB; 2849 2850 if (sc->bge_flags & BGE_PHY_FIBER_TBI) 2851 val |= BGE_PORTMODE_TBI; 2852 else if (sc->bge_flags & BGE_PHY_FIBER_MII) 2853 val |= BGE_PORTMODE_GMII; 2854 else 2855 val |= BGE_PORTMODE_MII; 2856 2857 /* Allow APE to send/receive frames. */ 2858 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) != 0) 2859 val |= BGE_MACMODE_APE_RX_EN | BGE_MACMODE_APE_TX_EN; 2860 2861 /* Turn on DMA, clear stats */ 2862 CSR_WRITE_4_FLUSH(sc, BGE_MAC_MODE, val); 2863 DELAY(40); 2864 2865 /* Set misc. local control, enable interrupts on attentions */ 2866 sc->bge_local_ctrl_reg = BGE_MLC_INTR_ONATTN | BGE_MLC_AUTO_EEPROM; 2867 2868 #ifdef notdef 2869 /* Assert GPIO pins for PHY reset */ 2870 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUT0| 2871 BGE_MLC_MISCIO_OUT1|BGE_MLC_MISCIO_OUT2); 2872 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUTEN0| 2873 BGE_MLC_MISCIO_OUTEN1|BGE_MLC_MISCIO_OUTEN2); 2874 #endif 2875 2876 #if defined(not_quite_yet) 2877 /* Linux driver enables enable gpio pin #1 on 5700s */ 2878 if (sc->bge_chipid == BGE_CHIPID_BCM5700) { 2879 sc->bge_local_ctrl_reg |= 2880 (BGE_MLC_MISCIO_OUT1|BGE_MLC_MISCIO_OUTEN1); 2881 } 2882 #endif 2883 CSR_WRITE_4(sc, BGE_MISC_LOCAL_CTL, sc->bge_local_ctrl_reg); 2884 2885 /* Turn on DMA completion state machine */ 2886 if (!(BGE_IS_5705_PLUS(sc))) 2887 CSR_WRITE_4(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 2888 2889 val = BGE_WDMAMODE_ENABLE | BGE_WDMAMODE_ALL_ATTNS; 2890 2891 /* Enable host coalescing bug fix. */ 2892 if (BGE_IS_5755_PLUS(sc)) 2893 val |= BGE_WDMAMODE_STATUS_TAG_FIX; 2894 2895 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785) 2896 val |= BGE_WDMAMODE_BURST_ALL_DATA; 2897 2898 /* Turn on write DMA state machine */ 2899 CSR_WRITE_4_FLUSH(sc, BGE_WDMA_MODE, val); 2900 DELAY(40); 2901 2902 val = BGE_RDMAMODE_ENABLE | BGE_RDMAMODE_ALL_ATTNS; 2903 2904 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5717) 2905 val |= BGE_RDMAMODE_MULT_DMA_RD_DIS; 2906 2907 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5784 || 2908 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785 || 2909 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57780) 2910 val |= BGE_RDMAMODE_BD_SBD_CRPT_ATTN | 2911 BGE_RDMAMODE_MBUF_RBD_CRPT_ATTN | 2912 BGE_RDMAMODE_MBUF_SBD_CRPT_ATTN; 2913 2914 if (sc->bge_flags & BGE_PCIE) 2915 val |= BGE_RDMAMODE_FIFO_LONG_BURST; 2916 if (sc->bge_flags & BGE_TSO) 2917 val |= BGE_RDMAMODE_TSO4_ENABLE; 2918 2919 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) { 2920 val |= CSR_READ_4(sc, BGE_RDMA_MODE) & 2921 BGE_RDMAMODE_H2BNC_VLAN_DET; 2922 /* 2923 * Allow multiple outstanding read requests from 2924 * non-LSO read DMA engine. 2925 */ 2926 val &= ~BGE_RDMAMODE_MULT_DMA_RD_DIS; 2927 } 2928 2929 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761 || 2930 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5784 || 2931 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785 || 2932 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57780 || 2933 BGE_IS_5717_PLUS(sc)) { /* XXX 57765? */ 2934 dmactl = CSR_READ_4(sc, BGE_RDMA_RSRVCTRL); 2935 /* 2936 * Adjust tx margin to prevent TX data corruption and 2937 * fix internal FIFO overflow. 2938 */ 2939 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719 || 2940 sc->bge_chipid == BGE_CHIPID_BCM5719_A0) { 2941 dmactl &= ~(BGE_RDMA_RSRVCTRL_FIFO_LWM_MASK | 2942 BGE_RDMA_RSRVCTRL_FIFO_HWM_MASK | 2943 BGE_RDMA_RSRVCTRL_TXMRGN_MASK); 2944 dmactl |= BGE_RDMA_RSRVCTRL_FIFO_LWM_1_5K | 2945 BGE_RDMA_RSRVCTRL_FIFO_HWM_1_5K | 2946 BGE_RDMA_RSRVCTRL_TXMRGN_320B; 2947 } 2948 /* 2949 * Enable fix for read DMA FIFO overruns. 2950 * The fix is to limit the number of RX BDs 2951 * the hardware would fetch at a fime. 2952 */ 2953 CSR_WRITE_4(sc, BGE_RDMA_RSRVCTRL, dmactl | 2954 BGE_RDMA_RSRVCTRL_FIFO_OFLW_FIX); 2955 } 2956 2957 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719) { 2958 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL, 2959 CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL) | 2960 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_4K | 2961 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K); 2962 } else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) { 2963 /* 2964 * Allow 4KB burst length reads for non-LSO frames. 2965 * Enable 512B burst length reads for buffer descriptors. 2966 */ 2967 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL, 2968 CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL) | 2969 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_512 | 2970 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K); 2971 } 2972 2973 /* Turn on read DMA state machine */ 2974 CSR_WRITE_4_FLUSH(sc, BGE_RDMA_MODE, val); 2975 delay(40); 2976 2977 /* Turn on RX data completion state machine */ 2978 CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 2979 2980 /* Turn on RX BD initiator state machine */ 2981 CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 2982 2983 /* Turn on RX data and RX BD initiator state machine */ 2984 CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE); 2985 2986 /* Turn on Mbuf cluster free state machine */ 2987 if (!BGE_IS_5705_PLUS(sc)) 2988 CSR_WRITE_4(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 2989 2990 /* Turn on send BD completion state machine */ 2991 CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 2992 2993 /* Turn on send data completion state machine */ 2994 val = BGE_SDCMODE_ENABLE; 2995 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761) 2996 val |= BGE_SDCMODE_CDELAY; 2997 CSR_WRITE_4(sc, BGE_SDC_MODE, val); 2998 2999 /* Turn on send data initiator state machine */ 3000 if (sc->bge_flags & BGE_TSO) { 3001 /* XXX: magic value from Linux driver */ 3002 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE | 0x08); 3003 } else 3004 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 3005 3006 /* Turn on send BD initiator state machine */ 3007 CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 3008 3009 /* Turn on send BD selector state machine */ 3010 CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 3011 3012 CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF); 3013 CSR_WRITE_4(sc, BGE_SDI_STATS_CTL, 3014 BGE_SDISTATSCTL_ENABLE | BGE_SDISTATSCTL_FASTER); 3015 3016 /* ack/clear link change events */ 3017 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED | 3018 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE | 3019 BGE_MACSTAT_LINK_CHANGED); 3020 CSR_WRITE_4(sc, BGE_MI_STS, 0); 3021 3022 /* 3023 * Enable attention when the link has changed state for 3024 * devices that use auto polling. 3025 */ 3026 if (sc->bge_flags & BGE_PHY_FIBER_TBI) { 3027 CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK); 3028 } else { 3029 BGE_STS_SETBIT(sc, BGE_STS_AUTOPOLL); 3030 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL | (10 << 16)); 3031 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700) 3032 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, 3033 BGE_EVTENB_MI_INTERRUPT); 3034 } 3035 3036 /* 3037 * Clear any pending link state attention. 3038 * Otherwise some link state change events may be lost until attention 3039 * is cleared by bge_intr() -> bge_link_upd() sequence. 3040 * It's not necessary on newer BCM chips - perhaps enabling link 3041 * state change attentions implies clearing pending attention. 3042 */ 3043 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED | 3044 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE | 3045 BGE_MACSTAT_LINK_CHANGED); 3046 3047 /* Enable link state change attentions. */ 3048 BGE_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED); 3049 3050 return 0; 3051 } 3052 3053 static const struct bge_revision * 3054 bge_lookup_rev(uint32_t chipid) 3055 { 3056 const struct bge_revision *br; 3057 3058 for (br = bge_revisions; br->br_name != NULL; br++) { 3059 if (br->br_chipid == chipid) 3060 return br; 3061 } 3062 3063 for (br = bge_majorrevs; br->br_name != NULL; br++) { 3064 if (br->br_chipid == BGE_ASICREV(chipid)) 3065 return br; 3066 } 3067 3068 return NULL; 3069 } 3070 3071 static const struct bge_product * 3072 bge_lookup(const struct pci_attach_args *pa) 3073 { 3074 const struct bge_product *bp; 3075 3076 for (bp = bge_products; bp->bp_name != NULL; bp++) { 3077 if (PCI_VENDOR(pa->pa_id) == bp->bp_vendor && 3078 PCI_PRODUCT(pa->pa_id) == bp->bp_product) 3079 return bp; 3080 } 3081 3082 return NULL; 3083 } 3084 3085 static uint32_t 3086 bge_chipid(const struct pci_attach_args *pa) 3087 { 3088 uint32_t id; 3089 3090 id = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_MISC_CTL) 3091 >> BGE_PCIMISCCTL_ASICREV_SHIFT; 3092 3093 if (BGE_ASICREV(id) == BGE_ASICREV_USE_PRODID_REG) { 3094 switch (PCI_PRODUCT(pa->pa_id)) { 3095 case PCI_PRODUCT_BROADCOM_BCM5717: 3096 case PCI_PRODUCT_BROADCOM_BCM5718: 3097 case PCI_PRODUCT_BROADCOM_BCM5719: 3098 case PCI_PRODUCT_BROADCOM_BCM5720: 3099 case PCI_PRODUCT_BROADCOM_BCM5724: /* ??? */ 3100 id = pci_conf_read(pa->pa_pc, pa->pa_tag, 3101 BGE_PCI_GEN2_PRODID_ASICREV); 3102 break; 3103 case PCI_PRODUCT_BROADCOM_BCM57761: 3104 case PCI_PRODUCT_BROADCOM_BCM57762: 3105 case PCI_PRODUCT_BROADCOM_BCM57765: 3106 case PCI_PRODUCT_BROADCOM_BCM57766: 3107 case PCI_PRODUCT_BROADCOM_BCM57781: 3108 case PCI_PRODUCT_BROADCOM_BCM57785: 3109 case PCI_PRODUCT_BROADCOM_BCM57791: 3110 case PCI_PRODUCT_BROADCOM_BCM57795: 3111 id = pci_conf_read(pa->pa_pc, pa->pa_tag, 3112 BGE_PCI_GEN15_PRODID_ASICREV); 3113 break; 3114 default: 3115 id = pci_conf_read(pa->pa_pc, pa->pa_tag, 3116 BGE_PCI_PRODID_ASICREV); 3117 break; 3118 } 3119 } 3120 3121 return id; 3122 } 3123 3124 /* 3125 * Probe for a Broadcom chip. Check the PCI vendor and device IDs 3126 * against our list and return its name if we find a match. Note 3127 * that since the Broadcom controller contains VPD support, we 3128 * can get the device name string from the controller itself instead 3129 * of the compiled-in string. This is a little slow, but it guarantees 3130 * we'll always announce the right product name. 3131 */ 3132 static int 3133 bge_probe(device_t parent, cfdata_t match, void *aux) 3134 { 3135 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 3136 3137 if (bge_lookup(pa) != NULL) 3138 return 1; 3139 3140 return 0; 3141 } 3142 3143 static void 3144 bge_attach(device_t parent, device_t self, void *aux) 3145 { 3146 struct bge_softc *sc = device_private(self); 3147 struct pci_attach_args *pa = aux; 3148 prop_dictionary_t dict; 3149 const struct bge_product *bp; 3150 const struct bge_revision *br; 3151 pci_chipset_tag_t pc; 3152 pci_intr_handle_t ih; 3153 const char *intrstr = NULL; 3154 bus_dma_segment_t seg; 3155 int rseg; 3156 uint32_t hwcfg = 0; 3157 uint32_t command; 3158 struct ifnet *ifp; 3159 uint32_t misccfg; 3160 void * kva; 3161 u_char eaddr[ETHER_ADDR_LEN]; 3162 pcireg_t memtype, subid, reg; 3163 bus_addr_t memaddr; 3164 bus_size_t memsize, apesize; 3165 uint32_t pm_ctl; 3166 bool no_seeprom; 3167 3168 bp = bge_lookup(pa); 3169 KASSERT(bp != NULL); 3170 3171 sc->sc_pc = pa->pa_pc; 3172 sc->sc_pcitag = pa->pa_tag; 3173 sc->bge_dev = self; 3174 3175 sc->bge_pa = *pa; 3176 pc = sc->sc_pc; 3177 subid = pci_conf_read(pc, sc->sc_pcitag, PCI_SUBSYS_ID_REG); 3178 3179 aprint_naive(": Ethernet controller\n"); 3180 aprint_normal(": %s\n", bp->bp_name); 3181 3182 /* 3183 * Map control/status registers. 3184 */ 3185 DPRINTFN(5, ("Map control/status regs\n")); 3186 command = pci_conf_read(pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG); 3187 command |= PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_MASTER_ENABLE; 3188 pci_conf_write(pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG, command); 3189 command = pci_conf_read(pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG); 3190 3191 if (!(command & PCI_COMMAND_MEM_ENABLE)) { 3192 aprint_error_dev(sc->bge_dev, 3193 "failed to enable memory mapping!\n"); 3194 return; 3195 } 3196 3197 DPRINTFN(5, ("pci_mem_find\n")); 3198 memtype = pci_mapreg_type(sc->sc_pc, sc->sc_pcitag, BGE_PCI_BAR0); 3199 switch (memtype) { 3200 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 3201 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 3202 if (pci_mapreg_map(pa, BGE_PCI_BAR0, 3203 memtype, 0, &sc->bge_btag, &sc->bge_bhandle, 3204 &memaddr, &memsize) == 0) 3205 break; 3206 default: 3207 aprint_error_dev(sc->bge_dev, "can't find mem space\n"); 3208 return; 3209 } 3210 3211 DPRINTFN(5, ("pci_intr_map\n")); 3212 if (pci_intr_map(pa, &ih)) { 3213 aprint_error_dev(sc->bge_dev, "couldn't map interrupt\n"); 3214 return; 3215 } 3216 3217 DPRINTFN(5, ("pci_intr_string\n")); 3218 intrstr = pci_intr_string(pc, ih); 3219 3220 DPRINTFN(5, ("pci_intr_establish\n")); 3221 sc->bge_intrhand = pci_intr_establish(pc, ih, IPL_NET, bge_intr, sc); 3222 3223 if (sc->bge_intrhand == NULL) { 3224 aprint_error_dev(sc->bge_dev, 3225 "couldn't establish interrupt%s%s\n", 3226 intrstr ? " at " : "", intrstr ? intrstr : ""); 3227 return; 3228 } 3229 aprint_normal_dev(sc->bge_dev, "interrupting at %s\n", intrstr); 3230 3231 /* Save various chip information. */ 3232 sc->bge_chipid = bge_chipid(pa); 3233 sc->bge_phy_addr = bge_phy_addr(sc); 3234 3235 if ((pci_get_capability(sc->sc_pc, sc->sc_pcitag, PCI_CAP_PCIEXPRESS, 3236 &sc->bge_pciecap, NULL) != 0) 3237 || (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785)) { 3238 /* PCIe */ 3239 sc->bge_flags |= BGE_PCIE; 3240 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719 || 3241 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) 3242 sc->bge_expmrq = 2048; 3243 else 3244 sc->bge_expmrq = 4096; 3245 bge_set_max_readrq(sc); 3246 } else if ((pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_PCISTATE) & 3247 BGE_PCISTATE_PCI_BUSMODE) == 0) { 3248 /* PCI-X */ 3249 sc->bge_flags |= BGE_PCIX; 3250 if (pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_PCIX, 3251 &sc->bge_pcixcap, NULL) == 0) 3252 aprint_error_dev(sc->bge_dev, 3253 "unable to find PCIX capability\n"); 3254 } 3255 3256 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX) { 3257 /* 3258 * Kludge for 5700 Bx bug: a hardware bug (PCIX byte enable?) 3259 * can clobber the chip's PCI config-space power control 3260 * registers, leaving the card in D3 powersave state. We do 3261 * not have memory-mapped registers in this state, so force 3262 * device into D0 state before starting initialization. 3263 */ 3264 pm_ctl = pci_conf_read(pc, sc->sc_pcitag, BGE_PCI_PWRMGMT_CMD); 3265 pm_ctl &= ~(PCI_PWR_D0|PCI_PWR_D1|PCI_PWR_D2|PCI_PWR_D3); 3266 pm_ctl |= (1 << 8) | PCI_PWR_D0 ; /* D0 state */ 3267 pci_conf_write(pc, sc->sc_pcitag, BGE_PCI_PWRMGMT_CMD, pm_ctl); 3268 DELAY(1000); /* 27 usec is allegedly sufficent */ 3269 } 3270 3271 /* Save chipset family. */ 3272 switch (BGE_ASICREV(sc->bge_chipid)) { 3273 case BGE_ASICREV_BCM57765: 3274 case BGE_ASICREV_BCM57766: 3275 sc->bge_flags |= BGE_57765_PLUS; 3276 /* FALLTHROUGH */ 3277 case BGE_ASICREV_BCM5717: 3278 case BGE_ASICREV_BCM5719: 3279 case BGE_ASICREV_BCM5720: 3280 sc->bge_flags |= BGE_5717_PLUS | BGE_5755_PLUS | BGE_575X_PLUS | 3281 BGE_5705_PLUS; 3282 break; 3283 case BGE_ASICREV_BCM5755: 3284 case BGE_ASICREV_BCM5761: 3285 case BGE_ASICREV_BCM5784: 3286 case BGE_ASICREV_BCM5785: 3287 case BGE_ASICREV_BCM5787: 3288 case BGE_ASICREV_BCM57780: 3289 sc->bge_flags |= BGE_5755_PLUS | BGE_575X_PLUS | BGE_5705_PLUS; 3290 break; 3291 case BGE_ASICREV_BCM5700: 3292 case BGE_ASICREV_BCM5701: 3293 case BGE_ASICREV_BCM5703: 3294 case BGE_ASICREV_BCM5704: 3295 sc->bge_flags |= BGE_5700_FAMILY | BGE_JUMBO_CAPABLE; 3296 break; 3297 case BGE_ASICREV_BCM5714_A0: 3298 case BGE_ASICREV_BCM5780: 3299 case BGE_ASICREV_BCM5714: 3300 sc->bge_flags |= BGE_5714_FAMILY; 3301 /* FALLTHROUGH */ 3302 case BGE_ASICREV_BCM5750: 3303 case BGE_ASICREV_BCM5752: 3304 case BGE_ASICREV_BCM5906: 3305 sc->bge_flags |= BGE_575X_PLUS; 3306 /* FALLTHROUGH */ 3307 case BGE_ASICREV_BCM5705: 3308 sc->bge_flags |= BGE_5705_PLUS; 3309 break; 3310 } 3311 3312 /* Identify chips with APE processor. */ 3313 switch (BGE_ASICREV(sc->bge_chipid)) { 3314 case BGE_ASICREV_BCM5717: 3315 case BGE_ASICREV_BCM5719: 3316 case BGE_ASICREV_BCM5720: 3317 case BGE_ASICREV_BCM5761: 3318 sc->bge_flags |= BGE_APE; 3319 break; 3320 } 3321 3322 /* Chips with APE need BAR2 access for APE registers/memory. */ 3323 if ((sc->bge_flags & BGE_APE) != 0) { 3324 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, BGE_PCI_BAR2); 3325 if (pci_mapreg_map(pa, BGE_PCI_BAR2, memtype, 0, 3326 &sc->bge_apetag, &sc->bge_apehandle, NULL, &apesize)) { 3327 aprint_error_dev(sc->bge_dev, 3328 "couldn't map BAR2 memory\n"); 3329 return; 3330 } 3331 3332 /* Enable APE register/memory access by host driver. */ 3333 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_PCISTATE); 3334 reg |= BGE_PCISTATE_ALLOW_APE_CTLSPC_WR | 3335 BGE_PCISTATE_ALLOW_APE_SHMEM_WR | 3336 BGE_PCISTATE_ALLOW_APE_PSPACE_WR; 3337 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_PCISTATE, reg); 3338 3339 bge_ape_lock_init(sc); 3340 bge_ape_read_fw_ver(sc); 3341 } 3342 3343 /* Identify the chips that use an CPMU. */ 3344 if (BGE_IS_5717_PLUS(sc) || 3345 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5784 || 3346 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761 || 3347 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785 || 3348 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57780) 3349 sc->bge_flags |= BGE_CPMU_PRESENT; 3350 3351 if ((sc->bge_flags & BGE_CPMU_PRESENT) != 0) 3352 CSR_WRITE_4(sc, BGE_MI_MODE, BGE_MIMODE_500KHZ_CONST); 3353 else 3354 CSR_WRITE_4(sc, BGE_MI_MODE, BGE_MIMODE_BASE); 3355 3356 /* 3357 * When using the BCM5701 in PCI-X mode, data corruption has 3358 * been observed in the first few bytes of some received packets. 3359 * Aligning the packet buffer in memory eliminates the corruption. 3360 * Unfortunately, this misaligns the packet payloads. On platforms 3361 * which do not support unaligned accesses, we will realign the 3362 * payloads by copying the received packets. 3363 */ 3364 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5701 && 3365 sc->bge_flags & BGE_PCIX) 3366 sc->bge_flags |= BGE_RX_ALIGNBUG; 3367 3368 if (BGE_IS_5700_FAMILY(sc)) 3369 sc->bge_flags |= BGE_JUMBO_CAPABLE; 3370 3371 if ((BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 3372 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5701) && 3373 PCI_VENDOR(subid) == PCI_VENDOR_DELL) 3374 sc->bge_flags |= BGE_NO_3LED; 3375 3376 misccfg = CSR_READ_4(sc, BGE_MISC_CFG); 3377 misccfg &= BGE_MISCCFG_BOARD_ID_MASK; 3378 3379 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5705 && 3380 (misccfg == BGE_MISCCFG_BOARD_ID_5788 || 3381 misccfg == BGE_MISCCFG_BOARD_ID_5788M)) 3382 sc->bge_flags |= BGE_IS_5788; 3383 3384 /* 3385 * Some controllers seem to require a special firmware to use 3386 * TSO. But the firmware is not available to FreeBSD and Linux 3387 * claims that the TSO performed by the firmware is slower than 3388 * hardware based TSO. Moreover the firmware based TSO has one 3389 * known bug which can't handle TSO if ethernet header + IP/TCP 3390 * header is greater than 80 bytes. The workaround for the TSO 3391 * bug exist but it seems it's too expensive than not using 3392 * TSO at all. Some hardwares also have the TSO bug so limit 3393 * the TSO to the controllers that are not affected TSO issues 3394 * (e.g. 5755 or higher). 3395 */ 3396 if (BGE_IS_5755_PLUS(sc)) { 3397 /* 3398 * BCM5754 and BCM5787 shares the same ASIC id so 3399 * explicit device id check is required. 3400 */ 3401 if ((PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_BROADCOM_BCM5754) && 3402 (PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_BROADCOM_BCM5754M)) 3403 sc->bge_flags |= BGE_TSO; 3404 } 3405 3406 if ((BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5703 && 3407 (misccfg == 0x4000 || misccfg == 0x8000)) || 3408 (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5705 && 3409 PCI_VENDOR(pa->pa_id) == PCI_VENDOR_BROADCOM && 3410 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5901 || 3411 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5901A2 || 3412 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5705F)) || 3413 (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_BROADCOM && 3414 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5751F || 3415 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5753F || 3416 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5787F)) || 3417 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM57790 || 3418 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM57791 || 3419 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM57795 || 3420 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 3421 sc->bge_flags |= BGE_10_100_ONLY; 3422 3423 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 3424 (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5705 && 3425 (sc->bge_chipid != BGE_CHIPID_BCM5705_A0 && 3426 sc->bge_chipid != BGE_CHIPID_BCM5705_A1)) || 3427 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 3428 sc->bge_flags |= BGE_NO_ETH_WIRE_SPEED; 3429 3430 if (sc->bge_chipid == BGE_CHIPID_BCM5701_A0 || 3431 sc->bge_chipid == BGE_CHIPID_BCM5701_B0) 3432 sc->bge_flags |= BGE_PHY_CRC_BUG; 3433 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5703_AX || 3434 BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5704_AX) 3435 sc->bge_flags |= BGE_PHY_ADC_BUG; 3436 if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0) 3437 sc->bge_flags |= BGE_PHY_5704_A0_BUG; 3438 3439 if (BGE_IS_5705_PLUS(sc) && 3440 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5906 && 3441 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5785 && 3442 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM57780 && 3443 !BGE_IS_5717_PLUS(sc)) { 3444 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5755 || 3445 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761 || 3446 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5784 || 3447 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5787) { 3448 if (PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_BROADCOM_BCM5722 && 3449 PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_BROADCOM_BCM5756) 3450 sc->bge_flags |= BGE_PHY_JITTER_BUG; 3451 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5755M) 3452 sc->bge_flags |= BGE_PHY_ADJUST_TRIM; 3453 } else 3454 sc->bge_flags |= BGE_PHY_BER_BUG; 3455 } 3456 3457 /* 3458 * SEEPROM check. 3459 * First check if firmware knows we do not have SEEPROM. 3460 */ 3461 if (prop_dictionary_get_bool(device_properties(self), 3462 "without-seeprom", &no_seeprom) && no_seeprom) 3463 sc->bge_flags |= BGE_NO_EEPROM; 3464 3465 /* Now check the 'ROM failed' bit on the RX CPU */ 3466 else if (CSR_READ_4(sc, BGE_RXCPU_MODE) & BGE_RXCPUMODE_ROMFAIL) 3467 sc->bge_flags |= BGE_NO_EEPROM; 3468 3469 sc->bge_asf_mode = 0; 3470 /* No ASF if APE present. */ 3471 if ((sc->bge_flags & BGE_APE) == 0) { 3472 if (bge_allow_asf && (bge_readmem_ind(sc, BGE_SRAM_DATA_SIG) == 3473 BGE_SRAM_DATA_SIG_MAGIC)) { 3474 if (bge_readmem_ind(sc, BGE_SRAM_DATA_CFG) & 3475 BGE_HWCFG_ASF) { 3476 sc->bge_asf_mode |= ASF_ENABLE; 3477 sc->bge_asf_mode |= ASF_STACKUP; 3478 if (BGE_IS_575X_PLUS(sc)) 3479 sc->bge_asf_mode |= ASF_NEW_HANDSHAKE; 3480 } 3481 } 3482 } 3483 3484 bge_stop_fw(sc); 3485 bge_sig_pre_reset(sc, BGE_RESET_START); 3486 if (bge_reset(sc)) 3487 aprint_error_dev(sc->bge_dev, "chip reset failed\n"); 3488 3489 bge_sig_legacy(sc, BGE_RESET_START); 3490 bge_sig_post_reset(sc, BGE_RESET_START); 3491 3492 if (bge_chipinit(sc)) { 3493 aprint_error_dev(sc->bge_dev, "chip initialization failed\n"); 3494 bge_release_resources(sc); 3495 return; 3496 } 3497 3498 /* 3499 * Get station address from the EEPROM. 3500 */ 3501 if (bge_get_eaddr(sc, eaddr)) { 3502 aprint_error_dev(sc->bge_dev, 3503 "failed to read station address\n"); 3504 bge_release_resources(sc); 3505 return; 3506 } 3507 3508 br = bge_lookup_rev(sc->bge_chipid); 3509 3510 if (br == NULL) { 3511 aprint_normal_dev(sc->bge_dev, "unknown ASIC (0x%x)", 3512 sc->bge_chipid); 3513 } else { 3514 aprint_normal_dev(sc->bge_dev, "ASIC %s (0x%x)", 3515 br->br_name, sc->bge_chipid); 3516 } 3517 aprint_normal(", Ethernet address %s\n", ether_sprintf(eaddr)); 3518 3519 /* Allocate the general information block and ring buffers. */ 3520 if (pci_dma64_available(pa)) 3521 sc->bge_dmatag = pa->pa_dmat64; 3522 else 3523 sc->bge_dmatag = pa->pa_dmat; 3524 DPRINTFN(5, ("bus_dmamem_alloc\n")); 3525 if (bus_dmamem_alloc(sc->bge_dmatag, sizeof(struct bge_ring_data), 3526 PAGE_SIZE, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 3527 aprint_error_dev(sc->bge_dev, "can't alloc rx buffers\n"); 3528 return; 3529 } 3530 DPRINTFN(5, ("bus_dmamem_map\n")); 3531 if (bus_dmamem_map(sc->bge_dmatag, &seg, rseg, 3532 sizeof(struct bge_ring_data), &kva, 3533 BUS_DMA_NOWAIT)) { 3534 aprint_error_dev(sc->bge_dev, 3535 "can't map DMA buffers (%zu bytes)\n", 3536 sizeof(struct bge_ring_data)); 3537 bus_dmamem_free(sc->bge_dmatag, &seg, rseg); 3538 return; 3539 } 3540 DPRINTFN(5, ("bus_dmamem_create\n")); 3541 if (bus_dmamap_create(sc->bge_dmatag, sizeof(struct bge_ring_data), 1, 3542 sizeof(struct bge_ring_data), 0, 3543 BUS_DMA_NOWAIT, &sc->bge_ring_map)) { 3544 aprint_error_dev(sc->bge_dev, "can't create DMA map\n"); 3545 bus_dmamem_unmap(sc->bge_dmatag, kva, 3546 sizeof(struct bge_ring_data)); 3547 bus_dmamem_free(sc->bge_dmatag, &seg, rseg); 3548 return; 3549 } 3550 DPRINTFN(5, ("bus_dmamem_load\n")); 3551 if (bus_dmamap_load(sc->bge_dmatag, sc->bge_ring_map, kva, 3552 sizeof(struct bge_ring_data), NULL, 3553 BUS_DMA_NOWAIT)) { 3554 bus_dmamap_destroy(sc->bge_dmatag, sc->bge_ring_map); 3555 bus_dmamem_unmap(sc->bge_dmatag, kva, 3556 sizeof(struct bge_ring_data)); 3557 bus_dmamem_free(sc->bge_dmatag, &seg, rseg); 3558 return; 3559 } 3560 3561 DPRINTFN(5, ("bzero\n")); 3562 sc->bge_rdata = (struct bge_ring_data *)kva; 3563 3564 memset(sc->bge_rdata, 0, sizeof(struct bge_ring_data)); 3565 3566 /* Try to allocate memory for jumbo buffers. */ 3567 if (BGE_IS_JUMBO_CAPABLE(sc)) { 3568 if (bge_alloc_jumbo_mem(sc)) { 3569 aprint_error_dev(sc->bge_dev, 3570 "jumbo buffer allocation failed\n"); 3571 } else 3572 sc->ethercom.ec_capabilities |= ETHERCAP_JUMBO_MTU; 3573 } 3574 3575 /* Set default tuneable values. */ 3576 sc->bge_stat_ticks = BGE_TICKS_PER_SEC; 3577 sc->bge_rx_coal_ticks = 150; 3578 sc->bge_rx_max_coal_bds = 64; 3579 #ifdef ORIG_WPAUL_VALUES 3580 sc->bge_tx_coal_ticks = 150; 3581 sc->bge_tx_max_coal_bds = 128; 3582 #else 3583 sc->bge_tx_coal_ticks = 300; 3584 sc->bge_tx_max_coal_bds = 400; 3585 #endif 3586 if (BGE_IS_5705_PLUS(sc)) { 3587 sc->bge_tx_coal_ticks = (12 * 5); 3588 sc->bge_tx_max_coal_bds = (12 * 5); 3589 aprint_verbose_dev(sc->bge_dev, 3590 "setting short Tx thresholds\n"); 3591 } 3592 3593 if (BGE_IS_5717_PLUS(sc)) 3594 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT; 3595 else if (BGE_IS_5705_PLUS(sc)) 3596 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT_5705; 3597 else 3598 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT; 3599 3600 /* Set up ifnet structure */ 3601 ifp = &sc->ethercom.ec_if; 3602 ifp->if_softc = sc; 3603 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 3604 ifp->if_ioctl = bge_ioctl; 3605 ifp->if_stop = bge_stop; 3606 ifp->if_start = bge_start; 3607 ifp->if_init = bge_init; 3608 ifp->if_watchdog = bge_watchdog; 3609 IFQ_SET_MAXLEN(&ifp->if_snd, max(BGE_TX_RING_CNT - 1, IFQ_MAXLEN)); 3610 IFQ_SET_READY(&ifp->if_snd); 3611 DPRINTFN(5, ("strcpy if_xname\n")); 3612 strcpy(ifp->if_xname, device_xname(sc->bge_dev)); 3613 3614 if (sc->bge_chipid != BGE_CHIPID_BCM5700_B0) 3615 sc->ethercom.ec_if.if_capabilities |= 3616 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx; 3617 #if 1 /* XXX TCP/UDP checksum offload breaks with pf(4) */ 3618 sc->ethercom.ec_if.if_capabilities |= 3619 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 3620 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 3621 #endif 3622 sc->ethercom.ec_capabilities |= 3623 ETHERCAP_VLAN_HWTAGGING | ETHERCAP_VLAN_MTU; 3624 3625 if (sc->bge_flags & BGE_TSO) 3626 sc->ethercom.ec_if.if_capabilities |= IFCAP_TSOv4; 3627 3628 /* 3629 * Do MII setup. 3630 */ 3631 DPRINTFN(5, ("mii setup\n")); 3632 sc->bge_mii.mii_ifp = ifp; 3633 sc->bge_mii.mii_readreg = bge_miibus_readreg; 3634 sc->bge_mii.mii_writereg = bge_miibus_writereg; 3635 sc->bge_mii.mii_statchg = bge_miibus_statchg; 3636 3637 /* 3638 * Figure out what sort of media we have by checking the hardware 3639 * config word in the first 32k of NIC internal memory, or fall back to 3640 * the config word in the EEPROM. Note: on some BCM5700 cards, 3641 * this value appears to be unset. If that's the case, we have to rely 3642 * on identifying the NIC by its PCI subsystem ID, as we do below for 3643 * the SysKonnect SK-9D41. 3644 */ 3645 if (bge_readmem_ind(sc, BGE_SRAM_DATA_SIG) == BGE_SRAM_DATA_SIG_MAGIC) { 3646 hwcfg = bge_readmem_ind(sc, BGE_SRAM_DATA_CFG); 3647 } else if (!(sc->bge_flags & BGE_NO_EEPROM)) { 3648 bge_read_eeprom(sc, (void *)&hwcfg, 3649 BGE_EE_HWCFG_OFFSET, sizeof(hwcfg)); 3650 hwcfg = be32toh(hwcfg); 3651 } 3652 /* The SysKonnect SK-9D41 is a 1000baseSX card. */ 3653 if (PCI_PRODUCT(pa->pa_id) == SK_SUBSYSID_9D41 || 3654 (hwcfg & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER) { 3655 if (BGE_IS_5714_FAMILY(sc)) 3656 sc->bge_flags |= BGE_PHY_FIBER_MII; 3657 else 3658 sc->bge_flags |= BGE_PHY_FIBER_TBI; 3659 } 3660 3661 /* set phyflags and chipid before mii_attach() */ 3662 dict = device_properties(self); 3663 prop_dictionary_set_uint32(dict, "phyflags", sc->bge_flags); 3664 prop_dictionary_set_uint32(dict, "chipid", sc->bge_chipid); 3665 3666 if (sc->bge_flags & BGE_PHY_FIBER_TBI) { 3667 ifmedia_init(&sc->bge_ifmedia, IFM_IMASK, bge_ifmedia_upd, 3668 bge_ifmedia_sts); 3669 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER |IFM_1000_SX, 0, NULL); 3670 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_1000_SX|IFM_FDX, 3671 0, NULL); 3672 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_AUTO, 0, NULL); 3673 ifmedia_set(&sc->bge_ifmedia, IFM_ETHER | IFM_AUTO); 3674 /* Pretend the user requested this setting */ 3675 sc->bge_ifmedia.ifm_media = sc->bge_ifmedia.ifm_cur->ifm_media; 3676 } else { 3677 /* 3678 * Do transceiver setup and tell the firmware the 3679 * driver is down so we can try to get access the 3680 * probe if ASF is running. Retry a couple of times 3681 * if we get a conflict with the ASF firmware accessing 3682 * the PHY. 3683 */ 3684 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 3685 bge_asf_driver_up(sc); 3686 3687 ifmedia_init(&sc->bge_mii.mii_media, 0, bge_ifmedia_upd, 3688 bge_ifmedia_sts); 3689 mii_attach(sc->bge_dev, &sc->bge_mii, 0xffffffff, 3690 sc->bge_phy_addr, MII_OFFSET_ANY, 3691 MIIF_DOPAUSE); 3692 3693 if (LIST_EMPTY(&sc->bge_mii.mii_phys)) { 3694 aprint_error_dev(sc->bge_dev, "no PHY found!\n"); 3695 ifmedia_add(&sc->bge_mii.mii_media, 3696 IFM_ETHER|IFM_MANUAL, 0, NULL); 3697 ifmedia_set(&sc->bge_mii.mii_media, 3698 IFM_ETHER|IFM_MANUAL); 3699 } else 3700 ifmedia_set(&sc->bge_mii.mii_media, 3701 IFM_ETHER|IFM_AUTO); 3702 3703 /* 3704 * Now tell the firmware we are going up after probing the PHY 3705 */ 3706 if (sc->bge_asf_mode & ASF_STACKUP) 3707 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 3708 } 3709 3710 /* 3711 * Call MI attach routine. 3712 */ 3713 DPRINTFN(5, ("if_attach\n")); 3714 if_attach(ifp); 3715 DPRINTFN(5, ("ether_ifattach\n")); 3716 ether_ifattach(ifp, eaddr); 3717 ether_set_ifflags_cb(&sc->ethercom, bge_ifflags_cb); 3718 rnd_attach_source(&sc->rnd_source, device_xname(sc->bge_dev), 3719 RND_TYPE_NET, 0); 3720 #ifdef BGE_EVENT_COUNTERS 3721 /* 3722 * Attach event counters. 3723 */ 3724 evcnt_attach_dynamic(&sc->bge_ev_intr, EVCNT_TYPE_INTR, 3725 NULL, device_xname(sc->bge_dev), "intr"); 3726 evcnt_attach_dynamic(&sc->bge_ev_tx_xoff, EVCNT_TYPE_MISC, 3727 NULL, device_xname(sc->bge_dev), "tx_xoff"); 3728 evcnt_attach_dynamic(&sc->bge_ev_tx_xon, EVCNT_TYPE_MISC, 3729 NULL, device_xname(sc->bge_dev), "tx_xon"); 3730 evcnt_attach_dynamic(&sc->bge_ev_rx_xoff, EVCNT_TYPE_MISC, 3731 NULL, device_xname(sc->bge_dev), "rx_xoff"); 3732 evcnt_attach_dynamic(&sc->bge_ev_rx_xon, EVCNT_TYPE_MISC, 3733 NULL, device_xname(sc->bge_dev), "rx_xon"); 3734 evcnt_attach_dynamic(&sc->bge_ev_rx_macctl, EVCNT_TYPE_MISC, 3735 NULL, device_xname(sc->bge_dev), "rx_macctl"); 3736 evcnt_attach_dynamic(&sc->bge_ev_xoffentered, EVCNT_TYPE_MISC, 3737 NULL, device_xname(sc->bge_dev), "xoffentered"); 3738 #endif /* BGE_EVENT_COUNTERS */ 3739 DPRINTFN(5, ("callout_init\n")); 3740 callout_init(&sc->bge_timeout, 0); 3741 3742 if (pmf_device_register(self, NULL, NULL)) 3743 pmf_class_network_register(self, ifp); 3744 else 3745 aprint_error_dev(self, "couldn't establish power handler\n"); 3746 3747 bge_sysctl_init(sc); 3748 3749 #ifdef BGE_DEBUG 3750 bge_debug_info(sc); 3751 #endif 3752 } 3753 3754 static void 3755 bge_release_resources(struct bge_softc *sc) 3756 { 3757 if (sc->bge_vpd_prodname != NULL) 3758 free(sc->bge_vpd_prodname, M_DEVBUF); 3759 3760 if (sc->bge_vpd_readonly != NULL) 3761 free(sc->bge_vpd_readonly, M_DEVBUF); 3762 } 3763 3764 static int 3765 bge_reset(struct bge_softc *sc) 3766 { 3767 uint32_t cachesize, command; 3768 uint32_t reset, mac_mode, mac_mode_mask; 3769 pcireg_t devctl, reg; 3770 int i, val; 3771 void (*write_op)(struct bge_softc *, int, int); 3772 3773 mac_mode_mask = BGE_MACMODE_HALF_DUPLEX | BGE_MACMODE_PORTMODE; 3774 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) != 0) 3775 mac_mode_mask |= BGE_MACMODE_APE_RX_EN | BGE_MACMODE_APE_TX_EN; 3776 mac_mode = CSR_READ_4(sc, BGE_MAC_MODE) & mac_mode_mask; 3777 3778 if (BGE_IS_575X_PLUS(sc) && !BGE_IS_5714_FAMILY(sc) && 3779 (BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5906)) { 3780 if (sc->bge_flags & BGE_PCIE) 3781 write_op = bge_writemem_direct; 3782 else 3783 write_op = bge_writemem_ind; 3784 } else 3785 write_op = bge_writereg_ind; 3786 3787 if (BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5700 && 3788 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5701) { 3789 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_SET1); 3790 for (i = 0; i < 8000; i++) { 3791 if (CSR_READ_4(sc, BGE_NVRAM_SWARB) & 3792 BGE_NVRAMSWARB_GNT1) 3793 break; 3794 DELAY(20); 3795 } 3796 if (i == 8000) { 3797 printf("%s: NVRAM lock timedout!\n", 3798 device_xname(sc->bge_dev)); 3799 } 3800 } 3801 /* Take APE lock when performing reset. */ 3802 bge_ape_lock(sc, BGE_APE_LOCK_GRC); 3803 3804 /* Save some important PCI state. */ 3805 cachesize = pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CACHESZ); 3806 command = pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CMD); 3807 3808 /* Step 5b-5d: */ 3809 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MISC_CTL, 3810 BGE_PCIMISCCTL_INDIRECT_ACCESS | BGE_PCIMISCCTL_MASK_PCI_INTR | 3811 BGE_HIF_SWAP_OPTIONS | BGE_PCIMISCCTL_PCISTATE_RW); 3812 3813 /* XXX ???: Disable fastboot on controllers that support it. */ 3814 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5752 || 3815 BGE_IS_5755_PLUS(sc)) 3816 CSR_WRITE_4(sc, BGE_FASTBOOT_PC, 0); 3817 3818 /* 3819 * Step 6: Write the magic number to SRAM at offset 0xB50. 3820 * When firmware finishes its initialization it will 3821 * write ~BGE_MAGIC_NUMBER to the same location. 3822 */ 3823 bge_writemem_ind(sc, BGE_SRAM_FW_MB, BGE_SRAM_FW_MB_MAGIC); 3824 3825 /* Step 7: */ 3826 reset = BGE_MISCCFG_RESET_CORE_CLOCKS | BGE_32BITTIME_66MHZ; 3827 /* 3828 * XXX: from FreeBSD/Linux; no documentation 3829 */ 3830 if (sc->bge_flags & BGE_PCIE) { 3831 if (BGE_ASICREV(sc->bge_chipid != BGE_ASICREV_BCM5785) && 3832 !BGE_IS_57765_PLUS(sc) && 3833 (CSR_READ_4(sc, BGE_PHY_TEST_CTRL_REG) == 3834 (BGE_PHY_PCIE_LTASS_MODE | BGE_PHY_PCIE_SCRAM_MODE))) { 3835 /* PCI Express 1.0 system */ 3836 CSR_WRITE_4(sc, BGE_PHY_TEST_CTRL_REG, 3837 BGE_PHY_PCIE_SCRAM_MODE); 3838 } 3839 if (sc->bge_chipid != BGE_CHIPID_BCM5750_A0) { 3840 /* 3841 * Prevent PCI Express link training 3842 * during global reset. 3843 */ 3844 CSR_WRITE_4(sc, BGE_MISC_CFG, 1 << 29); 3845 reset |= (1<<29); 3846 } 3847 } 3848 3849 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 3850 i = CSR_READ_4(sc, BGE_VCPU_STATUS); 3851 CSR_WRITE_4(sc, BGE_VCPU_STATUS, 3852 i | BGE_VCPU_STATUS_DRV_RESET); 3853 i = CSR_READ_4(sc, BGE_VCPU_EXT_CTRL); 3854 CSR_WRITE_4(sc, BGE_VCPU_EXT_CTRL, 3855 i & ~BGE_VCPU_EXT_CTRL_HALT_CPU); 3856 } 3857 3858 /* 3859 * Set GPHY Power Down Override to leave GPHY 3860 * powered up in D0 uninitialized. 3861 */ 3862 if (BGE_IS_5705_PLUS(sc) && 3863 (sc->bge_flags & BGE_CPMU_PRESENT) == 0) 3864 reset |= BGE_MISCCFG_GPHY_PD_OVERRIDE; 3865 3866 /* XXX 5721, 5751 and 5752 */ 3867 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5750) 3868 reset |= BGE_MISCCFG_GRC_RESET_DISABLE; 3869 3870 /* Issue global reset */ 3871 write_op(sc, BGE_MISC_CFG, reset); 3872 3873 /* Step 8: wait for complete */ 3874 if (sc->bge_flags & BGE_PCIE) 3875 delay(100*1000); /* too big */ 3876 else 3877 delay(1000); 3878 3879 if (sc->bge_flags & BGE_PCIE) { 3880 if (sc->bge_chipid == BGE_CHIPID_BCM5750_A0) { 3881 DELAY(500000); 3882 /* XXX: Magic Numbers */ 3883 reg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 3884 BGE_PCI_UNKNOWN0); 3885 pci_conf_write(sc->sc_pc, sc->sc_pcitag, 3886 BGE_PCI_UNKNOWN0, 3887 reg | (1 << 15)); 3888 } 3889 devctl = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 3890 sc->bge_pciecap + PCI_PCIE_DCSR); 3891 /* Clear enable no snoop and disable relaxed ordering. */ 3892 devctl &= ~(PCI_PCIE_DCSR_ENA_RELAX_ORD | 3893 PCI_PCIE_DCSR_ENA_NO_SNOOP); 3894 3895 /* Set PCIE max payload size to 128 for older PCIe devices */ 3896 if ((sc->bge_flags & BGE_CPMU_PRESENT) == 0) 3897 devctl &= ~(0x00e0); 3898 /* Clear device status register. Write 1b to clear */ 3899 devctl |= PCI_PCIE_DCSR_URD | PCI_PCIE_DCSR_FED 3900 | PCI_PCIE_DCSR_NFED | PCI_PCIE_DCSR_CED; 3901 pci_conf_write(sc->sc_pc, sc->sc_pcitag, 3902 sc->bge_pciecap + PCI_PCIE_DCSR, devctl); 3903 bge_set_max_readrq(sc); 3904 } 3905 3906 /* From Linux: dummy read to flush PCI posted writes */ 3907 reg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CMD); 3908 3909 /* Step 9-10: Reset some of the PCI state that got zapped by reset */ 3910 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MISC_CTL, 3911 BGE_PCIMISCCTL_INDIRECT_ACCESS | BGE_PCIMISCCTL_MASK_PCI_INTR | 3912 BGE_HIF_SWAP_OPTIONS | BGE_PCIMISCCTL_PCISTATE_RW); 3913 val = BGE_PCISTATE_ROM_ENABLE | BGE_PCISTATE_ROM_RETRY_ENABLE; 3914 if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0 && 3915 (sc->bge_flags & BGE_PCIX) != 0) 3916 val |= BGE_PCISTATE_RETRY_SAME_DMA; 3917 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) != 0) 3918 val |= BGE_PCISTATE_ALLOW_APE_CTLSPC_WR | 3919 BGE_PCISTATE_ALLOW_APE_SHMEM_WR | 3920 BGE_PCISTATE_ALLOW_APE_PSPACE_WR; 3921 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_PCISTATE, val); 3922 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CACHESZ, cachesize); 3923 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CMD, command); 3924 3925 /* Step 11: disable PCI-X Relaxed Ordering. */ 3926 if (sc->bge_flags & BGE_PCIX) { 3927 reg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, sc->bge_pcixcap 3928 + PCI_PCIX_CMD); 3929 pci_conf_write(sc->sc_pc, sc->sc_pcitag, sc->bge_pcixcap 3930 + PCI_PCIX_CMD, reg & ~PCI_PCIX_CMD_RELAXED_ORDER); 3931 } 3932 3933 /* Step 12: Enable memory arbiter. */ 3934 if (BGE_IS_5714_FAMILY(sc)) { 3935 val = CSR_READ_4(sc, BGE_MARB_MODE); 3936 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE | val); 3937 } else 3938 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 3939 3940 /* XXX 5721, 5751 and 5752 */ 3941 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5750) { 3942 /* Step 19: */ 3943 BGE_SETBIT(sc, BGE_TLP_CONTROL_REG, 1 << 29 | 1 << 25); 3944 /* Step 20: */ 3945 BGE_SETBIT(sc, BGE_TLP_CONTROL_REG, BGE_TLP_DATA_FIFO_PROTECT); 3946 } 3947 3948 /* Step 28: Fix up byte swapping */ 3949 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS); 3950 3951 /* Step 21: 5822 B0 errata */ 3952 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5704_BX) { 3953 pcireg_t msidata; 3954 3955 msidata = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 3956 BGE_PCI_MSI_DATA); 3957 msidata |= ((1 << 13 | 1 << 12 | 1 << 10) << 16); 3958 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MSI_DATA, 3959 msidata); 3960 } 3961 3962 /* 3963 * Step 18: wirte mac mode 3964 * XXX Write 0x0c for 5703S and 5704S 3965 */ 3966 val = CSR_READ_4(sc, BGE_MAC_MODE); 3967 val = (val & ~mac_mode_mask) | mac_mode; 3968 CSR_WRITE_4_FLUSH(sc, BGE_MAC_MODE, val); 3969 DELAY(40); 3970 3971 bge_ape_unlock(sc, BGE_APE_LOCK_GRC); 3972 3973 /* Step 17: Poll until the firmware initialization is complete */ 3974 bge_poll_fw(sc); 3975 3976 /* 3977 * The 5704 in TBI mode apparently needs some special 3978 * adjustment to insure the SERDES drive level is set 3979 * to 1.2V. 3980 */ 3981 if (sc->bge_flags & BGE_PHY_FIBER_TBI && 3982 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) { 3983 uint32_t serdescfg; 3984 3985 serdescfg = CSR_READ_4(sc, BGE_SERDES_CFG); 3986 serdescfg = (serdescfg & ~0xFFF) | 0x880; 3987 CSR_WRITE_4(sc, BGE_SERDES_CFG, serdescfg); 3988 } 3989 3990 if (sc->bge_flags & BGE_PCIE && 3991 !BGE_IS_57765_PLUS(sc) && 3992 sc->bge_chipid != BGE_CHIPID_BCM5750_A0 && 3993 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5785) { 3994 uint32_t v; 3995 3996 /* Enable PCI Express bug fix */ 3997 v = CSR_READ_4(sc, BGE_TLP_CONTROL_REG); 3998 CSR_WRITE_4(sc, BGE_TLP_CONTROL_REG, 3999 v | BGE_TLP_DATA_FIFO_PROTECT); 4000 } 4001 4002 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) 4003 BGE_CLRBIT(sc, BGE_CPMU_CLCK_ORIDE, 4004 CPMU_CLCK_ORIDE_MAC_ORIDE_EN); 4005 4006 return 0; 4007 } 4008 4009 /* 4010 * Frame reception handling. This is called if there's a frame 4011 * on the receive return list. 4012 * 4013 * Note: we have to be able to handle two possibilities here: 4014 * 1) the frame is from the jumbo receive ring 4015 * 2) the frame is from the standard receive ring 4016 */ 4017 4018 static void 4019 bge_rxeof(struct bge_softc *sc) 4020 { 4021 struct ifnet *ifp; 4022 uint16_t rx_prod, rx_cons; 4023 int stdcnt = 0, jumbocnt = 0; 4024 bus_dmamap_t dmamap; 4025 bus_addr_t offset, toff; 4026 bus_size_t tlen; 4027 int tosync; 4028 4029 rx_cons = sc->bge_rx_saved_considx; 4030 rx_prod = sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx; 4031 4032 /* Nothing to do */ 4033 if (rx_cons == rx_prod) 4034 return; 4035 4036 ifp = &sc->ethercom.ec_if; 4037 4038 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 4039 offsetof(struct bge_ring_data, bge_status_block), 4040 sizeof (struct bge_status_block), 4041 BUS_DMASYNC_POSTREAD); 4042 4043 offset = offsetof(struct bge_ring_data, bge_rx_return_ring); 4044 tosync = rx_prod - rx_cons; 4045 4046 if (tosync != 0) 4047 rnd_add_uint32(&sc->rnd_source, tosync); 4048 4049 toff = offset + (rx_cons * sizeof (struct bge_rx_bd)); 4050 4051 if (tosync < 0) { 4052 tlen = (sc->bge_return_ring_cnt - rx_cons) * 4053 sizeof (struct bge_rx_bd); 4054 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 4055 toff, tlen, BUS_DMASYNC_POSTREAD); 4056 tosync = -tosync; 4057 } 4058 4059 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 4060 offset, tosync * sizeof (struct bge_rx_bd), 4061 BUS_DMASYNC_POSTREAD); 4062 4063 while (rx_cons != rx_prod) { 4064 struct bge_rx_bd *cur_rx; 4065 uint32_t rxidx; 4066 struct mbuf *m = NULL; 4067 4068 cur_rx = &sc->bge_rdata->bge_rx_return_ring[rx_cons]; 4069 4070 rxidx = cur_rx->bge_idx; 4071 BGE_INC(rx_cons, sc->bge_return_ring_cnt); 4072 4073 if (cur_rx->bge_flags & BGE_RXBDFLAG_JUMBO_RING) { 4074 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT); 4075 m = sc->bge_cdata.bge_rx_jumbo_chain[rxidx]; 4076 sc->bge_cdata.bge_rx_jumbo_chain[rxidx] = NULL; 4077 jumbocnt++; 4078 bus_dmamap_sync(sc->bge_dmatag, 4079 sc->bge_cdata.bge_rx_jumbo_map, 4080 mtod(m, char *) - (char *)sc->bge_cdata.bge_jumbo_buf, 4081 BGE_JLEN, BUS_DMASYNC_POSTREAD); 4082 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 4083 ifp->if_ierrors++; 4084 bge_newbuf_jumbo(sc, sc->bge_jumbo, m); 4085 continue; 4086 } 4087 if (bge_newbuf_jumbo(sc, sc->bge_jumbo, 4088 NULL)== ENOBUFS) { 4089 ifp->if_ierrors++; 4090 bge_newbuf_jumbo(sc, sc->bge_jumbo, m); 4091 continue; 4092 } 4093 } else { 4094 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT); 4095 m = sc->bge_cdata.bge_rx_std_chain[rxidx]; 4096 4097 sc->bge_cdata.bge_rx_std_chain[rxidx] = NULL; 4098 stdcnt++; 4099 dmamap = sc->bge_cdata.bge_rx_std_map[rxidx]; 4100 sc->bge_cdata.bge_rx_std_map[rxidx] = 0; 4101 if (dmamap == NULL) { 4102 ifp->if_ierrors++; 4103 bge_newbuf_std(sc, sc->bge_std, m, dmamap); 4104 continue; 4105 } 4106 bus_dmamap_sync(sc->bge_dmatag, dmamap, 0, 4107 dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 4108 bus_dmamap_unload(sc->bge_dmatag, dmamap); 4109 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 4110 ifp->if_ierrors++; 4111 bge_newbuf_std(sc, sc->bge_std, m, dmamap); 4112 continue; 4113 } 4114 if (bge_newbuf_std(sc, sc->bge_std, 4115 NULL, dmamap) == ENOBUFS) { 4116 ifp->if_ierrors++; 4117 bge_newbuf_std(sc, sc->bge_std, m, dmamap); 4118 continue; 4119 } 4120 } 4121 4122 ifp->if_ipackets++; 4123 #ifndef __NO_STRICT_ALIGNMENT 4124 /* 4125 * XXX: if the 5701 PCIX-Rx-DMA workaround is in effect, 4126 * the Rx buffer has the layer-2 header unaligned. 4127 * If our CPU requires alignment, re-align by copying. 4128 */ 4129 if (sc->bge_flags & BGE_RX_ALIGNBUG) { 4130 memmove(mtod(m, char *) + ETHER_ALIGN, m->m_data, 4131 cur_rx->bge_len); 4132 m->m_data += ETHER_ALIGN; 4133 } 4134 #endif 4135 4136 m->m_pkthdr.len = m->m_len = cur_rx->bge_len - ETHER_CRC_LEN; 4137 m->m_pkthdr.rcvif = ifp; 4138 4139 /* 4140 * Handle BPF listeners. Let the BPF user see the packet. 4141 */ 4142 bpf_mtap(ifp, m); 4143 4144 m->m_pkthdr.csum_flags = M_CSUM_IPv4; 4145 4146 if (BGE_IS_5717_PLUS(sc)) { 4147 if ((cur_rx->bge_error_flag & 4148 BGE_RXERRFLAG_IP_CSUM_NOK) != 0) 4149 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 4150 } else { 4151 if ((cur_rx->bge_ip_csum ^ 0xffff) != 0) 4152 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 4153 } 4154 /* 4155 * Rx transport checksum-offload may also 4156 * have bugs with packets which, when transmitted, 4157 * were `runts' requiring padding. 4158 */ 4159 if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM && 4160 (/* (sc->_bge_quirks & BGE_QUIRK_SHORT_CKSUM_BUG) == 0 ||*/ 4161 m->m_pkthdr.len >= ETHER_MIN_NOPAD)) { 4162 m->m_pkthdr.csum_data = 4163 cur_rx->bge_tcp_udp_csum; 4164 m->m_pkthdr.csum_flags |= 4165 (M_CSUM_TCPv4|M_CSUM_UDPv4| 4166 M_CSUM_DATA); 4167 } 4168 4169 /* 4170 * If we received a packet with a vlan tag, pass it 4171 * to vlan_input() instead of ether_input(). 4172 */ 4173 if (cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) { 4174 VLAN_INPUT_TAG(ifp, m, cur_rx->bge_vlan_tag, continue); 4175 } 4176 4177 (*ifp->if_input)(ifp, m); 4178 } 4179 4180 sc->bge_rx_saved_considx = rx_cons; 4181 bge_writembx(sc, BGE_MBX_RX_CONS0_LO, sc->bge_rx_saved_considx); 4182 if (stdcnt) 4183 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std); 4184 if (jumbocnt) 4185 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo); 4186 } 4187 4188 static void 4189 bge_txeof(struct bge_softc *sc) 4190 { 4191 struct bge_tx_bd *cur_tx = NULL; 4192 struct ifnet *ifp; 4193 struct txdmamap_pool_entry *dma; 4194 bus_addr_t offset, toff; 4195 bus_size_t tlen; 4196 int tosync; 4197 struct mbuf *m; 4198 4199 ifp = &sc->ethercom.ec_if; 4200 4201 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 4202 offsetof(struct bge_ring_data, bge_status_block), 4203 sizeof (struct bge_status_block), 4204 BUS_DMASYNC_POSTREAD); 4205 4206 offset = offsetof(struct bge_ring_data, bge_tx_ring); 4207 tosync = sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx - 4208 sc->bge_tx_saved_considx; 4209 4210 if (tosync != 0) 4211 rnd_add_uint32(&sc->rnd_source, tosync); 4212 4213 toff = offset + (sc->bge_tx_saved_considx * sizeof (struct bge_tx_bd)); 4214 4215 if (tosync < 0) { 4216 tlen = (BGE_TX_RING_CNT - sc->bge_tx_saved_considx) * 4217 sizeof (struct bge_tx_bd); 4218 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 4219 toff, tlen, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 4220 tosync = -tosync; 4221 } 4222 4223 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 4224 offset, tosync * sizeof (struct bge_tx_bd), 4225 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 4226 4227 /* 4228 * Go through our tx ring and free mbufs for those 4229 * frames that have been sent. 4230 */ 4231 while (sc->bge_tx_saved_considx != 4232 sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx) { 4233 uint32_t idx = 0; 4234 4235 idx = sc->bge_tx_saved_considx; 4236 cur_tx = &sc->bge_rdata->bge_tx_ring[idx]; 4237 if (cur_tx->bge_flags & BGE_TXBDFLAG_END) 4238 ifp->if_opackets++; 4239 m = sc->bge_cdata.bge_tx_chain[idx]; 4240 if (m != NULL) { 4241 sc->bge_cdata.bge_tx_chain[idx] = NULL; 4242 dma = sc->txdma[idx]; 4243 bus_dmamap_sync(sc->bge_dmatag, dma->dmamap, 0, 4244 dma->dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 4245 bus_dmamap_unload(sc->bge_dmatag, dma->dmamap); 4246 SLIST_INSERT_HEAD(&sc->txdma_list, dma, link); 4247 sc->txdma[idx] = NULL; 4248 4249 m_freem(m); 4250 } 4251 sc->bge_txcnt--; 4252 BGE_INC(sc->bge_tx_saved_considx, BGE_TX_RING_CNT); 4253 ifp->if_timer = 0; 4254 } 4255 4256 if (cur_tx != NULL) 4257 ifp->if_flags &= ~IFF_OACTIVE; 4258 } 4259 4260 static int 4261 bge_intr(void *xsc) 4262 { 4263 struct bge_softc *sc; 4264 struct ifnet *ifp; 4265 uint32_t statusword; 4266 4267 sc = xsc; 4268 ifp = &sc->ethercom.ec_if; 4269 4270 /* It is possible for the interrupt to arrive before 4271 * the status block is updated prior to the interrupt. 4272 * Reading the PCI State register will confirm whether the 4273 * interrupt is ours and will flush the status block. 4274 */ 4275 4276 /* read status word from status block */ 4277 statusword = sc->bge_rdata->bge_status_block.bge_status; 4278 4279 if ((statusword & BGE_STATFLAG_UPDATED) || 4280 (!(pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_PCISTATE) & 4281 BGE_PCISTATE_INTR_NOT_ACTIVE))) { 4282 /* Ack interrupt and stop others from occuring. */ 4283 bge_writembx_flush(sc, BGE_MBX_IRQ0_LO, 1); 4284 4285 BGE_EVCNT_INCR(sc->bge_ev_intr); 4286 4287 /* clear status word */ 4288 sc->bge_rdata->bge_status_block.bge_status = 0; 4289 4290 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 4291 statusword & BGE_STATFLAG_LINKSTATE_CHANGED || 4292 BGE_STS_BIT(sc, BGE_STS_LINK_EVT)) 4293 bge_link_upd(sc); 4294 4295 if (ifp->if_flags & IFF_RUNNING) { 4296 /* Check RX return ring producer/consumer */ 4297 bge_rxeof(sc); 4298 4299 /* Check TX ring producer/consumer */ 4300 bge_txeof(sc); 4301 } 4302 4303 if (sc->bge_pending_rxintr_change) { 4304 uint32_t rx_ticks = sc->bge_rx_coal_ticks; 4305 uint32_t rx_bds = sc->bge_rx_max_coal_bds; 4306 uint32_t junk; 4307 4308 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, rx_ticks); 4309 DELAY(10); 4310 junk = CSR_READ_4(sc, BGE_HCC_RX_COAL_TICKS); 4311 4312 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, rx_bds); 4313 DELAY(10); 4314 junk = CSR_READ_4(sc, BGE_HCC_RX_MAX_COAL_BDS); 4315 4316 sc->bge_pending_rxintr_change = 0; 4317 } 4318 bge_handle_events(sc); 4319 4320 /* Re-enable interrupts. */ 4321 bge_writembx_flush(sc, BGE_MBX_IRQ0_LO, 0); 4322 4323 if (ifp->if_flags & IFF_RUNNING && !IFQ_IS_EMPTY(&ifp->if_snd)) 4324 bge_start(ifp); 4325 4326 return 1; 4327 } else 4328 return 0; 4329 } 4330 4331 static void 4332 bge_asf_driver_up(struct bge_softc *sc) 4333 { 4334 if (sc->bge_asf_mode & ASF_STACKUP) { 4335 /* Send ASF heartbeat aprox. every 2s */ 4336 if (sc->bge_asf_count) 4337 sc->bge_asf_count --; 4338 else { 4339 sc->bge_asf_count = 2; 4340 4341 bge_wait_for_event_ack(sc); 4342 4343 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_MB, 4344 BGE_FW_CMD_DRV_ALIVE); 4345 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_LEN_MB, 4); 4346 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_DATA_MB, 4347 BGE_FW_HB_TIMEOUT_SEC); 4348 CSR_WRITE_4_FLUSH(sc, BGE_RX_CPU_EVENT, 4349 CSR_READ_4(sc, BGE_RX_CPU_EVENT) | 4350 BGE_RX_CPU_DRV_EVENT); 4351 } 4352 } 4353 } 4354 4355 static void 4356 bge_tick(void *xsc) 4357 { 4358 struct bge_softc *sc = xsc; 4359 struct mii_data *mii = &sc->bge_mii; 4360 int s; 4361 4362 s = splnet(); 4363 4364 if (BGE_IS_5705_PLUS(sc)) 4365 bge_stats_update_regs(sc); 4366 else 4367 bge_stats_update(sc); 4368 4369 if (sc->bge_flags & BGE_PHY_FIBER_TBI) { 4370 /* 4371 * Since in TBI mode auto-polling can't be used we should poll 4372 * link status manually. Here we register pending link event 4373 * and trigger interrupt. 4374 */ 4375 BGE_STS_SETBIT(sc, BGE_STS_LINK_EVT); 4376 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET); 4377 } else { 4378 /* 4379 * Do not touch PHY if we have link up. This could break 4380 * IPMI/ASF mode or produce extra input errors. 4381 * (extra input errors was reported for bcm5701 & bcm5704). 4382 */ 4383 if (!BGE_STS_BIT(sc, BGE_STS_LINK)) 4384 mii_tick(mii); 4385 } 4386 4387 bge_asf_driver_up(sc); 4388 4389 callout_reset(&sc->bge_timeout, hz, bge_tick, sc); 4390 4391 splx(s); 4392 } 4393 4394 static void 4395 bge_stats_update_regs(struct bge_softc *sc) 4396 { 4397 struct ifnet *ifp = &sc->ethercom.ec_if; 4398 4399 ifp->if_collisions += CSR_READ_4(sc, BGE_MAC_STATS + 4400 offsetof(struct bge_mac_stats_regs, etherStatsCollisions)); 4401 4402 ifp->if_ierrors += CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_DROPS); 4403 ifp->if_ierrors += CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_ERRORS); 4404 ifp->if_ierrors += CSR_READ_4(sc, BGE_RXLP_LOCSTAT_OUT_OF_BDS); 4405 } 4406 4407 static void 4408 bge_stats_update(struct bge_softc *sc) 4409 { 4410 struct ifnet *ifp = &sc->ethercom.ec_if; 4411 bus_size_t stats = BGE_MEMWIN_START + BGE_STATS_BLOCK; 4412 4413 #define READ_STAT(sc, stats, stat) \ 4414 CSR_READ_4(sc, stats + offsetof(struct bge_stats, stat)) 4415 4416 ifp->if_collisions += 4417 (READ_STAT(sc, stats, dot3StatsSingleCollisionFrames.bge_addr_lo) + 4418 READ_STAT(sc, stats, dot3StatsMultipleCollisionFrames.bge_addr_lo) + 4419 READ_STAT(sc, stats, dot3StatsExcessiveCollisions.bge_addr_lo) + 4420 READ_STAT(sc, stats, dot3StatsLateCollisions.bge_addr_lo)) - 4421 ifp->if_collisions; 4422 4423 BGE_EVCNT_UPD(sc->bge_ev_tx_xoff, 4424 READ_STAT(sc, stats, outXoffSent.bge_addr_lo)); 4425 BGE_EVCNT_UPD(sc->bge_ev_tx_xon, 4426 READ_STAT(sc, stats, outXonSent.bge_addr_lo)); 4427 BGE_EVCNT_UPD(sc->bge_ev_rx_xoff, 4428 READ_STAT(sc, stats, 4429 xoffPauseFramesReceived.bge_addr_lo)); 4430 BGE_EVCNT_UPD(sc->bge_ev_rx_xon, 4431 READ_STAT(sc, stats, xonPauseFramesReceived.bge_addr_lo)); 4432 BGE_EVCNT_UPD(sc->bge_ev_rx_macctl, 4433 READ_STAT(sc, stats, 4434 macControlFramesReceived.bge_addr_lo)); 4435 BGE_EVCNT_UPD(sc->bge_ev_xoffentered, 4436 READ_STAT(sc, stats, xoffStateEntered.bge_addr_lo)); 4437 4438 #undef READ_STAT 4439 4440 #ifdef notdef 4441 ifp->if_collisions += 4442 (sc->bge_rdata->bge_info.bge_stats.dot3StatsSingleCollisionFrames + 4443 sc->bge_rdata->bge_info.bge_stats.dot3StatsMultipleCollisionFrames + 4444 sc->bge_rdata->bge_info.bge_stats.dot3StatsExcessiveCollisions + 4445 sc->bge_rdata->bge_info.bge_stats.dot3StatsLateCollisions) - 4446 ifp->if_collisions; 4447 #endif 4448 } 4449 4450 /* 4451 * Pad outbound frame to ETHER_MIN_NOPAD for an unusual reason. 4452 * The bge hardware will pad out Tx runts to ETHER_MIN_NOPAD, 4453 * but when such padded frames employ the bge IP/TCP checksum offload, 4454 * the hardware checksum assist gives incorrect results (possibly 4455 * from incorporating its own padding into the UDP/TCP checksum; who knows). 4456 * If we pad such runts with zeros, the onboard checksum comes out correct. 4457 */ 4458 static inline int 4459 bge_cksum_pad(struct mbuf *pkt) 4460 { 4461 struct mbuf *last = NULL; 4462 int padlen; 4463 4464 padlen = ETHER_MIN_NOPAD - pkt->m_pkthdr.len; 4465 4466 /* if there's only the packet-header and we can pad there, use it. */ 4467 if (pkt->m_pkthdr.len == pkt->m_len && 4468 M_TRAILINGSPACE(pkt) >= padlen) { 4469 last = pkt; 4470 } else { 4471 /* 4472 * Walk packet chain to find last mbuf. We will either 4473 * pad there, or append a new mbuf and pad it 4474 * (thus perhaps avoiding the bcm5700 dma-min bug). 4475 */ 4476 for (last = pkt; last->m_next != NULL; last = last->m_next) { 4477 continue; /* do nothing */ 4478 } 4479 4480 /* `last' now points to last in chain. */ 4481 if (M_TRAILINGSPACE(last) < padlen) { 4482 /* Allocate new empty mbuf, pad it. Compact later. */ 4483 struct mbuf *n; 4484 MGET(n, M_DONTWAIT, MT_DATA); 4485 if (n == NULL) 4486 return ENOBUFS; 4487 n->m_len = 0; 4488 last->m_next = n; 4489 last = n; 4490 } 4491 } 4492 4493 KDASSERT(!M_READONLY(last)); 4494 KDASSERT(M_TRAILINGSPACE(last) >= padlen); 4495 4496 /* Now zero the pad area, to avoid the bge cksum-assist bug */ 4497 memset(mtod(last, char *) + last->m_len, 0, padlen); 4498 last->m_len += padlen; 4499 pkt->m_pkthdr.len += padlen; 4500 return 0; 4501 } 4502 4503 /* 4504 * Compact outbound packets to avoid bug with DMA segments less than 8 bytes. 4505 */ 4506 static inline int 4507 bge_compact_dma_runt(struct mbuf *pkt) 4508 { 4509 struct mbuf *m, *prev; 4510 int totlen, prevlen; 4511 4512 prev = NULL; 4513 totlen = 0; 4514 prevlen = -1; 4515 4516 for (m = pkt; m != NULL; prev = m,m = m->m_next) { 4517 int mlen = m->m_len; 4518 int shortfall = 8 - mlen ; 4519 4520 totlen += mlen; 4521 if (mlen == 0) 4522 continue; 4523 if (mlen >= 8) 4524 continue; 4525 4526 /* If we get here, mbuf data is too small for DMA engine. 4527 * Try to fix by shuffling data to prev or next in chain. 4528 * If that fails, do a compacting deep-copy of the whole chain. 4529 */ 4530 4531 /* Internal frag. If fits in prev, copy it there. */ 4532 if (prev && M_TRAILINGSPACE(prev) >= m->m_len) { 4533 memcpy(prev->m_data + prev->m_len, m->m_data, mlen); 4534 prev->m_len += mlen; 4535 m->m_len = 0; 4536 /* XXX stitch chain */ 4537 prev->m_next = m_free(m); 4538 m = prev; 4539 continue; 4540 } 4541 else if (m->m_next != NULL && 4542 M_TRAILINGSPACE(m) >= shortfall && 4543 m->m_next->m_len >= (8 + shortfall)) { 4544 /* m is writable and have enough data in next, pull up. */ 4545 4546 memcpy(m->m_data + m->m_len, m->m_next->m_data, 4547 shortfall); 4548 m->m_len += shortfall; 4549 m->m_next->m_len -= shortfall; 4550 m->m_next->m_data += shortfall; 4551 } 4552 else if (m->m_next == NULL || 1) { 4553 /* Got a runt at the very end of the packet. 4554 * borrow data from the tail of the preceding mbuf and 4555 * update its length in-place. (The original data is still 4556 * valid, so we can do this even if prev is not writable.) 4557 */ 4558 4559 /* if we'd make prev a runt, just move all of its data. */ 4560 KASSERT(prev != NULL /*, ("runt but null PREV")*/); 4561 KASSERT(prev->m_len >= 8 /*, ("runt prev")*/); 4562 4563 if ((prev->m_len - shortfall) < 8) 4564 shortfall = prev->m_len; 4565 4566 #ifdef notyet /* just do the safe slow thing for now */ 4567 if (!M_READONLY(m)) { 4568 if (M_LEADINGSPACE(m) < shorfall) { 4569 void *m_dat; 4570 m_dat = (m->m_flags & M_PKTHDR) ? 4571 m->m_pktdat : m->dat; 4572 memmove(m_dat, mtod(m, void*), m->m_len); 4573 m->m_data = m_dat; 4574 } 4575 } else 4576 #endif /* just do the safe slow thing */ 4577 { 4578 struct mbuf * n = NULL; 4579 int newprevlen = prev->m_len - shortfall; 4580 4581 MGET(n, M_NOWAIT, MT_DATA); 4582 if (n == NULL) 4583 return ENOBUFS; 4584 KASSERT(m->m_len + shortfall < MLEN 4585 /*, 4586 ("runt %d +prev %d too big\n", m->m_len, shortfall)*/); 4587 4588 /* first copy the data we're stealing from prev */ 4589 memcpy(n->m_data, prev->m_data + newprevlen, 4590 shortfall); 4591 4592 /* update prev->m_len accordingly */ 4593 prev->m_len -= shortfall; 4594 4595 /* copy data from runt m */ 4596 memcpy(n->m_data + shortfall, m->m_data, 4597 m->m_len); 4598 4599 /* n holds what we stole from prev, plus m */ 4600 n->m_len = shortfall + m->m_len; 4601 4602 /* stitch n into chain and free m */ 4603 n->m_next = m->m_next; 4604 prev->m_next = n; 4605 /* KASSERT(m->m_next == NULL); */ 4606 m->m_next = NULL; 4607 m_free(m); 4608 m = n; /* for continuing loop */ 4609 } 4610 } 4611 prevlen = m->m_len; 4612 } 4613 return 0; 4614 } 4615 4616 /* 4617 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data 4618 * pointers to descriptors. 4619 */ 4620 static int 4621 bge_encap(struct bge_softc *sc, struct mbuf *m_head, uint32_t *txidx) 4622 { 4623 struct bge_tx_bd *f = NULL; 4624 uint32_t frag, cur; 4625 uint16_t csum_flags = 0; 4626 uint16_t txbd_tso_flags = 0; 4627 struct txdmamap_pool_entry *dma; 4628 bus_dmamap_t dmamap; 4629 int i = 0; 4630 struct m_tag *mtag; 4631 int use_tso, maxsegsize, error; 4632 4633 cur = frag = *txidx; 4634 4635 if (m_head->m_pkthdr.csum_flags) { 4636 if (m_head->m_pkthdr.csum_flags & M_CSUM_IPv4) 4637 csum_flags |= BGE_TXBDFLAG_IP_CSUM; 4638 if (m_head->m_pkthdr.csum_flags & (M_CSUM_TCPv4|M_CSUM_UDPv4)) 4639 csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM; 4640 } 4641 4642 /* 4643 * If we were asked to do an outboard checksum, and the NIC 4644 * has the bug where it sometimes adds in the Ethernet padding, 4645 * explicitly pad with zeros so the cksum will be correct either way. 4646 * (For now, do this for all chip versions, until newer 4647 * are confirmed to not require the workaround.) 4648 */ 4649 if ((csum_flags & BGE_TXBDFLAG_TCP_UDP_CSUM) == 0 || 4650 #ifdef notyet 4651 (sc->bge_quirks & BGE_QUIRK_SHORT_CKSUM_BUG) == 0 || 4652 #endif 4653 m_head->m_pkthdr.len >= ETHER_MIN_NOPAD) 4654 goto check_dma_bug; 4655 4656 if (bge_cksum_pad(m_head) != 0) 4657 return ENOBUFS; 4658 4659 check_dma_bug: 4660 if (!(BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX)) 4661 goto doit; 4662 4663 /* 4664 * bcm5700 Revision B silicon cannot handle DMA descriptors with 4665 * less than eight bytes. If we encounter a teeny mbuf 4666 * at the end of a chain, we can pad. Otherwise, copy. 4667 */ 4668 if (bge_compact_dma_runt(m_head) != 0) 4669 return ENOBUFS; 4670 4671 doit: 4672 dma = SLIST_FIRST(&sc->txdma_list); 4673 if (dma == NULL) 4674 return ENOBUFS; 4675 dmamap = dma->dmamap; 4676 4677 /* 4678 * Set up any necessary TSO state before we start packing... 4679 */ 4680 use_tso = (m_head->m_pkthdr.csum_flags & M_CSUM_TSOv4) != 0; 4681 if (!use_tso) { 4682 maxsegsize = 0; 4683 } else { /* TSO setup */ 4684 unsigned mss; 4685 struct ether_header *eh; 4686 unsigned ip_tcp_hlen, iptcp_opt_words, tcp_seg_flags, offset; 4687 struct mbuf * m0 = m_head; 4688 struct ip *ip; 4689 struct tcphdr *th; 4690 int iphl, hlen; 4691 4692 /* 4693 * XXX It would be nice if the mbuf pkthdr had offset 4694 * fields for the protocol headers. 4695 */ 4696 4697 eh = mtod(m0, struct ether_header *); 4698 switch (htons(eh->ether_type)) { 4699 case ETHERTYPE_IP: 4700 offset = ETHER_HDR_LEN; 4701 break; 4702 4703 case ETHERTYPE_VLAN: 4704 offset = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 4705 break; 4706 4707 default: 4708 /* 4709 * Don't support this protocol or encapsulation. 4710 */ 4711 return ENOBUFS; 4712 } 4713 4714 /* 4715 * TCP/IP headers are in the first mbuf; we can do 4716 * this the easy way. 4717 */ 4718 iphl = M_CSUM_DATA_IPv4_IPHL(m0->m_pkthdr.csum_data); 4719 hlen = iphl + offset; 4720 if (__predict_false(m0->m_len < 4721 (hlen + sizeof(struct tcphdr)))) { 4722 4723 aprint_debug_dev(sc->bge_dev, 4724 "TSO: hard case m0->m_len == %d < ip/tcp hlen %zd," 4725 "not handled yet\n", 4726 m0->m_len, hlen+ sizeof(struct tcphdr)); 4727 #ifdef NOTYET 4728 /* 4729 * XXX jonathan (at) NetBSD.org: untested. 4730 * how to force this branch to be taken? 4731 */ 4732 BGE_EVCNT_INCR(&sc->sc_ev_txtsopain); 4733 4734 m_copydata(m0, offset, sizeof(ip), &ip); 4735 m_copydata(m0, hlen, sizeof(th), &th); 4736 4737 ip.ip_len = 0; 4738 4739 m_copyback(m0, hlen + offsetof(struct ip, ip_len), 4740 sizeof(ip.ip_len), &ip.ip_len); 4741 4742 th.th_sum = in_cksum_phdr(ip.ip_src.s_addr, 4743 ip.ip_dst.s_addr, htons(IPPROTO_TCP)); 4744 4745 m_copyback(m0, hlen + offsetof(struct tcphdr, th_sum), 4746 sizeof(th.th_sum), &th.th_sum); 4747 4748 hlen += th.th_off << 2; 4749 iptcp_opt_words = hlen; 4750 #else 4751 /* 4752 * if_wm "hard" case not yet supported, can we not 4753 * mandate it out of existence? 4754 */ 4755 (void) ip; (void)th; (void) ip_tcp_hlen; 4756 4757 return ENOBUFS; 4758 #endif 4759 } else { 4760 ip = (struct ip *) (mtod(m0, char *) + offset); 4761 th = (struct tcphdr *) (mtod(m0, char *) + hlen); 4762 ip_tcp_hlen = iphl + (th->th_off << 2); 4763 4764 /* Total IP/TCP options, in 32-bit words */ 4765 iptcp_opt_words = (ip_tcp_hlen 4766 - sizeof(struct tcphdr) 4767 - sizeof(struct ip)) >> 2; 4768 } 4769 if (BGE_IS_575X_PLUS(sc)) { 4770 th->th_sum = 0; 4771 csum_flags &= ~(BGE_TXBDFLAG_TCP_UDP_CSUM); 4772 } else { 4773 /* 4774 * XXX jonathan (at) NetBSD.org: 5705 untested. 4775 * Requires TSO firmware patch for 5701/5703/5704. 4776 */ 4777 th->th_sum = in_cksum_phdr(ip->ip_src.s_addr, 4778 ip->ip_dst.s_addr, htons(IPPROTO_TCP)); 4779 } 4780 4781 mss = m_head->m_pkthdr.segsz; 4782 txbd_tso_flags |= 4783 BGE_TXBDFLAG_CPU_PRE_DMA | 4784 BGE_TXBDFLAG_CPU_POST_DMA; 4785 4786 /* 4787 * Our NIC TSO-assist assumes TSO has standard, optionless 4788 * IPv4 and TCP headers, which total 40 bytes. By default, 4789 * the NIC copies 40 bytes of IP/TCP header from the 4790 * supplied header into the IP/TCP header portion of 4791 * each post-TSO-segment. If the supplied packet has IP or 4792 * TCP options, we need to tell the NIC to copy those extra 4793 * bytes into each post-TSO header, in addition to the normal 4794 * 40-byte IP/TCP header (and to leave space accordingly). 4795 * Unfortunately, the driver encoding of option length 4796 * varies across different ASIC families. 4797 */ 4798 tcp_seg_flags = 0; 4799 if (iptcp_opt_words) { 4800 if (BGE_IS_5705_PLUS(sc)) { 4801 tcp_seg_flags = 4802 iptcp_opt_words << 11; 4803 } else { 4804 txbd_tso_flags |= 4805 iptcp_opt_words << 12; 4806 } 4807 } 4808 maxsegsize = mss | tcp_seg_flags; 4809 ip->ip_len = htons(mss + ip_tcp_hlen); 4810 4811 } /* TSO setup */ 4812 4813 /* 4814 * Start packing the mbufs in this chain into 4815 * the fragment pointers. Stop when we run out 4816 * of fragments or hit the end of the mbuf chain. 4817 */ 4818 error = bus_dmamap_load_mbuf(sc->bge_dmatag, dmamap, m_head, 4819 BUS_DMA_NOWAIT); 4820 if (error) 4821 return ENOBUFS; 4822 /* 4823 * Sanity check: avoid coming within 16 descriptors 4824 * of the end of the ring. 4825 */ 4826 if (dmamap->dm_nsegs > (BGE_TX_RING_CNT - sc->bge_txcnt - 16)) { 4827 BGE_TSO_PRINTF(("%s: " 4828 " dmamap_load_mbuf too close to ring wrap\n", 4829 device_xname(sc->bge_dev))); 4830 goto fail_unload; 4831 } 4832 4833 mtag = sc->ethercom.ec_nvlans ? 4834 m_tag_find(m_head, PACKET_TAG_VLAN, NULL) : NULL; 4835 4836 4837 /* Iterate over dmap-map fragments. */ 4838 for (i = 0; i < dmamap->dm_nsegs; i++) { 4839 f = &sc->bge_rdata->bge_tx_ring[frag]; 4840 if (sc->bge_cdata.bge_tx_chain[frag] != NULL) 4841 break; 4842 4843 BGE_HOSTADDR(f->bge_addr, dmamap->dm_segs[i].ds_addr); 4844 f->bge_len = dmamap->dm_segs[i].ds_len; 4845 4846 /* 4847 * For 5751 and follow-ons, for TSO we must turn 4848 * off checksum-assist flag in the tx-descr, and 4849 * supply the ASIC-revision-specific encoding 4850 * of TSO flags and segsize. 4851 */ 4852 if (use_tso) { 4853 if (BGE_IS_575X_PLUS(sc) || i == 0) { 4854 f->bge_rsvd = maxsegsize; 4855 f->bge_flags = csum_flags | txbd_tso_flags; 4856 } else { 4857 f->bge_rsvd = 0; 4858 f->bge_flags = 4859 (csum_flags | txbd_tso_flags) & 0x0fff; 4860 } 4861 } else { 4862 f->bge_rsvd = 0; 4863 f->bge_flags = csum_flags; 4864 } 4865 4866 if (mtag != NULL) { 4867 f->bge_flags |= BGE_TXBDFLAG_VLAN_TAG; 4868 f->bge_vlan_tag = VLAN_TAG_VALUE(mtag); 4869 } else { 4870 f->bge_vlan_tag = 0; 4871 } 4872 cur = frag; 4873 BGE_INC(frag, BGE_TX_RING_CNT); 4874 } 4875 4876 if (i < dmamap->dm_nsegs) { 4877 BGE_TSO_PRINTF(("%s: reached %d < dm_nsegs %d\n", 4878 device_xname(sc->bge_dev), i, dmamap->dm_nsegs)); 4879 goto fail_unload; 4880 } 4881 4882 bus_dmamap_sync(sc->bge_dmatag, dmamap, 0, dmamap->dm_mapsize, 4883 BUS_DMASYNC_PREWRITE); 4884 4885 if (frag == sc->bge_tx_saved_considx) { 4886 BGE_TSO_PRINTF(("%s: frag %d = wrapped id %d?\n", 4887 device_xname(sc->bge_dev), frag, sc->bge_tx_saved_considx)); 4888 4889 goto fail_unload; 4890 } 4891 4892 sc->bge_rdata->bge_tx_ring[cur].bge_flags |= BGE_TXBDFLAG_END; 4893 sc->bge_cdata.bge_tx_chain[cur] = m_head; 4894 SLIST_REMOVE_HEAD(&sc->txdma_list, link); 4895 sc->txdma[cur] = dma; 4896 sc->bge_txcnt += dmamap->dm_nsegs; 4897 4898 *txidx = frag; 4899 4900 return 0; 4901 4902 fail_unload: 4903 bus_dmamap_unload(sc->bge_dmatag, dmamap); 4904 4905 return ENOBUFS; 4906 } 4907 4908 /* 4909 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 4910 * to the mbuf data regions directly in the transmit descriptors. 4911 */ 4912 static void 4913 bge_start(struct ifnet *ifp) 4914 { 4915 struct bge_softc *sc; 4916 struct mbuf *m_head = NULL; 4917 uint32_t prodidx; 4918 int pkts = 0; 4919 4920 sc = ifp->if_softc; 4921 4922 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 4923 return; 4924 4925 prodidx = sc->bge_tx_prodidx; 4926 4927 while (sc->bge_cdata.bge_tx_chain[prodidx] == NULL) { 4928 IFQ_POLL(&ifp->if_snd, m_head); 4929 if (m_head == NULL) 4930 break; 4931 4932 #if 0 4933 /* 4934 * XXX 4935 * safety overkill. If this is a fragmented packet chain 4936 * with delayed TCP/UDP checksums, then only encapsulate 4937 * it if we have enough descriptors to handle the entire 4938 * chain at once. 4939 * (paranoia -- may not actually be needed) 4940 */ 4941 if (m_head->m_flags & M_FIRSTFRAG && 4942 m_head->m_pkthdr.csum_flags & (CSUM_DELAY_DATA)) { 4943 if ((BGE_TX_RING_CNT - sc->bge_txcnt) < 4944 M_CSUM_DATA_IPv4_OFFSET(m_head->m_pkthdr.csum_data) + 16) { 4945 ifp->if_flags |= IFF_OACTIVE; 4946 break; 4947 } 4948 } 4949 #endif 4950 4951 /* 4952 * Pack the data into the transmit ring. If we 4953 * don't have room, set the OACTIVE flag and wait 4954 * for the NIC to drain the ring. 4955 */ 4956 if (bge_encap(sc, m_head, &prodidx)) { 4957 ifp->if_flags |= IFF_OACTIVE; 4958 break; 4959 } 4960 4961 /* now we are committed to transmit the packet */ 4962 IFQ_DEQUEUE(&ifp->if_snd, m_head); 4963 pkts++; 4964 4965 /* 4966 * If there's a BPF listener, bounce a copy of this frame 4967 * to him. 4968 */ 4969 bpf_mtap(ifp, m_head); 4970 } 4971 if (pkts == 0) 4972 return; 4973 4974 /* Transmit */ 4975 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); 4976 /* 5700 b2 errata */ 4977 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX) 4978 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); 4979 4980 sc->bge_tx_prodidx = prodidx; 4981 4982 /* 4983 * Set a timeout in case the chip goes out to lunch. 4984 */ 4985 ifp->if_timer = 5; 4986 } 4987 4988 static int 4989 bge_init(struct ifnet *ifp) 4990 { 4991 struct bge_softc *sc = ifp->if_softc; 4992 const uint16_t *m; 4993 uint32_t mode; 4994 int s, error = 0; 4995 4996 s = splnet(); 4997 4998 ifp = &sc->ethercom.ec_if; 4999 5000 /* Cancel pending I/O and flush buffers. */ 5001 bge_stop(ifp, 0); 5002 5003 bge_stop_fw(sc); 5004 bge_sig_pre_reset(sc, BGE_RESET_START); 5005 bge_reset(sc); 5006 bge_sig_legacy(sc, BGE_RESET_START); 5007 bge_sig_post_reset(sc, BGE_RESET_START); 5008 5009 bge_chipinit(sc); 5010 5011 /* 5012 * Init the various state machines, ring 5013 * control blocks and firmware. 5014 */ 5015 error = bge_blockinit(sc); 5016 if (error != 0) { 5017 aprint_error_dev(sc->bge_dev, "initialization error %d\n", 5018 error); 5019 splx(s); 5020 return error; 5021 } 5022 5023 ifp = &sc->ethercom.ec_if; 5024 5025 /* Specify MTU. */ 5026 CSR_WRITE_4(sc, BGE_RX_MTU, ifp->if_mtu + 5027 ETHER_HDR_LEN + ETHER_CRC_LEN + ETHER_VLAN_ENCAP_LEN); 5028 5029 /* Load our MAC address. */ 5030 m = (const uint16_t *)&(CLLADDR(ifp->if_sadl)[0]); 5031 CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0])); 5032 CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, (htons(m[1]) << 16) | htons(m[2])); 5033 5034 /* Enable or disable promiscuous mode as needed. */ 5035 if (ifp->if_flags & IFF_PROMISC) 5036 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 5037 else 5038 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 5039 5040 /* Program multicast filter. */ 5041 bge_setmulti(sc); 5042 5043 /* Init RX ring. */ 5044 bge_init_rx_ring_std(sc); 5045 5046 /* 5047 * Workaround for a bug in 5705 ASIC rev A0. Poll the NIC's 5048 * memory to insure that the chip has in fact read the first 5049 * entry of the ring. 5050 */ 5051 if (sc->bge_chipid == BGE_CHIPID_BCM5705_A0) { 5052 uint32_t v, i; 5053 for (i = 0; i < 10; i++) { 5054 DELAY(20); 5055 v = bge_readmem_ind(sc, BGE_STD_RX_RINGS + 8); 5056 if (v == (MCLBYTES - ETHER_ALIGN)) 5057 break; 5058 } 5059 if (i == 10) 5060 aprint_error_dev(sc->bge_dev, 5061 "5705 A0 chip failed to load RX ring\n"); 5062 } 5063 5064 /* Init jumbo RX ring. */ 5065 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 5066 bge_init_rx_ring_jumbo(sc); 5067 5068 /* Init our RX return ring index */ 5069 sc->bge_rx_saved_considx = 0; 5070 5071 /* Init TX ring. */ 5072 bge_init_tx_ring(sc); 5073 5074 /* Enable TX MAC state machine lockup fix. */ 5075 mode = CSR_READ_4(sc, BGE_TX_MODE); 5076 if (BGE_IS_5755_PLUS(sc) || 5077 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 5078 mode |= BGE_TXMODE_MBUF_LOCKUP_FIX; 5079 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) { 5080 mode &= ~(BGE_TXMODE_JMB_FRM_LEN | BGE_TXMODE_CNT_DN_MODE); 5081 mode |= CSR_READ_4(sc, BGE_TX_MODE) & 5082 (BGE_TXMODE_JMB_FRM_LEN | BGE_TXMODE_CNT_DN_MODE); 5083 } 5084 5085 /* Turn on transmitter */ 5086 CSR_WRITE_4_FLUSH(sc, BGE_TX_MODE, mode | BGE_TXMODE_ENABLE); 5087 DELAY(100); 5088 5089 /* Turn on receiver */ 5090 mode = CSR_READ_4(sc, BGE_RX_MODE); 5091 if (BGE_IS_5755_PLUS(sc)) 5092 mode |= BGE_RXMODE_IPV6_ENABLE; 5093 CSR_WRITE_4_FLUSH(sc, BGE_RX_MODE, mode | BGE_RXMODE_ENABLE); 5094 DELAY(10); 5095 5096 CSR_WRITE_4(sc, BGE_MAX_RX_FRAME_LOWAT, 2); 5097 5098 /* Tell firmware we're alive. */ 5099 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 5100 5101 /* Enable host interrupts. */ 5102 PCI_SETBIT(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MISC_CTL, 5103 BGE_PCIMISCCTL_CLEAR_INTA); 5104 PCI_CLRBIT(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MISC_CTL, 5105 BGE_PCIMISCCTL_MASK_PCI_INTR); 5106 bge_writembx_flush(sc, BGE_MBX_IRQ0_LO, 0); 5107 5108 if ((error = bge_ifmedia_upd(ifp)) != 0) 5109 goto out; 5110 5111 ifp->if_flags |= IFF_RUNNING; 5112 ifp->if_flags &= ~IFF_OACTIVE; 5113 5114 callout_reset(&sc->bge_timeout, hz, bge_tick, sc); 5115 5116 out: 5117 sc->bge_if_flags = ifp->if_flags; 5118 splx(s); 5119 5120 return error; 5121 } 5122 5123 /* 5124 * Set media options. 5125 */ 5126 static int 5127 bge_ifmedia_upd(struct ifnet *ifp) 5128 { 5129 struct bge_softc *sc = ifp->if_softc; 5130 struct mii_data *mii = &sc->bge_mii; 5131 struct ifmedia *ifm = &sc->bge_ifmedia; 5132 int rc; 5133 5134 /* If this is a 1000baseX NIC, enable the TBI port. */ 5135 if (sc->bge_flags & BGE_PHY_FIBER_TBI) { 5136 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 5137 return EINVAL; 5138 switch (IFM_SUBTYPE(ifm->ifm_media)) { 5139 case IFM_AUTO: 5140 /* 5141 * The BCM5704 ASIC appears to have a special 5142 * mechanism for programming the autoneg 5143 * advertisement registers in TBI mode. 5144 */ 5145 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) { 5146 uint32_t sgdig; 5147 sgdig = CSR_READ_4(sc, BGE_SGDIG_STS); 5148 if (sgdig & BGE_SGDIGSTS_DONE) { 5149 CSR_WRITE_4(sc, BGE_TX_TBI_AUTONEG, 0); 5150 sgdig = CSR_READ_4(sc, BGE_SGDIG_CFG); 5151 sgdig |= BGE_SGDIGCFG_AUTO | 5152 BGE_SGDIGCFG_PAUSE_CAP | 5153 BGE_SGDIGCFG_ASYM_PAUSE; 5154 CSR_WRITE_4_FLUSH(sc, BGE_SGDIG_CFG, 5155 sgdig | BGE_SGDIGCFG_SEND); 5156 DELAY(5); 5157 CSR_WRITE_4_FLUSH(sc, BGE_SGDIG_CFG, 5158 sgdig); 5159 } 5160 } 5161 break; 5162 case IFM_1000_SX: 5163 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 5164 BGE_CLRBIT(sc, BGE_MAC_MODE, 5165 BGE_MACMODE_HALF_DUPLEX); 5166 } else { 5167 BGE_SETBIT(sc, BGE_MAC_MODE, 5168 BGE_MACMODE_HALF_DUPLEX); 5169 } 5170 DELAY(40); 5171 break; 5172 default: 5173 return EINVAL; 5174 } 5175 /* XXX 802.3x flow control for 1000BASE-SX */ 5176 return 0; 5177 } 5178 5179 BGE_STS_SETBIT(sc, BGE_STS_LINK_EVT); 5180 if ((rc = mii_mediachg(mii)) == ENXIO) 5181 return 0; 5182 5183 /* 5184 * Force an interrupt so that we will call bge_link_upd 5185 * if needed and clear any pending link state attention. 5186 * Without this we are not getting any further interrupts 5187 * for link state changes and thus will not UP the link and 5188 * not be able to send in bge_start. The only way to get 5189 * things working was to receive a packet and get a RX intr. 5190 */ 5191 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 5192 sc->bge_flags & BGE_IS_5788) 5193 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET); 5194 else 5195 BGE_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW); 5196 5197 return rc; 5198 } 5199 5200 /* 5201 * Report current media status. 5202 */ 5203 static void 5204 bge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 5205 { 5206 struct bge_softc *sc = ifp->if_softc; 5207 struct mii_data *mii = &sc->bge_mii; 5208 5209 if (sc->bge_flags & BGE_PHY_FIBER_TBI) { 5210 ifmr->ifm_status = IFM_AVALID; 5211 ifmr->ifm_active = IFM_ETHER; 5212 if (CSR_READ_4(sc, BGE_MAC_STS) & 5213 BGE_MACSTAT_TBI_PCS_SYNCHED) 5214 ifmr->ifm_status |= IFM_ACTIVE; 5215 ifmr->ifm_active |= IFM_1000_SX; 5216 if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX) 5217 ifmr->ifm_active |= IFM_HDX; 5218 else 5219 ifmr->ifm_active |= IFM_FDX; 5220 return; 5221 } 5222 5223 mii_pollstat(mii); 5224 ifmr->ifm_status = mii->mii_media_status; 5225 ifmr->ifm_active = (mii->mii_media_active & ~IFM_ETH_FMASK) | 5226 sc->bge_flowflags; 5227 } 5228 5229 static int 5230 bge_ifflags_cb(struct ethercom *ec) 5231 { 5232 struct ifnet *ifp = &ec->ec_if; 5233 struct bge_softc *sc = ifp->if_softc; 5234 int change = ifp->if_flags ^ sc->bge_if_flags; 5235 5236 if ((change & ~(IFF_CANTCHANGE|IFF_DEBUG)) != 0) 5237 return ENETRESET; 5238 else if ((change & (IFF_PROMISC | IFF_ALLMULTI)) == 0) 5239 return 0; 5240 5241 if ((ifp->if_flags & IFF_PROMISC) == 0) 5242 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 5243 else 5244 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 5245 5246 bge_setmulti(sc); 5247 5248 sc->bge_if_flags = ifp->if_flags; 5249 return 0; 5250 } 5251 5252 static int 5253 bge_ioctl(struct ifnet *ifp, u_long command, void *data) 5254 { 5255 struct bge_softc *sc = ifp->if_softc; 5256 struct ifreq *ifr = (struct ifreq *) data; 5257 int s, error = 0; 5258 struct mii_data *mii; 5259 5260 s = splnet(); 5261 5262 switch (command) { 5263 case SIOCSIFMEDIA: 5264 /* XXX Flow control is not supported for 1000BASE-SX */ 5265 if (sc->bge_flags & BGE_PHY_FIBER_TBI) { 5266 ifr->ifr_media &= ~IFM_ETH_FMASK; 5267 sc->bge_flowflags = 0; 5268 } 5269 5270 /* Flow control requires full-duplex mode. */ 5271 if (IFM_SUBTYPE(ifr->ifr_media) == IFM_AUTO || 5272 (ifr->ifr_media & IFM_FDX) == 0) { 5273 ifr->ifr_media &= ~IFM_ETH_FMASK; 5274 } 5275 if (IFM_SUBTYPE(ifr->ifr_media) != IFM_AUTO) { 5276 if ((ifr->ifr_media & IFM_ETH_FMASK) == IFM_FLOW) { 5277 /* We can do both TXPAUSE and RXPAUSE. */ 5278 ifr->ifr_media |= 5279 IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE; 5280 } 5281 sc->bge_flowflags = ifr->ifr_media & IFM_ETH_FMASK; 5282 } 5283 /* FALLTHROUGH */ 5284 case SIOCGIFMEDIA: 5285 if (sc->bge_flags & BGE_PHY_FIBER_TBI) { 5286 error = ifmedia_ioctl(ifp, ifr, &sc->bge_ifmedia, 5287 command); 5288 } else { 5289 mii = &sc->bge_mii; 5290 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, 5291 command); 5292 } 5293 break; 5294 default: 5295 if ((error = ether_ioctl(ifp, command, data)) != ENETRESET) 5296 break; 5297 5298 error = 0; 5299 5300 if (command != SIOCADDMULTI && command != SIOCDELMULTI) 5301 ; 5302 else if (ifp->if_flags & IFF_RUNNING) 5303 bge_setmulti(sc); 5304 break; 5305 } 5306 5307 splx(s); 5308 5309 return error; 5310 } 5311 5312 static void 5313 bge_watchdog(struct ifnet *ifp) 5314 { 5315 struct bge_softc *sc; 5316 5317 sc = ifp->if_softc; 5318 5319 aprint_error_dev(sc->bge_dev, "watchdog timeout -- resetting\n"); 5320 5321 ifp->if_flags &= ~IFF_RUNNING; 5322 bge_init(ifp); 5323 5324 ifp->if_oerrors++; 5325 } 5326 5327 static void 5328 bge_stop_block(struct bge_softc *sc, bus_addr_t reg, uint32_t bit) 5329 { 5330 int i; 5331 5332 BGE_CLRBIT_FLUSH(sc, reg, bit); 5333 5334 for (i = 0; i < 1000; i++) { 5335 delay(100); 5336 if ((CSR_READ_4(sc, reg) & bit) == 0) 5337 return; 5338 } 5339 5340 /* 5341 * Doesn't print only when the register is BGE_SRS_MODE. It occurs 5342 * on some environment (and once after boot?) 5343 */ 5344 if (reg != BGE_SRS_MODE) 5345 aprint_error_dev(sc->bge_dev, 5346 "block failed to stop: reg 0x%lx, bit 0x%08x\n", 5347 (u_long)reg, bit); 5348 } 5349 5350 /* 5351 * Stop the adapter and free any mbufs allocated to the 5352 * RX and TX lists. 5353 */ 5354 static void 5355 bge_stop(struct ifnet *ifp, int disable) 5356 { 5357 struct bge_softc *sc = ifp->if_softc; 5358 5359 callout_stop(&sc->bge_timeout); 5360 5361 /* Disable host interrupts. */ 5362 PCI_SETBIT(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MISC_CTL, 5363 BGE_PCIMISCCTL_MASK_PCI_INTR); 5364 bge_writembx_flush(sc, BGE_MBX_IRQ0_LO, 1); 5365 5366 /* 5367 * Tell firmware we're shutting down. 5368 */ 5369 bge_stop_fw(sc); 5370 bge_sig_pre_reset(sc, BGE_RESET_SHUTDOWN); 5371 5372 /* 5373 * Disable all of the receiver blocks. 5374 */ 5375 bge_stop_block(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE); 5376 bge_stop_block(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 5377 bge_stop_block(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 5378 if (BGE_IS_5700_FAMILY(sc)) 5379 bge_stop_block(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 5380 bge_stop_block(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE); 5381 bge_stop_block(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 5382 bge_stop_block(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE); 5383 5384 /* 5385 * Disable all of the transmit blocks. 5386 */ 5387 bge_stop_block(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 5388 bge_stop_block(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 5389 bge_stop_block(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 5390 bge_stop_block(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE); 5391 bge_stop_block(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE); 5392 if (BGE_IS_5700_FAMILY(sc)) 5393 bge_stop_block(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 5394 bge_stop_block(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 5395 5396 BGE_CLRBIT_FLUSH(sc, BGE_MAC_MODE, BGE_MACMODE_TXDMA_ENB); 5397 delay(40); 5398 5399 bge_stop_block(sc, BGE_TX_MODE, BGE_TXMODE_ENABLE); 5400 5401 /* 5402 * Shut down all of the memory managers and related 5403 * state machines. 5404 */ 5405 bge_stop_block(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE); 5406 bge_stop_block(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE); 5407 if (BGE_IS_5700_FAMILY(sc)) 5408 bge_stop_block(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 5409 5410 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 5411 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 5412 5413 if (BGE_IS_5700_FAMILY(sc)) { 5414 bge_stop_block(sc, BGE_BMAN_MODE, BGE_BMANMODE_ENABLE); 5415 bge_stop_block(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 5416 } 5417 5418 bge_reset(sc); 5419 bge_sig_legacy(sc, BGE_RESET_SHUTDOWN); 5420 bge_sig_post_reset(sc, BGE_RESET_SHUTDOWN); 5421 5422 /* 5423 * Keep the ASF firmware running if up. 5424 */ 5425 if (sc->bge_asf_mode & ASF_STACKUP) 5426 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 5427 else 5428 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 5429 5430 /* Free the RX lists. */ 5431 bge_free_rx_ring_std(sc); 5432 5433 /* Free jumbo RX list. */ 5434 if (BGE_IS_JUMBO_CAPABLE(sc)) 5435 bge_free_rx_ring_jumbo(sc); 5436 5437 /* Free TX buffers. */ 5438 bge_free_tx_ring(sc); 5439 5440 /* 5441 * Isolate/power down the PHY. 5442 */ 5443 if (!(sc->bge_flags & BGE_PHY_FIBER_TBI)) 5444 mii_down(&sc->bge_mii); 5445 5446 sc->bge_tx_saved_considx = BGE_TXCONS_UNSET; 5447 5448 /* Clear MAC's link state (PHY may still have link UP). */ 5449 BGE_STS_CLRBIT(sc, BGE_STS_LINK); 5450 5451 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 5452 } 5453 5454 static void 5455 bge_link_upd(struct bge_softc *sc) 5456 { 5457 struct ifnet *ifp = &sc->ethercom.ec_if; 5458 struct mii_data *mii = &sc->bge_mii; 5459 uint32_t status; 5460 int link; 5461 5462 /* Clear 'pending link event' flag */ 5463 BGE_STS_CLRBIT(sc, BGE_STS_LINK_EVT); 5464 5465 /* 5466 * Process link state changes. 5467 * Grrr. The link status word in the status block does 5468 * not work correctly on the BCM5700 rev AX and BX chips, 5469 * according to all available information. Hence, we have 5470 * to enable MII interrupts in order to properly obtain 5471 * async link changes. Unfortunately, this also means that 5472 * we have to read the MAC status register to detect link 5473 * changes, thereby adding an additional register access to 5474 * the interrupt handler. 5475 */ 5476 5477 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700) { 5478 status = CSR_READ_4(sc, BGE_MAC_STS); 5479 if (status & BGE_MACSTAT_MI_INTERRUPT) { 5480 mii_pollstat(mii); 5481 5482 if (!BGE_STS_BIT(sc, BGE_STS_LINK) && 5483 mii->mii_media_status & IFM_ACTIVE && 5484 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) 5485 BGE_STS_SETBIT(sc, BGE_STS_LINK); 5486 else if (BGE_STS_BIT(sc, BGE_STS_LINK) && 5487 (!(mii->mii_media_status & IFM_ACTIVE) || 5488 IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) 5489 BGE_STS_CLRBIT(sc, BGE_STS_LINK); 5490 5491 /* Clear the interrupt */ 5492 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, 5493 BGE_EVTENB_MI_INTERRUPT); 5494 bge_miibus_readreg(sc->bge_dev, sc->bge_phy_addr, 5495 BRGPHY_MII_ISR); 5496 bge_miibus_writereg(sc->bge_dev, sc->bge_phy_addr, 5497 BRGPHY_MII_IMR, BRGPHY_INTRS); 5498 } 5499 return; 5500 } 5501 5502 if (sc->bge_flags & BGE_PHY_FIBER_TBI) { 5503 status = CSR_READ_4(sc, BGE_MAC_STS); 5504 if (status & BGE_MACSTAT_TBI_PCS_SYNCHED) { 5505 if (!BGE_STS_BIT(sc, BGE_STS_LINK)) { 5506 BGE_STS_SETBIT(sc, BGE_STS_LINK); 5507 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) 5508 BGE_CLRBIT(sc, BGE_MAC_MODE, 5509 BGE_MACMODE_TBI_SEND_CFGS); 5510 CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF); 5511 if_link_state_change(ifp, LINK_STATE_UP); 5512 } 5513 } else if (BGE_STS_BIT(sc, BGE_STS_LINK)) { 5514 BGE_STS_CLRBIT(sc, BGE_STS_LINK); 5515 if_link_state_change(ifp, LINK_STATE_DOWN); 5516 } 5517 /* 5518 * Discard link events for MII/GMII cards if MI auto-polling disabled. 5519 * This should not happen since mii callouts are locked now, but 5520 * we keep this check for debug. 5521 */ 5522 } else if (BGE_STS_BIT(sc, BGE_STS_AUTOPOLL)) { 5523 /* 5524 * Some broken BCM chips have BGE_STATFLAG_LINKSTATE_CHANGED 5525 * bit in status word always set. Workaround this bug by 5526 * reading PHY link status directly. 5527 */ 5528 link = (CSR_READ_4(sc, BGE_MI_STS) & BGE_MISTS_LINK)? 5529 BGE_STS_LINK : 0; 5530 5531 if (BGE_STS_BIT(sc, BGE_STS_LINK) != link) { 5532 mii_pollstat(mii); 5533 5534 if (!BGE_STS_BIT(sc, BGE_STS_LINK) && 5535 mii->mii_media_status & IFM_ACTIVE && 5536 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) 5537 BGE_STS_SETBIT(sc, BGE_STS_LINK); 5538 else if (BGE_STS_BIT(sc, BGE_STS_LINK) && 5539 (!(mii->mii_media_status & IFM_ACTIVE) || 5540 IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) 5541 BGE_STS_CLRBIT(sc, BGE_STS_LINK); 5542 } 5543 } 5544 5545 /* Clear the attention */ 5546 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED| 5547 BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE| 5548 BGE_MACSTAT_LINK_CHANGED); 5549 } 5550 5551 static int 5552 bge_sysctl_verify(SYSCTLFN_ARGS) 5553 { 5554 int error, t; 5555 struct sysctlnode node; 5556 5557 node = *rnode; 5558 t = *(int*)rnode->sysctl_data; 5559 node.sysctl_data = &t; 5560 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 5561 if (error || newp == NULL) 5562 return error; 5563 5564 #if 0 5565 DPRINTF2(("%s: t = %d, nodenum = %d, rnodenum = %d\n", __func__, t, 5566 node.sysctl_num, rnode->sysctl_num)); 5567 #endif 5568 5569 if (node.sysctl_num == bge_rxthresh_nodenum) { 5570 if (t < 0 || t >= NBGE_RX_THRESH) 5571 return EINVAL; 5572 bge_update_all_threshes(t); 5573 } else 5574 return EINVAL; 5575 5576 *(int*)rnode->sysctl_data = t; 5577 5578 return 0; 5579 } 5580 5581 /* 5582 * Set up sysctl(3) MIB, hw.bge.*. 5583 */ 5584 static void 5585 bge_sysctl_init(struct bge_softc *sc) 5586 { 5587 int rc, bge_root_num; 5588 const struct sysctlnode *node; 5589 5590 if ((rc = sysctl_createv(&sc->bge_log, 0, NULL, NULL, 5591 CTLFLAG_PERMANENT, CTLTYPE_NODE, "hw", NULL, 5592 NULL, 0, NULL, 0, CTL_HW, CTL_EOL)) != 0) { 5593 goto out; 5594 } 5595 5596 if ((rc = sysctl_createv(&sc->bge_log, 0, NULL, &node, 5597 0, CTLTYPE_NODE, "bge", 5598 SYSCTL_DESCR("BGE interface controls"), 5599 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL)) != 0) { 5600 goto out; 5601 } 5602 5603 bge_root_num = node->sysctl_num; 5604 5605 /* BGE Rx interrupt mitigation level */ 5606 if ((rc = sysctl_createv(&sc->bge_log, 0, NULL, &node, 5607 CTLFLAG_READWRITE, 5608 CTLTYPE_INT, "rx_lvl", 5609 SYSCTL_DESCR("BGE receive interrupt mitigation level"), 5610 bge_sysctl_verify, 0, 5611 &bge_rx_thresh_lvl, 5612 0, CTL_HW, bge_root_num, CTL_CREATE, 5613 CTL_EOL)) != 0) { 5614 goto out; 5615 } 5616 5617 bge_rxthresh_nodenum = node->sysctl_num; 5618 5619 return; 5620 5621 out: 5622 aprint_error("%s: sysctl_createv failed (rc = %d)\n", __func__, rc); 5623 } 5624 5625 #ifdef BGE_DEBUG 5626 void 5627 bge_debug_info(struct bge_softc *sc) 5628 { 5629 5630 printf("Hardware Flags:\n"); 5631 if (BGE_IS_57765_PLUS(sc)) 5632 printf(" - 57765 Plus\n"); 5633 if (BGE_IS_5717_PLUS(sc)) 5634 printf(" - 5717 Plus\n"); 5635 if (BGE_IS_5755_PLUS(sc)) 5636 printf(" - 5755 Plus\n"); 5637 if (BGE_IS_575X_PLUS(sc)) 5638 printf(" - 575X Plus\n"); 5639 if (BGE_IS_5705_PLUS(sc)) 5640 printf(" - 5705 Plus\n"); 5641 if (BGE_IS_5714_FAMILY(sc)) 5642 printf(" - 5714 Family\n"); 5643 if (BGE_IS_5700_FAMILY(sc)) 5644 printf(" - 5700 Family\n"); 5645 if (sc->bge_flags & BGE_IS_5788) 5646 printf(" - 5788\n"); 5647 if (sc->bge_flags & BGE_JUMBO_CAPABLE) 5648 printf(" - Supports Jumbo Frames\n"); 5649 if (sc->bge_flags & BGE_NO_EEPROM) 5650 printf(" - No EEPROM\n"); 5651 if (sc->bge_flags & BGE_PCIX) 5652 printf(" - PCI-X Bus\n"); 5653 if (sc->bge_flags & BGE_PCIE) 5654 printf(" - PCI Express Bus\n"); 5655 if (sc->bge_flags & BGE_NO_3LED) 5656 printf(" - No 3 LEDs\n"); 5657 if (sc->bge_flags & BGE_RX_ALIGNBUG) 5658 printf(" - RX Alignment Bug\n"); 5659 if (sc->bge_flags & BGE_APE) 5660 printf(" - APE\n"); 5661 if (sc->bge_flags & BGE_CPMU_PRESENT) 5662 printf(" - CPMU\n"); 5663 if (sc->bge_flags & BGE_TSO) 5664 printf(" - TSO\n"); 5665 } 5666 #endif /* BGE_DEBUG */ 5667 5668 static int 5669 bge_get_eaddr_fw(struct bge_softc *sc, uint8_t ether_addr[]) 5670 { 5671 prop_dictionary_t dict; 5672 prop_data_t ea; 5673 5674 if ((sc->bge_flags & BGE_NO_EEPROM) == 0) 5675 return 1; 5676 5677 dict = device_properties(sc->bge_dev); 5678 ea = prop_dictionary_get(dict, "mac-address"); 5679 if (ea != NULL) { 5680 KASSERT(prop_object_type(ea) == PROP_TYPE_DATA); 5681 KASSERT(prop_data_size(ea) == ETHER_ADDR_LEN); 5682 memcpy(ether_addr, prop_data_data_nocopy(ea), ETHER_ADDR_LEN); 5683 return 0; 5684 } 5685 5686 return 1; 5687 } 5688 5689 static int 5690 bge_get_eaddr_mem(struct bge_softc *sc, uint8_t ether_addr[]) 5691 { 5692 uint32_t mac_addr; 5693 5694 mac_addr = bge_readmem_ind(sc, BGE_SRAM_MAC_ADDR_HIGH_MB); 5695 if ((mac_addr >> 16) == 0x484b) { 5696 ether_addr[0] = (uint8_t)(mac_addr >> 8); 5697 ether_addr[1] = (uint8_t)mac_addr; 5698 mac_addr = bge_readmem_ind(sc, BGE_SRAM_MAC_ADDR_LOW_MB); 5699 ether_addr[2] = (uint8_t)(mac_addr >> 24); 5700 ether_addr[3] = (uint8_t)(mac_addr >> 16); 5701 ether_addr[4] = (uint8_t)(mac_addr >> 8); 5702 ether_addr[5] = (uint8_t)mac_addr; 5703 return 0; 5704 } 5705 return 1; 5706 } 5707 5708 static int 5709 bge_get_eaddr_nvram(struct bge_softc *sc, uint8_t ether_addr[]) 5710 { 5711 int mac_offset = BGE_EE_MAC_OFFSET; 5712 5713 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 5714 mac_offset = BGE_EE_MAC_OFFSET_5906; 5715 5716 return (bge_read_nvram(sc, ether_addr, mac_offset + 2, 5717 ETHER_ADDR_LEN)); 5718 } 5719 5720 static int 5721 bge_get_eaddr_eeprom(struct bge_softc *sc, uint8_t ether_addr[]) 5722 { 5723 5724 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 5725 return 1; 5726 5727 return (bge_read_eeprom(sc, ether_addr, BGE_EE_MAC_OFFSET + 2, 5728 ETHER_ADDR_LEN)); 5729 } 5730 5731 static int 5732 bge_get_eaddr(struct bge_softc *sc, uint8_t eaddr[]) 5733 { 5734 static const bge_eaddr_fcn_t bge_eaddr_funcs[] = { 5735 /* NOTE: Order is critical */ 5736 bge_get_eaddr_fw, 5737 bge_get_eaddr_mem, 5738 bge_get_eaddr_nvram, 5739 bge_get_eaddr_eeprom, 5740 NULL 5741 }; 5742 const bge_eaddr_fcn_t *func; 5743 5744 for (func = bge_eaddr_funcs; *func != NULL; ++func) { 5745 if ((*func)(sc, eaddr) == 0) 5746 break; 5747 } 5748 return (*func == NULL ? ENXIO : 0); 5749 } 5750
Indexes created Tue Sep 23 14:10:03 GMT 2025