if_bge.c revision 1.219
1 /* $NetBSD: if_bge.c,v 1.219 2013/03/19 03:40:16 msaitoh Exp $ */ 2 3 /* 4 * Copyright (c) 2001 Wind River Systems 5 * Copyright (c) 1997, 1998, 1999, 2001 6 * Bill Paul <wpaul (at) windriver.com>. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Bill Paul. 19 * 4. Neither the name of the author nor the names of any co-contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 33 * THE POSSIBILITY OF SUCH DAMAGE. 34 * 35 * $FreeBSD: if_bge.c,v 1.13 2002/04/04 06:01:31 wpaul Exp $ 36 */ 37 38 /* 39 * Broadcom BCM570x family gigabit ethernet driver for NetBSD. 40 * 41 * NetBSD version by: 42 * 43 * Frank van der Linden <fvdl (at) wasabisystems.com> 44 * Jason Thorpe <thorpej (at) wasabisystems.com> 45 * Jonathan Stone <jonathan (at) dsg.stanford.edu> 46 * 47 * Originally written for FreeBSD by Bill Paul <wpaul (at) windriver.com> 48 * Senior Engineer, Wind River Systems 49 */ 50 51 /* 52 * The Broadcom BCM5700 is based on technology originally developed by 53 * Alteon Networks as part of the Tigon I and Tigon II gigabit ethernet 54 * MAC chips. The BCM5700, sometimes referred to as the Tigon III, has 55 * two on-board MIPS R4000 CPUs and can have as much as 16MB of external 56 * SSRAM. The BCM5700 supports TCP, UDP and IP checksum offload, jumbo 57 * frames, highly configurable RX filtering, and 16 RX and TX queues 58 * (which, along with RX filter rules, can be used for QOS applications). 59 * Other features, such as TCP segmentation, may be available as part 60 * of value-added firmware updates. Unlike the Tigon I and Tigon II, 61 * firmware images can be stored in hardware and need not be compiled 62 * into the driver. 63 * 64 * The BCM5700 supports the PCI v2.2 and PCI-X v1.0 standards, and will 65 * function in a 32-bit/64-bit 33/66MHz bus, or a 64-bit/133MHz bus. 66 * 67 * The BCM5701 is a single-chip solution incorporating both the BCM5700 68 * MAC and a BCM5401 10/100/1000 PHY. Unlike the BCM5700, the BCM5701 69 * does not support external SSRAM. 70 * 71 * Broadcom also produces a variation of the BCM5700 under the "Altima" 72 * brand name, which is functionally similar but lacks PCI-X support. 73 * 74 * Without external SSRAM, you can only have at most 4 TX rings, 75 * and the use of the mini RX ring is disabled. This seems to imply 76 * that these features are simply not available on the BCM5701. As a 77 * result, this driver does not implement any support for the mini RX 78 * ring. 79 */ 80 81 #include <sys/cdefs.h> 82 __KERNEL_RCSID(0, "$NetBSD: if_bge.c,v 1.219 2013/03/19 03:40:16 msaitoh Exp $"); 83 84 #include "vlan.h" 85 86 #include <sys/param.h> 87 #include <sys/systm.h> 88 #include <sys/callout.h> 89 #include <sys/sockio.h> 90 #include <sys/mbuf.h> 91 #include <sys/malloc.h> 92 #include <sys/kernel.h> 93 #include <sys/device.h> 94 #include <sys/socket.h> 95 #include <sys/sysctl.h> 96 97 #include <net/if.h> 98 #include <net/if_dl.h> 99 #include <net/if_media.h> 100 #include <net/if_ether.h> 101 102 #include <sys/rnd.h> 103 104 #ifdef INET 105 #include <netinet/in.h> 106 #include <netinet/in_systm.h> 107 #include <netinet/in_var.h> 108 #include <netinet/ip.h> 109 #endif 110 111 /* Headers for TCP Segmentation Offload (TSO) */ 112 #include <netinet/in_systm.h> /* n_time for <netinet/ip.h>... */ 113 #include <netinet/in.h> /* ip_{src,dst}, for <netinet/ip.h> */ 114 #include <netinet/ip.h> /* for struct ip */ 115 #include <netinet/tcp.h> /* for struct tcphdr */ 116 117 118 #include <net/bpf.h> 119 120 #include <dev/pci/pcireg.h> 121 #include <dev/pci/pcivar.h> 122 #include <dev/pci/pcidevs.h> 123 124 #include <dev/mii/mii.h> 125 #include <dev/mii/miivar.h> 126 #include <dev/mii/miidevs.h> 127 #include <dev/mii/brgphyreg.h> 128 129 #include <dev/pci/if_bgereg.h> 130 #include <dev/pci/if_bgevar.h> 131 132 #include <prop/proplib.h> 133 134 #define ETHER_MIN_NOPAD (ETHER_MIN_LEN - ETHER_CRC_LEN) /* i.e., 60 */ 135 136 137 /* 138 * Tunable thresholds for rx-side bge interrupt mitigation. 139 */ 140 141 /* 142 * The pairs of values below were obtained from empirical measurement 143 * on bcm5700 rev B2; they ar designed to give roughly 1 receive 144 * interrupt for every N packets received, where N is, approximately, 145 * the second value (rx_max_bds) in each pair. The values are chosen 146 * such that moving from one pair to the succeeding pair was observed 147 * to roughly halve interrupt rate under sustained input packet load. 148 * The values were empirically chosen to avoid overflowing internal 149 * limits on the bcm5700: increasing rx_ticks much beyond 600 150 * results in internal wrapping and higher interrupt rates. 151 * The limit of 46 frames was chosen to match NFS workloads. 152 * 153 * These values also work well on bcm5701, bcm5704C, and (less 154 * tested) bcm5703. On other chipsets, (including the Altima chip 155 * family), the larger values may overflow internal chip limits, 156 * leading to increasing interrupt rates rather than lower interrupt 157 * rates. 158 * 159 * Applications using heavy interrupt mitigation (interrupting every 160 * 32 or 46 frames) in both directions may need to increase the TCP 161 * windowsize to above 131072 bytes (e.g., to 199608 bytes) to sustain 162 * full link bandwidth, due to ACKs and window updates lingering 163 * in the RX queue during the 30-to-40-frame interrupt-mitigation window. 164 */ 165 static const struct bge_load_rx_thresh { 166 int rx_ticks; 167 int rx_max_bds; } 168 bge_rx_threshes[] = { 169 { 16, 1 }, /* rx_max_bds = 1 disables interrupt mitigation */ 170 { 32, 2 }, 171 { 50, 4 }, 172 { 100, 8 }, 173 { 192, 16 }, 174 { 416, 32 }, 175 { 598, 46 } 176 }; 177 #define NBGE_RX_THRESH (sizeof(bge_rx_threshes) / sizeof(bge_rx_threshes[0])) 178 179 /* XXX patchable; should be sysctl'able */ 180 static int bge_auto_thresh = 1; 181 static int bge_rx_thresh_lvl; 182 183 static int bge_rxthresh_nodenum; 184 185 typedef int (*bge_eaddr_fcn_t)(struct bge_softc *, uint8_t[]); 186 187 static uint32_t bge_chipid(const struct pci_attach_args *pa); 188 static int bge_probe(device_t, cfdata_t, void *); 189 static void bge_attach(device_t, device_t, void *); 190 static void bge_release_resources(struct bge_softc *); 191 192 static int bge_get_eaddr_fw(struct bge_softc *, uint8_t[]); 193 static int bge_get_eaddr_mem(struct bge_softc *, uint8_t[]); 194 static int bge_get_eaddr_nvram(struct bge_softc *, uint8_t[]); 195 static int bge_get_eaddr_eeprom(struct bge_softc *, uint8_t[]); 196 static int bge_get_eaddr(struct bge_softc *, uint8_t[]); 197 198 static void bge_txeof(struct bge_softc *); 199 static void bge_rxcsum(struct bge_softc *, struct bge_rx_bd *, struct mbuf *); 200 static void bge_rxeof(struct bge_softc *); 201 202 static void bge_asf_driver_up (struct bge_softc *); 203 static void bge_tick(void *); 204 static void bge_stats_update(struct bge_softc *); 205 static void bge_stats_update_regs(struct bge_softc *); 206 static int bge_encap(struct bge_softc *, struct mbuf *, uint32_t *); 207 208 static int bge_intr(void *); 209 static void bge_start(struct ifnet *); 210 static int bge_ifflags_cb(struct ethercom *); 211 static int bge_ioctl(struct ifnet *, u_long, void *); 212 static int bge_init(struct ifnet *); 213 static void bge_stop(struct ifnet *, int); 214 static void bge_watchdog(struct ifnet *); 215 static int bge_ifmedia_upd(struct ifnet *); 216 static void bge_ifmedia_sts(struct ifnet *, struct ifmediareq *); 217 218 static uint8_t bge_nvram_getbyte(struct bge_softc *, int, uint8_t *); 219 static int bge_read_nvram(struct bge_softc *, uint8_t *, int, int); 220 221 static uint8_t bge_eeprom_getbyte(struct bge_softc *, int, uint8_t *); 222 static int bge_read_eeprom(struct bge_softc *, void *, int, int); 223 static void bge_setmulti(struct bge_softc *); 224 225 static void bge_handle_events(struct bge_softc *); 226 static int bge_alloc_jumbo_mem(struct bge_softc *); 227 #if 0 /* XXX */ 228 static void bge_free_jumbo_mem(struct bge_softc *); 229 #endif 230 static void *bge_jalloc(struct bge_softc *); 231 static void bge_jfree(struct mbuf *, void *, size_t, void *); 232 static int bge_newbuf_std(struct bge_softc *, int, struct mbuf *, 233 bus_dmamap_t); 234 static int bge_newbuf_jumbo(struct bge_softc *, int, struct mbuf *); 235 static int bge_init_rx_ring_std(struct bge_softc *); 236 static void bge_free_rx_ring_std(struct bge_softc *); 237 static int bge_init_rx_ring_jumbo(struct bge_softc *); 238 static void bge_free_rx_ring_jumbo(struct bge_softc *); 239 static void bge_free_tx_ring(struct bge_softc *); 240 static int bge_init_tx_ring(struct bge_softc *); 241 242 static int bge_chipinit(struct bge_softc *); 243 static int bge_blockinit(struct bge_softc *); 244 static int bge_phy_addr(struct bge_softc *); 245 static uint32_t bge_readmem_ind(struct bge_softc *, int); 246 static void bge_writemem_ind(struct bge_softc *, int, int); 247 static void bge_writembx(struct bge_softc *, int, int); 248 static void bge_writembx_flush(struct bge_softc *, int, int); 249 static void bge_writemem_direct(struct bge_softc *, int, int); 250 static void bge_writereg_ind(struct bge_softc *, int, int); 251 static void bge_set_max_readrq(struct bge_softc *); 252 253 static int bge_miibus_readreg(device_t, int, int); 254 static void bge_miibus_writereg(device_t, int, int, int); 255 static void bge_miibus_statchg(struct ifnet *); 256 257 #define BGE_RESET_SHUTDOWN 0 258 #define BGE_RESET_START 1 259 #define BGE_RESET_SUSPEND 2 260 static void bge_sig_post_reset(struct bge_softc *, int); 261 static void bge_sig_legacy(struct bge_softc *, int); 262 static void bge_sig_pre_reset(struct bge_softc *, int); 263 static void bge_wait_for_event_ack(struct bge_softc *); 264 static void bge_stop_fw(struct bge_softc *); 265 static int bge_reset(struct bge_softc *); 266 static void bge_link_upd(struct bge_softc *); 267 static void bge_sysctl_init(struct bge_softc *); 268 static int bge_sysctl_verify(SYSCTLFN_PROTO); 269 270 static void bge_ape_lock_init(struct bge_softc *); 271 static void bge_ape_read_fw_ver(struct bge_softc *); 272 static int bge_ape_lock(struct bge_softc *, int); 273 static void bge_ape_unlock(struct bge_softc *, int); 274 static void bge_ape_send_event(struct bge_softc *, uint32_t); 275 static void bge_ape_driver_state_change(struct bge_softc *, int); 276 277 #ifdef BGE_DEBUG 278 #define DPRINTF(x) if (bgedebug) printf x 279 #define DPRINTFN(n,x) if (bgedebug >= (n)) printf x 280 #define BGE_TSO_PRINTF(x) do { if (bge_tso_debug) printf x ;} while (0) 281 int bgedebug = 0; 282 int bge_tso_debug = 0; 283 void bge_debug_info(struct bge_softc *); 284 #else 285 #define DPRINTF(x) 286 #define DPRINTFN(n,x) 287 #define BGE_TSO_PRINTF(x) 288 #endif 289 290 #ifdef BGE_EVENT_COUNTERS 291 #define BGE_EVCNT_INCR(ev) (ev).ev_count++ 292 #define BGE_EVCNT_ADD(ev, val) (ev).ev_count += (val) 293 #define BGE_EVCNT_UPD(ev, val) (ev).ev_count = (val) 294 #else 295 #define BGE_EVCNT_INCR(ev) /* nothing */ 296 #define BGE_EVCNT_ADD(ev, val) /* nothing */ 297 #define BGE_EVCNT_UPD(ev, val) /* nothing */ 298 #endif 299 300 static const struct bge_product { 301 pci_vendor_id_t bp_vendor; 302 pci_product_id_t bp_product; 303 const char *bp_name; 304 } bge_products[] = { 305 /* 306 * The BCM5700 documentation seems to indicate that the hardware 307 * still has the Alteon vendor ID burned into it, though it 308 * should always be overridden by the value in the EEPROM. We'll 309 * check for it anyway. 310 */ 311 { PCI_VENDOR_ALTEON, 312 PCI_PRODUCT_ALTEON_BCM5700, 313 "Broadcom BCM5700 Gigabit Ethernet", 314 }, 315 { PCI_VENDOR_ALTEON, 316 PCI_PRODUCT_ALTEON_BCM5701, 317 "Broadcom BCM5701 Gigabit Ethernet", 318 }, 319 { PCI_VENDOR_ALTIMA, 320 PCI_PRODUCT_ALTIMA_AC1000, 321 "Altima AC1000 Gigabit Ethernet", 322 }, 323 { PCI_VENDOR_ALTIMA, 324 PCI_PRODUCT_ALTIMA_AC1001, 325 "Altima AC1001 Gigabit Ethernet", 326 }, 327 { PCI_VENDOR_ALTIMA, 328 PCI_PRODUCT_ALTIMA_AC1003, 329 "Altima AC1003 Gigabit Ethernet", 330 }, 331 { PCI_VENDOR_ALTIMA, 332 PCI_PRODUCT_ALTIMA_AC9100, 333 "Altima AC9100 Gigabit Ethernet", 334 }, 335 { PCI_VENDOR_APPLE, 336 PCI_PRODUCT_APPLE_BCM5701, 337 "APPLE BCM5701 Gigabit Ethernet", 338 }, 339 { PCI_VENDOR_BROADCOM, 340 PCI_PRODUCT_BROADCOM_BCM5700, 341 "Broadcom BCM5700 Gigabit Ethernet", 342 }, 343 { PCI_VENDOR_BROADCOM, 344 PCI_PRODUCT_BROADCOM_BCM5701, 345 "Broadcom BCM5701 Gigabit Ethernet", 346 }, 347 { PCI_VENDOR_BROADCOM, 348 PCI_PRODUCT_BROADCOM_BCM5702, 349 "Broadcom BCM5702 Gigabit Ethernet", 350 }, 351 { PCI_VENDOR_BROADCOM, 352 PCI_PRODUCT_BROADCOM_BCM5702X, 353 "Broadcom BCM5702X Gigabit Ethernet" }, 354 { PCI_VENDOR_BROADCOM, 355 PCI_PRODUCT_BROADCOM_BCM5703, 356 "Broadcom BCM5703 Gigabit Ethernet", 357 }, 358 { PCI_VENDOR_BROADCOM, 359 PCI_PRODUCT_BROADCOM_BCM5703X, 360 "Broadcom BCM5703X Gigabit Ethernet", 361 }, 362 { PCI_VENDOR_BROADCOM, 363 PCI_PRODUCT_BROADCOM_BCM5703_ALT, 364 "Broadcom BCM5703 Gigabit Ethernet", 365 }, 366 { PCI_VENDOR_BROADCOM, 367 PCI_PRODUCT_BROADCOM_BCM5704C, 368 "Broadcom BCM5704C Dual Gigabit Ethernet", 369 }, 370 { PCI_VENDOR_BROADCOM, 371 PCI_PRODUCT_BROADCOM_BCM5704S, 372 "Broadcom BCM5704S Dual Gigabit Ethernet", 373 }, 374 { PCI_VENDOR_BROADCOM, 375 PCI_PRODUCT_BROADCOM_BCM5705, 376 "Broadcom BCM5705 Gigabit Ethernet", 377 }, 378 { PCI_VENDOR_BROADCOM, 379 PCI_PRODUCT_BROADCOM_BCM5705F, 380 "Broadcom BCM5705F Gigabit Ethernet", 381 }, 382 { PCI_VENDOR_BROADCOM, 383 PCI_PRODUCT_BROADCOM_BCM5705K, 384 "Broadcom BCM5705K Gigabit Ethernet", 385 }, 386 { PCI_VENDOR_BROADCOM, 387 PCI_PRODUCT_BROADCOM_BCM5705M, 388 "Broadcom BCM5705M Gigabit Ethernet", 389 }, 390 { PCI_VENDOR_BROADCOM, 391 PCI_PRODUCT_BROADCOM_BCM5705M_ALT, 392 "Broadcom BCM5705M Gigabit Ethernet", 393 }, 394 { PCI_VENDOR_BROADCOM, 395 PCI_PRODUCT_BROADCOM_BCM5714, 396 "Broadcom BCM5714 Gigabit Ethernet", 397 }, 398 { PCI_VENDOR_BROADCOM, 399 PCI_PRODUCT_BROADCOM_BCM5714S, 400 "Broadcom BCM5714S Gigabit Ethernet", 401 }, 402 { PCI_VENDOR_BROADCOM, 403 PCI_PRODUCT_BROADCOM_BCM5715, 404 "Broadcom BCM5715 Gigabit Ethernet", 405 }, 406 { PCI_VENDOR_BROADCOM, 407 PCI_PRODUCT_BROADCOM_BCM5715S, 408 "Broadcom BCM5715S Gigabit Ethernet", 409 }, 410 { PCI_VENDOR_BROADCOM, 411 PCI_PRODUCT_BROADCOM_BCM5717, 412 "Broadcom BCM5717 Gigabit Ethernet", 413 }, 414 { PCI_VENDOR_BROADCOM, 415 PCI_PRODUCT_BROADCOM_BCM5718, 416 "Broadcom BCM5718 Gigabit Ethernet", 417 }, 418 { PCI_VENDOR_BROADCOM, 419 PCI_PRODUCT_BROADCOM_BCM5719, 420 "Broadcom BCM5719 Gigabit Ethernet", 421 }, 422 { PCI_VENDOR_BROADCOM, 423 PCI_PRODUCT_BROADCOM_BCM5720, 424 "Broadcom BCM5720 Gigabit Ethernet", 425 }, 426 { PCI_VENDOR_BROADCOM, 427 PCI_PRODUCT_BROADCOM_BCM5721, 428 "Broadcom BCM5721 Gigabit Ethernet", 429 }, 430 { PCI_VENDOR_BROADCOM, 431 PCI_PRODUCT_BROADCOM_BCM5722, 432 "Broadcom BCM5722 Gigabit Ethernet", 433 }, 434 { PCI_VENDOR_BROADCOM, 435 PCI_PRODUCT_BROADCOM_BCM5723, 436 "Broadcom BCM5723 Gigabit Ethernet", 437 }, 438 { PCI_VENDOR_BROADCOM, 439 PCI_PRODUCT_BROADCOM_BCM5724, 440 "Broadcom BCM5724 Gigabit Ethernet", 441 }, 442 { PCI_VENDOR_BROADCOM, 443 PCI_PRODUCT_BROADCOM_BCM5750, 444 "Broadcom BCM5750 Gigabit Ethernet", 445 }, 446 { PCI_VENDOR_BROADCOM, 447 PCI_PRODUCT_BROADCOM_BCM5750M, 448 "Broadcom BCM5750M Gigabit Ethernet", 449 }, 450 { PCI_VENDOR_BROADCOM, 451 PCI_PRODUCT_BROADCOM_BCM5751, 452 "Broadcom BCM5751 Gigabit Ethernet", 453 }, 454 { PCI_VENDOR_BROADCOM, 455 PCI_PRODUCT_BROADCOM_BCM5751F, 456 "Broadcom BCM5751F Gigabit Ethernet", 457 }, 458 { PCI_VENDOR_BROADCOM, 459 PCI_PRODUCT_BROADCOM_BCM5751M, 460 "Broadcom BCM5751M Gigabit Ethernet", 461 }, 462 { PCI_VENDOR_BROADCOM, 463 PCI_PRODUCT_BROADCOM_BCM5752, 464 "Broadcom BCM5752 Gigabit Ethernet", 465 }, 466 { PCI_VENDOR_BROADCOM, 467 PCI_PRODUCT_BROADCOM_BCM5752M, 468 "Broadcom BCM5752M Gigabit Ethernet", 469 }, 470 { PCI_VENDOR_BROADCOM, 471 PCI_PRODUCT_BROADCOM_BCM5753, 472 "Broadcom BCM5753 Gigabit Ethernet", 473 }, 474 { PCI_VENDOR_BROADCOM, 475 PCI_PRODUCT_BROADCOM_BCM5753F, 476 "Broadcom BCM5753F Gigabit Ethernet", 477 }, 478 { PCI_VENDOR_BROADCOM, 479 PCI_PRODUCT_BROADCOM_BCM5753M, 480 "Broadcom BCM5753M Gigabit Ethernet", 481 }, 482 { PCI_VENDOR_BROADCOM, 483 PCI_PRODUCT_BROADCOM_BCM5754, 484 "Broadcom BCM5754 Gigabit Ethernet", 485 }, 486 { PCI_VENDOR_BROADCOM, 487 PCI_PRODUCT_BROADCOM_BCM5754M, 488 "Broadcom BCM5754M Gigabit Ethernet", 489 }, 490 { PCI_VENDOR_BROADCOM, 491 PCI_PRODUCT_BROADCOM_BCM5755, 492 "Broadcom BCM5755 Gigabit Ethernet", 493 }, 494 { PCI_VENDOR_BROADCOM, 495 PCI_PRODUCT_BROADCOM_BCM5755M, 496 "Broadcom BCM5755M Gigabit Ethernet", 497 }, 498 { PCI_VENDOR_BROADCOM, 499 PCI_PRODUCT_BROADCOM_BCM5756, 500 "Broadcom BCM5756 Gigabit Ethernet", 501 }, 502 { PCI_VENDOR_BROADCOM, 503 PCI_PRODUCT_BROADCOM_BCM5761, 504 "Broadcom BCM5761 Gigabit Ethernet", 505 }, 506 { PCI_VENDOR_BROADCOM, 507 PCI_PRODUCT_BROADCOM_BCM5761E, 508 "Broadcom BCM5761E Gigabit Ethernet", 509 }, 510 { PCI_VENDOR_BROADCOM, 511 PCI_PRODUCT_BROADCOM_BCM5761S, 512 "Broadcom BCM5761S Gigabit Ethernet", 513 }, 514 { PCI_VENDOR_BROADCOM, 515 PCI_PRODUCT_BROADCOM_BCM5761SE, 516 "Broadcom BCM5761SE Gigabit Ethernet", 517 }, 518 { PCI_VENDOR_BROADCOM, 519 PCI_PRODUCT_BROADCOM_BCM5764, 520 "Broadcom BCM5764 Gigabit Ethernet", 521 }, 522 { PCI_VENDOR_BROADCOM, 523 PCI_PRODUCT_BROADCOM_BCM5780, 524 "Broadcom BCM5780 Gigabit Ethernet", 525 }, 526 { PCI_VENDOR_BROADCOM, 527 PCI_PRODUCT_BROADCOM_BCM5780S, 528 "Broadcom BCM5780S Gigabit Ethernet", 529 }, 530 { PCI_VENDOR_BROADCOM, 531 PCI_PRODUCT_BROADCOM_BCM5781, 532 "Broadcom BCM5781 Gigabit Ethernet", 533 }, 534 { PCI_VENDOR_BROADCOM, 535 PCI_PRODUCT_BROADCOM_BCM5782, 536 "Broadcom BCM5782 Gigabit Ethernet", 537 }, 538 { PCI_VENDOR_BROADCOM, 539 PCI_PRODUCT_BROADCOM_BCM5784M, 540 "BCM5784M NetLink 1000baseT Ethernet", 541 }, 542 { PCI_VENDOR_BROADCOM, 543 PCI_PRODUCT_BROADCOM_BCM5785F, 544 "BCM5785F NetLink 10/100 Ethernet", 545 }, 546 { PCI_VENDOR_BROADCOM, 547 PCI_PRODUCT_BROADCOM_BCM5785G, 548 "BCM5785G NetLink 1000baseT Ethernet", 549 }, 550 { PCI_VENDOR_BROADCOM, 551 PCI_PRODUCT_BROADCOM_BCM5786, 552 "Broadcom BCM5786 Gigabit Ethernet", 553 }, 554 { PCI_VENDOR_BROADCOM, 555 PCI_PRODUCT_BROADCOM_BCM5787, 556 "Broadcom BCM5787 Gigabit Ethernet", 557 }, 558 { PCI_VENDOR_BROADCOM, 559 PCI_PRODUCT_BROADCOM_BCM5787F, 560 "Broadcom BCM5787F 10/100 Ethernet", 561 }, 562 { PCI_VENDOR_BROADCOM, 563 PCI_PRODUCT_BROADCOM_BCM5787M, 564 "Broadcom BCM5787M Gigabit Ethernet", 565 }, 566 { PCI_VENDOR_BROADCOM, 567 PCI_PRODUCT_BROADCOM_BCM5788, 568 "Broadcom BCM5788 Gigabit Ethernet", 569 }, 570 { PCI_VENDOR_BROADCOM, 571 PCI_PRODUCT_BROADCOM_BCM5789, 572 "Broadcom BCM5789 Gigabit Ethernet", 573 }, 574 { PCI_VENDOR_BROADCOM, 575 PCI_PRODUCT_BROADCOM_BCM5901, 576 "Broadcom BCM5901 Fast Ethernet", 577 }, 578 { PCI_VENDOR_BROADCOM, 579 PCI_PRODUCT_BROADCOM_BCM5901A2, 580 "Broadcom BCM5901A2 Fast Ethernet", 581 }, 582 { PCI_VENDOR_BROADCOM, 583 PCI_PRODUCT_BROADCOM_BCM5903M, 584 "Broadcom BCM5903M Fast Ethernet", 585 }, 586 { PCI_VENDOR_BROADCOM, 587 PCI_PRODUCT_BROADCOM_BCM5906, 588 "Broadcom BCM5906 Fast Ethernet", 589 }, 590 { PCI_VENDOR_BROADCOM, 591 PCI_PRODUCT_BROADCOM_BCM5906M, 592 "Broadcom BCM5906M Fast Ethernet", 593 }, 594 { PCI_VENDOR_BROADCOM, 595 PCI_PRODUCT_BROADCOM_BCM57760, 596 "Broadcom BCM57760 Fast Ethernet", 597 }, 598 { PCI_VENDOR_BROADCOM, 599 PCI_PRODUCT_BROADCOM_BCM57761, 600 "Broadcom BCM57761 Fast Ethernet", 601 }, 602 { PCI_VENDOR_BROADCOM, 603 PCI_PRODUCT_BROADCOM_BCM57762, 604 "Broadcom BCM57762 Gigabit Ethernet", 605 }, 606 { PCI_VENDOR_BROADCOM, 607 PCI_PRODUCT_BROADCOM_BCM57765, 608 "Broadcom BCM57765 Fast Ethernet", 609 }, 610 { PCI_VENDOR_BROADCOM, 611 PCI_PRODUCT_BROADCOM_BCM57766, 612 "Broadcom BCM57766 Fast Ethernet", 613 }, 614 { PCI_VENDOR_BROADCOM, 615 PCI_PRODUCT_BROADCOM_BCM57780, 616 "Broadcom BCM57780 Fast Ethernet", 617 }, 618 { PCI_VENDOR_BROADCOM, 619 PCI_PRODUCT_BROADCOM_BCM57781, 620 "Broadcom BCM57781 Fast Ethernet", 621 }, 622 { PCI_VENDOR_BROADCOM, 623 PCI_PRODUCT_BROADCOM_BCM57782, 624 "Broadcom BCM57782 Fast Ethernet", 625 }, 626 { PCI_VENDOR_BROADCOM, 627 PCI_PRODUCT_BROADCOM_BCM57785, 628 "Broadcom BCM57785 Fast Ethernet", 629 }, 630 { PCI_VENDOR_BROADCOM, 631 PCI_PRODUCT_BROADCOM_BCM57786, 632 "Broadcom BCM57786 Fast Ethernet", 633 }, 634 { PCI_VENDOR_BROADCOM, 635 PCI_PRODUCT_BROADCOM_BCM57788, 636 "Broadcom BCM57788 Fast Ethernet", 637 }, 638 { PCI_VENDOR_BROADCOM, 639 PCI_PRODUCT_BROADCOM_BCM57790, 640 "Broadcom BCM57790 Fast Ethernet", 641 }, 642 { PCI_VENDOR_BROADCOM, 643 PCI_PRODUCT_BROADCOM_BCM57791, 644 "Broadcom BCM57791 Fast Ethernet", 645 }, 646 { PCI_VENDOR_BROADCOM, 647 PCI_PRODUCT_BROADCOM_BCM57795, 648 "Broadcom BCM57795 Fast Ethernet", 649 }, 650 { PCI_VENDOR_SCHNEIDERKOCH, 651 PCI_PRODUCT_SCHNEIDERKOCH_SK_9DX1, 652 "SysKonnect SK-9Dx1 Gigabit Ethernet", 653 }, 654 { PCI_VENDOR_3COM, 655 PCI_PRODUCT_3COM_3C996, 656 "3Com 3c996 Gigabit Ethernet", 657 }, 658 { PCI_VENDOR_FUJITSU4, 659 PCI_PRODUCT_FUJITSU4_PW008GE4, 660 "Fujitsu PW008GE4 Gigabit Ethernet", 661 }, 662 { PCI_VENDOR_FUJITSU4, 663 PCI_PRODUCT_FUJITSU4_PW008GE5, 664 "Fujitsu PW008GE5 Gigabit Ethernet", 665 }, 666 { PCI_VENDOR_FUJITSU4, 667 PCI_PRODUCT_FUJITSU4_PP250_450_LAN, 668 "Fujitsu Primepower 250/450 Gigabit Ethernet", 669 }, 670 { 0, 671 0, 672 NULL }, 673 }; 674 675 #define BGE_IS_JUMBO_CAPABLE(sc) ((sc)->bge_flags & BGE_JUMBO_CAPABLE) 676 #define BGE_IS_5700_FAMILY(sc) ((sc)->bge_flags & BGE_5700_FAMILY) 677 #define BGE_IS_5705_PLUS(sc) ((sc)->bge_flags & BGE_5705_PLUS) 678 #define BGE_IS_5714_FAMILY(sc) ((sc)->bge_flags & BGE_5714_FAMILY) 679 #define BGE_IS_575X_PLUS(sc) ((sc)->bge_flags & BGE_575X_PLUS) 680 #define BGE_IS_5755_PLUS(sc) ((sc)->bge_flags & BGE_5755_PLUS) 681 #define BGE_IS_5717_PLUS(sc) ((sc)->bge_flags & BGE_5717_PLUS) 682 #define BGE_IS_57765_PLUS(sc) ((sc)->bge_flags & BGE_57765_PLUS) 683 684 static const struct bge_revision { 685 uint32_t br_chipid; 686 const char *br_name; 687 } bge_revisions[] = { 688 { BGE_CHIPID_BCM5700_A0, "BCM5700 A0" }, 689 { BGE_CHIPID_BCM5700_A1, "BCM5700 A1" }, 690 { BGE_CHIPID_BCM5700_B0, "BCM5700 B0" }, 691 { BGE_CHIPID_BCM5700_B1, "BCM5700 B1" }, 692 { BGE_CHIPID_BCM5700_B2, "BCM5700 B2" }, 693 { BGE_CHIPID_BCM5700_B3, "BCM5700 B3" }, 694 { BGE_CHIPID_BCM5700_ALTIMA, "BCM5700 Altima" }, 695 { BGE_CHIPID_BCM5700_C0, "BCM5700 C0" }, 696 { BGE_CHIPID_BCM5701_A0, "BCM5701 A0" }, 697 { BGE_CHIPID_BCM5701_B0, "BCM5701 B0" }, 698 { BGE_CHIPID_BCM5701_B2, "BCM5701 B2" }, 699 { BGE_CHIPID_BCM5701_B5, "BCM5701 B5" }, 700 { BGE_CHIPID_BCM5703_A0, "BCM5702/5703 A0" }, 701 { BGE_CHIPID_BCM5703_A1, "BCM5702/5703 A1" }, 702 { BGE_CHIPID_BCM5703_A2, "BCM5702/5703 A2" }, 703 { BGE_CHIPID_BCM5703_A3, "BCM5702/5703 A3" }, 704 { BGE_CHIPID_BCM5703_B0, "BCM5702/5703 B0" }, 705 { BGE_CHIPID_BCM5704_A0, "BCM5704 A0" }, 706 { BGE_CHIPID_BCM5704_A1, "BCM5704 A1" }, 707 { BGE_CHIPID_BCM5704_A2, "BCM5704 A2" }, 708 { BGE_CHIPID_BCM5704_A3, "BCM5704 A3" }, 709 { BGE_CHIPID_BCM5704_B0, "BCM5704 B0" }, 710 { BGE_CHIPID_BCM5705_A0, "BCM5705 A0" }, 711 { BGE_CHIPID_BCM5705_A1, "BCM5705 A1" }, 712 { BGE_CHIPID_BCM5705_A2, "BCM5705 A2" }, 713 { BGE_CHIPID_BCM5705_A3, "BCM5705 A3" }, 714 { BGE_CHIPID_BCM5750_A0, "BCM5750 A0" }, 715 { BGE_CHIPID_BCM5750_A1, "BCM5750 A1" }, 716 { BGE_CHIPID_BCM5750_A3, "BCM5750 A3" }, 717 { BGE_CHIPID_BCM5750_B0, "BCM5750 B0" }, 718 { BGE_CHIPID_BCM5750_B1, "BCM5750 B1" }, 719 { BGE_CHIPID_BCM5750_C0, "BCM5750 C0" }, 720 { BGE_CHIPID_BCM5750_C1, "BCM5750 C1" }, 721 { BGE_CHIPID_BCM5750_C2, "BCM5750 C2" }, 722 { BGE_CHIPID_BCM5752_A0, "BCM5752 A0" }, 723 { BGE_CHIPID_BCM5752_A1, "BCM5752 A1" }, 724 { BGE_CHIPID_BCM5752_A2, "BCM5752 A2" }, 725 { BGE_CHIPID_BCM5714_A0, "BCM5714 A0" }, 726 { BGE_CHIPID_BCM5714_B0, "BCM5714 B0" }, 727 { BGE_CHIPID_BCM5714_B3, "BCM5714 B3" }, 728 { BGE_CHIPID_BCM5715_A0, "BCM5715 A0" }, 729 { BGE_CHIPID_BCM5715_A1, "BCM5715 A1" }, 730 { BGE_CHIPID_BCM5715_A3, "BCM5715 A3" }, 731 { BGE_CHIPID_BCM5717_A0, "BCM5717 A0" }, 732 { BGE_CHIPID_BCM5717_B0, "BCM5717 B0" }, 733 { BGE_CHIPID_BCM5719_A0, "BCM5719 A0" }, 734 { BGE_CHIPID_BCM5720_A0, "BCM5720 A0" }, 735 { BGE_CHIPID_BCM5755_A0, "BCM5755 A0" }, 736 { BGE_CHIPID_BCM5755_A1, "BCM5755 A1" }, 737 { BGE_CHIPID_BCM5755_A2, "BCM5755 A2" }, 738 { BGE_CHIPID_BCM5755_C0, "BCM5755 C0" }, 739 { BGE_CHIPID_BCM5761_A0, "BCM5761 A0" }, 740 { BGE_CHIPID_BCM5761_A1, "BCM5761 A1" }, 741 { BGE_CHIPID_BCM5784_A0, "BCM5784 A0" }, 742 { BGE_CHIPID_BCM5784_A1, "BCM5784 A1" }, 743 /* 5754 and 5787 share the same ASIC ID */ 744 { BGE_CHIPID_BCM5787_A0, "BCM5754/5787 A0" }, 745 { BGE_CHIPID_BCM5787_A1, "BCM5754/5787 A1" }, 746 { BGE_CHIPID_BCM5787_A2, "BCM5754/5787 A2" }, 747 { BGE_CHIPID_BCM5906_A0, "BCM5906 A0" }, 748 { BGE_CHIPID_BCM5906_A1, "BCM5906 A1" }, 749 { BGE_CHIPID_BCM5906_A2, "BCM5906 A2" }, 750 { BGE_CHIPID_BCM57765_A0, "BCM57765 A0" }, 751 { BGE_CHIPID_BCM57765_B0, "BCM57765 B0" }, 752 { BGE_CHIPID_BCM57780_A0, "BCM57780 A0" }, 753 { BGE_CHIPID_BCM57780_A1, "BCM57780 A1" }, 754 755 { 0, NULL } 756 }; 757 758 /* 759 * Some defaults for major revisions, so that newer steppings 760 * that we don't know about have a shot at working. 761 */ 762 static const struct bge_revision bge_majorrevs[] = { 763 { BGE_ASICREV_BCM5700, "unknown BCM5700" }, 764 { BGE_ASICREV_BCM5701, "unknown BCM5701" }, 765 { BGE_ASICREV_BCM5703, "unknown BCM5703" }, 766 { BGE_ASICREV_BCM5704, "unknown BCM5704" }, 767 { BGE_ASICREV_BCM5705, "unknown BCM5705" }, 768 { BGE_ASICREV_BCM5750, "unknown BCM5750" }, 769 { BGE_ASICREV_BCM5714, "unknown BCM5714" }, 770 { BGE_ASICREV_BCM5714_A0, "unknown BCM5714" }, 771 { BGE_ASICREV_BCM5752, "unknown BCM5752" }, 772 { BGE_ASICREV_BCM5780, "unknown BCM5780" }, 773 { BGE_ASICREV_BCM5755, "unknown BCM5755" }, 774 { BGE_ASICREV_BCM5761, "unknown BCM5761" }, 775 { BGE_ASICREV_BCM5784, "unknown BCM5784" }, 776 { BGE_ASICREV_BCM5785, "unknown BCM5785" }, 777 /* 5754 and 5787 share the same ASIC ID */ 778 { BGE_ASICREV_BCM5787, "unknown BCM5754/5787" }, 779 { BGE_ASICREV_BCM5906, "unknown BCM5906" }, 780 { BGE_ASICREV_BCM57765, "unknown BCM57765" }, 781 { BGE_ASICREV_BCM57766, "unknown BCM57766" }, 782 { BGE_ASICREV_BCM57780, "unknown BCM57780" }, 783 { BGE_ASICREV_BCM5717, "unknown BCM5717" }, 784 { BGE_ASICREV_BCM5719, "unknown BCM5719" }, 785 { BGE_ASICREV_BCM5720, "unknown BCM5720" }, 786 787 { 0, NULL } 788 }; 789 790 static int bge_allow_asf = 1; 791 792 CFATTACH_DECL_NEW(bge, sizeof(struct bge_softc), 793 bge_probe, bge_attach, NULL, NULL); 794 795 static uint32_t 796 bge_readmem_ind(struct bge_softc *sc, int off) 797 { 798 pcireg_t val; 799 800 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906 && 801 off >= BGE_STATS_BLOCK && off < BGE_SEND_RING_1_TO_4) 802 return 0; 803 804 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_BASEADDR, off); 805 val = pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_DATA); 806 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_BASEADDR, 0); 807 return val; 808 } 809 810 static void 811 bge_writemem_ind(struct bge_softc *sc, int off, int val) 812 { 813 814 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_BASEADDR, off); 815 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_DATA, val); 816 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_BASEADDR, 0); 817 } 818 819 /* 820 * PCI Express only 821 */ 822 static void 823 bge_set_max_readrq(struct bge_softc *sc) 824 { 825 pcireg_t val; 826 827 val = pci_conf_read(sc->sc_pc, sc->sc_pcitag, sc->bge_pciecap 828 + PCI_PCIE_DCSR); 829 val &= ~PCI_PCIE_DCSR_MAX_READ_REQ; 830 switch (sc->bge_expmrq) { 831 case 2048: 832 val |= BGE_PCIE_DEVCTL_MAX_READRQ_2048; 833 break; 834 case 4096: 835 val |= BGE_PCIE_DEVCTL_MAX_READRQ_4096; 836 break; 837 default: 838 panic("incorrect expmrq value(%d)", sc->bge_expmrq); 839 break; 840 } 841 pci_conf_write(sc->sc_pc, sc->sc_pcitag, sc->bge_pciecap 842 + PCI_PCIE_DCSR, val); 843 } 844 845 #ifdef notdef 846 static uint32_t 847 bge_readreg_ind(struct bge_softc *sc, int off) 848 { 849 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_REG_BASEADDR, off); 850 return (pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_REG_DATA)); 851 } 852 #endif 853 854 static void 855 bge_writereg_ind(struct bge_softc *sc, int off, int val) 856 { 857 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_REG_BASEADDR, off); 858 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_REG_DATA, val); 859 } 860 861 static void 862 bge_writemem_direct(struct bge_softc *sc, int off, int val) 863 { 864 CSR_WRITE_4(sc, off, val); 865 } 866 867 static void 868 bge_writembx(struct bge_softc *sc, int off, int val) 869 { 870 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 871 off += BGE_LPMBX_IRQ0_HI - BGE_MBX_IRQ0_HI; 872 873 CSR_WRITE_4(sc, off, val); 874 } 875 876 static void 877 bge_writembx_flush(struct bge_softc *sc, int off, int val) 878 { 879 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 880 off += BGE_LPMBX_IRQ0_HI - BGE_MBX_IRQ0_HI; 881 882 CSR_WRITE_4_FLUSH(sc, off, val); 883 } 884 885 /* 886 * Clear all stale locks and select the lock for this driver instance. 887 */ 888 void 889 bge_ape_lock_init(struct bge_softc *sc) 890 { 891 struct pci_attach_args *pa = &(sc->bge_pa); 892 uint32_t bit, regbase; 893 int i; 894 895 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761) 896 regbase = BGE_APE_LOCK_GRANT; 897 else 898 regbase = BGE_APE_PER_LOCK_GRANT; 899 900 /* Clear any stale locks. */ 901 for (i = BGE_APE_LOCK_PHY0; i <= BGE_APE_LOCK_GPIO; i++) { 902 switch (i) { 903 case BGE_APE_LOCK_PHY0: 904 case BGE_APE_LOCK_PHY1: 905 case BGE_APE_LOCK_PHY2: 906 case BGE_APE_LOCK_PHY3: 907 bit = BGE_APE_LOCK_GRANT_DRIVER0; 908 break; 909 default: 910 if (pa->pa_function != 0) 911 bit = BGE_APE_LOCK_GRANT_DRIVER0; 912 else 913 bit = (1 << pa->pa_function); 914 } 915 APE_WRITE_4(sc, regbase + 4 * i, bit); 916 } 917 918 /* Select the PHY lock based on the device's function number. */ 919 switch (pa->pa_function) { 920 case 0: 921 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY0; 922 break; 923 case 1: 924 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY1; 925 break; 926 case 2: 927 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY2; 928 break; 929 case 3: 930 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY3; 931 break; 932 default: 933 printf("%s: PHY lock not supported on function\n", 934 device_xname(sc->bge_dev)); 935 break; 936 } 937 } 938 939 /* 940 * Check for APE firmware, set flags, and print version info. 941 */ 942 void 943 bge_ape_read_fw_ver(struct bge_softc *sc) 944 { 945 const char *fwtype; 946 uint32_t apedata, features; 947 948 /* Check for a valid APE signature in shared memory. */ 949 apedata = APE_READ_4(sc, BGE_APE_SEG_SIG); 950 if (apedata != BGE_APE_SEG_SIG_MAGIC) { 951 sc->bge_mfw_flags &= ~ BGE_MFW_ON_APE; 952 return; 953 } 954 955 /* Check if APE firmware is running. */ 956 apedata = APE_READ_4(sc, BGE_APE_FW_STATUS); 957 if ((apedata & BGE_APE_FW_STATUS_READY) == 0) { 958 printf("%s: APE signature found but FW status not ready! " 959 "0x%08x\n", device_xname(sc->bge_dev), apedata); 960 return; 961 } 962 963 sc->bge_mfw_flags |= BGE_MFW_ON_APE; 964 965 /* Fetch the APE firwmare type and version. */ 966 apedata = APE_READ_4(sc, BGE_APE_FW_VERSION); 967 features = APE_READ_4(sc, BGE_APE_FW_FEATURES); 968 if ((features & BGE_APE_FW_FEATURE_NCSI) != 0) { 969 sc->bge_mfw_flags |= BGE_MFW_TYPE_NCSI; 970 fwtype = "NCSI"; 971 } else if ((features & BGE_APE_FW_FEATURE_DASH) != 0) { 972 sc->bge_mfw_flags |= BGE_MFW_TYPE_DASH; 973 fwtype = "DASH"; 974 } else 975 fwtype = "UNKN"; 976 977 /* Print the APE firmware version. */ 978 printf(", APE firmware %s %d.%d.%d.%d", fwtype, 979 (apedata & BGE_APE_FW_VERSION_MAJMSK) >> BGE_APE_FW_VERSION_MAJSFT, 980 (apedata & BGE_APE_FW_VERSION_MINMSK) >> BGE_APE_FW_VERSION_MINSFT, 981 (apedata & BGE_APE_FW_VERSION_REVMSK) >> BGE_APE_FW_VERSION_REVSFT, 982 (apedata & BGE_APE_FW_VERSION_BLDMSK)); 983 } 984 985 int 986 bge_ape_lock(struct bge_softc *sc, int locknum) 987 { 988 struct pci_attach_args *pa = &(sc->bge_pa); 989 uint32_t bit, gnt, req, status; 990 int i, off; 991 992 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0) 993 return (0); 994 995 /* Lock request/grant registers have different bases. */ 996 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761) { 997 req = BGE_APE_LOCK_REQ; 998 gnt = BGE_APE_LOCK_GRANT; 999 } else { 1000 req = BGE_APE_PER_LOCK_REQ; 1001 gnt = BGE_APE_PER_LOCK_GRANT; 1002 } 1003 1004 off = 4 * locknum; 1005 1006 switch (locknum) { 1007 case BGE_APE_LOCK_GPIO: 1008 /* Lock required when using GPIO. */ 1009 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761) 1010 return (0); 1011 if (pa->pa_function == 0) 1012 bit = BGE_APE_LOCK_REQ_DRIVER0; 1013 else 1014 bit = (1 << pa->pa_function); 1015 break; 1016 case BGE_APE_LOCK_GRC: 1017 /* Lock required to reset the device. */ 1018 if (pa->pa_function == 0) 1019 bit = BGE_APE_LOCK_REQ_DRIVER0; 1020 else 1021 bit = (1 << pa->pa_function); 1022 break; 1023 case BGE_APE_LOCK_MEM: 1024 /* Lock required when accessing certain APE memory. */ 1025 if (pa->pa_function == 0) 1026 bit = BGE_APE_LOCK_REQ_DRIVER0; 1027 else 1028 bit = (1 << pa->pa_function); 1029 break; 1030 case BGE_APE_LOCK_PHY0: 1031 case BGE_APE_LOCK_PHY1: 1032 case BGE_APE_LOCK_PHY2: 1033 case BGE_APE_LOCK_PHY3: 1034 /* Lock required when accessing PHYs. */ 1035 bit = BGE_APE_LOCK_REQ_DRIVER0; 1036 break; 1037 default: 1038 return (EINVAL); 1039 } 1040 1041 /* Request a lock. */ 1042 APE_WRITE_4_FLUSH(sc, req + off, bit); 1043 1044 /* Wait up to 1 second to acquire lock. */ 1045 for (i = 0; i < 20000; i++) { 1046 status = APE_READ_4(sc, gnt + off); 1047 if (status == bit) 1048 break; 1049 DELAY(50); 1050 } 1051 1052 /* Handle any errors. */ 1053 if (status != bit) { 1054 printf("%s: APE lock %d request failed! " 1055 "request = 0x%04x[0x%04x], status = 0x%04x[0x%04x]\n", 1056 device_xname(sc->bge_dev), 1057 locknum, req + off, bit & 0xFFFF, gnt + off, 1058 status & 0xFFFF); 1059 /* Revoke the lock request. */ 1060 APE_WRITE_4(sc, gnt + off, bit); 1061 return (EBUSY); 1062 } 1063 1064 return (0); 1065 } 1066 1067 void 1068 bge_ape_unlock(struct bge_softc *sc, int locknum) 1069 { 1070 struct pci_attach_args *pa = &(sc->bge_pa); 1071 uint32_t bit, gnt; 1072 int off; 1073 1074 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0) 1075 return; 1076 1077 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761) 1078 gnt = BGE_APE_LOCK_GRANT; 1079 else 1080 gnt = BGE_APE_PER_LOCK_GRANT; 1081 1082 off = 4 * locknum; 1083 1084 switch (locknum) { 1085 case BGE_APE_LOCK_GPIO: 1086 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761) 1087 return; 1088 if (pa->pa_function == 0) 1089 bit = BGE_APE_LOCK_GRANT_DRIVER0; 1090 else 1091 bit = (1 << pa->pa_function); 1092 break; 1093 case BGE_APE_LOCK_GRC: 1094 if (pa->pa_function == 0) 1095 bit = BGE_APE_LOCK_GRANT_DRIVER0; 1096 else 1097 bit = (1 << pa->pa_function); 1098 break; 1099 case BGE_APE_LOCK_MEM: 1100 if (pa->pa_function == 0) 1101 bit = BGE_APE_LOCK_GRANT_DRIVER0; 1102 else 1103 bit = (1 << pa->pa_function); 1104 break; 1105 case BGE_APE_LOCK_PHY0: 1106 case BGE_APE_LOCK_PHY1: 1107 case BGE_APE_LOCK_PHY2: 1108 case BGE_APE_LOCK_PHY3: 1109 bit = BGE_APE_LOCK_GRANT_DRIVER0; 1110 break; 1111 default: 1112 return; 1113 } 1114 1115 /* Write and flush for consecutive bge_ape_lock() */ 1116 APE_WRITE_4_FLUSH(sc, gnt + off, bit); 1117 } 1118 1119 /* 1120 * Send an event to the APE firmware. 1121 */ 1122 void 1123 bge_ape_send_event(struct bge_softc *sc, uint32_t event) 1124 { 1125 uint32_t apedata; 1126 int i; 1127 1128 /* NCSI does not support APE events. */ 1129 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0) 1130 return; 1131 1132 /* Wait up to 1ms for APE to service previous event. */ 1133 for (i = 10; i > 0; i--) { 1134 if (bge_ape_lock(sc, BGE_APE_LOCK_MEM) != 0) 1135 break; 1136 apedata = APE_READ_4(sc, BGE_APE_EVENT_STATUS); 1137 if ((apedata & BGE_APE_EVENT_STATUS_EVENT_PENDING) == 0) { 1138 APE_WRITE_4(sc, BGE_APE_EVENT_STATUS, event | 1139 BGE_APE_EVENT_STATUS_EVENT_PENDING); 1140 bge_ape_unlock(sc, BGE_APE_LOCK_MEM); 1141 APE_WRITE_4(sc, BGE_APE_EVENT, BGE_APE_EVENT_1); 1142 break; 1143 } 1144 bge_ape_unlock(sc, BGE_APE_LOCK_MEM); 1145 DELAY(100); 1146 } 1147 if (i == 0) { 1148 printf("%s: APE event 0x%08x send timed out\n", 1149 device_xname(sc->bge_dev), event); 1150 } 1151 } 1152 1153 void 1154 bge_ape_driver_state_change(struct bge_softc *sc, int kind) 1155 { 1156 uint32_t apedata, event; 1157 1158 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0) 1159 return; 1160 1161 switch (kind) { 1162 case BGE_RESET_START: 1163 /* If this is the first load, clear the load counter. */ 1164 apedata = APE_READ_4(sc, BGE_APE_HOST_SEG_SIG); 1165 if (apedata != BGE_APE_HOST_SEG_SIG_MAGIC) 1166 APE_WRITE_4(sc, BGE_APE_HOST_INIT_COUNT, 0); 1167 else { 1168 apedata = APE_READ_4(sc, BGE_APE_HOST_INIT_COUNT); 1169 APE_WRITE_4(sc, BGE_APE_HOST_INIT_COUNT, ++apedata); 1170 } 1171 APE_WRITE_4(sc, BGE_APE_HOST_SEG_SIG, 1172 BGE_APE_HOST_SEG_SIG_MAGIC); 1173 APE_WRITE_4(sc, BGE_APE_HOST_SEG_LEN, 1174 BGE_APE_HOST_SEG_LEN_MAGIC); 1175 1176 /* Add some version info if bge(4) supports it. */ 1177 APE_WRITE_4(sc, BGE_APE_HOST_DRIVER_ID, 1178 BGE_APE_HOST_DRIVER_ID_MAGIC(1, 0)); 1179 APE_WRITE_4(sc, BGE_APE_HOST_BEHAVIOR, 1180 BGE_APE_HOST_BEHAV_NO_PHYLOCK); 1181 APE_WRITE_4(sc, BGE_APE_HOST_HEARTBEAT_INT_MS, 1182 BGE_APE_HOST_HEARTBEAT_INT_DISABLE); 1183 APE_WRITE_4(sc, BGE_APE_HOST_DRVR_STATE, 1184 BGE_APE_HOST_DRVR_STATE_START); 1185 event = BGE_APE_EVENT_STATUS_STATE_START; 1186 break; 1187 case BGE_RESET_SHUTDOWN: 1188 APE_WRITE_4(sc, BGE_APE_HOST_DRVR_STATE, 1189 BGE_APE_HOST_DRVR_STATE_UNLOAD); 1190 event = BGE_APE_EVENT_STATUS_STATE_UNLOAD; 1191 break; 1192 case BGE_RESET_SUSPEND: 1193 event = BGE_APE_EVENT_STATUS_STATE_SUSPEND; 1194 break; 1195 default: 1196 return; 1197 } 1198 1199 bge_ape_send_event(sc, event | BGE_APE_EVENT_STATUS_DRIVER_EVNT | 1200 BGE_APE_EVENT_STATUS_STATE_CHNGE); 1201 } 1202 1203 static uint8_t 1204 bge_nvram_getbyte(struct bge_softc *sc, int addr, uint8_t *dest) 1205 { 1206 uint32_t access, byte = 0; 1207 int i; 1208 1209 /* Lock. */ 1210 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_SET1); 1211 for (i = 0; i < 8000; i++) { 1212 if (CSR_READ_4(sc, BGE_NVRAM_SWARB) & BGE_NVRAMSWARB_GNT1) 1213 break; 1214 DELAY(20); 1215 } 1216 if (i == 8000) 1217 return 1; 1218 1219 /* Enable access. */ 1220 access = CSR_READ_4(sc, BGE_NVRAM_ACCESS); 1221 CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access | BGE_NVRAMACC_ENABLE); 1222 1223 CSR_WRITE_4(sc, BGE_NVRAM_ADDR, addr & 0xfffffffc); 1224 CSR_WRITE_4(sc, BGE_NVRAM_CMD, BGE_NVRAM_READCMD); 1225 for (i = 0; i < BGE_TIMEOUT * 10; i++) { 1226 DELAY(10); 1227 if (CSR_READ_4(sc, BGE_NVRAM_CMD) & BGE_NVRAMCMD_DONE) { 1228 DELAY(10); 1229 break; 1230 } 1231 } 1232 1233 if (i == BGE_TIMEOUT * 10) { 1234 aprint_error_dev(sc->bge_dev, "nvram read timed out\n"); 1235 return 1; 1236 } 1237 1238 /* Get result. */ 1239 byte = CSR_READ_4(sc, BGE_NVRAM_RDDATA); 1240 1241 *dest = (bswap32(byte) >> ((addr % 4) * 8)) & 0xFF; 1242 1243 /* Disable access. */ 1244 CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access); 1245 1246 /* Unlock. */ 1247 CSR_WRITE_4_FLUSH(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_CLR1); 1248 1249 return 0; 1250 } 1251 1252 /* 1253 * Read a sequence of bytes from NVRAM. 1254 */ 1255 static int 1256 bge_read_nvram(struct bge_softc *sc, uint8_t *dest, int off, int cnt) 1257 { 1258 int error = 0, i; 1259 uint8_t byte = 0; 1260 1261 if (BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5906) 1262 return 1; 1263 1264 for (i = 0; i < cnt; i++) { 1265 error = bge_nvram_getbyte(sc, off + i, &byte); 1266 if (error) 1267 break; 1268 *(dest + i) = byte; 1269 } 1270 1271 return (error ? 1 : 0); 1272 } 1273 1274 /* 1275 * Read a byte of data stored in the EEPROM at address 'addr.' The 1276 * BCM570x supports both the traditional bitbang interface and an 1277 * auto access interface for reading the EEPROM. We use the auto 1278 * access method. 1279 */ 1280 static uint8_t 1281 bge_eeprom_getbyte(struct bge_softc *sc, int addr, uint8_t *dest) 1282 { 1283 int i; 1284 uint32_t byte = 0; 1285 1286 /* 1287 * Enable use of auto EEPROM access so we can avoid 1288 * having to use the bitbang method. 1289 */ 1290 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM); 1291 1292 /* Reset the EEPROM, load the clock period. */ 1293 CSR_WRITE_4(sc, BGE_EE_ADDR, 1294 BGE_EEADDR_RESET | BGE_EEHALFCLK(BGE_HALFCLK_384SCL)); 1295 DELAY(20); 1296 1297 /* Issue the read EEPROM command. */ 1298 CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr); 1299 1300 /* Wait for completion */ 1301 for (i = 0; i < BGE_TIMEOUT * 10; i++) { 1302 DELAY(10); 1303 if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE) 1304 break; 1305 } 1306 1307 if (i == BGE_TIMEOUT * 10) { 1308 aprint_error_dev(sc->bge_dev, "eeprom read timed out\n"); 1309 return 1; 1310 } 1311 1312 /* Get result. */ 1313 byte = CSR_READ_4(sc, BGE_EE_DATA); 1314 1315 *dest = (byte >> ((addr % 4) * 8)) & 0xFF; 1316 1317 return 0; 1318 } 1319 1320 /* 1321 * Read a sequence of bytes from the EEPROM. 1322 */ 1323 static int 1324 bge_read_eeprom(struct bge_softc *sc, void *destv, int off, int cnt) 1325 { 1326 int error = 0, i; 1327 uint8_t byte = 0; 1328 char *dest = destv; 1329 1330 for (i = 0; i < cnt; i++) { 1331 error = bge_eeprom_getbyte(sc, off + i, &byte); 1332 if (error) 1333 break; 1334 *(dest + i) = byte; 1335 } 1336 1337 return (error ? 1 : 0); 1338 } 1339 1340 static int 1341 bge_miibus_readreg(device_t dev, int phy, int reg) 1342 { 1343 struct bge_softc *sc = device_private(dev); 1344 uint32_t val; 1345 uint32_t autopoll; 1346 int i; 1347 1348 if (bge_ape_lock(sc, sc->bge_phy_ape_lock) != 0) 1349 return 0; 1350 1351 /* Reading with autopolling on may trigger PCI errors */ 1352 autopoll = CSR_READ_4(sc, BGE_MI_MODE); 1353 if (autopoll & BGE_MIMODE_AUTOPOLL) { 1354 BGE_STS_CLRBIT(sc, BGE_STS_AUTOPOLL); 1355 BGE_CLRBIT_FLUSH(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 1356 DELAY(80); 1357 } 1358 1359 CSR_WRITE_4_FLUSH(sc, BGE_MI_COMM, BGE_MICMD_READ | BGE_MICOMM_BUSY | 1360 BGE_MIPHY(phy) | BGE_MIREG(reg)); 1361 1362 for (i = 0; i < BGE_TIMEOUT; i++) { 1363 delay(10); 1364 val = CSR_READ_4(sc, BGE_MI_COMM); 1365 if (!(val & BGE_MICOMM_BUSY)) { 1366 DELAY(5); 1367 val = CSR_READ_4(sc, BGE_MI_COMM); 1368 break; 1369 } 1370 } 1371 1372 if (i == BGE_TIMEOUT) { 1373 aprint_error_dev(sc->bge_dev, "PHY read timed out\n"); 1374 val = 0; 1375 goto done; 1376 } 1377 1378 done: 1379 if (autopoll & BGE_MIMODE_AUTOPOLL) { 1380 BGE_STS_SETBIT(sc, BGE_STS_AUTOPOLL); 1381 BGE_SETBIT_FLUSH(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 1382 DELAY(80); 1383 } 1384 1385 bge_ape_unlock(sc, sc->bge_phy_ape_lock); 1386 1387 if (val & BGE_MICOMM_READFAIL) 1388 return 0; 1389 1390 return (val & 0xFFFF); 1391 } 1392 1393 static void 1394 bge_miibus_writereg(device_t dev, int phy, int reg, int val) 1395 { 1396 struct bge_softc *sc = device_private(dev); 1397 uint32_t autopoll; 1398 int i; 1399 1400 if (bge_ape_lock(sc, sc->bge_phy_ape_lock) != 0) 1401 return; 1402 1403 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906 && 1404 (reg == BRGPHY_MII_1000CTL || reg == BRGPHY_MII_AUXCTL)) 1405 return; 1406 1407 /* Reading with autopolling on may trigger PCI errors */ 1408 autopoll = CSR_READ_4(sc, BGE_MI_MODE); 1409 if (autopoll & BGE_MIMODE_AUTOPOLL) { 1410 BGE_STS_CLRBIT(sc, BGE_STS_AUTOPOLL); 1411 BGE_CLRBIT_FLUSH(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 1412 DELAY(80); 1413 } 1414 1415 CSR_WRITE_4_FLUSH(sc, BGE_MI_COMM, BGE_MICMD_WRITE | BGE_MICOMM_BUSY | 1416 BGE_MIPHY(phy) | BGE_MIREG(reg) | val); 1417 1418 for (i = 0; i < BGE_TIMEOUT; i++) { 1419 delay(10); 1420 if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY)) { 1421 delay(5); 1422 CSR_READ_4(sc, BGE_MI_COMM); 1423 break; 1424 } 1425 } 1426 1427 if (autopoll & BGE_MIMODE_AUTOPOLL) { 1428 BGE_STS_SETBIT(sc, BGE_STS_AUTOPOLL); 1429 BGE_SETBIT_FLUSH(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 1430 delay(80); 1431 } 1432 1433 bge_ape_unlock(sc, sc->bge_phy_ape_lock); 1434 1435 if (i == BGE_TIMEOUT) 1436 aprint_error_dev(sc->bge_dev, "PHY read timed out\n"); 1437 } 1438 1439 static void 1440 bge_miibus_statchg(struct ifnet *ifp) 1441 { 1442 struct bge_softc *sc = ifp->if_softc; 1443 struct mii_data *mii = &sc->bge_mii; 1444 uint32_t mac_mode, rx_mode, tx_mode; 1445 1446 /* 1447 * Get flow control negotiation result. 1448 */ 1449 if (IFM_SUBTYPE(mii->mii_media.ifm_cur->ifm_media) == IFM_AUTO && 1450 (mii->mii_media_active & IFM_ETH_FMASK) != sc->bge_flowflags) { 1451 sc->bge_flowflags = mii->mii_media_active & IFM_ETH_FMASK; 1452 mii->mii_media_active &= ~IFM_ETH_FMASK; 1453 } 1454 1455 /* Set the port mode (MII/GMII) to match the link speed. */ 1456 mac_mode = CSR_READ_4(sc, BGE_MAC_MODE) & 1457 ~(BGE_MACMODE_PORTMODE | BGE_MACMODE_HALF_DUPLEX); 1458 tx_mode = CSR_READ_4(sc, BGE_TX_MODE); 1459 rx_mode = CSR_READ_4(sc, BGE_RX_MODE); 1460 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T || 1461 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX) 1462 mac_mode |= BGE_PORTMODE_GMII; 1463 else 1464 mac_mode |= BGE_PORTMODE_MII; 1465 1466 tx_mode &= ~BGE_TXMODE_FLOWCTL_ENABLE; 1467 rx_mode &= ~BGE_RXMODE_FLOWCTL_ENABLE; 1468 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 1469 if (sc->bge_flowflags & IFM_ETH_TXPAUSE) 1470 tx_mode |= BGE_TXMODE_FLOWCTL_ENABLE; 1471 if (sc->bge_flowflags & IFM_ETH_RXPAUSE) 1472 rx_mode |= BGE_RXMODE_FLOWCTL_ENABLE; 1473 } else 1474 mac_mode |= BGE_MACMODE_HALF_DUPLEX; 1475 1476 CSR_WRITE_4_FLUSH(sc, BGE_MAC_MODE, mac_mode); 1477 DELAY(40); 1478 CSR_WRITE_4(sc, BGE_TX_MODE, tx_mode); 1479 CSR_WRITE_4(sc, BGE_RX_MODE, rx_mode); 1480 } 1481 1482 /* 1483 * Update rx threshold levels to values in a particular slot 1484 * of the interrupt-mitigation table bge_rx_threshes. 1485 */ 1486 static void 1487 bge_set_thresh(struct ifnet *ifp, int lvl) 1488 { 1489 struct bge_softc *sc = ifp->if_softc; 1490 int s; 1491 1492 /* For now, just save the new Rx-intr thresholds and record 1493 * that a threshold update is pending. Updating the hardware 1494 * registers here (even at splhigh()) is observed to 1495 * occasionaly cause glitches where Rx-interrupts are not 1496 * honoured for up to 10 seconds. jonathan (at) NetBSD.org, 2003-04-05 1497 */ 1498 s = splnet(); 1499 sc->bge_rx_coal_ticks = bge_rx_threshes[lvl].rx_ticks; 1500 sc->bge_rx_max_coal_bds = bge_rx_threshes[lvl].rx_max_bds; 1501 sc->bge_pending_rxintr_change = 1; 1502 splx(s); 1503 } 1504 1505 1506 /* 1507 * Update Rx thresholds of all bge devices 1508 */ 1509 static void 1510 bge_update_all_threshes(int lvl) 1511 { 1512 struct ifnet *ifp; 1513 const char * const namebuf = "bge"; 1514 int namelen; 1515 1516 if (lvl < 0) 1517 lvl = 0; 1518 else if (lvl >= NBGE_RX_THRESH) 1519 lvl = NBGE_RX_THRESH - 1; 1520 1521 namelen = strlen(namebuf); 1522 /* 1523 * Now search all the interfaces for this name/number 1524 */ 1525 IFNET_FOREACH(ifp) { 1526 if (strncmp(ifp->if_xname, namebuf, namelen) != 0) 1527 continue; 1528 /* We got a match: update if doing auto-threshold-tuning */ 1529 if (bge_auto_thresh) 1530 bge_set_thresh(ifp, lvl); 1531 } 1532 } 1533 1534 /* 1535 * Handle events that have triggered interrupts. 1536 */ 1537 static void 1538 bge_handle_events(struct bge_softc *sc) 1539 { 1540 1541 return; 1542 } 1543 1544 /* 1545 * Memory management for jumbo frames. 1546 */ 1547 1548 static int 1549 bge_alloc_jumbo_mem(struct bge_softc *sc) 1550 { 1551 char *ptr, *kva; 1552 bus_dma_segment_t seg; 1553 int i, rseg, state, error; 1554 struct bge_jpool_entry *entry; 1555 1556 state = error = 0; 1557 1558 /* Grab a big chunk o' storage. */ 1559 if (bus_dmamem_alloc(sc->bge_dmatag, BGE_JMEM, PAGE_SIZE, 0, 1560 &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 1561 aprint_error_dev(sc->bge_dev, "can't alloc rx buffers\n"); 1562 return ENOBUFS; 1563 } 1564 1565 state = 1; 1566 if (bus_dmamem_map(sc->bge_dmatag, &seg, rseg, BGE_JMEM, (void **)&kva, 1567 BUS_DMA_NOWAIT)) { 1568 aprint_error_dev(sc->bge_dev, 1569 "can't map DMA buffers (%d bytes)\n", (int)BGE_JMEM); 1570 error = ENOBUFS; 1571 goto out; 1572 } 1573 1574 state = 2; 1575 if (bus_dmamap_create(sc->bge_dmatag, BGE_JMEM, 1, BGE_JMEM, 0, 1576 BUS_DMA_NOWAIT, &sc->bge_cdata.bge_rx_jumbo_map)) { 1577 aprint_error_dev(sc->bge_dev, "can't create DMA map\n"); 1578 error = ENOBUFS; 1579 goto out; 1580 } 1581 1582 state = 3; 1583 if (bus_dmamap_load(sc->bge_dmatag, sc->bge_cdata.bge_rx_jumbo_map, 1584 kva, BGE_JMEM, NULL, BUS_DMA_NOWAIT)) { 1585 aprint_error_dev(sc->bge_dev, "can't load DMA map\n"); 1586 error = ENOBUFS; 1587 goto out; 1588 } 1589 1590 state = 4; 1591 sc->bge_cdata.bge_jumbo_buf = (void *)kva; 1592 DPRINTFN(1,("bge_jumbo_buf = %p\n", sc->bge_cdata.bge_jumbo_buf)); 1593 1594 SLIST_INIT(&sc->bge_jfree_listhead); 1595 SLIST_INIT(&sc->bge_jinuse_listhead); 1596 1597 /* 1598 * Now divide it up into 9K pieces and save the addresses 1599 * in an array. 1600 */ 1601 ptr = sc->bge_cdata.bge_jumbo_buf; 1602 for (i = 0; i < BGE_JSLOTS; i++) { 1603 sc->bge_cdata.bge_jslots[i] = ptr; 1604 ptr += BGE_JLEN; 1605 entry = malloc(sizeof(struct bge_jpool_entry), 1606 M_DEVBUF, M_NOWAIT); 1607 if (entry == NULL) { 1608 aprint_error_dev(sc->bge_dev, 1609 "no memory for jumbo buffer queue!\n"); 1610 error = ENOBUFS; 1611 goto out; 1612 } 1613 entry->slot = i; 1614 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, 1615 entry, jpool_entries); 1616 } 1617 out: 1618 if (error != 0) { 1619 switch (state) { 1620 case 4: 1621 bus_dmamap_unload(sc->bge_dmatag, 1622 sc->bge_cdata.bge_rx_jumbo_map); 1623 case 3: 1624 bus_dmamap_destroy(sc->bge_dmatag, 1625 sc->bge_cdata.bge_rx_jumbo_map); 1626 case 2: 1627 bus_dmamem_unmap(sc->bge_dmatag, kva, BGE_JMEM); 1628 case 1: 1629 bus_dmamem_free(sc->bge_dmatag, &seg, rseg); 1630 break; 1631 default: 1632 break; 1633 } 1634 } 1635 1636 return error; 1637 } 1638 1639 /* 1640 * Allocate a jumbo buffer. 1641 */ 1642 static void * 1643 bge_jalloc(struct bge_softc *sc) 1644 { 1645 struct bge_jpool_entry *entry; 1646 1647 entry = SLIST_FIRST(&sc->bge_jfree_listhead); 1648 1649 if (entry == NULL) { 1650 aprint_error_dev(sc->bge_dev, "no free jumbo buffers\n"); 1651 return NULL; 1652 } 1653 1654 SLIST_REMOVE_HEAD(&sc->bge_jfree_listhead, jpool_entries); 1655 SLIST_INSERT_HEAD(&sc->bge_jinuse_listhead, entry, jpool_entries); 1656 return (sc->bge_cdata.bge_jslots[entry->slot]); 1657 } 1658 1659 /* 1660 * Release a jumbo buffer. 1661 */ 1662 static void 1663 bge_jfree(struct mbuf *m, void *buf, size_t size, void *arg) 1664 { 1665 struct bge_jpool_entry *entry; 1666 struct bge_softc *sc; 1667 int i, s; 1668 1669 /* Extract the softc struct pointer. */ 1670 sc = (struct bge_softc *)arg; 1671 1672 if (sc == NULL) 1673 panic("bge_jfree: can't find softc pointer!"); 1674 1675 /* calculate the slot this buffer belongs to */ 1676 1677 i = ((char *)buf 1678 - (char *)sc->bge_cdata.bge_jumbo_buf) / BGE_JLEN; 1679 1680 if ((i < 0) || (i >= BGE_JSLOTS)) 1681 panic("bge_jfree: asked to free buffer that we don't manage!"); 1682 1683 s = splvm(); 1684 entry = SLIST_FIRST(&sc->bge_jinuse_listhead); 1685 if (entry == NULL) 1686 panic("bge_jfree: buffer not in use!"); 1687 entry->slot = i; 1688 SLIST_REMOVE_HEAD(&sc->bge_jinuse_listhead, jpool_entries); 1689 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, entry, jpool_entries); 1690 1691 if (__predict_true(m != NULL)) 1692 pool_cache_put(mb_cache, m); 1693 splx(s); 1694 } 1695 1696 1697 /* 1698 * Initialize a standard receive ring descriptor. 1699 */ 1700 static int 1701 bge_newbuf_std(struct bge_softc *sc, int i, struct mbuf *m, 1702 bus_dmamap_t dmamap) 1703 { 1704 struct mbuf *m_new = NULL; 1705 struct bge_rx_bd *r; 1706 int error; 1707 1708 if (dmamap == NULL) { 1709 error = bus_dmamap_create(sc->bge_dmatag, MCLBYTES, 1, 1710 MCLBYTES, 0, BUS_DMA_NOWAIT, &dmamap); 1711 if (error != 0) 1712 return error; 1713 } 1714 1715 sc->bge_cdata.bge_rx_std_map[i] = dmamap; 1716 1717 if (m == NULL) { 1718 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1719 if (m_new == NULL) 1720 return ENOBUFS; 1721 1722 MCLGET(m_new, M_DONTWAIT); 1723 if (!(m_new->m_flags & M_EXT)) { 1724 m_freem(m_new); 1725 return ENOBUFS; 1726 } 1727 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1728 1729 } else { 1730 m_new = m; 1731 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1732 m_new->m_data = m_new->m_ext.ext_buf; 1733 } 1734 if (!(sc->bge_flags & BGE_RX_ALIGNBUG)) 1735 m_adj(m_new, ETHER_ALIGN); 1736 if (bus_dmamap_load_mbuf(sc->bge_dmatag, dmamap, m_new, 1737 BUS_DMA_READ|BUS_DMA_NOWAIT)) 1738 return ENOBUFS; 1739 bus_dmamap_sync(sc->bge_dmatag, dmamap, 0, dmamap->dm_mapsize, 1740 BUS_DMASYNC_PREREAD); 1741 1742 sc->bge_cdata.bge_rx_std_chain[i] = m_new; 1743 r = &sc->bge_rdata->bge_rx_std_ring[i]; 1744 BGE_HOSTADDR(r->bge_addr, dmamap->dm_segs[0].ds_addr); 1745 r->bge_flags = BGE_RXBDFLAG_END; 1746 r->bge_len = m_new->m_len; 1747 r->bge_idx = i; 1748 1749 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 1750 offsetof(struct bge_ring_data, bge_rx_std_ring) + 1751 i * sizeof (struct bge_rx_bd), 1752 sizeof (struct bge_rx_bd), 1753 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1754 1755 return 0; 1756 } 1757 1758 /* 1759 * Initialize a jumbo receive ring descriptor. This allocates 1760 * a jumbo buffer from the pool managed internally by the driver. 1761 */ 1762 static int 1763 bge_newbuf_jumbo(struct bge_softc *sc, int i, struct mbuf *m) 1764 { 1765 struct mbuf *m_new = NULL; 1766 struct bge_rx_bd *r; 1767 void *buf = NULL; 1768 1769 if (m == NULL) { 1770 1771 /* Allocate the mbuf. */ 1772 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1773 if (m_new == NULL) 1774 return ENOBUFS; 1775 1776 /* Allocate the jumbo buffer */ 1777 buf = bge_jalloc(sc); 1778 if (buf == NULL) { 1779 m_freem(m_new); 1780 aprint_error_dev(sc->bge_dev, 1781 "jumbo allocation failed -- packet dropped!\n"); 1782 return ENOBUFS; 1783 } 1784 1785 /* Attach the buffer to the mbuf. */ 1786 m_new->m_len = m_new->m_pkthdr.len = BGE_JUMBO_FRAMELEN; 1787 MEXTADD(m_new, buf, BGE_JUMBO_FRAMELEN, M_DEVBUF, 1788 bge_jfree, sc); 1789 m_new->m_flags |= M_EXT_RW; 1790 } else { 1791 m_new = m; 1792 buf = m_new->m_data = m_new->m_ext.ext_buf; 1793 m_new->m_ext.ext_size = BGE_JUMBO_FRAMELEN; 1794 } 1795 if (!(sc->bge_flags & BGE_RX_ALIGNBUG)) 1796 m_adj(m_new, ETHER_ALIGN); 1797 bus_dmamap_sync(sc->bge_dmatag, sc->bge_cdata.bge_rx_jumbo_map, 1798 mtod(m_new, char *) - (char *)sc->bge_cdata.bge_jumbo_buf, BGE_JLEN, 1799 BUS_DMASYNC_PREREAD); 1800 /* Set up the descriptor. */ 1801 r = &sc->bge_rdata->bge_rx_jumbo_ring[i]; 1802 sc->bge_cdata.bge_rx_jumbo_chain[i] = m_new; 1803 BGE_HOSTADDR(r->bge_addr, BGE_JUMBO_DMA_ADDR(sc, m_new)); 1804 r->bge_flags = BGE_RXBDFLAG_END|BGE_RXBDFLAG_JUMBO_RING; 1805 r->bge_len = m_new->m_len; 1806 r->bge_idx = i; 1807 1808 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 1809 offsetof(struct bge_ring_data, bge_rx_jumbo_ring) + 1810 i * sizeof (struct bge_rx_bd), 1811 sizeof (struct bge_rx_bd), 1812 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1813 1814 return 0; 1815 } 1816 1817 /* 1818 * The standard receive ring has 512 entries in it. At 2K per mbuf cluster, 1819 * that's 1MB or memory, which is a lot. For now, we fill only the first 1820 * 256 ring entries and hope that our CPU is fast enough to keep up with 1821 * the NIC. 1822 */ 1823 static int 1824 bge_init_rx_ring_std(struct bge_softc *sc) 1825 { 1826 int i; 1827 1828 if (sc->bge_flags & BGE_RXRING_VALID) 1829 return 0; 1830 1831 for (i = 0; i < BGE_SSLOTS; i++) { 1832 if (bge_newbuf_std(sc, i, NULL, 0) == ENOBUFS) 1833 return ENOBUFS; 1834 } 1835 1836 sc->bge_std = i - 1; 1837 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std); 1838 1839 sc->bge_flags |= BGE_RXRING_VALID; 1840 1841 return 0; 1842 } 1843 1844 static void 1845 bge_free_rx_ring_std(struct bge_softc *sc) 1846 { 1847 int i; 1848 1849 if (!(sc->bge_flags & BGE_RXRING_VALID)) 1850 return; 1851 1852 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { 1853 if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) { 1854 m_freem(sc->bge_cdata.bge_rx_std_chain[i]); 1855 sc->bge_cdata.bge_rx_std_chain[i] = NULL; 1856 bus_dmamap_destroy(sc->bge_dmatag, 1857 sc->bge_cdata.bge_rx_std_map[i]); 1858 } 1859 memset((char *)&sc->bge_rdata->bge_rx_std_ring[i], 0, 1860 sizeof(struct bge_rx_bd)); 1861 } 1862 1863 sc->bge_flags &= ~BGE_RXRING_VALID; 1864 } 1865 1866 static int 1867 bge_init_rx_ring_jumbo(struct bge_softc *sc) 1868 { 1869 int i; 1870 volatile struct bge_rcb *rcb; 1871 1872 if (sc->bge_flags & BGE_JUMBO_RXRING_VALID) 1873 return 0; 1874 1875 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 1876 if (bge_newbuf_jumbo(sc, i, NULL) == ENOBUFS) 1877 return ENOBUFS; 1878 } 1879 1880 sc->bge_jumbo = i - 1; 1881 sc->bge_flags |= BGE_JUMBO_RXRING_VALID; 1882 1883 rcb = &sc->bge_rdata->bge_info.bge_jumbo_rx_rcb; 1884 rcb->bge_maxlen_flags = 0; 1885 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 1886 1887 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo); 1888 1889 return 0; 1890 } 1891 1892 static void 1893 bge_free_rx_ring_jumbo(struct bge_softc *sc) 1894 { 1895 int i; 1896 1897 if (!(sc->bge_flags & BGE_JUMBO_RXRING_VALID)) 1898 return; 1899 1900 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 1901 if (sc->bge_cdata.bge_rx_jumbo_chain[i] != NULL) { 1902 m_freem(sc->bge_cdata.bge_rx_jumbo_chain[i]); 1903 sc->bge_cdata.bge_rx_jumbo_chain[i] = NULL; 1904 } 1905 memset((char *)&sc->bge_rdata->bge_rx_jumbo_ring[i], 0, 1906 sizeof(struct bge_rx_bd)); 1907 } 1908 1909 sc->bge_flags &= ~BGE_JUMBO_RXRING_VALID; 1910 } 1911 1912 static void 1913 bge_free_tx_ring(struct bge_softc *sc) 1914 { 1915 int i; 1916 struct txdmamap_pool_entry *dma; 1917 1918 if (!(sc->bge_flags & BGE_TXRING_VALID)) 1919 return; 1920 1921 for (i = 0; i < BGE_TX_RING_CNT; i++) { 1922 if (sc->bge_cdata.bge_tx_chain[i] != NULL) { 1923 m_freem(sc->bge_cdata.bge_tx_chain[i]); 1924 sc->bge_cdata.bge_tx_chain[i] = NULL; 1925 SLIST_INSERT_HEAD(&sc->txdma_list, sc->txdma[i], 1926 link); 1927 sc->txdma[i] = 0; 1928 } 1929 memset((char *)&sc->bge_rdata->bge_tx_ring[i], 0, 1930 sizeof(struct bge_tx_bd)); 1931 } 1932 1933 while ((dma = SLIST_FIRST(&sc->txdma_list))) { 1934 SLIST_REMOVE_HEAD(&sc->txdma_list, link); 1935 bus_dmamap_destroy(sc->bge_dmatag, dma->dmamap); 1936 free(dma, M_DEVBUF); 1937 } 1938 1939 sc->bge_flags &= ~BGE_TXRING_VALID; 1940 } 1941 1942 static int 1943 bge_init_tx_ring(struct bge_softc *sc) 1944 { 1945 int i; 1946 bus_dmamap_t dmamap; 1947 struct txdmamap_pool_entry *dma; 1948 1949 if (sc->bge_flags & BGE_TXRING_VALID) 1950 return 0; 1951 1952 sc->bge_txcnt = 0; 1953 sc->bge_tx_saved_considx = 0; 1954 1955 /* Initialize transmit producer index for host-memory send ring. */ 1956 sc->bge_tx_prodidx = 0; 1957 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx); 1958 /* 5700 b2 errata */ 1959 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX) 1960 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx); 1961 1962 /* NIC-memory send ring not used; initialize to zero. */ 1963 bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0); 1964 /* 5700 b2 errata */ 1965 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX) 1966 bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0); 1967 1968 SLIST_INIT(&sc->txdma_list); 1969 for (i = 0; i < BGE_RSLOTS; i++) { 1970 if (bus_dmamap_create(sc->bge_dmatag, BGE_TXDMA_MAX, 1971 BGE_NTXSEG, ETHER_MAX_LEN_JUMBO, 0, BUS_DMA_NOWAIT, 1972 &dmamap)) 1973 return ENOBUFS; 1974 if (dmamap == NULL) 1975 panic("dmamap NULL in bge_init_tx_ring"); 1976 dma = malloc(sizeof(*dma), M_DEVBUF, M_NOWAIT); 1977 if (dma == NULL) { 1978 aprint_error_dev(sc->bge_dev, 1979 "can't alloc txdmamap_pool_entry\n"); 1980 bus_dmamap_destroy(sc->bge_dmatag, dmamap); 1981 return ENOMEM; 1982 } 1983 dma->dmamap = dmamap; 1984 SLIST_INSERT_HEAD(&sc->txdma_list, dma, link); 1985 } 1986 1987 sc->bge_flags |= BGE_TXRING_VALID; 1988 1989 return 0; 1990 } 1991 1992 static void 1993 bge_setmulti(struct bge_softc *sc) 1994 { 1995 struct ethercom *ac = &sc->ethercom; 1996 struct ifnet *ifp = &ac->ec_if; 1997 struct ether_multi *enm; 1998 struct ether_multistep step; 1999 uint32_t hashes[4] = { 0, 0, 0, 0 }; 2000 uint32_t h; 2001 int i; 2002 2003 if (ifp->if_flags & IFF_PROMISC) 2004 goto allmulti; 2005 2006 /* Now program new ones. */ 2007 ETHER_FIRST_MULTI(step, ac, enm); 2008 while (enm != NULL) { 2009 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 2010 /* 2011 * We must listen to a range of multicast addresses. 2012 * For now, just accept all multicasts, rather than 2013 * trying to set only those filter bits needed to match 2014 * the range. (At this time, the only use of address 2015 * ranges is for IP multicast routing, for which the 2016 * range is big enough to require all bits set.) 2017 */ 2018 goto allmulti; 2019 } 2020 2021 h = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN); 2022 2023 /* Just want the 7 least-significant bits. */ 2024 h &= 0x7f; 2025 2026 hashes[(h & 0x60) >> 5] |= 1 << (h & 0x1F); 2027 ETHER_NEXT_MULTI(step, enm); 2028 } 2029 2030 ifp->if_flags &= ~IFF_ALLMULTI; 2031 goto setit; 2032 2033 allmulti: 2034 ifp->if_flags |= IFF_ALLMULTI; 2035 hashes[0] = hashes[1] = hashes[2] = hashes[3] = 0xffffffff; 2036 2037 setit: 2038 for (i = 0; i < 4; i++) 2039 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]); 2040 } 2041 2042 static void 2043 bge_sig_pre_reset(struct bge_softc *sc, int type) 2044 { 2045 2046 /* 2047 * Some chips don't like this so only do this if ASF is enabled 2048 */ 2049 if (sc->bge_asf_mode) 2050 bge_writemem_ind(sc, BGE_SRAM_FW_MB, BGE_SRAM_FW_MB_MAGIC); 2051 2052 if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) { 2053 switch (type) { 2054 case BGE_RESET_START: 2055 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 2056 BGE_FW_DRV_STATE_START); 2057 break; 2058 case BGE_RESET_SHUTDOWN: 2059 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 2060 BGE_FW_DRV_STATE_UNLOAD); 2061 break; 2062 case BGE_RESET_SUSPEND: 2063 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 2064 BGE_FW_DRV_STATE_SUSPEND); 2065 break; 2066 } 2067 } 2068 2069 if (type == BGE_RESET_START || type == BGE_RESET_SUSPEND) 2070 bge_ape_driver_state_change(sc, type); 2071 } 2072 2073 static void 2074 bge_sig_post_reset(struct bge_softc *sc, int type) 2075 { 2076 2077 if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) { 2078 switch (type) { 2079 case BGE_RESET_START: 2080 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 2081 BGE_FW_DRV_STATE_START_DONE); 2082 /* START DONE */ 2083 break; 2084 case BGE_RESET_SHUTDOWN: 2085 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 2086 BGE_FW_DRV_STATE_UNLOAD_DONE); 2087 break; 2088 } 2089 } 2090 2091 if (type == BGE_RESET_SHUTDOWN) 2092 bge_ape_driver_state_change(sc, type); 2093 } 2094 2095 static void 2096 bge_sig_legacy(struct bge_softc *sc, int type) 2097 { 2098 2099 if (sc->bge_asf_mode) { 2100 switch (type) { 2101 case BGE_RESET_START: 2102 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 2103 BGE_FW_DRV_STATE_START); 2104 break; 2105 case BGE_RESET_SHUTDOWN: 2106 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 2107 BGE_FW_DRV_STATE_UNLOAD); 2108 break; 2109 } 2110 } 2111 } 2112 2113 static void 2114 bge_wait_for_event_ack(struct bge_softc *sc) 2115 { 2116 int i; 2117 2118 /* wait up to 2500usec */ 2119 for (i = 0; i < 250; i++) { 2120 if (!(CSR_READ_4(sc, BGE_RX_CPU_EVENT) & 2121 BGE_RX_CPU_DRV_EVENT)) 2122 break; 2123 DELAY(10); 2124 } 2125 } 2126 2127 static void 2128 bge_stop_fw(struct bge_softc *sc) 2129 { 2130 2131 if (sc->bge_asf_mode) { 2132 bge_wait_for_event_ack(sc); 2133 2134 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_MB, BGE_FW_CMD_PAUSE); 2135 CSR_WRITE_4_FLUSH(sc, BGE_RX_CPU_EVENT, 2136 CSR_READ_4(sc, BGE_RX_CPU_EVENT) | BGE_RX_CPU_DRV_EVENT); 2137 2138 bge_wait_for_event_ack(sc); 2139 } 2140 } 2141 2142 static int 2143 bge_poll_fw(struct bge_softc *sc) 2144 { 2145 uint32_t val; 2146 int i; 2147 2148 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 2149 for (i = 0; i < BGE_TIMEOUT; i++) { 2150 val = CSR_READ_4(sc, BGE_VCPU_STATUS); 2151 if (val & BGE_VCPU_STATUS_INIT_DONE) 2152 break; 2153 DELAY(100); 2154 } 2155 if (i >= BGE_TIMEOUT) { 2156 aprint_error_dev(sc->bge_dev, "reset timed out\n"); 2157 return -1; 2158 } 2159 } else if ((sc->bge_flags & BGE_NO_EEPROM) == 0) { 2160 /* 2161 * Poll the value location we just wrote until 2162 * we see the 1's complement of the magic number. 2163 * This indicates that the firmware initialization 2164 * is complete. 2165 * XXX 1000ms for Flash and 10000ms for SEEPROM. 2166 */ 2167 for (i = 0; i < BGE_TIMEOUT; i++) { 2168 val = bge_readmem_ind(sc, BGE_SRAM_FW_MB); 2169 if (val == ~BGE_SRAM_FW_MB_MAGIC) 2170 break; 2171 DELAY(10); 2172 } 2173 2174 if (i >= BGE_TIMEOUT) { 2175 aprint_error_dev(sc->bge_dev, 2176 "firmware handshake timed out, val = %x\n", val); 2177 return -1; 2178 } 2179 } 2180 2181 if (sc->bge_chipid == BGE_CHIPID_BCM57765_A0) { 2182 /* tg3 says we have to wait extra time */ 2183 delay(10 * 1000); 2184 } 2185 2186 return 0; 2187 } 2188 2189 int 2190 bge_phy_addr(struct bge_softc *sc) 2191 { 2192 struct pci_attach_args *pa = &(sc->bge_pa); 2193 int phy_addr = 1; 2194 2195 /* 2196 * PHY address mapping for various devices. 2197 * 2198 * | F0 Cu | F0 Sr | F1 Cu | F1 Sr | 2199 * ---------+-------+-------+-------+-------+ 2200 * BCM57XX | 1 | X | X | X | 2201 * BCM5704 | 1 | X | 1 | X | 2202 * BCM5717 | 1 | 8 | 2 | 9 | 2203 * BCM5719 | 1 | 8 | 2 | 9 | 2204 * BCM5720 | 1 | 8 | 2 | 9 | 2205 * 2206 * | F2 Cu | F2 Sr | F3 Cu | F3 Sr | 2207 * ---------+-------+-------+-------+-------+ 2208 * BCM57XX | X | X | X | X | 2209 * BCM5704 | X | X | X | X | 2210 * BCM5717 | X | X | X | X | 2211 * BCM5719 | 3 | 10 | 4 | 11 | 2212 * BCM5720 | X | X | X | X | 2213 * 2214 * Other addresses may respond but they are not 2215 * IEEE compliant PHYs and should be ignored. 2216 */ 2217 switch (BGE_ASICREV(sc->bge_chipid)) { 2218 case BGE_ASICREV_BCM5717: 2219 case BGE_ASICREV_BCM5719: 2220 case BGE_ASICREV_BCM5720: 2221 phy_addr = pa->pa_function; 2222 if (sc->bge_chipid == BGE_CHIPID_BCM5717_A0) { 2223 phy_addr += (CSR_READ_4(sc, BGE_SGDIG_STS) & 2224 BGE_SGDIGSTS_IS_SERDES) ? 8 : 1; 2225 } else { 2226 phy_addr += (CSR_READ_4(sc, BGE_CPMU_PHY_STRAP) & 2227 BGE_CPMU_PHY_STRAP_IS_SERDES) ? 8 : 1; 2228 } 2229 } 2230 2231 return phy_addr; 2232 } 2233 2234 /* 2235 * Do endian, PCI and DMA initialization. Also check the on-board ROM 2236 * self-test results. 2237 */ 2238 static int 2239 bge_chipinit(struct bge_softc *sc) 2240 { 2241 uint32_t dma_rw_ctl, mode_ctl, reg; 2242 int i; 2243 2244 /* Set endianness before we access any non-PCI registers. */ 2245 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MISC_CTL, 2246 BGE_INIT); 2247 2248 /* 2249 * Clear the MAC statistics block in the NIC's 2250 * internal memory. 2251 */ 2252 for (i = BGE_STATS_BLOCK; 2253 i < BGE_STATS_BLOCK_END + 1; i += sizeof(uint32_t)) 2254 BGE_MEMWIN_WRITE(sc->sc_pc, sc->sc_pcitag, i, 0); 2255 2256 for (i = BGE_STATUS_BLOCK; 2257 i < BGE_STATUS_BLOCK_END + 1; i += sizeof(uint32_t)) 2258 BGE_MEMWIN_WRITE(sc->sc_pc, sc->sc_pcitag, i, 0); 2259 2260 /* 5717 workaround from tg3 */ 2261 if (sc->bge_chipid == BGE_CHIPID_BCM5717_A0) { 2262 /* Save */ 2263 mode_ctl = CSR_READ_4(sc, BGE_MODE_CTL); 2264 2265 /* Temporary modify MODE_CTL to control TLP */ 2266 reg = mode_ctl & ~BGE_MODECTL_PCIE_TLPADDRMASK; 2267 CSR_WRITE_4(sc, BGE_MODE_CTL, reg | BGE_MODECTL_PCIE_TLPADDR1); 2268 2269 /* Control TLP */ 2270 reg = CSR_READ_4(sc, BGE_TLP_CONTROL_REG + 2271 BGE_TLP_PHYCTL1); 2272 CSR_WRITE_4(sc, BGE_TLP_CONTROL_REG + BGE_TLP_PHYCTL1, 2273 reg | BGE_TLP_PHYCTL1_EN_L1PLLPD); 2274 2275 /* Restore */ 2276 CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl); 2277 } 2278 2279 /* XXX Should we use 57765_FAMILY? */ 2280 if (BGE_IS_57765_PLUS(sc)) { 2281 if (sc->bge_chipid == BGE_CHIPID_BCM57765_A0) { 2282 /* Save */ 2283 mode_ctl = CSR_READ_4(sc, BGE_MODE_CTL); 2284 2285 /* Temporary modify MODE_CTL to control TLP */ 2286 reg = mode_ctl & ~BGE_MODECTL_PCIE_TLPADDRMASK; 2287 CSR_WRITE_4(sc, BGE_MODE_CTL, 2288 reg | BGE_MODECTL_PCIE_TLPADDR1); 2289 2290 /* Control TLP */ 2291 reg = CSR_READ_4(sc, BGE_TLP_CONTROL_REG + 2292 BGE_TLP_PHYCTL5); 2293 CSR_WRITE_4(sc, BGE_TLP_CONTROL_REG + BGE_TLP_PHYCTL5, 2294 reg | BGE_TLP_PHYCTL5_DIS_L2CLKREQ); 2295 2296 /* Restore */ 2297 CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl); 2298 } 2299 if (BGE_CHIPREV(sc->bge_chipid) != BGE_CHIPREV_57765_AX) { 2300 reg = CSR_READ_4(sc, BGE_CPMU_PADRNG_CTL); 2301 CSR_WRITE_4(sc, BGE_CPMU_PADRNG_CTL, 2302 reg | BGE_CPMU_PADRNG_CTL_RDIV2); 2303 2304 /* Save */ 2305 mode_ctl = CSR_READ_4(sc, BGE_MODE_CTL); 2306 2307 /* Temporary modify MODE_CTL to control TLP */ 2308 reg = mode_ctl & ~BGE_MODECTL_PCIE_TLPADDRMASK; 2309 CSR_WRITE_4(sc, BGE_MODE_CTL, 2310 reg | BGE_MODECTL_PCIE_TLPADDR0); 2311 2312 /* Control TLP */ 2313 reg = CSR_READ_4(sc, BGE_TLP_CONTROL_REG + 2314 BGE_TLP_FTSMAX); 2315 reg &= ~BGE_TLP_FTSMAX_MSK; 2316 CSR_WRITE_4(sc, BGE_TLP_CONTROL_REG + BGE_TLP_FTSMAX, 2317 reg | BGE_TLP_FTSMAX_VAL); 2318 2319 /* Restore */ 2320 CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl); 2321 } 2322 2323 reg = CSR_READ_4(sc, BGE_CPMU_LSPD_10MB_CLK); 2324 reg &= ~BGE_CPMU_LSPD_10MB_MACCLK_MASK; 2325 reg |= BGE_CPMU_LSPD_10MB_MACCLK_6_25; 2326 CSR_WRITE_4(sc, BGE_CPMU_LSPD_10MB_CLK, reg); 2327 } 2328 2329 /* Set up the PCI DMA control register. */ 2330 dma_rw_ctl = BGE_PCI_READ_CMD | BGE_PCI_WRITE_CMD; 2331 if (sc->bge_flags & BGE_PCIE) { 2332 /* Read watermark not used, 128 bytes for write. */ 2333 DPRINTFN(4, ("(%s: PCI-Express DMA setting)\n", 2334 device_xname(sc->bge_dev))); 2335 dma_rw_ctl |= BGE_PCIDMARWCTL_WR_WAT_SHIFT(3); 2336 } else if (sc->bge_flags & BGE_PCIX) { 2337 DPRINTFN(4, ("(:%s: PCI-X DMA setting)\n", 2338 device_xname(sc->bge_dev))); 2339 /* PCI-X bus */ 2340 if (BGE_IS_5714_FAMILY(sc)) { 2341 /* 256 bytes for read and write. */ 2342 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(2) | 2343 BGE_PCIDMARWCTL_WR_WAT_SHIFT(2); 2344 2345 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5780) 2346 dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL; 2347 else 2348 dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE_LOCAL; 2349 } else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) { 2350 /* 1536 bytes for read, 384 bytes for write. */ 2351 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(7) | 2352 BGE_PCIDMARWCTL_WR_WAT_SHIFT(3); 2353 } else { 2354 /* 384 bytes for read and write. */ 2355 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(3) | 2356 BGE_PCIDMARWCTL_WR_WAT_SHIFT(3) | 2357 (0x0F); 2358 } 2359 2360 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5703 || 2361 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) { 2362 uint32_t tmp; 2363 2364 /* Set ONEDMA_ATONCE for hardware workaround. */ 2365 tmp = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 2366 BGE_PCI_CLKCTL) & 0x1f; 2367 if (tmp == 6 || tmp == 7) 2368 dma_rw_ctl |= 2369 BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL; 2370 2371 /* Set PCI-X DMA write workaround. */ 2372 dma_rw_ctl |= BGE_PCIDMARWCTL_ASRT_ALL_BE; 2373 } 2374 } else { 2375 /* Conventional PCI bus: 256 bytes for read and write. */ 2376 DPRINTFN(4, ("(%s: PCI 2.2 DMA setting)\n", 2377 device_xname(sc->bge_dev))); 2378 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(7) | 2379 BGE_PCIDMARWCTL_WR_WAT_SHIFT(7); 2380 2381 if (BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5705 && 2382 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5750) 2383 dma_rw_ctl |= 0x0F; 2384 } 2385 2386 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 2387 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5701) 2388 dma_rw_ctl |= BGE_PCIDMARWCTL_USE_MRM | 2389 BGE_PCIDMARWCTL_ASRT_ALL_BE; 2390 2391 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5703 || 2392 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) 2393 dma_rw_ctl &= ~BGE_PCIDMARWCTL_MINDMA; 2394 2395 if (BGE_IS_5717_PLUS(sc)) { 2396 dma_rw_ctl &= ~BGE_PCIDMARWCTL_DIS_CACHE_ALIGNMENT; 2397 if (sc->bge_chipid == BGE_CHIPID_BCM57765_A0) 2398 dma_rw_ctl &= ~BGE_PCIDMARWCTL_CRDRDR_RDMA_MRRS_MSK; 2399 2400 /* 2401 * Enable HW workaround for controllers that misinterpret 2402 * a status tag update and leave interrupts permanently 2403 * disabled. 2404 */ 2405 if (BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5717 && 2406 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM57765) 2407 dma_rw_ctl |= BGE_PCIDMARWCTL_TAGGED_STATUS_WA; 2408 } 2409 2410 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_DMA_RW_CTL, 2411 dma_rw_ctl); 2412 2413 /* 2414 * Set up general mode register. 2415 */ 2416 mode_ctl = BGE_DMA_SWAP_OPTIONS; 2417 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) { 2418 /* Retain Host-2-BMC settings written by APE firmware. */ 2419 mode_ctl |= CSR_READ_4(sc, BGE_MODE_CTL) & 2420 (BGE_MODECTL_BYTESWAP_B2HRX_DATA | 2421 BGE_MODECTL_WORDSWAP_B2HRX_DATA | 2422 BGE_MODECTL_B2HRX_ENABLE | BGE_MODECTL_HTX2B_ENABLE); 2423 } 2424 mode_ctl |= BGE_MODECTL_MAC_ATTN_INTR | BGE_MODECTL_HOST_SEND_BDS | 2425 BGE_MODECTL_TX_NO_PHDR_CSUM; 2426 2427 /* 2428 * BCM5701 B5 have a bug causing data corruption when using 2429 * 64-bit DMA reads, which can be terminated early and then 2430 * completed later as 32-bit accesses, in combination with 2431 * certain bridges. 2432 */ 2433 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5701 && 2434 sc->bge_chipid == BGE_CHIPID_BCM5701_B5) 2435 mode_ctl |= BGE_MODECTL_FORCE_PCI32; 2436 2437 /* 2438 * Tell the firmware the driver is running 2439 */ 2440 if (sc->bge_asf_mode & ASF_STACKUP) 2441 mode_ctl |= BGE_MODECTL_STACKUP; 2442 2443 CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl); 2444 2445 /* 2446 * Disable memory write invalidate. Apparently it is not supported 2447 * properly by these devices. 2448 */ 2449 PCI_CLRBIT(sc->sc_pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG, 2450 PCI_COMMAND_INVALIDATE_ENABLE); 2451 2452 #ifdef __brokenalpha__ 2453 /* 2454 * Must insure that we do not cross an 8K (bytes) boundary 2455 * for DMA reads. Our highest limit is 1K bytes. This is a 2456 * restriction on some ALPHA platforms with early revision 2457 * 21174 PCI chipsets, such as the AlphaPC 164lx 2458 */ 2459 PCI_SETBIT(sc, BGE_PCI_DMA_RW_CTL, BGE_PCI_READ_BNDRY_1024, 4); 2460 #endif 2461 2462 /* Set the timer prescaler (always 66MHz) */ 2463 CSR_WRITE_4(sc, BGE_MISC_CFG, BGE_32BITTIME_66MHZ); 2464 2465 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 2466 DELAY(40); /* XXX */ 2467 2468 /* Put PHY into ready state */ 2469 BGE_CLRBIT_FLUSH(sc, BGE_MISC_CFG, BGE_MISCCFG_EPHY_IDDQ); 2470 DELAY(40); 2471 } 2472 2473 return 0; 2474 } 2475 2476 static int 2477 bge_blockinit(struct bge_softc *sc) 2478 { 2479 volatile struct bge_rcb *rcb; 2480 bus_size_t rcb_addr; 2481 int i; 2482 struct ifnet *ifp = &sc->ethercom.ec_if; 2483 bge_hostaddr taddr; 2484 uint32_t dmactl, val; 2485 2486 /* 2487 * Initialize the memory window pointer register so that 2488 * we can access the first 32K of internal NIC RAM. This will 2489 * allow us to set up the TX send ring RCBs and the RX return 2490 * ring RCBs, plus other things which live in NIC memory. 2491 */ 2492 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_BASEADDR, 0); 2493 2494 /* Step 33: Configure mbuf memory pool */ 2495 if (!BGE_IS_5705_PLUS(sc)) { 2496 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, 2497 BGE_BUFFPOOL_1); 2498 2499 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) 2500 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000); 2501 else 2502 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000); 2503 2504 /* Configure DMA resource pool */ 2505 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_BASEADDR, 2506 BGE_DMA_DESCRIPTORS); 2507 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LEN, 0x2000); 2508 } 2509 2510 /* Step 35: Configure mbuf pool watermarks */ 2511 #ifdef ORIG_WPAUL_VALUES 2512 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 24); 2513 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 24); 2514 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 48); 2515 #else 2516 2517 /* new broadcom docs strongly recommend these: */ 2518 if (BGE_IS_5717_PLUS(sc)) { 2519 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0); 2520 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x2a); 2521 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0xa0); 2522 } else if (BGE_IS_5705_PLUS(sc)) { 2523 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0); 2524 2525 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 2526 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x04); 2527 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x10); 2528 } else { 2529 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x10); 2530 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60); 2531 } 2532 } else { 2533 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x50); 2534 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x20); 2535 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60); 2536 } 2537 #endif 2538 2539 /* Step 36: Configure DMA resource watermarks */ 2540 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5); 2541 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10); 2542 2543 /* Step 38: Enable buffer manager */ 2544 val = BGE_BMANMODE_ENABLE | BGE_BMANMODE_ATTN; 2545 /* 2546 * Change the arbitration algorithm of TXMBUF read request to 2547 * round-robin instead of priority based for BCM5719. When 2548 * TXFIFO is almost empty, RDMA will hold its request until 2549 * TXFIFO is not almost empty. 2550 */ 2551 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719) 2552 val |= BGE_BMANMODE_NO_TX_UNDERRUN; 2553 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5717 || 2554 sc->bge_chipid == BGE_CHIPID_BCM5719_A0 || 2555 sc->bge_chipid == BGE_CHIPID_BCM5720_A0) 2556 val |= BGE_BMANMODE_LOMBUF_ATTN; 2557 CSR_WRITE_4(sc, BGE_BMAN_MODE, val); 2558 2559 /* Step 39: Poll for buffer manager start indication */ 2560 for (i = 0; i < BGE_TIMEOUT * 2; i++) { 2561 DELAY(10); 2562 if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE) 2563 break; 2564 } 2565 2566 if (i == BGE_TIMEOUT * 2) { 2567 aprint_error_dev(sc->bge_dev, 2568 "buffer manager failed to start\n"); 2569 return ENXIO; 2570 } 2571 2572 /* Step 40: Enable flow-through queues */ 2573 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 2574 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 2575 2576 /* Wait until queue initialization is complete */ 2577 for (i = 0; i < BGE_TIMEOUT * 2; i++) { 2578 if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0) 2579 break; 2580 DELAY(10); 2581 } 2582 2583 if (i == BGE_TIMEOUT * 2) { 2584 aprint_error_dev(sc->bge_dev, 2585 "flow-through queue init failed\n"); 2586 return ENXIO; 2587 } 2588 2589 /* Step 41: Initialize the standard RX ring control block */ 2590 rcb = &sc->bge_rdata->bge_info.bge_std_rx_rcb; 2591 BGE_HOSTADDR(rcb->bge_hostaddr, BGE_RING_DMA_ADDR(sc, bge_rx_std_ring)); 2592 if (BGE_IS_5717_PLUS(sc)) 2593 rcb->bge_maxlen_flags = 2594 BGE_RCB_MAXLEN_FLAGS(512, BGE_MAX_FRAMELEN << 2); 2595 else if (BGE_IS_5705_PLUS(sc)) 2596 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(512, 0); 2597 else 2598 rcb->bge_maxlen_flags = 2599 BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 0); 2600 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5717 || 2601 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719 || 2602 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) 2603 rcb->bge_nicaddr = BGE_STD_RX_RINGS_5717; 2604 else 2605 rcb->bge_nicaddr = BGE_STD_RX_RINGS; 2606 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcb->bge_hostaddr.bge_addr_hi); 2607 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcb->bge_hostaddr.bge_addr_lo); 2608 CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 2609 CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcb->bge_nicaddr); 2610 2611 /* 2612 * Step 42: Initialize the jumbo RX ring control block 2613 * We set the 'ring disabled' bit in the flags 2614 * field until we're actually ready to start 2615 * using this ring (i.e. once we set the MTU 2616 * high enough to require it). 2617 */ 2618 if (BGE_IS_JUMBO_CAPABLE(sc)) { 2619 rcb = &sc->bge_rdata->bge_info.bge_jumbo_rx_rcb; 2620 BGE_HOSTADDR(rcb->bge_hostaddr, 2621 BGE_RING_DMA_ADDR(sc, bge_rx_jumbo_ring)); 2622 rcb->bge_maxlen_flags = 2623 BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 2624 BGE_RCB_FLAG_RING_DISABLED); 2625 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5717 || 2626 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719 || 2627 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) 2628 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS_5717; 2629 else 2630 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS; 2631 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI, 2632 rcb->bge_hostaddr.bge_addr_hi); 2633 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO, 2634 rcb->bge_hostaddr.bge_addr_lo); 2635 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, 2636 rcb->bge_maxlen_flags); 2637 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcb->bge_nicaddr); 2638 /* Reset the jumbo receive producer ring producer index. */ 2639 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0); 2640 } 2641 2642 /* Disable the mini receive producer ring RCB. */ 2643 if (BGE_IS_5700_FAMILY(sc)) { 2644 /* Set up dummy disabled mini ring RCB */ 2645 rcb = &sc->bge_rdata->bge_info.bge_mini_rx_rcb; 2646 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0, 2647 BGE_RCB_FLAG_RING_DISABLED); 2648 CSR_WRITE_4(sc, BGE_RX_MINI_RCB_MAXLEN_FLAGS, 2649 rcb->bge_maxlen_flags); 2650 /* Reset the mini receive producer ring producer index. */ 2651 bge_writembx(sc, BGE_MBX_RX_MINI_PROD_LO, 0); 2652 2653 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 2654 offsetof(struct bge_ring_data, bge_info), 2655 sizeof (struct bge_gib), 2656 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2657 } 2658 2659 /* Choose de-pipeline mode for BCM5906 A0, A1 and A2. */ 2660 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 2661 if (sc->bge_chipid == BGE_CHIPID_BCM5906_A0 || 2662 sc->bge_chipid == BGE_CHIPID_BCM5906_A1 || 2663 sc->bge_chipid == BGE_CHIPID_BCM5906_A2) 2664 CSR_WRITE_4(sc, BGE_ISO_PKT_TX, 2665 (CSR_READ_4(sc, BGE_ISO_PKT_TX) & ~3) | 2); 2666 } 2667 /* 2668 * Set the BD ring replenish thresholds. The recommended 2669 * values are 1/8th the number of descriptors allocated to 2670 * each ring. 2671 */ 2672 i = BGE_STD_RX_RING_CNT / 8; 2673 2674 /* 2675 * Use a value of 8 for the following chips to workaround HW errata. 2676 * Some of these chips have been added based on empirical 2677 * evidence (they don't work unless this is done). 2678 */ 2679 if (BGE_IS_5705_PLUS(sc)) 2680 i = 8; 2681 2682 CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, i); 2683 CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH, BGE_JUMBO_RX_RING_CNT / 8); 2684 2685 if (BGE_IS_5717_PLUS(sc)) { 2686 CSR_WRITE_4(sc, BGE_STD_REPL_LWM, 4); 2687 CSR_WRITE_4(sc, BGE_JUMBO_REPL_LWM, 4); 2688 } 2689 2690 /* 2691 * Disable all unused send rings by setting the 'ring disabled' 2692 * bit in the flags field of all the TX send ring control blocks. 2693 * These are located in NIC memory. 2694 */ 2695 rcb_addr = BGE_MEMWIN_START + BGE_SEND_RING_RCB; 2696 for (i = 0; i < BGE_TX_RINGS_EXTSSRAM_MAX; i++) { 2697 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 2698 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED)); 2699 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 0); 2700 rcb_addr += sizeof(struct bge_rcb); 2701 } 2702 2703 /* Configure TX RCB 0 (we use only the first ring) */ 2704 rcb_addr = BGE_MEMWIN_START + BGE_SEND_RING_RCB; 2705 BGE_HOSTADDR(taddr, BGE_RING_DMA_ADDR(sc, bge_tx_ring)); 2706 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi); 2707 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo); 2708 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5717 || 2709 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719 || 2710 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) 2711 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, BGE_SEND_RING_5717); 2712 else 2713 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 2714 BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT)); 2715 if (BGE_IS_5700_FAMILY(sc)) 2716 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 2717 BGE_RCB_MAXLEN_FLAGS(BGE_TX_RING_CNT, 0)); 2718 2719 /* Disable all unused RX return rings */ 2720 rcb_addr = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB; 2721 for (i = 0; i < BGE_RX_RINGS_MAX; i++) { 2722 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_hi, 0); 2723 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_lo, 0); 2724 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 2725 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 2726 BGE_RCB_FLAG_RING_DISABLED)); 2727 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 0); 2728 bge_writembx(sc, BGE_MBX_RX_CONS0_LO + 2729 (i * (sizeof(uint64_t))), 0); 2730 rcb_addr += sizeof(struct bge_rcb); 2731 } 2732 2733 /* 2734 * Set up RX return ring 0 2735 * Note that the NIC address for RX return rings is 0x00000000. 2736 * The return rings live entirely within the host, so the 2737 * nicaddr field in the RCB isn't used. 2738 */ 2739 rcb_addr = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB; 2740 BGE_HOSTADDR(taddr, BGE_RING_DMA_ADDR(sc, bge_rx_return_ring)); 2741 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi); 2742 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo); 2743 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 0x00000000); 2744 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 2745 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 0)); 2746 2747 /* Set random backoff seed for TX */ 2748 CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF, 2749 CLLADDR(ifp->if_sadl)[0] + CLLADDR(ifp->if_sadl)[1] + 2750 CLLADDR(ifp->if_sadl)[2] + CLLADDR(ifp->if_sadl)[3] + 2751 CLLADDR(ifp->if_sadl)[4] + CLLADDR(ifp->if_sadl)[5] + 2752 BGE_TX_BACKOFF_SEED_MASK); 2753 2754 /* Set inter-packet gap */ 2755 val = 0x2620; 2756 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) 2757 val |= CSR_READ_4(sc, BGE_TX_LENGTHS) & 2758 (BGE_TXLEN_JMB_FRM_LEN_MSK | BGE_TXLEN_CNT_DN_VAL_MSK); 2759 CSR_WRITE_4(sc, BGE_TX_LENGTHS, val); 2760 2761 /* 2762 * Specify which ring to use for packets that don't match 2763 * any RX rules. 2764 */ 2765 CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08); 2766 2767 /* 2768 * Configure number of RX lists. One interrupt distribution 2769 * list, sixteen active lists, one bad frames class. 2770 */ 2771 CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181); 2772 2773 /* Inialize RX list placement stats mask. */ 2774 CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF); 2775 CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1); 2776 2777 /* Disable host coalescing until we get it set up */ 2778 CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000); 2779 2780 /* Poll to make sure it's shut down. */ 2781 for (i = 0; i < BGE_TIMEOUT * 2; i++) { 2782 DELAY(10); 2783 if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE)) 2784 break; 2785 } 2786 2787 if (i == BGE_TIMEOUT * 2) { 2788 aprint_error_dev(sc->bge_dev, 2789 "host coalescing engine failed to idle\n"); 2790 return ENXIO; 2791 } 2792 2793 /* Set up host coalescing defaults */ 2794 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bge_rx_coal_ticks); 2795 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bge_tx_coal_ticks); 2796 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bge_rx_max_coal_bds); 2797 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bge_tx_max_coal_bds); 2798 if (!(BGE_IS_5705_PLUS(sc))) { 2799 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT, 0); 2800 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT, 0); 2801 } 2802 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 0); 2803 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 0); 2804 2805 /* Set up address of statistics block */ 2806 if (BGE_IS_5700_FAMILY(sc)) { 2807 BGE_HOSTADDR(taddr, BGE_RING_DMA_ADDR(sc, bge_info.bge_stats)); 2808 CSR_WRITE_4(sc, BGE_HCC_STATS_TICKS, sc->bge_stat_ticks); 2809 CSR_WRITE_4(sc, BGE_HCC_STATS_BASEADDR, BGE_STATS_BLOCK); 2810 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_HI, taddr.bge_addr_hi); 2811 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_LO, taddr.bge_addr_lo); 2812 } 2813 2814 /* Set up address of status block */ 2815 BGE_HOSTADDR(taddr, BGE_RING_DMA_ADDR(sc, bge_status_block)); 2816 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_BASEADDR, BGE_STATUS_BLOCK); 2817 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI, taddr.bge_addr_hi); 2818 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO, taddr.bge_addr_lo); 2819 sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx = 0; 2820 sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx = 0; 2821 2822 /* Set up status block size. */ 2823 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 && 2824 sc->bge_chipid != BGE_CHIPID_BCM5700_C0) { 2825 val = BGE_STATBLKSZ_FULL; 2826 bzero(&sc->bge_rdata->bge_status_block, BGE_STATUS_BLK_SZ); 2827 } else { 2828 val = BGE_STATBLKSZ_32BYTE; 2829 bzero(&sc->bge_rdata->bge_status_block, 32); 2830 } 2831 2832 /* Turn on host coalescing state machine */ 2833 CSR_WRITE_4(sc, BGE_HCC_MODE, val | BGE_HCCMODE_ENABLE); 2834 2835 /* Turn on RX BD completion state machine and enable attentions */ 2836 CSR_WRITE_4(sc, BGE_RBDC_MODE, 2837 BGE_RBDCMODE_ENABLE | BGE_RBDCMODE_ATTN); 2838 2839 /* Turn on RX list placement state machine */ 2840 CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 2841 2842 /* Turn on RX list selector state machine. */ 2843 if (!(BGE_IS_5705_PLUS(sc))) 2844 CSR_WRITE_4(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 2845 2846 val = BGE_MACMODE_TXDMA_ENB | BGE_MACMODE_RXDMA_ENB | 2847 BGE_MACMODE_RX_STATS_CLEAR | BGE_MACMODE_TX_STATS_CLEAR | 2848 BGE_MACMODE_RX_STATS_ENB | BGE_MACMODE_TX_STATS_ENB | 2849 BGE_MACMODE_FRMHDR_DMA_ENB; 2850 2851 if (sc->bge_flags & BGE_PHY_FIBER_TBI) 2852 val |= BGE_PORTMODE_TBI; 2853 else if (sc->bge_flags & BGE_PHY_FIBER_MII) 2854 val |= BGE_PORTMODE_GMII; 2855 else 2856 val |= BGE_PORTMODE_MII; 2857 2858 /* Allow APE to send/receive frames. */ 2859 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) != 0) 2860 val |= BGE_MACMODE_APE_RX_EN | BGE_MACMODE_APE_TX_EN; 2861 2862 /* Turn on DMA, clear stats */ 2863 CSR_WRITE_4_FLUSH(sc, BGE_MAC_MODE, val); 2864 DELAY(40); 2865 2866 /* Set misc. local control, enable interrupts on attentions */ 2867 sc->bge_local_ctrl_reg = BGE_MLC_INTR_ONATTN | BGE_MLC_AUTO_EEPROM; 2868 2869 #ifdef notdef 2870 /* Assert GPIO pins for PHY reset */ 2871 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUT0| 2872 BGE_MLC_MISCIO_OUT1|BGE_MLC_MISCIO_OUT2); 2873 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUTEN0| 2874 BGE_MLC_MISCIO_OUTEN1|BGE_MLC_MISCIO_OUTEN2); 2875 #endif 2876 2877 #if defined(not_quite_yet) 2878 /* Linux driver enables enable gpio pin #1 on 5700s */ 2879 if (sc->bge_chipid == BGE_CHIPID_BCM5700) { 2880 sc->bge_local_ctrl_reg |= 2881 (BGE_MLC_MISCIO_OUT1|BGE_MLC_MISCIO_OUTEN1); 2882 } 2883 #endif 2884 CSR_WRITE_4(sc, BGE_MISC_LOCAL_CTL, sc->bge_local_ctrl_reg); 2885 2886 /* Turn on DMA completion state machine */ 2887 if (!(BGE_IS_5705_PLUS(sc))) 2888 CSR_WRITE_4(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 2889 2890 val = BGE_WDMAMODE_ENABLE | BGE_WDMAMODE_ALL_ATTNS; 2891 2892 /* Enable host coalescing bug fix. */ 2893 if (BGE_IS_5755_PLUS(sc)) 2894 val |= BGE_WDMAMODE_STATUS_TAG_FIX; 2895 2896 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785) 2897 val |= BGE_WDMAMODE_BURST_ALL_DATA; 2898 2899 /* Turn on write DMA state machine */ 2900 CSR_WRITE_4_FLUSH(sc, BGE_WDMA_MODE, val); 2901 DELAY(40); 2902 2903 val = BGE_RDMAMODE_ENABLE | BGE_RDMAMODE_ALL_ATTNS; 2904 2905 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5717) 2906 val |= BGE_RDMAMODE_MULT_DMA_RD_DIS; 2907 2908 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5784 || 2909 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785 || 2910 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57780) 2911 val |= BGE_RDMAMODE_BD_SBD_CRPT_ATTN | 2912 BGE_RDMAMODE_MBUF_RBD_CRPT_ATTN | 2913 BGE_RDMAMODE_MBUF_SBD_CRPT_ATTN; 2914 2915 if (sc->bge_flags & BGE_PCIE) 2916 val |= BGE_RDMAMODE_FIFO_LONG_BURST; 2917 if (sc->bge_flags & BGE_TSO) 2918 val |= BGE_RDMAMODE_TSO4_ENABLE; 2919 2920 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) { 2921 val |= CSR_READ_4(sc, BGE_RDMA_MODE) & 2922 BGE_RDMAMODE_H2BNC_VLAN_DET; 2923 /* 2924 * Allow multiple outstanding read requests from 2925 * non-LSO read DMA engine. 2926 */ 2927 val &= ~BGE_RDMAMODE_MULT_DMA_RD_DIS; 2928 } 2929 2930 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761 || 2931 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5784 || 2932 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785 || 2933 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57780 || 2934 BGE_IS_5717_PLUS(sc)) { /* XXX 57765? */ 2935 dmactl = CSR_READ_4(sc, BGE_RDMA_RSRVCTRL); 2936 /* 2937 * Adjust tx margin to prevent TX data corruption and 2938 * fix internal FIFO overflow. 2939 */ 2940 if (sc->bge_chipid == BGE_CHIPID_BCM5719_A0) { 2941 dmactl &= ~(BGE_RDMA_RSRVCTRL_FIFO_LWM_MASK | 2942 BGE_RDMA_RSRVCTRL_FIFO_HWM_MASK | 2943 BGE_RDMA_RSRVCTRL_TXMRGN_MASK); 2944 dmactl |= BGE_RDMA_RSRVCTRL_FIFO_LWM_1_5K | 2945 BGE_RDMA_RSRVCTRL_FIFO_HWM_1_5K | 2946 BGE_RDMA_RSRVCTRL_TXMRGN_320B; 2947 } 2948 /* 2949 * Enable fix for read DMA FIFO overruns. 2950 * The fix is to limit the number of RX BDs 2951 * the hardware would fetch at a fime. 2952 */ 2953 CSR_WRITE_4(sc, BGE_RDMA_RSRVCTRL, dmactl | 2954 BGE_RDMA_RSRVCTRL_FIFO_OFLW_FIX); 2955 } 2956 2957 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719) { 2958 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL, 2959 CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL) | 2960 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_4K | 2961 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K); 2962 } else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) { 2963 /* 2964 * Allow 4KB burst length reads for non-LSO frames. 2965 * Enable 512B burst length reads for buffer descriptors. 2966 */ 2967 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL, 2968 CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL) | 2969 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_512 | 2970 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K); 2971 } 2972 2973 /* Turn on read DMA state machine */ 2974 CSR_WRITE_4_FLUSH(sc, BGE_RDMA_MODE, val); 2975 delay(40); 2976 2977 /* Turn on RX data completion state machine */ 2978 CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 2979 2980 /* Turn on RX BD initiator state machine */ 2981 CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 2982 2983 /* Turn on RX data and RX BD initiator state machine */ 2984 CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE); 2985 2986 /* Turn on Mbuf cluster free state machine */ 2987 if (!BGE_IS_5705_PLUS(sc)) 2988 CSR_WRITE_4(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 2989 2990 /* Turn on send BD completion state machine */ 2991 CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 2992 2993 /* Turn on send data completion state machine */ 2994 val = BGE_SDCMODE_ENABLE; 2995 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761) 2996 val |= BGE_SDCMODE_CDELAY; 2997 CSR_WRITE_4(sc, BGE_SDC_MODE, val); 2998 2999 /* Turn on send data initiator state machine */ 3000 if (sc->bge_flags & BGE_TSO) { 3001 /* XXX: magic value from Linux driver */ 3002 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE | 0x08); 3003 } else 3004 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 3005 3006 /* Turn on send BD initiator state machine */ 3007 CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 3008 3009 /* Turn on send BD selector state machine */ 3010 CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 3011 3012 CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF); 3013 CSR_WRITE_4(sc, BGE_SDI_STATS_CTL, 3014 BGE_SDISTATSCTL_ENABLE | BGE_SDISTATSCTL_FASTER); 3015 3016 /* ack/clear link change events */ 3017 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED | 3018 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE | 3019 BGE_MACSTAT_LINK_CHANGED); 3020 CSR_WRITE_4(sc, BGE_MI_STS, 0); 3021 3022 /* 3023 * Enable attention when the link has changed state for 3024 * devices that use auto polling. 3025 */ 3026 if (sc->bge_flags & BGE_PHY_FIBER_TBI) { 3027 CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK); 3028 } else { 3029 BGE_STS_SETBIT(sc, BGE_STS_AUTOPOLL); 3030 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL | (10 << 16)); 3031 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700) 3032 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, 3033 BGE_EVTENB_MI_INTERRUPT); 3034 } 3035 3036 /* 3037 * Clear any pending link state attention. 3038 * Otherwise some link state change events may be lost until attention 3039 * is cleared by bge_intr() -> bge_link_upd() sequence. 3040 * It's not necessary on newer BCM chips - perhaps enabling link 3041 * state change attentions implies clearing pending attention. 3042 */ 3043 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED | 3044 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE | 3045 BGE_MACSTAT_LINK_CHANGED); 3046 3047 /* Enable link state change attentions. */ 3048 BGE_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED); 3049 3050 return 0; 3051 } 3052 3053 static const struct bge_revision * 3054 bge_lookup_rev(uint32_t chipid) 3055 { 3056 const struct bge_revision *br; 3057 3058 for (br = bge_revisions; br->br_name != NULL; br++) { 3059 if (br->br_chipid == chipid) 3060 return br; 3061 } 3062 3063 for (br = bge_majorrevs; br->br_name != NULL; br++) { 3064 if (br->br_chipid == BGE_ASICREV(chipid)) 3065 return br; 3066 } 3067 3068 return NULL; 3069 } 3070 3071 static const struct bge_product * 3072 bge_lookup(const struct pci_attach_args *pa) 3073 { 3074 const struct bge_product *bp; 3075 3076 for (bp = bge_products; bp->bp_name != NULL; bp++) { 3077 if (PCI_VENDOR(pa->pa_id) == bp->bp_vendor && 3078 PCI_PRODUCT(pa->pa_id) == bp->bp_product) 3079 return bp; 3080 } 3081 3082 return NULL; 3083 } 3084 3085 static uint32_t 3086 bge_chipid(const struct pci_attach_args *pa) 3087 { 3088 uint32_t id; 3089 3090 id = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_MISC_CTL) 3091 >> BGE_PCIMISCCTL_ASICREV_SHIFT; 3092 3093 if (BGE_ASICREV(id) == BGE_ASICREV_USE_PRODID_REG) { 3094 switch (PCI_PRODUCT(pa->pa_id)) { 3095 case PCI_PRODUCT_BROADCOM_BCM5717: 3096 case PCI_PRODUCT_BROADCOM_BCM5718: 3097 case PCI_PRODUCT_BROADCOM_BCM5719: 3098 case PCI_PRODUCT_BROADCOM_BCM5720: 3099 case PCI_PRODUCT_BROADCOM_BCM5724: /* ??? */ 3100 id = pci_conf_read(pa->pa_pc, pa->pa_tag, 3101 BGE_PCI_GEN2_PRODID_ASICREV); 3102 break; 3103 case PCI_PRODUCT_BROADCOM_BCM57761: 3104 case PCI_PRODUCT_BROADCOM_BCM57762: 3105 case PCI_PRODUCT_BROADCOM_BCM57765: 3106 case PCI_PRODUCT_BROADCOM_BCM57766: 3107 case PCI_PRODUCT_BROADCOM_BCM57781: 3108 case PCI_PRODUCT_BROADCOM_BCM57785: 3109 case PCI_PRODUCT_BROADCOM_BCM57791: 3110 case PCI_PRODUCT_BROADCOM_BCM57795: 3111 id = pci_conf_read(pa->pa_pc, pa->pa_tag, 3112 BGE_PCI_GEN15_PRODID_ASICREV); 3113 break; 3114 default: 3115 id = pci_conf_read(pa->pa_pc, pa->pa_tag, 3116 BGE_PCI_PRODID_ASICREV); 3117 break; 3118 } 3119 } 3120 3121 return id; 3122 } 3123 3124 /* 3125 * Probe for a Broadcom chip. Check the PCI vendor and device IDs 3126 * against our list and return its name if we find a match. Note 3127 * that since the Broadcom controller contains VPD support, we 3128 * can get the device name string from the controller itself instead 3129 * of the compiled-in string. This is a little slow, but it guarantees 3130 * we'll always announce the right product name. 3131 */ 3132 static int 3133 bge_probe(device_t parent, cfdata_t match, void *aux) 3134 { 3135 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 3136 3137 if (bge_lookup(pa) != NULL) 3138 return 1; 3139 3140 return 0; 3141 } 3142 3143 static void 3144 bge_attach(device_t parent, device_t self, void *aux) 3145 { 3146 struct bge_softc *sc = device_private(self); 3147 struct pci_attach_args *pa = aux; 3148 prop_dictionary_t dict; 3149 const struct bge_product *bp; 3150 const struct bge_revision *br; 3151 pci_chipset_tag_t pc; 3152 pci_intr_handle_t ih; 3153 const char *intrstr = NULL; 3154 bus_dma_segment_t seg; 3155 int rseg; 3156 uint32_t hwcfg = 0; 3157 uint32_t command; 3158 struct ifnet *ifp; 3159 uint32_t misccfg; 3160 void * kva; 3161 u_char eaddr[ETHER_ADDR_LEN]; 3162 pcireg_t memtype, subid, reg; 3163 bus_addr_t memaddr; 3164 bus_size_t memsize, apesize; 3165 uint32_t pm_ctl; 3166 bool no_seeprom; 3167 3168 bp = bge_lookup(pa); 3169 KASSERT(bp != NULL); 3170 3171 sc->sc_pc = pa->pa_pc; 3172 sc->sc_pcitag = pa->pa_tag; 3173 sc->bge_dev = self; 3174 3175 sc->bge_pa = *pa; 3176 pc = sc->sc_pc; 3177 subid = pci_conf_read(pc, sc->sc_pcitag, PCI_SUBSYS_ID_REG); 3178 3179 aprint_naive(": Ethernet controller\n"); 3180 aprint_normal(": %s\n", bp->bp_name); 3181 3182 /* 3183 * Map control/status registers. 3184 */ 3185 DPRINTFN(5, ("Map control/status regs\n")); 3186 command = pci_conf_read(pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG); 3187 command |= PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_MASTER_ENABLE; 3188 pci_conf_write(pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG, command); 3189 command = pci_conf_read(pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG); 3190 3191 if (!(command & PCI_COMMAND_MEM_ENABLE)) { 3192 aprint_error_dev(sc->bge_dev, 3193 "failed to enable memory mapping!\n"); 3194 return; 3195 } 3196 3197 DPRINTFN(5, ("pci_mem_find\n")); 3198 memtype = pci_mapreg_type(sc->sc_pc, sc->sc_pcitag, BGE_PCI_BAR0); 3199 switch (memtype) { 3200 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 3201 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 3202 if (pci_mapreg_map(pa, BGE_PCI_BAR0, 3203 memtype, 0, &sc->bge_btag, &sc->bge_bhandle, 3204 &memaddr, &memsize) == 0) 3205 break; 3206 default: 3207 aprint_error_dev(sc->bge_dev, "can't find mem space\n"); 3208 return; 3209 } 3210 3211 DPRINTFN(5, ("pci_intr_map\n")); 3212 if (pci_intr_map(pa, &ih)) { 3213 aprint_error_dev(sc->bge_dev, "couldn't map interrupt\n"); 3214 return; 3215 } 3216 3217 DPRINTFN(5, ("pci_intr_string\n")); 3218 intrstr = pci_intr_string(pc, ih); 3219 3220 DPRINTFN(5, ("pci_intr_establish\n")); 3221 sc->bge_intrhand = pci_intr_establish(pc, ih, IPL_NET, bge_intr, sc); 3222 3223 if (sc->bge_intrhand == NULL) { 3224 aprint_error_dev(sc->bge_dev, 3225 "couldn't establish interrupt%s%s\n", 3226 intrstr ? " at " : "", intrstr ? intrstr : ""); 3227 return; 3228 } 3229 aprint_normal_dev(sc->bge_dev, "interrupting at %s\n", intrstr); 3230 3231 /* Save various chip information. */ 3232 sc->bge_chipid = bge_chipid(pa); 3233 sc->bge_phy_addr = bge_phy_addr(sc); 3234 3235 if ((pci_get_capability(sc->sc_pc, sc->sc_pcitag, PCI_CAP_PCIEXPRESS, 3236 &sc->bge_pciecap, NULL) != 0) 3237 || (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785)) { 3238 /* PCIe */ 3239 sc->bge_flags |= BGE_PCIE; 3240 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719 || 3241 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) 3242 sc->bge_expmrq = 2048; 3243 else 3244 sc->bge_expmrq = 4096; 3245 bge_set_max_readrq(sc); 3246 } else if ((pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_PCISTATE) & 3247 BGE_PCISTATE_PCI_BUSMODE) == 0) { 3248 /* PCI-X */ 3249 sc->bge_flags |= BGE_PCIX; 3250 if (pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_PCIX, 3251 &sc->bge_pcixcap, NULL) == 0) 3252 aprint_error_dev(sc->bge_dev, 3253 "unable to find PCIX capability\n"); 3254 } 3255 3256 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX) { 3257 /* 3258 * Kludge for 5700 Bx bug: a hardware bug (PCIX byte enable?) 3259 * can clobber the chip's PCI config-space power control 3260 * registers, leaving the card in D3 powersave state. We do 3261 * not have memory-mapped registers in this state, so force 3262 * device into D0 state before starting initialization. 3263 */ 3264 pm_ctl = pci_conf_read(pc, sc->sc_pcitag, BGE_PCI_PWRMGMT_CMD); 3265 pm_ctl &= ~(PCI_PWR_D0|PCI_PWR_D1|PCI_PWR_D2|PCI_PWR_D3); 3266 pm_ctl |= (1 << 8) | PCI_PWR_D0 ; /* D0 state */ 3267 pci_conf_write(pc, sc->sc_pcitag, BGE_PCI_PWRMGMT_CMD, pm_ctl); 3268 DELAY(1000); /* 27 usec is allegedly sufficent */ 3269 } 3270 3271 /* Save chipset family. */ 3272 switch (BGE_ASICREV(sc->bge_chipid)) { 3273 case BGE_ASICREV_BCM57765: 3274 case BGE_ASICREV_BCM57766: 3275 sc->bge_flags |= BGE_57765_PLUS; 3276 /* FALLTHROUGH */ 3277 case BGE_ASICREV_BCM5717: 3278 case BGE_ASICREV_BCM5719: 3279 case BGE_ASICREV_BCM5720: 3280 sc->bge_flags |= BGE_5717_PLUS | BGE_5755_PLUS | BGE_575X_PLUS | 3281 BGE_5705_PLUS; 3282 break; 3283 case BGE_ASICREV_BCM5755: 3284 case BGE_ASICREV_BCM5761: 3285 case BGE_ASICREV_BCM5784: 3286 case BGE_ASICREV_BCM5785: 3287 case BGE_ASICREV_BCM5787: 3288 case BGE_ASICREV_BCM57780: 3289 sc->bge_flags |= BGE_5755_PLUS | BGE_575X_PLUS | BGE_5705_PLUS; 3290 break; 3291 case BGE_ASICREV_BCM5700: 3292 case BGE_ASICREV_BCM5701: 3293 case BGE_ASICREV_BCM5703: 3294 case BGE_ASICREV_BCM5704: 3295 sc->bge_flags |= BGE_5700_FAMILY | BGE_JUMBO_CAPABLE; 3296 break; 3297 case BGE_ASICREV_BCM5714_A0: 3298 case BGE_ASICREV_BCM5780: 3299 case BGE_ASICREV_BCM5714: 3300 sc->bge_flags |= BGE_5714_FAMILY; 3301 /* FALLTHROUGH */ 3302 case BGE_ASICREV_BCM5750: 3303 case BGE_ASICREV_BCM5752: 3304 case BGE_ASICREV_BCM5906: 3305 sc->bge_flags |= BGE_575X_PLUS; 3306 /* FALLTHROUGH */ 3307 case BGE_ASICREV_BCM5705: 3308 sc->bge_flags |= BGE_5705_PLUS; 3309 break; 3310 } 3311 3312 /* Identify chips with APE processor. */ 3313 switch (BGE_ASICREV(sc->bge_chipid)) { 3314 case BGE_ASICREV_BCM5717: 3315 case BGE_ASICREV_BCM5719: 3316 case BGE_ASICREV_BCM5720: 3317 case BGE_ASICREV_BCM5761: 3318 sc->bge_flags |= BGE_APE; 3319 break; 3320 } 3321 3322 /* Chips with APE need BAR2 access for APE registers/memory. */ 3323 if ((sc->bge_flags & BGE_APE) != 0) { 3324 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, BGE_PCI_BAR2); 3325 if (pci_mapreg_map(pa, BGE_PCI_BAR2, memtype, 0, 3326 &sc->bge_apetag, &sc->bge_apehandle, NULL, &apesize)) { 3327 aprint_error_dev(sc->bge_dev, 3328 "couldn't map BAR2 memory\n"); 3329 return; 3330 } 3331 3332 /* Enable APE register/memory access by host driver. */ 3333 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_PCISTATE); 3334 reg |= BGE_PCISTATE_ALLOW_APE_CTLSPC_WR | 3335 BGE_PCISTATE_ALLOW_APE_SHMEM_WR | 3336 BGE_PCISTATE_ALLOW_APE_PSPACE_WR; 3337 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_PCISTATE, reg); 3338 3339 bge_ape_lock_init(sc); 3340 bge_ape_read_fw_ver(sc); 3341 } 3342 3343 /* Identify the chips that use an CPMU. */ 3344 if (BGE_IS_5717_PLUS(sc) || 3345 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5784 || 3346 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761 || 3347 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785 || 3348 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57780) 3349 sc->bge_flags |= BGE_CPMU_PRESENT; 3350 3351 if ((sc->bge_flags & BGE_CPMU_PRESENT) != 0) 3352 CSR_WRITE_4(sc, BGE_MI_MODE, BGE_MIMODE_500KHZ_CONST); 3353 else 3354 CSR_WRITE_4(sc, BGE_MI_MODE, BGE_MIMODE_BASE); 3355 3356 /* 3357 * When using the BCM5701 in PCI-X mode, data corruption has 3358 * been observed in the first few bytes of some received packets. 3359 * Aligning the packet buffer in memory eliminates the corruption. 3360 * Unfortunately, this misaligns the packet payloads. On platforms 3361 * which do not support unaligned accesses, we will realign the 3362 * payloads by copying the received packets. 3363 */ 3364 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5701 && 3365 sc->bge_flags & BGE_PCIX) 3366 sc->bge_flags |= BGE_RX_ALIGNBUG; 3367 3368 if (BGE_IS_5700_FAMILY(sc)) 3369 sc->bge_flags |= BGE_JUMBO_CAPABLE; 3370 3371 if ((BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 3372 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5701) && 3373 PCI_VENDOR(subid) == PCI_VENDOR_DELL) 3374 sc->bge_flags |= BGE_NO_3LED; 3375 3376 misccfg = CSR_READ_4(sc, BGE_MISC_CFG); 3377 misccfg &= BGE_MISCCFG_BOARD_ID_MASK; 3378 3379 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5705 && 3380 (misccfg == BGE_MISCCFG_BOARD_ID_5788 || 3381 misccfg == BGE_MISCCFG_BOARD_ID_5788M)) 3382 sc->bge_flags |= BGE_IS_5788; 3383 3384 /* 3385 * Some controllers seem to require a special firmware to use 3386 * TSO. But the firmware is not available to FreeBSD and Linux 3387 * claims that the TSO performed by the firmware is slower than 3388 * hardware based TSO. Moreover the firmware based TSO has one 3389 * known bug which can't handle TSO if ethernet header + IP/TCP 3390 * header is greater than 80 bytes. The workaround for the TSO 3391 * bug exist but it seems it's too expensive than not using 3392 * TSO at all. Some hardwares also have the TSO bug so limit 3393 * the TSO to the controllers that are not affected TSO issues 3394 * (e.g. 5755 or higher). 3395 */ 3396 if (BGE_IS_5755_PLUS(sc)) { 3397 /* 3398 * BCM5754 and BCM5787 shares the same ASIC id so 3399 * explicit device id check is required. 3400 */ 3401 if ((PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_BROADCOM_BCM5754) && 3402 (PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_BROADCOM_BCM5754M)) 3403 sc->bge_flags |= BGE_TSO; 3404 } 3405 3406 if ((BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5703 && 3407 (misccfg == 0x4000 || misccfg == 0x8000)) || 3408 (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5705 && 3409 PCI_VENDOR(pa->pa_id) == PCI_VENDOR_BROADCOM && 3410 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5901 || 3411 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5901A2 || 3412 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5705F)) || 3413 (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_BROADCOM && 3414 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5751F || 3415 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5753F || 3416 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5787F)) || 3417 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM57790 || 3418 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM57791 || 3419 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM57795 || 3420 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 3421 sc->bge_flags |= BGE_10_100_ONLY; 3422 3423 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 3424 (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5705 && 3425 (sc->bge_chipid != BGE_CHIPID_BCM5705_A0 && 3426 sc->bge_chipid != BGE_CHIPID_BCM5705_A1)) || 3427 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 3428 sc->bge_flags |= BGE_NO_ETH_WIRE_SPEED; 3429 3430 if (sc->bge_chipid == BGE_CHIPID_BCM5701_A0 || 3431 sc->bge_chipid == BGE_CHIPID_BCM5701_B0) 3432 sc->bge_flags |= BGE_PHY_CRC_BUG; 3433 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5703_AX || 3434 BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5704_AX) 3435 sc->bge_flags |= BGE_PHY_ADC_BUG; 3436 if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0) 3437 sc->bge_flags |= BGE_PHY_5704_A0_BUG; 3438 3439 if (BGE_IS_5705_PLUS(sc) && 3440 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5906 && 3441 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5785 && 3442 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM57780 && 3443 !BGE_IS_5717_PLUS(sc)) { 3444 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5755 || 3445 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761 || 3446 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5784 || 3447 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5787) { 3448 if (PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_BROADCOM_BCM5722 && 3449 PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_BROADCOM_BCM5756) 3450 sc->bge_flags |= BGE_PHY_JITTER_BUG; 3451 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5755M) 3452 sc->bge_flags |= BGE_PHY_ADJUST_TRIM; 3453 } else 3454 sc->bge_flags |= BGE_PHY_BER_BUG; 3455 } 3456 3457 /* 3458 * SEEPROM check. 3459 * First check if firmware knows we do not have SEEPROM. 3460 */ 3461 if (prop_dictionary_get_bool(device_properties(self), 3462 "without-seeprom", &no_seeprom) && no_seeprom) 3463 sc->bge_flags |= BGE_NO_EEPROM; 3464 3465 /* Now check the 'ROM failed' bit on the RX CPU */ 3466 else if (CSR_READ_4(sc, BGE_RXCPU_MODE) & BGE_RXCPUMODE_ROMFAIL) 3467 sc->bge_flags |= BGE_NO_EEPROM; 3468 3469 sc->bge_asf_mode = 0; 3470 /* No ASF if APE present. */ 3471 if ((sc->bge_flags & BGE_APE) == 0) { 3472 if (bge_allow_asf && (bge_readmem_ind(sc, BGE_SRAM_DATA_SIG) == 3473 BGE_SRAM_DATA_SIG_MAGIC)) { 3474 if (bge_readmem_ind(sc, BGE_SRAM_DATA_CFG) & 3475 BGE_HWCFG_ASF) { 3476 sc->bge_asf_mode |= ASF_ENABLE; 3477 sc->bge_asf_mode |= ASF_STACKUP; 3478 if (BGE_IS_575X_PLUS(sc)) 3479 sc->bge_asf_mode |= ASF_NEW_HANDSHAKE; 3480 } 3481 } 3482 } 3483 3484 bge_stop_fw(sc); 3485 bge_sig_pre_reset(sc, BGE_RESET_START); 3486 if (bge_reset(sc)) 3487 aprint_error_dev(sc->bge_dev, "chip reset failed\n"); 3488 3489 bge_sig_legacy(sc, BGE_RESET_START); 3490 bge_sig_post_reset(sc, BGE_RESET_START); 3491 3492 if (bge_chipinit(sc)) { 3493 aprint_error_dev(sc->bge_dev, "chip initialization failed\n"); 3494 bge_release_resources(sc); 3495 return; 3496 } 3497 3498 /* 3499 * Get station address from the EEPROM. 3500 */ 3501 if (bge_get_eaddr(sc, eaddr)) { 3502 aprint_error_dev(sc->bge_dev, 3503 "failed to read station address\n"); 3504 bge_release_resources(sc); 3505 return; 3506 } 3507 3508 br = bge_lookup_rev(sc->bge_chipid); 3509 3510 if (br == NULL) { 3511 aprint_normal_dev(sc->bge_dev, "unknown ASIC (0x%x)", 3512 sc->bge_chipid); 3513 } else { 3514 aprint_normal_dev(sc->bge_dev, "ASIC %s (0x%x)", 3515 br->br_name, sc->bge_chipid); 3516 } 3517 aprint_normal(", Ethernet address %s\n", ether_sprintf(eaddr)); 3518 3519 /* Allocate the general information block and ring buffers. */ 3520 if (pci_dma64_available(pa)) 3521 sc->bge_dmatag = pa->pa_dmat64; 3522 else 3523 sc->bge_dmatag = pa->pa_dmat; 3524 DPRINTFN(5, ("bus_dmamem_alloc\n")); 3525 if (bus_dmamem_alloc(sc->bge_dmatag, sizeof(struct bge_ring_data), 3526 PAGE_SIZE, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 3527 aprint_error_dev(sc->bge_dev, "can't alloc rx buffers\n"); 3528 return; 3529 } 3530 DPRINTFN(5, ("bus_dmamem_map\n")); 3531 if (bus_dmamem_map(sc->bge_dmatag, &seg, rseg, 3532 sizeof(struct bge_ring_data), &kva, 3533 BUS_DMA_NOWAIT)) { 3534 aprint_error_dev(sc->bge_dev, 3535 "can't map DMA buffers (%zu bytes)\n", 3536 sizeof(struct bge_ring_data)); 3537 bus_dmamem_free(sc->bge_dmatag, &seg, rseg); 3538 return; 3539 } 3540 DPRINTFN(5, ("bus_dmamem_create\n")); 3541 if (bus_dmamap_create(sc->bge_dmatag, sizeof(struct bge_ring_data), 1, 3542 sizeof(struct bge_ring_data), 0, 3543 BUS_DMA_NOWAIT, &sc->bge_ring_map)) { 3544 aprint_error_dev(sc->bge_dev, "can't create DMA map\n"); 3545 bus_dmamem_unmap(sc->bge_dmatag, kva, 3546 sizeof(struct bge_ring_data)); 3547 bus_dmamem_free(sc->bge_dmatag, &seg, rseg); 3548 return; 3549 } 3550 DPRINTFN(5, ("bus_dmamem_load\n")); 3551 if (bus_dmamap_load(sc->bge_dmatag, sc->bge_ring_map, kva, 3552 sizeof(struct bge_ring_data), NULL, 3553 BUS_DMA_NOWAIT)) { 3554 bus_dmamap_destroy(sc->bge_dmatag, sc->bge_ring_map); 3555 bus_dmamem_unmap(sc->bge_dmatag, kva, 3556 sizeof(struct bge_ring_data)); 3557 bus_dmamem_free(sc->bge_dmatag, &seg, rseg); 3558 return; 3559 } 3560 3561 DPRINTFN(5, ("bzero\n")); 3562 sc->bge_rdata = (struct bge_ring_data *)kva; 3563 3564 memset(sc->bge_rdata, 0, sizeof(struct bge_ring_data)); 3565 3566 /* Try to allocate memory for jumbo buffers. */ 3567 if (BGE_IS_JUMBO_CAPABLE(sc)) { 3568 if (bge_alloc_jumbo_mem(sc)) { 3569 aprint_error_dev(sc->bge_dev, 3570 "jumbo buffer allocation failed\n"); 3571 } else 3572 sc->ethercom.ec_capabilities |= ETHERCAP_JUMBO_MTU; 3573 } 3574 3575 /* Set default tuneable values. */ 3576 sc->bge_stat_ticks = BGE_TICKS_PER_SEC; 3577 sc->bge_rx_coal_ticks = 150; 3578 sc->bge_rx_max_coal_bds = 64; 3579 #ifdef ORIG_WPAUL_VALUES 3580 sc->bge_tx_coal_ticks = 150; 3581 sc->bge_tx_max_coal_bds = 128; 3582 #else 3583 sc->bge_tx_coal_ticks = 300; 3584 sc->bge_tx_max_coal_bds = 400; 3585 #endif 3586 if (BGE_IS_5705_PLUS(sc)) { 3587 sc->bge_tx_coal_ticks = (12 * 5); 3588 sc->bge_tx_max_coal_bds = (12 * 5); 3589 aprint_verbose_dev(sc->bge_dev, 3590 "setting short Tx thresholds\n"); 3591 } 3592 3593 if (BGE_IS_5717_PLUS(sc)) 3594 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT; 3595 else if (BGE_IS_5705_PLUS(sc)) 3596 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT_5705; 3597 else 3598 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT; 3599 3600 /* Set up ifnet structure */ 3601 ifp = &sc->ethercom.ec_if; 3602 ifp->if_softc = sc; 3603 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 3604 ifp->if_ioctl = bge_ioctl; 3605 ifp->if_stop = bge_stop; 3606 ifp->if_start = bge_start; 3607 ifp->if_init = bge_init; 3608 ifp->if_watchdog = bge_watchdog; 3609 IFQ_SET_MAXLEN(&ifp->if_snd, max(BGE_TX_RING_CNT - 1, IFQ_MAXLEN)); 3610 IFQ_SET_READY(&ifp->if_snd); 3611 DPRINTFN(5, ("strcpy if_xname\n")); 3612 strcpy(ifp->if_xname, device_xname(sc->bge_dev)); 3613 3614 if (sc->bge_chipid != BGE_CHIPID_BCM5700_B0) 3615 sc->ethercom.ec_if.if_capabilities |= 3616 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx; 3617 #if 1 /* XXX TCP/UDP checksum offload breaks with pf(4) */ 3618 sc->ethercom.ec_if.if_capabilities |= 3619 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 3620 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 3621 #endif 3622 sc->ethercom.ec_capabilities |= 3623 ETHERCAP_VLAN_HWTAGGING | ETHERCAP_VLAN_MTU; 3624 3625 if (sc->bge_flags & BGE_TSO) 3626 sc->ethercom.ec_if.if_capabilities |= IFCAP_TSOv4; 3627 3628 /* 3629 * Do MII setup. 3630 */ 3631 DPRINTFN(5, ("mii setup\n")); 3632 sc->bge_mii.mii_ifp = ifp; 3633 sc->bge_mii.mii_readreg = bge_miibus_readreg; 3634 sc->bge_mii.mii_writereg = bge_miibus_writereg; 3635 sc->bge_mii.mii_statchg = bge_miibus_statchg; 3636 3637 /* 3638 * Figure out what sort of media we have by checking the hardware 3639 * config word in the first 32k of NIC internal memory, or fall back to 3640 * the config word in the EEPROM. Note: on some BCM5700 cards, 3641 * this value appears to be unset. If that's the case, we have to rely 3642 * on identifying the NIC by its PCI subsystem ID, as we do below for 3643 * the SysKonnect SK-9D41. 3644 */ 3645 if (bge_readmem_ind(sc, BGE_SRAM_DATA_SIG) == BGE_SRAM_DATA_SIG_MAGIC) { 3646 hwcfg = bge_readmem_ind(sc, BGE_SRAM_DATA_CFG); 3647 } else if (!(sc->bge_flags & BGE_NO_EEPROM)) { 3648 bge_read_eeprom(sc, (void *)&hwcfg, 3649 BGE_EE_HWCFG_OFFSET, sizeof(hwcfg)); 3650 hwcfg = be32toh(hwcfg); 3651 } 3652 /* The SysKonnect SK-9D41 is a 1000baseSX card. */ 3653 if (PCI_PRODUCT(pa->pa_id) == SK_SUBSYSID_9D41 || 3654 (hwcfg & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER) { 3655 if (BGE_IS_5714_FAMILY(sc)) 3656 sc->bge_flags |= BGE_PHY_FIBER_MII; 3657 else 3658 sc->bge_flags |= BGE_PHY_FIBER_TBI; 3659 } 3660 3661 /* set phyflags and chipid before mii_attach() */ 3662 dict = device_properties(self); 3663 prop_dictionary_set_uint32(dict, "phyflags", sc->bge_flags); 3664 prop_dictionary_set_uint32(dict, "chipid", sc->bge_chipid); 3665 3666 if (sc->bge_flags & BGE_PHY_FIBER_TBI) { 3667 ifmedia_init(&sc->bge_ifmedia, IFM_IMASK, bge_ifmedia_upd, 3668 bge_ifmedia_sts); 3669 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER |IFM_1000_SX, 0, NULL); 3670 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_1000_SX|IFM_FDX, 3671 0, NULL); 3672 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_AUTO, 0, NULL); 3673 ifmedia_set(&sc->bge_ifmedia, IFM_ETHER | IFM_AUTO); 3674 /* Pretend the user requested this setting */ 3675 sc->bge_ifmedia.ifm_media = sc->bge_ifmedia.ifm_cur->ifm_media; 3676 } else { 3677 /* 3678 * Do transceiver setup and tell the firmware the 3679 * driver is down so we can try to get access the 3680 * probe if ASF is running. Retry a couple of times 3681 * if we get a conflict with the ASF firmware accessing 3682 * the PHY. 3683 */ 3684 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 3685 bge_asf_driver_up(sc); 3686 3687 ifmedia_init(&sc->bge_mii.mii_media, 0, bge_ifmedia_upd, 3688 bge_ifmedia_sts); 3689 mii_attach(sc->bge_dev, &sc->bge_mii, 0xffffffff, 3690 sc->bge_phy_addr, MII_OFFSET_ANY, 3691 MIIF_DOPAUSE); 3692 3693 if (LIST_EMPTY(&sc->bge_mii.mii_phys)) { 3694 aprint_error_dev(sc->bge_dev, "no PHY found!\n"); 3695 ifmedia_add(&sc->bge_mii.mii_media, 3696 IFM_ETHER|IFM_MANUAL, 0, NULL); 3697 ifmedia_set(&sc->bge_mii.mii_media, 3698 IFM_ETHER|IFM_MANUAL); 3699 } else 3700 ifmedia_set(&sc->bge_mii.mii_media, 3701 IFM_ETHER|IFM_AUTO); 3702 3703 /* 3704 * Now tell the firmware we are going up after probing the PHY 3705 */ 3706 if (sc->bge_asf_mode & ASF_STACKUP) 3707 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 3708 } 3709 3710 /* 3711 * Call MI attach routine. 3712 */ 3713 DPRINTFN(5, ("if_attach\n")); 3714 if_attach(ifp); 3715 DPRINTFN(5, ("ether_ifattach\n")); 3716 ether_ifattach(ifp, eaddr); 3717 ether_set_ifflags_cb(&sc->ethercom, bge_ifflags_cb); 3718 rnd_attach_source(&sc->rnd_source, device_xname(sc->bge_dev), 3719 RND_TYPE_NET, 0); 3720 #ifdef BGE_EVENT_COUNTERS 3721 /* 3722 * Attach event counters. 3723 */ 3724 evcnt_attach_dynamic(&sc->bge_ev_intr, EVCNT_TYPE_INTR, 3725 NULL, device_xname(sc->bge_dev), "intr"); 3726 evcnt_attach_dynamic(&sc->bge_ev_tx_xoff, EVCNT_TYPE_MISC, 3727 NULL, device_xname(sc->bge_dev), "tx_xoff"); 3728 evcnt_attach_dynamic(&sc->bge_ev_tx_xon, EVCNT_TYPE_MISC, 3729 NULL, device_xname(sc->bge_dev), "tx_xon"); 3730 evcnt_attach_dynamic(&sc->bge_ev_rx_xoff, EVCNT_TYPE_MISC, 3731 NULL, device_xname(sc->bge_dev), "rx_xoff"); 3732 evcnt_attach_dynamic(&sc->bge_ev_rx_xon, EVCNT_TYPE_MISC, 3733 NULL, device_xname(sc->bge_dev), "rx_xon"); 3734 evcnt_attach_dynamic(&sc->bge_ev_rx_macctl, EVCNT_TYPE_MISC, 3735 NULL, device_xname(sc->bge_dev), "rx_macctl"); 3736 evcnt_attach_dynamic(&sc->bge_ev_xoffentered, EVCNT_TYPE_MISC, 3737 NULL, device_xname(sc->bge_dev), "xoffentered"); 3738 #endif /* BGE_EVENT_COUNTERS */ 3739 DPRINTFN(5, ("callout_init\n")); 3740 callout_init(&sc->bge_timeout, 0); 3741 3742 if (pmf_device_register(self, NULL, NULL)) 3743 pmf_class_network_register(self, ifp); 3744 else 3745 aprint_error_dev(self, "couldn't establish power handler\n"); 3746 3747 bge_sysctl_init(sc); 3748 3749 #ifdef BGE_DEBUG 3750 bge_debug_info(sc); 3751 #endif 3752 } 3753 3754 static void 3755 bge_release_resources(struct bge_softc *sc) 3756 { 3757 if (sc->bge_vpd_prodname != NULL) 3758 free(sc->bge_vpd_prodname, M_DEVBUF); 3759 3760 if (sc->bge_vpd_readonly != NULL) 3761 free(sc->bge_vpd_readonly, M_DEVBUF); 3762 } 3763 3764 static int 3765 bge_reset(struct bge_softc *sc) 3766 { 3767 uint32_t cachesize, command; 3768 uint32_t reset, mac_mode, mac_mode_mask; 3769 pcireg_t devctl, reg; 3770 int i, val; 3771 void (*write_op)(struct bge_softc *, int, int); 3772 3773 mac_mode_mask = BGE_MACMODE_HALF_DUPLEX | BGE_MACMODE_PORTMODE; 3774 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) != 0) 3775 mac_mode_mask |= BGE_MACMODE_APE_RX_EN | BGE_MACMODE_APE_TX_EN; 3776 mac_mode = CSR_READ_4(sc, BGE_MAC_MODE) & mac_mode_mask; 3777 3778 if (BGE_IS_575X_PLUS(sc) && !BGE_IS_5714_FAMILY(sc) && 3779 (BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5906)) { 3780 if (sc->bge_flags & BGE_PCIE) 3781 write_op = bge_writemem_direct; 3782 else 3783 write_op = bge_writemem_ind; 3784 } else 3785 write_op = bge_writereg_ind; 3786 3787 if (BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5700 && 3788 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5701) { 3789 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_SET1); 3790 for (i = 0; i < 8000; i++) { 3791 if (CSR_READ_4(sc, BGE_NVRAM_SWARB) & 3792 BGE_NVRAMSWARB_GNT1) 3793 break; 3794 DELAY(20); 3795 } 3796 if (i == 8000) { 3797 printf("%s: NVRAM lock timedout!\n", 3798 device_xname(sc->bge_dev)); 3799 } 3800 } 3801 /* Take APE lock when performing reset. */ 3802 bge_ape_lock(sc, BGE_APE_LOCK_GRC); 3803 3804 /* Save some important PCI state. */ 3805 cachesize = pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CACHESZ); 3806 command = pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CMD); 3807 3808 /* Step 5b-5d: */ 3809 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MISC_CTL, 3810 BGE_PCIMISCCTL_INDIRECT_ACCESS | BGE_PCIMISCCTL_MASK_PCI_INTR | 3811 BGE_HIF_SWAP_OPTIONS | BGE_PCIMISCCTL_PCISTATE_RW); 3812 3813 /* XXX ???: Disable fastboot on controllers that support it. */ 3814 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5752 || 3815 BGE_IS_5755_PLUS(sc)) 3816 CSR_WRITE_4(sc, BGE_FASTBOOT_PC, 0); 3817 3818 /* 3819 * Step 6: Write the magic number to SRAM at offset 0xB50. 3820 * When firmware finishes its initialization it will 3821 * write ~BGE_MAGIC_NUMBER to the same location. 3822 */ 3823 bge_writemem_ind(sc, BGE_SRAM_FW_MB, BGE_SRAM_FW_MB_MAGIC); 3824 3825 /* Step 7: */ 3826 reset = BGE_MISCCFG_RESET_CORE_CLOCKS | BGE_32BITTIME_66MHZ; 3827 /* 3828 * XXX: from FreeBSD/Linux; no documentation 3829 */ 3830 if (sc->bge_flags & BGE_PCIE) { 3831 if (BGE_ASICREV(sc->bge_chipid != BGE_ASICREV_BCM5785) && 3832 !BGE_IS_57765_PLUS(sc) && 3833 (CSR_READ_4(sc, BGE_PHY_TEST_CTRL_REG) == 3834 (BGE_PHY_PCIE_LTASS_MODE | BGE_PHY_PCIE_SCRAM_MODE))) { 3835 /* PCI Express 1.0 system */ 3836 CSR_WRITE_4(sc, BGE_PHY_TEST_CTRL_REG, 3837 BGE_PHY_PCIE_SCRAM_MODE); 3838 } 3839 if (sc->bge_chipid != BGE_CHIPID_BCM5750_A0) { 3840 /* 3841 * Prevent PCI Express link training 3842 * during global reset. 3843 */ 3844 CSR_WRITE_4(sc, BGE_MISC_CFG, 1 << 29); 3845 reset |= (1<<29); 3846 } 3847 } 3848 3849 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 3850 i = CSR_READ_4(sc, BGE_VCPU_STATUS); 3851 CSR_WRITE_4(sc, BGE_VCPU_STATUS, 3852 i | BGE_VCPU_STATUS_DRV_RESET); 3853 i = CSR_READ_4(sc, BGE_VCPU_EXT_CTRL); 3854 CSR_WRITE_4(sc, BGE_VCPU_EXT_CTRL, 3855 i & ~BGE_VCPU_EXT_CTRL_HALT_CPU); 3856 } 3857 3858 /* 3859 * Set GPHY Power Down Override to leave GPHY 3860 * powered up in D0 uninitialized. 3861 */ 3862 if (BGE_IS_5705_PLUS(sc) && 3863 (sc->bge_flags & BGE_CPMU_PRESENT) == 0) 3864 reset |= BGE_MISCCFG_GPHY_PD_OVERRIDE; 3865 3866 /* XXX 5721, 5751 and 5752 */ 3867 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5750) 3868 reset |= BGE_MISCCFG_GRC_RESET_DISABLE; 3869 3870 /* Issue global reset */ 3871 write_op(sc, BGE_MISC_CFG, reset); 3872 3873 /* Step 8: wait for complete */ 3874 if (sc->bge_flags & BGE_PCIE) 3875 delay(100*1000); /* too big */ 3876 else 3877 delay(1000); 3878 3879 if (sc->bge_flags & BGE_PCIE) { 3880 if (sc->bge_chipid == BGE_CHIPID_BCM5750_A0) { 3881 DELAY(500000); 3882 /* XXX: Magic Numbers */ 3883 reg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 3884 BGE_PCI_UNKNOWN0); 3885 pci_conf_write(sc->sc_pc, sc->sc_pcitag, 3886 BGE_PCI_UNKNOWN0, 3887 reg | (1 << 15)); 3888 } 3889 devctl = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 3890 sc->bge_pciecap + PCI_PCIE_DCSR); 3891 /* Clear enable no snoop and disable relaxed ordering. */ 3892 devctl &= ~(PCI_PCIE_DCSR_ENA_RELAX_ORD | 3893 PCI_PCIE_DCSR_ENA_NO_SNOOP); 3894 3895 /* Set PCIE max payload size to 128 for older PCIe devices */ 3896 if ((sc->bge_flags & BGE_CPMU_PRESENT) == 0) 3897 devctl &= ~(0x00e0); 3898 /* Clear device status register. Write 1b to clear */ 3899 devctl |= PCI_PCIE_DCSR_URD | PCI_PCIE_DCSR_FED 3900 | PCI_PCIE_DCSR_NFED | PCI_PCIE_DCSR_CED; 3901 pci_conf_write(sc->sc_pc, sc->sc_pcitag, 3902 sc->bge_pciecap + PCI_PCIE_DCSR, devctl); 3903 bge_set_max_readrq(sc); 3904 } 3905 3906 /* From Linux: dummy read to flush PCI posted writes */ 3907 reg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CMD); 3908 3909 /* Step 9-10: Reset some of the PCI state that got zapped by reset */ 3910 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MISC_CTL, 3911 BGE_PCIMISCCTL_INDIRECT_ACCESS | BGE_PCIMISCCTL_MASK_PCI_INTR | 3912 BGE_HIF_SWAP_OPTIONS | BGE_PCIMISCCTL_PCISTATE_RW); 3913 val = BGE_PCISTATE_ROM_ENABLE | BGE_PCISTATE_ROM_RETRY_ENABLE; 3914 if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0 && 3915 (sc->bge_flags & BGE_PCIX) != 0) 3916 val |= BGE_PCISTATE_RETRY_SAME_DMA; 3917 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) != 0) 3918 val |= BGE_PCISTATE_ALLOW_APE_CTLSPC_WR | 3919 BGE_PCISTATE_ALLOW_APE_SHMEM_WR | 3920 BGE_PCISTATE_ALLOW_APE_PSPACE_WR; 3921 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_PCISTATE, val); 3922 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CACHESZ, cachesize); 3923 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CMD, command); 3924 3925 /* Step 11: disable PCI-X Relaxed Ordering. */ 3926 if (sc->bge_flags & BGE_PCIX) { 3927 reg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, sc->bge_pcixcap 3928 + PCI_PCIX_CMD); 3929 pci_conf_write(sc->sc_pc, sc->sc_pcitag, sc->bge_pcixcap 3930 + PCI_PCIX_CMD, reg & ~PCI_PCIX_CMD_RELAXED_ORDER); 3931 } 3932 3933 /* Step 12: Enable memory arbiter. */ 3934 if (BGE_IS_5714_FAMILY(sc)) { 3935 val = CSR_READ_4(sc, BGE_MARB_MODE); 3936 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE | val); 3937 } else 3938 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 3939 3940 /* XXX 5721, 5751 and 5752 */ 3941 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5750) { 3942 /* Step 19: */ 3943 BGE_SETBIT(sc, BGE_TLP_CONTROL_REG, 1 << 29 | 1 << 25); 3944 /* Step 20: */ 3945 BGE_SETBIT(sc, BGE_TLP_CONTROL_REG, BGE_TLP_DATA_FIFO_PROTECT); 3946 } 3947 3948 /* Step 28: Fix up byte swapping */ 3949 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS); 3950 3951 /* Step 21: 5822 B0 errata */ 3952 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5704_BX) { 3953 pcireg_t msidata; 3954 3955 msidata = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 3956 BGE_PCI_MSI_DATA); 3957 msidata |= ((1 << 13 | 1 << 12 | 1 << 10) << 16); 3958 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MSI_DATA, 3959 msidata); 3960 } 3961 3962 /* 3963 * Step 18: wirte mac mode 3964 * XXX Write 0x0c for 5703S and 5704S 3965 */ 3966 val = CSR_READ_4(sc, BGE_MAC_MODE); 3967 val = (val & ~mac_mode_mask) | mac_mode; 3968 CSR_WRITE_4_FLUSH(sc, BGE_MAC_MODE, val); 3969 DELAY(40); 3970 3971 bge_ape_unlock(sc, BGE_APE_LOCK_GRC); 3972 3973 /* Step 17: Poll until the firmware initialization is complete */ 3974 bge_poll_fw(sc); 3975 3976 /* 3977 * The 5704 in TBI mode apparently needs some special 3978 * adjustment to insure the SERDES drive level is set 3979 * to 1.2V. 3980 */ 3981 if (sc->bge_flags & BGE_PHY_FIBER_TBI && 3982 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) { 3983 uint32_t serdescfg; 3984 3985 serdescfg = CSR_READ_4(sc, BGE_SERDES_CFG); 3986 serdescfg = (serdescfg & ~0xFFF) | 0x880; 3987 CSR_WRITE_4(sc, BGE_SERDES_CFG, serdescfg); 3988 } 3989 3990 if (sc->bge_flags & BGE_PCIE && 3991 !BGE_IS_57765_PLUS(sc) && 3992 sc->bge_chipid != BGE_CHIPID_BCM5750_A0 && 3993 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5785) { 3994 uint32_t v; 3995 3996 /* Enable PCI Express bug fix */ 3997 v = CSR_READ_4(sc, BGE_TLP_CONTROL_REG); 3998 CSR_WRITE_4(sc, BGE_TLP_CONTROL_REG, 3999 v | BGE_TLP_DATA_FIFO_PROTECT); 4000 } 4001 4002 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) 4003 BGE_CLRBIT(sc, BGE_CPMU_CLCK_ORIDE, 4004 CPMU_CLCK_ORIDE_MAC_ORIDE_EN); 4005 4006 return 0; 4007 } 4008 4009 /* 4010 * Frame reception handling. This is called if there's a frame 4011 * on the receive return list. 4012 * 4013 * Note: we have to be able to handle two possibilities here: 4014 * 1) the frame is from the jumbo receive ring 4015 * 2) the frame is from the standard receive ring 4016 */ 4017 4018 static void 4019 bge_rxeof(struct bge_softc *sc) 4020 { 4021 struct ifnet *ifp; 4022 uint16_t rx_prod, rx_cons; 4023 int stdcnt = 0, jumbocnt = 0; 4024 bus_dmamap_t dmamap; 4025 bus_addr_t offset, toff; 4026 bus_size_t tlen; 4027 int tosync; 4028 4029 rx_cons = sc->bge_rx_saved_considx; 4030 rx_prod = sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx; 4031 4032 /* Nothing to do */ 4033 if (rx_cons == rx_prod) 4034 return; 4035 4036 ifp = &sc->ethercom.ec_if; 4037 4038 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 4039 offsetof(struct bge_ring_data, bge_status_block), 4040 sizeof (struct bge_status_block), 4041 BUS_DMASYNC_POSTREAD); 4042 4043 offset = offsetof(struct bge_ring_data, bge_rx_return_ring); 4044 tosync = rx_prod - rx_cons; 4045 4046 if (tosync != 0) 4047 rnd_add_uint32(&sc->rnd_source, tosync); 4048 4049 toff = offset + (rx_cons * sizeof (struct bge_rx_bd)); 4050 4051 if (tosync < 0) { 4052 tlen = (sc->bge_return_ring_cnt - rx_cons) * 4053 sizeof (struct bge_rx_bd); 4054 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 4055 toff, tlen, BUS_DMASYNC_POSTREAD); 4056 tosync = -tosync; 4057 } 4058 4059 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 4060 offset, tosync * sizeof (struct bge_rx_bd), 4061 BUS_DMASYNC_POSTREAD); 4062 4063 while (rx_cons != rx_prod) { 4064 struct bge_rx_bd *cur_rx; 4065 uint32_t rxidx; 4066 struct mbuf *m = NULL; 4067 4068 cur_rx = &sc->bge_rdata->bge_rx_return_ring[rx_cons]; 4069 4070 rxidx = cur_rx->bge_idx; 4071 BGE_INC(rx_cons, sc->bge_return_ring_cnt); 4072 4073 if (cur_rx->bge_flags & BGE_RXBDFLAG_JUMBO_RING) { 4074 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT); 4075 m = sc->bge_cdata.bge_rx_jumbo_chain[rxidx]; 4076 sc->bge_cdata.bge_rx_jumbo_chain[rxidx] = NULL; 4077 jumbocnt++; 4078 bus_dmamap_sync(sc->bge_dmatag, 4079 sc->bge_cdata.bge_rx_jumbo_map, 4080 mtod(m, char *) - (char *)sc->bge_cdata.bge_jumbo_buf, 4081 BGE_JLEN, BUS_DMASYNC_POSTREAD); 4082 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 4083 ifp->if_ierrors++; 4084 bge_newbuf_jumbo(sc, sc->bge_jumbo, m); 4085 continue; 4086 } 4087 if (bge_newbuf_jumbo(sc, sc->bge_jumbo, 4088 NULL)== ENOBUFS) { 4089 ifp->if_ierrors++; 4090 bge_newbuf_jumbo(sc, sc->bge_jumbo, m); 4091 continue; 4092 } 4093 } else { 4094 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT); 4095 m = sc->bge_cdata.bge_rx_std_chain[rxidx]; 4096 4097 sc->bge_cdata.bge_rx_std_chain[rxidx] = NULL; 4098 stdcnt++; 4099 dmamap = sc->bge_cdata.bge_rx_std_map[rxidx]; 4100 sc->bge_cdata.bge_rx_std_map[rxidx] = 0; 4101 if (dmamap == NULL) { 4102 ifp->if_ierrors++; 4103 bge_newbuf_std(sc, sc->bge_std, m, dmamap); 4104 continue; 4105 } 4106 bus_dmamap_sync(sc->bge_dmatag, dmamap, 0, 4107 dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 4108 bus_dmamap_unload(sc->bge_dmatag, dmamap); 4109 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 4110 ifp->if_ierrors++; 4111 bge_newbuf_std(sc, sc->bge_std, m, dmamap); 4112 continue; 4113 } 4114 if (bge_newbuf_std(sc, sc->bge_std, 4115 NULL, dmamap) == ENOBUFS) { 4116 ifp->if_ierrors++; 4117 bge_newbuf_std(sc, sc->bge_std, m, dmamap); 4118 continue; 4119 } 4120 } 4121 4122 ifp->if_ipackets++; 4123 #ifndef __NO_STRICT_ALIGNMENT 4124 /* 4125 * XXX: if the 5701 PCIX-Rx-DMA workaround is in effect, 4126 * the Rx buffer has the layer-2 header unaligned. 4127 * If our CPU requires alignment, re-align by copying. 4128 */ 4129 if (sc->bge_flags & BGE_RX_ALIGNBUG) { 4130 memmove(mtod(m, char *) + ETHER_ALIGN, m->m_data, 4131 cur_rx->bge_len); 4132 m->m_data += ETHER_ALIGN; 4133 } 4134 #endif 4135 4136 m->m_pkthdr.len = m->m_len = cur_rx->bge_len - ETHER_CRC_LEN; 4137 m->m_pkthdr.rcvif = ifp; 4138 4139 /* 4140 * Handle BPF listeners. Let the BPF user see the packet. 4141 */ 4142 bpf_mtap(ifp, m); 4143 4144 bge_rxcsum(sc, cur_rx, m); 4145 4146 /* 4147 * If we received a packet with a vlan tag, pass it 4148 * to vlan_input() instead of ether_input(). 4149 */ 4150 if (cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) { 4151 VLAN_INPUT_TAG(ifp, m, cur_rx->bge_vlan_tag, continue); 4152 } 4153 4154 (*ifp->if_input)(ifp, m); 4155 } 4156 4157 sc->bge_rx_saved_considx = rx_cons; 4158 bge_writembx(sc, BGE_MBX_RX_CONS0_LO, sc->bge_rx_saved_considx); 4159 if (stdcnt) 4160 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std); 4161 if (jumbocnt) 4162 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo); 4163 } 4164 4165 static void 4166 bge_rxcsum(struct bge_softc *sc, struct bge_rx_bd *cur_rx, struct mbuf *m) 4167 { 4168 4169 if (BGE_IS_5717_PLUS(sc)) { 4170 if ((cur_rx->bge_flags & BGE_RXBDFLAG_IPV6) == 0) { 4171 if ((cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM) != 0) 4172 m->m_pkthdr.csum_flags = M_CSUM_IPv4; 4173 if ((cur_rx->bge_error_flag & 4174 BGE_RXERRFLAG_IP_CSUM_NOK) != 0) 4175 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 4176 if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM) { 4177 m->m_pkthdr.csum_data = 4178 cur_rx->bge_tcp_udp_csum; 4179 m->m_pkthdr.csum_flags |= 4180 (M_CSUM_TCPv4|M_CSUM_UDPv4| 4181 M_CSUM_DATA); 4182 } 4183 } 4184 } else { 4185 if ((cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM) != 0) 4186 m->m_pkthdr.csum_flags = M_CSUM_IPv4; 4187 if ((cur_rx->bge_ip_csum ^ 0xffff) != 0) 4188 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 4189 /* 4190 * Rx transport checksum-offload may also 4191 * have bugs with packets which, when transmitted, 4192 * were `runts' requiring padding. 4193 */ 4194 if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM && 4195 (/* (sc->_bge_quirks & BGE_QUIRK_SHORT_CKSUM_BUG) == 0 ||*/ 4196 m->m_pkthdr.len >= ETHER_MIN_NOPAD)) { 4197 m->m_pkthdr.csum_data = 4198 cur_rx->bge_tcp_udp_csum; 4199 m->m_pkthdr.csum_flags |= 4200 (M_CSUM_TCPv4|M_CSUM_UDPv4| 4201 M_CSUM_DATA); 4202 } 4203 } 4204 } 4205 4206 static void 4207 bge_txeof(struct bge_softc *sc) 4208 { 4209 struct bge_tx_bd *cur_tx = NULL; 4210 struct ifnet *ifp; 4211 struct txdmamap_pool_entry *dma; 4212 bus_addr_t offset, toff; 4213 bus_size_t tlen; 4214 int tosync; 4215 struct mbuf *m; 4216 4217 ifp = &sc->ethercom.ec_if; 4218 4219 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 4220 offsetof(struct bge_ring_data, bge_status_block), 4221 sizeof (struct bge_status_block), 4222 BUS_DMASYNC_POSTREAD); 4223 4224 offset = offsetof(struct bge_ring_data, bge_tx_ring); 4225 tosync = sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx - 4226 sc->bge_tx_saved_considx; 4227 4228 if (tosync != 0) 4229 rnd_add_uint32(&sc->rnd_source, tosync); 4230 4231 toff = offset + (sc->bge_tx_saved_considx * sizeof (struct bge_tx_bd)); 4232 4233 if (tosync < 0) { 4234 tlen = (BGE_TX_RING_CNT - sc->bge_tx_saved_considx) * 4235 sizeof (struct bge_tx_bd); 4236 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 4237 toff, tlen, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 4238 tosync = -tosync; 4239 } 4240 4241 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 4242 offset, tosync * sizeof (struct bge_tx_bd), 4243 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 4244 4245 /* 4246 * Go through our tx ring and free mbufs for those 4247 * frames that have been sent. 4248 */ 4249 while (sc->bge_tx_saved_considx != 4250 sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx) { 4251 uint32_t idx = 0; 4252 4253 idx = sc->bge_tx_saved_considx; 4254 cur_tx = &sc->bge_rdata->bge_tx_ring[idx]; 4255 if (cur_tx->bge_flags & BGE_TXBDFLAG_END) 4256 ifp->if_opackets++; 4257 m = sc->bge_cdata.bge_tx_chain[idx]; 4258 if (m != NULL) { 4259 sc->bge_cdata.bge_tx_chain[idx] = NULL; 4260 dma = sc->txdma[idx]; 4261 bus_dmamap_sync(sc->bge_dmatag, dma->dmamap, 0, 4262 dma->dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 4263 bus_dmamap_unload(sc->bge_dmatag, dma->dmamap); 4264 SLIST_INSERT_HEAD(&sc->txdma_list, dma, link); 4265 sc->txdma[idx] = NULL; 4266 4267 m_freem(m); 4268 } 4269 sc->bge_txcnt--; 4270 BGE_INC(sc->bge_tx_saved_considx, BGE_TX_RING_CNT); 4271 ifp->if_timer = 0; 4272 } 4273 4274 if (cur_tx != NULL) 4275 ifp->if_flags &= ~IFF_OACTIVE; 4276 } 4277 4278 static int 4279 bge_intr(void *xsc) 4280 { 4281 struct bge_softc *sc; 4282 struct ifnet *ifp; 4283 uint32_t statusword; 4284 4285 sc = xsc; 4286 ifp = &sc->ethercom.ec_if; 4287 4288 /* It is possible for the interrupt to arrive before 4289 * the status block is updated prior to the interrupt. 4290 * Reading the PCI State register will confirm whether the 4291 * interrupt is ours and will flush the status block. 4292 */ 4293 4294 /* read status word from status block */ 4295 statusword = sc->bge_rdata->bge_status_block.bge_status; 4296 4297 if ((statusword & BGE_STATFLAG_UPDATED) || 4298 (!(pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_PCISTATE) & 4299 BGE_PCISTATE_INTR_NOT_ACTIVE))) { 4300 /* Ack interrupt and stop others from occuring. */ 4301 bge_writembx_flush(sc, BGE_MBX_IRQ0_LO, 1); 4302 4303 BGE_EVCNT_INCR(sc->bge_ev_intr); 4304 4305 /* clear status word */ 4306 sc->bge_rdata->bge_status_block.bge_status = 0; 4307 4308 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 4309 statusword & BGE_STATFLAG_LINKSTATE_CHANGED || 4310 BGE_STS_BIT(sc, BGE_STS_LINK_EVT)) 4311 bge_link_upd(sc); 4312 4313 if (ifp->if_flags & IFF_RUNNING) { 4314 /* Check RX return ring producer/consumer */ 4315 bge_rxeof(sc); 4316 4317 /* Check TX ring producer/consumer */ 4318 bge_txeof(sc); 4319 } 4320 4321 if (sc->bge_pending_rxintr_change) { 4322 uint32_t rx_ticks = sc->bge_rx_coal_ticks; 4323 uint32_t rx_bds = sc->bge_rx_max_coal_bds; 4324 uint32_t junk; 4325 4326 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, rx_ticks); 4327 DELAY(10); 4328 junk = CSR_READ_4(sc, BGE_HCC_RX_COAL_TICKS); 4329 4330 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, rx_bds); 4331 DELAY(10); 4332 junk = CSR_READ_4(sc, BGE_HCC_RX_MAX_COAL_BDS); 4333 4334 sc->bge_pending_rxintr_change = 0; 4335 } 4336 bge_handle_events(sc); 4337 4338 /* Re-enable interrupts. */ 4339 bge_writembx_flush(sc, BGE_MBX_IRQ0_LO, 0); 4340 4341 if (ifp->if_flags & IFF_RUNNING && !IFQ_IS_EMPTY(&ifp->if_snd)) 4342 bge_start(ifp); 4343 4344 return 1; 4345 } else 4346 return 0; 4347 } 4348 4349 static void 4350 bge_asf_driver_up(struct bge_softc *sc) 4351 { 4352 if (sc->bge_asf_mode & ASF_STACKUP) { 4353 /* Send ASF heartbeat aprox. every 2s */ 4354 if (sc->bge_asf_count) 4355 sc->bge_asf_count --; 4356 else { 4357 sc->bge_asf_count = 2; 4358 4359 bge_wait_for_event_ack(sc); 4360 4361 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_MB, 4362 BGE_FW_CMD_DRV_ALIVE); 4363 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_LEN_MB, 4); 4364 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_DATA_MB, 4365 BGE_FW_HB_TIMEOUT_SEC); 4366 CSR_WRITE_4_FLUSH(sc, BGE_RX_CPU_EVENT, 4367 CSR_READ_4(sc, BGE_RX_CPU_EVENT) | 4368 BGE_RX_CPU_DRV_EVENT); 4369 } 4370 } 4371 } 4372 4373 static void 4374 bge_tick(void *xsc) 4375 { 4376 struct bge_softc *sc = xsc; 4377 struct mii_data *mii = &sc->bge_mii; 4378 int s; 4379 4380 s = splnet(); 4381 4382 if (BGE_IS_5705_PLUS(sc)) 4383 bge_stats_update_regs(sc); 4384 else 4385 bge_stats_update(sc); 4386 4387 if (sc->bge_flags & BGE_PHY_FIBER_TBI) { 4388 /* 4389 * Since in TBI mode auto-polling can't be used we should poll 4390 * link status manually. Here we register pending link event 4391 * and trigger interrupt. 4392 */ 4393 BGE_STS_SETBIT(sc, BGE_STS_LINK_EVT); 4394 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET); 4395 } else { 4396 /* 4397 * Do not touch PHY if we have link up. This could break 4398 * IPMI/ASF mode or produce extra input errors. 4399 * (extra input errors was reported for bcm5701 & bcm5704). 4400 */ 4401 if (!BGE_STS_BIT(sc, BGE_STS_LINK)) 4402 mii_tick(mii); 4403 } 4404 4405 bge_asf_driver_up(sc); 4406 4407 callout_reset(&sc->bge_timeout, hz, bge_tick, sc); 4408 4409 splx(s); 4410 } 4411 4412 static void 4413 bge_stats_update_regs(struct bge_softc *sc) 4414 { 4415 struct ifnet *ifp = &sc->ethercom.ec_if; 4416 4417 ifp->if_collisions += CSR_READ_4(sc, BGE_MAC_STATS + 4418 offsetof(struct bge_mac_stats_regs, etherStatsCollisions)); 4419 4420 ifp->if_ierrors += CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_DROPS); 4421 ifp->if_ierrors += CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_ERRORS); 4422 ifp->if_ierrors += CSR_READ_4(sc, BGE_RXLP_LOCSTAT_OUT_OF_BDS); 4423 } 4424 4425 static void 4426 bge_stats_update(struct bge_softc *sc) 4427 { 4428 struct ifnet *ifp = &sc->ethercom.ec_if; 4429 bus_size_t stats = BGE_MEMWIN_START + BGE_STATS_BLOCK; 4430 4431 #define READ_STAT(sc, stats, stat) \ 4432 CSR_READ_4(sc, stats + offsetof(struct bge_stats, stat)) 4433 4434 ifp->if_collisions += 4435 (READ_STAT(sc, stats, dot3StatsSingleCollisionFrames.bge_addr_lo) + 4436 READ_STAT(sc, stats, dot3StatsMultipleCollisionFrames.bge_addr_lo) + 4437 READ_STAT(sc, stats, dot3StatsExcessiveCollisions.bge_addr_lo) + 4438 READ_STAT(sc, stats, dot3StatsLateCollisions.bge_addr_lo)) - 4439 ifp->if_collisions; 4440 4441 BGE_EVCNT_UPD(sc->bge_ev_tx_xoff, 4442 READ_STAT(sc, stats, outXoffSent.bge_addr_lo)); 4443 BGE_EVCNT_UPD(sc->bge_ev_tx_xon, 4444 READ_STAT(sc, stats, outXonSent.bge_addr_lo)); 4445 BGE_EVCNT_UPD(sc->bge_ev_rx_xoff, 4446 READ_STAT(sc, stats, 4447 xoffPauseFramesReceived.bge_addr_lo)); 4448 BGE_EVCNT_UPD(sc->bge_ev_rx_xon, 4449 READ_STAT(sc, stats, xonPauseFramesReceived.bge_addr_lo)); 4450 BGE_EVCNT_UPD(sc->bge_ev_rx_macctl, 4451 READ_STAT(sc, stats, 4452 macControlFramesReceived.bge_addr_lo)); 4453 BGE_EVCNT_UPD(sc->bge_ev_xoffentered, 4454 READ_STAT(sc, stats, xoffStateEntered.bge_addr_lo)); 4455 4456 #undef READ_STAT 4457 4458 #ifdef notdef 4459 ifp->if_collisions += 4460 (sc->bge_rdata->bge_info.bge_stats.dot3StatsSingleCollisionFrames + 4461 sc->bge_rdata->bge_info.bge_stats.dot3StatsMultipleCollisionFrames + 4462 sc->bge_rdata->bge_info.bge_stats.dot3StatsExcessiveCollisions + 4463 sc->bge_rdata->bge_info.bge_stats.dot3StatsLateCollisions) - 4464 ifp->if_collisions; 4465 #endif 4466 } 4467 4468 /* 4469 * Pad outbound frame to ETHER_MIN_NOPAD for an unusual reason. 4470 * The bge hardware will pad out Tx runts to ETHER_MIN_NOPAD, 4471 * but when such padded frames employ the bge IP/TCP checksum offload, 4472 * the hardware checksum assist gives incorrect results (possibly 4473 * from incorporating its own padding into the UDP/TCP checksum; who knows). 4474 * If we pad such runts with zeros, the onboard checksum comes out correct. 4475 */ 4476 static inline int 4477 bge_cksum_pad(struct mbuf *pkt) 4478 { 4479 struct mbuf *last = NULL; 4480 int padlen; 4481 4482 padlen = ETHER_MIN_NOPAD - pkt->m_pkthdr.len; 4483 4484 /* if there's only the packet-header and we can pad there, use it. */ 4485 if (pkt->m_pkthdr.len == pkt->m_len && 4486 M_TRAILINGSPACE(pkt) >= padlen) { 4487 last = pkt; 4488 } else { 4489 /* 4490 * Walk packet chain to find last mbuf. We will either 4491 * pad there, or append a new mbuf and pad it 4492 * (thus perhaps avoiding the bcm5700 dma-min bug). 4493 */ 4494 for (last = pkt; last->m_next != NULL; last = last->m_next) { 4495 continue; /* do nothing */ 4496 } 4497 4498 /* `last' now points to last in chain. */ 4499 if (M_TRAILINGSPACE(last) < padlen) { 4500 /* Allocate new empty mbuf, pad it. Compact later. */ 4501 struct mbuf *n; 4502 MGET(n, M_DONTWAIT, MT_DATA); 4503 if (n == NULL) 4504 return ENOBUFS; 4505 n->m_len = 0; 4506 last->m_next = n; 4507 last = n; 4508 } 4509 } 4510 4511 KDASSERT(!M_READONLY(last)); 4512 KDASSERT(M_TRAILINGSPACE(last) >= padlen); 4513 4514 /* Now zero the pad area, to avoid the bge cksum-assist bug */ 4515 memset(mtod(last, char *) + last->m_len, 0, padlen); 4516 last->m_len += padlen; 4517 pkt->m_pkthdr.len += padlen; 4518 return 0; 4519 } 4520 4521 /* 4522 * Compact outbound packets to avoid bug with DMA segments less than 8 bytes. 4523 */ 4524 static inline int 4525 bge_compact_dma_runt(struct mbuf *pkt) 4526 { 4527 struct mbuf *m, *prev; 4528 int totlen, prevlen; 4529 4530 prev = NULL; 4531 totlen = 0; 4532 prevlen = -1; 4533 4534 for (m = pkt; m != NULL; prev = m,m = m->m_next) { 4535 int mlen = m->m_len; 4536 int shortfall = 8 - mlen ; 4537 4538 totlen += mlen; 4539 if (mlen == 0) 4540 continue; 4541 if (mlen >= 8) 4542 continue; 4543 4544 /* If we get here, mbuf data is too small for DMA engine. 4545 * Try to fix by shuffling data to prev or next in chain. 4546 * If that fails, do a compacting deep-copy of the whole chain. 4547 */ 4548 4549 /* Internal frag. If fits in prev, copy it there. */ 4550 if (prev && M_TRAILINGSPACE(prev) >= m->m_len) { 4551 memcpy(prev->m_data + prev->m_len, m->m_data, mlen); 4552 prev->m_len += mlen; 4553 m->m_len = 0; 4554 /* XXX stitch chain */ 4555 prev->m_next = m_free(m); 4556 m = prev; 4557 continue; 4558 } 4559 else if (m->m_next != NULL && 4560 M_TRAILINGSPACE(m) >= shortfall && 4561 m->m_next->m_len >= (8 + shortfall)) { 4562 /* m is writable and have enough data in next, pull up. */ 4563 4564 memcpy(m->m_data + m->m_len, m->m_next->m_data, 4565 shortfall); 4566 m->m_len += shortfall; 4567 m->m_next->m_len -= shortfall; 4568 m->m_next->m_data += shortfall; 4569 } 4570 else if (m->m_next == NULL || 1) { 4571 /* Got a runt at the very end of the packet. 4572 * borrow data from the tail of the preceding mbuf and 4573 * update its length in-place. (The original data is still 4574 * valid, so we can do this even if prev is not writable.) 4575 */ 4576 4577 /* if we'd make prev a runt, just move all of its data. */ 4578 KASSERT(prev != NULL /*, ("runt but null PREV")*/); 4579 KASSERT(prev->m_len >= 8 /*, ("runt prev")*/); 4580 4581 if ((prev->m_len - shortfall) < 8) 4582 shortfall = prev->m_len; 4583 4584 #ifdef notyet /* just do the safe slow thing for now */ 4585 if (!M_READONLY(m)) { 4586 if (M_LEADINGSPACE(m) < shorfall) { 4587 void *m_dat; 4588 m_dat = (m->m_flags & M_PKTHDR) ? 4589 m->m_pktdat : m->dat; 4590 memmove(m_dat, mtod(m, void*), m->m_len); 4591 m->m_data = m_dat; 4592 } 4593 } else 4594 #endif /* just do the safe slow thing */ 4595 { 4596 struct mbuf * n = NULL; 4597 int newprevlen = prev->m_len - shortfall; 4598 4599 MGET(n, M_NOWAIT, MT_DATA); 4600 if (n == NULL) 4601 return ENOBUFS; 4602 KASSERT(m->m_len + shortfall < MLEN 4603 /*, 4604 ("runt %d +prev %d too big\n", m->m_len, shortfall)*/); 4605 4606 /* first copy the data we're stealing from prev */ 4607 memcpy(n->m_data, prev->m_data + newprevlen, 4608 shortfall); 4609 4610 /* update prev->m_len accordingly */ 4611 prev->m_len -= shortfall; 4612 4613 /* copy data from runt m */ 4614 memcpy(n->m_data + shortfall, m->m_data, 4615 m->m_len); 4616 4617 /* n holds what we stole from prev, plus m */ 4618 n->m_len = shortfall + m->m_len; 4619 4620 /* stitch n into chain and free m */ 4621 n->m_next = m->m_next; 4622 prev->m_next = n; 4623 /* KASSERT(m->m_next == NULL); */ 4624 m->m_next = NULL; 4625 m_free(m); 4626 m = n; /* for continuing loop */ 4627 } 4628 } 4629 prevlen = m->m_len; 4630 } 4631 return 0; 4632 } 4633 4634 /* 4635 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data 4636 * pointers to descriptors. 4637 */ 4638 static int 4639 bge_encap(struct bge_softc *sc, struct mbuf *m_head, uint32_t *txidx) 4640 { 4641 struct bge_tx_bd *f = NULL; 4642 uint32_t frag, cur; 4643 uint16_t csum_flags = 0; 4644 uint16_t txbd_tso_flags = 0; 4645 struct txdmamap_pool_entry *dma; 4646 bus_dmamap_t dmamap; 4647 int i = 0; 4648 struct m_tag *mtag; 4649 int use_tso, maxsegsize, error; 4650 4651 cur = frag = *txidx; 4652 4653 if (m_head->m_pkthdr.csum_flags) { 4654 if (m_head->m_pkthdr.csum_flags & M_CSUM_IPv4) 4655 csum_flags |= BGE_TXBDFLAG_IP_CSUM; 4656 if (m_head->m_pkthdr.csum_flags & (M_CSUM_TCPv4|M_CSUM_UDPv4)) 4657 csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM; 4658 } 4659 4660 /* 4661 * If we were asked to do an outboard checksum, and the NIC 4662 * has the bug where it sometimes adds in the Ethernet padding, 4663 * explicitly pad with zeros so the cksum will be correct either way. 4664 * (For now, do this for all chip versions, until newer 4665 * are confirmed to not require the workaround.) 4666 */ 4667 if ((csum_flags & BGE_TXBDFLAG_TCP_UDP_CSUM) == 0 || 4668 #ifdef notyet 4669 (sc->bge_quirks & BGE_QUIRK_SHORT_CKSUM_BUG) == 0 || 4670 #endif 4671 m_head->m_pkthdr.len >= ETHER_MIN_NOPAD) 4672 goto check_dma_bug; 4673 4674 if (bge_cksum_pad(m_head) != 0) 4675 return ENOBUFS; 4676 4677 check_dma_bug: 4678 if (!(BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX)) 4679 goto doit; 4680 4681 /* 4682 * bcm5700 Revision B silicon cannot handle DMA descriptors with 4683 * less than eight bytes. If we encounter a teeny mbuf 4684 * at the end of a chain, we can pad. Otherwise, copy. 4685 */ 4686 if (bge_compact_dma_runt(m_head) != 0) 4687 return ENOBUFS; 4688 4689 doit: 4690 dma = SLIST_FIRST(&sc->txdma_list); 4691 if (dma == NULL) 4692 return ENOBUFS; 4693 dmamap = dma->dmamap; 4694 4695 /* 4696 * Set up any necessary TSO state before we start packing... 4697 */ 4698 use_tso = (m_head->m_pkthdr.csum_flags & M_CSUM_TSOv4) != 0; 4699 if (!use_tso) { 4700 maxsegsize = 0; 4701 } else { /* TSO setup */ 4702 unsigned mss; 4703 struct ether_header *eh; 4704 unsigned ip_tcp_hlen, iptcp_opt_words, tcp_seg_flags, offset; 4705 struct mbuf * m0 = m_head; 4706 struct ip *ip; 4707 struct tcphdr *th; 4708 int iphl, hlen; 4709 4710 /* 4711 * XXX It would be nice if the mbuf pkthdr had offset 4712 * fields for the protocol headers. 4713 */ 4714 4715 eh = mtod(m0, struct ether_header *); 4716 switch (htons(eh->ether_type)) { 4717 case ETHERTYPE_IP: 4718 offset = ETHER_HDR_LEN; 4719 break; 4720 4721 case ETHERTYPE_VLAN: 4722 offset = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 4723 break; 4724 4725 default: 4726 /* 4727 * Don't support this protocol or encapsulation. 4728 */ 4729 return ENOBUFS; 4730 } 4731 4732 /* 4733 * TCP/IP headers are in the first mbuf; we can do 4734 * this the easy way. 4735 */ 4736 iphl = M_CSUM_DATA_IPv4_IPHL(m0->m_pkthdr.csum_data); 4737 hlen = iphl + offset; 4738 if (__predict_false(m0->m_len < 4739 (hlen + sizeof(struct tcphdr)))) { 4740 4741 aprint_debug_dev(sc->bge_dev, 4742 "TSO: hard case m0->m_len == %d < ip/tcp hlen %zd," 4743 "not handled yet\n", 4744 m0->m_len, hlen+ sizeof(struct tcphdr)); 4745 #ifdef NOTYET 4746 /* 4747 * XXX jonathan (at) NetBSD.org: untested. 4748 * how to force this branch to be taken? 4749 */ 4750 BGE_EVCNT_INCR(&sc->sc_ev_txtsopain); 4751 4752 m_copydata(m0, offset, sizeof(ip), &ip); 4753 m_copydata(m0, hlen, sizeof(th), &th); 4754 4755 ip.ip_len = 0; 4756 4757 m_copyback(m0, hlen + offsetof(struct ip, ip_len), 4758 sizeof(ip.ip_len), &ip.ip_len); 4759 4760 th.th_sum = in_cksum_phdr(ip.ip_src.s_addr, 4761 ip.ip_dst.s_addr, htons(IPPROTO_TCP)); 4762 4763 m_copyback(m0, hlen + offsetof(struct tcphdr, th_sum), 4764 sizeof(th.th_sum), &th.th_sum); 4765 4766 hlen += th.th_off << 2; 4767 iptcp_opt_words = hlen; 4768 #else 4769 /* 4770 * if_wm "hard" case not yet supported, can we not 4771 * mandate it out of existence? 4772 */ 4773 (void) ip; (void)th; (void) ip_tcp_hlen; 4774 4775 return ENOBUFS; 4776 #endif 4777 } else { 4778 ip = (struct ip *) (mtod(m0, char *) + offset); 4779 th = (struct tcphdr *) (mtod(m0, char *) + hlen); 4780 ip_tcp_hlen = iphl + (th->th_off << 2); 4781 4782 /* Total IP/TCP options, in 32-bit words */ 4783 iptcp_opt_words = (ip_tcp_hlen 4784 - sizeof(struct tcphdr) 4785 - sizeof(struct ip)) >> 2; 4786 } 4787 if (BGE_IS_575X_PLUS(sc)) { 4788 th->th_sum = 0; 4789 csum_flags &= ~(BGE_TXBDFLAG_TCP_UDP_CSUM); 4790 } else { 4791 /* 4792 * XXX jonathan (at) NetBSD.org: 5705 untested. 4793 * Requires TSO firmware patch for 5701/5703/5704. 4794 */ 4795 th->th_sum = in_cksum_phdr(ip->ip_src.s_addr, 4796 ip->ip_dst.s_addr, htons(IPPROTO_TCP)); 4797 } 4798 4799 mss = m_head->m_pkthdr.segsz; 4800 txbd_tso_flags |= 4801 BGE_TXBDFLAG_CPU_PRE_DMA | 4802 BGE_TXBDFLAG_CPU_POST_DMA; 4803 4804 /* 4805 * Our NIC TSO-assist assumes TSO has standard, optionless 4806 * IPv4 and TCP headers, which total 40 bytes. By default, 4807 * the NIC copies 40 bytes of IP/TCP header from the 4808 * supplied header into the IP/TCP header portion of 4809 * each post-TSO-segment. If the supplied packet has IP or 4810 * TCP options, we need to tell the NIC to copy those extra 4811 * bytes into each post-TSO header, in addition to the normal 4812 * 40-byte IP/TCP header (and to leave space accordingly). 4813 * Unfortunately, the driver encoding of option length 4814 * varies across different ASIC families. 4815 */ 4816 tcp_seg_flags = 0; 4817 if (iptcp_opt_words) { 4818 if (BGE_IS_5705_PLUS(sc)) { 4819 tcp_seg_flags = 4820 iptcp_opt_words << 11; 4821 } else { 4822 txbd_tso_flags |= 4823 iptcp_opt_words << 12; 4824 } 4825 } 4826 maxsegsize = mss | tcp_seg_flags; 4827 ip->ip_len = htons(mss + ip_tcp_hlen); 4828 4829 } /* TSO setup */ 4830 4831 /* 4832 * Start packing the mbufs in this chain into 4833 * the fragment pointers. Stop when we run out 4834 * of fragments or hit the end of the mbuf chain. 4835 */ 4836 error = bus_dmamap_load_mbuf(sc->bge_dmatag, dmamap, m_head, 4837 BUS_DMA_NOWAIT); 4838 if (error) 4839 return ENOBUFS; 4840 /* 4841 * Sanity check: avoid coming within 16 descriptors 4842 * of the end of the ring. 4843 */ 4844 if (dmamap->dm_nsegs > (BGE_TX_RING_CNT - sc->bge_txcnt - 16)) { 4845 BGE_TSO_PRINTF(("%s: " 4846 " dmamap_load_mbuf too close to ring wrap\n", 4847 device_xname(sc->bge_dev))); 4848 goto fail_unload; 4849 } 4850 4851 mtag = sc->ethercom.ec_nvlans ? 4852 m_tag_find(m_head, PACKET_TAG_VLAN, NULL) : NULL; 4853 4854 4855 /* Iterate over dmap-map fragments. */ 4856 for (i = 0; i < dmamap->dm_nsegs; i++) { 4857 f = &sc->bge_rdata->bge_tx_ring[frag]; 4858 if (sc->bge_cdata.bge_tx_chain[frag] != NULL) 4859 break; 4860 4861 BGE_HOSTADDR(f->bge_addr, dmamap->dm_segs[i].ds_addr); 4862 f->bge_len = dmamap->dm_segs[i].ds_len; 4863 4864 /* 4865 * For 5751 and follow-ons, for TSO we must turn 4866 * off checksum-assist flag in the tx-descr, and 4867 * supply the ASIC-revision-specific encoding 4868 * of TSO flags and segsize. 4869 */ 4870 if (use_tso) { 4871 if (BGE_IS_575X_PLUS(sc) || i == 0) { 4872 f->bge_rsvd = maxsegsize; 4873 f->bge_flags = csum_flags | txbd_tso_flags; 4874 } else { 4875 f->bge_rsvd = 0; 4876 f->bge_flags = 4877 (csum_flags | txbd_tso_flags) & 0x0fff; 4878 } 4879 } else { 4880 f->bge_rsvd = 0; 4881 f->bge_flags = csum_flags; 4882 } 4883 4884 if (mtag != NULL) { 4885 f->bge_flags |= BGE_TXBDFLAG_VLAN_TAG; 4886 f->bge_vlan_tag = VLAN_TAG_VALUE(mtag); 4887 } else { 4888 f->bge_vlan_tag = 0; 4889 } 4890 cur = frag; 4891 BGE_INC(frag, BGE_TX_RING_CNT); 4892 } 4893 4894 if (i < dmamap->dm_nsegs) { 4895 BGE_TSO_PRINTF(("%s: reached %d < dm_nsegs %d\n", 4896 device_xname(sc->bge_dev), i, dmamap->dm_nsegs)); 4897 goto fail_unload; 4898 } 4899 4900 bus_dmamap_sync(sc->bge_dmatag, dmamap, 0, dmamap->dm_mapsize, 4901 BUS_DMASYNC_PREWRITE); 4902 4903 if (frag == sc->bge_tx_saved_considx) { 4904 BGE_TSO_PRINTF(("%s: frag %d = wrapped id %d?\n", 4905 device_xname(sc->bge_dev), frag, sc->bge_tx_saved_considx)); 4906 4907 goto fail_unload; 4908 } 4909 4910 sc->bge_rdata->bge_tx_ring[cur].bge_flags |= BGE_TXBDFLAG_END; 4911 sc->bge_cdata.bge_tx_chain[cur] = m_head; 4912 SLIST_REMOVE_HEAD(&sc->txdma_list, link); 4913 sc->txdma[cur] = dma; 4914 sc->bge_txcnt += dmamap->dm_nsegs; 4915 4916 *txidx = frag; 4917 4918 return 0; 4919 4920 fail_unload: 4921 bus_dmamap_unload(sc->bge_dmatag, dmamap); 4922 4923 return ENOBUFS; 4924 } 4925 4926 /* 4927 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 4928 * to the mbuf data regions directly in the transmit descriptors. 4929 */ 4930 static void 4931 bge_start(struct ifnet *ifp) 4932 { 4933 struct bge_softc *sc; 4934 struct mbuf *m_head = NULL; 4935 uint32_t prodidx; 4936 int pkts = 0; 4937 4938 sc = ifp->if_softc; 4939 4940 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 4941 return; 4942 4943 prodidx = sc->bge_tx_prodidx; 4944 4945 while (sc->bge_cdata.bge_tx_chain[prodidx] == NULL) { 4946 IFQ_POLL(&ifp->if_snd, m_head); 4947 if (m_head == NULL) 4948 break; 4949 4950 #if 0 4951 /* 4952 * XXX 4953 * safety overkill. If this is a fragmented packet chain 4954 * with delayed TCP/UDP checksums, then only encapsulate 4955 * it if we have enough descriptors to handle the entire 4956 * chain at once. 4957 * (paranoia -- may not actually be needed) 4958 */ 4959 if (m_head->m_flags & M_FIRSTFRAG && 4960 m_head->m_pkthdr.csum_flags & (CSUM_DELAY_DATA)) { 4961 if ((BGE_TX_RING_CNT - sc->bge_txcnt) < 4962 M_CSUM_DATA_IPv4_OFFSET(m_head->m_pkthdr.csum_data) + 16) { 4963 ifp->if_flags |= IFF_OACTIVE; 4964 break; 4965 } 4966 } 4967 #endif 4968 4969 /* 4970 * Pack the data into the transmit ring. If we 4971 * don't have room, set the OACTIVE flag and wait 4972 * for the NIC to drain the ring. 4973 */ 4974 if (bge_encap(sc, m_head, &prodidx)) { 4975 ifp->if_flags |= IFF_OACTIVE; 4976 break; 4977 } 4978 4979 /* now we are committed to transmit the packet */ 4980 IFQ_DEQUEUE(&ifp->if_snd, m_head); 4981 pkts++; 4982 4983 /* 4984 * If there's a BPF listener, bounce a copy of this frame 4985 * to him. 4986 */ 4987 bpf_mtap(ifp, m_head); 4988 } 4989 if (pkts == 0) 4990 return; 4991 4992 /* Transmit */ 4993 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); 4994 /* 5700 b2 errata */ 4995 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX) 4996 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); 4997 4998 sc->bge_tx_prodidx = prodidx; 4999 5000 /* 5001 * Set a timeout in case the chip goes out to lunch. 5002 */ 5003 ifp->if_timer = 5; 5004 } 5005 5006 static int 5007 bge_init(struct ifnet *ifp) 5008 { 5009 struct bge_softc *sc = ifp->if_softc; 5010 const uint16_t *m; 5011 uint32_t mode; 5012 int s, error = 0; 5013 5014 s = splnet(); 5015 5016 ifp = &sc->ethercom.ec_if; 5017 5018 /* Cancel pending I/O and flush buffers. */ 5019 bge_stop(ifp, 0); 5020 5021 bge_stop_fw(sc); 5022 bge_sig_pre_reset(sc, BGE_RESET_START); 5023 bge_reset(sc); 5024 bge_sig_legacy(sc, BGE_RESET_START); 5025 bge_sig_post_reset(sc, BGE_RESET_START); 5026 5027 bge_chipinit(sc); 5028 5029 /* 5030 * Init the various state machines, ring 5031 * control blocks and firmware. 5032 */ 5033 error = bge_blockinit(sc); 5034 if (error != 0) { 5035 aprint_error_dev(sc->bge_dev, "initialization error %d\n", 5036 error); 5037 splx(s); 5038 return error; 5039 } 5040 5041 ifp = &sc->ethercom.ec_if; 5042 5043 /* Specify MTU. */ 5044 CSR_WRITE_4(sc, BGE_RX_MTU, ifp->if_mtu + 5045 ETHER_HDR_LEN + ETHER_CRC_LEN + ETHER_VLAN_ENCAP_LEN); 5046 5047 /* Load our MAC address. */ 5048 m = (const uint16_t *)&(CLLADDR(ifp->if_sadl)[0]); 5049 CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0])); 5050 CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, (htons(m[1]) << 16) | htons(m[2])); 5051 5052 /* Enable or disable promiscuous mode as needed. */ 5053 if (ifp->if_flags & IFF_PROMISC) 5054 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 5055 else 5056 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 5057 5058 /* Program multicast filter. */ 5059 bge_setmulti(sc); 5060 5061 /* Init RX ring. */ 5062 bge_init_rx_ring_std(sc); 5063 5064 /* 5065 * Workaround for a bug in 5705 ASIC rev A0. Poll the NIC's 5066 * memory to insure that the chip has in fact read the first 5067 * entry of the ring. 5068 */ 5069 if (sc->bge_chipid == BGE_CHIPID_BCM5705_A0) { 5070 uint32_t v, i; 5071 for (i = 0; i < 10; i++) { 5072 DELAY(20); 5073 v = bge_readmem_ind(sc, BGE_STD_RX_RINGS + 8); 5074 if (v == (MCLBYTES - ETHER_ALIGN)) 5075 break; 5076 } 5077 if (i == 10) 5078 aprint_error_dev(sc->bge_dev, 5079 "5705 A0 chip failed to load RX ring\n"); 5080 } 5081 5082 /* Init jumbo RX ring. */ 5083 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 5084 bge_init_rx_ring_jumbo(sc); 5085 5086 /* Init our RX return ring index */ 5087 sc->bge_rx_saved_considx = 0; 5088 5089 /* Init TX ring. */ 5090 bge_init_tx_ring(sc); 5091 5092 /* Enable TX MAC state machine lockup fix. */ 5093 mode = CSR_READ_4(sc, BGE_TX_MODE); 5094 if (BGE_IS_5755_PLUS(sc) || 5095 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 5096 mode |= BGE_TXMODE_MBUF_LOCKUP_FIX; 5097 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) { 5098 mode &= ~(BGE_TXMODE_JMB_FRM_LEN | BGE_TXMODE_CNT_DN_MODE); 5099 mode |= CSR_READ_4(sc, BGE_TX_MODE) & 5100 (BGE_TXMODE_JMB_FRM_LEN | BGE_TXMODE_CNT_DN_MODE); 5101 } 5102 5103 /* Turn on transmitter */ 5104 CSR_WRITE_4_FLUSH(sc, BGE_TX_MODE, mode | BGE_TXMODE_ENABLE); 5105 DELAY(100); 5106 5107 /* Turn on receiver */ 5108 mode = CSR_READ_4(sc, BGE_RX_MODE); 5109 if (BGE_IS_5755_PLUS(sc)) 5110 mode |= BGE_RXMODE_IPV6_ENABLE; 5111 CSR_WRITE_4_FLUSH(sc, BGE_RX_MODE, mode | BGE_RXMODE_ENABLE); 5112 DELAY(10); 5113 5114 CSR_WRITE_4(sc, BGE_MAX_RX_FRAME_LOWAT, 2); 5115 5116 /* Tell firmware we're alive. */ 5117 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 5118 5119 /* Enable host interrupts. */ 5120 PCI_SETBIT(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MISC_CTL, 5121 BGE_PCIMISCCTL_CLEAR_INTA); 5122 PCI_CLRBIT(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MISC_CTL, 5123 BGE_PCIMISCCTL_MASK_PCI_INTR); 5124 bge_writembx_flush(sc, BGE_MBX_IRQ0_LO, 0); 5125 5126 if ((error = bge_ifmedia_upd(ifp)) != 0) 5127 goto out; 5128 5129 ifp->if_flags |= IFF_RUNNING; 5130 ifp->if_flags &= ~IFF_OACTIVE; 5131 5132 callout_reset(&sc->bge_timeout, hz, bge_tick, sc); 5133 5134 out: 5135 sc->bge_if_flags = ifp->if_flags; 5136 splx(s); 5137 5138 return error; 5139 } 5140 5141 /* 5142 * Set media options. 5143 */ 5144 static int 5145 bge_ifmedia_upd(struct ifnet *ifp) 5146 { 5147 struct bge_softc *sc = ifp->if_softc; 5148 struct mii_data *mii = &sc->bge_mii; 5149 struct ifmedia *ifm = &sc->bge_ifmedia; 5150 int rc; 5151 5152 /* If this is a 1000baseX NIC, enable the TBI port. */ 5153 if (sc->bge_flags & BGE_PHY_FIBER_TBI) { 5154 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 5155 return EINVAL; 5156 switch (IFM_SUBTYPE(ifm->ifm_media)) { 5157 case IFM_AUTO: 5158 /* 5159 * The BCM5704 ASIC appears to have a special 5160 * mechanism for programming the autoneg 5161 * advertisement registers in TBI mode. 5162 */ 5163 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) { 5164 uint32_t sgdig; 5165 sgdig = CSR_READ_4(sc, BGE_SGDIG_STS); 5166 if (sgdig & BGE_SGDIGSTS_DONE) { 5167 CSR_WRITE_4(sc, BGE_TX_TBI_AUTONEG, 0); 5168 sgdig = CSR_READ_4(sc, BGE_SGDIG_CFG); 5169 sgdig |= BGE_SGDIGCFG_AUTO | 5170 BGE_SGDIGCFG_PAUSE_CAP | 5171 BGE_SGDIGCFG_ASYM_PAUSE; 5172 CSR_WRITE_4_FLUSH(sc, BGE_SGDIG_CFG, 5173 sgdig | BGE_SGDIGCFG_SEND); 5174 DELAY(5); 5175 CSR_WRITE_4_FLUSH(sc, BGE_SGDIG_CFG, 5176 sgdig); 5177 } 5178 } 5179 break; 5180 case IFM_1000_SX: 5181 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 5182 BGE_CLRBIT(sc, BGE_MAC_MODE, 5183 BGE_MACMODE_HALF_DUPLEX); 5184 } else { 5185 BGE_SETBIT(sc, BGE_MAC_MODE, 5186 BGE_MACMODE_HALF_DUPLEX); 5187 } 5188 DELAY(40); 5189 break; 5190 default: 5191 return EINVAL; 5192 } 5193 /* XXX 802.3x flow control for 1000BASE-SX */ 5194 return 0; 5195 } 5196 5197 BGE_STS_SETBIT(sc, BGE_STS_LINK_EVT); 5198 if ((rc = mii_mediachg(mii)) == ENXIO) 5199 return 0; 5200 5201 /* 5202 * Force an interrupt so that we will call bge_link_upd 5203 * if needed and clear any pending link state attention. 5204 * Without this we are not getting any further interrupts 5205 * for link state changes and thus will not UP the link and 5206 * not be able to send in bge_start. The only way to get 5207 * things working was to receive a packet and get a RX intr. 5208 */ 5209 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 5210 sc->bge_flags & BGE_IS_5788) 5211 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET); 5212 else 5213 BGE_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW); 5214 5215 return rc; 5216 } 5217 5218 /* 5219 * Report current media status. 5220 */ 5221 static void 5222 bge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 5223 { 5224 struct bge_softc *sc = ifp->if_softc; 5225 struct mii_data *mii = &sc->bge_mii; 5226 5227 if (sc->bge_flags & BGE_PHY_FIBER_TBI) { 5228 ifmr->ifm_status = IFM_AVALID; 5229 ifmr->ifm_active = IFM_ETHER; 5230 if (CSR_READ_4(sc, BGE_MAC_STS) & 5231 BGE_MACSTAT_TBI_PCS_SYNCHED) 5232 ifmr->ifm_status |= IFM_ACTIVE; 5233 ifmr->ifm_active |= IFM_1000_SX; 5234 if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX) 5235 ifmr->ifm_active |= IFM_HDX; 5236 else 5237 ifmr->ifm_active |= IFM_FDX; 5238 return; 5239 } 5240 5241 mii_pollstat(mii); 5242 ifmr->ifm_status = mii->mii_media_status; 5243 ifmr->ifm_active = (mii->mii_media_active & ~IFM_ETH_FMASK) | 5244 sc->bge_flowflags; 5245 } 5246 5247 static int 5248 bge_ifflags_cb(struct ethercom *ec) 5249 { 5250 struct ifnet *ifp = &ec->ec_if; 5251 struct bge_softc *sc = ifp->if_softc; 5252 int change = ifp->if_flags ^ sc->bge_if_flags; 5253 5254 if ((change & ~(IFF_CANTCHANGE|IFF_DEBUG)) != 0) 5255 return ENETRESET; 5256 else if ((change & (IFF_PROMISC | IFF_ALLMULTI)) == 0) 5257 return 0; 5258 5259 if ((ifp->if_flags & IFF_PROMISC) == 0) 5260 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 5261 else 5262 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 5263 5264 bge_setmulti(sc); 5265 5266 sc->bge_if_flags = ifp->if_flags; 5267 return 0; 5268 } 5269 5270 static int 5271 bge_ioctl(struct ifnet *ifp, u_long command, void *data) 5272 { 5273 struct bge_softc *sc = ifp->if_softc; 5274 struct ifreq *ifr = (struct ifreq *) data; 5275 int s, error = 0; 5276 struct mii_data *mii; 5277 5278 s = splnet(); 5279 5280 switch (command) { 5281 case SIOCSIFMEDIA: 5282 /* XXX Flow control is not supported for 1000BASE-SX */ 5283 if (sc->bge_flags & BGE_PHY_FIBER_TBI) { 5284 ifr->ifr_media &= ~IFM_ETH_FMASK; 5285 sc->bge_flowflags = 0; 5286 } 5287 5288 /* Flow control requires full-duplex mode. */ 5289 if (IFM_SUBTYPE(ifr->ifr_media) == IFM_AUTO || 5290 (ifr->ifr_media & IFM_FDX) == 0) { 5291 ifr->ifr_media &= ~IFM_ETH_FMASK; 5292 } 5293 if (IFM_SUBTYPE(ifr->ifr_media) != IFM_AUTO) { 5294 if ((ifr->ifr_media & IFM_ETH_FMASK) == IFM_FLOW) { 5295 /* We can do both TXPAUSE and RXPAUSE. */ 5296 ifr->ifr_media |= 5297 IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE; 5298 } 5299 sc->bge_flowflags = ifr->ifr_media & IFM_ETH_FMASK; 5300 } 5301 /* FALLTHROUGH */ 5302 case SIOCGIFMEDIA: 5303 if (sc->bge_flags & BGE_PHY_FIBER_TBI) { 5304 error = ifmedia_ioctl(ifp, ifr, &sc->bge_ifmedia, 5305 command); 5306 } else { 5307 mii = &sc->bge_mii; 5308 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, 5309 command); 5310 } 5311 break; 5312 default: 5313 if ((error = ether_ioctl(ifp, command, data)) != ENETRESET) 5314 break; 5315 5316 error = 0; 5317 5318 if (command != SIOCADDMULTI && command != SIOCDELMULTI) 5319 ; 5320 else if (ifp->if_flags & IFF_RUNNING) 5321 bge_setmulti(sc); 5322 break; 5323 } 5324 5325 splx(s); 5326 5327 return error; 5328 } 5329 5330 static void 5331 bge_watchdog(struct ifnet *ifp) 5332 { 5333 struct bge_softc *sc; 5334 5335 sc = ifp->if_softc; 5336 5337 aprint_error_dev(sc->bge_dev, "watchdog timeout -- resetting\n"); 5338 5339 ifp->if_flags &= ~IFF_RUNNING; 5340 bge_init(ifp); 5341 5342 ifp->if_oerrors++; 5343 } 5344 5345 static void 5346 bge_stop_block(struct bge_softc *sc, bus_addr_t reg, uint32_t bit) 5347 { 5348 int i; 5349 5350 BGE_CLRBIT_FLUSH(sc, reg, bit); 5351 5352 for (i = 0; i < 1000; i++) { 5353 delay(100); 5354 if ((CSR_READ_4(sc, reg) & bit) == 0) 5355 return; 5356 } 5357 5358 /* 5359 * Doesn't print only when the register is BGE_SRS_MODE. It occurs 5360 * on some environment (and once after boot?) 5361 */ 5362 if (reg != BGE_SRS_MODE) 5363 aprint_error_dev(sc->bge_dev, 5364 "block failed to stop: reg 0x%lx, bit 0x%08x\n", 5365 (u_long)reg, bit); 5366 } 5367 5368 /* 5369 * Stop the adapter and free any mbufs allocated to the 5370 * RX and TX lists. 5371 */ 5372 static void 5373 bge_stop(struct ifnet *ifp, int disable) 5374 { 5375 struct bge_softc *sc = ifp->if_softc; 5376 5377 callout_stop(&sc->bge_timeout); 5378 5379 /* Disable host interrupts. */ 5380 PCI_SETBIT(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MISC_CTL, 5381 BGE_PCIMISCCTL_MASK_PCI_INTR); 5382 bge_writembx_flush(sc, BGE_MBX_IRQ0_LO, 1); 5383 5384 /* 5385 * Tell firmware we're shutting down. 5386 */ 5387 bge_stop_fw(sc); 5388 bge_sig_pre_reset(sc, BGE_RESET_SHUTDOWN); 5389 5390 /* 5391 * Disable all of the receiver blocks. 5392 */ 5393 bge_stop_block(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE); 5394 bge_stop_block(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 5395 bge_stop_block(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 5396 if (BGE_IS_5700_FAMILY(sc)) 5397 bge_stop_block(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 5398 bge_stop_block(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE); 5399 bge_stop_block(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 5400 bge_stop_block(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE); 5401 5402 /* 5403 * Disable all of the transmit blocks. 5404 */ 5405 bge_stop_block(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 5406 bge_stop_block(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 5407 bge_stop_block(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 5408 bge_stop_block(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE); 5409 bge_stop_block(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE); 5410 if (BGE_IS_5700_FAMILY(sc)) 5411 bge_stop_block(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 5412 bge_stop_block(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 5413 5414 BGE_CLRBIT_FLUSH(sc, BGE_MAC_MODE, BGE_MACMODE_TXDMA_ENB); 5415 delay(40); 5416 5417 bge_stop_block(sc, BGE_TX_MODE, BGE_TXMODE_ENABLE); 5418 5419 /* 5420 * Shut down all of the memory managers and related 5421 * state machines. 5422 */ 5423 bge_stop_block(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE); 5424 bge_stop_block(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE); 5425 if (BGE_IS_5700_FAMILY(sc)) 5426 bge_stop_block(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 5427 5428 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 5429 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 5430 5431 if (BGE_IS_5700_FAMILY(sc)) { 5432 bge_stop_block(sc, BGE_BMAN_MODE, BGE_BMANMODE_ENABLE); 5433 bge_stop_block(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 5434 } 5435 5436 bge_reset(sc); 5437 bge_sig_legacy(sc, BGE_RESET_SHUTDOWN); 5438 bge_sig_post_reset(sc, BGE_RESET_SHUTDOWN); 5439 5440 /* 5441 * Keep the ASF firmware running if up. 5442 */ 5443 if (sc->bge_asf_mode & ASF_STACKUP) 5444 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 5445 else 5446 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 5447 5448 /* Free the RX lists. */ 5449 bge_free_rx_ring_std(sc); 5450 5451 /* Free jumbo RX list. */ 5452 if (BGE_IS_JUMBO_CAPABLE(sc)) 5453 bge_free_rx_ring_jumbo(sc); 5454 5455 /* Free TX buffers. */ 5456 bge_free_tx_ring(sc); 5457 5458 /* 5459 * Isolate/power down the PHY. 5460 */ 5461 if (!(sc->bge_flags & BGE_PHY_FIBER_TBI)) 5462 mii_down(&sc->bge_mii); 5463 5464 sc->bge_tx_saved_considx = BGE_TXCONS_UNSET; 5465 5466 /* Clear MAC's link state (PHY may still have link UP). */ 5467 BGE_STS_CLRBIT(sc, BGE_STS_LINK); 5468 5469 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 5470 } 5471 5472 static void 5473 bge_link_upd(struct bge_softc *sc) 5474 { 5475 struct ifnet *ifp = &sc->ethercom.ec_if; 5476 struct mii_data *mii = &sc->bge_mii; 5477 uint32_t status; 5478 int link; 5479 5480 /* Clear 'pending link event' flag */ 5481 BGE_STS_CLRBIT(sc, BGE_STS_LINK_EVT); 5482 5483 /* 5484 * Process link state changes. 5485 * Grrr. The link status word in the status block does 5486 * not work correctly on the BCM5700 rev AX and BX chips, 5487 * according to all available information. Hence, we have 5488 * to enable MII interrupts in order to properly obtain 5489 * async link changes. Unfortunately, this also means that 5490 * we have to read the MAC status register to detect link 5491 * changes, thereby adding an additional register access to 5492 * the interrupt handler. 5493 */ 5494 5495 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700) { 5496 status = CSR_READ_4(sc, BGE_MAC_STS); 5497 if (status & BGE_MACSTAT_MI_INTERRUPT) { 5498 mii_pollstat(mii); 5499 5500 if (!BGE_STS_BIT(sc, BGE_STS_LINK) && 5501 mii->mii_media_status & IFM_ACTIVE && 5502 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) 5503 BGE_STS_SETBIT(sc, BGE_STS_LINK); 5504 else if (BGE_STS_BIT(sc, BGE_STS_LINK) && 5505 (!(mii->mii_media_status & IFM_ACTIVE) || 5506 IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) 5507 BGE_STS_CLRBIT(sc, BGE_STS_LINK); 5508 5509 /* Clear the interrupt */ 5510 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, 5511 BGE_EVTENB_MI_INTERRUPT); 5512 bge_miibus_readreg(sc->bge_dev, sc->bge_phy_addr, 5513 BRGPHY_MII_ISR); 5514 bge_miibus_writereg(sc->bge_dev, sc->bge_phy_addr, 5515 BRGPHY_MII_IMR, BRGPHY_INTRS); 5516 } 5517 return; 5518 } 5519 5520 if (sc->bge_flags & BGE_PHY_FIBER_TBI) { 5521 status = CSR_READ_4(sc, BGE_MAC_STS); 5522 if (status & BGE_MACSTAT_TBI_PCS_SYNCHED) { 5523 if (!BGE_STS_BIT(sc, BGE_STS_LINK)) { 5524 BGE_STS_SETBIT(sc, BGE_STS_LINK); 5525 if (BGE_ASICREV(sc->bge_chipid) 5526 == BGE_ASICREV_BCM5704) { 5527 BGE_CLRBIT(sc, BGE_MAC_MODE, 5528 BGE_MACMODE_TBI_SEND_CFGS); 5529 DELAY(40); 5530 } 5531 CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF); 5532 if_link_state_change(ifp, LINK_STATE_UP); 5533 } 5534 } else if (BGE_STS_BIT(sc, BGE_STS_LINK)) { 5535 BGE_STS_CLRBIT(sc, BGE_STS_LINK); 5536 if_link_state_change(ifp, LINK_STATE_DOWN); 5537 } 5538 /* 5539 * Discard link events for MII/GMII cards if MI auto-polling disabled. 5540 * This should not happen since mii callouts are locked now, but 5541 * we keep this check for debug. 5542 */ 5543 } else if (BGE_STS_BIT(sc, BGE_STS_AUTOPOLL)) { 5544 /* 5545 * Some broken BCM chips have BGE_STATFLAG_LINKSTATE_CHANGED 5546 * bit in status word always set. Workaround this bug by 5547 * reading PHY link status directly. 5548 */ 5549 link = (CSR_READ_4(sc, BGE_MI_STS) & BGE_MISTS_LINK)? 5550 BGE_STS_LINK : 0; 5551 5552 if (BGE_STS_BIT(sc, BGE_STS_LINK) != link) { 5553 mii_pollstat(mii); 5554 5555 if (!BGE_STS_BIT(sc, BGE_STS_LINK) && 5556 mii->mii_media_status & IFM_ACTIVE && 5557 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) 5558 BGE_STS_SETBIT(sc, BGE_STS_LINK); 5559 else if (BGE_STS_BIT(sc, BGE_STS_LINK) && 5560 (!(mii->mii_media_status & IFM_ACTIVE) || 5561 IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) 5562 BGE_STS_CLRBIT(sc, BGE_STS_LINK); 5563 } 5564 } 5565 5566 /* Clear the attention */ 5567 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED| 5568 BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE| 5569 BGE_MACSTAT_LINK_CHANGED); 5570 } 5571 5572 static int 5573 bge_sysctl_verify(SYSCTLFN_ARGS) 5574 { 5575 int error, t; 5576 struct sysctlnode node; 5577 5578 node = *rnode; 5579 t = *(int*)rnode->sysctl_data; 5580 node.sysctl_data = &t; 5581 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 5582 if (error || newp == NULL) 5583 return error; 5584 5585 #if 0 5586 DPRINTF2(("%s: t = %d, nodenum = %d, rnodenum = %d\n", __func__, t, 5587 node.sysctl_num, rnode->sysctl_num)); 5588 #endif 5589 5590 if (node.sysctl_num == bge_rxthresh_nodenum) { 5591 if (t < 0 || t >= NBGE_RX_THRESH) 5592 return EINVAL; 5593 bge_update_all_threshes(t); 5594 } else 5595 return EINVAL; 5596 5597 *(int*)rnode->sysctl_data = t; 5598 5599 return 0; 5600 } 5601 5602 /* 5603 * Set up sysctl(3) MIB, hw.bge.*. 5604 */ 5605 static void 5606 bge_sysctl_init(struct bge_softc *sc) 5607 { 5608 int rc, bge_root_num; 5609 const struct sysctlnode *node; 5610 5611 if ((rc = sysctl_createv(&sc->bge_log, 0, NULL, NULL, 5612 CTLFLAG_PERMANENT, CTLTYPE_NODE, "hw", NULL, 5613 NULL, 0, NULL, 0, CTL_HW, CTL_EOL)) != 0) { 5614 goto out; 5615 } 5616 5617 if ((rc = sysctl_createv(&sc->bge_log, 0, NULL, &node, 5618 0, CTLTYPE_NODE, "bge", 5619 SYSCTL_DESCR("BGE interface controls"), 5620 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL)) != 0) { 5621 goto out; 5622 } 5623 5624 bge_root_num = node->sysctl_num; 5625 5626 /* BGE Rx interrupt mitigation level */ 5627 if ((rc = sysctl_createv(&sc->bge_log, 0, NULL, &node, 5628 CTLFLAG_READWRITE, 5629 CTLTYPE_INT, "rx_lvl", 5630 SYSCTL_DESCR("BGE receive interrupt mitigation level"), 5631 bge_sysctl_verify, 0, 5632 &bge_rx_thresh_lvl, 5633 0, CTL_HW, bge_root_num, CTL_CREATE, 5634 CTL_EOL)) != 0) { 5635 goto out; 5636 } 5637 5638 bge_rxthresh_nodenum = node->sysctl_num; 5639 5640 return; 5641 5642 out: 5643 aprint_error("%s: sysctl_createv failed (rc = %d)\n", __func__, rc); 5644 } 5645 5646 #ifdef BGE_DEBUG 5647 void 5648 bge_debug_info(struct bge_softc *sc) 5649 { 5650 5651 printf("Hardware Flags:\n"); 5652 if (BGE_IS_57765_PLUS(sc)) 5653 printf(" - 57765 Plus\n"); 5654 if (BGE_IS_5717_PLUS(sc)) 5655 printf(" - 5717 Plus\n"); 5656 if (BGE_IS_5755_PLUS(sc)) 5657 printf(" - 5755 Plus\n"); 5658 if (BGE_IS_575X_PLUS(sc)) 5659 printf(" - 575X Plus\n"); 5660 if (BGE_IS_5705_PLUS(sc)) 5661 printf(" - 5705 Plus\n"); 5662 if (BGE_IS_5714_FAMILY(sc)) 5663 printf(" - 5714 Family\n"); 5664 if (BGE_IS_5700_FAMILY(sc)) 5665 printf(" - 5700 Family\n"); 5666 if (sc->bge_flags & BGE_IS_5788) 5667 printf(" - 5788\n"); 5668 if (sc->bge_flags & BGE_JUMBO_CAPABLE) 5669 printf(" - Supports Jumbo Frames\n"); 5670 if (sc->bge_flags & BGE_NO_EEPROM) 5671 printf(" - No EEPROM\n"); 5672 if (sc->bge_flags & BGE_PCIX) 5673 printf(" - PCI-X Bus\n"); 5674 if (sc->bge_flags & BGE_PCIE) 5675 printf(" - PCI Express Bus\n"); 5676 if (sc->bge_flags & BGE_NO_3LED) 5677 printf(" - No 3 LEDs\n"); 5678 if (sc->bge_flags & BGE_RX_ALIGNBUG) 5679 printf(" - RX Alignment Bug\n"); 5680 if (sc->bge_flags & BGE_APE) 5681 printf(" - APE\n"); 5682 if (sc->bge_flags & BGE_CPMU_PRESENT) 5683 printf(" - CPMU\n"); 5684 if (sc->bge_flags & BGE_TSO) 5685 printf(" - TSO\n"); 5686 } 5687 #endif /* BGE_DEBUG */ 5688 5689 static int 5690 bge_get_eaddr_fw(struct bge_softc *sc, uint8_t ether_addr[]) 5691 { 5692 prop_dictionary_t dict; 5693 prop_data_t ea; 5694 5695 if ((sc->bge_flags & BGE_NO_EEPROM) == 0) 5696 return 1; 5697 5698 dict = device_properties(sc->bge_dev); 5699 ea = prop_dictionary_get(dict, "mac-address"); 5700 if (ea != NULL) { 5701 KASSERT(prop_object_type(ea) == PROP_TYPE_DATA); 5702 KASSERT(prop_data_size(ea) == ETHER_ADDR_LEN); 5703 memcpy(ether_addr, prop_data_data_nocopy(ea), ETHER_ADDR_LEN); 5704 return 0; 5705 } 5706 5707 return 1; 5708 } 5709 5710 static int 5711 bge_get_eaddr_mem(struct bge_softc *sc, uint8_t ether_addr[]) 5712 { 5713 uint32_t mac_addr; 5714 5715 mac_addr = bge_readmem_ind(sc, BGE_SRAM_MAC_ADDR_HIGH_MB); 5716 if ((mac_addr >> 16) == 0x484b) { 5717 ether_addr[0] = (uint8_t)(mac_addr >> 8); 5718 ether_addr[1] = (uint8_t)mac_addr; 5719 mac_addr = bge_readmem_ind(sc, BGE_SRAM_MAC_ADDR_LOW_MB); 5720 ether_addr[2] = (uint8_t)(mac_addr >> 24); 5721 ether_addr[3] = (uint8_t)(mac_addr >> 16); 5722 ether_addr[4] = (uint8_t)(mac_addr >> 8); 5723 ether_addr[5] = (uint8_t)mac_addr; 5724 return 0; 5725 } 5726 return 1; 5727 } 5728 5729 static int 5730 bge_get_eaddr_nvram(struct bge_softc *sc, uint8_t ether_addr[]) 5731 { 5732 int mac_offset = BGE_EE_MAC_OFFSET; 5733 5734 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 5735 mac_offset = BGE_EE_MAC_OFFSET_5906; 5736 5737 return (bge_read_nvram(sc, ether_addr, mac_offset + 2, 5738 ETHER_ADDR_LEN)); 5739 } 5740 5741 static int 5742 bge_get_eaddr_eeprom(struct bge_softc *sc, uint8_t ether_addr[]) 5743 { 5744 5745 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 5746 return 1; 5747 5748 return (bge_read_eeprom(sc, ether_addr, BGE_EE_MAC_OFFSET + 2, 5749 ETHER_ADDR_LEN)); 5750 } 5751 5752 static int 5753 bge_get_eaddr(struct bge_softc *sc, uint8_t eaddr[]) 5754 { 5755 static const bge_eaddr_fcn_t bge_eaddr_funcs[] = { 5756 /* NOTE: Order is critical */ 5757 bge_get_eaddr_fw, 5758 bge_get_eaddr_mem, 5759 bge_get_eaddr_nvram, 5760 bge_get_eaddr_eeprom, 5761 NULL 5762 }; 5763 const bge_eaddr_fcn_t *func; 5764 5765 for (func = bge_eaddr_funcs; *func != NULL; ++func) { 5766 if ((*func)(sc, eaddr) == 0) 5767 break; 5768 } 5769 return (*func == NULL ? ENXIO : 0); 5770 } 5771
Indexes created Wed Sep 24 02:09:48 GMT 2025